This is information on a product in full production.
April 2017 DocID025370 Rev 4 1/15
RHFLVDS31A
Rad-hard quad LVDS driver
Datasheet - production data
Features
•LVDS output
•CMOS input
•Enable/Disable function with high-impedance
•ANSI TIA/EIA-644 compliant
•400 Mbps (200 MHz)
•Cold spare on all pins
•3.3 V operating power supply
•4.8 V absolute rating
•Output voltage: 350 mV on 100-ohm load
•Power consumption: 55 mW at 3.3 V
•Hermetic package
•Guaranteed up to 300 krad TID
•SEL immune up to 135 MeV.cm²/mg
•SET/SEU immune up to 67 MeV.cm²/mg
Description
The RHFLVDS31A is a quad, low-voltage,
differential signaling (LVDS) driver specifically
designed, packaged, and qualified for use in
aerospace environments in a low-power and fast
point-to-point baseband data transmission
standard.
Operating at 3.3 V power supply, the
RHFLVDS31A operates over a controlled
impedance of 100-ohm transmission media that
may be printed circuit board traces, back planes
or cables.
The circuit features an internal fail-safe function to
ensure a known state in case of floating input. All
pins have cold spare buffers to ensure they are in
high impedance when VCC is tied to GND.
Designed on ST's proprietary CMOS process with
specific mitigation techniques, the RHFLVDS31A
achieves “best in the class” for hardness to total
ionisation dose and heavy ions.
The RHFLVDS31A can operate over a large
temperature range of -55 °C to +125 °C and it is
housed in an hermetic Ceramic Flat-16 package.
Ceramic Flat-16
The upper metallic lid is
electrically connected to ground
Table 1. Device summary
Reference SMD pin Quality level Package Lead finish Mass EPPL(1)
1. EPPL = ESA preferred part list
Temp. range
RHFLVDS31AK1 - Engineering
model Ceramic
Flat-16 Gold 0.65 g
--55 °C to
125 °C
RHFLVDS31AK01V 5962F98651 QML-V flight Target
www.st.com
Contents RHFLVDS31A
2/15 DocID025370 Rev 4
Contents
1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Maximum ratings and operating conditions . . . . . . . . . . . . . . . . . . . . . . 5
4 Radiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.1 Ceramic Flat-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
9 Shipping information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DocID025370 Rev 4 3/15
RHFLVDS31A Functional description
15
1 Functional description
Figure 1. Logic diagram and logic symbol
Note: 1 The G input features an internal pull-up network. The G input features an internal pull-down
network. If they are floating the circuit is enabled.
2 L = low level, H = high Level, X = irrelevant, Z = high impedance (off)
Table 2. Truth table
Input Enables Outputs
AGGYZ
HHXHL
LHXLH
HXLHL
LXLLH
XLHZZ
OPEN H X L H
OPEN X L L H
1A
2A
3A
4A
2
3
1Y
1Z
6
5
2Y
2Z
10
11
3Y
3Z
14
13
4Y
4Z
7
9
15
1
G4
12
CS05830
G
1A
2A
3A
4A
2
3
1Y
1Z
6
5
2Y
2Z
10
11
3Y
3Z
14
13
4Y
4Z
7
9
15
1
G4
12
G
EN
CS05860
Pin configuration RHFLVDS31A
4/15 DocID025370 Rev 4
2 Pin configuration
Figure 2. Pin connections (top view)
Table 3. Pin description
Pin number Symbol Name and function
1, 7, 9, 15 1A to 4A Driver inputs
2, 6, 10, 14 1Y to 4Y
Driver outputs
3, 5, 11, 13 1Z to 4Z
4G
Enable
12 G
8 GND Ground
16 VCC Supply voltage
DocID025370 Rev 4 5/15
RHFLVDS31A Maximum ratings and operating conditions
15
3 Maximum ratings and operating conditions
Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied.
Table 4. Absolute maximum ratings
Symbol Parameter Value Unit
VCC Supply voltage(1)
1. All voltages, except differential I/O bus voltage, are with respect to the network ground terminal.
4.8
VViTTL inputs (operating or cold spare) -0.3 to +4.8
VOUT LVDS outputs (operating or coldspare) -0.3 to +4.8
Tstg Storage temperature range -65 to +150
°C
TjMaximum junction temperature +150
Rthjc Thermal resistance junction to case(2)
2. Short-circuits can cause excessive heating. Destructive dissipation can result from short-circuits on the
amplifiers.
22 °C/W
ESD
HBM: Human body model
– All pins except LVDS outputs
– LVDS outputs vs. GND
2
8
kV
CDM: Charge device model 500 V
Table 5. Operating conditions
Symbol Parameter Min. Typ. Max. Unit
VCC Supply voltage 3 3.3 3.6
V
VIN Driver DC input voltage (TTL inputs) 0 3.6
TAAmbient temperature range -55 +125 °C
Radiation RHFLVDS31A
6/15 DocID025370 Rev 4
4 Radiation
Total dose (MIL-STD-883 TM 1019)
The products guaranteed in radiation within the RHA QML-V system fully comply with the
MIL-STD-883 TM 1019 specification.
The RHFLVDS31A is RHA QML-V, tested and characterized in full compliance with the
MIL-STD-883 specification, between 50 and 300 rad/s only (full CMOS technology).
All parameters provided in Table 7: Electrical characteristics apply to both pre- and post-
irradiation, as follows:
•All test are performed in accordance with MIL-PRF-38535 and test method 1019 of
MIL-STD-883 for total ionizing dose (TID).
•The initial characterization is performed in qualification only on both biased and
unbiased parts.
•Each wafer lot is tested at high dose rate only, in the worst bias case condition, based
on the results obtained during the initial qualification.
Heavy ions
The behavior of the product when submitted to heavy ions is not tested in production.
Heavy-ion trials are performed on qualification lots only.
Table 6. Radiation
Type Characteristics Value Unit
TID High-dose rate (50 - 300 rad/sec) up to: 300 krad
Heavy ions
SEL immune up to:
(with a particle angle of 60 ° at 125 °C)
135
MeV.cm²/mg
SEL immune up to:
(with a particle angle of 0 ° at 125 °C)
67
SET/SEU immune up to:
(at 25 °C)
67
DocID025370 Rev 4 7/15
RHFLVDS31A Electrical characteristics
15
5 Electrical characteristics
In Table 7 below, VCC = 3 V to 3.6 V, capa-load (CL) = 10 pF, typical values are at
Tamb = +25 °C, min. and max values are at Tamb = - 55 °C and + 125 °C unless otherwise
specified
Table 7. Electrical characteristics
Symbol Parameter Test conditions Min. Typ. Max. Unit
ICCL
Total enabled supply current,
drivers enabled, not switching
VIN = 0 V or VCC
Load = 100 Ω on all channels 16.5 20
mA
ICCZ
Total disabled supply current,
loaded or not loaded,
drivers disabled
VIN = 0 V or VCC
G = GND, G = VCC
2.8 4
IOFF (1)
TTL input power-off leakage
current VCC = 0 V, VIN = 3.6 V -10 10
µA
LVDS output power-off leakage
current VCC = 0 V, VOUT = 3.6 V -50 +50
VOH Output voltage high
RL = 100 Ω
1.65
V
VOL Output voltage low 0.925
VOD1 Differential output voltage 250 400
mV
DVOD1
Change of magnitude of VOD1
for complementary output
states
10
VOS Offset voltage 1.125 1.45 V
DVOS
Change of magnitude of VOS for
complementary output states 15 mV
IOS Output short-circuit current VIN = 0 V and VO(Z) = 0 V or
VIN = VCC and VO(Y) = 0 V -9 mA
IOHigh impedance output current Disabled, VOUT = 3.6 V or GND -10 10 µA
VIH Input voltage high
G, G, and TTL inputs
2V
CC V
VIL Input voltage low GND 0.8
IIH High level input current G, G, and TTL inputs
VCC = 3.6 V, VIN = VCC
-10 10
µA
IIL Low level input current G, G and TTL inputs
VCC = 3.6 V, VIN = 0 -10 10
CIN Input capacitance 3 pF
Electrical characteristics RHFLVDS31A
8/15 DocID025370 Rev 4
Cold sparing
The RHFLVDS31A features a cold spare input and output buffer. In high reliability
applications, cold sparing enables a redundant device to be tied to the data bus with its
power supply at 0 V (VCC = GND) without affecting the bus signals or injecting current from
the I/Os to the power supplies. Cold sparing also allows redundant devices to be kept
powered off so that they can be switched on only when required. This has no impact on the
application. Cold sparing is achieved by implementing a high impedance between the I/Os
and VCC. ESD protection is ensured through a non-conventional dedicated structure.
Fail-safe
In many applications, inputs need a fail-safe function to avoid an uncertain output state
when the inputs are not connected properly. In case of TTL floating inputs, the LVDS outputs
remain in a stable logic-high state.
tPHLD
Propagation delay time, high to
low output
Refer to Figure 4
0.5 1.5
ns
tPLHD
Propagation delay time, low to
high output 0.5 1.5
t r
Differential output signal rise
time 0.8
t f
Differential output signal fall
time 0.8
tSK1 Channel-to-channel skew(2)
Load: refer to Figure 4
0.28
ns
tSK2 Chip-to-chip skew(3)(4) 0.7
tSKD
Differential skew(5)
(tPHLD-tPLHD) 0.3
tPHZ
Propagation delay time, high
level to high impedance output 2.8
tPLZ
Propagation delay time, low
level to high impedance output 2.8
tPZH
Propagation delay time, high
impedance to high level output 2.5
tPZL
Propagation delay time, high
impedance to low level output 2.5
1. All pins except pin under test and VCC are floating.
2. tSK1 is the maximum delay time difference between all outputs of the same device (measured with all inputs connected
together).
3. tSK2 is the maximum delay time difference between outputs of all devices when they operate with the same supply voltage,
at the same temperature.
4. Guaranteed by design.
5. tSKD is the maximum delay time difference between tPHLD and tPLHD (see Figure 4).
Table 7. Electrical characteristics (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
DocID025370 Rev 4 9/15
RHFLVDS31A Test circuit
15
6 Test circuit
Figure 3. Voltage and current definition
Figure 4. Test circuit, timing and voltage definitions for differential output signal
1. All input pulses are supplied by a generator with the following characteristics: tr or tf ≤ 1 ns, f = 1 MHz,
ZO = 50 Ω, and duty cycle = 50%.
2. The product is guaranteed in test with CL = 10 pF
VOD
LVDS
Driver
(Y) OUT+
(Z) OUT-
VOZ VOY
VOS=(VOZ+VOY)/2
VIN
II
CL=10pF
100ohm
LVDS
Driver
CL=10pF
VIN
tPHLD tPLHD
tf
VOD
tr
80%
20%
80%
20%
Vcc/2 Vcc/2
Test circuit RHFLVDS31A
10/15 DocID025370 Rev 4
Figure 5. Enable and disable waveform
1. All input pulses are supplied by a generator with the following characteristics: tr or tf ≤ 1 ns,
fG or fG = 500 kHz, and pulse width G or G = 500 ns.
2. The product is guaranteed in test with CL = 10 pF
VOD
CL=10pF
50ohm
LVDS
Driver
CL=10pF
OUT+
OUT- 50ohm
1.2V
VOS
G
TPZH
50% 50%
TPZL
50%
50%
TPHZ
TPLZ
50%
50%
VOUT+ or VOUT-
50% 50%
G
VOUT+ or VOUT-
DocID025370 Rev 4 11/15
RHFLVDS31A Package information
15
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Package information RHFLVDS31A
12/15 DocID025370 Rev 4
7.1 Ceramic Flat-16 package information
Figure 6. Ceramic Flat-16 package mechanical drawing
1. The upper metallic lid is electrically connected to ground.
Table 8. Ceramic Flat-16 package mechanical data
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 2.31 2.72 0.091 0.107
b 0.38 0.48 0.015 0.019
c 0.10 0.18 0.004 0.007
D 9.75 10.13 0.384 0.399
E 6.75 7.06 0.266 0.278
E2 4.32 0.170
E3 0.76 0.030
e 1.27 0.050
L 6.35 7.36 0.250 0.290
Q 0.66 1.14 0.026 0.045
S1 0.13 0.005
DocID025370 Rev 4 13/15
RHFLVDS31A Ordering information
15
8 Ordering information
Note: Contact your ST sales office for information regarding the specific conditions for products in
die form and QML-Q versions.
9 Shipping information
Date code
The date code is structured as follows:
•Engineering model: EM xyywwz
•QML flight model: FM yywwz
Where:
x = 3 (EM only), assembly location Rennes (France)
yy = last two digits of the year
ww = week digits
z = lot index of the week
Table 9. Order codes
Order code Description Temp. range Package Marking(1)
1. Specific marking only. Complete marking includes the following:
- SMD pin (on QML-V flight only)
- ST logo
- Date code (date the package was sealed) in YYWWA (year, week, and lot index of week)
- QML logo (Q or V)
- Country of origin (FR = France).
Packing
RHFLVDS31AK1 Engineering
model -55 °C to
125 °C
Ceramic
Flat-16
RHFLVDS31AK1
Strip pack
RHFLVDS31AK01V QML-V flight 5962F9865107VZC
Revision history RHFLVDS31A
14/15 DocID025370 Rev 4
10 Revision history
Table 10. Document revision history
Date Revision Changes
29-Oct-2013 1 Initial release
30-Oct-2014 2
– Updated production status and marking information relative to order
code RHFLVDS31AK01V in Table 1: Device summary and Table 9:
Order codes.
– Changed title of Section 4 to “Radiation” and moved Electrical
characteristics to Section 5.
04-Mar-2015 3 Added VOUT to Table 4: Absolute maximum ratings.
28-Apr-2017 4 Table 1: Device summary: added mass value
DocID025370 Rev 4 15/15
RHFLVDS31A
15
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2017 STMicroelectronics – All rights reserved