CX20415 - Rockwell - Datasheet.Live

Data Sheet Conexant Doc. No. 100550B

March 31, 2000

Single-Chip FaxEngine Codec

Integrated Analog Device (CX20415)

The Conexant™ Single-Chip FaxEngine Integrated Analog (IA) device

(CX20415) is packaged in a 32-pin TQFP package and provides the analog

functionality of the modem. It serves as a voice/line codec and line interface

device between the CX9450 DSP and the PSTN. The DSP communicates

with the integrated analog device via a serial interface. The IA has an 8-bit

read from via the serial interface.

Codec

The voice/line codec is a monolithic CMOS integrated circuit operating off a

regulated analog 5V ±10% power supply. It consists of an A/D and D/A

converter path, with digital filtering and analog signal processing circuits to

realize a complete ITU G.714-compatible voice frequency linear

coder/decoder.

The codec is intended as a low power general purpose voice codec and line

interface for applications like fax, telephony, mobile telephony, etc. A block

diagram is shown in Figure 1. The diagram shows the principal functional

sections of the codec and double serial interfaces to the Conexant family of

DSPs.

Features

• Voice/Line Codec

− Delta-sigma ADC/DAC with

dynamic range >70 dB

− Line input and output for 600Ω

PSTN interface

− Differential speaker driver

capable of a 150 Ω load

− Single-ended line driver capable

of a 350 Ω load

− Differential microphone input

with internal gain and filtering

− Analog and digital filtering in

both directions

− Input/output mode selection and

control

• Power Requirements

− Analog power supply: 5 V

− Digital power supply: 3.3 V

• Package

− Codec: 32-pin TQFP

Control and Timing Logic

Serial Interface Control

SOUT

SIN

POR CTRLSIN MCLK ICLK FSYNC MODE[1:0]

RTLoop[1:0]

LineSel[1:0]

MICIN +

MICIN -

LINEO

LINEIN

LineIEn

ADC

DAC

Fs 2FsN

ADCGain DACGain

Vref

3rd

Order

LPF

2nd

Order

LPF

ADCGain

DACGain

Serial

Interface

Serial

Interface

Interpolation

Filter

Decimatio

Filter

4th

order

LPF

2nd

order

HPF

FsN

LPF

Switched

Capacitor

LPF

Fs Vref

Fs Vref Fs 2FsN

Fs FsN 2FsN

SpkOEn

SPKRO

SPKRO-

LineOEn

Analog

Controls

MicGain[1:0]

MicEn

VOX[1:0]

Line

Driver

SPKR

Driver

Figure 1. Integrated Analog Device Block Diagram

Single-Chip FaxEngine Codec Integrated Analog Device (CX20415)

2Conexant 100550B

Single-Chip FaxE ngine Family Characteristics and Ordering Information

Device Set

Number Description Marketing

Abbreviation Single-Chip

FaxEngine Integrated

Analog Device Full-Duplex

Speakerphone DTAM

Support

DSFE-L400-011 9600 Single-Chip FaxEngine SCE109 CXD9450-25 20415-11 (one) No No

DSFE-L400-001 9600 Single-Chip Fax Engine

with DTAM SCE109-V CXD9450-24 20415-11 (one) No Yes

DSFE-L400-021 9600 Single-Chip Fax Engine with

DTAM and Speak erphone Support SCE109-VS CXD9450-23 20415-11 (t wo) Yes Yes

DSFE-L410-001 14400 Single-Chip FaxEngine SCE114 CXD9450-15 20415-11 (one) No No

DSFE-L410-011 14400 Single-Chip Fax Engine

with DTAM SCE114-V CXD9450-14 20415-11 (one) No Yes

DSFE-L410-021 14400 Single-Chip Fax Engine with

DTAM and Speak erphone Support SCE114-VS CXD9450-13 20415-11 (t wo) Yes Yes

Revision History

Revision Date Comments

223DS (100550A) 08/25/99 Initial limit ed rel ease of docum ent

100550B 03/31/00 Reformat, new product name, add order i nfo

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Integrated Analog Device (CX20415) Single-Chip FaxEngine Codec

100550B Conexant 3

Microphone Input

This input provides programmable gain for a microphone

signal and low pass filtering to avoid aliasing before the

signal is converted into a digital format. The microphone

can be connected to this device either differentially or

single-ended. A programmable gain amplifier provides

four selectable gain settings from 0 to 30 dB.

Line Input

This input provides low pass filtering to avoid aliasing

before the signal is converted into a digital format. The

line input is single-ended and is AC coupled into the

device. The filter structure realizes a two pole LPF filter.

The gain on the line input is fixed to 0 dB. The input

impedance is 150K ohm minimum. Either Line input or

Microphone input or both can be selected by using the

LineIEn and MicEn control signals.

A/D Converter

The signal level out of the anti-aliasing filters can be as

high as 3.2V pp. To avoid a potential overload problem, 4

dB of attenuation can be provided at the ADC input. This

can be enabled using the ADC Gain control.

The ADC is a second order sigma-delta type ADC which

samples at a rate between 1.024 MHz and 2.048 MHz to

produce a programmable baseband sample, depending

on the decimation ratio programmed in the decimation

filter and the clock value. An option exists to disable the

HPF biquad filter and in this case the output is available

at a 16 KHz sample rate. The LPF biquad filter can also

be enabled or disabled.

D/A Converter

The incoming digital signal from the DSP is fed to a low-

pass interpolation filter and then to a second order delta-

sigma type DAC. The DAC gain is controlled by the

DACGn control signal. The DAC analog output drives a

switched capacitor analog filter.

The output of this filter is a differential 2V pp or 4V pp

signal depending on DAC Gain status. It is passed to a

passive continuous-time second order low pass filter

which removes signal images around the switched

capacitor clock frequency.

Speaker Output

The SPKR+ and SPKR- signals form a differential output

capable of driving a 150 Ω resistive load or a highly

capacitive (100 nF) ceramic receiver via dual 75 Ω series

resistors. This output is used to drive either the PSTN or

a handset earpiece.

The speaker driver is intended to buffer and drive the

low impedance speaker load with the signal selected

on its input. The microphone input, or the line input,

or the transmit output signal can be selected to be

the speaker output.

The speaker driver is enabled by using the SpkOEn

signal. The speaker driver has a very high input

impedance, while the line driver has a moderate

input impedance. Thus , the speaker driver does not

introduce gain loss when interfaced to a nominal

load.

Line Output

The main purpose of the line output stage is to buffer

the signal and drive the low impedance line load with

the signal selected on its input. The microphone

input, or the line input, or the speaker output can be

selected to be the output.

The line driver provides a single-ended output. Since

all internal signals are differential, the line driver

provides differential to single-ended conversion.

The load attenuation for the line driver output is

controlled by the VOX [1:0] lines in steps of -6 dB.

The line driver output can be tri-stated using the

control signal LineOEn.

Serial Interface

The codec provides two serial digital interfaces for

communication with the DSP. Depending upon the

configuration used to communicate with the DSP, all

clock signals are either provided by the DSP or by

the IA.

Two modes of serial interface are available: Primary

and Secondary. The first mode is used with the

Primary IA which utilizes the line codec and the

second mode is used with the Secondary IA which

utilizes the voice codec. Both modes are used in

support of the speakerphone option. Mode selection

is made as follows:

IA Type Mode 1 Mode 0

Primary 0 0

Secondary 0 1

Hardware Interface

A har dware interface diag r am of a typical system

design using the 32-pin package is shown in

Figure 2. The 32-pin codec pin assignment diagram

is shown in Figure 3.

The 32-pin codec signals are described in detail in

Table 1.

Single-Chip FaxEngine Codec Integrated Analog Device (CX20415)

4Conexant 100550B

Electrical Charact eri st i cs

The Integrated Analog device’s absolute maximum

ratings, recommended operating conditions, current and

power requirements, and digital interface electrical

characteristics are listed in Table 2 through Table 5,

respectively.

Package Dimensions

Package dimensions for the Integrated Analog

device are shown in Figure 4.

CXD9450

DSP IA

IA1CLK ICLK

IACLK MCLK

FSYNC

CTRLSINSR1IO

SOUT

SIN

SA1CLK

SR3IN

SR4OUT

PORGPO0

MODE 0

MODE 1

Typical Microphone

Circuit

Typical Speaker Circuit

Typical External Hybrid LINEIN

LINEO

SPKRO-

SPKRO+

MICIN +

MICIN -

GND

Connections for MODE 0

and MODE 1 pins are

shown for a Line IA.

Figure 2. Hardware Interface Diagram

223DS - IA Device 32-pin

CTRLSIN

Reserved

SOUT

SIN

FSYNC

POR

AVSS

MODE0

MODE1

Reserved

DVDD

DVSS

SPKRO-

SPKRO+

LINEO

LINEIN

MICIN+

MICIN-

MICBIAS

VREF

AGND

AVDD

AVSS

MCLK

ICLK

Figure 3. 32-Pin Integrated Analog Device - Pin Assignments

Integrated Analog Device (CX20415) Single-Chip FaxEngine Codec

100550B Conexant 5

Table 1. Integrated Analog Device Signal Description – 32-pin TQFP

Pin # Pin Name Type

(Note 1) Description

1 CTRLSIN I Serial control data input

2 Reserved — No connect i on al l owed

3 Reserved — No connect i on al l owed

4 SOUT O Serial data output

5 SIN I Serial data i nput

6 FSYNC I /O Frame sync

7 POR I Reset input , activ e l ow

8 AVSS I Analog Ground

9 LINEIN I-A Analog input to line pre-amp, ADC channel .

10 MICIN+ I Pos i t i ve diff erential analog i nput to mic rophone pream pl i fier

11 MICIN- I Negative di f ferential anal og i nput to microphone preamplifier

12 MICBI AS O 2.2 V nominal DC bias source for mic rophone

13 VREF O-A Analog reference volt age out put. Bypass to AVSS with 0.1µF c apac itor

14 AGND I-A Analog ground bias output. By pas s to AVSS with 0.1µF c apacitor

15 AVDD I-A Analog power supply

16 AVSS I-A Analog ground

17 LINEO O-A Line driver out put , DAC channel or filtered LINEIN, or filtered MICIN

18 SPKRO+ O-A Pos it ive speaker driv er output, DAC channel, or filtered LINE I N, or f ilt ered MICIN

19 SPKRO- O-A Negative speaker driv er output, DAC channel, or filtered LINE I N, or f iltered MICIN

20 DVSS I Digital ground

21 DVDD I Digital power supply

22 Reserved — No connect i on al l owed

23 MODE1 I Serial interface mode s el ection

24 MODE0 I Serial interface mode s el ection

25 Reserved — No connect i on al l owed

26 ICLK I Bit c l ock input/output for digital serial int erface

27-30 NC — No connect

31 MCLK I M ai n clock input

32 NC — No connect

Note 1:

I Digi tal I nput: CMOS receiver

O Digital Output: 4 m A driver

I-A Analog Input: A nalog receiv er

O-A Analog Output: A nal og dri ver

Single-Chip FaxEngine Codec Integrated Analog Device (CX20415)

6Conexant 100550B

Table 2. Absolute Maximum Ratings

Parameter Symbol Limits Units

Supply voltage V

Analog AVDD +7.0

Digital DVDD +3.6

Digital i nputs VIN –0.3 ≤ VIN < DVDD + 0.3 V V

Analog inputs VIN –0.3 ≤ VIN < AVDD + 0. 3 V V

DC input cl am p current IIK ±10 mA

DC output c l am p current IOK ±10 mA

Stati c disc harge voltage (25 ° C) VESD ±2500 V

Latch-up c urrent (25 °C) ITRIG ±150 mA

Operating tem perat ure range T A0 to +70 °C

Storage tem perature range TSTG –55 to +150 °C

Relative humidity HREL Up to 90% non-condens i ng, or a wet bulb

temperature up t o 35 °C, whichever is l ess.

Note: Vol t ages referenced to ground (Vss).

Table 3. Recommended Operating Conditions

Parameter Symbol Limits Units

Supply voltage V

Analog AVDD 5 ±10%

Digital DVDD 3.3 ± 10%

Operating ambient temperature range Ta 0 to +70 °C

Note: Vol tages referenced to ground (Vss).

Table 4. Current Requirements

Typical Current @ 25 °

°°

°C (mA)

Mode 3.3V 5V

Operating 4.6 6 mA

Sleep < 0.5 10 µA

Table 5. Digital Interface Electrical Characteristics

Parameter Symbol Test Conditions Min Max Unit

Input high v ol tage (Logic 1) Vih DVDD = 3.3 V 2.2 V

Input low voltage (Logic 0) Vil DVDD = 3.3 V 1.1 V

Output high v ol tage (Logic 1) Voh DVDD = 3. 3 V 2.5 V

Output low v ol tage (Logic 0) V ol DVDD = 3.3 V 0.4 V

Input leak age current Iin DVDD = 3.3 V ±10 µA

Notes:

1. Applies to types: I and O unless otherwise indi cated.

2. All voltages referenced t o ground (VSS). Currents are posit i ve when flowing i n t o the device.

Integrated Analog Device (CX20415) Single-Chip FaxEngine Codec

100550B Conexant 7

DETAIL A

Millimeters

0.05

8.75

0.5

0.30

0.13

1.6 MAX

0.15

1.4 REF

9.25

7.0 REF

5.6 REF

0.75

1.0 REF

0.80 BSC

0.40

0.19

0.10 MAX

0.0020

0.3445

0.0197

0.0118

0.0051

Coplanarity

Min. Max. Min. Max.

Inches

Dim.

Ref: 32-PIN TQFP (GP00-D262)

Metric values (millimeters) should be used for

PCB layout. English values (inches) are

converted from metric values and may include

round-off errors.

0.0630 MAX

0.0059

0.0551 REF

0.3642

0.2756 REF

0.2205 REF

0.0295

0.0394 REF

0.0315 BSC

0.0157

0.0075

0.004 MAX

PD-TQFP-32 (040395)

DETAIL A

DD2

PIN 1

REF

Figure 4. Integrated Analog (IA) Device Package Dimensions – 32-Pin TQFP

Further Information

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