LatticeXP2TM Family Handbook HB1004 Version 03.2, January 2012 LatticeXP2 Family Handbook Table of Contents January 2012 Section I. LatticeXP2 Family Data Sheet Introduction Features ............................................................................................................................................................. 1-1 Introduction ........................................................................................................................................................ 1-2 Architecture Architecture Overview ........................................................................................................................................ 2-1 PFU Blocks ........................................................................................................................................................ 2-2 Slice .......................................................................................................................................................... 2-3 Modes of Operation................................................................................................................................... 2-5 Routing............................................................................................................................................................... 2-6 sysCLOCK Phase Locked Loops (PLL) ............................................................................................................. 2-6 Clock Dividers .................................................................................................................................................... 2-7 Clock Distribution Network ................................................................................................................................. 2-8 Primary Clock Sources.............................................................................................................................. 2-8 Secondary Clock/Control Sources .......................................................................................................... 2-10 Edge Clock Sources................................................................................................................................ 2-11 Primary Clock Routing ............................................................................................................................ 2-12 Dynamic Clock Select (DCS) .................................................................................................................. 2-12 Secondary Clock/Control Routing ........................................................................................................... 2-12 Slice Clock Selection............................................................................................................................... 2-14 Edge Clock Routing ................................................................................................................................ 2-15 sysMEM Memory ............................................................................................................................................. 2-16 sysMEM Memory Block........................................................................................................................... 2-16 Bus Size Matching .................................................................................................................................. 2-16 FlashBAK EBR Content Storage............................................................................................................. 2-16 Memory Cascading ................................................................................................................................. 2-17 Single, Dual and Pseudo-Dual Port Modes............................................................................................. 2-17 Memory Core Reset ................................................................................................................................ 2-17 EBR Asynchronous Reset....................................................................................................................... 2-18 sysDSPTM Block ............................................................................................................................................... 2-18 sysDSP Block Approach Compare to General DSP ............................................................................... 2-18 sysDSP Block Capabilities ...................................................................................................................... 2-19 MULT sysDSP Element .......................................................................................................................... 2-20 MAC sysDSP Element ............................................................................................................................ 2-21 MULTADDSUB sysDSP Element ........................................................................................................... 2-22 MULTADDSUBSUM sysDSP Element ................................................................................................... 2-23 Clock, Clock Enable and Reset Resources ............................................................................................ 2-23 Signed and Unsigned with Different Widths............................................................................................ 2-24 OVERFLOW Flag from MAC .................................................................................................................. 2-24 IPexpressTM............................................................................................................................................. 2-25 Optimized DSP Functions ................................................................................................................................ 2-25 Resources Available in the LatticeXP2 Family........................................................................................ 2-25 LatticeXP2 DSP Performance................................................................................................................. 2-25 Programmable I/O Cells (PIC) ......................................................................................................................... 2-26 PIO ................................................................................................................................................................... 2-27 Input Register Block ................................................................................................................................ 2-27 Output Register Block ............................................................................................................................. 2-28 Tristate Register Block ............................................................................................................................ 2-30 (c) 2012 Lattice Semiconductor Corp. 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The specifications and information herein are subject to change without notice. www.latticesemi.com 1 Table of Contents LatticeXP2 Family Handbook Lattice Semiconductor Control Logic Block ................................................................................................................................. 2-30 DDR Memory Support...................................................................................................................................... 2-30 DLL Calibrated DQS Delay Block ........................................................................................................... 2-32 Polarity Control Logic .............................................................................................................................. 2-33 DQSXFER............................................................................................................................................... 2-34 sysIO Buffer ..................................................................................................................................................... 2-34 sysIO Buffer Banks ................................................................................................................................. 2-34 Typical sysIO I/O Behavior During Power-up.......................................................................................... 2-35 Supported sysIO Standards .................................................................................................................... 2-35 Hot Socketing.......................................................................................................................................... 2-37 IEEE 1149.1-Compliant Boundary Scan Testability......................................................................................... 2-37 flexiFLASH Device Configuration..................................................................................................................... 2-38 Serial TAG Memory................................................................................................................................. 2-39 Live Update Technology ......................................................................................................................... 2-39 Soft Error Detect (SED) Support ............................................................................................................. 2-40 On-Chip Oscillator................................................................................................................................... 2-40 Density Shifting ................................................................................................................................................ 2-41 DC and Switching Characteristics Absolute Maximum Ratings ............................................................................................................................... 3-1 Recommended Operating Conditions ................................................................................................................ 3-1 On-Chip Flash Memory Specifications............................................................................................................... 3-1 Hot Socketing Specifications.............................................................................................................................. 3-2 ESD Performance .............................................................................................................................................. 3-2 DC Electrical Characteristics.............................................................................................................................. 3-2 Supply Current (Standby)................................................................................................................................... 3-3 Initialization Supply Current ............................................................................................................................... 3-4 Programming and Erase Flash Supply Current ................................................................................................. 3-5 sysIO Recommended Operating Conditions...................................................................................................... 3-6 sysIO Single-Ended DC Electrical Characteristics............................................................................................. 3-7 sysIO Differential Electrical Characteristics ....................................................................................................... 3-8 LVDS......................................................................................................................................................... 3-8 Differential HSTL and SSTL...................................................................................................................... 3-8 LVDS25E .................................................................................................................................................. 3-8 LVCMOS33D ............................................................................................................................................ 3-9 BLVDS .................................................................................................................................................... 3-10 LVPECL .................................................................................................................................................. 3-11 RSDS ...................................................................................................................................................... 3-12 MLVDS.................................................................................................................................................... 3-13 Typical Building Block Function Performance.................................................................................................. 3-14 Pin-to-Pin Performance (LVCMOS25 12mA Drive) ................................................................................ 3-14 Register-to-Register Performance .......................................................................................................... 3-14 Derating Timing Tables .................................................................................................................................... 3-15 LatticeXP2 External Switching Characteristics ................................................................................................ 3-16 LatticeXP2 Internal Switching Characteristics.................................................................................................. 3-19 EBR Timing Diagrams...................................................................................................................................... 3-22 LatticeXP2 Family Timing Adders .................................................................................................................... 3-24 sysCLOCK PLL Timing .................................................................................................................................... 3-27 LatticeXP2 sysCONFIG Port Timing Specifications......................................................................................... 3-28 On-Chip Oscillator and Configuration Master Clock Characteristics................................................................ 3-29 Flash Download Time (from On-Chip Flash to SRAM) .................................................................................... 3-30 Flash Program Time......................................................................................................................................... 3-30 Flash Erase Time ............................................................................................................................................. 3-30 FlashBAK Time (from EBR to Flash) ............................................................................................................... 3-31 JTAG Port Timing Specifications ..................................................................................................................... 3-31 2 Table of Contents LatticeXP2 Family Handbook Lattice Semiconductor Switching Test Conditions................................................................................................................................ 3-33 Pinout Information Signal Descriptions ............................................................................................................................................ 4-1 PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin .................................................... 4-3 Pin Information Summary................................................................................................................................... 4-4 Logic Signal Connections................................................................................................................................... 4-5 Thermal Management ........................................................................................................................................ 4-5 For Further Information ...................................................................................................................................... 4-5 Ordering Information Part Number Description.................................................................................................................................... 5-1 Ordering Information .......................................................................................................................................... 5-1 Lead-Free Packaging................................................................................................................................ 5-2 Conventional Packaging ........................................................................................................................... 5-5 Supplemental Information For Further Information ...................................................................................................................................... 6-1 LatticeXP2 Family Data Sheet Revision History Revision History ................................................................................................................................................. 7-1 Section II. LatticeXP2 Family Technical Notes LatticeXP2 sysIO Usage Guide Introduction ........................................................................................................................................................ 8-1 sysIO Buffer Overview ....................................................................................................................................... 8-1 Supported sysIO Standards ............................................................................................................................... 8-1 sysIO Banking Scheme...................................................................................................................................... 8-3 SPI Flash Interface.................................................................................................................................... 8-3 JTAG Interface .......................................................................................................................................... 8-3 VCCIO (1.2V/1.5V/1.8V/2.5V/3.3V) ............................................................................................................ 8-4 VCCAUX (3.3V) ........................................................................................................................................... 8-4 VCCJ (1.2V/1.5V/1.8V/2.5V/3.3V).............................................................................................................. 8-4 Input Reference Voltage (VREF1, VREF2)................................................................................................... 8-4 VREF1 for DDR Memory Interface ............................................................................................................. 8-4 Mixed Voltage Support in a Bank.............................................................................................................. 8-4 sysIO Standards Supported by Bank ........................................................................................................ 8-5 LVCMOS Buffer Configurations ......................................................................................................................... 8-6 Bus Maintenance Circuit ........................................................................................................................... 8-6 Programmable Drive ................................................................................................................................. 8-6 Programmable Slew Rate ......................................................................................................................... 8-6 Open-Drain Control ................................................................................................................................... 8-6 Differential SSTL and HSTL support......................................................................................................... 8-6 PCI Support with Programmable PCICLAMP ........................................................................................... 8-7 Programmable Input Delay ....................................................................................................................... 8-7 Software sysIO Attributes................................................................................................................................... 8-7 IO_TYPE ................................................................................................................................................... 8-7 OPENDRAIN............................................................................................................................................. 8-8 DRIVE ....................................................................................................................................................... 8-8 PULLMODE .............................................................................................................................................. 8-9 PCICLAMP................................................................................................................................................ 8-9 SLEWRATE .............................................................................................................................................. 8-9 FIXEDDELAY.......................................................................................................................................... 8-10 INBUF ..................................................................................................................................................... 8-10 DIN/DOUT............................................................................................................................................... 8-10 LOC......................................................................................................................................................... 8-10 Design Considerations and Usage................................................................................................................... 8-10 Banking Rules ......................................................................................................................................... 8-10 3 Table of Contents LatticeXP2 Family Handbook Lattice Semiconductor Differential I/O Rules ............................................................................................................................... 8-10 Differential I/O Implementation......................................................................................................................... 8-11 LVDS....................................................................................................................................................... 8-11 BLVDS .................................................................................................................................................... 8-11 RSDS ...................................................................................................................................................... 8-11 LVPECL .................................................................................................................................................. 8-11 Differential SSTL and HSTL.................................................................................................................... 8-11 MLVDS.................................................................................................................................................... 8-11 Technical Support Assistance.......................................................................................................................... 8-11 Revision History ............................................................................................................................................... 8-11 Appendix A. HDL Attributes for Synplicity(R) and Precision(R) RTL Synthesis...................................................... 8-12 VHDL Synplicity/Precision RTL Synthesis .............................................................................................. 8-12 Verilog Synplicity..................................................................................................................................... 8-14 Verilog Precision ..................................................................................................................................... 8-15 Appendix B. sysIO Attributes Using the Design Planner User Interface .......................................................... 8-16 Appendix C. sysIO Attributes Using Preference File (ASCII File) .................................................................... 8-18 IOBUF ..................................................................................................................................................... 8-18 LOCATE.................................................................................................................................................. 8-18 USE DIN CELL........................................................................................................................................ 8-19 USE DOUT CELL.................................................................................................................................... 8-19 GROUP VREF ........................................................................................................................................ 8-19 Appendix D. sysIO Attributes Using the Diamond Spreadsheet View User Interface...................................... 8-20 LatticeXP2 sysCLOCK PLL Design and Usage Guide Introduction ........................................................................................................................................................ 9-1 Clock/Control Distribution Network .................................................................................................................... 9-1 LatticeXP2 Top Level View ................................................................................................................................ 9-1 Primary Clocks ................................................................................................................................................... 9-2 Secondary Clocks .............................................................................................................................................. 9-2 Edge Clocks ....................................................................................................................................................... 9-2 Primary Clock Note ............................................................................................................................................ 9-3 Specifying Clocks in the Design Tools ............................................................................................................... 9-3 Primary-Pure and Primary-DCS................................................................................................................ 9-3 Global Primary Clock and Quadrant Primary Clock ........................................................................................... 9-3 Global Primary Clock ................................................................................................................................ 9-3 Quadrant Primary Clock............................................................................................................................ 9-4 sysCLOCKTM PLL .............................................................................................................................................. 9-4 Functional Description........................................................................................................................................ 9-5 PLL Divider and Delay Blocks................................................................................................................... 9-5 PLL Inputs and Outputs ..................................................................................................................................... 9-5 CLKI Input ................................................................................................................................................. 9-5 RST Input .................................................................................................................................................. 9-5 RSTK Input................................................................................................................................................ 9-6 CLKFB Input.............................................................................................................................................. 9-6 CLKOP Output .......................................................................................................................................... 9-6 CLKOS Output with Phase and Duty Cycle Select ................................................................................... 9-6 CLKOK Output with Lower Frequency ...................................................................................................... 9-6 CLKOK2 Output ........................................................................................................................................ 9-6 LOCK Output............................................................................................................................................. 9-6 Dynamic Phase and Dynamic Duty Cycle Adjustment.............................................................................. 9-6 WRDEL (Write Delay) ............................................................................................................................... 9-7 PLL Attributes..................................................................................................................................................... 9-7 FIN ............................................................................................................................................................ 9-7 CLKI_DIV, CLKFB_DIV, CLKOP_DIV, CLKOK_DIV ................................................................................ 9-7 FREQUENCY_PIN_CLKI, FREQUENCY_PIN_CLKOP, FREQUENCY_PIN_CLKOK ............................ 9-7 4 Table of Contents LatticeXP2 Family Handbook Lattice Semiconductor CLKOP Frequency Tolerance ................................................................................................................... 9-7 LatticeXP2 PLL Primitive Definition.................................................................................................................... 9-8 EPLLD Design Migration from LatticeECP2 to LatticeXP2 ....................................................................... 9-8 Dynamic Phase/Duty Mode....................................................................................................................... 9-8 Dynamic Phase Adjustment/Duty Cycle Select.................................................................................................. 9-9 PLL Usage in IPexpressTM ............................................................................................................................... 9-10 Configuration Tab.................................................................................................................................... 9-11 PLL Modes of Operation .................................................................................................................................. 9-13 PLL Clock Injection Removal .................................................................................................................. 9-13 PLL Clock Phase Adjustment.................................................................................................................. 9-14 IPexpress Output ............................................................................................................................................. 9-14 Use of the Pre-Map Preference Editor ............................................................................................................. 9-15 Clock Dividers (CLKDIV).................................................................................................................................. 9-15 CLKDIV Primitive Definition .................................................................................................................... 9-15 CLKDIV Declaration in VHDL Source Code............................................................................................ 9-16 CLKDIV Usage with Verilog - Example ................................................................................................... 9-17 CLKDIV Example Circuits ....................................................................................................................... 9-17 Reset Behavior........................................................................................................................................ 9-18 Release Behavior.................................................................................................................................... 9-18 CLKDIV Inputs-to-Outputs Delay Matching............................................................................................. 9-19 DCS (Dynamic Clock Select) ........................................................................................................................... 9-19 DCS Primitive Definition.......................................................................................................................... 9-19 DCS Timing Diagrams ............................................................................................................................ 9-20 DCS Usage with VHDL - Example .......................................................................................................... 9-21 DCS Usage with Verilog - Example ........................................................................................................ 9-22 Oscillator (OSCE).................................................................................................................................... 9-22 OSC Primitive Symbol (OSCE) ............................................................................................................... 9-22 OSC Usage with VHDL - Example.......................................................................................................... 9-23 OSC Usage with Verilog - Example ........................................................................................................ 9-23 Setting Clock Preferences....................................................................................................................... 9-23 Power Supplies ................................................................................................................................................ 9-23 Technical Support Assistance.......................................................................................................................... 9-23 Revision History ............................................................................................................................................... 9-23 Appendix A. Primary Clock Sources and Distribution ...................................................................................... 9-24 Appendix B. PLL, CLKDIV and ECLK Locations and Connectivity .................................................................. 9-25 Appendix C. Clock Preferences ....................................................................................................................... 9-26 ASIC........................................................................................................................................................ 9-26 FREQUENCY.......................................................................................................................................... 9-26 MAXSKEW.............................................................................................................................................. 9-26 MULTICYCLE ......................................................................................................................................... 9-26 PERIOD .................................................................................................................................................. 9-26 PROHIBIT ............................................................................................................................................... 9-26 USE PRIMARY ....................................................................................................................................... 9-26 USE SECONDARY ................................................................................................................................. 9-26 USE EDGE.............................................................................................................................................. 9-27 CLOCK_TO_OUT ................................................................................................................................... 9-27 INPUT_SETUP ....................................................................................................................................... 9-27 PLL_PHASE_BACK................................................................................................................................ 9-27 LatticeXP2 Memory Usage Guide Introduction ...................................................................................................................................................... 10-1 Memories in LatticeXP2 Devices ..................................................................................................................... 10-1 Utilizing IPexpress............................................................................................................................................ 10-2 IPexpress Flow........................................................................................................................................ 10-3 Memory Modules.............................................................................................................................................. 10-6 5 Table of Contents LatticeXP2 Family Handbook Lattice Semiconductor Single Port RAM (RAM_DQ) - EBR Based ............................................................................................ 10-6 True Dual Port RAM (RAM_DP_TRUE) - EBR Based ......................................................................... 10-11 Pseudo Dual Port RAM (RAM_DP) - EBR Based ................................................................................ 10-17 Read Only Memory (ROM) - EBR Based.............................................................................................. 10-20 First In First Out (FIFO, FIFO_DC) - EBR Based................................................................................. 10-23 Distributed Single Port RAM (Distributed_SPRAM) - PFU Based........................................................ 10-35 Distributed Dual Port RAM (Distributed_DPRAM) - PFU Based .......................................................... 10-37 Distributed ROM (Distributed_ROM) - PFU Based .............................................................................. 10-39 User TAG Memory ................................................................................................................................ 10-41 Basic Specifications for TAG Memory............................................................................................................ 10-41 General Description .............................................................................................................................. 10-43 Pin Descriptions .................................................................................................................................... 10-43 SPI Operations...................................................................................................................................... 10-44 Specifications and Timing Diagrams..................................................................................................... 10-49 Initializing Memory ......................................................................................................................................... 10-50 Initialization File Format ........................................................................................................................ 10-50 Binary File ............................................................................................................................................. 10-51 Hex File ................................................................................................................................................. 10-51 Addressed Hex...................................................................................................................................... 10-51 FlashBakTM Capability.................................................................................................................................... 10-52 Technical Support Assistance........................................................................................................................ 10-52 Revision History ............................................................................................................................................. 10-53 Appendix A. Attribute Definitions.................................................................................................................... 10-54 DATA_WIDTH....................................................................................................................................... 10-54 REGMODE............................................................................................................................................ 10-54 RESETMODE ....................................................................................................................................... 10-54 CSDECODE.......................................................................................................................................... 10-54 WRITEMODE........................................................................................................................................ 10-54 GSR ...................................................................................................................................................... 10-54 LatticeXP2 High-Speed I/O Interface Introduction ...................................................................................................................................................... 11-1 DDR and DDR2 SDRAM Interfaces Overview................................................................................................. 11-1 Implementing DDR Memory Interfaces with LatticeXP2 Devices .................................................................... 11-3 DQS Grouping......................................................................................................................................... 11-3 DDR Software Primitives......................................................................................................................... 11-4 Memory Read Implementation ....................................................................................................................... 11-14 DLL Compensated DQS Delay Elements ............................................................................................. 11-14 DQS Transition Detect or Automatic Clock Polarity Select ................................................................... 11-14 Data Valid Module................................................................................................................................. 11-15 DDR I/O Register Implementation......................................................................................................... 11-15 Memory Read Implementation in Software ........................................................................................... 11-15 Read Timing Waveforms....................................................................................................................... 11-16 Memory Write Implementation .............................................................................................................. 11-19 Generic High Speed DDR Implementation .................................................................................................... 11-22 Generic DDR Software Primitives ......................................................................................................... 11-23 Design Rules/Guidelines....................................................................................................................... 11-34 DDR Usage in ispLEVER IPexpress.............................................................................................................. 11-34 DDR Generic......................................................................................................................................... 11-35 Configuration Tab.................................................................................................................................. 11-36 DDR_MEM ............................................................................................................................................ 11-36 Configuration Tab.................................................................................................................................. 11-37 FCRAM ("Fast Cycle Random Access Memory") Interface ........................................................................... 11-39 Board Design Guidelines ............................................................................................................................... 11-39 References..................................................................................................................................................... 11-39 6 Table of Contents LatticeXP2 Family Handbook Lattice Semiconductor Technical Support Assistance........................................................................................................................ 11-40 Revision History ............................................................................................................................................. 11-40 Appendix A. DDR Generation using Diamond IPexpress .............................................................................. 11-41 DDR Generic......................................................................................................................................... 11-41 Configuration Tab.................................................................................................................................. 11-42 DDR_MEM ............................................................................................................................................ 11-43 Configuration Tab.................................................................................................................................. 11-44 Power Estimation and Management for LatticeXP2 Devices Introduction ...................................................................................................................................................... 12-1 Power Supply Sequencing and Hot Socketing................................................................................................. 12-1 Recommended Power-up Sequence ...................................................................................................... 12-1 Power Calculator Hardware Assumptions........................................................................................................ 12-1 Power Calculation Equations ........................................................................................................................... 12-1 Power Calculations ................................................................................................................................. 12-2 Using the Power Calculator.............................................................................................................................. 12-3 Starting the Power Calculator ................................................................................................................. 12-3 Creating a Power Calculator Project ....................................................................................................... 12-4 Power Calculator Main Window .............................................................................................................. 12-5 Power Calculator Wizard......................................................................................................................... 12-7 Creating a New Project Without the NCD File ...................................................................................... 12-10 Creating a New Project with the NCD File ............................................................................................ 12-10 Opening an Existing Project.................................................................................................................. 12-12 Importing a Simulation File (VCD)......................................................................................................... 12-12 Importing a Trace Report File (TWR).................................................................................................... 12-13 Activity Factor and Toggle Rate ..................................................................................................................... 12-13 Ambient and Junction Temperatures and Airflow .......................................................................................... 12-14 Managing Power Consumption ...................................................................................................................... 12-14 Power Calculator Assumptions ...................................................................................................................... 12-15 Technical Support Assistance........................................................................................................................ 12-15 Revision History ............................................................................................................................................. 12-15 LatticeXP2 sysDSP Usage Guide Introduction ...................................................................................................................................................... 13-1 sysDSP Block Hardware .................................................................................................................................. 13-1 sysDSP Block Software ................................................................................................................................... 13-2 Overview ................................................................................................................................................. 13-2 Targeting sysDSP Block Using IPexpress .............................................................................................. 13-2 Targeting the sysDSP Block by Inference........................................................................................................ 13-9 sysDSP Blocks in the Report File .................................................................................................................. 13-11 MAP Report File.................................................................................................................................... 13-11 Post PAR Report File ............................................................................................................................ 13-12 Targeting the sysDSP Block Using Simulink.................................................................................................. 13-13 Simulink Overview................................................................................................................................. 13-13 Targeting the sysDSP Block by Instantiating Primitives................................................................................. 13-14 sysDSP Block Control Signal and Data Signal Descriptions.......................................................................... 13-14 Technical Support Assistance........................................................................................................................ 13-14 Revision History ............................................................................................................................................. 13-15 Appendix A. DSP Block Primitives ................................................................................................................. 13-16 MULT18X18B........................................................................................................................................ 13-16 MULT18X18ADDSUBB......................................................................................................................... 13-16 MULT18X18ADDSUBSUMB................................................................................................................. 13-17 MULT18X18MACB................................................................................................................................ 13-19 MULT36X36B........................................................................................................................................ 13-20 MULT9X9B............................................................................................................................................ 13-21 MULT9X9ADDSUBB............................................................................................................................. 13-21 7 Table of Contents LatticeXP2 Family Handbook Lattice Semiconductor MULT9X9ADDSUBSUMB..................................................................................................................... 13-22 LatticeXP2 sysCONFIG Usage Guide Introduction ...................................................................................................................................................... 14-1 Programming Overview.................................................................................................................................... 14-1 Configuration Pins............................................................................................................................................ 14-2 sysCONFIG Pins..................................................................................................................................... 14-3 Programming Sequence .................................................................................................................................. 14-7 SRAM...................................................................................................................................................... 14-7 Flash Background ................................................................................................................................... 14-7 ispJTAG Pins ................................................................................................................................................... 14-8 TDO......................................................................................................................................................... 14-8 TDI .......................................................................................................................................................... 14-8 TMS......................................................................................................................................................... 14-8 TCK ......................................................................................................................................................... 14-8 VCCJ....................................................................................................................................................... 14-8 Configuration and JTAG Voltage Levels ................................................................................................. 14-8 Configuration Modes and Options.................................................................................................................... 14-9 Configuration Options ............................................................................................................................. 14-9 Slave SPI Mode ...................................................................................................................................... 14-9 Master SPI Mode .................................................................................................................................. 14-10 Self Download Mode ............................................................................................................................. 14-10 ispJTAG Mode ...................................................................................................................................... 14-10 Wake Up Options ........................................................................................................................................... 14-11 Wake Up Sequence .............................................................................................................................. 14-11 Software Selectable Options.......................................................................................................................... 14-12 Slave SPI Port....................................................................................................................................... 14-12 Master SPI Port..................................................................................................................................... 14-13 Configuration Mode............................................................................................................................... 14-13 DONE Open Drain ................................................................................................................................ 14-13 DONE External...................................................................................................................................... 14-13 Master Clock Selection ......................................................................................................................... 14-13 Security ................................................................................................................................................. 14-14 Wake Up Sequence .............................................................................................................................. 14-14 Wake On Lock Selection....................................................................................................................... 14-14 Power Save........................................................................................................................................... 14-14 One Time Programmable Fuse...................................................................................................................... 14-14 User GOE....................................................................................................................................................... 14-14 Tag Memory ................................................................................................................................................... 14-15 Slave SPI Mode Operation.................................................................................................................... 14-16 User Flash...................................................................................................................................................... 14-16 Technical Support Assistance........................................................................................................................ 14-17 Revision History ............................................................................................................................................. 14-17 LatticeXP2 Configuration Encryption and Security Usage Guide Introduction ...................................................................................................................................................... 15-1 Encryption/Decryption Flow ............................................................................................................................. 15-1 Encrypting the JEDEC File............................................................................................................................... 15-1 ispLEVER Flow ....................................................................................................................................... 15-2 ispVM Flow.............................................................................................................................................. 15-2 Programming the Key into the Device..................................................................................................... 15-4 Security Bit for the Configuration and User Flash (CONFIG_SECURE).......................................................... 15-6 Advanced Security Settings ............................................................................................................................. 15-6 One-Time Programmable (OTP) or Permanent Lock ...................................................................................... 15-6 Flash Protect .................................................................................................................................................... 15-7 Changing Flash Protect........................................................................................................................... 15-7 8 Table of Contents LatticeXP2 Family Handbook Lattice Semiconductor Encryption ........................................................................................................................................................ 15-8 Usercode in Encrypted Files ............................................................................................................................ 15-8 Decryption Flow ............................................................................................................................................... 15-8 Verifying a Configuration.................................................................................................................................. 15-9 References....................................................................................................................................................... 15-9 Technical Support Assistance.......................................................................................................................... 15-9 Revision History ............................................................................................................................................... 15-9 LatticeXP2 Soft Error Detection (SED) Usage Guide Introduction ...................................................................................................................................................... 16-1 SED Overview.................................................................................................................................................. 16-1 Basic SED and One-shot SED Modes ............................................................................................................. 16-2 Basic SED ............................................................................................................................................... 16-2 One-Shot SED ........................................................................................................................................ 16-2 Hardware Description....................................................................................................................................... 16-2 Signal Descriptions .......................................................................................................................................... 16-2 SEDCLKIN .............................................................................................................................................. 16-3 OSC_DIV ................................................................................................................................................ 16-3 SEDENABLE........................................................................................................................................... 16-3 SEDCLKOUT .......................................................................................................................................... 16-3 SEDSTART ............................................................................................................................................. 16-3 SEDFRCERRN ....................................................................................................................................... 16-3 SEDINPROG........................................................................................................................................... 16-4 SEDDONE .............................................................................................................................................. 16-4 SEDERR ................................................................................................................................................. 16-4 SED Flow ......................................................................................................................................................... 16-4 SED Run Time ................................................................................................................................................. 16-5 Sample Code ................................................................................................................................................... 16-6 Basic SED VHDL Example ..................................................................................................................... 16-6 One Shot SED in VHDL .......................................................................................................................... 16-7 Basic SED Verilog Example.................................................................................................................... 16-8 One-Shot SED in Verilog ........................................................................................................................ 16-9 Technical Support Assistance.......................................................................................................................... 16-9 Revision History ............................................................................................................................................. 16-10 Introduction ...................................................................................................................................................... 17-1 LatticeXP2 Dual Boot Feature Dual Boot Feature ................................................................................................................................... 17-2 Definitions ........................................................................................................................................................ 17-3 SPI .......................................................................................................................................................... 17-3 Master SPI .............................................................................................................................................. 17-3 SDM (Self Download Mode).................................................................................................................... 17-3 Erase....................................................................................................................................................... 17-3 Program .................................................................................................................................................. 17-3 Configure................................................................................................................................................. 17-3 Primary Boot ........................................................................................................................................... 17-3 Golden Boot ............................................................................................................................................ 17-3 Dual Boot ................................................................................................................................................ 17-4 Refresh.................................................................................................................................................... 17-4 Bitstream Data File (.BIT File)................................................................................................................. 17-4 JEDEC File (.JED File)............................................................................................................................ 17-4 TransFR .................................................................................................................................................. 17-4 Security ................................................................................................................................................... 17-4 SED CRC ................................................................................................................................................ 17-4 One Shot SED......................................................................................................................................... 17-4 Background Mode (User Mode) .............................................................................................................. 17-4 9 Table of Contents LatticeXP2 Family Handbook Lattice Semiconductor Direct Mode (IEEE 1532 Access Modal State) ....................................................................................... 17-4 Purpose............................................................................................................................................................ 17-4 Resource.......................................................................................................................................................... 17-5 Dual Boot Mode ............................................................................................................................................... 17-6 Critical Points ................................................................................................................................................... 17-7 Programming Procedures ................................................................................................................................ 17-9 Part 1: Program the Golden Pattern into the SPI Flash Devices ............................................................ 17-9 Part 2: Program the Primary Pattern into LatticeXP2 Embedded Flash ............................................... 17-12 Reference Material......................................................................................................................................... 17-14 LatticeXP2 Bitstream File Format ......................................................................................................... 17-14 Implement SPI Flash Programming on ispVM System ......................................................................... 17-14 References..................................................................................................................................................... 17-15 Technical Support Assistance........................................................................................................................ 17-16 Revision History ............................................................................................................................................. 17-16 ....................................................................................................................................................................... 17-16 LatticeXP2 Hardware Checklist Introduction ...................................................................................................................................................... 18-1 Power Supply ................................................................................................................................................... 18-1 Power Supply Sequencing ...................................................................................................................... 18-1 Power Supply Ramp ............................................................................................................................... 18-2 Power Estimation .................................................................................................................................... 18-2 Configuration.................................................................................................................................................... 18-2 JTAG Interface ........................................................................................................................................ 18-3 I/O Interface and Critical Pins .......................................................................................................................... 18-3 I/O Pin Assignments Around VCCPLL ...................................................................................................... 18-3 DDR/DDR2 Memory Interface Pin Assignments..................................................................................... 18-4 True-LVDS Output Pin Assignments....................................................................................................... 18-4 HSTL and SSTL Pin Assignments .......................................................................................................... 18-4 PCI Clamp Pin Assignment..................................................................................................................... 18-4 Test Output Enable (TOE) ...................................................................................................................... 18-4 Checklist........................................................................................................................................................... 18-5 Technical Support Assistance.......................................................................................................................... 18-5 Revision History ............................................................................................................................................... 18-5 Section III. LatticeXP2 Family Handbook Revision History Revision History ............................................................................................................................................... 19-1 10 Section I. LatticeXP2 Family Data Sheet DS1009 Version 01.8, January 2012 LatticeXP2 Family Data Sheet Introduction January 2012 Data Sheet DS1009 Flexible I/O Buffer Features * sysIOTM buffer supports: - LVCMOS 33/25/18/15/12; LVTTL - SSTL 33/25/18 class I, II - HSTL15 class I; HSTL18 class I, II - PCI - LVDS, Bus-LVDS, MLVDS, LVPECL, RSDS flexiFLASHTM Architecture * * * * * * Instant-on Infinitely reconfigurable Single chip FlashBAKTM technology Serial TAG memory Design security Pre-engineered Source Synchronous Interfaces Live Update Technology * DDR / DDR2 interfaces up to 200 MHz * 7:1 LVDS interfaces support display applications * XGMII * TransFRTM technology * Secure updates with 128 bit AES encryption * Dual-boot with external SPI Density And Package Options sysDSPTM Block * 5k to 40k LUT4s, 86 to 540 I/Os * csBGA, TQFP, PQFP, ftBGA and fpBGA packages * Density migration supported * Three to eight blocks for high performance Multiply and Accumulate * 12 to 32 18x18 multipliers * Each block supports one 36x36 multiplier or four 18x18 or eight 9x9 multipliers Flexible Device Configuration * SPI (master and slave) Boot Flash Interface * Dual Boot Image supported * Soft Error Detect (SED) macro embedded Embedded and Distributed Memory * Up to 885 Kbits sysMEMTM EBR * Up to 83 Kbits Distributed RAM System Level Support * IEEE 1149.1 and IEEE 1532 Compliant * On-chip oscillator for initialization & general use * Devices operate with 1.2V power supply sysCLOCKTM PLLs * Up to four analog PLLs per device * Clock multiply, divide and phase shifting Table 1-1. LatticeXP2 Family Selection Guide Device LUTs (K) XP2-5 XP2-8 XP2-17 XP2-30 XP2-40 5 8 17 29 40 Distributed RAM (KBits) 10 18 35 56 83 EBR SRAM (KBits) 166 221 276 387 885 EBR SRAM Blocks 9 12 15 21 48 sysDSP Blocks 3 4 5 7 8 18 x 18 Multipliers 12 16 20 28 32 VCC Voltage 1.2 1.2 1.2 1.2 1.2 GPLL Max Available I/O 2 2 4 4 4 172 201 358 472 540 86 86 Packages and I/O Combinations 132-Ball csBGA (8 x 8 mm) 144-Pin TQFP (20 x 20 mm) 100 100 208-Pin PQFP (28 x 28 mm) 146 146 256-Ball ftBGA (17 x17 mm) 172 201 484-Ball fpBGA (23 x 23 mm) 672-Ball fpBGA (27 x 27 mm) 146 201 201 358 363 363 472 540 (c) 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1-1 DS1009 Introduction_01.3 Introduction LatticeXP2 Family Data Sheet Lattice Semiconductor Introduction LatticeXP2 devices combine a Look-up Table (LUT) based FPGA fabric with non-volatile Flash cells in an architecture referred to as flexiFLASH. The flexiFLASH approach provides benefits including instant-on, infinite reconfigurability, on chip storage with FlashBAK embedded block memory and Serial TAG memory and design security. The parts also support Live Update technology with TransFR, 128-bit AES Encryption and Dual-boot technologies. The LatticeXP2 FPGA fabric was optimized for the new technology from the outset with high performance and low cost in mind. LatticeXP2 devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O support and enhanced sysDSP blocks. Lattice Diamond(R) design software allows large and complex designs to be efficiently implemented using the LatticeXP2 family of FPGA devices. Synthesis library support for LatticeXP2 is available for popular logic synthesis tools. The Diamond software uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LatticeXP2 device. The Diamond tool extracts the timing from the routing and back-annotates it into the design for timing verification. Lattice provides many pre-designed Intellectual Property (IP) LatticeCORETM modules for the LatticeXP2 family. By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity. 1-2 LatticeXP2 Family Data Sheet Architecture January 2012 Data Sheet DS1009 Architecture Overview Each LatticeXP2 device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEMTM Embedded Block RAM (EBR) and a row of sysDSPTM Digital Signal Processing blocks as shown in Figure 2-1. On the left and right sides of the Programmable Functional Unit (PFU) array, there are Non-volatile Memory Blocks. In configuration mode the nonvolatile memory is programmed via the IEEE 1149.1 TAP port or the sysCONFIGTM peripheral port. On power up, the configuration data is transferred from the Non-volatile Memory Blocks to the configuration SRAM. With this technology, expensive external configuration memory is not required, and designs are secured from unauthorized read-back. This transfer of data from non-volatile memory to configuration SRAM via wide busses happens in microseconds, providing an "instant-on" capability that allows easy interfacing in many applications. LatticeXP2 devices can also transfer data from the sysMEM EBR blocks to the Non-volatile Memory Blocks at user request. There are two kinds of logic blocks, the PFU and the PFU without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM and ROM functions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks are optimized for flexibility allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a two-dimensional array. Only one type of block is used per row. LatticeXP2 devices contain one or more rows of sysMEM EBR blocks. sysMEM EBRs are large dedicated 18Kbit memory blocks. Each sysMEM block can be configured in a variety of depths and widths of RAM or ROM. In addition, LatticeXP2 devices contain up to two rows of DSP Blocks. Each DSP block has multipliers and adder/accumulators, which are the building blocks for complex signal processing capabilities. Each PIC block encompasses two PIOs (PIO pairs) with their respective sysIO buffers. The sysIO buffers of the LatticeXP2 devices are arranged into eight banks, allowing the implementation of a wide variety of I/O standards. PIO pairs on the left and right edges of the device can be configured as LVDS transmit/receive pairs. The PIC logic also includes pre-engineered support to aid in the implementation of high speed source synchronous standards such as 7:1 LVDS interfaces, found in many display applications, and memory interfaces including DDR and DDR2. Other blocks provided include PLLs and configuration functions. The LatticeXP2 architecture provides up to four General Purpose PLLs (GPLL) per device. The GPLL blocks are located in the corners of the device. The configuration block that supports features such as configuration bit-stream de-encryption, transparent updates and dual boot support is located between banks two and three. Every device in the LatticeXP2 family supports a sysCONFIG port, muxed with bank seven I/Os, which supports serial device configuration. A JTAG port is provided between banks two and three. This family also provides an on-chip oscillator. LatticeXP2 devices use 1.2V as their core voltage. (c) 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 2-1 DS1009 Architecture_01.5 Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor Figure 2-1. Simplified Block Diagram, LatticeXP2-17 Device (Top Level) sysIO Buffers, Pre-Engineered Source Synchronous Support On-chip Oscillator Programmable Function Units (PFUs) SPI Port sysMEM Block RAM JTAG Port DSP Blocks Flash sysCLOCK PLLs Flexible Routing PFU Blocks The core of the LatticeXP2 device is made up of logic blocks in two forms, PFUs and PFFs. PFUs can be programmed to perform logic, arithmetic, distributed RAM and distributed ROM functions. PFF blocks can be programmed to perform logic, arithmetic and ROM functions. Except where necessary, the remainder of this data sheet will use the term PFU to refer to both PFU and PFF blocks. Each PFU block consists of four interconnected slices, numbered Slice 0 through Slice 3, as shown in Figure 2-2. All the interconnections to and from PFU blocks are from routing. There are 50 inputs and 23 outputs associated with each PFU block. 2-2 Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor Figure 2-2. PFU Diagram From Routing LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY Slice 0 LUT4 & CARRY Slice 1 D FF LUT4 & CARRY D D FF LUT4 D FF FF LUT4 Slice 3 Slice 2 D FF LUT4 & CARRY D FF To Routing Slice Slice 0 through Slice 2 contain two 4-input combinatorial Look-Up Tables (LUT4), which feed two registers. Slice 3 contains two LUT4s and no registers. For PFUs, Slice 0 and Slice 2 can also be configured as distributed memory, a capability not available in PFF blocks. Table 2-1 shows the capability of the slices in both PFF and PFU blocks along with the operation modes they enable. In addition, each PFU contains logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select and wider RAM/ROM functions. Figure 2-3 shows an overview of the internal logic of the slice. The registers in the slice can be configured as positive/negative edge triggered or level sensitive clocks. Table 2-1. Resources and Modes Available per Slice PFU BLock Slice Resources PFF Block Modes Resources Modes Slice 0 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM Slice 1 2 LUT4s and 2 Registers 2 LUT4s and 2 Registers Logic, Ripple, ROM Slice 2 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM Slice 3 2 LUT4s Logic, Ripple, ROM Logic, ROM 2 LUT4s Logic, ROM Slice 0 through Slice 2 have 14 input signals: 13 signals from routing and one from the carry-chain (from the adjacent slice or PFU). There are seven outputs: six to routing and one to carry-chain (to the adjacent PFU). Slice 3 has 13 input signals from routing and four signals to routing. Table 2-2 lists the signals associated with Slice 0 to Slice 2. 2-3 Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor Figure 2-3. Slice Diagram FCO from Slice/PFU, FCI into Different Slice/PFU SLICE FXB FXA OFX1 A1 B1 C1 D1 CO F1 F/SUM D LUT4 & CARRY* Q1 FF* To Routing CI M1 M0 LUT5 Mux From Routing OFX0 A0 B0 C0 D0 CO LUT4 & CARRY* F0 F/SUM Q0 D FF* CI CE CLK LSR * Not in Slice 3 FCI into Slice/PFU, FCO from Different Slice/PFU For Slices 0 and 2, memory control signals are generated from Slice 1 as follows: WCK is CLK WRE is from LSR DI[3:2] for Slice 2 and DI[1:0] for Slice 0 data WAD [A:D] is a 4bit address from slice 1 LUT input Table 2-2. Slice Signal Descriptions Function Type Signal Names Input Data signal A0, B0, C0, D0 Inputs to LUT4 Description Input Data signal A1, B1, C1, D1 Inputs to LUT4 Input Multi-purpose M0 Multipurpose Input Input Multi-purpose M1 Multipurpose Input Input Control signal CE Clock Enable Input Control signal LSR Local Set/Reset Input Control signal CLK System Clock Input Inter-PFU signal FCI Fast Carry-In1 Input Inter-slice signal FXA Intermediate signal to generate LUT6 and LUT7 Input Inter-slice signal FXB Intermediate signal to generate LUT6 and LUT7 Output Data signals F0, F1 LUT4 output register bypass signals Output Data signals Q0, Q1 Register outputs Output Data signals OFX0 Output of a LUT5 MUX Output Data signals OFX1 Output of a LUT6, LUT7, LUT82 MUX depending on the slice Output Inter-PFU signal FCO Slice 2 of each PFU is the fast carry chain output1 1. See Figure 2-3 for connection details. 2. Requires two PFUs. 2-4 Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor Modes of Operation Each slice has up to four potential modes of operation: Logic, Ripple, RAM and ROM. Logic Mode In this mode, the LUTs in each slice are configured as LUT4s. A LUT4 has 16 possible input combinations. Fourinput logic functions are generated by programming the LUT4. Since there are two LUT4s per slice, a LUT5 can be constructed within one slice. Larger LUTs such as LUT6, LUT7 and LUT8, can be constructed by concatenating two or more slices. Note that a LUT8 requires more than four slices. Ripple Mode Ripple mode allows efficient implementation of small arithmetic functions. In ripple mode, the following functions can be implemented by each slice: * Addition 2-bit * Subtraction 2-bit * Add/Subtract 2-bit using dynamic control * Up counter 2-bit * Down counter 2-bit * Up/Down counter with async clear * Up/Down counter with preload (sync) * Ripple mode multiplier building block * Multiplier support * Comparator functions of A and B inputs - A greater-than-or-equal-to B - A not-equal-to B - A less-than-or-equal-to B Two carry signals, FCI and FCO, are generated per slice in this mode, allowing fast arithmetic functions to be constructed by concatenating slices. RAM Mode In this mode, a 16x4-bit distributed Single Port RAM (SPR) can be constructed using each LUT block in Slice 0 and Slice 2 as a 16x1-bit memory. Slice 1 is used to provide memory address and control signals. A 16x2-bit Pseudo Dual Port RAM (PDPR) memory is created by using one slice as the read-write port and the other companion slice as the read-only port. The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the software will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3 shows the number of slices required to implement different distributed RAM primitives. For more information on using RAM in LatticeXP2 devices, please see TN1137, LatticeXP2 Memory Usage Guide. Table 2-3. Number of Slices Required For Implementing Distributed RAM Number of slices SPR 16X4 PDPR 16X4 3 3 Note: SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM ROM Mode ROM mode uses the LUT logic; hence, Slices 0 through 3 can be used in the ROM mode. Preloading is accomplished through the programming interface during PFU configuration. 2-5 Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor Routing There are many resources provided in the LatticeXP2 devices to route signals individually or as busses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) or x6 (spans seven PFU) connections. The x1 and x2 connections provide fast and efficient connections in horizontal and vertical directions. The x2 and x6 resources are buffered to allow both short and long connections routing between PFUs. The LatticeXP2 family has an enhanced routing architecture to produce a compact design. The Diamond design tool takes the output of the synthesis tool and places and routes the design. Generally, the place and route tool is completely automatic, although an interactive routing editor is available to optimize the design. sysCLOCK Phase Locked Loops (PLL) The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The LatticeXP2 family supports between two and four full featured General Purpose PLLs (GPLL). The architecture of the GPLL is shown in Figure 2-4. CLKI, the PLL reference frequency, is provided either from the pin or from routing; it feeds into the Input Clock Divider block. CLKFB, the feedback signal, is generated from CLKOP (the primary clock output) or from a user clock pin/logic. CLKFB feeds into the Feedback Divider and is used to multiply the reference frequency. Both the input path and feedback signals enter the Voltage Controlled Oscillator (VCO) block. The phase and frequency of the VCO are determined from the input path and feedback signals. A LOCK signal is generated by the VCO to indicate that the VCO is locked with the input clock signal. The output of the VCO feeds into the CLKOP Divider, a post-scalar divider. The duty cycle of the CLKOP Divider output can be fine tuned using the Duty Trim block, which creates the CLKOP signal. By allowing the VCO to operate at higher frequencies than CLKOP, the frequency range of the GPLL is expanded. The output of the CLKOP Divider is passed through the CLKOK Divider, a secondary clock divider, to generate lower frequencies for the CLKOK output. For applications that require even lower frequencies, the CLKOP signal is passed through a divideby-three divider to produce the CLKOK2 output. The CLKOK2 output is provided for applications that use source synchronous logic. The Phase/Duty Cycle/Duty Trim block is used to adjust the phase and duty cycle of the CLKOP Divider output to generate the CLKOS signal. The phase/duty cycle setting can be pre-programmed or dynamically adjusted. The clock outputs from the GPLL; CLKOP, CLKOK, CLKOK2 and CLKOS, are fed to the clock distribution network. For further information on the GPLL please see TN1126, LatticeXP2 sysCLOCK PLL Design and Usage Guide. 2-6 Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor Figure 2-4. General Purpose PLL (GPLL) Diagram WRDEL DDUTY DPHASE 3 Phase/ Duty Cycle/ Duty Trim CLKI Divider CLKI PFD CLKFB VCO/ LOOP FILTER CLKOP Divider CLKFB Divider CLKOK2 CLKOS CLKOP Duty Trim CLKOK CLKOK Divider Internal Feedback RSTK RST Lock Detect LOCK Table 2-4 provides a description of the signals in the GPLL blocks. Table 2-4. GPLL Block Signal Descriptions Signal I/O Description CLKI I Clock input from external pin or routing CLKFB I PLL feedback input from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock (PIN or logic) RST I "1" to reset PLL counters, VCO, charge pumps and M-dividers RSTK I "1" to reset K-divider DPHASE [3:0] I DPA Phase Adjust input DDDUTY [3:0] I DPA Duty Cycle Select input WRDEL I DPA Fine Delay Adjust input CLKOS O PLL output clock to clock tree (phase shifted/duty cycle changed) CLKOP O PLL output clock to clock tree (no phase shift) CLKOK O PLL output to clock tree through secondary clock divider CLKOK2 O PLL output to clock tree (CLKOP divided by 3) LOCK O "1" indicates PLL LOCK to CLKI Clock Dividers LatticeXP2 devices have two clock dividers, one on the left side and one on the right side of the device. These are intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in a /2, /4 or /8 mode and maintains a known phase relationship between the divided down clock and the high-speed clock based on the release of its reset signal. The clock dividers can be fed from the CLKOP output from the GPLLs or from the Edge Clocks (ECLK). The clock divider outputs serve as primary clock sources and feed into the clock distribution network. The Reset (RST) control signal resets the input and forces all outputs to low. The RELEASE signal releases outputs to the input clock. For further information on clock dividers, please see TN1126, LatticeXP2 sysCLOCK PLL Design and Usage Guide. Figure 2-5 shows the clock divider connections. 2-7 Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor Figure 2-5. Clock Divider Connections ECLK /1 CLKOP (GPLL) /2 CLKDIV /4 RST /8 RELEASE Clock Distribution Network LatticeXP2 devices have eight quadrant-based primary clocks and between six and eight flexible region-based secondary clocks/control signals. Two high performance edge clocks are available on each edge of the device to support high speed interfaces. The clock inputs are selected from external I/Os, the sysCLOCK PLLs, or routing. Clock inputs are fed throughout the chip via the primary, secondary and edge clock networks. Primary Clock Sources LatticeXP2 devices derive primary clocks from four sources: PLL outputs, CLKDIV outputs, dedicated clock inputs and routing. LatticeXP2 devices have two to four sysCLOCK PLLs, located in the four corners of the device. There are eight dedicated clock inputs, two on each side of the device. Figure 2-6 shows the primary clock sources. 2-8 Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor Figure 2-6. Primary Clock Sources for XP2-17 Clock Input Clock Input From Routing PLL Input GPLL GPLL CLK DIV CLK DIV Clock Input Clock Input Primary Clock Sources to Eight Quadrant Clock Selection Clock Input Clock Input PLL Input PLL Input GPLL GPLL From Routing Clock Input Clock Input Note: This diagram shows sources for the XP2-17 device. Smaller LatticeXP2 devices have two GPLLs. 2-9 PLL Input Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor Secondary Clock/Control Sources LatticeXP2 devices derive secondary clocks (SC0 through SC7) from eight dedicated clock input pads and the rest from routing. Figure 2-7 shows the secondary clock sources. Figure 2-7. Secondary Clock Sources Clock Input From Routing Clock Input From Routing From Routing From Routing From Routing From Routing From Routing From Routing Clock Input Clock Input Secondary Clock Sources Clock Input Clock Input From Routing From Routing From Routing From Routing From Routing From Routing From Routing Clock Input Clock Input 2-10 From Routing Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor Edge Clock Sources Edge clock resources can be driven from a variety of sources at the same edge. Edge clock resources can be driven from adjacent edge clock PIOs, primary clock PIOs, PLLs and clock dividers as shown in Figure 2-8. Figure 2-8. Edge Clock Sources Clock Input Clock Input From Routing From Routing Sources for top edge clocks PLL Input GPLL CLKOP CLKOP CLKOS CLKOS GPLL From Routing From Routing Clock Input Clock Input Eight Edge Clocks (ECLK) Two Clocks per Edge Clock Input Clock Input From Routing PLL Input PLL Input From Routing GPLL CLKOP CLKOP CLKOS CLKOS GPLL PLL Input Sources for right edge clocks Sources for left edge clocks Sources for bottom edge clocks From Routing From Routing Clock Input Clock Input Note: This diagram shows sources for the XP2-17 device. Smaller LatticeXP2 devices have two GPLLs. 2-11 Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor Primary Clock Routing The clock routing structure in LatticeXP2 devices consists of a network of eight primary clock lines (CLK0 through CLK7) per quadrant. The primary clocks of each quadrant are generated from muxes located in the center of the device. All the clock sources are connected to these muxes. Figure 2-9 shows the clock routing for one quadrant. Each quadrant mux is identical. If desired, any clock can be routed globally. Figure 2-9. Per Quadrant Primary Clock Selection Primary Clock Sources: PLLs + CLKDIVs + PIOs + Routing 30:1 30:1 30:1 30:1 30:1 30:1 29:1 29:1 DCS CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 29:1 29:1 DCS CLK7 8 Primary Clocks (CLK0 to CLK7) per Quadrant Dynamic Clock Select (DCS) The DCS is a smart multiplexer function available in the primary clock routing. It switches between two independent input clock sources without any glitches or runt pulses. This is achieved irrespective of when the select signal is toggled. There are two DCS blocks per quadrant; in total, eight DCS blocks per device. The inputs to the DCS block come from the center muxes. The output of the DCS is connected to primary clocks CLK6 and CLK7 (see Figure 29). Figure 2-10 shows the timing waveforms of the default DCS operating mode. The DCS block can be programmed to other modes. For more information on the DCS, please see TN1126, LatticeXP2 sysCLOCK PLL Design and Usage Guide. Figure 2-10. DCS Waveforms CLK0 CLK1 SEL DCSOUT Secondary Clock/Control Routing Secondary clocks in the LatticeXP2 devices are region-based resources. The benefit of region-based resources is the relatively low injection delay and skew within the region, as compared to primary clocks. EBR rows, DSP rows and a special vertical routing channel bound the secondary clock regions. This special vertical routing channel aligns with either the left edge of the center DSP block in the DSP row or the center of the DSP row. Figure 2-11 shows this special vertical routing channel and the eight secondary clock regions for the LatticeXP2-40. 2-12 Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor LatticeXP2-30 and smaller devices have six secondary clock regions. All devices in the LatticeXP2 family have four secondary clocks (SC0 to SC3) which are distributed to every region. The secondary clock muxes are located in the center of the device. Figure 2-12 shows the mux structure of the secondary clock routing. Secondary clocks SC0 to SC3 are used for clock and control and SC4 to SC7 are used for high fan-out signals. Figure 2-11. Secondary Clock Regions XP2-40 I/O Bank 0 I/O Bank 1 Secondary Clock Region 5 Secondary Clock Region 2 Secondary Clock Region 6 Secondary Clock Region 3 Secondary Clock Region 7 Secondary Clock Region 4 Secondary Clock Region 8 I/O Bank 5 I/O Bank 4 2-13 I/O Bank 3 I/O Bank 6 Secondary Clock Region 1 I/O Bank 2 I/O Bank 7 Vertical Routing Channel Regional Boundary EBR Row Regional Boundary EBR Row Regional Boundary DSP Row Regional Boundary Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor Figure 2-12. Secondary Clock Selection Secondary Clock Feedlines: 8 PIOs + 16 Routing 24:1 SC0 24:1 SC1 24:1 SC2 24:1 SC3 24:1 SC4 24:1 SC5 24:1 SC6 24:1 SC7 4 Secondary Clocks/CE/LSR (SC0 to SC3) per Region Clock/Control 4 High Fan-out Data Signals (SC4 to SC7) per Region High Fan-out Data Slice Clock Selection Figure 2-13 shows the clock selections and Figure 2-14 shows the control selections for Slice0 through Slice2. All the primary clocks and the four secondary clocks are routed to this clock selection mux. Other signals, via routing, can be used as clock inputs to the slices. Slice controls are generated from the secondary clocks or other signals connected via routing. If none of the signals are selected for both clock and control, then the default value of the mux output is 1. Slice 3 does not have any registers; therefore it does not have the clock or control muxes. Figure 2-13. Slice0 through Slice2 Clock Selection Primary Clock 8 Secondary Clock Clock to Slice 4 25:1 Routing 12 Vcc 1 2-14 Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor Figure 2-14. Slice0 through Slice2 Control Selection Secondary Clock 3 Slice Control Routing 16:1 12 Vcc 1 Edge Clock Routing LatticeXP2 devices have eight high-speed edge clocks that are intended for use with the PIOs in the implementation of high-speed interfaces. Each device has two edge clocks per edge. Figure 2-15 shows the selection muxes for these clocks. Figure 2-15. Edge Clock Mux Connections Top and Bottom Edge Clocks ECLK1/ ECLK2 Clock Input Pad (Both Muxes) Routing Left and Right Edge Clocks ECLK1 Input Pad GPLL Input Pad GPLL Output CLKOP Routing Left and Right Edge Clocks ECLK2 Input Pad GPLL Input Pad GPLL Output CLKOS Routing 2-15 Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor sysMEM Memory LatticeXP2 devices contains a number of sysMEM Embedded Block RAM (EBR). The EBR consists of 18 Kbit RAM with dedicated input and output registers. sysMEM Memory Block The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in a variety of depths and widths as shown in Table 2-5. FIFOs can be implemented in sysMEM EBR blocks by using support logic with PFUs. The EBR block supports an optional parity bit for each data byte to facilitate parity checking. EBR blocks provide byte-enable support for configurations with18-bit and 36-bit data widths. Table 2-5. sysMEM Block Configurations Memory Mode Configurations Single Port 16,384 x 1 8,192 x 2 4,096 x 4 2,048 x 9 1,024 x 18 512 x 36 True Dual Port 16,384 x 1 8,192 x 2 4,096 x 4 2,048 x 9 1,024 x 18 Pseudo Dual Port 16,384 x 1 8,192 x 2 4,096 x 4 2,048 x 9 1,024 x 18 512 x 36 Bus Size Matching All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for each port varies, this mapping scheme applies to each port. FlashBAK EBR Content Storage All the EBR memory in the LatticeXP2 is shadowed by Flash memory. Optionally, initialization values for the memory blocks can be defined using the Lattice Diamond design tools. The initialization values are loaded into the Flash memory during device programming and into the SRAM at power up or whenever the device is reconfigured. This feature is ideal for the storage of a variety of information such as look-up tables and microprocessor code. It is also possible to write the current contents of the EBR memory back to Flash memory. This capability is useful for the storage of data such as error codes and calibration information. For additional information on the FlashBAK capability see TN1137, LatticeXP2 Memory Usage Guide. 2-16 Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor Figure 2-16. FlashBAK Technology Write to Flash During Programming Make Infinite Reads and Writes to EBR Flash JTAG / SPI Port EBR FPGA Logic Write From Flash to EBR During Configuration / Write From EBR to Flash on User Command Memory Cascading Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs. Single, Dual and Pseudo-Dual Port Modes In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory array. The output data of the memory is optionally registered at the output. EBR memory supports two forms of write behavior for single port or dual port operation: 1. Normal - Data on the output appears only during a read cycle. During a write cycle, the data (at the current address) does not appear on the output. This mode is supported for all data widths. 2. Write Through - A copy of the input data appears at the output of the same port during a write cycle. This mode is supported for all data widths. Memory Core Reset The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchronously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A and Port B respectively. GSRN, the global reset signal, resets both ports. The output data latches and associated resets for both ports are as shown in Figure 2-17. Figure 2-17. Memory Core Reset Memory Core D SET Q Port A[17:0] LCLR Output Data Latches D SET Q LCLR RSTA RSTB GSRN Programmable Disable 2-17 Port B[17:0] Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor For further information on the sysMEM EBR block, please see TN1137, LatticeXP2 Memory Usage Guide. EBR Asynchronous Reset EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the reset is applied and released a clock cycle after the low-to-high transition of the reset signal, as shown in Figure 2-18. The GSR input to the EBR is always asynchronous. Figure 2-18. EBR Asynchronous Reset (Including GSR) Timing Diagram Reset Clock Clock Enable If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after the EBR read and write clock inputs are in a steady state condition for a minimum of 1/fMAX (EBR clock). The reset release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge. If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during device Wake Up must occur before the release of the device I/Os becoming active. These instructions apply to all EBR RAM and ROM implementations. Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled. sysDSPTM Block The LatticeXP2 family provides a sysDSP block making it ideally suited for low cost, high performance Digital Signal Processing (DSP) applications. Typical functions used in these applications include Bit Correlators, Fast Fourier Transform (FFT) functions, Finite Impulse Response (FIR) Filter, Reed-Solomon Encoder/Decoder, Turbo Encoder/ Decoder and Convolutional Encoder/Decoder. These complex signal processing functions use similar building blocks such as multiply-adders and multiply-accumulators. sysDSP Block Approach Compare to General DSP Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with fixed data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by higher clock speeds. The LatticeXP2 family, on the other hand, has many DSP blocks that support different datawidths. This allows the designer to use highly parallel implementations of DSP functions. The designer can optimize the DSP performance vs. area by choosing appropriate levels of parallelism. Figure 2-19 compares the fully serial and the mixed parallel and serial implementations. 2-18 Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor Figure 2-19. Comparison of General DSP and LatticeXP2 Approaches Operand A Operand A Operand A Operand B Operand A Single Multiplier Operand B Operand B Operand B x x M loops Multiplier 0 Multiplier 1 x Accumulator (k adds) Function implemented in General purpose DSP x m/k loops Multiplier k + m/k accumulate Output Function implemented in LatticeXP2 sysDSP Block Capabilities The sysDSP block in the LatticeXP2 family supports four functional elements in three 9, 18 and 36 data path widths. The user selects a function element for a DSP block and then selects the width and type (signed/unsigned) of its operands. The operands in the LatticeXP2 family sysDSP Blocks can be either signed or unsigned but not mixed within a function element. Similarly, the operand widths cannot be mixed within a block. DSP elements can be concatenated. The resources in each sysDSP block can be configured to support the following four elements: * MULT (Multiply) * MAC (Multiply, Accumulate) * MULTADDSUB (Multiply, Addition/Subtraction) * MULTADDSUBSUM (Multiply, Addition/Subtraction, Accumulate) The number of elements available in each block depends on the width selected from the three available options: x9, x18, and x36. A number of these elements are concatenated for highly parallel implementations of DSP functions. Table 2-6 shows the capabilities of the block. Table 2-6. Maximum Number of Elements in a Block Width of Multiply x9 x18 x36 MULT 8 4 1 MAC 2 2 -- MULTADDSUB 4 2 -- MULTADDSUBSUM 2 1 -- Some options are available in four elements. The input register in all the elements can be directly loaded or can be loaded as shift register from previous operand registers. By selecting `dynamic operation' the following operations are possible: 2-19 Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor * In the `Signed/Unsigned' options the operands can be switched between signed and unsigned on every cycle. * In the `Add/Sub' option the Accumulator can be switched between addition and subtraction on every cycle. * The loading of operands can switch between parallel and serial operations. MULT sysDSP Element This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, A and B, are multiplied and the result is available at the output. The user can enable the input/output and pipeline registers. Figure 2-20 shows the MULT sysDSP element. Figure 2-20. MULT sysDSP Element Shift Register B In Shift Register A In Multiplier m m n n m Input Data Register A n m Multiplier n Input Data Register B x m+n (default) Output Register Multiplicand Pipeline Register m n Signed A Input Register To Multiplier Signed B Input Register To Multiplier CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) Shift Register B Out Shift Register A Out 2-20 m+n Output Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor MAC sysDSP Element In this case, the two operands, A and B, are multiplied and the result is added with the previous accumulated value. This accumulated value is available at the output. The user can enable the input and pipeline registers but the output register is always enabled. The output register is used to store the accumulated value. The Accumulators in the DSP blocks in LatticeXP2 family can be initialized dynamically. A registered overflow signal is also available. The overflow conditions are provided later in this document. Figure 2-21 shows the MAC sysDSP element. Figure 2-21. MAC sysDSP Serial Register B in Serial Register A in Multiplicand m Preload m Accumulator Input Data Register A n Input Data Register B m Multiplier n x m+n (default) Pipeline Register n n Signed A Input Register Pipeline Register To Accumulator Signed B Input Register Pipeline Register To Accumulator Addn Input Register Pipeline Register To Accumulator Accumsload Input Register Pipeline Register To Accumulator m+n+16 (default) Output Register m n n m+n+16 (default) Output Register Multiplier CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) SROB SROA 2-21 Output Overflow signal Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor MULTADDSUB sysDSP Element In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multiplier operation of operands A1 and B1. The user can enable the input, output and pipeline registers. Figure 2-22 shows the MULTADDSUB sysDSP element. Figure 2-22. MULTADDSUB Shift Register B In Shift Register A In Multiplicand A0 m CLK (CLK0,CLK1,CLK2,CLK3) m CE (CE0,CE1,CE2,CE3) Multiplier B0 m n n RST (RST0,RST1,RST2,RST3) Input Data Register A n Multiplier m x n Input Data Register B Pipeline Register m m+n (default) Add/Sub Multiplicand A1 Multiplier B1 m m+n+1 (default) m n Input Data Register A n Signed B Addn Shift Register B Out n x n Input Data Register B Signed A Multiplier m Pipeline Register m Input Register Pipeline Pipe Register Reg To Add/Sub Input Register Pipeline Pipe Register Reg To Add/Sub Input Register Pipeline Pipe Register Reg To Add/Sub Shift Register A Out 2-22 m+n (default) Output Register n Output m+n+1 (default) Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor MULTADDSUBSUM sysDSP Element In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multiplier operation of operands A1 and B1. Additionally the operands A2 and B2 are multiplied and the result is added/ subtracted with the result of the multiplier operation of operands A3 and B3. The result of both addition/subtraction are added in a summation block. The user can enable the input, output and pipeline registers. Figure 2-23 shows the MULTADDSUBSUM sysDSP element. Figure 2-23. MULTADDSUBSUM Shift Register B In Shift Register A In Multiplicand A0 m m CLK (CLK0,CLK1,CLK2,CLK3) m n n CE (CE0,CE1,CE2,CE3) Input Data Register A n n Input Data Register B Multiplier x m+n (default) Pipeline Register m RST(RST0,RST1,RST2,RST3) Add/Sub0 n Multiplicand A1 Multiplier B1 m m m+n (default) m n Input Data Register A n n Input Data Register B Multiplicand A2 n Multiplier m+n+1 x SUM Pipeline Register m m m+n+2 Multiplier B2 m n n Input Data Register A n n Input Data Register B Multiplier x m+n+2 m+n (default) m+n+1 Pipeline Register m Output Add/Sub1 n Multiplicand A3 Multiplier B3 m Output Register Multiplier B0 m n Input Data Register A n Input Data Register B Signed A Signed B Addn0 Addn1 Shift Register B Out m+n (default) m n m n Multiplier x Pipeline Register m Input Register Pipeline Register To Add/Sub0, Add/Sub1 Input Register Pipeline Register To Add/Sub0, Add/Sub1 Input Register Pipeline Register To Add/Sub0 Input Register Pipeline Register To Add/Sub1 Shift Register A Out Clock, Clock Enable and Reset Resources Global Clock, Clock Enable (CE) and Reset (RST) signals from routing are available to every DSP block. From four clock sources (CLK0, CLK1, CLK2, CLK3) one clock is selected for each input register, pipeline register and output 2-23 Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor register. Similarly, CE and RST are selected from their four respective sources (CE0, CE1, CE2, CE3 and RST0, RST1, RST2, RST3) at each input register, pipeline register and output register. Signed and Unsigned with Different Widths The DSP block supports other widths, in addition to x9, x18 and x36 widths, of signed and unsigned multipliers. For unsigned operands, unused upper data bits should be filled to create a valid x9, x18 or x36 operand. For signed two's complement operands, sign extension of the most significant bit should be performed until x9, x18 or x36 width is reached. Table 2-7 provides an example of this. Table 2-7. Sign Extension Example Number Unsigned Unsigned 9-bit Unsigned 18-bit Signed Two's Complement Signed 9 Bits Two's Complement Signed 18 Bits +5 0101 000000101 000000000000000101 0101 000000101 000000000000000101 -6 N/A N/A N/A 1010 111111010 111111111111111010 OVERFLOW Flag from MAC The sysDSP block provides an overflow output to indicate that the accumulator has overflowed. "Roll-over" occurs and an overflow signal is indicated when any of the following is true: two unsigned numbers are added and the result is a smaller number than the accumulator, two positive numbers are added with a negative sum or two negative numbers are added with a positive sum. Note that when overflow occurs the overflow flag is present for only one cycle. By counting these overflow pulses in FPGA logic, larger accumulators can be constructed. The conditions for the overflow signal for signed and unsigned operands are listed in Figure 2-24. Figure 2-24. Accumulator Overflow/Underflow 011111100 011111101 011111110 011111111 100000000 100000001 100000010 252 253 254 255 256 257 258 000000011 000000010 000000001 000000000 3 2 1 0 111111111 111111110 111111101 511 510 509 Unsigned Operation Overflow signal is generated for one cycle when this boundary is crossed 011111100 011111101 011111110 011111111 100000000 100000001 100000010 000000011 000000010 000000001 000000000 111111111 111111110 111111101 252 253 254 255 -256 -255 -254 Signed Operation 2-24 +3 +2 +1 0 -1 -2 -3 Carry signal is generated for one cycle when this boundary is crossed Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor IPexpressTM The user can access the sysDSP block via the Lattice IPexpress tool, which provides the option to configure each DSP module (or group of modules), or by direct HDL instantiation. In addition, Lattice has partnered with The MathWorks(R) to support instantiation in the Simulink(R) tool, a graphical simulation environment. Simulink works with Diamond to dramatically shorten the DSP design cycle in Lattice FPGAs. Optimized DSP Functions Lattice provides a library of optimized DSP IP functions. Some of the IP cores planned for the LatticeXP2 DSP include the Bit Correlator, FFT functions, FIR Filter, Reed-Solomon Encoder/Decoder, Turbo Encoder/Decoder and Convolutional Encoder/Decoder. Please contact Lattice to obtain the latest list of available DSP IP cores. Resources Available in the LatticeXP2 Family Table 2-8 shows the maximum number of multipliers for each member of the LatticeXP2 family. Table 2-9 shows the maximum available EBR RAM Blocks and Serial TAG Memory bits in each LatticeXP2 device. EBR blocks, together with Distributed RAM can be used to store variables locally for fast DSP operations. Table 2-8. Maximum Number of DSP Blocks in the LatticeXP2 Family Device DSP Block 9x9 Multiplier 18x18 Multiplier 36x36 Multiplier XP2-5 3 24 12 3 XP2-8 4 32 16 4 XP2-17 5 40 20 5 XP2-30 7 56 28 7 XP2-40 8 64 32 8 Table 2-9. Embedded SRAM/TAG Memory in the LatticeXP2 Family Device EBR SRAM Block Total EBR SRAM (Kbits) TAG Memory (Bits) XP2-5 9 166 632 XP2-8 12 221 768 XP2-17 15 276 2184 XP2-30 21 387 2640 XP2-40 48 885 3384 LatticeXP2 DSP Performance Table 2-10 lists the maximum performance in Millions of MAC (MMAC) operations per second for each member of the LatticeXP2 family. Table 2-10. DSP Performance Device DSP Block DSP Performance MMAC XP2-5 3 3,900 XP2-8 4 5,200 XP2-17 5 6,500 XP2-30 7 9,100 XP2-40 8 10,400 For further information on the sysDSP block, please see TN1140, LatticeXP2 sysDSP Usage Guide. 2-25 Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor Programmable I/O Cells (PIC) Each PIC contains two PIOs connected to their respective sysIO buffers as shown in Figure 2-25. The PIO Block supplies the output data (DO) and the tri-state control signal (TO) to the sysIO buffer and receives input from the buffer. Table 2-11 provides the PIO signal list. Figure 2-25. PIC Diagram PIOA TD OPOS1 ONEG1 IOLT0 Tristate Register Block OPOS0 OPOS21 ONEG0 ONEG21 PADA "T" IOLD0 Output Register Block sysIO Buffer QNEG01 QNEG11 QPOS01 QPOS11 INCK2 INDD INFF IPOS0 IPOS1 CLK CE LSR GSRN ECLK1 ECLK2 DDRCLKPOL1 DQSXFER1 DQS DEL Control Muxes CLK1 CEO LSR GSR CLK0 CEI Input Register Block DI PADB "C" PIOB 1. Signals are available on left/right/bottom edges only. 2. Selected blocks. Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as "T" and "C") as shown in Figure 2-25. The PAD Labels "T" and "C" distinguish the two PIOs. Approximately 50% of the PIO pairs on the left and right edges of the device can be configured as true LVDS outputs. All I/O pairs can operate as inputs. 2-26 Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor Table 2-11. PIO Signal List Name Type Description CE Control from the core Clock enables for input and output block flip-flops CLK Control from the core System clocks for input and output blocks ECLK1, ECLK2 Control from the core Fast edge clocks LSR Control from the core Local Set/Reset GSRN Control from routing Global Set/Reset (active low) INCK2 Input to the core Input to Primary Clock Network or PLL reference inputs DQS Input to PIO DQS signal from logic (routing) to PIO INDD Input to the core Unregistered data input to core INFF Input to the core Registered input on positive edge of the clock (CLK0) IPOS0, IPOS1 Input to the core Double data rate registered inputs to the core 1 Input to the core Gearbox pipelined inputs to the core QNEG01, QNEG11 Input to the core Gearbox pipelined inputs to the core OPOS0, ONEG0, OPOS2, ONEG2 Output data from the core Output signals from the core for SDR and DDR operation OPOS1 ONEG1 Tristate control from the core Signals to Tristate Register block for DDR operation DEL[3:0] Control from the core Dynamic input delay control bits TD Tristate control from the core Tristate signal from the core used in SDR operation DDRCLKPOL Control from clock polarity bus Controls the polarity of the clock (CLK0) that feed the DDR input block DQSXFER Control from core 1 QPOS0 , QPOS1 Controls signal to the Output block 1. Signals available on left/right/bottom only. 2. Selected I/O. PIO The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic block. These blocks contain registers for operating in a variety of modes along with necessary clock and selection logic. Input Register Block The input register blocks for PIOs contain delay elements and registers that can be used to condition high-speed interface signals, such as DDR memory interfaces and source synchronous interfaces, before they are passed to the device core. Figure 2-26 shows the diagram of the input register block. Input signals are fed from the sysIO buffer to the input register block (as signal DI). If desired, the input signal can bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and, in selected blocks, the input to the DQS delay block. If an input delay is desired, designers can select either a fixed delay or a dynamic delay DEL[3:0]. The delay, if selected, reduces input register hold time requirements when using a global clock. The input block allows three modes of operation. In the Single Data Rate (SDR) mode, the data is registered, by one of the registers in the SDR Sync register block, with the system clock. In DDR mode two registers are used to sample the data on the positive and negative edges of the DQS signal which creates two data streams, D0 and D2. D0 and D2 are synchronized with the system clock before entering the core. Further information on this topic can be found in the DDR Memory Support section of this data sheet. By combining input blocks of the complementary PIOs and sharing registers from output blocks, a gearbox function can be implemented, that takes a double data rate signal applied to PIOA and converts it as four data streams, IPOS0A, IPOS1A, IPOS0B and IPOS1B. Figure 2-26 shows the diagram using this gearbox function. For more information on this topic, please see TN1138, LatticeXP2 High Speed I/O Interface. 2-27 Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures adequate timing when data is transferred from the DQS to system clock domain. For further discussion on this topic, see the DDR Memory section of this data sheet. Figure 2-26. Input Register Block INCK2 To DQS Delay Block2 DI (From sysIO Buffer) INDD SDR & Sync Registers DDR Registers Fixed Delay 0 Dynamic Delay 1 0 D DEL [3:0] D0 D IPOS0A Q D-Type /LATCH 1 Q Clock Transfer Registers D Q QPOS0A D-Type1 D-Type From Routing IPOS1A D Delayed DQS 0 Q D1 D D-Type D2 Q D Q D-Type /LATCH D-Type D Q QPOS1A D-Type1 To Routing 1 CLK0 (of PIO A) DDRCLKPOL CLKA True PIO (A) in LVDS I/O Pair Comp PIO (B) in LVDS I/O Pair DI (From sysIO Buffer) INCK2 To DQS Delay Block2 INDD DDRSRC Fixed Delay Dynamic Delay 0 0 D0 1 D DEL [3:0] SDR & Sync Registers DDR Registers 0 1 Q 1 D-Type From Routing D Q D-Type /LATCH Clock Transfer Registers D Q IPOS0B QPOS0B D-Type1 IPOS1B D Delayed DQS 0 Q D-Type D1 0 D Q D2 D-Type 1 D Q D-Type /LATCH D Q QPOS1B D-Type1 1 To Routing CLK0 (of PIO B) Gearbox Configuration Bit DDRCLKPOL CLKB Note: Simplified version does not show CE and SET/RESET details 1. Shared with output register 2. Selected PIO. Output Register Block The output register block provides the ability to register signals from the core of the device before they are passed to the sysIO buffers. The blocks on the PIOs on the left, right and bottom contain registers for SDR operation that are combined with an additional latch for DDR operation. Figure 2-27 shows the diagram of the Output Register Block for PIOs. In SDR mode, ONEG0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as a Dtype or latch. In DDR mode, ONEG0 and OPOS0 are fed into registers on the positive edge of the clock. At the next clock cycle the registered OPOS0 is latched. A multiplexer running off the same clock cycle selects the correct register to feed the output (D0). By combining output blocks of the complementary PIOs and sharing some registers from input blocks, a gearbox function can be implemented, to take four data streams ONEG0A, ONEG1A, ONEG1B and ONEG1B. Figure 2-27 2-28 Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor shows the diagram using this gearbox function. For more information on this topic, see TN1138, LatticeXP2 High Speed I/O Interface. Figure 2-27. Output and Tristate Block TD Tristate Logic D Q D-Type /LATCH ONEG1 0 1 0 0 D OPOS1 Q D 1 Q Latch From Routing To sysIO Buffer D-Type TO 1 0 ONEG0 D Q 0 D-Type* 1 1 D Q D-Type /LATCH DDR Output Registers DO 0 OPOS0 0 Q D D-Type* CLKA 0 Q D Latch D 0 1 1 Q D D-Type 1 1 Q Latch Clock Transfer Registers ECLK1 ECLK2 CLK1 (CLKA) DQSXFER Programmable Control 0 1 0 1 Output Logic True PIO (A) in LVDS I/O Pair Comp PIO (B) in LVDS I/O Pair TD Tristate Logic Q D D-Type /LATCH ONEG1 0 1 0 0 D OPOS1 Q D-Type 1 Q D TO 1 Latch From Routing To sysIO Buffer ONEG0 D Q D D-Type /LATCH Q D-Type* DDR Output Registers DO 0 OPOS0 0 D Q D-Type* CLKB ECLK1 ECLK2 CLK1 (CLKB) DQSXFER D D Q Latch Q D-Type D Q 1 1 Latch Clock Transfer Registers 0 1 0 1 * Shared with input register Programmable Control Output Logic Note: Simplified version does not show CE and SET/RESET details 2-29 Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor Tristate Register Block The tristate register block provides the ability to register tri-state control signals from the core of the device before they are passed to the sysIO buffers. The block contains a register for SDR operation and an additional latch for DDR operation. Figure 2-27 shows the Tristate Register Block with the Output Block In SDR mode, ONEG1 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as Dtype or latch. In DDR mode, ONEG1 and OPOS1 are fed into registers on the positive edge of the clock. Then in the next clock the registered OPOS1 is latched. A multiplexer running off the same clock cycle selects the correct register for feeding to the output (D0). Control Logic Block The control logic block allows the selection and modification of control signals for use in the PIO block. A clock signal is selected from general purpose routing, ECLK1, ECLK2 or a DQS signal (from the programmable DQS pin) and is provided to the input register block. The clock can optionally be inverted. DDR Memory Support PICs have additional circuitry to allow implementation of high speed source synchronous and DDR memory interfaces. PICs have registered elements that support DDR memory interfaces. Interfaces on the left and right edges are designed for DDR memories that support 16 bits of data, whereas interfaces on the top and bottom are designed for memories that support 18 bits of data. One of every 16 PIOs on the left and right and one of every 18 PIOs on the top and bottom contain delay elements to facilitate the generation of DQS signals. The DQS signals feed the DQS buses which span the set of 16 or 18 PIOs. Figure 2-28 and Figure 2-29 show the DQS pin assignments in each set of PIOs. The exact DQS pins are shown in a dual function in the Logic Signal Connections table in this data sheet. Additional detail is provided in the Signal Descriptions table. The DQS signal from the bus is used to strobe the DDR data from the memory into input register blocks. For additional information on using DDR memory support please see TN1138, LatticeXP2 High Speed I/O Interface. 2-30 Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor Figure 2-28. DQS Input Routing (Left and Right) PIO A PADA "T" PIO B PADB "C" PIO A PADA "T" PIO B PADB "C" LVDS Pair LVDS Pair PIO A PADA "T" PIO B PADB "C" PIO A PADA "T" PIO B PADB "C" LVDS Pair LVDS Pair PIO A DQS sysIO Buffer Delay Assigned DQS Pin PADA "T" LVDS Pair PADB "C" PIO B PIO A PADA "T" PIO B PADB "C" PIO A PADA "T" PIO B PADB "C" PIO A PADA "T" PIO B PADB "C" LVDS Pair LVDS Pair LVDS Pair Figure 2-29. DQS Input Routing (Top and Bottom) PIO A PADA "T" PIO B PADB "C" PIO A PADA "T" PIO B PADB "C" LVDS Pair LVDS Pair PIO A PADA "T" PIO B PADB "C" PIO A PADA "T" PIO B PADB "C" LVDS Pair LVDS Pair PIO A DQS sysIO Buffer Delay PIO B Assigned DQS Pin PADA "T" LVDS Pair PADB "C" PIO A PADA "T" PIO B PADB "C" PIO A PADA "T" PIO B PADB "C" PIO A PADA "T" PIO B PADB "C" LVDS Pair LVDS Pair LVDS Pair PIO A PIO B 2-31 PADA "T" LVDS Pair PADB "C" Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor DLL Calibrated DQS Delay Block Source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at the input register. For most interfaces a PLL is used for this adjustment. However, in DDR memories the clock, referred to as DQS, is not free-running, and this approach cannot be used. The DQS Delay block provides the required clock alignment for DDR memory interfaces. The DQS signal (selected PIOs only, as shown in Figure 2-30) feeds from the PAD through a DQS delay element to a dedicated DQS routing resource. The DQS signal also feeds polarity control logic which controls the polarity of the clock to the sync registers in the input register blocks. Figure 2-30 and Figure 2-31 show how the DQS transition signals are routed to the PIOs. The temperature, voltage and process variations of the DQS delay block are compensated by a set of 6-bit bus calibration signals from two dedicated DLLs (DDR_DLL) on opposite sides of the device. Each DLL compensates DQS delays in its half of the device as shown in Figure 2-30. The DLL loop is compensated for temperature, voltage and process variations by the system clock and feedback loop. Figure 2-30. Edge Clock, DLL Calibration and DQS Local Bus Distribution I/O Bank 0 Spans 16 PIOs Left & Right Sides I/O Bank 1 ECLK1 ECLK2 I/O Bank 7 I/O Bank 2 DQS Input Delayed DQS DDR_DLL (Right) DDR_DLL (Left) Polarity Control I/O Bank 6 I/O Bank 3 Spans 18 PIOs Top & Bottom Sides I/O Bank 5 I/O Bank 4 2-32 DQSXFER DQS Delay Control Bus Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor DQS Polarity control DCNTL[6:0] DQSXFER CLK1 ECLK2 ECLK1 Figure 2-31. DQS Local Bus PIO Output Register Block DQSXFER Input Register Block GSR CEI DQS DDR Datain PAD sysIO Buffer DI To Sync Reg. CLK1 DQS To DDR Reg. DQS Strobe PAD sysIO Buffer PIO Polarity Control Logic DI DQS DQSDEL Calibration bus from DLL DCNTL[6:0] ECLK1 DQSXFER DQSXFERDEL* DCNTL[6:0] *DQSXFERDEL shifts ECLK1 by 90% and is not associated with a particular PIO. Polarity Control Logic In a typical DDR memory interface design, the phase relationship between the incoming delayed DQS strobe and the internal system clock (during the READ cycle) is unknown. The LatticeXP2 family contains dedicated circuits to transfer data between these domains. To prevent set-up and hold violations, at the domain transfer between DQS (delayed) and the system clock, a clock polarity selector is used. This changes the edge on which the data is registered in the synchronizing registers in the input register block and requires evaluation at the start of each READ cycle for the correct clock polarity. Prior to the READ operation in DDR memories, DQS is in tristate (pulled by termination). The DDR memory device drives DQS low at the start of the preamble state. A dedicated circuit detects this transition. This signal is used to control the polarity of the clock to the synchronizing registers. 2-33 Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor DQSXFER LatticeXP2 devices provide a DQSXFER signal to the output buffer to assist it in data transfer to DDR memories that require DQS strobe be shifted 90o. This shifted DQS strobe is generated by the DQSDEL block. The DQSXFER signal runs the span of the data bus. sysIO Buffer Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the periphery of the device in groups referred to as banks. The sysIO buffers allow users to implement the wide variety of standards that are found in today's systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL. sysIO Buffer Banks LatticeXP2 devices have eight sysIO buffer banks for user I/Os arranged two per side. Each bank is capable of supporting multiple I/O standards. Each sysIO bank has its own I/O supply voltage (VCCIO). In addition, each bank has voltage references, VREF1 and VREF2, that allow it to be completely independent from the others. Figure 2-32 shows the eight banks and their associated supplies. In LatticeXP2 devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS and PCI) are powered using VCCIO. LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as fixed threshold inputs independent of VCCIO. Each bank can support up to two separate VREF voltages, VREF1 and VREF2, that set the threshold for the referenced input buffers. Some dedicated I/O pins in a bank can be configured to be a reference voltage supply pin. Each I/O is individually configurable based on the bank's supply and reference voltages. Figure 2-32. LatticeXP2 Banks TOP GND V REF2(1) Bank 1 V CCIO2 CCIO7 V REF2(7) Bank 2 V REF1(7) Bank 7 V V REF1(1) V CCIO1 GND V REF2(0) V REF1(0) V CCIO0 Bank 0 V REF1(2) V REF2(2) GND GND LEFT RIGHT V CCIO3 V REF1(6) V REF1(3) Bank 3 V REF2(6) Bank 6 V CCIO6 V REF2(3) GND GND BOTTOM 2-34 GND V REF2(4) V CCIO4 V REF1(4) Bank 4 GND V REF2(5) V CCIO5 VREF1(5) Bank 5 Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor LatticeXP2 devices contain two types of sysIO buffer pairs. 1. Top and Bottom (Banks 0, 1, 4 and 5) sysIO Buffer Pairs (Single-Ended Outputs Only) The sysIO buffer pairs in the top banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). One of the referenced input buffers can also be configured as a differential input. The two pads in the pair are described as "true" and "comp", where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer. Only the I/Os on the top and bottom banks have programmable PCI clamps. 2. Left and Right (Banks 2, 3, 6 and 7) sysIO Buffer Pairs (50% Differential and 100% Single-Ended Outputs) The sysIO buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. One of the referenced input buffers can also be configured as a differential input. The two pads in the pair are described as "true" and "comp", where the true pad is associated with the positive side of the differential I/O, and the comp pad is associated with the negative side of the differential I/O. LVDS differential output drivers are available on 50% of the buffer pairs on the left and right banks. Typical sysIO I/O Behavior During Power-up The internal power-on-reset (POR) signal is deactivated when VCC and VCCAUX have reached satisfactory levels. After the POR signal is deactivated, the FPGA core logic becomes active. It is the user's responsibility to ensure that all other VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that are critical to the application. For more information on controlling the output logic state with valid input logic levels during power-up in LatticeXP2 devices, please see TN1136, LatticeXP2 sysIO Usage Guide. The VCC and VCCAUX supply the power to the FPGA core fabric, whereas the VCCIO supplies power to the I/O buffers. In order to simplify system design while providing consistent and predictable I/O behavior, it is recommended that the I/O buffers be powered-up prior to the FPGA core fabric. VCCIO supplies should be powered-up before or together with the VCC and VCCAUX supplies. Supported sysIO Standards The LatticeXP2 sysIO buffer supports both single-ended and differential standards. Single-ended standards can be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 1.2V, 1.5V, 1.8V, 2.5V and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individual configuration options for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain. Other single-ended standards supported include SSTL and HSTL. Differential standards supported include LVDS, MLVDS, BLVDS, LVPECL, RSDS, differential SSTL and differential HSTL. Tables 2-12 and 2-13 show the I/O standards (together with their supply and reference voltages) supported by LatticeXP2 devices. For further information on utilizing the sysIO buffer to support a variety of standards please see TN1136, LatticeXP2 sysIO Usage Guide. 2-35 Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor Table 2-12. Supported Input Standards VREF (Nom.) VCCIO1 (Nom.) LVTTL -- -- LVCMOS33 -- -- LVCMOS25 -- -- LVCMOS18 -- 1.8 LVCMOS15 -- 1.5 Input Standard Single Ended Interfaces LVCMOS12 -- -- PCI33 -- -- HSTL18 Class I, II 0.9 -- HSTL15 Class I 0.75 -- SSTL33 Class I, II 1.5 -- SSTL25 Class I, II 1.25 -- SSTL18 Class I, II 0.9 -- Differential SSTL18 Class I, II -- -- Differential SSTL25 Class I, II -- -- Differential Interfaces Differential SSTL33 Class I, II -- -- Differential HSTL15 Class I -- -- Differential HSTL18 Class I, II -- -- LVDS, MLVDS, LVPECL, BLVDS, RSDS -- -- 1. When not specified, VCCIO can be set anywhere in the valid operating range (page 3-1). 2-36 Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor Table 2-13. Supported Output Standards Output Standard Drive VCCIO (Nom.) 4mA, 8mA, 12mA, 16mA, 20mA 3.3 LVCMOS33 4mA, 8mA, 12mA 16mA, 20mA 3.3 LVCMOS25 4mA, 8mA, 12mA, 16mA, 20mA 2.5 LVCMOS18 4mA, 8mA, 12mA, 16mA 1.8 LVCMOS15 4mA, 8mA 1.5 Single-ended Interfaces LVTTL LVCMOS12 2mA, 6mA 1.2 LVCMOS33, Open Drain 4mA, 8mA, 12mA 16mA, 20mA -- LVCMOS25, Open Drain 4mA, 8mA, 12mA 16mA, 20mA -- LVCMOS18, Open Drain 4mA, 8mA, 12mA 16mA -- LVCMOS15, Open Drain 4mA, 8mA -- LVCMOS12, Open Drain 2mA, 6mA -- PCI33 N/A 3.3 HSTL18 Class I, II N/A 1.8 HSTL15 Class I N/A 1.5 SSTL33 Class I, II N/A 3.3 SSTL25 Class I, II N/A 2.5 SSTL18 Class I, II N/A 1.8 Differential SSTL33, Class I, II N/A 3.3 Differential SSTL25, Class I, II N/A 2.5 Differential SSTL18, Class I, II N/A 1.8 Differential HSTL18, Class I, II N/A 1.8 Differential HSTL15, Class I N/A 1.5 1, 2 LVDS N/A 2.5 MLVDS1 N/A 2.5 1 BLVDS N/A 2.5 LVPECL1 N/A 3.3 Differential Interfaces 1 RSDS LVCMOS33D1 N/A 2.5 4mA, 8mA, 12mA, 16mA, 20mA 3.3 1. Emulated with external resistors. 2. On the left and right edges, LVDS outputs are supported with a dedicated differential output driver on 50% of the I/Os. This solution does not require external resistors at the driver. Hot Socketing LatticeXP2 devices have been carefully designed to ensure predictable behavior during power-up and powerdown. Power supplies can be sequenced in any order. During power-up and power-down sequences, the I/Os remain in tri-state until the power supply voltage is high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled to within specified limits. This allows for easy integration with the rest of the system. These capabilities make the LatticeXP2 ideal for many multiple power supply and hot-swap applications. IEEE 1149.1-Compliant Boundary Scan Testability All LatticeXP2 devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant Test Access Port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in 2-37 Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage VCCJ and can operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards. For more information, please see TN1141, LatticeXP2 sysCONFIG Usage Guide. flexiFLASH Device Configuration The LatticeXP2 devices combine Flash and SRAM on a single chip to provide users with flexibility in device programming and configuration. Figure 2-33 provides an overview of the arrangement of Flash and SRAM configuration cells within the device. The remainder of this section provides an overview of these capabilities. See TN1141, LatticeXP2 sysCONFIG Usage Guide for a more detailed description. Figure 2-33. Overview of Flash and SRAM Configuration Cells Within LatticeXP2 Devices Massively Parallel Data Transfer Instant-ON EBR Blocks Flash Memory Flash for Single-Chip Solution SRAM Configuration Bits FlashBAK for EBR Storage EBR Blocks TAG Memory Decryption and Device Lock Device Lock for Design Security SPI and JTAG At power-up, or on user command, data is transferred from the on-chip Flash memory to the SRAM configuration cells that control the operation of the device. This is done with massively parallel buses enabling the parts to operate within microseconds of the power supplies reaching valid levels; this capability is referred to as Instant-On. The on-chip Flash enables a single-chip solution eliminating the need for external boot memory. This Flash can be programmed through either the JTAG or Slave SPI ports of the device. The SRAM configuration space can also be infinitely reconfigured through the JTAG and Master SPI ports. The JTAG port is IEEE 1149.1 and IEEE 1532 compliant. As described in the EBR section of the data sheet, the FlashBAK capability of the parts enables the contents of the EBR blocks to be written back into the Flash storage area without erasing or reprogramming other aspects of the device configuration. Serial TAG memory is also available to allow the storage of small amounts of data such as calibration coefficients and error codes. For applications where security is important, the lack of an external bitstream provides a solution that is inherently more secure than SRAM only FPGAs. This is further enhanced by device locking. The device can be in one of three modes: 2-38 Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor 1. Unlocked 2. Key Locked - Presenting the key through the programming interface allows the device to be unlocked. 3. Permanently Locked - The device is permanently locked. To further complement the security of the device a One Time Programmable (OTP) mode is available. Once the device is set in this mode it is not possible to erase or re-program the Flash portion of the device. Serial TAG Memory LatticeXP2 devices offer 0.6 to 3.3kbits of Flash memory in the form of Serial TAG memory. The TAG memory is an area of the on-chip Flash that can be used for non-volatile storage including electronic ID codes, version codes, date stamps, asset IDs and calibration settings. A block diagram of the TAG memory is shown in Figure 2-34. The TAG memory is accessed in the same way as external SPI Flash and it can be read or programmed either through JTAG, an external Slave SPI Port, or directly from FPGA logic. To read the TAG memory, a start address is specified and the entire TAG memory contents are read sequentially in a first-in-first-out manner. The TAG memory is independent of the Flash used for device configuration and given its use for general-purpose storage functions is always accessible regardless of the device security settings. For more information, see TN1137, LatticeXP2 Memory Usage Guide and TN1141, LatticeXP2 sysCONFIG Usage Guide. Figure 2-34. Serial TAG Memory Diagram External Slave SPI Port External Slave SPI Port TDI JTAG TDO Data Shift Register FPGA Logic JTAG FPGA Logic Sequential Address Counter Flash Flash Memory Array Live Update Technology Many applications require field updates of the FPGA. LatticeXP2 devices provide three features that enable this configuration to be done in a secure and failsafe manner while minimizing impact on system operation. 1. Decryption Support LatticeXP2 devices provide on-chip, non-volatile key storage to support decryption of a 128-bit AES encrypted bitstream, securing designs and deterring design piracy. 2. TransFR (Transparent Field Reconfiguration) TransFR I/O (TFR) is a unique Lattice technology that allows users to update their logic in the field without interrupting system operation using a single ispVM command. TransFR I/O allows I/O states to be frozen during device configuration. This allows the device to be field updated with a minimum of system disruption and downtime. For more information please see TN1087, Minimizing System Interruption During Configuration Using TransFR Technology. 3. Dual Boot Image Support Dual boot images are supported for applications requiring reliable remote updates of configuration data for the system FPGA. After the system is running with a basic configuration, a new boot image can be downloaded remotely and stored in a separate location in the configuration storage device. Any time after the update the LatticeXP2 can be re-booted from this new configuration file. If there is a problem such as corrupt data during download or incorrect version number with this new boot image, the LatticeXP2 device can revert back to the 2-39 Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor original backup configuration and try again. This all can be done without power cycling the system. For more information please see TN1220, LatticeXP2 Dual Boot Feature. For more information on device configuration, please see TN1141, LatticeXP2 sysCONFIG Usage Guide. Soft Error Detect (SED) Support LatticeXP2 devices have dedicated logic to perform Cyclic Redundancy Code (CRC) checks. During configuration, the configuration data bitstream can be checked with the CRC logic block. In addition, LatticeXP2 devices can be programmed for checking soft errors in SRAM. SED can be run on a programmed device when the user logic is not active. In the event a soft error occurs, the device can be programmed to either reload from a known good boot image (from internal Flash or external SPI memory) or generate an error signal. For further information on SED support, please see TN1130, LatticeXP2 Soft Error Detection (SED) Usage Guide. On-Chip Oscillator Every LatticeXP2 device has an internal CMOS oscillator that is used to derive a Master Clock (CCLK) for configuration. The oscillator and CCLK run continuously and are available to user logic after configuration is complete. The available CCLK frequencies are listed in Table 2-14. When a different CCLK frequency is selected during the design process, the following sequence takes place: 1. Device powers up with the default CCLK frequency. 2. During configuration, users select a different CCLK frequency. 3. CCLK frequency changes to the selected frequency after clock configuration bits are received. This internal CMOS oscillator is available to the user by routing it as an input clock to the clock tree. For further information on the use of this oscillator for configuration or user mode, please see TN1141, LatticeXP2 sysCONFIG Usage Guide. Table 2-14. Selectable CCLKs and Oscillator Frequencies During Configuration and User Mode CCLK/Oscillator (MHz) 2.51 3.12 4.3 5.4 6.9 8.1 9.2 10 13 15 20 26 32 40 54 803 1633 1. Software default oscillator frequency. 2. Software default CCLK frequency. 3. Frequency not valid for CCLK. 2-40 Architecture LatticeXP2 Family Data Sheet Lattice Semiconductor Density Shifting The LatticeXP2 family is designed to ensure that different density devices in the same family and in the same package have the same pinout. Furthermore, the architecture ensures a high success rate when performing design migration from lower density devices to higher density devices. In many cases, it is also possible to shift a lower utilization design targeted for a high-density device to a lower density device. However, the exact details of the final resource utilization will impact the likely success in each case. 2-41 LatticeXP2 Family Data Sheet DC and Switching Characteristics January 2012 Data Sheet DS1009 Absolute Maximum Ratings1, 2, 3 Supply Voltage VCC . . . . . . . . . . . . . . . . . . . -0.5 to 1.32V Supply Voltage VCCAUX . . . . . . . . . . . . . . . . -0.5 to 3.75V Supply Voltage VCCJ . . . . . . . . . . . . . . . . . . -0.5 to 3.75V Supply Voltage VCCPLL4 . . . . . . . . . . . . . . . . -0.5 to 3.75V Output Supply Voltage VCCIO . . . . . . . . . . . -0.5 to 3.75V Input or I/O Tristate Voltage Applied5 . . . . . . -0.5 to 3.75V Storage Temperature (Ambient) . . . . . . . . . -65 to 150C Junction Temperature Under Bias (Tj) . . . . . . . . . +125C 1. Stress above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 2. Compliance with the Lattice Thermal Management document is required. 3. All voltages referenced to GND. 4. VCCPLL only available on csBGA, PQFP and TQFP packages. 5. Overshoot and undershoot of -2V to (VIHMAX + 2) volts is permitted for a duration of <20 ns. Recommended Operating Conditions Symbol Parameter Min. Max. Units VCC Core Supply Voltage 1.14 1.26 V VCCAUX4, 5 Auxiliary Supply Voltage 3.135 3.465 V VCCPLL1 PLL Supply Voltage 3.135 3.465 V VCCIO I/O Driver Supply Voltage 1.14 3.465 V VCCJ2 Supply Voltage for IEEE 1149.1 Test Access Port 1.14 3.465 V tJCOM Junction Temperature, Commercial Operation tJIND Junction Temperature, Industrial Operation 2, 3, 4 0 85 C -40 100 C 1. VCCPLL only available on csBGA, PQFP and TQFP packages. 2. If VCCIO or VCCJ is set to 1.2V, they must be connected to the same power supply as VCC. If VCCIO or VCCJ is set to 3.3V, they must be connected to the same power supply as VCCAUX. 3. See recommended voltages by I/O standard in subsequent table. 4. To ensure proper I/O behavior, VCCIO must be turned off at the same time or earlier than VCCAUX. 5. In fpBGA and ftBGA packages, the PLLs are connected to, and powered from, the auxiliary power supply. On-Chip Flash Memory Specifications Symbol Parameter 1 NPROGCYC Max. Flash Programming Cycles per tRETENTION 10,000 Flash Functional Programming Cycles 100,000 Units Cycles 1. The minimum data retention, tRETENTION, is 20 years. (c) 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 3-1 DS1009 DC and Switching_01.8 DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor Hot Socketing Specifications1, 2, 3, 4 Symbol IDK 1. 2. 3. 4. Parameter Condition 0 VIN VIH (MAX.) Input or I/O Leakage Current Min. Typ. Max. Units -- -- +/-1 mA Insensitive to sequence of VCC, VCCAUX and VCCIO. However, assumes monotonic rise/fall rates for VCC, VCCAUX and VCCIO. 0 VCC VCC (MAX), 0 VCCIO VCCIO (MAX) or 0 VCCAUX VCCAUX (MAX). IDK is additive to IPU, IPW or IBH. LVCMOS and LVTTL only. ESD Performance Please refer to the LatticeXP2 Product Family Qualification Summary for complete qualification data, including ESD performance. DC Electrical Characteristics Over Recommended Operating Conditions Symbol Parameter Condition 0 VIN VCCIO Min. Typ. Max. Units -- -- 10 A IIL, IIH1 Input or I/O Low Leakage VCCIO VIN VIH (MAX) -- -- 150 A IPU I/O Active Pull-up Current 0 VIN 0.7 VCCIO -30 -- -150 A IPD I/O Active Pull-down Current VIL (MAX) VIN VCCIO 30 -- 210 A IBHLS 30 -- -- A IBHHS Bus Hold Low Sustaining Current VIN = VIL (MAX) Bus Hold High Sustaining Current VIN = 0.7 VCCIO -30 -- -- A IBHLO Bus Hold Low Overdrive Current 0 VIN VCCIO -- -- 210 A IBHHO Bus Hold High Overdrive Current 0 VIN VCCIO VBHT Bus Hold Trip Points C1 I/O Capacitance2 C2 Dedicated Input Capacitance -- -- -150 A VIL (MAX) -- VIH (MIN) V VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, VCC = 1.2V, VIO = 0 to VIH (MAX) -- 8 -- pf VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, VCC = 1.2V, VIO = 0 to VIH (MAX) -- 6 -- pf 1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured with the output driver active. Bus maintenance circuits are disabled. 2. TA 25oC, f = 1.0 MHz. 3-2 DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor Supply Current (Standby)1, 2, 3, 4 Over Recommended Operating Conditions Symbol ICC ICCAUX Units XP2-5 14 mA XP2-8 18 mA XP2-17 24 mA XP2-30 35 mA Device Core Power Supply Current Auxiliary Power Supply Current 6 ICCPLL PLL Power Supply Current (per PLL) ICCIO Bank Power Supply Current (per bank) ICCJ VCCJ Power Supply Current 1. 2. 3. 4. 5. 6. Typical5 Parameter XP2-40 45 mA XP2-5 15 mA XP2-8 15 mA XP2-17 15 mA XP2-30 16 mA XP2-40 16 mA 0.1 mA 2 mA 0.25 mA For further information on supply current, please see TN1139, Power Estimation and Management for LatticeXP2 Devices. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND. Frequency 0 MHz. Pattern represents a "blank" configuration data file. TJ = 25oC, power supplies at nominal voltage. In fpBGA and ftBGA packages the PLLs are connected to and powered from the auxiliary power supply. For these packages, the actual auxiliary supply current is the sum of ICCAUX and ICCPLL. For csBGA, PQFP and TQFP packages the PLLs are powered independent of the auxiliary power supply. 3-3 DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor Initialization Supply Current1, 2, 3, 4, 5 Over Recommended Operating Conditions Symbol ICC ICCAUX Parameter Typical (25C, Max. Supply)6 Units XP2-5 20 mA XP2-8 21 mA XP2-17 44 mA XP2-30 58 mA Device Core Power Supply Current Auxiliary Power Supply Current7 XP2-40 62 mA XP2-5 67 mA XP2-8 74 mA XP2-17 112 mA XP2-30 124 mA XP2-40 130 mA ICCPLL PLL Power Supply Current (per PLL) 1.8 mA ICCIO Bank Power Supply Current (per Bank) 6.4 mA ICCJ VCCJ Power Supply Current 1.2 mA 1. 2. 3. 4. 5. For further information on supply current, please see TN1139, Power Estimation and Management for LatticeXP2 Devices. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND. Frequency 0 MHz. Does not include additional current from bypass or decoupling capacitor across the supply. A specific configuration pattern is used that scales with the size of the device; consists of 75% PFU utilization, 50% EBR, and 25% I/O configuration. 6. TJ = 25C, power supplies at nominal voltage. 7. In fpBGA and ftBGA packages the PLLs are connected to and powered from the auxiliary power supply. For these packages, the actual auxiliary supply current is the sum of ICCAUX and ICCPLL. For csBGA, PQFP and TQFP packages the PLLs are powered independent of the auxiliary power supply. 3-4 DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor Programming and Erase Flash Supply Current1, 2, 3, 4, 5 Over Recommended Operating Conditions Symbol ICC ICCAUX Typical (25C, Max. Supply)6 Units XP2-5 17 mA XP2-8 21 mA XP2-17 28 mA XP2-30 36 mA XP2-40 50 mA XP2-5 64 mA XP2-8 66 mA XP2-17 83 mA XP2-30 87 mA XP2-40 88 mA Parameter Core Power Supply Current Auxiliary Power Supply Current7 Device ICCPLL PLL Power Supply Current (per PLL) 0.1 mA ICCIO Bank Power Supply Current (per Bank) 5 mA ICCJ VCCJ Power Supply Current8 14 mA 1. 2. 3. 4. 5. 6. 7. 8. For further information on supply current, please see TN1139, Power Estimation and Management for LatticeXP2 Devices. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND. Frequency 0 MHz (excludes dynamic power from FPGA operation). A specific configuration pattern is used that scales with the size of the device; consists of 75% PFU utilization, 50% EBR, and 25% I/O configuration. Bypass or decoupling capacitor across the supply. TJ = 25C, power supplies at nominal voltage. In fpBGA and ftBGA packages the PLLs are connected to and powered from the auxiliary power supply. For these packages, the actual auxiliary supply current is the sum of ICCAUX and ICCPLL. For csBGA, PQFP and TQFP packages the PLLs are powered independent of the auxiliary power supply. When programming via JTAG. 3-5 DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor sysIO Recommended Operating Conditions Over Recommended Operating Conditions VREF (V) VCCIO Min. Typ. Max. Min. Typ. Max. 2 LVCMOS33 3.135 3.3 3.465 -- -- -- LVCMOS252 2.375 2.5 2.625 -- -- -- LVCMOS18 1.71 1.8 1.89 -- -- -- LVCMOS15 1.425 1.5 1.575 -- -- -- LVCMOS122 1.14 1.2 1.26 -- -- -- LVTTL332 3.135 3.3 3.465 -- -- -- PCI33 3.135 3.3 3.465 -- -- -- SSTL18_I2, SSTL18_II2 1.71 1.8 1.89 0.833 0.9 0.969 SSTL25_I2, SSTL25_II2 2.375 2.5 2.625 1.15 1.25 1.35 SSTL33_I2, SSTL33_II2 3.135 3.3 3.465 1.3 1.5 1.7 HSTL15_I2 1.425 1.5 1.575 0.68 0.75 0.9 HSTL18_I2, HSTL18_II2 1.71 1.8 1.89 0.816 0.9 1.08 LVDS252 2.375 2.5 2.625 -- -- -- Standard MLVDS25 1 2.375 2.5 2.625 -- -- -- LVPECL331, 2 3.135 3.3 3.465 -- -- -- BLVDS251, 2 2.375 2.5 2.625 -- -- -- RSDS 2.375 2.5 2.625 -- -- -- SSTL18D_I2, SSTL18D_II2 1.71 1.8 1.89 -- -- -- SSTL25D_ I2, SSTL25D_II2 2.375 2.5 2.625 -- -- -- SSTL33D_ I2, SSTL33D_ II2 3.135 3.3 3.465 -- -- -- HSTL15D_ I2 1.425 1.5 1.575 -- -- -- 1.71 1.8 1.89 -- -- -- 1, 2 2 HSTL18D_ I , HSTL18D_ II2 1. Inputs on chip. Outputs are implemented with the addition of external resistors. 2. Input on this standard does not depend on the value of VCCIO. 3-6 DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor sysIO Single-Ended DC Electrical Characteristics Over Recommended Operating Conditions Input/Output Standard LVCMOS33 LVTTL33 LVCMOS25 LVCMOS18 VIL VIH Min. (V) Max. (V) Min. (V) Max. (V) -0.3 0.8 2.0 3.6 -0.3 -0.3 -0.3 0.8 0.7 0.35 VCCIO 2.0 1.7 0.65 VCCIO 3.6 3.6 3.6 LVCMOS15 -0.3 0.35 VCCIO 0.65 VCCIO 3.6 LVCMOS12 -0.3 0.35 VCC 0.65 VCC 3.6 PCI33 -0.3 0.3 VCCIO 0.5 VCCIO 3.6 VOL VOH Max. (V) Min. (V) VCCIO - 0.4 20, 16, 12, 8, 4 -20, -16, -12, -8, -4 0.2 VCCIO - 0.2 0.1 -0.1 0.4 VCCIO - 0.4 20, 16, 12, 8, 4 -20, -16, -12, -8, -4 0.2 VCCIO - 0.2 0.1 -0.1 0.4 VCCIO - 0.4 20, 16, 12, 8, 4 -20, -16, -12, -8, -4 0.2 VCCIO - 0.2 0.1 -0.1 0.4 VCCIO - 0.4 16, 12, 8, 4 -16, -12, -8, -4 0.2 VCCIO - 0.2 0.1 -0.1 0.4 VCCIO - 0.4 8, 4 -8, -4 0.2 VCCIO - 0.2 0.1 -0.1 0.4 VCCIO - 0.4 6, 2 -6, -2 0.2 VCCIO - 0.2 0.1 -0.1 0.1 VCCIO 0.9 VCCIO 0.7 VCCIO - 1.1 1.5 -0.5 SSTL33_I -0.3 VREF - 0.2 VREF + 0.2 3.6 -0.3 VREF - 0.2 VREF + 0.2 3.6 0.5 VCCIO - 0.9 SSTL25_I -0.3 VREF - 0.18 VREF + 0.18 3.6 0.54 VCCIO - 0.62 SSTL25_II -0.3 VREF - 0.18 VREF + 0.18 3.6 0.35 VCCIO - 0.43 SSTL18_I -0.3 VREF - 0.125 VREF + 0.125 3.6 0.4 VCCIO - 0.4 -0.3 VREF - 0.125 VREF + 0.125 HSTL15_I -0.3 VREF - 0.1 HSTL18_I -0.3 HSTL18_II -0.3 IOH1 (mA) 0.4 SSTL33_II SSTL18_II IOL1 (mA) 3.6 0.28 VCCIO - 0.28 VREF + 0.1 3.6 0.4 VCCIO - 0.4 VREF - 0.1 VREF + 0.1 3.6 0.4 VCCIO - 0.4 VREF - 0.1 VREF + 0.1 3.6 0.4 VCCIO - 0.4 8 -8 16 -16 7.6 -7.6 12 -12 15.2 -15.2 20 -20 6.7 -6.7 8 -8 11 -11 4 -4 8 -8 8 -8 12 -12 16 -16 1. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O bank and the end of an I/O bank, as shown in the logic signal connections table shall not exceed n * 8mA, where n is the number of I/Os between bank GND connections or between the last GND in a bank and the end of a bank. 3-7 DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor sysIO Differential Electrical Characteristics LVDS Over Recommended Operating Conditions Parameter Description Test Conditions Min. Typ. Max. Units 0 -- 2.4 V 0.05 -- 2.35 V +/-100 -- -- mV -- -- +/-10 A -- 1.38 1.60 V VINP, VINM Input Voltage VCM Input Common Mode Voltage Half the Sum of the Two Inputs VTHD Differential Input Threshold Difference Between the Two Inputs IIN Input Current Power On or Power Off VOH Output High Voltage for VOP or VOM RT = 100 Ohm VOL Output Low Voltage for VOP or VOM RT = 100 Ohm 0.9V 1.03 -- V VOD Output Voltage Differential (VOP - VOM), RT = 100 Ohm 250 350 450 mV VOD Change in VOD Between High and Low -- -- 50 mV VOS Output Voltage Offset 1.125 1.20 1.375 V VOS Change in VOS Between H and L -- -- 50 mV ISA Output Short Circuit Current VOD = 0V Driver Outputs Shorted to Ground -- -- 24 mA ISAB Output Short Circuit Current VOD = 0V Driver Outputs Shorted to Each Other -- -- 12 mA (VOP + VOM)/2, RT = 100 Ohm Differential HSTL and SSTL Differential HSTL and SSTL outputs are implemented as a pair of complementary single-ended outputs. All allowable single-ended output classes (class I and class II) are supported in this mode. For further information on LVPECL, RSDS, MLVDS, BLVDS and other differential interfaces please see details in additional technical notes listed at the end of this data sheet. LVDS25E The top and bottom sides of LatticeXP2 devices support LVDS outputs via emulated complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-1 is one possible solution for point-to-point signals. Figure 3-1. LVDS25E Output Termination Example VCCIO = 2.5V (5%) RS=158 ohms (1%) 8 mA VCCIO = 2.5V (5%) RS=158 ohms (1%) RP = 140 ohms (1%) RT = 100 ohms (1%) 8 mA Transmission line, Zo = 100 ohm differential OFF-chip ON-chip ON-chip OFF-chip 3-8 + - DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor Table 3-1. LVDS25E DC Conditions Parameter Description Typical Units VCCIO Output Driver Supply (+/-5%) 2.50 V ZOUT Driver Impedance 20 RS Driver Series Resistor (+/-1%) 158 RP Driver Parallel Resistor (+/-1%) 140 RT Receiver Termination (+/-1%) 100 VOH Output High Voltage (after RP) 1.43 V VOL Output Low Voltage (after RP) 1.07 V VOD Output Differential Voltage (After RP) 0.35 V VCM Output Common Mode Voltage 1.25 V ZBACK Back Impedance 100.5 IDC DC Output Current 6.03 mA LVCMOS33D All I/O banks support emulated differential I/O using the LVCMOS33D I/O type. This option, along with the external resistor network, provides the system designer the flexibility to place differential outputs on an I/O bank with 3.3V VCCIO. The default drive current for LVCMOS33D output is 12mA with the option to change the device strength to 4mA, 8mA, 16mA or 20mA. Follow the LVCMOS33 specifications for the DC characteristics of the LVCMOS33D. 3-9 DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor BLVDS The LatticeXP2 devices support the BLVDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one possible solution for bi-directional multi-point differential signals. Figure 3-2. BLVDS Multi-point Output Example Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential 2.5V RS = 90 ohms RS = 90 ohms 16mA 2.5V 16mA 45-90 ohms 45-90 ohms RTL RTR 2.5V 2.5V 16mA 16mA RS = 90 ohms RS = 90 ohms + 2.5V 2.5V 16mA RS = 90 ohms ... + - - + - 2.5V 16mA RS = 90 ohms + RS = 90 ohms RS = 90 ohms 2.5V 16mA - 16mA Table 3-2. BLVDS DC Conditions1 Over Recommended Operating Conditions Typical Parameter Description Zo = 45 Zo = 90 Units VCCIO Output Driver Supply (+/- 5%) 2.50 2.50 V ZOUT Driver Impedance 10.00 10.00 RS Driver Series Resistor (+/- 1%) 90.00 90.00 RTL Driver Parallel Resistor (+/- 1%) 45.00 90.00 RTR Receiver Termination (+/- 1%) 45.00 90.00 VOH Output High Voltage (After RTL) 1.38 1.48 V VOL Output Low Voltage (After RTL) 1.12 1.02 V VOD Output Differential Voltage (After RTL) 0.25 0.46 V VCM Output Common Mode Voltage 1.25 1.25 V IDC DC Output Current 11.24 10.20 mA 1. For input buffer, see LVDS table. 3-10 DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor LVPECL The LatticeXP2 devices support the differential LVPECL standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for pointto-point signals. Figure 3-3. Differential LVPECL VCCIO = 3.3V (+/-5%) RS = 93.1 ohms (+/-1%) 16mA VCCIO = 3.3V (+/-5%) RP = 196 ohms (+/-1%) RS = 93.1 ohms (+/-1%) 16mA + RT = 100 ohms (+/-1%) - Transmission line, Zo = 100 ohm differential On-chip Off-chip Off-chip On-chip Table 3-3. LVPECL DC Conditions1 Over Recommended Operating Conditions Parameter Description Typical Units VCCIO Output Driver Supply (+/-5%) ZOUT Driver Impedance RS RP RT VOH VOL Output Low Voltage (After RP) 1.25 V VOD Output Differential Voltage (After RP) 0.80 V 3.30 V 10 Driver Series Resistor (+/-1%) 93 Driver Parallel Resistor (+/-1%) 196 Receiver Termination (+/-1%) 100 Output High Voltage (After RP) 2.05 V VCM Output Common Mode Voltage 1.65 V ZBACK Back Impedance 100.5 IDC DC Output Current 12.11 mA 1. For input buffer, see LVDS table. 3-11 DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor RSDS The LatticeXP2 devices support differential RSDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS standard implementation. Resistor values in Figure 3-4 are industry standard values for 1% resistors. Figure 3-4. RSDS (Reduced Swing Differential Standard) VCCIO = 2.5V (+/-5%) RS = 294 ohms (+/-1%) 8mA VCCIO = 2.5V (+/-5%) RS = 294 ohms (+/-1%) 8mA RP = 121 ohms (+/-1%) + RT = 100 ohms (+/-1%) - Transmission line, Zo = 100 ohm differential On-chip Off-chip Off-chip On-chip Table 3-4. RSDS DC Conditions1 Over Recommended Operating Conditions Parameter Description Typical Units VCCIO Output Driver Supply (+/-5%) ZOUT Driver Impedance 2.50 V 20 RS RP Driver Series Resistor (+/-1%) 294 Driver Parallel Resistor (+/-1%) 121 RT VOH Receiver Termination (+/-1%) 100 Output High Voltage (After RP) 1.35 V VOL Output Low Voltage (After RP) 1.15 V VOD Output Differential Voltage (After RP) 0.20 V VCM Output Common Mode Voltage 1.25 V ZBACK Back Impedance 101.5 IDC DC Output Current 3.66 mA 1. For input buffer, see LVDS table. 3-12 DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor MLVDS The LatticeXP2 devices support the differential MLVDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The MLVDS input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-5 is one possible solution for MLVDS standard implementation. Resistor values in Figure 3-5 are industry standard values for 1% resistors. Figure 3-5. MLVDS (Reduced Swing Differential Standard) Heavily loaded backplace, effective Zo~50 to 70 ohms differential 2.5V RS = 35ohms RS = 35ohms 2.5V 16mA 16mA 2.5V RTL 50 to 70 ohms +/-1% 50 to 70 ohms +/-1% RTR 2.5V 16mA RS = 35ohms 16mA RS = 35ohms RS = 35ohms + - RS = 35ohms RS = 35ohms RS = 35ohms + - 2.5V 2.5V 2.5V 16mA 16mA - + - + ... 2.5V 16mA 16mA Table 3-5. MLVDS DC Conditions1 Typical Parameter Description Zo=50 Zo=70 Units VCCIO Output Driver Supply (+/-5%) 2.50 2.50 V ZOUT Driver Impedance 10.00 10.00 RS Driver Series Resistor (+/-1%) 35.00 35.00 RTL Driver Parallel Resistor (+/-1%) 50.00 70.00 RTR Receiver Termination (+/-1%) 50.00 70.00 VOH Output High Voltage (After RTL) 1.52 1.60 V VOL Output Low Voltage (After RTL) 0.98 0.90 V VOD Output Differential Voltage (After RTL) 0.54 0.70 V VCM Output Common Mode Voltage 1.25 1.25 V IDC DC Output Current 21.74 20.00 mA 1. For input buffer, see LVDS table. For further information on LVPECL, RSDS, MLVDS, BLVDS and other differential interfaces please see details of additional technical information at the end of this data sheet. 3-13 DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor Typical Building Block Function Performance1 Pin-to-Pin Performance (LVCMOS25 12mA Drive) Function -7 Timing Units 16-bit Decoder 4.4 ns 32-bit Decoder 5.2 ns 64-bit Decoder 5.6 ns 4:1 MUX 3.7 ns 8:1 MUX 3.9 ns 16:1 MUX 4.3 ns 32:1 MUX 4.5 ns -7 Timing Units 16-bit Decoder 521 MHz 32-bit Decoder 537 MHz 64-bit Decoder 484 MHz 4:1 MUX 744 MHz 8:1 MUX 678 MHz 16:1 MUX 616 MHz 32:1 MUX 529 MHz 8-bit Adder 570 MHz 16-bit Adder 507 MHz 64-bit Adder 293 MHz 16-bit Counter 541 MHz 32-bit Counter 440 MHz 64-bit Counter 321 MHz 64-bit Accumulator 261 MHz 512x36 Single Port RAM, EBR Output Registers 315 MHz 1024x18 True-Dual Port RAM (Write Through or Normal, EBR Output Registers) 315 MHz 1024x18 True-Dual Port RAM (Write Through or Normal, PLC Output Registers) 231 MHz 16x4 Pseudo-Dual Port RAM (One PFU) 760 MHz 32x2 Pseudo-Dual Port RAM 455 MHz 64x1 Pseudo-Dual Port RAM 351 MHz 18x18 Multiplier (All Registers) 342 MHz 9x9 Multiplier (All Registers) 342 MHz 36x36 Multiply (All Registers) 330 MHz Basic Functions Register-to-Register Performance Function Basic Functions Embedded Memory Functions Distributed Memory Functions DSP Functions 18x18 Multiply/Accumulate (Input and Output Registers) 218 MHz 18x18 Multiply-Add/Sub-Sum (All Registers) 292 MHz 3-14 DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor Register-to-Register Performance (Continued) Function -7 Timing Units 16-Tap Fully-Parallel FIR Filter 198 MHz 1024-pt FFT 221 MHz 8X8 Matrix Multiplication 196 MHz DSP IP Functions 1. These timing numbers were generated using the ispLEVER design tool. Exact performance may vary with device, design and tool version. The tool uses internal parameters that have been characterized but are not tested on every device. Timing v. A 0.12 Derating Timing Tables Logic timing provided in the following sections of this data sheet and the Diamond design tools are worst case numbers in the operating range. Actual delays at nominal temperature and voltage for best case process, can be much better than the values given in the tables. The Diamond design tool can provide logic timing numbers at a particular temperature and voltage. 3-15 DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor LatticeXP2 External Switching Characteristics Over Recommended Operating Conditions -7 Parameter Description Device Min. -6 -5 Max. Min. Max. Min. Max. Units General I/O Pin Parameters (using Primary Clock without PLL)1 tCO tSU tH tSU_DEL tH_DEL fMAX_IO Clock to Output - PIO Output Register Clock to Data Setup - PIO Input Register Clock to Data Hold - PIO Input Register Clock to Data Setup - PIO Input Register with Data Input Delay Clock to Data Hold - PIO Input Register with Input Data Delay XP2-5 -- 3.80 -- 4.20 -- 4.60 ns XP2-8 -- 3.80 -- 4.20 -- 4.60 ns XP2-17 -- 3.80 -- 4.20 -- 4.60 ns XP2-30 -- 4.00 -- 4.40 -- 4.90 ns XP2-40 -- 4.00 -- 4.40 -- 4.90 ns XP2-5 0.00 -- 0.00 -- 0.00 -- ns XP2-8 0.00 -- 0.00 -- 0.00 -- ns XP2-17 0.00 -- 0.00 -- 0.00 -- ns XP2-30 0.00 -- 0.00 -- 0.00 -- ns XP2-40 0.00 -- 0.00 -- 0.00 -- ns XP2-5 1.40 -- 1.70 -- 1.90 -- ns XP2-8 1.40 -- 1.70 -- 1.90 -- ns XP2-17 1.40 -- 1.70 -- 1.90 -- ns XP2-30 1.40 -- 1.70 -- 1.90 -- ns XP2-40 1.40 -- 1.70 -- 1.90 -- ns XP2-5 1.40 -- 1.70 -- 1.90 -- ns XP2-8 1.40 -- 1.70 -- 1.90 -- ns XP2-17 1.40 -- 1.70 -- 1.90 -- ns XP2-30 1.40 -- 1.70 -- 1.90 -- ns XP2-40 1.40 -- 1.70 -- 1.90 -- ns XP2-5 0.00 -- 0.00 -- 0.00 -- ns XP2-8 0.00 -- 0.00 -- 0.00 -- ns XP2-17 0.00 -- 0.00 -- 0.00 -- ns XP2-30 0.00 -- 0.00 -- 0.00 -- ns XP2-40 0.00 -- 0.00 -- 0.00 -- ns -- 420 -- 357 -- 311 MHz XP2-5 -- 3.20 -- 3.60 -- 3.90 ns XP2-8 -- 3.20 -- 3.60 -- 3.90 ns XP2-17 -- 3.20 -- 3.60 -- 3.90 ns XP2-30 -- 3.20 -- 3.60 -- 3.90 ns XP2-40 -- 3.20 -- 3.60 -- 3.90 ns XP2-5 0.00 -- 0.00 -- 0.00 -- ns XP2-8 0.00 -- 0.00 -- 0.00 -- ns XP2-17 0.00 -- 0.00 -- 0.00 -- ns XP2-30 0.00 -- 0.00 -- 0.00 -- ns XP2-40 0.00 -- 0.00 -- 0.00 -- ns Clock Frequency of I/O and PFU XP2 Register General I/O Pin Parameters (using Edge Clock without PLL)1 tCOE tSUE Clock to Output - PIO Output Register Clock to Data Setup - PIO Input Register 3-16 DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor LatticeXP2 External Switching Characteristics (Continued) Over Recommended Operating Conditions -7 Parameter tHE tSU_DELE tH_DELE fMAX_IOE Description Clock to Data Hold - PIO Input Register Clock to Data Setup - PIO Input Register with Data Input Delay Clock to Data Hold - PIO Input Register with Input Data Delay Device -6 -5 Min. Max. Min. Max. Min. Max. Units XP2-5 1.00 -- 1.30 -- 1.60 -- ns XP2-8 1.00 -- 1.30 -- 1.60 -- ns XP2-17 1.00 -- 1.30 -- 1.60 -- ns XP2-30 1.20 -- 1.60 -- 1.90 -- ns XP2-40 1.20 -- 1.60 -- 1.90 -- ns XP2-5 1.00 -- 1.30 -- 1.60 -- ns XP2-8 1.00 -- 1.30 -- 1.60 -- ns XP2-17 1.00 -- 1.30 -- 1.60 -- ns XP2-30 1.20 -- 1.60 -- 1.90 -- ns XP2-40 1.20 -- 1.60 -- 1.90 -- ns XP2-5 0.00 -- 0.00 -- 0.00 -- ns XP2-8 0.00 -- 0.00 -- 0.00 -- ns XP2-17 0.00 -- 0.00 -- 0.00 -- ns XP2-30 0.00 -- 0.00 -- 0.00 -- ns XP2-40 0.00 -- 0.00 -- 0.00 -- ns -- 420 -- 357 -- 311 MHz XP2-5 -- 3.00 -- 3.30 -- 3.70 ns XP2-8 -- 3.00 -- 3.30 -- 3.70 ns XP2-17 -- 3.00 -- 3.30 -- 3.70 ns XP2-30 -- 3.00 -- 3.30 -- 3.70 ns XP2-40 -- 3.00 -- 3.30 -- 3.70 ns XP2-5 1.00 -- 1.20 -- 1.40 -- ns XP2-8 1.00 -- 1.20 -- 1.40 -- ns XP2-17 1.00 -- 1.20 -- 1.40 -- ns XP2-30 1.00 -- 1.20 -- 1.40 -- ns XP2-40 1.00 -- 1.20 -- 1.40 -- ns XP2-5 0.90 -- 1.10 -- 1.30 -- ns XP2-8 0.90 -- 1.10 -- 1.30 -- ns XP2-17 0.90 -- 1.10 -- 1.30 -- ns XP2-30 1.00 -- 1.20 -- 1.40 -- ns XP2-40 1.00 -- 1.20 -- 1.40 -- ns XP2-5 1.90 -- 2.10 -- 2.30 -- ns XP2-8 1.90 -- 2.10 -- 2.30 -- ns XP2-17 1.90 -- 2.10 -- 2.30 -- ns XP2-30 2.00 -- 2.20 -- 2.40 -- ns XP2-40 2.00 -- 2.20 -- 2.40 -- ns Clock Frequency of I/O and PFU XP2 Register General I/O Pin Parameters (using Primary Clock with PLL)1 tCOPLL tSUPLL tHPLL tSU_DELPLL Clock to Output - PIO Output Register Clock to Data Setup - PIO Input Register Clock to Data Hold - PIO Input Register Clock to Data Setup - PIO Input Register with Data Input Delay 3-17 DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor LatticeXP2 External Switching Characteristics (Continued) Over Recommended Operating Conditions -7 Parameter tH_DELPLL Description Clock to Data Hold - PIO Input Register with Input Data Delay Device -6 -5 Min. Max. Min. Max. Min. Max. Units XP2-5 0.00 -- 0.00 -- 0.00 -- ns XP2-8 0.00 -- 0.00 -- 0.00 -- ns XP2-17 0.00 -- 0.00 -- 0.00 -- ns XP2-30 0.00 -- 0.00 -- 0.00 -- ns XP2-40 0.00 -- 0.00 -- 0.00 -- ns DDR2 and DDR23 I/O Pin Parameters tDVADQ Data Valid After DQS (DDR Read) XP2 -- 0.29 -- 0.29 -- 0.29 UI tDVEDQ Data Hold After DQS (DDR Read) XP2 0.71 -- 0.71 -- 0.71 -- UI tDQVBS Data Valid Before DQS XP2 0.25 -- 0.25 -- 0.25 -- UI tDQVAS Data Valid After DQS XP2 0.25 -- 0.25 -- 0.25 -- UI fMAX_DDR DDR Clock Frequency XP2 95 200 95 166 95 133 MHz fMAX_DDR2 DDR Clock Frequency XP2 133 200 133 200 133 166 MHz fMAX_PRI Frequency for Primary Clock Tree XP2 -- 420 -- 357 -- 311 MHz tW_PRI Clock Pulse Width for Primary Clock XP2 1 -- 1 -- 1 -- ns tSKEW_PRI Primary Clock Skew Within a Bank XP2 -- 160 -- 160 -- 160 ps Primary Clock Edge Clock (ECLK1 and ECLK2) fMAX_ECLK Frequency for Edge Clock XP2 -- 420 -- 357 -- 311 MHz tW_ECLK Clock Pulse Width for Edge Clock XP2 1 -- 1 -- 1 -- ns tSKEW_ECLK Edge Clock Skew Within an Edge of the Device XP2 -- 130 -- 130 -- 130 ps 1. General timing numbers based on LVCMOS 2.5, 12mA, 0pf load. 2. DDR timing numbers based on SSTL25. 3. DDR2 timing numbers based on SSTL18. Timing v. A 0.12 3-18 DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor LatticeXP2 Internal Switching Characteristics1 Over Recommended Operating Conditions -7 Parameter Description -6 -5 Min. Max. Min. Max. Min. Max. Units PFU/PFF Logic Mode Timing tLUT4_PFU LUT4 delay (A to D inputs to F output) -- 0.216 -- 0.238 -- 0.260 ns tLUT6_PFU LUT6 delay (A to D inputs to OFX output) -- 0.304 -- 0.399 -- 0.494 ns tLSR_PFU Set/Reset to output of PFU (Asynchronous) -- 0.720 -- 0.769 -- 0.818 ns tSUM_PFU Clock to Mux (M0,M1) Input Setup Time 0.154 -- 0.151 -- 0.148 -- ns tHM_PFU Clock to Mux (M0,M1) Input Hold Time -0.061 -- -0.057 -- -0.053 -- ns tSUD_PFU Clock to D input setup time 0.061 -- 0.077 -- 0.093 -- ns tHD_PFU Clock to D input hold time 0.002 -- 0.003 -- 0.003 -- ns tCK2Q_PFU Clock to Q delay, (D-type Register Configuration) -- 0.342 -- 0.363 -- 0.383 ns tRSTREC_PFU Asynchronous reset recovery time for PFU Logic -- 0.520 -- 0.634 -- 0.748 ns tRST_PFU Asynchronous reset time for PFU Logic -- 0.720 -- 0.769 -- 0.818 ns PFU Dual Port Memory Mode Timing tCORAM_PFU Clock to Output (F Port) -- 1.082 -- 1.267 -- 1.452 ns tSUDATA_PFU Data Setup Time -0.206 -- -0.240 -- -0.274 -- ns tHDATA_PFU Data Hold Time 0.239 -- 0.275 -- 0.312 -- ns tSUADDR_PFU Address Setup Time -0.294 -- -0.333 -- -0.371 -- ns tHADDR_PFU Address Hold Time 0.295 -- 0.333 -- 0.371 -- ns tSUWREN_PFU Write/Read Enable Setup Time -0.146 -- -0.169 -- -0.193 -- ns tHWREN_PFU Write/Read Enable Hold Time 0.158 -- 0.182 -- 0.207 -- ns PIO Input/Output Buffer Timing tIN_PIO Input Buffer Delay (LVCMOS25) -- 0.858 -- 0.766 -- 0.674 ns tOUT_PIO Output Buffer Delay (LVCMOS25) -- 1.561 -- 1.403 -- 1.246 ns IOLOGIC Input/Output Timing tSUI_PIO Input Register Setup Time (Data Before Clock) 0.583 -- 0.893 -- 1.201 -- ns tHI_PIO Input Register Hold Time (Data after Clock) 0.062 -- 0.322 -- 0.482 -- ns tCOO_PIO Output Register Clock to Output Delay -- 0.608 -- 0.661 -- 0.715 ns tSUCE_PIO Input Register Clock Enable Setup Time 0.032 -- 0.037 -- 0.041 -- ns tHCE_PIO Input Register Clock Enable Hold Time -0.022 -- -0.025 -- -0.028 -- ns tSULSR_PIO Set/Reset Setup Time 0.184 -- 0.201 -- 0.217 -- ns tHLSR_PIO Set/Reset Hold Time -0.080 -- -0.086 -- -0.093 -- ns tRSTREC_PIO Asynchronous reset recovery time for IO Logic 0.228 -- 0.247 -- 0.266 -- ns 3-19 DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor LatticeXP2 Internal Switching Characteristics1 (Continued) Over Recommended Operating Conditions -7 Parameter -6 -5 Description Min. Max. Min. Max. Min. Max. Units tRST_PIO Asynchronous reset time for PFU Logic -- 0.386 -- 0.419 -- 0.452 ns tDEL Dynamic Delay Step Size 0.035 0.035 0.035 0.035 0.035 0.035 ns EBR Timing tCO_EBR Clock (Read) to Output from Address or Data -- 2.774 -- 3.142 -- 3.510 ns tCOO_EBR Clock (Write) to Output from EBR Output Register -- 0.360 -- 0.408 -- 0.456 ns tSUDATA_EBR Setup Data to EBR Memory (Write Clk) -0.167 -- -0.198 -- -0.229 -- ns tHDATA_EBR Hold Data to EBR Memory (Write Clk) 0.194 -- 0.231 -- 0.267 -- ns tSUADDR_EBR Setup Address to EBR Memory (Write Clk) -0.117 -- -0.137 -- -0.157 -- ns tHADDR_EBR Hold Address to EBR Memory (Write Clk) 0.157 -- 0.182 -- 0.207 -- ns tSUWREN_EBR Setup Write/Read Enable to EBR Memory (Write/Read Clk) -0.135 -- -0.159 -- -0.182 -- ns tHWREN_EBR Hold Write/Read Enable to EBR Memory (Write/Read Clk) 0.158 -- 0.186 -- 0.214 -- ns tSUCE_EBR Clock Enable Setup Time to EBR Output Register (Read Clk) 0.144 -- 0.160 -- 0.176 -- ns tHCE_EBR Clock Enable Hold Time to EBR Output Register (Read Clk) -0.097 -- -0.113 -- -0.129 -- ns tRSTO_EBR Reset To Output Delay Time from EBR Output Register (Asynchronous) -- 1.156 -- 1.341 -- 1.526 ns tSUBE_EBR Byte Enable Set-Up Time to EBR Output Register -0.117 -- -0.137 -- -0.157 -- ns tHBE_EBR Byte Enable Hold Time to EBR Output Register Dynamic Delay on Each PIO 0.157 -- 0.182 -- 0.207 -- ns tRSTREC_EBR Asynchronous reset recovery time for EBR 0.233 -- 0.291 -- 0.347 -- ns tRST_EBR Asynchronous reset time for EBR -- 1.156 -- 1.341 -- 1.526 ns PLL Parameters tRSTKREC_PLL After RSTK De-assert, Recovery Time Before Next Clock Edge Can Toggle K-divider Counter 1.000 -- 1.000 -- 1.000 -- ns tRSTREC_PLL After RST De-assert, Recovery Time Before Next Clock Edge Can Toggle M-divider Counter (Applies to M-Divider Portion of RST Only2) 1.000 -- 1.000 -- 1.000 -- ns DSP Block Timing tSUI_DSP Input Register Setup Time 0.135 -- 0.151 -- 0.166 -- ns tHI_DSP Input Register Hold Time 0.021 -- -0.006 -- -0.031 -- ns tSUP_DSP Pipeline Register Setup Time 2.505 -- 2.784 -- 3.064 -- ns 3-20 DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor LatticeXP2 Internal Switching Characteristics1 (Continued) Over Recommended Operating Conditions -7 Parameter Description -6 -5 Min. Max. Min. Max. Min. Max. Units tHP_DSP Pipeline Register Hold Time -0.787 -- -0.890 -- -0.994 -- ns tSUO_DSP Output Register Setup Time 4.896 -- 5.413 -- 5.931 -- ns tHO_DSP Output Register Hold Time -1.439 -- -1.604 -- -1.770 -- ns tCOI_DSP Input Register Clock to Output Time -- 4.513 -- 4.947 -- 5.382 ns tCOP_DSP3 Pipeline Register Clock to Output Time -- 2.153 -- 2.272 -- 2.391 ns tCOO_DSP3 Output Register Clock to Output Time -- 0.569 -- 0.600 -- 0.631 ns tSUADSUB AdSub Input Register Setup Time -0.270 -- -0.298 -- -0.327 -- ns tHADSUB AdSub Input Register Hold Time 0.306 -- 0.338 -- 0.371 -- ns 3 1. Internal parameters are characterized, but not tested on every device. 2. RST resets VCO and all counters in PLL. 3. These parameters include the Adder Subtractor block in the path. Timing v. A 0.12 3-21 DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor EBR Timing Diagrams Figure 3-6. Read/Write Mode (Normal) CLKA CSA WEA A0 ADA A1 A0 A1 A0 tSU tH DIA D0 D1 tCO_EBR DOA tCO_EBR D0 Invalid Data tCO_EBR D1 D0 Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock. Figure 3-7. Read/Write Mode with Input and Output Registers CLKA CSA WEA ADA A0 tSU DIA A1 A0 A1 A0 tH D0 D1 tCOO_EBR DOA (Regs) Mem(n) data from previous read output is only updated during a read cycle 3-22 tCOO_EBR D0 D1 DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor Figure 3-8. Write Through (SP Read/Write on Port A, Input Registers Only) CLKA CSA WEA Three consecutive writes to A0 ADA A0 tSU DIA A1 tH D0 D2 D1 tACCESS DOA A0 Data from Prev Read or Write tACCESS D0 D3 D4 tACCESS D1 tACCESS D2 D3 D4 Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock. 3-23 DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor LatticeXP2 Family Timing Adders1, 2, 3 Over Recommended Operating Conditions Buffer Type Description -7 -6 -5 Units Input Adjusters LVDS25 LVDS -0.26 -0.11 0.04 ns BLVDS25 BLVDS -0.26 -0.11 0.04 ns MLVDS LVDS -0.26 -0.11 0.04 ns RSDS RSDS -0.26 -0.11 0.04 ns LVPECL33 LVPECL -0.26 -0.11 0.04 ns HSTL18_I HSTL_18 class I -0.23 -0.08 0.07 ns HSTL18_II HSTL_18 class II -0.23 -0.08 0.07 ns HSTL18D_I Differential HSTL 18 class I -0.28 -0.13 0.02 ns HSTL18D_II Differential HSTL 18 class II -0.28 -0.13 0.02 ns HSTL15_I HSTL_15 class I -0.23 -0.09 0.06 ns HSTL15D_I Differential HSTL 15 class I -0.28 -0.13 0.01 ns SSTL33_I SSTL_3 class I -0.20 -0.04 0.12 ns SSTL33_II SSTL_3 class II -0.20 -0.04 0.12 ns SSTL33D_I Differential SSTL_3 class I -0.27 -0.11 0.04 ns SSTL33D_II Differential SSTL_3 class II -0.27 -0.11 0.04 ns SSTL25_I SSTL_2 class I -0.21 -0.06 0.10 ns SSTL25_II SSTL_2 class II -0.21 -0.06 0.10 ns SSTL25D_I Differential SSTL_2 class I -0.27 -0.12 0.03 ns SSTL25D_II Differential SSTL_2 class II -0.27 -0.12 0.03 ns SSTL18_I SSTL_18 class I -0.23 -0.08 0.07 ns SSTL18_II SSTL_18 class II -0.23 -0.08 0.07 ns SSTL18D_I Differential SSTL_18 class I -0.28 -0.13 0.02 ns SSTL18D_II Differential SSTL_18 class II -0.28 -0.13 0.02 ns LVTTL33 LVTTL -0.09 0.05 0.18 ns LVCMOS33 LVCMOS 3.3 -0.09 0.05 0.18 ns LVCMOS25 LVCMOS 2.5 0.00 0.00 0.00 ns LVCMOS18 LVCMOS 1.8 -0.23 -0.07 0.09 ns LVCMOS15 LVCMOS 1.5 -0.20 -0.02 0.16 ns LVCMOS12 LVCMOS 1.2 -0.35 -0.20 -0.04 ns PCI33 3.3V PCI -0.09 0.05 0.18 ns LVDS25E LVDS 2.5 E4 -0.25 0.02 0.30 ns LVDS25 LVDS 2.5 -0.25 0.02 0.30 ns Output Adjusters BLVDS25 BLVDS 2.5 -0.28 0.00 0.28 ns MLVDS MLVDS 2.54 -0.28 0.00 0.28 ns RSDS RSDS 2.54 -0.25 0.02 0.30 ns 4 LVPECL33 LVPECL 3.3 -0.37 -0.10 0.18 ns HSTL18_I HSTL_18 class I 8mA drive -0.17 0.13 0.43 ns HSTL18_II HSTL_18 class II -0.29 0.00 0.29 ns HSTL18D_I Differential HSTL 18 class I 8mA drive -0.17 0.13 0.43 ns HSTL18D_II Differential HSTL 18 class II -0.29 0.00 0.29 ns 3-24 DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor LatticeXP2 Family Timing Adders1, 2, 3 (Continued) Over Recommended Operating Conditions Buffer Type Description -7 -6 -5 Units HSTL15_I HSTL_15 class I 4mA drive 0.32 0.69 1.06 ns HSTL15D_I Differential HSTL 15 class I 4mA drive 0.32 0.69 1.06 ns SSTL33_I SSTL_3 class I -0.25 0.05 0.35 ns SSTL33_II SSTL_3 class II -0.31 -0.02 0.27 ns SSTL33D_I Differential SSTL_3 class I -0.25 0.05 0.35 ns SSTL33D_II Differential SSTL_3 class II -0.31 -0.02 0.27 ns SSTL25_I SSTL_2 class I 8mA drive -0.25 0.02 0.30 ns SSTL25_II SSTL_2 class II 16mA drive -0.28 0.00 0.28 ns SSTL25D_I Differential SSTL_2 class I 8mA drive -0.25 0.02 0.30 ns SSTL25D_II Differential SSTL_2 class II 16mA drive -0.28 0.00 0.28 ns SSTL18_I SSTL_1.8 class I -0.17 0.13 0.43 ns SSTL18_II SSTL_1.8 class II 8mA drive -0.18 0.12 0.42 ns SSTL18D_I Differential SSTL_1.8 class I -0.17 0.13 0.43 ns SSTL18D_II Differential SSTL_1.8 class II 8mA drive -0.18 0.12 0.42 ns LVTTL33_4mA LVTTL 4mA drive -0.37 -0.05 0.26 ns LVTTL33_8mA LVTTL 8mA drive -0.45 -0.18 0.10 ns LVTTL33_12mA LVTTL 12mA drive -0.52 -0.24 0.04 ns LVTTL33_16mA LVTTL 16mA drive -0.43 -0.14 0.14 ns LVTTL33_20mA LVTTL 20mA drive -0.46 -0.18 0.09 ns LVCMOS33_4mA LVCMOS 3.3 4mA drive, fast slew rate -0.37 -0.05 0.26 ns LVCMOS33_8mA LVCMOS 3.3 8mA drive, fast slew rate -0.45 -0.18 0.10 ns LVCMOS33_12mA LVCMOS 3.3 12mA drive, fast slew rate -0.52 -0.24 0.04 ns LVCMOS33_16mA LVCMOS 3.3 16mA drive, fast slew rate -0.43 -0.14 0.14 ns LVCMOS33_20mA LVCMOS 3.3 20mA drive, fast slew rate -0.46 -0.18 0.09 ns LVCMOS25_4mA LVCMOS 2.5 4mA drive, fast slew rate -0.42 -0.15 0.13 ns LVCMOS25_8mA LVCMOS 2.5 8mA drive, fast slew rate -0.48 -0.21 0.05 ns LVCMOS25_12mA LVCMOS 2.5 12mA drive, fast slew rate 0.00 0.00 0.00 ns LVCMOS25_16mA LVCMOS 2.5 16mA drive, fast slew rate -0.45 -0.18 0.08 ns LVCMOS25_20mA LVCMOS 2.5 20mA drive, fast slew rate -0.49 -0.22 0.04 ns LVCMOS18_4mA LVCMOS 1.8 4mA drive, fast slew rate -0.46 -0.18 0.10 ns LVCMOS18_8mA LVCMOS 1.8 8mA drive, fast slew rate -0.52 -0.25 0.02 ns LVCMOS18_12mA LVCMOS 1.8 12mA drive, fast slew rate -0.56 -0.30 -0.03 ns LVCMOS18_16mA LVCMOS 1.8 16mA drive, fast slew rate -0.50 -0.24 0.03 ns LVCMOS15_4mA LVCMOS 1.5 4mA drive, fast slew rate -0.45 -0.17 0.11 ns LVCMOS15_8mA LVCMOS 1.5 8mA drive, fast slew rate -0.53 -0.26 0.00 ns LVCMOS12_2mA LVCMOS 1.2 2mA drive, fast slew rate -0.46 -0.19 0.08 ns LVCMOS12_6mA LVCMOS 1.2 6mA drive, fast slew rate -0.55 -0.29 -0.02 ns LVCMOS33_4mA LVCMOS 3.3 4mA drive, slow slew rate 0.98 1.41 1.84 ns LVCMOS33_8mA LVCMOS 3.3 8mA drive, slow slew rate 0.74 1.16 1.58 ns LVCMOS33_12mA LVCMOS 3.3 12mA drive, slow slew rate 0.56 0.97 1.38 ns LVCMOS33_16mA LVCMOS 3.3 16mA drive, slow slew rate 0.77 1.19 1.61 ns LVCMOS33_20mA LVCMOS 3.3 20mA drive, slow slew rate 0.57 0.98 1.40 ns 3-25 DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor LatticeXP2 Family Timing Adders1, 2, 3 (Continued) Over Recommended Operating Conditions Buffer Type Description -7 -6 -5 Units LVCMOS25_4mA LVCMOS 2.5 4mA drive, slow slew rate 1.05 1.43 1.81 ns LVCMOS25_8mA LVCMOS 2.5 8mA drive, slow slew rate 0.78 1.15 1.52 ns LVCMOS25_12mA LVCMOS 2.5 12mA drive, slow slew rate 0.59 0.96 1.33 ns LVCMOS25_16mA LVCMOS 2.5 16mA drive, slow slew rate 0.81 1.18 1.55 ns LVCMOS25_20mA LVCMOS 2.5 20mA drive, slow slew rate 0.61 0.98 1.35 ns LVCMOS18_4mA LVCMOS 1.8 4mA drive, slow slew rate 1.01 1.38 1.75 ns LVCMOS18_8mA LVCMOS 1.8 8mA drive, slow slew rate 0.72 1.08 1.45 ns LVCMOS18_12mA LVCMOS 1.8 12mA drive, slow slew rate 0.53 0.90 1.26 ns LVCMOS18_16mA LVCMOS 1.8 16mA drive, slow slew rate 0.74 1.11 1.48 ns LVCMOS15_4mA LVCMOS 1.5 4mA drive, slow slew rate 0.96 1.33 1.71 ns LVCMOS15_8mA LVCMOS 1.5 8mA drive, slow slew rate -0.53 -0.26 0.00 ns LVCMOS12_2mA LVCMOS 1.2 2mA drive, slow slew rate 0.90 1.27 1.65 ns LVCMOS12_6mA LVCMOS 1.2 6mA drive, slow slew rate -0.55 -0.29 -0.02 ns PCI33 3.3V PCI -0.29 -0.01 0.26 ns 1. Timing Adders are characterized but not tested on every device. 2. LVCMOS timing measured with the load specified in Switching Test Condition table. 3. All other standards tested according to the appropriate specifications. 4. These timing adders are measured with the recommended resistor values. Timing v. A 0.12 3-26 DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor sysCLOCK PLL Timing Over Recommended Operating Conditions Min. Typ. Max. Units fIN Parameter Input Clock Frequency (CLKI, CLKFB) Description Conditions 10 -- 435 MHz fOUT Output Clock Frequency (CLKOP, CLKOS) 10 -- 435 MHz fOUT2 K-Divider Output Frequency 0.078 -- 217.5 MHz 3.3 -- 145 MHz fVCO PLL VCO Frequency 435 -- 870 MHz fPFD Phase Detector Input Frequency 10 -- 435 MHz 45 50 55 % -5 0 5 % CLKOK CLKOK2 AC Characteristics tDT Output Clock Duty Cycle tCPA Coarse Phase Adjust tPH4 Output Phase Accuracy Default duty cycle selected 3 fOUT > 400 MHz tOPJIT1 Output Clock Period Jitter -5 0 5 % -- -- 50 ps 100 MHz < fOUT < 400 MHz -- -- 125 ps fOUT < 100 MHz -- -- 0.025 UIPP tSK Input Clock to Output Clock Skew N/M = integer -- -- 240 ps tOPW Output Clock Pulse Width At 90% or 10% 1 -- -- ns tLOCK2 PLL Lock-in Time 25 to 435 MHz -- -- 50 s 10 to 25 MHz -- -- 100 s tIPJIT Input Clock Period Jitter -- -- 200 ps tFBKDLY External Feedback Delay -- -- 10 ns tHI Input Clock High Time 90% to 90% 0.5 -- -- ns tLO Input Clock Low Time 10% to 10% 0.5 -- -- ns tR / tF Input Clock Rise/Fall Time 10% to 90% -- -- 1 ns tRSTKW Reset Signal Pulse Width (RSTK) 10 -- -- ns tRSTW Reset Signal Pulse Width (RST) 500 -- -- ns 1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock. 2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment. 3. Using LVDS output buffers. 4. Relative to CLKOP. Timing v. A 0.12 3-27 DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor LatticeXP2 sysCONFIG Port Timing Specifications Over Recommended Operating Conditions Parameter Description Min Max Units -- 50 ms sysCONFIG POR, Initialization and Wake Up tICFG Minimum Vcc to INITN High tVMC Time from tICFG to valid Master CCLK -- 2 s tPRGMRJ PROGRAMN Pin Pulse Rejection -- 12 ns tPRGM PROGRAMN Low Time to Start Configuration 50 -- ns tDINIT1 PROGRAMN High to INITN High Delay -- 1 ms tDPPINIT Delay Time from PROGRAMN Low to INITN Low -- 50 ns tDPPDONE Delay Time from PROGRAMN Low to DONE Low -- 50 ns tIODISS User I/O Disable from PROGRAMN Low -- 35 ns tIOENSS User I/O Enabled Time from CCLK Edge During Wake-up Sequence -- 25 ns tMWC Additional Wake Master Clock Signals after DONE Pin High 0 -- Cycles sysCONFIG SPI Port (Master) tCFGX INITN High to CCLK Low -- 1 s tCSSPI INITN High to CSSPIN Low -- 2 s tCSCCLK CCLK Low before CSSPIN Low 0 -- ns tSOCDO CCLK Low to Output Valid -- 15 ns tCSPID CSSPIN[0:1] Low to First CCLK Edge Setup Time 2cyc 600+6cyc ns fMAXSPI Max CCLK Frequency -- 20 MHz tSUSPI SOSPI Data Setup Time Before CCLK 7 -- ns tHSPI SOSPI Data Hold Time After CCLK 10 -- ns 25 MHz mV/ns sysCONFIG SPI Port (Slave) fMAXSPIS Slave CCLK Frequency -- tRF Rise and Fall Time 50 -- tSTCO Falling Edge of CCLK to SOSPI Active -- 20 ns tSTOZ Falling Edge of CCLK to SOSPI Disable -- 20 ns tSTSU Data Setup Time (SISPI) 8 -- ns tSTH Data Hold Time (SISPI) 10 -- ns tSTCKH CCLK Clock Pulse Width, High 0.02 200 s tSTCKL CCLK Clock Pulse Width, Low 0.02 200 s tSTVO Falling Edge of CCLK to Valid SOSPI Output -- 20 ns tSCS CSSPISN High Time 25 -- ns tSCSS CSSPISN Setup Time 25 -- ns tSCSH CSSPISN Hold Time 25 -- ns 1. Re-toggling the PROGRAMN pin is not permitted until the INITN pin is high. Avoid consecutive toggling of PROGRAMN. 3-28 DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor On-Chip Oscillator and Configuration Master Clock Characteristics Over Recommended Operating Conditions Parameter Master Clock Frequency Duty Cycle Min. Max. Units Selected value -30% Selected value +30% MHz 40 60 % Timing v. A 0.12 Figure 3-9. Master SPI Configuration Waveforms Capture CR0 Capture CFGx VCC PROGRAMN DONE INITN CSSPIN 0 1 2 3 ... 7 8 9 10 ... 31 32 33 34 ... 127 128 CCLK SISPI Opcode Address Ignore SOSPI 3-29 Valid Bitstream DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor Flash Download Time (from On-Chip Flash to SRAM) Over Recommended Operating Conditions Symbol Parameter XP2-5 Min. Typ. Max. Units -- 1.8 2.1 ms XP2-8 PROGRAMN Low-toHigh. Transition to Done XP2-17 High. XP2-30 -- 1.9 2.3 ms -- 1.7 2.0 ms -- 2.0 2.1 ms XP2-40 -- 2.0 2.3 ms XP2-5 -- 1.8 2.1 ms XP2-8 -- 1.9 2.3 ms XP2-17 -- 1.7 2.0 ms XP2-30 -- 2.0 2.1 ms XP2-40 -- 2.0 2.3 ms tREFRESH Power-up refresh when PROGRAMN is pulled up to VCC (VCC=VCC Min) Flash Program Time Over Recommended Operating Conditions Program Time Device Flash Density XP2-5 1.2M XP2-8 2.0M XP2-17 3.6M XP2-30 6.0M XP2-40 8.0M Typ. Units TAG 1.0 ms Main Array 1.1 s TAG 1.0 ms Main Array 1.4 s TAG 1.0 ms Main Array 1.8 s TAG 2.0 ms Main Array 3.0 s TAG 2.0 ms Main Array 4.0 s Flash Erase Time Over Recommended Operating Conditions Erase Time Device Flash Density XP2-5 1.2M XP2-8 2.0M XP2-17 3.6M XP2-30 6.0M XP2-40 8.0M Typ. Units TAG 1.0 s Main Array 3.0 s TAG 1.0 s Main Array 4.0 s TAG 1.0 s Main Array 5.0 s TAG 2.0 s Main Array 7.0 s TAG 2.0 s Main Array 9.0 s 3-30 DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor FlashBAK Time (from EBR to Flash) Over Recommended Operating Conditions EBR Density (Bits) Time (Typ.) Units XP2-5 Device 166K 1.5 s XP2-8 221K 1.5 s XP2-17 276K 1.5 s XP2-30 387K 2.0 s XP2-40 885K 3.0 s JTAG Port Timing Specifications Over Recommended Operating Conditions Min. Max. Units fMAX Symbol TCK Clock Frequency Parameter -- 25 MHz tBTCP TCK [BSCAN] clock pulse width 40 -- ns tBTCPH TCK [BSCAN] clock pulse width high 20 -- ns tBTCPL TCK [BSCAN] clock pulse width low 20 -- ns tBTS TCK [BSCAN] setup time 8 -- ns tBTH TCK [BSCAN] hold time 10 -- ns tBTRF TCK [BSCAN] rise/fall time 50 -- mV/ns tBTCO TAP controller falling edge of clock to valid output -- 10 ns tBTCODIS TAP controller falling edge of clock to valid disable -- 10 ns tBTCOEN TAP controller falling edge of clock to valid enable -- 10 ns tBTCRS BSCAN test capture register setup time 8 -- ns tBTCRH BSCAN test capture register hold time 25 -- ns tBUTCO BSCAN test update register, falling edge of clock to valid output -- 25 ns tBTUODIS BSCAN test update register, falling edge of clock to valid disable -- 25 ns tBTUPOEN BSCAN test update register, falling edge of clock to valid enable -- 25 ns Timing v. A 0.12 3-31 DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor Figure 3-10. JTAG Port Timing Waveforms TMS TDI tBTS tBTCPH tBTH tBTCP tBTCPL TCK tBTCO tBTCOEN TDO Valid Data tBTCRS Data to be captured from I/O tBTCODIS Valid Data tBTCRH Data Captured tBTUPOEN tBUTCO Data to be driven out to I/O Valid Data 3-32 tBTUODIS Valid Data DC and Switching Characteristics LatticeXP2 Family Data Sheet Lattice Semiconductor Switching Test Conditions Figure 3-11 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 3-6. Figure 3-11. Output Test Load, LVTTL and LVCMOS Standards VT R1 DUT Test Poi nt R2 CL* *CL Includes Test Fixture and Probe Capacitance Table 3-6. Test Fixture Required Components, Non-Terminated Interfaces Test Condition LVTTL and other LVCMOS settings (L -> H, H -> L) R1 R2 LVCMOS 2.5 I/O (Z -> H) LVCMOS 2.5 I/O (Z -> L) 1M LVCMOS 2.5 I/O (H -> Z) LVCMOS 2.5 I/O (L -> Z) 100 CL 0pF 1M 100 Note: Output test conditions for all other interfaces are determined by the respective standards. 3-33 Timing Ref. VT LVCMOS 3.3 = 1.5V -- LVCMOS 2.5 = VCCIO/2 -- LVCMOS 1.8 = VCCIO/2 -- LVCMOS 1.5 = VCCIO/2 -- LVCMOS 1.2 = VCCIO/2 -- VCCIO/2 -- VCCIO/2 VCCIO VOH - 0.10 -- VOL + 0.10 VCCIO LatticeXP2 Family Data Sheet Pinout Information January 2012 Data Sheet DS1009 Signal Descriptions Signal Name I/O Description General Purpose [Edge] indicates the edge of the device on which the pad is located. Valid edge designations are L (Left), B (Bottom), R (Right), T (Top). [Row/Column Number] indicates the PFU row or the column of the device on which the PIC exists. When Edge is T (Top) or B (Bottom), only need to specify Row Number. When Edge is L (Left) or R (Right), only need to specify Column Number. P[Edge] [Row/Column Number*]_[A/B] I/O [A/B] indicates the PIO within the PIC to which the pad is connected. Some of these user-programmable pins are shared with special function pins. These pins, when not used as special purpose pins, can be programmed as I/Os for user logic. During configuration the user-programmable I/Os are tri-stated with an internal pull-up resistor enabled. If any pin is not used (or not bonded to a package pin), it is also tri-stated with an internal pull-up resistor enabled after configuration. GSRN I Global RESET signal (active low). Any I/O pin can be GSRN. NC -- No connect. GND -- Ground. Dedicated pins. VCC -- Power supply pins for core logic. Dedicated pins. VCCAUX -- Auxiliary power supply pin. This dedicated pin powers all the differential and referenced input buffers. VCCPLL -- PLL supply pins. csBGA, PQFP and TQFP packages only. VCCIOx -- Dedicated power supply pins for I/O bank x. VREF1_x, VREF2_x -- Reference supply pins for I/O bank x. Pre-determined pins in each bank are assigned as VREF inputs. When not used, they may be used as I/O pins. PLL and Clock Functions (Used as user programmable I/O pins when not in use for PLL or clock pins) [LOC][num]_VCCPLL -- Power supply pin for PLL: LLC, LRC, URC, ULC, num = row from center. [LOC][num]_GPLL[T, C]_IN_A I General Purpose PLL (GPLL) input pads: LLC, LRC, URC, ULC, num = row from center, T = true and C = complement, index A,B,C...at each side. [LOC][num]_GPLL[T, C]_FB_A I Optional feedback GPLL input pads: LLC, LRC, URC, ULC, num = row from center, T = true and C = complement, index A,B,C...at each side. PCLK[T, C]_[n:0]_[3:0] I Primary Clock pads, T = true and C = complement, n per side, indexed by bank and 0,1,2,3 within bank. [LOC]DQS[num] I DQS input pads: T (Top), R (Right), B (Bottom), L (Left), DQS, num = ball function number. Any pad can be configured to be output. TMS I Test Mode Select input, used to control the 1149.1 state machine. Pull-up is enabled during configuration. TCK I Test Clock input pin, used to clock the 1149.1 state machine. No pull-up enabled. I Test Data in pin. Used to load data into device using 1149.1 state machine. After power-up, this TAP port can be activated for configuration by sending appropriate command. (Note: once a configuration port is selected it is locked. Another configuration port cannot be selected until the power-up sequence). Pull-up is enabled during configuration. Test and Programming (Dedicated Pins) TDI (c) 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 4-1 Pinout Information_01.6 Pinout Information LatticeXP2 Family Data Sheet Lattice Semiconductor Signal Descriptions (Cont.) I/O Description TDO Signal Name O Output pin. Test Data Out pin used to shift data out of a device using 1149.1. VCCJ -- Power supply pin for JTAG Test Access Port. Configuration Pads (Used during sysCONFIG) CFG[1:0] INITN1 I Mode pins used to specify configuration mode values latched on rising edge of INITN. During configuration, an internal pull-up is enabled. I/O Open Drain pin. Indicates the FPGA is ready to be configured. During configuration, a pull-up is enabled. I Initiates configuration sequence when asserted low. This pin always has an active pull-up. DONE I/O Open Drain pin. Indicates that the configuration sequence is complete, and the startup sequence is in progress. CCLK I/O Configuration Clock for configuring an FPGA in sysCONFIG mode. I/O Input data pin in slave SPI mode and Output data pin in Master SPI mode. I/O Output data pin in slave SPI mode and Input data pin in Master SPI mode. CSSPIN O Chip select for external SPI Flash memory in Master SPI mode. This pin has a weak internal pull-up. CSSPISN I Chip select in Slave SPI mode. This pin has a weak internal pull-up. PROGRAMN SISPI 2 SOSPI2 2 Test Output Enable tristates all I/O pins when driven low. This pin has a weak internal pull-up, but when not used an external pull-up to VCC is recommended. 1. If not actively driven, the internal pull-up may not be sufficient. An external pull-up resistor of 4.7k to 10k is recommended. TOE I 2. When using the device in Master SPI mode, it must be mutually exclusive from JTAG operations (i.e. TCK tied to GND) or the JTAG TCK must be free-running when used in a system JTAG test environment. If Master SPI mode is used in conjunction with a JTAG download cable, the device power cycle is required after the cable is unplugged. 4-2 Pinout Information LatticeXP2 Family Data Sheet Lattice Semiconductor PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin PICs Associated with DQS Strobe PIO Within PIC DDR Strobe (DQS) and Data (DQ) Pins For Left and Right Edges of the Device P[Edge] [n-4] P[Edge] [n-3] P[Edge] [n-2] P[Edge] [n-1] P[Edge] [n] P[Edge] [n+1] P[Edge] [n+2] P[Edge] [n+3] A DQ B DQ A DQ B DQ A DQ B DQ A DQ B DQ A [Edge]DQSn B DQ A DQ B DQ A DQ B DQ A DQ B DQ For Top and Bottom Edges of the Device P[Edge] [n-4] P[Edge] [n-3] P[Edge] [n-2] P[Edge] [n-1] P[Edge] [n] P[Edge] [n+1] P[Edge] [n+2] P[Edge] [n+3] P[Edge] [n+4] A DQ B DQ A DQ B DQ A DQ B DQ A DQ B DQ A [Edge]DQSn B DQ A DQ B DQ A DQ B DQ A DQ B DQ A DQ B DQ Notes: 1. "n" is a row PIC number. 2. The DDR interface is designed for memories that support one DQS strobe up to 16 bits of data for the left and right edges and up to 18 bits of data for the top and bottom edges. In some packages, all the potential DDR data (DQ) pins may not be available. PIC numbering definitions are provided in the "Signal Names" column of the Signal Descriptions table. 4-3 Pinout Information LatticeXP2 Family Data Sheet Lattice Semiconductor Pin Information Summary XP2-5 Pin Type Single Ended User I/O Differential Pair User I/O Configuration Non Configuration XP2-8 XP2-17 XP2-30 XP2-40 132 144 208 256 132 144 208 256 208 256 484 256 484 672 484 672 csBGA TQFP PQFP ftBGA csBGA TQFP PQFP ftBGA PQFP ftBGA fpBGA ftBGA fpBGA fpBGA fpBGA fpBGA 86 100 146 172 86 100 146 201 146 201 358 201 363 472 363 540 35 39 57 66 35 39 57 77 57 77 135 77 137 180 137 204 Highspeed 8 11 16 20 8 11 16 23 16 23 44 23 44 56 44 66 TAP 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Muxed 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 Dedicated 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Muxed 5 5 7 7 7 7 9 9 11 11 21 7 11 13 11 13 Dedicated 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 6 4 9 6 6 4 9 6 9 6 16 6 16 20 16 20 8 Normal Vcc Vccaux 4 4 4 4 4 4 4 4 4 4 8 4 8 8 8 VCCPLL 2 2 2 - 2 2 2 - 4 - - - - - - - Bank0 2 2 2 2 2 2 2 2 2 2 4 2 4 4 4 4 Bank1 1 1 2 2 1 1 2 2 2 2 4 2 4 4 4 4 Bank2 2 2 2 2 2 2 2 2 2 2 4 2 4 4 4 4 Bank3 1 1 2 2 1 1 2 2 2 2 4 2 4 4 4 4 Bank4 1 1 2 2 1 1 2 2 2 2 4 2 4 4 4 4 Bank5 2 2 2 2 2 2 2 2 2 2 4 2 4 4 4 4 Bank6 1 1 2 2 1 1 2 2 2 2 4 2 4 4 4 4 Bank7 2 2 2 2 2 2 2 2 2 2 4 2 4 4 4 4 15 15 20 20 15 15 22 20 22 20 56 20 56 64 56 64 - 4 - 2 VCCIO GND, GND0-GND7 NC Bank0 18/9 20/10 20/10 31 - 26/13 18/9 20/10 20/10 2 - 2 7 2 2 69 2 1 28/14 20/10 28/14 52/26 28/14 52/26 70/35 52/26 70/35 Bank1 4/2 6/3 18/9 18/9 4/2 6/3 18/9 22/11 18/9 22/11 36/18 22/11 36/18 54/27 36/18 70/35 Bank2 16/8 18/9 18/9 22/11 16/8 18/9 18/9 26/13 18/9 26/13 46/23 26/13 46/23 56/28 46/23 64/32 Bank3 4/2 4/2 16/8 20/10 4/2 4/2 16/8 24/12 16/8 24/12 44/22 24/12 46/23 56/28 46/23 66/33 Bank4 8/4 8/4 18/9 18/9 8/4 8/4 18/9 26/13 18/9 26/13 36/18 26/13 38/19 54/27 38/19 70/35 Bank5 14/7 18/9 20/10 24/12 14/7 18/9 20/10 24/12 20/10 24/12 52/26 24/12 53/26 70/35 53/26 70/35 Bank6 6/3 8/4 18/9 22/11 6/3 8/4 18/9 27/13 18/9 27/13 46/23 27/13 46/23 56/28 46/23 66/33 Bank7 16/8 18/9 18/9 22/11 16/8 18/9 18/9 24/12 18/9 24/12 46/23 24/12 46/23 56/28 46/23 64/32 Bank0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bank1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bank2 3 4 4 5 3 4 4 6 4 6 11 6 11 14 11 16 True LVDS Pairs Bank3 Bonding Out per Bank4 Bank 1 1 4 5 1 1 4 6 4 6 11 6 11 14 11 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bank5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bank6 1 2 4 5 1 2 4 6 4 6 11 6 11 14 11 17 Bank7 3 4 4 5 3 4 4 5 4 5 11 5 11 14 11 16 Bank0 1 1 1 1 1 1 1 1 1 1 3 1 2 4 2 4 Bank1 0 0 1 1 0 0 1 1 1 1 2 1 2 3 2 4 Bank2 1 1 1 1 1 1 1 1 1 1 2 1 3 3 3 4 DDR Banks Bank3 Bonding Out per 1 Bank4 I/O Bank 0 0 1 1 0 0 1 1 1 1 2 1 3 3 3 4 0 0 1 1 0 0 1 1 1 1 2 1 2 3 2 4 Bank5 1 1 1 1 1 1 1 1 1 1 3 1 2 4 2 4 Bank6 0 0 1 1 0 0 1 1 1 1 2 1 3 3 3 4 Bank7 1 1 1 1 1 1 1 1 1 1 2 1 3 3 3 4 Single Ended/ Differential I/O per Bank 4-4 Pinout Information LatticeXP2 Family Data Sheet Lattice Semiconductor Pin Information Summary (Cont.) XP2-5 Pin Type XP2-8 XP2-17 XP2-30 XP2-40 132 144 208 256 132 144 208 256 208 256 484 256 484 672 484 672 csBGA TQFP PQFP ftBGA csBGA TQFP PQFP ftBGA PQFP ftBGA fpBGA ftBGA fpBGA fpBGA fpBGA fpBGA Bank0 18 20 20 26 18 20 20 28 20 28 52 28 52 70 52 70 Bank1 4 6 18 18 4 6 18 22 18 22 36 22 36 54 36 70 Bank2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCI capable I/Os Bank3 Bonding Out per Bank4 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 8 18 18 8 8 18 26 18 26 36 26 38 54 38 70 Bank5 14 18 20 24 14 18 20 24 20 24 52 24 53 70 53 70 Bank6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bank7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1 DQSB + 8 DQs + 1 DM + Bank VREF1). Logic Signal Connections Package pinout information can be found under "Data Sheets" on the LatticeXP2 product page of the Lattice website a www.latticesemi.com/products/fpga/xp2 and in the Lattice Diamond design software. Thermal Management Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal characteristics of a system, Lattice specifies a maximum allowable junction temperature in all device data sheets. Designers must complete a thermal analysis of their specific design to ensure that the device and package do not exceed the junction temperature limits. Refer to the Lattice Thermal Management document to find the device/ package specific thermal values. For Further Information * TN1139, Power Estimation and Management for LatticeXP2 Devices * Power Calculator tool is included with the Lattice Diamond design tool or as a standalone download from www.latticesemi.com/products/designsoftware 4-5 LatticeXP2 Family Data Sheet Ordering Information August 2008 Data Sheet DS1009 Part Number Description LFXP2 - XX E - X XXXXX X Device Family XP2 Grade C = Commercial I = Industrial Logic Capacity 5 = 5K LUTs 8 = 8K LUTs 17 = 17K LUTs 30 = 30K LUTs 40 = 40K LUTs Package M132 = 132-ball csBGA FT256 = 256-ball ftBGA F484 = 484-ball fpBGA F672 = 672-ball fpBGA Supply Voltage E = 1.2V MN132 = 132-ball Lead-Free csBGA TN144 = 144-pin Lead-Free TQFP QN208 = 208-pin Lead-Free PQFP FTN256 = 256-ball Lead-Free ftBGA FN484 = 484-ball Lead-Free fpBGA FN672 = 672-ball Lead-Free fpBGA Speed 5 = Slowest 6 7 = Fastest Ordering Information The LatticeXP2 devices are marked with a single temperature grade, either Commercial or Industrial, as shown below. XP2 XP2 LFXP2-17E 7FT256C LFXP2-17E 6FT256I Datecode Datecode (c) 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 5-1 Order Info_01.2 Ordering Information LatticeXP2 Family Data Sheet Lattice Semiconductor Lead-Free Packaging Commercial Part Number Voltage Grade Package Pins Temp. LUTs (k) LFXP2-5E-5MN132C 1.2V -5 Lead-Free csBGA 132 COM 5 LFXP2-5E-6MN132C 1.2V -6 Lead-Free csBGA 132 COM 5 LFXP2-5E-7MN132C 1.2V -7 Lead-Free csBGA 132 COM 5 LFXP2-5E-5TN144C 1.2V -5 Lead-Free TQFP 144 COM 5 LFXP2-5E-6TN144C 1.2V -6 Lead-Free TQFP 144 COM 5 LFXP2-5E-7TN144C 1.2V -7 Lead-Free TQFP 144 COM 5 LFXP2-5E-5QN208C 1.2V -5 Lead-Free PQFP 208 COM 5 LFXP2-5E-6QN208C 1.2V -6 Lead-Free PQFP 208 COM 5 LFXP2-5E-7QN208C 1.2V -7 Lead-Free PQFP 208 COM 5 LFXP2-5E-5FTN256C 1.2V -5 Lead-Free ftBGA 256 COM 5 LFXP2-5E-6FTN256C 1.2V -6 Lead-Free ftBGA 256 COM 5 LFXP2-5E-7FTN256C 1.2V -7 Lead-Free ftBGA 256 COM 5 Voltage Grade Package Pins Temp. LUTs (k) LFXP2-8E-5MN132C Part Number 1.2V -5 Lead-Free csBGA 132 COM 8 LFXP2-8E-6MN132C 1.2V -6 Lead-Free csBGA 132 COM 8 LFXP2-8E-7MN132C 1.2V -7 Lead-Free csBGA 132 COM 8 LFXP2-8E-5TN144C 1.2V -5 Lead-Free TQFP 144 COM 8 LFXP2-8E-6TN144C 1.2V -6 Lead-Free TQFP 144 COM 8 LFXP2-8E-7TN144C 1.2V -7 Lead-Free TQFP 144 COM 8 LFXP2-8E-5QN208C 1.2V -5 Lead-Free PQFP 208 COM 8 LFXP2-8E-6QN208C 1.2V -6 Lead-Free PQFP 208 COM 8 LFXP2-8E-7QN208C 1.2V -7 Lead-Free PQFP 208 COM 8 LFXP2-8E-5FTN256C 1.2V -5 Lead-Free ftBGA 256 COM 8 LFXP2-8E-6FTN256C 1.2V -6 Lead-Free ftBGA 256 COM 8 LFXP2-8E-7FTN256C 1.2V -7 Lead-Free ftBGA 256 COM 8 Voltage Grade Package Pins Temp. LUTs (k) LFXP2-17E-5QN208C 1.2V -5 Lead-Free PQFP 208 COM 17 LFXP2-17E-6QN208C 1.2V -6 Lead-Free PQFP 208 COM 17 Part Number LFXP2-17E-7QN208C 1.2V -7 Lead-Free PQFP 208 COM 17 LFXP2-17E-5FTN256C 1.2V -5 Lead-Free ftBGA 256 COM 17 LFXP2-17E-6FTN256C 1.2V -6 Lead-Free ftBGA 256 COM 17 LFXP2-17E-7FTN256C 1.2V -7 Lead-Free ftBGA 256 COM 17 LFXP2-17E-5FN484C 1.2V -5 Lead-Free fpBGA 484 COM 17 LFXP2-17E-6FN484C 1.2V -6 Lead-Free fpBGA 484 COM 17 LFXP2-17E-7FN484C 1.2V -7 Lead-Free fpBGA 484 COM 17 5-2 Ordering Information LatticeXP2 Family Data Sheet Lattice Semiconductor Voltage Grade Package Pins Temp. LUTs (k) LFXP2-30E-5FTN256C Part Number 1.2V -5 Lead-Free ftBGA 256 COM 30 LFXP2-30E-6FTN256C 1.2V -6 Lead-Free ftBGA 256 COM 30 LFXP2-30E-7FTN256C 1.2V -7 Lead-Free ftBGA 256 COM 30 LFXP2-30E-5FN484C 1.2V -5 Lead-Free fpBGA 484 COM 30 LFXP2-30E-6FN484C 1.2V -6 Lead-Free fpBGA 484 COM 30 LFXP2-30E-7FN484C 1.2V -7 Lead-Free fpBGA 484 COM 30 LFXP2-30E-5FN672C 1.2V -5 Lead-Free fpBGA 672 COM 30 LFXP2-30E-6FN672C 1.2V -6 Lead-Free fpBGA 672 COM 30 LFXP2-30E-7FN672C 1.2V -7 Lead-Free fpBGA 672 COM 30 Voltage Grade Package Pins Temp. LUTs (k) LFXP2-40E-5FN484C Part Number 1.2V -5 Lead-Free fpBGA 484 COM 40 LFXP2-40E-6FN484C 1.2V -6 Lead-Free fpBGA 484 COM 40 LFXP2-40E-7FN484C 1.2V -7 Lead-Free fpBGA 484 COM 40 LFXP2-40E-5FN672C 1.2V -5 Lead-Free fpBGA 672 COM 40 LFXP2-40E-6FN672C 1.2V -6 Lead-Free fpBGA 672 COM 40 LFXP2-40E-7FN672C 1.2V -7 Lead-Free fpBGA 672 COM 40 Industrial Voltage Grade Package Pins Temp. LUTs (k) LFXP2-5E-5MN132I Part Number 1.2V -5 Lead-Free csBGA 132 IND 5 LFXP2-5E-6MN132I 1.2V -6 Lead-Free csBGA 132 IND 5 LFXP2-5E-5TN144I 1.2V -5 Lead-Free TQFP 144 IND 5 LFXP2-5E-6TN144I 1.2V -6 Lead-Free TQFP 144 IND 5 LFXP2-5E-5QN208I 1.2V -5 Lead-Free PQFP 208 IND 5 LFXP2-5E-6QN208I 1.2V -6 Lead-Free PQFP 208 IND 5 LFXP2-5E-5FTN256I 1.2V -5 Lead-Free ftBGA 256 IND 5 LFXP2-5E-6FTN256I 1.2V -6 Lead-Free ftBGA 256 IND 5 Voltage Grade Package Pins Temp. LUTs (k) LFXP2-8E-5MN132I 1.2V -5 Lead-Free csBGA 132 IND 8 LFXP2-8E-6MN132I 1.2V -6 Lead-Free csBGA 132 IND 8 LFXP2-8E-5TN144I 1.2V -5 Lead-Free TQFP 144 IND 8 LFXP2-8E-6TN144I 1.2V -6 Lead-Free TQFP 144 IND 8 LFXP2-8E-5QN208I 1.2V -5 Lead-Free PQFP 208 IND 8 LFXP2-8E-6QN208I 1.2V -6 Lead-Free PQFP 208 IND 8 LFXP2-8E-5FTN256I 1.2V -5 Lead-Free ftBGA 256 IND 8 LFXP2-8E-6FTN256I 1.2V -6 Lead-Free ftBGA 256 IND 8 Part Number 5-3 Ordering Information LatticeXP2 Family Data Sheet Lattice Semiconductor Voltage Grade Package Pins Temp. LUTs (k) LFXP2-17E-5QN208I Part Number 1.2V -5 Lead-Free PQFP 208 IND 17 LFXP2-17E-6QN208I 1.2V -6 Lead-Free PQFP 208 IND 17 LFXP2-17E-5FTN256I 1.2V -5 Lead-Free ftBGA 256 IND 17 LFXP2-17E-6FTN256I 1.2V -6 Lead-Free ftBGA 256 IND 17 LFXP2-17E-5FN484I 1.2V -5 Lead-Free fpBGA 484 IND 17 LFXP2-17E-6FN484I 1.2V -6 Lead-Free fpBGA 484 IND 17 Voltage Grade Package Pins Temp. LUTs (k) LFXP2-30E-5FTN256I 1.2V -5 Lead-Free ftBGA 256 IND 30 LFXP2-30E-6FTN256I 1.2V -6 Lead-Free ftBGA 256 IND 30 LFXP2-30E-5FN484I 1.2V -5 Lead-Free fpBGA 484 IND 30 LFXP2-30E-6FN484I 1.2V -6 Lead-Free fpBGA 484 IND 30 LFXP2-30E-5FN672I 1.2V -5 Lead-Free fpBGA 672 IND 30 LFXP2-30E-6FN672I 1.2V -6 Lead-Free fpBGA 672 IND 30 Part Number Voltage Grade Package Pins Temp. LUTs (k) LFXP2-40E-5FN484I Part Number 1.2V -5 Lead-Free fpBGA 484 IND 40 LFXP2-40E-6FN484I 1.2V -6 Lead-Free fpBGA 484 IND 40 LFXP2-40E-5FN672I 1.2V -5 Lead-Free fpBGA 672 IND 40 LFXP2-40E-6FN672I 1.2V -6 Lead-Free fpBGA 672 IND 40 5-4 Ordering Information LatticeXP2 Family Data Sheet Lattice Semiconductor Conventional Packaging Commercial Part Number Voltage Grade Package Pins Temp. LUTs (k) LFXP2-5E-5M132C 1.2V -5 csBGA 132 COM 5 LFXP2-5E-6M132C 1.2V -6 csBGA 132 COM 5 LFXP2-5E-7M132C 1.2V -7 csBGA 132 COM 5 LFXP2-5E-5FT256C 1.2V -5 ftBGA 256 COM 5 LFXP2-5E-6FT256C 1.2V -6 ftBGA 256 COM 5 LFXP2-5E-7FT256C 1.2V -7 ftBGA 256 COM 5 Voltage Grade Package Pins Temp. LUTs (k) LFXP2-8E-5M132C Part Number 1.2V -5 csBGA 132 COM 8 LFXP2-8E-6M132C 1.2V -6 csBGA 132 COM 8 LFXP2-8E-7M132C 1.2V -7 csBGA 132 COM 8 LFXP2-8E-5FT256C 1.2V -5 ftBGA 256 COM 8 LFXP2-8E-6FT256C 1.2V -6 ftBGA 256 COM 8 LFXP2-8E-7FT256C 1.2V -7 ftBGA 256 COM 8 Voltage Grade Package Pins Temp. LUTs (k) LFXP2-17E-5FT256C 1.2V -5 ftBGA 256 COM 17 LFXP2-17E-6FT256C 1.2V -6 ftBGA 256 COM 17 LFXP2-17E-7FT256C 1.2V -7 ftBGA 256 COM 17 LFXP2-17E-5F484C 1.2V -5 fpBGA 484 COM 17 LFXP2-17E-6F484C 1.2V -6 fpBGA 484 COM 17 LFXP2-17E-7F484C 1.2V -7 fpBGA 484 COM 17 Part Number Voltage Grade Package Pins Temp. LUTs (k) LFXP2-30E-5FT256C Part Number 1.2V -5 ftBGA 256 COM 30 LFXP2-30E-6FT256C 1.2V -6 ftBGA 256 COM 30 LFXP2-30E-7FT256C 1.2V -7 ftBGA 256 COM 30 LFXP2-30E-5F484C 1.2V -5 fpBGA 484 COM 30 LFXP2-30E-6F484C 1.2V -6 fpBGA 484 COM 30 LFXP2-30E-7F484C 1.2V -7 fpBGA 484 COM 30 LFXP2-30E-5F672C 1.2V -5 fpBGA 672 COM 30 LFXP2-30E-6F672C 1.2V -6 fpBGA 672 COM 30 LFXP2-30E-7F672C 1.2V -7 fpBGA 672 COM 30 5-5 Ordering Information LatticeXP2 Family Data Sheet Lattice Semiconductor Voltage Grade Package Pins Temp. LUTs (k) LFXP2-40E-5F484C Part Number 1.2V -5 fpBGA 484 COM 40 LFXP2-40E-6F484C 1.2V -6 fpBGA 484 COM 40 LFXP2-40E-7F484C 1.2V -7 fpBGA 484 COM 40 LFXP2-40E-5F672C 1.2V -5 fpBGA 672 COM 40 LFXP2-40E-6F672C 1.2V -6 fpBGA 672 COM 40 LFXP2-40E-7F672C 1.2V -7 fpBGA 672 COM 40 Industrial Part Number LFXP2-5E-5M132I Voltage Grade Package Pins Temp. LUTs (k) 1.2V -5 csBGA 132 IND 5 LFXP2-5E-6M132I 1.2V -6 csBGA 132 IND 5 LFXP2-5E-6FT256I 1.2V -6 ftBGA 256 IND 5 Voltage Grade Package Pins Temp. LUTs (k) 1.2V -5 csBGA 132 IND 8 Part Number LFXP2-8E-5M132I LFXP2-8E-6M132I 1.2V -6 csBGA 132 IND 8 LFXP2-5E-5FT256I 1.2V -5 ftBGA 256 IND 5 LFXP2-8E-5FT256I 1.2V -5 ftBGA 256 IND 8 LFXP2-8E-6FT256I 1.2V -6 ftBGA 256 IND 8 Voltage Grade Package Pins Temp. LUTs (k) LFXP2-17E-5FT256I Part Number 1.2V -5 ftBGA 256 IND 17 LFXP2-17E-6FT256I 1.2V -6 ftBGA 256 IND 17 LFXP2-17E-5F484I 1.2V -5 fpBGA 484 IND 17 LFXP2-17E-6F484I 1.2V -6 fpBGA 484 IND 17 Voltage Grade Package Pins Temp. LUTs (k) LFXP2-30E-5FT256I 1.2V -5 ftBGA 256 IND 30 LFXP2-30E-6FT256I 1.2V -6 ftBGA 256 IND 30 LFXP2-30E-5F484I 1.2V -5 fpBGA 484 IND 30 LFXP2-30E-6F484I 1.2V -6 fpBGA 484 IND 30 LFXP2-30E-5F672I 1.2V -5 fpBGA 672 IND 30 LFXP2-30E-6F672I 1.2V -6 fpBGA 672 IND 30 Part Number 5-6 Ordering Information LatticeXP2 Family Data Sheet Lattice Semiconductor Voltage Grade Package Pins Temp. LUTs (k) LFXP2-40E-5F484I Part Number 1.2V -5 fpBGA 484 IND 40 LFXP2-40E-6F484I 1.2V -6 fpBGA 484 IND 40 LFXP2-40E-5F672I 1.2V -5 fpBGA 672 IND 40 LFXP2-40E-6F672I 1.2V -6 fpBGA 672 IND 40 5-7 LatticeXP2 Family Data Sheet Supplemental Information May 2007 Data Sheet DS1009 For Further Information A variety of technical notes for the LatticeXP2 FPGA family are available on the Lattice Semiconductor web site at www.latticesemi.com. * TN1136, LatticeXP2 sysIO Usage Guide * TN1137, LatticeXP2 Memory Usage Guide * TN1138, LatticeXP2 High Speed I/O Interface * TN1126, LatticeXP2 sysCLOCK PLL Design and Usage Guide * TN1139, Power Estimation and Management for LatticeXP2 Devices * TN1140, LatticeXP2 sysDSP Usage Guide * TN1141, LatticeXP2 sysCONFIG Usage Guide * TN1142, LatticeXP2 Configuration Encryption and Security Usage Guide * TN1087, Minimizing System Interruption During Configuration Using TransFR Technology * TN1220, LatticeXP2 Dual Boot Feature * TN1130, LatticeXP2 Soft Error Detection (SED) Usage Guide * TN1143, LatticeXP2 Hardware Checklist For further information on interface standards refer to the following websites: * JEDEC Standards (LVTTL, LVCMOS, SSTL, HSTL): www.jedec.org * PCI: www.pcisig.com (c) 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 6-1 Further Info_01.1 LatticeXP2 Family Data Sheet Revision History January 2012 Data Sheet DS1009 Revision History Date Version Section May 2007 01.1 -- September 2007 01.2 DC and Switching Characteristics Change Summary Initial release. Added JTAG Port Timing Waveforms diagram. Updated sysCLOCK PLL Timing table. Pinout Information February 2008 01.3 Architecture Added Thermal Management text section. Added LVCMOS33D to Supported Output Standards table. Clarified: "This Flash can be programmed through either the JTAG or Slave SPI ports of the device. The SRAM configuration space can also be infinitely reconfigured through the JTAG and Master SPI ports." Added External Slave SPI Port to Serial TAG Memory section. Updated Serial TAG Memory diagram. DC and Switching Characteristics Updated Flash Programming Specifications table. Added "8W" specification to Hot Socketing Specifications table. Updated Timing Tables Clarifications for IIH in DC Electrical Characteristics table. Added LVCMOS33D section Updated DOA and DOA (Regs) to EBR Timing diagrams. Removed Master Clock Frequency and Duty Cycle sections from the LatticeXP2 sysCONFIG Port Timing Specifications table. These are listed on the On-chip Oscillator and Configuration Master Clock Characteristics table. Changed CSSPIN to CSSPISN in description of tSCS, tSCSS, and tSCSH parameters. Removed tSOE parameter. Clarified On-chip Oscillator documentation Added Switching Test Conditions Pinout Information Added "True LVDS Pairs Bonding Out per Bank," "DDR Banks Bonding Out per I/O Bank," and "PCI capable I/Os Bonding Out per Bank" to Pin Information Summary in place of previous blank table "PCI and DDR Capabilities of the Device-Package Combinations" Removed pinout listing. This information is available on the LatticeXP2 product web pages April 2008 01.4 Ordering Information Added XP2-17 "8W" and all other family OPNs. DC and Switching Characteristics Updated Absolute Maximum Ratings footnotes. Updated Recommended Operating Conditions Table footnotes. Updated Supply Current (Standby) Table Updated Initialization Supply Current Table Updated Programming and Erase Flash Supply Current Table Updated Register to Register Performance Table Updated LatticeXP2 External Switching Characteristics Table Updated LatticeXP2 Internal Switching Characteristics Table Updated sysCLOCK PLL Timing Table (c) 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 7-1 Revision History LatticeXP2 Family Data Sheet Lattice Semiconductor Date Version April 2008 (cont.) 01.4 (cont.) Section Change Summary DC and Switching Updated Flash Download Time (From On-Chip Flash to SRAM) Table Characteristics (cont.) Updated Flash Program Time Table Updated Flash Erase Time Table Updated FlashBAK (from EBR to Flash) Table Updated Hot Socketing Specifications Table footnotes Pinout Information June 2008 01.5 Architecture Updated Signal Descriptions Table Removed Read-Before-Write sysMEM EBR mode. Clarification of the operation of the secondary clock regions. August 2008 01.6 DC and Switching Characteristics Removed Read-Before-Write sysMEM EBR mode. Pinout Information Updated DDR Banks Bonding Out per I/O Bank section of Pin Information Summary Table. -- Architecture DC and Switching Characteristics Data sheet status changed from preliminary to final. Clarification of the operation of the secondary clock regions. Removed "8W" specification from Hot Socketing Specifications table. Removed "8W" footnote from DC Electrical Characteristics table. Updated Register-to-Register Performance table. Ordering Information Removed "8W" option from Part Number Description. Removed XP2-17 "8W" OPNs. April 2011 01.7 DC and Switching Characteristics Recommended Operating Conditions table, added footnote 5. On-Chip Flash Memory Specifications table, added footnote 1. BLVDS DC Conditions, corrected column title to be Z0 = 90 ohms. sysCONFIG Port Timing Specifications table, added footnote 1 for tDINIT. January 2012 01.8 Multiple Architecture DC and Switching Characteristics Added support for Lattice Diamond design software. Corrected information regarding SED support. Added reference to ESD Performance Qualification Summary information. 7-2 Section II. LatticeXP2 Family Technical Notes LatticeXP2 sysIO Usage Guide June 2010 Technical Note TN1136 Introduction The LatticeXP2TM sysIOTM buffers give the designer the ability to easily interface with other devices using advanced system I/O standards. This technical note describes the sysIO standards available and how they can be implemented using Lattice's ispLEVER(R) design software. sysIO Buffer Overview The LatticeXP2 sysIO interface contains multiple Programmable I/O Cells (PIC) blocks. Each PIC contains two Programmable I/Os (PIO), PIOA and PIOB, connected to their respective sysIO Buffers. Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as "T" and "C"). Each Programmable I/O (PIO) includes a sysIO Buffer and I/O Logic (IOLOGIC). The LatticeXP2 sysIO buffers supports a variety of single-ended and differential signaling standards. The sysIO buffer also supports the DQS strobe signal that is required for interfacing with the DDR memory. One of every 16/18 PIOs in the LatticeXP2 contains a delay element to facilitate the generation of DQS signals. The DQS signal from the bus is used to strobe the DDR data from the memory into input register blocks. For more information on the architecture of the sysIO buffer please refer to the LatticeXP2 Family Data Sheet. The IOLOGIC includes input, output and tristate registers that implement both single data rate (SDR) and double data rate (DDR) applications along with the necessary clock and data selection logic. Programmable delay lines and dedicated logic within the IOLOGIC are used to provide the required shift to incoming clock and data signals and the delay required by DQS inputs in DDR memory. The DDR implementation in the IOLOGIC and the DDR memory interface support are discussed in more detail in TN1138, LatticeXP2 High Speed I/O Interface. Supported sysIO Standards The LatticeXP2 sysIO buffer supports both single-ended and differential standards. Single-ended standards can be further subdivided into internally ratioed standard such as LVCMOS, LVTTL and PCI; and externally referenced standards such as HSTL and SSTL. The buffers support the LVTTL, LVCMOS 1.2, 1.5, 1.8, 2.5 and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch). Other single-ended standards supported include SSTL and HSTL. Differential standards supported include MLVDS, LVDS, RSDS, BLVDS, LVPECL, differential SSTL and differential HSTL. Tables 1 and 2 list the sysIO standards supported in LatticeXP2 devices. Table 8-1. Supported Input Standards VREF (Nom.) VCCIO1 (Nom.) LVTTL -- -- LVCMOS33 -- -- LVCMOS25 -- -- LVCMOS18 -- 1.8 LVCMOS15 -- 1.5 LVCMOS12 -- -- PCI 33 -- 3.3 HSTL18 Class I, II 0.9 -- HSTL15 Class I 0.75 -- SSTL3 Class I, II 1.5 -- Input Standard Single Ended Interfaces (c) 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 8-1 tn1136_01.3 Lattice Semiconductor LatticeXP2 sysIO Usage Guide Table 8-1. Supported Input Standards (Continued) VREF (Nom.) VCCIO1 (Nom.) SSTL2 Class I, II 1.25 -- SSTL18 Class I, II 0.9 -- Input Standard Differential Interfaces Differential SSTL18 Class I, II -- -- Differential SSTL2 Class I, II -- -- Differential SSTL3 Class I, II -- -- Differential HSTL15 Class I -- -- Differential HSTL18 Class I, II -- -- LVDS, MLVDS, LVPECL, BLVDS, RSDS -- -- 1 When not specified, VCCIO can be set anywhere in the valid operating range. Table 8-2. Supported Output Standards Output Standard Drive VCCIO (Nom.) LVTTL 4mA, 8mA, 12mA, 16mA, 20mA 3.3 LVTTL, Open Drain 4mA, 8mA, 12mA, 16mA, 20mA -- LVCMOS33 4mA, 8mA, 12mA 16mA, 20mA 3.3 LVCMOS25 4mA, 8mA, 12mA, 16mA, 20mA 2.5 LVCMOS18 4mA, 8mA, 12mA, 16mA 1.8 LVCMOS15 4mA, 8mA 1.5 Single-ended Interfaces LVCMOS12 2mA, 6mA 1.2 LVCMOS33, Open Drain 4mA, 8mA, 12mA 16mA, 20mA -- LVCMOS25, Open Drain 4mA, 8mA, 12mA 16mA, 20mA -- LVCMOS18, Open Drain 4mA, 8mA, 12mA 16mA -- LVCMOS15, Open Drain 4mA, 8mA -- LVCMOS12, Open Drain 2mA, 6mA -- 2 PCI33 HSTL18 Class I N/A 3.3 8mA, 12mA 1.8 HSTL18 Class II N/A 1.8 HSTL15 Class I 4mA, 8mA 1.5 SSTL3 Class I, II N/A 3.3 SSTL2 Class I 8mA, 12mA 2.5 SSTL2 Class II 16mA, 20mA 2.5 SSTL18 Class I N/A 1.8 SSTL18 Class II 8mA, 12mA 1.8 Differential Interfaces Differential SSTL3, Class I, II N/A 3.3 Differential SSTL2, Class I 8mA, 12mA 2.5 Differential SSTL2, Class II 16mA, 20mA 2.5 Differential SSTL18, Class I N/A 1.8 Differential SSTL18, Class II 8mA, 12mA 1.8 Differential HSTL18, Class I 8mA, 12mA 1.8 Differential HSTL18, Class II N/A 1.8 Differential HSTL15, Class I 4mA, 8mA 1.5 8-2 Lattice Semiconductor LatticeXP2 sysIO Usage Guide Table 8-2. Supported Output Standards (Continued) Output Standard LVDS Drive VCCIO (Nom.) N/A 2.5 1 MLVDS N/A 2.5 BLVDS1 N/A 2.5 LVPECL1 N/A 3.3 RSDS1 N/A 2.5 1. Emulated with external resistors. 2. PCI33 is PCIX compatible. sysIO Banking Scheme LatticeXP2 devices have eight general purpose programmable sysIO banks. Each of the eight general purpose sysIO banks has a VCCIO supply voltage, and two reference voltages, VREF1 and VREF2. Figure 8-1 shows the eight general purpose banks. On the top and bottom banks, the sysIO buffer pair consists of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). The left and right sysIO buffer pair consists of two singleended output drivers and two sets of single-ended input buffers (both ratioed and referenced). The referenced input buffer can also be configured as a differential input. True LVDS support is available on only 50% of the left and right I/Os (starting with the topmost pairs). There are no LVDS on the top and bottom I/Os. In 50% of the pairs there is also one differential output driver. The two pads in the pair are described as "true" and "comp", where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer. SPI Flash Interface The SPI pins (master/slave) are multiplexed with the I/Os in Bank 7. The two dedicated pins CFG[0] and TOE are powered by VCC and reside between Banks 6 and 7. JTAG Interface The JTAG pins are located between Banks 2 and 3 and are powered by VCCJ. Figure 8-1. LatticeXP2 sysIO Banking Bank 0 Bank 1 Bank 7 Bank 2 Bank 6 Bank 3 Bank 5 Bank 4 8-3 Lattice Semiconductor LatticeXP2 sysIO Usage Guide VCCIO (1.2V/1.5V/1.8V/2.5V/3.3V) There are a total of eight VCCIO supplies, VCCIO0 - VCCIO7. Each bank has a separate VCCIO supply that powers the single-ended output drivers and the ratioed input buffers such as LVTTL, LVCMOS, and PCI. LVTTL, LVCMOS3.3, LVCMOS2.5 and LVCMOS1.2 also have fixed threshold options allowing them to be placed in any bank. The VCCIO voltage applied to the bank determines the ratioed input standards that can be supported in that bank. It is also used to power the differential output drivers. VCCAUX (3.3V) In addition to the bank VCCIO supplies, devices have a VCC core logic power supply and a VCCAUX auxiliary supply that powers the differential and referenced input buffers. VCCAUX is used to supply I/O reference voltage requiring 3.3V to satisfy the common-mode range of the drivers and input buffers. VCCJ (1.2V/1.5V/1.8V/2.5V/3.3V) The JTAG pins have a separate VCCJ power supply that is independent of the bank VCCIO supplies. VCCJ determines the electrical characteristics of the LVCMOS JTAG pins, both the output high level and the input threshold. Table 8-3 shows a summary of all the required power supplies. Table 8-3. Power Supplies Power Supply VCC Value1 Description Core Power Supply 2 1.2V VCCIO Power Supply for the I/O Banks 1.2V/1.5V/1.8V/2.5V/3.3V VCCAUX Auxiliary Power Supply 3.3V VCCJ2 Power Supply for JTAG Pins 1.2V/1.5V/1.8V/2.5V/3.3V 1. Refer to the LatticeXP2 Family Data Sheet for recommended min. and max. values. 2. If VCCIO or VCCJ is set to 3.3V, they MUST be connected to the same power supply as VCCAUX. Input Reference Voltage (VREF1, VREF2) Each bank can support up to two separate VREF input voltages, VREF1 and VREF2, that are used to set the threshold for the referenced input buffers. The locations of these VREF pins are pre-determined within the bank. These pins can be used as regular I/Os if the bank does not require a VREF voltage. VREF1 for DDR Memory Interface When interfacing to DDR memory, the VREF1 input must be used as the reference voltage for the DQS and DQ input from the memory. A voltage divider between VREF1 and GND is used to generate an on-chip reference voltage that is used by the DQS transition detector circuit. This voltage divider is only present on VREF1 it is not available on VREF2. For more information on the DQS transition detect logic and its implementation, please refer to Lattice technical note number TN1138, LatticeXP2 High Speed I/O Interface. For DDR1 memory interfaces, the VREF1 should be connected to 1.25V. Therefore, only SSTL25_II signaling is allowed. For DDR2 memory interfaces this should be connected to 0.9V, and only SSTL18_II signaling is allowed. Mixed Voltage Support in a Bank The LatticeXP2 sysIO buffer is connected to three parallel ratioed input buffers. These three parallel buffers are connected to VCCIO, VCCAUX and VCC, giving support for thresholds that track with VCCIO as well as fixed thresholds for 3.3V (VCCAUX) and 1.2V (VCC) inputs. This allows the input threshold for ratioed buffers to be assigned on a pin-by-pin basis rather than tracking with VCCIO. This option is available for all 1.2V, 2.5V and 3.3V ratioed inputs and is independent of the bank VCCIO voltage. For example, if the bank VCCIO is 1.8V, it is possible to have 1.2V and 3.3V ratioed input buffers with fixed thresholds, as well as 2.5V ratioed inputs with tracking thresholds. 8-4 Lattice Semiconductor LatticeXP2 sysIO Usage Guide Prior to device configuration, the ratioed input thresholds always tracks the bank VCCIO. This option only takes effect after configuration. Output standards within a bank are always set by VCCIO. Table 8-4 shows the sysIO standards that can be mixed in the same bank. Table 8-4. Mixed Voltage Support Input sysIO Standards VCCIO 1.2V 1.2V Yes 1.5V Yes 1.8V Yes 2.5V Yes 3.3V Yes 1.5V 1.8V Yes Yes Output sysIO Standards 2.5V 3.3V 1.2V Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 1.5V 1.8V 2.5V 3.3V Yes Yes Yes Yes sysIO Standards Supported by Bank Table 8-5. I/O Standards Supported by Bank Description Top Side Banks 0-1 Right Side Banks 2-3 Bottom Side Banks 4-5 Left Side Banks 6-7 I/O Buffers Single-ended Single-ended and Differential Single-ended Single-ended and Differential Output Standards Supported LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 SSTL18 Class I, II SSTL25 Class I, II SSTL33 Class I, II SSTL18 Class I, II SSTL25 Class I, II SSTL33 Class I, II SSTL18 Class I, II SSTL2 Class I, II SSTL3 Class I, II SSTL18 Class I SSTL2 Class I, II SSTL3 Class I, II HSTL15 Class I HSTL18_I, II HSTL15 Class I HSTL18 Class I, II HSTL15 Class I HSTL18 Class I, II HSTL15 Class I, III HSTL18 Class I, II, III SSTL18D Class I, II SSTL25D Class I, II SSTL33D Class I, II SSTL18D Class I, II SSTL25D Class I, II SSTL33D Class I, II SSTL18D Class I, II SSTL25D Class I, II, SSTL33D Class I, II SSTL18D Class I, SSTL25D Class I, II, SSTL33D_I, II HSTL15D Class I HSTL18D Class I, II HSTL15D Class I HSTL18D Class I, II HSTL15D Class I HSTL18D Class I, II HSTL15D Class I HSTL18D Class I, II MLVDS LVDS25E1 LVPECL1 BLVDS1 RSDS1 MLVDS LVDS LVDS25E1 LVPECL1 BLVDS1 RSDS1 MLVDS LVDS25E1 LVPECL1 BLVDS1 RSDS1 MLVDS LVDS LVDS25E1 LVPECL1 BLVDS1 RSDS1 Inputs All Single-ended, Differential All Single-ended, Differential All Single-ended, Differential All Single-ended, Differential Clock Inputs All Single-ended, Differential All Single-ended, Differential All Single-ended, Differential All Single-ended, Differential PCI Support PCI33 with clamp PCI33 without clamp PCI33 with clamp PCI33 without clamp LVDS Output Buffers LVDS (3.5mA) Buffers2 LVDS (3.5mA) Buffers2 1. These differential standards are implemented by using a complementary LVCMOS driver with external resistor pack. 2. Available only on 50% of the I/Os in the bank. 8-5 Lattice Semiconductor LatticeXP2 sysIO Usage Guide LVCMOS Buffer Configurations All LVCMOS buffer have programmable pull, programmable drive and programmable slew configurations that can be set in the software. Bus Maintenance Circuit Each pad has a weak pull-up, weak pull-down and weak buskeeper capability. The pull-up and pull-down settings offer a fixed characteristic, which is useful in creating wired logic such as wired ORs. However, current can be slightly higher than other options, depending on the signal state. The bus-keeper option latches the signal in the last driven state, holding it at a valid level with minimal power dissipation. Users can also choose to turn off the bus maintenance circuitry, minimizing power dissipation and input leakage. Note that in this case, it is important to ensure that inputs are driven to a known state to avoid unnecessary power dissipation in the input buffer. The internal weak pull-up is enabled on all unused pins. Programmable Drive Each LVCMOS or LVTTL, as well as some of the referenced (SSTL and HSTL) output buffers, has a programmable drive strength option. This option can be set for each I/O independently. The drive strength settings available are 2mA, 4mA, 6mA, 8mA, 12mA, 16mA and 20mA. Actual options available vary by the I/O voltage. The user must consider the maximum allowable current per bank and the package thermal limit current when selecting the drive strength. Table 8-6 shows the available drive settings for each of the output standards. Table 8-6. Programmable Drive Values for Single-ended Buffers Single Ended I/O Standard Programmable Drive (mA) HSTL15_I 4, 8 HSTL18_I 8, 12 SSTL25_I 8, 12 SSTL25_II 16, 20 SSTL18_II 8, 12 LVCMOS12 2, 6 LVCMOS15 4, 8 LVCMOS18 4, 8, 12, 16 LVCMOS25 4, 8, 12, 16, 20 LVCMOS33 4, 8, 12, 16, 20 LVTTL 4, 8, 12, 16, 20 Programmable Slew Rate Each LVCMOS or LVTTL output buffer pin also has a programmable output slew rate control that can be configured for either low noise or high-speed performance. Each I/O pin has an individual slew rate control. This allows designers to specify slew rate control on a pin-by-pin basis. This slew rate control affects both the rising and falling edges. Open-Drain Control All LVCMOS and LVTTL output buffers can be configured to function as open drain outputs. The user can implement an open drain output by turning on the OPENDRAIN attribute in the software. Differential SSTL and HSTL support The single-ended driver associated with the complementary `C' pad can optionally be driven by the complement of the data that drives the single-ended driver associated with the true pad. This allows a pair of single-ended drivers to be used to drive complementary outputs with the lowest possible skew between the signals. This is used for driving complementary SSTL and HSTL signals (as required by the differential SSTL and HSTL clock inputs on syn- 8-6 Lattice Semiconductor LatticeXP2 sysIO Usage Guide chronous DRAM and synchronous SRAM devices respectively). This capability is also used in conjunction with offchip resistors to emulate LVPECL, and BLVDS output drivers. Table 8-7. Programmable Drive Values for Differential Buffers Differential I/O Standard Programmable Drive (mA) HSTL15D_I 4, 8 HSTL18D_I 8, 12 SSTL25D_I 8, 12 SSTL25D_II 16, 20 SSTL18D_II 8, 12 PCI Support with Programmable PCICLAMP Each sysIO buffer can be configured to support PCI33. The buffers on the top and bottom sides of the device have an optional PCI clamp diode that may optionally be specified in the ispLEVER design tools. Programmable PCICLAMP can be turned ON or OFF. This option is available on each I/O independently on the top and bottom side banks. Programmable Input Delay Each input can optionally be delayed before it is passed to the core logic or input registers. The primary use for the input delay is to achieve zero hold time for the input registers when using a direct drive primary clock. To arrive at zero hold time, the input delay will delay the data by at least as much as the primary clock injection delay. This option can be turned ON or OFF for each I/O independently in the software using the FIXEDDELAY attribute. This attribute is described in more detail in the software sysIO attribute section. Appendix A shows how this feature can be enabled in the software using HDL attributes. Software sysIO Attributes sysIO attributes can be specified in the HDL, using the Spreadsheet View of the Design Planner or in the ASCII preference file (.lpf) file directly. Appendices A, B and C list examples of how these can be assigned using each of these methods. This section describes each of these attributes in detail. IO_TYPE This is used to set the sysIO standard for an I/O. The VCCIO required to set these I/O standards are embedded in the attribute names itself. There is no separate attribute to set the VCCIO requirements. Table 8-8 lists the available I/O types. 8-7 Lattice Semiconductor LatticeXP2 sysIO Usage Guide Table 8-8. IO_TYPE Attribute Values sysIO Signaling Standard IO_TYPE DEFAULT LVCMOS25 LVDS 2.5V LVDS25 RSDS RSDS1 Emulated LVDS 2.5V LVDS25E1 Bus LVDS 2.5V BLVDS251 LVPECL 3.3V LVPECL331 HSTL18 Class I and II HSTL18_I, HTSL18_II Differential HSTL 18 Class I and II HSTL18D_I, HSTL18D_II HSTL 15 Class I HSTL15_I Differential HSTL 15 Class I HSTL15D_I SSTL 33 Class I and II SSTL33_I, SSTL33_II Differential SSTL 33 Class I and II SSTL33D_I, SSTL3D_II SSTL 25 Class I and II SSTL25_I,SSTL25_II Differential SSTL 25 Class I and II SSTL25D_I, SSTL25D_II SSTL 18 Class I and II SSTL18_I, SSTL18_II Differential SSTL 18 Class I and II SSTL18D_I,SSTL18D_II LVTTL LVTTL33 3.3V LVCMOS LVCMOS33 2.5V LVCMOS LVCMOS25 1.8V LVCMOS LVCMOS18 1.5V LVCMOS LVCMOS15 1.2V LVCMOS LVCMOS12 3.3V PCI PCI33 MLVDS MLVDS1 1. These differential standards are implemented by using a complementary LVCMOS driver with external resistor pack. OPENDRAIN LVCMOS and LVTTL I/O standards can be set to open drain configuration by using the OPENDRAIN attribute. Values: ON, OFF Default: OFF DRIVE The DRIVE attribute will set the programmable drive strength for the output standards that have programmable drive capability 8-8 Lattice Semiconductor LatticeXP2 sysIO Usage Guide Table 8-9. DRIVE Settings Output Standard DRIVE (mA) Default (mA) HSTL15_I/ HSTL15D_I 4, 8 8 HSTL18_I/ HSTL18D_I 8, 12 12 SSTL25_I/ SSTL25D_I 8, 12 8 SSTL25_II/ SSTL25D_II 16, 20 16 SSTL18_II/SSTL18D_II 8, 12 12 LVCMOS12 2, 6 6 LVCMOS15 4, 8 8 LVCMOS18 4, 8, 12, 16 12 LVCMOS25 4, 8, 12, 16, 20 12 LVCMOS33 4, 8, 12, 16, 20 12 LVTTL 4, 8, 12, 16, 20 12 PULLMODE The PULLMODE attribute is available for all the LVTTL, LVCMOS and PCI inputs and outputs. This attribute can be enabled for each I/O independently. Values: UP, DOWN, NONE, KEEPER Default: UP Table 8-10. PULLMODE Values PULL Options PULLMODE Value Pull-up (Default) UP Pull-down DOWN Bus Keeper KEEPER Pull Off NONE PCICLAMP PCI33 inputs on the top and bottom of the device have an optional PCI clamp that is enabled via the PCICLAMP attribute. The PCICLAMP is also available for all LVCMOS33 and LVTTL inputs. Values: ON, OFF Table 8-11. PCICLAMP Values Input Type PCICLAMP Value PCI33 ON (default), OFF LVCMOS33 OFF (default), ON LVTTL OFF (default), ON SLEWRATE The SLEWRATE attribute is available for all LVTTL and LVCMOS output drivers. Each I/O pin has an individual slew rate control. This allows a designer to specify slew rate control on a pin-by-pin basis. Values: FAST, SLOW Default: FAST 8-9 Lattice Semiconductor LatticeXP2 sysIO Usage Guide FIXEDDELAY The FIXEDDELAY attribute is available to each input pin. This attribute, when enabled, is used to achieve zero hold time for the input registers when using global clock. This attribute can only be assigned in the HDL source. Values: TRUE, FALSE Default: FALSE INBUF By default, all the unused input buffers are disabled. The INBUF attribute is used to enable the unused input buffers when performing a boundary scan test. This is a global attribute and can be globally set to ON or OFF. Values: ON, OFF Default: ON DIN/DOUT This attribute can be used to assign I/O registers. Using DIN will assert an input register and using the DOUT attribute will assert an output register. By default, the software will try to assign the I/O registers, if applicable. The user can turn this OFF by using the synthesis attribute or by using the Spreadsheet View of the Design Planner. These attributes can only be applied to registers. LOC This attribute can be used to make pin assignments to the I/O ports in the design. This attributes is only used when the pin assignments are made in HDL source. Designers can also assign pins directly using the Spreadsheet View of the Design Planner in the ispLEVER software. The appendices explain this in further detail. Design Considerations and Usage This section discusses some of the design rules and considerations that must be taken into account when designing with the LatticeXP2 sysIO buffer Banking Rules * If VCCIO or VCCJ for any bank is set to 3.3 V, it is recommended that it be connected to the same power supply as VCCAUX, thus minimizing leakage. * If VCCIO or VCCJ for any bank is set to 1.2V, it is recommended that it be connected to the same power supply as VCC, thus minimizing leakage. * When implementing DDR memory interfaces, the VREF1 of the bank is used to provide reference to the interface pins and cannot be used to power any other referenced inputs. * Only the top and bottom banks (banks 0, 1, 4 and 5)) will support PCI clamps. * All legal input buffers should be independent of bank VCCIO, except for 1.8V and 1.5V buffers, which require a bank VCCIO of 1.8V and 1.5V. Differential I/O Rules * All banks can support LVDS input buffers. Only the banks on the right and left sides (Banks 2, 3, 6 and 7) will support True Differential output buffers. The banks on all sides will support the LVDS input buffers. The user can use emulated LVDS output buffers on these banks. * All banks support emulated differential buffers using external resistor pack and complementary LVCMOS drivers. * Only 50% of the I/Os on the left and right sides can provide LVDS output buffer capability. LVDS can only be assigned to the TRUE pad. The ispLEVER design tool will automatically assign the other I/Os of the differential pair to the complementary pad. Refer to the device data sheet to see the pin listings for all LVDS pairs. 8-10 Lattice Semiconductor LatticeXP2 sysIO Usage Guide Differential I/O Implementation The LatticeXP2 devices support a variety of differential standards as detailed in the following sections. LVDS True LVDS (LVDS25) drivers are available on 50% of the I/Os on the left and right side of the devices. LVDS input support is provided on all sides of the device. All four sides of the device support LVDS using complementary LVCMOS drivers with external resistors (LVDS25E). Refer to the LatticeXP2 Family Data Sheet for a detailed explanation of these LVDS implementations. BLVDS All single-ended sysIO buffers pairs support the Bus-LVDS standard using complementary LVCMOS drivers with external resistors. Please refer to the LatticeXP2 Family Data Sheet for a detailed explanation of BLVDS implementation. RSDS All single-ended sysIO buffers pairs support RSDS standard using complementary LVCMOS drivers with external resistors. Please refer to the LatticeXP2 Family Data Sheet for a detailed explanation of RSDS implementation. LVPECL All the sysIO buffers will support LVPECL inputs. LVPECL outputs are supported using complementary LVCMOS driver with external resistors. Please refer to the LatticeXP2 Family Data Sheet for a detailed explanation of LVPECL implementation. Differential SSTL and HSTL All single-ended sysIO buffers pairs support differential SSTL and HSTL. Please refer to the LatticeXP2 Family Data Sheet for a detailed explanation of Differential HSTL and SSTL implementation. MLVDS All single-ended sysIO buffers pairs support MLVDS standard using complementary LVCMOS drivers with external resistors. Please refer to the LatticeXP2 Family Data Sheet for a detailed explanation of MLVDS implementation. Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com Revision History Date Version Change Summary February 2007 01.0 Initial release. April 2008 01.1 Updated Supported Output Standards table. February 2009 01.2 Updated I/O Standards Supported by Bank table. June 2010 01.3 Added Appendix D - sysIO Attributes Using the Diamond Spreadsheet View User Interface. Updated sysIO Banking figure. 8-11 Lattice Semiconductor LatticeXP2 sysIO Usage Guide Appendix A. HDL Attributes for Synplicity(R) and Precision(R) RTL Synthesis Using these HDL attributes, designers can assign the sysIO attributes directly in their source. The attribute definition and syntax for the appropriate synthesis vendor must be used. Below are a list of all the sysIO attributes, syntax and examples for Precision RTL Synthesis and Synplicity. This section only lists the sysIO buffer attributes for these devices. These attributes are available through the ispLEVER software Help system. VHDL Synplicity/Precision RTL Synthesis This section lists syntax and examples for all the sysIO Attributes in VHDL when using the Precision RTL Synthesis or Synplicity synthesis tools. Syntax Table 8-12. VHDL Attribute Syntax for Synplicity and Precision RTL Synthesis Attribute Syntax IO_TYPE attribute IO_TYPE: string; attribute IO_TYPE of Pinname: signal is "IO_TYPE Value"; OPENDRAIN attribute OPENDRAIN: string; attribute OPENDRAIN of Pinname: signal is "OpenDrain Value"; DRIVE attribute DRIVE: string; attribute DRIVE of Pinname: signal is "Drive Value"; PULLMODE attribute PULLMODE: string; attribute PULLMODE of Pinname: signal is "Pullmode Value"; PCICLAMP attribute PCICLAMP: string; attribute PCICLAMP of Pinname: signal is "PCIClamp Value"; SLEWRATE attribute PULLMODE: string; attribute PULLMODE of Pinname: signal is "Slewrate Value"; FIXEDDELAY attribute FIXEDDELAY: string; attribute FIXEDDELAY of Pinname: signal is "Fixeddelay Value"; DIN attribute DIN: string; attribute DIN of Pinname: signal is " "; DOUT attribute DOUT: string; attribute DOUT of Pinname: signal is " "; LOC attribute LOC: string; attribute LOC of Pinname: signal is "pin_locations"; Examples IO_TYPE --***Attribute Declaration*** ATTRIBUTE IO_TYPE: string; --***IO_TYPE assignment for I/O Pin*** ATTRIBUTE IO_TYPE OF portA: SIGNAL IS "PCI33"; ATTRIBUTE IO_TYPE OF portB: SIGNAL IS "LVCMOS33"; ATTRIBUTE IO_TYPE OF portC: SIGNAL IS "LVDS25"; OPENDRAIN --***Attribute Declaration*** ATTRIBUTE OPENDRAIN: string; --***DRIVE assignment for I/O Pin*** ATTRIBUTE OPENDRAIN OF portB: SIGNAL IS "ON"; 8-12 Lattice Semiconductor LatticeXP2 sysIO Usage Guide DRIVE --***Attribute Declaration*** ATTRIBUTE DRIVE: string; --***DRIVE assignment for I/O Pin*** ATTRIBUTE DRIVE OF portB: SIGNAL IS "20"; PULLMODE --***Attribute Declaration*** ATTRIBUTE PULLMODE : string; --***PULLMODE assignment for I/O Pin*** ATTRIBUTE PULLMODE OF portA: SIGNAL IS "DOWN"; ATTRIBUTE PULLMODE OF portB: SIGNAL IS "UP"; PCICLAMP --***Attribute Declaration*** ATTRIBUTE PCICLAMP: string; --***PULLMODE assignment for I/O Pin*** ATTRIBUTE PCICLAMP OF portA: SIGNAL IS "ON"; SLEWRATE --***Attribute Declaration*** ATTRIBUTE SLEWRATE : string; --*** SLEWRATE assignment for I/O Pin*** ATTRIBUTE SLEWRATE OF portB: SIGNAL IS "FAST"; FIXEDDELAY --***Attribute Declaration*** ATTRIBUTE FIXEDDELAY: string; --*** SLEWRATE assignment for I/O Pin*** ATTRIBUTE FIXEDDELAY OF portB: SIGNAL IS "TRUE"; DIN/DOUT --***Attribute Declaration*** ATTRIBUTE din : string; ATTRIBUTE dout : string; --*** din/dout assignment for I/O Pin*** ATTRIBUTE din OF input_vector: SIGNAL IS " "; ATTRIBUTE dout OF output_vector: SIGNAL IS " "; LOC --***Attribute Declaration*** ATTRIBUTE LOC : string; --*** LOC assignment for I/O Pin*** ATTRIBUTE LOC OF input_vector: SIGNAL IS "E3,B3,C3 "; 8-13 Lattice Semiconductor LatticeXP2 sysIO Usage Guide Verilog Synplicity This section lists syntax and examples for all the sysIO Attributes in Verilog using the Synplicity synthesis tool. Syntax Table 8-13. Verilog Synplicity Attribute Syntax Attribute Syntax IO_TYPE PinType PinName /* synthesis IO_TYPE="IO_Type Value"*/; OPENDRAIN PinType PinName /* synthesis OPENDRAIN ="OpenDrain Value"*/; DRIVE PinType PinName /* synthesis DRIVE="Drive Value"*/; PULLMODE PinType PinName /* synthesis PULLMODE="Pullmode Value"*/; PCICLAMP PinType PinName /* synthesis PCICLAMP =" PCIClamp Value"*/; SLEWRATE PinType PinName /* synthesis SLEWRATE="Slewrate Value"*/; FIXEDDELAY PinType PinName /* synthesis FIXEDDELAY="Fixeddelay Value"*/; DIN PinType PinName /* synthesis DIN=" "*/; DOUT PinType PinName /* synthesis DOUT=" "*/; LOC PinType PinName /* synthesis LOC="pin_locations "*/; Examples //IO_TYPE, PULLMODE, SLEWRATE and DRIVE assignment output portB /*synthesis IO_TYPE="LVCMOS33" PULLMODE ="UP" SLEWRATE ="FAST" DRIVE ="20"*/; output portC /*synthesis IO_TYPE="LVDS25" */; //OPENDRAIN output portA /*synthesis OPENDRAIN ="ON"*/; //PCICLAMP output portA /*synthesis IO_TYPE="PCI33" PULLMODE ="PCICLAMP"*/; // Fixeddelay input load /* synthesis FIXEDDELAY="TRUE" */; // Place the flip-flops near the load input input load /* synthesis din="" */; // Place the flip-flops near the outload output output outload /* synthesis dout="" */; //I/O pin location input [3:0] DATA0 /* synthesis loc="E3,B1,F3"*/; //Register pin location reg data_in_ch1_buf_reg3 /* synthesis loc="R40C47" */; //Vectored internal bus reg [3:0] data_in_ch1_reg /*synthesis loc ="R40C47,R40C46,R40C45,R40C44" */; 8-14 Lattice Semiconductor LatticeXP2 sysIO Usage Guide Verilog Precision This section lists syntax and examples for all the sysIO Attributes in Verilog using the Precision RTL Synthesis tool. Syntax Table 8-14. Verilog Precision Attribute Syntax Attribute Syntax IO_TYPE //pragma attribute PinName IO_TYPE IO_TYPE Value OPENDRAIN // pragma attribute PinName OPENDRAIN OpenDrain Value DRIVE // pragma attribute PinName DRIVE Drive Value PULLMODE // pragma attribute PinName IO_TYPE Pullmode Value PCICLAMP // pragma attribute PinName PCICLAMP PCIClamp Value SLEWRATE // pragma attribute PinName IO_TYPE Slewrate Value FIXEDDELAY // pragma attribute PinName IO_TYPE Fixeddelay Value LOC // pragma attribute PinName LOC pin_location Examples //****IO_TYPE *** //pragma attribute portA IO_TYPE PCI33 //pragma attribute portB IO_TYPE LVCMOS33 //pragma attribute portC IO_TYPE SSTL25_II //*** Opendrain *** //pragma attribute portB OPENDRAIN ON //pragma attribute portD OPENDRAIN OFF //*** Drive *** //pragma attribute portB DRIVE 20 //pragma attribute portD DRIVE 8 //*** Pullmode*** //pragma attribute portB PULLMODE UP //*** PCIClamp*** //pragma attribute portB PCICLAMP ON //*** Slewrate *** //pragma attribute portB SLEWRATE FAST //pragma attribute portD SLEWRATE SLOW // ***Fixeddelay*** // pragma attribute load FIXEDDELAY TRUE //***LOC*** //pragma attribute portB loc E3 8-15 Lattice Semiconductor LatticeXP2 sysIO Usage Guide Appendix B. sysIO Attributes Using the Design Planner User Interface Designers can assign sysIO buffer attributes using the Design Planner GUI available in the ispLEVER design tool. If you are using Lattice DiamondTM design software, refer to Appendix D. The Pin Attribute Sheet list all the ports in a design and all the available sysIO attributes as preferences. By clicking on each of these cells, a list of all the valid I/O preference for that port is displayed. Each column takes precedence over the next. Therefore, when a particular IO_TYPE is chosen, the DRIVE, PULLMODE and SLEWRATE columns will only list the valid combinations for that IO_TYPE. The pin locations can be locked using the pin location column of the Pin Attribute sheet. Rightclicking on a cell will list the available pin locations. The Spreadsheet View will also conduct a DRC check to search for any incorrect pin assignments. Designers can enter DIN/DOUT preferences using the Cell Attributes sheet of the Preference Editor. All the preferences assigned using the Preference Editor are written into the preference file (.prf). Figures 8-2 and 8-3 show the Pin Attribute sheet and the Cell Attribute sheet views of the preference editor. For further information on how to use the Preference Editor, refer to the ispLEVER Help documentation in the Help menu option of the software. Figure 8-2. Port Attributes Tab 8-16 Lattice Semiconductor LatticeXP2 sysIO Usage Guide Figure 8-3. Cell Attributes Tab 8-17 Lattice Semiconductor LatticeXP2 sysIO Usage Guide Appendix C. sysIO Attributes Using Preference File (ASCII File) Designers can enter sysIO attributes directly in the preference (.lpf) file as sysIO buffer preferences. The LPF file is a post-synthesis FPGA constraint file that stores logical preferences that have been created or modified in the Design Planner or Text Editor. It also contains logical preferences originating in the HDL source that have been modified. . Below are a list of sysIO buffer preference syntax and examples. IOBUF This preference is used to assign the attribute IO_TYPE, PULLMODE, SLEWRATE,PCICLAMP and DRIVE. Syntax IOBUF [ALLPORTS | PORT <port_name> | GROUP <group_name>] (keyword=<value>)+; where: <port_name> = These are not the actual top-level port names, but should be the signal name attached to the port. PIOs in the physical design (.ncd) file are named using this convention. Any multiple listings or wildcarding should be done using GROUPs Keyword = IO_TYPE, OPENDRAIN, DRIVE, PULLMODE, PCICLAMP, SLEWRATE. Example IOBUF PORT "port1" IO_TYPE=LVTTL33 OPENDRAIN=ON DRIVE=8 PULLMODE=UP PCICLAMP =OFF SLEWRATE=FAST; DEFINE PORT GROUP "bank1" "in*" "out_[0-31]"; IOBUF GROUP "bank1" IO_TYPE=SSTL18_II; LOCATE When this preference is applied to a specified component, it places the component at a specified site and locks the component to the site. If applied to a specified macro instance, it places the macro's reference component at a specified site, places all of the macro's pre-placed components (that is, all components that were placed in the macro's library file) in sites relative to the reference component, and locks all of these placed components at their sites. Below are some of the LOCATE syntax and examples. For further information, refer to the ispLEVER Help documentation in the Help menu option of the software. Syntax LOCATE [COMP <comp_name> | MACRO <macro_name>] SITE <site_name>; LOCATE VREF <vref_name> SITE <site_name>; Note: If the comp_name, macro_name, or site_name begins with anything other than an alpha character (for example, "11C7"), you must enclose the name in quotes. Wildcard expressions are allowed in <comp_name>. Examples This command places the port Clk0 on the site A4: LOCATE COMP "Clk0" SITE "A4"; This command places the component PFU1 on the site named R1C7: LOCATE COMP "PFU1" SITE "R1C7"; LOCATE VREF "ref1" SITE PR29C; 8-18 Lattice Semiconductor LatticeXP2 sysIO Usage Guide USE DIN CELL This preference specifies the given register to be used as an input flip-flop. Syntax USE DIN CELL <cell_name>; where: <cell_name> := string Example USE DIN CELL "din0"; USE DOUT CELL Specifies the given register to be used as an output flip-flop. Syntax USE DOUT CELL <cell_name>; where: <cell_name> := string Example USE DOUT CELL "dout1"; GROUP VREF This preference is used to group all the components that need to be associated to one VREF pin within a bank. Syntax LOCATE VREF <vref_name> SITE <site_name>; Example IOBUF GROUP LOCATE VREF LOCATE VREF IOBUF GROUP <group_name> BANK=<bank_name> VREF=<Vref_name> "ref1" SITE PR29C; "ref2" SITE PR48B; "group1" IO_TYPE=SSTL18_II BANK=0 VREF=vref1 ; 8-19 Lattice Semiconductor LatticeXP2 sysIO Usage Guide Appendix D. sysIO Attributes Using the Diamond Spreadsheet View User Interface sysIO buffer attributes can be assigned using the Spreadsheet View available in the Lattice Diamond design software. The Port Assignments Sheet lists all the ports in a design and all the available sysIO attributes in multiple columns. Click on each of these cells for a list of all valid I/O preferences for that port. Each column takes precedence over the next. Therefore, when you choose a particular IO_TYPE, the columns for the DRIVE, PULLMODE, SLEWRATE and other attributes will only list the valid entries for that IO_TYPE. Pin locations can be locked using the Pin column of the Port Assignments sheet or using the Pin Assignments sheet. You can right-click on a cell and go to Assign Pins to see a list of available pins. The Spreadsheet View also has an option to run a DRC check to check for any incorrect pin assignments. You can enter the DIN/DOUT preferences using the Cell Mapping Tab. All the preferences assigned using the Spreadsheet View are written into the logical preference file (.lpf). Figure 8-4 shows the Port Assignments Sheet of the Spreadsheet View. For further information on how to use the Spreadsheet View, refer to the Diamond Help documentation, available in the Help menu option of the software. Figure 8-4. Port Attributes Tab of Spreadsheet View Users can create a VREF pin using the Spreadsheet View as shown in Figure 8-5 and then assign VREF for a bank using the VREF Column in the Ports Assignment Tab of the Spreadsheet View as show in Figure 8-6. See the Diamond online help for a more detailed description of this setting. Figure 8-5. Creating a VREF in Spreadsheet View 8-20 Lattice Semiconductor LatticeXP2 sysIO Usage Guide Figure 8-6. Assigning VREF for an Input Port in Spreadsheet View 8-21 LatticeXP2 sysCLOCK PLL Design and Usage Guide February 2010 Technical Note TN1126 Introduction This user's guide describes the clock resources available in the LatticeXP2TM device architecture. Details are provided for primary clocks, secondary clocks and edge clocks as well as clock elements such as PLLs, clock dividers and more. The number of PLLs and DDR-DLLs for each device is listed in Table 9-1. Table 9-1. Number of PLLs and DDR-DLLs Parameter Description Number of GPLLs XP2-5 XP2-8 XP2-17 XP2-30 XP2-40 2 2 4 4 4 2 2 2 2 2 General purpose PLL Number of DDR-DLLs DDL for DDR applications Clock/Control Distribution Network LatticeXP2 devices provide global clock distribution in the form of eight quadrant-based primary clocks and flexible secondary clocks. Two edge clocks are also provided on every edge of the device. Other clock sources include clock input pins, internal nodes, PLLs, and clock dividers. LatticeXP2 Top Level View Figure 9-1 provides a view of the primary clocking structure of the LatticeXP2-40 device. Figure 9-1. LatticeXP2 Clocking Structure (LFXP2-40) sysIO Bank 0 sysIO Bank 1 QUADRANT BL QUADRANT BR ECLK1 sysIO Bank 2 sysIO Bank 3 Primary Clocks DQSDLL GPLL ECLK2 QUADRANT TR GPLL CLKDIV QUADRANT TL CLKDIV ECLK2 ECLK1 GPLL ECLK2 GPLL sysIO Bank 6 DQSDLL sysIO Bank 7 ECLK1 ECLK2 ECLK1 sysIO Bank 5 sysIO Bank 4 (c) 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 9-1 tn1126_01.1 LatticeXP2 sysCLOCK PLL Design and Usage Guide Lattice Semiconductor Primary Clocks Each quadrant receives up to eight primary clocks. Two of these clocks provide the Dynamic Clock Selection (DCS) feature. The six primary clocks without DCS can be specified in the Pre-map Preference Editor as `Primary Pure' and the two DCS clocks as `Primary-DCS'. The sources of primary clocks are: * PLL outputs * CLKDIV outputs * Dedicated clock pins * Internal nodes Secondary Clocks The LatticeXP2 secondary clocks are a flexible region-based clocking resource. Each region can have four independent clock inputs. Since the secondary clock is a regional resource, it can cross the primary clock quadrant boundaries. There are eight secondary clock muxes per quadrant. Each mux has inputs from four different sources. Three of these are from internal nodes. The fourth input comes from a primary clock pin. The input sources are not necessarily located in the same quadrant as the mux. This structure enables global use of secondary clocks. The sources of secondary clocks are: * Dedicated clock pins * Clock Divider (CLKDIV) outputs * Internal nodes Table 9-2 lists the number of secondary clock regions in LatticeXP2 devices. Table 9-2. Number of Secondary Clock Regions Parameter Number of regions XP2-5 XP2-8 XP2-17 XP2-30 XP2-40 6 6 6 6 8 Edge Clocks The LatticeXP2 device has two Edge Clocks (ECLK) per side. These clocks, which have low injection time and skew, are used to clock I/O registers. Edge clock resources are designed for high speed I/O interfaces with high fanout capability. Refer to Appendix B for detailed information on ECLK locations and connectivity. The sources of edge clocks are: * Left and Right Edge Clocks - Dedicated clock pins - PLL outputs - PLL input pins - Internal nodes * Top and Bottom Edge Clocks - Dedicated clock pins - Internal nodes Edge clocks can directly drive the secondary clock resources and general routing resources. Refer to Figure 9-21 for detailed information on edge clock routing. 9-2 LatticeXP2 sysCLOCK PLL Design and Usage Guide Lattice Semiconductor Figure 9-2 describes the structure of the secondary clocks and edge clocks. Figure 9-2. LatticeXP2 Secondary Clocks and Edge Clocks (LFXP2-40) sysIO Bank 0 sysIO Bank 1 DSP Row DSP Row Secondary Clock Region 7 Secondary Clock Region 3 Secondary Clock Region 8 GPLL Secondary Clock Region 4 ECLK2 ECLK2 GPLL EBR Row sysIO Bank 3 DQSDLL DQSDLL Secondary Clock Region 6 sysIO Bank 2 Secondary Clock Region 5 Secondary Clock Region 2 sysIO Bank 6 ECLK1 Secondary Clock Region 1 GPLL ECLK1 ECLK2 GPLL sysIO Bank 7 ECLK1 ECLK2 ECLK1 sysIO Bank 5 sysIO Bank 4 Primary Clock Note The CLKOP must be used as the feedback source to optimize PLL performance. Most designers use PLLs for clock tree injection removal mode and the CLKOP should be assigned to a primary clock. This is done automatically by the software unless otherwise specified by the user. CLKOP can route only to CLK0 to CLK5, while CLKOS/CLKOK can route to all primary clocks (CLK0 TO CLK7). When CLK6 or CLK7 is used as a primary clock and there is only one clock input to the DCS, the DCS is assigned as a buffer mode by the software. Please see the DCS section of this document for detailed information. Specifying Clocks in the Design Tools If desired, designers can specify the clock resources, primary, secondary or edge to be used to distribute a given clock source. Figure 9-3 illustrates how this can be done in the Pre-map Preference editor. Alternatively, the preference file can be used, as discussed in Appendix C. Primary-Pure and Primary-DCS Primary Clock Net can be assigned to either Primary-Pure (CLK0 to CLK5) or Primary-DCS (CLK6 and CLK7). Global Primary Clock and Quadrant Primary Clock Global Primary Clock If a primary clock is not assigned as a quadrant clock, the software assumes it is a global clock. There are six Global Primary/Pure clocks and two Global Primary/DCS clocks available. 9-3 LatticeXP2 sysCLOCK PLL Design and Usage Guide Lattice Semiconductor Quadrant Primary Clock Any primary clock may be assigned to a quadrant clock. The clock may be assigned to a single quadrant or to two adjacent quadrants (not diagonally adjacent). When a quadrant clock net is used, the user must ensure that the registers each clock drives can be assigned in that quadrant without any routing issues. In the Quadrant Primary Clocking scheme, the maximum number of primary clocks is 32, as long as all the primary clock sources are available. Figure 9-3. Clock Attributes in the Pre-map Preference Editor Refer to Appendix A for detailed clock network diagrams. sysCLOCKTM PLL The LatticeXP2 PLL provides features such as clock injection delay removal, frequency synthesis, phase/duty cycle adjustment, and dynamic delay adjustment. Figure 9-4 shows the block diagram of the LatticeXP2 PLL. Figure 9-4. LatticeXP2 PLL Block Diagram WRDEL DDUTY DPHASE /3 CLKI CLKFB CLKI Divider Phase & Frequency Detector CLKFB Divider Voltage Controlled Oscillator/ Loop Filter Phase Duty Cycle Duty Trim CLKOP Divider CLKOK2 CLKOS CLKOP Duty Trim CLKOK CLKOK Divider Internal Feedback Lock Detect RSTK RST 9-4 LOCK LatticeXP2 sysCLOCK PLL Design and Usage Guide Lattice Semiconductor Functional Description PLL Divider and Delay Blocks Input Clock (CLKI) Divider The CLKI divider is used to control the input clock frequency into the PLL block. The divider setting directly corresponds to the divisor of the output clock. The input and output of the input divider must be within the input and output frequency ranges specified in the device data sheet. Feedback Loop (CLKFB) Divider The CLKFB divider is used to divide the feedback signal. Effectively, this multiplies the output clock, because the divided feedback must speed up to match the input frequency into the PLL block. The PLL block increases the output frequency until the divided feedback frequency equals the input frequency. The input and output of the feedback divider must be within the input and output frequency ranges specified in the device data sheet. Output Clock (CLKOP) Divider The CLKOP divider serves the dual purposes of squaring the duty cycle of the VCO output and scaling up the VCO frequency into the 435MHz to 870MHz range to minimize jitter. The CLKOP divider values are the same whether or not the CLKOS is used. CLKOK Divider The CLKOK divider acts as a source for the global clock nets. It divides the CLKOP signal of the PLL by the value of the divider to produce lower frequency clock. CLKOK2 Divider The CLKOK2 is CLKOP divided by 3 for generating 140 MHz from 420 MHz to support SPI4.2. Phase Adjustment and Duty Cycle Select (Static Mode) Users can program CLKOS with Phase and Duty Cycle options. Phase adjustment can be done in 22.5 steps. The duty cycle resolution is 1/16th of a period except 1/16th and 15/16th duty cycle options are not supported to avoid minimum pulse violation. Dynamic Phase Adjustment (DPHASE) and Dynamic Duty Cycle (DDUTY) Select The Phase Adjustment and Duty Cycle Select can be controlled in dynamic mode. When this mode is selected, both the Phase Adjustment and Duty Cycle Select must be in dynamic mode. If only one of the features is to be used in dynamic mode, users can set the other control inputs with the fixed logic levels of their choice. Duty Trim Adjustment With the LatticeXP2 device family, the duty cycle can be fine-tuned with the Duty Trim Adjustment. Fine Delay Adjust This optional feature is controlled by the input port, WRDEL. See information on the WRDEL input in the next section of this document. PLL Inputs and Outputs CLKI Input The CLKI signal is the reference clock for the PLL. It must conform to the specifications in the data sheet in order for the PLL to operate correctly. The CLKI can be derived from a dedicated dual-purpose pin or from routing. RST Input The PLL reset occurs under two conditions. At power-up an internal power-up reset signal from the configuration block resets the PLL. The user-controlled PLL reset signal RST is provided as part of the PLL module that can be driven by an internally generated reset function or a pin. This RST signal resets all internal PLL counters, flip-flops (including the M-Divider) and the charge pump. The M-Divider reset synchronizes the M-Divider output to the input clock. When RST goes inactive, the PLL will start the lock-in process, and will take the tLOCK time to complete the PLL lock. Figure 9-5 shows the timing diagram of the RST input. RST is active high. The RST signal is optional. 9-5 LatticeXP2 sysCLOCK PLL Design and Usage Guide Lattice Semiconductor Figure 9-5. RST Input Timing Diagram tRST PLL_RST tLOCK LOCK RSTK Input RSTK is the reset input for the K-Divider. This K-Divider reset is used to synchronize the K-Divider output clock to the input clock. LatticeXP2 has an optional gearbox in the I/O cell for both outputs and inputs. The K-Divider reset is useful for the gearbox implementation. RSTK is active high. CLKFB Input The feedback signal to the PLL, which is fed through the feedback divider, can be derived from the Primary Clock net (CLKOP), a preferred pin, directly from the CLKOP divider or from general routing. External feedback allows the designer to compensate for board-level clock alignment. CLKOP Output The sysCLOCK PLL main clock output, CLKOP, is a signal available for selection as a primary clock. This clock signal is available at the CLK_OUT pin. CLKOS Output with Phase and Duty Cycle Select The sysCLOCK PLL auxiliary clock output, CLKOS, is a signal available for selection as a primary clock. The CLKOS is used when phase shift and/or duty cycle adjustment is desired. The programmable phase shift allows for different phase in increments of 22.5. The duty select feature provides duty select in 1/16th of the clock period. This feature is also supported in Dynamic Control Mode. CLKOK Output with Lower Frequency The CLKOK is used when a lower frequency is desired. It is a signal available for selection as a primary clock. CLKOK2 Output This extra clock is provided for SPI4.2 application. The 420 MHz CLKOP clock is divided by 3, producing 140 MHz. The clock can also be used for any applications where CLKOP-divided-by-3 is required. LOCK Output The LOCK output provides information about the status of the PLL. After the device is powered up and the input clock is valid, the PLL will achieve lock within the specified lock time. Once lock is achieved, the PLL lock signal will be asserted. If, during operation, the input clock or feedback signals to the PLL become invalid, the PLL will lose lock. However, when the input clock completely stops, the LOCK output will remain in its last state, since it is internally registered by this clock. It is recommended to assert PLL RST to re-synchronize the PLL to the reference clock. The LOCK signal is available to the FPGA routing to implement generation of RST. ModelSim(R) simulation models take two to four reference clock cycles from RST release to LOCK high. Dynamic Phase and Dynamic Duty Cycle Adjustment The DPHASE[3:0] port is used with the Dynamic Phase Adjustment feature to allow the user to connect a control signal to the PLL. The DDUTY[3:0] port is used with the Dynamic Duty Adjustment feature to allow the user to connect a control signal to the PLL. The DPHASE and DDUTY ports are listed in Table 9-3. The Dynamic Phase and Dynamic Duty Cycle Adjustment features will be discussed in more detail in later sections of this document. 9-6 LatticeXP2 sysCLOCK PLL Design and Usage Guide Lattice Semiconductor Table 9-3. Dynamic Phase and Duty Cycle Adjust Ports Port Name I/O Description DPHASE[3:0] I Dynamic Phase Adjust inputs DDUTY[3:0] I Dynamic Duty Cycle Adjust inputs WRDEL (Write Delay) The fine delay option supports SPI4.2. The PLL has a coarse phase adjust feature in which a cycle is divided into 16 equal steps (22.5). For SPI4.2 running at 840 Mbps, the clock frequency is 420 MHz. At this frequency, the period is roughly 150 ps. This is slightly too coarse for dynamic phase adjust requirements. It may be more effective to use increments half as large. Combined with coarse phase adjust, a 70 ps (nominal) step provides effectively 32 steps of phase adjustment. This fine delay only applies to CLKOS (just like the coarse phase adjust). This is convenient since it allows one GPLL to be used for both read and write (where read uses CLKOS and write uses CLKOP). PLL Attributes The PLL utilizes several attributes that allow the configuration of the PLL through source constraints and a preference file. The following section details these attributes and their usage. FIN The input frequency can be any value within the specified frequency range based on the divider settings. CLKI_DIV, CLKFB_DIV, CLKOP_DIV, CLKOK_DIV These dividers determine the output frequencies of each output clock. The user is not allowed to input an invalid combination. Valid combinations are determined by the input frequency, the dividers, and the PLL specifications. Note: Unlike PLLs in the LatticeECPTM, LatticeECTM, LatticeXPTM and MachXOTM devices, the CLKOP divider values are the same whether or not CLKOS is used. The CLKOP_DIV value is calculated to maximize the fVCO within the specified range based on FIN and CLKOP_FREQ in conjunction with the CLKI_DIV and CLKFB_DIV values. These value settings are designed such that the output clock duty cycle is as close to 50% as possible. Table 9-4 shows the possible divider ranges. Table 9-4. Divider Ranges Attribute CLKI Divider Setting Name Value Default CLKI_DIV 1 to 43 1 CLKFB Divider Setting CLKFB_DIV 1 to 43 1 CLKOP Divider Setting CLKOP_DIV 2, 4, 8, 16, 32, 48, 64, 80 8 CLKOK Divider Setting CLKOK_DIV 2, 4, 6,.., 126, 128 2 FREQUENCY_PIN_CLKI, FREQUENCY_PIN_CLKOP, FREQUENCY_PIN_CLKOK These input and output clock frequencies determine the divider values. CLKOP Frequency Tolerance When the desired output frequency is not achievable, users may enter the frequency tolerance of the clock output. PHASEADJ (Phase Shift Adjust) The PHASEADJ attribute is used to select Phase Shift for CLKOS output. The phase adjustment is programmable in 22.5 increments. 9-7 LatticeXP2 sysCLOCK PLL Design and Usage Guide Lattice Semiconductor DUTY (Duty Cycle) The DUTY attribute is used to select the Duty Cycle for CLKOS output. The Duty Cycle is programmable at 1/16th of the period increment. Steps 2 to 14 are supported. 1/16th and 15/16th duty cycles are not supported to avoid the minimum pulse width violation. FB_MODE There are three sources of feedback signals that can drive the CLKFB Divider: Internal, CLKOP (Clock Tree) and user clock. CLKOP (Clock Tree) feedback is used by default. Internal feedback takes the CLKOP output at CLKOP Divider output before the Clock Tree to minimize the feedback path delay. The user clock feedback is driven from the dedicated pin, clock pin or user-specified internal logic. DUTY_TRIM Adjustment (Dynamic mode only) Users can fine tune the duty cycle of CLKOP and/or CLKOS with the DUTY_TRIM feature when Dynamic PHASE/DUTY Adjustment is selected. * TRIM Polarity Select: Users can select either rising edge or falling edge of clock to trim. * TRIM Delay of CLKOP can be set to 0 to 7 steps of unit trim delay. * TRIM Delay of CLKOS can be set to 0 to 3 steps of unit trim delay. CLKOS/CLKOK/CLKOK2 Select Users select these output clocks only when they are used in the design. CLKOP/CLKOS/CLKOK BYPASS These bypasses are enabled if set. CLKI is directly routed to its corresponding output clock. RST/RSTK Select Users may select these reset signals only when they are used in the design. LatticeXP2 PLL Primitive Definition One PLL primitive is used for LatticeXP2 PLL implementation. Figure 9-6 shows the LatticeXP2 PLL primitive library symbols. Figure 9-6. LatticeXP2 PLL Primitive Symbol EHXPLLE RST RSTK CLKI CLKFB WRDEL DPHASE[3:0] DDUTY[3:] CLKOP CLKOS CLKOK CLKOK2 LOCK EPLLD Design Migration from LatticeECP2 to LatticeXP2 The EPLLD generated for LatticeECP2 can be used with minor changes. If the configuration does not include Dynamic Phase and Duty Options, the migration is fully supported. If Dynamic Phase and Duty Options are included, the user must tie the DPAMODE port to ground. Dynamic Phase/Duty Mode This mode sets both Dynamic Phase Adjustment and Dynamic Duty Select at the same time. There are two modes, "Dynamic Phase and Dynamic Duty" and "Dynamic Phase and 50% Duty". Dynamic Phase and 50% Duty This mode allows users to set up Dynamic Phase inputs only. The 50% Duty Cycle is handled internally by the ispLEVER(R) software. The DDUTY[3:0] ports are user-transparent in this mode. 9-8 LatticeXP2 sysCLOCK PLL Design and Usage Guide Lattice Semiconductor Dynamic Phase and Dynamic Duty This mode allows designers to use both DDPHASE[3:0] and DDUTY[3:0] ports to input dynamic values. To use Dynamic Phase Adjustment with a fixed duty cycle other than a 50%, simply set the DDUTY[3:0] inputs to the desired duty cycle value. Figure 9-7 illustrates an example circuit. Example: Assume a design uses dynamic phase adjustment and a fixed duty cycle select and the desired duty cycle in 3/16th of a period. The setup should be as shown in Figure 9-7. Figure 9-7. Example of Dynamic Phase Adjustment with a Fixed Duty Cycle of 3/16th of a Period DPHASE[3] DPHASE[2] DPHASE[3:0] DPHASE[1] DPHASE[0] DPAMODE DDUTY[3] DDUTY[2] DDUTY[1] DDUTY[0] Dynamic Phase Adjustment/Duty Cycle Select Phase Adjustment settings are described in Table 9-5. Table 9-5. Phase Adjustment Settings DPHASE[3:0] Phase () 0000 0 0001 22.5 0010 45 0011 67.5 0100 90 0101 112.5 0110 135 0111 157.5 1000 180 1001 202.5 1010 225 1011 247.5 1100 270 1101 292.5 1110 315 1111 337.5 9-9 PLL LatticeXP2 sysCLOCK PLL Design and Usage Guide Lattice Semiconductor Duty Cycle Select settings are described in Table 9-6. Table 9-6. Duty Cycle Select Settings DDUTY[3:0] Duty Cycle (1/16th of a Period) Comment 0000 0 Not Supported 0001 1 Not Supported 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15 Not Supported Note: PHASE/DUTY_CTNL is selected in the GUI `PLL Phase & Duty Options' box and if it is set to `Dynamic Mode', then both DPHASE[3:0] and DDUTY[3:0] inputs must be provided. If one of these inputs is a fixed value, the inputs must be tied to the desired fixed logic levels. PLL Usage in IPexpressTM IPexpress is used to create and configure a PLL. The graphical user interface is used to select parameters for the PLL. The result is an HDL model to be used in the simulation and synthesis flow. Figure 9-8 shows the main window when PLL is selected. The only entry required in this window is the module name. Other entries are set to the project settings. Users may change these entries, if desired. After entering the module name of choice, clicking on Customize will open the Configuration Tab window as shown in Figure 9. 9-10 LatticeXP2 sysCLOCK PLL Design and Usage Guide Lattice Semiconductor Figure 9-8. IPexpress Main Window Configuration Tab The Configuration Tab lists all user accessible attributes with default values set. Upon completion, clicking Generate will generate source and constraint files. Users may choose to use the .lpc file to load parameters. Configuration Modes There are two modes that can be used to configure the PLL in the Configuration Tab, Frequency Mode and Divider Mode. Frequency Mode: In this mode, the user enters input and output clock frequencies and the software calculates the divider settings. If the output frequency entered is not achievable the nearest frequency will be displayed in the `Actual' text box. After input and output frequencies are entered, clicking the Calculate button will display the divider values. Divider Mode: In this mode, the user sets the divider settings with input frequency. Users must choose the CLKOP Divider value to maximize the fVCO and achieve optimum PLL performance. After input frequency and divider settings are set, clicking the Calculate button will display the frequencies. Figure 9-9 shows the Configuration Tab. 9-11 LatticeXP2 sysCLOCK PLL Design and Usage Guide Lattice Semiconductor Figure 9-9. LatticeXP2 PLL Configuration Tab Table 9-7 describes the user parameters in the IPexpress GUI and their usage. Table 9-7. User Parameters in the IPexpress GUI User Parameters Description Range Default Frequency Mode User desired CLKI and CLKOP frequency ON/OFF ON Divider Mode User desired CLKI frequency and dividers settings ON/OFF OFF 10 MHz to 435 MHz 100 MHz 1 to 43 1 Internal, CLKOP, User Clock CLKOP 1 to 43 1 CLKI Frequency Input Clock frequency Divider Input Clock Divider Setting (Divider Mode) Feedback Mode Feedback Mode Divider Feedback Clock Divider Setting (Divider Mode) CLKFB None No Phase & Duty Options ON/OFF ON Static Mode CLKOS Phase/Duty in Static Mode ON/OFF OFF CLKOS Dynamic Mode Phase/Duty Setting ON/OFF OFF CLKOS Duty Trimming ON/OFF OFF CLKOP Duty Trimming ON/OFF OFF PLL Phase & Duty Options Dynamic Mode 9-12 LatticeXP2 sysCLOCK PLL Design and Usage Guide Lattice Semiconductor Table 9-7. User Parameters in the IPexpress GUI (Continued) User Parameters Bypass Description Bypass PLL: CLKOP = CLKI Desired Frequency User enters desired CLKOP frequency CLKOP CLKOS CLKOK CLKOK2 Range Default ON/OFF OFF 10 MHz to 435 MHz 100 MHz 2, 4, 8, 16, 32, 48, 64, 80 8 0.0, 0.1, 0.2, 0.5, 0.1, 0.2, 0.5, 1.0 0.0 -- -- Divider CLKOP Divider Setting (Divider Mode) Tolerance CLKOP tolerance users can tolerate Actual Frequency Actual frequency achievable. Read only Rising Rising Edge Trim ON/OFF OFF Falling Falling Edge Trim ON/OFF OFF Delay Multiplier Number of delay steps Enable Enable CLKOS output clock Bypass Bypass PLL: CLKOS = CLKI Phase Shift CLKOS Static Phase Shift Rising Rising Edge Trim Delay Multiplier Number of Delay steps Enable Enable CLKOS output clock Bypass Bypass PLL: CLKOK = CLKI Frequency User enters desired CLKOK frequency Divider CLKOK Divider Setting Tolerance CLKOK tolerance users can tolerate Actual Frequency Actual frequency achievable. Read only Enable Enable CLKOK2 output clock 0 to 7 0 ON/OFF OFF ON/OFF OFF 0, 22.5, 45..337.5 0 ON/OFF OFF 0 to 7 0 ON/OFF OFF ON/OFF OFF 78.125 kHz to 217.5 MHz 50 MHz 2 to 128 2 0.0, 0.1, 0.2, 0.5, 0.1, 0.2, 0.5, 1.0 0.00 -- -- ON/OFF OFF Provide PLL Reset Provide PLL Reset Port (RESET) ON/OFF OFF Provide CLKOK Divide Reset Provide CLKOK Reset Port (RSTK) ON/OFF OFF Provide CLKOS Fine Delay Port Provide CLKOS Fine Delay Port (WRDEL) ON/OFF OFF Import LPC to ispLEVER Project Import .lpc file to ispLEVER project ON/OFF OFF PLL Modes of Operation PLLs have many uses within a logic design. The two most popular are Clock Injection Removal and Clock Phase Adjustment. These two modes of operation are described below. PLL Clock Injection Removal In this mode the PLL is used to reduce clock injection delay. Clock injection delay is the delay from the input pin of the device to a destination element such as a flip-flop. The phase detector of the PLL aligns the CLKI with CLKFB. If the CLKFB signal comes from the clock tree (CLKOP), then the PLL delay and the clock tree delay is removed. Figure 9-10 Illustrates an example block diagram and waveform. 9-13 LatticeXP2 sysCLOCK PLL Design and Usage Guide Lattice Semiconductor Figure 9-10. Clock Injection Delay Removal Application CLKI CLKFB CLKOP PLL Clock Tree CLKI Clock Injection Delay Clock at Clock Tree without PLL CLKOP/CLKOS at Clock Tree with PLL PLL Clock Phase Adjustment In this mode the PLL is used to create fixed phase relationships in 22.5 increments. Creating fixed phase relationships is useful for forward clock interfaces where a specific relationship between clock and data is required. The fixed phase relationship can be used between CLKI and CLKOS or between CLKOP and CLKOS. Figure 9-11. CLKOS Phase Adjustment from CLKOP CLKOP CLKI CLKFB PLL CLKOS CLKI CLKOP CLKOS with 90 Phase Shift IPexpress Output There are two IPexpress outputs that are important for use in the design. The first is the <module_name>.[v|vhd] file. This is the user-named module that was generated by the tool to be used in both synthesis and simulation flows. The second is a template file, <module_name>_tmpl.[v|vhd]. This file contains a sample instantiation of the module. This file is provided for the user to copy/paste the instance and is not intended to be used in the synthesis or simulation flows directly. For the PLL, IPexpress sets attributes in the HDL module that are specific to the data rate selected. Although these attributes can be easily changed, they should only be modified by re-running the GUI so that the performance of the PLL is maintained. After the map stage in the design flow, FREQUENCY preferences will be included in the preference file to automatically constrain the clocks produced from the PLL. 9-14 LatticeXP2 sysCLOCK PLL Design and Usage Guide Lattice Semiconductor Use of the Pre-Map Preference Editor Clock preferences can be set in the Pre-Map Preference Editor. Figure 9-12 shows an example screen shot. The Pre-Map Preference Editor is a part of the ispLEVER Design Planner. Figure 9-12. Pre-Map Preference Editor Example Clock Dividers (CLKDIV) The clock divider divides the high-speed clock by 1, 2, 4 or 8. All the outputs have matched input to output delay. CLKDIV can take as its input the edge clocks and the CLKOP of the PLL. The divided outputs drive the primary clock and are also available for general routing or secondary clocks. The clock dividers are used for providing the low speed FPGA clocks for shift registers (x2, x4, x8) and DDR/SPI4 I/O logic interfaces. CLKDIV Primitive Definition Users can instantiate CLKDIV in the source code as defined in this section. Figure 9-13 and Tables 9-8 and 9-9 describe the CLKDIVB definitions. Figure 9-13. CLKDIV Primitive Symbol CLKDIVB CLKI CDIV1 RST CDIV2 RELEASE CDIV4 CDIV8 9-15 LatticeXP2 sysCLOCK PLL Design and Usage Guide Lattice Semiconductor Table 9-8. CLKDIVB Port Definition Name Description CLKI Clock Input RST Reset Input, asynchronously forces all outputs low. RELEASE Releases outputs synchronously to input clock. CDIV1 Divided BY 1 Output CDIV2 Divided BY 2 Output CDIV4 Divided BY 4 Output CDIV8 Divided BY 8 Output Table 9-9. CLKDIVB Attribute Definition Name Description Value Default GSR GSR Enable ENABLED/DISABLED DISABLED CLKDIV Declaration in VHDL Source Code COMPONENT CLKDIVB -- synthesis translate_off GENERIC ( GSR : in String); -- synthesis translate_on PORT ( CLKI,RST, RELEASE:IN std_logic; CDIV1, CDIV2, CDIV4, CDIV8:OUT std_logic); END COMPONENT; attribute GSR : string; attribute GSR of CLKDIVinst0 : label is "DISABLED"; begin CLKDIVinst0: CLKDIVB -- synthesis translate_off GENERIC MAP( GSR => "disabled" ); -- synthesis translate_on PORT MAP( CLKI => CLKIsig, RST => RSTsig, RELEASE => RELEASEsig, CDIV1 => CDIV1sig, CDIV2 => CDIV2sig, CDIV4 => CDIV4sig, CDIV8 => CDIV8sig ); 9-16 LatticeXP2 sysCLOCK PLL Design and Usage Guide Lattice Semiconductor CLKDIV Usage with Verilog - Example module clkdiv_top(RST,CLKI,RELEASE,CDIV1,CDIV2,CDIV4,CDIV8); input CLKI,RST,RELEASE; output CDIV1,CDIV2,CDIV4,CDIV8; CLKDIVB CLKDIBinst0 (.RST(RST),.CLKI(CLKI),.RELEASE(RELEASE), .CDIV1(CDIV1),.CDIV2(CDIV2),.CDIV4(CDIV4),.CDIV8(CDIV8)); defparam CLKDIBint0.GXR = "DISABLED"; endmodule CLKDIV Example Circuits The clock divider (CLKDIV) can divide a clock by 2 or 4 and drives a primary clock network. Clock dividers are useful for providing the low speed FPGA clocks for I/O shift registers (x2, x4) and DDR (x2, x4) I/O logic interfaces. Divide by 8 is provided for slow speed/low power operation. To guarantee a synchronous transfer in the I/O logic the CLKDIV input clock must come from an edge clock and the output drive from a primary clock. In this case, they are phase matched. It is especially useful to synchronously reset the I/O logic when Mux/DeMux gearing is used in order to synchronize the entire data bus as shown in Figure 9-14. Using the low skew characteristics of the edge clock routing a reset can be provided to all bits of the data bus to synchronize the Mux/DeMux gearing. The second circuit shows that a DLL can replace CLKDIV for x2 and x4 applications. Figure 9-14. CLKDIV Application Example Data D GEARING (2x) Q 8 Primary Clock ECLK RST CLKDIV 9-17 16 LatticeXP2 sysCLOCK PLL Design and Usage Guide Lattice Semiconductor Reset Behavior Figure 9-15 illustrates the asynchronous RST behavior. Figure 9-15. CLKDIV Reset Behavior CLKI RST CDIV1 CDIV2 CDIV4 CDIV8 RST asserted asynchronously. All clock outputs are forced low. After de-asserted RST is registered all outputs start toggling. De-asserted RST is registered. Release Behavior The port, "Release" is used to synchronize the all outputs after RST is de-asserted. Figure 9-16 Illustrates the release behavior. Figure 9-16. CLKDIV Release Behavior CLKI RST CDIV1 RELEASE CDIV2 CDIV4 CDIV8 De-asserted RST registered Release synchronizes outputs Clock start counting 9-18 LatticeXP2 sysCLOCK PLL Design and Usage Guide Lattice Semiconductor CLKDIV Inputs-to-Outputs Delay Matching Figure 9-17. CLKDIV Inputs-to-Outputs Delay Matching CLKI CDIV1 CDIV2 CDIV4 CDIV8 DCS (Dynamic Clock Select) DCS is a global clock buffer incorporating a smart multiplexer function that takes two independent input clock sources and avoids glitches or runt pulses on the output clock, regardless of where the enable signal is toggled. There are two DCSs for each quadrant. The outputs of the DCS then reach primary clock distribution via the feedlines. Figure 9-18 shows the block diagram of the DCS. Figure 9-18. DCS Primitive Symbol DCS CLK0 CLK1 SEL DCSOUT DCS Primitive Definition Table 9-10 defines the I/O ports of the DCS block. There are eight modes to select from. Table 9-11 describes how each mode is configured. Table 9-10. DCS I/O Definition I/O Input Output Name Description SEL Input Clock Select CLK0 Clock input 0 CLK1 Clock Input 1 DCSOUT Clock Output 9-19 LatticeXP2 sysCLOCK PLL Design and Usage Guide Lattice Semiconductor Table 9-11. DCS Modes of Operation Output Attribute Name SEL=0 SEL=1 Value Rising edge triggered, latched state is high Description CLK0 CLK1 POS Falling edge triggered, latched state is low CLK0 CLK1 NEG 0 CLK1 HIGH_LOW 1 CLK1 HIGH_HIGH CLK0 0 LOW_LOW Sel is active high, Disabled output is low DCS MODE Sel is active high, Disabled output is high Sel is active low, Disabled output is low Sel is active low, Disabled output is high CLK0 1 LOW_HIGH Buffer for CLK0 CLK0 CLK0 CLK0 Buffer for CLK1 CLK1 CLK1 CLK1 DCS Timing Diagrams Each mode performs a unique operation. The clock output timing is determined by input clocks and the edge of the SEL signal. Figure 9-19 describes the timing of each mode. Figure 9-19. Timing Diagrams by DCS MODE DCS MODE = POS CLK0 CLK1 SEL DCSOUT SEL Falling edge: - Wait for CLK1 rising edge, latch output & remain high - Switch output at CLK0 rising edge SEL Rising edge: - Wait for CLK0 rising edge, latch output & remain high - Switch output at CLK1 rising edge DCS MODE = NEG CLK0 CLK1 SEL DCSOUT SEL Falling edge: - Wait for CLK1 falling edge, latch output & remain low - Switch output at CLK0 falling edge SEL Rising edge: - Wait for CLK0 falling edge, latch output & remain low - Switch output at CLK1 falling edge 9-20 LatticeXP2 sysCLOCK PLL Design and Usage Guide Lattice Semiconductor Figure 9-20. Timing Diagrams by DCS MODE (Cont.) DCS MODE = LOW_LOW DCS MODE = HIGH_LOW CLK1 CLK0 SEL SEL DCSOUT DCSOUT - Switch low @CLK1 falling edge. - If SEL is low, output stays low at on CLK1 rising edge. SEL must not change during setup prior to rising clock. - Switch low @CLK0 falling edge. - If SEL is high, output stays low at on CLK0 rising edge. DCS MODE = HIGH_HIGH DCS MODE = LOW_HIGH CLK1 CLK0 SEL SEL DCSOUT DCSOUT - Switch high @CLK1 rising edge. - If SEL is low, output stays low high on CLK1 falling edge. - Switch high @ CLK0 rising edge. - If SEL is high, output stays high on CLK0 falling edge. DCS Usage with VHDL - Example COMPONENT DCS -- synthesis translate_off GENERIC ( DCSMODE : string := ; -- synthesis translate_on PORT "POS" ( END COMPONENT; attribute DCSMODE : string; attribute DCSMODE of DCSinst0 : label is "POS"; begin DCSInst0: DCS -- synthesis translate_off GENERIC MAP ( 9-21 LatticeXP2 sysCLOCK PLL Design and Usage Guide Lattice Semiconductor DCSMODE => "POS" ) -- synthesis translate_on PORT MAP ( SEL CLK0 CLK1 DCSOUT ); => => => => clksel, dcsclk0, sysclk1, dcsclk DCS Usage with Verilog - Example module dcs(clk0,clk1,sel,dcsout); input clk0, clk1, sel; output dcsout; DCS DCSInst0 (.SEL(sel),.CLK0(clk0),.CLK1(clk1),.DCSOUT(dcsout)); defparam DCSInst0.DCSMODE = "CLK0"; endmodule Oscillator (OSCE) There is a dedicated oscillator in the LatticeXP2 device whose output is made available for users. The oscillator frequency output is routed through a divider which is used as an input clock to the clock tree. The available outputs of the divider are shown in Table 9-13. The oscillator frequency output can be further divided by internal logic (user logic) for lower frequencies, if desired. The oscillator is powered down when not in use. The output of this oscillator is not a precision clock. It is intended as an extra clock that does not require accurate clocking. Primitive Name: OSCE Table 9-12. OSCE Port Definition I/O Name Description Output OSC Oscillator Clock Output Table 9-13. OSCE Attribute Definition User Attribute Attribute Name Value (MHz) Default Value Nominal Frequency NOM_FREQ 2.5, 3.14, 4.3, 5.4, 6.9, 8.1, 9.2, 10, 13, 15, 20, 26, 32, 40, 54, 80, 163 2.5 OSC Primitive Symbol (OSCE) Figure 9-21. OSC Symbol OSCE OSC 9-22 LatticeXP2 sysCLOCK PLL Design and Usage Guide Lattice Semiconductor OSC Usage with VHDL - Example COMPONENT OSCE PORT (OSC:OUT std_logic); END COMPONENT; begin OSCInst0: OSCE PORT MAP ( OSC=> osc_int); OSC Usage with Verilog - Example module OSC_TOP(OSC_CLK); output OSC_CLK; OSCE OSCinst0 (.OSC(OSC_CLK)); endmodule Setting Clock Preferences Designers can use clock preferences to implement clocks to the desired performance. Preferences can be set in the Pre-Map Preference Editor (Design Planner) or in preference files. Frequently used preferences are described in Appendix C. Power Supplies Each PLL has its own power supply pin, VCCPLL. Since VCCAUX and VCCPLL are normally the same 3.3V, it is recommended that they are driven from the same power supply on the circuit board, thus minimizing leakage. In addition, each of these supplies should be independently isolated from the main 3.3V supply on the board using proper board filtering techniques to minimize the noise coupling between them. Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com Revision History Date Version Change Summary February 2007 01.0 Initial release. February 2010 01.1 Reconciled LOCK description among MachXO, LatticeXP2, LatticeECP2/M and LatticeECP3. 9-23 LatticeXP2 sysCLOCK PLL Design and Usage Guide Lattice Semiconductor Appendix A. Primary Clock Sources and Distribution Figure 9-22. LatticeXP2 Primary Clock Sources and Distribution QUADRANT TL CLK6 CLK7 CLK7 CLK6 CLK5 CLK4 CLK3 CLK2 CLK1 CLK0 DCS DCS DCS DCS General Routing General Routing 2 GPLL* CLKOP CLKOS CLKOK CLKOK2 GPLL CLKOP CLKOS CLKOK CLKOK2 36:1 36:1 36:1 36:1 32:1 32:1 32:1 32:1 32:1 32:1 32:1 32:1 36:1 36:1 36:1 36:1 36:1 36:1 PCLKT2 Primary Clocks in Center Switch Box GPLL* : Available in XP2-17 and larger devices CLKDIV1 CLKDIV2 CLKDIV4 CLKDIV8 PCLKT6 36:1 36:1 36:1 36:1 36:1 36:1 32:1 32:1 32:1 32:1 32:1 32:1 32:1 32:1 36:1 36:1 36:1 36:1 CLKOP CLKOS CLKOK CLKOK2 GPLL CLKDIV1 CLKDIV2 CLKDIV4 CLKDIV8 CLKDIV 3 DCS PCLKT5 GPLL* PCLKT3 36:1 36:1 2 CLKOP CLKOS CLKOK CLKOK2 DCS DCS DCS General Routing General Routing CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 CLK7 CLK6 QUADRANT BL CLK5 CLK4 CLK3 CLK2 CLK1 CLK0 PCLKT4 CLKDIV 3 36:1 36:1 PCLKT7 PCLKT1 PCLKT0 CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 QUADRANT TR QUADRANT BR Figure 9-23. LatticeXP2 Primary Clock Muxes VCC 4 PCLK pins General Routing 8 CLKDIV outputs CLK0 - 5 4 PCLK pins 2 from General Routing 9-24 DCS 30:1 8 CLKDIV outputs 29:1 16 PLL outputs 16 PLL outputs CLK6 - 7 LatticeXP2 sysCLOCK PLL Design and Usage Guide Lattice Semiconductor Appendix B. PLL, CLKDIV and ECLK Locations and Connectivity Figure 9-24 shows the locations, site names and connectivity of the PLLs, CLKDIVs and ECLKs Internal Node PCLKT1 Internal Node PCLKT0 Figure 9-24. PLL, CLKDIV and ECLK Locations and Connectivity ECLK1 ECLK2 PCLKT7 PCLKT2 Internal Node CLKOP CLKOS ECL K2 URGPLL E CLK1 E CLK2 ECL K1 ULGPLL Internal Node CLKOP CLKOS URGPLL_IN LLGPLL_IN LRGPLL_IN LLGPLL RCLKDIV LCLKDIV ULGPLL_IN CLKOP CLKOP CLKOS CLKOS Internal Node PCLKT6 LRGPLL Internal Node PCLKT3 ECLK2 9-25 Internal Node PCLKT4 Internal Node PCLKT5 ECLK1 LatticeXP2 sysCLOCK PLL Design and Usage Guide Lattice Semiconductor Appendix C. Clock Preferences A few key clock preferences are introduced below. Refer to the `Help' file for other preferences and detailed information. ASIC The following preference command assigns a phase of 90 degrees to the CIMDLLA CLKOP. ASIC "my_dll" TYPE "CIMDLLA" CLKOP_PHASE=90; FREQUENCY The following physical preference command assigns a frequency of 100 MHz to a net named clk1: FREQUENCY NET "clk1" 100 MHz; The following preference specifies a hold margin value for each clock domain: FREQUENCY NET "RX_CLKA_CMOS_c" 100.000 MHz HOLD_MARGIN 1 ns; MAXSKEW The following command assigns a maximum skew of 5 nanoseconds to a net named NetB: MAXSKEW NET "NetB" 5 NS; MULTICYCLE The following command will relax the period to 50 nanoseconds for the path starting at COMPA to COMPB (NET1): MULTICYCLE "PATH1" START COMP "COMPA" END COMP "COMPB" NET "NET1" 50 NS ; PERIOD The following command assigns a clock period of 30 nanoseconds to the port named Clk1: PERIOD PORT "Clk1" 30 NS; PROHIBIT This command prohibits the use of a primary clock to route a clock net named bf_clk: PROHIBIT PRIMARY NET "bf_clk"; USE PRIMARY Use a primary clock resource to route the specified net: USE PRIMARY NET clk_fast; USE PRIMARY DCS NET "bf_clk"; USE PRIMARY PURE NET "bf_clk" QUADRANT_TL; USE SECONDARY Use a secondary clock resource to route the specified net: USE SECONDARY NET "clk_lessfast" QUADRANT_TL; 9-26 LatticeXP2 sysCLOCK PLL Design and Usage Guide Lattice Semiconductor USE EDGE Use a edge clock resource to route the specified net: USE EDGE NET "clk_fast"; CLOCK_TO_OUT Specifies a maximum allowable output delay relative to a clock. Here are two preferences using both the CLKPORT and CLKNET keywords showing the corresponding scope of TRACE reporting. The CLKNET will stop tracing the path before the PLL, so you will not get PLL compensation timing numbers. CLOCK_TO_OUT PORT "RxAddr_0" 6.000000 ns CLKNET "pll_rxclk" ; The above preference will yield the following clock path: Clock path pll_inst/pll_utp_0_0 to PFU_33: Name ROUTE Fanout 49 -------2.892 Delay (ns) 2.892 Site Resource ULPPLL.MCLK to R3C14.CLK0 pll_rxclk (0.0% logic, 100.0% route), 0 logic levels. If CLKPORT is used, the trace is complete back to the clock port resource and provides PLL compensation timing numbers. CLOCK_TO_OUT PORT "RxAddr_0" 6.000000 ns CLKPORT "RxClk" ; The above preference will yield the following clock path: Clock path RxClk to PFU_33: Name Fanout Delay (ns) Site Resource IN_DEL --1.431 D5.PAD to D5.INCK RxClk ROUTE 1 0.843 D5.INCK to ULPPLL.CLKIN RxClk_c MCLK_DEL --3.605 ULPPLL.CLKIN to ULPPLL.MCLK pll_inst/pll_utp_0_0 ROUTE 49 2.892 ULPPLL.MCLK to R3C14.CLK0 pll_rxclk -------8.771 (57.4% logic, 42.6% route), 2 logic levels. INPUT_SETUP Specifies an setup time requirement for input ports relative to a clock net. INPUT_SETUP PORT PLL_PHASE_BACK ; "datain" 2.000000 ns HOLD 1.000000 ns CLKPORT "clk" PLL_PHASE_BACK This preference is used with INPUT_SETUP when a user needs a trace calculation based on the previous clock edge. This preference is useful when setting the PLL output phase adjustment. Since there is no negative phase adjustment provided, the PLL_PHASE_BACK preference works as if negative phase adjustment is available. 9-27 LatticeXP2 sysCLOCK PLL Design and Usage Guide Lattice Semiconductor For example: If phase adjustment of -90 of CLKOS is desired, a user can set the Phase to 270 and set the INPUT_SETUP preference with PLL_PHASE_BACK. PLL_PHASE_BACK Usage in Pre-Map Preference Editor The Pre-Map Preference Editor can be used to set the PLL_PHASE_BACK attribute. 1. Open the Design Planner (Pre-Map). 2. In the Design Planner control window, select View -> Spreadsheet View. 3. In the Spreadsheet View window, select Input_setup/Clock_to_out... The INPUT_SETUP/CLOCK_TO_OUT Preference window is shown in Figure 9-25. Figure 9-25. INPUT_SETUP/CLOCK_TO_OUT Preference Window 9-28 LatticeXP2 Memory Usage Guide July 2011 Technical Note TN1137 Introduction This technical note discusses memory usage for the LatticeXP2TM device family. It is intended to be used by design engineers as a guide for integrating the User TAG, EBR- (Embedded Block RAM) and PFU-based memories in this device family using the ispLEVER(R) design tool. The architecture of these devices provides resources for FPGA on-chip memory applications. The sysMEMTM EBR complements the distributed PFU-based memory. Single-Port RAM, Dual-Port RAM, Pseudo Dual-Port RAM, FIFO and ROM memories can be constructed using the EBR. LUTs and PFU can implement Distributed Single-Port RAM, Dual-Port RAM and ROM. User TAG memories in varying sizes, depending on the specific chip, are also on the device. The capabilities of the User TAG memory, EBR RAM and PFU RAM are referred to as primitives and are described later in this document. Designers can utilize the memory primitives in two ways via the IPexpressTM tool in the ispLEVER software. The IPexpress GUI allows users to specify the memory type and size required. IPexpress takes this specification and constructs a netlist to implement the desired memory by using one or more of the memory primitives. The remainder of this document discusses the use of IPexpress, memory modules and memory primitives. Memories in LatticeXP2 Devices There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional Unit without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM and register functions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks are optimized for flexibility allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a two-dimensional array. Only one type of block is used per row. The LatticeXP2 family of devices contains up to two rows of sysMEM EBR blocks. sysMEM EBRs are large, dedicated 18K fast memory blocks. Each sysMEM block can be configured in a variety of depths and widths of RAM or ROM. Each LatticeXP2 device also contains one dedicated row of User TAG memory with up to 451 bytes of space. Table 10-1. LatticeXP2 LUT and Memory Densities Parameter XP2-5 XP2-8 XP2-17 XP2-30 XP2-40 EBR Rows 1 1 1 1 2 EBR Blocks 9 12 15 21 48 EBR Bits 165888 221184 276480 387072 884736 Distributed RAM Bits 10368 18432 34560 64512 82944 Total Memory Bits 176256 239616 311040 451584 967680 (c) 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 10-1 tn1137_01.9 Lattice Semiconductor LatticeXP2 Memory Usage Guide Figure 10-1. Simplified Block Diagram, LatticeXP2 Device (Top Level) sysIO Buffers, Pre-Engineered Source Synchronous Support On-chip Oscillator Programmable Function Units (PFUs) SPI Port sysMEM Block RAM JTAG Port DSP Blocks Flash sysCLOCK PLLs Flexible Routing Utilizing IPexpress Designers can utilize IPexpress to easily specify a variety of memories in their designs. These modules are constructed using one or more memory primitives along with general purpose routing and LUTs, as required. The available primitives are: * Single Port RAM (RAM_DQ) - EBR-based * Dual PORT RAM (RAM_DP_TRUE) - EBR-based * Pseudo Dual Port RAM (RAM_DP) - EBR-based * Read Only Memory (ROM) - EBR-Based * First In First Out Memory (Dual Clock) (FIFO_DC) - EBR-based * Distributed Single Port RAM (Distributed_SPRAM) - PFU-based * Distributed Dual Port RAM (Distributed_DPRAM) - PFU-based * Distributed ROM (Distributed_ROM) - PFU/PFF-based * User TAG memory (SSPIA) - TAG-based 10-2 Lattice Semiconductor LatticeXP2 Memory Usage Guide IPexpress Flow For generating any of these memories, create (or open) a project for the LatticeXP2 devices. From the Project Navigator, select Tools > IPexpress or click on the button in the toolbar when LatticeXP2 devices are targeted in the project. This opens the IPexpress main window as shown in Figure 10-2. Figure 10-2. IPexpress - Main Window The left pane of this window includes the Module Tree. The EBR-based Memory Modules are under the EBR_Components and the PFU-based Distributed Memory Modules are under Storage_Components, as shown in Figure 10-2. As an example, let us consider generating an EBR-based Pseudo Dual Port RAM of size 512x16. Select RAM_DP under EBR_Components. The right pane changes as shown in Figure 10-3. 10-3 Lattice Semiconductor LatticeXP2 Memory Usage Guide Figure 10-3. Example Generating Pseudo Dual Port RAM (RAM_DP) Using IPexpress In the right pane, options like the Device Family, Macro Type, Category, and Module_Name are device and selected module dependent. These cannot be changed in IPexpress. Users can change the directory where the generated module files will be placed by clicking the Browse button in the Project Path. The Module Name text box allows users to specify an entity name for the module they are about to generate. Users must provide this entity name. Design entry, Verilog or VHDL, by default, is the same as the project type. If the project is a VHDL project, the selected design entry option will be "Schematic/ VHDL", and "Schematic/ Verilog-HDL" if the project type is VerilogHDL. The Device pull-down menu allows users to select different devices within the same family, LatticeXP2 in this example. By clicking the Customize button, another window opens where users can customize the RAM (Figure 10-4). 10-4 Lattice Semiconductor LatticeXP2 Memory Usage Guide Figure 10-4. Example Generating Pseudo Dual Port RAM (RAM_DP) Module Customization The left side of this window shows the block diagram of the module. The right side includes the Configuration tab where users can choose options to customize the RAM_DP (e.g. specify the address port sizes and data widths). Users can specify the address depth and data width for the Read Port and the Write Port in the text boxes provided. In this example, we are generating a Pseudo Dual Port RAM of size 512 x 16. Users can also create RAMs of different port widths for Pseudo Dual Port and True Dual Port RAMs. The Input Data and the Address Control are always registered, as the hardware only supports the clocked write operation for the EBR based RAMs. The check box Enable Output Registers inserts the output registers in the Read Data Port. Output registers are optional for EBR-based RAMs. Users have the option to set the Reset Mode as Asynchronous Reset or Synchronous Reset. Enable GSR can be checked to enable the Global Set Reset. Users can also pre-initialize their memory with the contents specified in the Memory File. It is optional to provide this file in the RAM; however for ROM, the Memory File is required. These files can be of Binary, Hex or Addresses Hex format. The details of these formats are discussed in the Initialization File section of this document. At this point, users can click the Generate button to generate the module they have customized. A VHDL or Verilog netlist is then generated and placed in the specified location. Users can incorporate this netlist in their designs. Another important button is the Load Parameters button. IPexpress stores the parameters specified in a <module_name>.lpc file. This file is generated along with the module. Users can click on the Load Parameters button to load the parameters of a previously generated module to re-visit or make changes to them. Once the module is generated, users can either instantiate the *.lpc or the Verilog-HDL/ VHDL file in top-level module of their design. 10-5 Lattice Semiconductor LatticeXP2 Memory Usage Guide The various memory modules, both EBR and distributed, are discussed in detail in this document. Memory Modules ECC is supported in most memories. If you choose to use ECC, you will have a 2-bit error signal. * When Error[1:0]=00, there is no error. * When Error[0]=1, it indicates that there was a 1 bit error which was fixed. * When Error[1]=1, it indicates that there was a 2-bit error which cannot be corrected. Single Port RAM (RAM_DQ) - EBR Based The EBR blocks in LatticeXP2 devices can be configured as Single Port RAM or RAM_DQ. IPexpress allows users to generate the Verilog-HDL or VHDL along EDIF netlist for the memory size as per design requirements. IPexpress generates the memory module as shown in Figure 10-5. Figure 10-5. Single Port Memory Module Generated by IPexpress Clock ClockEn Reset WE RAM_DQ EBR-based Single Port Memory Q Address Data Since the device has a number of EBR blocks, the generated module makes use of these EBR blocks, or primitives, and cascades them to create the memory sizes specified by the user in the IPexpress GUI. For memory sizes smaller than an EBR block, the module will be created in one EBR block. For memory sizes larger than one EBR block, multiple EBR blocks can be cascaded in depth or width (as required to create these sizes). In Single Port RAM mode, the input data and address for the ports are registered at the input of the memory array. The output data of the memory is optionally registered at the output. The various ports and their definitions for the Single Port Memory are listed in Table 10-2. The table lists the corresponding ports for the module generated by IPexpress and for the EBR RAM_DQ primitive. 10-6 Lattice Semiconductor LatticeXP2 Memory Usage Guide Table 10-2. EBR-based Single Port Memory Port Definitions Port Name in Generated Module Port Name in the EBR Block Primitive Description Active State Clock CLK Clock Rising Clock Edge ClockEn CE Clock Enable Active High Address AD[x:0] Address Bus -- Data DI[y:0] Data In -- Q DO[y:0] Data Out -- WE WE Write Enable Active High Reset RST Reset Active High -- CS[2:0] Chip Select -- Reset (or RST) resets only the input and output registers of the RAM. It does not reset the contents of the memory. Chip Select (CS) is a useful port in the EBR primitive when multiple cascaded EBR blocks are required by the memory. The CS signal forms the MSB for the address when multiple EBR blocks are cascaded. CS is a 3-bit bus, so it can cascade eight memories easily. If the memory size specified by the user requires more than eight EBR blocks, the ispLEVER software automatically generates the additional address decoding logic, which is implemented in the PFU (external to the EBR blocks). Each EBR block consists of 18,432 bits of RAM. The values for x (address) and y (data) for each EBR block for the devices are listed in Table 10-3. Table 10-3. Single Port Memory Sizes for 16K Memories for LatticeXP2 Single Port Memory Size Input Data Output Data Address [MSB:LSB] 16K x 1 DI DO AD[13:0] 8K x 2 DI[1:0] DO[1:0] AD[12:0] 4K x 4 DI[3:0] DO[3:0] AD[11:0] 2K x 9 DI[8:0] DO[8:0] AD[10:0] 1K x 18 DI[17:0] DO[17:0] AD[9:0] 512 x 36 DI[35:0] DO[35:0] AD[8:0] Table 10-4 shows the various attributes available for the Single Port Memory (RAM_DQ). Some of these attributes are user-selectable through the IPexpress GUI. For detailed attribute definitions, refer to Appendix A. 10-7 Lattice Semiconductor LatticeXP2 Memory Usage Guide Table 10-4. Single Port RAM Attributes for LatticeXP2 Attribute Description Values User Selectable Default Value Through IPexpress Address depth Address Depth Read Port 16K, 8K, 4K, 2K, 1K, 512 YES Data Width Data Word Width Read Port 1, 2, 4, 9, 18, 36 1 YES Enable Output Registers Register Mode (Pipelining) for Write Port NOREG, OUTREG NOREG YES Enable GSR Enables Global Set Reset ENABLE, DISABLE ENABLE YES Reset Mode Selects the Reset type ASYNC, SYNC ASYNC YES BINARY, HEX, ADDRESSED HEX Memory File Format YES Write Mode Read / Write Mode for Write Port NORMAL, WRITETHROUGH NORMAL YES Chip Select Decode Chip Select Decode for Read Port 0b000, 0b001, 0b010, 0b011, 0b100, 0b101, 0b110, 0b111 0b000 NO Initialization value 0x000000000000000000000 00000000000000000000000 00000000000000000000000 0000000000000......0xFFFF FFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFF 0x000000000 00000000000 00000000000 00000000000 00000000000 00000000000 00000000000 00000 NO Init Value The Single Port RAM (RAM_DQ) can be configured as NORMAL or WRITE THROUGH modes. Each of these modes affects the data coming out of port Q of the memory during the write operation followed by the read operation at the same memory location. Additionally, users can select to enable the output registers for RAM_DQ. Figures 10-6-10-9 show the internal timing waveforms for the Single Port RAM (RAM_DQ) with these options. It is important that no setup and hold time violations occur on the address registers (Address). Failing to to meet these requirements can result in corruption of memory contents. This applies to both read and write operations. A Post Place and Route timing report in Lattice Diamond(R) or ispLEVER design software can be run to verify that no such timing errors occur. Refer to the timing preferences in the Online Help documents. 10-8 Lattice Semiconductor LatticeXP2 Memory Usage Guide Figure 10-6. Single Port RAM Timing Waveform - NORMAL Mode, without Output Registers Clock tSUCE_EBR t HCE_EBR ClockEn tSUWREN_EBR tHWREN_EBR WrEn tSUADDR_EBR t HADDR_EBR Address Add_0 Add_1 Data Data_0 Data_1 t SUDATA_EBR Add_0 Add_1 Add_2 t HDATA_EBR Q Invalid Data Data_0 Data_1 Data_2 t CO_EBR Figure 10-7. Single Port RAM Timing Waveform - NORMAL Mode, with Output Registers Reset Clock tSUCE_EBR tHCE_EBR ClockEn tSUWREN_EBR t HWREN_EBR WrEn tSUADDR_EBR tHADDR_EBR Address Add_0 Add_1 Data Data_0 Data_1 tSUDATA_EBR Q Add_0 Add_1 Add_2 t HDATA_EBR Invalid Data Data_0 t COO_EBR 10-9 Data_1 Lattice Semiconductor LatticeXP2 Memory Usage Guide Figure 10-8. Single Port RAM Timing Waveform - WRITE THROUGH Mode, without Output Registers Clock t SUCE_EBR t HCE_EBR ClockEn t SUWREN_EBR t HWREN_EBR WrEn tSUADDR_EBR t HADDR_EBR Address Add_0 Add_1 Data Data_0 Data_1 t SUDATA_EBR Q Add_0 Data_2 Data_3 Data_4 t HDATA_EBR Invalid Data Data_0 Data_1 Data_2 Data_3 Data_4 t CO_EBR Figure 10-9. Single Port RAM Timing Waveform - WRITE THROUGH Mode, with Output Registers Reset Clock t SUCE_EBR t HCE_EBR ClockEn t SUWREN_EBR t HWREN_EBR WrEn t SUADDR_EBR t HADDR_EBR Address Add_0 Add_1 Data Data_0 Data_1 t SUDATA_EBR Q Add_0 Data_2 Data_3 Data_4 t HDATA_EBR Invalid Data Data_0 Data_1 t COO_EBR 10-10 Data_2 Data_3 Lattice Semiconductor LatticeXP2 Memory Usage Guide True Dual Port RAM (RAM_DP_TRUE) - EBR Based The EBR blocks in the LatticeXP2 devices can be configured as True-Dual Port RAM or RAM_DP_TRUE. IPexpress allows users to generate the Verilog-HDL, VHDL or EDIF netlists for the memory size as per design requirements. IPexpress generates the memory module as shown in Figure 10-10. Figure 10-10. True Dual Port Memory Module Generated by IPexpress ClockA ClockB ClockEnA ClockEnB ResetA ResetB RAM_DP_TRUE WrA AddressA EBR-based True Dual Port Memory WrB AddressB DataInB DataInA QB QA The generated module makes use of these EBR blocks or primitives. For memory sizes smaller than an EBR block, the module will be created in one EBR block. When the specified memory is larger than one EBR block, multiple EBR blocks can be cascaded in depth or width (as required to create these sizes). In True Dual Port RAM mode, the input data and address for the ports are registered at the input of the memory array. The output data of the memory is optionally registered at the output. The various ports and their definitions for Single Port Memory are listed in Table 10-5. The table lists the corresponding ports for the module generated by IPexpress and for the EBR RAM_DP_TRUE primitive. Table 10-5. EBR-based True Dual Port Memory Port Definitions Port Name in Generated Module Port Name in the EBR Block Primitive Description ClockA, ClockB CLKA, CLKB Clock for PortA and PortB ClockEnA, ClockEnB CEA, CEB Clock Enables for Port CLKA and CLKB AddressA, AddressB ADA[x1:0], ADB[x2:0] Address Bus Port A and Port B Active State Rising Clock Edge Active High -- DataA, DataB DIA[y1:0], DIB[y2:0] Input Data Port A and Port B -- QA, QB DOA[y1:0], DOB[y2:0] Output Data Port A and Port B -- WrA, WrB WEA, WEB Write Enable Port A and Port B Active High ResetA, ResetB RSTA, RSTB Reset for Port A and Port B Active High -- CSA[2:0], CSB[2:0] Chip Selects for each port -- Reset (or RST) resets only the input and output registers of the RAM. It does not reset the contents of the memory. Chip Select (CS) is a useful port in the EBR primitive when multiple cascaded EBR blocks are required by the memory. The CS signal forms the MSB for the address when multiple EBR blocks are cascaded. Since CS is a 3bit bus, it can cascade eight memories easily. However, if the memory size specified by the user requires more than eight EBR blocks, the ispLEVER software automatically generates the additional address decoding logic, which is implemented in the PFU external to the EBR blocks. 10-11 Lattice Semiconductor LatticeXP2 Memory Usage Guide Each EBR block consists of 18,432 bits of RAM. The values for x's (for address) and y's (data) for each EBR block for the devices are listed in Table 10-6. Table 10-6. True Dual Port Memory Sizes for 16K Memory for LatticeXP2 Dual Port Memory Size Input Data Port A Input Data Port B Output Data Port A Output Data Port B Address Port A Address Port B [MSB:LSB] [MSB:LSB] 16K x 1 DIA DIB DOA DOB ADA[13:0] ADB[13:0] 8K x 2 DIA[1:0] DIB[1:0] DOA[1:0] DOB[1:0] ADA[12:0] ADB[12:0] 4K x 4 DIA[3:0] DIB[3:0] DOA[3:0] DOB[3:0] ADA[11:0] ADB[11:0] 2K x 9 DIA[8:0] DIB[8:0] DOA[8:0] DOB[8:0] ADA[10:0] ADB[10:0] 1K x 18 DIA[17:0] DIB[17:0] DOA[17:0] DOB[17:0] ADA[9:0] ADB[9:0] Table 10-7 shows the various attributes available for the Single Port Memory (RAM_DQ). Some of these attributes are user-selectable through the IPexpress GUI. For detailed attribute definitions, refer to the Appendix A. Table 10-7. True Dual Port RAM Attributes for LatticeXP2 Attribute Description Values Port A Address depth Address Depth Port A 16K, 8K, 4K, 2K, 1K Port A Data Width Data Word Width Port A 1, 2, 4, 9, 18 Port B Address depth Address Depth Port B 16K, 8K, 4K, 2K, 1K Port B Data Width Data Word Width Port B 1, 2, 4, 9, 18 Port A Enable Output Registers Register Mode (Pipelining) for Port A Port B Enable Output Registers Register Mode (Pipelining) for Port B Default Value User Selectable Through IPexpress 1 YES YES YES 1 YES NOREG, OUTREG NOREG YES NOREG, OUTREG NOREG YES Enable GSR Enables Global Set Reset ENABLE, DISABLE ENABLE YES Reset Mode Selects the Reset type ASYNC YES ASYNC, SYNC BINARY, HEX, ADDRESSED HEX Memory File Format YES Port A Write Mode Read / Write Mode for Port A NORMAL, WRITETHROUGH NORMAL YES Port B Write Mode Read / Write Mode for Port B NORMAL, WRITETHROUGH NORMAL YES Chip Select Decode for Port A Chip Select Decode for Port A 0b000, 0b001, 0b010, 0b011, 0b100, 0b101, 0b110, 0b111 0b000 NO Chip Select Decode for Port B Chip Select Decode for Port B 0b000, 0b001, 0b010, 0b011, 0b100, 0b101, 0b110, 0b111 0b000 NO Initialization value 0x00000000000000000000 0000000000000000000000 0000000000000000000000 0000000000000000......0xF FFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFF 0x000000000 00000000000 00000000000 00000000000 00000000000 00000000000 00000000000 00000 NO Init Value 10-12 Lattice Semiconductor LatticeXP2 Memory Usage Guide The True Dual Port RAM (RAM_DP_TRUE) can be configured as NORMAL or WRITE THROUGH modes. Each of these modes affects what data comes out of the port Q of the memory during the write operation followed by the read operation at the same memory location. The detailed discussions of the WRITE modes and the constraints of the True Dual Port can be found in Appendix A. Additionally, users can select to enable the output registers for RAM_DP_TRUE. Figures 10-11 through 10-14 show the internal timing waveforms for the True Dual Port RAM (RAM_DP_TRUE) with these options. It is important that no setup and hold time violations occur on the address registers (AddressA and AddressB). Failing to to meet these requirements can result in corruption of memory contents. This applies to both read and write operations. A Post Place and Route timing report in Lattice Diamond or ispLEVER design software can be run to verify that no such timing errors occur. Refer to the timing preferences in the Online Help documents. Figure 10-11. True Dual Port RAM Timing Waveform - NORMAL Mode, without Output Registers ClockA tSUCE_EBR tHCE_EBR ClockEnA tSUWREN_EBR t HWREN_EBR WrEnA tSUADDR_EBR t HADDR_EBR AddressA Add_A0 Add_A1 DataA Data_A0 Data_A1 t SUDATA_EBR Add_A0 Add_A1 Add_A2 t HDATA_EBR Invalid Data QA Data_A0 Data_A1 Data_A2 tCO_EBR ClockB t SUCE_EBR tHCE_EBR ClockEnB t SUWREN_EBR t HWREN_EBR WrEnB tSUADDR_EBR t HADDR_EBR AddressB Add_B0 Add_B1 DataB Data_B0 Data_B1 tSUDATA_EBR QB Add_B0 Add_B1 Add_B2 Data_B0 Data_B1 tHDATA_EBR Invalid Data tCO_EBR 10-13 Data_B2 Lattice Semiconductor LatticeXP2 Memory Usage Guide Figure 10-12. True Dual Port RAM Timing Waveform - NORMAL Mode with Output Registers Reset ClockA t SUCE_EBR t HCE_EBR ClockEnA t SUWREN_EBR t HWREN_EBR WrEnA tSUADDR_EBR AddressA DataA t HADDR_EBR Add_A0 Add_A1 Data_A0 Data_A1 t SUDATA_EBR Add_A0 Add_A1 Add_A2 t HDATA_EBR QA Invalid Data Data_A0 Data_A1 t COO_EBR ClockB t SUCE_EBR t HCE_EBR ClockEnB tSUWREN_EBR t HWREN_EBR WrEnB t SUADDR_EBR t HADDR_EBR AddressB Add_B0 Add_B1 DataB Data_B0 Data_B1 t SUDATA_EBR QB Add_B0 Add_B1 Add_B2 t HDATA_EBR Invalid Data Data_B0 t COO_EBR 10-14 Data_B1 Lattice Semiconductor LatticeXP2 Memory Usage Guide Figure 10-13. True Dual Port RAM Timing Waveform - WRITE THROUGH Mode, without Output Registers ClockA t SUCE_EBR tHCE_EBR ClockEnA t SUWREN_EBR tHWREN_EBR WrEnA t SUADDR_EBR t HADDR_EBR AddressA Add_A0 Add_A1 DataA Data_A0 Data_A1 t SUDATA_EBR QA Add_A0 Data_A2 Data_A3 Data_A4 t HDATA_EBR Invalid Data Data_A0 Data_A1 Data_A2 Data_A3 Data_A4 tCO_EBR ClockB tSUCE_EBR t HCE_EBR ClockEnB t SUWREN_EBR t HWREN_EBR WrEnB tSUADDR_EBR tHADDR_EBR AddressB Add_B0 Add_B1 DataB Data_B0 Data_B1 t SUDATA_EBR QB Invalid Data Add_B0 Data_B2 Data_B3 Data_B4 tHDATA_EBR Data_B0 Data_B1 t CO_EBR 10-15 Data_B2 Data_B3 Data_B4 Lattice Semiconductor LatticeXP2 Memory Usage Guide Figure 10-14. True Dual Port RAM Timing Waveform - WRITE THROUGH Mode, with Output Registers Reset ClockA tSUCE_EBR t HCE_EBR ClockEnA t SUWREN_EBR t HWREN_EBR WrEnA tSUADDR_EBR t HADDR_EBR AddressA Add_0 Add_1 DataA Data_0 Data_1 t SUDATA_EBR QA Add_0 Data_2 Data_3 Data_4 t HDATA_EBR Invalid Data Data_0 Data_1 Data_2 Data_3 t COO_EBR ClockB t HCE_EBR tSUCE_EBR ClockEnB tSUWREN_EBR t HWREN_EBR WrEnB tSUADDR_EBR t HADDR_EBR AddressB Add_0 Add_1 DataB Data_0 Data_1 t SUDATA_EBR QB Add_0 Data_2 Data_3 Data_4 t HDATA_EBR Invalid Data Data_0 Data_1 t COO_EBR 10-16 Data_2 Data_3 Lattice Semiconductor LatticeXP2 Memory Usage Guide Pseudo Dual Port RAM (RAM_DP) - EBR Based The EBR blocks in LatticeXP2 devices can be configured as Pseudo-Dual Port RAM or RAM_DP. IPexpress allows users to generate the Verilog-HDL or VHDL along with EDIF netlists for the memory size as per design requirements. IPexpress generates the memory module as shown in Figure 10-15. Figure 10-15. Pseudo Dual Port Memory Module Generated by IPexpress WrClock RdClock WrClockEn RdClockEn RAM_DP Reset WE EBR based Pseudo Dual Port Memory WrAddress RdAddress Data Q The generated module makes use of these EBR blocks or primitives. For memory sizes smaller than an EBR block, the module will be created in one EBR block. If the specified memory is larger than one EBR block, multiple EBR blocks can be cascaded in depth or width (as required to create these sizes). In Pseudo Dual Port RAM mode, the input data and address for the ports are registered at the input of the memory array. The output data of the memory is optionally registered at the output. The various ports and their definitions for the Single Port Memory are listed in Table 10-8. The table lists the corresponding ports for the module generated by IPexpress and for the EBR RAM_DP primitive. Table 10-8. EBR-based Pseudo-Dual Port Memory Port Definitions Port Name in Generated Module Port Name in the EBR Block Primitive Description Active State RdAddress ADR[x1:0] Read Address -- WrAddress ADW[x2:0] Write Address -- RdClock CLKR Read Clock Rising Clock Edge WrClock CLKW Write Clock Rising Clock Edge RdClockEn CER Read Clock Enable Active High WrClockEn CEW Write Clock Enable Active High Q DO[y1:0] Read Data -- Data DI[y2:0] Write Data -- WE WE Write Enable Active High Reset RST Reset Active High -- CS[2:0] Chip Select -- Reset (RST) resets only the input and output registers of the RAM. It does not reset the contents of the memory. Chip Select (CS) is a useful port when multiple cascaded EBR blocks are required by the memory. The CS signal forms the MSB for the address when multiple EBR blocks are cascaded. Since CS is a 3-bit bus, it can cascade eight memories easily. However, if the memory size specified by the user requires more than eight EBR blocks, the ispLEVER software automatically generates the additional address decoding logic, which is implemented in the PFU external to the EBR blocks. 10-17 Lattice Semiconductor LatticeXP2 Memory Usage Guide Each EBR block consists of 18,432 bits of RAM. The values for x's (for address) and y's (data) for each EBR block for the devices are as in Table 10-9. Table 10-9. Pseudo-Dual Port Memory Sizes for 16K Memory for LatticeXP2 Pseudo-Dual Port Memory Size Input Data Port A Input Data Port B Output Data Port A Output Data Port B Read Address Port A [MSB:LSB] Write Address Port B [MSB:LSB] 16K x 1 DIA DIB DOA DOB RAD[13:0] WAD[13:0] 8K x 2 DIA[1:0] DIB[1:0] DOA[1:0] DOB[1:0] RAD[12:0] WAD[12:0] 4K x 4 DIA[3:0] DIB[3:0] DOA[3:0] DOB[3:0] RAD[11:0] WAD[11:0] 2K x 9 DIA[8:0] DIB[8:0] DOA[8:0] DOB[8:0] RAD[10:0] WAD[10:0] 1K x 18 DIA[17:0] DIB[17:0] DOA[17:0] DOB[17:0] RAD[9:0] WAD[9:0] 512 x 36 DIA[35:0] DIB[35:0] DOA[35:0] DOB[35:0] RAD[8:0] WAD[8:0] Table 10-10 shows the various attributes available for the Pseudo-Dual Port Memory (RAM_DP). Some of these attributes are user-selectable through the IPexpress GUI. For detailed attribute definitions, refer to Appendix A. Table 10-10. Pseudo-Dual Port RAM Attributes for LatticeXP2 Attribute Description Values Read Port Address Depth Address Depth Read Port 16K, 8K, 4K, 2K, 1K, 512 Read Port Data Width Data Word Width Read Port 1, 2, 4, 9, 18, 36 Write Port Address Depth Address Depth Write 16K, 8K, 4K, 2K, 1K Port Write Port Data Width Data Word Width Write Port Write Port Enable Output Registers 1, 2, 4, 9, 18, 36 Default Value User Selectable Through IPexpress YES 1 YES YES 1 YES Register Mode (Pipelining) for Write NOREG, OUTREG Port NOREG YES Enable GSR Enables Global Set Reset ENABLE, DISABLE ENABLE YES Reset Mode Selects the Reset type ASYNC, SYNC ASYNC YES BINARY, HEX, ADDRESSED HEX Memory File Format YES Read Port Write Mode Read / Write Mode for Read Port NORMAL NORMAL YES Write Port Write Mode Read / Write Mode for Write Port NORMAL NORMAL YES Chip Select Decode for Read Port Chip Select Decode 0b000, 0b001, 0b010, 0b011, for Read Port 0b100, 0b101, 0b110, 0b111 0b000 NO Chip Select Decode for Write Port Chip Select Decode 0b000, 0b001, 0b010, 0b011, for Write Port 0b100, 0b101, 0b110, 0b111 0b000 NO 0x000000000000 00000000000000 00000000000000 00000000000000 00000000000000 000000000000 NO Init Value Initialization value 0x0000000000000000000000000 000000000000000000000000000 000000000000000000000000000 0......0xFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFF 10-18 Lattice Semiconductor LatticeXP2 Memory Usage Guide Users have the option to enable the output registers for Pseudo-Dual Port RAM (RAM_DP). Figures 10-16 and 1017 show the internal timing waveforms for Pseudo-Dual Port RAM (RAM_DP) with these options. It is important that no setup and hold time violations occur on the address registers (RdAddress and WrAddress). Failing to meet these requirements can result in corruption of memory contents. This applies to both read and write operations. A Post Place and Route timing report in Lattice Diamond or ispLEVER design software can be run to verify that no such timing errors occur. Refer to the timing preferences in the Online Help documents. Figure 10-16. PSEUDO DUAL PORT RAM Timing Diagram - without Output Registers WrClock tSUCE_EBR tHCE_EBR WrClockEn RdClock t SUCE_EBR tHCE_EBR RdClockEn t HADDR_EBR t SUADDR_EBR Add_0 WrAddress Add_1 Add_2 t HADDR_EBR t SUADDR_EBR Add_0 RdAddress Data_0 Data t SUDATA_EBR Q Add_1 Data_1 Add_2 Data_2 t HDATA_EBR Invalid Data Data_0 t CO_EBR 10-19 Data_1 Dat a_2 Lattice Semiconductor LatticeXP2 Memory Usage Guide Figure 10-17. PSEUDO DUAL PORT RAM Timing Diagram - with Output Registers WrClock t SUCE_EBR t HCE_EBR WrClockEn RdClock t SUCE_EBR tHCE_EBR RdClockEn t HADDR_EBR t SUADDR_EBR Add_0 WrAddress Add_1 Add_2 tHADDR_EBR t SUADDR_EBR Add_0 RdAddress Data_0 Data t SUDATA_EBR Add_1 Data_1 Add_2 Data_2 t HDATA_EBR Invalid Data Q Data_0 Dat a_1 t COO_EBR Read Only Memory (ROM) - EBR Based The EBR blocks in the LatticeXP2 devices can be configured as Read Only Memory or ROM. IPexpress allows users to generate the Verilog-HDL or VHDL and the EDIF netlist for the memory size, as per design requirements. Users are required to provide the ROM memory content in the form of an initialization file. IPexpress generates the memory module as shown in Figure 10-18. Figure 10-18. Read-Only Memory Module Generated by IPexpress OutClock OutClockEn Reset ROM EBR based Read Only Memory Q Address The generated module makes use of these EBR blocks or primitives. For memory sizes smaller than an EBR block, the module will be created in one EBR block. If the specified memory is larger than one EBR block, multiple EBR blocks can be cascaded, in depth or width (as required to create these sizes). In ROM mode, the address for the port is registered at the input of the memory array. The output data of the memory is optionally registered at the output. 10-20 Lattice Semiconductor LatticeXP2 Memory Usage Guide The various ports and their definitions for the ROM are listed in Table 10-11. The table lists the corresponding ports for the module generated by IPexpress and for the ROM primitive. Table 10-11. EBR-based ROM Port Definitions Port Name in Generated Module Port Name in the EBR block Primitive Description Active State Address AD[x:0] Read Address -- OutClock CLK Clock Rising Clock Edge OutClockEn CE Clock Enable Active High Reset RST Reset Active High -- CS[2:0] Chip Select -- Reset (RST) resets only the input and output registers of the RAM. It does not reset the contents of the memory. Chip Select (CS) is a useful port when multiple cascaded EBR blocks are required by the memory. The CS signal forms the MSB for the address when multiple EBR blocks are cascaded. Since CS is a 3-bit bus, it can cascade eight memories easily. However, if the memory size specified by the user requires more than eight EBR blocks, the ispLEVER software automatically generates the additional address decoding logic, which is implemented in the PFU external to the EBR blocks. While generating the ROM using IPexpress, the user must provide the initialization file to pre-initialize the contents of the ROM. These files are the *.mem files and they can be of Binary, Hex or the Addressed Hex formats. The initialization files are discussed in detail in the Initializing Memory section of this document. Users have the option of enabling the output registers for Read Only Memory (ROM). Figures 10-19 and 10-20 show the internal timing waveforms for the Read Only Memory (ROM) with these options. Each EBR block consists of 18,432 bits of RAM. The values for x's (for address) and y's (data) for each EBR block for the devices are as per Table 10-12. Table 10-12. ROM Memory Sizes for 16K Memory for LatticeXP2 Output Data Address Port [MSB:LSB] 16K x 1 DOA WAD[13:0] 8K x 2 DOA[1:0] WAD[12:0] 4K x 4 DOA[3:0] WAD[11:0] ROM 2K x 9 DOA[8:0] WAD[10:0] 1K x 18 DOA[17:0] WAD[9:0] 512 x 36 DOA[35:0] WAD[8:0] Table 10-13 shows the various attributes available for the Read Only Memory (ROM). Some of these attributes are user-selectable through the IPexpress GUI. For detailed attribute definitions, refer to Appendix A. 10-21 Lattice Semiconductor LatticeXP2 Memory Usage Guide Table 10-13. Pseudo-Dual Port RAM Attributes for LatticeXP2 Attribute Description Default Value Values Address depth Address Depth Read Port 16K, 8K, 4K, 2K, 1K, 512 Data Width Data Word Width Read Port 1, 2, 4, 9, 18, 36 User Selectable Through IPexpress YES 1 YES Enable Output Registers Register Mode (Pipelining) for Write Port NOREG, OUTREG NOREG YES Enable GSR Enables Global Set Reset ENABLE, DISABLE ENABLE YES Reset Mode Selects the Reset type ASYNC, SYNC ASYNC YES BINARY, HEX, ADDRESSED HEX Memory File Format Chip Select Decode Chip Select Decode for Read Port 0b000, 0b001, 0b010, 0b011, 0b100, 0b101, 0b110, 0b111 YES 0b000 NO Users have the option to enable the output registers for Read Only Memory (ROM). Figures 10-19 and 10-20 show the internal timing waveforms for ROM with these options. It is important that no setup and hold time violations occur on the address registers (Address). Failing to to meet these requirements can result in corruption of memory contents. This applies to both read operations in this case. A Post Place and Route timing report in Lattice Diamond or ispLEVER design software can be run to verify that no such timing errors occur. Refer to the timing preferences in the Online Help documents. Figure 10-19. ROM Timing Waveform - Without Output Registers OutClock t SUCE_EBR t HCE_EBR OutClockEn Add_0 Address tSUADDR_EBR Q Invalid Data Add_1 Add_2 Add_3 Add_4 Data_1 Data_2 Data_3 tHADDR_EBR Data_0 t CO_EBR 10-22 Data_4 Lattice Semiconductor LatticeXP2 Memory Usage Guide Figure 10-20. ROM Timing Waveform - with Output Registers OutClock t SUCE_EBR t HCE_EBR OutClockEn Address Add_0 tSUADDR_EBR Q Add_1 Add_2 Add_3 Add_4 t HADDR_EBR Invalid Data Data_0 Data_1 Data_2 Data_3 t COO_EBR First In First Out (FIFO, FIFO_DC) - EBR Based FIFOs are not supported in certain devices such as the LatticeECP/EC, LatticeECP2/M, LatticeXP and MachXO. The hardware has Embedded Block RAM (EBR) which can be configured in Single Port (RAM_DQ), Pseudo-Dual Port (RAM_DP) and True Dual Port (RAM_DP_TRUE) RAMs. The FIFOs in these devices can be emulated FIFOs that are built around these RAMs. The IPexpress point tool in the ispLEVER design software allows users to build a FIFO and FIFO_DC around Pseudo Dual Port RAM (or DP_RAM). Each of these FIFOs can be configured with (pipelined) and without (non-pipelined) output registers. In the pipelined mode users have an extra option to enable the output registers by the RdEn signal. We will discuss the operation in the following sections. Let us take a look at the operation of these FIFOs. First In First Out (FIFO) Memory The FIFO, or the single clock FIFO, is an emulated FIFO. The address logic and the flag logic is implemented in the FPGA fabric around the RAM. The ports available on the FIFO are: * Reset * Clock * WrEn * RdEn * Data * Q * Full Flag * Almost Full Flag * Empty Flag * Almost Empty Flag Let us first discuss the non-pipelined or the FIFO without output registers. Figure 10-21 shows the operation of the FIFO when it is empty and the data starts to get written into it. 10-23 Lattice Semiconductor LatticeXP2 Memory Usage Guide Figure 10-21. FIFO without Output Registers, Start of Data Write Cycle Reset Clock WrEn RdEn Data Invalid Data Data_1 Data_2 Q Data_3 Data_4 Data_5 Invalid Q Empty Almost Empty Full Almost Full The WrEn signal must be high to start writing into the FIFO. The Empty and Almost Empty flags are high to begin and Full and Almost Full are low. When the first data is written into the FIFO, the Empty flag de-asserts (or goes low), as the FIFO is no longer empty. In this figure we assume that the Almost Empty setting flag setting is 3 (address location 3). So the Almost Empty flag gets de-asserted when the third address location is filled. Now let us assume that we continue to write into the FIFO to fill it. When the FIFO is filled, the Almost Full and Full Flags are asserted. Figure 10-22 shows the behavior of these flags. In this figure we assume that FIFO depth is 'N'. Figure 10-22. FIFO without Output Registers, End of Data Write Cycle Reset Clock WrEn RdEn Data Q Data_N-2 Data_N-1 Data_N Data_X Data_X Invalid Q Empty Almost Empty Full Almost Full In this case, the Almost Full flag is in the 2 location before the FIFO is filled. The Almost Full flag is asserted when the N-2 location is written, and the Full flag is asserted when the last word is written into the FIFO. 10-24 Lattice Semiconductor LatticeXP2 Memory Usage Guide Data_X data inputs do not get written as the FIFO is full (the Full flag is high). Now let us look at the waveforms when the contents of the FIFO are read out. Figure 10-23 shows the start of the read cycle. RdEn goes high and the data read starts. The Full and Almost Full flags are de-asserted, as shown. Figure 10-23. FIFO without Output Registers, Start of Data Read Cycle Reset Clock WrEn RdEn Data Q Invalid Data Invalid Data Data_1 Data_2 Data_3 Data_4 Data_5 Empty Almost Empty Full Almost Full Similarly, as the data is read out and FIFO is emptied, the Almost Empty and Empty flags are asserted. Figure 10-24. FIFO without Output Registers, End of Data Read Cycle Reset Clock WrEn RdEn Data Q Invalid Data Data_N-4 Data_N-3 Data_N-2 Data_N-1 Data_N Empty Almost Empty Full Almost Full Figures 10-21 to 10-24 show the behavior of non-pipelined FIFO or FIFO without output registers. When we pipeline the registers, the output data is delayed by one clock cycle. There is also the extra option for Output registers to be enabled by the RdEn signal. 10-25 Lattice Semiconductor LatticeXP2 Memory Usage Guide Figures 10-25 to 10-28 show the similar waveforms for the FIFO with output register and with output register enable with RdEn. It should be noted that flags are asserted and de-asserted with similar timing to the FIFO without output registers. However, it is only the data out 'Q' that is delayed by one clock cycle. Figure 10-25. FIFO with Output Registers, Start of Data Write Cycle Reset Clock WrEn RdEn Data Invalid Data Data_1 Data_2 Q Data_3 Data_4 Data_5 Invalid Q Empty Almost Empty Full Almost Full Figure 10-26. FIFO with Output Registers, End of Data Write Cycle Reset Clock WrEn RdEn Data Q Data_N-2 Data_N-1 Data_N Invalid Q Empty Almost Empty Full Almost Full 10-26 Data_X Data_X Lattice Semiconductor LatticeXP2 Memory Usage Guide Figure 10-27. FIFO with Output Registers, Start of Data Read Cycle Reset Clock WrEn RdEn Data Invalid Data Q Invalid Data Data_1 Data_2 Data_3 Data_4 Data_N-1 Data_N Empty Almost Empty Full Almost Full Figure 10-28. FIFO with Output Registers, End of Data Read Cycle Reset Clock WrEn RdEn Data Q Invalid Data Data_N-5 Data_N-4 Data_N-3 Data_N-2 Empty Almost Empty Full Almost Full And finally, if you select the option enable output register with RdEn, it still delays the data out by one clock cycle (as compared to the non-pipelined FIFO). The RdEn should also be high during that clock cycle, otherwise the data takes an extra clock cycle when the RdEn goes true. 10-27 Lattice Semiconductor LatticeXP2 Memory Usage Guide Figure 10-29. FIFO with Output Registers and RdEn on Output Registers Reset Clock WrEn RdEn Data Invalid Data Data_1 Q Data_2 Data_3 Invalid Data Data_4 Data_5 Data_1 Data_2 Empty Almost Empty Full Almost Full Dual Clock First In First Out (FIFO_DC) Memory: The FIFO_DC or the dual clock FIFO is also an emulated FIFO. Again, the address logic and the flag logic is implemented in the FPGA fabric around the RAM. The ports available on the FIFO_DC are: * Reset * RPReset * WrClock * RdClock * WrEn * RdEn * Data * Q * Full Flag * Almost Full Flag * Empty Flag * Almost Empty Flag FIFO_DC Flags The FIFO_DC, as an emulated FIFO, required the flags to be implemented in the FPGA logic around the block RAM. Because of the two clocks, the flags were required to change clock domains from read clock to write clock and vice versa. This adds latency to the flags either during assertion or de-assertion. The latency can be avoided only in one of the cases (either assertion or de-assertion) or distributed among these cases. In the current emulated FIFO_DC, there is no latency during assertion of these flags which we feel is more important. Thus, when these flags are required to go true, there is no latency. However, due to the design of the flag logic running on two clock domains, there is latency during the de-assertion. 10-28 Lattice Semiconductor LatticeXP2 Memory Usage Guide Let us assume that we start to write into the FIFO_DC to fill it. The write operation is controlled by WrClock and WrEn, however it takes extra RdClock cycles for de-assertion of the Empty and Almost Empty flags. On the other hand, de-assertion of Full and Almost Full result in the reading out of the data from the FIFO_DC. It takes extra WrClock cycles, after reading this data, for the flags to come out. With this in mind, let us look at the FIFO_DC without output registers waveforms. Figure 10-30 shows the operation of the FIFO_DC when it is empty and the data starts to be written into it. Figure 10-30. FIFO_DC without Output Registers, Start of Data Write Cycle Reset WrClock RdClock RPReset WrEn RdEn Data Q Invalid Data Data_1 Data_2 Data_3 Data_4 Data_5 Invalid Q Empty Almost Empty Full Almost Full The WrEn signal must be high to start writing into the FIFO_DC. The Empty and Almost Empty flags are high to begin and Full and Almost full are low. When the first data is written into the FIFO_DC, the Empty flag de-asserts (or goes low), as the FIFO_DC is no longer empty. In this figure we assume that the Almost Empty setting flag setting is 3 (address location 3). So the Almost Empty flag is de-asserted when the third address location is filled. Now let us assume that we continue to write into the FIFO_DC to fill it. When the FIFO_DC is filled, the Almost Full and Full Flags are asserted. Figure 10-31 shows the behavior of these flags. In this figure the FIFO_DC depth is 'N'. 10-29 Lattice Semiconductor LatticeXP2 Memory Usage Guide Figure 10-31. FIFO_DC without Output Registers, End of Data Write Cycle Reset WrClock RdClock RPReset WrEn RdEn Data Q Data_N-2 Data_N-1 Data_N Data_X Data_X Invalid Q Empty Almost Empty Full Almost Full In this case, the Almost Full flag is in the 2 location before the FIFO_DC is filled. The Almost Full flag is asserted when the N-2 location is written, and the Full flag is asserted when the last word is written into the FIFO_DC. Data_X data inputs do not get written as the FIFO_DC is full (the Full flag is high). Note that the assertion of these flags is immediate and there is no latency when they go true. Now let us look at the waveforms when the contents of the FIFO_DC are read out. Figure 10-32 shows the start of the read cycle. RdEn goes high and the data read starts. The Full and Almost Full flags are de-asserted, as shown. In this case, note that the de-assertion is delayed by two clock cycles. 10-30 Lattice Semiconductor LatticeXP2 Memory Usage Guide Figure 10-32. FIFO_DC without Output Registers, Start of Data Read Cycle Reset WrClock RdClock RPReset WrEn RdEn Data Q Invalid Data Invalid Q Data_1 Data_2 Data_3 Data_4 Data_5 Data_6 Empty Almost Empty Full Almost Full Similarly, as the data is read out, and FIFO_DC is emptied, the Almost Empty and Empty flags are asserted. Figure 10-33. FIFO_DC without Output Registers, End of Data Read Cycle Reset WrClock RdClock RPReset WrEn RdEn Data Q Invalid Data Data_N-3 Data_N-2 Data_N-1 Empty Almost Empty Full Almost Full 10-31 Data_N Data_N Lattice Semiconductor LatticeXP2 Memory Usage Guide Figure 10-33 show the behavior of non-pipelined FIFO_DC or FIFO_DC without output registers. When we pipeline the registers, the output data is delayed by one clock cycle. There is an extra option for the output registers to be enabled by the RdEn signal. Figures 10-34 to 10-37 show the similar waveforms for the FIFO_DC with output register and without output register enable with RdEn. Note that flags are asserted and de-asserted with similar timing to the FIFO_DC without output registers. However, it is only the data out 'Q' that is delayed by one clock cycle. Figure 10-34. FIFO_DC with Output Registers, Start of Data Write Cycle Reset WrClock RdClock RPReset WrEn RdEn Data Q Invalid Data Data_1 Data_2 Data_3 Invalid Q Empty Almost Empty Full Almost Full 10-32 Data_4 Data_5 Lattice Semiconductor LatticeXP2 Memory Usage Guide Figure 10-35. FIFO_DC with Output Registers, End of Data Write Cycle Reset WrClock RdClock RPReset WrEn RdEn Data Data_N-2 Data_N-1 Q Invalid Data Data_N Invalid Data Invalid Q Empty Almost Empty Full Almost Full Figure 10-36. FIFO_DC with Output Registers, Start of Data Read Cycle Reset WrClock RdClock RPReset WrEn RdEn Data Q Invalid Data Invalid Q Data_1 Data_2 Empty Almost Empty Full Almost Full 10-33 Data_3 Data_4 Data_5 Lattice Semiconductor LatticeXP2 Memory Usage Guide Figure 10-37. FIFO_DC with Output Registers, End of Data Read Cycle Reset WrClock RdClock RPReset WrEn RdEn Data Q Invalid Data Data_N-4 Data_N-3 Data_N-2 Data_1 Data_N Empty Almost Empty Full Almost Full And finally, if you select the option to enable the output register with RdEn, it still delays the data out by one clock cycle (as compared to the non-pipelined FIFO_DC). The RdEn should also be high during that clock cycle, otherwise the data takes an extra clock cycle when the RdEn is goes true. Figure 10-38. FIFO_DC with Output Registers and RdEn on Output Registers Reset WrClock RdClock RPReset WrEn RdEn Invalid Data Data Q Invalid Q Data_1 Empty Almost Empty Full Almost Full 10-34 Data_2 Data_3 Lattice Semiconductor LatticeXP2 Memory Usage Guide Distributed Single Port RAM (Distributed_SPRAM) - PFU Based PFU-based Distributed Single Port RAM is created using the 4-input LUT (Look-Up Table) available in the PFU. These LUTs can be cascaded to create larger Distributed Memory sizes. Figure 10-39 shows the Distributed Single Port RAM module as generated by IPexpress. Figure 10-39. Distributed Single Port RAM Module Generated by IPexpress Clock ClockEn Reset PFU based Distributed Single Port Memory WE Q Address Data The generated module makes use 4-input LUT available in the PFU. Additional logic like Clock, Reset is generated by utilizing the resources available in the PFU. Ports such as Read Clock (RdClock) and Read Clock Enable (RdClockEn), are not available in the hardware primitive. These are generated by IPexpress when the user wants the to enable the output registers in their IPexpress configuration. The various ports and their definitions for the memory are as per Table 10-14. The table lists the corresponding ports for the module generated by IPexpress and for the primitive. Table 10-14. PFU-based Distributed Single Port RAM Port Definitions Port Name in Generated Module Port Name in the PFU Primitive Description Active State Clock CK Clock Rising Clock Edge ClockEn -- Clock Enable Active High Reset -- Reset Active High WE WRE Write Enable Active High Address AD[3:0] Address -- Data DI[1:0] Data In -- Q DO[1:0] Data Out -- Ports such as Clock Enable (ClockEn) are not available in the hardware primitive. These are generated by IPexpress when the user wishes to enable the output registers in the IPexpress configuration. Users have the option of enabling the output registers for Distributed Single Port RAM (Distributed_SPRAM). Figures 10-40 and 10-41 show the internal timing waveforms for the Distributed Single Port RAM (Distributed_SPRAM) with these options. 10-35 Lattice Semiconductor LatticeXP2 Memory Usage Guide Figure 10-40. PFU Based Distributed Single Port RAM Timing Waveform - without Output Registers Clock ClockEn tSUWREN_PFU t HWREN_PFU WE t SUADDR_PFU Address Data t HADDR_PFU Add_0 Add_1 Data_0 Data_1 t SUDATA_PFU Add_0 Add_2 t HDATA_PFU Invalid Data Q Add_1 Data_0 Data_1 Data_2 t CORAM_PFU Figure 10-41. PFU Based Distributed Single Port RAM Timing Waveform - with Output Registers Reset Clock ClockEn t HWREN_PFU t SUWREN_PFU WE t HADDR_PFU tSUADDR_PFU Address Add_0 Add_1 Data Data_0 Data_1 t SUDATA_PFU Q Add_0 Add_1 Add_2 t HDATA_PFU Invalid Data Data_0 t CO 10-36 Data_1 Data_2 Lattice Semiconductor LatticeXP2 Memory Usage Guide Distributed Dual Port RAM (Distributed_DPRAM) - PFU Based PFU-based Distributed Dual Port RAM is also created using the 4-input LUT (Look-Up Table) available in the PFU. These LUTs can be cascaded to create a larger Distributed Memory sizes. Figure 10-42. Distributed Dual Port RAM Module Generated by IPexpress WrAddress RdAddress RdClock RdClockEn PFU based Distributed Dual Port Memory Reset Q WrClock WrClockEn WE Data The generated module makes use of the 4-input LUT available in the PFU. Additional logic like Clock and Reset is generated by utilizing the resources available in the PFU. Ports such as Read Clock (RdClock) and Read Clock Enable (RdClockEn), are not available in the hardware primitive. These are generated by IPexpress when the user wants the to enable the output registers in the IPexpress configuration. The various ports and their definitions for memory are as per Table 10-15. The table lists the corresponding ports for the module generated by IPexpress and for the primitive. Table 10-15. PFU-based Distributed Dual-Port RAM Port Definitions Port Name in Generated Module Port Name in the EBR Block Primitive Description Active State WrAddress WAD[3:0] Write Address -- RdAddress RAD[3:0] Read Address -- RdClock -- Read Clock Rising Clock Edge RdClockEn -- Read Clock Enable Active High WrClock WCK Write Clock Rising Clock Edge WrClockEn -- Write Clock Enable Active High WE WRE Write Enable Active High Data DI[1:0] Data Input -- Q RDO[1:0] Data Out -- Ports such as Read Clock (RdClock) and Read Clock Enable (RdClockEn) are not available in the hardware primitive. These are generated by IPexpress when the user wants to enable the output registers in the IPexpress configuration. 10-37 Lattice Semiconductor LatticeXP2 Memory Usage Guide Users have the option of enabling the output registers for Distributed Dual Port RAM (Distributed_DPRAM). Figures 10-43 and 10-44 show the internal timing waveforms for the Distributed Dual Port RAM (Distributed_DPRAM) with these options. Figure 10-43. PFU Based Distributed Dual Port RAM Timing Waveform - without Output Registers WrClock t HCE_EBR t SUCE_EBR WrClockEn WE t SUADDR_EBR WrAddress t HADDR_EBR Add_0 Add_1 Add_2 RdAddress Add_0 Data Data_0 t SUDATA_EBR Q Data_1 Add_1 Add_2 Data_2 t HDATA_EBR Invalid Data Data_0 t CORAM_PFU 10-38 Data_1 Data_2 Lattice Semiconductor LatticeXP2 Memory Usage Guide Figure 10-44. PFU Based Distributed Dual Port RAM Timing Waveform - with Output Registers Reset WrClock tSUWREN_PFU tHWREN_PFU WrClockEn RdClock t SUCE_PFU t HCE_PFU RdClockEn tSUWREN_PFU t HWREN_PFU t SUADDR_PFU t HADDR_PFU WE WrAddress Add_0 Add_1 RdAddress Add_0 Data Data_0 t SUDATA_PFU Q Add_1 Data_1 t HDATA_PFU Invalid Data Data_0 Data_1 t CORAM_PFU Distributed ROM (Distributed_ROM) - PFU Based PFU-based Distributed ROM is also created using the 4-input LUT (Look-Up Table) available in the PFU. These LUTs can be cascaded to create larger Distributed Memory sizes. Figure 10-45 shows the Distributed ROM module as generated by IPexpress. Figure 10-45. Distributed ROM Generated by IPexpress Address OutClock OutClockEn PFU-based Distributed ROM Q Reset The generated module makes use of the 4-input LUT available in the PFU. Additional logic like Clock and Reset is generated by utilizing the resources available in the PFU. 10-39 Lattice Semiconductor LatticeXP2 Memory Usage Guide Ports such as Out Clock (OutClock) and Out Clock Enable (OutClockEn) are not available in the hardware primitive. These are generated by IPexpress when the user wants to enable the output registers in the IPexpress configuration. The various ports and their definitions for memory are as per Table 10-16. The table lists the corresponding ports for the module generated by IPexpress and for the primitive. Table 10-16. PFU-based Distributed ROM Port Definitions Port Name in Generated Module Port Name in the PFU Block Primitive Address AD[3:0] Address -- OutClock -- Out Clock Rising Clock Edge OutClockEn -- Out Clock Enable Active High Reset -- Reset Active High Q DO Data Out -- Description Active State Users have the option to enable the output registers for Distributed ROM (Distributed_ROM). Figures 10-46 and 10-47 show the internal timing waveforms for the Distributed ROM with these options. Figure 10-46. PFU Based ROM Timing Waveform - without Output Registers t SUADDR_PFU Address tHADDR_PFU Add_0 Q Add_1 Invalid Data Data_0 Add_2 Data_1 Data_2 t CORAM_PFU Figure 10-47. PFU Based ROM Timing Waveform - with Output Registers Reset OutClock OutClockEn t SUADDR_PFU Address Q t HADDR_PFU Add_0 Add_1 Invalid Data Add_2 Data_0 CORAM_PFU 10-40 Data_1 Lattice Semiconductor LatticeXP2 Memory Usage Guide User TAG Memory The TAG memory is an area on the on-chip Flash which can be used for non-volatile storage. It is accessed in your design as if it were an external SPI Flash. Both SPI bus operation modes 0 (0,0) and 3 (1,1) are supported. Figure 10-48. SSPIA Primitive SI SSPIA CLK SO CS Table 10-17. User TAG Memory Signal Description Primitive Port Name Description SI Data input SO Data output CLK Clock CS Chip select Basic Specifications for TAG Memory There is one full page of TAG memory in each LatticeXP2 device. Page size ranges from 56 to 451 bytes. Table 10-18. TAG Memory Density Device TAG Memory (Bits) TAG Memory (Bytes) XP2-5 632 79 XP2-8 768 96 XP2-17 2184 273 XP2-30 2640 330 XP2-40 3384 423 10-41 Lattice Semiconductor LatticeXP2 Memory Usage Guide Table 10-19. Timing Specifications Symbol Parameter Min Max Units fMAXSPI Slave SPI CCLK Clock Frequency 25 MHz tRF Clock and Data Input Rise and Fall Time 20 ns tCSCCLK Slave SPI CCLK Clock High Time 20 ns tSOCDO Slave SPI CCLK Clock Low Time 20 ns tSCS CSSPIN High Time 25 ns tSCSS CSSPIN Setup Time 25 ns tSCSH CSSPIN Hold Time 25 ns tSTSU Slave SPI Data In Setup Time 5 ns tSTH Slave SPI Data In Hold Time 5 ns Slave SPI Output Valid (after WRITE_EN) tSTVO Slave SPI Output Valid (without WRITE_EN)(1) 3 tSTCO Slave SPI Output Hold Time 0 tSDIS Slave SPI Output Disable Time 20 ns 20 s ns 100 ns Note: If the READ_TAG command is issued without first loading the WRITE_EN command, the device will need extra time, up to 20s maximum, to transfer the data from TAG Flash to the data-shift register. Figure 10-49. Generic Timing Diagram tSCS CSSPISN 0 Command 7 8 3-Byte Dummy 31 32 Byte Bounded Data Out (n-1) th CCLK tSOCDO tCSCLK SISPI tSTSU tSCSS tSTSU tSTVO tSTH HI-Z SO tSCSH tSDIS tSTCO 0 1 2 8 Command Shifting Clocks n-1 HI-Z Data Shifting Clocks Programming via the SPI Interface Since the SSPIA module is an internal module, I/Os can be treated as I/Os of any other soft module. Therefore, they can be routed to other internal modules, or they can go out to I/O pads. The recommended routing is to the sysCONFIG port pins. Table 10-20. Usage Of Commands OPCODE Bytes 1-31, 2 Data READ_TAG 0x4E Dummy Out PROGRAM_TAG 0x8E Dummy In ERASE_TAG 0x0E Dummy Command Name Delay Time Description 3s min. Read TAG memory 1ms min., 25ms max. Program TAG memory 100ms min., 1000ms max. Erase TAG memory 1. Data bytes are shifted with most significant bit first. 2. Byte 1-3 are dummy clocks to provide extra timing for the device to execute the command. The data presented at the SI pin during these dummy clocks can be any value and do not have to be 0x00 as shown. 10-42 Lattice Semiconductor LatticeXP2 Memory Usage Guide General Description The LatticeXP2 family of devices is designed with instant-on, standalone TAG memory that is always available. TAG memory is organized as a one-page Flash non-volatile memory accessible by the hardwired Serial Peripheral Interface port or the JTAG port. The standalone TAG memory is ideal for use as scratch pad memory for critical data, board serialization, board revision logs and programmed pattern identification. The integration of TAG memory into the LatticeXP2 device family saves chip count and board space. It also can be used to replace obsoleted low-density SPI EEPROM devices. The hardwired SPI interface does not require the device to pre-program the configuration Flash first to enable the SPI interface. The interface is already enabled when the device is shipped from Lattice, saving board test time. The hard-wired SPI interface allows the TAG memory to retain its independent identity or accessible always in spite of the TAG Memory Flash is embedded into the LatticeXP2 devices. The hard-wired SPI interface is also important for field upgrades so that critical data can be maintained on the TAG memory and guaranteed to be accessible even if the device is field upgraded to a new pattern. The instant-on capability is achieved by enabling the SPI interface when the devices are shipped from Lattice. Unlike the configuration Flash, the security setting of the device, standard or advanced, has no effect on the accessibility of the TAG memory. Therefore, the TAG memory is always accessible. The TAG memory, same as other Flash fuses, can also be programmed using the IEEE 1532 compliant programming flow on the JTAG port for production programming support or for system debugging. Pin Descriptions The pins described below are not dedicated pins. If the TAG memory feature is not required, these pins can be regular user I/O pins. If the TAG memory feature is required, the TAG memory can be accessed by the internal SPI interface through the core. The internal SPI interface makes the TAG Memory capable of supporting advanced applications. For example: 1. Use an I2C to SPI translator to convert the SPI TAG memory to be an I2C TAG memory device. 2. Route the four SPI interfaces to the other four user I/Os. Selections are made using the ispLEVER design tool. By default, the external SPI interface is enabled and TAG memory is selected. The functional descriptions of the pins below are applicable to both the internal and external SPI interfaces. Serial Data Input (SI) The SPI Serial Data Input pin provides a means for commands and data to be serially written to (shifted into) the device. Data is latched on the falling edge of the serial clock (CLK) input pin. Serial Data Output (SO) The SPI Serial Data Output pin provides a means for status and data to be serially read out (shifted out of) the device. Data is shifted out on the falling edge of the serial clock (CLK) input pin. Serial Clock (CLK) The SPI Serial Clock Input pin provides the timing for serial input and output operations. Chip Select (CS) The SPI Chip Select pin enables and disables SPI interface operations. When the Chip Select is high the SPI interface is deselected and the Serial Data Output (SO) pin is at high impedance. When it is brought low, the SPI inter- 10-43 Lattice Semiconductor LatticeXP2 Memory Usage Guide face is selected and commands can be written into and data read from the device. After power up, CS must transit from high to low before a new command can be accepted. SPI Operations SPI Modes The SPI interface is accessible through the SPI-compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (CS), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3 concerns the normal state of the CLK pin when the SPI master is in standby and data is not being transferred to the device's SPI interface. For Mode 0 the CLK is normally low and for Mode 3 the CLK signal is normally high. In either case, data input on the SI pin is sampled only during the rising edge. Data output on the SO pin is clocked out only on the falling edge of CLK. Status Register The SPI interface can access the 1-bit status register required to support TAG Memory Flash programming. The programming complete status register: This is the single bit status register for pooling. If the programming or erase operation is complete, then the status bit is set to 1, otherwise it is set to 0 for more programming or erase time. Commands Table 10-21. Commands Command Name Byte 1 (Opcode) Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 n-Byte (D0-D7) (D8-D15) (D24-D31) READ_ID 0x98 0x00 0x00 0x00 WRITE_EN 0xAC 0x00 0x00 0x00 WRITE_DIS 0x78 0x00 0x00 0x00 ERASE_TAG 0x0E 0x00 0x00 0x00 PROGRAM_TAG 0x8E 0x00 0x00 0x00 D7-D0 Next Byte Last Byte READ_TAG 0x4E 0x00 0x00 0x00 (D7-D0) (Next Byte) (Continue) STATUS 0x4A 0x00 0x00 0x00 (b1xxxxxxx or b0xxxxxxx) Notes: 1. Data bytes are shifted with most significant bit first. Byte field with data in parenthesis ( ) indicate data being read from the SO pin. 2. Byte 2-4 are dummy clocks to provide extra timing for the device to execute the command. The data presented at the SI pin during these dummy clocks can be any value and do not have to be 0x00 as shown. 3. The READ_ID command reads out the 32 bits JTAG IDCODE of the device. The first bit shifted out on SO pin is thus bit 0 of the JTAG IDCODE and the last bit is bit 31 of the IDCODE. 4. The PROGRAM_TAG command supports page programming only. The programming data shift into the TAG Memory must be exactly the same size as the one page of the TAG Memory. Under shifting or over shifting will cause erroneous data programmed into the TAG Memory. The Last Byte shown on the n-Byte column indicates the last byte of the data must be shifted into the device before driving the Chip Select to high to start the programming action. 5. The STATUS command read from the single bit status register. When read from the register, only the first bit is valid, the other bits are dummies and should be ignored. READ_ID (98h) The READ_ID command captures the IEEE 1149.1 JTAG IDCODE out of the device on the SO pin. This command is commonly used to verify whether communication is established with the SPI bus. After the 8-bit READ_ID command is received, the device ignores the data presented at the Serial Data Input (SI) pin. The Serial Output (SO) pin is enabled on the falling edge of clock 31 to drive out the first bit of the IDCODE. After 32 bits of the IDCODE are shifted out, additional clocking will cause dummy data to be shifted out on SO. 10-44 Lattice Semiconductor LatticeXP2 Memory Usage Guide Figure 10-50. READ_ID Waveform CS CLK SI HI-Z SO 0 1 2 8 Bits READ_ID Command 24 Bits Dummy 31 HI-Z 32 Bits JTAG IDCODE WRITE_EN (ACh) The WRITE_EN command enables the TAG memory for programming. If the WRITE_EN command has not been shifted into the device first, the PROGRAM_TAG, ERASE_TAG and STATUS commands do not take effect. This is to prevent the TAG memory from erroneous erase or program. The command is executed when the Chip Select pin is driven from low to high after the 24th dummy clock. Any extra dummy clocks, if presented before driving the Chip Select pin to high, are ignored. After the Chip Select pin is driven from low to high, a minimum of three clocks are required to complete the execution of the command. The effect of this command is terminated by the WRITE_DIS command. Figure 10-51. WRITE_EN Waveform Optional Extra Clocks 3 Clocks To Initiate And Complete CS CLK SI HIGH IMPEDANCE SO 8 Command Shifting Clocks WRITE_DIS (78h) The WRITE_DIS command disables the TAG memory for programming. It does not nullify the READ_TAG and READ_ID commands. The command is executed when the Chip Select pin is driven from low to high after the 24th dummy clock. Any extra dummy clocks, if presented before driving the Chip Select pin to high, are ignored. After the Chip Select pin is driven from low to high, a minimum of three clocks are required to complete the execution of the command. 10-45 Lattice Semiconductor LatticeXP2 Memory Usage Guide Figure 10-52. WRITE_DIS Waveform Optional Extra Clocks Three Clocks to Initiate And Complete CS CLK SI HIGH IMPEDANCE SO 8 Command Shifting Clocks ERASE_TAG (0Eh) The ERASE_TAG command is enabled after the command WRITE_EN has been shifted into the device and executed. The ERASE_TAG command erases all the TAG Memory Flash cells. The command is executed when the Chip Select pin is driven from low to high after the 24th dummy clock. Any extra dummy clocks, if presented before driving the Chip Select pin to high, are ignored. After the Chip Select pin is driven from low to high, a minimum of three clocks is required to initiate the erase action. After the three clocks, extra clocks are optional. Once the erase action is initiated, it will be carried out until it is done. There is no mechanism to terminate the erase action. This command sets the STATUS bit to 0 when the erase action begins. The programming engine sets the status bit to 1 when the erase is done successfully. Figure 10-53. ERASE_TAG Waveform Optional Extra Clocks Three Clocks To Initiate the Erase Action CS CLK SI HIGH IMPEDANCE SO 8 Command Shifting Clocks PROGRAM_TAG (8Eh) The PROGRAM_TAG is enabled after the command WRITE_EN has been shifted into the device and executed. The PROGRAM_TAG command programs the entire TAG memory page at once. After the command is shifted into the device on the SI pin, and followed by 24 dummy clocks, the TAG memory column decoder serves as the data buffer for the programming data to be shifted into serially. The shifting direction is from left to right, as shown. The first bit to be shifted out closest to the SO pin appears on the right-most side of the shift register. The data buffer functions like a FIFO (First In First Out) serial data shift register. In order to make sure that bit 0 will be read out first, data bit 0 must be shifted into the right-most location of the data shift register. To achieve this, the data buffer must be filled up completely. Consequently, over-filling the data buffer will cause overflow of the data buffer, resulting in loss of data. 10-46 Lattice Semiconductor LatticeXP2 Memory Usage Guide The SO pin stays in the HIGHZ state throughout this command. Figure 10-54. Bit Shifting Order Bit 0 Bit N-1 SI SO When the data buffer has filled up to one page of data, driving the Chip Select pin to high terminates the data shifting. After the Chip Select pin is driven from low to high, a minimum of three clocks are required to initiate the programming action. In the programming action, the data buffer content is copied in parallel from the data buffer into the TAG memory Flash cells. The status bit is set to 0 when the programming actions begin. The status bit is set to 1 when the programming action is done successfully. Figure 10-55. Data Buffer to Flash Cell Mapping Bit N-1 Bit 0 Flash Cell N-1 Flash Memory Cells Flash Cell 0 When the programming action complete, the STATUS bit is set to 1. The exact same image is written into the Flash cells of the TAG Memory block when the programming action complete. Figure 10-56. PROGRAM_TAG Waveform Optional Extra Clocks Three Clocks To Initiate The Program Action CS CLK SI HIGH IMPEDANCE SO 8 Command Shifting Clocks READ_TAG (4Eh) The READ_TAG command enables the Flash programming engine to transfer data programmed in the Flash cells to the data buffer. The transfer action starts on the third dummy clock after the 8-bit opcode. The delay time derived from the 21 dummy clocks is the time required to transfer the Flash cells data into the data buffer. The transfer action, once initiated, does not need the clock to continue to run. The clock count is only required to enable the SO pin. If the Flash circuitry is not yet enabled, the device will need extra delay time to enable the Flash circuitry before transfer can take place. This extra delay must be provided after the third dummy clock and before the 24th dummy clock. If the READ_TAG command is preceded by the WRITE _EN command, then it is fast read. The device does not require extra delay to enable the Flash circuitry. The 20 dummy clocks after the transfer is initiated to before enabling the SO pin are considered delay clocks. 10-47 Lattice Semiconductor LatticeXP2 Memory Usage Guide Delay time = 20 x 1/frequency. The transfer delay time, including the extra delay time to enable the Flash circuitry, is 5uS minimum. The clock frequency can then be set to 2.5 MHz if continuous clocking is desired. When all the data captured into the data buffer are shifted out, additional clocks will shift out dummy data. The SI pin is not connected to the input of the data buffer when the READ_TAG command is shifted into the device. While the data in the data buffer is shifted out to the direction of SO, dummy data is shifted into the data buffer. Consequently, when over-shifting occurs, dummy data of unknown value is shifted out. Figure 10-57. Readout Order Bit 0 Bit N-1 Flash Cell N-1 Flash Cell 0 Flash Memory Cells Bit 0 Bit N-1 SO Figure 10-58. READ_TAG Waveform Time elapsed must be 5s Enable SO on 24th Dummy Clock. Bit 0 is valid. If the clock is too fast add delay before 21st clock Data capture starts at 21st clock CS CLK SI HI-Z SO N-1 0 1 2 8 Bits READ_TAG Command 24 Bits Dummy HI-Z TAG Memory Data STATUS (4Ah) The STATUS command allows the single-bit status register to be read. This command can be loaded at any time after the WRITE_EN command has already been shifted into the device first. This command does not terminate the programming or erase action. It is used to report the progress of the programming or erase action. The status register actual size is only 1 bit. Dummy data is shifted out on the SO pin if extra data shifting clocks are applied. The command can be shifted into the device again to capture the status bit and then read out. During the interval of shifting the command, the additional programming or erase time is provided by driving the Chip Select pin to high and holding the CLK pin low. Clocking while holding the Chip Select pin high is optional. If the maximum programming time or erasure has expired and the status bit still is not set to 1, then erase or programming has failed. 10-48 Lattice Semiconductor LatticeXP2 Memory Usage Guide Figure 10-59. STATUS Waveform Provide Device Additional Erase Or Programming Time Enable SO On 24th Dummy Clock Capture Starts on Third Dummy Clock CS CLK SI HI-Z HI-Z SO 0 1 2 8 Bits READ_TAG Command 24 Bits Dummy 6 7 Dummy Status Bit Specifications and Timing Diagrams Powering Up TAG memory is available when the boot-up either from the internal embedded Flash or from the external SPI Flash boot PROM is complete. If the embedded Flash is blank, the boot up will not work. It is recommended to wait for the same amount of delay as if the embedded configuration has been programmed before accessing the TAG memory. If the boot-up is from external SPI Flash, longer delay time should be given or check the DONE pin for a high first before accessing the TAG memory. The SPI interface needs the low-to-high transition on the Chip Select pin to reset. During power-up, the low-to-high transition is assured by requiring the CLK pin tracking the VCC. The other method is to drive the Chip Select pin to high then low then high to reset the SPI interface before shifting the first command into the device. Figure 10-60. Device Power-up Waveform Chip Select Must Track VCC. TAG Memory Is Fully Accessible. Boot Up From The Embedded FLASH. VCCAUX Or VCC Whichever Is The Last. VCCmin Power Up Timing And Voltage Level 10-49 Lattice Semiconductor LatticeXP2 Memory Usage Guide Availability of TAG Memory TAG memory is available most of time on the Slave SPI interface with the following exceptions: * When the SRAM fuses are being accessed by the JTAG port, Slave SPI interface or refreshing * When the other Flash cells are being accessed through the JTAG port or Slave SPI interface * While JTAG BSCAN testing is taking place * The Slave SPI interface is disabled with the persistent fuse programmed (set to off) AC Timing * 25 MHz maximum CLK * 5 uS minimum read command delay * 2 mS minimum delay from VCCmin to shifting in the first command Programming Timing * 1 sec. maximum erase time * 5 mS maximum programming time Programming via the JTAG Interface .VME files can be generated for the ispVM System software which only programs the TAG memory. These .VME files are handled according to the standard ispVME flow. Initializing Memory In the EBR based ROM or RAM memory modes and the PFU based ROM memory mode, it is possible to specify the power-on state of each bit in the memory array. Each bit in the memory array can have one of two values: 0 or 1. Initialization File Format The initialization file is an ASCII file, which users can create or edit using any ASCII editor. IPexpress supports three types of memory file formats: * Binary file * Hex File * Addressed Hex The file name for the memory initialization file is *.mem (<file_name>.mem). Each row depicts the value to be stored in a particular memory location and the number of characters (or the number of columns) represents the number of bits for each address (or the width of the memory module). The Initialization File is primarily used for configuring the ROMs. The EBR in RAM mode can optionally use this Initialization File also to preload the memory contents. The TAG memory uses hex or binary non-addressed files. Since it is a SPI, it cannot use the addressed hex file. 10-50 Lattice Semiconductor LatticeXP2 Memory Usage Guide Binary File The file is essentially a text file of 0's and 1's. The rows indicate the number of words and columns indicate the width of the memory. Memory Size 20x32 00100000010000000010000001000000 00000001000000010000000100000001 00000010000000100000001000000010 00000011000000110000001100000011 00000100000001000000010000000100 00000101000001010000010100000101 00000110000001100000011000000110 00000111000001110000011100000111 00001000010010000000100001001000 00001001010010010000100101001001 00001010010010100000101001001010 00001011010010110000101101001011 00001100000011000000110000001100 00001101001011010000110100101101 00001110001111100000111000111110 00001111001111110000111100111111 00010000000100000001000000010000 00010001000100010001000100010001 00010010000100100001001000010010 00010011000100110001001100010011 Hex File The Hex file is essentially a text file of Hex characters arranged in a similar row-column arrangement. The number of rows in the file is same as the number of address locations, with each row indicating the content of the memory location. Memory Size 8x16 A001 0B03 1004 CE06 0007 040A 0017 02A4 Addressed Hex Addressed Hex consists of lines of address and data. Each line starts with an address, followed by a colon, and any number of data. The format of memfile is address: data data data data ... where address and data are hexadecimal numbers. -A0 : 03 F3 3E 4F -B2 : 3B 9F The first line puts 03 at address A0, F3 at address A1, 3E at address A2,and 4F at address A3. The second line puts 3B at address B2 and 9F at address B3. There is no limitation on the values of address and data. The value range is automatically checked based on the values of addr_width and data_width. If there is an error in an address or data value, an error message is printed. 10-51 Lattice Semiconductor LatticeXP2 Memory Usage Guide Users need not specify data at all address locations. If data is not specified at certain address, the data at that location is initialized to 0. IPexpress makes memory initialization possible both through the synthesis and simulation flows. FlashBakTM Capability The LatticeXP2 FPGA family offers FlashBak capability, which is a way to store the data in the EBRs to the Flash memory upon user command. This protects the user's data from being lost when the system is powered off. The FlashBak module (STFA primitive) has a single-command-two-operation process (see Figure 10-61). When the FlashBak operation is initiated, an erase-UFM-Flash signal is enabled to erase the Flash, followed by the transferto-flash operation. Once the transfer is done, the Flash controller sends a transfer-done signal back to the user logic. During the FlashBak operation, the EBRs are not accessible. There is no difference between the regular EBR RAM configuration and the shadow Flash (UFM) EBR RAM configuration in the ispLEVER GUI. The presence of the STFA (FlashBak) primitive in a design determines the EBR RAM configuration. FlashBak cannot be used if the soft-error detect (SED) is operating in an Always mode. Since there is no addressing but just a `dump' of all EBR to Flash, only one STFA module is necessary. Multiple modules are not necessary or allowed. Figure 10-61. FlashBak Primitive STOREN UFMFAIL UFMBUSYN STFA Figure 10-62. FlashBak Waveform Minimum pulse width = 780ns STOREN UFM BUSYN 1.85s delay regardless of whether STOREN is released Table 10-22. STFA Port Descriptions Port Name Corresponding Hardware Port Name I/O Description STOREN storecmdn I Initiates to store the EBR content to Flash UFMFAIL ufm_fail O Store to Flash operation failed UFMBUSYN fl_busyn O Tells the user whether the Flash is in the busy state or not Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com 10-52 Lattice Semiconductor LatticeXP2 Memory Usage Guide Revision History Date Version February 2007 01.0 Initial release. Change Summary July 2007 01.1 Added FlashBak Capability section. November 2007 01.2 TAG memory added. January 2008 01.3 Updated Read_Tag Commands Waveform diagram. Changed minimum delay between the 3rd and 24th dummy clock from 3s to 5s. February 2008 01.4 Updated FIFO_DC without Output Registers (Non-Pipelined) diagram. March 2008 01.5 Added FlashBAK Waveform diagram. June 2008 01.6 Removed Read-Before-Write sysMEM EBR mode. Updated "First In First Out (FIFO, FIFO_DC) - EBR Based" section. June 2008 01.7 Added TAG memory timing waveforms and instructions. November 2008 01.8 Updated the following waveform figures: Generic Timing Diagram, READ_ID Waveform, WRITE_EN Waveform, WRITE_DIS Waveform, ERASE_TAT Waveform, PROGRAM_TAW Waveform, READ_TAG Waveform, STATUS Waveform. Updated Serial Data Input (SI) text section. Updated Memory Modules text section. July 2011 01.9 Added the setup and hold requirements for addresses to EBR-based memories. 10-53 Lattice Semiconductor LatticeXP2 Memory Usage Guide Appendix A. Attribute Definitions DATA_WIDTH Data width is associated with the RAM and FIFO elements. The DATA_WIDTH attribute will define the number of bits in each word. It takes the values as defined in the RAM size tables in each memory module. REGMODE REGMODE or the Register mode attribute is used to enable pipelining in the memory. This attribute is associated with the RAM and FIFO elements. The REGMODE attribute takes the NOREG or OUTREG mode parameter that disables and enables the output pipeline registers. RESETMODE The RESETMODE attribute allows users to select the mode of reset in the memory. This attribute is associated with the block RAM elements. RESETMODE takes two parameters: SYNC and ASYNC. SYNC means that the memory reset is synchronized with the clock. ASYNC means that the memory reset is asynchronous to clock. CSDECODE CSDECODE or the Chip Select Decode attributes are associated to block RAM elements. CS, or Chip Select, is the port available in the EBR primitive that is useful when memory requires multiple EBR blocks cascaded. The CS signal forms the MSB for the address when multiple EBR blocks are cascaded. CS is a 3-bit bus, so it can cascade eight memories easily. CSDECODE takes the following parameters: "000", "001", "010", "011", "100", "101", "110", and "111". CSDECODE values determine the decoding value of CS[2:0]. CSDECODE_W is chip select decode for write and CSDECODE_R is chip select decode for read for Pseudo Dual Port RAM. CSDECODE_A and CSDECODE_B are used for true dual port RAM elements and refer to the A and B ports. WRITEMODE The WRITEMODE attribute is associated with the block RAM elements. It takes the NORMAL, WRITETHROUGH, and READBEFOREWRITE mode parameters. In NORMAL mode, the output data does not change or get updated, during the write operation. This mode is supported for all data widths. In WRITETHROUGH mode, the output data is updated with the input data during the write cycle. This mode is supported for all data widths. In READBEFOREWRITE mode, the output data port is updated with the existing data stored in the write address, during a write cycle. This mode is supported for x9, x18 and x36 data widths. WRITEMODE_A and WRITEMODE_B are used for dual port RAM elements and refer to the A and B ports in case of a True Dual Port RAM. For all modes (of the True Dual Port module), simultaneous read access from one port and write access from the other port to the same memory address is not recommended. The read data may be unknown in this situation. Also, simultaneous write access to the same address from both ports is not recommended. (When this occurs, the data stored in the address becomes undetermined when one port tries to write a `H' and the other tries to write a `L'). It is recommended that the designer implements control logic to identify this situation if it occurs and either: 1. Implement status signals to flag the read data as possibly invalid, or 2. Implement control logic to prevent the simultaneous access from both ports. GSR GSR or the Global Set/ Reset attribute is used to enable or disable the global set/reset for RAM element. 10-54 LatticeXP2 High-Speed I/O Interface June 2010 Technical Note TN1138 Introduction LatticeXP2TM devices support Double Data Rate (DDR) and Single Data Rate (SDR) interfaces using the logic built into the Programmable I/O (PIO). SDR applications capture data on one edge of a clock while the DDR interfaces capture data on both the rising and falling edges of the clock, thus doubling performance. The LatticeXP2 I/Os also have dedicated circuitry to support DDR and DDR2 SDRAM memory interfaces. This technical note details the use of LatticeXP2 devices to implement both a high-speed generic DDR interface and DDR and DDR2 memory interfaces. DDR and DDR2 SDRAM Interfaces Overview A DDR SDRAM interface will transfer data at both the rising and falling edges of the clock. The DDR2 is the second generation of the DDR SRDRAM memory. The DDR and DDR2 SDRAM interfaces rely on the use of a data strobe signal, called DQS, for high-speed operation. The DDR SDRAM interface uses a single-ended DQS strobe signal, whereas the DDR2 interface uses a differential DQS strobe. Figures 11-1 and 11-2 show typical DDR and DDR2 SDRAM interface signals. SDRAM interfaces are typically implemented with eight DQ data bits per DQS. An x16 interface will use two DQS signals and each DQS is associated with eight DQ bits. Both the DQ and DQS are bi-directional ports used to both read and write to the memory. When reading data from the external memory device, data coming into the device is edge-aligned with respect to the DQS signal. This DQS strobe signal needs to be phase-shifted 90 degrees before FPGA logic can sample the read data. When writing to a DDR/DDR2 SDRAM, the memory controller (FPGA) must shift the DQS by 90 degrees to center-align with the data signals (DQ). A clock signal is also provided to the memory. This clock is provided as a differential clock (CLKP and CLKN) to minimize duty cycle variations. The memory also uses these clock signals to generate the DQS signal during a read via a DLL inside the memory. Figures 11-3 and 11-4 show DQ and DQS timing relationships for read and write cycles. For other detailed timing requirements, please refer to the DDR SDRAM JEDEC specification (JESD79C). During read, the DQS signal is LOW for some duration after it comes out of tristate. This state is called Preamble. The state when the DQS is LOW before it goes into Tristate is the Postamble state. This is the state after the last valid data transition. DDR SDRAM also requires a Data Mask (DM) signal to mask data bits during write cycles. Note that the ratio of DQS to data bits is independent of the overall width of the memory. An 8-bit interface will have one strobe signal. DDR SDRAM interfaces use the SSTL25 Class I/II I/O standards whereas the DDR2 SDRAM interface uses the SSTL18 Class I/II I/O standards. The DDR2 SDRAM interface also supports differential DQS (DQS and DQS#). (c) 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 11-1 tn1138_01.4 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Figure 11-1. Typical DDR SDRAM Interface FPGA (DDR Memory Controller) DDR Memory DQ<7:0> DQS DM ADDRESS COMMAND CONTROL CLK/CLKN DQ<7:0> 8 DQ<7:0> DQS DQS DM DM ADDRESS X COMMAND Y CONTROL Z CLKP/CLKN ADDRESS COMMAND CONTROL CLK/CLKN Figure 11-2. Typical DDR2 SDRAM Interface DDR Memory FPGA (DDR Memory Controller) DQ<7:0> DQS, DQS# DM ADDRESS COMMAND CONTROL CLK/CLKN DQ<7:0> 8 DQ<7:0> DQS, DQS# DQS, DQS# DM DM ADDRESS X COMMAND Y CONTROL Z CLKP/CLKN ADDRESS COMMAND CONTROL CLK/CLKN The following two figures show the DQ and DQS relationship for memory read and write interfaces. Figure 11-3. DQ-DQS During READ DQS (at PIN) Preamble Postamble DQ (at PIN) DQS (at REG) DQ (at REG) DQS PIN to REG and 90 Degree Phase Shift 11-2 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Figure 11-4. DQ-DQS During WRITE DQS (at PIN) DQ (at PIN) Implementing DDR Memory Interfaces with LatticeXP2 Devices As described in the DDRSDRAM overview section, the DDR SDRAM interfaces rely primarily on the use of a data strobe signal called DQS for high-speed operation. When reading data from the external memory device, data coming into the LatticeXP2 device is edge-aligned with respect to the DQS signal. Therefore, the LatticeXP2 device needs to shift the DQS (a 90-degree phase shift) before using it to sample the read data. When writing to a DDR SDRAM, the memory controller from the LatticeXP2 device must generate a DQS signal that is center-aligned with the DQ, the data signals. This is accomplished by ensuring the DQS strobe is 90 degrees ahead relative to DQ data. LatticeXP2 devices have dedicated DQS support circuitry for generating the appropriate phase shifting for DQS. The DQS phase shift circuit uses a frequency reference DLL to generate delay control signals associated with each of the dedicated DQS pins and is designed to compensate for process, voltage and temperature (PVT) variations. The frequency reference is provided through one of the global clock pins. The dedicated DDR support circuit is also designed to provide comfortable and consistent margins for data sampling window. This section describes how to implement the read and write sections of a DDR memory interface. It also provides details of the DQ and DQS grouping rules associated with the LatticeXP2 devices. DQS Grouping Each DQS group generally consists of at least 10 I/Os (one DQS, eight DQ and one DM) to implement a complete 8-bit DDR memory interface. LatticeXP2 devices support DQS signals on all sides of the device. Each DQS signal on the top and bottom halves of the device will span across 18 I/Os and on the left and right sides of the device will span across 16 I/Os. Any 10 of these I/Os spanned by the DQS can be used to implement an 8-bit DDR memory interface. In addition to the DQS grouping, the user must also assign one reference voltage VREF1 for a given I/O bank. Figure 11-5. DQ-DQS Grouping n* I/O PADS DQ or DM DQ or DM DQS PAD (Ninth I/O Pad) *n=18 on bottom banks and n=16 on the left and right side banks. 11-3 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Figure 11-5 shows a typical DQ-DQS group for LatticeXP2 devices. The ninth I/O of this group of 16 or 18 I/Os is the dedicated DQS pin. The 8 pads before of the DQS and 6/9 (6 for left and right side and 9 for top and bottom side) pads after the DQS are covered by the DQS bus span. Users can assign any eight of these I/O pads to be DQ data pins. Hence, to implement a 32-bit wide memory interface you would need to use four such DQ-DQS groups. When not interfacing with the memory, the dedicated DQS pin can be used as a general purpose I/O. Each of the dedicated DQS pin is internally connected to the DQS phase shift circuitry. The pinout information contained in the LatticeXP2 Family Data Sheet shows pin locations for the DQS pads. DDR Software Primitives This section describes the software primitives that can be used to implement DDR interfaces. These primitives include: * DQSDLL - The DQS delay calibration DLL * DQSBUFC - The DQS delay function and the clock polarity selection logic * IDDRMX1A - The DDR input and DQS to system clock transfer registers with half clock cycle transfer * IDDRMFX1A - The DDR input and DQS to system clock transfer registers with full clock cycle transfer * ODDRMXA - The DDR output registers HDL usage examples for each of these primitives are listed in Appendices A and B. DQSDLL The DQSDLL generates a 90-degree phase shift required for the DQS signal. This primitive implements the onchip DQSDLL. Only one DQSDLL should be instantiated for all the DDR implementations on one half of the device. The clock input to this DLL should be at the same frequency as the DDR interface. The DLL generates the delay based on this clock frequency and the update control input to this block. The DLL updates the dynamic delay control to the DQS delay block when this update control (UDDCNTL) input is asserted. Figure 11-6 shows the primitive symbol. The active low signal on UDDCNTL updates the DQS phase alignment and should be initiated at the beginning of READ cycles. Figure 11-6. DQSDLL Symbol DQSDLL CLK LOCK RST DQSDEL UDDCNTL Table 11-1 provides a description of the ports. Table 11-1. DQSDLL Ports Port Name I/O Description CLK I System CLK should be at the frequency of the DDR interface from the FPGA core. RST I Resets the DQSDLL UDDCNTL I Provides update signal to the DLL that will update the dynamic delay. LOCK O Indicates when the DLL is in phase. DQSDEL O The digital delay generated by the DLL, should be connected to the DQSBUF primitive. DQSDLL Update Control: The DQS Delay can be updated for PVT variation using the UDDCNTL input. The DQSDEL is updated when the when the UDDCNTL is held LOW. The DQSDEL can be updated when variations are expected. DQSDEL can be updated anytime, except when the memory controller is receiving data from the memory. 11-4 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface DQSDLL Configuration: By default, this DLL will generate a 90-degree phase shift for the DQS strobe based on the frequency of the input reference clock to the DLL. The user can control the sensitivity to jitter by using the LOCK_SENSITIVITY attribute. This configuration bit can be programmed to be either "HIGH" or "LOW". The DLL Lock Detect circuit has two modes of operation controlled by the LOCK_SENSITIVITY bit, which selects more or less sensitivity to jitter. If this DLL is operated at or above 150 MHz, it is recommended that the LOCK_SENSITIVITY bit be programmed "HIGH" (more sensitive). When running at or below 100 MHz, it is recommended that the bit be programmed "LOW" (more tolerant). For 133 MHz, the LOCK_SENSITIVITY bit can go either way. DQSBUFC This primitive implements the DQS delay and the DQS transition detector logic. Figure 11-7 shows the primitive symbol. Figure 11-7. DQSBUFC Symbol DQSBUFC DQSI DQSO CLK DDRCLKPOL READ DQSC DQSDEL PRMBDET XCLK DQSXFER DATAVALID The DQSBUFC is composed of the DQS Delay, the DQS Transition Detect and the DQSXFER block as shown in Figure 11-8. This block inputs the DQS and delays it by 90 degrees. It also generates the DDR Clock Polarity and the DQSXFER signal. The preamble detect (PRMBDET) signal is generated from the DQSI input using a voltage divider circuit. 11-5 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Figure 11-8. DQSBUFC Function DQSDEL + - DQSI Vref Vref- DV* + - DQS DELAY DQSO DQS TRANSITION DETECT DQSC PRMBDET DQSXFER DQSXFER PRMBDET READ FPGA CLK XCLK DATA VALID MODULE DDRCLKPOL DATAVALID *DV ~ 170mV for DDR1 (SSTL25 signaling) *DV ~ 120mV for DDR2 (SSTL18 signaling) DQS Delay Block: The DQS Delay block receives the digital control delay line (DQSDEL) coming from one of the two DQSDLL blocks. These control signals are used to delay the DQSI by 90 degrees. DQSO is the delayed DQS and is connected to the clock input of the first set of DDR registers. DQS Transition Detect: The DQS Transition Detect block generates the DDR Clock Polarity signal based on the phase of the FPGA clock at the first DQS transition. The DDR READ control signal and FPGA CLK inputs to this coming and should be coming from the FPGA core. DQSXFER: This block generates the 90-degree phase shifted clock to for the DDR Write interface. The input to this block is the XCLK. The user can choose to connect this either to the edge clock or the FPGA clocks. The DQSXFER is routed using the DQSXFER tree to all the I/Os spanned by that DQS. Data Valid Module: The data valid module generates a DATAVALID signal. This signal indicates to the FPGA that valid data is transmitted out of the input DDR registers to the FPGA core. Table 11-2 provides a description of the I/O ports associated with the DQSBUFC primitive. 11-6 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Table 11-2. DQSBUFC Ports Port Name I/O Description DQSI I DQS Strobe signal from memory CLK I System CLK READ I Read generated from the FPGA core DQSDEL I DQS Delay from the DQSDLL primitive XCLK I Edge Clock or System CLK DQSO O Delayed DQS Strobe signal, to the input capture register block DQSC O DQS Strobe signal before delay, going to the FPGA core logic DDRCLKPOL O DDR Clock Polarity signal PRMBDET O Preamble detect signal, going to the FPGA core logic DQSXFER O 90 degree shifted clock going to the Output DDR register Block DATAVALID O Signal indicating transmission of Valid data to the FPGA core READ Pulse Generation The READ signal to the DQSBUFC block is internally generated in the FPGA core. The READ signal goes high when the READ command to control the DDR-SDRAM is initially asserted. This precedes the DQS preamble by one cycle, yet may overlap the trailing bits of a prior read cycle. The DQS Detect circuitry of the LatticeXP2 device requires the falling edge of the READ signal to be placed within the preamble stage. The preamble state of the DQS can be detected using the CAS latency and the round trip delay for the signals between the FPGA and the memory device. Note that the internal FPGA core generates the READ pulse. The rise of the READ pulse should coincide with the initial READ command of the Read Burst and need to go low before the Preamble goes high. Figure 11-9 shows a READ Pulse timing example with respect to the PRMBDET signal. Figure 11-9. READ Pulse Generation POSTAMBLE PREAMBLE FIRST DQS TRANSITION PRIOR READ CYCLE DQS VTH PRMBDET OK READ FAIL READ FAIL READ OK READ 11-7 POSTAMBLE Lattice Semiconductor LatticeXP2 High-Speed I/O Interface IDDRMX1A This primitive will implement the input register block in memory mode. The DDR registers are designed to use edge clock routing on the I/O side and the primary clock on the FPGA side. The ECLK input is used to connect to the DQS strobe coming from the DQS delay block (DQSBUFC primitive). The SCLK input is connected to the system (FPGA) clock. DDRCLKPOL is an input from the DQS Clock Polarity tree. This signal is generated by the DQS Transition detect circuit in the hardware. The DDRCLKPOL signal is used to choose the polarity of the SCLK to the synchronization registers. Figure 11-10. IDDRMX1A Symbol IDDRMX1A D QA ECLK QB RST SCLK CE DDRCLKPOL Table 11-3 provides a description of all I/O ports associated with the IDDRMX1A primitive. Table 11-3. IDDRMX1A Ports Port Name D I/O I Definition DDR Data ECLK I The phase shifted DQS should be connected to this input RST I Reset SCLK I System CLK CE I Clock enable DDRCLKPOL I DDR clock polarity signal QA O Data at Positive edge of the CLK QB O Data at the negative edge of the CLK Note: The DDRCLKPOL input to IDDRMX1A should be connected to the DDRCLKPOL output of DQSBUFC. Figure 11-11 shows the Input Register Block configured in the IDDRMX1A mode. 11-8 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Figure 11-11. Input Register Block in IDDRMX1A Mode IDDRMX1A Synchronization Registers DDR Registers QB DATA B E QA A C ECLK SCLK DDRCLKPOL Figure 11-12 shows the IDDRMX1A timing waveform. 11-9 D Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Figure 11-12. IDDRMX1A Waveform DQS at I/O DDR DATA at I/O P0 N0 P0 N0 P1 N1 P2 N2 P3 N3 P4 N1 P2 N2 P3 N3 P4 ECLK( DQS shifted 90 deg) DDR DATA at IDDRMX1A A P1 P1 P0 P2 B XX N0 N1 C XX P0 P1 P3 N2 P2 N4 P4 N3 N4 P3 P4 Case 1: DDRCLKPOL = 0 SCLK QA XX P0 P1 P2 P3 QB XX N0 N1 N2 N3 QA XX P0 P1 P2 P3 QB XX N0 N1 N2 N3 Case 2: DDRCLKPOL = 1 SCLK IDDRMFX1A With the IDDRMX1A, the data can enter the FPGA at either the positive or negative edge of the SCLK depending on the state of the DDRCLKPOL signal. The IDDRMFX1A module includes an additional clock transfer stage that ensures that the data is transferred at a known edge of the system clock. Figure 11-13. IDDRMFX1A Symbol IDDRMFX1A D QA ECLK QB RST CLK1 CLK2 CE DDRCLKPOL Table 11-4 provides a description of all I/O ports associated with the IDDRMFX1A primitive. 11-10 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Table 11-4. IDDRMFX1A Ports Port Name I/O Description D I DDR Data ECLK I The phase shifted DQS should be connected to this input RST I Reset CLK1 I Slow FPGA CLK CLK2 I Slow FPGA CLK CE I Clock enable DDRCLKPOL I DDR clock polarity signal QA O Data at the positive edge of the CLK QB O Data at the negative edge of the CLK Note: The DDRCLKPOL input to IDDRMFX1A should be connected to the DDRCLKPOL output of DQSBUFC. Figure 11-14 shows the LatticeXP2 Input Register Block configured to function in the IDDRXMFX1A mode. The DDR registers are designed to use Edge clock routing on the I/O side and the primary clock on the FPGA side. The ECLK input is used to connect to the DQS strobe coming from the DQS delay block (DQSBUFC primitive). The CLK1 and CLK2 inputs should be connected to the slow system (FPGA) clock. DDRCLKPOL is an input from the DQS Clock Polarity tree. This signal is generated by the DQS Transition detect circuit in the hardware. The additional clock transfer registers are shared with the output register block. Figure 11-14. Input Register Block in IDDRMFX1A Mode IDDRMFX1A DDR Registers Clock Transfer Registers Synchronization Registers QB DATA B E H D I QA A C ECLK CLK1 DDRCLKPOL CLK2 Figure 11-15 shows the IDDRMFX1A timing waveform. 11-11 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Figure 11-15. IDDRMFX1A Waveform DQS at I/O DDR DATA at I/O P0 N0 P0 N0 P1 N1 P2 N2 P3 N3 P4 N1 P2 N2 P3 N3 P4 ECLK( DQS shifted 90 deg) DDR DATA at IDDRMFX1A A P1 P1 P0 P2 B XX N0 N1 C XX P0 P1 P3 N4 P4 N2 P2 N3 N4 P3 P4 Case 1: DDRCLKPOL = 0 CLK1 D/E XX P0/N0 P1/N1 P2/N2 P3/N3 XX P0/N0 P1/N1 P2/N2 P3/N3 Case 2: DDRCLKPOL = 1 CLK1 D/E CLK2 QA XX P0 P1 P2 P3 QB XX N0 N1 N2 N3 ODDRMXA The ODDRMXA primitive implements the output register for both the write and the tristate functions. This primitive is used to output DDR data and the DQS strobe to the memory. All the DDR output tristate functions are also implemented using this primitive. Figure 11-16 shows the ODDRMXA primitive symbol and its I/O ports. Figure 11-16. ODDRMXA Symbol ODDRMXA CLK Q DA DB RST DQSXFER Table 11-5 provides a description of all I/O ports associated with the ODDRMXA primitive. 11-12 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Table 11-5. ODDRMXA Ports Port Name I/O Description CLK I System CLK or ECLK DA I Data at the negative edge of the clock DB I Data at the positive edge of the clock RST I Reset DQSXFER I 90-degree phase shifted clock coming from the DQSBUFC block Q I DDR data to the memory Notes: 1. RST should be held low during DDR Write operation. 2. DDR output and tristate registers do not have CE support. RST is available for the tristate DDRX mode (while reading). The LSR will default to set when used in the tristate mode. 3. When asserting reset during DDR writes, it is important to keep in mind that this only resets the flip-flops and not the latches. Figure 11-17 shows the LatticeXP2 Output Register Block configured in the ODDRXMA mode. Figure 11-17. Output Register Block in ODDRXMA Mode ODDRXMA DA A0 Q DB B0 C0 ECLK DQSXFER Figure 11-18 shows the ODDRMXA timing waveform. 11-13 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Figure 11-18. ODDRMXA Waveform DA XX P0 P1 P2 P3 P4 .. DB XX N0 N1 N2 N3 N4 .. ECLK Reg A0 XX P0 P1 P2 P3 Reg B0 XX N0 N1 N2 N3 N0 XX Latch C0 N1 P4 N4 N3 N2 DQSXFER Q XX P0 N0 P1 N1 P2 N2 P3 N3 P4 Note that the DQSXFER is inverted inside the ODDRXMA. This will cause the data coming out of the ODDRXMA to be -90 in phase with the output of the ODDRXC module. Memory Read Implementation LatticeXP2 devices contain a variety of features to simplify implementation of the read portion of a DDR interface: * DLL compensated DQS delay elements * DDR input registers * Automatic DQS to system clock domain transfer circuitry * Data Valid Module DLL Compensated DQS Delay Elements The DQS from the memory is connected to the DQS Delay element. The DQS Delay block receives a 6-bit delay control from the on-chip DQSDLL. The LatticeXP2 devices support two DQSDLL, one on the left and one on the right side of the device. The DQSDEL generated by the DQSDLL on the left side is routed to all the DQS blocks on the left and bottom/top half of the device. The delay generated by the DQSDLL on the right side is distributed to all the DQS Delay blocks on the right side and the other bottom/top half of the device. These digital delay control signals are used to delay the DQS from the memory by 90 degrees. The DQS received from the memory is delayed in each of the DQS Delay blocks and this delay DQS is used to clock the first set stage DDR input registers. DQS Transition Detect or Automatic Clock Polarity Select In a typical DDR memory interface design, the phase relation between the incoming delayed DQS strobe and the internal system clock (during the READ cycle) is unknown. Prior to the READ operation in DDR memories, DQS is in tristate (pulled by termination). Coming out of tristate, the DDR memory device drives DQS low in the Preamble State. The DQS Transition Detect block detects the first DQS rising edge after the Preamble transition and generates a signal indicating the required polarity for the FPGA system clock (DDRCLKPOL). This signal is used to control the polarity of the clock to the synchronizing registers. 11-14 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Data Valid Module The data valid module generates a DATAVALID signal. This signal indicates to the FPGA that valid data is transmitted out the input DDR registers to the FPGA core. DDR I/O Register Implementation The first set of DDR registers is used to de-mux the DDR data at the positive and negative edge of the phase shifted DQS signal. The register that captures the positive-edge data is followed by a negative-edge triggered register. This register transfers the positive edge data from the first register to the negative edge of DQS so that both the positive and negative portions of the data are now aligned to the negative edge of DQS. The second stage of registers is clocked by the FPGA clock, the polarity of this clock is selected by the DDR Clock Polarity signal generated by the DQS Transition Detect Block. The I/O Logic registers can be implemented in two modes: * Half Clock Transfer Mode * Full Clock Transfer Mode In Half Clock Transfer mode the data is transferred to the FPGA core after the second stage of the register. In Full Clock Transfer mode, an additional stage of I/O registers clocked by the FPGA clock is used to transfer the data to the FPGA core. The LatticeXP2 Family Data Sheet explains each of these circuit elements in more detail. Memory Read Implementation in Software Three primitives in the ispLEVER(R) design tools represent the capability of these three elements. The DQSDLL represents the DLL used for calibration. The IDDRMX1A/IDDRMFX1A primitive represents the DDR input registers and clock domain transfer registers with or without full clock transfer. Finally, the DQSBUFC represents the DQS delay block, the clock polarity control logic and the Data Valid module. Figures 11-19 and 11-20 show the READ interface block generated using the IPexpressTM tool in the ispLEVER software. Figure 11-19. Software Primitive Implementation for Memory READ (Half Clock Transfer) dq D DQSBUFC DQSI dqs clk DQSO DDRCLKPOL CLK READ xclk XCLK ECLK QA datain_p QB datain_n DDRCLKPOL DQSC PRMBDET read IDDRMX1A RST DQSXFER CE DATAVALID DQSDEL SCLK 6 DQSDEL reset uddcntl RST UDDCNTL LOCK DQSDLL ce 11-15 dqsc prmbdet dqsxfer datavalid lock Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Figure 11-20. Software Primitive Implementation for Memory READ (Full Clock Transfer) dq D DQSBUFC DQSI dqs clk DQSO DDRCLKPOL CLK READ xclk XCLK ECLK QA datain_p QB datain_n DDRCLKPOL DQSC PRMBDET read IDDRMFX1A RST DQSXFER CE DATAVALID DQSDEL CLK1 CLK2 6 dqsc prmbdet dqsxfer datavalid DQSDEL reset uddcntl RST UDDCNTL DQSDLL LOCK lock ce Read Timing Waveforms Figures 11-21 and 11-22 show READ data transfer for half and full clock cycle data transfer based on the results of the DQS Transition detector logic. This circuitry decides whether or not to invert the phase of FPGA system CLK to the synchronization registers based on the relative phases of PRMBDET and CLK. * Case 1: If the FPGA clock is low on the first PRMBDET transition, then DDRCLKPOL is low and no inversion is required. * Case 2: If the FPGA clock is high on the first PRMBDET, then DDRCLKPOL is high and the FPGA clock (CLK) needs to be inverted before it is used for synchronization. Figure 11-21 illustrates the DDR data timing using half clock transfer mode at different stages of the IDDRMX1A registers. The first stage of the register captures data on the positive edge as shown by signal A and the negative edge as shown by signal B. Data stream A goes through an additional half clock cycle transfer shown by signal C. Phase-aligned data streams B and C are presented to the next stage registers clocked by the FPGA clock. Figure 11-22 illustrates the DDR data timing using full clock transfer mode at different stages of IDDRMFX1A registers. In addition to the first two register stages in the half clock mode, the full clock transfer mode has an additional stage register clocked by the FPGA clock. In this case, D and E are the data streams after the second register stage presented to the final stage of registers clocked by the FPGA clock. 11-16 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Figure 11-21. READ Data Transfer When Using IDDRMX1A DQS at PIN DQ at PIN P0 N0 N1 P1 PRMBDET DQS at IOL DQ at IOL P0 A N0 P1 N1 P1 P0 B N0 N1 C P0 P1 FPGA CLK DDRCLKPOL= 0 CLK TO SYNC IO REGISTERS QA P0 QB N0 FPGA CLK DDRCLKPOL=1 CLK TO SYNC IO REGISTERS QA P0 QB N0 DATAVALID Notes: 1. DDR memory sends DQ aligned to DQS Strobe. 2. The DQS Strobe is delayed by 90 degrees using the dedicated DQS logic. 3. DQ is now center aligned to DQS Strobe. 4. PRMBDET is the Preamble detect signal generated using the DQSBUFB primitive. This is used to generate the DDRCLKPOL signal. 5. The first set of I/O registers, A and B, capture data on the positive and negative edges of DQS. 6. I/O Register C transfers data so that both data are now aligned to negative edge of DQS. 7. DDCLKPOL signal generated will determine if the FPGA CLK going into the synchronization registers need to be inverted. The DDRCLKPOL=0 when the FPGA CLK is LOW at the first rising edge of PRMBDET. The clock to the synchronization registers is not inverted. The DDRCLKPOL=1 when the FPGA CLK is HIGH at the first rising edge of PRMBDET. In this case the clock to the synchronization register is inverted. 8. The I/O synchronization registers capture data on either the rising or falling edge of the FPGA clock. 9. The DATAVALID signal goes HIGH when valid data enters the FPGA core. Once DATA VALID is asserted, it stays high until the next READ pulse. 11-17 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Figure 11-22. Read Data Transfer When Using IDDRMFX1A DQS at PIN DQ at PIN P0 N0 P1 P0 N0 N1 P2 N2 PRMBDET DQS at IOL DQ at IOL A P1 P0 N1 P2 P1 N2 P2 B N0 N1 N2 C P0 P1 P2 FPGA CLK (Case 1) DDRCLKPOL= 0 CLK TO SYNC IO REGISTERS D P0 P1 P2 E N0 N1 N2 QA P0 P1 QB N0 N1 FPGA CLK (Case 2) DDRCLKPOL=1 CLK TO SYNC IO REGISTERS D P0 P1 P2 E N0 N1 N2 QA P0 P0 QB N0 N1 DATAVALID Notes: 1. DDR memory sends DQ aligned to DQS Strobe. 2. The DQS Strobe is delayed by 90 degrees using the dedicated DQS logic. 3. DQ is now center-aligned to DQS Strobe. 4. PRMBDET is the Preamble detect signal generated using the DQSBUFB primitive. This is used to generate the DDRCLKPOL signal. 5. The first set of I/O registers, A and B, capture data on the positive and negative edges of DQS. 6. I/O register C transfers data so that both data are now aligned to the negative edge of DQS. 7. DDCLKPOL signal generated will determine if the FPGA clock going into the synchronization registers need to be inverted. The DDRCLKPOL=0 when the FPGA CLK is LOW at the first rising edge of PRMBDET. So the clock to the synchronization registers is not inverted. The DDRCLKPOL=1 when the FPGA CLK is HIGH at the first rising edge of PRMBDET. In this case the clock to the synchronization register is inverted. 8. Registers D and E capture data at the FPGA clock. 9. The data is then again registers at the FPGA clock to ensure a Full Clock Cycle transfer. 10.DATAVALID signal goes HIGH when valid data enters the FPGA core. Once DATA VALID is asserted, it stays high until the next READ pulse. 11-18 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Data Read Critical Path Data in the second stage DDR registers can be registered either on the positive edge or on the falling edge of FPGA clock depending on the DDRCLKPOL signal. In order to ensure that the data transferred to the FPGA core registers is aligned to the rising edge of the system clock, this path should be constrained with a half clock transfer. This half clock transfer can be forced in the software by assigning a multi-cycle constraint (multi-cycle of 0.5 X) on all the data paths to first PFU register. DQS Postamble At the end of a READ cycle, the DDR SDRAM device executes the READ cycle postamble and then immediately tristates both the DQ and DQS output drivers. Since neither the memory controller (FPGA) nor the DDR SDRAM device are driving DQ or DQS at that time, these signals float to a level determined by the off-chip termination resistors. While these signals are floating, noise on the DQS strobe may be interpreted as a valid strobe signal by the FPGA input buffer. This can cause the last READ data captured in the IOL input DDR registers to be overwritten before the data has been transferred to the free running resynchronization registers inside the FPGA. Figure 11-23. Postamble Effect on READ DQS at PIN DQ at PIN P0 N0 P1 N1 P0 N0 P1 N1 DQS at IOL DQ at IOL P0 A P1 B N0 N1 C P0 P1 CLK at synce reg DATAIN_P P0 DATAIN_N N0 LatticeXP2 devices have extra dedicated logic in the in the DQS Delay Block that prevents this postamble problem. The DQS postamble logic is automatically implemented when the user instantiates the DQS Delay logic (DQSBUFC software primitive) in the design. Memory Write Implementation To implement the write portion of a DDR memory interface, two streams of single data rate data must be multiplexed together with data transitioning on both edges of the clock. In addition, during a write cycle, DQS must arrive at the memory pins center-aligned with the data, DQ. Along with the DQS strobe and data this portion of the interface must also provide the CLKP, CLKN Address/Command and Data Mask (DM) signals to the memory. It is the responsibility of the FPGA output control to edge-align the DDR output signals (ADDR,CMD, DQS, but not DQ, DM) to the rising edge of the outgoing differential clock (CLKP/CLKN). Challenges encountered by the during Memory WRITE: 1. DQS needs to be center-aligned with the outgoing DDR Data, DQ. 2. Differential CLK signals (CLKP and CLKN) need to be generated. 11-19 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface 3. The controller must meet the DDR interface specification for tDSS and tDSH parameters, defined as DQS falling to CLKP rising setup and hold times. 4. The DDR output data must be muxed from two SDR streams into a single outgoing DDR data stream. All DDR output signals ("ADDR, CMD", DQS, DQ, DM) are initially aligned to the rising edge of the FPGA clock inside the FPGA core. The relative phase of the signals may be adjusted in the IOL logic before departing the FPGA. These adjustments are shown in Figure 11-24. LatticeXP2 devices contain DDR output and tri-state registers along with the DQSXFER signal generated by the DQSBUFC that allows easy implementation of the write portion of the DDR memory interfaces. The DDR output registers can be accessed in the design tools via the ODDRMXA and the ODDRXC primitives. The DQS signal and the DDR clock outputs are generated using the ODDRXC primitive. As shown in the figure, the CLKP and DQS signals are generated so that they are 180 degrees in phase with the clock. This is done by connecting "1" to the DA input and "0" to the DB inputs of the ODDRXC primitive. Refer to the DDR Generic Software Primitive section of this document to see the ODDRXC timing waveforms. The DDR clock output is then fed into a SSTL differential output buffer to generate CLKP and CLKN differential clocks. Generating the CLKN in this manner prevents any skew between the two signals. When interfacing to DDR1, SDRAM memory CLKP should be connected to the SSTL25D I/O standard. When interfacing to DDR2 memory, it should be connected to the SSTL18D I/O standard. The DQSXFER output from the DQSBUFC block is the 90-degree phase shifted clock. This 90-degree phase shifted clock is used as an input to the ODDRMXA block. The ODDRMXA is used to generate the DQ and DM data outputs going to the memory. In the ODDRMXA module, the data is first registered using the ECLK or FPGA clock input and then shifted out using the DQSXFER signal. To ensure that the data going to the memory is centeraligned to the DQS, the DQSXFER is inverted inside the ODDRXMA primitive. This will generate data that is center-aligned to the DQS. Refer to the Software Primitives section of this document for the ODDRXMA timing waveforms. The DDR interface specification for tDSS and tDSH parameters defined as DQS falling to CLKP rising setup and hold times must be met. This is accomplished by ensuring that the CLKP and DQS signals are identical in phase. The tristate control for the DQS and DQ outputs can also be implemented using the ODDRXC primitive. Figure 11-24 shows the DDR Write implementation using the DDR primitives. 11-20 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface ECLK / FPGA Clock DQSXFER (clk+90) Figure 11-24. Software Implementation for Memory Write CLKP (CLK+180) ODDRXC Q CLK "1" DA "0" DB CLKN (CLK) RST ODDRXC CLK dqstri_p DA dqstri_n DB Q RST ODDRXC "1" DA "0" DB DQS (CLK+180) Q CLK RST ODDRMXA CLK datatri_p DA datatri_n DB Q RST DQSXFER DQ (CLK+270) ODDRMXA CLK dataout_p DA dataout_n DB Q RST DQSXFER ODDRMXA CLK dmout_p DA dmout_n DB RST DQSXFER 11-21 DM (CLK+270) Q Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Write Timing Waveforms Figure 11-25 shows the DDR write side data transfer timing for the DQ Data pad and the DQS Strobe Pad. When writing to the DDR memory device, the DM (Data Mask) and the ADDR/ CMD (Address and Command) signals are also sent to the memory device along with the data and strobe signals. Figure 11-25. DDR Write Data Transfer for DQ Data DA P0 P1 P2 P3 P4 .. DB N0 N1 N2 N3 N4 .. ECLK DQS CLKP CLKN DQSXFER DQ XX P0 N0 P1 N1 P2 N2 P3 N3 P4 .. Design Rules/Guidelines Listed below are some rules and guidelines to keep in mind when implementing DDR memory interfaces in the LatticeXP2 devices. * The LatticeXP2 devices have dedicated DQ-DQS banks. Please refer to the logical signal connections of the groups in the LatticeXP2 Family Data Sheet before locking these pins. * There are two DQSDLL on the device, one for the left half and one for the right half of the device. Therefore, only one DQSDLL primitive should be instantiated for each half of the device. Since there is only one DQSDLL on each half of the device, all the DDR memory interfaces on that half of the device should run at the same frequency. Each of the DQSDLL will generate 90-degree digital delay bits for all the DQS delay blocks on that half of the device based on the reference clock input to the DLL. * When implementing a DDR SDRAM interface, all interface signals should be connected to the SSTL25 I/O standard. In the case of the DDR2 SDRAM interface, the interface signal should be connected to SSTL18 I/O standard. * For DDR2, the differential DQS signals need to be connected to SSTL18 the Differential I/O standard. * When implementing the DDR interface, the VREF1 of the bank is used to provide the reference voltage for the interface pins. Generic High Speed DDR Implementation In addition to the DDR memory interface, the I/O logic DDR registers can be used to implement high speed DDR interfaces. The Input DDR registers can operate in full clock transfer and half clock transfer modes. The DDR input and output register also support x1 and x2 gearing ratios. A gearing capability is provided to Mux/DeMux the I/O data rate (ECLK) to the FPGA clock rate (SCLK). For DDR interfaces, this ratio is slightly different than the SDR ratio. A basic 2x DDR element provides four FPGA side bits for two I/O side bits at half the clock rate on the FPGA side. 11-22 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface The data going to the DDR registers can be optionally delayed before going to the DDR register block. Generic DDR Software Primitives The IPexpress tool in the ispLEVER software can be used to generate the DDR modules. The various DDR modes described below can be configured in the IPexpress tool. The various modes are implemented using the following software primitives. * IDDRXC - DDR Generic Input * IDDRFXA - DDR Generic Input with full clock transfer (x1 gearbox) * IDDRX2B - DDR Generic Input with 2x gearing ratio. DDRX2 inputs a double data rate signal as four data streams. Two stages of DDR registers are used to convert serial DDR data at input pad into four SDR data streams entering FPGA core logic. * ODDRXC - DDR Generic Output * ODDRX2B - DDR Generic Output with 2x gearing ratio. The DDRX2 inputs four separate data streams and outputs a single data stream to the I/O buffer. * DELAYB - The DDR input can be optionally delayed before it is input to the DDR registers. The user can choose to implement a fixed delay value or use a dynamic delay. IDDRXC This primitive inputs DDR data at both edges of the CLK and generates two streams of data. The CLK to this module can be connected to either the edge clock or the primary FPGA clock. Figure 11-26 shows the primitive symbol for IDDRXC mode. Figure 11-26. IDDRXC Symbol IDDRXC QA D CLK QB CE RST Table 11-6 lists the port names and descriptions for the IDDRXC primitive. Table 11-6. IDDRXC Port Names Port Name D I/O I Definition DDR data CLK I This clock can be connected to the ECLK or the FPGA clock CE I Clock enable signal RST I Reset to the DDR register QA O Data at the positive edge of the clock QB O Data at the negative edge of the clock Figure 11-27 shows the LatticeXP2 Input Register Block configured in the IDDRXFC mode. 11-23 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Figure 11-27. Input Register Block Configured as IDDRXC IDDRXC Synchronization Registers DDR Registers DATA QB B E QA A C D CLK Edge Clock FPGA Clock Figure 11-28 shows the timing waveform when using the IDDRXC module. Figure 11-28. IDDRXC Waveform CLK at I/O DDR DATA at I/O P0 N0 P0 N0 P1 N1 P2 N2 P3 N3 P4 N1 P2 N2 P3 N3 P4 CLK at IDDRXC DDR DATA at IDDRXC A P1 P1 P0 P2 B XX N0 N1 C XX P0 P1 P3 N2 P2 N4 P4 N3 N4 P3 P4 QA XX P0 P1 P2 P3 QB XX N0 N1 N2 N3 IDDRFXA This primitive inputs DDR data at both edges of clock CLK1 and generates two streams of data aligned to clock CLK2. CLK1 can be connected either to the edge clock or the internal FPGA clock. If the Edge clock input is used for CLK1 then CLK2 should be generated from the same clock going to CLK1. 11-24 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Figure 11-29. IDDRFXA Symbol IDDRFXA QA D CLK1 QB CLK2 CE RST Table 11-7 lists the port names and descriptions for the IDDRFXA primitive. Table 11-7. IDDRFXA Port Names Port Name I/O Description D I DDR data CLK1 I This clock can be connected to the ECLK or the FPGA clock CLK2 I This clock should be connected to the FPGA clock CE I Clock Enable signal RST I Reset to the DDR register QA O Data at the positive edge of the clock QB O Data at the negative edge of the clock Figure 11-31 shows the LatticeXP2 Input Register Block configured in the IDDRXFXA mode. CLK1 used to register the DDR registers and the first set of synchronization registers. CLK2 is used by the third stage of registers and should be clocked by the FPGA clock. These clock transfer registers are shared with the output register block. Figure 11-30. Input Register Block configured as IDDRFXA IDDRFXA DDR Registers Synchronization Registers Clock Transfer Registers E H D I DATA QB B QA A C CLK1 Edge Clock Figure 11-31 shows the timing waveform when using the IDDRFXA module. 11-25 CLK2 FPGA Clock Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Figure 11-31. IDDRFXA Waveform CLK at I/O DDR DATA at I/O P0 N0 P0 N0 P1 N1 P2 N2 P3 N3 P4 N1 P2 N2 P3 N3 P4 CLK1 (shifted 90 deg) DDR DATA at IDDRFXA A P1 P2 P1 P0 B XX N0 N1 C XX P0 P1 D/E P2 P1/N1 P0/N0 XX P4 P3 N2 N4 N3 N4 P3 P4 P2/N2 P3/N3 CLK2 QA XX P0 P1 P2 P3 QB XX N0 N1 N2 N3 11-26 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface IDDRX2B This module is used when a gearing function is required. This primitive inputs the DDR data at both edges of the edge clock and generates four streams of data aligned to SCLK. SCLK is always half the frequency of ECLK. It is recommended that the CLKDIV module or PLL be used to generate the SCLK from the ECLK. Figure 11-32 shows the primitive symbol for the IDDRX2B mode. Figure 11-32. IDDRX2B Symbol IDDRX2B D QA0 ECLK QA1 SCLK QB0 CE QB1 RST Table 11-8 lists the port names and descriptions for the IDDRX2B primitive. Table 11-8. IDDRX2B Port Names Port Name I/O Description D I DDR data ECLK I This clock can be connected to the fast edge clock SCLK I This clock should be connected to the FPGA clock CE I Clock enable signal RST I Reset to the DDR register QA0, QA1 O Data at the positive edge of the clock QB0, QB1 O Data at the negative edge of the clock Figure 11-33 shows the LatticeXP2 Input Register Block configured in the IDDRX2B mode. The DDR registers and the first set of synchronization registers are clocked by the ECLK input. The SCLK is used to clock the third stage of register. This primitive will output four streams of data. The 2x gearing function is implemented by using the synchronization registers of the complementary PIO. The clock transfer registers are shared with the output register block. 11-27 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Figure 11-33. Input Register Block Configured as IDDRX2B IDDRX2B Synchronization Registers DDR Registers Clock Transfer Registers DATA QB1 B E H D I QA1 A C TRUE PIO in LVDS sysI/O Pair COMP PIO in LVDS sysI/O Pair Synchronization Registers Clock Transfer Registers G J F K QB0 QA0 ECLK Figure 11-34 shows the timing waveform using the IDDRX2B module. 11-28 SCLK Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Figure 11-34. IDDRX2B Waveform CLK at I/O DDR DATA at I/O P0 N0 P0 N0 P1 N1 P2 N2 P3 N3 P4 N1 P2 N2 P3 N3 P4 ECLK (shifted 90 deg) DDR DATA at IDDRX2B A P1 P1 P0 P2 P3 N4 P4 B XX N0 N1 N2 N3 N4 C XX P0 P1 P2 P3 P4 D/E P1/N1 P0/N0 XX XX F/G P0/N0 P2/N2 P3/N3 P1/N1 P2/N2 SCLK QB1 XX P0 P2 QA1 XX P1 P3 QB0 XX N0 N2 QB1 XX N1 N3 ODDRXC This is the DDR output module. This primitive will input two data streams and mux them together to generate a single stream of data going to the sysIOTM buffer. The CLK to this module can be connected to the edge clock or to the FPGA clock. This primitive is also used for when DDR function is required for the tristate signal. Figure 11-35 shows the primitive symbol for the ODDRXC mode. Figure 11-35. ODDRXC Symbol ODDRXC Q CLK DA DB RST Table 11-9 lists the port names and descriptions for the ODDRXC primitive. 11-29 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Table 11-9. ODDRXC Port Names Port Name I/O Definition DA I Data at the negative edge of the clock DB I Data at the positive edge of the clock CLK I This clock can be connected to the edge clock or to the FPGA clock RST I Reset signal Q O DDR data output Figure 11-36 shows the Output Register Block of the LatticeXP2 device configured in ODDRXC mode. Figure 11-36. Output Register Block in ODDRC Mode ODDRXC DA A0 Q DB B0 C0 ECLK Figure 11-37 shows the timing waveform when using the ODDRXC module. Figure 11-37. ODDRXC Waveform DA XX P0 P1 P2 P3 P4 .. DB XX N0 N1 N2 N3 N4 .. ECLK Reg A0 XX P0 P1 P2 P3 Reg B0 XX N0 N1 N2 N3 Latch C0 XX Q XX N0 P0 N0 N1 P1 N1 P4 N4 N3 N2 P2 N2 P3 N3 P4 ODDRX2B This DDR output module can be used when a gearbox function is required. This primitive inputs four data streams and muxes them together to generate a single stream of data going to the sysIO buffer. 11-30 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface DDR registers of the complementary PIO are used in this mode. The complementary PIO register can no longer be used to perform the DDR function. There are two clocks going to this primitive. The ECLK is connected to the faster edge clock and the SCLK is connected to the slower FPGA clock. The DDR data output of this primitive is aligned to the faster edge clock. Figure 11-38 shows the primitive symbol for the ODDRX2B mode. Figure 11-38. ODDRX2B Symbol ODDRX2B Q ECLK SCLK DA0 DA1 DB0 DB1 RST Table 11-10 lists the port names and descriptions for the ODDRX2B primitive. Table 11-10. ODDRX2B Port Names Port Name I/O Description DA0, DB0 I DA1, DB1 I Data at the negative edge of the clock Data at the positive edge of the clock ECLK I This clock should be connected to the faster edge clock SCLK I This clock should be connected to the slower FPGA clock RST I Reset signal Q O DDR data output Figure 11-39 shows the LatticeXP2 Output Register Block in the ODDRX2B mode. 11-31 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Figure 11-39. Output Register Block Configured in ODDRX2B Mode ODDRX2B D0 DB0 Q A0 DB1 B0 E0 C0 F0 TRUE PIO in LVDS sysI/O Pair COMP PIO in LVDS sysI/O Pair DA0 A1 DA1 B1 SCLK C1 ECLK Figure 11-40 shows the timing waveform when using the ODDRXC module. 11-32 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Figure 11-40. ODDRX2B Waveform DB0 XX d1 d5 d9 d13 d17 .. DB1 XX d3 d7 d11 d15 d19 .. SCLK Reg A0 XX d1 d5 d9 d13 Reg B0 XX d3 d7 d11 d15 Latch C0 XX A ( Mux0) XX d3 d1 d7 d3 d5 d17 d19 d15 d11 d7 d9 DA0 XX d0 d4 d8 d12 DA1 XX d2 d6 d10 d14 d11 d13 d15 d17 .. d16 d18 .. SCLK Reg A1 Reg B1 XX d4 d0 XX d6 d2 d2 d8 d12 d16 d10 d14 d18 d6 d14 d10 Latch C1 XX B ( Mux1) XX d0 d2 d4 d6 d8 d10 d12 d14 d16 Copy of A ( Mux0) XX d1 d3 d5 d7 d9 d11 d13 d15 d17 ECLK Reg D0 XX d0 d2 d4 d6 d8 d10 d12 d14 Reg E0 XX d1 d3 d5 d7 d9 d11 d13 d15 Latch F0 XX d1 Q XX d0 d1 d3 d5 d7 d2 d3 d4 d5 d6 d9 d7 d8 d11 d13 d15 d9 d10 d11 d12 d13 d14 DELAYB Data going to the DDR registers can be optionally delayed using the Delay block. The Delay block receives 4-bit delay control. The 4-bit delay can be set using fixed multiplier values or it can be controlled by the user. The DELAYB block is available for use with the input DDR registers. The DELAYB block can be configured when generating the DDR input modules in the IPexpress tool of the software. The delay can be adjusted in 35ps steps. Users can choose from three types of delay values: 1. Dynamic - The delay value is controlled by the user logic using the DEL[3:0] input of the DELAYB block. 11-33 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface 2. Fixed - When choosing the fixed value, the user will also need to choose from one of the 16 multiplier values. This will tie the inputs DEL[3:0] of the DELAYB block to a fixed value depending on the multiplier value chosen. 3. FIXED_XGMII - The DEL [3:0] will be configured with the delay value required when implementing a XGMII interface. Figure 11-41 shows the primitive symbol for the DELAYB mode. Figure 11-41. DELAYB Symbol DELAYB Z A DEL(0:3) Table 11-11 lists the port names and descriptions for the DELAYB primitive. Table 11-11. DELAYB Port Names Port Name A I/O Definition I DDR input from the sysIO buffer DEL (0:3) I Delay inputs Z O Delay DDR data Design Rules/Guidelines Listed below are some rules and guidelines for implementing generic DDR interfaces in LatticeXP2 devices. * When implementing a 2x gearing mode, the complement PIO registers are used. This complementary PIO register can no longer be used and should not be connected. DDR Usage in ispLEVER IPexpress This section describes how IPexpress is used to generate the DDR modules in ispLEVER. If you are using Lattice DiamondTM design software, refer to Appendix A for information on how DDR modules are generated in Diamond. IPexpress can be used to configure and generate the DDR Memory Interface and Generic DDR Module. The tool will generate an HDL module that will contain the DDR primitives. This module can be using in the top level design. Figure 11-42 shows the main window of IPexpress. The DDR_Generic and DDR_MEM options under Architechture->IO are used to configure the DDR modules. 11-34 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Figure 11-42. IPexpress Main Window DDR Generic Figure 11-43 shows the main window when DDR_Generic is selected. The only entry required in this window is the module name. Other entries are set to the project settings. The user may change these entries if desired. After entering the module name, click on Customize to open the Configuration Tab window as shown in Figure 11-44. Figure 11-43. IPexpress Main Window for DDR_Generic 11-35 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Configuration Tab The Configuration Tab lists all user-accessible attributes with default values set. Upon completion, click Generate to generate source and constraint files. The user may choose to use the .lpc file to load parameters. Figure 11-44. Configuration Tab for DDR_Generic The user can change the Mode parameter to choose either Input, Output, Bidirection or Tristate DDR module. The other configuration parameters will change according to the mode selected. The Delay parameter is only available for Input and Bidirectional modes. Similarly the Multiplier for Fixed Delay parameter is only available when the Delay parameter is configured to Fixed. Table 11-12. User Parameters in the IPexpress GUI User Parameters Description Mode Mode selection for the DDR block. Data Width Width of the data bus. Values/Range Default Input, Output, Bidirectional, Tristate Input 1-64 8 1 Gearing ratio selection. 1x, 2x 1x Delay Input delay configuration Dynamic, Fixed, Fixed XGMII Dynamic Multiplier for Fixed Delay Fixed delay setting. Available only when delay is configured as fixed. 0-15 0 Use Single Clk for 1x Allows for the selection of a single clock for the gearing logic. On/Off Off Gearing Ratio 1. Only 1x available when Mode is Bidirection or Tristate. DDR_MEM Figure 11-45 shows the main window when DDR_MEM is selected. Similar to the DDR_Generic, the only entry required here is the module name. Other entries are set to the project settings. The user may change these entries 11-36 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface if desired. After entering the module name, click on Customize to open the Configuration Tab window as shown in Figure 11-46. Figure 11-45. IPexpress Main Window for DDR_MEM Configuration Tab The Configuration Tab lists all user-accessible attributes with default values set. Upon completion, click Generate to generate source and constraint files. The user may choose to use the .lpc file to load parameters. 11-37 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Figure 11-46. Configuration Tab for DDR_MEM The user can change the Mode parameter to choose either the DDR or DDR2 interface. The other configuration parameters will change according to the Mode selected. The Number of DQS parameter determines the number of DDR interfaces. The software will assume there are eight data bits for every DQS. The user can also choose the frequency of operation and the DDR DLL will be configured to this frequency. The user has an option to enable the clock enable and tristate enables for the DDR registers. It is recommend that the Lock/Jitter be enabled if the DDR interface is running at 150MHz or higher. The parameters available depend on the mode selected. Tables 11-13 and 11-14 describe all user parameters in the IPexpress GUI and their usage for modes DDR and DDR2. Table 11-13. User Parameters in the IPexpress GUI when in DDR Mode User Parameters Description Values/Range Default SSTL25_I, SSTL25_II SSTL25_I 8-64 8 I/O Buffer Configuration I/O Standard used for the Interface. This will also depend on the Mode selected. Data Width Width of the Data bus Number of DQS Number of DQS will determine the number of DQS Groups 1, 2, 4, 8 1 Frequency of DQS DDR Interface Frequency. This is also input to the DDR DLL. The values will depend on the mode selected. 100MHz, 133MHz, 166MHz, 200MHz 200MHz Lock/Jitter Sensitivity DLL Sensitivity to Jitter High, Low High LSR for DDR Input Register LSR Control RESET, SET RESET Create Clock Enable for DDR Input Register Create Clock enable inputs to the block On/Off Off Tri-state Enable for DDR Output Registers Creates Tri-state control for the DDR data output registers. On/Off On DDR Tristate enable for the DQS output Creates Tristate control for DQS output On/Off On 11-38 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Table 11-14. User Parameters in the IPexpress GUI when in DDR2 Mode User Parameters I/O Buffer Configuration Description I/O Standard used for the Interface. This will also depend on the Mode selected. Values/Range Default SSTL18_I, SSTL18_II SSTL18_I Data Width Width of the Data bus 8-64 8 Number of DQS Number of DQS will determine the number of DQS Groups 1, 2, 4, 8 1 Frequency of DQS DDR Interface Frequency. This is also input to the DDR DLL. The values will depend on the mode selected. 166MHz, 200MHz, 266MHz 200MHz Lock/Jitter Sensitivity DLL Sensitivity to Jitter LSR for DDR Input Register LSR Control High, Low High RESET, SET RESET Create Clock Enable for DDR Input Register Create Clock enable inputs to the block On/Off Off Tri-state Enable for DDR Output Registers Creates Tri-state control for the DDR data output registers. On/Off On DDR Tristate enable for the DQS output Creates Tristate control for DQS output On/Off On DQS Buffer Configuration for DDR2 DQS Buffer can be configured as Differential On/Off Off FCRAM ("Fast Cycle Random Access Memory") Interface FCRAM is a DDR-type DRAM, which performs data output at both the rising and falling edges of the clock. FCRAM devices operate at a core voltage of 2.5V with SSTL Class II I/O. It has enhanced both the core and peripheral logic of the SDRAM. In FCRAM the address and command signals are synchronized with the clock input, and the data pins are synchronized with the DQS signal. Data output takes place at both the rising and falling edges of the DQS. DQS is in phase with the clock input of the device. The DDR SDRAM and DDR FCRAM controller will have different pinouts. LatticeXP2 devices can implement the FCRAM interface using dedicated DQS logic, input DDR registers and output DDR registers, as described in the Implementing Memory Interfaces section of this document. Generation of address and control signals for FCRAM are different than in DDR SDRAM devices. Please refer to the FCRAM data sheets to see detailed specifications. Toshiba, Inc. and Fujitsu, Inc. offer FCRAM devices in 256Mb densities. They are available in x8 or x16 configurations. Board Design Guidelines The most common challenge associated with implementing DDR memory interfaces is the board design and layout. It is required that users strictly follow the guidelines recommended by memory device vendors. Some of the common recommendations include matching trace lengths of interface signals to avoid skew, proper DQ-DQS signal grouping, proper termination of the SSTL2 or SSTL18 I/O Standard, proper VREF and VTT generation decoupling and proper PCB routing. The following documents include board layout guidelines: * www.idt.com, IDT, PCB Design for Double Data Rate Memory * www.motorola.com, AN2582, Hardware and Layout Design Considerations for DDR Interfaces References * www.jedec.org, JEDEC Standard 79, Double Data Rate (DDR) SDRAM Specification * www.micron.com, DDR SDRAM Data Sheets 11-39 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface * www.infinion.com, DDR SDRAM Data Sheets * www.samsung.com, DDR SDRAM Data Sheets * www.toshiba.com, DDR FCRAM Data Sheet * www.fujitsu.com, DDR FCRAM Data Sheet * RD1019, QDR Memory Controller Reference Design * IPUG35, DDR1 & DDR2 SDRAM Controller (Pipelined Versions) User's Guide Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com Revision History Date Version Change Summary February 2007 01.0 Initial release. May 2007 01.1 Updated the port names on the input DDR block diagrams. Updated text in DQS Transition Detect section under Memory Read Implementation. February 2009 01.2 Updated DLL Compensated DQS Delay Elements text section. June 2009 01.3 Updated DQSDLL Update Control text section. June 2010 01.4 Added Appendix A - DDR Generation using Diamond IPexpress 11-40 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Appendix A. DDR Generation using Diamond IPexpress The IPexpress tool in the Lattice Diamond design software can be used to configure and generate the DDR Memory Interface and Generic DDR Module. The tool will generate an HDL module that contains the DDR primitives. This module can be using in the top level design. Figure 11-47 shows the main window of IPexpress. The DDR_Generic and DDR_MEM options under Architechture > IO are used to configure the DDR modules. Figure 11-47. IPexpress Main Window DDR Generic Figure 11-48 shows the main window when DDR_Generic is selected. The only entry required in this window is the module name. Other entries are set to the project settings. The user may change these entries if desired. After entering the module name, click on Customize to open the Configuration Tab window as shown in Figure 11-49. 11-41 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Figure 11-48. IPexpress Main Window for DDR_Generic Configuration Tab The Configuration Tab lists all user-accessible attributes with default values set. Upon completion, click Generate to generate source and constraint files. The user may choose to use the .lpx file to load parameters. Figure 11-49. Configuration Tab for DDR_Generic 11-42 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface The user can change the Mode parameter to choose either the Input, Output, Bi-directional or Tristate DDR module. The other configuration parameters will change according to the mode selected. The Delay parameter is only available for Input and Bi-directional modes. Similarly, the Multiplier for the Fixed Delay parameter is only available when the Delay parameter is configured to Fixed. Table 11-15. User Parameters in the IPexpress GUI User Parameters Description Values/Range Default Input, Output, Bidirectional, Tristate Input Mode Mode selection for the DDR block. Data Width Width of the data bus. 1-64 8 Gearing Ratio Gearing ratio selection. 1x, 2x1 1x Delay Input delay configuration Dynamic, Fixed, Fixed XGMII Dynamic Multiplier for Fixed Delay Fixed delay setting. Available only when delay is configured as fixed. 0-15 0 Use Single Clk for 1x Allows for the selection of a single clock for the gearing logic. On/Off Off 1. Only 1x available when Mode is Bidirection or Tristate. DDR_MEM Figure 11-50 shows the main window when DDR_MEM is selected. Similar to DDR_Generic, the only entry required is the module name. Other entries are set to the project settings. The user may change these entries if desired. After entering the module name, click on Customize to open the Configuration Tab window as shown in Figure 11-51. Figure 11-50. IPexpress Main Window for DDR_MEM 11-43 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Configuration Tab The Configuration Tab lists all user-accessible attributes with default values set. Upon completion, click Generate to generate source and constraint files. The user may choose to use the .lpx file to load parameters. Figure 11-51. Configuration Tab for DDR_MEM The user can change the Mode parameter to choose either the DDR or DDR2 interface. The other configuration parameters will change according to the Mode selected. The Number of DQS parameter determines the number of DDR interfaces. The software will assume there are eight data bits for every DQS. The user can choose the frequency of operation and the DDR DLL will be configured to this frequency. The user has the option to enable the clock enable and tristate enables for the DDR registers. It is recommend that the Lock/Jitter be enabled if the DDR interface is running at 150 MHz or higher. The parameters available depend on the mode selected. Tables 11-16 and 11-17 describe all user parameters in the IPexpress GUI and their usage for modes DDR and DDR2. 11-44 Lattice Semiconductor LatticeXP2 High-Speed I/O Interface Table 11-16. User Parameters in the IPexpress GUI when in DDR Mode User Parameters Description Values/Range Default SSTL25_I, SSTL25_II SSTL25_I 8-64 8 I/O Buffer Configuration I/O Standard used for the Interface. This will also depend on the Mode selected. Data Width Width of the Data bus Number of DQS Number of DQS will determine the number of DQS Groups 1, 2, 4, 8 1 Frequency of DQS DDR Interface Frequency. This is also input to the DDR DLL. The values will depend on the mode selected. 100MHz, 133MHz, 166MHz, 200MHz 200MHz Lock/Jitter Sensitivity DLL Sensitivity to Jitter High, Low High LSR for DDR Input Register LSR Control RESET, SET RESET Create Clock Enable for DDR Input Register Create Clock enable inputs to the block On/Off Off Tri-state Enable for DDR Output Registers Creates Tri-state control for the DDR data output registers. On/Off On DDR Tristate enable for the DQS output Creates Tristate control for DQS output On/Off On Values/Range Default SSTL18_I, SSTL18_II SSTL18_I Table 11-17. User Parameters in the IPexpress GUI when in DDR2 Mode User Parameters I/O Buffer Configuration Description I/O Standard used for the Interface. This will also depend on the Mode selected. Data Width Width of the Data bus 8-64 8 Number of DQS Number of DQS will determine the number of DQS Groups 1, 2, 4, 8 1 Frequency of DQS DDR Interface Frequency. This is also input to the DDR DLL. The values will depend on the mode selected. 166MHz, 200MHz, 266MHz 200MHz Lock/Jitter Sensitivity DLL Sensitivity to Jitter LSR for DDR Input Register LSR Control High, Low High RESET, SET RESET Create Clock Enable for DDR Input Register Create Clock enable inputs to the block On/Off Off Tri-state Enable for DDR Output Registers Creates Tri-state control for the DDR data output registers. On/Off On DDR Tristate enable for the DQS output Creates Tristate control for DQS output On/Off On DQS Buffer Configuration for DDR2 DQS Buffer can be configured as Differential On/Off Off 11-45 Power Estimation and Management for LatticeXP2 Devices February 2007 Technical Note TN1139 Introduction One requirement for design engineers using programmable devices is the ability to calculate the power dissipation for a particular device used on a board. Lattice's ispLEVER(R) design tools include the Power Calculator tool, which allows designers to calculate the power dissipation for a given device. This technical note describes how to use the Power Calculator tool to calculate the power consumption of the LatticeXP2TM family of devices. General guidelines to reduce power consumption are also included. Power Supply Sequencing and Hot Socketing LatticeXP2 devices have been designed to ensure predictable behavior during power-up and power-down. Power supplies can be sequenced in any order. During power-up and power-down sequences, the I/Os remain in tri-state until the power supply voltage is high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled to within the limits specified in the LatticeXP2 Family Data Sheet, allowing for easy integration with the rest of the system. These capabilities make the LatticeXP2 ideal for many multiple power supply and hot-swap applications. Recommended Power-up Sequence As described above, the supplies can be sequenced in any order. However, once internal power good is achieved (determined by VCC, VCCAUX, VCCIO Bank x) the device releases the I/Os from tri-state and the management of the I/Os becomes the designer's responsibility. To simplify a system design, it is recommended that supplies be sequenced in the following order: VCCIO, VCC, VCCAUX. If VCCIO is tied to VCC or VCCAUX, then it is recommended that VCCIO and the associated power supply are powered up before the remaining supply. Please refer to the Hot Socketing section of the LatticeXP2 Family Data Sheet for more information. Power Calculator Hardware Assumptions Power consumption for a device can be coarsely broken down into the DC portion and the AC portion. The Power Calculator reports the power dissipation in terms of: 1. DC portion of the power consumption. 2. AC portion of the power consumption. The DC Power (or the Static power consumption) is the total power consumption of the used and the unused resources. These power components are fixed for each resource used and depends upon the number of resource units utilized. The DC component also includes the static power dissipation for the unused resources of the device. The AC portion of power consumption is associated with the used resources. This is the dynamic part of the power consumption. Its power dissipation is directly proportional to the frequency at which the resource is running and the number of resource units used. Power Calculation Equations The following are the power equations used in the Power Calculator: (c) 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 12-1 tn1139_01.0 Power Estimation and Management for LatticeXP2 Devices Lattice Semiconductor Total DC Power (Resource) = Total DC Power of Used Portion + Total DC Power of Unused Portion = [DC Leakage per Resource when Used * NRESOURCE] + [DC Leakage per Resource when Unused * (NTOTAL RESOURCE - NRESOURCE)] Where: NTOTAL RESOURCE NRESOURCE is the total number of resources in a device is the number of resources used in the design The total DC power consumption for all the resources as per the design data is the Quiescent Power in the Power Calculator. The AC Power is governed by the following equation: Total AC Power (Resource) = KRESOURCE * fMAX * AFRESOURCE * NRESOURCE Where: NTOTALRESOURCE NRESOURCE KRESOURCE fMAX AFRESOURCE is the number of resources in a device is the number of resources used in the design is the power constant for the resource in mW/MHz is the max frequency at which the resource is running. Frequency is measured in MHz. is the activity factor for the resource group.The Activity Factor is a percentage of the switching frequency. For example, the power consumption of the Slice portion is calculated in the following equation, Total DC Power (Slice) = Total DC Power of Used Portion + Total DC Power of Unused Portion = [DC Leakage per Slice when Used * NSLICE] = +[DC Leakage per Slice when Unused * (NTOTALSLICE - NSLICE)] Total AC Power (Slice) = KSLICE * fMAX * AFSLICE * NSLICE Power Calculations The Power Calculator allows users to estimate power consumption at three different levels: 1. Estimate of the utilized resources before completing place and route 2. Post place and route design 3. Post place and route, post trace, and post simulation For the first level of estimation, the user provides estimates of device usage in the Power Calculator Wizard and the tool provides a rough estimate of the power consumption. The second level is a more accurate approach. The user imports the actual device utilization by importing the post Place and Route netlist (NCD) file. The third level brings even more accuracy to the calculation by importing the Trace (TWR) file to populate the maximum frequencies (fMAX) into the tool. Users also have the option of importing the information from the post simulation (VCD) file and calculating the Activity Factor and Toggle Rates of various components. These three stages of power calculation are discussed in detail in the following sections of this document. 12-2 Power Estimation and Management for LatticeXP2 Devices Lattice Semiconductor Using the Power Calculator Starting the Power Calculator The Power Calculator can be launched by one of two methods. The first method is to click the Power Calculator button in the toolbar as shown in Figure 12-1. Figure 12-1. Starting Power Calculator from the Toolbar The Power Calculator can also be launched by going to the Tools menu and selecting the option Power Calculator as shown in Figure 12-2. 12-3 Power Estimation and Management for LatticeXP2 Devices Lattice Semiconductor Figure 12-2. Starting Power Calculator from Tools Menu Note: The Power Calculator does not support some older Lattice devices. The toolbar button and menu item are only present when supported devices are selected. Creating a Power Calculator Project After starting the Power Calculator, the Power Calculator window is displayed. Click on the File menu and select New to get to the Start Project window as shown in Figure 12-3. Figure 12-3. Power Calculator Start Project Window (Create New Project) 12-4 Power Estimation and Management for LatticeXP2 Devices Lattice Semiconductor The Start Project window is used to create a new Power Calculator Project (*.pep project). Three pieces of data are entered into the Start Project window. 1. The Power Calculator project name by default is same as the Project Navigator project name. It can be changed, if desired. 2. Project Directory is where the Power Calculator project (*.pep) file will be stored. By default it is stored in the main project folder. 3. The NCD file is automatically selected, if available, or users can browse to the NCD file in a different location. Power Calculator Main Window The Power Calculator main window is shown in Figure 4. Figure 12-4. Power Calculator Main Window (Type View) The top pane of the window shows information about the device family, device and the part number as it appears in the Project Navigator. The VCC used for the power calculation is also listed. Users have the choice of selecting the core voltage VCC with +5% of the nominal value (or values). The option of selecting VCCJ is also available. Users can provide the ambient temperature, and the junction temperature is calculated based on that. Users can also enter values for airflow in Linear Feet per Minute (LFM) along with heat sink to obtain the junction temperature. The table near the top of the Power Calculator main window summarizes the currents and power consumption associated with each type of power supply for the device. This also takes into consideration the I/O power supplies. 12-5 Power Estimation and Management for LatticeXP2 Devices Lattice Semiconductor In the middle pane of the window, there are three tabs: 1. Power View The first tab is the Power view. This tab provides an interactive spreadsheet type interface with all values in terms of power consumption mW. The first column breaks down the design in terms of clock domains. The second and third columns, which are shaded blue, provide the DC (static) and AC (dynamic) power consumption, respectively. Next are four columns shaded blue. These provide information on the I/O DC and AC power, including core voltage, VCC and the I/O voltage supply, VCCIO. The first three rows show the Quiescent Power for VCC, VCCAUX and VCCJ. These are DC power numbers for a blank device or device with no resource utilization. Some of the cells are shaded yellow. These cells are editable cells and users can type in values such as frequency, activity factors and resource utilization. The second tab (the Report tab) is the summary of the Power View. This report is in text format and provides details of the power consumption. 2. ICC View The second tab is the ICC view. This tab is exactly same as the Power View tab, except that all values are expressed in terms of current or mA. 3. Report View The third and final tab is the Report view. This is an HTML type of Power Calculator report. It summarizes the contents of the Power and ICC views. The final pane, the lower pane of the window, is the log pane where users can see a log of the various operations in the Power Calculator. Figure 12-5. Power Calculator Main Window (Power Report View) 12-6 Power Estimation and Management for LatticeXP2 Devices Lattice Semiconductor Power Calculator Wizard The Power Calculator Wizard allows users to estimate the power consumption of a design. This estimation is done before the design is created. It is important for the user to understand the logic requirements of the design. The wizard allows the user to provide the required parameters and then estimates the power consumption of the device. To start the Power Calculator in the wizard mode, go to the File menu and select Wizard. Alternatively, you can click on the Wizard button to see the Power Calculator - Wizard window as shown in Figure 12-6. Select the option Create a new Project and check the Wizard check box in the Power Calculator Start Project window. Provide the project name and the project folder and click Continue. Since this is power estimation before the actual design, no NCD file is required. Figure 12-6. Power Calculator Start Project Window (Using the New Project Window Wizard) In the next screen, the device family, device, and part number are chosen. After making the proper selections, click Continue. This is shown in Figure 7. 12-7 Power Estimation and Management for LatticeXP2 Devices Lattice Semiconductor Figure 12-7. Power Calculator Wizard Mode Window - Device Selection In the following screens (Figures 8-12) users can select additional resources, such as I/O types, clock name, frequency at which the clock in running and other parameters by selecting the appropriate resource using the pulldown Type menu. 1. Routing Resources 2. Logic 3. EBR 4. I/O 5. PLL 6. Clock Tree The number in these windows refers to the number of clocks and the index corresponds to each of the clocks. By default, the clock names are clk_1, clk_2, and so on. Clock names can be changed by typing in the Clock Name text box. For each clock domain and resource, parameters such as Frequency and Activity Factor can be specified. In the final window, click the Create button for each clock driven resource to include the parameters specified for it. 12-8 Power Estimation and Management for LatticeXP2 Devices Lattice Semiconductor Figure 12-8. Power Calculator Wizard Mode Window - Resource Specification These parameters are then used in the Power Type View window, which can be seen upon clicking on Finish (see Figure 9). Figure 12-9. Power Calculator Wizard Mode - Main Window 12-9 Power Estimation and Management for LatticeXP2 Devices Lattice Semiconductor Creating a New Project Without the NCD File A new project can be started without the NCD file, either by using the wizard (as discussed above) or by selecting the Create a New Project option in the Power Calculator - Start Project. The project name and project directory must be provided. After clicking Continue the Power Calculator main window will be displayed. However, in this case there are no resources added. The power estimation row for the routing resources is always available in the Power Calculator. Additional information such as the Slice, EBR, I/O, PLL, and clock tree utilization must be provided to calculate the power consumption. For example, if the user wants to add the logic resources shown in Figure 10, right-click on Logic >> and then select Add Row in the menu that pops up. Figure 12-10. Power Calculator Main Window - Adding Resources This adds a new row for the logic resource utilization with clock domain named clk_1. Similarly, other resources like EBR, I/Os, PLLs and routing can be added. Each of these resources is used for AC power estimation and categorized by clock domains. Creating a New Project with the NCD File If the post place and routed NCD file is available, the Power Calculator can use it to import accurate information about the design data and resource utilization for power calculation. After starting the Power Calculator, the NCD file is automatically placed in the NCD File option, if it is available in the project directory. Otherwise, browse to the NCD file using the Power Calculator. 12-10 Power Estimation and Management for LatticeXP2 Devices Lattice Semiconductor Figure 12-11. Power Calculator Start Project Window with Post PAR NCD File The information from the NCD file is automatically inserted into the correct rows and Power Calculator uses the Clock names from the design as shown in Figure 12-12. Figure 12-12. Power Calculator Main Window - Resource Utilization Picked Up from the NCD File 12-11 Power Estimation and Management for LatticeXP2 Devices Lattice Semiconductor Opening an Existing Project The Power Calculator - Start Project window also allows users to open an existing project. Select Open Existing Project and browse to the *.pep project file and click Continue. This opens the existing project in windows similar to those discussed above (see Figure 12-13). Figure 12-13. Opening an Existing Project in Power Calculator Importing a Simulation File (VCD) A post simulation VCD file can be imported into the Power Calculator project to estimate a design's activity factors. Under the File menu, select Open Simulation File and browse to the VCD file location and select Open. All AF and Toggle Rate fields are then populated with the information from this file, as shown in Figure 12-14. Figure 12-14. Importing a Simulation File in an Existing Power Calculator Project 12-12 Power Estimation and Management for LatticeXP2 Devices Lattice Semiconductor Importing a Trace Report File (TWR) Post Trace TWR file can be imported into the Power Calculator project to estimate a design's activity factors. Under the File menu, select Open Trace Report File, browse to the TWR file location and select Open. All Freq. (MHz) fields are then populated with the information from this file, as shown in Figure 12-15. Figure 12-15. Importing a Trace Report File to a Power Calculator Project Activity Factor and Toggle Rate Activity Factor% (or AF%) is defined as the percentage of frequency (or time) that a signal is active or toggling of the output. Most of the resources associated with a clock domain are running or toggling at some percentage of the frequency at which the clock is running. Users must provide this value as a percentage under the AF% column in the Power Calculator tool. Another term used is the I/O Toggle Rate or the I/O Toggle Frequency. The AF% is applicable to the PFU, routing and memory read write ports, etc. The activity of the I/Os is determined by the signals provided by the user (for inputs) or as an output of the design (for outputs). Therefore, the rates at which I/Os toggle define their activity. The Toggle Rate (or TR) in MHz of the output is defined by the following equation: Toggle Rate (MHz) = 1/2 * fMAX * AF% Users must provide the TR (MHz) value for the I/O instead of providing the Frequency and AF% in case of other resources. The AF can be calculated for each routing resource, output or PFU. However, it involves long calculations. The general recommendation for a design occupying roughly 30% to 70% of the device is an AF% of 15% to 25%. This is an average value that can be seen most of the design. An accurate value for an activity factor depends upon clock frequency, stimulus to the design and the final output. 12-13 Power Estimation and Management for LatticeXP2 Devices Lattice Semiconductor Ambient and Junction Temperatures and Airflow A common method of characterizing a packaged device's thermal performance is with thermal resistance, or . For a semiconductor device, thermal resistance indicates the steady state temperature rise of the die junction above a given reference for each watt of power (heat) dissipated at the die surface. Its units are C/W. The most common examples are JA, Thermal Resistance Junction-to-Ambient (in C/W) and JC, Thermal Resistance Junction-to-Case (also in C/W). Another factor is JB, Thermal Resistance Junction-to-Board (in C/W). Knowing the reference (i.e. ambient, case, or board) temperature, the power, and the relevant value, the junction temp can be calculated by the following equations. TJ = TA + JA * P (1) TJ = TC + JC * P (2) TJ = TB + JB * P (3) While TJ, TA,TC and TB are the Junction, Ambient, Case (or Package) and Board temperatures (in C) respectively, P is the total power dissipation of the device. JA is commonly used with natural and forced convection air-cooled systems. JC is useful when the package has a high conductivity case mounted directly to a PCB or heatsink. And JB applies when the board temp adjacent to the package is known. The Power Calculator utilizes the Ambient Temperature (C) to calculate the Junction Temperature (C) based on the JA for the targeted device, per Equation 1 above. Users can also provide the Airflow values (in LFM) to get a more accurate value of the Junction temperature. Managing Power Consumption One of the most critical design factors today is the reduction of system power consumption, especially for modern handheld devices and electronics. There are several design techniques that can significantly reduce overall system power consumption. Some of these include: 1. Reducing operating voltage. 2. Operating within the specified package temperature limitations. 3. Using the optimum clock frequency to reduce power consumption, since dynamic power is directly proportional to the frequency of operation. Designers must determine if a portion of their design can be clocked at a lower rate that will reduce power. 4. Reducing the span of the design across 5. Reducing the voltage swing of the I/Os where possible. 6. Using optimum encoding where possible. For example, a 16-bit binary counter has, on average, only 12% Activity Factor and a 7-bit binary counter has an average of 28% Activity Factor. On the other hand, a 7-bit Linear Feedback Shift Register could toggle as much as 50% Activity Factor, which causes higher power consumption. A gray code counter, where only one bit changes at each clock edge, will use the least amount of power, as the Activity Factor would be less than 10%. 7. Minimize the operating temperature, by the following methods: a. Use packages that can better dissipate heat. For example, packages with lower thermal impedance. b. Place heat sinks and thermal planes around the device on the PCB. c. Better airflow techniques using mechanical airflow guides and fans (both system fans and device mounted fans). 12-14 Power Estimation and Management for LatticeXP2 Devices Lattice Semiconductor Power Calculator Assumptions The following are the assumptions made by the Power Calculator: 1. The Power Calculator tool is based on equations with constants based on a room temperature of 25C. 2. The user can define the Ambient Temperature (TA) for device Junction Temperature (TJ) calculation based on the power estimation. TJ is calculated from user-entered TA and power calculation of typical room temperature. 3. I/O power consumption is based on output loading of 5pF. Users can change this capacitive loading. 4. The Power Calculator provides an estimate of the power dissipation and current for each of the following types of power supplies: VCC, VCCIO, VCCJ and VCCAUX. 5. The nominal VCC is used by default to calculate power consumption. A lower or higher VCC can be chosen from a list of available values. 6. Airflow in Linear Feet per Minute (LFM) can be entered by the user along with the Heat Sink option to calculate the Junction Temperature. 7. The default value of the I/O types is LVCMOS12, 6mA. 8. The Activity Factor (AF) is defined as the toggle rate of the registered output. For example, assuming that the input of a flip-flop is changing at every clock cycle, 100% AF of a flip-flop running at 100MHz is 50MHz. Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com Revision History Date Version February 2007 01.0 Change Summary Initial release. 12-15 LatticeXP2 sysDSP Usage Guide February 2007 Technical Note TN1140 Introduction This technical note discusses how to access the features of the LatticeXP2TM sysDSPTM (Digital Signal Processing) Block described in the LatticeXP2 Family Data Sheet. Designs targeting the sysDSP Block can offer significant improvement over traditional LUT-based implementations. Table 13-1 provides an example of the performance and area benefits of this approach: Table 13-1. sysDSP Block vs. LUT-based Multipliers XP2-17-7 Uses One sysDSP Block XP2-17-7 Uses LUTs Multiplier Width Register Pipelining fMAX (MHz)1 LUTs fMAX (MHz)1 LUTs 9x9 Input, Multiplier, Output 365 0 103 192 18x18 Input, Multiplier, Output 365 0 76 698 36x36 Input, Multiplier, Output 323 0 50 2732 (R) 1. These timing numbers were generated using the ispLEVER design tool. Exact performance may vary with design and tool version. sysDSP Block Hardware The LatticeXP2 sysDSP Blocks are located in rows throughout device. Below is a block diagram of one of the sysDSP Blocks: OutB3(18) OutA3(18) OutB2(18) OutA2(18) OutB1(18) OutA1(18) Output Registers OutB0(18) OutA0(18) Figure 13-1. LatticeXP2 sysDSP Block Accumulator (52) 1 Accumulator (52) 3 Add/Sub (36) (9x9 2x18) 1 Add/Sub (36) (9x9 2x18) 3 PR0 (36) 9x9 9x9 Mult18-0 PR1 (36) 9x9 9x9 Mult18-1 PR2 (36) 9x9 9x9 Mult18-2 9x9 9x9 Mult18-3 36x36 (Mult36) Input Registers from SRO of left-side sysDSP Block (or tied to zero if none) In Reg A0 In Reg A1 In Reg A2 In Reg A3 36 36 In Reg B0 In Reg B1 In Reg B2 Adder, Subtractor and Accumulator Functions PR3 (36) One of these Intermediate Pipeline Registers One of these Summation (38) (Two 20 Bits in 9x9 Mode) In Reg B3 36x36, 18x18 and 9x9 Multiplier Functions Output Registers to SRI of right-side sysDSP Block (if it exists) and/or General Logic* *Can only be routed to general logic routing when configured with less than three MULT18X18. Note: Each sysDSP Block spans nine columns of PFUs. (c) 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 13-1 tn1140_01.0 Lattice Semiconductor Lattice XP2 sysDSP Usage Guide The sysDSP Block can be configured as: * One 36x36 Multiplier - Basic multiplier, no add/sub/accum/sum blocks * Four 18x18 Multipliers - Two add/sub/accum blocks - One summation block for adding four multipliers * Eight 9x9 Multipliers - Four add/sub blocks - Two summation blocks Note that a sysDSP block can only be configured in one mode at a time. sysDSP Block Software Overview The sysDSP Block of the LatticeXP2 device can be targeted in a number of ways. * The IPexpressTM tool in the ispLEVER software allows the rapid creation of modules implementing sysDSP elements. These modules can then be used in HDL designs as appropriate. * The coding of certain functions into a design's HDL and allowing the synthesis tools to Inference the use of a sysDSP block. * The implementation of designs in The MathWorks(R) Simulink(R) tool using a Lattice block set. The ispLEVER sysDSP portion of the ispLEVER design tools will then convert these blocks into HDL as appropriate. * Instantiation of sysDSP primitives directly in the source code Targeting sysDSP Block Using IPexpress IPexpress allows you to graphically specify sysDSP elements. Once the element is specified, a HDL file is generated, which can be instantiated in a design. IPexpress allows users to configure all ports and set all available parameters. The following modules target the sysDSP Block. For design examples using IPexpress, refer to EXAMPLES in the ispLEVER Software (from the Project Navigator pull down-menu, go to File and open Example). The following four types of elements can be specified via IPexpress: * MULT (Multiplier) * MAC (Multiplier Accumulate) * MULTADDSUB (Multiplier Add/Subtract) * MULTADDSUBSUM (Multiply Add/Subtract and SUM) MULT Module The MULT Module configures elements to be packed into the sysDSP primitives. The Basic mode screen illustrated in Figure 13-2 consists of an optional one clock, one clock enable and one reset tied to all registers. Multiple sysDSP Blocks can be spanned to accommodate large multiplications. Additional LUTs may be required if multiple sysDSP blocks are needed. Select Area/Speed to determine the LUT implementation. The input data format can be selected as Parallel, Shift or Dynamic. The Shift format can only be enabled if inputs are less than 18 bits. The Shift format enables a sample/shift register, which is useful in applications such as the FIR filter. The Advanced mode screen, illustrated in Figure 13-3, allows finer control over the register. In the Advanced mode, users can control each register with independent clocks, clock enables and resets. MULT inputs can be from 2 to 72 bits. 13-2 Lattice Semiconductor Lattice XP2 sysDSP Usage Guide Figure 13-2. MULT Mode Basic Set-up Figure 13-3. MULT Mode Advanced Set-up 13-3 Lattice Semiconductor Lattice XP2 sysDSP Usage Guide MAC Module The MAC Module configures multiply accumulate elements to be packed into the primitive MULT18X18MACB. The Basic mode, shown in Figure 13-4, consists of an optional one clock, one clock enable and one reset tied to all registers. Because of the accumulator, the output register is automatically enabled. Multiple sysDSP Blocks can be spanned to accommodate large multiplications. The accumulator of the sysDSP block is 52 bits deep and additional LUTs can be used if a larger accumulation is required. If sysDSP blocks are spanned, additional LUT logic may be required. Select Area/Speed to determine the LUT implementation. The input data format can be selected as Parallel, Shift or Dynamic. The Shift format can only be enabled if inputs are less than 18 bits. The Shift format enables a sample/shift register. The Accumsload loads the accumulator with the value from the LD port. This is required to initialize and load the first value of the accumulation. The Advanced mode, shown in Figure 13-5, allows finer control over the registers. In the advanced mode, users can control each register with independent clocks, clock enables and resets. MAC inputs can be from 2 to 72 bits. Figure 13-4. MAC Mode Basic Set-up 13-4 Lattice Semiconductor Lattice XP2 sysDSP Usage Guide Figure 13-5. MAC Mode Advanced Set-up MULTADDSUB Module The MULTADDSUB GUI configures multiplier addition/subtraction elements to be packed into the primitives MULT18X18ADDSUBB or MULT9X9ADDSUBB. The Basic mode, shown in Figure 13-6, consists of an optional one clock, one clock enable and one reset tied to all registers. Multiple sysDSP Blocks can be spanned to accommodate large multiplications. If sysDSP blocks are spanned, additional LUT logic may be required. Select Area/Speed to determine the LUT implementation. The input data format can be selected as Parallel, Shift or Dynamic. The Shift format can only be enabled if inputs are less than 18 bits. The Shift format enables a sample/shift register, which is useful in applications such as the FIR filter. The Advanced mode, shown in Figure 13-7, provides finer control over the registers. In the advanced mode, users can control each register with independent clocks, clock enables and resets. MULTADDSUB inputs can be from 2 to 72 bits. 13-5 Lattice Semiconductor Lattice XP2 sysDSP Usage Guide Figure 13-6. MULTADDSUB Mode Basic Set-up Figure 13-7. MULTADDSUB Mode Advanced Set-up 13-6 Lattice Semiconductor Lattice XP2 sysDSP Usage Guide MULTADDSUBSUM Module The MULTADDSUBSUM GUI configures Multiplier Addition/Subtraction Addition elements to be packed into the primitives MULT18X18ADDSUBSUMB or MULT9X9ADDSUBSUMB. The Basic mode, shown in Figure 13-8, consists of an optional one clock, one clock enable and one reset tied to all registers. Multiple sysDSP Blocks can be spanned to accommodate large multiplications. If sysDSP blocks are spanned, additional LUT logic may be required. Select Area/Speed to determine the LUT implementation. The input data format can be selected as Parallel, Shift or Dynamic. The Shift format is can only be enabled if inputs are less than 18 bits. The Shift format enables a sample/shift register, which is useful in applications such as the FIR filter. The Advanced mode, shown in Figure 13-9, provides finer control over the registers. In the advanced mode, users can control each register with independent clocks, clock enables and resets. MULTADDSUBSUM inputs can be from 2 to 72 bits. Figure 13-8. MULTADDSUBSUM Mode Basic Set-up 13-7 Lattice Semiconductor Lattice XP2 sysDSP Usage Guide Figure 13-9. MULTADDSUBSUM Mode Advance Figure 13-10. MULTADDSUBSUM Mode Advance 13-8 Lattice Semiconductor Lattice XP2 sysDSP Usage Guide Targeting the sysDSP Block by Inference The Inferencing flow enables the design tools to infer sysDSP Blocks from a HDL design. It is important to note that when using the Inferencing flow, unless the code style matches the sysDSP Block, results will not be optimal. Consider the following Verilog and VHDL examples: // This Verilog example will be mapped into single MULT18X18MACB with the output register enabled module mult_acc (dataout, dataax, dataay, clk); output [16:0] dataout; input [7:0] dataax, dataay; input clk; reg [16:0] dataout; wire [15:0] multa = dataax * dataay; // 9x9 Multiplier wire [16:0] adder_out; assign adder_out = multa + dataout; // Accumulator always @(posedge clk) begin dataout <= adder_out; // Output Register of the Accumulator end endmodule -- This VHDL example will be mapped into single MULT18X18MACB with all the registers enabled library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mac is port (clk, reset : in std_logic; dataax, dataay : in std_logic_vector(8 downto 0); dataout : out std_logic_vector(17 downto 0)); end; architecture arch of mac is signal dataax_reg, dataay_reg : std_logic_vector(8 downto 0); signal multout, multout_reg : std_logic_vector(17 downto 0); signal addout : std_logic_vector(17 downto 0); signal dataout_reg : std_logic_vector(17 downto 0); begin dataout <= dataout_reg; process (clk, reset) begin if (reset = `1') then dataax_reg <= (others => `0'); dataay_reg <= (others => `0'); elsif (clk'event and clk='1') then dataax_reg <= dataax; dataay_reg <= dataay; end if; end process; multout <= dataax_reg * dataay_reg; process (clk, reset) begin if (reset = `1') then multout_reg <= (others => `0'); elsif (clk'event and clk='1') then multout_reg <= multout; end if; 13-9 Lattice Semiconductor Lattice XP2 sysDSP Usage Guide end process; addout <= multout_reg + dataout_reg; process (clk, reset) begin if (reset = `1') then dataout_reg <= (others => `0'); elsif (clk'event and clk='1') then dataout_reg <= addout; end if; end process; end arch; The above RTL will infer the following block diagram: Figure 13-11. MULT18X18MACB Block Diagram Multiplier Accumulator This block diagram can be mapped directly into the sysDSP primitives. Note that if a test point were added between the multiplier and the accumulator, or two output registers, etc. the code could not be mapped into a MULT18X18MACB of a sysDSP Block. Therefore, options that could be included in a design are input registers, pipeline registers, etc. For more Inferring design examples refer to EXAMPLES in the ispLEVER software. 13-10 Lattice Semiconductor Lattice XP2 sysDSP Usage Guide Figure 13-12. MAC18X18MACB Packed into a sysDSP Block SOURCEA[3,1]* SOURCEB[3,1]* ADDNSUB[3,1]* ACCUMSLOAD[3,1]* SIGNEDA[3,1]* SIGNEDB[3,1]* 18x18 - 3 +/- 52-bit Accum 1 +/- 52-bit Accum 3 Pipe 1 Pipe 2 In Reg B 0 In Reg B1 Pipe 3 MUI18A3[8:0] MUI18B3[8:0] In Reg B 3 18x18 - 2 In Reg A 3 SLOAD DATA3[15:0]* MUI18A2[17:0] MUI18B2[17:0] 18x18 - 1 In Reg B 2 In Reg A 0 MUI18A1[17:0] MUI18B1[17:0] 18x18 - 0 In Reg A1 MUI18A0[17:0] MUI18B0[17:0] In Reg A 2 SLOAD DATA1[15:0]* Pipe 0 CLK[3:0]** CE[3:0]* RST[3:0]* SRIA[17:0]* SRIB[17:0]* Out Reg 0 Out Reg 1 Out Reg 2 OVERFLOW1 ACCUM1[51:0] OVERFLOW3 ACCUM3[51:0] Out Reg 3 unused SROA[17:0]* SROB[17:0]* Notes: *These signals are optional. **At least one clock is required. sysDSP Blocks in the Report File To check the configuration of the sysDSP Blocks in your design you can look at the MAP and Post PAR report files. The MAP report file shows the mapped sysDSP components/primitives in your design. The Post PAR report file shows the number of components in each sysDSP Block. The report files that follow show how the inferred MAC was used. MAP Report File . MULT18X18MACB addout_17_0: Multiplier Operation Unsigned Operation Registers CLK CE RST -------------------------------------------Input Pipeline Operation Registers CLK CE RST -------------------------------------------Input Pipeline 13-11 Lattice Semiconductor Lattice XP2 sysDSP Usage Guide AddSub Operation Add Operation Registers CLK CE RST -------------------------------------------Input Pipeline Data Input Registers CLK CE RST --------------------------------------------A CLK0 CE0 RST0 B CLK0 CE0 RST0 Pipeline Registers CLK CE RST -------------------------------------------Pipe CLK0 CE0 RST0 Output Register CLK CE RST -------------------------------------------Output CLK0 CE0 RST0 Other GSR ENABLED Number Of Mapped DSP Components: -------------------------------MULT36X36B 0 MULT18X18B 0 MULT18X18MACB 1 MULT18X18ADDSUBB 0 MULT18X18ADDSUBSUMB 0 MULT9X9B 0 MULT9X9ADDSUBB 0 MULT9X9ADDSUBSUMB 0 -------------------------------- Post PAR Report File DSP Utilization Summary: DSP Block #: 1 2 3 4 # of MULT36X36B # of MULT18X18B # of MULT18X18MACB # of MULT18X18ADDSUBB # of MULT18X18ADDSUBSUMB # of MULT9X9B # of MULT9X9ADDSUBB # of MULT9X9ADDSUBSUMB DSP Block 1 Component_Type DSP Block 2 Component_Type DSP Block 3 Component_Type DSP Block 4 Component_Type DSP Block 5 Component_Type DSP Block 6 Component_Type DSP Block 7 Component_Type DSP Block 8 Component_Type DSP Block 9 Component_Type R45C81 MULT18X18MACB DSP Block 10 Component_Type DSP Block 11 Component_Type DSP Block 12 Component_Type DSP Block 13 Component_Type DSP Block 14 Component_Type DSP Block 15 Component_Type DSP Block 16 Component_Type DSP Block 17 Component_Type DSP Block 18 Component_Type 5 6 7 8 9 10 11 1 Instance_Name Instance_Name Instance_Name Instance_Name Instance_Name Instance_Name Instance_Name Instance_Name Instance_Name addout_17_0 Instance_Name Instance_Name Instance_Name Instance_Name Instance_Name Instance_Name Instance_Name Instance_Name Instance_Name 13-12 12 13 14 15 16 17 18 Lattice Semiconductor Lattice XP2 sysDSP Usage Guide Targeting the sysDSP Block Using Simulink Simulink Overview Simulink is a graphical add-on (similar to schematic entry) for Matlab(R), which is produced by The MathWorks. For more information, refer to the Simulink web page at www.mathworks.com/products/simulink/. Why is Simulink used? * It allows users to create algorithms using floating point numbers. * It helps users convert floating point algorithms into fixed point algorithms. How does Simulink fit into the normal ispLEVER design flow? * Once you have converted have your algorithm working in fixed point. You can use the Lattice ispDSP Block to create HDL files, which can be instantiated in your HDL design. Currently there is only support for VHDL. What does Lattice provide? * Lattice provides a library of blocks for the Simulink tool, which include Multipliers, Adders, Registers, and other standard building blocks. Besides the basic building blocks there are a couple of unique Lattice blocks: Gateways In and Out Everything between Gateways In and Out represents the HDL code. Everything before a Gateway In is the stimulus your test bench. Everything after the Gateway Out are the signals you will be monitoring in the test bench. Below is an example. The box on the left contains Gateways In's and the three boxes on the right contain Gateway Outs in Figure 13-13. Generate The Generate block is used to convert Fixed point Simulink design into HDL files which can be instantiated in a HDL design. The Generate Block is identified by the Lattice logo and can be seen in Figure 13-13. 13-13 Lattice Semiconductor Lattice XP2 sysDSP Usage Guide Figure 13-13. Simulink Design Targeting the sysDSP Block by Instantiating Primitives The sysDSP Block can be targeted by instantiating the sysDSP Block primitives into the design. The advantage of instantiating primitives is that it provides access to all ports and sets all available parameters. The disadvantage of this flow is that all this customization requires extra coding by the user. Appendix A details the syntax for the sysDSP Block primitives. sysDSP Block Control Signal and Data Signal Descriptions RST SIGNEDA SIGNEDB ACCUMSLOAD ADDNSUB SOURCEA SOURCEB Asynchronous reset of selected registers Dynamic signal: 0 = unsigned, 1 = signed Dynamic signal: 0 = unsigned, 1 = signed Dynamic signal: 0 = accumulate, 1 = load Dynamic signal: 0 = subtract, 1 = add Dynamic signal: 0 = parallel input, 1 = shift input Dynamic signal: 0 = parallel input, 1 = shift input Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com 13-14 Lattice Semiconductor Lattice XP2 sysDSP Usage Guide Revision History Date Version February 2007 01.0 Change Summary Initial release. 13-15 Lattice Semiconductor Lattice XP2 sysDSP Usage Guide Appendix A. DSP Block Primitives MULT18X18B input A17,A16,A15,A14,A13,A12,A11,A10,A9,A8,A7,A6,A5,A4,A3,A2,A1,A0; input B17,B16,B15,B14,B13,B12,B11,B10,B9,B8,B7,B6,B5,B4,B3,B2,B1,B0; input SIGNEDA, SIGNEDB, SOURCEA, SOURCEB; input CE0,CE1,CE2,CE3,CLK0,CLK1,CLK2,CLK3,RST0,RST1,RST2,RST3; input SRIA17,SRIA16,SRIA15,SRIA14,SRIA13,SRIA12,SRIA11,SRIA10,SRIA9; input SRIA8,SRIA7,SRIA6,SRIA5,SRIA4,SRIA3,SRIA2,SRIA1,SRIA0; input SRIB17,SRIB16,SRIB15,SRIB14,SRIB13,SRIB12,SRIB11,SRIB10,SRIB9; input SRIB8,SRIB7,SRIB6,SRIB5,SRIB4,SRIB3,SRIB2,SRIB1,SRIB0; output SROA17,SROA16,SROA15,SROA14,SROA13,SROA12,SROA11,SROA10,SROA9; output SROA8,SROA7,SROA6,SROA5,SROA4,SROA3,SROA2,SROA1,SROA0; output SROB17,SROB16,SROB15,SROB14,SROB13,SROB12,SROB11,SROB10,SROB9; output SROB8,SROB7,SROB6,SROB5,SROB4,SROB3,SROB2,SROB1,SROB0; output P35,P34,P33,P32,P31,P30,P29,P28,P27,P26,P25,P24,P23,P22,P21,P20,P19,P18; output P17,P16,P15,P14,P13,P12,P11,P10,P9,P8,P7,P6,P5,P4,P3,P2,P1,P0; parameter REG_INPUTA_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_INPUTA_CE = " CE0, CE1, CE2, CE3 "; parameter REG_INPUTA_RST = " RST0, RST1, RST2, RST3 "; parameter REG_INPUTB_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_INPUTB_CE = = " CE0, CE1, CE2, CE3 "; parameter REG_INPUTB_RST = " RST0, RST1, RST2, RST3 "; parameter REG_PIPELINE_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_PIPELINE_CE = " CE0, CE1, CE2, CE3 "; parameter REG_PIPELINE_RST = " RST0, RST1, RST2, RST3 "; parameter REG_OUTPUT_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_OUTPUT_CE = " CE0, CE1, CE2, CE3 "; parameter REG_OUTPUT_RST = " RST0, RST1, RST2, RST3 "; parameter REG_SIGNEDA_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_SIGNEDA_CE = " CE0, CE1, CE2, CE3 "; parameter REG_SIGNEDA_RST = " RST0, RST1, RST2, RST3 "; parameter REG_SIGNEDB_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_SIGNEDB_CE = " CE0, CE1, CE2, CE3 "; parameter REG_SIGNEDB_RST = " RST0, RST1, RST2, RST3 "; parameter GSR = " Enabled, Disabled "; MULT18X18ADDSUBB input A017,A016,A015,A014,A013,A012,A011,A010,A09; input A08,A07,A06,A05,A04,A03,A02,A01,A00; input A117,A116,A115,A114,A113,A112,A111,A110,A19; input A18,A17,A16,A15,A14,A13,A12,A11,A10; input B017,B016,B015,B014,B013,B012,B011,B010,B09; input B08,B07,B06,B05,B04,B03,B02,B01,B00; input B117,B116,B115,B114,B113,B112,B111,B110,B19; input B18,B17,B16,B15,B14,B13,B12,B11,B10; input SIGNEDA, SIGNEDB, SOURCEA0, SOURCEA1, SOURCEB0, SOURCEB1, ADDNSUB; input CE0,CE1,CE2,CE3,CLK0,CLK1,CLK2,CLK3,RST0,RST1,RST2,RST3; input SRIA17,SRIA16,SRIA15,SRIA14,SRIA13,SRIA12,SRIA11,SRIA10,SRIA9; input SRIA8,SRIA7,SRIA6,SRIA5,SRIA4,SRIA3,SRIA2,SRIA1,SRIA0; input SRIB17,SRIB16,SRIB15,SRIB14,SRIB13,SRIB12,SRIB11,SRIB10,SRIB9; input SRIB8,SRIB7,SRIB6,SRIB5,SRIB4,SRIB3,SRIB2,SRIB1,SRIB0; output SROA17,SROA16,SROA15,SROA14,SROA13,SROA12,SROA11,SROA10,SROA9; output SROA8,SROA7,SROA6,SROA5,SROA4,SROA3,SROA2,SROA1,SROA0; output SROB17,SROB16,SROB15,SROB14,SROB13,SROB12,SROB11,SROB10,SROB9; output SROB8,SROB7,SROB6,SROB5,SROB4,SROB3,SROB2,SROB1,SROB0; output SUM36,SUM35,SUM34,SUM33,SUM32,SUM31,SUM30,SUM29,SUM28,SUM27,SUM26,SUM25,SUM24,SUM23,SUM22,SUM21,SU M20,SUM19,SUM18,SUM17,SUM16,SUM15,SUM14,SUM13,SUM12,SUM11,SUM10,SUM9,SUM8,SUM7,SUM6,SUM5,SUM4,SUM3 ,SUM2,SUM1,SUM0; 13-16 Lattice Semiconductor parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter Lattice XP2 sysDSP Usage Guide REG_INPUTA0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_INPUTA0_CE = " CE0, CE1, CE2, CE3 "; REG_INPUTA0_RST = " RST0, RST1, RST2, RST3 "; REG_INPUTA1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_INPUTA1_CE = " CE0, CE1, CE2, CE3 "; REG_INPUTA1_RST = " RST0, RST1, RST2, RST3 "; REG_INPUTB0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_INPUTB0_CE = " CE0, CE1, CE2, CE3 "; REG_INPUTB0_RST = " RST0, RST1, RST2, RST3 "; REG_INPUTB1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_INPUTB1_CE = " CE0, CE1, CE2, CE3 "; REG_INPUTB1_RST = " RST0, RST1, RST2, RST3 "; REG_PIPELINE0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_PIPELINE0_CE = " CE0, CE1, CE2, CE3 "; REG_PIPELINE0_RST = " RST0, RST1, RST2, RST3 "; REG_PIPELINE1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_PIPELINE1_CE = " CE0, CE1, CE2, CE3 "; REG_PIPELINE1_RST = " RST0, RST1, RST2, RST3 "; REG_OUTPUT_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_OUTPUT_CE = " CE0, CE1, CE2, CE3 "; REG_OUTPUT_RST = " RST0, RST1, RST2, RST3 "; REG_SIGNEDA_0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_SIGNEDA_0_CE = " CE0, CE1, CE2, CE3 "; REG_SIGNEDA_0_RST = " RST0, RST1, RST2, RST3 "; REG_SIGNEDA_1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_SIGNEDA_1_CE = " CE0, CE1, CE2, CE3 "; REG_SIGNEDA_1_RST = " RST0, RST1, RST2, RST3 "; REG_SIGNEDB_0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_SIGNEDB_0_CE = " CE0, CE1, CE2, CE3 "; REG_SIGNEDB_0_RST = " RST0, RST1, RST2, RST3 "; REG_SIGNEDB_1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_SIGNEDB_1_CE = " CE0, CE1, CE2, CE3 "; REG_SIGNEDB_1_RST = " RST0, RST1, RST2, RST3 "; REG_ADDNSUB_0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_ADDNSUB_0_CE = " CE0, CE1, CE2, CE3 "; REG_ADDNSUB_0_RST = " RST0, RST1, RST2, RST3 "; REG_ADDNSUB_1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_ADDNSUB_1_CE = " CE0, CE1, CE2, CE3 "; REG_ADDNSUB_1_RST = " RST0, RST1, RST2, RST3 "; GSR = " Enabled, Disabled "; MULT18X18ADDSUBSUMB input input input input input input input input input input input input input input input input input input input A017,A016,A015,A014,A013,A012,A011,A010,A09; A08,A07,A06,A05,A04,A03,A02,A01,A00; A117,A116,A115,A114,A113,A112,A111,A110,A19; A18,A17,A16,A15,A14,A13,A12,A11,A10; A217,A216,A215,A214,A213,A212,A211,A210,A29; A28,A27,A26,A25,A24,A23,A22,A21,A20; A317,A316,A315,A314,A313,A312,A311,A310,A39; A38,A37,A36,A35,A34,A33,A32,A31,A30; B017,B016,B015,B014,B013,B012,B011,B010,B09; B08,B07,B06,B05,B04,B03,B02,B01,B00; B117,B116,B115,B114,B113,B112,B111,B110,B19; B18,B17,B16,B15,B14,B13,B12,B11,B10; B217,B216,B215,B214,B213,B212,B211,B210,B29; B28,B27,B26,B25,B24,B23,B22,B21,B20; B317,B316,B315,B314,B313,B312,B311,B310,B39; B38,B37,B36,B35,B34,B33,B32,B31,B30; SIGNEDA, SIGNEDB,ADDNSUB1,ADDNSUB3; SOURCEA0, SOURCEA1, SOURCEA2, SOURCEA3; SOURCEB0, SOURCEB1, SOURCEB2, SOURCEB3; 13-17 Lattice Semiconductor Lattice XP2 sysDSP Usage Guide input CE0,CE1,CE2,CE3,CLK0,CLK1,CLK2,CLK3,RST0,RST1,RST2,RST3; input SRIA17,SRIA16,SRIA15,SRIA14,SRIA13,SRIA12,SRIA11,SRIA10,SRIA9; input SRIA8,SRIA7,SRIA6,SRIA5,SRIA4,SRIA3,SRIA2,SRIA1,SRIA0; input SRIB17,SRIB16,SRIB15,SRIB14,SRIB13,SRIB12,SRIB11,SRIB10,SRIB9; input SRIB8,SRIB7,SRIB6,SRIB5,SRIB4,SRIB3,SRIB2,SRIB1,SRIB0; output SROA17,SROA16,SROA15,SROA14,SROA13,SROA12,SROA11,SROA10,SROA9; output SROA8,SROA7,SROA6,SROA5,SROA4,SROA3,SROA2,SROA1,SROA0; output SROB17,SROB16,SROB15,SROB14,SROB13,SROB12,SROB11,SROB10,SROB9; output SROB8,SROB7,SROB6,SROB5,SROB4,SROB3,SROB2,SROB1,SROB0; output SUM37,SUM36,SUM35,SUM34,SUM33,SUM32,SUM31,SUM30,SUM29,SUM28,SUM27,SUM26,SUM25,SUM24,SUM23,SUM22,SU M21,SUM20,SUM19,SUM18,SUM17,SUM16,SUM15,SUM14,SUM13,SUM12,SUM11,SUM10,SUM9,SUM8,SUM7,SUM6,SUM5,SUM 4,SUM3,SUM2,SUM1,SUM0; parameter REG_INPUTA0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_INPUTA0_CE = " CE0, CE1, CE2, CE3 "; parameter REG_INPUTA0_RST = " RST0, RST1, RST2, RST3 "; parameter REG_INPUTA1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_INPUTA1_CE = " CE0, CE1, CE2, CE3 "; parameter REG_INPUTA1_RST = " RST0, RST1, RST2, RST3 "; parameter REG_INPUTA2_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_INPUTA2_CE = " CE0, CE1, CE2, CE3 "; parameter REG_INPUTA2_RST = " RST0, RST1, RST2, RST3 "; parameter REG_INPUTA3_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_INPUTA3_CE = " CE0, CE1, CE2, CE3 "; parameter REG_INPUTA3_RST = " RST0, RST1, RST2, RST3 "; parameter REG_INPUTB0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_INPUTB0_CE = " CE0, CE1, CE2, CE3 "; parameter REG_INPUTB0_RST = " RST0, RST1, RST2, RST3 "; parameter REG_INPUTB1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_INPUTB1_CE = " CE0, CE1, CE2, CE3 "; parameter REG_INPUTB1_RST = " RST0, RST1, RST2, RST3 "; parameter REG_INPUTB2_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_INPUTB2_CE = " CE0, CE1, CE2, CE3 "; parameter REG_INPUTB2_RST = " RST0, RST1, RST2, RST3 "; parameter REG_INPUTB3_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_INPUTB3_CE = " CE0, CE1, CE2, CE3 "; parameter REG_INPUTB3_RST = " RST0, RST1, RST2, RST3 "; parameter REG_PIPELINE0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_PIPELINE0_CE = " CE0, CE1, CE2, CE3 "; parameter REG_PIPELINE0_RST = " RST0, RST1, RST2, RST3 "; parameter REG_PIPELINE1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_PIPELINE1_CE = " CE0, CE1, CE2, CE3 "; parameter REG_PIPELINE1_RST = " RST0, RST1, RST2, RST3 "; parameter REG_PIPELINE2_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_PIPELINE2_CE = " CE0, CE1, CE2, CE3 "; parameter REG_PIPELINE2_RST = " RST0, RST1, RST2, RST3 "; parameter REG_PIPELINE3_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_PIPELINE3_CE = " CE0, CE1, CE2, CE3 "; parameter REG_PIPELINE3_RST = " RST0, RST1, RST2, RST3 "; parameter REG_OUTPUT_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_OUTPUT_CE = " CE0, CE1, CE2, CE3 "; parameter REG_OUTPUT_RST = " RST0, RST1, RST2, RST3 "; parameter REG_SIGNEDA_0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_SIGNEDA_0_CE = " CE0, CE1, CE2, CE3 "; parameter REG_SIGNEDA_0_RST = " RST0, RST1, RST2, RST3 "; parameter REG_SIGNEDA_1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_SIGNEDA_1_CE = " CE0, CE1, CE2, CE3 "; parameter REG_SIGNEDA_1_RST = " RST0, RST1, RST2, RST3 "; parameter REG_SIGNEDB_0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_SIGNEDB_0_CE = " CE0, CE1, CE2, CE3 "; parameter REG_SIGNEDB_0_RST = " RST0, RST1, RST2, RST3 "; 13-18 Lattice Semiconductor parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter Lattice XP2 sysDSP Usage Guide REG_SIGNEDB_1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_SIGNEDB_1_CE = " CE0, CE1, CE2, CE3 "; REG_SIGNEDB_1_RST = " RST0, RST1, RST2, RST3 "; REG_ADDNSUB1_0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_ADDNSUB1_0_CE = " CE0, CE1, CE2, CE3 "; REG_ADDNSUB1_0_RST = " RST0, RST1, RST2, RST3 "; REG_ADDNSUB1_1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_ADDNSUB1_1_CE = " CE0, CE1, CE2, CE3 "; REG_ADDNSUB1_1_RST = " RST0, RST1, RST2, RST3 "; REG_ADDNSUB3_0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_ADDNSUB3_0_CE = " CE0, CE1, CE2, CE3 "; REG_ADDNSUB3_0_RST = " RST0, RST1, RST2, RST3 "; REG_ADDNSUB3_1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_ADDNSUB3_1_CE = " CE0, CE1, CE2, CE3 "; REG_ADDNSUB3_1_RST = " RST0, RST1, RST2, RST3 "; GSR = " Enabled, Disabled "; MULT18X18MACB input A17,A16,A15,A14,A13,A12,A11,A10,A9; input A8,A7,A6,A5,A4,A3,A2,A1,A0; input B17,B16,B15,B14,B13,B12,B11,B10,B9; input B8,B7,B6,B5,B4,B3,B2,B1,B0; input ADDNSUB, SIGNEDA, SIGNEDB,ACCUMSLOAD; input SOURCEA, SOURCEB; input CE0,CE1,CE2,CE3,CLK0,CLK1,CLK2,CLK3,RST0,RST1,RST2,RST3; input LD51, LD50, LD49, LD48, LD47, LD46, LD45, LD44, LD43, LD42, LD41, LD40 input LD39, LD38, LD37, LD36, LD35, LD34, LD33, LD32, LD31, LD30 input LD29, LD28, LD27, LD26, LD25, LD24, LD23, LD22, LD21, LD20 input LD19, LD18, LD17, LD16, LD15, LD14, LD13, LD12, LD11, LD10 input LD9, LD8, LD7, LD6, LD5, LD4, LD3, LD2, LD1, LD0; input SRIA17,SRIA16,SRIA15,SRIA14,SRIA13,SRIA12,SRIA11,SRIA10,SRIA9; input SRIA8,SRIA7,SRIA6,SRIA5,SRIA4,SRIA3,SRIA2,SRIA1,SRIA0; input SRIB17,SRIB16,SRIB15,SRIB14,SRIB13,SRIB12,SRIB11,SRIB10,SRIB9; input SRIB8,SRIB7,SRIB6,SRIB5,SRIB4,SRIB3,SRIB2,SRIB1,SRIB0; output SROA17,SROA16,SROA15,SROA14,SROA13,SROA12,SROA11,SROA10,SROA9; output SROA8,SROA7,SROA6,SROA5,SROA4,SROA3,SROA2,SROA1,SROA0; output SROB17,SROB16,SROB15,SROB14,SROB13,SROB12,SROB11,SROB10,SROB9; output SROB8,SROB7,SROB6,SROB5,SROB4,SROB3,SROB2,SROB1,SROB0; output ACCUM51,ACCUM50,ACCUM49,ACCUM48,ACCUM47,ACCUM46,ACCUM45,ACCUM44,ACCUM43,ACCUM42,ACCUM41,ACCUM40,AC CUM39,ACCUM38,ACCUM37,ACCUM36,ACCUM35,ACCUM34,ACCUM33,ACCUM32,ACCUM31,ACCUM30,ACCUM29,ACCUM28,ACCU M27,ACCUM26,ACCUM25,ACCUM24,ACCUM23,ACCUM22,ACCUM21,ACCUM20,ACCUM19,ACCUM18,ACCUM17,ACCUM16,ACCUM1 5,ACCUM14,ACCUM13,ACCUM12,ACCUM11,ACCUM10,ACCUM9,ACCUM8,ACCUM7,ACCUM6,ACCUM5,ACCUM4,ACCUM3,ACCUM2, ACCUM1,ACCUM0,OVERFLOW; parameter REG_INPUTA_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_INPUTA_CE = " CE0, CE1, CE2, CE3 "; parameter REG_INPUTA_RST = " RST0, RST1, RST2, RST3 "; parameter REG_INPUTB_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_INPUTB_CE = " CE0, CE1, CE2, CE3 "; parameter REG_INPUTB_RST = " RST0, RST1, RST2, RST3 "; parameter REG_PIPELINE_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_PIPELINE_CE = " CE0, CE1, CE2, CE3 "; parameter REG_PIPELINE_RST = " RST0, RST1, RST2, RST3 "; parameter REG_OUTPUT_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_OUTPUT_CE = " CE0, CE1, CE2, CE3 "; parameter REG_OUTPUT_RST = " RST0, RST1, RST2, RST3 "; parameter REG_SIGNEDA_0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_SIGNEDA_0_CE = " CE0, CE1, CE2, CE3 "; parameter REG_SIGNEDA_0_RST = " RST0, RST1, RST2, RST3 "; parameter REG_SIGNEDA_1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_SIGNEDA_1_CE = " CE0, CE1, CE2, CE3 "; 13-19 Lattice Semiconductor parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter Lattice XP2 sysDSP Usage Guide REG_SIGNEDA_1_RST = " RST0, RST1, RST2, RST3 "; REG_SIGNEDB_0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_SIGNEDB_0_CE = " CE0, CE1, CE2, CE3 "; REG_SIGNEDB_0_RST = " RST0, RST1, RST2, RST3 "; REG_SIGNEDB_1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_SIGNEDB_1_CE = " CE0, CE1, CE2, CE3 "; REG_SIGNEDB_1_RST = " RST0, RST1, RST2, RST3 "; REG_ACCUMSLOAD_0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_ACCUMSLOAD_0_CE = " CE0, CE1, CE2, CE3 "; REG_ACCUMSLOAD_0_RST = " RST0, RST1, RST2, RST3 "; REG_ACCUMSLOAD_1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_ACCUMSLOAD_1_CE = " CE0, CE1, CE2, CE3 "; REG_ACCUMSLOAD_1_RST = " RST0, RST1, RST2, RST3 "; REG_ADDNSUB_0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_ADDNSUB_0_CE = " CE0, CE1, CE2, CE3 "; REG_ADDNSUB_0_RST = " RST0, RST1, RST2, RST3 "; REG_ADDNSUB_1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_ADDNSUB_1_CE = " CE0, CE1, CE2, CE3 "; REG_ADDNSUB_1_RST = " RST0, RST1, RST2, RST3 "; GSR = " Enabled, Disabled "; MULT36X36B input A35,A34,A33,A32,A31,A30,A29,A28,A27,A26,A25,A24,A23,A22,A21,A20,A19,A18; input A17,A16,A15,A14,A13,A12,A11,A10,A9,A8,A7,A6,A5,A4,A3,A2,A1,A0; input B35,B34,B33,B32,B31,B30,B29,B28,B27,B26,B25,B24,B23,B22,B21,B20,B19,B18; input B17,B16,B15,B14,B13,B12,B11,B10,B9,B8,B7,B6,B5,B4,B3,B2,B1,B0; input SIGNEDA, SIGNEDB; input CE0,CE1,CE2,CE3,CLK0,CLK1,CLK2,CLK3,RST0,RST1,RST2,RST3; output P71,P70,P69,P68,P67,P66,P65,P64,P63,P62,P61,P60,P59,P58,P57,P56,P55,P54; output P53,P52,P51,P50,P49,P48,P47,P46,P45,P44,P43,P42,P41,P40,P39,P38,P37,P36; output P35,P34,P33,P32,P31,P30,P29,P28,P27,P26,P25,P24,P23,P22,P21,P20,P19,P18; output P17,P16,P15,P14,P13,P12,P11,P10,P9,P8,P7,P6,P5,P4,P3,P2,P1,P0; parameter REG_INPUTA_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_INPUTA_CE = " CE0, CE1, CE2, CE3 "; parameter REG_INPUTA_RST = " RST0, RST1, RST2, RST3 "; parameter REG_INPUTB_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_INPUTB_CE = " CE0, CE1, CE2, CE3 "; parameter REG_INPUTB_RST = " RST0, RST1, RST2, RST3 "; parameter REG_PIPELINE_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_PIPELINE_CE = " CE0, CE1, CE2, CE3 "; parameter REG_PIPELINE_RST = " RST0, RST1, RST2, RST3 "; parameter REG_OUTPUT_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_OUTPUT_CE = " CE0, CE1, CE2, CE3 "; parameter REG_OUTPUT_RST = " RST0, RST1, RST2, RST3 "; parameter REG_SIGNEDA_0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_SIGNEDA_0_CE = " CE0, CE1, CE2, CE3 "; parameter REG_SIGNEDA_0_RST = " RST0, RST1, RST2, RST3 "; parameter REG_SIGNEDA_1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_SIGNEDA_1_CE = " CE0, CE1, CE2, CE3 "; parameter REG_SIGNEDA_1_RST = " RST0, RST1, RST2, RST3 "; parameter REG_SIGNEDB_0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_SIGNEDB_0_CE = " CE0, CE1, CE2, CE3 "; parameter REG_SIGNEDB_0_RST = " RST0, RST1, RST2, RST3 "; parameter REG_SIGNEDB_1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_SIGNEDB_1_CE = " CE0, CE1, CE2, CE3 "; parameter REG_SIGNEDB_1_RST = " RST0, RST1, RST2, RST3 "; parameter GSR = " Enabled, Disabled "; 13-20 Lattice Semiconductor Lattice XP2 sysDSP Usage Guide MULT9X9B input A8,A7,A6,A5,A4,A3,A2,A1,A0; input B8,B7,B6,B5,B4,B3,B2,B1,B0; input SIGNEDA, SIGNEDB, SOURCEA, SOURCEB; input CE0,CE1,CE2,CE3,CLK0,CLK1,CLK2,CLK3,RST0,RST1,RST2,RST3; input SRIA8,SRIA7,SRIA6,SRIA5,SRIA4,SRIA3,SRIA2,SRIA1,SRIA0; input SRIB8,SRIB7,SRIB6,SRIB5,SRIB4,SRIB3,SRIB2,SRIB1,SRIB0; output SROA8,SROA7,SROA6,SROA5,SROA4,SROA3,SROA2,SROA1,SROA0; output SROB8,SROB7,SROB6,SROB5,SROB4,SROB3,SROB2,SROB1,SROB0; output P17,P16,P15,P14,P13,P12,P11,P10,P9,P8,P7,P6,P5,P4,P3,P2,P1,P0; parameter REG_INPUTA_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_INPUTA_CE = " CE0, CE1, CE2, CE3 "; parameter REG_INPUTA_RST = " RST0, RST1, RST2, RST3 "; parameter REG_INPUTB_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_INPUTB_CE = " CE0, CE1, CE2, CE3 "; parameter REG_INPUTB_RST = " RST0, RST1, RST2, RST3 "; parameter REG_PIPELINE_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_PIPELINE_CE = " CE0, CE1, CE2, CE3 "; parameter REG_PIPELINE_RST = " RST0, RST1, RST2, RST3 "; parameter REG_OUTPUT_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_OUTPUT_CE = " CE0, CE1, CE2, CE3 "; parameter REG_OUTPUT_RST = " RST0, RST1, RST2, RST3 "; parameter REG_SIGNEDA_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_SIGNEDA_CE = " CE0, CE1, CE2, CE3 "; parameter REG_SIGNEDA_RST = " RST0, RST1, RST2, RST3 "; parameter REG_SIGNEDB_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_SIGNEDB_CE = " CE0, CE1, CE2, CE3 "; parameter REG_SIGNEDB_RST = " RST0, RST1, RST2, RST3 "; parameter GSR = " Enabled, Disabled "; MULT9X9ADDSUBB input A08,A07,A06,A05,A04,A03,A02,A01,A00; input A18,A17,A16,A15,A14,A13,A12,A11,A10; input B08,B07,B06,B05,B04,B03,B02,B01,B00; input B18,B17,B16,B15,B14,B13,B12,B11,B10; input SIGNEDA, SIGNEDB,ADDNSUB; input SOURCEA0, SOURCEA1, SOURCEB0, SOURCEB1; input CE0,CE1,CE2,CE3,CLK0,CLK1,CLK2,CLK3,RST0,RST1,RST2,RST3; input SRIA8,SRIA7,SRIA6,SRIA5,SRIA4,SRIA3,SRIA2,SRIA1,SRIA0; input SRIB8,SRIB7,SRIB6,SRIB5,SRIB4,SRIB3,SRIB2,SRIB1,SRIB0; output SROA8,SROA7,SROA6,SROA5,SROA4,SROA3,SROA2,SROA1,SROA0; output SROB8,SROB7,SROB6,SROB5,SROB4,SROB3,SROB2,SROB1,SROB0; output SUM18,SUM17,SUM16,SUM15,SUM14,SUM13,SUM12,SUM11,SUM10,SUM9,SUM8,SUM7,SUM6,SUM5,SUM4,SUM3,SUM2,SUM1 ,SUM0; parameter REG_INPUTA0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_INPUTA0_CE = " CE0, CE1, CE2, CE3 "; parameter REG_INPUTA0_RST = " RST0, RST1, RST2, RST3 "; parameter REG_INPUTA1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_INPUTA1_CE = " CE0, CE1, CE2, CE3 "; parameter REG_INPUTA1_RST = " RST0, RST1, RST2, RST3 "; parameter REG_INPUTB0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_INPUTB0_CE = " CE0, CE1, CE2, CE3 "; parameter REG_INPUTB0_RST = " RST0, RST1, RST2, RST3 "; parameter REG_INPUTB1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_INPUTB1_CE = " CE0, CE1, CE2, CE3 "; parameter REG_INPUTB1_RST = " RST0, RST1, RST2, RST3 "; parameter REG_PIPELINE0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_PIPELINE0_CE = " CE0, CE1, CE2, CE3 "; parameter REG_PIPELINE0_RST = " RST0, RST1, RST2, RST3 "; 13-21 Lattice Semiconductor parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter Lattice XP2 sysDSP Usage Guide REG_PIPELINE1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 REG_PIPELINE1_CE = " CE0, CE1, CE2, CE3 "; REG_PIPELINE1_RST = " RST0, RST1, RST2, RST3 "; REG_OUTPUT_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_OUTPUT_CE = " CE0, CE1, CE2, CE3 "; REG_OUTPUT_RST = " RST0, RST1, RST2, RST3 "; REG_SIGNEDA_0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 REG_SIGNEDA_0_CE = " CE0, CE1, CE2, CE3 "; REG_SIGNEDA_0_RST = " RST0, RST1, RST2, RST3 "; REG_SIGNEDA_1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 REG_SIGNEDA_1_CE = " CE0, CE1, CE2, CE3 "; REG_SIGNEDA_1_RST = " RST0, RST1, RST2, RST3 "; REG_SIGNEDB_0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 REG_SIGNEDB_0_CE = " CE0, CE1, CE2, CE3 "; REG_SIGNEDB_0_RST = " RST0, RST1, RST2, RST3 "; REG_SIGNEDB_1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 REG_SIGNEDB_1_CE = " CE0, CE1, CE2, CE3 "; REG_SIGNEDB_1_RST = " RST0, RST1, RST2, RST3 "; REG_ADDNSUB_0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 REG_ADDNSUB_0_CE = " CE0, CE1, CE2, CE3 "; REG_ADDNSUB_0_RST = " RST0, RST1, RST2, RST3 "; REG_ADDNSUB_1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 REG_ADDNSUB_1_CE = " CE0, CE1, CE2, CE3 "; REG_ADDNSUB_1_RST = " RST0, RST1, RST2, RST3 "; GSR = " Enabled, Disabled "; "; "; "; "; "; "; "; MULT9X9ADDSUBSUMB input A08,A07,A06,A05,A04,A03,A02,A01,A00; input A18,A17,A16,A15,A14,A13,A12,A11,A10; input A28,A27,A26,A25,A24,A23,A22,A21,A20; input A38,A37,A36,A35,A34,A33,A32,A31,A30; input B08,B07,B06,B05,B04,B03,B02,B01,B00; input B18,B17,B16,B15,B14,B13,B12,B11,B10; input B28,B27,B26,B25,B24,B23,B22,B21,B20; input B38,B37,B36,B35,B34,B33,B32,B31,B30; input SIGNEDA, SIGNEDB,ADDNSUB1,ADDNSUB3; input SOURCEA0, SOURCEA1, SOURCEA2, SOURCEA3; input SOURCEB0, SOURCEB1, SOURCEB2, SOURCEB3; input CE0,CE1,CE2,CE3,CLK0,CLK1,CLK2,CLK3,RST0,RST1,RST2,RST3; input SRIA8,SRIA7,SRIA6,SRIA5,SRIA4,SRIA3,SRIA2,SRIA1,SRIA0; input SRIB8,SRIB7,SRIB6,SRIB5,SRIB4,SRIB3,SRIB2,SRIB1,SRIB0; output SROA8,SROA7,SROA6,SROA5,SROA4,SROA3,SROA2,SROA1,SROA0; output SROB8,SROB7,SROB6,SROB5,SROB4,SROB3,SROB2,SROB1,SROB0; output SUM19,SUM18,SUM17,SUM16,SUM15,SUM14,SUM13,SUM12,SUM11,SUM10,SUM9,SUM8,SUM7,SUM6,SUM5,SUM4,SUM3,SUM 2,SUM1,SUM0; parameter REG_INPUTA0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_INPUTA0_CE = " CE0, CE1, CE2, CE3 "; parameter REG_INPUTA0_RST = " RST0, RST1, RST2, RST3 "; parameter REG_INPUTA1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_INPUTA1_CE = " CE0, CE1, CE2, CE3 "; parameter REG_INPUTA1_RST = " RST0, RST1, RST2, RST3 "; parameter REG_INPUTA2_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_INPUTA2_CE = " CE0, CE1, CE2, CE3 "; parameter REG_INPUTA2_RST = " RST0, RST1, RST2, RST3 "; parameter REG_INPUTA3_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_INPUTA3_CE = " CE0, CE1, CE2, CE3 "; parameter REG_INPUTA3_RST = " RST0, RST1, RST2, RST3 "; parameter REG_INPUTB0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; parameter REG_INPUTB0_CE = " CE0, CE1, CE2, CE3 "; parameter REG_INPUTB0_RST = " RST0, RST1, RST2, RST3 "; 13-22 Lattice Semiconductor parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter Lattice XP2 sysDSP Usage Guide REG_INPUTB1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_INPUTB1_CE = " CE0, CE1, CE2, CE3 "; REG_INPUTB1_RST = " RST0, RST1, RST2, RST3 "; REG_INPUTB2_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_INPUTB2_CE = " CE0, CE1, CE2, CE3 "; REG_INPUTB2_RST = " RST0, RST1, RST2, RST3 "; REG_INPUTB3_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_INPUTB3_CE = " CE0, CE1, CE2, CE3 "; REG_INPUTB3_RST = " RST0, RST1, RST2, RST3 "; REG_PIPELINE0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_PIPELINE0_CE = " CE0, CE1, CE2, CE3 "; REG_PIPELINE0_RST = " RST0, RST1, RST2, RST3 "; REG_PIPELINE1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_PIPELINE1_CE = " CE0, CE1, CE2, CE3 "; REG_PIPELINE1_RST = " RST0, RST1, RST2, RST3 "; REG_PIPELINE2_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_PIPELINE2_CE = " CE0, CE1, CE2, CE3 "; REG_PIPELINE2_RST = " RST0, RST1, RST2, RST3 "; REG_PIPELINE3_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_PIPELINE3_CE = " CE0, CE1, CE2, CE3 "; REG_PIPELINE3_RST = " RST0, RST1, RST2, RST3 "; REG_OUTPUT_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_OUTPUT_CE = " CE0, CE1, CE2, CE3 "; REG_OUTPUT_RST = " RST0, RST1, RST2, RST3 "; REG_SIGNEDA_0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_SIGNEDA_0_CE = " CE0, CE1, CE2, CE3 "; REG_SIGNEDA_0_RST = " RST0, RST1, RST2, RST3 "; REG_SIGNEDA_1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_SIGNEDA_1_CE = " CE0, CE1, CE2, CE3 "; REG_SIGNEDA_1_RST = " RST0, RST1, RST2, RST3 "; REG_SIGNEDB_0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_SIGNEDB_0_CE = " CE0, CE1, CE2, CE3 "; REG_SIGNEDB_0_RST = " RST0, RST1, RST2, RST3 "; REG_SIGNEDB_1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_SIGNEDB_1_CE = " CE0, CE1, CE2, CE3 "; REG_SIGNEDB_1_RST = " RST0, RST1, RST2, RST3 "; REG_ADDNSUB1_0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_ADDNSUB1_0_CE = " CE0, CE1, CE2, CE3 "; REG_ADDNSUB1_0_RST = " RST0, RST1, RST2, RST3 "; REG_ADDNSUB1_1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_ADDNSUB1_1_CE = " CE0, CE1, CE2, CE3 "; REG_ADDNSUB1_1_RST = " RST0, RST1, RST2, RST3 "; REG_ADDNSUB3_0_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_ADDNSUB3_0_CE = " CE0, CE1, CE2, CE3 "; REG_ADDNSUB3_0_RST = " RST0, RST1, RST2, RST3 "; REG_ADDNSUB3_1_CLK = " NONE, CLK0, CLK1, CLK2, CLK3 "; REG_ADDNSUB3_1_CE = " CE0, CE1, CE2, CE3 "; REG_ADDNSUB3_1_RST = " RST0, RST1, RST2, RST3 "; GSR = " Enabled, Disabled "; 13-23 LatticeXP2 sysCONFIG Usage Guide July 2011 Technical Note TN1141 Introduction The memory in the LatticeXP2TM FPGAs is built using Flash cells, along with SRAM cells, so that configuration memory can be loaded automatically at power-up, or at any time the user wishes to update the device. In addition to "instant-on" capability, on-chip Flash memory greatly increases design security by getting rid of the external configuration bitstream; while maintaining the ease of use and reprogrammability of an SRAM-based FPGA. The LatticeXP2 supports the use of an encryption key to protect the contents of the Flash memory for additional security. The LatticeXP2 also supports the use of a One-Time-Programmable (OTP) feature to protect the Flash memory from being erased or re-programmed. While an external device is not required, the LatticeXP2 does support several external configuration modes. The available external configuration modes are: * Slave SPI * Master SPI * ispJTAGTM (1149.1 interface) This guide will cover all the configuration options available for the LatticeXP2. Programming Overview The LatticeXP2 contains two types of memory, SRAM and Flash (refer to Figure 14-1). SRAM contains the FPGA configuration, essentially the "fuses" that define the circuit connections; Flash provides an internal storage space for the configuration data. The LatticeXP2 also contains additional Flash memory area and that is designated for Tag memory and User Flash memory. The Tag memory is a scratch pad memory that is available to the user for storage of mission critical data, board serialization, revision information, programmed pattern identification, or other information. The User Flash memory is available to provide a back up the contents of the EBR RAM modules if the user desires. These functions will be discussed in more detail in later sections of this document. The SRAM can be configured using JTAG, the external Master SPI port, or by using the data stored in on-chip Flash. The configuration process consists of SRAM initialization (clear the RAM and the address pointers), loading the SRAM with the configuration data, and setting the FPGA into user mode (waking up the FPGA). On-chip Flash can be programmed by using JTAG or by using the external Slave SPI port. JTAG Flash programming can be performed any time the device is powered up. The Slave SPl port uses the sysCONFIGTM pins and can program the Flash directly or in the background. Direct programming takes place during config mode, background programming during user mode. The FPGA enters config mode at power up, when the PROGRAMN pin is pulled low, or when a refresh command is issued via JTAG; it enters user mode when it wakes up, i.e. when the device begins running user code. These two programming modes, direct and background, will be referred to in this document as Flash Direct and Flash Background. (c) 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 14-1 tn1141_01.7 Lattice Semiconductor LatticeXP2 sysCONFIG Usage Guide Figure 14-1. Programming Block Diagram ispJTAG 1149.1 TAP sysCONFIG Port JTAG 1532 Master SPI Slave SPI Port Program in seconds Program in milliseconds Mode SDM Flash Memory Space Program in microseconds SRAM Memory Space Memory Space Configuration Pins The LatticeXP2 has one dedicated and nine dual-purpose sysCONFIG pins. The dual-purpose pins are available as extra I/O pins if they are not used for configuration. The configuration mode pins, along with a programmable option, controls how the LatticeXP2 will be configured. The configuration mode pins (CFG[1:0]) are generally hard wired on the PCB and determine which configuration mode will be used; the programmable option is accessed via preferences in Lattice ispLEVER(R) design software, or as HDL source file attributes, and allows the user to protect the configuration pins from accidental use by the user or the place-and-route software. The LatticeXP2 devices also support ispJTAG for configuration, including transparent readback, and for JTAG testing. The following sections describe the functionality of the sysCONFIG and JTAG pins. Note that JTAG and ispJTAG will be used interchangeably in this document. Table 14-1 is provided for reference. Table 14-1. Configuration Pins for the LatticeXP2 Device 1 Pin Name I/O Type Pin Type Mode Used CFG0 Input, weak pull-up Dedicated All CFG1 Input, weak pull-up Dual-Purpose2 MSPI, SSPI PROGRAMN Input, weak pull-up Dual-Purpose2 MSPI, SSPI INITN Bi-Directional Open Drain, weak pull-up Dual-Purpose2 MSPI, SSPI 2 DONE Bi-Directional Open Drain with weak pull-up or Active Drive Dual-Purpose MSPI, SSPI CCLK Input or Output Dual-Purpose MSPI, SSPI SISPI Input or Output Dual-Purpose MSPI, SSPI SOSPI Input or Output Dual-Purpose MSPI, SSPI CSSPISN Input, weak pull-up Dual-Purpose Slave SPI CSSPIN Output, tri-state, weak pull-up Dual-Purpose Master SPI TDI Input, weak pull-up JTAG TDO Output JTAG TCK Input with Hysteresis JTAG 14-2 Lattice Semiconductor LatticeXP2 sysCONFIG Usage Guide Table 14-1. Configuration Pins for the LatticeXP2 Device (Continued)1 Pin Name TMS I/O Type Pin Type Input, weak pull-up Mode Used JTAG 1. Weak pull-ups consist of a current source of 30uA to 150uA. The pull-up for CFG tracks VCC (core). This means that any voltage level above VCC is considered a "high." The pull-ups for TDI and TMS track VCCJ; all other pull-ups track the VCCIO for that pin. 2. This pin becomes a dedicated programming pin when the CFG0 pin is low. sysCONFIG Pins Following is a description of the sysCONFIG pins for the LatticeXP2 device. These pins are used to control or monitor the configuration process. These pins are used for non-JTAG programming sequences only. The JTAG pins will be explained later in the ispJTAG Pins section of this document. CFG[1:0] The Configuration Mode pin CFG0 is a dedicated input with a weak pull-up. The CFG1 pin is a dual-purpose input pin with a weak pull-up. The CFG pins are used to select the configuration mode for the LatticeXP2, i.e. what type of device the LatticeXP2 will configure from. At Power-On-Reset (POR), or when the PROGRAMN pin is driven low, the device will enter the configuration mode selected by the CFG[1:0] pins. Table 14-2. LatticeXP2 Configuration Modes Configuration Mode CFG[1] CFG[0] Mode Description Dual-Boot Mode 1 0 0 Will attempt to boot from the external SPI Flash first. If unsuccessful, then it tries to boot from internal Flash. Dual-Boot Mode 2 1 0 Will attempt to boot from the internal Flash first. If unsuccessful, then it tries to boot from external SPI Flash. Self Download Mode (SDM) X1 1 Single boot mode. The device will only try to boot from internal Flash. 1. Don't care. When the CFG0 pin is high, the device will configure itself by reading the data stored in on-chip Flash; this is referred to as SDM, or Self Download Mode. See the Self-Download section of this document for more information regarding SDM. If the CFG0 pin is low then the device will read the CFG1 pin to determine which mode to enter. When CFG1 is low the device will first attempt to configure the SRAM using Master SPI mode with the external SPI Flash port. If this fails then the device will configure itself from the on-chip Flash if a configuration file is stored there. When CFG1 is high the device will first attempt to configure the SRAM using on-chip Flash. If a configuration file is not stored there then the device will configure itself using Master SPI mode with the external SPI Flash port. Dual-Purpose sysCONFIG Pins The following is a list of the dual-purpose sysCONFIG pins. These pins are available as general purpose I/O after configuration. If a dual-purpose pin is to be used both for configuration and as a general purpose I/O the user must adhere to the following: * The I/O type must remain the same. In other words, if the pin is a 3.3V CMOS pin (LVCMOS33) during configuration it must remain a 3.3V CMOS pin as a GPIO. * The Persistent option must be set to OFF. The Persistent option will be set to OFF by the software unless the user sets the SLAVE_SPI_PORT to ENABLE using the Design Planner in ispLEVER. This option is shown in the Global tab of the Design Planner Speadsheet view. * The user is responsible for insuring that no internal or external logic will interfere with device configuration. After configuration these pins, if not used as GPIO, are tri-stated and weakly pulled up. 14-3 Lattice Semiconductor LatticeXP2 sysCONFIG Usage Guide CFG1 The CFG1 pin is a dual-purpose input with a weak pull-up. Its function is described in the section above. When the CFG0 pin is high, the CFG1 pin is not used for configuration and becomes a general purpose I/O pin available to the user. PROGRAMN The PROGRAMN pin is a dual-purpose input with a weak pull-up. This pin is used to initiate a non-JTAG SRAM configuration sequence. A high to low signal applied to PROGRAMN sets the device into configuration mode. The PROGRAMN pin can be used to trigger configuration at any time. If the device is using JTAG then PROGRAMN will be ignored until the device is released from JTAG mode. The PROGRAMN pin is only available if the CFG0 pin is set to 0 (not in SDM mode). When the CFG0 pin is set to 1 then PROGRAMN becomes a general purpose I/O pin available to the user. When the CFG0 pin is set to 0, the PROGRAMN pin becomes a dedicated programming pin. INITN The INITN pin is a dual-purpose bi-directional open drain pin with a weak pull-up. INITN is capable of driving a low pulse out as well as detecting a low pulse driven in. When using either the SPI Flash boot or Embedded Flash Boot mode to configure the SRAM, INITN going low indicates that the SRAM is being initialized; INITN going high indicates that the FPGA is ready to accept configuration data. To delay configuration the INITN pin can be held low externally. The device will not enter configuration mode as long as the INITN pin is held low. After configuration has started INITN is used to indicate a bitstream error. The INITN pin will be driven low if the calculated CRC and the configuration data CRC do not match; DONE will then remain low and the LatticeXP2 will not wake up. When using SDM, configuration from on-chip Flash INITN is not used or monitored. When programming on-chip Flash the INITN pin is not used. During Flash Direct programming an error will prevent the FPGA from configuring from the Flash, during Flash Background programming an error will not affect the configuration already running in SRAM. The INITN pin is only available if the CFG0 pin is set to 0 (not in SDM mode). When the CFG0 pin is set to 1 then INITN becomes a general purpose I/O pin available to the user. When the CFG0 pin is set to 0, the INITN pin becomes a dedicated programming pin. DONE The DONE pin is a dual-purpose bi-directional open drain with a weak pull-up (default), or an actively driven pin. DONE will be driven low when the device is in configuration mode and the internal DONE bit is not programmed. When the INITN and PROGRAMN pins go high, and the internal DONE bit is programmed, the DONE pin will be released (or driven high, if it is an actively driven pin). The DONE pin can be held low externally and, depending on the wake-up sequence selected, the device will not become functional until the DONE pin is externally brought high. Reading the DONE bit is a good way for an external device to tell if the FPGA is configured. When using JTAG to configure SRAM the DONE pin is driven by the boundary scan cell, so the state of the DONE pin has no meaning until configuration is completed. The DONE pin is only available if the CFG0 pin is set to 0 (not in SDM mode). When the CFG0 pin is set to 1 then DONE becomes a general purpose I/O pin available to the user. When the CFG0 pin is set to 0, the DONE pin becomes a dedicated programming pin. 14-4 Lattice Semiconductor LatticeXP2 sysCONFIG Usage Guide CCLK CCLK is a dual-purpose bi-directional pin; direction depends on whether a Master or Slave mode is selected. If a Master mode is selected, the CCLK pin will become an output pin; otherwise CCLK is an input pin. If the CCLK pin becomes an output, the internal programmable oscillator is connected to the CCLK and is driven out to slave devices. CCLK will stop 100 to 500 clock cycles after the DONE pin is brought high and the device wake-up sequence completed. The extra clock cycles ensure that enough clocks are provided to wake-up other devices in the chain. When stopped, CCLK becomes an input (tri-stated output). CCLK will restart (become an output) on the next configuration initialization sequence. CSSPIN The CSSPIN pin is a dual-purpose output pin with a weak pull-up. The CSSPIN is an active low chip select to an external SPI flash when used with the Master SPI mode. The CSSPIN pin becomes a dedicated pin if the CFG0 pin is set to 0 (not in SDM mode). When the CFG0 pin is set to 1 then CSSPIN becomes a general purpose I/O pin available to the user. If the CFG0 is set to 0 then this pin should be driven high unless the Master SPI mode is selected to avoid contention between the Master and Slave SPI modes. CSSPISN The CSSPISN pin is a dual-purpose input pin with a weak pull-up. The CSSPISN is an active low chip select to the internal SPI interface and is used with the Slave SPI mode. If the CSSPISN is driven low while in the middle of Master SPI port activity the Master SPI shall be disabled and the Slave SPI interface activated. The PERSISTENT preference must be set to ON in order to preserve this pin as CSSPISN and allow access to the Slave SPI interface. The PERSISTENT preference will be set by the software automatically when the user sets the SLAVE_SPI_PORT option in the Design Planner. SISPI The SISPI pin is a dual-purpose bi-directional pin; direction depends upon whether a Master or Slave mode is active. The SISPI is the Input data pin when using the Slave SPI mode and is the Output data pin when using the Master SPI mode. The PERSISTENT preference must be set to ON in order to preserve this pin as SISPI and allow access to the Slave SPI interface. The PERSISTENT preference will be set by the software automatically when the user sets the SLAVE_SPI_PORT option in the Design Planner. SOSPI The SOSPI pin is a dual-purpose bi-directional pin; direction depends upon whether a Master or Slave mode is active. The SOSPI is the Input data pin when using the Master SPI mode and is the Output data pin when using the Slave SPI mode. The PERSISTENT preference must be set to ON in order to preserve this pin as SOSPI and allow access to the Slave SPI interface. The PERSISTENT preference will be set by the software automatically when the user sets the SLAVE_SPI_PORT option in the Design Planner. 14-5 Lattice Semiconductor LatticeXP2 sysCONFIG Usage Guide Table 14-3. Flash Programming Mode Pin Usage Flash Programming Mode Port Direct 6 Pins User I/O States Background Direct Background 1 Slave SPI ispJTAG CCLK, CSSPISN, SISPI, SOSPI TAP Tristate User Keep at High Keep At High2 INITN Pass/Fail Pass/Fail Not Used3 DONE Done Not Used Keep at High4 Don't Caret5 ENABLE5 Don't Care PROGRAMN SLAVE_SPI_PORT preference BSCAN User 1. ispJTAG can be used to program the Flash regardless of the state of the CFG pins. 2. The state of the PROGRAMN pin is ignored by the device during JTAG Flash programming but the pin should be held high as a low will cause a configuration failure. When the device is in the SDM mode, the PROGRAMN pin is a dedicated I/O pin so it does not affect configuration. 3. The state of the INITN pin is ignored by the device during JTAG Flash programming but the pin should be allowed to float high using the internal pull-up. When the device is in the SDM mode, the INITN pin is a dedicated I/O pin so it does not affect configuration. 4. The state of the DONE pin is ignored by the device during JTAG Flash programming but the pin should be allowed to float high using the internal pull-up as a low can keep the device from waking up. When the device is in the SDM mode, the DONE pin is a dedicated I/O pin so it does not affect configuration. 5. The SLAVE_SPI_PORT preference must be set to ENABLE to use the Slave SPI port after the device has been configured. The Slave SPI port is also available when the device is not configured. 6. The Master SPI port can only be used to configure the SRAM in direct mode from an external SPI Flash memory. The CFG pins must be set per Table 14-2 to enable this mode. Table 14-4. Memory Access Modes Flash Mode Read 2 Slave SPI Yes Master SPI No SRAM Write 1 Read Write Yes Yes No No No Yes3 1. Slave SPI mode can only write to on-chip Flash memory in background mode unless the Flash memory is erased. 2. Slave SPI mode can read from on-chip Flash memory in background mode only. 3. Master SPI mode can write to SRAM in direct mode only. External SPI Flash When the Master SPI mode is used for configuration an external SPI Flash device is required to hold the configuration data. The size of the bitstream and the required external SPI Flash is shown in Table 14-5. Table 14-5. Maximum Configuration Bits Density Bitstream Size (Mb) SPI Flash (Mb) XP2-5 1.27 2 XP2-8 1.99 2 XP2-17 3.54 4 XP2-30 5.79 8 XP2-40 8.03 16 14-6 Lattice Semiconductor LatticeXP2 sysCONFIG Usage Guide Programming Sequence There are two types of programming, SRAM, and Flash Background. This section goes through the process for each showing how the dedicated pins are used. SRAM When not using SDM (Self Download Mode, on-chip Flash) to program the SRAM, the sequence begins when the internal power-on reset (POR) is released or the PROGRAMN pin is driven low (see Figure 14-2). The LatticeXP2 then drives INITN low, tri-states the I/Os, and initializes the internal SRAM and control logic. When this is complete, if PROGRAMN is high, INITN will be released. If INITN is held low externally the LatticeXP2 will wait until it goes high. When INITN goes high the LatticeXP2 begins looking for the configuration data using the internal Flash memory or the Master SPI port, as determined by the CFG pins. If the CFG1 pin is high and the Flash Done bit is set (indicating that the on-chip Flash memory is programmed) then the LatticeXP2 will boot from the on-chip Flash memory. If the Flash Done bit is not set then the LatticeXP2 will boot from the external SPI Flash memory using the Master SPI mode. If the CFG1 pin is low then the LatticeXP2 will boot from the external SPI Flash memory using the Master SPI mode. In the event of an error the LatticeXP2 will boot from the on-chip Flash memory if the Flash Done bit is set. Once configuration is complete the internal DONE bit is set, the DONE pin goes high, and the FPGA wakes up (enters user mode). If a CRC error is detected when reading the bitstream INITN will go low, the internal DONE bit will not be set, the DONE pin will stay low, and the LatticeXP2 will not wake up. When using SDM to program SRAM the sequence is similar but INITN is not used or monitored. The sequence begins when the internal power-on reset (POR) is released. The LatticeXP2 then tri-states the I/Os and initializes the internal SRAM and control logic. When initialization is complete the LatticeXP2 begins loading configuration data from on-chip Flash. When using SDM, if the Flash has been programmed, then the configuration sequence will proceed using the data in on-chip Flash. If the Flash has not been programmed, the configuration sequence will stop. Once the Flash has been programmed, a POR or JTAG Refresh instruction must occur to restart the configuration sequence. When using SDM, once configuration is complete, the internal DONE bit is set and the FPGA wakes up (enters user mode). The external Done pin is not available when using SDM configuration. Figure 14-2. SRAM Configuration Timing Diagram CCLK PROGRAMN INITN DONE Initialize Configure Wake-Up Flash Background Flash Background programming is possible using the Slave SPI port when it is enabled. The Slave SPI port can be enabled in the SDM mode as well as the SPI mode. Flash Background will not disturb the FPGA's present configuration in SRAM. 14-7 Lattice Semiconductor LatticeXP2 sysCONFIG Usage Guide Flash Background programming may be used in both config mode and user mode (Done bit = 0 or 1). To support Flash Background programming in user mode the SLAVE_SPI_PORT preference must be set to ENABLE. When the CSSPISN pin goes low, the FPGA will wait for the preamble and then look for the proper commands. A low on INITN indicates an error during a Flash erase or program. Data is written and read on the SISPI and SOSPI pins. After programming the Flash the user may toggle the PROGRAMN pin to transfer the Flash data to SRAM if the SPI mode is being used. If the SDM mode is being used then the SRAM will be updated on the next power up sequence of when a refresh instruction is issued. If the CSSPISN pin is driven low, the CSSPIN should be driven high and CCLK maintained as an input to prevent activating the Master SPI interface. This will avoid contention between the Master and Slave SPI interfaces. ispJTAG Pins The ispJTAG pins are standard IEEE 1149.1 TAP (Test Access Port) pins. The ispJTAG pins are dedicated pins and are always accessible when the LatticeXP2 device is powered up. When programming the SRAM via ispJTAG the dedicated programming pins, such as DONE, cannot be used to determine programming progress. This is because the state of the boundary scan cell will drive the pin, per JTAG 1149.1, rather than normal internal logic. TDO The Test Data Output pin is used to shift out serial test instructions and data. When TDO is not being driven by the internal circuitry, the pin will be in a high impedance state. TDI The Test Data Input pin is used to shift in serial test instructions and data. An internal pull-up resistor on the TDI pin is provided. The internal resistor is pulled up to VCCJ. TMS The Test Mode Select pin controls test operations on the TAP controller. On the falling edge of TCK, depending on the state of TMS, a transition will be made in the TAP controller state machine. An internal pull-up resistor on the TMS pin is provided. The internal resistor is pulled up to VCCJ. TCK The test clock pin, TCK, provides the clock to run the TAP controller, which loads and unloads the data and instruction registers. TCK can be stopped in either the high or low state and can be clocked at frequencies up to the frequency indicated in the device data sheet. The TCK pin supports the value is shown in the DC parameter table of the data sheet. The TCK pin does not have a pull-up. A pull-down on the PCB of 4.7 K is recommended to avoid inadvertent clocking of the TAP controller as VCC ramps up. VCCJ JTAG VCC (VCCJ) supplies independent power to the JTAG port to allow chaining with other JTAG devices at a common voltage. VCCJ must be connected even if JTAG is not used. This voltage may also power the JTAG download cable. Valid voltage levels are 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V. Please see In-System Programming Design Guidelines for ispJTAG Devices for further information. Configuration and JTAG Voltage Levels All of the control pins and programming pins default to LVCMOS. The CFG0 pin is linked to VCC (core); TCK, TDI, TDO, and TMS track VCCJ; all other pins track the VCCIO for that pin. 14-8 Lattice Semiconductor LatticeXP2 sysCONFIG Usage Guide Configuration Modes and Options The LatticeXP2 device supports two configuration modes, utilizing the SPI port or self-configuration. On power up, or upon driving the PROGRAMN pin low depending upon the current mode, the CFG[1:0] pins are sampled to determine the mode that will be used to configure the LatticeXP2 device. The CFG pins are generally hard wired on the PCB and determine how the device will retrieve its configuration data. The SLAVE_SPI_PORT preference is a programmable option which can be set using the Design Planner in Lattice ispLEVER design software, or as HDL source file attributes, and allow the user to protect the configuration pins from accidental use by the user or the place-and-route software. Configuration Options Several configuration options are available for each configuration mode. * When using a master clock, the master clock frequency can be set. * A security bit is provided to prevent SRAM or Flash readback. By setting the proper parameters in the Lattice ispLEVER design software the selected configuration options are set in the generated bitstream. As the bitstream is loaded into the device the selected configuration options take effect. These options are described in the following sections. Master Clock If the LatticeXP2 is a Master device the CCLK pin will become an output with the frequency set by the user. The default Master Clock Frequency is 2.5 MHz. The software default adjusts the MCLK frequency to 3.1 MHz in the programming bitstream. The user can determine the Master Clock frequency by setting the MCCLK_FREQ. One of the first things loaded during configuration is the MCCLK_FREQ parameter; once this parameter is loaded the frequency changes to the selected value using a glitchless switch. Care should be exercised not to exceed the frequency specification of the slave devices or the signal integrity capabilities of the PCB layout. The MCCLK frequency selections made by the user are only valid if the LatticeXP2 device is booted from external SPI Flash. The internal Flash will not control the MCCLK frequency setting in the JEDEC file. In the case of device boot from internal Flash the MCCLK frequency is always 3.1 MHz. In the case of booting the device from external SPI Flash, the user can use UFW program inside the ispVM tool suite to convert the JEDEC file to bitstream format. The UFW program supports MCCLK_FREQ selections. In this case the user can select MCCLK_FREQ during bitstream conversion. MCCLK FREQ selections from UFW range 2.5 MHz to 130 MHz. Security Bit Setting the security bit prevents readback of the SRAM and Flash from JTAG or the sysCONFIG pins. When the security bit is set the only operations available are erase and write. The security bit is updated as the last operation of SRAM configuration or Flash programming. By using on-chip Flash, and setting the security bit, the user can create a very secure device. The security bit is accessed via the Design Planner in ispLEVER design software. More information on device security can be found in the document FPGA Design Security Issues: Using the ispXPGA Family of FPGAs to Achieve High Design Security. Slave SPI Mode In the Slave SPI mode the CCLK pin becomes an input and commands will be read into the LatticeXP2 on the SISPI pin at the rising edge of CCLK. Data will be written out of the LatticeXP2 on the SOSPI pin at the falling edge of CCLK. Care must be exercised during read back of EBR or PFU memory. It is up to the user to ensure that reading these RAMs will not cause data corruption, i.e. these RAMs may not be read while being accessed by user code. 14-9 Lattice Semiconductor LatticeXP2 sysCONFIG Usage Guide The CSSPISN enables and disables the SPI interface operation. When CSSPISN is high the SPI interface is deselected and the SOSPI pin is at high impedance. When CSSPISN is brought low the SPI interface is selected, commands can be written into and data read from the LatticeXP2. After power up the CSSPISN must transition from high to low before a new command can be accepted. The Slave SPI mode can also be used to access on-chip Flash. The CSSPISN pin must be held low to write to onchip Flash; data is input from SISPI. The Slave SPI mode can also be used for readback of both Flash and SRAM. By driving the CSSPISN low, the device will input the readback instructions on the SISPI pin and the data will be written out on the SOSPI pin; a bit in the read command will determine if the read is directed to Flash or SRAM. In order to support readback while the device is in user mode (the DONE pin is high), the SLAVE_SPI_PORT preference must be set to ENABLE using the Design Planner. Master SPI Mode In Master SPI mode the LatticeXP2 will drive CCLK out to the Slave SPI Flash device that will provide the bitstream. The Master device will write commands out on SISPI at the rising edge of CCLK and will accept data on SOSPI at the falling edge of CCLK. The Master Serial device starts driving CCLK at the beginning of the configuration and continues to drive CCLK until the external DONE pin is driven high and an additional 100 to 500 clock cycles have been generated. The CCLK frequency on power up defaults to 2.5 MHz. The master clock frequency default remains unless a new clock frequency is loaded from the bitstream. Self Download Mode Self Download Mode (SDM) allows the FPGA to configure itself without using any external devices, and because the bitstream is not exposed this is also a very secure configuration mode. The user may access on-chip Flash using ispJTAG or the slave SPI port pins. JTAG may access the on-chip Flash any time the device is powered up, without disturbing device operation. JTAG may also read and write the configuration SRAM. If access to the on-chip Flash and SRAM is limited to JTAG then SLAVE_SPI_PORT can be set to DISABLE, freeing the dual-purpose pins for use as general purpose I/O. ispJTAG Mode The LatticeXP2 device can be configured through the ispJTAG port. The ispJTAG port is always on and available, regardless of the configuration mode selected. The SLAVE_SPI_PORT can be set to DISABLE in the Lattice ispLEVER design software to tell the place and route tools that the JTAG port will be used exclusively, i.e. the SPI port will not be used. Setting the SLAVE_SPI_PORT to DISABLE allows software to use all of the dual-purpose pins as general purpose I/Os. ISC 1532 Configuration through the ispJTAG port conforms to the IEEE 1532 Standard. The Boundary Scan cells take control of the I/Os during any 1532 mode instruction. The Boundary Scan cells can be set to a pre-determined value whenever using the JTAG 1532 mode. Because of this the dedicated pins, such as DONE, cannot be relied upon for valid configuration status. Transparent Readback The ispJTAG Transparent Readback mode allows the user to read the content of the device SRAM or Flash while the device remains in a functional state. Care must be exercised when reading EBR and distributed RAM, as it is possible to cause conflicts with accesses from the user design (causing possible data corruption). The I/O and non-JTAG configuration pins remain active during a Transparent Readback. The device enters the Transparent Readback mode through a JTAG instruction. Boundary Scan and BSDL Files BSDL files for this device can be found on the Lattice website at www.latticesemi.com. The boundary scan ring covers all of the I/O pins, as well as the dedicated and dual-purpose sysCONFIG pins. 14-10 Lattice Semiconductor LatticeXP2 sysCONFIG Usage Guide Wake Up Options When configuration is complete (the SRAM has been loaded), the device should wake up in a predictable fashion. The following selections determine how the device will wake up. Two synchronous wake up processes are available. One automatically wakes the device up when the internal Done bit is set regardless of whether the DONE pin is held low externally or not, the other waits for the DONE pin to be driven high before starting the wake up process. The DONE_EX preference determines whether the external DONE pin will control the synchronous wake up. When the device is in the SDM mode the DONE pin is not used and therefore the DONE_EX preference has no effect. Wake Up Sequence Table 14-6 provides a list of the wake up sequences supported by the LatticeXP2. Table 14-6. Wake Up Sequences Supported by LatticeXP2 Sequence Phase T0 Phase T1 Phase T2 Phase T3 1 DONE GOE, GWDIS, GSR 2 DONE 3 DONE 4 DONE GOE 5 DONE GOE 6 DONE GOE GWDIS GSR 7 DONE GOE GSR GWDIS 8 DONE GOE, GWDIS, GSR 9 DONE 10 DONE GWDIS, GSR GOE 11 DONE GOE GWDIS, GSR DONE GOE, GWDIS, GSR 13 GOE, GWDIS, GSR DONE 14 GOE DONE GWDIS, GSR 15 GOE, GWDIS DONE GSR GOE, GWDIS, GSR GOE, GWDIS, GSR GWDIS, GSR GWDIS, GSR GOE, GWDIS, GSR 12 16 GWDIS DONE GOE, GSR 17 GWDIS, GSR DONE GOE 18 GOE, GSR 19 20 21 (Default) DONE GWDIS GOE, GWDIS, GSR DONE GWDIS, GSR DONE GOE, GWDIS, GSR GOE DONE 22 GOE, GWDIS GSR DONE 23 GWDIS GOE, GSR DONE 24 GWDIS, GSR GOE DONE 25 GOE, GSR GWDIS DONE 14-11 Lattice Semiconductor LatticeXP2 sysCONFIG Usage Guide Figure 14-3. Wake Up Sequence to Internal Clock BCLK DONE BIT GLOBAL OUTPUT ENABLE GLOBAL SET/RESET GLOBAL WRITE DISABLE DONE PIN T0 T1 T2 T3 Synchronous to Internal Done Bit If the LatticeXP2 device is the only device in the chain, or the last device in a chain, the wake up process should be initiated by the completion of the configuration. Once the configuration is complete, the internal Done bit will be set and then the wake up process will begin. Synchronous to External DONE Signal The DONE pin can be selected to delay wake up. If DONE_EX is true then the wake up sequence will be delayed until the DONE pin is high. The device will then follow the WAKE_UP sequence selected. When the device is in the SDM mode the DONE pin is not used and therefore the DONE_EX preference has no effect. Software Selectable Options In order to control the configuration of the LatticeXP2 device beyond the default settings, software preferences are used. Table 14-7 is a list of the preferences with their default settings. Table 14-7. Software Preference List for the LatticeXP2 Preference Name SLAVE_SPI_PORT Default Setting [List of All Settings] DISABLE [disable, enable] MASTER_SPI_PORT DISABLE [disable, enable] DONE_OD ON [off, on] DONE_EX OFF [off, on] CONFIG_SECURE OFF [off, on] WAKE_UP 21 (DONE_EX = off) 4 (DONE_EX = on) WAKE_ON_LOCK OFF [off, on] INBUF ON [off, on] Slave SPI Port In order to use the Slave SPI port while in user mode to read SRAM or Flash memory, the SLAVE_SPI_PORT preference must be set to ENABLE. Setting this preference preserves the Slave SPI port pins so the FPGA can be accessed by an external device while in user mode. This also lets the software know that the Slave SPI port pins are reserved and NOT available for use by the fitter or the user. 14-12 Lattice Semiconductor LatticeXP2 sysCONFIG Usage Guide Master SPI Port In order to use the Master SPI Port for configuration, the MASTER_SPI_PORT preference should be set to ENABLE. Configuration Mode The device knows which physical sysCONFIG port will be used by reading the state of the CFG[1:0] pins, but the fitter software also needs to know which port will be used. The fitter will determine the configuration mode based upon the setting of the SLAVE_SPI_PORT and the MASTER_SPI_PORT preferences. The user may set these preferences, and the ones listed below, using the Design Planner tool. There are several additional configuration options, such as overflow, that are set by software. These options are selected by clicking Properties under Generate Bitstream Data in ispLEVER. If either overflow option is selected, then the DONE_EX and WAKE_UP selections will be set to correspond (see Table 14-8). Refer to the Configuration Modes and Options section of this document for more details. Table 14-8. Overflow Option Defaults Overflow Option DONE_EX Preference WAKE_UP Preference Off Off (Default) Default 21 (user selectable 1 through 25) Off On Default 21 (user selectable 1 through 25) On (automatically set by software) Default 4 (User selectable 1 through 7) On (either) DONE Open Drain The "DONE_OD" preference allows the user to configure the DONE pin as an open drain pin. The "DONE_OD" preference is only used for the DONE pin. When the DONE pin is driven low, internally or externally, this indicates that configuration is not complete and the device is not ready for the wake up sequence. Once configuration is complete, with no errors, and the device is ready for wake up, the DONE pin must be driven high. For other devices to be able to control the wake up process an open drain configuration is needed to avoid contention on the DONE pin. The "DONE_OD" preference for the DONE pin defaults to ON. The DONE_OD preference is automatically set to ON if the DONE_EX preference is set to ON. See Table 14-9 for more information on the relationship between DONE_OD and DONE_EX. When the device is in the SDM mode the DONE pin is not used and therefore the DONE_OD and DONE_EX preferences have no effect. DONE External The LatticeXP2 device can wake up on its own after the Done bit is set or wait for the DONE pin to be driven high externally. Set DONE_EX = ON to delay wake up until the DONE pin is driven high by an external signal synchronous to the clock; select OFF to synchronously wake up when the internal Done bit is set and ignore any external driving of the DONE pin. The default is DONE_EX = OFF. If DONE_EX is set to ON, DONE_OD will be set to ON. If an external signal is driving the DONE pin it should be open drain as well (an external pull-up resistor may need to be added). See Table 14-9 for more information on the relationship between DONE_OD and DONE_EX. Table 14-9. Summary of DONE Pin Preferences DONE_EX1 Wake Up Process DONE_OD1 OFF External DONE ignored User selected ON External DONE low delays Set to Default (ON) 1. When the device is in the SDM mode the DONE pin is not used and therefore the DONE_OD and DONE_EX preferences have no effect. Master Clock Selection When the user has determined that the LatticeXP2 will be a master configuration device (by properly setting the CFG[1:0] pins), and therefore provide the source clocking for configuration, the CCLK pin becomes an output with the frequency set by the value in MCCLK_FREQ. At the start of configuration the device operates at the default 14-13 Lattice Semiconductor LatticeXP2 sysCONFIG Usage Guide Master Clock Frequency of 2.5 MHz. Some of the first bits in the configuration bitstream are MCCLK_FREQ, once these are read the clock immediately starts operating at the user-defined frequency. The clock frequency is changed using a glitchless switch. The default MCCLK frequency set in the bitstream is 3.1 MHz. Security When CONFIG_SECURE is set to ON, NO read back operation will be supported through the sysCONFIG or ispJTAG port of the general contents. The ispJTAG DeviceID area is readable and not considered securable. Default is OFF. Wake Up Sequence The WAKE_UP sequence controls three internal signals and the DONE pin. The DONE pin will be driven after configuration and prior to user mode. See the Wake Up Sequence section of this document for an example of the phase controls and information on the wake up selections. The default setting for the WAKE_UP preference is determined by the DONE_EX setting. Wake Up with DONE_EX = Off (Default Setting) The WAKE_UP preference for DONE_EX = OFF (default) supports the user selectable options 1 through 25, as shown in Table 14-6. If the user does not select a wake-up sequence, the default, for DONE_EX = OFF, will be wake-up sequence 21. Wake Up with DONE_EX = On The WAKE_UP preference for DONE_EX = ON supports the user selectable options 1 through 7, as shown in Table 14-6. If the user does not select a wake-up sequence, the default will be wake-up sequence 4. Wake On Lock Selection The Wake On Lock preference determines whether the device will wait for the PLL to lock before beginning the wake-up process. ON - The device will not wake up until the PLL lock signal for the given PLL is active. OFF (default) - The device will wake up regardless of the state of the PLL lock signal. Power Save An I/O Power Save mode option, called INBUF, is used for the LatticeXP2 device and will deactivate unused input buffers to save power. This is only affects comparator type inputs pins (pins that use VREF), like HSTL, SSTL, etc. The Power Save mode limits some of the functionality of Boundary Scan. For Boundary Scan testing it is recommended that the INBUF global preference be turned ON to activate all unused input buffers. One Time Programmable Fuse The LatticeXP2 has a One Time Programmable (OTP) fuse that can be used to prevent the on chip Flash configuration memory from being erased or programmed. This does not prevent the Flash Tag Memory or Flash User memory from being programmed, so these features are still available. The OTP fuse can be set using the Global Configuration options in the ispLEVER Design Planner or it can be set directly using the ispVM(R) System software at the time of download. User GOE The LatticeXP2 has a User GOE (Global Output Enable) feature. This allows the I/Os to be held in Boundary scan control after the standard wake-up sequence has completed. User logic determines when the outputs get turned over from Boundary Scan to User Logic control. This user logic input will be through a CIB and is valid for JTAG "wake up" instructions only. This feature is instantiated by the user as a macro called IOWAKEUP. This macro only has one signal and can only be controlled immediately after the wakeup sequence (not anytime after). 14-14 Lattice Semiconductor LatticeXP2 sysCONFIG Usage Guide Tag Memory The TAG Memory is a block of Flash memory which is always available for read or write (programming in Flash terms) through the Slave SPI port. The LatticeXP2 can be in user mode or an un-programmed state (blank device), independent of the CFG[1:0] pin setting. The only exceptions would be when the LatticeXP2 is in BSCAN test or in direct programming mode. During these modes the SPI interface is unavailable because the I/O is under BSCAN control. The TAG memory is also available through the JTAG port. Table 14-10 shows the amount of Tag memory available in each LatticeXP2 device. Each LatticeXP2 device has one dedicated row of TAG memory. Table 14-10. LatticeXP2 Family TAG Memory Device Density Tag Memory (Bits) Tag Memory (Bytes) XP2-5 632 79 XP2-8 768 96 XP2-17 2184 273 XP2-30 2640 330 XP2-40 3384 423 Note: The Initial Power on Value (INITVAL) for all Flash cells is all 1's. The TAG memory has the following features and limitations. * Each row of TAG memory is limited to sequential access only. Once the read command is specified, the entire TAG memory contents are read sequentially in a first-in-first-out manner. * Data access speed is limited by the speed of the TAG memory which is Flash based. * The TAG memory comes from the factory erased. It will retain the user assigned value after programming even during power off periods. * The TAG memory can be read or written using the hardwired JTAG and SPI interface pins. * The TAG memory is ready to use upon power-up of the LatticeXP2. It does not need any software IP or design loaded into the device to access the TAG memory via the hardwired interface. * The TAG memory can also be read and modified from the FPGA core logic using the slave-SPI CIB interface pins to emulate an I2C port. * The TAG memory is always accessible regardless of the security setting of the device. The TAG memory is designed for storing typically "static" data - data that is not likely to change. This TAG memory can take the place of an EEPROM or simple Flash memory on the PCB which might be used for the following system management and manufacturing control information (listed as examples only): * Saving Electronic ID codes * Version management * Date stamping * Manufacturing version control * Asset management and tracking * System calibration settings * Device serialization and/or inventory control. 14-15 Lattice Semiconductor LatticeXP2 sysCONFIG Usage Guide Slave SPI Mode Operation The Slave SPI Mode interface to the TAG memory supports both SPI Bus Mode 0 and Mode 3 operations. In SPI Bus Mode 0 the CLK pin is normally low when the SPI master is in standby and data is not being transmitted. In SPI Bus Mode 3 the CLK pin is normally high during this condition. In both cases the data at the SISPI pin is sampled on the rising edge of CCLK and the data output on the SOSPI pin is clocked on the falling edge of CCLK. For more information on using the TAG memory please see TN1137, LatticeXP2 Memory Usage Guide. User Flash The User Flash is designed as a non-volatile memory location to back up the data stored in the EBR RAM blocks. This gives the user a reliable method to save the contents of the RAM memory for later use. The amount of User Flash for LatticeXP2 devices is directly tied to the number of EBR blocks in the device and it scales with density. The User Flash is organized physically as either 1- or 2- separate User Flash Modules. However, all User Flash Modules are logically treated as one unified block. Table 14-11. User Flash Organization XP2-5K XP2-8K XP2-17K XP2-30K XP2-40K Physical UFM blocks Block Type 1 1 2 2 2 Logical UFM blocks 1 1 1 1 1 The EBR blocks act as the primary interface for the User Flash. Users do not have direct access to the User Flash. The contents of the EBR can be saved into the User Flash via a store-to-flash control signal. The EBR contents must be saved into the User Flash when required. Two signals, UFMFAIL and UFMBUSYN are provided for keeping track of the status of the store-to-flash command. If the UFMFAIL signal is low and the UFMBUSYN signal is high then the EBR contents were successfully stored in the Flash memory. The User Flash memory has the following constraints upon its usage. * The Store-to-Flash operation has impact only on the EBR RAM (Single-Port, True Dual-Port, Pseudo Dual-Port) configurations. * During the Store-to-Flash operation, the EBR blocks are unavailable for user operation and the Flash is unavailable for configuration operation. * No selective EBR storing is supported. A Store-to-Flash operation will store the contents of all EBR blocks. * Due to silicon limitations the user cannot use Store-to-Flash operation if the SED is operating in an Always mode. * UFM mode cannot concurrently be used with Transparent/Background mode (Flash or SRAM). The SSPI configuration and verify operations (which are essentially Transparent Mode operations) are initiated by the user and the user needs to ensure that the UFM operation is not requested at the same time. Table 14-12. Differences Between User Flash and Shadow Flash (EBR) Behavior Parameter User Flash Shadow Flash (EBR) Read/write access speed Slow Fast Access nature Sequential Random Data access Limited (refer to Sec13.3) Infinite or unlimited Data organization Sequential, one bit at a time Flexible, variable data width Data granularity Whole UFM block One EBR block For more information, please see TN1137, LatticeXP2 Memory Usage Guide. 14-16 Lattice Semiconductor LatticeXP2 sysCONFIG Usage Guide Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com Revision History Date Version Change Summary February 2007 01.0 Initial release. May 2007 01.1 Updated sysCONFIG Pin descriptions January 2008 01.2 Added footnote to Summary of DONE Pin Preferences table. Updated Slave SPI Port information and PROGRAMN pin usage. Removed PERSISTENT and CONFIG_MODE preferences. Added SLAVE_SPI_PORT and MASTER_SPI_PORT preferences. February 2008 01.3 Corrected SLAVE_SPI_PORT settings in ispJTAG mode section. Corrected INITN pin description. Corrected SDM configuration description in SRAM section. November 2008 01.4 Updated Dual-Purpose sysCONFIG Pins text section. April 2009 01.5 Updated LatticeXP2 Configuration Modes table. June 2009 01.6 Added clarification to MCCLK frequency selection. July 2011 01.7 Updated LatticeXP2 Configuration Modes table. 14-17 LatticeXP2 Configuration Encryption and Security Usage Guide May 2008 Technical Note TN1142 Introduction Unlike a volatile FPGA, which requires an external boot-prom to store configuration data, the LatticeXP2TM devices are non-volatile and have on-chip configuration Flash. Once programmed (either by JTAG or SPI port), this data is a part of the FPGA device and can be used to self-download the SRAM portion without requiring any additional external boot prom. Hence it is inherently more secure than volatile FPGAs. Like the LatticeECP2/M, the LatticeXP2 family also offers the 128-bit Advanced Encryption Standard (AES) to protect the externally stored programming file. The user has total control over the 128-bit key and no special voltages are required to maintain the key within the FPGA. Additional security enhancement for the LatticeXP2 includes: * A security bit for the Configuration and User Flash * One-Time-Programmable (OTP) or Permanent Lock capability * Flash Protect This document explains the encryption and security features and how to take advantage of them. Encryption/Decryption Flow The LatticeXP2 supports both encrypted and non-encrypted JEDEC files. Since the non-encrypted flow is covered in TN1141, LatticeXP2 sysCONFIGTM Usage Guide, this document will concentrate on the additional steps needed for the encrypted flow. The encrypted flow adds only two steps to the normal FPGA design flow, encryption of the configuration JEDEC file and programming the encryption key into the LatticeXP2. Figure 15-1 is a block diagram describing the LatticeXP2 encryption data paths that will be used throughout this document. Figure 15-1. Encryption Block Diagram along with Flash Protect SRAM AES Encrypt Enable 128-Bit Flash Decryption Key Encrypted Data AES Decrypted Data Data Shift Register CRC 64-Bit Flash Enable Key Flash Protect Key Configuration Flash Program Enable Configuration Flash Encrypting the JEDEC File As with any other Lattice FPGA design flow, the design engineer must first create the design using the ispLEVER(R) design tool suite. The design is synthesized, mapped, placed and routed, and verified. Once the user is satisfied with the design, the final JEDEC file is ready for FPGA programming. This final JEDEC file is used to secure the design. The JEDEC file can be encrypted using ispLEVER by going to the Tools -> Security Settings pull-down menu or by using the Universal File Writer (ispUFW), which is part of the Lattice ispVM(R) System tool suite. (c) 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 15-1 tn1142_01.1 LatticeXP2 Configuration Encryption and Security Usage Guide Lattice Semiconductor ispLEVER Flow 1. As mentioned above, to access the LatticeXP2 security setting GUI, go to Project Navigator -> Tools -> Security Settings. A password is required before entering the security features GUI section of the LatticeXP2. Figure 15-2. Password Prompt with Default Password 2. This Password GUI prompt will automatically show the default password "LATTICESEMI". The default password is in place for users who do not want to remember any administrative password, and especially for those who want to use the CONFIG_SECURE setting only. Users have the option of changing the password. It is the user's responsibility to track all the keys and passwords since they will not be stored in the design files. Figure 15-3. Security Settings 3. Once the user has selected security features, encrypted files will then be generated. ispVM Flow 1. Start ispUFW. You can start ispUFW from the Start -> Programs -> Lattice Semiconductor menu in Windows. You will see a window that looks similar to Figure 15-4. You can also launch the ispUFW from the ispVM GUI by clicking on the UFW button on the toolbar (shown in Figure 15-5). Select JEDEC as the output file format, as shown in Figure 15-4. 15-2 LatticeXP2 Configuration Encryption and Security Usage Guide Lattice Semiconductor Figure 15-4. Universal File Writer Figure 15-5. ispVM Main Window 2. Double-click on Input Data File and browse to the non-encrypted JEDEC file created using ispLEVER. Double-click on Output Data File and select an output file name. Right-click on Encryption and select ON. Right-click on Encryption Key and select Edit Encryption Key. You will see a window that looks similar to Figure 15-6. Figure 15-6. Encryption Dialog Window 3. Enter the desired 128-bit encryption key. The key can be entered in Hexadecimal or ASCII. Hex supports 0 through F and is not case sensitive. ASCII supports all printable (ASCII codes 30 through 126) characters. You may also import the 128-bit encryption key from the <Project_Name>.bek generated by ispLEVER. To do so, click on the Load From File button shown in Figure 15-6. Click On OK to go back to the main ispUFW window. Note: Be sure to remember this key, as Lattice cannot recover lost keys. 4. From the ispUFW menu bar click on Project -> Generate or the JEDEC file. icon to create the encrypted 5. Before the LatticeXP2 can configure with the encrypted JEDEC file, the 128-bit encryption key used to encrypt the JEDEC file must be programmed into the LatticeXP2 device. 15-3 LatticeXP2 Configuration Encryption and Security Usage Guide Lattice Semiconductor Programming the Key into the Device The next step is to program the 128-bit encryption key into the LatticeXP2. Note that this step is separated from JEDEC file encryption to allow flexibility in the manufacturing flow. This flow adds to design security and it allows the user to control over-building of a design. Over-building occurs when a third party builds more boards than are authorized and sells them to grey market customers. If the key is programmed at the factory, then the factory controls the number of working boards that enter the market. The LatticeXP2 will only configure from a file that has been encrypted with the same 128-bit encryption key that is programmed into the LatticeXP2. To program the 128-bit encryption key into the LatticeXP2, proceed as follows. 1. Start ispVM. You can start ispVM from the Start -> Programs -> Lattice Semiconductor menu in Windows or from the ispLEVER GUI. You will see a window that looks similar to Figure 15-5. 2. Attach a Lattice ispDOWNLOAD(R) cable from a PC to the JTAG connector wired to the LatticeXP2. Note: The 128-bit encryption key can only be programmed into the LatticeXP2 using the JTAG port. 3. Apply power to the board. 4. If the window does not show the board's JTAG chain, then proceed as follows. Otherwise, proceed to step number 5. a. Click the SCAN button in the toolbar to find all Lattice devices in the JTAG chain. The chain shown in Figure 15-5 has only one device, the LatticeXP2. Figure 15-7. ispVM Device information GUI 5. Double-click on the line in the chain containing the LatticeXP2. This will open the Device Information window (see Figure 15-7). From the Device Access Options drop-down box, select Advanced Security Mode, then click on the Security Key button to the right. The window will look similar to Figure 15-8. 15-4 LatticeXP2 Configuration Encryption and Security Usage Guide Lattice Semiconductor Figure 15-8. ispVM Flash Protection Key 6. Enter the 64-bit Flash Protect key or load it from the file (<Project_Name>.key). You can save this to a file by clicking Save to File button. Once you click Apply, you will be asked to enter the 128-bit encryption as shown in Figure 15-9. Figure 15-9. ispVM Encryption Key GUI 7. Now enter the desired 128-bit encryption key. The key can be entered in Hexadecimal or ASCII. Hex supports 0 through F and is not case sensitive. ASCII supports all printable (ASCII codes 30 through 126) characters. This key must be the same as the key used to encrypt the JEDEC file. The LatticeXP2 will only configure from an encrypted JEDEC file whose 128-bit encryption key matches the one loaded into the LatticeXP2. 15-5 LatticeXP2 Configuration Encryption and Security Usage Guide Lattice Semiconductor Note: Be sure to remember this key. Once the Key Lock is programmed, Lattice Semiconductor cannot read back the128-bit encryption key. a. The 128-bit encryption key can be saved to a file using the Save to File button. The 128-bit encryption key will be encrypted using an 8-character file password that the user selects. The name of the file will be <Project_Name>.bek. In the future, instead of entering the 128-bit key, simply click on Load from File and provide the file password. 8. Programming the Key Lock secures the 128-bit encryption key. When satisfied, type Yes to confirm, and then click Apply. Once the Key Lock is programmed and the device is power cycled, the 128-bit encryption key cannot be read out of the device. 9. From the main ispVM window (Figure 15-5) click on the green GO button on the toolbar to program the 128-bit encryption key into the LatticeXP2. When complete, the LatticeXP2 will only configure from a JEDEC file encrypted with a key that exactly matches the one just programmed. Security Bit for the Configuration and User Flash (CONFIG_SECURE) The CONFIG_SECURE setting is located in the GUI setting (Figure 15-3) mentioned in the previous section. After security for the device is selected, NO readback operation is supported through the sysCONFIG port or ispJTAGTM port of the general contents. This is considered the lowest level of security. Advanced Security Settings Selecting Advanced Security Settings will enable more security features. One-Time Programmable (OTP), Flash Protect and Encryption as shown in Figure 15-3. These settings are mutually exclusive. Selecting one or the other may nullify other fields that are not required for each particular security settings. One-Time Programmable (OTP) or Permanent Lock One-Time Programmable (OTP) or permanent lock is another feature that provides the highest level of security. This form of security is currently available only for LatticeXP2 devices. If OTP fuses are programmed it permanently prevents write access to the devices contents. Users must be aware before using this feature that once the OTP is programmed it is not possible to erase or reprogram the device or its security settings. As the name implies, it is a one-time event only. Table 15-1 specifies the behavior of the chip when security bit and the OTP bit are programmed. Table 15-1. Security and OTP Bit Settings Security CONFIG_SECURE OTP Bit 0 0 Action Do nothing Re-Program Read Back Erase Yes Yes Yes 0 1 Inhibit Erase or Programming No Yes No 1 0 Inhibit Readback Yes No Yes 1 1 Inhibit Erase, Programming or Readback No No No 15-6 LatticeXP2 Configuration Encryption and Security Usage Guide Lattice Semiconductor Flash Protect Figure 15-10. Flash Protect Key Input for Programming TDI TDO 64-Bit Key Shift Register Capture for Fuse Pattern Verify. Disabled when Key Lock Fuse. Output for Fuse Pattern Verification Update for Fuse Pattern Programming Flash Program Enable Flash Enable Fuses The next highest level of security for the LatticeXP2 is the 64-bit Flash Protect feature. The 64-bit Flash protect key is used to protect the embedded configuration flash from accidental or unauthorized erasure or reprogramming. This feature does not prevent the device from read back. Therefore, user is given the option to turn ON the CONFIG_SECURE feature. The default 64-bit Flash protect key is "_LATTICE". Users can also enter their own 64-bit Flash protect key. If there is an existing 64-bit Flash protect key in the Flash Protect key file, the 64-bit Flash protect key can be imported for the Flash Protect key file (<Project_Name>.key). The ispVM GUI will display the Flash Protect key in the same format selected when the 64-bit Flash Protect key was created. Users have the option to change the 64-bit Flash protect key using the default by clicking on the Default Key button. The ispVM software will automatically check the LatticeXP2 device to see if the Flash Protect feature is enabled. If it is, ispVM software will prompt the user to enter the 64-bit Flash Protect key before performing an erase or programming operation. If the 64-bit Flash Protect programmed in the device matches the 64-bit Flash Protect key entered in the ispVM GUI, the device can be erased and reprogrammed. If the keys are lost, the programmed device will be an OTP device. The re-programming of the device requires the user to enter the 64-bit Flash Protect key programmed into the device first. If it matches the 64-bit key (stored in the device), the device will enter the programming mode for erasure and re-programming of the Flash as well as the SRAM fuses. Note: The Flash Protect key cannot be the same as the Encryption Key. The Flash Protect key is 64 bits and the encryption key is 128 bits. Changing Flash Protect If the user decides to change the key, it can be done in the key field. The newly created Flash Protect key file (<Project_Name>.key) contains the new 64-bit Flash Protect key and is now ready to be programmed into a device. The user can also revert back to using the default password by clicking on the Default button next to the Flash Protect Key. The default password is "_LATTICE". 15-7 LatticeXP2 Configuration Encryption and Security Usage Guide Lattice Semiconductor Figure 15-11. Encryption/Flash Protect Advanced Feature Encryption The LatticeXP2 family of devices uses the 128-bit Advanced Encryption Standard (AES) security mechanism and has a built-in AES decryption engine hardwired in the core and embedded in the device. The JEDEC file must be encrypted with the same 128-bit AES encryption key programmed into the device in order to configure it. The file is shifted into the device's JTAG port using ispVM System software. The device decrypts the JEDEC file using the 128-bit encryption key programmed into the device. The device can only be programmed if the 128-bit encryption key programmed into the device matches the 128-bit encryption key used to encrypt the JEDEC file. Usercode in Encrypted Files Note: The usercode is stored as a comment and will be programmed into the device's usercode. If the USERCODE is used as a custom device ID (MY_ASSP), the U field will still be used in the JEDEC file for the CRC and the value of the Custom Device ID set by the user will be part of the comment field. The USERCODE will be available for readback regardless of the encryption setting (the USERCODE is always available for readback). Readback of the decrypted JEDEC file from a device through the JTAG port is not permitted because the security fuse is programmed when Encryption/Flash Protect is selected. Encryption will not affect the functionality of the SED Decryption Flow The decryption flow is a much simpler process. Start by programming the device with the 128-bit Encryption Key and the 64-bit Flash Protect Key fuses. Once the keys are programmed, the device can then be programmed with the encrypted JEDEC file. 15-8 LatticeXP2 Configuration Encryption and Security Usage Guide Lattice Semiconductor Figure 15-12. Decryption Flow Programming the Keys1 JEDEC File Programming2 Start Start Erase All Configuration Flash Fuses Enter 64-Bit Key Code Read In 64-Bit Flash Protect Key Enter 128-Bit Key Code Program, Verify Decryption Key Fuses Erase the Configuration Flash, Usercode Enter 64-Bit Key Code Program, Verify Flash Protect Key Fuses Program Configuration Flash Program, Key Lock (Security) Fuse(s) Program Usercode Done Verify Usercode Encrypted JEDEC File Program Done Fuse Notes: 1. Supported on JTAG port. 2. Supported on both JTAG port and slave SPI interface. Program Security Fuse Legend Done Optional step, dependent on user selection. Verifying a Configuration If the Flash is programmed directly, the data is first decrypted and then the FPGA performs a CRC on the data. If all CRCs pass, configuration was successful. If a CRC does not pass, the Done fuse is not programmed. References * TN1141, LatticeXP2 sysCONFIG Usage Guide * Federal Information Processing Standard Publication 197, Nov. 26, 2001. Advanced Encryption Standard (AES) Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com Revision History Date Version February 2007 01.0 Initial release. Change Summary May 2008 01.1 Updated ispLEVER Security Settings screen shot. 15-9 LatticeXP2 Soft Error Detection (SED) Usage Guide September 2009 Technical Note TN1130 Introduction Soft errors occur when high-energy charged particles alter the stored charge in a memory cell in an electronic circuit. The phenomenon first became an issue in DRAM, requiring error detection and correction for large memory systems in high-reliability applications. As device geometries have continued to shrink, the probability of soft errors in SRAM has become significant for some systems. Designers are using a variety of approaches to minimize the effects of soft errors on system behavior. SRAM-based FPGAs store logic configuration data in SRAM cells. As the number and density of SRAM cells in an FPGA increase, the probability that a soft error will alter the programmed logical behavior of the system increases. A number of approaches have been taken to address this issue, but most involve Intellectual Property (IP) cores that the user instantiates into the logic of their design, using valuable resources and possibly affecting design performance. The LatticeXP2 devices have a hardware implemented soft error detector which does not affect performance or heat dissipation of the devices. This document describes the hardware based soft error detect (SED) approach taken by Lattice Semiconductor for LatticeXP2TM FPGAs. SED Overview The SED hardware in the LatticeXP2 devices consists of an access point to FPGA configuration memory, a controller circuit, and a 32-bit register to store the CRC for a given bitstream (see Figure 16-1). The SED hardware reads serial data from the FPGA's configuration memory and calculates a CRC. The data that is read, and the CRC that is calculated, does not include EBR memory or PFUs used as RAM. The calculated CRC is then compared with the expected CRC that was stored in the 32-bit register. If the CRC values match it indicates that there has been no configuration memory corruption, but if the values differ an error signal is generated. SED checking does not impact the performance or operation of the user logic. Figure 16-1. System Block Diagram LatticeXP2 Logic Access SED Control Circuit 32-Bit CRC Register User Logic OSC Config Logic Internal Flash (c) 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 16-1 tn1130_02.0 LatticeXP2 Soft Error Detection Usage Guide Lattice Semiconductor Note that the calculated CRC is based on the particular arrangement of configuration memory for a particular design. Consequently, the expected CRC results cannot be specified until after the design is placed and routed. The ispLEVER(R) bitstream generation software analyzes the configuration of a placed and routed design and updates the 32-bit SED CRC register contents during bitstream generation. The following sections describe the LatticeXP2 SED implementation and flow, along with some sample code to get started with. Basic SED and One-shot SED Modes Basic SED Basic SED checks the CRC for all bits. For Basic SED (SEDBA), the inputs are SEDCLKIN, SEDENABLE, SEDSTART, and SEDFRCERRN. The output signals are SEDCLKOUT, SEDDONE, SEDINPROG, and SEDERR. Once an error is detected the SEDERR signal will stay high. SED supports the following Soft Error Corrections (SEC): "Do Nothing" or on-demand user reconfiguration by pulling the PROGAMN pin low from another device. One-Shot SED The One-Shot SED setting is based on the One-Shot Fuse. The module (SEDBB) has no input ports. The output signals are SEDDONE, SEDINPROG, and SEDERR. At a minimum, the user must connect SEDERR to an I/O pin in order to detect an error. Hardware Description As shown in Figure 16-2, the LatticeXP2 SED hardware has several inputs and outputs that allow the user to control, and monitor, SED behavior. Figure 16-2. Signal Block Diagram SEDCLKOUT SEDENABLE SEDDONE SEDSTART SED Hardware Block SEDFRCERRN SEDINPROG SEDERR SEDCLKIN (From Internal Oscillator) Signal Descriptions Table 16-1. SED Signal Descriptions Signal Name Direction Active Input N/A SEDENABLE Input High SED enable SEDCLKOUT Output N/A Output clock SEDCLKIN SEDSTART Description Clock Input High Start SED cycle SEDINPROG Output High SED cycle is in progress SEDDONE Output High SED cycle is complete Input Low Force an SED error flag Output High SED error flag SEDFRCERRN SEDERR 16-2 LatticeXP2 Soft Error Detection Usage Guide Lattice Semiconductor SEDCLKIN Clock input to the SED hardware. When external SPI configuration is used, this clock is derived from the LatticeXP2's on-chip oscillator. The on-chip oscillator's output goes through a divider to create MCCLK. MCCLK goes through another divider to create SEDCLKIN. The software default for MCCLK is 2.5 MHz, but this can be modified using the MCCLK_FREQ global preference in ispLEVER's pre-map Design Planner (see TN1141, LatticeXP2 sysCONFIG Usage Guide for supported values of MCCLK). It has a range of 2.5 MHz to 66 MHz. The divider for SEDCLKIN can be set to 1, 2, 4, 8, 16 or 32. The default is 1, so the default SEDCLKIN frequency is 2.5 MHz. The divider value can be set using a parameter, see the example code at the end of this document. If internal Flash configuration mode is used, SEDCLKIN can only be set to 3.1 MHz with a divider setting of 1. Note that SEDCLKIN is an internally generated signal, so it should not be included as an input in the user design. See the examples at the end of this document. Also note that while inputs to the SED block are clocked using SEDCLKIN, no attempt has been made to synchronize between clock domains. If this is a concern for a particular design then the designer will need to provide synchronization. OSC_DIV Options: 1, 2, 4, 8, 16 or 32 for external configuration. Only 1 can be selected for internal configuration. The CLK that drives the SED module will be set by MCCLK/OSC_DIV. SEDENABLE Level-sensitive signal which starts SED checking. Table 16-2. SEDENABLE State Description Enables output of SEDCLKOUT, arms SED hardware. SEDCLKOUT Gated version of SEDCLKIN, SEDCLKOUT is gated by SEDENABLE. SEDSTART Active high input to the SED hardware, sampled on the rising edge of SEDCLKIN. Table 16-3. SEDSTART State Description 1 Start error detection. Must be high a minimum of one SEDCLKIN period. 0 No action. SEDFRCERRN Active high input to the SED hardware, sampled on the rising edge of SEDCLKIN. Table 16-4. SEDFRCERRN State Description 1 No action. 0 Forces SEDERR high, simulating an SED error. 16-3 LatticeXP2 Soft Error Detection Usage Guide Lattice Semiconductor SEDINPROG Active high output from the SED hardware, clocked out on the rising edge of SEDCLKOUT. Table 16-5. SEDINPROG State Description 1 SED checking is in progress, goes high on the clock following SEDSTART high. 0 SED checking is not active. SEDDONE Active high output from the SED hardware, clocked out on the rising edge of SEDCLKOUT. Table 16-6. SEDDONE State Description 1 SED checking is complete. Reset by a high on SEDSTART or a low on SEDENABLE. 0 SED checking is not complete. SEDERR Active high output from the SED hardware, clocked out on the rising edge of SEDCLKOUT. Table 16-7. SEDERR State Description 1 SED has detected an error. Reset by SEDENABLE going low. 0 SED has not detected an error. SED Flow Figure 16-3. Timing Diagram SED_ENABLE 6 1 SED_CLK_OUT 2 2 3 3 SED_START SED_INPROG 4 4 5 5 SED_DONE SED_ERR[_PAD] 16-4 LatticeXP2 Soft Error Detection Usage Guide Lattice Semiconductor The general SED flow is as follows. 1. User logic sets SEDENABLE high. This signal may be tied high if desired. 2. User logic sets SEDSTART high. SEDINPROG goes high. If SEDDONE is already high it is driven low. SEDSTART may be tied high to enable continuous SED checking. 3. SED starts reading back data from the configuration SRAM. 4. SED finishes checking. SEDERR is updated, SEDINPROG goes low, and SEDDONE goes high. 5. If SEDERR is driven high there are only two ways to reset it, drive SEDENABLE low or reconfigure the FPGA. 6. SEDENABLE goes low when/if the user specifies, and SED is no longer in use. The user has two choices when an error is detected, ignore the error, and possibly log it, or reconfigure the FPGA. Reconfiguration can be accomplished by driving the PROGRAMN pin low. This can be done by externally connecting a GPIO pin to PROGRAMN. Figure 16-4. Example Schematic VCC LatticeXP2 10K PROGRAMN GPIO Open Drain Output SED Run Time The amount of time needed to perform an SED check depends on the density of the device and the frequency of SEDCLKIN. There will also be some overhead time for calculation, but it is fairly short in comparison. An approximation of the time required can be found by using the following formula: Maxbits / SEDCLKIN = Time Maxbits is in mega-bits and depends on the density of the FPGA (see Table 16-8). SEDCLKIN is frequency in MHz. Time is in seconds For example, for a design using a LatticeXP2 with 5K look-up tables and the SEDCLKIN is the software default of 3.1 MHz: 1.236 Mbits / 3.1 MHz = 398.71 ms In this example, SED checking will take approximately 398.71 ms. Remember that this happens in the background and does not affect user logic performance. Note that the internal oscillator used to generate SEDCLKIN can vary by 30%. 16-5 LatticeXP2 Soft Error Detection Usage Guide Lattice Semiconductor Table 16-8. SED Run Time Device XP2-5K XP2-8K XP2-17K XP2-30K XP2-40K Density 1.236M 1.954M 3.636M 5.964M 8.304M 66MHz 18.7ms 29.6ms 55.1ms 90.4ms 126.2ms 50MHz 24.7ms 39.1ms 72.7ms 119.3ms 166.1ms 3.1MHz 399ms 624ms 1.173s 1.924s 2.679s 2.5MHz 495ms 782ms 1.455s 2.395s 3.325s Sample Code The following simple example code shows how to instantiate the SED. In the example the SED is always on and always running, and the outputs of the SED hardware have been routed to FPGA output pins. Note that the SEDBA primitive is part of ispLEVER 6.1 or later. Basic SED VHDL Example library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity example is port ( sed_done sed_in_prog sed_clk_out sed_out end; : : : : out out out out std_logic; std_logic; std_logic; std_logic); architecture behavioral of example is component SEDBA -- SED component generic (OSC_DIV : integer := 1); -- set SEDCLKIN divider port ( SEDENABLE : in std_logic; SEDSTART : in std_logic; SEDFRCERRN : in std_logic; SEDERR : out std_logic; SEDDONE : out std_logic; SEDINPROG : out std_logic; SEDCLKOUT : out std_logic) ; end component; begin isnt1: SEDBA generic map (OSC_DIV=> "1") port map ( SEDENABLE => '1', -- tied high SEDSTART => '1', -- tied high SEDFRCERRN => '1', -- tied high SEDERR => sed_out, -- wired to an output SEDDONE => sed_done, -- wired to an output SEDINPROG => sed_in_prog, -- wired to an output SEDCLKOUT => sed_clk_out ) ; -- wired to an output end behavioral ; 16-6 LatticeXP2 Soft Error Detection Usage Guide Lattice Semiconductor One Shot SED in VHDL library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity example is port ( sed_done : out std_logic; sed_in_prog : out std_logic; sed_out : out std_logic); end; architecture behavioral of example is component SEDBB -- This is for One Shot SED generic (OSC_DIV : integer := 1); -- set SEDCLKIN divider port ( SEDDONE : out std_logic; SEDINPROG : out std_logic; SEDERR : out std_logic ); end component; begin isnt1: SEDBB generic map (OSC_DIV=> "1") port map ( SEDERR => sed_out, -- wired to an output SEDDONE => sed_done, -- wired to an output SEDINPROG => sed_in_prog); -- wired to an output end behavioral ; 16-7 LatticeXP2 Soft Error Detection Usage Guide Lattice Semiconductor Basic SED Verilog Example module example ( sed_done, sed_in_prog, sed_clk_out, sed_out) ; output output output output sed_done; sed_in_prog; sed_clk_out; sed_out; assign V_hi = 1'b1; assign V_lo = 1'b0; SEDBA #(.OSC_DIV(1)) SED_IP( .SEDENABLE(V_hi), // always high .SEDSTART(V_hi), // always high .SEDFRCERRN(V_hi), // always high .SEDERR(sed_out), // wired to an output .SEDDONE(sed_done), // wired to an output .SEDINPROG(sed_in_prog), // wired to an output .SEDCLKOUT(sed_clk_out)); // wired to an output endmodule 16-8 LatticeXP2 Soft Error Detection Usage Guide Lattice Semiconductor One-Shot SED in Verilog module example ( sed_done, sed_in_prog, sed_clk_out, sed_out) ; output output output output sed_done; sed_in_Prog; sed_clk_out; sed_out; assign V_hi = 1'b1; assign V_lo = 1'b0; SEDBB #(.OSC_DIV(1)) SED_IP( .SEDDONE(sed_done), .SEDINPROG(sed_inprog), .SEDERR(sed_out) ); endmodule module SEDBB (SEDERR, SEDDONE, SEDINPROG); output SEDERR, SEDDONE, SEDINPROG ; endmodule Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com 16-9 LatticeXP2 Soft Error Detection Usage Guide Lattice Semiconductor Revision History Date Version February 2007 01.0 Initial release. Change Summary January 2008 01.1 Updated code in the following sections: Basic SED VHDL Example, One Shot SED in VHDL, Basic SED Verilog Example, One Shot SED in Verilog. January 2008 01.2 Updated OSC_DIV text section. February 2008 01.3 Updated Timing Diagram. March 2008 01.4 Updated SEDCLKIN and OSC_DIV text sections and SEDENABLE table. Updated SED Flow text section. April 2008 01.5 Corrected "SEDFRCERR" to read "SEDFRCERRN". July 2008 01.6 Added footnote to SED Flow timing diagram. August 2008 01.7 Updated SEDCLKIN and OSC_DIV text sections. Updated SED Run Time text section and SED Run Time table. January 2009 01.8 Updated SED Flow text section. Added Example Schematic diagram. January 2009 01.9 Updated Basic SED Verilog Example code. September 2009 02.0 Updated One-Shot SED in Verilog code. Updated Basic SED VHDL Example code. Updated One-Shot SED in VHDL code. 16-10 LatticeXP2 Dual Boot Feature November 2010 Technical Note TN1220 Introduction Lattice is the inventor and the leader in the (ISP) In-System Programming PLD technology. One of the visions and ultimate goal of ISP is the live field upgrade of a mission critical system. Being a mission critical system, the field upgrade process must meet the following criteria. 1. It must be extremely reliable as any form of programming failure is not acceptable. 2. The system must remain functional throughout as even a small interruption is not acceptable including transitioning from the current pattern to the newly updated pattern. 3. Various security features will be required to protect the IP (Intellectual Property) of the mission critical system. With the introduction of the LatticeXP2 Flash based non-volatile FPGA family, Lattice deliver the first and only ISP products with all the critical attributes required to provide the ultimate solution of ISP, reliable and secure live field upgrade of a mission critical system. The critical attributes are: 1. Dual boot feature and Flash Protect to provide the extremely reliable system. 2. Instant-on, Background Programming, and TransFR features provide seamless live field upgrade. 3. Key Protect and Encryption to protect users' Intellectual Property. The block diagram of the LatticeXP2 device shown in Figure 17-1 provides a bird's eye view for the unique co-existence of the Master SPI port with the Slave SPI port. The detail of the LatticeXP2 Slave SPI interface can be found in the document dedicated on the subject. TransFR, the must have feature for the mission critical field upgrade, is available only on the JTAG port. Therefore, the programming activities described in this document will focus on the JTAG port only. Figure 17-1. LatticeXP2 Master SPI and Slave SPI Ports LatticeXP2 CSSPISN/IO SISPI/IO CCLK/IO SOSPI/IO TAG Enable 1 Slave SPI Engine 0 Persistent Fuse. Erase = 1 or On. Program = 0 or Off. TAG Memory Flash JTAG CONFIG. Flash ENABLE Embedded Flash 33 SSPIA SSPIA Primitiv Primitive e User I/O CSSPISN/IO INITN/IO DONE/IO 1 4 UserLogic Logic User The44 Internal Internal The SSPI Nodes Nodes SSPI Fuse Matrix for I/O Routing User I/O User I/O User I/O Any 4 User I/O Configure Chip Select 0 TCK TDI TMS TDO INITN (I/O) DONE (I/O) SISPI (Read Command Out) CCLK (Read Clock Out) Firing Circuit Master SPI Engine DONE Fuse State User I/O Power Cycling User I/O 1 PROGRAMN (Input) CFG1 Pin Setting 0 Master SPI Active Master Clock Oscillator Programming CFG1/IO CFG0 (c) 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 17-1 tn1220_01.0 Lattice Semiconductor LatticeXP2 Dual Boot Feature Complementing its internal Flash configuration memory, the LatticeXP2TM also provides support for inexpensive SPI Flash devices. This provides the ability to use an alternate or backup bitstream, referred to as the "golden" image. The device always attempts to load the primary image from the selected source. Should any unexpected interrupts occur during configuration of the primary image, the LatticeXP2 device will automatically switch sources and configure from the golden image location. Dual Boot Feature One of the biggest risks in the field upgrade applications is disruption during the field grade process. Examples: 1. Power disruption. 2. Communications disruption. 3. Data file corruption. To eliminate the risk completely, the device will automatically switch to load from the second known good (Golden) pattern when the first pattern is corrupted. This is the Dual Boot feature. Thus, the main purpose of the Dual Boot feature is to enhance the reliability of a field upgradeable system. The LatticeXP2 devices are known as non-volatile devices for the device has an embedded Flash block storing the configuration pattern. The advantage of a non-volatile device is the extremely fast instant-on time, made possible by the massive parallel loading from the embedded Flash into the SRAM block of the device. To keep the cost as low as possible, the LatticeXP2 only has enough embedded Flash to store one pattern. To enable the dual boot feature, Lattice designed into the LatticeXP2 device family the popular SPI Flash interface found originally in the LatticeECP/2/3 family of volatile FPGA devices. The SPI Flash device can be used to store the second (Golden) pattern. The basic connections for the two Dual Boot options are shown in Figure 17-2. Figure 17-2. Dual Boot Options PROGRAMN CFGO CFG1 XP2 Golden SPI Flash /S D Q C CCSPIN SISPI SOSPI CCLK INITN PROGRAMN CFGO CFG1 XP2 Flash SPI Flash DONE Option 1: Primary Pattern in Embedded Flash Golden Pattern in SPI Flash /S D Q C CCSPIN SISPI SOSPI CCLK INITN Flash Golden DONE Option 2: Primary Pattern in SPI Flash Golden Pattern in Embedded Flash The Dual Boot feature on the LatticeXP2 devices is designed to be simple for users by carrying out all the necessary procedures on the industry standard JTAG port. Thus, users do not need to learn a new tool or new flows. It also allows users to implement the feature incrementally. The block diagram in Figure 17-3 shows the built-in circuitry, Lattice designed into the FPGA product families, which enable the JTAG port to access the non-JTAG SPI Flash devices. This unique capability also allows the SPI Flash devices to be live field upgradable. The four methods shown in Figure 17-3 are listed below. 1. Use ispVM to program the SPI Flash directly during the board development phase. 2. Use ispVME to program the SPI Flash during the board production phase. 3. Use the CPU to access the SPI Flash directly bypassing the LatticeXP2 device. 17-2 Lattice Semiconductor LatticeXP2 Dual Boot Feature 4. Use off board programming method such as the third party programmers from BPM Microsystems or System General to pre-program the SPI Flash devices and then mount them on board. Methods 3 and 4 are of no interest as far as field upgrade is concerned. Therefore, this document will focus only on methods 1 and 2. Figure 17-3. Four Methods for Programming the SPI Flash Device 1 ispVM System LatticeXP2 SHIFT_DR_TCK SHIFT_DR_TDI SHIFT_DR_CSN SHIFT_DR_TDO isp DO WN LO AD Ca ble TCK TDI TMS TDO 2 CPU Note: The CSSPIN pin is dedicated when the CFGO pin is set to 0 to enable the dual boot feature. JTAG 11 IO IO CSSPIN IO 20 CCLK SISPI CSSPIN SPISO SCLK SI CSN SO SPI Flash 4 PROGRAM_SPI PIO 4G 4 GPIO ispVME 3 SPI Driver CPU Definitions SPI SPI stands for the Serial Peripheral Interface defined originally by Motorola. Master SPI The FPGA device boots itself by acting as the SPI host to clock bitstream data out of the external SPI Flash device. SDM (Self Download Mode) The FPGA device boots itself in a massive parallel fashion from the embedded Flash for instant-on. Erase Write into all the Flash cells state a logical one (1) (a.k.a. open fuse). Program Write into the selected Flash cells state a logical zero (0) (a.k.a. close fuse). Configure Write the pattern into the SRAM fuses of the FPGA device and wake up. It is also known as boot up. Primary Boot Upon power cycling, the FPGA device will load this pattern in first. Only one primary pattern is allowed. Golden Boot The guaranteed good pattern loaded into the FPGA device when booting failure occurs. It is also known as the root boot. Only one Golden boot pattern is allowed. 17-3 Lattice Semiconductor LatticeXP2 Dual Boot Feature Dual Boot The device has two patterns, namely a Primary pattern and a Golden pattern, to choose to load. Refresh The action loads the pattern from a non-volatile source to configure the FPGA device. Bitstream Data File (.BIT File) The configuration data file, for a single FPGA device, in the format that can be loaded directly into the FPGA device to configure the SRAM cells. The file is expressed in binary hex format. The file is not printable. JEDEC File (.JED File) The programming data file as defined by JEDEC 42.1C standard. The programming file is expressed in the ASCII 1 and 0 format. The file is printable. Third party programmers use it to support large volume production programming. TransFR The feature allows users to precisely control the user IO pins (high, low, or tri-state) while the embedded Flash is massively parallel loaded into the SRAM fuses. Security Standard security is the feature that disables the read back operation from the embedded Flash and SRAM blocks. Advanced security refers to the features providing encryption support and various Keys and Locks for protecting the Embedded Flash block. SED CRC Soft Error Detection (SED) by calculating the CRC value of the value of the SRAM fuses. Lattice implements the feature by using a 32-bit polynomial. One Shot SED After each boot from the embedded Flash, this feature enables the SED CRC feature automatically and immediately checking the integrity of the embedded Flash content. Background Mode (User Mode) The FPGA device shall remain fully operational as governed by the fuse pattern residing in the SRAM fuse module of the FPGA device at the time while programming activities being carried out on the FPGA device or the peripheral device (SPI Flash device) attached to it. This mode is the most critical attributes of the live field upgrade feature that can be found only on Lattice's FPGA devices. Direct Mode (IEEE 1532 Access Modal State) The FPGA device shall be removed from the governing of the fuse pattern residing in the SRAM fuse module, or so to say, put to sleep while programming activities being carried out on the FPGA device or on the peripheral device (SPI Flash device) attached to it. The IOs are either tri-stated or held statically while in this mode. Lack of a better term, Lattice uses it to contrast against the background mode. All PLD devices support this mode. Purpose It has been the ultimate goal for the In-System Programming revolution championed by Lattice since 1990 to provide a reliable and continuous live field upgradable system. The TransFR feature designed into Lattice devices since 2000 brings Lattice closer to the ultimate goal. With the introduction of the dual boot feature and the advanced security feature in 2007, the ultimate goal is achieved. 17-4 Lattice Semiconductor LatticeXP2 Dual Boot Feature This document provides detail technical explanation of the dual boot feature in the LatticeXP2 device family. The application details for using ispVM and ispVME to support dual boot feature during the different applications is as follows: 1. Use ispVM or ispVME to program the bitstream into the SPI Flash device 2. Use ispVM or ispVME to program the JEDEC file into the LatticeXP2 device. The application of the LatticeXP2 Advanced Security feature, TransFR feature, and Mission Critical Field Upgrade are briefly mentioned in this document. The details can be found in the LatticeXP2 Advanced Security Configuration, LatticeXP2 TransFR Feature, and LatticeXP2 Mission Critical Field Upgrade Usage Guides, respectively. Contact Lattice Applications for the other documents if required. Note: The LatticeXP2 devices only support encrypted JEDEC files, which target the embedded Flash of the LatticeXP2 devices. Figure 17-4. LatticeXP2 FPGA Dual Boot Feature Flow Diagram External SPI Flash Block 0 (0x000000) Dual Boot Flow Golden Pattern Start Unused Area Continue Until Entire Bitstream Loaded. Select the SPI Flash. Sen Read Opcode. Send block 0 Address. No Done Fuse Programmed? No Yes CRC OK? Yes Fail Embedded Flash Holding the Current New Pattern Load Current or New Pattern In Download from Embedded Flash Wake-Up Pass Resource The minimum SPI Flash density required to support the dual boot feature is listed in Table 17-1. Table 17-1. Required SPI Flash Device Size Device Name XP2-5 Bitstream Size Minimum SPI Flash Density M bits M bits 1.28 2 XP2-8 1.99 2 XP2-17 3.55 4 XP2-30 5.79 8 XP2-40 8.04 16 17-5 Lattice Semiconductor LatticeXP2 Dual Boot Feature Dual Boot Mode The LatticeXP2 Dual Boot sysCONFIGTM mode is selected using CFG pin settings. ists the sysCONFIG modes supported by the LatticeXP2 device family. Figure 17-1 illustrates the SPI Flash hardware connections. Table 17-2. LatticeXP2 sysCONFIG Modes CFG0 CFG1 Configuration Mode Primary Boot Source Secondary Boot Source 0 0 Dual Boot External SPI Flash Internal Flash 0 1 Dual Boot Internal Flash External SPI Flash 1 X Self Download Mode (SDM) Internal Flash None Figure 17-5. LatticeXP2 Hardware Connections to SPI Flash LatticeXP2 SPI Serial Flash CCSPIN SISPI Primary or Golden Image SOSPI CCLK Internal Flash Memory Internal logic is used to detect a configuration failure from the primary source and provides the ability to reattempt configuration from the secondary source. This sequence is used when the LatticeXP2 is set to dual boot mode and configuration is initiated. Configuration initiates in dual boot mode when any of the following events occur: * The device is powered-up with all supplies reaching their required minimum values. * The PROGRAMN pin is toggled. * The REFRESH command is issued via the ispJTAGTM port. Should configuration from both primary and golden images in dual boot mode fail, the INITN pin will be driven low and the configuration process will halt. Lattice strongly recommends using the embedded Flash as the first (Primary) boot to take full advantage of the features only embedded Flash can offer, for example fast instant-on time, standard or advance security, and TransFR. The dual boot flow described in this document focus only on setting CFG[0:1] to [01], respectively, to select the embedded Flash as the first boot. This flow is triggered either by power cycling or toggle the PROGRAMN pin. A. When the dual boot mode is selected by setting the CFG0 to low (0), the device checks the CFG1 pin first to decide the source of the first boot. It the CFG1 pin is high (1), the device will check the Flash done fuse immediately. 1. Done Fuse Programmed If the Done fuse is programmed, then the embedded Flash must have been programmed with a valid pat- 17-6 Lattice Semiconductor LatticeXP2 Dual Boot Feature tern. The device will boot from the embedded Flash. If it is desirable to check if the boot from the embedded Flash is error free, the One Shot SED feature can be used to confirm. Note: The devices carry out the one shot SED by reading the SRAM fuses and calculate the CRC value in Background mode. 2. Done Fuse Not Programmed (aka Erased) If the Done fuse is erased, then the embedded Flash must have an invalid pattern. The device will activate the Master SPI engine to load the data from the external SPI Flash device. The standard protocol of the Master SPI engine is to ignore the first 128 bits of data from the SPI Flash device, and then begins looking for the preamble code 0xBDB3. There are two possible failures. a. The preamble code is not detected within ~16K clocks. This will happen if the SPI Flash device is blank. This is known as a time out failure. b. The CRC value calculated by the Master SPI engine of the device does not match with the one embedded in the bitstream. This means the bitstream is corrupted. If there is a failure, the device drives the INITN pin low to indicate a failure. Otherwise, the device wakes up and functions. Note: The INITN pin is functional only when the Master SPI engine is active. Otherwise, it has no function. B. If the CFG1 pin is set to low (0), then the device will activate the Master SPI engine to boot the first pattern in. If failure occurs, as described above in 2a or 2b, the device will drive the INITN pin low and then high, and then check if the Flash-Done fuse is programmed. If the Done fuse is programmed, the device will perform the SDM, drive the DONE pin high, and the device wakes up. If the Done fuse is not programmed, then the device stops configuring and leaves the DONE pin low to indicate configuration did not complete. From the dual boot flow described above, it should become obvious why the Done fuse is always the very first fuse to be erased when performing an erase operation. Also, it is the last Flash fuse to be programmed when programming embedded Flash in LatticeXP2 devices. Critical Points 1. Check the maximum read frequency supported by the SPI Flash devices. Do not set the CCLK frequency in the bitstream beyond the maximum as specified on the data sheet of the SPI Flash devices. Reason: All SPI Flash devices support Slow Read command (0x03) and Fast Read command (0x0B). The LatticeXP2 family only supports the Slow Read command. When the device is powered up, the CCLK frequency is the silicon default, which is approximately 3.1 MHz. After the LatticeXP2 starts loading the bitstream, the CCLK frequency is updated to user's selected frequency. If the selected CCLK frequency exceeds maximum frequency supported by the SPI Flash device, the LatticeXP2 may not configure. Work-around Solution: When using the ispUFW to convert the JEDEC file into a bitstream file, select a CCLK frequency setting that meets the specifications of the target SPI Flash. 2. If the JTAG port has been used, do not toggle the PROGRAMN pin to reboot unless the board has been power cycled. (Note 2 of the Signal Descriptions Table of DS1009, LatticeXP2 Family Data Sheet, shown in Figure 18, describes this restriction.) 17-7 Lattice Semiconductor LatticeXP2 Dual Boot Feature Figure 18. LatticeXP2 Datasheet Note Reason: The JTAG port is designed to be all powerful so that even the PROGRAMN pin is disabled to prevent the pin from interrupting the JTAG port operations. Work-around Solution: Use the JTAG Refresh instruction to reboot instead of toggling the PROGRAMN pin. 3. When the standard security fuse is set, use Background Mode to reprogram the LatticeXP2 device will fail verification. Reason: The function of the standard security fuse is for disabling the read back operation. Whenever powering up the LatticeXP2 device, the security latch latches in the security fuse state to protect the fuse pattern residing in it. The Background Mode programming by design can not alter or corrupt the current pattern residing in the SRAM fuse module including the security latches. In other word, the security latch can't be cleared by Background operations. As a consequence, the security latch will block all subsequent Background read back operation. Work-around Solutions: A. Skip verification on Background Mode programming. B. Use Encryption Background Programming. 17-8 Lattice Semiconductor LatticeXP2 Dual Boot Feature Programming Procedures Part 1: Program the Golden Pattern into the SPI Flash Devices The SPI Flash device stores the Golden Pattern for the LatticeXP2 device. The Master SPI port requires the Golden Pattern to be in a bitstream format. The bitstream format is exactly the same as the LatticeECP/2/3 FPGA family of devices. The bitstream format can be found in the reference section at the end of this document. For LatticeXP2 FPGA products, Lattice's design software, ispLEVER(R), only generates a JEDEC file. The Universal File Writer (ispUFW(R)) utility shipped with the ispVM(R) System can be used to convert the LatticeXP2 JEDEC file into the bitstream file for the Master SPI port. The procedure is shown in Figure 17-1and Table 17-3. Figure 17-1. Using the ispUFW to Convert a JEDEC File to a Bitstream 1 6 2 3 4 5 Table 17-3. Procedure for Converting a JEDEC File to a Bitstream using the ispUFW Steps Description 1 Launch the UFW on ispVM. 2 Select the bitstream file as the output format. 3 Browse for the JEDEC input file name. The device name will be extracted from the JEDEC file. 4 Browse or enter the output file name. 17-9 Lattice Semiconductor LatticeXP2 Dual Boot Feature Table 17-3. Procedure for Converting a JEDEC File to a Bitstream using the ispUFW (Continued) Steps Description 5 This is optional. The default is 2.5 MHz. The maximum frequency recommended is 15 MHz due to the +/- 30% variance of the clock oscillator of the LatticeXP2 devices and the typical slow read (opcode = 0x03) frequency is 20 MHz maximum of the SPI Flash devices. The other settings following the Frequency shall be left to default to as shown. Just for completeness, the purpose of the other settings are described below: Ignore ID Code = Insert the LatticeXP2 device 32-bit Device ID checking into the bitstream. Default = do not check IDCODE. Program Secure = Insert the program security fuse command into the bitstream. Default = per the JEDEC file G field setting. Disable CRC Calculation = Remove CRC checking in the bitstream. OFF = the bitstream has CRC checking. (Note: The LatticeXP2 devices use the CRC value to check against bitstream corruption for configuration pass/fail decision. User must not change this setting when generating the final customer ready bitstream. These features are provided to aid board development and debugging.) 6 Click the file generation button to generate the bitstream. Once the bitstream is generated, follow the procedures shown in Figure 17-2 and Table 17-4 to program the bitstream into the SPI Flash device on ispVM System. ispVM System supports quite many useful SPI Flash operations. Most operations are intuitively understood by users thus do not require detail description in this document. After the SPI Flash is programmed with a valid bitstream, and if the LatticeXP2 device is not yet programmed, using JTAG refresh or power cycling the LatticeXP2 device will activate the Master SPI port to boot from the SPI Flash device. The PROGRAMN pin will work as long as the JTAG port has not been used. If the JTAG port has been used, power cycle the LatticeXP2 device will re-enable the PROGRAMN pin. Please refer to Critical Point 2 above for more details. The mechanical detail on the JTAG port in the LatticeXP2 device serving as a SPI host to access the external SPI Flash devices can be found in the reference section at the end of this document. Figure 17-2. Using ispVM to Program a Bitstream into the SPI Flash Device 9 10 8 1 7 5 6 3 2 4 17-10 Lattice Semiconductor LatticeXP2 Dual Boot Feature Table 17-4. Procedure for Program a Bitstream into the SPI Flash Device using ispVM Steps Description 1 Scan or select the LatticeXP2 device. 2 Select the SPI Flash Programming under the Device Access Options. 3 Select the SPI Flash operation from the operation list: (Note: Due to the operations describe here are all carried out on the JTAG port, as previously noted, the PROGRAMN pin function is disabled by any activities on the JTAG port, power cycling the LatticeXP2 device is the only way to re-enable the PROGRAMN pin.) SPI Flash Operation Comments Erase, Program, Verify This is a Direct Mode operation. The LatticeXP2 device will be forced into an erased state, by clearing (erase) the SRAM fuses, before and while programming the SPI Flash device. The purpose is to set the persistent fuse to be on to gain unconditional access to the SPI Flash device through the JTAG port. Background Erase, Program, Verify This is a Background Mode operation. The LatticeXP2 device can remain functional while programming the SPI Flash device. However, the persistent fuse in the LatticeXP2 device must be set to on first to use this operation. If the persistent fuse is not set to be on or the LatticeXP2 device is not blank, this operation will fail ID check. In that case, must use the operation above instead. Erase, Program, Verify, Refresh This Direct Mode operation is provided as a work around for the PROGRAMN pin disabled by the JTAG port activities. Must use this operation if need to boot the bitstream into the LatticeXP2 device immediately after completing the SPI Flash programming. Refresh = the JTAG refresh instruction which has the effect as toggling the PROGRAMN pin. Program (Erase, Program) This Direct Mode operation will erase and program the SPI Flash device in without verification in Direct Mode. The VME file size of this operation is half that of with verification. User might have no choice but use this operation when the EPROM size storing the VME file is too small to include verification. Background Program (Background Erase, Program) Same as above except it is conducted in Background Mode. The persistent fuse in the LatticeXP2 device must be on for this operation to work. Calculate File Size Checksum This Direct Mode operation will calculate the fuse checksum in the SPI Flash device per the starting address and ending address after browsing in the bitstream file at step 6 below. Example: The XP2-5E bitstream occupy sector 0, 1, and 2, or three sectors total. The checksum is calculated by reading the fuse data out from those three occupied sectors. Calculate Device Size Checksum This Direct Mode operation will calculate the fuse checksum of the entire SPI Flash device. Example: The 2Mb SPI Flash device has four sectors total. The checksum is calculated by reading out fuse data from all four sectors Scan SPI Flash Device This Direct Mode operation will scan SPI Flash device against the Lattice SPI Flash device database. If there is a match, then it shows what the device is on the message window for user to enter on step 6. If it is not in the database, then it returns an unknown device. User will need to find out the SPI Flash device name manually then select accordingly at step 6. 4 Launch the SPI Flash device menu. 5 Select the SPI Flash device. 6 Browse for the bitstream file. Note: Do not change the starting address from sector 0. The LatticeXP2 device will boot from sector 0. 7 Click OK to close the SPI Flash device menu. 8 Click OK to close the device selection menu. 9 Click GO to program the SPI Flash device. For embedded programming, skip this step. Go to step 10 to generate the VME file instead. 10 This is optional. For embedded programming, use the VME file generator to generate the VME file first then run the VME file to program the SPI Flash device then port the ispVME driver onto the embedded system. 17-11 Lattice Semiconductor LatticeXP2 Dual Boot Feature Part 2: Program the Primary Pattern into LatticeXP2 Embedded Flash Follow the procedures shown in Figure 17-3 and Table 17-5 too program the JEDEC file into the LatticeXP2 embedded Flash using the ispVM System. There is absolutely no difference between programming the LatticeXP2 device for standard single boot and dual boot applications. For live field upgrade of a mission critical application, Background Mode programming is strongly recommended. For more details on Background Mode programming mode for mission critical application, please refer to the LatticeXP2 Mission Critical Field Upgrade Usage Guide. Contact Lattice Applications for the document if required. Once the embedded Flash and Done fuse is programmed, it can be difficult to configure the LatticeXP2 device from the external SPI Flash device. There are two methods that can be used to test the dual boot feature does work. 1. Drive the CFG1 pin to 0. This will cause the bitstream in the SPI Flash to be the Primary pattern. 2. Use the ERASE_DONE command to erase only the Done fuse of the LatticeXP2 Embedded Flash. The only draw back of this approach is that entire LatticeXP2 Embedded Flash will need to be re-programmed. Simply programming the Done fuse will not work. Figure 17-3. Using ispVM to Program a JEDEC into the Embedded Flash 6 7 5 1 Operation List of Interest 4 FLASH Erase,Program,Verify FLASH Erase,Program,Verify,Secure FLASH Erase,Program,Verify,Refresh FLASH Verify Only 3 FLASH Erase Only FLASH Read Status Register 2 FLASH Read DONE bit FLASH Refresh 17-12 Lattice Semiconductor LatticeXP2 Dual Boot Feature Table 17-5. Procedure for Program a JEDEC File into the LatticeXP2 using ispVM Steps Description 1 Scan or select the LatticeXP2 device. 2 Select the Flash Programming Mode under the Device Access Options. 3 Select the Flash Programming operation from the operation list: (Note: Due to the operations describe here are all carried out on the JTAG port, as previously noted, the PROGRAMN pin function is disabled by any activities on the JTAG port, power cycling the LatticeXP2 device is the only way to re-enable the PROGRAMN pin.) Flash Background Operation Comments FLASH Erase,Program,Verify This is a Direct Mode operation. The LatticeXP2 device will be forced into an erased state, by clearing (erase) the SRAM fuses, before and while programming the embedded Flash. A post programming verification of the Flash fuses is performed. If all of the Flash fuses match the data in the JEDEC file, the Flash Done fuse is programmed. The pattern from embedded Flash device into the SRAM fuses using the JTAG ISC_DISABLE instructions at the end of the operation. FLASH Erase,Program,Verify,Secure This is a Direct Mode operation. The LatticeXP2 device will be forced into an erased state, by clearing (erase) the SRAM fuses, before and while programming the embedded Flash. A post programming verification of the Flash fuses is performed. If all of the Flash fuses match the data in the JEDEC file, the Flash Security and Done fuses are programmed. The pattern from embedded Flash device into the SRAM fuses using the JTAG ISC_DISABLE instructions at the end of the operation. FLASH Erase,Program,Verify,Refresh This is a Direct Mode operation. The LatticeXP2 device will be forced into an erased state, by clearing (erase) the SRAM fuses, before and while programming the embedded Flash. A post programming verification of the Flash fuses is performed. If all of the Flash fuses match the data in the JEDEC file, the Flash Done fuse is programmed. This operation loads the pattern from embedded Flash device into the SRAM fuses using the JTAG Refresh instruction. FLASH Verify Only This is a Direct Mode operation. The LatticeXP2 device will be forced into an erased state, by clearing (erase) the SRAM fuses, before and while programming the embedded Flash. A verification of the Flash fuses is performed. If all of the Flash fuses match the data in the JEDEC file, the Flash Done fuse is programmed. The pattern from embedded Flash device into the SRAM fuses using the JTAG ISC_DISABLE instructions at the end of the operation. FLASH Erase Only This is a Direct Mode operation. The LatticeXP2 device will be forced into an erased state, by clearing (erase) the SRAM fuses, before and while erasing the embedded Flash. Since the Flash Done bit is erased, the Flash to SRAM transfer does not happen, and the device remains in the unprogrammed mode. If dual boot configuration mode is selected, and the golden is located in the external SPI Flash, the device will configure from the golden pattern contained in the external SPI Flash device. FLASH Read Status Register This is a Direct Mode operation. The LatticeXP2 device will enter programming mode while the device Status Register is read and displayed. FLASH Read DONE bit This is a Direct Mode operation. The LatticeXP2 device will enter programming mode while the Flash Done Bit is read and displayed. FLASH Refresh This is a Direct Mode operation. This operation loads the pattern from embedded Flash device into the SRAM fuses using the JTAG Refresh instruction. The LatticeXP2 device will be forced into an erased state, by clearing (erase) the SRAM fuses, before and during the Flash to SRAM transfer. 17-13 Lattice Semiconductor LatticeXP2 Dual Boot Feature Table 17-5. Procedure for Program a JEDEC File into the LatticeXP2 using ispVM (Continued) Steps Description 4 Browse for the JEDEC file. 5 Click OK to close the device selection menu. 6 Click GO to program the LatticeXP2 embedded Flash. For embedded programming, skip this step. Go to step 7 to generate the VME file instead. 7 This is optional. For embedded programming, use the VME file generator to generate the VME file first then run the VME file to program the LatticeXP2 embedded Flash device then port the ispVME driver onto the embedded system. Reference Material LatticeXP2 Bitstream File Format Table 17-6 shows the format of a LatticeXP2 bitstream. The bitstream consists of a comment field, a header, the preamble, and the configuration setup, and data. Table 17-6. LatticeXP2 Bitstream File Forma Frame Comments Header Contents (Comment String) 1111...1111 1011110110110011 Description ASCII Comment (Argument) String and Terminator 16 Dummy bits 16-bit Standard Bitstream Preamble (0xBDB3) Verify ID 64 bits of command and data Control Register 0 64 bits of command and data Reset Address 32 bits of command and data Write Increment 32 bits of command and data Data 0 Data, 16-bit CRC, and Stop bits Data 1 Data, 16-bit CRC, and Stop bits ... ... Data n-1 End ... Data, 16-bit CRC, and Stop bits 1111...1111 Usercode Terminator bits and 16-bit CRC 64 bits of command and data SED CRC 64 bits of command and data Program Security 32 bits of command and data Program Done 32 bits of command and data, 16-bit CRC NOOP 1111...1111 64 bits of NOOP data End 1111...1111 32-bit Terminator (all ones) Note: The data in this table is intended for reference only. Implement SPI Flash Programming on ispVM System The LatticeECP2/3 and LatticeXP2 families of FPGA devices are designed to support a JTAG instruction, PROGRAM_SPI, which when executed, will effectively connect the four SPI interface signals of SPI Flash devices to four JTAG port signals. 17-14 Lattice Semiconductor LatticeXP2 Dual Boot Feature ispVM System and ispVME takes care of the detail to program the SPI Flash devices via the JTAG port. The detail task is shown in the waveform diagram on on Table 17-7. Description of the Hare-wired JTAG SPI Flash Programming IP Block # Title Description 1 Reset JTAG Port The standard method to set the JTAG state machine to a known state. 2 Send Instruction Shift in the PROGRAM_SPI instruction (OPCODE = 0x0X). Indicate bit 0 first shifting direction. 3 Connect The 4-pin JTAG port is connected to the 4-pin SPI interface. SLCK following TCK indicate connection is made. 4 Repeat Loop around to erase by sectors and programming by pages. 5 Shift Data Send in the command to erase a sector or shift in one page of programming data. The FPGA respond by driving the CSSPIN pin to low to gate on SCLK, SPID0, and SISPI. 6 Burn Time Delay Drive the CSSPIN to high to command the SPI Flash device to start the erase or programming action. Wait for the required erase or programming delay time then poll the complete status. Consult the SPI Flash datasheet for the polling method required. Figure 17-4. Waveform Diagram of the Hare-wired JTAG SPI Flash Programming IP 1 ??? ??? TLR TCK TMS 5 2 RTI DRS IRS UIR TLR RTICTRDRSSTRIRSE1IR CIR E1IR 4 3 RTI DRS SIR UIRCDRRTI 7 SDR CDR E1DR E2DR UDR DRS SDR PDR E1DR PDR E2DR DRS IRS TLR N-1 TDI TDO CCSPIN N-1 SCLK SIPI SPISO 5 6 References * Lattice Technical Note TN1087, Minimizing System Interruption During Configuration Using TransFR Technology * Lattice Technical Note TN1141, LatticeXP2 sysCONFIG Usage Guide * Lattice Technical Note TN1142, LatticeXP2 Configuration Encryption and Security Usage Guide 17-15 Lattice Semiconductor LatticeXP2 Dual Boot Feature Technical Support Assistance Hotline:1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com Revision History Date Version November 2010 01.0 Change Summary Initial release. 17-16 LatticeXP2 Hardware Checklist May 2011 Technical Note TN1143 Introduction Starting a complex system with a large FPGA hardware design requires that the FPGA designer pay attention to the critical hardware implementation to increase the chances of success for the hardware. This technical note systematically steps through these critical hardware implementation items relative to the LatticeXP2TM device. LatticeXP2 is the third-generation non-volatile FPGA from Lattice with on-chip Flash to store the configuration. The device family consists of FPGA LUT densities ranging from 5K to 40K. This technical note assumes that the reader is familiar with the LatticeXP2 device features as described in the LatticeXP2 Family Data Sheet. The critical hardware areas covered in this technical note are: * Power supplies as they related to the LatticeXP2 supply rails and how to connect them to the PCB and the associated system * Configuration and how to connect the configuration mode selection for proper power up configuration * Device I/O interface and critical signals Power Supply The VCC and VCCAUX power supplies determine the LatticeXP2 internal "power good" condition. In addition to the two power supplies, there are VCCIO0-7, VCCPLL and VCCJ supplies that power the I/O banks, PLL and JTAG port. All power supplies are required for the proper device operation but since VCC and VCCAUX determine the device power-on condition, it is recommended to have one of these supplies be the final power supply to power up the LatticeXP2 device after all other power supplies are stable. Table 18-1 shows the power supplies and the appropriate voltage levels for each supply. Table 18-1. Power Supply Description and Voltage Levels Supply Voltage (Typ.) Description VCC 1.2V Core power supply. A typical VCC device internal power up and power down trip point is between 0.7V and 0.9V. VCCAUX 3.3V Auxiliary power supply. A 3.3V supply that provides an internal reference to the input buffers. A typical VCCAUX device internal power up and power down trip point is between 2.0V and 2.8V. VCCPLL 3.3V Power supply for PLL. VCCIO0-7 1.2V to 3.3V I/O power supply. There are eight banks of I/Os and each bank has its own supply VCCIO0 to VCCIO7. VCCJ 1.2V to 3.3V JTAG power supply for TAP controller port. Power Supply Sequencing There is no specific power sequencing requirement for the LatticeXP2 device family. If the user's system has the option to design for power sequencing, a practical sequencing to keep in mind is based on the fact that VCC and VCCAUX determine when the core powers up. In order insure proper functional behavior, it is desirable to bring up the VCCIO, VCCJ and VCCPLL first in any order and bring up VCC first and VCCAUX next in a sequential order. Power sequencing considerations should also consider that common supplies generally are tied together to the same rail. For example, if there is a 3.3V VCCIO, it should be tied to the same supply as the 3.3V rail for VCCAUX. LatticeXP2 is able to tolerate any order of power sequencing without causing any high current leakage paths during power up. (c) 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 18-1 tn1143_01.2 Lattice Semiconductor LatticeXP2 Hardware Checklist Power Supply Ramp Similar to the power supply sequencing, there is no specific requirement for the LatticeXP2 but care must be given to the power supply ramp times in a reasonable range. The reasonable range is defined by the majority of the power supply related device test data taken as part of the device characterization. The fast end of the spectrum is defined to be 100s for the supply to transition from zero volts to minimum supply voltage level. The slow end of the spectrum is defined to be 100ms for the supply to transition from zero volts to minimum supply voltage. These ranges should be used as general guidelines for the system design consideration. Power Estimation Once the LatticeXP2 device density, package and logic implementation is decided, power estimation for the system environment should be determined based on the software Power Calculator provided as part of ispLEVER(R) design tool. The power estimation should keep two specific goals in mind. 1. Power supply budgeting should be considered based on the maximum of the power-up in-rush current, configuration current or maximum DC and AC current for given system environmental condition. 2. The ability for the system environment and LatticeXP2 device packaging to be able to support the specified maximum operating junction temperature. By determining these two criteria, system design planning can take the LatticeXP2 power requirements into consideration early in the design phase. Configuration There are two options to configure the LatticeXP2 devices. The obvious and most common method is using the onchip Flash memory. This method is called the Self Download Mode or SDM. The SDM is determined by the CFG0 signal. CFG0 needs to be pulled high in order to boot the device from the on-chip flash memory. External pull-up resistor highly recommended pulling up the CFG0 signal to the 3.3V supply rail. Table 18-2 shows the proper CFG bit setting. Table 18-2. Configuration Mode Selection Configuration Mode CFG1 CFG0 Description SPI Flash Boot 0 0 Master SPI Boot first then embedded Flash. Embedded Flash Boot 1 0 Embedded flash boot first then external SPI Flash. Self Download Mode (SDM) X 1 SDM only. The SPI configuration port resides in I/O bank 7. Accordingly, the VCCIO7 must match the supply rail of the SPI Flash. For example, if the external SPI Flash uses 3.3V rail, VCCIO7 must be tied to 3.3V supply rail as well. There are several dual-purpose pins that can be used as general-purpose I/O pins when not used for configuration. Table 18-3 lists these dual-purpose pins. When CFGx is set to one of the two external SPI flash options and persistence is OFF, the dual-purpose configuration pins will become general-purpose I/O pins after configuration. These pins should be used only when they are not used for configuration. When used for configuration, persistence should be ON, to dedicate these pins for configuration. In order to insure proper configuration, it is recommended to use external resistors for the configuration pins. The CFG0 must have external resistor for any configuration mode. When CFG0=0, CFG1, PROGRAMN, INITN and DONE pins must have the appropriate external pull-up or pulldown resistors. 18-2 Lattice Semiconductor LatticeXP2 Hardware Checklist Table 18-3. Configuration Pin Descriptions Pin Name I/O Type Pin Type CFG0 Input, weak pull-up Dedicated CFG1 Input, weak pull-up Dual-Purpose PROGRAMN Input, weak pull-up Dual-Purpose INITN Bi-Directional Open Drain, weak pull-up Dual-Purpose DONE Bi-Directional Open Drain with weak pull-up or Active Drive Dual-Purpose CCLK Input or Output Dual-Purpose SISPI Input or Output Dual-Purpose SOSPI Input or Output Dual-Purpose CSSPISN Input, weak pull-up Dual-Purpose CSSPIN Output, tri-state, weak pull-up Dual-Purpose Description FPGA configuration mode selection FPGA Configuration control and status signals Configuration clock SPI control and data signals JTAG Interface The JTAG interface pins are referenced to VCCJ. Typically, JTAG pins are referenced to 3.3V supply. VCCJ can support supplies from 1.2V to 3.3V. In cases where VCCJ is connected to supplies other than 3.3V, validate that the JTAG interface cable or tester can support I/O interface with the same I/O voltage standard. I/O Interface and Critical Pins There are eight I/O banks on every LatticeXP2 device. I/O Bank 7 contains the configuration pins and as such, the configuration requirements should have the highest priority to determine the supply voltage levels for VCCIO7. I/O Pin Assignments Around VCCPLL The VCCPLL provides a "quiet" supply for the internal PLLs. For the best PLL jitter performance, careful pin assignment must keep away the "noisy" I/O pins away from the BGA ball location that are identified as sensitive pins as shown in Figure 18-1. In this case the sensitive pins would be one of the VCCPLL supply pins. The "noisy" I/O pins are generally defined to have the highest switching frequency, highest VCCIO standard and fastest output slew rates. For example, using the Figure 18-1 3x3 and 5x5 grid of ball locations, one can identify the "keep out" ball locations for the potentially "noisy" signals. Note: In fpBGA and ftBGA packages, VCCPLL is not provided from its own pins; it is connected to the VCCAUX pins. In this case, this discussion applies to the VCCAUX pins. Figure 18-1. "Quiet" Pin Assignment Consideration for BGA Package 5x5 5x5 5x5 5x5 5x5 5x5 3x3 3x3 3x3 5x5 5x5 3x3 Sensitive Pin 3x3 5x5 5x5 3x3 3x3 3x3 5x5 5x5 5x5 5x5 5x5 5x5 18-3 Lattice Semiconductor LatticeXP2 Hardware Checklist DDR/DDR2 Memory Interface Pin Assignments The DDR Memory interface on the LatticeXP2 device family is provided with a pre-engineered I/O register along with the precision I/O DLL timing control. There are two I/O DLL specifically assigned to the two halves of the device. One I/O DLL supports I/O banks 1, 2, 3 and 4; another I/O DLL supports I/O banks 0, 5, 6 and 7. In addition to the I/O DLL assignments, there are pre-defined data strobes (DQS) signals that can support a span of I/O pins as part of the memory data lanes. When assigning DDR memory interface I/O pins, the FPGA designer must insure that there is enough I/O pins to assign DDR memory data pins for each of the assigned DQS signals. True-LVDS Output Pin Assignments True-LVDS outputs are available on 50% of the I/O pins on the left and right sides of the device. The left and right side I/O banks are banks 2, 3, 6 and 7. When using the LVDS outputs, a 2.5V supply needs to be connected to these VCCIO supply rails. HSTL and SSTL Pin Assignments These externally referenced I/O standards require an external reference voltage. Each of the LatticeXP2 device family I/O banks allows up to two pre-defined VREF pins. The VREF pin(s) should get the highest priority for pin assignment. PCI Clamp Pin Assignment PCI clamps are available on the top and bottom sides of the device. When the system design calls for PCI clamp, those pins should be assigned to I/O banks 0, 1, 4 and 5. For the clamp characteristic, refer to the IBIS buffer models either on the Lattice website at www.latticesemi.com or in the ispLEVER design tool. Test Output Enable (TOE) TOE signal is used to tri-state all I/O pins and override the functional outputs for board level test. It is recommended to have a pull-up resistor to make sure that when not in use, the TOE will not interfere with the normal functionality of the I/O pins. 18-4 Lattice Semiconductor LatticeXP2 Hardware Checklist Checklist LatticeXP2 Hardware Checklist Item 1 1.1 Core Supply VCC @1.2V 1.2 Auxiliary Supply VCCAUX @ 3.3V 1.3 PLL Supply VCCPLL @ 3.3V 1.4 JTAG Supply VCCJ from 1.2V to 3.3V 1.5 I/O Supply VCCIO0-7 from 1.2V to 3.3V 1.6 Supply Sequencing considerations 1.7 Supply Ramp considerations 1.8 Power Estimation 2 OK Configuration 2.1 Consistency of VCCIO7 Supply if external SPI Flash is used 2.2 Configuration control and status selections 2.2.1 Pull-up or Pull-down on CFG02 2.2.2 Pull-up or Pull-down on CFG11, 2 2.2.3 Pull-up on PROGRAMN1, 3, INITN1, 3, DONE1, 3, TOE2 2.2.4 2.3 3 N/A Power Supply Pull-down on TCK JTAG Supply and default logic levels I/O Pin Assignment 3.1 I/O pin assignments around VCCPLL 3.2 DDR Memory pin assignment considerations 3.3 True-LVDS pin assignment considerations 3.4 HSTL and SSTL pin assignment considerations 3.5 PCI clamp requirement considerations 1. Only necessary when CFG1=0. 2. CFG0, CFG1 and TOE pins are internally linked to the VCC core voltage and can be pulled up to either VCC core or 3.3V. 3. When used, PROGRAMN, INITN, and DONE pulled up to same voltage as VCCIO7. Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com Revision History Date Version June 2007 01.0 Initial release. Change Summary March 2011 01.1 Added note to "I/O Pin Assignments Around VCCPLL" text section. May 2011 01.2 Updated Checklist table footnotes. 18-5 Section III. LatticeXP2 Family Handbook Revision History LatticeXP2 Family Handbook Revision History January 2012 Handbook HB1004 Revision History Date Handbook Revison Number May 2007 01.1 Initial release. Change Summary July 2007 01.2 Technical note TN1137 updated to version 01.1. September 2007 01.3 LatticeXP2 Family Data Sheet updated to version 01.2. January 2008 01.4 Technical note TN1130 updated to version 01.1. Technical note TN1137 updated to version 01.3. Technical note TN1141 updated to version 01.2. February 2008 01.5 LatticeXP2 Family Data Sheet updated to version 01.3. Technical note TN1130 updated to version 01.3. Technical note TN1141 updated to version 01.3. Technical note TN1137 updated to version 01.4. April 2008 01.6 LatticeXP2 Family Data Sheet updated to version 01.4. Technical note TN1130 updated to version 01.4. Technical note TN1137 updated to version 01.5. April 2008 01.7 Technical note TN1136 updated to version 01.1. June 2008 01.8 LatticeXP2 Family Data Sheet updated to version 01.5. Technical note TN1137 updated to version 01.6. Technical note TN1142 updated to version 01.1. June 2008 01.9 Technical note TN1137 updated to version 01.7. July 2008 02.0 Technical note TN1130 updated to version 01.6. September 2008 02.1 LatticeXP2 Family Data Sheet updated to version 01.6. Technical note TN1130 updated to version 01.7. November 2008 02.2 Technical note TN1141 updated to version 01.4. Added TN1143, LatticeECP2/M Hardware Checklist. January 2009 02.3 Technical note TN1130 updated to version 01.8. May 2009 02.4 Technical note TN1130 updated to version 01.9. Technical note TN1136 updated to version 01.2. Technical note TN1137 updated to version 01.8. Technical note TN1138 updated to version 01.2. Technical note TN1141 updated to version 01.4. February 2010 02.5 Technical note TN1126 updated to version 01.1. Technical note TN1130 updated to version 02.0. Technical note TN1136 updated to version 01.2. Technical note TN1138 updated to version 01.3. Technical note TN1141 updated to version 01.6. February 2011 02.6 Replaced technical note TN1144 with TN1220. March 2011 02.7 Technical note TN1143 updated to version 01.1. April 2011 02.8 LatticeXP2 Family Data Sheet updated to version 01.7. May 2011 02.9 Technical note TN1143 updated to version 01.2. (c) 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 19-1 Revision History LatticeXP2 Family Handbook Lattice Semiconductor Date Handbook Revison Number July 2011 03.0 Change Summary Technical note TN1136 updated to version 01.3. Technical note TN1138 updated to version 01.4. Technical note TN1141 updated to version 01.7. July 2001 03.1 Technical note TN1137 updated to version 01.9. January 2012 03.2 LatticeXP2 Family Data Sheet updated to version 01.8. Technical note TN1136 updated to version 01.3. Technical note TN1138 updated to version 01.4. Technical note TN1141 updated to version 01.7. Note: For detailed revision changes, please refer to the revision history for each document. 19-2