LFXP2-8E-5MN132C - Lattice Semiconductor

LatticeXP2™ Family Handbook

HB1004 Version 03.2, January 2012

January 2012

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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Section I. LatticeXP2 Family Data Sheet

Introduction

Features ............................................................................................................................................................. 1-1

Introduction ........................................................................................................................................................ 1-2

Architecture

Architecture Overview ........................................................................................................................................ 2-1

PFU Blocks ........................................................................................................................................................ 2-2

Slice .......................................................................................................................................................... 2-3

Modes of Operation................................................................................................................................... 2-5

Routing............................................................................................................................................................... 2-6

sysCLOCK Phase Locked Loops (PLL) ............................................................................................................. 2-6

Clock Dividers .................................................................................................................................................... 2-7

Clock Distribution Network ................................................................................................................................. 2-8

Primary Clock Sources.............................................................................................................................. 2-8

Secondary Clock/Control Sources .......................................................................................................... 2-10

Edge Clock Sources................................................................................................................................ 2-11

Primary Clock Routing ............................................................................................................................ 2-12

Dynamic Clock Select (DCS) .................................................................................................................. 2-12

Secondary Clock/Control Routing ........................................................................................................... 2-12

Slice Clock Selection............................................................................................................................... 2-14

Edge Clock Routing ................................................................................................................................ 2-15

sysMEM Memory ............................................................................................................................................. 2-16

sysMEM Memory Block........................................................................................................................... 2-16

Bus Size Matching .................................................................................................................................. 2-16

FlashBAK EBR Content Storage............................................................................................................. 2-16

Memory Cascading ................................................................................................................................. 2-17

Single, Dual and Pseudo-Dual Port Modes............................................................................................. 2-17

Memory Core Reset................................................................................................................................ 2-17

EBR Asynchronous Reset....................................................................................................................... 2-18

sysDSP™ Block ............................................................................................................................................... 2-18

sysDSP Block Approach Compare to General DSP ............................................................................... 2-18

sysDSP Block Capabilities ...................................................................................................................... 2-19

MULT sysDSP Element .......................................................................................................................... 2-20

MAC sysDSP Element ............................................................................................................................ 2-21

MULTADDSUB sysDSP Element ........................................................................................................... 2-22

MULTADDSUBSUM sysDSP Element ................................................................................................... 2-23

Clock, Clock Enable and Reset Resources ............................................................................................ 2-23

Signed and Unsigned with Different Widths............................................................................................ 2-24

OVERFLOW Flag from MAC .................................................................................................................. 2-24

IPexpress™............................................................................................................................................. 2-25

Optimized DSP Functions ................................................................................................................................ 2-25

Resources Available in the LatticeXP2 Family........................................................................................ 2-25

LatticeXP2 DSP Performance................................................................................................................. 2-25

Programmable I/O Cells (PIC) ......................................................................................................................... 2-26

PIO ................................................................................................................................................................... 2-27

Input Register Block................................................................................................................................ 2-27

Output Register Block ............................................................................................................................. 2-28

Tristate Register Block............................................................................................................................ 2-30

LatticeXP2 Family Handbook

Table of Contents

Lattice Semiconductor LatticeXP2 Family Handbook

Control Logic Block ................................................................................................................................. 2-30

DDR Memory Support...................................................................................................................................... 2-30

DLL Calibrated DQS Delay Block ........................................................................................................... 2-32

Polarity Control Logic .............................................................................................................................. 2-33

DQSXFER............................................................................................................................................... 2-34

sysIO Buffer ..................................................................................................................................................... 2-34

sysIO Buffer Banks ................................................................................................................................. 2-34

Typical sysIO I/O Behavior During Power-up.......................................................................................... 2-35

Supported sysIO Standards .................................................................................................................... 2-35

Hot Socketing.......................................................................................................................................... 2-37

IEEE 1149.1-Compliant Boundary Scan Testability......................................................................................... 2-37

flexiFLASH Device Configuration..................................................................................................................... 2-38

Serial TAG Memory................................................................................................................................. 2-39

Live Update Technology ......................................................................................................................... 2-39

Soft Error Detect (SED) Support ............................................................................................................. 2-40

On-Chip Oscillator................................................................................................................................... 2-40

Density Shifting ................................................................................................................................................ 2-41

DC and Switching Characteristics

Absolute Maximum Ratings ............................................................................................................................... 3-1

Recommended Operating Conditions ................................................................................................................ 3-1

On-Chip Flash Memory Specifications............................................................................................................... 3-1

Hot Socketing Specifications.............................................................................................................................. 3-2

ESD Performance .............................................................................................................................................. 3-2

DC Electrical Characteristics.............................................................................................................................. 3-2

Supply Current (Standby)................................................................................................................................... 3-3

Initialization Supply Current ............................................................................................................................... 3-4

Programming and Erase Flash Supply Current ................................................................................................. 3-5

sysIO Recommended Operating Conditions...................................................................................................... 3-6

sysIO Single-Ended DC Electrical Characteristics............................................................................................. 3-7

sysIO Differential Electrical Characteristics ....................................................................................................... 3-8

LVDS......................................................................................................................................................... 3-8

Differential HSTL and SSTL...................................................................................................................... 3-8

LVDS25E .................................................................................................................................................. 3-8

LVCMOS33D ............................................................................................................................................ 3-9

BLVDS .................................................................................................................................................... 3-10

LVPECL .................................................................................................................................................. 3-11

RSDS ...................................................................................................................................................... 3-12

MLVDS.................................................................................................................................................... 3-13

Typical Building Block Function Performance.................................................................................................. 3-14

Pin-to-Pin Performance (LVCMOS25 12mA Drive) ................................................................................ 3-14

Register-to-Register Performance .......................................................................................................... 3-14

Derating Timing Tables .................................................................................................................................... 3-15

LatticeXP2 External Switching Characteristics ................................................................................................ 3-16

LatticeXP2 Internal Switching Characteristics.................................................................................................. 3-19

EBR Timing Diagrams...................................................................................................................................... 3-22

LatticeXP2 Family Timing Adders .................................................................................................................... 3-24

sysCLOCK PLL Timing .................................................................................................................................... 3-27

LatticeXP2 sysCONFIG Port Timing Specifications......................................................................................... 3-28

On-Chip Oscillator and Configuration Master Clock Characteristics................................................................ 3-29

Flash Download Time (from On-Chip Flash to SRAM) .................................................................................... 3-30

Flash Program Time......................................................................................................................................... 3-30

Flash Erase Time ............................................................................................................................................. 3-30

FlashBAK Time (from EBR to Flash) ............................................................................................................... 3-31

JTAG Port Timing Specifications ..................................................................................................................... 3-31

Table of Contents

Lattice Semiconductor LatticeXP2 Family Handbook

Switching Test Conditions................................................................................................................................ 3-33

Pinout Information

Signal Descriptions ............................................................................................................................................ 4-1

PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin .................................................... 4-3

Pin Information Summary................................................................................................................................... 4-4

Logic Signal Connections................................................................................................................................... 4-5

Thermal Management ........................................................................................................................................ 4-5

For Further Information ...................................................................................................................................... 4-5

Ordering Information

Part Number Description.................................................................................................................................... 5-1

Ordering Information .......................................................................................................................................... 5-1

Lead-Free Packaging................................................................................................................................ 5-2

Conventional Packaging ........................................................................................................................... 5-5

Supplemental Information

For Further Information ...................................................................................................................................... 6-1

LatticeXP2 Family Data Sheet Revision History

Revision History ................................................................................................................................................. 7-1

Section II. LatticeXP2 Family Technical Notes

LatticeXP2 sysIO Usage Guide

Introduction ........................................................................................................................................................ 8-1

sysIO Buffer Overview ....................................................................................................................................... 8-1

Supported sysIO Standards ............................................................................................................................... 8-1

sysIO Banking Scheme...................................................................................................................................... 8-3

SPI Flash Interface.................................................................................................................................... 8-3

JTAG Interface .......................................................................................................................................... 8-3

VCCIO (1.2V/1.5V/1.8V/2.5V/3.3V) ............................................................................................................ 8-4

VCCAUX (3.3V) ........................................................................................................................................... 8-4

VCCJ (1.2V/1.5V/1.8V/2.5V/3.3V).............................................................................................................. 8-4

Input Reference Voltage (VREF1, VREF2)................................................................................................... 8-4

VREF1 for DDR Memory Interface ............................................................................................................. 8-4

Mixed Voltage Support in a Bank.............................................................................................................. 8-4

sysIO Standards Supported by Bank ........................................................................................................ 8-5

LVCMOS Buffer Configurations ......................................................................................................................... 8-6

Bus Maintenance Circuit ........................................................................................................................... 8-6

Programmable Drive ................................................................................................................................. 8-6

Programmable Slew Rate ......................................................................................................................... 8-6

Open-Drain Control ................................................................................................................................... 8-6

Differential SSTL and HSTL support......................................................................................................... 8-6

PCI Support with Programmable PCICLAMP ........................................................................................... 8-7

Programmable Input Delay ....................................................................................................................... 8-7

Software sysIO Attributes................................................................................................................................... 8-7

IO_TYPE ................................................................................................................................................... 8-7

OPENDRAIN............................................................................................................................................. 8-8

DRIVE ....................................................................................................................................................... 8-8

PULLMODE .............................................................................................................................................. 8-9

PCICLAMP................................................................................................................................................ 8-9

SLEWRATE .............................................................................................................................................. 8-9

FIXEDDELAY.......................................................................................................................................... 8-10

INBUF ..................................................................................................................................................... 8-10

DIN/DOUT............................................................................................................................................... 8-10

LOC......................................................................................................................................................... 8-10

Design Considerations and Usage................................................................................................................... 8-10

Banking Rules ......................................................................................................................................... 8-10

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Lattice Semiconductor LatticeXP2 Family Handbook

Differential I/O Rules ............................................................................................................................... 8-10

Differential I/O Implementation......................................................................................................................... 8-11

LVDS....................................................................................................................................................... 8-11

BLVDS .................................................................................................................................................... 8-11

RSDS ...................................................................................................................................................... 8-11

LVPECL .................................................................................................................................................. 8-11

Differential SSTL and HSTL.................................................................................................................... 8-11

MLVDS.................................................................................................................................................... 8-11

Technical Support Assistance.......................................................................................................................... 8-11

Revision History ............................................................................................................................................... 8-11

Appendix A. HDL Attributes for Synplicity® and Precision® RTL Synthesis...................................................... 8-12

VHDL Synplicity/Precision RTL Synthesis .............................................................................................. 8-12

Verilog Synplicity..................................................................................................................................... 8-14

Verilog Precision ..................................................................................................................................... 8-15

Appendix B. sysIO Attributes Using the Design Planner User Interface .......................................................... 8-16

Appendix C. sysIO Attributes Using Preference File (ASCII File) .................................................................... 8-18

IOBUF ..................................................................................................................................................... 8-18

LOCATE.................................................................................................................................................. 8-18

USE DIN CELL........................................................................................................................................ 8-19

USE DOUT CELL.................................................................................................................................... 8-19

GROUP VREF ........................................................................................................................................ 8-19

Appendix D. sysIO Attributes Using the Diamond Spreadsheet View User Interface...................................... 8-20

LatticeXP2 sysCLOCK PLL Design and Usage Guide

Introduction ........................................................................................................................................................ 9-1

Clock/Control Distribution Network .................................................................................................................... 9-1

LatticeXP2 Top Level View ................................................................................................................................ 9-1

Primary Clocks ................................................................................................................................................... 9-2

Secondary Clocks .............................................................................................................................................. 9-2

Edge Clocks ....................................................................................................................................................... 9-2

Primary Clock Note ............................................................................................................................................ 9-3

Specifying Clocks in the Design Tools ............................................................................................................... 9-3

Primary-Pure and Primary-DCS................................................................................................................ 9-3

Global Primary Clock and Quadrant Primary Clock ........................................................................................... 9-3

Global Primary Clock ................................................................................................................................ 9-3

Quadrant Primary Clock............................................................................................................................ 9-4

sysCLOCK™ PLL .............................................................................................................................................. 9-4

Functional Description........................................................................................................................................ 9-5

PLL Divider and Delay Blocks................................................................................................................... 9-5

PLL Inputs and Outputs ..................................................................................................................................... 9-5

CLKI Input ................................................................................................................................................. 9-5

RST Input .................................................................................................................................................. 9-5

RSTK Input................................................................................................................................................ 9-6

CLKFB Input.............................................................................................................................................. 9-6

CLKOP Output .......................................................................................................................................... 9-6

CLKOS Output with Phase and Duty Cycle Select ...................................................................................9-6

CLKOK Output with Lower Frequency ...................................................................................................... 9-6

CLKOK2 Output ........................................................................................................................................ 9-6

LOCK Output............................................................................................................................................. 9-6

Dynamic Phase and Dynamic Duty Cycle Adjustment.............................................................................. 9-6

WRDEL (Write Delay) ............................................................................................................................... 9-7

PLL Attributes..................................................................................................................................................... 9-7

FIN ............................................................................................................................................................ 9-7

CLKI_DIV, CLKFB_DIV, CLKOP_DIV, CLKOK_DIV ................................................................................ 9-7

FREQUENCY_PIN_CLKI, FREQUENCY_PIN_CLKOP, FREQUENCY_PIN_CLKOK ............................ 9-7

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Lattice Semiconductor LatticeXP2 Family Handbook

CLKOP Frequency Tolerance ................................................................................................................... 9-7

LatticeXP2 PLL Primitive Definition.................................................................................................................... 9-8

EPLLD Design Migration from LatticeECP2 to LatticeXP2 ....................................................................... 9-8

Dynamic Phase/Duty Mode....................................................................................................................... 9-8

Dynamic Phase Adjustment/Duty Cycle Select.................................................................................................. 9-9

PLL Usage in IPexpress™ ............................................................................................................................... 9-10

Configuration Tab.................................................................................................................................... 9-11

PLL Modes of Operation .................................................................................................................................. 9-13

PLL Clock Injection Removal .................................................................................................................. 9-13

PLL Clock Phase Adjustment.................................................................................................................. 9-14

IPexpress Output ............................................................................................................................................. 9-14

Use of the Pre-Map Preference Editor ............................................................................................................. 9-15

Clock Dividers (CLKDIV).................................................................................................................................. 9-15

CLKDIV Primitive Definition .................................................................................................................... 9-15

CLKDIV Declaration in VHDL Source Code............................................................................................ 9-16

CLKDIV Usage with Verilog - Example ................................................................................................... 9-17

CLKDIV Example Circuits ....................................................................................................................... 9-17

Reset Behavior........................................................................................................................................ 9-18

Release Behavior.................................................................................................................................... 9-18

CLKDIV Inputs-to-Outputs Delay Matching............................................................................................. 9-19

DCS (Dynamic Clock Select) ........................................................................................................................... 9-19

DCS Primitive Definition.......................................................................................................................... 9-19

DCS Timing Diagrams ............................................................................................................................ 9-20

DCS Usage with VHDL - Example .......................................................................................................... 9-21

DCS Usage with Verilog - Example ........................................................................................................ 9-22

Oscillator (OSCE).................................................................................................................................... 9-22

OSC Primitive Symbol (OSCE) ............................................................................................................... 9-22

OSC Usage with VHDL - Example.......................................................................................................... 9-23

OSC Usage with Verilog - Example ........................................................................................................ 9-23

Setting Clock Preferences....................................................................................................................... 9-23

Power Supplies ................................................................................................................................................ 9-23

Technical Support Assistance.......................................................................................................................... 9-23

Revision History ............................................................................................................................................... 9-23

Appendix A. Primary Clock Sources and Distribution ...................................................................................... 9-24

Appendix B. PLL, CLKDIV and ECLK Locations and Connectivity .................................................................. 9-25

Appendix C. Clock Preferences ....................................................................................................................... 9-26

ASIC........................................................................................................................................................ 9-26

FREQUENCY.......................................................................................................................................... 9-26

MAXSKEW.............................................................................................................................................. 9-26

MULTICYCLE ......................................................................................................................................... 9-26

PERIOD .................................................................................................................................................. 9-26

PROHIBIT ............................................................................................................................................... 9-26

USE PRIMARY ....................................................................................................................................... 9-26

USE SECONDARY ................................................................................................................................. 9-26

USE EDGE.............................................................................................................................................. 9-27

CLOCK_TO_OUT ................................................................................................................................... 9-27

INPUT_SETUP ....................................................................................................................................... 9-27

PLL_PHASE_BACK................................................................................................................................ 9-27

LatticeXP2 Memory Usage Guide

Introduction ...................................................................................................................................................... 10-1

Memories in LatticeXP2 Devices ..................................................................................................................... 10-1

Utilizing IPexpress............................................................................................................................................ 10-2

IPexpress Flow........................................................................................................................................ 10-3

Memory Modules.............................................................................................................................................. 10-6

Table of Contents

Lattice Semiconductor LatticeXP2 Family Handbook

Single Port RAM (RAM_DQ) – EBR Based ............................................................................................10-6

True Dual Port RAM (RAM_DP_TRUE) – EBR Based ......................................................................... 10-11

Pseudo Dual Port RAM (RAM_DP) – EBR Based ................................................................................ 10-17

Read Only Memory (ROM) - EBR Based..............................................................................................10-20

First In First Out (FIFO, FIFO_DC) – EBR Based................................................................................. 10-23

Distributed Single Port RAM (Distributed_SPRAM) – PFU Based........................................................ 10-35

Distributed Dual Port RAM (Distributed_DPRAM) – PFU Based .......................................................... 10-37

Distributed ROM (Distributed_ROM) – PFU Based .............................................................................. 10-39

User TAG Memory ................................................................................................................................ 10-41

Basic Specifications for TAG Memory............................................................................................................ 10-41

General Description .............................................................................................................................. 10-43

Pin Descriptions .................................................................................................................................... 10-43

SPI Operations...................................................................................................................................... 10-44

Specifications and Timing Diagrams..................................................................................................... 10-49

Initializing Memory ......................................................................................................................................... 10-50

Initialization File Format ........................................................................................................................ 10-50

Binary File ............................................................................................................................................. 10-51

Hex File................................................................................................................................................. 10-51

Addressed Hex...................................................................................................................................... 10-51

FlashBak™ Capability.................................................................................................................................... 10-52

Technical Support Assistance........................................................................................................................ 10-52

Revision History ............................................................................................................................................. 10-53

Appendix A. Attribute Definitions.................................................................................................................... 10-54

DATA_WIDTH....................................................................................................................................... 10-54

REGMODE............................................................................................................................................ 10-54

RESETMODE ....................................................................................................................................... 10-54

CSDECODE.......................................................................................................................................... 10-54

WRITEMODE........................................................................................................................................ 10-54

GSR ...................................................................................................................................................... 10-54

LatticeXP2 High-Speed I/O Interface

Introduction ...................................................................................................................................................... 11-1

DDR and DDR2 SDRAM Interfaces Overview................................................................................................. 11-1

Implementing DDR Memory Interfaces with LatticeXP2 Devices .................................................................... 11-3

DQS Grouping......................................................................................................................................... 11-3

DDR Software Primitives......................................................................................................................... 11-4

Memory Read Implementation ....................................................................................................................... 11-14

DLL Compensated DQS Delay Elements ............................................................................................. 11-14

DQS Transition Detect or Automatic Clock Polarity Select ................................................................... 11-14

Data Valid Module................................................................................................................................. 11-15

DDR I/O Register Implementation......................................................................................................... 11-15

Memory Read Implementation in Software ........................................................................................... 11-15

Read Timing Waveforms....................................................................................................................... 11-16

Memory Write Implementation .............................................................................................................. 11-19

Generic High Speed DDR Implementation .................................................................................................... 11-22

Generic DDR Software Primitives ......................................................................................................... 11-23

Design Rules/Guidelines....................................................................................................................... 11-34

DDR Usage in ispLEVER IPexpress.............................................................................................................. 11-34

DDR Generic......................................................................................................................................... 11-35

Configuration Tab.................................................................................................................................. 11-36

DDR_MEM ............................................................................................................................................ 11-36

Configuration Tab.................................................................................................................................. 11-37

FCRAM (“Fast Cycle Random Access Memory”) Interface ........................................................................... 11-39

Board Design Guidelines ............................................................................................................................... 11-39

References..................................................................................................................................................... 11-39

Table of Contents

Lattice Semiconductor LatticeXP2 Family Handbook

Technical Support Assistance........................................................................................................................ 11-40

Revision History ............................................................................................................................................. 11-40

Appendix A. DDR Generation using Diamond IPexpress ..............................................................................11-41

DDR Generic......................................................................................................................................... 11-41

Configuration Tab.................................................................................................................................. 11-42

DDR_MEM ............................................................................................................................................ 11-43

Configuration Tab.................................................................................................................................. 11-44

Power Estimation and Management for LatticeXP2 Devices

Introduction ...................................................................................................................................................... 12-1

Power Supply Sequencing and Hot Socketing................................................................................................. 12-1

Recommended Power-up Sequence ...................................................................................................... 12-1

Power Calculator Hardware Assumptions........................................................................................................ 12-1

Power Calculation Equations ........................................................................................................................... 12-1

Power Calculations ................................................................................................................................. 12-2

Using the Power Calculator.............................................................................................................................. 12-3

Starting the Power Calculator ................................................................................................................. 12-3

Creating a Power Calculator Project ....................................................................................................... 12-4

Power Calculator Main Window .............................................................................................................. 12-5

Power Calculator Wizard......................................................................................................................... 12-7

Creating a New Project Without the NCD File ...................................................................................... 12-10

Creating a New Project with the NCD File ............................................................................................ 12-10

Opening an Existing Project.................................................................................................................. 12-12

Importing a Simulation File (VCD)......................................................................................................... 12-12

Importing a Trace Report File (TWR).................................................................................................... 12-13

Activity Factor and Toggle Rate ..................................................................................................................... 12-13

Ambient and Junction Temperatures and Airflow .......................................................................................... 12-14

Managing Power Consumption ...................................................................................................................... 12-14

Power Calculator Assumptions ...................................................................................................................... 12-15

Technical Support Assistance........................................................................................................................ 12-15

Revision History ............................................................................................................................................. 12-15

LatticeXP2 sysDSP Usage Guide

Introduction ...................................................................................................................................................... 13-1

sysDSP Block Hardware .................................................................................................................................. 13-1

sysDSP Block Software ................................................................................................................................... 13-2

Overview ................................................................................................................................................. 13-2

Targeting sysDSP Block Using IPexpress .............................................................................................. 13-2

Targeting the sysDSP Block by Inference........................................................................................................ 13-9

sysDSP Blocks in the Report File .................................................................................................................. 13-11

MAP Report File.................................................................................................................................... 13-11

Post PAR Report File ............................................................................................................................ 13-12

Targeting the sysDSP Block Using Simulink.................................................................................................. 13-13

Simulink Overview................................................................................................................................. 13-13

Targeting the sysDSP Block by Instantiating Primitives................................................................................. 13-14

sysDSP Block Control Signal and Data Signal Descriptions.......................................................................... 13-14

Technical Support Assistance........................................................................................................................ 13-14

Revision History ............................................................................................................................................. 13-15

Appendix A. DSP Block Primitives ................................................................................................................. 13-16

MULT18X18B........................................................................................................................................ 13-16

MULT18X18ADDSUBB......................................................................................................................... 13-16

MULT18X18ADDSUBSUMB................................................................................................................. 13-17

MULT18X18MACB................................................................................................................................ 13-19

MULT36X36B........................................................................................................................................ 13-20

MULT9X9B............................................................................................................................................ 13-21

MULT9X9ADDSUBB............................................................................................................................. 13-21

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Lattice Semiconductor LatticeXP2 Family Handbook

MULT9X9ADDSUBSUMB..................................................................................................................... 13-22

LatticeXP2 sysCONFIG Usage Guide

Introduction ...................................................................................................................................................... 14-1

Programming Overview.................................................................................................................................... 14-1

Configuration Pins............................................................................................................................................ 14-2

sysCONFIG Pins..................................................................................................................................... 14-3

Programming Sequence .................................................................................................................................. 14-7

SRAM...................................................................................................................................................... 14-7

Flash Background ................................................................................................................................... 14-7

ispJTAG Pins ................................................................................................................................................... 14-8

TDO......................................................................................................................................................... 14-8

TDI .......................................................................................................................................................... 14-8

TMS......................................................................................................................................................... 14-8

TCK......................................................................................................................................................... 14-8

VCCJ....................................................................................................................................................... 14-8

Configuration and JTAG Voltage Levels ................................................................................................. 14-8

Configuration Modes and Options.................................................................................................................... 14-9

Configuration Options ............................................................................................................................. 14-9

Slave SPI Mode ...................................................................................................................................... 14-9

Master SPI Mode .................................................................................................................................. 14-10

Self Download Mode ............................................................................................................................. 14-10

ispJTAG Mode ...................................................................................................................................... 14-10

Wake Up Options ........................................................................................................................................... 14-11

Wake Up Sequence .............................................................................................................................. 14-11

Software Selectable Options.......................................................................................................................... 14-12

Slave SPI Port....................................................................................................................................... 14-12

Master SPI Port..................................................................................................................................... 14-13

Configuration Mode............................................................................................................................... 14-13

DONE Open Drain ................................................................................................................................ 14-13

DONE External...................................................................................................................................... 14-13

Master Clock Selection ......................................................................................................................... 14-13

Security ................................................................................................................................................. 14-14

Wake Up Sequence .............................................................................................................................. 14-14

Wake On Lock Selection....................................................................................................................... 14-14

Power Save........................................................................................................................................... 14-14

One Time Programmable Fuse...................................................................................................................... 14-14

User GOE....................................................................................................................................................... 14-14

Tag Memory ................................................................................................................................................... 14-15

Slave SPI Mode Operation.................................................................................................................... 14-16

User Flash...................................................................................................................................................... 14-16

Technical Support Assistance........................................................................................................................ 14-17

Revision History ............................................................................................................................................. 14-17

LatticeXP2 Configuration Encryption and Security Usage Guide

Introduction ...................................................................................................................................................... 15-1

Encryption/Decryption Flow ............................................................................................................................. 15-1

Encrypting the JEDEC File............................................................................................................................... 15-1

ispLEVER Flow ....................................................................................................................................... 15-2

ispVM Flow.............................................................................................................................................. 15-2

Programming the Key into the Device..................................................................................................... 15-4

Security Bit for the Configuration and User Flash (CONFIG_SECURE).......................................................... 15-6

Advanced Security Settings ............................................................................................................................. 15-6

One-Time Programmable (OTP) or Permanent Lock ...................................................................................... 15-6

Flash Protect .................................................................................................................................................... 15-7

Changing Flash Protect........................................................................................................................... 15-7

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Lattice Semiconductor LatticeXP2 Family Handbook

Encryption ........................................................................................................................................................ 15-8

Usercode in Encrypted Files ............................................................................................................................ 15-8

Decryption Flow ............................................................................................................................................... 15-8

Verifying a Configuration.................................................................................................................................. 15-9

References....................................................................................................................................................... 15-9

Technical Support Assistance.......................................................................................................................... 15-9

Revision History ............................................................................................................................................... 15-9

LatticeXP2 Soft Error Detection (SED) Usage Guide

Introduction ...................................................................................................................................................... 16-1

SED Overview.................................................................................................................................................. 16-1

Basic SED and One-shot SED Modes ............................................................................................................. 16-2

Basic SED ............................................................................................................................................... 16-2

One-Shot SED ........................................................................................................................................ 16-2

Hardware Description....................................................................................................................................... 16-2

Signal Descriptions .......................................................................................................................................... 16-2

SEDCLKIN .............................................................................................................................................. 16-3

OSC_DIV ................................................................................................................................................ 16-3

SEDENABLE........................................................................................................................................... 16-3

SEDCLKOUT .......................................................................................................................................... 16-3

SEDSTART ............................................................................................................................................. 16-3

SEDFRCERRN ....................................................................................................................................... 16-3

SEDINPROG........................................................................................................................................... 16-4

SEDDONE .............................................................................................................................................. 16-4

SEDERR ................................................................................................................................................. 16-4

SED Flow ......................................................................................................................................................... 16-4

SED Run Time ................................................................................................................................................. 16-5

Sample Code ................................................................................................................................................... 16-6

Basic SED VHDL Example ..................................................................................................................... 16-6

One Shot SED in VHDL .......................................................................................................................... 16-7

Basic SED Verilog Example.................................................................................................................... 16-8

One-Shot SED in Verilog ........................................................................................................................ 16-9

Technical Support Assistance.......................................................................................................................... 16-9

Revision History ............................................................................................................................................. 16-10

Introduction ...................................................................................................................................................... 17-1

LatticeXP2 Dual Boot Feature

Dual Boot Feature................................................................................................................................... 17-2

Definitions ........................................................................................................................................................ 17-3

SPI .......................................................................................................................................................... 17-3

Master SPI .............................................................................................................................................. 17-3

SDM (Self Download Mode).................................................................................................................... 17-3

Erase....................................................................................................................................................... 17-3

Program .................................................................................................................................................. 17-3

Configure................................................................................................................................................. 17-3

Primary Boot ........................................................................................................................................... 17-3

Golden Boot ............................................................................................................................................ 17-3

Dual Boot ................................................................................................................................................ 17-4

Refresh.................................................................................................................................................... 17-4

Bitstream Data File (.BIT File)................................................................................................................. 17-4

JEDEC File (.JED File)............................................................................................................................ 17-4

TransFR .................................................................................................................................................. 17-4

Security ................................................................................................................................................... 17-4

SED CRC................................................................................................................................................ 17-4

One Shot SED......................................................................................................................................... 17-4

Background Mode (User Mode) .............................................................................................................. 17-4

Table of Contents

Lattice Semiconductor LatticeXP2 Family Handbook

Direct Mode (IEEE 1532 Access Modal State) ....................................................................................... 17-4

Purpose............................................................................................................................................................ 17-4

Resource.......................................................................................................................................................... 17-5

Dual Boot Mode ............................................................................................................................................... 17-6

Critical Points ................................................................................................................................................... 17-7

Programming Procedures ................................................................................................................................ 17-9

Part 1: Program the Golden Pattern into the SPI Flash Devices ............................................................ 17-9

Part 2: Program the Primary Pattern into LatticeXP2 Embedded Flash ............................................... 17-12

Reference Material......................................................................................................................................... 17-14

LatticeXP2 Bitstream File Format ......................................................................................................... 17-14

Implement SPI Flash Programming on ispVM System ......................................................................... 17-14

References..................................................................................................................................................... 17-15

Technical Support Assistance........................................................................................................................ 17-16

Revision History ............................................................................................................................................. 17-16

....................................................................................................................................................................... 17-16

LatticeXP2 Hardware Checklist

Introduction ...................................................................................................................................................... 18-1

Power Supply ................................................................................................................................................... 18-1

Power Supply Sequencing ...................................................................................................................... 18-1

Power Supply Ramp ............................................................................................................................... 18-2

Power Estimation .................................................................................................................................... 18-2

Configuration.................................................................................................................................................... 18-2

JTAG Interface ........................................................................................................................................ 18-3

I/O Interface and Critical Pins .......................................................................................................................... 18-3

I/O Pin Assignments Around VCCPLL ...................................................................................................... 18-3

DDR/DDR2 Memory Interface Pin Assignments..................................................................................... 18-4

True-LVDS Output Pin Assignments....................................................................................................... 18-4

HSTL and SSTL Pin Assignments .......................................................................................................... 18-4

PCI Clamp Pin Assignment..................................................................................................................... 18-4

Test Output Enable (TOE) ...................................................................................................................... 18-4

Checklist........................................................................................................................................................... 18-5

Technical Support Assistance.......................................................................................................................... 18-5

Revision History ............................................................................................................................................... 18-5

Section III. LatticeXP2 Family Handbook Revision History

Revision History ............................................................................................................................................... 19-1

Section I. LatticeXP2 Family Data Sheet

DS1009 Version 01.8, January 2012

www.latticesemi.com 1-1 DS1009 Introduction_01.3

January 2012 Data Sheet DS1009

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Features

flexiFLASH™ Architecture

• Instant-on

• Infinitely reconfigurable

• Single chip

• FlashBAK™ technology

•Serial TAG memory

•Design security

Live Update Technology

• TransFR™ technology

• Secure updates with 128 bit AES encryption

• Dual-boot with external SPI

sysDSP™ Block

• Three to eight blocks for high performance 

Multiply and Accumulate

• 12 to 32 18x18 multipliers

• Each block supports one 36x36 multiplier or four

18x18 or eight 9x9 multipliers

Embedded and Distributed Memory

• Up to 885 Kbits sysMEM™ EBR

• Up to 83 Kbits Distributed RAM

sysCLOCK™ PLLs

• Up to four analog PLLs per device

• Clock multiply, divide and phase shifting

Flexible I/O Buffer

• sysIO™ buffer supports:

– LVCMOS 33/25/18/15/12; LVTTL

– SSTL 33/25/18 class I, II

– HSTL15 class I; HSTL18 class I, II

–PCI

– LVDS, Bus-LVDS, MLVDS, LVPECL, RSDS

Pre-engineered Source Synchronous

Interfaces

• DDR / DDR2 interfaces up to 200 MHz

• 7:1 LVDS interfaces support display applications

•XGMII

Density And Package Options

• 5k to 40k LUT4s, 86 to 540 I/Os

• csBGA, TQFP, PQFP, ftBGA and fpBGA packages

• Density migration supported

Flexible Device Configuration

• SPI (master and slave) Boot Flash Interface

• Dual Boot Image supported

• Soft Error Detect (SED) macro embedded

System Level Support

• IEEE 1149.1 and IEEE 1532 Compliant

• On-chip oscillator for initialization & general use

• Devices operate with 1.2V power supply

Table 1-1. LatticeXP2 Family Selection Guide

Device XP2-5 XP2-8 XP2-17 XP2-30 XP2-40

LUTs (K) 5 8 172940

Distributed RAM (KBits) 1018355683

EBR SRAM (KBits) 166 221 276 387 885

EBR SRAM Blocks 9 12 15 21 48

sysDSP Blocks 3 4 5 7 8

18 x 18 Multipliers 1216202832

VCC Voltage 1.2 1.2 1.2 1.2 1.2

GPLL 22444

Max Available I/O 172 201 358 472 540

Packages and I/O Combinations

132-Ball csBGA (8 x 8 mm) 86 86

144-Pin TQFP (20 x 20 mm) 100 100

208-Pin PQFP (28 x 28 mm) 146 146 146

256-Ball ftBGA (17 x17 mm) 172 201 201 201

484-Ball fpBGA (23 x 23 mm) 358 363 363

672-Ball fpBGA (27 x 27 mm) 472 540

LatticeXP2 Family Data Sheet

Introduction

1-2

Introduction

Lattice Semiconductor LatticeXP2 Family Data Sheet

Introduction

LatticeXP2 devices combine a Look-up Table (LUT) based FPGA fabric with non-volatile Flash cells in an architec-

ture referred to as flexiFLASH.

The flexiFLASH approach provides benefits including instant-on, infinite reconfigurability, on chip storage with

FlashBAK embedded block memory and Serial TAG memory and design security. The parts also support Live

Update technology with TransFR, 128-bit AES Encryption and Dual-boot technologies.

The LatticeXP2 FPGA fabric was optimized for the new technology from the outset with high performance and low

cost in mind. LatticeXP2 devices include LUT-based logic, distributed and embedded memory, Phase Locked

Loops (PLLs), pre-engineered source synchronous I/O support and enhanced sysDSP blocks.

Lattice Diamond® design software allows large and complex designs to be efficiently implemented using the

LatticeXP2 family of FPGA devices. Synthesis library support for LatticeXP2 is available for popular logic synthesis

tools. The Diamond software uses the synthesis tool output along with the constraints from its floor planning tools

to place and route the design in the LatticeXP2 device. The Diamond tool extracts the timing from the routing and

back-annotates it into the design for timing verification.

Lattice provides many pre-designed Intellectual Property (IP) LatticeCORE™ modules for the LatticeXP2 family. By

using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design,

increasing their productivity.

www.latticesemi.com 2-1 DS1009 Architecture_01.5

January 2012 Data Sheet DS1009

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Architecture Overview

Each LatticeXP2 device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Inter-

spersed between the rows of logic blocks are rows of sysMEM™ Embedded Block RAM (EBR) and a row of sys-

DSP™ Digital Signal Processing blocks as shown in Figure 2-1.

On the left and right sides of the Programmable Functional Unit (PFU) array, there are Non-volatile Memory Blocks.

In configuration mode the nonvolatile memory is programmed via the IEEE 1149.1 TAP port or the sysCONFIG™

peripheral port. On power up, the configuration data is transferred from the Non-volatile Memory Blocks to the con-

figuration SRAM. With this technology, expensive external configuration memory is not required, and designs are

secured from unauthorized read-back. This transfer of data from non-volatile memory to configuration SRAM via

wide busses happens in microseconds, providing an “instant-on” capability that allows easy interfacing in many

applications. LatticeXP2 devices can also transfer data from the sysMEM EBR blocks to the Non-volatile Memory

Blocks at user request.

There are two kinds of logic blocks, the PFU and the PFU without RAM (PFF). The PFU contains the building

blocks for logic, arithmetic, RAM and ROM functions. The PFF block contains building blocks for logic, arithmetic

and ROM functions. Both PFU and PFF blocks are optimized for flexibility allowing complex designs to be imple-

mented quickly and efficiently. Logic Blocks are arranged in a two-dimensional array. Only one type of block is used

per row.

LatticeXP2 devices contain one or more rows of sysMEM EBR blocks. sysMEM EBRs are large dedicated 18Kbit

memory blocks. Each sysMEM block can be configured in a variety of depths and widths of RAM or ROM. In addi-

tion, LatticeXP2 devices contain up to two rows of DSP Blocks. Each DSP block has multipliers and adder/accumu-

lators, which are the building blocks for complex signal processing capabilities.

Each PIC block encompasses two PIOs (PIO pairs) with their respective sysIO buffers. The sysIO buffers of the

LatticeXP2 devices are arranged into eight banks, allowing the implementation of a wide variety of I/O standards.

PIO pairs on the left and right edges of the device can be configured as LVDS transmit/receive pairs. The PIC logic

also includes pre-engineered support to aid in the implementation of high speed source synchronous standards

such as 7:1 LVDS interfaces, found in many display applications, and memory interfaces including DDR and DDR2.

Other blocks provided include PLLs and configuration functions. The LatticeXP2 architecture provides up to four

General Purpose PLLs (GPLL) per device. The GPLL blocks are located in the corners of the device.

The configuration block that supports features such as configuration bit-stream de-encryption, transparent updates

and dual boot support is located between banks two and three. Every device in the LatticeXP2 family supports a

sysCONFIG port, muxed with bank seven I/Os, which supports serial device configuration. A JTAG port is provided

between banks two and three.

This family also provides an on-chip oscillator. LatticeXP2 devices use 1.2V as their core voltage.

LatticeXP2 Family Data Sheet

Architecture

2-2

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

Figure 2-1. Simplified Block Diagram, LatticeXP2-17 Device (Top Level)

PFU Blocks

The core of the LatticeXP2 device is made up of logic blocks in two forms, PFUs and PFFs. PFUs can be pro-

grammed to perform logic, arithmetic, distributed RAM and distributed ROM functions. PFF blocks can be pro-

grammed to perform logic, arithmetic and ROM functions. Except where necessary, the remainder of this data

sheet will use the term PFU to refer to both PFU and PFF blocks.

Each PFU block consists of four interconnected slices, numbered Slice 0 through Slice 3, as shown in Figure 2-2.

All the interconnections to and from PFU blocks are from routing. There are 50 inputs and 23 outputs associated

with each PFU block.

On-chip

Oscillator

Programmable

Function Units

(PFUs)

SPI Port

sysCLOCK PLLs Flexible Routing

Flash

JTAG Port

sysIO Buffers,

Pre-Engineered Source

Synchronous Support

sysMEM Block

RAM

DSP Blocks

2-3

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

Figure 2-2. PFU Diagram

Slice

Slice 0 through Slice 2 contain two 4-input combinatorial Look-Up Tables (LUT4), which feed two registers. Slice 3

contains two LUT4s and no registers. For PFUs, Slice 0 and Slice 2 can also be configured as distributed memory,

a capability not available in PFF blocks. Table 2-1 shows the capability of the slices in both PFF and PFU blocks

along with the operation modes they enable. In addition, each PFU contains logic that allows the LUTs to be com-

bined to perform functions such as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset func-

tions (programmable as synchronous/asynchronous), clock select, chip-select and wider RAM/ROM functions.

Figure 2-3 shows an overview of the internal logic of the slice. The registers in the slice can be configured as posi-

tive/negative edge triggered or level sensitive clocks.

Table 2-1. Resources and Modes Available per Slice

Slice 0 through Slice 2 have 14 input signals: 13 signals from routing and one from the carry-chain (from the adja-

cent slice or PFU). There are seven outputs: six to routing and one to carry-chain (to the adjacent PFU). Slice 3 has

13 input signals from routing and four signals to routing. Table 2-2 lists the signals associated with Slice 0 to Slice

Slice PFU BLock PFF Block

Resources Modes Resources Modes

Slice 0 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM

Slice 1 2 LUT4s and 2 Registers Logic, Ripple, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM

Slice 2 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM

Slice 3 2 LUT4s Logic, ROM 2 LUT4s Logic, ROM

Slice 0

LUT4 &

CARRY

LUT4 &

CARRY

D D

Slice 1

LUT4 &

CARRY

LUT4 &

CARRY

Slice 2

LUT4 &

CARRY

LUT4 &

CARRY

From

Routing

Slice 3

LUT4 LUT4

D D D D

FF FF FF FF FF FF

2-4

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

Figure 2-3. Slice Diagram

Table 2-2. Slice Signal Descriptions

Function Type Signal Names Description

Input Data signal A0, B0, C0, D0 Inputs to LUT4

Input Data signal A1, B1, C1, D1 Inputs to LUT4

Input Multi-purpose M0 Multipurpose Input

Input Multi-purpose M1 Multipurpose Input

Input Control signal CE Clock Enable

Input Control signal LSR Local Set/Reset

Input Control signal CLK System Clock

Input Inter-PFU signal FCI Fast Carry-In1

Input Inter-slice signal FXA Intermediate signal to generate LUT6 and LUT7

Input Inter-slice signal FXB Intermediate signal to generate LUT6 and LUT7

Output Data signals F0, F1 LUT4 output register bypass signals

Output Data signals Q0, Q1 Register outputs

Output Data signals OFX0 Output of a LUT5 MUX

Output Data signals OFX1 Output of a LUT6, LUT7, LUT82 MUX depending on the slice

Output Inter-PFU signal FCO Slice 2 of each PFU is the fast carry chain output1

1. See Figure 2-3 for connection details.

2. Requires two PFUs.

LUT4 &

CARRY*

LUT4 &

CARRY*

SLICE

FF*

OFX0

CLK

LSR

FF*

OFX1

F/SUM

F/SUM D

FCI into Slice/PFU, FCO from Different Slice/PFU

FCO from Slice/PFU, FCI into Different Slice/PFU

LUT5

Mux

From

Routing

FXB

FXA

For Slices 0 and 2, memory control signals are generated from Slice 1 as follows:

WCK is CLK

WRE is from LSR

DI[3:2] for Slice 2 and DI[1:0] for Slice 0 data

WAD [A:D] is a 4bit address from slice 1 LUT input

* Not in Slice 3

2-5

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

Modes of Operation

Each slice has up to four potential modes of operation: Logic, Ripple, RAM and ROM.

Logic Mode

In this mode, the LUTs in each slice are configured as LUT4s. A LUT4 has 16 possible input combinations. Four-

input logic functions are generated by programming the LUT4. Since there are two LUT4s per slice, a LUT5 can be

constructed within one slice. Larger LUTs such as LUT6, LUT7 and LUT8, can be constructed by concatenating

two or more slices. Note that a LUT8 requires more than four slices.

Ripple Mode

Ripple mode allows efficient implementation of small arithmetic functions. In ripple mode, the following functions

can be implemented by each slice:

• Addition 2-bit

• Subtraction 2-bit

• Add/Subtract 2-bit using dynamic control

• Up counter 2-bit

• Down counter 2-bit

• Up/Down counter with async clear

• Up/Down counter with preload (sync)

• Ripple mode multiplier building block

• Multiplier support

• Comparator functions of A and B inputs

– A greater-than-or-equal-to B

– A not-equal-to B

– A less-than-or-equal-to B

Two carry signals, FCI and FCO, are generated per slice in this mode, allowing fast arithmetic functions to be con-

structed by concatenating slices.

RAM Mode

In this mode, a 16x4-bit distributed Single Port RAM (SPR) can be constructed using each LUT block in Slice 0 and

Slice 2 as a 16x1-bit memory. Slice 1 is used to provide memory address and control signals. A 16x2-bit Pseudo

Dual Port RAM (PDPR) memory is created by using one slice as the read-write port and the other companion slice

as the read-only port.

The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft-

ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3

shows the number of slices required to implement different distributed RAM primitives. For more information on

using RAM in LatticeXP2 devices, please see TN1137, LatticeXP2 Memory Usage Guide.

Table 2-3. Number of Slices Required For Implementing Distributed RAM

ROM Mode

ROM mode uses the LUT logic; hence, Slices 0 through 3 can be used in the ROM mode. Preloading is accom-

plished through the programming interface during PFU configuration.

SPR 16X4 PDPR 16X4

Number of slices 3 3

Note: SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM

2-6

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

Routing

There are many resources provided in the LatticeXP2 devices to route signals individually or as busses with related

control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) seg-

ments.

The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) or x6 (spans seven PFU)

connections. The x1 and x2 connections provide fast and efficient connections in horizontal and vertical directions.

The x2 and x6 resources are buffered to allow both short and long connections routing between PFUs.

The LatticeXP2 family has an enhanced routing architecture to produce a compact design. The Diamond design

tool takes the output of the synthesis tool and places and routes the design. Generally, the place and route tool is

completely automatic, although an interactive routing editor is available to optimize the design.

sysCLOCK Phase Locked Loops (PLL)

The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The LatticeXP2 family supports between

two and four full featured General Purpose PLLs (GPLL). The architecture of the GPLL is shown in Figure 2-4.

CLKI, the PLL reference frequency, is provided either from the pin or from routing; it feeds into the Input Clock

Divider block. CLKFB, the feedback signal, is generated from CLKOP (the primary clock output) or from a user

clock pin/logic. CLKFB feeds into the Feedback Divider and is used to multiply the reference frequency.

Both the input path and feedback signals enter the Voltage Controlled Oscillator (VCO) block. The phase and fre-

quency of the VCO are determined from the input path and feedback signals. A LOCK signal is generated by the

VCO to indicate that the VCO is locked with the input clock signal.

The output of the VCO feeds into the CLKOP Divider, a post-scalar divider. The duty cycle of the CLKOP Divider

output can be fine tuned using the Duty Trim block, which creates the CLKOP signal. By allowing the VCO to oper-

ate at higher frequencies than CLKOP, the frequency range of the GPLL is expanded. The output of the CLKOP

Divider is passed through the CLKOK Divider, a secondary clock divider, to generate lower frequencies for the

CLKOK output. For applications that require even lower frequencies, the CLKOP signal is passed through a divide-

by-three divider to produce the CLKOK2 output. The CLKOK2 output is provided for applications that use source

synchronous logic. The Phase/Duty Cycle/Duty Trim block is used to adjust the phase and duty cycle of the CLKOP

Divider output to generate the CLKOS signal. The phase/duty cycle setting can be pre-programmed or dynamically

adjusted.

The clock outputs from the GPLL; CLKOP, CLKOK, CLKOK2 and CLKOS, are fed to the clock distribution network.

For further information on the GPLL please see TN1126, LatticeXP2 sysCLOCK PLL Design and Usage Guide.

2-7

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

Figure 2-4. General Purpose PLL (GPLL) Diag ram

Table 2-4 provides a description of the signals in the GPLL blocks.

Table 2-4. GPLL Block Signal Descriptions

Clock Dividers

LatticeXP2 devices have two clock dividers, one on the left side and one on the right side of the device. These are

intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in a ÷2, ÷4 or

÷8 mode and maintains a known phase relationship between the divided down clock and the high-speed clock

based on the release of its reset signal. The clock dividers can be fed from the CLKOP output from the GPLLs or

from the Edge Clocks (ECLK). The clock divider outputs serve as primary clock sources and feed into the clock dis-

tribution network. The Reset (RST) control signal resets the input and forces all outputs to low. The RELEASE sig-

nal releases outputs to the input clock. For further information on clock dividers, please see TN1126, LatticeXP2

sysCLOCK PLL Design and Usage Guide. Figure 2-5 shows the clock divider connections.

Signal I/O Description

CLKI I Clock input from external pin or routing

CLKFB I

PLL feedback input from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock

(PIN or logic)

RST I “1” to reset PLL counters, VCO, charge pumps and M-dividers

RSTK I “1” to reset K-divider

DPHASE [3:0] I DPA Phase Adjust input

DDDUTY [3:0] I DPA Duty Cycle Select input

WRDEL I DPA Fine Delay Adjust input

CLKOS O PLL output clock to clock tree (phase shifted/duty cycle changed)

CLKOP O PLL output clock to clock tree (no phase shift)

CLKOK O PLL output to clock tree through secondary clock divider

CLKOK2 O PLL output to clock tree (CLKOP divided by 3)

LOCK O “1” indicates PLL LOCK to CLKI

CLKFB

Divider

RST

CLKFB

CLKI

LOCK

CLKOP

CLKOS

RSTK

DPHASE

Internal Feedback

DDUTY

WRDEL

CLKOK2

CLKOK

CLKI

Divider

PFD VCO/

LOOP FILTER

CLKOP

Divider

Phase/

Duty Cycle/

Duty Trim

CLKOK

Divider

Lock

Detect

2-8

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

Figure 2-5. Clock Divider Connections

Clock Distribution Network

LatticeXP2 devices have eight quadrant-based primary clocks and between six and eight flexible region-based sec-

ondary clocks/control signals. Two high performance edge clocks are available on each edge of the device to sup-

port high speed interfaces. The clock inputs are selected from external I/Os, the sysCLOCK PLLs, or routing. Clock

inputs are fed throughout the chip via the primary, secondary and edge clock networks.

Primary Clock Sources

LatticeXP2 devices derive primary clocks from four sources: PLL outputs, CLKDIV outputs, dedicated clock inputs

and routing. LatticeXP2 devices have two to four sysCLOCK PLLs, located in the four corners of the device. There

are eight dedicated clock inputs, two on each side of the device. Figure 2-6 shows the primary clock sources.

RST

RELEASE

÷1

÷2

÷4

÷8

CLKOP (GPLL)

ECLK

CLKDIV

2-9

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

Figure 2-6. Primary Clock Sourc es for XP2-17

Primary Clock Sources

to Eight Quadrant Clock Selection

From Routing

GPLL

PLL Input

Note: This diagram shows sources for the XP2-17 device. Smaller LatticeXP2 devices have two GPLLs.

CLK

DIV

Clock

Input

Clock

Input

PLL Input

Clock

Input

Clock

Input

Clock Input

GPLL

CLK

DIV

2-10

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

Secondary Clock/Control Sources

LatticeXP2 devices derive secondary clocks (SC0 through SC7) from eight dedicated clock input pads and the rest

from routing. Figure 2-7 shows the secondary clock sources.

Figure 2-7. Secondary Clock Sources

Secondary Clock Sources

From Routing

From

Routing

From

Routing

From

Routing

From

Routing

From

Routing

From

Routing

From

Routing

From

Routing

From Routing

Clock Input

Clock

Input

Clock

Input

Clock

Input

Clock

Input

Clock Input

From Routing

Clock Input

From Routing

2-11

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

Edge Clock Sources

Edge clock resources can be driven from a variety of sources at the same edge. Edge clock resources can be

driven from adjacent edge clock PIOs, primary clock PIOs, PLLs and clock dividers as shown in Figure 2-8.

Figure 2-8. Edge Clock Sources

Eight Edge Clocks (ECLK)

Two Clocks per Edge

Sources for

bottom edge

clocks

Sources for right edge clocks

Clock

Input

Clock

Input

From Routing

From

Routing

From

Routing

From

Routing

From

Routing

Clock Input Clock Input

From Routing

Clock

Input

Clock

Input

From Routing

Sources for left edge clocks

Sources for top

edge clocks

PLL

Input

PLL

Input

GPLL

CLKOP

CLKOS

PLL

Input

GPLL

CLKOP

CLKOS

CLKOP

CLKOS GPLL

PLL

Input

CLKOP

CLKOS GPLL

Note: This diagram shows sources for the XP2-17 device. Smaller LatticeXP2 devices have two GPLLs.

2-12

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

Primary Clock Routing

The clock routing structure in LatticeXP2 devices consists of a network of eight primary clock lines (CLK0 through

CLK7) per quadrant. The primary clocks of each quadrant are generated from muxes located in the center of the

device. All the clock sources are connected to these muxes. Figure 2-9 shows the clock routing for one quadrant.

Each quadrant mux is identical. If desired, any clock can be routed globally.

Figure 2-9. Per Quadrant Primary Clock Selection

Dynamic Clock Select (DCS)

The DCS is a smart multiplexer function available in the primary clock routing. It switches between two independent

input clock sources without any glitches or runt pulses. This is achieved irrespective of when the select signal is

toggled. There are two DCS blocks per quadrant; in total, eight DCS blocks per device. The inputs to the DCS block

come from the center muxes. The output of the DCS is connected to primary clocks CLK6 and CLK7 (see Figure 2-

9).

Figure 2-10 shows the timing waveforms of the default DCS operating mode. The DCS block can be programmed

to other modes. For more information on the DCS, please see TN1126, LatticeXP2 sysCLOCK PLL Design and

Usage Guide.

Figure 2-10. DCS Waveforms

Secondary Clock/Control Routing

Secondary clocks in the LatticeXP2 devices are region-based resources. The benefit of region-based resources is

the relatively low injection delay and skew within the region, as compared to primary clocks. EBR rows, DSP rows

and a special vertical routing channel bound the secondary clock regions. This special vertical routing channel

aligns with either the left edge of the center DSP block in the DSP row or the center of the DSP row. Figure 2-11

shows this special vertical routing channel and the eight secondary clock regions for the LatticeXP2-40.

CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7

30:1 30:1 30:1 30:1 29:1 29:1 29:1 29:130:1 30:1

8 Primary Clocks (CLK0 to CLK7) per Quadrant

DCS DCS

Primary Clock Sources: PLLs + CLKDIVs + PIOs + Routing

CLK0

SEL

DCSOUT

CLK1

2-13

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

LatticeXP2-30 and smaller devices have six secondary clock regions. All devices in the LatticeXP2 family have four

secondary clocks (SC0 to SC3) which are distributed to every region.

The secondary clock muxes are located in the center of the device. Figure 2-12 shows the mux structure of the

secondary clock routing. Secondary clocks SC0 to SC3 are used for clock and control and SC4 to SC7 are used for

high fan-out signals.

Figure 2-11. Secondary Clock Regions XP2-40

I/O Bank 0

I/O Bank 7

I/O Bank 2 I/O Bank 3

I/O Bank 6

I/O Bank 1

I/O Bank 5 I/O Bank 4

Secondary Clock

Region 1

Secondary Clock

Region 2

Secondary Clock

Region 3

Secondary Clock

Region 4

Secondary Clock

Region 5

Secondary Clock

Region 6

Secondary Clock

Region 7

Secondary Clock

Region 8

Vertical Routing

Channel Regional

Boundary

DSP Row

Regional

Boundary

EBR Row

Regional

Boundary

EBR Row

Regional

Boundary

2-14

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

Figure 2-12. Secondary Clock Selection

Slice Clock Selection

Figure 2-13 shows the clock selections and Figure 2-14 shows the control selections for Slice0 through Slice2. All

the primary clocks and the four secondary clocks are routed to this clock selection mux. Other signals, via routing,

can be used as clock inputs to the slices. Slice controls are generated from the secondary clocks or other signals

connected via routing.

If none of the signals are selected for both clock and control, then the default value of the mux output is 1. Slice 3

does not have any registers; therefore it does not have the clock or control muxes.

Figure 2-13. Slice0 through Slice2 Clock Selection

SC0 SC1 SC2 SC3 SC4 SC5

24:1 24:1 24:1

SC6 SC7

24:1 24:1 24:1 24:1 24:1

4 Secondary Clocks/CE/LSR (SC0 to SC3) per Region

Clock/Control

Secondary Clock Feedlines: 8 PIOs + 16 Routing

High Fan-out Data

4 High Fan-out Data Signals (SC4 to SC7) per Region

Clock to Slice

Primary Clock

Secondary Clock

Routing

Vcc

25:1

2-15

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

Figure 2-14. Slice0 through Slice2 Control Selection

Edge Clock Routing

LatticeXP2 devices have eight high-speed edge clocks that are intended for use with the PIOs in the implementa-

tion of high-speed interfaces. Each device has two edge clocks per edge. Figure 2-15 shows the selection muxes

for these clocks.

Figure 2-15. Edge Clock Mux Connections

Slice Control

Secondary Clock

Routing

Vcc

16:1

Left and Right

Edge Clocks

ECLK1

Top and Bottom

Edge Clocks

ECLK1/ ECLK2

Clock Input Pad

Routing

Input Pad

GPLL Input Pad

GPLL Output CLKOP

Left and Right

Edge Clocks

ECLK2

Routing

Input Pad

GPLL Input Pad

GPLL Output CLKOS

(Both Muxes)

2-16

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

sysMEM Memory

LatticeXP2 devices contains a number of sysMEM Embedded Block RAM (EBR). The EBR consists of 18 Kbit

RAM with dedicated input and output registers.

sysMEM Memory Block

The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in

a variety of depths and widths as shown in Table 2-5. FIFOs can be implemented in sysMEM EBR blocks by using

support logic with PFUs. The EBR block supports an optional parity bit for each data byte to facilitate parity check-

ing. EBR blocks provide byte-enable support for configurations with18-bit and 36-bit data widths.

Table 2-5. sysMEM Block Configurations

Bus Size Matching

All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB

word 0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for

each port varies, this mapping scheme applies to each port.

FlashBAK EBR Content Storage

All the EBR memory in the LatticeXP2 is shadowed by Flash memory. Optionally, initialization values for the mem-

ory blocks can be defined using the Lattice Diamond design tools. The initialization values are loaded into the Flash

memory during device programming and into the SRAM at power up or whenever the device is reconfigured. This

feature is ideal for the storage of a variety of information such as look-up tables and microprocessor code. It is also

possible to write the current contents of the EBR memory back to Flash memory. This capability is useful for the

storage of data such as error codes and calibration information. For additional information on the FlashBAK capa-

bility see TN1137, LatticeXP2 Memory Usage Guide.

Memory Mode Configurations

Single Port

16,384 x 1

8,192 x 2

4,096 x 4

2,048 x 9

1,024 x 18

512 x 36

True Dual Port

16,384 x 1

8,192 x 2

4,096 x 4

2,048 x 9

1,024 x 18

Pseudo Dual Port

16,384 x 1

8,192 x 2

4,096 x 4

2,048 x 9

1,024 x 18

512 x 36

2-17

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

Figure 2-16. FlashBAK Technology

Memory Cascading

Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools

cascade memory transparently, based on specific design inputs.

Single, Dual and Pseudo-Dual Port Modes

In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory

array. The output data of the memory is optionally registered at the output.

EBR memory supports two forms of write behavior for single port or dual port operation:

1. Normal – Data on the output appears only during a read cycle. During a write cycle, the data (at the current

address) does not appear on the output. This mode is supported for all data widths.

2. Write Through – A copy of the input data appears at the output of the same port during a write cycle. This

mode is supported for all data widths.

Memory Core Reset

The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-

nously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A

and Port B respectively. GSRN, the global reset signal, resets both ports. The output data latches and associated

resets for both ports are as shown in Figure 2-17.

Figure 2-17. Memory Core Reset

Flash

EBR

JTAG / SPI Port

FPGA Logic

Write From Flash to

EBR During Configuration /

Write From EBR to Flash

on User Command

Make Infinite Reads and

Writes to EBR

Write to Flash During

Programming

SET

CLR

Output Data

Latches

Memory Core

Port A[17:0]

SET

Port B[17:0]

RSTB

GSRN

Pro

rammable Disable

RSTA

CLR

2-18

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

For further information on the sysMEM EBR block, please see TN1137, LatticeXP2 Memory Usage Guide.

EBR Asynchronous Reset

EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the

reset is applied and released a clock cycle after the low-to-high transition of the reset signal, as shown in Figure 2-18.

The GSR input to the EBR is always asynchronous.

Figure 2-18. EBR Asynchronous Reset (Including GSR) Timing Diagram

If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after

the EBR read and write clock inputs are in a steady state condition for a minimum of 1/fMAX (EBR clock). The reset

release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.

If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during

device Wake Up must occur before the release of the device I/Os becoming active.

These instructions apply to all EBR RAM and ROM implementations.

Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled.

sysDSP™ Block

The LatticeXP2 family provides a sysDSP block making it ideally suited for low cost, high performance Digital Sig-

nal Processing (DSP) applications. Typical functions used in these applications include Bit Correlators, Fast Fourier

Transform (FFT) functions, Finite Impulse Response (FIR) Filter, Reed-Solomon Encoder/Decoder, Turbo Encoder/

Decoder and Convolutional Encoder/Decoder. These complex signal processing functions use similar building

blocks such as multiply-adders and multiply-accumulators.

sysDSP Block Approach Compare to General DSP

Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with

fixed data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by

higher clock speeds. The LatticeXP2 family, on the other hand, has many DSP blocks that support different data-

widths. This allows the designer to use highly parallel implementations of DSP functions. The designer can opti-

mize the DSP performance vs. area by choosing appropriate levels of parallelism. Figure 2-19 compares the fully

serial and the mixed parallel and serial implementations.

Reset

Clock

Enable

2-19

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

Figure 2-19. Comparison of Gene ral DSP and LatticeXP2 Approaches

sysDSP Block Capabilities

The sysDSP block in the LatticeXP2 family supports four functional elements in three 9, 18 and 36 data path

widths. The user selects a function element for a DSP block and then selects the width and type (signed/unsigned)

of its operands. The operands in the LatticeXP2 family sysDSP Blocks can be either signed or unsigned but not

mixed within a function element. Similarly, the operand widths cannot be mixed within a block. DSP elements can

be concatenated.

The resources in each sysDSP block can be configured to support the following four elements:

• MULT (Multiply)

• MAC (Multiply, Accumulate)

• MULTADDSUB (Multiply, Addition/Subtraction)

• MULTADDSUBSUM (Multiply, Addition/Subtraction, Accumulate)

The number of elements available in each block depends on the width selected from the three available options: x9,

x18, and x36. A number of these elements are concatenated for highly parallel implementations of DSP functions.

Table 2-6 shows the capabilities of the block.

Table 2-6. Maximum Number of Elements in a Block

Some options are available in four elements. The input register in all the elements can be directly loaded or can be

loaded as shift register from previous operand registers. By selecting ‘dynamic operation’ the following operations

are possible:

Width of Multiply x9 x18 x36

MULT 841

MAC 2 2 —

MULTADDSUB 4 2 —

MULTADDSUBSUM 2 1 —

Multiplier 0

Operand

Multiplier 1 Multiplier k

(k adds)

Output

m/k

loops

Single

Multiplier x

Operand

Accumulator

Operand

M loops

Function implemented in

General purpose DSP

Function implemented

in LatticeXP2

m/k

accumulate

2-20

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

• In the ‘Signed/Unsigned’ options the operands can be switched between signed and unsigned on every cycle.

• In the ‘Add/Sub’ option the Accumulator can be switched between addition and subtraction on every cycle.

• The loading of operands can switch between parallel and serial operations.

MULT sysDSP Element

This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, A and B,

are multiplied and the result is available at the output. The user can enable the input/output and pipeline registers.

Figure 2-20 shows the MULT sysDSP element.

Figure 2-20. MULT sysDSP Element

Multiplier

m+n

(default)

CLK (CLK0,CLK1,CLK2,CLK3)

CE (CE0,CE1,CE2,CE3)

RST(RST0,RST1,RST2,RST3)

Pipeline

Input

Multiplier

Multiplicand

Signed A

Shift Register A InShift Register B In

Shift Register A OutShift Register B Out

Output

Input Data

Output

Multiplier

Input

Signed B To

Multiplier

2-21

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

MAC sysDSP Element

In this case, the two operands, A and B, are multiplied and the result is added with the previous accumulated value.

This accumulated value is available at the output. The user can enable the input and pipeline registers but the out-

put register is always enabled. The output register is used to store the accumulated value. The Accumulators in the

DSP blocks in LatticeXP2 family can be initialized dynamically. A registered overflow signal is also available. The

overflow conditions are provided later in this document. Figure 2-21 shows the MAC sysDSP element.

Figure 2-21. MAC sysDSP

Multiplier

Input Data

Output

Accumulator

Multiplier

Multiplicand

Signed A

Serial Register B in Serial Register A in

SROB SROA

Output

Addn

Accumsload

Pipeline

CLK (CLK0,CLK1,CLK2,CLK3)

CE (CE0,CE1,CE2,CE3)

RST(RST0,RST1,RST2,RST3)

Input

Pipeline

Input

Pipeline

Input

Pipeline

To Accumulator

Signed B Pipeline

Input To Accumulator

To Accumulator

Overflow

signal

m+n

(default)

m+n+16

(default)

m+n+16

(default)

Preload

2-22

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

MULTADDSUB sysDSP Element

In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi-

plier operation of operands A1 and B1. The user can enable the input, output and pipeline registers. Figure 2-22

shows the MULTADDSUB sysDSP element.

Figure 2-22. MULTADDSUB

Multiplier

Add/Sub

Pipe

Reg

Pipe

Reg

m+n

(default)

m+n+1

(default)

m+n+1

(default)

m+n

(default)

Multiplier B0

Multiplicand A0

Multiplier B1

Multiplicand A1

Signed A

Shift Register A InShift Register B In

Shift Register A OutShift Register B Out

Output

Addn

Pipeline

CLK (CLK0,CLK1,CLK2,CLK3)

CE (CE0,CE1,CE2,CE3)

RST (RST0,RST1,RST2,RST3)

Input

Pipeline

Input

Pipeline

Pipe

Reg

Signed B Pipeline

Input

Input Data

Output

To Add/Sub

2-23

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

MULTADDSUBSUM sysDSP Element

In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi-

plier operation of operands A1 and B1. Additionally the operands A2 and B2 are multiplied and the result is added/

subtracted with the result of the multiplier operation of operands A3 and B3. The result of both addition/subtraction

are added in a summation block. The user can enable the input, output and pipeline registers. Figure 2-23 shows

the MULTADDSUBSUM sysDSP element.

Figure 2-23. MULTADDSUBSUM

Clock, Clock Enable and Reset Resources

Global Clock, Clock Enable (CE) and Reset (RST) signals from routing are available to every DSP block. From four

clock sources (CLK0, CLK1, CLK2, CLK3) one clock is selected for each input register, pipeline register and output

Multiplier

Add/Sub0

mm+n

(default)

m+n

(default)

m+n+1

m+n+2 m+n+2

m+n+1

m+n

(default)

m+n

(default)

Multiplier

Add/Sub1

SUM

Multiplier B0

Multiplicand A0

Multiplier B1

Multiplicand A1

Multiplier B2

Multiplicand A2

Multiplier B3

Multiplicand A3

Signed A

Shift Register B In

Output

Addn0

Pipeline

CLK (CLK0,CLK1,CLK2,CLK3)

CE (CE0,CE1,CE2,CE3)

RST(RST0,RST1,RST2,RST3)

Input

Pipeline

Input

To Add/Sub0

To Add/Sub0, Add/Sub1

Pipeline

Signed B Pipeline

Input

Pipeline

Input

To Add/Sub1

Addn1

Pipeline

Shift Register A In

Shift Register B Out Shift Register A Out

Input Data

Output

2-24

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

RST1, RST2, RST3) at each input register, pipeline register and output register.

Signed and Unsigned with Different Wi dths

The DSP block supports other widths, in addition to x9, x18 and x36 widths, of signed and unsigned multipliers. For

unsigned operands, unused upper data bits should be filled to create a valid x9, x18 or x36 operand. For signed

two’s complement operands, sign extension of the most significant bit should be performed until x9, x18 or x36

width is reached. Table 2-7 provides an example of this.

Table 2-7. Sign Extension Example

OVERFLOW Flag from MAC

The sysDSP block provides an overflow output to indicate that the accumulator has overflowed. “Roll-over” occurs

and an overflow signal is indicated when any of the following is true: two unsigned numbers are added and the

result is a smaller number than the accumulator, two positive numbers are added with a negative sum or two nega-

tive numbers are added with a positive sum. Note that when overflow occurs the overflow flag is present for only

one cycle. By counting these overflow pulses in FPGA logic, larger accumulators can be constructed. The condi-

tions for the overflow signal for signed and unsigned operands are listed in Figure 2-24.

Figure 2-24. Accumula tor Overflow/Underflow

Number Unsigned Unsigned

9-bit Unsigned

18-bit Signed

Two’s Complement

Signed 9 Bits Two’s Complement

Signed 18 Bits

+5 0101 000000101 000000000000000101 0101 000000101 000000000000000101

-6 N/A N/A N/A 1010 111111010 111111111111111010

000000000

000000001

000000010

000000011

111111101

111111110

111111111

Overflow signal is generated

for one cycle when this

boundary is crossed

-3

-2

-1

Unsigned Operation

Signed Operation

255

254

253

252

-254

-255

-256

000000000

000000001

000000010

000000011

111111101

111111110

111111111

Carry signal is generated for

one cycle when this

boundary is crossed

509

510

511

255

254

253

252

258

257

256

011111100

011111101

011111110

011111111

100000000

100000001

100000010

011111100

011111101

011111110

011111111

100000000

100000001

100000010

2-25

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

IPexpress™

The user can access the sysDSP block via the Lattice IPexpress tool, which provides the option to configure each

DSP module (or group of modules), or by direct HDL instantiation. In addition, Lattice has partnered with The Math-

Works® to support instantiation in the Simulink® tool, a graphical simulation environment. Simulink works with Dia-

mond to dramatically shorten the DSP design cycle in Lattice FPGAs.

Optimized DSP Functions

Lattice provides a library of optimized DSP IP functions. Some of the IP cores planned for the LatticeXP2 DSP

include the Bit Correlator, FFT functions, FIR Filter, Reed-Solomon Encoder/Decoder, Turbo Encoder/Decoder and

Convolutional Encoder/Decoder. Please contact Lattice to obtain the latest list of available DSP IP cores.

Resources Available in the LatticeXP2 Family

Table 2-8 shows the maximum number of multipliers for each member of the LatticeXP2 family. Table 2-9 shows the

maximum available EBR RAM Blocks and Serial TAG Memory bits in each LatticeXP2 device. EBR blocks,

together with Distributed RAM can be used to store variables locally for fast DSP operations.

Table 2-8. Maximum Number of DSP Blocks in the LatticeXP2 Family

Table 2-9. Embedded SRAM/TAG Memory in the LatticeXP2 Family

LatticeXP2 DSP Performance

Table 2-10 lists the maximum performance in Millions of MAC (MMAC) operations per second for each member of

the LatticeXP2 family.

Table 2-10. DSP Performance

For further information on the sysDSP block, please see TN1140, LatticeXP2 sysDSP Usage Guide.

Device DSP Block 9x9 Multiplier 18x18 Multiplier 36x36 Multiplier

XP2-5 3 24 12 3

XP2-8 4 32 16 4

XP2-17 5 40 20 5

XP2-30 7 56 28 7

XP2-40 8 64 32 8

Device EBR SRAM Block

Total EBR SRAM

(Kbits ) TAG Memory

(Bits)

XP2-5 9 166 632

XP2-8 12 221 768

XP2-17 15 276 2184

XP2-30 21 387 2640

XP2-40 48 885 3384

Device DSP Block

DSP Performance

MMAC

XP2-5 3 3,900

XP2-8 4 5,200

XP2-17 5 6,500

XP2-30 7 9,100

XP2-40 8 10,400

2-26

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

Programmable I/O Cells (PIC)

Each PIC contains two PIOs connected to their respective sysIO buffers as shown in Figure 2-25. The PIO Block

supplies the output data (DO) and the tri-state control signal (TO) to the sysIO buffer and receives input from the

buffer. Table 2-11 provides the PIO signal list.

Figure 2-25. PIC Diagram

Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”) as shown in Figure 2-25.

The PAD Labels “T” and “C” distinguish the two PIOs. Approximately 50% of the PIO pairs on the left and right

edges of the device can be configured as true LVDS outputs. All I/O pairs can operate as inputs.

OPOS1

ONEG1

INCK

INDD

INFF

IPOS0

IPOS1

CLK

LSR

GSRN

CLK1

CLK0

CEO

CEI

sysIO

Buffer

PADA

“T”

PADB

“C”

LSR

GSR

ECLK1

DDRCLKPOL

1. Signals are available on left/right/bottom edges only.

2. Selected blocks.

IOLD0

Tristate

Block

Output

Block

Input

Block

Control

Muxes

PIOB

PIOA

OPOS0

OPOS2

ONEG0

ONEG2

DQSXFER

DQS

DEL

QPOS1

QNEG1

QNEG0

QPOS0

IOLT0

ECLK2

2-27

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

Table 2-11. PIO Signal List

PIO

The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic

block. These blocks contain registers for operating in a variety of modes along with necessary clock and selection

logic.

Input Register Block

The input register blocks for PIOs contain delay elements and registers that can be used to condition high-speed

interface signals, such as DDR memory interfaces and source synchronous interfaces, before they are passed to

the device core. Figure 2-26 shows the diagram of the input register block.

Input signals are fed from the sysIO buffer to the input register block (as signal DI). If desired, the input signal can

bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and,

in selected blocks, the input to the DQS delay block. If an input delay is desired, designers can select either a fixed

delay or a dynamic delay DEL[3:0]. The delay, if selected, reduces input register hold time requirements when

using a global clock.

The input block allows three modes of operation. In the Single Data Rate (SDR) mode, the data is registered, by

one of the registers in the SDR Sync register block, with the system clock. In DDR mode two registers are used to

sample the data on the positive and negative edges of the DQS signal which creates two data streams, D0 and D2.

D0 and D2 are synchronized with the system clock before entering the core. Further information on this topic can

be found in the DDR Memory Support section of this data sheet.

By combining input blocks of the complementary PIOs and sharing registers from output blocks, a gearbox function

can be implemented, that takes a double data rate signal applied to PIOA and converts it as four data streams,

IPOS0A, IPOS1A, IPOS0B and IPOS1B. Figure 2-26 shows the diagram using this gearbox function. For more

information on this topic, please see TN1138, LatticeXP2 High Speed I/O Interface.

Name Type Description

CE Control from the core Clock enables for input and output block flip-flops

CLK Control from the core System clocks for input and output blocks

ECLK1, ECLK2 Control from the core Fast edge clocks

LSR Control from the core Local Set/Reset

GSRN Control from routing Global Set/Reset (active low)

INCK2 Input to the core Input to Primary Clock Network or PLL reference inputs

DQS Input to PIO DQS signal from logic (routing) to PIO

INDD Input to the core Unregistered data input to core

INFF Input to the core Registered input on positive edge of the clock (CLK0)

IPOS0, IPOS1 Input to the core Double data rate registered inputs to the core

QPOS01, QPOS11 Input to the core Gearbox pipelined inputs to the core

QNEG01, QNEG11Input to the core Gearbox pipelined inputs to the core

OPOS0, ONEG0,

OPOS2, ONEG2 Output data from the core Output signals from the core for SDR and DDR operation

OPOS1 ONEG1 Tristate control from the core Signals to Tristate Register block for DDR operation

DEL[3:0] Control from the core Dynamic input delay control bits

TD Tristate control from the core Tristate signal from the core used in SDR operation

DDRCLKPOL Control from clock polarity bus Controls the polarity of the clock (CLK0) that feed the DDR input block

DQSXFER Control from core Controls signal to the Output block

1. Signals available on left/right/bottom only.

2. Selected I/O.

2-28

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures ade-

quate timing when data is transferred from the DQS to system clock domain. For further discussion on this topic,

see the DDR Memory section of this data sheet.

Figure 2-26. Input Register Block

Output Register Block

The output register block provides the ability to register signals from the core of the device before they are passed

to the sysIO buffers. The blocks on the PIOs on the left, right and bottom contain registers for SDR operation that

are combined with an additional latch for DDR operation. Figure 2-27 shows the diagram of the Output Register

Block for PIOs.

In SDR mode, ONEG0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as a D-

type or latch. In DDR mode, ONEG0 and OPOS0 are fed into registers on the positive edge of the clock. At the next

clock cycle the registered OPOS0 is latched. A multiplexer running off the same clock cycle selects the correct reg-

ister to feed the output (D0).

By combining output blocks of the complementary PIOs and sharing some registers from input blocks, a gearbox

function can be implemented, to take four data streams ONEG0A, ONEG1A, ONEG1B and ONEG1B. Figure 2-27

Clock Transfer Registers

SDR & Sync

Registers

DDR Registers

D-Type

/LATCH

D-Type

1DQ

Fixed Delay

Dynamic Delay

(From sysIO

Buffer)

(From sysIO

Buffer)

INCK2

INDD

IPOS0A

QPOS0A

IPOS1A

QPOS1A

DEL [3:0]

CLK0 (of PIO A)

Delayed

DQS 0

CLKA

1DQ

Fixed Delay

Dynamic Delay

INCK2

INDD

IPOS0B

QPOS0B

IPOS1B

QPOS1B

DEL [3:0]

CLK0 (of PIO B)

Delayed

DQS

CLKB

/LATCH

True PIO (A) in LVDS I/O Pair

Comp PIO (B) in LVDS I/O Pair

D-Type1

D-Type

/LATCH

D-Type

/LATCH

D-Type1

From

Routing

D1 D2

DDR Registers SDR & Sync

Registers

DDRSRC

Gearbox Configuration Bit

DDRCLKPOL

1. Shared with output register

2. Selected PIO.

Note: Simplified version does not

show CE and SET/RESET details

From

Routing

To DQS Delay Block2

D-TypeD-Type

D-Type

2-29

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

shows the diagram using this gearbox function. For more information on this topic, see TN1138, LatticeXP2 High

Speed I/O Interface.

Figure 2-27. Output and Tristate Block

Clock Transfer

Registers

ONEG1

CLKA

OPOS1

From Routing

DQDQ

D-Type

Latch

ONEG0

OPOS0

Programmable

Control

Programmable

Control

ECLK1

ECLK2

CLK1

Tristate Logic

Output Logic

True PIO (A) in LVDS I/O Pair

To sysIO Buffer

ONEG1

CLKB

OPOS1

From Routing

D-Type

/LATCH

D-Type

/LATCH

D-Type

/LATCH

D-Type

/LATCH

DQDQ

Latch D-Type

D-Type Latch

Latch

D-Type Latch

ONEG0

OPOS0

ECLK1

ECLK2

CLK1

Output Logic

To sysIO Buffer

Comp PIO (B) in LVDS I/O Pair

(CLKB)

(CLKA)

D-Type

D-Type*

Clock Transfer

Registers

DDR Output

Registers

DDR Output

Registers

* Shared with input register Note: Simplified version does not show CE and SET/RESET details

DQSXFER

2-30

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

Tristate Register Block

The tristate register block provides the ability to register tri-state control signals from the core of the device before

they are passed to the sysIO buffers. The block contains a register for SDR operation and an additional latch for

DDR operation. Figure 2-27 shows the Tristate Register Block with the Output Block

In SDR mode, ONEG1 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as D-

type or latch. In DDR mode, ONEG1 and OPOS1 are fed into registers on the positive edge of the clock. Then in

the next clock the registered OPOS1 is latched. A multiplexer running off the same clock cycle selects the correct

Control Logic Block

The control logic block allows the selection and modification of control signals for use in the PIO block. A clock sig-

nal is selected from general purpose routing, ECLK1, ECLK2 or a DQS signal (from the programmable DQS pin)

and is provided to the input register block. The clock can optionally be inverted.

DDR Memory Support

PICs have additional circuitry to allow implementation of high speed source synchronous and DDR memory inter-

faces.

PICs have registered elements that support DDR memory interfaces. Interfaces on the left and right edges are

designed for DDR memories that support 16 bits of data, whereas interfaces on the top and bottom are designed

for memories that support 18 bits of data. One of every 16 PIOs on the left and right and one of every 18 PIOs on

the top and bottom contain delay elements to facilitate the generation of DQS signals. The DQS signals feed the

DQS buses which span the set of 16 or 18 PIOs. Figure 2-28 and Figure 2-29 show the DQS pin assignments in

each set of PIOs.

The exact DQS pins are shown in a dual function in the Logic Signal Connections table in this data sheet. Addi-

tional detail is provided in the Signal Descriptions table. The DQS signal from the bus is used to strobe the DDR

data from the memory into input register blocks. For additional information on using DDR memory support please

see TN1138, LatticeXP2 High Speed I/O Interface.

2-31

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

Figure 2-28. DQS Input Routing (Left and Right)

Figure 2-29. DQS Input Routing (Top and Bottom)

PIO B

PIO A

PIO B

PIO A

Assigned

DQS Pin

DQS

Delay

sysIO

Buffer PADA "T"

PADB "C"

LVDS Pair

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

PIO B

PIO A

PIO B

PIO A

Assigned

DQS Pin

DQS

Delay

sysIO

Buffer PADA "T"

PADB "C"

LVDS Pair

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

PIO B

PIO A

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

2-32

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

DLL Calibrated DQS Delay Block

Source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at

the input register. For most interfaces a PLL is used for this adjustment. However, in DDR memories the clock,

referred to as DQS, is not free-running, and this approach cannot be used. The DQS Delay block provides the

required clock alignment for DDR memory interfaces.

The DQS signal (selected PIOs only, as shown in Figure 2-30) feeds from the PAD through a DQS delay element to

a dedicated DQS routing resource. The DQS signal also feeds polarity control logic which controls the polarity of

the clock to the sync registers in the input register blocks. Figure 2-30 and Figure 2-31 show how the DQS transi-

tion signals are routed to the PIOs.

The temperature, voltage and process variations of the DQS delay block are compensated by a set of 6-bit bus cal-

ibration signals from two dedicated DLLs (DDR_DLL) on opposite sides of the device. Each DLL compensates

DQS delays in its half of the device as shown in Figure 2-30. The DLL loop is compensated for temperature, volt-

age and process variations by the system clock and feedback loop.

Figure 2-30. Edge Clock, DLL Calibration and DQS Local Bus Distribution

I/O Bank 5

I/O Bank 6 I/O Bank 7

I/O Bank 2 I/O Bank 3

I/O Bank 4

I/O Bank 0 I/O Bank 1

DDR_DLL

(Right)

DDR_DLL

(Left)

ECLK1

ECLK2

Delayed

DQS

Polarity Control

DQSXFER

DQS Delay

Control Bus

DQS Input

Spans 18 PIOs

Top & Bottom

Sides

Spans 16 PIOs

Left & Right Sides

2-33

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

Figure 2-31. DQS Local Bus

Polarity Control Logic

In a typical DDR memory interface design, the phase relationship between the incoming delayed DQS strobe and

the internal system clock (during the READ cycle) is unknown. The LatticeXP2 family contains dedicated circuits to

transfer data between these domains. To prevent set-up and hold violations, at the domain transfer between DQS

(delayed) and the system clock, a clock polarity selector is used. This changes the edge on which the data is regis-

tered in the synchronizing registers in the input register block and requires evaluation at the start of each READ

cycle for the correct clock polarity.

Prior to the READ operation in DDR memories, DQS is in tristate (pulled by termination). The DDR memory device

drives DQS low at the start of the preamble state. A dedicated circuit detects this transition. This signal is used to

control the polarity of the clock to the synchronizing registers.

sysIO

Buffer

DDR

Datain

PAD

CLK1

CEI

PIO

sysIO

Buffer

GSR

DQS

To Sync

Reg.

DQS To DDR

Reg.

DQS

Strobe

PAD

PIO

DQSDEL

Polarity Control

Logic

DQS

Calibration bus

from DLL

DQSXFER

Output

Input

DQSXFER

DCNTL[6:0]

Polarity control

DQS

DQSXFERDEL*

DQSXFER

DCNTL[6:0]

*DQSXFERDEL shifts ECLK1 by 90% and is not associated with a particular PIO.

DCNTL[6:0]

ECLK1

CLK1

ECLK2

ECLK1

2-34

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

DQSXFER

LatticeXP2 devices provide a DQSXFER signal to the output buffer to assist it in data transfer to DDR memories

that require DQS strobe be shifted 90o. This shifted DQS strobe is generated by the DQSDEL block. The

DQSXFER signal runs the span of the data bus.

sysIO Buffer

Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the

periphery of the device in groups referred to as banks. The sysIO buffers allow users to implement the wide variety

of standards that are found in today’s systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL.

sysIO Buffer Banks

LatticeXP2 devices have eight sysIO buffer banks for user I/Os arranged two per side. Each bank is capable of sup-

porting multiple I/O standards. Each sysIO bank has its own I/O supply voltage (VCCIO). In addition, each bank has

voltage references, VREF1 and VREF2, that allow it to be completely independent from the others. Figure 2-32

shows the eight banks and their associated supplies.

In LatticeXP2 devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS and PCI) are pow-

ered using VCCIO. LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as fixed threshold inputs inde-

pendent of VCCIO.

Each bank can support up to two separate VREF voltages, VREF1 and VREF2, that set the threshold for the refer-

enced input buffers. Some dedicated I/O pins in a bank can be configured to be a reference voltage supply pin.

Each I/O is individually configurable based on the bank’s supply and reference voltages.

Figure 2-32. LatticeXP2 Banks

VREF1(2)

GND

Bank 2

VCCIO2

VREF2(2)

VREF1(3)

GND

Bank 3

VCCIO3

VREF2(3)

VREF1(7)

GND

Bank 7

VCCIO7

VREF2(7)

VREF1(6)

GND

Bank 6

VCCIO6

VREF2(6)

Bank 5 Bank 4

VREF1(0)

GND

Bank 0

VCCIO0

VREF2(0)

VREF1(1)

GND

Bank 1

VCCIO1

VREF2(1)

LEFT

RIGHT

TOP

VREF1(5)

GND

VCCIO5

VREF2(5)

VREF1(4)

GND

VCCIO4

VREF2(4)

BOTTOM

2-35

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

LatticeXP2 devices contain two types of sysIO buffer pairs.

1. Top and Bottom (Banks 0, 1, 4 and 5) sysIO Buffer Pairs (Single-Ended Outputs Only)

The sysIO buffer pairs in the top banks of the device consist of two single-ended output drivers and two sets of

single-ended input buffers (both ratioed and referenced). One of the referenced input buffers can also be con-

figured as a differential input. 



The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive

side of the differential input buffer and the comp (complementary) pad is associated with the negative side of

the differential input buffer. 



Only the I/Os on the top and bottom banks have programmable PCI clamps.

2. Lef t and Rig ht (Banks 2, 3, 6 and 7) sysIO Buffer Pa irs (50% Diffe rential and 100% Single- Ended Output s) 

The sysIO buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two

sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. One of the ref-

erenced input buffers can also be configured as a differential input. 



The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive

side of the differential I/O, and the comp pad is associated with the negative side of the differential I/O. 



LVDS differential output drivers are available on 50% of the buffer pairs on the left and right banks.

Typical sysIO I/O Behavior During Power-up

The internal power-on-reset (POR) signal is deactivated when VCC and VCCAUX have reached satisfactory levels.

After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to ensure

that all other VCCIO banks are active with valid input logic levels to properly control the output logic states of all the

I/O banks that are critical to the application. For more information on controlling the output logic state with valid

input logic levels during power-up in LatticeXP2 devices, please see TN1136, LatticeXP2 sysIO Usage Guide.

The VCC and VCCAUX supply the power to the FPGA core fabric, whereas the VCCIO supplies power to the I/O buf-

fers. In order to simplify system design while providing consistent and predictable I/O behavior, it is recommended

that the I/O buffers be powered-up prior to the FPGA core fabric. VCCIO supplies should be powered-up before or

together with the VCC and VCCAUX supplies.

Supported sysIO Standards

The LatticeXP2 sysIO buffer supports both single-ended and differential standards. Single-ended standards can be

further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 1.2V, 1.5V,

1.8V, 2.5V and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individual configuration options

for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain. Other

single-ended standards supported include SSTL and HSTL. Differential standards supported include LVDS,

MLVDS, BLVDS, LVPECL, RSDS, differential SSTL and differential HSTL. Tables 2-12 and 2-13 show the I/O stan-

dards (together with their supply and reference voltages) supported by LatticeXP2 devices. For further information

on utilizing the sysIO buffer to support a variety of standards please see TN1136, LatticeXP2 sysIO Usage Guide.

2-36

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

Table 2-12. Supported Input Standards

Input Standard VREF (Nom.) VCCIO1 (Nom.)

Single Ended Interfaces

LVTTL — —

LVCMOS3 3 — —

LVCMOS2 5 — —

LVCMOS1 8 — 1.8

LVCMOS1 5 — 1.5

LVCMOS1 2 — —

PCI33 — —

HSTL18 Class I, II 0.9 —

HSTL15 Class I 0.75 —

SSTL33 Class I, II 1.5 —

SSTL25 Class I, II 1.25 —

SSTL18 Class I, II 0.9 —

Differential Interfaces

Differential SSTL18 Class I, II — —

Differential SSTL25 Class I, II — —

Differential SSTL33 Class I, II — —

Differential HSTL15 Class I — —

Differential HSTL18 Class I, II — —

LVDS, MLVDS, LVPECL, BLVDS, RSDS — —

1. When not specified, VCCIO can be set anywhere in the valid operating range (page 3-1).

2-37

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

Table 2-13. Supported Output Standards

Hot Socketing

LatticeXP2 devices have been carefully designed to ensure predictable behavior during power-up and power-

down. Power supplies can be sequenced in any order. During power-up and power-down sequences, the I/Os

remain in tri-state until the power supply voltage is high enough to ensure reliable operation. In addition, leakage

into I/O pins is controlled to within specified limits. This allows for easy integration with the rest of the system.

These capabilities make the LatticeXP2 ideal for many multiple power supply and hot-swap applications.

IEEE 1149.1-Compliant Boundary Scan Testability

All LatticeXP2 devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant Test Access

Port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan

path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in

Output Standard Drive VCCIO (Nom.)

Single-ended Interfaces

LVTTL 4mA, 8mA, 12mA, 16mA, 20mA 3.3

LVCMOS33 4mA, 8mA, 12mA 16mA, 20mA 3.3

LVCMOS25 4mA, 8mA, 12mA, 16mA, 20mA 2.5

LVCMOS18 4mA, 8mA, 12mA, 16mA 1.8

LVCMOS15 4mA, 8mA 1.5

LVCMOS12 2mA, 6mA 1.2

LVCMOS33, Open Drain 4mA, 8mA, 12mA 16mA, 20mA —

LVCMOS25, Open Drain 4mA, 8mA, 12mA 16mA, 20mA —

LVCMOS18, Open Drain 4mA, 8mA, 12mA 16mA —

LVCMOS15, Open Drain 4mA, 8mA —

LVCMOS12, Open Drain 2mA, 6mA —

PCI33 N/A 3.3

HSTL18 Class I, II N/A 1.8

HSTL15 Class I N/A 1.5

SSTL33 Class I, II N/A 3.3

SSTL25 Class I, II N/A 2.5

SSTL18 Class I, II N/A 1.8

Differential Interfaces

Differential SSTL33, Class I, II N/A 3.3

Differential SSTL25, Class I, II N/A 2.5

Differential SSTL18, Class I, II N/A 1.8

Differential HSTL18, Class I, II N/A 1.8

Differential HSTL15, Class I N/A 1.5

LVDS1, 2 N/A 2.5

MLVDS1N/A 2.5

BLVDS1N/A 2.5

LVPECL1N/A 3.3

RSDS1N/A 2.5

LVCMOS33D14mA, 8mA, 12mA, 16mA, 20mA 3.3

1. Emulated with external resistors.

2. On the left and right edges, LVDS outputs are supported with a dedicated differential output driver on 50% of the I/Os. This

solution does not require external resistors at the driver.

2-38

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port

consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage VCCJ and can

operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards. For more information, please see TN1141, LatticeXP2

sysCONFIG Usage Guide.

flexiFLASH Device Configuration

The LatticeXP2 devices combine Flash and SRAM on a single chip to provide users with flexibility in device pro-

gramming and configuration. Figure 2-33 provides an overview of the arrangement of Flash and SRAM configura-

tion cells within the device. The remainder of this section provides an overview of these capabilities. See TN1141,

LatticeXP2 sysCONFIG Usage Guide for a more detailed description.

Figure 2-33. Overview of Flash and SRAM Configuration Cells Within LatticeXP2 Devices

At power-up, or on user command, data is transferred from the on-chip Flash memory to the SRAM configuration

cells that control the operation of the device. This is done with massively parallel buses enabling the parts to oper-

ate within microseconds of the power supplies reaching valid levels; this capability is referred to as Instant-On.

The on-chip Flash enables a single-chip solution eliminating the need for external boot memory. This Flash can be

programmed through either the JTAG or Slave SPI ports of the device. The SRAM configuration space can also be

infinitely reconfigured through the JTAG and Master SPI ports. The JTAG port is IEEE 1149.1 and IEEE 1532 com-

pliant.

As described in the EBR section of the data sheet, the FlashBAK capability of the parts enables the contents of the

EBR blocks to be written back into the Flash storage area without erasing or reprogramming other aspects of the

device configuration. Serial TAG memory is also available to allow the storage of small amounts of data such as

calibration coefficients and error codes.

For applications where security is important, the lack of an external bitstream provides a solution that is inherently

more secure than SRAM only FPGAs. This is further enhanced by device locking. The device can be in one of

three modes:

EBR Blocks

Flash Memory

EBR Blocks

SRAM

Configuration

Bits

Massively Parallel

Data Transfer

Instant-ON

Flash for

Single-Chip

Solution

FlashBAK

for EBR

Storage

Decryption

and Device

Lock

SPI and JTAG

TAG

Memory

Device Lock

for Design

Security

2-39

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

1. Unlocked

2. Key Locked – Presenting the key through the programming interface allows the device to be unlocked.

3. Permanently Locked – The device is permanently locked.

To further complement the security of the device a One Time Programmable (OTP) mode is available. Once the

device is set in this mode it is not possible to erase or re-program the Flash portion of the device.

Serial TAG Memory

LatticeXP2 devices offer 0.6 to 3.3kbits of Flash memory in the form of Serial TAG memory. The TAG memory is an

area of the on-chip Flash that can be used for non-volatile storage including electronic ID codes, version codes,

date stamps, asset IDs and calibration settings. A block diagram of the TAG memory is shown in Figure 2-34. The

TAG memory is accessed in the same way as external SPI Flash and it can be read or programmed either through

JTAG, an external Slave SPI Port, or directly from FPGA logic. To read the TAG memory, a start address is speci-

fied and the entire TAG memory contents are read sequentially in a first-in-first-out manner. The TAG memory is

independent of the Flash used for device configuration and given its use for general-purpose storage functions is

always accessible regardless of the device security settings. For more information, see TN1137, LatticeXP2 Mem-

ory Usage Guide and TN1141, LatticeXP2 sysCONFIG Usage Guide.

Figure 2-34. Serial TAG Memory Diagram

Live Update Technology

Many applications require field updates of the FPGA. LatticeXP2 devices provide three features that enable this

configuration to be done in a secure and failsafe manner while minimizing impact on system operation.

1. Decryption Support

LatticeXP2 devices provide on-chip, non-volatile key storage to support decryption of a 128-bit AES encrypted

bitstream, securing designs and deterring design piracy.

2. TransFR (Transparent Field Reconfiguration)

TransFR I/O (TFR) is a unique Lattice technology that allows users to update their logic in the field without

interrupting system operation using a single ispVM command. TransFR I/O allows I/O states to be frozen dur-

ing device configuration. This allows the device to be field updated with a minimum of system disruption and

downtime. For more information please see TN1087, Minimizing System Interruption During Configuration

Using TransFR Technology.

3. Dual Boot Image Support

Dual boot images are supported for applications requiring reliable remote updates of configuration data for the

system FPGA. After the system is running with a basic configuration, a new boot image can be downloaded

remotely and stored in a separate location in the configuration storage device. Any time after the update the

LatticeXP2 can be re-booted from this new configuration file. If there is a problem such as corrupt data during

download or incorrect version number with this new boot image, the LatticeXP2 device can revert back to the

Flash

JTAG

FPGA Logic

External Slave

SPI Port

JTAG

FPGA Logic

External Slave

SPI Port

TDI TDO

Data Shift Register

Flash Memory Array

Sequential

Address

Counter

2-40

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

original backup configuration and try again. This all can be done without power cycling the system. For more

information please see TN1220, LatticeXP2 Dual Boot Feature.

For more information on device configuration, please see TN1141, LatticeXP2 sysCONFIG Usage Guide.

Soft Error Detect (SED) Support

LatticeXP2 devices have dedicated logic to perform Cyclic Redundancy Code (CRC) checks. During configuration,

the configuration data bitstream can be checked with the CRC logic block. In addition, LatticeXP2 devices can be

programmed for checking soft errors in SRAM. SED can be run on a programmed device when the user logic is not

active. In the event a soft error occurs, the device can be programmed to either reload from a known good boot

image (from internal Flash or external SPI memory) or generate an error signal.

For further information on SED support, please see TN1130, LatticeXP2 Soft Error Detection (SED) Usage Guide.

On-Chip Oscillator

Every LatticeXP2 device has an internal CMOS oscillator that is used to derive a Master Clock (CCLK) for configu-

ration. The oscillator and CCLK run continuously and are available to user logic after configuration is complete. The

available CCLK frequencies are listed in Table 2-14. When a different CCLK frequency is selected during the

design process, the following sequence takes place:

1. Device powers up with the default CCLK frequency.

2. During configuration, users select a different CCLK frequency.

3. CCLK frequency changes to the selected frequency after clock configuration bits are received.

This internal CMOS oscillator is available to the user by routing it as an input clock to the clock tree. For further

information on the use of this oscillator for configuration or user mode, please see TN1141, LatticeXP2 sysCON-

FIG Usage Guide.

Table 2-14. Selectable CCLKs and Oscillator Frequencies During Configuration and User Mode

CCLK/Oscillator (MHz)

2.51

3.12

4.3

5.4

6.9

8.1

9.2

803

1633

1. Software default oscillator frequency.

2. Software default CCLK frequency.

3. Frequency not valid for CCLK.

2-41

Architecture

Lattice Semiconductor LatticeXP2 Family Data Sheet

Density Shifting

The LatticeXP2 family is designed to ensure that different density devices in the same family and in the same pack-

age have the same pinout. Furthermore, the architecture ensures a high success rate when performing design

migration from lower density devices to higher density devices. In many cases, it is also possible to shift a lower uti-

lization design targeted for a high-density device to a lower density device. However, the exact details of the final

resource utilization will impact the likely success in each case.

www.latticesemi.com 3-1 DS1009 DC and Switching_01.8

January 2012 Data Sheet DS1009

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Absolute Maximum Ratings1, 2, 3

Recommended Operating Conditions

On-Chip Flash Memory Specifications

Supply Voltage VCC . . . . . . . . . . . . . . . . . . . -0.5 to 1.32V

Supply Voltage VCCAUX . . . . . . . . . . . . . . . . -0.5 to 3.75V

Supply Voltage VCCJ . . . . . . . . . . . . . . . . . . -0.5 to 3.75V

Supply Voltage VCCPLL4. . . . . . . . . . . . . . . . -0.5 to 3.75V

Output Supply Voltage VCCIO . . . . . . . . . . . -0.5 to 3.75V

Input or I/O Tristate Voltage Applied5. . . . . . -0.5 to 3.75V

Storage Temperature (Ambient) . . . . . . . . . -65 to 150°C

Junction Temperature Under Bias (Tj). . . . . . . . . +125°C

1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

2. Compliance with the Lattice Thermal Management document is required.

3. All voltages referenced to GND.

4. VCCPLL only available on csBGA, PQFP and TQFP packages.

5. Overshoot and undershoot of -2V to (VIHMAX + 2) volts is permitted for a duration of <20 ns.

Symbol Parameter Min. Max. Units

VCC Core Supply Voltage 1.14 1.26 V

VCCAUX4, 5 Auxiliary Supply Voltage 3.135 3.465 V

VCCPLL1PLL Supply Voltage 3.135 3.465 V

VCCIO2, 3, 4 I/O Driver Supply Voltage 1.14 3.465 V

VCCJ2Supply Voltage for IEEE 1149.1 Test Access Port 1.14 3.465 V

tJCOM Junction Temperature, Commercial Operation 0 85 °C

tJIND Junction Temperature, Industrial Operation -40 100 °C

1. VCCPLL only available on csBGA, PQFP and TQFP packages.

2. If VCCIO or VCCJ is set to 1.2V, they must be connected to the same power supply as VCC. If VCCIO or VCCJ is set to 3.3V, they must be con-

nected to the same power supply as VCCAUX.

3. See recommended voltages by I/O standard in subsequent table.

4. To ensure proper I/O behavior, VCCIO must be turned off at the same time or earlier than VCCAUX.

5. In fpBGA and ftBGA packages, the PLLs are connected to, and powered from, the auxiliary power supply.

Symbol Parameter Max. Units

NPROGCYC

Flash Programming Cycles per tRETENTION110,000 Cycles

Flash Functional Programming Cycles 100,000

1. The minimum data retention, tRETENTION, is 20 years.

LatticeXP2 Family Data Sheet

DC and Switching Characteristics

3-2

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

Hot Socketing Specifications1, 2, 3, 4

ESD Performance

Please refer to the LatticeXP2 Product Family Qualification Summary for complete qualification data, including

ESD performance.

DC Electrical Characteristics

Over Recommended Operating Conditions

Symbol Parameter Condition Min. Typ. Max. Units

IDK Input or I/O Leakage Current 0  VIN  VIH (MAX.) — — +/-1 mA

1. Insensitive to sequence of VCC, VCCAUX and VCCIO. However, assumes monotonic rise/fall rates for VCC, VCCAUX and VCCIO.

2. 0  VCC  VCC (MAX), 0  VCCIO  VCCIO (MAX) or 0  VCCAUX  VCCAUX (MAX).

3. IDK is additive to IPU, IPW or IBH.

4. LVCMOS and LVTTL only.

Symbol Parameter Condition Min. Typ. Max. Units

IIL, IIH1Input or I/O Low Leakage 0  VIN  VCCIO ——10µA

VCCIO  VIN  VIH (MAX) — — 150 µA

IPU I/O Active Pull-up Current 0  VIN  0.7 VCCIO -30 — -150 µA

IPD I/O Active Pull-down Current VIL (MAX)  VIN  VCCIO 30 — 210 µA

IBHLS Bus Hold Low Sustaining Current VIN = VIL (MAX) 30 — — µA

IBHHS Bus Hold High Sustaining Current VIN = 0.7 VCCIO -30 — — µA

IBHLO Bus Hold Low Overdrive Current 0  VIN  VCCIO ——210µA

IBHHO Bus Hold High Overdrive Current 0  VIN  VCCIO ——-150µA

VBHT Bus Hold Trip Points VIL (MAX) — VIH (MIN) V

C1 I/O Capacitance2VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,

VCC = 1.2V, VIO = 0 to VIH (MAX) —8—pf

C2 Dedicated Input Capacitance VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,

VCC = 1.2V, VIO = 0 to VIH (MAX) —6—pf

1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured

with the output driver active. Bus maintenance circuits are disabled.

2. TA 25oC, f = 1.0 MHz.

3-3

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

Supply Current (Standby)1, 2, 3, 4

Over Recommended Operating Conditions

Symbol Parameter Device Typical5 Units

ICC Core Power Supply Current

XP2-5 14 mA

XP2-8 18 mA

XP2-17 24 mA

XP2-30 35 mA

XP2-40 45 mA

ICCAUX Auxiliary Power Supply Current6

XP2-5 15 mA

XP2-8 15 mA

XP2-17 15 mA

XP2-30 16 mA

XP2-40 16 mA

ICCPLL PLL Power Supply Current (per PLL) 0.1 mA

ICCIO Bank Power Supply Current (per bank) 2 mA

ICCJ VCCJ Power Supply Current 0.25 mA

1. For further information on supply current, please see TN1139, Power Estimation and Management for LatticeXP2 Devices.

2. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND.

3. Frequency 0 MHz.

4. Pattern represents a “blank” configuration data file.

5. TJ = 25oC, power supplies at nominal voltage.

6. In fpBGA and ftBGA packages the PLLs are connected to and powered from the auxiliary power supply. For these packages,

the actual auxiliary supply current is the sum of ICCAUX and ICCPLL. For csBGA, PQFP and TQFP packages the PLLs are

powered independent of the auxiliary power supply.

3-4

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

Initialization Supply Current1, 2, 3, 4, 5

Over Recommended Operating Conditions

Symbol Parameter Device Typical

(25°C, Max. Supply)6Units

ICC Core Power Supply Current

XP2-5 20 mA

XP2-8 21 mA

XP2-17 44 mA

XP2-30 58 mA

XP2-40 62 mA

ICCAUX Auxiliary Power Supply Current7

XP2-5 67 mA

XP2-8 74 mA

XP2-17 112 mA

XP2-30 124 mA

XP2-40 130 mA

ICCPLL PLL Power Supply Current (per PLL) 1.8 mA

ICCIO Bank Power Supply Current (per Bank) 6.4 mA

ICCJ VCCJ Power Supply Current 1.2 mA

1. For further information on supply current, please see TN1139, Power Estimation and Management for LatticeXP2 Devices.

2. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND.

3. Frequency 0 MHz.

4. Does not include additional current from bypass or decoupling capacitor across the supply.

5. A specific configuration pattern is used that scales with the size of the device; consists of 75% PFU utilization, 50% EBR, and 25% I/O con-

figuration.

6. TJ = 25°C, power supplies at nominal voltage.

7. In fpBGA and ftBGA packages the PLLs are connected to and powered from the auxiliary power supply. For these packages, the actual

auxiliary supply current is the sum of ICCAUX and ICCPLL. For csBGA, PQFP and TQFP packages the PLLs are powered independent of the

auxiliary power supply.

3-5

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

Programming and Erase Flash Supply Current1, 2, 3, 4, 5

Over Recommended Operating Conditions

Symbol Parameter Device Typical

(25°C, Max. Supply)6Units

ICC Core Power Supply Current

XP2-5 17 mA

XP2-8 21 mA

XP2-17 28 mA

XP2-30 36 mA

XP2-40 50 mA

ICCAUX Auxiliary Power Supply Current7

XP2-5 64 mA

XP2-8 66 mA

XP2-17 83 mA

XP2-30 87 mA

XP2-40 88 mA

ICCPLL PLL Power Supply Current (per PLL) 0.1 mA

ICCIO Bank Power Supply Current (per Bank) 5 mA

ICCJ VCCJ Power Supply Current814 mA

1. For further information on supply current, please see TN1139, Power Estimation and Management for LatticeXP2 Devices.

2. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND.

3. Frequency 0 MHz (excludes dynamic power from FPGA operation).

4. A specific configuration pattern is used that scales with the size of the device; consists of 75% PFU utilization, 50% EBR, and 25% I/O con-

figuration.

5. Bypass or decoupling capacitor across the supply.

6. TJ = 25°C, power supplies at nominal voltage.

7. In fpBGA and ftBGA packages the PLLs are connected to and powered from the auxiliary power supply. For these packages, the actual

auxiliary supply current is the sum of ICCAUX and ICCPLL. For csBGA, PQFP and TQFP packages the PLLs are powered independent of the

auxiliary power supply.

8. When programming via JTAG.

3-6

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

sysIO Recommended Operating Conditions

Over Recommended Operating Conditions

Standard VCCIO VREF (V)

Min. Typ. Max. Min. Typ. Max.

LVCMOS 3 3 2 3.135 3.3 3.465 — — —

LVCMOS 2 5 2 2.375 2.5 2.625 — — —

LVCMOS18 1.71 1.8 1.89 — — —

LVCMOS15 1.425 1.5 1.575 — — —

LVCMOS 1 2 2 1.14 1.2 1.26 — — —

LVTTL3 3 2 3.135 3.3 3.465 — — —

PCI33 3.135 3.3 3.465 — — —

SSTL18_I2,

SSTL18_II21.71 1.8 1.89 0.833 0.9 0.969

SSTL25_I2,

SSTL25_II22.375 2.5 2.625 1.15 1.25 1.35

SSTL33_I2,

SSTL33_II23.135 3.3 3.465 1.3 1.5 1.7

HSTL15_I2 1.425 1.5 1.575 0.68 0.75 0.9

HSTL18_I2,

HSTL18_II21.71 1.8 1.89 0.816 0.9 1.08

LVDS25 2 2.375 2.5 2.625 — — —

MLVDS251 2.375 2.5 2.625 — — —

LVPECL331, 2 3.135 3.3 3.465 — — —

BLVDS251, 2 2.375 2.5 2.625 — — —

RSDS1, 2 2.375 2.5 2.625 — — —

SSTL18D_I2,

SSTL18D_II21.71 1.8 1.89 — — —

SSTL25D_ I2,

SSTL25D_II22.375 2.5 2.625 — — —

SSTL33D_ I2,

SSTL33D_ II23.135 3.3 3.465 — — —

HSTL15D_ I21.425 1.5 1.575 — — —

HSTL18D_ I2,

HSTL18D_ II21.71 1.8 1.89 — — —

1. Inputs on chip. Outputs are implemented with the addition of external resistors.

2. Input on this standard does not depend on the value of VCCIO.

3-7

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

sysIO Single-Ended DC Electrical Characteristics

Over Recommended Operating Conditions

Input/Output

Standard VIL VIH VOL VOH IOL1 (mA) IOH1 (mA)Min. (V) Max. (V) Min. (V) M ax. (V) Max. (V) Min. (V)

LVCMOS33 -0.3 0.8 2.0 3.6 0.4 VCCIO - 0.4 20, 16,

12, 8, 4

-20, -16,

-12, -8, -4

0.2 VCCIO - 0.2 0.1 -0.1

LVTTL33 -0.3 0.8 2.0 3.6 0.4 VCCIO - 0.4 20, 16,

12, 8, 4

-20, -16,

-12, -8, -4

0.2 VCCIO - 0.2 0.1 -0.1

LVCMOS25 -0.3 0.7 1.7 3.6 0.4 VCCIO - 0.4 20, 16,

12, 8, 4

-20, -16,

-12, -8, -4

0.2 VCCIO - 0.2 0.1 -0.1

LVCMOS18 -0.3 0.35 VCCIO 0.65 VCCIO 3.6 0.4 VCCIO - 0.4 16, 12,

8, 4

-16, -12,

-8, -4

0.2 VCCIO - 0.2 0.1 -0.1

LVCMOS15 -0.3 0.35 VCCIO 0.65 VCCIO 3.6 0.4 VCCIO - 0.4 8, 4 -8, -4

0.2 VCCIO - 0.2 0.1 -0.1

LVCMOS12 -0.3 0.35 VCC 0.65 VCC 3.6 0.4 VCCIO - 0.4 6, 2 -6, -2

0.2 VCCIO - 0.2 0.1 -0.1

PCI33 -0.3 0.3 VCCIO 0.5 VCCIO 3.6 0.1 VCCIO 0.9 VCCIO 1.5 -0.5

SSTL33_I -0.3 VREF - 0.2 VREF + 0.2 3.6 0.7 VCCIO - 1.1 8 -8

SSTL33_II -0.3 VREF - 0.2 VREF + 0.2 3.6 0.5 VCCIO - 0.9 16 -16

SSTL25_I -0.3 VREF - 0.18 VREF + 0.18 3.6 0.54 VCCIO - 0.62 7.6 -7.6

12 -12

SSTL25_II -0.3 VREF - 0.18 VREF + 0.18 3.6 0.35 VCCIO - 0.43 15.2 -15.2

20 -20

SSTL18_I -0.3 VREF - 0.125 VREF + 0.125 3.6 0.4 VCCIO - 0.4 6.7 -6.7

SSTL18_II -0.3 VREF - 0.125 VREF + 0.125 3.6 0.28 VCCIO - 0.28 8-8

11 -11

HSTL15_I -0.3 VREF - 0.1 VREF + 0.1 3.6 0.4 VCCIO - 0.4 4-4

8-8

HSTL18_I -0.3 VREF - 0.1 VREF + 0.1 3.6 0.4 VCCIO - 0.4 8-8

12 -12

HSTL18_II -0.3 VREF - 0.1 VREF + 0.1 3.6 0.4 VCCIO - 0.4 16 -16

1. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O bank and the end of an I/O bank, as

shown in the logic signal connections table shall not exceed n * 8mA, where n is the number of I/Os between bank GND connections or

between the last GND in a bank and the end of a bank.

3-8

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

sysIO Differential Electrical Characteristics

LVDS Over Recommended Operating Conditions

Differential HSTL and SSTL

Differential HSTL and SSTL outputs are implemented as a pair of complementary single-ended outputs. All allow-

able single-ended output classes (class I and class II) are supported in this mode.

For further information on LVPECL, RSDS, MLVDS, BLVDS and other differential interfaces please see details in

additional technical notes listed at the end of this data sheet.

LVDS25E

The top and bottom sides of LatticeXP2 devices support LVDS outputs via emulated complementary LVCMOS out-

puts in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-1 is one possi-

ble solution for point-to-point signals.

Figure 3-1. LVDS25E Output Termination Example

Parameter Description Test Conditions Min. Typ. Max. Units

VINP

, VINM Input Voltage 0 — 2.4 V

VCM Input Common Mode Voltage Half the Sum of the Two Inputs 0.05 — 2.35 V

VTHD Differential Input Threshold Difference Between the Two Inputs +/-100 — — mV

IIN Input Current Power On or Power Off — — +/-10 µA

VOH Output High Voltage for VOP or VOM RT = 100 Ohm — 1.38 1.60 V

VOL Output Low Voltage for VOP or VOM RT = 100 Ohm 0.9V 1.03 — V

VOD Output Voltage Differential (VOP - VOM), RT = 100 Ohm 250 350 450 mV

VOD Change in VOD Between High and

Low ——50mV

VOS Output Voltage Offset (VOP + VOM)/2, RT = 100 Ohm 1.125 1.20 1.375 V

VOS Change in VOS Between H and L — — 50 mV

ISA Output Short Circuit Current VOD = 0V Driver Outputs Shorted to

Ground ——24mA

ISAB Output Short Circuit Current VOD = 0V Driver Outputs Shorted to

Each Other ——12mA

RS=158 ohms

(±1%)

RS=158 ohms

(±1%)

RP = 140 ohms

(±1%)

RT = 100 ohms

(±1%)

OFF-chip

Transmission line, Zo = 100 ohm differential

VCCIO = 2.5V (±5%)

8 mA

VCCIO = 2.5V (±5%)

ON-chip OFF-chip ON-chip

8 mA

3-9

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

Table 3-1. LVDS25E DC Conditions

LVCMOS33D

All I/O banks support emulated differential I/O using the LVCMOS33D I/O type. This option, along with the external

resistor network, provides the system designer the flexibility to place differential outputs on an I/O bank with 3.3V

VCCIO. The default drive current for LVCMOS33D output is 12mA with the option to change the device strength to

4mA, 8mA, 16mA or 20mA. Follow the LVCMOS33 specifications for the DC characteristics of the LVCMOS33D.

Parameter Description Typical Units

VCCIO Output Driver Supply (+/-5%) 2.50 V

ZOUT Driver Impedance 20 

RSDriver Series Resistor (+/-1%) 158 

RPDriver Parallel Resistor (+/-1%) 140 

RTReceiver Termination (+/-1%) 100 

VOH Output High Voltage (after RP)1.43V

VOL Output Low Voltage (after RP)1.07V

VOD Output Differential Voltage (After RP)0.35 V

VCM Output Common Mode Voltage 1.25 V

ZBACK Back Impedance 100.5 

IDC DC Output Current 6.03 mA

3-10

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

BLVDS

The LatticeXP2 devices support the BLVDS standard. This standard is emulated using complementary LVCMOS

outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when

multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one

possible solution for bi-directional multi-point differential signals.

Figure 3-2. BLVDS Multi-point Output Example

Table 3-2. BLVDS DC Conditions1

Over Recommended Operating Conditions

Parameter Description Typical UnitsZo = 45Zo = 90

VCCIO Output Driver Supply (+/- 5%) 2.50 2.50 V

ZOUT Driver Impedance 10.00 10.00 

RSDriver Series Resistor (+/- 1%) 90.00 90.00 

RTL Driver Parallel Resistor (+/- 1%) 45.00 90.00 

RTR Receiver Termination (+/- 1%) 45.00 90.00 

VOH Output High Voltage (After RTL) 1.38 1.48 V

VOL Output Low Voltage (After RTL) 1.12 1.02 V

VOD Output Differential Voltage (After RTL) 0.25 0.46 V

VCM Output Common Mode Voltage 1.25 1.25 V

IDC DC Output Current 11.24 10.20 mA

1. For input buffer, see LVDS table.

Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential

2.5V

RTL RTR

RS = 90 ohms

RS = 90 ohms RS =

90 ohms

RS =

90 ohms RS =

90 ohms

RS =

90 ohms

RS =

90 ohms

RS =

90 ohms

45-90

ohms

45-90

ohms

2.5V

2.5V 2.5V 2.5V 2.5V

2.5V

. . .

16mA

16mA 16mA 16mA 16mA

16mA

3-11

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

LVPECL

The LatticeXP2 devices support the differential LVPECL standard. This standard is emulated using complementary

LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input standard is

supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for point-

to-point signals.

Figure 3-3. Differential LVPECL

Table 3-3. LVPECL DC Conditions1

Over Recommended Operating Conditions

Parameter Description Typical Units

VCCIO Output Driver Supply (+/-5%) 3.30 V

ZOUT Driver Impedance 10 

RSDriver Series Resistor (+/-1%) 93 

RPDriver Parallel Resistor (+/-1%) 196 

RTReceiver Termination (+/-1%) 100 

VOH Output High Voltage (After RP)2.05V

VOL Output Low Voltage (After RP)1.25V

VOD Output Differential Voltage (After RP)0.80 V

VCM Output Common Mode Voltage 1.65 V

ZBACK Back Impedance 100.5 

IDC DC Output Current 12.11 mA

1. For input buffer, see LVDS table.

Transmission line,

Zo = 100 ohm differential

Off-chipOn-chip

VCCIO = 3.3V

(+/-5%)

VCCIO = 3.3V

(+/-5%)

RP = 196 ohms

(+/-1%) RT = 100 ohms

(+/-1%)

RS = 93.1 ohms

(+/-1%)

RS = 93.1 ohms

(+/-1%)

16mA

Off-chip On-chip

3-12

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

RSDS

The LatticeXP2 devices support differential RSDS standard. This standard is emulated using complementary LVC-

MOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input standard is sup-

ported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS

standard implementation. Resistor values in Figure 3-4 are industry standard values for 1% resistors.

Figure 3-4. RSDS (Reduced Swing Differential Standard)

Table 3-4. RSDS DC Conditions1

Over Recommended Operating Conditions

Parameter Description Typical Units

VCCIO Output Driver Supply (+/-5%) 2.50 V

ZOUT Driver Impedance 20 

RSDriver Series Resistor (+/-1%) 294 

RPDriver Parallel Resistor (+/-1%) 121 

RTReceiver Termination (+/-1%) 100 

VOH Output High Voltage (After RP)1.35V

VOL Output Low Voltage (After RP)1.15V

VOD Output Differential Voltage (After RP)0.20V

VCM Output Common Mode Voltage 1.25 V

ZBACK Back Impedance 101.5 

IDC DC Output Current 3.66 mA

1. For input buffer, see LVDS table.

= 294 ohms

(+/-1%)

= 294 ohms

(+/-1%)

= 121 ohms

(+/-1%)

= 100 ohms

(+/-1%)

On-chip On-chip

8mA

VCCIO = 2.5V

(+/-5%)

VCCIO = 2.5V

(+/-5%)

Transmission line,

Zo = 100 ohm differential

Off-chipOff-chip

3-13

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

MLVDS

The LatticeXP2 devices support the differential MLVDS standard. This standard is emulated using complementary

LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The MLVDS input standard is

supported by the LVDS differential input buffer. The scheme shown in Figure 3-5 is one possible solution for

MLVDS standard implementation. Resistor values in Figure 3-5 are industry standard values for 1% resistors.

Figure 3-5. MLVDS (Reduced Swing Differential Standard)

Table 3-5. MLVDS DC Conditions1

For further information on LVPECL, RSDS, MLVDS, BLVDS and other differential interfaces please see details of

additional technical information at the end of this data sheet.

Parameter Description Typical UnitsZo=50Zo=70

VCCIO Output Driver Supply (+/-5%) 2.50 2.50 V

ZOUT Driver Impedance 10.00 10.00 

RSDriver Series Resistor (+/-1%) 35.00 35.00 

RTL Driver Parallel Resistor (+/-1%) 50.00 70.00 

RTR Receiver Termination (+/-1%) 50.00 70.00 

VOH Output High Voltage (After RTL)1.521.60V

VOL Output Low Voltage (After RTL)0.980.90V

VOD Output Differential Voltage (After RTL)0.54 0.70 V

VCM Output Common Mode Voltage 1.25 1.25 V

IDC DC Output Current 21.74 20.00 mA

1. For input buffer, see LVDS table.

16mA

2.5V

. . .. . .

Am61

Heavily loaded backplace, effective Zo~50 to 70 ohms differential

50 to 70 ohms +/-1% 50 to 70 ohms +/-1%

35ohms

16mA

2.5V

Am61

2.5V

Am61

2.5V

Am61

2.5V

16mA

3-14

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

Typical Building Block Function Performance1

Pin-to-Pin Performance (LVCMOS25 12mA Drive)

Function -7 Timing Units

Basic Functions

16-bit Decoder 4.4 ns

32-bit Decoder 5.2 ns

64-bit Decoder 5.6 ns

4:1 MUX 3.7 ns

8:1 MUX 3.9 ns

16:1 MUX 4.3 ns

32:1 MUX 4.5 ns

Function -7 Timing Units

Basic Functions

16-bit Decoder 521 MHz

32-bit Decoder 537 MHz

64-bit Decoder 484 MHz

4:1 MUX 744 MHz

8:1 MUX 678 MHz

16:1 MUX 616 MHz

32:1 MUX 529 MHz

8-bit Adder 570 MHz

16-bit Adder 507 MHz

64-bit Adder 293 MHz

16-bit Counter 541 MHz

32-bit Counter 440 MHz

64-bit Counter 321 MHz

64-bit Accumulator 261 MHz

Embedded Memory Functions

512x36 Single Port RAM, EBR Output Registers 315 MHz

1024x18 True-Dual Port RAM (Write Through or Normal, EBR Output Registers) 315 MHz

1024x18 True-Dual Port RAM (Write Through or Normal, PLC Output Registers) 231 MHz

Distribute d Memory Functions

16x4 Pseudo-Dual Port RAM (One PFU) 760 MHz

32x2 Pseudo-Dual Port RAM 455 MHz

64x1 Pseudo-Dual Port RAM 351 MHz

DSP Functions

18x18 Multiplier (All Registers) 342 MHz

9x9 Multiplier (All Registers) 342 MHz

36x36 Multiply (All Registers) 330 MHz

18x18 Multiply/Accumulate (Input and Output Registers) 218 MHz

18x18 Multiply-Add/Sub-Sum (All Registers) 292 MHz

3-15

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

Derating Timing Tables

Logic timing provided in the following sections of this data sheet and the Diamond design tools are worst case num-

bers in the operating range. Actual delays at nominal temperature and voltage for best case process, can be much

better than the values given in the tables. The Diamond design tool can provide logic timing numbers at a particular

temperature and voltage.

DSP IP Functions

16-Tap Fully-Parallel FIR Filter 198 MHz

1024-pt FFT 221 MHz

8X8 Matrix Multiplication 196 MHz

1. These timing numbers were generated using the ispLEVER design tool. Exact performance may vary with device, design and tool version.

The tool uses internal parameters that have been characterized but are not tested on every device.

Timing v. A 0.12

Function -7 Timing Units

3-16

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

LatticeXP2 External Switching Characteristics

Over Recommended Operating Conditions

Parameter Description Device -7 -6 -5 UnitsMin. Max. Min. Max. Min. Max.

General I/O Pin Parameters (using Primary Clock without PLL) 1

tCO Clock to Output - PIO Output

XP2-5 — 3.80 — 4.20 — 4.60 ns

XP2-8 — 3.80 — 4.20 — 4.60 ns

XP2-17 — 3.80 — 4.20 — 4.60 ns

XP2-30 — 4.00 — 4.40 — 4.90 ns

XP2-40 — 4.00 — 4.40 — 4.90 ns

tSU Clock to Data Setup - PIO Input

XP2-5 0.00 — 0.00 — 0.00 — ns

XP2-8 0.00 — 0.00 — 0.00 — ns

XP2-17 0.00 — 0.00 — 0.00 — ns

XP2-30 0.00 — 0.00 — 0.00 — ns

XP2-40 0.00 — 0.00 — 0.00 — ns

tHClock to Data Hold - PIO Input

XP2-5 1.40 — 1.70 — 1.90 — ns

XP2-8 1.40 — 1.70 — 1.90 — ns

XP2-17 1.40 — 1.70 — 1.90 — ns

XP2-30 1.40 — 1.70 — 1.90 — ns

XP2-40 1.40 — 1.70 — 1.90 — ns

tSU_DEL Clock to Data Setup - PIO Input

XP2-5 1.40 — 1.70 — 1.90 — ns

XP2-8 1.40 — 1.70 — 1.90 — ns

XP2-17 1.40 — 1.70 — 1.90 — ns

XP2-30 1.40 — 1.70 — 1.90 — ns

XP2-40 1.40 — 1.70 — 1.90 — ns

tH_DEL Clock to Data Hold - PIO Input

XP2-5 0.00 — 0.00 — 0.00 — ns

XP2-8 0.00 — 0.00 — 0.00 — ns

XP2-17 0.00 — 0.00 — 0.00 — ns

XP2-30 0.00 — 0.00 — 0.00 — ns

XP2-40 0.00 — 0.00 — 0.00 — ns

fMAX_IO Clock Frequency of I/O and PFU

General I/O Pin Parameters (using Edge Clock wi thout PLL)1

tCOE Clock to Output - PIO Output

XP2-5 — 3.20 — 3.60 — 3.90 ns

XP2-8 — 3.20 — 3.60 — 3.90 ns

XP2-17 — 3.20 — 3.60 — 3.90 ns

XP2-30 — 3.20 — 3.60 — 3.90 ns

XP2-40 — 3.20 — 3.60 — 3.90 ns

tSUE Clock to Data Setup - PIO Input

XP2-5 0.00 — 0.00 — 0.00 — ns

XP2-8 0.00 — 0.00 — 0.00 — ns

XP2-17 0.00 — 0.00 — 0.00 — ns

XP2-30 0.00 — 0.00 — 0.00 — ns

XP2-40 0.00 — 0.00 — 0.00 — ns

3-17

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

tHE Clock to Data Hold - PIO Input

XP2-5 1.00 — 1.30 — 1.60 — ns

XP2-8 1.00 — 1.30 — 1.60 — ns

XP2-17 1.00 — 1.30 — 1.60 — ns

XP2-30 1.20 — 1.60 — 1.90 — ns

XP2-40 1.20 — 1.60 — 1.90 — ns

tSU_DELE Clock to Data Setup - PIO Input

XP2-5 1.00 — 1.30 — 1.60 — ns

XP2-8 1.00 — 1.30 — 1.60 — ns

XP2-17 1.00 — 1.30 — 1.60 — ns

XP2-30 1.20 — 1.60 — 1.90 — ns

XP2-40 1.20 — 1.60 — 1.90 — ns

tH_DELE Clock to Data Hold - PIO Input

XP2-5 0.00 — 0.00 — 0.00 — ns

XP2-8 0.00 — 0.00 — 0.00 — ns

XP2-17 0.00 — 0.00 — 0.00 — ns

XP2-30 0.00 — 0.00 — 0.00 — ns

XP2-40 0.00 — 0.00 — 0.00 — ns

fMAX_IOE Clock Frequency of I/O and PFU

General I/O Pin Parameters (using Primary Clock with PLL)1

tCOPLL Clock to Output - PIO Output

XP2-5 — 3.00 — 3.30 — 3.70 ns

XP2-8 — 3.00 — 3.30 — 3.70 ns

XP2-17 — 3.00 — 3.30 — 3.70 ns

XP2-30 — 3.00 — 3.30 — 3.70 ns

XP2-40 — 3.00 — 3.30 — 3.70 ns

tSUPLL Clock to Data Setup - PIO Input

XP2-5 1.00 — 1.20 — 1.40 — ns

XP2-8 1.00 — 1.20 — 1.40 — ns

XP2-17 1.00 — 1.20 — 1.40 — ns

XP2-30 1.00 — 1.20 — 1.40 — ns

XP2-40 1.00 — 1.20 — 1.40 — ns

tHPLL Clock to Data Hold - PIO Input

XP2-5 0.90 — 1.10 — 1.30 — ns

XP2-8 0.90 — 1.10 — 1.30 — ns

XP2-17 0.90 — 1.10 — 1.30 — ns

XP2-30 1.00 — 1.20 — 1.40 — ns

XP2-40 1.00 — 1.20 — 1.40 — ns

tSU_DELPLL Clock to Data Setup - PIO Input

XP2-5 1.90 — 2.10 — 2.30 — ns

XP2-8 1.90 — 2.10 — 2.30 — ns

XP2-17 1.90 — 2.10 — 2.30 — ns

XP2-30 2.00 — 2.20 — 2.40 — ns

XP2-40 2.00 — 2.20 — 2.40 — ns

LatticeXP2 External Switching Characteristics (Continued)

Over Recommended Operating Conditions

Parameter Description Device -7 -6 -5 UnitsMin. Max. Min. Max. Min. Max.

3-18

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

tH_DELPLL Clock to Data Hold - PIO Input

XP2-5 0.00 — 0.00 — 0.00 — ns

XP2-8 0.00 — 0.00 — 0.00 — ns

XP2-17 0.00 — 0.00 — 0.00 — ns

XP2-30 0.00 — 0.00 — 0.00 — ns

XP2-40 0.00 — 0.00 — 0.00 — ns

DDR2 and DDR23 I/O Pin Parameters

tDVADQ Data Valid After DQS 

(DDR Read) XP2 — 0.29 — 0.29 — 0.29 UI

tDVEDQ Data Hold After DQS 

(DDR Read) XP2 0.71 — 0.71 — 0.71 — UI

tDQVBS Data Valid Before DQS XP2 0.25 — 0.25 — 0.25 — UI

tDQVAS Data Valid After DQS XP2 0.25 — 0.25 — 0.25 — UI

fMAX_DDR DDR Clock Frequency XP2 95 200 95 166 95 133 MHz

fMAX_DDR2 DDR Clock Frequency XP2 133 200 133 200 133 166 MHz

Primary Clock

fMAX_PRI Frequency for Primary Clock

Tre e XP2 —420—357—311MHz

tW_PRI Clock Pulse Width for Primary

Clock XP2 1—1—1—ns

tSKEW_PRI Primary Clock Skew Within a

Bank XP2 —160—160—160ps

Edge Clock (ECLK1 and ECLK2)

fMAX_ECLK Frequency for Edge Clock XP2 — 420 — 357 — 311 MHz

tW_ECLK Clock Pulse Width for Edge

Clock XP2 1—1—1—ns

tSKEW_ECLK Edge Clock Skew Within an

Edge of the Device XP2 —130—130—130ps

1. General timing numbers based on LVCMOS 2.5, 12mA, 0pf load.

2. DDR timing numbers based on SSTL25.

3. DDR2 timing numbers based on SSTL18.

Timing v. A 0.12

LatticeXP2 External Switching Characteristics (Continued)

Over Recommended Operating Conditions

Parameter Description Device -7 -6 -5 UnitsMin. Max. Min. Max. Min. Max.

3-19

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

LatticeXP2 Internal Switching Characteristics1

Over Recommended Operating Conditions

Parameter Description -7 -6 -5 UnitsMin. Max. Min. Max. Min. Max.

PFU/PFF Logic Mo de Timing

tLUT4_PFU LUT4 delay (A to D inputs to F

o u t p u t ) — 0.216 — 0.238 — 0.260 ns

tLUT6_PFU LUT6 delay (A to D inputs to OFX

output) — 0.304 — 0.399 — 0.494 ns

tLSR_PFU Set/Reset to output of PFU (Asyn-

chronous) — 0.720 — 0.769 — 0.818 ns

tSUM_PFU Clock to Mux (M0,M1) Input

Setup Time 0.154 — 0.151 — 0.148 — ns

tHM_PFU Clock to Mux (M0,M1) Input Hold

Time -0.061 — -0.057 — -0.053 — ns

tSUD_PFU Clock to D input setup time 0.061 — 0.077 — 0.093 — ns

tHD_PFU Clock to D input hold time 0.002 — 0.003 — 0.003 — ns

tCK2Q_PFU Clock to Q delay, (D-type Register

Configuration) — 0.342 — 0.363 — 0.383 ns

tRSTREC_PFU Asynchronous reset recovery

time for PFU Logic — 0.520 — 0.634 — 0.748 ns

tRST_PFU Asynchronous reset time for PFU

Logic — 0.720 — 0.769 — 0.818 ns

PFU Dual Port Memory Mode Timing

tCORAM_PFU Clock to Output (F Port) — 1.082 — 1.267 — 1.452 ns

tSUDATA_PFU Data Setup Time -0.206 — -0.240 — -0.274 — ns

tHDATA_PFU Data Hold Time 0.239 — 0.275 — 0.312 — ns

tSUADDR_PFU Address Setup Time -0.294 — -0.333 — -0.371 — ns

tHADDR_PFU Address Hold Time 0.295 — 0.333 — 0.371 — ns

tSUWREN_PFU Write/Read Enable Setup Time -0.146 — -0.169 — -0.193 — ns

tHWREN_PFU Write/Read Enable Hold Time 0.158 — 0.182 — 0.207 — ns

PIO Input/Output Buffer Timing

tIN_PIO Input Buffer Delay (LVCMOS25) — 0.858 — 0.766 — 0.674 ns

tOUT_PIO Output Buffer Delay (LVCMOS25) — 1.561 — 1.403 — 1.246 ns

IOLOGIC Input/Output Timing

tSUI_PIO Input Register Setup Time (Data

Before Clock) 0.583 — 0.893 — 1.201 — ns

tHI_PIO Input Register Hold Time (Data

after Clock) 0.062 — 0.322 — 0.482 — ns

tCOO_PIO Output Register Clock to Output

Delay — 0.608 — 0.661 — 0.715 ns

tSUCE_PIO Input Register Clock Enable

Setup Time 0.032 — 0.037 — 0.041 — ns

tHCE_PIO Input Register Clock Enable Hold

Time -0.022 — -0.025 — -0.028 — ns

tSULSR_PIO Set/Reset Setup Time 0.184 — 0.201 — 0.217 — ns

tHLSR_PIO Set/Reset Hold Time -0.080 — -0.086 — -0.093 — ns

tRSTREC_PIO Asynchronous reset recovery

time for IO Logic 0.228 — 0.247 — 0.266 — ns

3-20

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

tRST_PIO Asynchronous reset time for PFU

Logic — 0.386 — 0.419 — 0.452 ns

tDEL Dynamic Delay Step Size 0.035 0.035 0.035 0.035 0.035 0.035 ns

EBR Timing

tCO_EBR Clock (Read) to Output from

Address or Data — 2.774 — 3.142 — 3.510 ns

tCOO_EBR Clock (Write) to Output from EBR

Output Register — 0.360 — 0.408 — 0.456 ns

tSUDATA_EBR Setup Data to EBR Memory

(Write Clk) -0.167 — -0.198 — -0.229 — ns

tHDATA_EBR Hold Data to EBR Memory (Write

Clk) 0.194 — 0.231 — 0.267 — ns

tSUADDR_EBR Setup Address to EBR Memory

(Write Clk) -0.117 — -0.137 — -0.157 — ns

tHADDR_EBR Hold Address to EBR Memory

(Write Clk) 0.157 — 0.182 — 0.207 — ns

tSUWREN_EBR Setup Write/Read Enable to EBR

Memory (Write/Read Clk) -0.135 — -0.159 — -0.182 — ns

tHWREN_EBR Hold Write/Read Enable to EBR

Memory (Write/Read Clk) 0.158 — 0.186 — 0.214 — ns

tSUCE_EBR Clock Enable Setup Time to EBR

Output Register (Read Clk) 0.144 — 0.160 — 0.176 — ns

tHCE_EBR Clock Enable Hold Time to EBR

Output Register (Read Clk) -0.097 — -0.113 — -0.129 — ns

tRSTO_EBR

Reset To Output Delay Time from

EBR Output Register (Asynchro-

nous)

— 1.156 — 1.341 — 1.526 ns

tSUBE_EBR Byte Enable Set-Up Time to EBR

Output Register -0.117 — -0.137 — -0.157 — ns

tHBE_EBR

Byte Enable Hold Time to EBR

Output Register Dynamic Delay

on Each PIO

0.157 — 0.182 — 0.207 — ns

tRSTREC_EBR Asynchronous reset recovery

time for EBR 0.233 — 0.291 — 0.347 — ns

tRST_EBR Asynchronous reset time for EBR — 1.156 — 1.341 — 1.526 ns

PLL Parameters

tRSTKREC_PLL

After RSTK De-assert, Recovery

Time Before Next Clock Edge

Can Toggle K-divider Counter

1.000 — 1.000 — 1.000 — ns

tRSTREC_PLL

After RST De-assert, Recovery

Time Before Next Clock Edge

Can Toggle M-divider Counter

(Applies to M-Divider Portion of

RST Only2)

1.000 — 1.000 — 1.000 — ns

DSP Block Timing

tSUI_DSP Input Register Setup Time 0.135 — 0.151 — 0.166 — ns

tHI_DSP Input Register Hold Time 0.021 — -0.006 — -0.031 — ns

tSUP_DSP Pipeline Register Setup Time 2.505 — 2.784 — 3.064 — ns

LatticeXP2 Internal Switching Characteristics1 (Continued)

Over Recommended Operating Conditions

Parameter Description -7 -6 -5 UnitsMin. Max. Min. Max. Min. Max.

3-21

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

tHP_DSP Pipeline Register Hold Time -0.787 — -0.890 — -0.994 — ns

tSUO_DSP Output Register Setup Time 4.896 — 5.413 — 5.931 — ns

tHO_DSP Output Register Hold Time -1.439 — -1.604 — -1.770 — ns

tCOI_DSP3Input Register Clock to Output

Time — 4.513 — 4.947 — 5.382 ns

tCOP_DSP3Pipeline Register Clock to Output

Time — 2.153 — 2.272 — 2.391 ns

tCOO_DSP3Output Register Clock to Output

Time — 0.569 — 0.600 — 0.631 ns

tSUADSUB AdSub Input Register Setup Time -0.270 — -0.298 — -0.327 — ns

tHADSUB AdSub Input Register Hold Time 0.306 — 0.338 — 0.371 — ns

1. Internal parameters are characterized, but not tested on every device.

2. RST resets VCO and all counters in PLL.

3. These parameters include the Adder Subtractor block in the path.

Timing v. A 0.12

LatticeXP2 Internal Switching Characteristics1 (Contin ued)

Over Recommended Operating Conditions

Parameter Description -7 -6 -5 UnitsMin. Max. Min. Max. Min. Max.

3-22

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

EBR Timing Diagrams

Figure 3-6. Read/Write Mode (Normal)

Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock.

Figure 3-7. Read/Write Mode with Input and Output Registers

A0 A1 A0 A1

D0 D1

DOA

CO_EBR

Invalid Data

CO_EBR

D0 D1 D0

DIA

ADA

WEA

CSA

CLKA

A0 A1 A0 A0

D0 D1

output is only updated during a read cycle

D0 D1

Mem(n) data from previous read

DIA

ADA

WEA

CSA

CLKA

DOA (Regs)

tSU tH

tCOO_EBR tCOO_EBR

3-23

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

Figure 3-8. Write Through (SP Read/Write on Port A, Input Registers Only)

Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock.

A0 A1 A0

D0 D1

tSU

tACCESS tACCESS tACCESS

D2 D3 D4

D0 D1 D2

Data from Prev Read

or Write

Three consecutive writes to A0

DOA

DIA

ADA

WEA

CSA

CLKA

tACCESS

3-24

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

LatticeXP2 Family Timing Adders1, 2, 3

Over Recommended Operating Conditions

Buffer Type Description -7 -6 -5 Units

Input Adjusters

LVDS25 LVDS -0.26 -0.11 0.04 ns

BLVDS25 BLVDS -0.26 -0.11 0.04 ns

MLVDS LVDS -0.26 -0.11 0.04 ns

RSDS RSDS -0.26 -0.11 0.04 ns

LVPECL33 LVPECL -0.26 -0.11 0.04 ns

HSTL18_I HSTL_18 class I -0.23 -0.08 0.07 ns

HSTL18_II HSTL_18 class II -0.23 -0.08 0.07 ns

HSTL18D_I Differential HSTL 18 class I -0.28 -0.13 0.02 ns

HSTL18D_II Differential HSTL 18 class II -0.28 -0.13 0.02 ns

HSTL15_I HSTL_15 class I -0.23 -0.09 0.06 ns

HSTL15D_I Differential HSTL 15 class I -0.28 -0.13 0.01 ns

SSTL33_I SSTL_3 class I -0.20 -0.04 0.12 ns

SSTL33_II SSTL_3 class II -0.20 -0.04 0.12 ns

SSTL33D_I Differential SSTL_3 class I -0.27 -0.11 0.04 ns

SSTL33D_II Differential SSTL_3 class II -0.27 -0.11 0.04 ns

SSTL25_I SSTL_2 class I -0.21 -0.06 0.10 ns

SSTL25_II SSTL_2 class II -0.21 -0.06 0.10 ns

SSTL25D_I Differential SSTL_2 class I -0.27 -0.12 0.03 ns

SSTL25D_II Differential SSTL_2 class II -0.27 -0.12 0.03 ns

SSTL18_I SSTL_18 class I -0.23 -0.08 0.07 ns

SSTL18_II SSTL_18 class II -0.23 -0.08 0.07 ns

SSTL18D_I Differential SSTL_18 class I -0.28 -0.13 0.02 ns

SSTL18D_II Differential SSTL_18 class II -0.28 -0.13 0.02 ns

LVTTL33 LVTTL -0.09 0.05 0.18 ns

LVCMOS33 LVCMOS 3.3 -0.09 0.05 0.18 ns

LVCMOS25 LVCMOS 2.5 0.00 0.00 0.00 ns

LVCMOS18 LVCMOS 1.8 -0.23 -0.07 0.09 ns

LVCMOS15 LVCMOS 1.5 -0.20 -0.02 0.16 ns

LVCMOS12 LVCMOS 1.2 -0.35 -0.20 -0.04 ns

PCI33 3.3V PCI -0.09 0.05 0.18 ns

Output Adjusters

LVDS25E LVDS 2 . 5 E4-0.25 0.02 0.30 ns

LVDS25 LVDS 2.5 -0.25 0.02 0.30 ns

BLVDS25 BLVDS 2.5 -0.28 0.00 0.28 ns

MLVDS MLVDS 2.54-0.28 0.00 0.28 ns

RSDS RSDS 2.54-0.25 0.02 0.30 ns

LVPECL33 LVPECL 3.34-0.37 -0.10 0.18 ns

HSTL18_I HSTL_18 class I 8mA drive -0.17 0.13 0.43 ns

HSTL18_II HSTL_18 class II -0.29 0.00 0.29 ns

HSTL18D_I Differential HSTL 18 class I 8mA drive -0.17 0.13 0.43 ns

HSTL18D_II Differential HSTL 18 class II -0.29 0.00 0.29 ns

3-25

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

HSTL15_I HSTL_15 class I 4mA drive 0.32 0.69 1.06 ns

HSTL15D_I Differential HSTL 15 class I 4mA drive 0.32 0.69 1.06 ns

SSTL33_I SSTL_3 class I -0.25 0.05 0.35 ns

SSTL33_II SSTL_3 class II -0.31 -0.02 0.27 ns

SSTL33D_I Differential SSTL_3 class I -0.25 0.05 0.35 ns

SSTL33D_II Differential SSTL_3 class II -0.31 -0.02 0.27 ns

SSTL25_I SSTL_2 class I 8mA drive -0.25 0.02 0.30 ns

SSTL25_II SSTL_2 class II 16mA drive -0.28 0.00 0.28 ns

SSTL25D_I Differential SSTL_2 class I 8mA drive -0.25 0.02 0.30 ns

SSTL25D_II Differential SSTL_2 class II 16mA drive -0.28 0.00 0.28 ns

SSTL18_I SSTL_1.8 class I -0.17 0.13 0.43 ns

SSTL18_II SSTL_1.8 class II 8mA drive -0.18 0.12 0.42 ns

SSTL18D_I Differential SSTL_1.8 class I -0.17 0.13 0.43 ns

SSTL18D_II Differential SSTL_1.8 class II 8mA drive -0.18 0.12 0.42 ns

LVTTL33_4mA LVTTL 4mA drive -0.37 -0.05 0.26 ns

LVTTL33_8mA LVTTL 8mA drive -0.45 -0.18 0.10 ns

LVTTL33_12mA LVTTL 12mA drive -0.52 -0.24 0.04 ns

LVTTL33_16mA LVTTL 16mA drive -0.43 -0.14 0.14 ns

LVTTL33_20mA LVTTL 20mA drive -0.46 -0.18 0.09 ns

LVCMOS33_4mA LVCMOS 3.3 4mA drive, fast slew rate -0.37 -0.05 0.26 ns

LVCMOS33_8mA LVCMOS 3.3 8mA drive, fast slew rate -0.45 -0.18 0.10 ns

LVCMOS33_12mA LVCMOS 3.3 12mA drive, fast slew rate -0.52 -0.24 0.04 ns

LVCMOS33_16mA LVCMOS 3.3 16mA drive, fast slew rate -0.43 -0.14 0.14 ns

LVCMOS33_20mA LVCMOS 3.3 20mA drive, fast slew rate -0.46 -0.18 0.09 ns

LVCMOS25_4mA LVCMOS 2.5 4mA drive, fast slew rate -0.42 -0.15 0.13 ns

LVCMOS25_8mA LVCMOS 2.5 8mA drive, fast slew rate -0.48 -0.21 0.05 ns

LVCMOS25_12mA LVCMOS 2.5 12mA drive, fast slew rate 0.00 0.00 0.00 ns

LVCMOS25_16mA LVCMOS 2.5 16mA drive, fast slew rate -0.45 -0.18 0.08 ns

LVCMOS25_20mA LVCMOS 2.5 20mA drive, fast slew rate -0.49 -0.22 0.04 ns

LVCMOS18_4mA LVCMOS 1.8 4mA drive, fast slew rate -0.46 -0.18 0.10 ns

LVCMOS18_8mA LVCMOS 1.8 8mA drive, fast slew rate -0.52 -0.25 0.02 ns

LVCMOS18_12mA LVCMOS 1.8 12mA drive, fast slew rate -0.56 -0.30 -0.03 ns

LVCMOS18_16mA LVCMOS 1.8 16mA drive, fast slew rate -0.50 -0.24 0.03 ns

LVCMOS15_4mA LVCMOS 1.5 4mA drive, fast slew rate -0.45 -0.17 0.11 ns

LVCMOS15_8mA LVCMOS 1.5 8mA drive, fast slew rate -0.53 -0.26 0.00 ns

LVCMOS12_2mA LVCMOS 1.2 2mA drive, fast slew rate -0.46 -0.19 0.08 ns

LVCMOS12_6mA LVCMOS 1.2 6mA drive, fast slew rate -0.55 -0.29 -0.02 ns

LVCMOS33_4mA LVCMOS 3.3 4mA drive, slow slew rate 0.98 1.41 1.84 ns

LVCMOS33_8mA LVCMOS 3.3 8mA drive, slow slew rate 0.74 1.16 1.58 ns

LVCMOS33_12mA LVCMOS 3.3 12mA drive, slow slew rate 0.56 0.97 1.38 ns

LVCMOS33_16mA LVCMOS 3.3 16mA drive, slow slew rate 0.77 1.19 1.61 ns

LVCMOS33_20mA LVCMOS 3.3 20mA drive, slow slew rate 0.57 0.98 1.40 ns

LatticeXP2 Family Timing Adders1, 2, 3 (Continued)

Over Recommended Operating Conditions

Buffer Type Description -7 -6 -5 Units

3-26

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

LVCMOS25_4mA LVCMOS 2.5 4mA drive, slow slew rate 1.05 1.43 1.81 ns

LVCMOS25_8mA LVCMOS 2.5 8mA drive, slow slew rate 0.78 1.15 1.52 ns

LVCMOS25_12mA LVCMOS 2.5 12mA drive, slow slew rate 0.59 0.96 1.33 ns

LVCMOS25_16mA LVCMOS 2.5 16mA drive, slow slew rate 0.81 1.18 1.55 ns

LVCMOS25_20mA LVCMOS 2.5 20mA drive, slow slew rate 0.61 0.98 1.35 ns

LVCMOS18_4mA LVCMOS 1.8 4mA drive, slow slew rate 1.01 1.38 1.75 ns

LVCMOS18_8mA LVCMOS 1.8 8mA drive, slow slew rate 0.72 1.08 1.45 ns

LVCMOS18_12mA LVCMOS 1.8 12mA drive, slow slew rate 0.53 0.90 1.26 ns

LVCMOS18_16mA LVCMOS 1.8 16mA drive, slow slew rate 0.74 1.11 1.48 ns

LVCMOS15_4mA LVCMOS 1.5 4mA drive, slow slew rate 0.96 1.33 1.71 ns

LVCMOS15_8mA LVCMOS 1.5 8mA drive, slow slew rate -0.53 -0.26 0.00 ns

LVCMOS12_2mA LVCMOS 1.2 2mA drive, slow slew rate 0.90 1.27 1.65 ns

LVCMOS12_6mA LVCMOS 1.2 6mA drive, slow slew rate -0.55 -0.29 -0.02 ns

PCI33 3.3V PCI -0.29 -0.01 0.26 ns

1. Timing Adders are characterized but not tested on every device.

2. LVCMOS timing measured with the load specified in Switching Test Condition table.

3. All other standards tested according to the appropriate specifications.

4. These timing adders are measured with the recommended resistor values.

Timing v. A 0.12

LatticeXP2 Family Timing Adders1, 2, 3 (Continued)

Over Recommended Operating Conditions

Buffer Type Description -7 -6 -5 Units

3-27

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

sysCLOCK PLL Timing

Over Recommended Operating Conditions

Parameter Description Conditions Min. Typ. Max. Units

fIN Input Clock Frequency (CLKI, CLKFB) 10 — 435 MHz

fOUT Output Clock Frequency (CLKOP,

CLKOS) 10 — 435 MHz

fOUT2 K-Divider Output Frequency CLKOK 0.078 — 217.5 MHz

CLKOK2 3.3 — 145 MHz

fVCO PLL VCO Frequency 435 — 870 MHz

fPFD Phase Detector Input Frequency 10 — 435 MHz

AC Characteristics

tDT Output Clock Duty Cycle Default duty cycle selected 345 50 55 %

tCPA Coarse Phase Adjust -5 0 5 %

tPH4Output Phase Accuracy -5 0 5 %

tOPJIT1Output Clock Period Jitter

fOUT > 400 MHz — — ±50 ps

100 MHz < fOUT < 400 MHz — — ±125 ps

fOUT < 100 MHz — — 0.025 UIPP

tSK Input Clock to Output Clock Skew N/M = integer — — ±240 ps

tOPW Output Clock Pulse Width At 90% or 10% 1 — — ns

tLOCK2PLL Lock-in Time 25 to 435 MHz — — 50 µs

10 to 25 MHz — — 100 µs

tIPJIT Input Clock Period Jitter — — ±200 ps

tFBKDLY External Feedback Delay — — 10 ns

tHI Input Clock High Time 90% to 90% 0.5 — — ns

tLO Input Clock Low Time 10% to 10% 0.5 — — ns

tR / tFInput Clock Rise/Fall Time 10% to 90% — — 1 ns

tRSTKW Reset Signal Pulse Width (RSTK) 10 — — ns

tRSTW Reset Signal Pulse Width (RST) 500 — — ns

1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock.

2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.

3. Using LVDS output buffers.

4. Relative to CLKOP.

Timing v. A 0.12

3-28

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

LatticeXP2 sysCONFIG Port Timing Specifications

Over Recommended Operating Conditions

Parameter Description Min Max Units

sysCONFIG POR, Initialization and Wake Up

tICFG Minimum Vcc to INITN High — 50 ms

tVMC Time from tICFG to valid Master CCLK — 2 µs

tPRGMRJ PROGRAMN Pin Pulse Rejection — 12 ns

tPRGM PROGRAMN Low Time to Start Configuration 50 — ns

tDINIT1PROGRAMN High to INITN High Delay — 1 ms

tDPPINIT Delay Time from PROGRAMN Low to INITN Low — 50 ns

tDPPDONE Delay Time from PROGRAMN Low to DONE Low — 50 ns

tIODISS User I/O Disable from PROGRAMN Low — 35 ns

tIOENSS User I/O Enabled Time from CCLK Edge During Wake-up Sequence — 25 ns

tMWC Additional Wake Master Clock Signals after DONE Pin High 0 — Cycles

sysCONFIG SPI Port (Master)

tCFGX INITN High to CCLK Low — 1 µs

tCSSPI INITN High to CSSPIN Low — 2 µs

tCSCCLK CCLK Low before CSSPIN Low 0 — ns

tSOCDO CCLK Low to Output Valid — 15 ns

tCSPID CSSPIN[0:1] Low to First CCLK Edge Setup Time 2cyc 600+6cyc ns

fMAXSPI Max CCLK Frequency — 20 MHz

tSUSPI SOSPI Data Setup Time Before CCLK 7 — ns

tHSPI SOSPI Data Hold Time After CCLK 10 — ns

sysCONFIG SPI Port (Slave)

fMAXSPIS Slave CCLK Frequency — 25 MHz

tRF Rise and Fall Time 50 — mV/ns

tSTCO Falling Edge of CCLK to SOSPI Active — 20 ns

tSTOZ Falling Edge of CCLK to SOSPI Disable — 20 ns

tSTSU Data Setup Time (SISPI) 8 — ns

tSTH Data Hold Time (SISPI) 10 — ns

tSTCKH CCLK Clock Pulse Width, High 0.02 200 µs

tSTCKL CCLK Clock Pulse Width, Low 0.02 200 µs

tSTVO Falling Edge of CCLK to Valid SOSPI Output — 20 ns

tSCS CSSPISN High Time 25 — ns

tSCSS CSSPISN Setup Time 25 — ns

tSCSH CSSPISN Hold Time 25 — ns

1. Re-toggling the PROGRAMN pin is not permitted until the INITN pin is high. Avoid consecutive toggling of PROGRAMN.

3-29

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

On-Chip Oscillator and Configuration Master Clock Characteristics

Over Recommended Operating Conditions

Figure 3-9. Master SPI Configuration Waveforms

Parameter Min. Max. Units

Master Clock Frequency Selected value -30% Selected value +30% MHz

Duty Cycle 40 60 %

Timing v. A 0.12

Opcode Address

0 1 2 3 … 7 8 9 10 … 31 32 33 34 … 127 128

VCC

PROGRAMN

DONE

INITN

CSSPIN

CCLK

SISPI

SOSPI

Capture CFGx

Capture CR0

Ignore Valid Bitstream

3-30

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

Flash Download Time (from On-Chip Flash to SRAM)

Over Recommended Operating Conditions

Flash Program Time Over Recommended Operating Conditions

Flash Erase Time Over Recommended Operating Conditions

Symbol Parameter Min. Typ. Max. Units

tREFRESH

PROGRAMN Low-to-

High. Transition to Done

High.

XP2-5 — 1.8 2.1 ms

XP2-8 — 1.9 2.3 ms

XP2-17 — 1.7 2.0 ms

XP2-30 — 2.0 2.1 ms

XP2-40 — 2.0 2.3 ms

Power-up refresh when

PROGRAMN is pulled

up to VCC 

(VCC=VCC Min)

XP2-5 — 1.8 2.1 ms

XP2-8 — 1.9 2.3 ms

XP2-17 — 1.7 2.0 ms

XP2-30 — 2.0 2.1 ms

XP2-40 — 2.0 2.3 ms

Device Flash Density Program Time UnitsTyp.

XP2-5 1.2M TAG 1. 0 m s

Main Array 1.1 s

XP2-8 2.0M TAG 1. 0 m s

Main Array 1.4 s

XP2-17 3.6M TAG 1. 0 m s

Main Array 1.8 s

XP2-30 6.0M TAG 2. 0 m s

Main Array 3.0 s

XP2-40 8.0M TAG 2. 0 m s

Main Array 4.0 s

Device Flash Density Eras e Time UnitsTyp.

XP2-5 1.2M TAG 1. 0 s

Main Array 3.0 s

XP2-8 2.0M TAG 1. 0 s

Main Array 4.0 s

XP2-17 3.6M TAG 1. 0 s

Main Array 5.0 s

XP2-30 6.0M TAG 2. 0 s

Main Array 7.0 s

XP2-40 8.0M TAG 2. 0 s

Main Array 9.0 s

3-31

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

FlashBAK Time (from EBR to Flash)

Over Recommended Operating Conditions

JTAG Port Timing Specifications

Over Recommended Operating Conditions

Device EBR Density (Bits) Time (Typ.) Units

XP2-5 166K 1.5 s

XP2-8 221K 1.5 s

XP2-17 276K 1.5 s

XP2-30 387K 2.0 s

XP2-40 885K 3.0 s

Symbol Parameter Min. Max. Units

fMAX TCK Clock Frequency — 25 MHz

tBTCP TCK [BSCAN] clock pulse width 40 — ns

tBTCPH TCK [BSCAN] clock pulse width high 20 — ns

tBTCPL TCK [BSCAN] clock pulse width low 20 — ns

tBTS TCK [BSCAN] setup time 8 — ns

tBTH TCK [BSCAN] hold time 10 — ns

tBTRF TCK [BSCAN] rise/fall time 50 — mV/ns

tBTCO TAP controller falling edge of clock to valid output — 10 ns

tBTCODIS TAP controller falling edge of clock to valid disable — 10 ns

tBTCOEN TAP controller falling edge of clock to valid enable — 10 ns

tBTCRS BSCAN test capture register setup time 8 — ns

tBTCRH BSCAN test capture register hold time 25 — ns

tBUTCO BSCAN test update register, falling edge of clock to valid output — 25 ns

tBTUODIS BSCAN test update register, falling edge of clock to valid disable — 25 ns

tBTUPOEN BSCAN test update register, falling edge of clock to valid enable — 25 ns

Timing v. A 0.12

3-32

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

Figure 3-10. JTAG Port Timing Waveforms

TMS

TDI

TCK

TDO

Data to be

captured

from I/O

Data to be

driven out

to I/O

ataD dilaVataD dilaV

Data Captured

BTCPH

BTCPL

BTCOEN

BTCRS

BTUPOEN

BUTCO

BTUODIS

BTCRH

BTCO

BTCODIS

BTS

BTH

BTCP

3-33

DC and Switching Characteristics

Lattice Semiconductor LatticeXP2 Family Data Sheet

Switching Test Conditions

Figure 3-11 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,

voltage, and other test conditions are shown in Table 3-6.

Figure 3-11. Output Test Load, LVTTL and LVCMOS S tandards

Table 3-6. Test Fixture Required Components, Non-Terminated Interfaces

Test Condition R1R2CLTiming Ref. V T

LVTTL and other LVCMOS settings (L -> H, H -> L) 

0pF

LVCMOS 3.3 = 1.5V —

LVCMOS 2.5 = VCCIO/2 —

LVCMOS 1.8 = VCCIO/2 —

LVCMOS 1.5 = VCCIO/2 —

LVCMOS 1.2 = VCCIO/2 —

LVCMOS 2.5 I/O (Z -> H) 1MVCCIO/2 —

LVCMOS 2.5 I/O (Z -> L) 1MVCCIO/2 VCCIO

LVCMOS 2.5 I/O (H -> Z) 100 VOH - 0.10 —

LVCMOS 2.5 I/O (L -> Z) 100 VOL + 0.10 VCCIO

Note: Output test conditions for all other interfaces are determined by the respective standards.

DUT

CL*

Test Point

*CL Includes Test Fixture and Probe Capacitance

www.latticesemi.com 4-1 Pinout Information_01.6

January 2012 Data Sheet DS1009

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Signal Descriptions

Signal Name I/O Description

General Purpose

P[Edge] [Row/Column Number*]_[A/B] I/O

[Edge] indicates the edge of the device on which the pad is located. Valid

edge designations are L (Left), B (Bottom), R (Right), T (Top).

[Row/Column Number] indicates the PFU row or the column of the device on

which the PIC exists. When Edge is T (Top) or B (Bottom), only need to spec-

ify Row Number. When Edge is L (Left) or R (Right), only need to specify Col-

umn Number.

[A/B] indicates the PIO within the PIC to which the pad is connected. Some of

these user-programmable pins are shared with special function pins. These

pins, when not used as special purpose pins, can be programmed as I/Os for

user logic. During configuration the user-programmable I/Os are tri-stated

with an internal pull-up resistor enabled. If any pin is not used (or not bonded

to a package pin), it is also tri-stated with an internal pull-up resistor enabled

after configuration.

GSRN I Global RESET signal (active low). Any I/O pin can be GSRN.

NC — No connect.

GND — Ground. Dedicated pins.

VCC — Power supply pins for core logic. Dedicated pins.

VCCAUX —

Auxiliary power supply pin. This dedicated pin powers all the differential and

referenced input buffers.

VCCPLL — PLL supply pins. csBGA, PQFP and TQFP packages only.

VCCIOx — Dedicated power supply pins for I/O bank x.

VREF1_x, VREF2_x —Reference supply pins for I/O bank x. Pre-determined pins in each bank are

assigned as VREF inputs. When not used, they may be used as I/O pins.

PLL and Clock Functions (Used as user programmable I/O pins when not in use for PLL or clock pins)

[LOC][num]_VCCPLL — Power supply pin for PLL: LLC, LRC, URC, ULC, num = row from center.

[LOC][num]_GPLL[T, C]_IN_A I General Purpose PLL (GPLL) input pads: LLC, LRC, URC, ULC, num = row

from center, T = true and C = complement, index A,B,C...at each side.

[LOC][num]_GPLL[T, C]_FB_A I Optional feedback GPLL input pads: LLC, LRC, URC, ULC, num = row from

center, T = true and C = complement, index A,B,C...at each side.

PCLK[T, C]_[n:0]_[3:0] I Primary Clock pads, T = true and C = complement, n per side, indexed by

bank and 0,1,2,3 within bank.

[LOC]DQS[num] I

DQS input pads: T (Top), R (Right), B (Bottom), L (Left), DQS, num = ball

function number. Any pad can be configured to be output.

Test and Programming (Dedicated Pins)

TMS I Test Mode Select input, used to control the 1149.1 state machine. Pull-up is

enabled during configuration.

TCK I

Test Clock input pin, used to clock the 1149.1 state machine. No pull-up

enabled.

TDI I

Test Data in pin. Used to load data into device using 1149.1 state machine.

After power-up, this TAP port can be activated for configuration by sending

appropriate command. (Note: once a configuration port is selected it is

locked. Another configuration port cannot be selected until the power-up

sequence). Pull-up is enabled during configuration.

LatticeXP2 Family Data Sheet

Pinout Information

4-2

Pinout Information

Lattice Semiconductor LatticeXP2 Family Data Sheet

TDO O Output pin. Test Data Out pin used to shift data out of a device using 1149.1.

VCCJ — Power supply pin for JTAG Test Access Port.

Configuration Pads (Used during sysCONFIG)

CFG[1:0] I Mode pins used to specify configuration mode values latched on rising edge

of INITN. During configuration, an internal pull-up is enabled.

INITN1I/O Open Drain pin. Indicates the FPGA is ready to be configured. During config-

uration, a pull-up is enabled.

PROGRAMN I

Initiates configuration sequence when asserted low. This pin always has an

active pull-up.

DONE I/O

Open Drain pin. Indicates that the configuration sequence is complete, and

the startup sequence is in progress.

CCLK I/O Configuration Clock for configuring an FPGA in sysCONFIG mode.

SISPI2I/O Input data pin in slave SPI mode and Output data pin in Master SPI mode.

SOSPI2I/O Output data pin in slave SPI mode and Input data pin in Master SPI mode.

CSSPIN2OChip select for external SPI Flash memory in Master SPI mode. This pin has

a weak internal pull-up.

CSSPISN I Chip select in Slave SPI mode. This pin has a weak internal pull-up.

TOE I

Test Output Enable tristates all I/O pins when driven low. This pin has a weak

internal pull-up, but when not used an external pull-up to VCC is recom-

mended.

1. If not actively driven, the internal pull-up may not be sufficient. An external pull-up resistor of 4.7k to 10k is recommended.

2. When using the device in Master SPI mode, it must be mutually exclusive from JTAG operations (i.e. TCK tied to GND) or the JTAG TCK

must be free-running when used in a system JTAG test environment. If Master SPI mode is used in conjunction with a JTAG download

cable, the device power cycle is required after the cable is unplugged.

Signal Descriptions (Cont.)

Signal Name I/O Description

4-3

Pinout Information

Lattice Semiconductor LatticeXP2 Family Data Sheet

PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin

PICs Associated with

DQS Strobe PIO Within PIC DDR Strobe (DQS) and

Data (DQ) Pins

For Left and Right Edges of the Device

P[Edge] [n-4] ADQ

BDQ

P[Edge] [n-3] ADQ

BDQ

P[Edge] [n-2] ADQ

BDQ

P[Edge] [n-1] ADQ

BDQ

P[Edge] [n] A[Edge]DQSn

BDQ

P[Edge] [n+1] ADQ

BDQ

P[Edge] [n+2] ADQ

BDQ

P[Edge] [n+3] ADQ

BDQ

For Top and Bottom Edges of the Device

P[Edge] [n-4] ADQ

BDQ

P[Edge] [n-3] ADQ

BDQ

P[Edge] [n-2] ADQ

BDQ

P[Edge] [n-1] ADQ

BDQ

P[Edge] [n] A [Edge]DQSn

BDQ

P[Edge] [n+1] ADQ

BDQ

P[Edge] [n+2] ADQ

BDQ

P[Edge] [n+3] ADQ

BDQ

P[Edge] [n+4] ADQ

BDQ

Notes:

1. “n” is a row PIC number.

2. The DDR interface is designed for memories that support one DQS strobe up to 16 bits

of data for the left and right edges and up to 18 bits of data for the top and bottom

edges. In some packages, all the potential DDR data (DQ) pins may not be available.

PIC numbering definitions are provided in the “Signal Names” column of the Signal

Descriptions table.

4-4

Pinout Information

Lattice Semiconductor LatticeXP2 Family Data Sheet

Pin Information Summary

Pin Type

XP2-5 XP2-8 XP2-17 XP2-30 XP2-40

132

csBGA 144

TQFP 208

PQFP 256

ftBGA 132

csBGA 144

TQFP 208

PQFP 256

ftBGA 208

PQFP 256

ftBGA 484

fpBGA 256

ftBGA 484

fpBGA 672

fpBGA 484

fpBGA 672

fpBGA

Single Ended User I/O 86 100 146 172 86 100 146 201 146 201 358 201 363 472 363 540

Differential Pair

User I/O

Normal 35 39 57 66 35 39 57 77 57 77 135 77 137 180 137 204

Highspeed 8 11 16 20 8 11 16 23 16 23 44 23 44 56 44 66

Configuration

TAP 5555555555555555

Muxed 9999999999999999

Dedicated1111111111111111

Non Configura-

tion

Muxed 5 57 7 7 79 9111121 7 11131113

Dedicated1111111111111111

Vcc 6 49 6 6 49 6 9 6 16 6 16201620

Vccaux 4444444444848888

VCCPLL 222-222-4-------

VCCIO

Bank0 2222222222424444

Bank1 1122112222424444

Bank2 2222222222424444

Bank3 1122112222424444

Bank4 1122112222424444

Bank5 2222222222424444

Bank6 1122112222424444

Bank7 2222222222424444

GND, GND0-GND7 15 15 20 20 15 15 22 20 22 20 56 20 56 64 56 64

NC - -431- -22-2722692 1

Single Ended/

Differential I/O

per Bank

Bank0 18/9 20/10 20/10 26/13 18/9 20/10 20/10 28/14 20/10 28/14 52/26 28/14 52/26 70/35 52/26 70/35

Bank1 4/2 6/3 18/9 18/9 4/2 6/3 18/9 22/11 18/9 22/11 36/18 22/11 36/18 54/27 36/18 70/35

Bank2 16/8 18/9 18/9 22/11 16/8 18/9 18/9 26/13 18/9 26/13 46/23 26/13 46/23 56/28 46/23 64/32

Bank3 4/2 4/2 16/8 20/10 4/2 4/2 16/8 24/12 16/8 24/12 44/22 24/12 46/23 56/28 46/23 66/33

Bank4 8/4 8/4 18/9 18/9 8/4 8/4 18/9 26/13 18/9 26/13 36/18 26/13 38/19 54/27 38/19 70/35

Bank5 14/7 18/9 20/10 24/12 14/7 18/9 20/10 24/12 20/10 24/12 52/26 24/12 53/26 70/35 53/26 70/35

Bank6 6/3 8/4 18/9 22/11 6/3 8/4 18/9 27/13 18/9 27/13 46/23 27/13 46/23 56/28 46/23 66/33

Bank7 16/8 18/9 18/9 22/11 16/8 18/9 18/9 24/12 18/9 24/12 46/23 24/12 46/23 56/28 46/23 64/32

True LVDS Pairs 

Bonding Out per

Bank

Bank0 0000000000000000

Bank1 0000000000000000

Bank2 3 44 5 3 44 6 4 6 11 6 11141116

Bank3 1 14 5 1 14 6 4 6 11 6 11141117

Bank4 0000000000000000

Bank5 0000000000000000

Bank6 1 24 5 1 24 6 4 6 11 6 11141117

Bank7 3 44 5 3 44 5 4 5 11 5 11141116

DDR Banks

Bonding Out per

I/O Bank1

Bank0 1111111111312424

Bank1 0011001111212324

Bank2 1111111111213334

Bank3 0011001111213334

Bank4 0011001111212324

Bank5 1111111111312424

Bank6 0011001111213334

Bank7 1111111111213334

4-5

Pinout Information

Lattice Semiconductor LatticeXP2 Family Data Sheet

Logic Signal Connections

Package pinout information can be found under “Data Sheets” on the LatticeXP2 product page of the Lattice web-

site a www.latticesemi.com/products/fpga/xp2 and in the Lattice Diamond design software.

Thermal Management

Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal

characteristics of a system, Lattice specifies a maximum allowable junction temperature in all device data sheets.

Designers must complete a thermal analysis of their specific design to ensure that the device and package do not

exceed the junction temperature limits. Refer to the Lattice Thermal Management document to find the device/

package specific thermal values.

For Further Information

• TN1139, Power Estimation and Management for LatticeXP2 Devices

• Power Calculator tool is included with the Lattice Diamond design tool or as a standalone download from 

www.latticesemi.com/products/designsoftware

PCI capable I/Os 

Bonding Out per

Bank

Bank0 18202026182020282028522852705270

Bank1 4 61818 4 618221822362236543670

Bank2 0000000000000000

Bank3 0000000000000000

Bank4 8 81818 8 818261826362638543870

Bank5 14182024141820242024522453705370

Bank6 0000000000000000

Bank7 0000000000000000

1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1 DQSB + 8 DQs + 1 DM

+ Bank VREF1).

Pin Information Summary (Cont.)

Pin Type

XP2-5 XP2-8 XP2-17 XP2-30 XP2-40

132

csBGA 144

TQFP 208

PQFP 256

ftBGA 132

csBGA 144

TQFP 208

PQFP 256

ftBGA 208

PQFP 256

ftBGA 484

fpBGA 256

ftBGA 484

fpBGA 672

fpBGA 484

fpBGA 672

fpBGA

www.latticesemi.com 5-1 Order Info_01.2

August 2008 Data Sheet DS1009

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Part Number Description

LFXP2 – XX E – X XXXXX X

Grade

C = Commercial

I = Industrial

Logic Capacity

5 = 5K LUTs

8 = 8K LUTs

17 = 17K LUTs

30 = 30K LUTs

40 = 40K LUTs

Supply Voltage

E = 1.2V

Speed

5 = Slowest

7 = Fastest

Package

M132 = 132-ball csBGA

FT256 = 256-ball ftBGA

F484 = 484-ball fpBGA

F672 = 672-ball fpBGA

MN132 = 132-ball Lead-Free csBGA

TN144 = 144-pin Lead-Free TQFP

QN208 = 208-pin Lead-Free PQFP

FTN256 = 256-ball Lead-Free ftBGA

FN484 = 484-ball Lead-Free fpBGA

FN672 = 672-ball Lead-Free fpBGA

Device Family

XP2

Ordering Information

The LatticeXP2 devices are marked with a single temperature grade, either Commercial or Industrial, as shown

below.

LFXP2-17E

7FT256C

Datecode

XP2

LFXP2-17E

6FT256I

Datecode

XP2

LatticeXP2 Family Data Sheet

Ordering Information

5-2

Ordering Information

Lattice Semiconductor LatticeXP2 Family Data Sheet

Lead-Free Packaging Commercial

Part Number Voltage Grade Package Pins Temp. LUTs (k)

LFXP2-5E-5MN132C 1.2V -5 Lead-Free csBGA 132 COM 5

LFXP2-5E-6MN132C 1.2V -6 Lead-Free csBGA 132 COM 5

LFXP2-5E-7MN132C 1.2V -7 Lead-Free csBGA 132 COM 5

LFXP2-5E-5TN144C 1.2V -5 Lead-Free TQFP 144 COM 5

LFXP2-5E-6TN144C 1.2V -6 Lead-Free TQFP 144 COM 5

LFXP2-5E-7TN144C 1.2V -7 Lead-Free TQFP 144 COM 5

LFXP2-5E-5QN208C 1.2V -5 Lead-Free PQFP 208 COM 5

LFXP2-5E-6QN208C 1.2V -6 Lead-Free PQFP 208 COM 5

LFXP2-5E-7QN208C 1.2V -7 Lead-Free PQFP 208 COM 5

LFXP2-5E-5FTN256C 1.2V -5 Lead-Free ftBGA 256 COM 5

LFXP2-5E-6FTN256C 1.2V -6 Lead-Free ftBGA 256 COM 5

LFXP2-5E-7FTN256C 1.2V -7 Lead-Free ftBGA 256 COM 5

Part Number Voltage Grade Package Pins Temp. LUTs (k)

LFXP2-8E-5MN132C 1.2V -5 Lead-Free csBGA 132 COM 8

LFXP2-8E-6MN132C 1.2V -6 Lead-Free csBGA 132 COM 8

LFXP2-8E-7MN132C 1.2V -7 Lead-Free csBGA 132 COM 8

LFXP2-8E-5TN144C 1.2V -5 Lead-Free TQFP 144 COM 8

LFXP2-8E-6TN144C 1.2V -6 Lead-Free TQFP 144 COM 8

LFXP2-8E-7TN144C 1.2V -7 Lead-Free TQFP 144 COM 8

LFXP2-8E-5QN208C 1.2V -5 Lead-Free PQFP 208 COM 8

LFXP2-8E-6QN208C 1.2V -6 Lead-Free PQFP 208 COM 8

LFXP2-8E-7QN208C 1.2V -7 Lead-Free PQFP 208 COM 8

LFXP2-8E-5FTN256C 1.2V -5 Lead-Free ftBGA 256 COM 8

LFXP2-8E-6FTN256C 1.2V -6 Lead-Free ftBGA 256 COM 8

LFXP2-8E-7FTN256C 1.2V -7 Lead-Free ftBGA 256 COM 8

Part Number Voltage Grade Package Pins Temp. LUTs (k)

LFXP2-17E-5QN208C 1.2V -5 Lead-Free PQFP 208 COM 17

LFXP2-17E-6QN208C 1.2V -6 Lead-Free PQFP 208 COM 17

LFXP2-17E-7QN208C 1.2V -7 Lead-Free PQFP 208 COM 17

LFXP2-17E-5FTN256C 1.2V -5 Lead-Free ftBGA 256 COM 17

LFXP2-17E-6FTN256C 1.2V -6 Lead-Free ftBGA 256 COM 17

LFXP2-17E-7FTN256C 1.2V -7 Lead-Free ftBGA 256 COM 17

LFXP2-17E-5FN484C 1.2V -5 Lead-Free fpBGA 484 COM 17

LFXP2-17E-6FN484C 1.2V -6 Lead-Free fpBGA 484 COM 17

LFXP2-17E-7FN484C 1.2V -7 Lead-Free fpBGA 484 COM 17

5-3

Ordering Information

Lattice Semiconductor LatticeXP2 Family Data Sheet

Industrial

Part Number Voltage Grade Package Pins Temp. LUTs (k)

LFXP2-30E-5FTN256C 1.2V -5 Lead-Free ftBGA 256 COM 30

LFXP2-30E-6FTN256C 1.2V -6 Lead-Free ftBGA 256 COM 30

LFXP2-30E-7FTN256C 1.2V -7 Lead-Free ftBGA 256 COM 30

LFXP2-30E-5FN484C 1.2V -5 Lead-Free fpBGA 484 COM 30

LFXP2-30E-6FN484C 1.2V -6 Lead-Free fpBGA 484 COM 30

LFXP2-30E-7FN484C 1.2V -7 Lead-Free fpBGA 484 COM 30

LFXP2-30E-5FN672C 1.2V -5 Lead-Free fpBGA 672 COM 30

LFXP2-30E-6FN672C 1.2V -6 Lead-Free fpBGA 672 COM 30

LFXP2-30E-7FN672C 1.2V -7 Lead-Free fpBGA 672 COM 30

Part Number Voltage Grade Package Pins Temp. LUTs (k)

LFXP2-40E-5FN484C 1.2V -5 Lead-Free fpBGA 484 COM 40

LFXP2-40E-6FN484C 1.2V -6 Lead-Free fpBGA 484 COM 40

LFXP2-40E-7FN484C 1.2V -7 Lead-Free fpBGA 484 COM 40

LFXP2-40E-5FN672C 1.2V -5 Lead-Free fpBGA 672 COM 40

LFXP2-40E-6FN672C 1.2V -6 Lead-Free fpBGA 672 COM 40

LFXP2-40E-7FN672C 1.2V -7 Lead-Free fpBGA 672 COM 40

Part Number Voltage Grade Package Pins Temp. LUTs (k)

LFXP2-5E-5MN132I 1.2V -5 Lead-Free csBGA 132 IND 5

LFXP2-5E-6MN132I 1.2V -6 Lead-Free csBGA 132 IND 5

LFXP2-5E-5TN144I 1.2V -5 Lead-Free TQFP 144 IND 5

LFXP2-5E-6TN144I 1.2V -6 Lead-Free TQFP 144 IND 5

LFXP2-5E-5QN208I 1.2V -5 Lead-Free PQFP 208 IND 5

LFXP2-5E-6QN208I 1.2V -6 Lead-Free PQFP 208 IND 5

LFXP2-5E-5FTN256I 1.2V -5 Lead-Free ftBGA 256 IND 5

LFXP2-5E-6FTN256I 1.2V -6 Lead-Free ftBGA 256 IND 5

Part Number Voltage Grade Package Pins Temp. LUTs (k)

LFXP2-8E-5MN132I 1.2V -5 Lead-Free csBGA 132 IND 8

LFXP2-8E-6MN132I 1.2V -6 Lead-Free csBGA 132 IND 8

LFXP2-8E-5TN144I 1.2V -5 Lead-Free TQFP 144 IND 8

LFXP2-8E-6TN144I 1.2V -6 Lead-Free TQFP 144 IND 8

LFXP2-8E-5QN208I 1.2V -5 Lead-Free PQFP 208 IND 8

LFXP2-8E-6QN208I 1.2V -6 Lead-Free PQFP 208 IND 8

LFXP2-8E-5FTN256I 1.2V -5 Lead-Free ftBGA 256 IND 8

LFXP2-8E-6FTN256I 1.2V -6 Lead-Free ftBGA 256 IND 8

5-4

Ordering Information

Lattice Semiconductor LatticeXP2 Family Data Sheet

Part Number Voltage Grade Package Pins Temp. LUTs (k)

LFXP2-17E-5QN208I 1.2V -5 Lead-Free PQFP 208 IND 17

LFXP2-17E-6QN208I 1.2V -6 Lead-Free PQFP 208 IND 17

LFXP2-17E-5FTN256I 1.2V -5 Lead-Free ftBGA 256 IND 17

LFXP2-17E-6FTN256I 1.2V -6 Lead-Free ftBGA 256 IND 17

LFXP2-17E-5FN484I 1.2V -5 Lead-Free fpBGA 484 IND 17

LFXP2-17E-6FN484I 1.2V -6 Lead-Free fpBGA 484 IND 17

Part Number Voltage Grade Package Pins Temp. LUTs (k)

LFXP2-30E-5FTN256I 1.2V -5 Lead-Free ftBGA 256 IND 30

LFXP2-30E-6FTN256I 1.2V -6 Lead-Free ftBGA 256 IND 30

LFXP2-30E-5FN484I 1.2V -5 Lead-Free fpBGA 484 IND 30

LFXP2-30E-6FN484I 1.2V -6 Lead-Free fpBGA 484 IND 30

LFXP2-30E-5FN672I 1.2V -5 Lead-Free fpBGA 672 IND 30

LFXP2-30E-6FN672I 1.2V -6 Lead-Free fpBGA 672 IND 30

Part Number Voltage Grade Package Pins Temp. LUTs (k)

LFXP2-40E-5FN484I 1.2V -5 Lead-Free fpBGA 484 IND 40

LFXP2-40E-6FN484I 1.2V -6 Lead-Free fpBGA 484 IND 40

LFXP2-40E-5FN672I 1.2V -5 Lead-Free fpBGA 672 IND 40

LFXP2-40E-6FN672I 1.2V -6 Lead-Free fpBGA 672 IND 40

5-5

Ordering Information

Lattice Semiconductor LatticeXP2 Family Data Sheet

Conventional Packaging Commercial

Part Number Voltage Grade Package Pins Temp. LUTs (k)

LFXP2-5E-5M132C 1.2V -5 csBGA 132 COM 5

LFXP2-5E-6M132C 1.2V -6 csBGA 132 COM 5

LFXP2-5E-7M132C 1.2V -7 csBGA 132 COM 5

LFXP2-5E-5FT256C 1.2V -5 ftBGA 256 COM 5

LFXP2-5E-6FT256C 1.2V -6 ftBGA 256 COM 5

LFXP2-5E-7FT256C 1.2V -7 ftBGA 256 COM 5

Part Number Voltage Grade Package Pins Temp. LUTs (k)

LFXP2-8E-5M132C 1.2V -5 csBGA 132 COM 8

LFXP2-8E-6M132C 1.2V -6 csBGA 132 COM 8

LFXP2-8E-7M132C 1.2V -7 csBGA 132 COM 8

LFXP2-8E-5FT256C 1.2V -5 ftBGA 256 COM 8

LFXP2-8E-6FT256C 1.2V -6 ftBGA 256 COM 8

LFXP2-8E-7FT256C 1.2V -7 ftBGA 256 COM 8

Part Number Voltage Grade Package Pins Temp. LUTs (k)

LFXP2-17E-5FT256C 1.2V -5 ftBGA 256 COM 17

LFXP2-17E-6FT256C 1.2V -6 ftBGA 256 COM 17

LFXP2-17E-7FT256C 1.2V -7 ftBGA 256 COM 17

LFXP2-17E-5F484C 1.2V -5 fpBGA 484 COM 17

LFXP2-17E-6F484C 1.2V -6 fpBGA 484 COM 17

LFXP2-17E-7F484C 1.2V -7 fpBGA 484 COM 17

Part Number Voltage Grade Package Pins Temp. LUTs (k)

LFXP2-30E-5FT256C 1.2V -5 ftBGA 256 COM 30

LFXP2-30E-6FT256C 1.2V -6 ftBGA 256 COM 30

LFXP2-30E-7FT256C 1.2V -7 ftBGA 256 COM 30

LFXP2-30E-5F484C 1.2V -5 fpBGA 484 COM 30

LFXP2-30E-6F484C 1.2V -6 fpBGA 484 COM 30

LFXP2-30E-7F484C 1.2V -7 fpBGA 484 COM 30

LFXP2-30E-5F672C 1.2V -5 fpBGA 672 COM 30

LFXP2-30E-6F672C 1.2V -6 fpBGA 672 COM 30

LFXP2-30E-7F672C 1.2V -7 fpBGA 672 COM 30

5-6

Ordering Information

Lattice Semiconductor LatticeXP2 Family Data Sheet

Industrial

Part Number Voltage Grade Package Pins Temp. LUTs (k)

LFXP2-40E-5F484C 1.2V -5 fpBGA 484 COM 40

LFXP2-40E-6F484C 1.2V -6 fpBGA 484 COM 40

LFXP2-40E-7F484C 1.2V -7 fpBGA 484 COM 40

LFXP2-40E-5F672C 1.2V -5 fpBGA 672 COM 40

LFXP2-40E-6F672C 1.2V -6 fpBGA 672 COM 40

LFXP2-40E-7F672C 1.2V -7 fpBGA 672 COM 40

Part Number Volt age Grade Package Pins Temp. LUTs (k)

LFXP2-5E-5M132I 1.2V -5 csBGA 132 IND 5

LFXP2-5E-6M132I 1.2V -6 csBGA 132 IND 5

LFXP2-5E-6FT256I 1.2V -6 ftBGA 256 IND 5

Part Number Volt age Grade Package Pins Temp. LUTs (k)

LFXP2-8E-5M132I 1.2V -5 csBGA 132 IND 8

LFXP2-8E-6M132I 1.2V -6 csBGA 132 IND 8

LFXP2-5E-5FT256I 1.2V -5 ftBGA 256 IND 5

LFXP2-8E-5FT256I 1.2V -5 ftBGA 256 IND 8

LFXP2-8E-6FT256I 1.2V -6 ftBGA 256 IND 8

Part Number Volt age Grade Package Pins Temp. LUTs (k)

LFXP2-17E-5FT256I 1.2V -5 ftBGA 256 IND 17

LFXP2-17E-6FT256I 1.2V -6 ftBGA 256 IND 17

LFXP2-17E-5F484I 1.2V -5 fpBGA 484 IND 17

LFXP2-17E-6F484I 1.2V -6 fpBGA 484 IND 17

Part Number Volt age Grade Package Pins Temp. LUTs (k)

LFXP2-30E-5FT256I 1.2V -5 ftBGA 256 IND 30

LFXP2-30E-6FT256I 1.2V -6 ftBGA 256 IND 30

LFXP2-30E-5F484I 1.2V -5 fpBGA 484 IND 30

LFXP2-30E-6F484I 1.2V -6 fpBGA 484 IND 30

LFXP2-30E-5F672I 1.2V -5 fpBGA 672 IND 30

LFXP2-30E-6F672I 1.2V -6 fpBGA 672 IND 30

5-7

Ordering Information

Lattice Semiconductor LatticeXP2 Family Data Sheet

Part Number Volt age Grade Package Pins Temp. LUTs (k)

LFXP2-40E-5F484I 1.2V -5 fpBGA 484 IND 40

LFXP2-40E-6F484I 1.2V -6 fpBGA 484 IND 40

LFXP2-40E-5F672I 1.2V -5 fpBGA 672 IND 40

LFXP2-40E-6F672I 1.2V -6 fpBGA 672 IND 40

May 2007 Data Sheet DS1009

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

www.latticesemi.com 6-1 Further Info_01.1

For Further Information

A variety of technical notes for the LatticeXP2 FPGA family are available on the Lattice Semiconductor web site at 

www.latticesemi.com.

• TN1136, LatticeXP2 sysIO Usage Guide

• TN1137, LatticeXP2 Memory Usage Guide

• TN1138, LatticeXP2 High Speed I/O Interface

• TN1126, LatticeXP2 sysCLOCK PLL Design and Usage Guide

• TN1139, Power Estimation and Management for LatticeXP2 Devices

• TN1140, LatticeXP2 sysDSP Usage Guide

• TN1141, LatticeXP2 sysCONFIG Usage Guide

• TN1142, LatticeXP2 Configuration Encryption and Security Usage Guide

• TN1087, Minimizing System Interruption During Configuration Using TransFR Technology

• TN1220, LatticeXP2 Dual Boot Feature

• TN1130, LatticeXP2 Soft Error Detection (SED) Usage Guide

• TN1143, LatticeXP2 Hardware Checklist

For further information on interface standards refer to the following websites:

• JEDEC Standards (LVTTL, LVCMOS, SSTL, HSTL): www.jedec.org

• PCI: www.pcisig.com

LatticeXP2 Family Data Sheet

Supplemental Information

January 2012 Data Sheet DS1009

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

www.latticesemi.com 7-1

Revision History

Date Version Section Change Summary

May 2007 01.1 — Initial release.

September 2007 01.2 DC and Switching

Characteristics

Added JTAG Port Timing Waveforms diagram.

Updated sysCLOCK PLL Timing table.

Pinout Information Added Thermal Management text section.

February 2008 01.3 Architecture Added LVCMOS33D to Supported Output Standards table.

Clarified: “This Flash can be programmed through either the JTAG or

Slave SPI ports of the device. The SRAM configuration space can also

be infinitely reconfigured through the JTAG and Master SPI ports.”

Added External Slave SPI Port to Serial TAG Memory section. Updated

Serial TAG Memory diagram.

DC and Switching

Characteristics

Updated Flash Programming Specifications table.

Added “8W” specification to Hot Socketing Specifications table.

Updated Timing Tables

Clarifications for IIH in DC Electrical Characteristics table.

Added LVCMOS33D section

Updated DOA and DOA (Regs) to EBR Timing diagrams.

Removed Master Clock Frequency and Duty Cycle sections from the

LatticeXP2 sysCONFIG Port Timing Specifications table. These are

listed on the On-chip Oscillator and Configuration Master Clock Charac-

teristics table.

Changed CSSPIN to CSSPISN in description of tSCS, tSCSS, and tSCSH

parameters. Removed tSOE parameter.

Clarified On-chip Oscillator documentation

Added Switching Test Conditions

Pinout Information Added “True LVDS Pairs Bonding Out per Bank,” “DDR Banks Bonding

Out per I/O Bank,” and “PCI capable I/Os Bonding Out per Bank” to Pin

Information Summary in place of previous blank table “PCI and DDR

Capabilities of the Device-Package Combinations”

Removed pinout listing. This information is available on the LatticeXP2

product web pages

Ordering Information Added XP2-17 “8W” and all other family OPNs.

April 2008 01.4 DC and Switching

Characteristics

Updated Absolute Maximum Ratings footnotes.

Updated Recommended Operating Conditions Table footnotes.

Updated Supply Current (Standby) Table

Updated Initialization Supply Current Table

Updated Programming and Erase Flash Supply Current Table

Updated Register to Register Performance Table

Updated LatticeXP2 External Switching Characteristics Table

Updated LatticeXP2 Internal Switching Characteristics Table

Updated sysCLOCK PLL Timing Table

LatticeXP2 Family Data Sheet

Revision History

7-2

Revision History

Lattice Semiconductor LatticeXP2 Family Data Sheet

April 2008

(cont.)

01.4

(cont.)

DC and Switching

Characteristics (cont.)

Updated Flash Download Time (From On-Chip Flash to SRAM) Table

Updated Flash Program Time Table

Updated Flash Erase Time Table

Updated FlashBAK (from EBR to Flash) Table

Updated Hot Socketing Specifications Table footnotes

Pinout Information Updated Signal Descriptions Table

June 2008 01.5 Architecture Removed Read-Before-Write sysMEM EBR mode.

Clarification of the operation of the secondary clock regions.

DC and Switching

Characteristics

Removed Read-Before-Write sysMEM EBR mode.

Pinout Information Updated DDR Banks Bonding Out per I/O Bank section of Pin Informa-

tion Summary Table.

August 2008 01.6 — Data sheet status changed from preliminary to final.

Architecture Clarification of the operation of the secondary clock regions.

DC and Switching

Characteristics

Removed “8W” specification from Hot Socketing Specifications table.

Removed "8W" footnote from DC Electrical Characteristics table.

Updated Register-to-Register Performance table.

Ordering Information Removed “8W” option from Part Number Description.

Removed XP2-17 “8W” OPNs.

April 2011 01.7 DC and Switching

Characteristics

Recommended Operating Conditions table, added footnote 5.

On-Chip Flash Memory Specifications table, added footnote 1.

BLVDS DC Conditions, corrected column title to be Z0 = 90 ohms.

sysCONFIG Port Timing Specifications table, added footnote 1 for 

tDINIT

January 2012 01.8 Multiple Added support for Lattice Diamond design software.

Architecture Corrected information regarding SED support.

DC and Switching

Characteristics

Added reference to ESD Performance Qualification Summary informa-

tion.

Date Version Section Change Summary

Section II. LatticeXP2 Family Technical Notes

www.latticesemi.com 8-1 tn1136_01.3

June 2010 Techn ical Note TN1136

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Introduction

The LatticeXP2™ sysIO™ buffers give the designer the ability to easily interface with other devices using advanced

system I/O standards. This technical note describes the sysIO standards available and how they can be imple-

mented using Lattice’s ispLEVER® design software.

sysIO Buffer Overview

The LatticeXP2 sysIO interface contains multiple Programmable I/O Cells (PIC) blocks. Each PIC contains two Pro-

grammable I/Os (PIO), PIOA and PIOB, connected to their respective sysIO Buffers. Two adjacent PIOs can be

joined to provide a differential I/O pair (labeled as “T” and “C”).

Each Programmable I/O (PIO) includes a sysIO Buffer and I/O Logic (IOLOGIC). The LatticeXP2 sysIO buffers

supports a variety of single-ended and differential signaling standards. The sysIO buffer also supports the DQS

strobe signal that is required for interfacing with the DDR memory. One of every 16/18 PIOs in the LatticeXP2 con-

tains a delay element to facilitate the generation of DQS signals. The DQS signal from the bus is used to strobe the

DDR data from the memory into input register blocks. For more information on the architecture of the sysIO buffer

please refer to the LatticeXP2 Family Data Sheet.

The IOLOGIC includes input, output and tristate registers that implement both single data rate (SDR) and double

data rate (DDR) applications along with the necessary clock and data selection logic. Programmable delay lines

and dedicated logic within the IOLOGIC are used to provide the required shift to incoming clock and data signals

and the delay required by DQS inputs in DDR memory. The DDR implementation in the IOLOGIC and the DDR

memory interface support are discussed in more detail in TN1138, LatticeXP2 High Speed I/O Interface.

Supported sysIO Standards

The LatticeXP2 sysIO buffer supports both single-ended and differential standards. Single-ended standards can be

further subdivided into internally ratioed standard such as LVCMOS, LVTTL and PCI; and externally referenced

standards such as HSTL and SSTL. The buffers support the LVTTL, LVCMOS 1.2, 1.5, 1.8, 2.5 and 3.3V stan-

dards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive strength, bus

maintenance (weak pull-up, weak pull-down, or a bus-keeper latch). Other single-ended standards supported

include SSTL and HSTL. Differential standards supported include MLVDS, LVDS, RSDS, BLVDS, LVPECL, differ-

ential SSTL and differential HSTL. Tables 1 and 2 list the sysIO standards supported in LatticeXP2 devices.

Table 8-1. Supported Input Sta ndards

Input Standard VREF (Nom.) VCCIO1 (Nom.)

Single Ended Interfaces

LVTTL — —

LVCMOS3 3 — —

LVCMOS2 5 — —

LVCMOS1 8 — 1.8

LVCMOS1 5 — 1.5

LVCMOS1 2 — —

PCI 33 — 3.3

HSTL18 Class I, II 0.9 —

HSTL15 Class I 0.75 —

SSTL3 Class I, II 1.5 —

LatticeXP2 sysIO Usage Guide

8-2

Lattice Semiconductor LatticeXP2 sysIO Usage Guide

SSTL2 Class I, II 1.25 —

SSTL18 Class I, II 0.9 —

Differential Interfaces

Differential SSTL18 Class I, II — —

Differential SSTL2 Class I, II — —

Differential SSTL3 Class I, II — —

Differential HSTL15 Class I — —

Differential HSTL18 Class I, II — —

LVDS, MLVDS, LVPECL, BLVDS, RSDS — —

1 When not specified, VCCIO can be set anywhere in the valid operating range.

Table 8-2. Supported Output Standards

Output Standard Drive VCCIO (Nom.)

Single-ended Interfaces

LVTTL 4mA, 8mA, 12mA, 16mA, 20mA 3.3

LVTTL, Open Drain 4mA, 8mA, 12mA, 16mA, 20mA —

LVCMOS33 4mA, 8mA, 12mA 16mA, 20mA 3.3

LVCMOS25 4mA, 8mA, 12mA, 16mA, 20mA 2.5

LVCMOS18 4mA, 8mA, 12mA, 16mA 1.8

LVCMOS15 4mA, 8mA 1.5

LVCMOS12 2mA, 6mA 1.2

LVCMOS33, Open Drain 4mA, 8mA, 12mA 16mA, 20mA —

LVCMOS25, Open Drain 4mA, 8mA, 12mA 16mA, 20mA —

LVCMOS18, Open Drain 4mA, 8mA, 12mA 16mA —

LVCMOS15, Open Drain 4mA, 8mA —

LVCMOS12, Open Drain 2mA, 6mA —

PCI332N/A 3.3

HSTL18 Class I 8mA, 12mA 1.8

HSTL18 Class II N/A 1.8

HSTL15 Class I 4mA, 8mA 1.5

SSTL3 Class I, II N/A 3.3

SSTL2 Class I 8mA, 12mA 2.5

SSTL2 Class II 16mA, 20mA 2.5

SSTL18 Class I N/A 1.8

SSTL18 Class II 8mA, 12mA 1.8

Differential Interfaces

Differential SSTL3, Class I, II N/A 3.3

Differential SSTL2, Class I 8mA, 12mA 2.5

Differential SSTL2, Class II 16mA, 20mA 2.5

Differential SSTL18, Class I N/A 1.8

Differential SSTL18, Class II 8mA, 12mA 1.8

Differential HSTL18, Class I 8mA, 12mA 1.8

Differential HSTL18, Class II N/A 1.8

Differential HSTL15, Class I 4mA, 8mA 1.5

Table 8-1. Supported Input Sta ndards (Continued)

Input Standard VREF (Nom.) VCCIO1 (Nom.)

8-3

Lattice Semiconductor LatticeXP2 sysIO Usage Guide

sysIO Banking Scheme

LatticeXP2 devices have eight general purpose programmable sysIO banks. Each of the eight general purpose

sysIO banks has a VCCIO supply voltage, and two reference voltages, VREF1 and VREF2. Figure 8-1 shows the eight

general purpose banks.

On the top and bottom banks, the sysIO buffer pair consists of two single-ended output drivers and two sets of sin-

gle-ended input buffers (both ratioed and referenced). The left and right sysIO buffer pair consists of two single-

ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). The referenced input

buffer can also be configured as a differential input. True LVDS support is available on only 50% of the left and right

I/Os (starting with the topmost pairs). There are no LVDS on the top and bottom I/Os. In 50% of the pairs there is

also one differential output driver. The two pads in the pair are described as “true” and “comp”, where the true pad

is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated

with the negative side of the differential input buffer.

SPI Flash Interface

The SPI pins (master/slave) are multiplexed with the I/Os in Bank 7. The two dedicated pins CFG[0] and TOE are

JTAG Interface

The JTAG pins are located between Banks 2 and 3 and are powered by VCCJ.

Figure 8-1. LatticeXP2 sysIO Bankin g

LVDS N/A 2.5

MLVDS1 N/A 2.5

BLVDS1N/A 2.5

LVPECL1N/A 3.3

RSDS1N/A 2.5

1. Emulated with external resistors.

2. PCI33 is PCIX compatible.

Table 8-2. Supported Output Standards (Continued)

Output Standard Drive VCCIO (Nom.)

Bank 0 Bank 1

Bank 5 Bank 4

Bank 7 Bank 2

Bank 3

Bank 6

8-4

Lattice Semiconductor LatticeXP2 sysIO Usage Guide

VCCIO (1.2V/1.5V/1.8V/2.5V/3.3V)

There are a total of eight VCCIO supplies, VCCIO0 - VCCIO7. Each bank has a separate VCCIO supply that powers the

single-ended output drivers and the ratioed input buffers such as LVTTL, LVCMOS, and PCI. LVTTL, LVCMOS3.3,

LVCMOS2.5 and LVCMOS1.2 also have fixed threshold options allowing them to be placed in any bank. The VCCIO

voltage applied to the bank determines the ratioed input standards that can be supported in that bank. It is also

used to power the differential output drivers.

VCCAUX (3.3V)

In addition to the bank VCCIO supplies, devices have a VCC core logic power supply and a VCCAUX auxiliary supply

that powers the differential and referenced input buffers. VCCAUX is used to supply I/O reference voltage requiring

3.3V to satisfy the common-mode range of the drivers and input buffers.

VCCJ (1.2V/1.5V/1.8V/2.5V/3.3V)

The JTAG pins have a separate VCCJ power supply that is independent of the bank VCCIO supplies. VCCJ deter-

mines the electrical characteristics of the LVCMOS JTAG pins, both the output high level and the input threshold.

Table 8-3 shows a summary of all the required power supplies.

Table 8-3. Power Supplies

Input Reference Voltage (VREF1, VREF2)

Each bank can support up to two separate VREF input voltages, VREF1 and VREF2, that are used to set the thresh-

old for the referenced input buffers. The locations of these VREF pins are pre-determined within the bank. These

pins can be used as regular I/Os if the bank does not require a VREF voltage.

VREF1 for DDR Memory Interface

When interfacing to DDR memory, the VREF1 input must be used as the reference voltage for the DQS and DQ

input from the memory. A voltage divider between VREF1 and GND is used to generate an on-chip reference volt-

age that is used by the DQS transition detector circuit. This voltage divider is only present on VREF1 it is not avail-

able on VREF2. For more information on the DQS transition detect logic and its implementation, please refer to

Lattice technical note number TN1138, LatticeXP2 High Speed I/O Interface. For DDR1 memory interfaces, the

VREF1 should be connected to 1.25V. Therefore, only SSTL25_II signaling is allowed. For DDR2 memory interfaces

this should be connected to 0.9V, and only SSTL18_II signaling is allowed.

Mixed Voltage Support in a Bank

The LatticeXP2 sysIO buffer is connected to three parallel ratioed input buffers. These three parallel buffers are

connected to VCCIO, VCCAUX and VCC, giving support for thresholds that track with VCCIO as well as fixed thresh-

olds for 3.3V (VCCAUX) and 1.2V (VCC) inputs. This allows the input threshold for ratioed buffers to be assigned on

a pin-by-pin basis rather than tracking with VCCIO. This option is available for all 1.2V, 2.5V and 3.3V ratioed inputs

and is independent of the bank VCCIO voltage. For example, if the bank VCCIO is 1.8V, it is possible to have 1.2V

and 3.3V ratioed input buffers with fixed thresholds, as well as 2.5V ratioed inputs with tracking thresholds.

Power Sup-

ply Description Value1

VCC Core Power Supply 1.2V

VCCIO2Power Supply for the I/O Banks 1.2V/1.5V/1.8V/2.5V/3.3V

VCCAUX Auxiliary Power Supply 3.3V

VCCJ2Power Supply for JTAG Pins 1.2V/1.5V/1.8V/2.5V/3.3V

1. Refer to the LatticeXP2 Family Data Sheet for recommended min. and max. values.

2. If VCCIO or VCCJ is set to 3.3V, they MUST be connected to the same power supply as VCCAUX.

8-5

Lattice Semiconductor LatticeXP2 sysIO Usage Guide

Prior to device configuration, the ratioed input thresholds always tracks the bank VCCIO. This option only takes

effect after configuration. Output standards within a bank are always set by VCCIO. Table 8-4 shows the sysIO stan-

dards that can be mixed in the same bank.

Table 8-4. Mixed Voltage Support

sysIO Standards Supported by Bank

Table 8-5. I/O Standards Supported by Bank

VCCIO

Input sysIO Standards Output sysIO Standards

1.2V 1.5V 1.8V 2.5V 3.3V 1.2V 1.5V 1.8V 2.5V 3.3V

1.2V Yes Yes Yes Yes

1.5V Yes Yes Yes Yes Yes

1 . 8 V Ye s Ye s Ye s Ye s Yes

2 . 5 V Ye s Ye s Ye s Ye s

3.3V Yes Yes Yes Yes

Description Top Side

Banks 0-1 Right Side

Banks 2-3 Bottom Side

Banks 4-5 Left Side

Banks 6- 7

I/O Buffers Single-ended Single-ended and

Differential

Single-ended Single-ended and

Differential

Output Standards

Supported

LVT T L

LVC M OS 3 3

LVC M OS 2 5

LVC M OS 1 8

LVC M OS 1 5

LVC M OS 1 2

SSTL18 Class I, II

SSTL25 Class I, II

SSTL33 Class I, II

HSTL15 Class I

HSTL18_I, II

SSTL18D Class I, II

SSTL25D Class I, II

SSTL33D Class I, II

HSTL15D Class I

HSTL18D Class I, II

MLVDS

LVD S 25 E 1

LVPECL1

BLVDS1

RSDS1

LVT T L

LVC M OS 3 3

LVC M OS 2 5

LVC M OS 1 8

LVC M OS 1 5

LVC M OS 1 2

SSTL18 Class I, II

SSTL25 Class I, II

SSTL33 Class I, II

HSTL15 Class I

HSTL18 Class I, II

SSTL18D Class I, II

SSTL25D Class I, II

SSTL33D Class I, II

HSTL15D Class I

HSTL18D Class I, II

MLVDS

LVD S

LVD S 25 E 1

LVPECL1

BLVDS1

RSDS1

LVTTL

LVC MOS33

LVC MOS25

LVC MOS18

LVC MOS15

LVC MOS12

SSTL18 Class I, II

SSTL2 Class I, II

SSTL3 Class I, II

HSTL15 Class I

HSTL18 Class I, II

SSTL18D Class I, II

SSTL25D Class I, II,

SSTL33D Class I, II

HSTL15D Class I

HSTL18D Class I, II

MLVDS

LVDS25E1

LVPECL1

BLVDS1

RSDS1

LVTTL

LVCMOS33

LVCMOS25

LVCMOS18

LVCMOS15

LVCMOS12

SSTL18 Class I

SSTL2 Class I, II

SSTL3 Class I, II

HSTL15 Class I, III

HSTL18 Class I, II, III

SSTL18D Class I,

SSTL25D Class I, II,

SSTL33D_I, II

HSTL15D Class I

HSTL18D Class I, II

MLVDS

LVDS

LVDS25E1

LVPECL1

BLVDS1

RSDS1

Inputs All Single-ended,

Differential

All Single-ended,

Differential

All Single-ended,

Differential

All Single-ended,

Differential

Clock Inputs All Single-ended,

Differential

All Single-ended,

Differential

All Single-ended,

Differential

All Single-ended,

Differential

PCI Support PCI33 with clamp PCI33 without clamp PCI33 with clamp PCI33 without clamp

LVDS Output Buffers LVDS (3.5mA) Buffers2LVDS (3.5mA) Buffers2

1. These differential standards are implemented by using a complementary LVCMOS driver with external resistor pack.

2. Available only on 50% of the I/Os in the bank.

8-6

Lattice Semiconductor LatticeXP2 sysIO Usage Guide

LVCMOS Buffer Configurations

All LVCMOS buffer have programmable pull, programmable drive and programmable slew configurations that can

be set in the software.

Bus Maintenance Circuit

Each pad has a weak pull-up, weak pull-down and weak buskeeper capability. The pull-up and pull-down settings

offer a fixed characteristic, which is useful in creating wired logic such as wired ORs. However, current can be

slightly higher than other options, depending on the signal state. The bus-keeper option latches the signal in the

last driven state, holding it at a valid level with minimal power dissipation. Users can also choose to turn off the bus

maintenance circuitry, minimizing power dissipation and input leakage. Note that in this case, it is important to

ensure that inputs are driven to a known state to avoid unnecessary power dissipation in the input buffer. The inter-

nal weak pull-up is enabled on all unused pins.

Programmable Drive

Each LVCMOS or LVTTL, as well as some of the referenced (SSTL and HSTL) output buffers, has a programmable

drive strength option. This option can be set for each I/O independently. The drive strength settings available are

2mA, 4mA, 6mA, 8mA, 12mA, 16mA and 20mA. Actual options available vary by the I/O voltage. The user must

consider the maximum allowable current per bank and the package thermal limit current when selecting the drive

strength. Table 8-6 shows the available drive settings for each of the output standards.

Table 8-6. Programmable Drive Va lues for Single-ended Buffers

Programmable Slew Rate

Each LVCMOS or LVTTL output buffer pin also has a programmable output slew rate control that can be configured

for either low noise or high-speed performance. Each I/O pin has an individual slew rate control. This allows

designers to specify slew rate control on a pin-by-pin basis. This slew rate control affects both the rising and falling

edges.

Open-Drain Control

All LVCMOS and LVTTL output buffers can be configured to function as open drain outputs. The user can imple-

ment an open drain output by turning on the OPENDRAIN attribute in the software.

Differential SSTL and HSTL support

The single-ended driver associated with the complementary ‘C’ pad can optionally be driven by the complement of

the data that drives the single-ended driver associated with the true pad. This allows a pair of single-ended drivers

to be used to drive complementary outputs with the lowest possible skew between the signals. This is used for driv-

ing complementary SSTL and HSTL signals (as required by the differential SSTL and HSTL clock inputs on syn-

Single Ended I/O Standard Programmable Drive (mA)

HSTL15_I 4, 8

HSTL18_I 8, 12

SSTL25_I 8, 12

SSTL25_II 16, 20

SSTL18_II 8, 12

LVCMOS1 2 2, 6

LVCMOS1 5 4, 8

LVCMOS18 4, 8, 12, 16

LVCMOS25 4, 8, 12, 16, 20

LVCMOS33 4, 8, 12, 16, 20

LVTTL 4, 8, 12, 16, 20

8-7

Lattice Semiconductor LatticeXP2 sysIO Usage Guide

chronous DRAM and synchronous SRAM devices respectively). This capability is also used in conjunction with off-

chip resistors to emulate LVPECL, and BLVDS output drivers.

Table 8-7. Programmable Drive Values for Differential Buffers

PCI Support with Programmable PCICLAMP

Each sysIO buffer can be configured to support PCI33. The buffers on the top and bottom sides of the device have

an optional PCI clamp diode that may optionally be specified in the ispLEVER design tools.

Programmable PCICLAMP can be turned ON or OFF. This option is available on each I/O independently on the top

and bottom side banks.

Programmable Input Delay

Each input can optionally be delayed before it is passed to the core logic or input registers. The primary use for the

input delay is to achieve zero hold time for the input registers when using a direct drive primary clock. To arrive at

zero hold time, the input delay will delay the data by at least as much as the primary clock injection delay. This

option can be turned ON or OFF for each I/O independently in the software using the FIXEDDELAY attribute. This

attribute is described in more detail in the software sysIO attribute section. Appendix A shows how this feature can

be enabled in the software using HDL attributes.

Software sysIO Attributes

sysIO attributes can be specified in the HDL, using the Spreadsheet View of the Design Planner or in the ASCII

preference file (.lpf) file directly. Appendices A, B and C list examples of how these can be assigned using each of

these methods. This section describes each of these attributes in detail.

IO_TYPE

This is used to set the sysIO standard for an I/O. The VCCIO required to set these I/O standards are embedded in

the attribute names itself. There is no separate attribute to set the VCCIO requirements. Table 8-8 lists the available

I/O types.

Differential I/O Standard Programmable Drive (mA)

HSTL15D_I 4, 8

HSTL18D_I 8, 12

SSTL25D_I 8, 12

SSTL25D_II 16, 20

SSTL18D_II 8, 12

8-8

Lattice Semiconductor LatticeXP2 sysIO Usage Guide

Table 8-8. IO_TYPE Attribute Values

OPENDRAIN

LVCMOS and LVTTL I/O standards can be set to open drain configuration by using the OPENDRAIN attribute.

Values: ON, OFF

Default: OFF

DRIVE

The DRIVE attribute will set the programmable drive strength for the output standards that have programmable

drive capability

sysIO Signaling Standard IO_TYPE

DEFAULT LVCMOS25

LVDS 2.5 V LVD S 25

RSDS RSDS1

Emulated LVDS 2.5V LVDS25E1

Bus LVDS 2.5V BLVDS251

LVPECL 3.3V LVPECL331

HSTL18 Class I and II HSTL18_I, HTSL18_II

Differential HSTL 18 Class I and II HSTL18D_I, HSTL18D_II

HSTL 15 Class I HSTL15_I

Differential HSTL 15 Class I HSTL15D_I

SSTL 33 Class I and II SSTL33_I, SSTL33_II

Differential SSTL 33 Class I and II SSTL33D_I, SSTL3D_II

SSTL 25 Class I and II SSTL25_I,SSTL25_II

Differential SSTL 25 Class I and II SSTL25D_I, SSTL25D_II

SSTL 18 Class I and II SSTL18_I, SSTL18_II

Differential SSTL 18 Class I and II SSTL18D_I,SSTL18D_II

LVTTL LVTTL33

3.3V LVCMOS LVCMOS33

2.5V LVCMOS LVCMOS25

1.8V LVCMOS LVCMOS18

1.5V LVCMOS LVCMOS15

1.2V LVCMOS LVCMOS12

3.3V PCI PCI33

MLVDS MLVDS1

1. These differential standards are implemented by using a complementary 

LVCMOS driver with external resistor pack.

8-9

Lattice Semiconductor LatticeXP2 sysIO Usage Guide

Table 8-9. DRIVE Settings

PULLMODE

The PULLMODE attribute is available for all the LVTTL, LVCMOS and PCI inputs and outputs. This attribute can be

enabled for each I/O independently.

Values: UP, DOWN, NONE, KEEPER

Default: UP

Table 8-10. PULLMODE Values

PCICLAMP

PCI33 inputs on the top and bottom of the device have an optional PCI clamp that is enabled via the PCICLAMP

attribute. The PCICLAMP is also available for all LVCMOS33 and LVTTL inputs.

Values: ON, OFF

Table 8-11. PCICLAMP Values

SLEWRATE

The SLEWRATE attribute is available for all LVTTL and LVCMOS output drivers. Each I/O pin has an individual

slew rate control. This allows a designer to specify slew rate control on a pin-by-pin basis.

Values: FAST, SLOW

Default: FAST

Output Standard DRIVE (mA) Default (mA)

HSTL15_I/ HSTL15D_I 4, 8 8

HSTL18_I/ HSTL18D_I 8, 12 12

SSTL25_I/ SSTL25D_I 8, 12 8

SSTL25_II/ SSTL25D_II 16, 20 16

SSTL18_II/SSTL18D_II 8, 12 12

LVCMOS12 2, 6 6

LVCMOS15 4, 8 8

LVCMOS18 4, 8, 12, 16 12

LVCMOS25 4, 8, 12, 16, 20 12

LVCMOS33 4, 8, 12, 16, 20 12

LVTTL 4, 8, 12, 16, 20 12

PULL Options PULLMODE Value

Pull-up (Default) UP

Pull-down DOWN

Bus Keeper KEEPER

Pull Off NONE

Input Type PCICLAMP Value

PCI33 ON (default), OFF

LVCMOS33 OFF (default), ON

LVTTL OFF (default), ON

8-10

Lattice Semiconductor LatticeXP2 sysIO Usage Guide

FIXEDDELAY

The FIXEDDELAY attribute is available to each input pin. This attribute, when enabled, is used to achieve zero hold

time for the input registers when using global clock. This attribute can only be assigned in the HDL source.

Values: TRUE, FALSE

Default: FALSE

INBUF

By default, all the unused input buffers are disabled. The INBUF attribute is used to enable the unused input buffers

when performing a boundary scan test. This is a global attribute and can be globally set to ON or OFF.

Values: ON, OFF

Default: ON

DIN/DOUT

This attribute can be used to assign I/O registers. Using DIN will assert an input register and using the DOUT attri-

bute will assert an output register. By default, the software will try to assign the I/O registers, if applicable. The user

can turn this OFF by using the synthesis attribute or by using the Spreadsheet View of the Design Planner. These

attributes can only be applied to registers.

LOC

This attribute can be used to make pin assignments to the I/O ports in the design. This attributes is only used when

the pin assignments are made in HDL source. Designers can also assign pins directly using the Spreadsheet View

of the Design Planner in the ispLEVER software. The appendices explain this in further detail.

Design Considerations and Usage

This section discusses some of the design rules and considerations that must be taken into account when design-

ing with the LatticeXP2 sysIO buffer

Banking Rules

•If V

CCIO or VCCJ for any bank is set to 3.3 V, it is recommended that it be connected to the same power supply as

VCCAUX, thus minimizing leakage.

•If V

CCIO or VCCJ for any bank is set to 1.2V, it is recommended that it be connected to the same power supply as

VCC, thus minimizing leakage.

• When implementing DDR memory interfaces, the VREF1 of the bank is used to provide reference to the interface

pins and cannot be used to power any other referenced inputs.

• Only the top and bottom banks (banks 0, 1, 4 and 5)) will support PCI clamps.

• All legal input buffers should be independent of bank VCCIO, except for 1.8V and 1.5V buffers, which require a

bank VCCIO of 1.8V and 1.5V.

Differential I/O Rules

• All banks can support LVDS input buffers. Only the banks on the right and left sides (Banks 2, 3, 6 and 7) will

support True Differential output buffers. The banks on all sides will support the LVDS input buffers. The user can

use emulated LVDS output buffers on these banks.

• All banks support emulated differential buffers using external resistor pack and complementary LVCMOS drivers.

• Only 50% of the I/Os on the left and right sides can provide LVDS output buffer capability. LVDS can only be

assigned to the TRUE pad. The ispLEVER design tool will automatically assign the other I/Os of the differential

pair to the complementary pad. Refer to the device data sheet to see the pin listings for all LVDS pairs.

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Lattice Semiconductor LatticeXP2 sysIO Usage Guide

Differential I/O Implementation

The LatticeXP2 devices support a variety of differential standards as detailed in the following sections.

LVDS

True LVDS (LVDS25) drivers are available on 50% of the I/Os on the left and right side of the devices. LVDS input

support is provided on all sides of the device. All four sides of the device support LVDS using complementary LVC-

MOS drivers with external resistors (LVDS25E). Refer to the LatticeXP2 Family Data Sheet for a detailed explana-

tion of these LVDS implementations.

BLVDS

All single-ended sysIO buffers pairs support the Bus-LVDS standard using complementary LVCMOS drivers with

external resistors. Please refer to the LatticeXP2 Family Data Sheet for a detailed explanation of BLVDS implemen-

tation.

RSDS

All single-ended sysIO buffers pairs support RSDS standard using complementary LVCMOS drivers with external

resistors. Please refer to the LatticeXP2 Family Data Sheet for a detailed explanation of RSDS implementation.

LVPECL

All the sysIO buffers will support LVPECL inputs. LVPECL outputs are supported using complementary LVCMOS

driver with external resistors. Please refer to the LatticeXP2 Family Data Sheet for a detailed explanation of

LVPECL implementation.

Differential SSTL and HSTL

All single-ended sysIO buffers pairs support differential SSTL and HSTL. Please refer to the LatticeXP2 Family

Data Sheet for a detailed explanation of Differential HSTL and SSTL implementation.

MLVDS

All single-ended sysIO buffers pairs support MLVDS standard using complementary LVCMOS drivers with external

resistors. Please refer to the LatticeXP2 Family Data Sheet for a detailed explanation of MLVDS implementation.

Technical Support Assistance

Hotline: 1-800-LATTICE (North America)

+1-503-268-8001 (Outside North America)

e-mail: techsupport@latticesemi.com

Internet: www.latticesemi.com

Revision History

Date Version Change Summary

February 2007 01.0 Initial release.

April 2008 01.1 Updated Supported Output Standards table.

Updated sysIO Banking figure.

February 2009 01.2 Updated I/O Standards Supported by Bank table.

June 2010 01.3 Added Appendix D - sysIO Attributes Using the Diamond Spreadsheet

View User Interface.

8-12

Lattice Semiconductor LatticeXP2 sysIO Usage Guide

Appendix A. HDL Attributes for Synplicity® and Precision® RTL Synthesis

Using these HDL attributes, designers can assign the sysIO attributes directly in their source. The attribute defini-

tion and syntax for the appropriate synthesis vendor must be used. Below are a list of all the sysIO attributes, syn-

tax and examples for Precision RTL Synthesis and Synplicity. This section only lists the sysIO buffer attributes for

these devices. These attributes are available through the ispLEVER software Help system.

VHDL Synplicity/Precision RTL Synthesis

This section lists syntax and examples for all the sysIO Attributes in VHDL when using the Precision RTL Synthesis

or Synplicity synthesis tools.

Syntax

Table 8-12. VHDL Attribute Syntax for Synplicity and Precision RTL Synthesis

Examples

IO_TYPE

--***Attribute Declaration***

ATTRIBUTE IO_TYPE: string;

--***IO_TYPE assignment for I/O Pin***

ATTRIBUTE IO_TYPE OF portA: SIGNAL IS “PCI33”;

ATTRIBUTE IO_TYPE OF portB: SIGNAL IS “LVCMOS33”;

ATTRIBUTE IO_TYPE OF portC: SIGNAL IS “LVDS25”;

OPENDRAIN

--***Attribute Declaration***

ATTRIBUTE OPENDRAIN: string;

--***DRIVE assignment for I/O Pin***

ATTRIBUTE OPENDRAIN OF portB: SIGNAL IS “ON”;

Attribute Syntax

IO_TYPE attribute IO_TYPE: string;

attribute IO_TYPE of Pinname: signal is “IO_TYPE Value”;

OPENDRAIN attribute OPENDRAIN: string;

attribute OPENDRAIN of Pinname: signal is “OpenDrain Value”;

DRIVE attribute DRIVE: string;

attribute DRIVE of Pinname: signal is “Drive Value”;

PULLMODE attribute PULLMODE: string;

attribute PULLMODE of Pinname: signal is “Pullmode Value”;

PCICLAMP attribute PCICLAMP: string;

attribute PCICLAMP of Pinname: signal is “PCIClamp V alue”;

SLEWRATE attribute PULLMODE: string;

attribute PULLMODE of Pinname: signal is “Slewrate Value”;

FIXEDDELAY attribute FIXEDDELAY: string;

attribute FIXEDDELAY of Pinname: signal is “Fixeddelay Value”;

DIN attribute DIN: string;

attribute DIN of Pinname: signal is “ ”;

DOUT attribute DOUT: string;

attribute DOUT of Pinname: signal is “ ”;

LOC attribute LOC: string;

attribute LOC of Pinname: signal is “pin_locations”;

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Lattice Semiconductor LatticeXP2 sysIO Usage Guide

DRIVE

--***Attribute Declaration***

ATTRIBUTE DRIVE: string;

--***DRIVE assignment for I/O Pin***

ATTRIBUTE DRIVE OF portB: SIGNAL IS “20”;

PULLMODE

--***Attribute Declaration***

ATTRIBUTE PULLMODE : string;

--***PULLMODE assignment for I/O Pin***

ATTRIBUTE PULLMODE OF portA: SIGNAL IS “DOWN”;

ATTRIBUTE PULLMODE OF portB: SIGNAL IS “UP”;

PCICLAMP

--***Attribute Declaration***

ATTRIBUTE PCICLAMP: string;

--***PULLMODE assignment for I/O Pin***

ATTRIBUTE PCICLAMP OF portA: SIGNAL IS “ON”;

SLEWRATE

--***Attribute Declaration***

ATTRIBUTE SLEWRATE : string;

--*** SLEWRATE assignment for I/O Pin***

ATTRIBUTE SLEWRATE OF portB: SIGNAL IS “FAST”;

FIXEDDELAY

--***Attribute Declaration***

ATTRIBUTE FIXEDDELAY: string;

--*** SLEWRATE assignment for I/O Pin***

ATTRIBUTE FIXEDDELAY OF portB: SIGNAL IS “TRUE”;

DIN/DOUT

--***Attribute Declaration***

ATTRIBUTE din : string;

ATTRIBUTE dout : string;

--*** din/dout assignment for I/O Pin***

ATTRIBUTE din OF input_vector: SIGNAL IS “ “;

ATTRIBUTE dout OF output_vector: SIGNAL IS “ “;

LOC

--***Attribute Declaration***

ATTRIBUTE LOC : string;

--*** LOC assignment for I/O Pin***

ATTRIBUTE LOC OF input_vector: SIGNAL IS “E3,B3,C3 “;

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Lattice Semiconductor LatticeXP2 sysIO Usage Guide

Verilog Synplicity

This section lists syntax and examples for all the sysIO Attributes in Verilog using the Synplicity synthesis tool.

Syntax

Table 8-13. Verilog Synplicity Attribute Syntax

Examples

//IO_TYPE, PULLMODE, SLEWRATE and DRIVE assignment

output portB /*synthesis IO_TYPE=”LVCMOS33” PULLMODE =”UP” SLEWRATE =”FAST”

DRIVE =”20”*/;

output portC /*synthesis IO_TYPE=”LVDS25” */;

//OPENDRAIN

output portA /*synthesis OPENDRAIN =”ON”*/;

//PCICLAMP

output portA /*synthesis IO_TYPE=”PCI33” PULLMODE =”PCICLAMP”*/;

// Fixeddelay

input load /* synthesis FIXEDDELAY=”TRUE” */;

// Place the flip-flops near the load input

input load /* synthesis din=”” */;

// Place the flip-flops near the outload output

output outload /* synthesis dout=”” */;

//I/O pin location

input [3:0] DATA0 /* synthesis loc=”E3,B1,F3”*/;

//Register pin location

reg data_in_ch1_buf_reg3 /* synthesis loc=”R40C47” */;

//Vectored internal bus

reg [3:0] data_in_ch1_reg /*synthesis loc =”R40C47,R40C46,R40C45,R40C44” */;

Attribute Syntax

IO_TYPE PinType PinName /* synthesis IO_TYPE=”IO_Type Value”*/;

OPENDRAIN PinType PinName /* synthesis OPENDRAIN =”OpenDrain Value”*/;

DRIVE PinType PinName /* synthesis DRIVE=”Drive Value”*/;

PULLMODE PinType PinName /* synthesis PULLMODE=”Pullmode Value”*/;

PCICLAMP PinType PinName /* synthesis PCICLAMP =” PCIClamp Value”*/;

SLEWRATE PinType PinName /* synthesis SLEWRATE=”Slewrate Value”*/;

FIXEDDELAY PinType PinName /* synthesis FIXEDDELAY=”Fixeddelay Value”*/;

DIN PinType PinName /* synthesis DIN=” “*/;

DOUT PinType PinName /* synthesis DOUT=” “*/;

LOC PinType PinName /* synthesis LOC=”pin_locations “*/;

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Lattice Semiconductor LatticeXP2 sysIO Usage Guide

Verilog Precision

This section lists syntax and examples for all the sysIO Attributes in Verilog using the Precision RTL Synthesis tool.

Syntax

Table 8-14. Verilog Precision Attribute Syntax

Examples

//****IO_TYPE ***

//pragma attribute portA IO_TYPE PCI33

//pragma attribute portB IO_TYPE LVCMOS33

//pragma attribute portC IO_TYPE SSTL25_II

//*** Opendrain ***

//pragma attribute portB OPENDRAIN ON

//pragma attribute portD OPENDRAIN OFF

//*** Drive ***

//pragma attribute portB DRIVE 20

//pragma attribute portD DRIVE 8

//*** Pullmode***

//pragma attribute portB PULLMODE UP

//*** PCIClamp***

//pragma attribute portB PCICLAMP ON

//*** Slewrate ***

//pragma attribute portB SLEWRATE FAST

//pragma attribute portD SLEWRATE SLOW

// ***Fixeddelay***

// pragma attribute load FIXEDDELAY TRUE

//***LOC***

//pragma attribute portB loc E3

Attribute Syntax

IO_TYPE //pragma attribute PinName IO_TYPE IO_TYPE Value

OPENDRAIN // pragma attribute PinName OPENDRAIN OpenDrain Value

DRIVE // pragma attribute PinName DRIVE Drive Value

PULLMODE // pragma attribute PinName IO_TYPE Pullmode Value

PCICLAMP // pragma attribute PinName PCICLAMP PCIClamp Value

SLEWRATE // pragma attribute PinName IO_TYPE Slewrate Value

FIXEDDELAY // pragma attribute PinName IO_TYPE Fixeddelay Value

LOC // pragma attribute PinName LOC pin_location

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Lattice Semiconductor LatticeXP2 sysIO Usage Guide

Appendix B. sysIO Attributes Using the Design Planner User Interface

Designers can assign sysIO buffer attributes using the Design Planner GUI available in the ispLEVER design tool.

If you are using Lattice Diamond™ design software, refer to Appendix D. The Pin Attribute Sheet list all the ports in

a design and all the available sysIO attributes as preferences. By clicking on each of these cells, a list of all the

valid I/O preference for that port is displayed. Each column takes precedence over the next. Therefore, when a par-

ticular IO_TYPE is chosen, the DRIVE, PULLMODE and SLEWRATE columns will only list the valid combinations

for that IO_TYPE. The pin locations can be locked using the pin location column of the Pin Attribute sheet. Right-

clicking on a cell will list the available pin locations. The Spreadsheet View will also conduct a DRC check to search

for any incorrect pin assignments.

Designers can enter DIN/DOUT preferences using the Cell Attributes sheet of the Preference Editor. All the prefer-

ences assigned using the Preference Editor are written into the preference file (.prf).

Figures 8-2 and 8-3 show the Pin Attribute sheet and the Cell Attribute sheet views of the preference editor. For fur-

ther information on how to use the Preference Editor, refer to the ispLEVER Help documentation in the Help menu

option of the software.

Figure 8-2. Port Attributes Tab

8-17

Lattice Semiconductor LatticeXP2 sysIO Usage Guide

Figure 8-3. Cell Attrib utes Tab

8-18

Lattice Semiconductor LatticeXP2 sysIO Usage Guide

Appendix C. sysIO Attributes Using Preference File (ASCII File)

Designers can enter sysIO attributes directly in the preference (.lpf) file as sysIO buffer preferences. The LPF file is

a post-synthesis FPGA constraint file that stores logical preferences that have been created or modified in the

Design Planner or Text Editor. It also contains logical preferences originating in the HDL source that have been

modified.

. Below are a list of sysIO buffer preference syntax and examples.

IOBUF

This preference is used to assign the attribute IO_TYPE, PULLMODE, SLEWRATE,PCICLAMP and DRIVE.

Syntax

IOBUF [ALLPORTS | PORT <port_name> | GROUP <group_name>] (keyword=<value>)+;

where:

<port_name> = These are not the actual top-level port names, but should be the signal name attached to the port.

PIOs in the physical design (.ncd) file are named using this convention. Any multiple listings or wildcarding should

be done using GROUPs

Keyword = IO_TYPE, OPENDRAIN, DRIVE, PULLMODE, PCICLAMP, SLEWRATE.

Example

IOBUF PORT “port1” IO_TYPE=LVTTL33 OPENDRAIN=ON DRIVE=8 PULLMODE=UP

PCICLAMP =OFF SLEWRATE=FAST;

DEFINE PORT GROUP “bank1” “in*” “out_[0-31]”;

IOBUF GROUP “bank1” IO_TYPE=SSTL18_II;

LOCATE

When this preference is applied to a specified component, it places the component at a specified site and locks the

component to the site. If applied to a specified macro instance, it places the macro’s reference component at a

specified site, places all of the macro’s pre-placed components (that is, all components that were placed in the

macro’s library file) in sites relative to the reference component, and locks all of these placed components at their

sites. Below are some of the LOCATE syntax and examples. For further information, refer to the ispLEVER Help

documentation in the Help menu option of the software.

Syntax

LOCATE [COMP <comp_name> | MACRO <macro_name>] SITE <site_name>;

LOCATE VREF <vref_name> SITE <site_name>;

Note: If the comp_name, macro_name, or site_name begins with anything other than an alpha character (for exam-

ple, “11C7”), you must enclose the name in quotes. Wildcard expressions are allowed in <comp_name>.

Examples

This command places the port Clk0 on the site A4:

LOCATE COMP “Clk0” SITE “A4”;

This command places the component PFU1 on the site named R1C7:

LOCATE COMP “PFU1” SITE “R1C7”;

LOCATE VREF “ref1” SITE PR29C;

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Lattice Semiconductor LatticeXP2 sysIO Usage Guide

USE DIN CELL

This preference specifies the given register to be used as an input flip-flop.

Syntax

USE DIN CELL <cell_name>;

where:

<cell_name> := string

Example

USE DIN CELL “din0”;

USE DOUT CELL

Specifies the given register to be used as an output flip-flop.

Syntax

USE DOUT CELL <cell_name>;

where:

<cell_name> := string

Example

USE DOUT CELL “dout1”;

GROUP VREF

This preference is used to group all the components that need to be associated to one VREF pin within a bank.

Syntax

LOCATE VREF <vref_name> SITE <site_name>;

Example

IOBUF GROUP <group_name> BANK=<bank_name> VREF=<Vref_name>

LOCATE VREF “ref1” SITE PR29C;

LOCATE VREF “ref2” SITE PR48B;

IOBUF GROUP "group1" IO_TYPE=SSTL18_II BANK=0 VREF=vref1 ;

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Lattice Semiconductor LatticeXP2 sysIO Usage Guide

Appendix D. sysIO Attributes Using the Diamond Spreadsheet View User

Interface

sysIO buffer attributes can be assigned using the Spreadsheet View available in the Lattice Diamond design soft-

ware. The Port Assignments Sheet lists all the ports in a design and all the available sysIO attributes in multiple col-

umns. Click on each of these cells for a list of all valid I/O preferences for that port. Each column takes precedence

over the next. Therefore, when you choose a particular IO_TYPE, the columns for the DRIVE, PULLMODE, SLE-

WRATE and other attributes will only list the valid entries for that IO_TYPE.

Pin locations can be locked using the Pin column of the Port Assignments sheet or using the Pin Assignments

sheet. You can right-click on a cell and go to Assign Pins to see a list of available pins.

The Spreadsheet View also has an option to run a DRC check to check for any incorrect pin assignments. You can

enter the DIN/DOUT preferences using the Cell Mapping Tab. All the preferences assigned using the Spreadsheet

View are written into the logical preference file (.lpf).

Figure 8-4 shows the Port Assignments Sheet of the Spreadsheet View. For further information on how to use the

Spreadsheet View, refer to the Diamond Help documentation, available in the Help menu option of the software.

Figure 8-4. Port Attributes Tab of Spreadsheet View

Users can create a VREF pin using the Spreadsheet View as shown in Figure 8-5 and then assign VREF for a

bank using the VREF Column in the Ports Assignment Tab of the Spreadsheet View as show in Figure 8-6. See the

Diamond online help for a more detailed description of this setting.

Figure 8-5. Creating a VREF in Spreadsheet View

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Lattice Semiconductor LatticeXP2 sysIO Usage Guide

Figure 8-6. Assigning VREF for an Input Port in Spreadsheet View

www.latticesemi.com 9-1 tn1126_01.1

February 2010 Technical Note TN1126

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Introduction

This user’s guide describes the clock resources available in the LatticeXP2™ device architecture. Details are pro-

vided for primary clocks, secondary clocks and edge clocks as well as clock elements such as PLLs, clock dividers

and more.

The number of PLLs and DDR-DLLs for each device is listed in Table 9-1.

Table 9-1. Number of PLLs and DDR-DLLs

Clock/Control Distribution Network

LatticeXP2 devices provide global clock distribution in the form of eight quadrant-based primary clocks and flexible

secondary clocks. Two edge clocks are also provided on every edge of the device. Other clock sources include

clock input pins, internal nodes, PLLs, and clock dividers.

LatticeXP2 Top Level View

Figure 9-1 provides a view of the primary clocking structure of the LatticeXP2-40 device.

Figure 9-1. LatticeXP2 Clocking Structure (LFXP2-40)

Parameter Description XP2-5 XP2-8 XP2-17 XP2-30 XP2-40

Number of GPLLsGeneral purpose PLL 22444

Number of DDR-DLLs DDL for DDR applications 22222

GPLL

sysIO Bank 5 sysIO Bank 4

sysIO Bank 0 sysIO Bank 1

sysIO Bank 6 sysIO Bank 7

sysIO Bank 3 sysIO Bank 2

GPLL

QUADRANT BRQUADRANT BL

QUADRANT TRQUADRANT TL

Primary Clocks

ECLK2

ECLK1

ECLK2

ECLK1

ECLK2

ECLK1

ECLK2

ECLK1

DQSDLL

GPLL GPLL

DQSDLL

CLKDIV

LatticeXP2 sysCLOCK PLL

Design and Usage Guide

9-2

LatticeXP2 sysCLOCK PLL

Lattice Semiconductor Design and Usage Guide

Primary Clocks

Each quadrant receives up to eight primary clocks. Two of these clocks provide the Dynamic Clock Selection (DCS)

feature. The six primary clocks without DCS can be specified in the Pre-map Preference Editor as ‘Primary Pure’

and the two DCS clocks as ‘Primary-DCS’.

The sources of primary clocks are:

• PLL outputs

• CLKDIV outputs

• Dedicated clock pins

• Internal nodes

Secondary Clocks

The LatticeXP2 secondary clocks are a flexible region-based clocking resource. Each region can have four inde-

pendent clock inputs. Since the secondary clock is a regional resource, it can cross the primary clock quadrant

boundaries.

There are eight secondary clock muxes per quadrant. Each mux has inputs from four different sources. Three of

these are from internal nodes. The fourth input comes from a primary clock pin. The input sources are not neces-

sarily located in the same quadrant as the mux. This structure enables global use of secondary clocks.

The sources of secondary clocks are:

• Dedicated clock pins

• Clock Divider (CLKDIV) outputs

• Internal nodes

Table 9-2 lists the number of secondary clock regions in LatticeXP2 devices.

Table 9-2. Number of Secondary Clock Regions

Edge Clocks

The LatticeXP2 device has two Edge Clocks (ECLK) per side. These clocks, which have low injection time and

skew, are used to clock I/O registers. Edge clock resources are designed for high speed I/O interfaces with high

fanout capability. Refer to Appendix B for detailed information on ECLK locations and connectivity.

The sources of edge clocks are:

• Left and Right Edge Clocks

– Dedicated clock pins

– PLL outputs

– PLL input pins

– Internal nodes

• Top and Bottom Edge Clocks

– Dedicated clock pins

– Internal nodes

Edge clocks can directly drive the secondary clock resources and general routing resources. Refer to Figure 9-21

for detailed information on edge clock routing.

Parameter XP2-5 XP2-8 XP2-17 XP2-30 XP2-40

Number of regions 66668

9-3

LatticeXP2 sysCLOCK PLL

Lattice Semiconductor Design and Usage Guide

Figure 9-2 describes the structure of the secondary clocks and edge clocks.

Figure 9-2. LatticeXP2 Secondary Clocks and Edge Clocks (LFXP2-40)

Primary Clock Note

The CLKOP must be used as the feedback source to optimize PLL performance.

Most designers use PLLs for clock tree injection removal mode and the CLKOP should be assigned to a primary

clock. This is done automatically by the software unless otherwise specified by the user.

CLKOP can route only to CLK0 to CLK5, while CLKOS/CLKOK can route to all primary clocks (CLK0 TO CLK7).

When CLK6 or CLK7 is used as a primary clock and there is only one clock input to the DCS, the DCS is assigned

as a buffer mode by the software. Please see the DCS section of this document for detailed information.

Specifying Clocks in the Design Tools

If desired, designers can specify the clock resources, primary, secondary or edge to be used to distribute a given

clock source. Figure 9-3 illustrates how this can be done in the Pre-map Preference editor. Alternatively, the prefer-

ence file can be used, as discussed in Appendix C.

Primary-Pure and Primary-DCS

Primary Clock Net can be assigned to either Primary-Pure (CLK0 to CLK5) or Primary-DCS (CLK6 and CLK7).

Global Primary Clock and Quadrant Primary Clock

Global Primary Clock

If a primary clock is not assigned as a quadrant clock, the software assumes it is a global clock.

There are six Global Primary/Pure clocks and two Global Primary/DCS clocks available.

sysIO Bank 5 sysIO Bank 4

sysIO Bank 0 sysIO Bank 1

sysIO Bank 6 sysIO Bank 7

sysIO Bank 3 sysIO Bank 2

GPLLGPLL

ECLK2

ECLK1

ECLK2

ECLK1

ECLK2

ECLK1

DQSDLL

GPLLGPLL DQSDLL

Secondary Clock

Region 2

Secondary Clock

Region 5Region 1

Secondary Clock

Region 6

Secondary Clock

Region 3

Secondary Clock

Region 4

Secondary Clock

Region 7

Secondary Clock

Region 8

DSP Row

EBR Row

9-4

LatticeXP2 sysCLOCK PLL

Lattice Semiconductor Design and Usage Guide

Quadrant Primary Clock

Any primary clock may be assigned to a quadrant clock. The clock may be assigned to a single quadrant or to two

adjacent quadrants (not diagonally adjacent).

When a quadrant clock net is used, the user must ensure that the registers each clock drives can be assigned in

that quadrant without any routing issues.

In the Quadrant Primary Clocking scheme, the maximum number of primary clocks is 32, as long as all the primary

clock sources are available.

Figure 9-3. Clock Attributes in the Pre-map Preference Editor

Refer to Appendix A for detailed clock network diagrams.

sysCLOCK™ PLL

The LatticeXP2 PLL provides features such as clock injection delay removal, frequency synthesis, phase/duty

cycle adjustment, and dynamic delay adjustment. Figure 9-4 shows the block diagram of the LatticeXP2 PLL.

Figure 9-4. LatticeXP2 PLL Block Diagram

CLKI

Divider

CLKFB

Divider

CLKOP

Divider

Phase Duty

Cycle

Duty T rim

CLKOK

Divider

Lock

Detect

RST

CLKFB

CLKI

WRDEL

DDUTY

DPHASE

LOCK

CLKOP

CLKOK

CLKOS

Internal Feedback

RSTK

÷3

Phase &

Frequency

Detector

Voltage

Controlled

Oscillator/

Loop

Filter

CLKOK2

9-5

LatticeXP2 sysCLOCK PLL

Lattice Semiconductor Design and Usage Guide

Functional Description

PLL Divider and Delay Blocks

Input Clock (CLKI) Divider

The CLKI divider is used to control the input clock frequency into the PLL block. The divider setting directly corre-

sponds to the divisor of the output clock. The input and output of the input divider must be within the input and out-

put frequency ranges specified in the device data sheet.

Feedback Loop (CLKFB) Divider

The CLKFB divider is used to divide the feedback signal. Effectively, this multiplies the output clock, because the

divided feedback must speed up to match the input frequency into the PLL block. The PLL block increases the out-

put frequency until the divided feedback frequency equals the input frequency. The input and output of the feed-

back divider must be within the input and output frequency ranges specified in the device data sheet.

Output Clock (CLKOP) Divider

The CLKOP divider serves the dual purposes of squaring the duty cycle of the VCO output and scaling up the VCO

frequency into the 435MHz to 870MHz range to minimize jitter. The CLKOP divider values are the same whether or

not the CLKOS is used.

CLKOK Divider

The CLKOK divider acts as a source for the global clock nets. It divides the CLKOP signal of the PLL by the value

of the divider to produce lower frequency clock.

CLKOK2 Divider

The CLKOK2 is CLKOP divided by 3 for generating 140 MHz from 420 MHz to support SPI4.2.

Phase Adjustment and Duty Cycle Select (Static Mode)

Users can program CLKOS with Phase and Duty Cycle options. Phase adjustment can be done in 22.5° steps. The

duty cycle resolution is 1/16th of a period except 1/16th and 15/16th duty cycle options are not supported to avoid

minimum pulse violation.

Dynamic Phase Adjustment (DPHASE) and Dynamic Duty Cycle (DDUTY) Select

The Phase Adjustment and Duty Cycle Select can be controlled in dynamic mode. When this mode is selected,

both the Phase Adjustment and Duty Cycle Select must be in dynamic mode. If only one of the features is to be

used in dynamic mode, users can set the other control inputs with the fixed logic levels of their choice.

Duty Trim Adjustment

With the LatticeXP2 device family, the duty cycle can be fine-tuned with the Duty Trim Adjustment.

Fine Delay Adjust

This optional feature is controlled by the input port, WRDEL. See information on the WRDEL input in the next sec-

tion of this document.

PLL Inputs and Outputs

CLKI Input

The CLKI signal is the reference clock for the PLL. It must conform to the specifications in the data sheet in order

for the PLL to operate correctly. The CLKI can be derived from a dedicated dual-purpose pin or from routing.

RST Input

The PLL reset occurs under two conditions. At power-up an internal power-up reset signal from the configuration

block resets the PLL. The user-controlled PLL reset signal RST is provided as part of the PLL module that can be

driven by an internally generated reset function or a pin. This RST signal resets all internal PLL counters, flip-flops

(including the M-Divider) and the charge pump. The M-Divider reset synchronizes the M-Divider output to the input

clock. When RST goes inactive, the PLL will start the lock-in process, and will take the tLOCK time to complete the

PLL lock. Figure 9-5 shows the timing diagram of the RST input. RST is active high. The RST signal is optional.

9-6

LatticeXP2 sysCLOCK PLL

Lattice Semiconductor Design and Usage Guide

Figure 9-5. RST Input Timing Diagram

RSTK Input

RSTK is the reset input for the K-Divider. This K-Divider reset is used to synchronize the K-Divider output clock to

the input clock. LatticeXP2 has an optional gearbox in the I/O cell for both outputs and inputs. The K-Divider reset

is useful for the gearbox implementation. RSTK is active high.

CLKFB Input

The feedback signal to the PLL, which is fed through the feedback divider, can be derived from the Primary Clock

net (CLKOP), a preferred pin, directly from the CLKOP divider or from general routing. External feedback allows the

designer to compensate for board-level clock alignment.

CLKOP Output

The sysCLOCK PLL main clock output, CLKOP, is a signal available for selection as a primary clock. This clock sig-

nal is available at the CLK_OUT pin.

CLKOS Output with Pha se and Duty Cycle Select

The sysCLOCK PLL auxiliary clock output, CLKOS, is a signal available for selection as a primary clock. The

CLKOS is used when phase shift and/or duty cycle adjustment is desired. The programmable phase shift allows for

different phase in increments of 22.5°. The duty select feature provides duty select in 1/16th of the clock period.

This feature is also supported in Dynamic Control Mode.

CLKOK Output with Lower Frequency

The CLKOK is used when a lower frequency is desired. It is a signal available for selection as a primary clock.

CLKOK2 Output

This extra clock is provided for SPI4.2 application. The 420 MHz CLKOP clock is divided by 3, producing 140 MHz.

The clock can also be used for any applications where CLKOP-divided-by-3 is required.

LOCK Output

The LOCK output provides information about the status of the PLL. After the device is powered up and the input

clock is valid, the PLL will achieve lock within the specified lock time. Once lock is achieved, the PLL lock signal will

be asserted. If, during operation, the input clock or feedback signals to the PLL become invalid, the PLL will lose

lock. However, when the input clock completely stops, the LOCK output will remain in its last state, since it is inter-

nally registered by this clock. It is recommended to assert PLL RST to re-synchronize the PLL to the reference

clock. The LOCK signal is available to the FPGA routing to implement generation of RST. ModelSim® simulation

models take two to four reference clock cycles from RST release to LOCK high.

Dynamic Phase and Dynamic Duty Cycle Adjustment

The DPHASE[3:0] port is used with the Dynamic Phase Adjustment feature to allow the user to connect a control

signal to the PLL. The DDUTY[3:0] port is used with the Dynamic Duty Adjustment feature to allow the user to con-

nect a control signal to the PLL. The DPHASE and DDUTY ports are listed in Table 9-3.

The Dynamic Phase and Dynamic Duty Cycle Adjustment features will be discussed in more detail in later sections

of this document.

tLOCK

tRST

PLL_RST

LOCK

9-7

LatticeXP2 sysCLOCK PLL

Lattice Semiconductor Design and Usage Guide

Table 9-3. Dynamic Phase and Duty Cycle Adjust Ports

WRDEL (Write Delay)

The fine delay option supports SPI4.2. The PLL has a coarse phase adjust feature in which a cycle is divided into

16 equal steps (22.5°). For SPI4.2 running at 840 Mbps, the clock frequency is 420 MHz. At this frequency, the

period is roughly 150 ps. This is slightly too coarse for dynamic phase adjust requirements. It may be more effective

to use increments half as large. Combined with coarse phase adjust, a 70 ps (nominal) step provides effectively 32

steps of phase adjustment. This fine delay only applies to CLKOS (just like the coarse phase adjust). This is conve-

nient since it allows one GPLL to be used for both read and write (where read uses CLKOS and write uses

CLKOP).

PLL Attributes

The PLL utilizes several attributes that allow the configuration of the PLL through source constraints and a prefer-

ence file. The following section details these attributes and their usage.

FIN

The input frequency can be any value within the specified frequency range based on the divider settings.

CLKI_DIV, CLKFB_DIV, CLKOP_DIV, CLKOK_DIV

These dividers determine the output frequencies of each output clock. The user is not allowed to input an invalid

combination. Valid combinations are determined by the input frequency, the dividers, and the PLL specifications.

Note: Unlike PLLs in the LatticeECP™, LatticeEC™, LatticeXP™ and MachXO™ devices, the CLKOP divider val-

ues are the same whether or not CLKOS is used.

The CLKOP_DIV value is calculated to maximize the fVCO within the specified range based on FIN and

CLKOP_FREQ in conjunction with the CLKI_DIV and CLKFB_DIV values. These value settings are designed such

that the output clock duty cycle is as close to 50% as possible. Table 9-4 shows the possible divider ranges.

Table 9-4. Divider Ranges

FREQUENCY_PIN_CLKI, FREQUENCY _PIN_CLKOP, FREQUENCY_PIN_CLKOK

These input and output clock frequencies determine the divider values.

CLKOP Frequency Tolerance

When the desired output frequency is not achievable, users may enter the frequency tolerance of the clock output.

PHASEADJ (Phase Shift Adjust)

The PHASEADJ attribute is used to select Phase Shift for CLKOS output. The phase adjustment is programmable

in 22.5° increments.

Port Name I/O Description

DPHASE[3:0] I Dynamic Phase Adjust inputs

DDUTY[3:0] I Dynamic Duty Cycle Adjust inputs

Attribute Name Value Default

CLKI Divider Setting CLKI_DIV 1 to 43 1

CLKFB Divider Setting CLKFB_DIV 1 to 43 1

CLKOP Divider Setting CLKOP_DIV 2, 4, 8, 16, 32, 48, 64, 80 8

CLKOK Divider Setting CLKOK_DIV 2, 4, 6,.., 126, 128 2

9-8

LatticeXP2 sysCLOCK PLL

Lattice Semiconductor Design and Usage Guide

DUTY (Duty Cycle)

The DUTY attribute is used to select the Duty Cycle for CLKOS output. The Duty Cycle is programmable at 1/16th

of the period increment. Steps 2 to 14 are supported. 1/16th and 15/16th duty cycles are not supported to avoid the

minimum pulse width violation.

FB_MODE

There are three sources of feedback signals that can drive the CLKFB Divider: Internal, CLKOP (Clock Tree) and

user clock. CLKOP (Clock Tree) feedback is used by default. Internal feedback takes the CLKOP output at CLKOP

Divider output before the Clock Tree to minimize the feedback path delay. The user clock feedback is driven from

the dedicated pin, clock pin or user-specified internal logic.

DUTY_TRIM Adjustment (Dynamic mode only)

Users can fine tune the duty cycle of CLKOP and/or CLKOS with the DUTY_TRIM feature when Dynamic

PHASE/DUTY Adjustment is selected.

• TRIM Polarity Select: Users can select either rising edge or falling edge of clock to trim.

• TRIM Delay of CLKOP can be set to 0 to 7 steps of unit trim delay.

• TRIM Delay of CLKOS can be set to 0 to 3 steps of unit trim delay.

CLKOS/CLKOK/CLKOK2 Select

Users select these output clocks only when they are used in the design.

CLKOP/CLKOS/CLKOK BYPASS

These bypasses are enabled if set. CLKI is directly routed to its corresponding output clock.

RST/RSTK Select

Users may select these reset signals only when they are used in the design.

LatticeXP2 PLL Primitive Definition

One PLL primitive is used for LatticeXP2 PLL implementation. Figure 9-6 shows the LatticeXP2 PLL primitive

library symbols.

Figure 9-6. LatticeXP2 PLL Primitive Symbol

EPLLD Design Migration from LatticeECP2 to LatticeXP2

The EPLLD generated for LatticeECP2 can be used with minor changes. If the configuration does not include

Dynamic Phase and Duty Options, the migration is fully supported. If Dynamic Phase and Duty Options are

included, the user must tie the DPAMODE port to ground.

Dynamic Phase/Duty Mode

This mode sets both Dynamic Phase Adjustment and Dynamic Duty Select at the same time. There are two

modes, “Dynamic Phase and Dynamic Duty” and “Dynamic Phase and 50% Duty”.

Dynamic Phase and 50% Duty

This mode allows users to set up Dynamic Phase inputs only. The 50% Duty Cycle is handled internally by the isp-

LEVER® software. The DDUTY[3:0] ports are user-transparent in this mode.

EHXPLLE

RST

RSTK

CLKI

CLKFB

WRDEL

DPHASE[3:0]

DDUTY[3:]

CLKOP

CLKOS

CLKOK

CLKOK2

LOCK

9-9

LatticeXP2 sysCLOCK PLL

Lattice Semiconductor Design and Usage Guide

Dynamic Phase and Dynamic Duty

This mode allows designers to use both DDPHASE[3:0] and DDUTY[3:0] ports to input dynamic values.

To use Dynamic Phase Adjustment with a fixed duty cycle other than a 50%, simply set the DDUTY[3:0] inputs to

the desired duty cycle value. Figure 9-7 illustrates an example circuit.

Example: Assume a design uses dynamic phase adjustment and a fixed duty cycle select and the desired duty

cycle in 3/16th of a period. The setup should be as shown in Figure 9-7.

Figure 9-7. Example of Dynamic Phase Adjustment with a Fixed Duty Cycle of 3/16th of a Period

Dynamic Phase Adjustment/Duty Cycle Select

Phase Adjustment settings are described in Table 9-5.

Table 9-5. Phase Adjustment Settings

DPHASE[3:0] Phase (°)

0000 0

0001 22.5

0010 45

0011 67.5

0100 90

0101 112.5

0110 135

0111 157.5

1000 180

1001 202.5

1010 225

1011 247.5

1100 270

1101 292.5

1110 315

1111 337.5

DPHASE[3]

DPHASE[2]

DPHASE[1]

DPHASE[0]

DPAMODE PLL

DDUTY[3]

DDUTY[2]

DDUTY[1]

DDUTY[0]

DPHASE[3:0]

9-10

LatticeXP2 sysCLOCK PLL

Lattice Semiconductor Design and Usage Guide

Duty Cycle Select settings are described in Table 9-6.

Table 9-6. Duty Cycle Select Settings

PLL Usage in IPexpress™

IPexpress is used to create and configure a PLL. The graphical user interface is used to select parameters for the

PLL. The result is an HDL model to be used in the simulation and synthesis flow.

Figure 9-8 shows the main window when PLL is selected. The only entry required in this window is the module

name. Other entries are set to the project settings. Users may change these entries, if desired. After entering the

module name of choice, clicking on Customize will open the Configuration Tab window as shown in Figure 9.

DDUTY[3:0] Duty Cycle

(1/16th of a Period) Commen t

0000 0 Not Supported

0001 1 Not Supported

0010 2

0011 3

0100 4

0101 5

0110 6

0111 7

1000 8

1001 9

1010 10

1011 11

1100 12

1101 13

1110 14

1111 15 Not Supported

Note: PHASE/DUTY_CTNL is selected in the GUI ‘PLL Phase & Duty Options’ box and if it is set to ‘Dynamic

Mode’, then both DPHASE[3:0] and DDUTY[3:0] inputs must be provided. If one of these inputs is a fixed value,

the inputs must be tied to the desired fixed logic levels.

9-11

LatticeXP2 sysCLOCK PLL

Lattice Semiconductor Design and Usage Guide

Figure 9-8. IPexpress Main Window

Configuration Tab

The Configuration Tab lists all user accessible attributes with default values set. Upon completion, clicking Gener-

ate will generate source and constraint files. Users may choose to use the .lpc file to load parameters.

Configuration Modes

There are two modes that can be used to configure the PLL in the Configuration Tab, Frequency Mode and Divider

Mode.

Frequency Mode: In this mode, the user enters input and output clock frequencies and the software calculates the

divider settings. If the output frequency entered is not achievable the nearest frequency will be displayed in the

‘Actual’ text box. After input and output frequencies are entered, clicking the Calculate button will display the

divider values.

Divider Mode: In this mode, the user sets the divider settings with input frequency. Users must choose the CLKOP

Divider value to maximize the fVCO and achieve optimum PLL performance. After input frequency and divider set-

tings are set, clicking the Calculate button will display the frequencies. Figure 9-9 shows the Configuration Tab.

9-12

LatticeXP2 sysCLOCK PLL

Lattice Semiconductor Design and Usage Guide

Figure 9-9. LatticeXP2 PLL Configuration Tab

Table 9-7 describes the user parameters in the IPexpress GUI and their usage.

Table 9-7. User Parameters in the IPexpress GUI

User Parameters Description Range Default

Frequency Mode User desired CLKI and CLKOP frequency ON/OFF ON

Divider Mode User desired CLKI frequency and dividers

settings ON/OFF OFF

CLKI Frequency Input Clock frequency 10 MHz to

435 MHz 100 MHz

Divider Input Clock Divider Setting (Divider Mode) 1 to 43 1

CLKFB

Feedback Mode Feedback Mode Internal, CLKOP,

User Clock CLKOP

Divider Feedback Clock Divider Setting (Divider

Mode) 1 to 43 1

PLL Phase & Duty Options

None No Phase & Duty Options ON/OFF ON

Static Mode CLKOS Phase/Duty in Static Mode ON/OFF OFF

Dynamic Mode

CLKOS Dynamic Mode Phase/Duty 

Setting ON/OFF OFF

CLKOS Duty Trimming ON/OFF OFF

CLKOP Duty Trimming ON/OFF OFF

9-13

LatticeXP2 sysCLOCK PLL

Lattice Semiconductor Design and Usage Guide

PLL Modes of Operation

PLLs have many uses within a logic design. The two most popular are Clock Injection Removal and Clock Phase

Adjustment. These two modes of operation are described below.

PLL Clock Injection Removal

In this mode the PLL is used to reduce clock injection delay. Clock injection delay is the delay from the input pin of

the device to a destination element such as a flip-flop. The phase detector of the PLL aligns the CLKI with CLKFB.

If the CLKFB signal comes from the clock tree (CLKOP), then the PLL delay and the clock tree delay is removed.

Figure 9-10 Illustrates an example block diagram and waveform.

CLKOP

Bypass Bypass PLL: CLKOP = CLKI ON/OFF OFF

Desired Frequency User enters desired CLKOP frequency 10 MHz to

435 MHz 100 MHz

Divider CLKOP Divider Setting (Divider Mode) 2, 4, 8, 16, 32,

48, 64, 80 8

Tolerance CLKOP tolerance users can tolerate 0.0, 0.1, 0.2, 0.5,

0.1, 0.2, 0.5, 1.0 0.0

Actual Frequency Actual frequency achievable. Read only — —

Rising Rising Edge Trim ON/OFF OFF

Falling Falling Edge Trim ON/OFF OFF

Delay Multiplier Number of delay steps 0 to 7 0

CLKOS

Enable Enable CLKOS output clock ON/OFF OFF

Bypass Bypass PLL: CLKOS = CLKI ON/OFF OFF

Phase Shift CLKOS Static Phase Shift 0°, 22.5°,

45°..337.5° 0°

Rising Rising Edge Trim ON/OFF OFF

Delay Multiplier Number of Delay steps 0 to 7 0

CLKOK

Enable Enable CLKOS output clock ON/OFF OFF

Bypass Bypass PLL: CLKOK = CLKI ON/OFF OFF

Frequency User enters desired CLKOK frequency 78.125 kHz to

217.5 MHz 50 MHz

Divider CLKOK Divider Setting 2 to 128 2

Tolerance CLKOK tolerance users can tolerate 0.0, 0.1, 0.2, 0.5,

0.1, 0.2, 0.5, 1.0 0.00

Actual Frequency Actual frequency achievable. Read only — —

CLKOK2 Enable Enable CLKOK2 output clock ON/OFF OFF

Provide PLL Reset Provide PLL Reset Port (RESET) ON/OFF OFF

Provide CLKOK Divide Reset Provide CLKOK Reset Port (RSTK) ON/OFF OFF

Provide CLKOS Fine Delay Port Provide CLKOS Fine Delay Port (WRDEL) ON/OFF OFF

Import LPC to ispLEVER Project Import .lpc file to ispLEVER project ON/OFF OFF

Table 9-7. User Parameters in the IPexpress GUI (Continued)

User Parameters Description Range Default

9-14

LatticeXP2 sysCLOCK PLL

Lattice Semiconductor Design and Usage Guide

Figure 9-10. Clock Injection Delay Removal Application

PLL Clock Phase Adjustment

In this mode the PLL is used to create fixed phase relationships in 22.5° increments. Creating fixed phase relation-

ships is useful for forward clock interfaces where a specific relationship between clock and data is required.

The fixed phase relationship can be used between CLKI and CLKOS or between CLKOP and CLKOS.

Figure 9-11. CLKOS Phase Adjustment from CLKOP

IPexpress Output

There are two IPexpress outputs that are important for use in the design. The first is the <module_name>.[v|vhd]

file. This is the user-named module that was generated by the tool to be used in both synthesis and simulation

flows. The second is a template file, <module_name>_tmpl.[v|vhd]. This file contains a sample instantiation of the

module. This file is provided for the user to copy/paste the instance and is not intended to be used in the synthesis

or simulation flows directly.

For the PLL, IPexpress sets attributes in the HDL module that are specific to the data rate selected. Although these

attributes can be easily changed, they should only be modified by re-running the GUI so that the performance of

the PLL is maintained. After the map stage in the design flow, FREQUENCY preferences will be included in the

preference file to automatically constrain the clocks produced from the PLL.

CLKI

Clock at

Clock Tree

without PLL

CLKOP/CLKOS

at Clock Tree

with PLL

Clock Injection Delay

PLL

CLKI

CLKFB

CLKOP

Clock Tree

CLKI

CLKOP

CLKOS with 90°

Phase Shift

PLL

CLKI

CLKFB

CLKOP

CLKOS

9-15

LatticeXP2 sysCLOCK PLL

Lattice Semiconductor Design and Usage Guide

Use of the Pre-Map Preference Editor

Clock preferences can be set in the Pre-Map Preference Editor. Figure 9-12 shows an example screen shot. The

Pre-Map Preference Editor is a part of the ispLEVER Design Planner.

Figure 9-12. Pre-Map Preference Editor Example

Clock Dividers (CLKDIV)

The clock divider divides the high-speed clock by 1, 2, 4 or 8. All the outputs have matched input to output delay.

CLKDIV can take as its input the edge clocks and the CLKOP of the PLL. The divided outputs drive the primary

clock and are also available for general routing or secondary clocks. The clock dividers are used for providing the

low speed FPGA clocks for shift registers (x2, x4, x8) and DDR/SPI4 I/O logic interfaces.

CLKDIV Primitive Definition

Users can instantiate CLKDIV in the source code as defined in this section. Figure 9-13 and Tables 9-8 and 9-9

describe the CLKDIVB definitions.

Figure 9-13. CLKDIV Primitive Symbol

CLKDIVB

CDIV1

CDIV2

CDIV4

CDIV8

CLKI

RST

RELEASE

9-16

LatticeXP2 sysCLOCK PLL

Lattice Semiconductor Design and Usage Guide

Table 9-8. CLKDIVB Port Definition

Table 9-9. CLKDIVB Attribute Definition

CLKDIV Declaration in VHDL Source Code

COMPONENT CLKDIVB

-- synthesis translate_off

GENERIC (

GSR : in String);

-- synthesis translate_on

PORT (

CLKI,RST, RELEASE:IN std_logic;

CDIV1, CDIV2, CDIV4, CDIV8:OUT std_logic);

END COMPONENT;

attribute GSR : string;

attribute GSR of CLKDIVinst0 : label is “DISABLED”;

begin

CLKDIVinst0: CLKDIVB

-- synthesis translate_off

GENERIC MAP(

GSR => “disabled”

);

-- synthesis translate_on

PORT MAP(

CLKI => CLKIsig,

RST => RSTsig,

RELEASE => RELEASEsig,

CDIV1 => CDIV1sig,

CDIV2 => CDIV2sig,

CDIV4 => CDIV4sig,

CDIV8 => CDIV8sig

);

Name Description

CLKI Clock Input

RST Reset Input, asynchronously forces all outputs low.

RELEASE Releases outputs synchronously to input clock.

CDIV1 Divided BY 1 Output

CDIV2 Divided BY 2 Output

CDIV4 Divided BY 4 Output

CDIV8 Divided BY 8 Output

Name Description Value Default

GSR GSR Enable ENABLED/DISABLED DISABLED

9-17

LatticeXP2 sysCLOCK PLL

Lattice Semiconductor Design and Usage Guide

CLKDIV Usage with Verilog - Example

module clkdiv_top(RST,CLKI,RELEASE,CDIV1,CDIV2,CDIV4,CDIV8);

input CLKI,RST,RELEASE;

output CDIV1,CDIV2,CDIV4,CDIV8;

CLKDIVB CLKDIBinst0 (.RST(RST),.CLKI(CLKI),.RELEASE(RELEASE),

.CDIV1(CDIV1),.CDIV2(CDIV2),.CDIV4(CDIV4),.CDIV8(CDIV8));

defparam CLKDIBint0.GXR = “DISABLED”;

endmodule

CLKDIV Example Circuits

The clock divider (CLKDIV) can divide a clock by 2 or 4 and drives a primary clock network. Clock dividers are use-

ful for providing the low speed FPGA clocks for I/O shift registers (x2, x4) and DDR (x2, x4) I/O logic interfaces.

Divide by 8 is provided for slow speed/low power operation.

To guarantee a synchronous transfer in the I/O logic the CLKDIV input clock must come from an edge clock and the

output drive from a primary clock. In this case, they are phase matched.

It is especially useful to synchronously reset the I/O logic when Mux/DeMux gearing is used in order to synchronize

the entire data bus as shown in Figure 9-14. Using the low skew characteristics of the edge clock routing a reset

can be provided to all bits of the data bus to synchronize the Mux/DeMux gearing.

The second circuit shows that a DLL can replace CLKDIV for x2 and x4 applications.

Figure 9-14. CLKDIV Application Example

CLKDIV

ECLK

Data

DQ GEARING

(2x)

RST

Primary

Clock

816

9-18

LatticeXP2 sysCLOCK PLL

Lattice Semiconductor Design and Usage Guide

Reset Behavior

Figure 9-15 illustrates the asynchronous RST behavior.

Figure 9-15. CLKDIV Reset Behavior

Release Behavior

The port, “Release” is used to synchronize the all outputs after RST is de-asserted. Figure 9-16 Illustrates the

release behavior.

Figure 9-16. CLKDIV Release Behavior

CLKI

RST

CDIV1

CDIV2

CDIV4

CDIV8

RST asserted

asynchronously.

All clock outputs are

forced low. De-asserted RST is

registered.

After de-asserted RST is

registered all outputs start

toggling.

CLKI

RST

RELEASE

CDIV1

CDIV2

CDIV4

CDIV8

De-asserted RST

registered Clock start counting Release synchronizes

outputs

9-19

LatticeXP2 sysCLOCK PLL

Lattice Semiconductor Design and Usage Guide

CLKDIV Inputs-to-Outputs Delay Matching

Figure 9-17. CLKDIV Inputs-to-Outputs Delay Matching

DCS (Dynamic Clock Select)

DCS is a global clock buffer incorporating a smart multiplexer function that takes two independent input clock

sources and avoids glitches or runt pulses on the output clock, regardless of where the enable signal is toggled.

There are two DCSs for each quadrant.

The outputs of the DCS then reach primary clock distribution via the feedlines. Figure 9-18 shows the block dia-

gram of the DCS.

Figure 9-18. DCS Primitive Symbol

DCS Primitive Definition

Table 9-10 defines the I/O ports of the DCS block. There are eight modes to select from. Table 9-11 describes how

each mode is configured.

Table 9-10. DCS I/O Definition

I/O Name Description

Input

SEL Input Clock Select

CLK0 Clock input 0

CLK1 Clock Input 1

Output DCSOUT Clock Output

CLKI

CDIV1

CDIV2

CDIV4

CDIV8

DCS

DCSOUT

CLK0

SEL

CLK1

9-20

LatticeXP2 sysCLOCK PLL

Lattice Semiconductor Design and Usage Guide

Table 9-11 . DCS Modes of Operation

DCS Timing Diagrams

Each mode performs a unique operation. The clock output timing is determined by input clocks and the edge of the

SEL signal. Figure 9-19 describes the timing of each mode.

Figure 9-19. Timing Diagrams by DCS MODE

Attribute Name Description Output ValueSEL=0 SEL=1

DCS MODE

Rising edge triggered, latched state is high CLK0 CLK1 POS

Falling edge triggered, latched state is low CLK0 CLK1 NEG

Sel is active high, Disabled output is low 0 CLK1 HIGH_LOW

Sel is active high, Disabled output is high 1 CLK1 HIGH_HIGH

Sel is active low, Disabled output is low CLK0 0 LOW_LOW

Sel is active low, Disabled output is high CLK0 1 LOW_HIGH

Buffer for CLK0 CLK0 CLK0 CLK0

Buffer for CLK1 CLK1 CLK1 CLK1

CLK0

CLK1

SEL

DCSOUT

CLK0

CLK1

SEL

DCSOUT

SEL Falling edge:

- Wait for CLK1 falling edge,

latch output & remain low

- Switch output at CLK0 falling edge

SEL Rising edge:

- Wait for CLK0 falling edge,

latch output & remain low

- Switch output at CLK1 falling edge

SEL Falling edge:

- Wait for CLK1 rising edge,

latch output & remain high

- Switch output at CLK0 rising edge

SEL Rising edge:

- Wait for CLK0 rising edge,

latch output & remain high

- Switch output at CLK1 rising edge

DCS MODE = NEG

DCS MODE = POS

9-21

LatticeXP2 sysCLOCK PLL

Lattice Semiconductor Design and Usage Guide

Figure 9-20. Timing Diagrams by DCS MODE (Cont.)

DCS Usage with VHDL - Example

COMPONENT DCS

-- synthesis translate_off

GENERIC (

DCSMODE : string := “POS”

;

-- synthesis translate_on

PORT (

END COMPONENT;

attribute DCSMODE : string;

attribute DCSMODE of DCSinst0 : label is “POS”;

begin

DCSInst0: DCS

-- synthesis translate_off

GENERIC MAP (

CLK1

SEL

DCSOUT

- Switch low @CLK1 falling edge.

- If SEL is low, output stays low at on

CLK1 rising edge. SEL must not

change during setup prior to rising clock.

DCS MODE = HIGH_LOW

CLK0

SEL

DCSOUT

- Switch low @CLK0 falling edge.

- If SEL is high, output stays low at

on CLK0 rising edge.

DCS MODE = LOW_LOW

CLK1

SEL

DCSOUT

- Switch high @CLK1 rising edge.

- If SEL is low, output stays low high

on CLK1 falling edge.

DCS MODE = HIGH_HIGH

CLK0

SEL

DCSOUT

- Switch high @ CLK0 rising edge.

- If SEL is high, output stays high on

CLK0 falling edge.

DCS MODE = LOW_HIGH

9-22

LatticeXP2 sysCLOCK PLL

Lattice Semiconductor Design and Usage Guide

DCSMODE => “POS”

)

-- synthesis translate_on

PORT MAP (

SEL => clksel,

CLK0 => dcsclk0,

CLK1 => sysclk1,

DCSOUT => dcsclk

);

DCS Usage with Verilog - Example

module dcs(clk0,clk1,sel,dcsout);

input clk0, clk1, sel;

output dcsout;

DCS DCSInst0 (.SEL(sel),.CLK0(clk0),.CLK1(clk1),.DCSOUT(dcsout));

defparam DCSInst0.DCSMODE = “CLK0”;

endmodule

Oscillator (OSCE)

There is a dedicated oscillator in the LatticeXP2 device whose output is made available for users.

The oscillator frequency output is routed through a divider which is used as an input clock to the clock tree. The

available outputs of the divider are shown in Table 9-13. The oscillator frequency output can be further divided by

internal logic (user logic) for lower frequencies, if desired. The oscillator is powered down when not in use.

The output of this oscillator is not a precision clock. It is intended as an extra clock that does not require accurate

clocking.

Primitive Name: OSCE

Table 9-12. OSCE Port Definition

Table 9-13. OSCE Attribute Definition

OSC Primitive Symbol (OSCE)

Figure 9-21. OSC Symbol

I/O Name Description

Output OSC Oscillator Clock Output

User Attribute Attribute Name Value (MHz) Default Value

Nominal Frequency NOM_FREQ 2.5, 3.14, 4.3, 5.4, 6.9, 8.1, 9.2, 10, 13, 15,

20, 26, 32, 40, 54, 80, 163 2.5

OSCE

OSC

9-23

LatticeXP2 sysCLOCK PLL

Lattice Semiconductor Design and Usage Guide

OSC Usage with VHDL - Example

COMPONENT OSCE

PORT (OSC:OUT std_logic);

END COMPONENT;

begin

OSCInst0: OSCE

PORT MAP ( OSC=> osc_int);

OSC Usage with Verilog - Example

module OSC_TOP(OSC_CLK);

output OSC_CLK;

OSCE OSCinst0 (.OSC(OSC_CLK));

endmodule

Setting Clock Preferences

Designers can use clock preferences to implement clocks to the desired performance. Preferences can be set in

the Pre-Map Preference Editor (Design Planner) or in preference files. Frequently used preferences are described

in Appendix C.

Power Supplies

Each PLL has its own power supply pin, VCCPLL. Since VCCAUX and VCCPLL are normally the same 3.3V, it is

recommended that they are driven from the same power supply on the circuit board, thus minimizing leakage. In

addition, each of these supplies should be independently isolated from the main 3.3V supply on the board using

proper board filtering techniques to minimize the noise coupling between them.

Technical Support Assistance

Hotline: 1-800-LATTICE (North America)

+1-503-268-8001 (Outside North America)

e-mail: techsupport@latticesemi.com

Internet: www.latticesemi.com

Revision History

Date Version Change Summary

February 2007 01.0 Initial release.

February 2010 01.1 Reconciled LOCK description among MachXO, LatticeXP2,

LatticeECP2/M and LatticeECP3.

9-24

LatticeXP2 sysCLOCK PLL

Lattice Semiconductor Design and Usage Guide

Appendix A. Primary Clock Sources and Distribution

Figure 9-22. LatticeXP2 Primary Clock Sources and Distribution

Figure 9-23. LatticeXP2 Primary Clock Muxes

Primary Clocks in Center Switch Box

GPLL* : Available in XP2-17 and larger devices

General

Routing

QUADRANT TL

General

Routing

QUADRANT TR

DCS

36:136:1 36:1 36:1 36:1 36:1 32:132:1 32:1 32:1

DCS DCS

36:1 36:136:136:136:136:132:1 32:132:132:1

DCS

General

Routing

QUADRANT BL

General

Routing

QUADRANT BR

2 3

CLK0 CLK0CLK1 CLK1CLK2 CLK2CLK3 CLK3CLK4 CLK4CLK5 CLK5CLK6 CLK6CLK7

CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7

CLK7

CLK0CLK1CLK2CLK3CLK4CLK5CLK6CLK7

DCS

36:1

36:1 36:1 36:1 36:1 36:1 32:132:1 32:1 32:1

DCS DCS

36:1 36:136:136:1

36:136:132:1 32:1

32:1

DCS

PCLKT7

PCLKT6

PCLKT2

PCLKT3

PCLKT4

PCLKT5

PCLKT0

CLKDIV

CLKDIV1

CLKDIV2

CLKDIV4

CLKDIV8

GPLL*

CLKOP

CLKOS

CLKOK

CLKOK2

GPLL

CLKOP

CLKOS

CLKOK

CLKOK2

CLKDIV

CLKDIV1

CLKDIV2

CLKDIV4

CLKDIV8

GPLL*

CLKOP

CLKOS

CLKOK

CLKOK2

GPLL

CLKOP

CLKOS

CLKOK

CLKOK2

PCLKT1

CLK6 - 7

16 PLL outputs

8 CLKDIV outputs

4 PCLK pins

2 from General

Routing

CLK0 - 5

16 PLL outputs

8 CLKDIV outputs

4 PCLK pins

General Routing

VCC

DCS

30:1

29:1

9-25

LatticeXP2 sysCLOCK PLL

Lattice Semiconductor Design and Usage Guide

Appendix B. PLL, CLKDIV and ECLK Locations and Connectivity

Figure 9-24 shows the locations, site names and connectivity of the PLLs, CLKDIVs and ECLKs

Figure 9-24. PLL, CLKDIV and ECLK Locations and Connectivity

ECLK1

ECLK2

ECLK1

ECLK2

ECLK1

ECLK2

PCLKT7

ULGPLL_IN

Internal Node

LLGPLL_IN

CLKOP

CLKOS

ULGPLL

CLKOP

CLKOS

LLGPLL

Internal Node

PCLKT6

PCLKT2

URGPLL_IN

Internal Node

LRGPLL_IN

Internal Node

PCLKT3

Internal Node

RCLKDIV

LCLKDIV

Internal Node

PCLKT4

PCLKT5

PCLKT1

PCLKT0

CLKOP

CLKOS LRGPLL

CLKOP

CLKOS URGPLL

9-26

LatticeXP2 sysCLOCK PLL

Lattice Semiconductor Design and Usage Guide

Appendix C. Clock Preferences

A few key clock preferences are introduced below. Refer to the ‘Help’ file for other preferences and detailed infor-

mation.

ASIC

The following preference command assigns a phase of 90 degrees to the CIMDLLA CLKOP.

ASIC “my_dll” TYPE “CIMDLLA” CLKOP_PHASE=90;

FREQUENCY

The following physical preference command assigns a frequency of 100 MHz to a net named clk1:

FREQUENCY NET “clk1” 100 MHz;

The following preference specifies a hold margin value for each clock domain:

FREQUENCY NET “RX_CLKA_CMOS_c” 100.000 MHz HOLD_MARGIN 1 ns;

MAXSKEW

The following command assigns a maximum skew of 5 nanoseconds to a net named NetB:

MAXSKEW NET “NetB” 5 NS;

MULTICYCLE

The following command will relax the period to 50 nanoseconds for the path starting at COMPA to COMPB (NET1):

MULTICYCLE “PATH1” START COMP “COMPA” END COMP “COMPB” NET “NET1” 50 NS ;

PERIOD

The following command assigns a clock period of 30 nanoseconds to the port named Clk1:

PERIOD PORT “Clk1” 30 NS;

PROHIBIT

This command prohibits the use of a primary clock to route a clock net named bf_clk:

PROHIBIT PRIMARY NET “bf_clk”;

USE PRIMARY

Use a primary clock resource to route the specified net:

USE PRIMARY NET clk_fast;

USE PRIMARY DCS NET “bf_clk”;

USE PRIMARY PURE NET “bf_clk” QUADRANT_TL;

USE SECONDARY

Use a secondary clock resource to route the specified net:

USE SECONDARY NET “clk_lessfast” QUADRANT_TL;

9-27

LatticeXP2 sysCLOCK PLL

Lattice Semiconductor Design and Usage Guide

USE EDGE

Use a edge clock resource to route the specified net:

USE EDGE NET “clk_fast”;

CLOCK_TO_OUT

Specifies a maximum allowable output delay relative to a clock.

Here are two preferences using both the CLKPORT and CLKNET keywords showing the corresponding scope of

TRACE reporting.

The CLKNET will stop tracing the path before the PLL, so you will not get PLL compensation timing numbers.

CLOCK_TO_OUT PORT “RxAddr_0” 6.000000 ns CLKNET “pll_rxclk” ;

The above preference will yield the following clock path:

Clock path pll_inst/pll_utp_0_0 to PFU_33:

Name Fanout Delay (ns) Site Resource

ROUTE 49 2.892 ULPPLL.MCLK to R3C14.CLK0 pll_rxclk

--------

2.892 (0.0% logic, 100.0% route), 0 logic levels.

If CLKPORT is used, the trace is complete back to the clock port resource and provides PLL compensation timing

numbers.

CLOCK_TO_OUT PORT “RxAddr_0” 6.000000 ns CLKPORT “RxClk” ;

The above preference will yield the following clock path:

Clock path RxClk to PFU_33:

Name Fanout Delay (ns) Site Resource

IN_DEL --- 1.431 D5.PAD to D5.INCK RxClk

ROUTE 1 0.843 D5.INCK to ULPPLL.CLKIN RxClk_c

MCLK_DEL --- 3.605 ULPPLL.CLKIN to ULPPLL.MCLK pll_inst/pll_utp_0_0

ROUTE 49 2.892 ULPPLL.MCLK to R3C14.CLK0 pll_rxclk

--------

8.771 (57.4% logic, 42.6% route), 2 logic levels.

INPUT_SETUP

Specifies an setup time requirement for input ports relative to a clock net.

INPUT_SETUP PORT “datain” 2.000000 ns HOLD 1.000000 ns CLKPORT “clk”

PLL_PHASE_BACK ;

PLL_PHASE_BACK

This preference is used with INPUT_SETUP when a user needs a trace calculation based on the previous clock

edge.

This preference is useful when setting the PLL output phase adjustment. Since there is no negative phase adjust-

ment provided, the PLL_PHASE_BACK preference works as if negative phase adjustment is available.

9-28

LatticeXP2 sysCLOCK PLL

Lattice Semiconductor Design and Usage Guide

For example:

If phase adjustment of -90° of CLKOS is desired, a user can set the Phase to 270° and set the INPUT_SETUP

preference with PLL_PHASE_BACK.

PLL_PHASE_BACK Usage in Pre-Map Preference Editor

The Pre-Map Preference Editor can be used to set the PLL_PHASE_BACK attribute.

1. Open the Design Planner (Pre-Map).

2. In the Design Planner control window, select View -> Spreadsheet View.

3. In the Spreadsheet View window, select Input_setup/Clock_to_out...

The INPUT_SETUP/CLOCK_TO_OUT Preference window is shown in Figure 9-25.

Figure 9-25. INPUT_SETUP/CLOCK_TO_OUT Preference W indow

www.latticesemi.com 10-1 tn1137_01.9

July 201 1 Technical Note TN1137

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Introduction

This technical note discusses memory usage for the LatticeXP2™ device family. It is intended to be used by design

engineers as a guide for integrating the User TAG, EBR- (Embedded Block RAM) and PFU-based memories in this

device family using the ispLEVER® design tool.

The architecture of these devices provides resources for FPGA on-chip memory applications. The sysMEM™ EBR

complements the distributed PFU-based memory. Single-Port RAM, Dual-Port RAM, Pseudo Dual-Port RAM, FIFO

and ROM memories can be constructed using the EBR. LUTs and PFU can implement Distributed Single-Port

RAM, Dual-Port RAM and ROM. User TAG memories in varying sizes, depending on the specific chip, are also on

the device.

The capabilities of the User TAG memory, EBR RAM and PFU RAM are referred to as primitives and are described

later in this document. Designers can utilize the memory primitives in two ways via the IPexpress™ tool in the isp-

LEVER software. The IPexpress GUI allows users to specify the memory type and size required. IPexpress takes

this specification and constructs a netlist to implement the desired memory by using one or more of the memory

primitives.

The remainder of this document discusses the use of IPexpress, memory modules and memory primitives.

Memories in LatticeXP2 Devices

There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional Unit

without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM and register functions.

The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks are opti-

mized for flexibility allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged

in a two-dimensional array. Only one type of block is used per row.

The LatticeXP2 family of devices contains up to two rows of sysMEM EBR blocks. sysMEM EBRs are large, dedi-

cated 18K fast memory blocks. Each sysMEM block can be configured in a variety of depths and widths of RAM or

ROM. Each LatticeXP2 device also contains one dedicated row of User TAG memory with up to 451 bytes of

space.

Table 10-1. LatticeXP2 LUT and Memory Densities

Parameter XP2-5 XP2-8 XP2-17 XP2-30 XP2-40

EBR Rows 11112

EBR Blocks 9 12152148

EBR Bits 165888 221184 276480 387072 884736

Distributed RAM Bits 10368 18432 34560 64512 82944

Total Memory Bits 176256 239616 311040 451584 967680

LatticeXP2 Memory Usage Guide

10-2

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Figure 10-1. Simplified Block Diagram, LatticeXP2 Device (Top Level)

Utilizing IPexpress

Designers can utilize IPexpress to easily specify a variety of memories in their designs. These modules are con-

structed using one or more memory primitives along with general purpose routing and LUTs, as required. The

available primitives are:

• Single Port RAM (RAM_DQ) – EBR-based

• Dual PORT RAM (RAM_DP_TRUE) – EBR-based

• Pseudo Dual Port RAM (RAM_DP) – EBR-based

• Read Only Memory (ROM) – EBR-Based

• First In First Out Memory (Dual Clock) (FIFO_DC) – EBR-based

• Distributed Single Port RAM (Distributed_SPRAM) – PFU-based

• Distributed Dual Port RAM (Distributed_DPRAM) – PFU-based

• Distributed ROM (Distributed_ROM) – PFU/PFF-based

• User TAG memory (SSPIA) – TAG-based

On-chip

Oscillator

Programmable

Function Units

(PFUs)

SPI Port

sysCLOCK PLLs Flexible Routing

Flash

JTAG Port

sysIO Buffers,

Pre-Engineered Source

Synchronous Support

sysMEM Block

RAM

DSP Blocks

10-3

Lattice Semiconductor LatticeXP2 Memory Usage Guide

IPexpress Flow

For generating any of these memories, create (or open) a project for the LatticeXP2 devices.

From the Project Navigator, select Tools > IPexpress or click on the button in the toolbar when LatticeXP2 devices

are targeted in the project. This opens the IPexpress main window as shown in Figure 10-2.

Figure 10-2. IPexpress - Main Window

The left pane of this window includes the Module Tree. The EBR-based Memory Modules are under the

EBR_Components and the PFU-based Distributed Memory Modules are under Storage_Components, as shown

in Figure 10-2.

As an example, let us consider generating an EBR-based Pseudo Dual Port RAM of size 512x16. Select RAM_DP

under EBR_Components. The right pane changes as shown in Figure 10-3.

10-4

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Figure 10-3. Example Generating Pseudo Dual Port RAM (RAM_DP) Using IPexpress

In the right pane, options like the Device Family, Macro Type, Category, and Module_Name are device and

selected module dependent. These cannot be changed in IPexpress.

Users can change the directory where the generated module files will be placed by clicking the Browse button in

the Project Path.

The Module Name text box allows users to specify an entity name for the module they are about to generate.

Users must provide this entity name.

Design entry, Verilog or VHDL, by default, is the same as the project type. If the project is a VHDL project, the

selected design entry option will be “Schematic/ VHDL”, and “Schematic/ Verilog-HDL” if the project type is Verilog-

HDL.

The Device pull-down menu allows users to select different devices within the same family, LatticeXP2 in this

example. By clicking the Customize button, another window opens where users can customize the RAM

(Figure 10-4).

10-5

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Figure 10-4. Example Generating Pseudo Dual Port RAM (RAM_DP) Module Customization

The left side of this window shows the block diagram of the module. The right side includes the Configuration tab

where users can choose options to customize the RAM_DP (e.g. specify the address port sizes and data widths).

Users can specify the address depth and data width for the Read Port and the Wr ite Po rt in the text boxes pro-

vided. In this example, we are generating a Pseudo Dual Port RAM of size 512 x 16. Users can also create RAMs

of different port widths for Pseudo Dual Port and True Dual Port RAMs.

The Input Data and the Address Control are always registered, as the hardware only supports the clocked write

operation for the EBR based RAMs. The check box Enable Output Registers inserts the output registers in the

Read Data Port. Output registers are optional for EBR-based RAMs.

Users have the option to set the Reset Mode as Asynchronous Reset or Synchronous Reset. Enable GSR can be

checked to enable the Global Set Reset.

Users can also pre-initialize their memory with the contents specified in the Memory File. It is optional to provide

this file in the RAM; however for ROM, the Memory File is required. These files can be of Binary, Hex or Addresses

Hex format. The details of these formats are discussed in the Initialization File section of this document.

At this point, users can click the Generate button to generate the module they have customized. A VHDL or Verilog

netlist is then generated and placed in the specified location. Users can incorporate this netlist in their designs.

Another important button is the Load Parameters button. IPexpress stores the parameters specified in a

<module_name>.lpc file. This file is generated along with the module. Users can click on the Load Parameters but-

ton to load the parameters of a previously generated module to re-visit or make changes to them.

Once the module is generated, users can either instantiate the *.lpc or the Verilog-HDL/ VHDL file in top-level mod-

ule of their design.

10-6

Lattice Semiconductor LatticeXP2 Memory Usage Guide

The various memory modules, both EBR and distributed, are discussed in detail in this document.

Memory Modules

ECC is supported in most memories. If you choose to use ECC, you will have a 2-bit error signal.

• When Error[1:0]=00, there is no error.

• When Error[0]=1, it indicates that there was a 1 bit error which was fixed.

• When Error[1]=1, it indicates that there was a 2-bit error which cannot be corrected.

Single Port RAM (RAM_DQ) – EBR Based

The EBR blocks in LatticeXP2 devices can be configured as Single Port RAM or RAM_DQ. IPexpress allows users

to generate the Verilog-HDL or VHDL along EDIF netlist for the memory size as per design requirements.

IPexpress generates the memory module as shown in Figure 10-5.

Figure 10-5. Single Port Memory Module Generated by IPexpress

Since the device has a number of EBR blocks, the generated module makes use of these EBR blocks, or primi-

tives, and cascades them to create the memory sizes specified by the user in the IPexpress GUI. For memory sizes

smaller than an EBR block, the module will be created in one EBR block. For memory sizes larger than one EBR

block, multiple EBR blocks can be cascaded in depth or width (as required to create these sizes).

In Single Port RAM mode, the input data and address for the ports are registered at the input of the memory array.

The output data of the memory is optionally registered at the output.

The various ports and their definitions for the Single Port Memory are listed in Table 10-2. The table lists the corre-

sponding ports for the module generated by IPexpress and for the EBR RAM_DQ primitive.

RAM_DQ

EBR-based Single Port

Memory

Clock

ClockEn

Reset

Address

Data

10-7

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Table 10-2. EBR-based Single Port Memory Port Definitions

Reset (or RST) resets only the input and output registers of the RAM. It does not reset the contents of the memory.

Chip Select (CS) is a useful port in the EBR primitive when multiple cascaded EBR blocks are required by the

memory. The CS signal forms the MSB for the address when multiple EBR blocks are cascaded. CS is a 3-bit bus,

so it can cascade eight memories easily. If the memory size specified by the user requires more than eight EBR

blocks, the ispLEVER software automatically generates the additional address decoding logic, which is imple-

mented in the PFU (external to the EBR blocks).

Each EBR block consists of 18,432 bits of RAM. The values for x (address) and y (data) for each EBR block for the

devices are listed in Table 10-3.

Table 10-3. Single Port Memory Sizes for 16K Memories for LatticeXP2

Table 10-4 shows the various attributes available for the Single Port Memory (RAM_DQ). Some of these attributes

are user-selectable through the IPexpress GUI. For detailed attribute definitions, refer to Appendix A.

Port Name in

Generated Module Port Name in the

EBR Block Primitive Description Active State

Clock CLK Clock Rising Clock Edge

ClockEn CE Clock Enable Active High

Address AD[x:0] Address Bus —

Data DI[y:0] Data In —

Q DO[y:0] Data Out —

WE WE Write Enable Active High

Reset RST Reset Active High

— CS[2:0] Chip Select —

Single Port

Memory Size Input Data Output Data Address [MSB:LSB]

16K x 1 DI DO AD[13:0]

8K x 2 DI[1:0] DO[1:0] AD[12:0]

4K x 4 DI[3:0] DO[3:0] AD[11:0]

2K x 9 DI[8:0] DO[8:0] AD[10:0]

1K x 18 DI[17:0] DO[17:0] AD[9:0]

512 x 36 DI[35:0] DO[35:0] AD[8:0]

10-8

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Table 10-4. Single Port RAM Attributes for LatticeXP2

The Single Port RAM (RAM_DQ) can be configured as NORMAL or WRITE THROUGH modes. Each of these

modes affects the data coming out of port Q of the memory during the write operation followed by the read opera-

tion at the same memory location.

Additionally, users can select to enable the output registers for RAM_DQ. Figures 10-6-10-9 show the internal tim-

ing waveforms for the Single Port RAM (RAM_DQ) with these options.

It is important that no setup and hold time violations occur on the address registers (Address). Failing to to meet

these requirements can result in corruption of memory contents. This applies to both read and write operations.

A Post Place and Route timing report in Lattice Diamond® or ispLEVER design software can be run to verify that no

such timing errors occur. Refer to the timing preferences in the Online Help documents.

Attribute Description Values Defau lt Value Use r Selectable

Through IPexp ress

Address depth Address Depth Read Port 16K, 8K, 4K, 2K, 1K, 512 YES

Data Width Data Word Width Read Port 1, 2, 4, 9, 18, 36 1 YES

Enable Output Registers Register Mode (Pipelining)

for Write Port NOREG, OUTREG NOREG YES

Enable GSR Enables Global Set Reset ENABLE, DISABLE ENABLE YES

Reset Mode Selects the Reset type ASYNC, SYNC ASYNC YES

Memory File Format BINARY, HEX, ADDRESSED

HEX YES

Write Mode Read / Write Mode for Write

Port

NORMAL, WRITE-

THROUGH NORMAL YES

Chip Select Decode Chip Select Decode for

Read Port

0b000, 0b001, 0b010,

0b011, 0b100, 0b101,

0b110, 0b111

0b000 NO

Init Value Initialization value

0x000000000000000000000

00000000000000000000000

0000000000000......0xFFFF

FFFFFFFFFFFFFFFFFFFFF

FFFFFFFFFFFFF

0x000000000

00000000000

00000

10-9

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Figure 10-6. Single Port RAM Timing Waveform - NORMAL Mode, without Output Registers

Figure 10-7. Single Port RAM Timing Waveform - NORMAL Mode, with Output Registers

Add_0 Add_1 Add_0 Add_1 Add_2

Data_0 Data_1

Invalid Data Data_0

Clock

WrEn

Address

Data

ClockEn

SUWREN_EBR

HWREN_EBR

SUADDR_EBR

HADDR_EBR

SUDATA_EBR

HDATA_EBR

SUCE_EBR

HCE_EBR

CO_EBR

Data_1 Data_2

Add_0 Add_1 Add_0 Add_1 Add_2

Data_0 Data_1

Invalid Data Data_0 Data_1

Clock

Reset

WrEn

Address

Data

ClockEn

SUWREN_EBR

HWREN_EBR

SUADDR_EBR

HADDR_EBR

SUDATA_EBR

HDATA_EBR

SUCE_EBR

HCE_EBR

COO_EBR

10-10

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Figure 10-8. Single Port RAM Timing Waveform - WRITE THROUGH Mode, without Output Registers

Figure 10-9. Single Port RAM Timing Waveform - WRITE THROUGH Mode, with Output Registers

Add_0 Add_1 Add_0

Data_0 Data_1 Data_2 Data_3 Data_4

Invalid Data Data_1

Clock

WrEn

Address

Data

ClockEn

SUWREN_EBR

HWREN_EBR

SUADDR_EBR

HADDR_EBR

SUDATA_EBR

HDATA_EBR

SUCE_EBR

HCE_EBR

CO_EBR

Data_2Data_0 Data_3 Data_4

Add_0 Add_1 Add_0

Data_0 Data_1 Data_2 Data_3 Data_4

Invalid Data Data_1

Clock

WrEn

Address

Data

ClockEn

SUWREN_EBR

HWREN_EBR

SUADDR_EBR

HADDR_EBR

SUDATA_EBR

HDATA_EBR

SUCE_EBR

HCE_EBR

COO_EBR

Data_2Data_0 Data_3

Reset

10-11

Lattice Semiconductor LatticeXP2 Memory Usage Guide

True Dual Port RAM (RAM_DP_TRUE) – EBR Based

The EBR blocks in the LatticeXP2 devices can be configured as True-Dual Port RAM or RAM_DP_TRUE. IPex-

press allows users to generate the Verilog-HDL, VHDL or EDIF netlists for the memory size as per design require-

ments.

IPexpress generates the memory module as shown in Figure 10-10.

Figure 10-10. True Dual Port Memory Module Generated by IPexpress

The generated module makes use of these EBR blocks or primitives. For memory sizes smaller than an EBR block,

the module will be created in one EBR block. When the specified memory is larger than one EBR block, multiple

EBR blocks can be cascaded in depth or width (as required to create these sizes).

In True Dual Port RAM mode, the input data and address for the ports are registered at the input of the memory

array. The output data of the memory is optionally registered at the output.

The various ports and their definitions for Single Port Memory are listed in Table 10-5. The table lists the corre-

sponding ports for the module generated by IPexpress and for the EBR RAM_DP_TRUE primitive.

Table 10-5. EBR-based True Dual Port Memory Port De finitions

Reset (or RST) resets only the input and output registers of the RAM. It does not reset the contents of the memory.

Chip Select (CS) is a useful port in the EBR primitive when multiple cascaded EBR blocks are required by the

memory. The CS signal forms the MSB for the address when multiple EBR blocks are cascaded. Since CS is a 3-

bit bus, it can cascade eight memories easily. However, if the memory size specified by the user requires more than

eight EBR blocks, the ispLEVER software automatically generates the additional address decoding logic, which is

implemented in the PFU external to the EBR blocks.

Port Name in

Generated Module Port Name in the

EBR Block Primitive Description Active State

ClockA, ClockB CLKA, CLKB Clock for PortA and PortB Rising Clock Edge

ClockEnA, ClockEnB CEA, CEB Clock Enables for Port CLKA and CLKB Active High

AddressA, AddressB ADA[x1:0], ADB[x2:0] Address Bus Port A and Port B —

DataA, DataB DIA[y1:0], DIB[y2:0] Input Data Port A and Port B —

QA, QB DOA[y1:0], DOB[y2:0] Output Data Port A and Port B —

WrA, WrB WEA, WEB Write Enable Port A and Port B Active High

ResetA, ResetB RSTA, RSTB Reset for Port A and Port B Active High

— CSA[2:0], CSB[2:0] Chip Selects for each port —

RAM_DP_TRUE

EBR-based T rue

Dual Port Memory

ClockA

ClockEnA

ResetA

WrA

AddressA

DataInA

ClockB

ClockEnB

ResetB

WrB

AddressB

DataInB

10-12

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Each EBR block consists of 18,432 bits of RAM. The values for x’s (for address) and y’s (data) for each EBR block

for the devices are listed in Table 10-6.

Table 10-6. True Dual Port Memory Sizes for 16K Memory for LatticeXP2

Table 10-7 shows the various attributes available for the Single Port Memory (RAM_DQ). Some of these attributes

are user-selectable through the IPexpress GUI. For detailed attribute definitions, refer to the Appendix A.

Table 10-7. True Dual Port RAM Attributes for LatticeXP2

Dual Port

Memory Size Input Data

Port A Input Data

Port B Output Data

Port A Output Data

Port B Address Port A

[MSB:LSB] Address Port B

[MSB:LSB]

16K x 1 DIA DIB DOA DOB ADA[13:0] ADB[13:0]

8K x 2 DIA[1:0] DIB[1:0] DOA[1:0] DOB[1:0] ADA[12:0] ADB[12:0]

4K x 4 DIA[3:0] DIB[3:0] DOA[3:0] DOB[3:0] ADA[11:0] ADB[11:0]

2K x 9 DIA[8:0] DIB[8:0] DOA[8:0] DOB[8:0] ADA[10:0] ADB[10:0]

1K x 18 DIA[17:0] DIB[17:0] DOA[17:0] DOB[17:0] ADA[9:0] ADB[9:0]

Attribute Description Values Default

Value User Selectable

Through IPexpress

Port A Address depth Address Depth Port A 16K, 8K, 4K, 2K, 1K YES

Port A Data Width Data Word Width Port A 1, 2, 4, 9, 18 1 YES

Port B Address depth Address Depth Port B 16K, 8K, 4K, 2K, 1K YES

Port B Data Width Data Word Width Port B 1, 2, 4, 9, 18 1 YES

Port A Enable Output Registers Register Mode

(Pipelining) for Port A NOREG, OUTREG NOREG YES

Port B Enable Output Registers Register Mode

(Pipelining) for Port B NOREG, OUTREG NOREG YES

Enable GSR Enables Global Set Reset ENABLE, DISABLE ENABLE YES

Reset Mode Selects the Reset type ASYNC, SYNC ASYNC YES

Memory File Format BINARY, HEX,

ADDRESSED HEX YES

Port A Write Mode Read / Write Mode for

Port A

NORMAL, WRITE-

THROUGH NORMAL YES

Port B Write Mode Read / Write Mode for

Port B

NORMAL, WRITE-

THROUGH NORMAL YES

Chip Select Decode for Port A Chip Select Decode for

Port A

0b000, 0b001, 0b010,

0b011, 0b100, 0b101,

0b110, 0b111

0b000 NO

Chip Select Decode for Port B Chip Select Decode for

Port B

0b000, 0b001, 0b010,

0b011, 0b100, 0b101,

0b110, 0b111

0b000 NO

Init Value Initialization value

0x00000000000000000000

0000000000000000000000

0000000000000000......0xF

FFFFFFFFFFFFFFFFFFFF

FFFFFFFFFFFFFFFFFFF

0x000000000

00000000000

00000

10-13

Lattice Semiconductor LatticeXP2 Memory Usage Guide

The True Dual Port RAM (RAM_DP_TRUE) can be configured as NORMAL or WRITE THROUGH modes. Each of

these modes affects what data comes out of the port Q of the memory during the write operation followed by the

read operation at the same memory location. The detailed discussions of the WRITE modes and the constraints of

the True Dual Port can be found in Appendix A.

Additionally, users can select to enable the output registers for RAM_DP_TRUE. Figures 10-11 through 10-14

show the internal timing waveforms for the True Dual Port RAM (RAM_DP_TRUE) with these options.

It is important that no setup and hold time violations occur on the address registers (AddressA and AddressB). Fail-

ing to to meet these requirements can result in corruption of memory contents. This applies to both read and write

operations.

A Post Place and Route timing report in Lattice Diamond or ispLEVER design software can be run to verify that no

such timing errors occur. Refer to the timing preferences in the Online Help documents.

Figure 10-11. True Dual Port RAM Timing Waveform – NORMAL Mode, without Output Registers

Add_A0 Add_A1 Add_A0 Add_A1 Add_A2

Data_A0 Data_A1

Invalid Data Data_A0

ClockA

WrEnA

AddressA

DataA

ClockEnA

tSUWREN_EBR tHWREN_EBR

tSUADDR_EBR tHADDR_EBR

tSUDATA_EBR tHDATA_EBR

tSUCE_EBR tHCE_EBR

tCO_EBR

Data_A1 Data_A2

Add_B0 Add_B1 Add_B0 Add_B1 Add_B2

Data_B0 Data_B1

Invalid Data Data_B0

ClockB

WrEnB

AddressB

DataB

ClockEnB

tSUWREN_EBR tHWREN_EBR

tSUADDR_EBR tHADDR_EBR

tSUDATA_EBR tHDATA_EBR

tSUCE_EBR tHCE_EBR

tCO_EBR

Data_B1 Data_B2

10-14

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Figure 10-12. True Dual Port RAM Timing Waveform - NORMAL Mode with Output Registers

Add_A0 Add_A1 Add_A0 Add_A1 Add_A2

Data_A0 Data_A1

ClockA

WrEnA

AddressA

DataA

ClockEnA

tSUWREN_EBR tHWREN_EBR

tSUADDR_EBR tHADDR_EBR

tSUDATA_EBR tHDATA_EBR

tSUCE_EBR tHCE_EBR

Add_B0 Add_B1 Add_B0 Add_B1 Add_B2

Data_B0 Data_B1

Invalid Data Data_B0

ClockB

WrEnB

AddressB

DataB

ClockEnB

tSUWREN_EBR tHWREN_EBR

tSUADDR_EBR tHADDR_EBR

tSUDATA_EBR tHDATA_EBR

tSUCE_EBR tHCE_EBR

tCOO_EBR

Data_B1

Invalid Data Data_A0

tCOO_EBR

Data_A1

Reset

10-15

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Figure 10-13. True Dual Port RAM Timing Waveform - WRITE THROUGH Mode, without Output Registers

Add_A0 Add_A1 Add_A0

Data_A0 Data_A1 Data_A2 Data_A3 Data_A4

Invalid Data Data_A1

ClockA

WrEnA

AddressA

DataA

ClockEnA

tSUWREN_EBR tHWREN_EBR

tSUADDR_EBR tHADDR_EBR

tSUDATA_EBR tHDATA_EBR

tSUCE_EBR tHCE_EBR

tCO_EBR

Data_A2Data_A0 Data_A3 Data_A4

Add_B0 Add_B1 Add_B0

Data_B0 Data_B1 Data_B2 Data_B3 Data_B4

Invalid Data Data_B1

ClockB

WrEnB

AddressB

DataB

ClockEnB

tSUWREN_EBR tHWREN_EBR

tSUADDR_EBR tHADDR_EBR

tSUDATA_EBR tHDATA_EBR

tSUCE_EBR tHCE_EBR

tCO_EBR

Data_B2Data_B0 Data_B3 Data_B4

10-16

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Figure 10-14. True Dual Port RAM Timing Waveform - WRITE THROUGH Mode, with Output Registers

Add_0 Add_1 Add_0

Data_0 Data_1 Data_2 Data_3 Data_4

Invalid Data Data_1

ClockA

WrEnA

AddressA

DataA

ClockEnA

tSUWREN_EBR tHWREN_EBR

tSUADDR_EBR tHADDR_EBR

tSUDATA_EBR tHDATA_EBR

tSUCE_EBR tHCE_EBR

tCOO_EBR

Data_2Data_0 Data_3

Add_0 Add_1 Add_0

Data_0 Data_1 Data_2 Data_3 Data_4

Invalid Data Data_1

ClockB

WrEnB

AddressB

DataB

ClockEnB

tSUWREN_EBR tHWREN_EBR

tSUADDR_EBR tHADDR_EBR

tSUDATA_EBR tHDATA_EBR

tSUCE_EBR tHCE_EBR

tCOO_EBR

Data_2Data_0 Data_3

Reset

10-17

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Pseudo Dual Port RAM (RAM_DP) – EBR Based

The EBR blocks in LatticeXP2 devices can be configured as Pseudo-Dual Port RAM or RAM_DP. IPexpress allows

users to generate the Verilog-HDL or VHDL along with EDIF netlists for the memory size as per design require-

ments.

IPexpress generates the memory module as shown in Figure 10-15.

Figure 10-15. Pseudo Dual Port Memory Module Generated by IPexpress

The generated module makes use of these EBR blocks or primitives. For memory sizes smaller than an EBR block,

the module will be created in one EBR block. If the specified memory is larger than one EBR block, multiple EBR

blocks can be cascaded in depth or width (as required to create these sizes).

In Pseudo Dual Port RAM mode, the input data and address for the ports are registered at the input of the memory

array. The output data of the memory is optionally registered at the output.

The various ports and their definitions for the Single Port Memory are listed in Table 10-8. The table lists the corre-

sponding ports for the module generated by IPexpress and for the EBR RAM_DP primitive.

Table 10-8. EBR-based Pseudo-Dual Port Memory Port Definitions

Reset (RST) resets only the input and output registers of the RAM. It does not reset the contents of the memory.

Chip Select (CS) is a useful port when multiple cascaded EBR blocks are required by the memory. The CS signal

forms the MSB for the address when multiple EBR blocks are cascaded. Since CS is a 3-bit bus, it can cascade

eight memories easily. However, if the memory size specified by the user requires more than eight EBR blocks, the

ispLEVER software automatically generates the additional address decoding logic, which is implemented in the

PFU external to the EBR blocks.

Port Name in

Generated Module Port Name in the

EBR Block Primitive Description Active State

RdAddress ADR[x1:0] Read Address —

WrAddress ADW[x2:0] Write Address —

RdClock CLKR Read Clock Rising Clock Edge

WrClock CLKW Write Clock Rising Clock Edge

RdClockEn CER Read Clock Enable Active High

WrClockEn CEW Write Clock Enable Active High

Q DO[y1:0] Read Data —

Data DI[y2:0] Write Data —

WE WE Write Enable Active High

Reset RST Reset Active High

— CS[2:0] Chip Select —

RAM_DP

EBR based Pseudo

Dual Port Memory

WrClock

WrClockEn

Reset

WrAddress

Data

RdClock

RdClockEn

RdAddress

10-18

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Each EBR block consists of 18,432 bits of RAM. The values for x’s (for address) and y’s (data) for each EBR block

for the devices are as in Table 10-9.

Table 10-9. Pseudo-Dual Port Memory Sizes for 16K Memor y for LatticeXP2

Table 10-10 shows the various attributes available for the Pseudo-Dual Port Memory (RAM_DP). Some of these

attributes are user-selectable through the IPexpress GUI. For detailed attribute definitions, refer to Appendix A.

Table 10-10. Pseudo-Dual Port RAM Attributes for LatticeXP2

Pseudo-Dual

Port Memory

Size Input Data

Port A Input Data

Port B Output Data

Port A Output Data

Port B

Read Address

Port A

[MSB:LSB]

Write Address

Port B

[MSB:LSB]

16K x 1 DIA DIB DOA DOB RAD[13:0] WAD[13:0]

8K x 2 DIA[1:0] DIB[1:0] DOA[1:0] DOB[1:0] RAD[12:0] WAD[12:0]

4K x 4 DIA[3:0] DIB[3:0] DOA[3:0] DOB[3:0] RAD[11:0] WAD[11:0]

2K x 9 DIA[8:0] DIB[8:0] DOA[8:0] DOB[8:0] RAD[10:0] WAD[10:0]

1K x 18 DIA[17:0] DIB[17:0] DOA[17:0] DOB[17:0] RAD[9:0] WAD[9:0]

512 x 36 DIA[35:0] DIB[35:0] DOA[35:0] DOB[35:0] RAD[8:0] WAD[8:0]

Attribute Description Values Default Value Us er Selectable

Through IPexpress

Read Port Address

Depth

Address Depth

Read Port 16K, 8K, 4K, 2K, 1K, 512 YES

Read Port Data Width Data Word Width

Read Port 1, 2, 4, 9, 18, 36 1 YES

Write Port Address

Depth

Address Depth Write

Port 16K, 8K, 4K, 2K, 1K YES

Write Port Data Width Data Word Width

Write Port 1, 2, 4, 9, 18, 36 1 YES

Write Port Enable Out-

put Registers

(Pipelining) for Write

Port

NOREG, OUTREG NOREG YES

Enable GSR Enables Global Set

Reset ENABLE, DISABLE ENABLE YES

Reset Mode Selects the Reset

type ASYNC, SYNC ASYNC YES

Memory File Format BINARY, HEX, ADDRESSED

HEX YES

Read Port Write Mode Read / Write Mode

for Read Port NORMAL NORMAL YES

Write Port Write Mode Read / Write Mode

for Write Port NORMAL NORMAL YES

Chip Select Decode for

Read Port

Chip Select Decode

for Read Port

0b000, 0b001, 0b010, 0b011,

0b100, 0b101, 0b110, 0b111 0b000 NO

Chip Select Decode for

Write Port

Chip Select Decode

for Write Port

0b000, 0b001, 0b010, 0b011,

0b100, 0b101, 0b110, 0b111 0b000 NO

Init Value Initialization value

0x0000000000000000000000000

000000000000000000000000000

0......0xFFFFFFFFFFFFFFFFFFF

FFFFFFFFFFFFFFFFFFFFFFFF

FFFFFFFFFFFFF

0x000000000000

00000000000000

000000000000

10-19

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Users have the option to enable the output registers for Pseudo-Dual Port RAM (RAM_DP). Figures 10-16 and 10-

17 show the internal timing waveforms for Pseudo-Dual Port RAM (RAM_DP) with these options. It is important

that no setup and hold time violations occur on the address registers (RdAddress and WrAddress). Failing to meet

these requirements can result in corruption of memory contents. This applies to both read and write operations.

A Post Place and Route timing report in Lattice Diamond or ispLEVER design software can be run to verify that no

such timing errors occur. Refer to the timing preferences in the Online Help documents.

Figure 10-16. PSEUDO DUAL PORT RAM Timing Diagram – without Output Registers

Data_0 Data_1 Data_2

Invalid Data Data_0

WrClock

Data

WrClockEn

SUDATA_EBR

HDATA_EBR

SUCE_EBR

HCE_EBR

CO_EBR

Data_1 Dat

a_2

Add_0 Add_1 Add_2

RdAddress

SUADDR_EBR

HADDR_EBR

RdClock

RdClockEn

SUCE_EBR

HCE_EBR

Add_0 Add_1 Add_2

WrAddress

SUADDR_EBR

HADDR_EBR

10-20

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Figure 10-17. PSEUDO DUAL PORT RAM Timing Diagram - with Output Registers

Read Only Memory (ROM) - EBR Based

The EBR blocks in the LatticeXP2 devices can be configured as Read Only Memory or ROM. IPexpress allows

users to generate the Verilog-HDL or VHDL and the EDIF netlist for the memory size, as per design requirements.

Users are required to provide the ROM memory content in the form of an initialization file.

IPexpress generates the memory module as shown in Figure 10-18.

Figure 10-18. Read-Only Memory Module Generated by IPexpre ss

The generated module makes use of these EBR blocks or primitives. For memory sizes smaller than an EBR block,

the module will be created in one EBR block. If the specified memory is larger than one EBR block, multiple EBR

blocks can be cascaded, in depth or width (as required to create these sizes).

In ROM mode, the address for the port is registered at the input of the memory array. The output data of the mem-

ory is optionally registered at the output.

Data_0 Data_1 Data_2

Invalid Data Data_0

WrClock

Data

WrClockEn

tSUDATA_EBR tHDATA_EBR

tSUCE_EBR tHCE_EBR

tCOO_EBR

Dat

a_1

Add_0 Add_1 Add_2

RdAddress

tSUADDR_EBR tHADDR_EBR

RdClock

RdClockEn

tSUCE_EBR tHCE_EBR

Add_0 Add_1 Add_2

WrAddress

tSUADDR_EBR tHADDR_EBR

ROM

EBR based Read Only

Memory

OutClock

OutClockEn

Reset

Address

10-21

Lattice Semiconductor LatticeXP2 Memory Usage Guide

The various ports and their definitions for the ROM are listed in Table 10-11. The table lists the corresponding ports

for the module generated by IPexpress and for the ROM primitive.

Table 10-11. EBR-based ROM Port Definitions

Reset (RST) resets only the input and output registers of the RAM. It does not reset the contents of the memory.

Chip Select (CS) is a useful port when multiple cascaded EBR blocks are required by the memory. The CS signal

forms the MSB for the address when multiple EBR blocks are cascaded. Since CS is a 3-bit bus, it can cascade

eight memories easily. However, if the memory size specified by the user requires more than eight EBR blocks, the

ispLEVER software automatically generates the additional address decoding logic, which is implemented in the

PFU external to the EBR blocks.

While generating the ROM using IPexpress, the user must provide the initialization file to pre-initialize the contents

of the ROM. These files are the *.mem files and they can be of Binary, Hex or the Addressed Hex formats. The ini-

tialization files are discussed in detail in the Initializing Memory section of this document.

Users have the option of enabling the output registers for Read Only Memory (ROM). Figures 10-19 and 10-20

show the internal timing waveforms for the Read Only Memory (ROM) with these options.

Each EBR block consists of 18,432 bits of RAM. The values for x’s (for address) and y’s (data) for each EBR block

for the devices are as per Table 10-12.

Table 10-12. ROM Memory Sizes for 16K Memory for LatticeXP2

Table 10-13 shows the various attributes available for the Read Only Memory (ROM). Some of these attributes are

user-selectable through the IPexpress GUI. For detailed attribute definitions, refer to Appendix A.

Port Name

in Generated Module Port Name in the

EBR block Primitive Description Active State

Address AD[x:0] Read Address —

OutClock CLK Clock Rising Clock Edge

OutClockEn CE Clock Enable Active High

Reset RST Reset Active High

— CS[2:0] Chip Select —

ROM Output Data Address Port

[MSB:LSB]

16K x 1 DOA WAD[13:0]

8K x 2 DOA[1:0] WAD[12:0]

4K x 4 DOA[3:0] WAD[11:0]

2K x 9 DOA[8:0] WAD[10:0]

1K x 18 DOA[17:0] WAD[9:0]

512 x 36 DOA[35:0] WAD[8:0]

10-22

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Table 10-13. Pseudo-Dual Port RAM Attributes for LatticeXP2

Users have the option to enable the output registers for Read Only Memory (ROM). Figures 10-19 and 10-20 show

the internal timing waveforms for ROM with these options.

It is important that no setup and hold time violations occur on the address registers (Address). Failing to to meet

these requirements can result in corruption of memory contents. This applies to both read operations in this case.

A Post Place and Route timing report in Lattice Diamond or ispLEVER design software can be run to verify that no

such timing errors occur. Refer to the timing preferences in the Online Help documents.

Figure 10-19. ROM Timing Waveform – Without Output Registers

Attribute Description Values Default

Value Use r Selectable

Through IPexp ress

Address depth Address Depth Read Port 16K, 8K, 4K, 2K, 1K,

512 YES

Data Width Data Word Width Read Port 1, 2, 4, 9, 18, 36 1 YES

Enable Output Registers Register Mode (Pipelining) for Write Port NOREG, OUTREG NOREG YES

Enable GSR Enables Global Set Reset ENABLE, DISABLE ENABLE YES

Reset Mode Selects the Reset type ASYNC, SYNC ASYNC YES

Memory File Format BINARY, HEX,

ADDRESSED HEX YES

Chip Select Decode Chip Select Decode for Read Port

0b000, 0b001, 0b010,

0b011, 0b100, 0b101,

0b110, 0b111

0b000 NO

Add_0 Add_1 Add_2 Add_3 Add_4

Invalid Data Data_0

OutClock

Address

OutClockEn

SUADDR_EBR

HADDR_EBR

SUCE_EBR

HCE_EBR

CO_EBR

Data_1 Data_2 Data_3 Data_4

10-23

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Figure 10-20. ROM Timing Waveform - with Output Registers

First In First Out (FIFO, FIFO_DC) – EBR Based

FIFOs are not supported in certain devices such as the LatticeECP/EC, LatticeECP2/M, LatticeXP and MachXO.

The hardware has Embedded Block RAM (EBR) which can be configured in Single Port (RAM_DQ), Pseudo-Dual

Port (RAM_DP) and True Dual Port (RAM_DP_TRUE) RAMs. The FIFOs in these devices can be emulated FIFOs

that are built around these RAMs. The IPexpress point tool in the ispLEVER design software allows users to build a

FIFO and FIFO_DC around Pseudo Dual Port RAM (or DP_RAM).

Each of these FIFOs can be configured with (pipelined) and without (non-pipelined) output registers. In the pipe-

lined mode users have an extra option to enable the output registers by the RdEn signal. We will discuss the oper-

ation in the following sections.

Let us take a look at the operation of these FIFOs.

First In First Out (FIFO) Memory

The FIFO, or the single clock FIFO, is an emulated FIFO. The address logic and the flag logic is implemented in the

FPGA fabric around the RAM.

The ports available on the FIFO are:

• Reset

•Clock

•WrEn

•RdEn

•Data

•Q

• Full Flag

• Almost Full Flag

• Empty Flag

• Almost Empty Flag

Let us first discuss the non-pipelined or the FIFO without output registers. Figure 10-21 shows the operation of the

FIFO when it is empty and the data starts to get written into it.

Add_0 Add_1 Add_2 Add_3 Add_4

Invalid Data Data_0

OutClock

Address

OutClockEn

tSUADDR_EBR tHADDR_EBR

tSUCE_EBR tHCE_EBR

tCOO_EBR

Data_1 Data_2 Data_3

10-24

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Figure 10-21. FIFO without Output Registers, Start of Data Write Cycle

The WrEn signal must be high to start writing into the FIFO. The Empty and Almost Empty flags are high to begin

and Full and Almost Full are low.

When the first data is written into the FIFO, the Empty flag de-asserts (or goes low), as the FIFO is no longer

empty. In this figure we assume that the Almost Empty setting flag setting is 3 (address location 3). So the Almost

Empty flag gets de-asserted when the third address location is filled.

Now let us assume that we continue to write into the FIFO to fill it. When the FIFO is filled, the Almost Full and Full

Flags are asserted. Figure 10-22 shows the behavior of these flags. In this figure we assume that FIFO depth is 'N'.

Figure 10-22. FIFO without Output Re gisters, End of Data Wr ite Cycle

In this case, the Almost Full flag is in the 2 location before the FIFO is filled. The Almost Full flag is asserted when

the N-2 location is written, and the Full flag is asserted when the last word is written into the FIFO.

Data_1Invalid Data Data_2 Data_3 Data_4 Data_5

Clock

Reset

WrEn

RdEn

Data

Empty

Almost

Empty

Full

Almost

Full

Invalid QQ

Data_N-2 Data_N-1 Data_N Data_X

Clock

Reset

WrEn

RdEn

Data

Empty

Almost

Empty

Full

Almost Full

Invalid QQ

Data_X

10-25

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Data_X data inputs do not get written as the FIFO is full (the Full flag is high).

Now let us look at the waveforms when the contents of the FIFO are read out. Figure 10-23 shows the start of the

read cycle. RdEn goes high and the data read starts. The Full and Almost Full flags are de-asserted, as shown.

Figure 10-23. FIFO without Output Registers, Start of Data Read Cycle

Similarly, as the data is read out and FIFO is emptied, the Almost Empty and Empty flags are asserted.

Figure 10-24. FIFO without Output Registers, End of Data Read Cycle

Figures 10-21 to 10-24 show the behavior of non-pipelined FIFO or FIFO without output registers. When we pipe-

line the registers, the output data is delayed by one clock cycle. There is also the extra option for Output registers to

be enabled by the RdEn signal.

Data_1Invalid Data Data_2 Data_3 Data_4 Data_5

Clock

Reset

WrEn

RdEn

Data

Empty

Almost

Empty

Full

Almost Full

Invalid Data

Data_N-3 Data_N-2 Data_N-1 Data_N

Clock

Reset

WrEn

RdEn

Data

Empty

Almost

Empty

Full

Almost Full

Invalid Data

Data_N-4

10-26

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Figures 10-25 to 10-28 show the similar waveforms for the FIFO with output register and with output register enable

with RdEn. It should be noted that flags are asserted and de-asserted with similar timing to the FIFO without output

registers. However, it is only the data out 'Q' that is delayed by one clock cycle.

Figure 10-25. FIFO with Output Registers, Start of Data Write Cycle

Figure 10-26. FIFO with Output Registers, End of Data Write Cycle

Data_1Invalid Data Data_2 Data_3 Data_4 Data_5

Clock

Reset

WrEn

RdEn

Data

Empty

Almost

Empty

Full

Almost

Full

Invalid Q

Data_N-2 Data_N-1 Data_N Data_X

Clock

Reset

WrEn

RdEn

Data

Empty

Almost

Empty

Full

Almost Full

Invalid Q

Data_X

10-27

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Figure 10-27. FIFO with Output Registers, Start of Data Read Cycle

Figure 10-28. FIFO with Output Regist ers, End of Data Read Cycle

And finally, if you select the option enable output register with RdEn, it still delays the data out by one clock cycle

(as compared to the non-pipelined FIFO). The RdEn should also be high during that clock cycle, otherwise the data

takes an extra clock cycle when the RdEn goes true.

Data_1

Invalid Data

Data_2 Data_3 Data_4

Clock

Reset

WrEn

RdEn

Data

Empty

Almost

Empty

Full

Almost Full

Invalid Data

Data_N-4 Data_N-3 Data_N-2 Data_N-1 Data_N

Clock

Reset

WrEn

RdEn

Data

Empty

Almost

Empty

Full

Almost Full

Invalid Data

QData_N-5

10-28

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Figure 10-29. FIFO with Output Registers and RdEn on Output Registers

Dual Clock First In First Out (FIFO_DC) Memory:

The FIFO_DC or the dual clock FIFO is also an emulated FIFO. Again, the address logic and the flag logic is imple-

mented in the FPGA fabric around the RAM.

The ports available on the FIFO_DC are:

• Reset

• RPReset

• WrClock

•RdClock

•WrEn

•RdEn

•Data

•Q

• Full Flag

• Almost Full Flag

• Empty Flag

• Almost Empty Flag

FIFO_DC Flags

The FIFO_DC, as an emulated FIFO, required the flags to be implemented in the FPGA logic around the block

RAM. Because of the two clocks, the flags were required to change clock domains from read clock to write clock

and vice versa. This adds latency to the flags either during assertion or de-assertion. The latency can be avoided

only in one of the cases (either assertion or de-assertion) or distributed among these cases.

In the current emulated FIFO_DC, there is no latency during assertion of these flags which we feel is more impor-

tant. Thus, when these flags are required to go true, there is no latency. However, due to the design of the flag logic

running on two clock domains, there is latency during the de-assertion.

Data_1Invalid Data Data_2 Data_3 Data_4 Data_5

Clock

Reset

WrEn

RdEn

Data

Empty

Almost

Empty

Full

Almost

Full

Data_1

Invalid Data

Data_2

10-29

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Let us assume that we start to write into the FIFO_DC to fill it. The write operation is controlled by WrClock and

WrEn, however it takes extra RdClock cycles for de-assertion of the Empty and Almost Empty flags.

On the other hand, de-assertion of Full and Almost Full result in the reading out of the data from the FIFO_DC. It

takes extra WrClock cycles, after reading this data, for the flags to come out.

With this in mind, let us look at the FIFO_DC without output registers waveforms. Figure 10-30 shows the operation

of the FIFO_DC when it is empty and the data starts to be written into it.

Figure 10-30. FIFO_DC without Output Registers, Start of Data Write Cycle

The WrEn signal must be high to start writing into the FIFO_DC. The Empty and Almost Empty flags are high to

begin and Full and Almost full are low.

When the first data is written into the FIFO_DC, the Empty flag de-asserts (or goes low), as the FIFO_DC is no lon-

ger empty. In this figure we assume that the Almost Empty setting flag setting is 3 (address location 3). So the

Almost Empty flag is de-asserted when the third address location is filled.

Now let us assume that we continue to write into the FIFO_DC to fill it. When the FIFO_DC is filled, the Almost Full

and Full Flags are asserted. Figure 10-31 shows the behavior of these flags. In this figure the FIFO_DC depth is

'N'.

Data_1Invalid Data Data_2 Data_3 Data_4 Data_5

WrClock

Reset

WrEn

RdEn

Data

Empty

Almost

Empty

Full

Almost

Full

Invalid Q

RdClock

RPReset

10-30

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Figure 10-31. FIFO_DC without Output Registers, End of Data Write Cycle

In this case, the Almost Full flag is in the 2 location before the FIFO_DC is filled. The Almost Full flag is asserted

when the N-2 location is written, and the Full flag is asserted when the last word is written into the FIFO_DC.

Data_X data inputs do not get written as the FIFO_DC is full (the Full flag is high).

Note that the assertion of these flags is immediate and there is no latency when they go true.

Now let us look at the waveforms when the contents of the FIFO_DC are read out. Figure 10-32 shows the start of

the read cycle. RdEn goes high and the data read starts. The Full and Almost Full flags are de-asserted, as shown.

In this case, note that the de-assertion is delayed by two clock cycles.

WrClock

Reset

Empty

Almost

Empty

Full

Almost

Full

Invalid Q

RdClock

RPReset

Data_N-2 Data_N-1 Data_N Data_X Data_X

WrEn

RdEn

Data

10-31

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Figure 10-32. FIFO_DC without Output Registers, Start of Data Read Cycle

Similarly, as the data is read out, and FIFO_DC is emptied, the Almost Empty and Empty flags are asserted.

Figure 10-33. FIFO_DC without Output Registers, End of Data Read Cycle

WrClock

Reset

Empty

Almost

Empty

Full

Almost

Full

Invalid Data

RdClock

RPReset

Data_1 Data_2Invalid Q

WrEn

RdEn

Data

Data_3 Data_6Data_5Data_4

WrClock

Reset

Empty

Almost

Empty

Full

Almost

Full

Invalid Data

RdClock

RPReset

WrEn

RdEn

Data

Data_N-2 Data_N-1 Data_N Data_NData_N-3

10-32

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Figure 10-33 show the behavior of non-pipelined FIFO_DC or FIFO_DC without output registers. When we pipeline

the registers, the output data is delayed by one clock cycle. There is an extra option for the output registers to be

enabled by the RdEn signal.

Figures 10-34 to 10-37 show the similar waveforms for the FIFO_DC with output register and without output regis-

ter enable with RdEn. Note that flags are asserted and de-asserted with similar timing to the FIFO_DC without out-

put registers. However, it is only the data out 'Q' that is delayed by one clock cycle.

Figure 10-34. FIFO_DC with Output Registers, Start of Data Write Cycle

Data_1Invalid Data Data_2 Data_3 Data_4 Data_5

WrClock

Reset

WrEn

RdEn

Data

Empty

Almost

Empty

Full

Almost

Full

Invalid Q

RdClock

RPReset

10-33

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Figure 10-35. FIFO_DC with Output Registers, End of Data Write Cycle

Figure 10-36. FIFO_DC with Output Re gisters, Start of Data Read Cycle

WrClock

Reset

Empty

Almost

Empty

Full

Almost

Full

Invalid Q

RdClock

RPReset

Data_N-2 Data_N-1 Data_N Invalid

Data

Invalid

Data

WrEn

RdEn

Data

WrClock

Reset

Empty

Almost

Empty

Full

Almost

Full

Invalid Data

RdClock

RPReset

Data_1

Invalid Q

WrEn

RdEn

Data

Data_2 Data_5Data_4Data_3

10-34

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Figure 10-37. FIFO_DC with Output Registers, End of Data Read Cycle

And finally, if you select the option to enable the output register with RdEn, it still delays the data out by one clock

cycle (as compared to the non-pipelined FIFO_DC). The RdEn should also be high during that clock cycle, other-

wise the data takes an extra clock cycle when the RdEn is goes true.

Figure 10-38. FIFO_DC with Output Registers and RdEn on Output Registers

WrClock

Reset

Empty

Almost

Empty

Full

Almost

Full

Invalid Data

RdClock

RPReset

WrEn

RdEn

Data

Data_N-3 Data_N-2 Data_1 Data_NData_N-4

WrClock

Reset

Empty

Almost

Empty

Full

Almost

Full

Invalid Data

RdClock

RPReset

Invalid Q

WrEn

RdEn

Data

Data_3Data_2Data_1

10-35

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Distributed Single Port RAM (Distributed_SPRAM) – PFU Based

PFU-based Distributed Single Port RAM is created using the 4-input LUT (Look-Up Table) available in the PFU.

These LUTs can be cascaded to create larger Distributed Memory sizes.

Figure 10-39 shows the Distributed Single Port RAM module as generated by IPexpress.

Figure 10-39. Distributed Single Port RAM Module Generated by IPexpress

The generated module makes use 4-input LUT available in the PFU. Additional logic like Clock, Reset is generated

by utilizing the resources available in the PFU.

Ports such as Read Clock (RdClock) and Read Clock Enable (RdClockEn), are not available in the hardware prim-

itive. These are generated by IPexpress when the user wants the to enable the output registers in their IPexpress

configuration.

The various ports and their definitions for the memory are as per Table 10-14. The table lists the corresponding

ports for the module generated by IPexpress and for the primitive.

Table 10-14. PFU-based Distributed Single Port RAM Port Definitions

Ports such as Clock Enable (ClockEn) are not available in the hardware primitive. These are generated by IPex-

press when the user wishes to enable the output registers in the IPexpress configuration.

Users have the option of enabling the output registers for Distributed Single Port RAM (Distributed_SPRAM). Fig-

ures 10-40 and 10-41 show the internal timing waveforms for the Distributed Single Port RAM

(Distributed_SPRAM) with these options.

Port Name in

Generated Module Port Name in the

PFU Primitive Description Active State

Clock CK Clock Rising Clock Edge

ClockEn — Clock Enable Active High

Reset — Reset Active High

WE WRE Write Enable Active High

Address AD[3:0] Address —

Data DI[1:0] Data In —

Q DO[1:0] Data Out —

PFU based

Distributed Single Port

Memory

Clock

ClockEn

Reset

Address

Data

10-36

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Figure 10-40. PFU Based Distribut ed Single Port RAM Timing Waveform - without Output Registers

Figure 10-41. PFU Based Distribut ed Single Port RAM Timing Waveform - with Output Registers

Add_0 Add_1 Add_0 Add_1 Add_2

Data_0 Data_1

Invalid Data Data_0

Clock

Address

Data

ClockEn

HWREN_PFU

SUADDR_PFU HADDR_PFU

SUDATA_PFU HDATA_PFU

CORAM_PFU

Data_1

SUWREN_PFU

Data_2

Add_0 Add_1 Add_0 Add_1 Add_2

Data_0 Data_1

Invalid Data Data_0

Clock

Address

Data

ClockEn

HWREN_PFU

SUADDR_PFU HADDR_PFU

SUDATA_PFU HDATA_PFU

SUWREN_PFU

Reset

Data_1 Data_2

10-37

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Distributed Dual Port RAM (Distributed_DPRAM) – PFU Based

PFU-based Distributed Dual Port RAM is also created using the 4-input LUT (Look-Up Table) available in the PFU.

These LUTs can be cascaded to create a larger Distributed Memory sizes.

Figure 10-42. Distributed Dual Port RAM Module Generate d by IPexpress

The generated module makes use of the 4-input LUT available in the PFU. Additional logic like Clock and Reset is

generated by utilizing the resources available in the PFU.

Ports such as Read Clock (RdClock) and Read Clock Enable (RdClockEn), are not available in the hardware prim-

itive. These are generated by IPexpress when the user wants the to enable the output registers in the IPexpress

configuration.

The various ports and their definitions for memory are as per Table 10-15. The table lists the corresponding ports

for the module generated by IPexpress and for the primitive.

Table 10-15. PFU-based Distributed Dual-Port RAM Port Definitions

Ports such as Read Clock (RdClock) and Read Clock Enable (RdClockEn) are not available in the hardware primi-

tive. These are generated by IPexpress when the user wants to enable the output registers in the IPexpress config-

uration.

Port Name in

Generated Module Port Name in the EBR

Block Primitive Description Active State

WrAddress WAD[3:0] Write Address —

RdAddress RAD[3:0] Read Address —

RdClock — Read Clock Rising Clock Edge

RdClockEn — Read Clock Enable Active High

WrClock WCK Write Clock Rising Clock Edge

WrClockEn — Write Clock Enable Active High

WE WRE Write Enable Active High

Data DI[1:0] Data Input —

Q RDO[1:0] Data Out —

PFU based

Distributed Dual Port

Memory

WrAddress

RdAddress

RdClock

RdClockEn

Reset Q

WrClock

WrClockEn

Data

10-38

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Users have the option of enabling the output registers for Distributed Dual Port RAM (Distributed_DPRAM). Fig-

ures 10-43 and 10-44 show the internal timing waveforms for the Distributed Dual Port RAM (Distributed_DPRAM)

with these options.

Figure 10-43. PFU Based Distributed Dual Port RAM Timing Waveform - without Output Registers

Data_0 Data_1 Data_2

Invalid Data

WrClock

Data

WrClockEn

SUDATA_EBR HDATA_EBR

CORAM_PFU

SUCE_EBR HCE_EBR

RdAddress

Add_0 Add_1 Add_2WrAddress

SUADDR_EBR HADDR_EBR

Add_0 Add_1 Add_2

Data_0

Data_1 Data_2

10-39

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Figure 10-44. PFU Based Distributed Dual Port RAM Timing Waveform - with Output Registers

Distributed ROM (Distributed_ROM) – PFU Based

PFU-based Distributed ROM is also created using the 4-input LUT (Look-Up Table) available in the PFU. These

LUTs can be cascaded to create larger Distributed Memory sizes.

Figure 10-45 shows the Distributed ROM module as generated by IPexpress.

Figure 10-45. Distrib uted ROM Generated by IPexpress

The generated module makes use of the 4-input LUT available in the PFU. Additional logic like Clock and Reset is

generated by utilizing the resources available in the PFU.

Data_0 Data_1

Invalid Data Data_0

WrClock

Data

WrClockEn

SUDATA_PFU HDATA_PFU

SUWREN_PFU HWREN_PFU

CORAM_PFU

Data_1

Add_0 Add_1

RdAddress

RdClock

RdClockEn

SUCE_PFU HCE_PFU

Add_0 Add_1

WrAddress

SUADDR_PFU HADDR_PFU

Reset

SUWREN_PFU HWREN_PFU

PFU-based

Distributed ROM

Address

OutClock

OutClockEn

Reset

10-40

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Ports such as Out Clock (OutClock) and Out Clock Enable (OutClockEn) are not available in the hardware primi-

tive. These are generated by IPexpress when the user wants to enable the output registers in the IPexpress config-

uration.

The various ports and their definitions for memory are as per Table 10-16. The table lists the corresponding ports

for the module generated by IPexpress and for the primitive.

Table 10-16. PFU-based Distributed ROM Port Definitions

Users have the option to enable the output registers for Distributed ROM (Distributed_ROM). Figures 10-46 and

10-47 show the internal timing waveforms for the Distributed ROM with these options.

Figure 10-46. PFU Based ROM Timing Waveform – without Output Registers

Figure 10-47. PFU Based ROM Timing Waveform – with Output Registers

Port Name in

Generated Module Port Name in the PFU

Block Primitive Description Active State

Address AD[3:0] Address —

OutClock — Out Clock Rising Clock Edge

OutClockEn — Out Clock Enable Active High

Reset — Reset Active High

Q DO Data Out —

Add_0 Add_1 Add_2

Invalid Data Data_0

Address

SUADDR_PFU HADDR_PFU

CORAM_PFU

Data_1 Data_2

Add_0 Add_1 Add_2

Invalid Data Data_0

OutClock

Address

OutClockEn

SUADDR_PFU HADDR_PFU

Data_1

Reset

CORAM_PFU

10-41

Lattice Semiconductor LatticeXP2 Memory Usage Guide

User TAG Memory

The TAG memory is an area on the on-chip Flash which can be used for non-volatile storage. It is accessed in your

design as if it were an external SPI Flash. Both SPI bus operation modes 0 (0,0) and 3 (1,1) are supported.

Figure 10-48. SSPIA Primitive

Table 10-17. User TAG Memory Signal Description

Basic Specifications for TAG Memory

There is one full page of TAG memory in each LatticeXP2 device. Page size ranges from 56 to 451 bytes.

Table 10-18. TAG Memory Density

Primitive

Port Name Description

SI Data input

SO Data output

CLK Clock

CS Chip select

Device TAG Memory (Bits) TAG Memory

(Bytes)

XP2-5 632 79

XP2-8 768 96

XP2-17 2184 273

XP2-30 2640 330

XP2-40 3384 423

SSPIA

CLK

10-42

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Table 10-19. Timing Specifications

Figure 10-49. Generic Timing Diagram

Programming via the SPI Interface

Since the SSPIA module is an internal module, I/Os can be treated as I/Os of any other soft module. Therefore,

they can be routed to other internal modules, or they can go out to I/O pads. The recommended routing is to the

sysCONFIG port pins.

Table 10-20. Usage Of Commands

Symbol Parameter Min Max Units

fMAXSPI Slave SPI CCLK Clock Frequency 25 MHz

tRF Clock and Data Input Rise and Fall Time 20 ns

tCSCCLK Slave SPI CCLK Clock High Time 20 ns

tSOCDO Slave SPI CCLK Clock Low Time 20 ns

tSCS CSSPIN High Time 25 ns

tSCSS CSSPIN Setup Time 25 ns

tSCSH CSSPIN Hold Time 25 ns

tSTSU Slave SPI Data In Setup Time 5 ns

tSTH Slave SPI Data In Hold Time 5 ns

tSTVO

Slave SPI Output Valid (after WRITE_EN) 20 ns

Slave SPI Output Valid (without WRITE_EN)(1) 3 20 µs

tSTCO Slave SPI Output Hold Time 0 ns

tSDIS Slave SPI Output Disable Time 100 ns

Note: If the READ_TAG command is issued without first loading the WRITE_EN command, the device will need extra time,

up to 20µs maximum, to transfer the data from TAG Flash to the data-shift register.

Command Name OPCODE Bytes 1-31, 2 Data Delay Time Description

READ_TAG 0x4E Dummy Out 3µs min. Read TAG memory

PROGRAM_TAG 0x8E Dummy In 1ms min., 25ms max. Program TAG memory

ERASE_TAG 0x0E Dummy 100ms min., 1000ms max. Erase TAG memory

1. Data bytes are shifted with most significant bit first.

2. Byte 1-3 are dummy clocks to provide extra timing for the device to execute the command. The data presented at the SI pin

during these dummy clocks can be any value and do not have to be 0x00 as shown.

tSCS

0 Command 7 8 3-Byte Dummy 31 32 Byte Bounded Data Out (n-1)th

CSSPISN

CCLK

SISPI

SO HI-Z

Data Shifting Clocks

8 Command

Shifting Clocks

0 1 2 n-1

tSCSS

tSTVO

tSTSU

tSTH

tSTCO tSDIS

tSCSH

HI-Z

tSTSU

tSOCDO

tCSCLK

10-43

Lattice Semiconductor LatticeXP2 Memory Usage Guide

General Description

The LatticeXP2 family of devices is designed with instant-on, standalone TAG memory that is always available.

TAG memory is organized as a one-page Flash non-volatile memory accessible by the hardwired Serial Peripheral

Interface port or the JTAG port.

The standalone TAG memory is ideal for use as scratch pad memory for critical data, board serialization, board

revision logs and programmed pattern identification.

The integration of TAG memory into the LatticeXP2 device family saves chip count and board space. It also can be

used to replace obsoleted low-density SPI EEPROM devices.

The hardwired SPI interface does not require the device to pre-program the configuration Flash first to enable the

SPI interface. The interface is already enabled when the device is shipped from Lattice, saving board test time.

The hard-wired SPI interface allows the TAG memory to retain its independent identity or accessible always in spite

of the TAG Memory Flash is embedded into the LatticeXP2 devices.

The hard-wired SPI interface is also important for field upgrades so that critical data can be maintained on the TAG

memory and guaranteed to be accessible even if the device is field upgraded to a new pattern.

The instant-on capability is achieved by enabling the SPI interface when the devices are shipped from Lattice.

Unlike the configuration Flash, the security setting of the device, standard or advanced, has no effect on the acces-

sibility of the TAG memory. Therefore, the TAG memory is always accessible.

The TAG memory, same as other Flash fuses, can also be programmed using the IEEE 1532 compliant program-

ming flow on the JTAG port for production programming support or for system debugging.

Pin Descriptions

The pins described below are not dedicated pins. If the TAG memory feature is not required, these pins can be reg-

ular user I/O pins. If the TAG memory feature is required, the TAG memory can be accessed by the internal SPI

interface through the core. The internal SPI interface makes the TAG Memory capable of supporting advanced

applications. For example:

1. Use an I2C to SPI translator to convert the SPI TAG memory to be an I2C TAG memory device.

2. Route the four SPI interfaces to the other four user I/Os.

Selections are made using the ispLEVER design tool. By default, the external SPI interface is enabled and TAG

memory is selected.

The functional descriptions of the pins below are applicable to both the internal and external SPI interfaces.

Serial Data Input (SI)

The SPI Serial Data Input pin provides a means for commands and data to be serially written to (shifted into) the

device. Data is latched on the falling edge of the serial clock (CLK) input pin.

Serial Data Output (SO)

The SPI Serial Data Output pin provides a means for status and data to be serially read out (shifted out of) the

device. Data is shifted out on the falling edge of the serial clock (CLK) input pin.

Serial Clock (CLK)

The SPI Serial Clock Input pin provides the timing for serial input and output operations.

Chip Select (CS)

The SPI Chip Select pin enables and disables SPI interface operations. When the Chip Select is high the SPI inter-

face is deselected and the Serial Data Output (SO) pin is at high impedance. When it is brought low, the SPI inter-

10-44

Lattice Semiconductor LatticeXP2 Memory Usage Guide

face is selected and commands can be written into and data read from the device. After power up, CS must transit

from high to low before a new command can be accepted.

SPI Operations

SPI Modes

The SPI interface is accessible through the SPI-compatible bus consisting of four signals: Serial Clock (CLK), Chip

Select (CS), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus operation Modes 0 (0,0) and 3 (1,1)

are supported. The primary difference between Mode 0 and Mode 3 concerns the normal state of the CLK pin

when the SPI master is in standby and data is not being transferred to the device’s SPI interface. For Mode 0 the

CLK is normally low and for Mode 3 the CLK signal is normally high. In either case, data input on the SI pin is sam-

pled only during the rising edge. Data output on the SO pin is clocked out only on the falling edge of CLK.

Stat u s Re gi st er

The SPI interface can access the 1-bit status register required to support TAG Memory Flash programming.

The programming complete status register: This is the single bit status register for pooling. If the programming or

erase operation is complete, then the status bit is set to 1, otherwise it is set to 0 for more programming or erase

time.

Commands

Table 10-21. Commands

READ_ID (98h)

The READ_ID command captures the IEEE 1149.1 JTAG IDCODE out of the device on the SO pin. This command

is commonly used to verify whether communication is established with the SPI bus. After the 8-bit READ_ID com-

mand is received, the device ignores the data presented at the Serial Data Input (SI) pin. The Serial Output (SO)

pin is enabled on the falling edge of clock 31 to drive out the first bit of the IDCODE. After 32 bits of the IDCODE

are shifted out, additional clocking will cause dummy data to be shifted out on SO.

Command Name Byte 1

(Opcode) Byte 2 Byte 3 Byt e 4 Byte 5 Byte 6 n-Byte

READ_ID 0x98 0x00 0x00 0x00 (D0-D7) (D8-D15) (D24-D31)

WRITE_EN 0xAC 0x00 0x00 0x00

WRITE_DIS 0x78 0x00 0x00 0x00

ERASE_TAG 0x0E 0x00 0x00 0x00

PROGRAM_TAG 0x8E 0x00 0x00 0x00 D7-D0 Next Byte Last Byte

READ_TAG 0x4E 0x00 0x00 0x00 (D7-D0) (Next Byte) (Continue)

STATUS 0x4A 0x00 0x00 0x00

(b1xxxxxxx

b0xxxxxxx)

Notes:

1. Data bytes are shifted with most significant bit first. Byte field with data in parenthesis ( ) indicate data being read from the SO pin.

2. Byte 2-4 are dummy clocks to provide extra timing for the device to execute the command. The data presented at the SI pin during these

dummy clocks can be any value and do not have to be 0x00 as shown.

3. The READ_ID command reads out the 32 bits JTAG IDCODE of the device. The first bit shifted out on SO pin is thus bit 0 of the JTAG

IDCODE and the last bit is bit 31 of the IDCODE.

4. The PROGRAM_TAG command supports page programming only. The programming data shift into the TAG Memory must be exactly the

same size as the one page of the TAG Memory. Under shifting or over shifting will cause erroneous data programmed into the TAG Mem-

ory. The Last Byte shown on the n-Byte column indicates the last byte of the data must be shifted into the device before driving the Chip

Select to high to start the programming action.

5. The STATUS command read from the single bit status register. When read from the register, only the first bit is valid, the other bits are dum-

mies and should be ignored.

10-45

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Figure 10-50. READ_ID Waveform

WRITE_EN (ACh)

The WRITE_EN command enables the TAG memory for programming. If the WRITE_EN command has not been

shifted into the device first, the PROGRAM_TAG, ERASE_TAG and STATUS commands do not take effect. This is

to prevent the TAG memory from erroneous erase or program.

The command is executed when the Chip Select pin is driven from low to high after the 24th dummy clock. Any

extra dummy clocks, if presented before driving the Chip Select pin to high, are ignored. After the Chip Select pin is

driven from low to high, a minimum of three clocks are required to complete the execution of the command.

The effect of this command is terminated by the WRITE_DIS command.

Figure 10-51. WRITE_EN Waveform

WRITE_DIS (78h)

The WRITE_DIS command disables the TAG memory for programming. It does not nullify the READ_TAG and

READ_ID commands.

The command is executed when the Chip Select pin is driven from low to high after the 24th dummy clock. Any

extra dummy clocks, if presented before driving the Chip Select pin to high, are ignored. After the Chip Select pin is

driven from low to high, a minimum of three clocks are required to complete the execution of the command.

CLK

HI-Z

32 Bits JTAG IDCODE

8 Bits READ_ID

Command

0 1 2 31 HI-Z

24 Bits Dummy

CLK

HIGH IMPEDANCE

3 Clocks To Initiate And Complete

Optional Extra Clocks

8 Command

Shifting Clocks

10-46

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Figure 10-52. WRITE_DIS Waveform

ERASE_TAG (0Eh)

The ERASE_TAG command is enabled after the command WRITE_EN has been shifted into the device and exe-

cuted. The ERASE_TAG command erases all the TAG Memory Flash cells.

The command is executed when the Chip Select pin is driven from low to high after the 24th dummy clock. Any

extra dummy clocks, if presented before driving the Chip Select pin to high, are ignored. After the Chip Select pin is

driven from low to high, a minimum of three clocks is required to initiate the erase action. After the three clocks,

extra clocks are optional. Once the erase action is initiated, it will be carried out until it is done. There is no mecha-

nism to terminate the erase action.

This command sets the STATUS bit to 0 when the erase action begins. The programming engine sets the status bit

to 1 when the erase is done successfully.

Figure 10-53. ERASE_TAG Wav eform

PROGRAM_TAG (8Eh)

The PROGRAM_TAG is enabled after the command WRITE_EN has been shifted into the device and executed.

The PROGRAM_TAG command programs the entire TAG memory page at once.

After the command is shifted into the device on the SI pin, and followed by 24 dummy clocks, the TAG memory col-

umn decoder serves as the data buffer for the programming data to be shifted into serially. The shifting direction is

from left to right, as shown. The first bit to be shifted out closest to the SO pin appears on the right-most side of the

shift register. The data buffer functions like a FIFO (First In First Out) serial data shift register. In order to make sure

that bit 0 will be read out first, data bit 0 must be shifted into the right-most location of the data shift register. To

achieve this, the data buffer must be filled up completely. Consequently, over-filling the data buffer will cause over-

flow of the data buffer, resulting in loss of data.

CLK

SO HIGH IMPEDANCE

Three Clocks to Initiate And Complete

Optional Extra Clocks

8 Command

Shifting Clocks

CLK

HIGH IMPEDANCE

Three Clocks To Initiate the Erase Action

Optional Extra Clocks

8 Command

Shifting Clocks

10-47

Lattice Semiconductor LatticeXP2 Memory Usage Guide

The SO pin stays in the HIGHZ state throughout this command.

Figure 10-54. Bit Shifting Order

When the data buffer has filled up to one page of data, driving the Chip Select pin to high terminates the data shift-

ing. After the Chip Select pin is driven from low to high, a minimum of three clocks are required to initiate the pro-

gramming action. In the programming action, the data buffer content is copied in parallel from the data buffer into

the TAG memory Flash cells. The status bit is set to 0 when the programming actions begin. The status bit is set to

1 when the programming action is done successfully.

Figure 10-55. Data Buffer to Flash Cell Mapping

When the programming action complete, the STATUS bit is set to 1. The exact same image is written into the Flash

cells of the TAG Memory block when the programming action complete.

Figure 10-56. PROGRAM_TAG Waveform

READ_TAG (4Eh)

The READ_TAG command enables the Flash programming engine to transfer data programmed in the Flash cells

to the data buffer. The transfer action starts on the third dummy clock after the 8-bit opcode. The delay time derived

from the 21 dummy clocks is the time required to transfer the Flash cells data into the data buffer. The transfer

action, once initiated, does not need the clock to continue to run. The clock count is only required to enable the SO

pin. If the Flash circuitry is not yet enabled, the device will need extra delay time to enable the Flash circuitry before

transfer can take place. This extra delay must be provided after the third dummy clock and before the 24th dummy

clock.

If the READ_TAG command is preceded by the WRITE _EN command, then it is fast read. The device does not

require extra delay to enable the Flash circuitry.

The 20 dummy clocks after the transfer is initiated to before enabling the SO pin are considered delay clocks.

SI SO

Bit 0

Bit N-1

Flash Memory Cells

Bit N-1 Bit 0

Flash

Cell 0

Flash

Cell N-1

CLK

HIGH IMPEDANCE

Three Clocks To Initiate The Program Action

Optional Extra Clocks

8 Command

Shifting Clocks

10-48

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Delay time = 20 x 1/frequency.

The transfer delay time, including the extra delay time to enable the Flash circuitry, is 5uS minimum. The clock fre-

quency can then be set to 2.5 MHz if continuous clocking is desired.

When all the data captured into the data buffer are shifted out, additional clocks will shift out dummy data. The SI

pin is not connected to the input of the data buffer when the READ_TAG command is shifted into the device. While

the data in the data buffer is shifted out to the direction of SO, dummy data is shifted into the data buffer. Conse-

quently, when over-shifting occurs, dummy data of unknown value is shifted out.

Figure 10-57. Readout Order

Figure 10-58. READ_TAG Waveform

STATUS (4Ah)

The STATUS command allows the single-bit status register to be read. This command can be loaded at any time

after the WRITE_EN command has already been shifted into the device first. This command does not terminate

the programming or erase action. It is used to report the progress of the programming or erase action.

The status register actual size is only 1 bit. Dummy data is shifted out on the SO pin if extra data shifting clocks are

applied. The command can be shifted into the device again to capture the status bit and then read out.

During the interval of shifting the command, the additional programming or erase time is provided by driving the

Chip Select pin to high and holding the CLK pin low. Clocking while holding the Chip Select pin high is optional.

If the maximum programming time or erasure has expired and the status bit still is not set to 1, then erase or pro-

gramming has failed.

Flash Memory Cells

Bit 0

Bit N-1

Flash

Cell 0

Flash

Cell N-1

Bit 0

Bit N-1

CLK

SO HI-Z

8 Bits READ_TAG

Command

0 1 2 N-1 HI-Z

24 Bits Dummy

Enable SO on 24th Dummy Clock.

Bit 0 is valid.

Time elapsed must be 5µs

Data capture

starts at

21st clock

If the clock is too fast

add delay before

21st clock

TAG Memory Data

10-49

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Figure 10-59. STATUS Waveform

Specifications and T iming Diagrams

Powering Up

TAG memory is available when the boot-up either from the internal embedded Flash or from the external SPI Flash

boot PROM is complete. If the embedded Flash is blank, the boot up will not work. It is recommended to wait for the

same amount of delay as if the embedded configuration has been programmed before accessing the TAG memory.

If the boot-up is from external SPI Flash, longer delay time should be given or check the DONE pin for a high first

before accessing the TAG memory.

The SPI interface needs the low-to-high transition on the Chip Select pin to reset. During power-up, the low-to-high

transition is assured by requiring the CLK pin tracking the VCC. The other method is to drive the Chip Select pin to

high then low then high to reset the SPI interface before shifting the first command into the device.

Figure 10-60. Device Power-up Waveform

CLK

SO HI-Z

8 Bits READ_TAG

Command

0 1 2

Dummy

HI-Z

24 Bits Dummy

Capture Starts on Third Dummy Clock

Enable SO On 24th Dummy Clock

Status Bit

6 7

Provide Device Additional Erase

Or Programming Time

Power Up Timing And Voltage Level

VCCAUX Or VCC

Whichever Is The

Last.

VCCmin

Boot Up From The

Embedded FLASH.

TAG Memory Is Fully

Accessible.

Chip Select Must Track VCC.

10-50

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Availability of TAG Memory

TAG memory is available most of time on the Slave SPI interface with the following exceptions:

• When the SRAM fuses are being accessed by the JTAG port, Slave SPI interface or refreshing

• When the other Flash cells are being accessed through the JTAG port or Slave SPI interface

• While JTAG BSCAN testing is taking place

• The Slave SPI interface is disabled with the persistent fuse programmed (set to off)

AC Timing

• 25 MHz maximum CLK

• 5 uS minimum read command delay

• 2 mS minimum delay from VCCmin to shifting in the first command

Programming Timing

• 1 sec. maximum erase time

• 5 mS maximum programming time

Programming via the JTAG Interface

.VME files can be generated for the ispVM System software which only programs the TAG memory. These .VME

files are handled according to the standard ispVME flow.

Initializing Memory

In the EBR based ROM or RAM memory modes and the PFU based ROM memory mode, it is possible to specify

the power-on state of each bit in the memory array. Each bit in the memory array can have one of two values: 0 or

Initialization File Format

The initialization file is an ASCII file, which users can create or edit using any ASCII editor. IPexpress supports

three types of memory file formats:

• Binary file

• Hex File

• Addressed Hex

The file name for the memory initialization file is *.mem (<file_name>.mem). Each row depicts the value to be

stored in a particular memory location and the number of characters (or the number of columns) represents the

number of bits for each address (or the width of the memory module).

The Initialization File is primarily used for configuring the ROMs. The EBR in RAM mode can optionally use this Ini-

tialization File also to preload the memory contents.

The TAG memory uses hex or binary non-addressed files. Since it is a SPI, it cannot use the addressed hex file.

10-51

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Binary File

The file is essentially a text file of 0’s and 1’s. The rows indicate the number of words and columns indicate the

width of the memory.

Memory Size 20x32

00100000010000000010000001000000

00000001000000010000000100000001

00000010000000100000001000000010

00000011000000110000001100000011

00000100000001000000010000000100

00000101000001010000010100000101

00000110000001100000011000000110

00000111000001110000011100000111

00001000010010000000100001001000

00001001010010010000100101001001

00001010010010100000101001001010

00001011010010110000101101001011

00001100000011000000110000001100

00001101001011010000110100101101

00001110001111100000111000111110

00001111001111110000111100111111

00010000000100000001000000010000

00010001000100010001000100010001

00010010000100100001001000010010

00010011000100110001001100010011

Hex File

The Hex file is essentially a text file of Hex characters arranged in a similar row-column arrangement. The number

of rows in the file is same as the number of address locations, with each row indicating the content of the memory

location.

Memory Size 8x16

A001

0B03

1004

CE06

0007

040A

0017

02A4

Addressed Hex

Addressed Hex consists of lines of address and data. Each line starts with an address, followed by a colon, and

any number of data. The format of memfile is address: data data data data ... where address and data are hexa-

decimal numbers.

-A0 : 03 F3 3E 4F

-B2 : 3B 9F

The first line puts 03 at address A0, F3 at address A1, 3E at address A2,and 4F at address A3. The second line

puts 3B at address B2 and 9F at address B3.

There is no limitation on the values of address and data. The value range is automatically checked based on the

values of addr_width and data_width. If there is an error in an address or data value, an error message is printed.

10-52

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Users need not specify data at all address locations. If data is not specified at certain address, the data at that loca-

tion is initialized to 0. IPexpress makes memory initialization possible both through the synthesis and simulation

flows.

FlashBak™ Capability

The LatticeXP2 FPGA family offers FlashBak capability, which is a way to store the data in the EBRs to the Flash

memory upon user command. This protects the user’s data from being lost when the system is powered off. The

FlashBak module (STFA primitive) has a single-command-two-operation process (see Figure 10-61). When the

FlashBak operation is initiated, an erase-UFM-Flash signal is enabled to erase the Flash, followed by the transfer-

to-flash operation. Once the transfer is done, the Flash controller sends a transfer-done signal back to the user

logic. During the FlashBak operation, the EBRs are not accessible. There is no difference between the regular EBR

RAM configuration and the shadow Flash (UFM) EBR RAM configuration in the ispLEVER GUI. The presence of

the STFA (FlashBak) primitive in a design determines the EBR RAM configuration. FlashBak cannot be used if the

soft-error detect (SED) is operating in an Always mode. Since there is no addressing but just a ‘dump’ of all EBR to

Flash, only one STFA module is necessary. Multiple modules are not necessary or allowed.

Figure 10-61. FlashBak Primitive

Figure 10-62. FlashBak Waveform

Table 10-22. STFA Port Descriptions

Technical Support Assistance

Hotline: 1-800-LATTICE (North America)

+1-503-268-8001 (Outside North America)

e-mail: techsupport@latticesemi.com

Internet: www.latticesemi.com

Port Name Corresponding

Hardware Port Name I/O Description

STOREN storecmdn I Initiates to store the EBR content to Flash

UFMFAIL ufm_fail O Store to Flash operation failed

UFMBUSYN fl_busyn O Tells the user whether the Flash is in the busy state or not

STOREN UFMFAIL

UFMBUSYN

STFA

STOREN

UFM BUSYN

1.85µs delay regardless of

whether STOREN is released

Minimum pulse width = 780ns

10-53

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Revision History

Date Version Change Summary

February 2007 01.0 Initial release.

July 2007 01.1 Added FlashBak Capability section.

November 2007 01.2 TAG memory added.

January 2008 01.3 Updated Read_Tag Commands Waveform diagram. Changed minimum

delay between the 3rd and 24th dummy clock from 3µs to 5µs.

February 2008 01.4 Updated FIFO_DC without Output Registers (Non-Pipelined) diagram.

March 2008 01.5 Added FlashBAK Waveform diagram.

June 2008 01.6 Removed Read-Before-Write sysMEM EBR mode.

Updated “First In First Out (FIFO, FIFO_DC) – EBR Based” section.

June 2008 01.7 Added TAG memory timing waveforms and instructions.

November 2008 01.8 Updated the following waveform figures: Generic Timing Diagram,

READ_ID Waveform, WRITE_EN Waveform, WRITE_DIS Waveform,

ERASE_TAT Waveform, PROGRAM_TAW Waveform, READ_TAG

Waveform, STATUS Waveform.

Updated Serial Data Input (SI) text section.

Updated Memory Modules text section.

July 2011 01.9 Added the setup and hold requirements for addresses to EBR-based

memories.

10-54

Lattice Semiconductor LatticeXP2 Memory Usage Guide

Appendix A. Attribute Definitions

DATA_WIDTH

Data width is associated with the RAM and FIFO elements. The DATA_WIDTH attribute will define the number of

bits in each word. It takes the values as defined in the RAM size tables in each memory module.

REGMODE

REGMODE or the Register mode attribute is used to enable pipelining in the memory. This attribute is associated

with the RAM and FIFO elements. The REGMODE attribute takes the NOREG or OUTREG mode parameter that

disables and enables the output pipeline registers.

RESETMODE

The RESETMODE attribute allows users to select the mode of reset in the memory. This attribute is associated

with the block RAM elements. RESETMODE takes two parameters: SYNC and ASYNC. SYNC means that the

memory reset is synchronized with the clock. ASYNC means that the memory reset is asynchronous to clock.

CSDECODE

CSDECODE or the Chip Select Decode attributes are associated to block RAM elements. CS, or Chip Select, is

the port available in the EBR primitive that is useful when memory requires multiple EBR blocks cascaded. The CS

signal forms the MSB for the address when multiple EBR blocks are cascaded. CS is a 3-bit bus, so it can cascade

eight memories easily. CSDECODE takes the following parameters: “000”, “001”, “010”, “011”, “100”, “101”, “110”,

and “111”. CSDECODE values determine the decoding value of CS[2:0]. CSDECODE_W is chip select decode for

write and CSDECODE_R is chip select decode for read for Pseudo Dual Port RAM. CSDECODE_A and

CSDECODE_B are used for true dual port RAM elements and refer to the A and B ports.

WRITEMODE

The WRITEMODE attribute is associated with the block RAM elements. It takes the NORMAL, WRITETHROUGH,

and READBEFOREWRITE mode parameters.

In NORMAL mode, the output data does not change or get updated, during the write operation. This mode is sup-

ported for all data widths.

In WRITETHROUGH mode, the output data is updated with the input data during the write cycle. This mode is sup-

ported for all data widths.

In READBEFOREWRITE mode, the output data port is updated with the existing data stored in the write address,

during a write cycle. This mode is supported for x9, x18 and x36 data widths.

WRITEMODE_A and WRITEMODE_B are used for dual port RAM elements and refer to the A and B ports in case

of a True Dual Port RAM.

For all modes (of the True Dual Port module), simultaneous read access from one port and write access from the

other port to the same memory address is not recommended. The read data may be unknown in this situation.

Also, simultaneous write access to the same address from both ports is not recommended. (When this occurs, the

data stored in the address becomes undetermined when one port tries to write a ‘H’ and the other tries to write a

‘L’).

It is recommended that the designer implements control logic to identify this situation if it occurs and either:

1. Implement status signals to flag the read data as possibly invalid, or

2. Implement control logic to prevent the simultaneous access from both ports.

GSR

GSR or the Global Set/ Reset attribute is used to enable or disable the global set/reset for RAM element.

www.latticesemi.com 11-1 tn1138_01.4

June 2010 Techn ical Note TN1138

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Introduction

LatticeXP2™ devices support Double Data Rate (DDR) and Single Data Rate (SDR) interfaces using the logic built

into the Programmable I/O (PIO). SDR applications capture data on one edge of a clock while the DDR interfaces

capture data on both the rising and falling edges of the clock, thus doubling performance. The LatticeXP2 I/Os also

have dedicated circuitry to support DDR and DDR2 SDRAM memory interfaces. This technical note details the use

of LatticeXP2 devices to implement both a high-speed generic DDR interface and DDR and DDR2 memory inter-

faces.

DDR and DDR2 SDRAM Interfaces Overview

A DDR SDRAM interface will transfer data at both the rising and falling edges of the clock. The DDR2 is the second

generation of the DDR SRDRAM memory.

The DDR and DDR2 SDRAM interfaces rely on the use of a data strobe signal, called DQS, for high-speed opera-

tion. The DDR SDRAM interface uses a single-ended DQS strobe signal, whereas the DDR2 interface uses a dif-

ferential DQS strobe. Figures 11-1 and 11-2 show typical DDR and DDR2 SDRAM interface signals. SDRAM

interfaces are typically implemented with eight DQ data bits per DQS. An x16 interface will use two DQS signals

and each DQS is associated with eight DQ bits. Both the DQ and DQS are bi-directional ports used to both read

and write to the memory.

When reading data from the external memory device, data coming into the device is edge-aligned with respect to

the DQS signal. This DQS strobe signal needs to be phase-shifted 90 degrees before FPGA logic can sample the

read data. When writing to a DDR/DDR2 SDRAM, the memory controller (FPGA) must shift the DQS by 90

degrees to center-align with the data signals (DQ). A clock signal is also provided to the memory. This clock is pro-

vided as a differential clock (CLKP and CLKN) to minimize duty cycle variations. The memory also uses these

clock signals to generate the DQS signal during a read via a DLL inside the memory. Figures 11-3 and 11-4 show

DQ and DQS timing relationships for read and write cycles. For other detailed timing requirements, please refer to

the DDR SDRAM JEDEC specification (JESD79C).

During read, the DQS signal is LOW for some duration after it comes out of tristate. This state is called Preamble.

The state when the DQS is LOW before it goes into Tristate is the Postamble state. This is the state after the last

valid data transition.

DDR SDRAM also requires a Data Mask (DM) signal to mask data bits during write cycles. Note that the ratio of

DQS to data bits is independent of the overall width of the memory. An 8-bit interface will have one strobe signal.

DDR SDRAM interfaces use the SSTL25 Class I/II I/O standards whereas the DDR2 SDRAM interface uses the

SSTL18 Class I/II I/O standards. The DDR2 SDRAM interface also supports differential DQS (DQS and DQS#).

LatticeXP2 High-Speed I/O Interface

11-2

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Figure 11-1. Typical DDR SDRAM Interface

Figure 11-2. Typical DDR2 SDRAM Interface

The following two figures show the DQ and DQS relationship for memory read and write interfaces.

Figure 11-3. DQ-DQS During READ

DDR Memory

FPGA

(DDR Memory Controller)

DQ<7:0>

DQS

ADDRESS

CONTROL

COMMAND

CLK/CLKN

ADDRESS

CONTROL

COMMAND

CLKP/CLKN

ADDRESS

CONTROL

COMMAND

DQ<7:0>

DQS

CLK/CLKN

DQS

DM DM

FPGA

(DDR Memory Controller)

DDR Memory

DQ<7:0>

DQS, DQS#

ADDRESS

CONTROL

COMMAND

CLK/CLKN

ADDRESS

CONTROL

COMMAND

CLKP/CLKN

ADDRESS

CONTROL

COMMAND

DQ<7:0>

DQS, DQS#

CLK/CLKN

DQS, DQS#

DM DM

DQS

(at PIN) Preamble Postamble

DQS PIN to

REG and 90

Degree

Phase Shift

(at PIN)

DQS

(at REG)

11-3

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Figure 11-4. DQ-DQS During WRITE

Implementing DDR Memory Interfaces with LatticeXP2 Devices

As described in the DDRSDRAM overview section, the DDR SDRAM interfaces rely primarily on the use of a data

strobe signal called DQS for high-speed operation. When reading data from the external memory device, data

coming into the LatticeXP2 device is edge-aligned with respect to the DQS signal. Therefore, the LatticeXP2 device

needs to shift the DQS (a 90-degree phase shift) before using it to sample the read data. When writing to a DDR

SDRAM, the memory controller from the LatticeXP2 device must generate a DQS signal that is center-aligned with

the DQ, the data signals. This is accomplished by ensuring the DQS strobe is 90 degrees ahead relative to DQ

data.

LatticeXP2 devices have dedicated DQS support circuitry for generating the appropriate phase shifting for DQS.

The DQS phase shift circuit uses a frequency reference DLL to generate delay control signals associated with each

of the dedicated DQS pins and is designed to compensate for process, voltage and temperature (PVT) variations.

The frequency reference is provided through one of the global clock pins.

The dedicated DDR support circuit is also designed to provide comfortable and consistent margins for data sam-

pling window.

This section describes how to implement the read and write sections of a DDR memory interface. It also provides

details of the DQ and DQS grouping rules associated with the LatticeXP2 devices.

DQS Grouping

Each DQS group generally consists of at least 10 I/Os (one DQS, eight DQ and one DM) to implement a complete

8-bit DDR memory interface. LatticeXP2 devices support DQS signals on all sides of the device. Each DQS signal

on the top and bottom halves of the device will span across 18 I/Os and on the left and right sides of the device will

span across 16 I/Os. Any 10 of these I/Os spanned by the DQS can be used to implement an 8-bit DDR memory

interface. In addition to the DQS grouping, the user must also assign one reference voltage VREF1 for a given I/O

bank.

Figure 11-5. DQ-DQS Grouping

DQS

(at PIN)

DQS PAD

n* I/O PADS

(Ninth I/O Pad)

DQ or DM DQ or DM

*n=18 on bottom banks and n=16 on the left and right side banks.

11-4

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Figure 11-5 shows a typical DQ-DQS group for LatticeXP2 devices. The ninth I/O of this group of 16 or 18 I/Os is

the dedicated DQS pin. The 8 pads before of the DQS and 6/9 (6 for left and right side and 9 for top and bottom

side) pads after the DQS are covered by the DQS bus span. Users can assign any eight of these I/O pads to be DQ

data pins. Hence, to implement a 32-bit wide memory interface you would need to use four such DQ-DQS groups.

When not interfacing with the memory, the dedicated DQS pin can be used as a general purpose I/O. Each of the

dedicated DQS pin is internally connected to the DQS phase shift circuitry. The pinout information contained in the

LatticeXP2 Family Data Sheet shows pin locations for the DQS pads.

DDR Software Primitives

This section describes the software primitives that can be used to implement DDR interfaces. These primitives

include:

•DQSDLL – The DQS delay calibration DLL

•DQSBUFC – The DQS delay function and the clock polarity selection logic

•IDDRMX1A – The DDR input and DQS to system clock transfer registers with half clock cycle transfer

•IDDRMFX1A – The DDR input and DQS to system clock transfer registers with full clock cycle transfer

•ODDRMXA – The DDR output registers

HDL usage examples for each of these primitives are listed in Appendices A and B.

DQSDLL

The DQSDLL generates a 90-degree phase shift required for the DQS signal. This primitive implements the on-

chip DQSDLL. Only one DQSDLL should be instantiated for all the DDR implementations on one half of the device.

The clock input to this DLL should be at the same frequency as the DDR interface. The DLL generates the delay

based on this clock frequency and the update control input to this block. The DLL updates the dynamic delay con-

trol to the DQS delay block when this update control (UDDCNTL) input is asserted. Figure 11-6 shows the primitive

symbol. The active low signal on UDDCNTL updates the DQS phase alignment and should be initiated at the

beginning of READ cycles.

Figure 11-6. DQSDLL Symbol

Table 11-1 provides a description of the ports.

Table 11-1. DQSDLL Ports

DQSDLL Update Control: The DQS Delay can be updated for PVT variation using the UDDCNTL input. The

DQSDEL is updated when the when the UDDCNTL is held LOW. The DQSDEL can be updated when variations

are expected. DQSDEL can be updated anytime, except when the memory controller is receiving data from the

memory.

Port Name I/O Description

CLK I System CLK should be at the frequency of the DDR interface from the FPGA core.

RST I Resets the DQSDLL

UDDCNTL I Provides update signal to the DLL that will update the dynamic delay.

LOCK O Indicates when the DLL is in phase.

DQSDEL O The digital delay generated by the DLL, should be connected to the DQSBUF primitive.

CLK

RST

UDDCNTL

LOCK

DQSDEL

DQSDLL

11-5

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

DQSDLL Configuration: By default, this DLL will generate a 90-degree phase shift for the DQS strobe based on

the frequency of the input reference clock to the DLL. The user can control the sensitivity to jitter by using the

LOCK_SENSITIVITY attribute. This configuration bit can be programmed to be either “HIGH” or “LOW”.

The DLL Lock Detect circuit has two modes of operation controlled by the LOCK_SENSITIVITY bit, which selects

more or less sensitivity to jitter. If this DLL is operated at or above 150 MHz, it is recommended that the

LOCK_SENSITIVITY bit be programmed “HIGH” (more sensitive). When running at or below 100 MHz, it is recom-

mended that the bit be programmed “LOW” (more tolerant). For 133 MHz, the LOCK_SENSITIVITY bit can go

either way.

DQSBUFC

This primitive implements the DQS delay and the DQS transition detector logic. Figure 11-7 shows the primitive

symbol.

Figure 11-7. DQSBUFC Symbol

The DQSBUFC is composed of the DQS Delay, the DQS Transition Detect and the DQSXFER block as shown in

Figure 11-8. This block inputs the DQS and delays it by 90 degrees. It also generates the DDR Clock Polarity and

the DQSXFER signal. The preamble detect (PRMBDET) signal is generated from the DQSI input using a voltage

divider circuit.

DQSI DQSO

DQSBUFC

CLK

READ

DDRCLKPOL

DQSC

PRMBDET

DQSDEL

XCLK DQSXFER

DATAVALID

11-6

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Figure 11-8. DQSBUFC Function

DQS Delay Block: The DQS Delay block receives the digital control delay line (DQSDEL) coming from one of the

two DQSDLL blocks. These control signals are used to delay the DQSI by 90 degrees. DQSO is the delayed DQS

and is connected to the clock input of the first set of DDR registers.

DQS Transition Detect: The DQS Transition Detect block generates the DDR Clock Polarity signal based on the

phase of the FPGA clock at the first DQS transition. The DDR READ control signal and FPGA CLK inputs to this

coming and should be coming from the FPGA core.

DQSXFER: This block generates the 90-degree phase shifted clock to for the DDR Write interface. The input to this

block is the XCLK. The user can choose to connect this either to the edge clock or the FPGA clocks. The

DQSXFER is routed using the DQSXFER tree to all the I/Os spanned by that DQS.

Data Valid Module: The data valid module generates a DATAVALID signal. This signal indicates to the FPGA that

valid data is transmitted out of the input DDR registers to the FPGA core.

Table 11-2 provides a description of the I/O ports associated with the DQSBUFC primitive.

DQS

DELAY

DQS

TRANSITION

DETECT

PRMBDET

DQSI

DQSO

-Vref- DV*

*DV ~ 170mV for DDR1 (SSTL25 signaling)

*DV ~ 120mV for DDR2 (SSTL18 signaling)

READ

FPGA CLK

DQSDEL

Vref

DDRCLKPOL

DQSC

PRMBDET

DQSXFER

XCLK DQSXFER

DATA VALID

MODULE DATAVALID

11-7

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Table 11-2. DQSBUFC Ports

READ Pulse Generation

The READ signal to the DQSBUFC block is internally generated in the FPGA core. The READ signal goes high

when the READ command to control the DDR-SDRAM is initially asserted. This precedes the DQS preamble by

one cycle, yet may overlap the trailing bits of a prior read cycle. The DQS Detect circuitry of the LatticeXP2 device

requires the falling edge of the READ signal to be placed within the preamble stage.

The preamble state of the DQS can be detected using the CAS latency and the round trip delay for the signals

between the FPGA and the memory device. Note that the internal FPGA core generates the READ pulse. The rise

of the READ pulse should coincide with the initial READ command of the Read Burst and need to go low before the

Preamble goes high.

Figure 11-9 shows a READ Pulse timing example with respect to the PRMBDET signal.

Figure 11-9. READ Pulse Generation

Port Name I/O Description

DQSI I DQS Strobe signal from memory

CLK I System CLK

READ I Read generated from the FPGA core

DQSDEL I DQS Delay from the DQSDLL primitive

XCLK I Edge Clock or System CLK

DQSO O Delayed DQS Strobe signal, to the input capture register block

DQSC O DQS Strobe signal before delay, going to the FPGA core logic

DDRCLKPOL O DDR Clock Polarity signal

PRMBDET O Preamble detect signal, going to the FPGA core logic

DQSXFER O 90 degree shifted clock going to the Output DDR register Block

DATAVALID O Signal indicating transmission of Valid data to the FPGA core

READ

DQS

PRMBDET

FIRST DQS

TRANSITION

PREAMBLE

PRIOR READ CYCLE

POSTAMBLE

READ

FAIL

READ

FAIL

VTH

READ

11-8

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

IDDRMX1A

This primitive will implement the input register block in memory mode. The DDR registers are designed to use edge

clock routing on the I/O side and the primary clock on the FPGA side. The ECLK input is used to connect to the

DQS strobe coming from the DQS delay block (DQSBUFC primitive). The SCLK input is connected to the system

(FPGA) clock. DDRCLKPOL is an input from the DQS Clock Polarity tree. This signal is generated by the DQS

Transition detect circuit in the hardware. The DDRCLKPOL signal is used to choose the polarity of the SCLK to the

synchronization registers.

Figure 11-10. IDDRMX1A Symbol

Table 11-3 provides a description of all I/O ports associated with the IDDRMX1A primitive.

Table 11-3. IDDRMX1A Ports

Figure 11-11 shows the Input Register Block configured in the IDDRMX1A mode.

Port Name I/O Definition

D I DDR Data

ECLK I The phase shifted DQS should be connected to this input

RST I Reset

SCLK I System CLK

CE I Clock enable

DDRCLKPOL I DDR clock polarity signal

QA O Data at Positive edge of the CLK

QB O Data at the negative edge of the CLK

Note: The DDRCLKPOL input to IDDRMX1A should be connected to the DDRCLKPOL output of

DQSBUFC.

IDDRMX1A

ECLK

RST

SCLK

DDRCLKPOL

11-9

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Figure 11-11. Input Register Block in IDDRMX1A Mode

Figure 11-12 shows the IDDRMX1A timing waveform.

DATA

IDDRMX1A

DDR Registers Synchronization

Registers

ECLK

SCLK

DDRCLKPOL

11-10

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Figure 11-12. IDDRMX1A Waveform

IDDRMFX1A

With the IDDRMX1A, the data can enter the FPGA at either the positive or negative edge of the SCLK depending

on the state of the DDRCLKPOL signal. The IDDRMFX1A module includes an additional clock transfer stage that

ensures that the data is transferred at a known edge of the system clock.

Figure 11-13. IDDRMFX1A Symbol

Table 11-4 provides a description of all I/O ports associated with the IDDRMFX1A primitive.

DQS at I/O

DDR DATA at I/O

ECLK( DQS shifted 90 deg)

P0 N0 P1 N1 N2P2 P3 N3 P4

P0 N0 P1 N1 P2 N2 P3 N3 P4

N0 N1 N2 N3

P0 P1 P2 P3

DDR DATA at IDDRMX1A

P0 P1 P2 P3 P4

P0 P1 P2 P3XX

SCLK

Case 1: DDRCLKPOL = 0

Case 2: DDRCLKPOL = 1

QB N0 N1 N2 N3XX

N0 N1 N2 N3XXQB

IDDRMFX1A

ECLK

RST

CLK1

DDRCLKPOL

CLK2

11-11

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Table 11-4. IDDRMFX1A Ports

Figure 11-14 shows the LatticeXP2 Input Register Block configured to function in the IDDRXMFX1A mode.

The DDR registers are designed to use Edge clock routing on the I/O side and the primary clock on the FPGA side.

The ECLK input is used to connect to the DQS strobe coming from the DQS delay block (DQSBUFC primitive). The

CLK1 and CLK2 inputs should be connected to the slow system (FPGA) clock. DDRCLKPOL is an input from the

DQS Clock Polarity tree. This signal is generated by the DQS Transition detect circuit in the hardware. The addi-

tional clock transfer registers are shared with the output register block.

Figure 11-14. Input Register Block in IDDRMFX1A Mode

Figure 11-15 shows the IDDRMFX1A timing waveform.

Port Name I/O Description

D I DDR Data

ECLK I The phase shifted DQS should be connected to this input

RST I Reset

CLK1 I Slow FPGA CLK

CLK2 I Slow FPGA CLK

CE I Clock enable

DDRCLKPOL I DDR clock polarity signal

QA O Data at the positive edge of the CLK

QB O Data at the negative edge of the CLK

Note: The DDRCLKPOL input to IDDRMFX1A should be connected to the DDRCLKPOL output of DQSBUFC.

DATA

IDDRMFX1A

DDR Registers Synchronization

Registers

Clock Transfer

Registers

ECLK

CLK2

CLK1

DDRCLKPOL

11-12

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Figure 11-15. IDDRMFX1A Waveform

ODDRMXA

The ODDRMXA primitive implements the output register for both the write and the tristate functions. This primitive

is used to output DDR data and the DQS strobe to the memory. All the DDR output tristate functions are also imple-

mented using this primitive.

Figure 11-16 shows the ODDRMXA primitive symbol and its I/O ports.

Figure 11-16. ODDRMXA Symbol

Table 11-5 provides a description of all I/O ports associated with the ODDRMXA primitive.

DQS at I/O

DDR DATA at I/O

ECLK( DQS shifted 90 deg)

P0 N0 P1 N1 N2P2 P3 N3 P4

P0 N0 P1 N1 P2 N2 P3 N3 P4

N0 N1 N2 N3

P0/N0 P1/N1 P2/N2 P3/N3

DDR DATA at IDDRMFX1A

D/E

P0 P1 P2 P3 P4

CLK2

P0 P1 P2 P3XX

N0 N1 N2 N3XX

P0/N0 P1/N1 P2/N2 P3/N3XX

D/E

CLK1

Case 1: DDRCLKPOL = 0

Case 2: DDRCLKPOL = 1

ODDRMXA

CLK

RST

DQSXFER

11-13

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Table 11-5. ODDRMXA Ports

Figure 11-17 shows the LatticeXP2 Output Register Block configured in the ODDRXMA mode.

Figure 11-17. Output Register Block in ODDRXMA Mode

Figure 11-18 shows the ODDRMXA timing waveform.

Port Name I/O Description

CLK I System CLK or ECLK

DA I Data at the negative edge of the clock

DB I Data at the positive edge of the clock

RST I Reset

DQSXFER I 90-degree phase shifted clock coming from the DQSBUFC block

Q I DDR data to the memory

Notes:

1. RST should be held low during DDR Write operation.

2. DDR output and tristate registers do not have CE support. RST is available for the tristate DDRX mode (while read-

ing). The LSR will default to set when used in the tristate mode.

3. When asserting reset during DDR writes, it is important to keep in mind that this only resets the flip-flops and not

the latches.

ODDRXMA

ECLK

B0 C0

DQSXFER

11-14

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Figure 11-18. ODDRMXA Waveform

Note that the DQSXFER is inverted inside the ODDRXMA. This will cause the data coming out of the ODDRXMA

to be -90° in phase with the output of the ODDRXC module.

Memory Read Implementation

LatticeXP2 devices contain a variety of features to simplify implementation of the read portion of a DDR interface:

• DLL compensated DQS delay elements

• DDR input registers

• Automatic DQS to system clock domain transfer circuitry

• Data Valid Module

DLL Compensated DQS Delay Elements

The DQS from the memory is connected to the DQS Delay element. The DQS Delay block receives a 6-bit delay

control from the on-chip DQSDLL. The LatticeXP2 devices support two DQSDLL, one on the left and one on the

right side of the device. The DQSDEL generated by the DQSDLL on the left side is routed to all the DQS blocks on

the left and bottom/top half of the device. The delay generated by the DQSDLL on the right side is distributed to all

the DQS Delay blocks on the right side and the other bottom/top half of the device. These digital delay control sig-

nals are used to delay the DQS from the memory by 90 degrees.

The DQS received from the memory is delayed in each of the DQS Delay blocks and this delay DQS is used to

clock the first set stage DDR input registers.

DQS Transition Detect or Automatic Clock Polarity Select

In a typical DDR memory interface design, the phase relation between the incoming delayed DQS strobe and the

internal system clock (during the READ cycle) is unknown. Prior to the READ operation in DDR memories, DQS is

in tristate (pulled by termination). Coming out of tristate, the DDR memory device drives DQS low in the Preamble

State. The DQS Transition Detect block detects the first DQS rising edge after the Preamble transition and gener-

ates a signal indicating the required polarity for the FPGA system clock (DDRCLKPOL). This signal is used to con-

trol the polarity of the clock to the synchronizing registers.

ECLK

Reg A0

Reg B0

P0 P1 P2 P3 P4

Latch C0

P0 P1 P2 P3 P4

N0 N1 N2 N3

XX N4

N0 N1 N2 N3

XX N4

N0 N1 N2

P0 N0 P1 N1 P2 N2 P3

XX N3 P4

DQSXFER

11-15

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Data Valid Module

The data valid module generates a DATAVALID signal. This signal indicates to the FPGA that valid data is transmit-

ted out the input DDR registers to the FPGA core.

DDR I/O Register Implementation

The first set of DDR registers is used to de-mux the DDR data at the positive and negative edge of the phase

shifted DQS signal. The register that captures the positive-edge data is followed by a negative-edge triggered reg-

ister. This register transfers the positive edge data from the first register to the negative edge of DQS so that both

the positive and negative portions of the data are now aligned to the negative edge of DQS.

The second stage of registers is clocked by the FPGA clock, the polarity of this clock is selected by the DDR Clock

Polarity signal generated by the DQS Transition Detect Block.

The I/O Logic registers can be implemented in two modes:

• Half Clock Transfer Mode

• Full Clock Transfer Mode

In Half Clock Transfer mode the data is transferred to the FPGA core after the second stage of the register. In Full

Clock Transfer mode, an additional stage of I/O registers clocked by the FPGA clock is used to transfer the data to

the FPGA core.

The LatticeXP2 Family Data Sheet explains each of these circuit elements in more detail.

Memory Read Implementation in Software

Three primitives in the ispLEVER® design tools represent the capability of these three elements. The DQSDLL rep-

resents the DLL used for calibration. The IDDRMX1A/IDDRMFX1A primitive represents the DDR input registers

and clock domain transfer registers with or without full clock transfer. Finally, the DQSBUFC represents the DQS

delay block, the clock polarity control logic and the Data Valid module. Figures 11-19 and 11-20 show the READ

interface block generated using the IPexpress™ tool in the ispLEVER software.

Figure 11-19. Software Primitive Implementation for Memory READ (Half Clo c k Transfer)

DDRCLKPOL

dqs

lock

DQSDLL

DQSI

CLK

READ

DQSDEL

DQSO

SCLK

ECLK

DDRCLKPOL

RST

UDDCNTL

DQSDEL

datain_p

datain_n

DQSC

PRMBDET

LOCK

DQSBUFC

IDDRMX1A

dqsc

prmbdet

XCLK

DQSXFER

DATAVALID

dqsxfer

datavalid

reset

clk

uddcntl

read

xclk

11-16

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Figure 11-20. Software Primitive Implementation for Memory READ (Full Clock Transfer)

Read Timing Waveforms

Figures 11-21 and 11-22 show READ data transfer for half and full clock cycle data transfer based on the results of

the DQS Transition detector logic. This circuitry decides whether or not to invert the phase of FPGA system CLK to

the synchronization registers based on the relative phases of PRMBDET and CLK.

•Case 1: If the FPGA clock is low on the first PRMBDET transition, then DDRCLKPOL is low and no inversion is

required.

•Case 2: If the FPGA clock is high on the first PRMBDET, then DDRCLKPOL is high and the FPGA clock (CLK)

needs to be inverted before it is used for synchronization.

Figure 11-21 illustrates the DDR data timing using half clock transfer mode at different stages of the IDDRMX1A

registers. The first stage of the register captures data on the positive edge as shown by signal A and the negative

edge as shown by signal B. Data stream A goes through an additional half clock cycle transfer shown by signal C.

Phase-aligned data streams B and C are presented to the next stage registers clocked by the FPGA clock.

Figure 11-22 illustrates the DDR data timing using full clock transfer mode at different stages of IDDRMFX1A regis-

ters. In addition to the first two register stages in the half clock mode, the full clock transfer mode has an additional

stage register clocked by the FPGA clock. In this case, D and E are the data streams after the second register

stage presented to the final stage of registers clocked by the FPGA clock.

DDRCLKPOL

dqs

lock

DQSDLL

DQSI

CLK

READ

DQSDEL

DQSO

CLK2

ECLK

DDRCLKPOL

RST

UDDCNTL

DQSDEL

datain_p

datain_n

DQSC

PRMBDET

LOCK

DQSBUFC

IDDRMFX1A

dqsc

prmbdet

XCLK

DQSXFER

DATAVALID

dqsxfer

datavalid

CLK1

reset

clk

uddcntl

read

xclk

11-17

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Figure 11-21. READ Data Transfer When Using IDDR MX1A

Notes:

1. DDR memory sends DQ aligned to DQS Strobe.

2. The DQS Strobe is delayed by 90 degrees using the dedicated DQS logic.

3. DQ is now center aligned to DQS Strobe.

4. PRMBDET is the Preamble detect signal generated using the DQSBUFB primitive. This is used to generate the DDRCLKPOL signal.

5. The first set of I/O registers, A and B, capture data on the positive and negative edges of DQS.

6. I/O Register C transfers data so that both data are now aligned to negative edge of DQS.

7. DDCLKPOL signal generated will determine if the FPGA CLK going into the synchronization registers need to be inverted. The DDRCLK-

POL=0 when the FPGA CLK is LOW at the first rising edge of PRMBDET. The clock to the synchronization registers is not inverted. The

DDRCLKPOL=1 when the FPGA CLK is HIGH at the first rising edge of PRMBDET. In this case the clock to the synchronization register is

inverted.

8. The I/O synchronization registers capture data on either the rising or falling edge of the FPGA clock.

9. The DATAVALID signal goes HIGH when valid data enters the FPGA core. Once DATA VALID is asserted, it stays high until the next READ

pulse.

DDRCLKPOL= 0

DQS at PIN

DQ at PIN

DQS at IOL

FPGA CLK

PRMBDET

CLK TO SYNC

IO REGISTERS

P0 N0 N1 P1

P0 N0 P1 N1

P0 P1

N0 N1

P0 P1

DQ at IOL

FPGA CLK

DDRCLKPOL=1

CLK TO SYNC

IO REGISTERS

DATAVALID

11-18

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Figure 11-22. Read Data Transfer When Using IDDRMFX1A

Notes:

1. DDR memory sends DQ aligned to DQS Strobe.

2. The DQS Strobe is delayed by 90 degrees using the dedicated DQS logic.

3. DQ is now center-aligned to DQS Strobe.

4. PRMBDET is the Preamble detect signal generated using the DQSBUFB primitive. This is used to generate the DDRCLKPOL signal.

5. The first set of I/O registers, A and B, capture data on the positive and negative edges of DQS.

6. I/O register C transfers data so that both data are now aligned to the negative edge of DQS.

7. DDCLKPOL signal generated will determine if the FPGA clock going into the synchronization registers need to be inverted. The DDRCLK-

POL=0 when the FPGA CLK is LOW at the first rising edge of PRMBDET. So the clock to the synchronization registers is not inverted. The

DDRCLKPOL=1 when the FPGA CLK is HIGH at the first rising edge of PRMBDET. In this case the clock to the synchronization register is

inverted.

8. Registers D and E capture data at the FPGA clock.

9. The data is then again registers at the FPGA clock to ensure a Full Clock Cycle transfer.

10.DATAVALID signal goes HIGH when valid data enters the FPGA core. Once DATA VALID is asserted, it stays high until the next READ pulse.

DQS at PIN

DQ at PIN

DQS at IOL

FPGA CLK

(Case 1)

DDRCLKPOL= 0

PRMBDET

CLK TO SYNC

IO REGISTERS

P0 N0 N1P1

P0 N0 P1 N1

DQ at IOL

FPGA CLK

(Case 2)

DDRCLKPOL=1

CLK TO SYNC

IO REGISTERS

N0 N1

P1P0 P2

N0 N1 N2

P1P0

N0 N1

P0 P2

N0 N1 N2

P0 P2

P2 N2

DATAVALID

11-19

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Data Read Critical Path

Data in the second stage DDR registers can be registered either on the positive edge or on the falling edge of

FPGA clock depending on the DDRCLKPOL signal. In order to ensure that the data transferred to the FPGA core

registers is aligned to the rising edge of the system clock, this path should be constrained with a half clock transfer.

This half clock transfer can be forced in the software by assigning a multi-cycle constraint (multi-cycle of 0.5 X) on

all the data paths to first PFU register.

DQS Postamble

At the end of a READ cycle, the DDR SDRAM device executes the READ cycle postamble and then immediately

tristates both the DQ and DQS output drivers. Since neither the memory controller (FPGA) nor the DDR SDRAM

device are driving DQ or DQS at that time, these signals float to a level determined by the off-chip termination

resistors. While these signals are floating, noise on the DQS strobe may be interpreted as a valid strobe signal by

the FPGA input buffer. This can cause the last READ data captured in the IOL input DDR registers to be overwrit-

ten before the data has been transferred to the free running resynchronization registers inside the FPGA.

Figure 11-23. Postamble Effect on READ

LatticeXP2 devices have extra dedicated logic in the in the DQS Delay Block that prevents this postamble problem.

The DQS postamble logic is automatically implemented when the user instantiates the DQS Delay logic (DQS-

BUFC software primitive) in the design.

Memory Write Implementation

To implement the write portion of a DDR memory interface, two streams of single data rate data must be multi-

plexed together with data transitioning on both edges of the clock. In addition, during a write cycle, DQS must arrive

at the memory pins center-aligned with the data, DQ. Along with the DQS strobe and data this portion of the inter-

face must also provide the CLKP, CLKN Address/Command and Data Mask (DM) signals to the memory.

It is the responsibility of the FPGA output control to edge-align the DDR output signals (ADDR,CMD, DQS, but not

DQ, DM) to the rising edge of the outgoing differential clock (CLKP/CLKN).

Challenges encountered by the during Memory WRITE:

1. DQS needs to be center-aligned with the outgoing DDR Data, DQ.

2. Differential CLK signals (CLKP and CLKN) need to be generated.

P0 P1

DQ at IOL

DQS at PIN

DQ at PIN

DQS at IOL

P0 N0 N1P1

CLK at

synce reg

DATAIN_P

DATAIN_N

11-20

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

3. The controller must meet the DDR interface specification for tDSS and tDSH parameters, defined as DQS

falling to CLKP rising setup and hold times.

4. The DDR output data must be muxed from two SDR streams into a single outgoing DDR data stream.

All DDR output signals (“ADDR, CMD”, DQS, DQ, DM) are initially aligned to the rising edge of the FPGA clock

inside the FPGA core. The relative phase of the signals may be adjusted in the IOL logic before departing the

FPGA. These adjustments are shown in Figure 11-24.

LatticeXP2 devices contain DDR output and tri-state registers along with the DQSXFER signal generated by the

DQSBUFC that allows easy implementation of the write portion of the DDR memory interfaces. The DDR output

registers can be accessed in the design tools via the ODDRMXA and the ODDRXC primitives.

The DQS signal and the DDR clock outputs are generated using the ODDRXC primitive. As shown in the figure, the

CLKP and DQS signals are generated so that they are 180 degrees in phase with the clock. This is done by con-

necting “1” to the DA input and “0” to the DB inputs of the ODDRXC primitive. Refer to the DDR Generic Software

Primitive section of this document to see the ODDRXC timing waveforms.

The DDR clock output is then fed into a SSTL differential output buffer to generate CLKP and CLKN differential

clocks. Generating the CLKN in this manner prevents any skew between the two signals. When interfacing to

DDR1, SDRAM memory CLKP should be connected to the SSTL25D I/O standard. When interfacing to DDR2

memory, it should be connected to the SSTL18D I/O standard.

The DQSXFER output from the DQSBUFC block is the 90-degree phase shifted clock. This 90-degree phase

shifted clock is used as an input to the ODDRMXA block. The ODDRMXA is used to generate the DQ and DM data

outputs going to the memory. In the ODDRMXA module, the data is first registered using the ECLK or FPGA clock

input and then shifted out using the DQSXFER signal. To ensure that the data going to the memory is center-

aligned to the DQS, the DQSXFER is inverted inside the ODDRXMA primitive. This will generate data that is cen-

ter-aligned to the DQS. Refer to the Software Primitives section of this document for the ODDRXMA timing wave-

forms.

The DDR interface specification for tDSS and tDSH parameters defined as DQS falling to CLKP rising setup and hold

times must be met. This is accomplished by ensuring that the CLKP and DQS signals are identical in phase.

The tristate control for the DQS and DQ outputs can also be implemented using the ODDRXC primitive.

Figure 11-24 shows the DDR Write implementation using the DDR primitives.

11-21

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Figure 11-24. Software Implementation for Memory Write

CLK Q

“1”

“0”

“1”

“0”

dqstri_p

CLKP (CLK+180)

ODDRXC

ODDRMXA

DQSXFER (clk+90)

ECLK / FPGA Clock

DQS (CLK+180)

DQ (CLK+270)

DM (CLK+270)

CLKN (CLK)

dqstri_n

datatri_p

datatri_n

dataout_p

dataout_n

dmout_p

dmout_n

RST

CLK

RST

CLK

RST

CLK

RST

DQSXFER

CLK

RST

DQSXFER

CLK

RST

DQSXFER

11-22

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Write Ti ming Waveforms

Figure 11-25 shows the DDR write side data transfer timing for the DQ Data pad and the DQS Strobe Pad. When

writing to the DDR memory device, the DM (Data Mask) and the ADDR/ CMD (Address and Command) signals are

also sent to the memory device along with the data and strobe signals.

Figure 11-25. DDR Write Data Transfer for DQ Data

Design Rules/Guidelines

Listed below are some rules and guidelines to keep in mind when implementing DDR memory interfaces in the

LatticeXP2 devices.

• The LatticeXP2 devices have dedicated DQ-DQS banks. Please refer to the logical signal connections of the

groups in the LatticeXP2 Family Data Sheet before locking these pins.

• There are two DQSDLL on the device, one for the left half and one for the right half of the device. Therefore, only

one DQSDLL primitive should be instantiated for each half of the device. Since there is only one DQSDLL on

each half of the device, all the DDR memory interfaces on that half of the device should run at the same fre-

quency. Each of the DQSDLL will generate 90-degree digital delay bits for all the DQS delay blocks on that half of

the device based on the reference clock input to the DLL.

• When implementing a DDR SDRAM interface, all interface signals should be connected to the SSTL25 I/O stan-

dard. In the case of the DDR2 SDRAM interface, the interface signal should be connected to SSTL18 I/O stan-

dard.

• For DDR2, the differential DQS signals need to be connected to SSTL18 the Differential I/O standard.

• When implementing the DDR interface, the VREF1 of the bank is used to provide the reference voltage for the

interface pins.

Generic High Speed DDR Implementation

In addition to the DDR memory interface, the I/O logic DDR registers can be used to implement high speed DDR

interfaces. The Input DDR registers can operate in full clock transfer and half clock transfer modes. The DDR input

and output register also support x1 and x2 gearing ratios. A gearing capability is provided to Mux/DeMux the I/O

data rate (ECLK) to the FPGA clock rate (SCLK). For DDR interfaces, this ratio is slightly different than the SDR

ratio. A basic 2x DDR element provides four FPGA side bits for two I/O side bits at half the clock rate on the FPGA

side.

P0 N0 P1 N1 P2 N2 P3XX N3 P4

ECLK

P0 P1 P2 P3 P4

N0 N1 N2 N3 N4 ..

DQS

CLKP

CLKN

DQSXFER

DQ ..

11-23

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

The data going to the DDR registers can be optionally delayed before going to the DDR register block.

Generic DDR Software Primitives

The IPexpress tool in the ispLEVER software can be used to generate the DDR modules. The various DDR modes

described below can be configured in the IPexpress tool. The various modes are implemented using the following

software primitives.

• IDDRXC – DDR Generic Input

• IDDRFXA – DDR Generic Input with full clock transfer (x1 gearbox)

• IDDRX2B – DDR Generic Input with 2x gearing ratio. DDRX2 inputs a double data rate signal as four data

streams. Two stages of DDR registers are used to convert serial DDR data at input pad into four SDR data

streams entering FPGA core logic.

• ODDRXC – DDR Generic Output

• ODDRX2B – DDR Generic Output with 2x gearing ratio. The DDRX2 inputs four separate data streams and out-

puts a single data stream to the I/O buffer.

• DELAYB – The DDR input can be optionally delayed before it is input to the DDR registers. The user can choose

to implement a fixed delay value or use a dynamic delay.

IDDRXC

This primitive inputs DDR data at both edges of the CLK and generates two streams of data. The CLK to this mod-

ule can be connected to either the edge clock or the primary FPGA clock.

Figure 11-26 shows the primitive symbol for IDDRXC mode.

Figure 11-26. IDDRXC Symbol

Table 11-6 lists the port names and descriptions for the IDDRXC primitive.

Table 11-6. IDDRXC Port Names

Figure 11-27 shows the LatticeXP2 Input Register Block configured in the IDDRXFC mode.

Port Name I/O Definition

D I DDR data

CLK I This clock can be connected to the ECLK or the FPGA clock

CE I Clock enable signal

RST I Reset to the DDR register

QA O Data at the positive edge of the clock

QB O Data at the negative edge of the clock

CLK

RST

IDDRXC

11-24

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Figure 11-27. Input Register Block Configured as IDDRXC

Figure 11-28 shows the timing waveform when using the IDDRXC module.

Figure 11-28. IDDRXC Waveform

IDDRFXA

This primitive inputs DDR data at both edges of clock CLK1 and generates two streams of data aligned to clock

CLK2. CLK1 can be connected either to the edge clock or the internal FPGA clock. If the Edge clock input is used

for CLK1 then CLK2 should be generated from the same clock going to CLK1.

DATA

IDDRXC

FPGA ClockEdge Clock

DDR Registers Synchronization

Registers

CLK

CLK at I/O

DDR DATA at I/O

CLK at IDDRXC

P0 N0 P1 N1 N2P2 P3 N3 P4

P0 N0 P1 N1 P2 N2 P3 N3 P4

N0 N1 N2 N3

P0 P1 P2 P3

DDR DATA at IDDRXC

P0 P1 P2 P3 P4

N0 N1 N2 N3XX

11-25

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Figure 11-29. IDDRFXA Symbol

Table 11-7 lists the port names and descriptions for the IDDRFXA primitive.

Table 11-7. IDDRFXA Port Names

Figure 11-31 shows the LatticeXP2 Input Register Block configured in the IDDRXFXA mode. CLK1 used to register

the DDR registers and the first set of synchronization registers. CLK2 is used by the third stage of registers and

should be clocked by the FPGA clock. These clock transfer registers are shared with the output register block.

Figure 11-30. Input Register Block configured as IDDRFXA

Figure 11-31 shows the timing waveform when using the IDDRFXA module.

Port Name I/O Description

D I DDR data

CLK1 I This clock can be connected to the ECLK or the FPGA clock

CLK2 I This clock should be connected to the FPGA clock

CE I Clock Enable signal

RST I Reset to the DDR register

QA O Data at the positive edge of the clock

QB O Data at the negative edge of the clock

CLK1

CLK2

RST

IDDRFXA

DATA

IDDRFXA

FPGA ClockEdge Clock

DDR Registers Synchronization

Registers

Clock Transfer

Registers

CLK1 CLK2

11-26

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Figure 11-31. IDDRFXA Waveform

CLK at I/O

DDR DATA at I/O

CLK1 (shifted 90 deg)

P0 N0 P1 N1 N2P2 P3 N3 P4

P0 N0 P1 N1 P2 N2 P3 N3 P4

N0 N1 N2 N3

P0/N0 P1/N1 P2/N2 P3/N3

DDR DATA at IDDRFXA

D/E

P0 P1 P2 P3 P4

P0 P1 P2 P3 P4XX

CLK2

P0 P1 P2 P3XX

N0 N1 N2 N3XX

11-27

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

IDDRX2B

This module is used when a gearing function is required. This primitive inputs the DDR data at both edges of the

edge clock and generates four streams of data aligned to SCLK. SCLK is always half the frequency of ECLK. It is

recommended that the CLKDIV module or PLL be used to generate the SCLK from the ECLK.

Figure 11-32 shows the primitive symbol for the IDDRX2B mode.

Figure 11-32. IDDRX2B Symbol

Table 11-8 lists the port names and descriptions for the IDDRX2B primitive.

Table 11-8. IDDRX2B Port Names

Figure 11-33 shows the LatticeXP2 Input Register Block configured in the IDDRX2B mode. The DDR registers and

the first set of synchronization registers are clocked by the ECLK input. The SCLK is used to clock the third stage

of register. This primitive will output four streams of data. The 2x gearing function is implemented by using the syn-

chronization registers of the complementary PIO. The clock transfer registers are shared with the output register

block.

Port Name I/O Description

D I DDR data

ECLK I This clock can be connected to the fast edge clock

SCLK I This clock should be connected to the FPGA clock

CE I Clock enable signal

RST I Reset to the DDR register

QA0, QA1 O Data at the positive edge of the clock

QB0, QB1 O Data at the negative edge of the clock

ECLK

SCLK

RST

QA0

QA1

QB0

QB1

IDDRX2B

11-28

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Figure 11-33. Input Register Block Configured as IDDRX2B

Figure 11-34 shows the timing waveform using the IDDRX2B module.

DATA

IDDRX2B

SCLKECLK

TRUE PIO in LVDS sysI/O Pair

COMP PIO in LVDS sysI/O Pair

QB1

QA1

QB0

QA0

DDR Registers Synchronization

Registers

Clock Transfer

Registers

Synchronization

Registers

Clock Transfer

Registers

11-29

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Figure 11-34. IDDRX2B Wavef orm

ODDRXC

This is the DDR output module. This primitive will input two data streams and mux them together to generate a sin-

gle stream of data going to the sysIO™ buffer. The CLK to this module can be connected to the edge clock or to the

FPGA clock. This primitive is also used for when DDR function is required for the tristate signal.

Figure 11-35 shows the primitive symbol for the ODDRXC mode.

Figure 11-35. ODDRXC Symbol

Table 11-9 lists the port names and descriptions for the ODDRXC primitive.

CLK at I/O

DDR DATA at I/O

ECLK (shifted 90 deg)

P0 N0 P1 N1 N2P2 P3 N3 P4

P0 N0 P1 N1 P2 N2 P3 N3 P4

N0 N1 N2 N3

P0/N0 P1/N1 P2/N2 P3/N3

P0/N0 P1/N1 P2/N2

DDR DATA at IDDRX2B

D/E

F/G XX

P0 P1 P2 P3 P4

SCLK

QB1

QA1

QB0

QB1

CLK

RST

ODDRXC

11-30

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Table 11-9. ODDRXC Port Names

Figure 11-36 shows the Output Register Block of the LatticeXP2 device configured in ODDRXC mode.

Figure 11-36. Output Register Block in ODDRC Mode

Figure 11-37 shows the timing waveform when using the ODDRXC module.

Figure 11-37. ODDRXC Waveform

ODDRX2B

This DDR output module can be used when a gearbox function is required. This primitive inputs four data streams

and muxes them together to generate a single stream of data going to the sysIO buffer.

Port Name I/O Definition

DA I Data at the negative edge of the clock

DB I Data at the positive edge of the clock

CLK I This clock can be connected to the edge clock or to the FPGA clock

RST I Reset signal

Q O DDR data output

ODDRXC

ECLK

B0 C0

ECLK

Reg A0

Reg B0

P0 P1 P2 P3 P4

Latch C0

P0 P1 P2 P3 P4

N0 N1 N2 N3XX N4

N0 N1 N2

P0 N0 P1 N1 P2 N2 P3

XX N3 P4

11-31

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

DDR registers of the complementary PIO are used in this mode. The complementary PIO register can no longer be

used to perform the DDR function. There are two clocks going to this primitive. The ECLK is connected to the faster

edge clock and the SCLK is connected to the slower FPGA clock. The DDR data output of this primitive is aligned

to the faster edge clock.

Figure 11-38 shows the primitive symbol for the ODDRX2B mode.

Figure 11-38. ODDRX2B Symbol

Table 11-10 lists the port names and descriptions for the ODDRX2B primitive.

Table 11-10. ODDRX2B Port Names

Figure 11-39 shows the LatticeXP2 Output Register Block in the ODDRX2B mode.

Port Name I/O Descriptio n

DA0, DB0 I Data at the negative edge of the clock

DA1, DB1 I Data at the positive edge of the clock

ECLK I This clock should be connected to the faster edge clock

SCLK I This clock should be connected to the slower FPGA clock

RST I Reset signal

Q O DDR data output

ECLK

SCLK

DA0

DA1

DB0

DB1

RST

ODDRX2B

11-32

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Figure 11-39. Output Register Block Configured in ODDRX2B Mode

Figure 11-40 shows the timing waveform when using the ODDRXC module.

DB0

DB1

TRUE PIO in LVDS sysI/O Pair

COMP PIO in LVDS sysI/O Pair

DA0

DA1

ODDRX2B

SCLK ECLK

B0 C0

B1 C1

E0 F0

11-33

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Figure 11-40. ODDRX2B Waveform

DELAYB

Data going to the DDR registers can be optionally delayed using the Delay block. The Delay block receives 4-bit

delay control. The 4-bit delay can be set using fixed multiplier values or it can be controlled by the user. The

DELAYB block is available for use with the input DDR registers.

The DELAYB block can be configured when generating the DDR input modules in the IPexpress tool of the soft-

ware. The delay can be adjusted in 35ps steps. Users can choose from three types of delay values:

1. Dynamic – The delay value is controlled by the user logic using the DEL[3:0] input of the DELAYB block.

SCLK

Reg A0

Reg B0

d1 d5 d9 d13 d17

Latch C0

d1 d5 d9 d13 d17

d3 d7 d11 d15

XX d19

d3 d7 d11 d15XX d19

d3 d7 d11

A ( Mux0)

d15

DB0

DB1

SCLK

Reg A1

Reg B1

d0 d4 d8 d12 d16

Latch C1

d0 d4 d8 d12 d16

d2 d6 d10 d14

XX d18

d2 d6 d10 d14XX d18

d2 d6 d10

B ( Mux1)

d14

d0 d2 d4 d6 d8 d10 d12 d14

DA0

DA1

d16

d1 d3 d5 d7 d9 d11 d13

XX d15 d17

d1 d3 d5 d7 d9 d11 d13

XX d15 d17

Copy of A

( Mux0)

d0 d2 d4 d6 d8 d10 d12 d14

d1 d3 d5 d7 d9 d11 d13

XX d15

d1 d3 d5 d7 d9 d11 d13 d15

Qd0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14

Latch F0

Reg E0

Reg D0

ECLK

11-34

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

2. Fixed – When choosing the fixed value, the user will also need to choose from one of the 16 multiplier val-

ues. This will tie the inputs DEL[3:0] of the DELAYB block to a fixed value depending on the multiplier value

chosen.

3. FIXED_XGMII – The DEL [3:0] will be configured with the delay value required when implementing a

XGMII interface.

Figure 11-41 shows the primitive symbol for the DELAYB mode.

Figure 11-41. DELAYB Symbol

Table 11-11 lists the port names and descriptions for the DELAYB primitive.

Table 11-11. DELAYB Port Names

Design Rules/Guidelines

Listed below are some rules and guidelines for implementing generic DDR interfaces in LatticeXP2 devices.

• When implementing a 2x gearing mode, the complement PIO registers are used. This complementary PIO regis-

ter can no longer be used and should not be connected.

DDR Usage in ispLEVER IPexpress

This section describes how IPexpress is used to generate the DDR modules in ispLEVER. If you are using Lattice

Diamond™ design software, refer to Appendix A for information on how DDR modules are generated in Diamond.

IPexpress can be used to configure and generate the DDR Memory Interface and Generic DDR Module. The tool

will generate an HDL module that will contain the DDR primitives. This module can be using in the top level design.

Figure 11-42 shows the main window of IPexpress. The DDR_Generic and DDR_MEM options under Architech-

ture->IO are used to configure the DDR modules.

Port Name I/O Definition

A I DDR input from the sysIO buffer

DEL (0:3) I Delay inputs

Z O Delay DDR data

DEL(0:3)

DELAYB

11-35

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Figure 11-42. IPexpress Main W indow

DDR Generic

Figure 11-43 shows the main window when DDR_Generic is selected. The only entry required in this window is the

module name. Other entries are set to the project settings. The user may change these entries if desired. After

entering the module name, click on Customize to open the Configuration Tab window as shown in Figure 11-44.

Figure 11-43. IPexpress Main Win dow for DDR_Generic

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Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Configuration Tab

The Configuration Tab lists all user-accessible attributes with default values set. Upon completion, click Generate

to generate source and constraint files. The user may choose to use the .lpc file to load parameters.

Figure 11-44. Configuration Tab for DDR_Generic

The user can change the Mode parameter to choose either Input, Output, Bidirection or Tristate DDR module. The

other configuration parameters will change according to the mode selected. The Delay parameter is only available

for Input and Bidirectional modes. Similarly the Multiplier for Fixed Delay parameter is only available when the

Delay parameter is configured to Fixed.

Table 11-12. User Parameters in the IPexpr ess GUI

DDR_MEM

Figure 11-45 shows the main window when DDR_MEM is selected. Similar to the DDR_Generic, the only entry

required here is the module name. Other entries are set to the project settings. The user may change these entries

User Parameters Description Values/Range Default

Mode Mode selection for the DDR block. Input, Output,

Bidirectional, Tristate Input

Data Width Width of the data bus. 1-64 8

Gearing Ratio Gearing ratio selection. 1x, 2x11x

Delay Input delay configuration Dynamic, Fixed,

Fixed XGMII Dynamic

Multiplier for Fixed Delay Fixed delay setting. Available only when delay is

configured as fixed. 0-15 0

Use Single Clk for 1x Allows for the selection of a single clock for the

gearing logic. On/Off Off

1. Only 1x available when Mode is Bidirection or Tristate.

11-37

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

if desired. After entering the module name, click on Customize to open the Configuration Tab window as shown

in Figure 11-46.

Figure 11-45. IPexpress Main Window for DDR_MEM

Configuration Tab

The Configuration Tab lists all user-accessible attributes with default values set. Upon completion, click Generate

to generate source and constraint files. The user may choose to use the .lpc file to load parameters.

11-38

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Figure 11-46. Configuration Tab for DDR_MEM

The user can change the Mode parameter to choose either the DDR or DDR2 interface. The other configuration

parameters will change according to the Mode selected. The Number of DQS parameter determines the number of

DDR interfaces. The software will assume there are eight data bits for every DQS. The user can also choose the

frequency of operation and the DDR DLL will be configured to this frequency.

The user has an option to enable the clock enable and tristate enables for the DDR registers. It is recommend that

the Lock/Jitter be enabled if the DDR interface is running at 150MHz or higher.

The parameters available depend on the mode selected. Tables 11-13 and 11-14 describe all user parameters in

the IPexpress GUI and their usage for modes DDR and DDR2.

Table 11-13. User Parameters in the IPexpress GUI when in DDR Mode

User Parameters Description Values/Range Default

I/O Buffer Configuration I/O Standard used for the Interface. This will

also depend on the Mode selected.

SSTL25_I,

SSTL25_II SSTL25_I

Data Width Width of the Data bus 8-64 8

Number of DQS Number of DQS will determine the number of

DQS Groups 1, 2, 4, 8 1

Frequency of DQS

DDR Interface Frequency. This is also input to

the DDR DLL. The values will depend on the

mode selected.

100MHz, 133MHz,

166MHz, 200MHz 200MHz

Lock/Jitter Sensitivity DLL Sensitivity to Jitter High, Low High

LSR for DDR Input Register LSR Control RESET, SET RESET

Create Clock Enable for DDR

Input Register Create Clock enable inputs to the block On/Off Off

Tri-state Enable for DDR

Output Registers

Creates Tri-state control for the DDR data output

registers. On/Off On

DDR Tristate enable for the

DQS output Creates Tristate control for DQS output On/Off On

11-39

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Table 11-14. User Parameters in the IPexpress GUI when in DDR2 Mode

FCRAM (“Fast Cycle Random Access Memory”) Interface

FCRAM is a DDR-type DRAM, which performs data output at both the rising and falling edges of the clock. FCRAM

devices operate at a core voltage of 2.5V with SSTL Class II I/O. It has enhanced both the core and peripheral logic

of the SDRAM. In FCRAM the address and command signals are synchronized with the clock input, and the data

pins are synchronized with the DQS signal. Data output takes place at both the rising and falling edges of the DQS.

DQS is in phase with the clock input of the device. The DDR SDRAM and DDR FCRAM controller will have differ-

ent pinouts.

LatticeXP2 devices can implement the FCRAM interface using dedicated DQS logic, input DDR registers and out-

put DDR registers, as described in the Implementing Memory Interfaces section of this document. Generation of

address and control signals for FCRAM are different than in DDR SDRAM devices. Please refer to the FCRAM

data sheets to see detailed specifications. Toshiba, Inc. and Fujitsu, Inc. offer FCRAM devices in 256Mb densities.

They are available in x8 or x16 configurations.

Board Design Guidelines

The most common challenge associated with implementing DDR memory interfaces is the board design and lay-

out. It is required that users strictly follow the guidelines recommended by memory device vendors.

Some of the common recommendations include matching trace lengths of interface signals to avoid skew, proper

DQ-DQS signal grouping, proper termination of the SSTL2 or SSTL18 I/O Standard, proper VREF and VTT gener-

ation decoupling and proper PCB routing.

The following documents include board layout guidelines:

• www.idt.com, IDT, PCB Design for Double Data Rate Memory

• www.motorola.com, AN2582, Hardware and Layout Design Considerations for DDR Interfaces

References

• www.jedec.org, JEDEC Standard 79, Double Data Rate (DDR) SDRAM Specification

• www.micron.com, DDR SDRAM Data Sheets

User Parameters Description Values/Range Default

I/O Buffer Configuration I/O Standard used for the Interface. This will

also depend on the Mode selected. SSTL18_I, SSTL18_II SSTL18_I

Data Width Width of the Data bus 8-64 8

Number of DQS Number of DQS will determine the number of

DQS Groups 1, 2, 4, 8 1

Frequency of DQS

DDR Interface Frequency. This is also input to

the DDR DLL. The values will depend on the

mode selected.

166MHz, 200MHz, 266MHz 200MHz

Lock/Jitter Sensitivity DLL Sensitivity to Jitter High, Low High

LSR for DDR Input Register LSR Control RESET, SET RESET

Create Clock Enable for DDR

Input Register Create Clock enable inputs to the block On/Off Off

Tri-state Enable for DDR

Output Registers

Creates Tri-state control for the DDR data output

registers. On/Off On

DDR Tristate enable for the

DQS output Creates Tristate control for DQS output On/Off On

DQS Buffer Configuration for

DDR2 DQS Buffer can be configured as Differential On/Off Off

11-40

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

• www.infinion.com, DDR SDRAM Data Sheets

• www.samsung.com, DDR SDRAM Data Sheets

• www.toshiba.com, DDR FCRAM Data Sheet

• www.fujitsu.com, DDR FCRAM Data Sheet

• RD1019, QDR Memory Controller Reference Design

•IPUG35, DDR1 & DDR2 SDRAM Controller (Pipelined Versions) User’s Guide

Technical Support Assistance

Hotline: 1-800-LATTICE (North America)

+1-503-268-8001 (Outside North America)

e-mail: techsupport@latticesemi.com

Internet: www.latticesemi.com

Revision History

Date Version Change Summary

February 2007 01.0 Initial release.

May 2007 01.1 Updated the port names on the input DDR block diagrams.

Updated text in DQS Transition Detect section under Memory Read

Implementation.

February 2009 01.2 Updated DLL Compensated DQS Delay Elements text section.

June 2009 01.3 Updated DQSDLL Update Control text section.

June 2010 01.4 Added Appendix A - DDR Generation using Diamond IPexpress

11-41

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Appendix A. DDR Generation using Diamond IPexpress

The IPexpress tool in the Lattice Diamond design software can be used to configure and generate the DDR Mem-

ory Interface and Generic DDR Module. The tool will generate an HDL module that contains the DDR primitives.

This module can be using in the top level design.

Figure 11-47 shows the main window of IPexpress. The DDR_Generic and DDR_MEM options under Architech-

ture > IO are used to configure the DDR modules.

Figure 11-47. IPexpress Main W indow

DDR Generic

Figure 11-48 shows the main window when DDR_Generic is selected. The only entry required in this window is the

module name. Other entries are set to the project settings.

The user may change these entries if desired. After entering the module name, click on Customize to open the

Configuration Tab window as shown in Figure 11-49.

11-42

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Figure 11-48. IPexpress Main Win dow for DDR_Generic

Configuration Tab

The Configuration Tab lists all user-accessible attributes with default values set. Upon completion, click Generate

to generate source and constraint files. The user may choose to use the .lpx file to load parameters.

Figure 11-49. Configuration Tab for DDR_Generic

11-43

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

The user can change the Mode parameter to choose either the Input, Output, Bi-directional or Tristate DDR mod-

ule. The other configuration parameters will change according to the mode selected. The Delay parameter is only

available for Input and Bi-directional modes. Similarly, the Multiplier for the Fixed Delay parameter is only available

when the Delay parameter is configured to Fixed.

Table 11-15. User Parameters in the IPexpr ess GUI

DDR_MEM

Figure 11-50 shows the main window when DDR_MEM is selected. Similar to DDR_Generic, the only entry

required is the module name. Other entries are set to the project settings. The user may change these entries if

desired. After entering the module name, click on Customize to open the Configuration Tab window as shown in

Figure 11-51.

Figure 11-50. IPexpress Main Window for DDR_MEM

User Parameters Description Values/Range Default

Mode Mode selection for the DDR block. Input, Output,

Bidirectional, Tristate Input

Data Width Width of the data bus. 1-64 8

Gearing Ratio Gearing ratio selection. 1x, 2x11x

Delay Input delay configuration Dynamic, Fixed,

Fixed XGMII Dynamic

Multiplier for Fixed Delay Fixed delay setting. Available only when delay is

configured as fixed. 0-15 0

Use Single Clk for 1x Allows for the selection of a single clock for the

gearing logic. On/Off Off

1. Only 1x available when Mode is Bidirection or Tristate.

11-44

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Configuration Tab

The Configuration Tab lists all user-accessible attributes with default values set. Upon completion, click Generate to

generate source and constraint files. The user may choose to use the .lpx file to load parameters.

Figure 11-51. Configuration Tab for DDR_MEM

The user can change the Mode parameter to choose either the DDR or DDR2 interface. The other configuration

parameters will change according to the Mode selected. The Number of DQS parameter determines the number of

DDR interfaces. The software will assume there are eight data bits for every DQS. The user can choose the fre-

quency of operation and the DDR DLL will be configured to this frequency.

The user has the option to enable the clock enable and tristate enables for the DDR registers. It is recommend that

the Lock/Jitter be enabled if the DDR interface is running at 150 MHz or higher.

The parameters available depend on the mode selected. Tables 11-16 and 11-17 describe all user parameters in

the IPexpress GUI and their usage for modes DDR and DDR2.

11-45

Lattice Semiconductor LatticeXP2 High-Speed I/O Interface

Table 11-16. User Parameters in the IPexpress GUI when in DDR Mode

Table 11-17. User Parameters in the IPexpress GUI when in DDR2 Mode

User Parameters Description Values/Range Default

I/O Buffer Configuration I/O Standard used for the Interface. This will

also depend on the Mode selected.

SSTL25_I,

SSTL25_II SSTL25_I

Data Width Width of the Data bus 8-64 8

Number of DQS Number of DQS will determine the number of

DQS Groups 1, 2, 4, 8 1

Frequency of DQS

DDR Interface Frequency. This is also input to

the DDR DLL. The values will depend on the

mode selected.

100MHz, 133MHz,

166MHz, 200MHz 200MHz

Lock/Jitter Sensitivity DLL Sensitivity to Jitter High, Low High

LSR for DDR Input Register LSR Control RESET, SET RESET

Create Clock Enable for DDR

Input Register Create Clock enable inputs to the block On/Off Off

Tri-state Enable for DDR

Output Registers

Creates Tri-state control for the DDR data output

registers. On/Off On

DDR Tristate enable for the

DQS output Creates Tristate control for DQS output On/Off On

User Parameters Description Values/Range Default

I/O Buffer Configuration I/O Standard used for the Interface. This will

also depend on the Mode selected. SSTL18_I, SSTL18_II SSTL18_I

Data Width Width of the Data bus 8-64 8

Number of DQS Number of DQS will determine the number of

DQS Groups 1, 2, 4, 8 1

Frequency of DQS

DDR Interface Frequency. This is also input to

the DDR DLL. The values will depend on the

mode selected.

166MHz, 200MHz, 266MHz 200MHz

Lock/Jitter Sensitivity DLL Sensitivity to Jitter High, Low High

LSR for DDR Input Register LSR Control RESET, SET RESET

Create Clock Enable for DDR

Input Register Create Clock enable inputs to the block On/Off Off

Tri-state Enable for DDR

Output Registers

Creates Tri-state control for the DDR data output

registers. On/Off On

DDR Tristate enable for the

DQS output Creates Tristate control for DQS output On/Off On

DQS Buffer Configuration for

DDR2 DQS Buffer can be configured as Differential On/Off Off

www.latticesemi.com 12-1 tn1139_01.0

February 2007 Technical Note TN1139

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Introduction

One requirement for design engineers using programmable devices is the ability to calculate the power dissipation

for a particular device used on a board. Lattice’s ispLEVER® design tools include the Power Calculator tool, which

allows designers to calculate the power dissipation for a given device. This technical note describes how to use the

Power Calculator tool to calculate the power consumption of the LatticeXP2™ family of devices. General guidelines

to reduce power consumption are also included.

Power Supply Sequencing and Hot Socketing

LatticeXP2 devices have been designed to ensure predictable behavior during power-up and power-down. Power

supplies can be sequenced in any order. During power-up and power-down sequences, the I/Os remain in tri-state

until the power supply voltage is high enough to ensure reliable operation. In addition, leakage into I/O pins is con-

trolled to within the limits specified in the LatticeXP2 Family Data Sheet, allowing for easy integration with the rest

of the system. These capabilities make the LatticeXP2 ideal for many multiple power supply and hot-swap applica-

tions.

Recommended Power-up Sequence

As described above, the supplies can be sequenced in any order. However, once internal power good is achieved

(determined by VCC, VCCAUX, VCCIO Bank x) the device releases the I/Os from tri-state and the management of

the I/Os becomes the designer's responsibility. To simplify a system design, it is recommended that supplies be

sequenced in the following order: VCCIO, VCC, VCCAUX. If VCCIO is tied to VCC or VCCAUX, then it is recom-

mended that VCCIO and the associated power supply are powered up before the remaining supply.

Please refer to the Hot Socketing section of the LatticeXP2 Family Data Sheet for more information.

Power Calculator Hardware Assumptions

Power consumption for a device can be coarsely broken down into the DC portion and the AC portion.

The Power Calculator reports the power dissipation in terms of:

1. DC portion of the power consumption.

2. AC portion of the power consumption.

The DC Power (or the Static power consumption) is the total power consumption of the used and the unused

resources. These power components are fixed for each resource used and depends upon the number of resource

units utilized. The DC component also includes the static power dissipation for the unused resources of the device.

The AC portion of power consumption is associated with the used resources. This is the dynamic part of the power

consumption. Its power dissipation is directly proportional to the frequency at which the resource is running and the

number of resource units used.

Power Calculation Equations

The following are the power equations used in the Power Calculator:

Power Estimation and Manage-

ment for LatticeXP2 Devices

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Total DC Power (Resource)

= Total DC Power of Used Portion + Total DC Power of Unused Portion

= [DC Leakage per Resource when Used * NRESOURCE]

+ [DC Leakage per Resource when Unused * (NTOTAL RESOURCE - NRESOURCE)]

Where:

NTOTAL RESOURCE is the total number of resources in a device

NRESOURCE is the number of resources used in the design

The total DC power consumption for all the resources as per the design data is the Quiescent Power in the Power

Calculator.

The AC Power is governed by the following equation:

Total AC Power (Resource)

= KRESOURCE * fMAX * AFRESOURCE * NRESOURCE

Where:

NTOTALRESOURCE is the number of resources in a device

NRESOURCE is the number of resources used in the design

KRESOURCE is the power constant for the resource in mW/MHz

fMAX is the max frequency at which the resource is running. Frequency is measured in MHz.

AFRESOURCE is the activity factor for the resource group.The Activity Factor is a percentage of the switching

frequency.

For example, the power consumption of the Slice portion is calculated in the following equation,

Total DC Power (Slice)

= Total DC Power of Used Portion + Total DC Power of Unused Portion

= [DC Leakage per Slice when Used * NSLICE]

= +[DC Leakage per Slice when Unused * (NTOTALSLICE - NSLICE)]

Total AC Power (Slice)

= KSLICE * fMAX * AFSLICE * NSLICE

Power Calculations

The Power Calculator allows users to estimate power consumption at three different levels:

1. Estimate of the utilized resources before completing place and route

2. Post place and route design

3. Post place and route, post trace, and post simulation

For the first level of estimation, the user provides estimates of device usage in the Power Calculator Wizard and the

tool provides a rough estimate of the power consumption.

The second level is a more accurate approach. The user imports the actual device utilization by importing the post

Place and Route netlist (NCD) file.

The third level brings even more accuracy to the calculation by importing the Trace (TWR) file to populate the max-

imum frequencies (fMAX) into the tool. Users also have the option of importing the information from the post simula-

tion (VCD) file and calculating the Activity Factor and Toggle Rates of various components.

These three stages of power calculation are discussed in detail in the following sections of this document.

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Using the Power Calculator

Starting the Power Calculator

The Power Calculator can be launched by one of two methods. The first method is to click the Power Calculator

button in the toolbar as shown in Figure 12-1.

Figure 12-1. Starting Power Calculator from the Toolbar

The Power Calculator can also be launched by going to the Tools menu and selecting the option Power Calcula-

tor as shown in Figure 12-2.

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Power Estimation and Management

Lattice Semiconductor for LatticeXP2 Devices

Figure 12-2. Starting Power Calculator from Tools Menu

Note: The Power Calculator does not support some older Lattice devices. The toolbar button and menu item are

only present when supported devices are selected.

Creating a Power Calculator Project

After starting the Power Calculator, the Power Calculator window is displayed. Click on the File menu and select

New to get to the Start Project window as shown in Figure 12-3.

Figure 12-3. Power Calc ulator Start Project Window (Create New Project)

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Power Estimation and Management

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The Start Project window is used to create a new Power Calculator Project (*.pep project). Three pieces of data are

entered into the Start Project window.

1. The Power Calculator project name by default is same as the Project Navigator project name. It can be

changed, if desired.

2. Project Directory is where the Power Calculator project (*.pep) file will be stored. By default it is stored in

the main project folder.

3. The NCD file is automatically selected, if available, or users can browse to the NCD file in a different loca-

tion.

Power Calculator Main Window

The Power Calculator main window is shown in Figure 4.

Figure 12-4. Power Calc ulator Main Window (Type View)

The top pane of the window shows information about the device family, device and the part number as it appears in

the Project Navigator. The VCC used for the power calculation is also listed. Users have the choice of selecting the

core voltage VCC with +5% of the nominal value (or values). The option of selecting VCCJ is also available. Users

can provide the ambient temperature, and the junction temperature is calculated based on that.

Users can also enter values for airflow in Linear Feet per Minute (LFM) along with heat sink to obtain the junction

temperature.

The table near the top of the Power Calculator main window summarizes the currents and power consumption

associated with each type of power supply for the device. This also takes into consideration the I/O power supplies.

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In the middle pane of the window, there are three tabs:

1. Power View

The first tab is the Power view. This tab provides an interactive spreadsheet type interface with all values in

terms of power consumption mW.

The first column breaks down the design in terms of clock domains. The second and third columns, which

are shaded blue, provide the DC (static) and AC (dynamic) power consumption, respectively.

Next are four columns shaded blue. These provide information on the I/O DC and AC power, including core

voltage, VCC and the I/O voltage supply, VCCIO.

The first three rows show the Quiescent Power for VCC, VCCAUX and VCCJ. These are DC power num-

bers for a blank device or device with no resource utilization.

Some of the cells are shaded yellow. These cells are editable cells and users can type in values such as

frequency, activity factors and resource utilization. The second tab (the Report tab) is the summary of the

Power View. This report is in text format and provides details of the power consumption.

2. ICC View

The second tab is the ICC view. This tab is exactly same as the Power View tab, except that all values are

expressed in terms of current or mA.

3. Report View

The third and final tab is the Report view. This is an HTML type of Power Calculator report. It summarizes

the contents of the Power and ICC views.

The final pane, the lower pane of the window, is the log pane where users can see a log of the various operations

in the Power Calculator.

Figure 12-5. Power Calculator Main Window (Power Report View)

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Power Estimation and Management

Lattice Semiconductor for LatticeXP2 Devices

Power Calculator Wizard

The Power Calculator Wizard allows users to estimate the power consumption of a design. This estimation is done

before the design is created. It is important for the user to understand the logic requirements of the design. The

wizard allows the user to provide the required parameters and then estimates the power consumption of the

device.

To start the Power Calculator in the wizard mode, go to the File menu and select Wizard. Alternatively, you can

click on the Wizard button to see the Power Calculator - Wizard window as shown in Figure 12-6. Select the option

Create a new Project and check the Wizard check box in the Power Calculator Start Project window. Provide the

project name and the project folder and click Continue. Since this is power estimation before the actual design, no

NCD file is required.

Figure 12-6. Power Calc ulator Start Project Window (Using the New Project Window Wizard)

In the next screen, the device family, device, and part number are chosen. After making the proper selections, click

Continue. This is shown in Figure 7.

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Power Estimation and Management

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Figure 12-7. Power Calc ulator Wizard Mode Window - Device Selection

In the following screens (Figures 8-12) users can select additional resources, such as I/O types, clock name, fre-

quency at which the clock in running and other parameters by selecting the appropriate resource using the pull-

down Type menu.

1. Routing Resources

2. Logic

3. EBR

4. I/O

5. PLL

6. Clock Tree

The number in these windows refers to the number of clocks and the index corresponds to each of the clocks. By

default, the clock names are clk_1, clk_2, and so on. Clock names can be changed by typing in the Clock Name

text box. For each clock domain and resource, parameters such as Frequency and Activity Factor can be specified.

In the final window, click the Create button for each clock driven resource to include the parameters specified for it.

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Power Estimation and Management

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Figure 12-8. Power Calc ulator Wizard Mode Window - Resource Specification

These parameters are then used in the Power Type View window, which can be seen upon clicking on Finish (see

Figure 9).

Figure 12-9. Power Calc ulator Wizard Mode - Main Window

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Power Estimation and Management

Lattice Semiconductor for LatticeXP2 Devices

Creating a New Project Without the NCD File

A new project can be started without the NCD file, either by using the wizard (as discussed above) or by selecting

the Create a New Project option in the Power Calculator - Start Project. The project name and project directory

must be provided. After clicking Continue the Power Calculator main window will be displayed.

However, in this case there are no resources added. The power estimation row for the routing resources is always

available in the Power Calculator. Additional information such as the Slice, EBR, I/O, PLL, and clock tree utilization

must be provided to calculate the power consumption.

For example, if the user wants to add the logic resources shown in Figure 10, right-click on Logic >> and then

select Add Row in the menu that pops up.

Figure 12-10. Power Calculator Main Window - Adding Resources

This adds a new row for the logic resource utilization with clock domain named clk_1.

Similarly, other resources like EBR, I/Os, PLLs and routing can be added. Each of these resources is used for AC

power estimation and categorized by clock domains.

Creating a New Project with the NCD Fi le

If the post place and routed NCD file is available, the Power Calculator can use it to import accurate information

about the design data and resource utilization for power calculation. After starting the Power Calculator, the NCD

file is automatically placed in the NCD File option, if it is available in the project directory. Otherwise, browse to the

NCD file using the Power Calculator.

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Power Estimation and Management

Lattice Semiconductor for LatticeXP2 Devices

Figure 12-11. Power Calculator Start Project Window with Post PAR NCD File

The information from the NCD file is automatically inserted into the correct rows and Power Calculator uses the

Clock names from the design as shown in Figure 12-12.

Figure 12-12. Power Calculator Main Window - Resource Utilization Picked Up from the NCD File

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Power Estimation and Management

Lattice Semiconductor for LatticeXP2 Devices

Opening an Existing Project

The Power Calculator - Start Project window also allows users to open an existing project. Select Open Existing

Project and browse to the *.pe p project file and click Continue. This opens the existing project in windows similar

to those discussed above (see Figure 12-13).

Figure 12-13. Opening an Existing Project in Power Calculator

Importing a Simulation File (VCD)

A post simulation VCD file can be imported into the Power Calculator project to estimate a design’s activity factors.

Under the File menu, select Open Simulation File and browse to the VCD file location and select Open. All AF

and Toggle Rate fields are then populated with the information from this file, as shown in Figure 12-14.

Figure 12-14. Importing a Simu lation File in an Existing Power Calculator Project

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Power Estimation and Management

Lattice Semiconductor for LatticeXP2 Devices

Importing a Trace Report File (TWR)

Post Trace TWR file can be imported into the Power Calculator project to estimate a design’s activity factors. Under

the File menu, select Open Trace Report File, browse to the TWR file location and select Open. All Freq. (MHz)

fields are then populated with the information from this file, as shown in Figure 12-15.

Figure 12-15. Importing a Trace Report File to a Power Calculator Project

Activity Factor and Toggle Rate

Activity Factor% (or AF%) is defined as the percentage of frequency (or time) that a signal is active or toggling of

the output. Most of the resources associated with a clock domain are running or toggling at some percentage of the

frequency at which the clock is running. Users must provide this value as a percentage under the AF% column in

the Power Calculator tool.

Another term used is the I/O Toggle Rate or the I/O Toggle Frequency. The AF% is applicable to the PFU, routing

and memory read write ports, etc. The activity of the I/Os is determined by the signals provided by the user (for

inputs) or as an output of the design (for outputs). Therefore, the rates at which I/Os toggle define their activity. The

Toggle Rate (or TR) in MHz of the output is defined by the following equation:

Toggle Rate (MHz) = 1/2 * fMAX * AF%

Users must provide the TR (MHz) value for the I/O instead of providing the Frequency and AF% in case of other

resources. The AF can be calculated for each routing resource, output or PFU. However, it involves long calcula-

tions. The general recommendation for a design occupying roughly 30% to 70% of the device is an AF% of 15% to

25%. This is an average value that can be seen most of the design. An accurate value for an activity factor depends

upon clock frequency, stimulus to the design and the final output.

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Power Estimation and Management

Lattice Semiconductor for LatticeXP2 Devices

Ambient and Junction Temperatures and Airflow

A common method of characterizing a packaged device’s thermal performance is with thermal resistance, or . For

a semiconductor device, thermal resistance indicates the steady state temperature rise of the die junction above a

given reference for each watt of power (heat) dissipated at the die surface. Its units are °C/W.

The most common examples are JA, Thermal Resistance Junction-to-Ambient (in °C/W) and JC, Thermal Resis-

tance Junction-to-Case (also in °C/W). Another factor is JB, Thermal Resistance Junction-to-Board (in °C/W).

Knowing the reference (i.e. ambient, case, or board) temperature, the power, and the relevant  value, the junction

temp can be calculated by the following equations.

TJ = TA + JA * P (1)

TJ = TC + JC * P (2)

TJ = TB + JB * P (3)

While TJ, TA,TC and TB are the Junction, Ambient, Case (or Package) and Board temperatures (in °C) respectively,

P is the total power dissipation of the device.

JA is commonly used with natural and forced convection air-cooled systems. JC is useful when the package has

a high conductivity case mounted directly to a PCB or heatsink. And JB applies when the board temp adjacent to

the package is known.

The Power Calculator utilizes the Ambient Temperature (°C) to calculate the Junction Temperature (°C) based on

the JA for the targeted device, per Equation 1 above. Users can also provide the Airflow values (in LFM) to get a

more accurate value of the Junction temperature.

Managing Power Consumption

One of the most critical design factors today is the reduction of system power consumption, especially for modern

handheld devices and electronics. There are several design techniques that can significantly reduce overall system

power consumption. Some of these include:

1. Reducing operating voltage.

2. Operating within the specified package temperature limitations.

3. Using the optimum clock frequency to reduce power consumption, since dynamic power is directly propor-

tional to the frequency of operation. Designers must determine if a portion of their design can be clocked at

a lower rate that will reduce power.

4. Reducing the span of the design across

5. Reducing the voltage swing of the I/Os where possible.

6. Using optimum encoding where possible. For example, a 16-bit binary counter has, on average, only 12%

Activity Factor and a 7-bit binary counter has an average of 28% Activity Factor. On the other hand, a 7-bit

Linear Feedback Shift Register could toggle as much as 50% Activity Factor, which causes higher power

consumption. A gray code counter, where only one bit changes at each clock edge, will use the least

amount of power, as the Activity Factor would be less than 10%.

7. Minimize the operating temperature, by the following methods:

a. Use packages that can better dissipate heat. For example, packages with lower thermal impedance.

b. Place heat sinks and thermal planes around the device on the PCB.

c. Better airflow techniques using mechanical airflow guides and fans (both system fans and device

mounted fans).

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Lattice Semiconductor for LatticeXP2 Devices

Power Calculator Assumptions

The following are the assumptions made by the Power Calculator:

1. The Power Calculator tool is based on equations with constants based on a room temperature of 25°C.

2. The user can define the Ambient Temperature (TA) for device Junction Temperature (TJ) calculation based

on the power estimation. TJ is calculated from user-entered TA and power calculation of typical room tem-

perature.

3. I/O power consumption is based on output loading of 5pF. Users can change this capacitive loading.

4. The Power Calculator provides an estimate of the power dissipation and current for each of the following

types of power supplies: VCC, VCCIO, VCCJ and VCCAUX.

5. The nominal VCC is used by default to calculate power consumption. A lower or higher VCC can be cho-

sen from a list of available values.

6. Airflow in Linear Feet per Minute (LFM) can be entered by the user along with the Heat Sink option to cal-

culate the Junction Temperature.

7. The default value of the I/O types is LVCMOS12, 6mA.

8. The Activity Factor (AF) is defined as the toggle rate of the registered output. For example, assuming that

the input of a flip-flop is changing at every clock cycle, 100% AF of a flip-flop running at 100MHz is 50MHz.

Technical Support Assistance

Hotline: 1-800-LATTICE (North America)

+1-503-268-8001 (Outside North America)

e-mail: techsupport@latticesemi.com

Internet: www.latticesemi.com

Revision History

Date Version Change Summary

February 2007 01.0 Initial release.

www.latticesemi.com 13-1 tn1140_01.0

February 2007 Technical Note TN1140

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Introduction

This technical note discusses how to access the features of the LatticeXP2™ sysDSP™ (Digital Signal Process-

ing) Block described in the LatticeXP2 Family Data Sheet. Designs targeting the sysDSP Block can offer significant

improvement over traditional LUT-based implementations. Table 13-1 provides an example of the performance and

area benefits of this approach:

Table 13-1. sysDSP Block vs. LUT-based Multipliers

sysDSP Block Hardware

The LatticeXP2 sysDSP Blocks are located in rows throughout device. Below is a block diagram of one of the sys-

DSP Blocks:

Figure 13-1. LatticeXP2 sysDSP Block

Multiplier Width Register Pipelining

XP2-17-7

Uses One sysDSP Block XP2-17-7

Uses LUTs

fMAX (MHz)1LUTs fMAX (MHz)1LUTs

9x9 Input, Multiplier, Output 365 0 103 192

18x18 Input, Multiplier, Output 365 0 76 698

36x36 Input, Multiplier, Output 323 0 50 2732

1. These timing numbers were generated using the ispLEVER® design tool. Exact performance may vary with design and tool

version.

OutA0(18)

OutB0(18)

OutA1(18)

OutB1(18)

OutA2(18)

OutB2(18)

OutA3(18)

OutB3(18)

Summation (38) (Two 20 Bits in 9x9 Mode)

36x36 (Mult36)

Accumulator (52) 1

Output

Registers

Intermediate

Pipeline Registers

Adder, Subtractor and

Accumulator Functions

One of these One of these

36x36, 18x18 and

9x9 Multiplier Functions

Output Registers to SRI

of right-side sysDSP Block

(if it exists) and/or General

Logic*

Input Registers from

SRO of left-side

sysDSP Block (or

tied to zero if none)

Accumulator (52) 3

Add/Sub (36) (9x9 ≤ 2x18) 1

PR0 (36)

In Reg A0 In Reg A1

In Reg B1

In Reg A2 In Reg A3

In Reg B0 In Reg B2 In Reg B3

9x9 9x9

9x9 9x9 9x9 9x9 9x9 9x9

PR1 (36) PR2 (36) PR3 (36)

Mult18-0 Mult18-1 Mult18-2 Mult18-3

Add/Sub (36) (9x9 ≤ 2x18) 3

*Can only be routed to general logic routing when configured with less than

three MULT18X18.

Note: Each sysDSP Block spans nine columns of PFUs.

LatticeXP2 sysDSP

Usage Guide

13-2

Lattice Semiconductor Lattice XP2 sysDSP Usage Guide

The sysDSP Block can be configured as:

• One 36x36 Multiplier

– Basic multiplier, no add/sub/accum/sum blocks

• Four 18x18 Multipliers

– Two add/sub/accum blocks

– One summation block for adding four multipliers

• Eight 9x9 Multipliers

– Four add/sub blocks

– Two summation blocks

Note that a sysDSP block can only be configured in one mode at a time.

sysDSP Block Software

Overview

The sysDSP Block of the LatticeXP2 device can be targeted in a number of ways.

• The IPexpress™ tool in the ispLEVER software allows the rapid creation of modules implementing sysDSP ele-

ments. These modules can then be used in HDL designs as appropriate.

• The coding of certain functions into a design’s HDL and allowing the synthesis tools to Inference the use of a

sysDSP block.

• The implementation of designs in The MathWorks® Simulink® tool using a Lattice block set. The ispLEVER sys-

DSP portion of the ispLEVER design tools will then convert these blocks into HDL as appropriate.

• Instantiation of sysDSP primitives directly in the source code

Targeting sysDSP Block Using IPexpress

IPexpress allows you to graphically specify sysDSP elements. Once the element is specified, a HDL file is gener-

ated, which can be instantiated in a design. IPexpress allows users to configure all ports and set all available

parameters. The following modules target the sysDSP Block. For design examples using IPexpress, refer to EXAM-

PLES in the ispLEVER Software (from the Project Navigator pull down-menu, go to File and open Example). The

following four types of elements can be specified via IPexpress:

• MULT (Multiplier)

• MAC (Multiplier Accumulate)

• MULTADDSUB (Multiplier Add/Subtract)

• MULTADDSUBSUM (Multiply Add/Subtract and SUM)

MULT Module

The MULT Module configures elements to be packed into the sysDSP primitives. The Basic mode screen illustrated

in Figure 13-2 consists of an optional one clock, one clock enable and one reset tied to all registers. Multiple sys-

DSP Blocks can be spanned to accommodate large multiplications. Additional LUTs may be required if multiple

sysDSP blocks are needed. Select Area/Speed to determine the LUT implementation. The input data format can

be selected as Parallel, Shift or Dynamic. The Shift format can only be enabled if inputs are less than 18 bits. The

Shift format enables a sample/shift register, which is useful in applications such as the FIR filter. The Advanced

mode screen, illustrated in Figure 13-3, allows finer control over the register. In the Advanced mode, users can

control each register with independent clocks, clock enables and resets. MULT inputs can be from 2 to 72 bits.

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Lattice Semiconductor Lattice XP2 sysDSP Usage Guide

Figure 13-2. MULT Mode Basic Set-up

Figure 13-3. MULT Mode Advanced Set-up

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Lattice Semiconductor Lattice XP2 sysDSP Usage Guide

MAC Module

The MAC Module configures multiply accumulate elements to be packed into the primitive MULT18X18MACB. The

Basic mode, shown in Figure 13-4, consists of an optional one clock, one clock enable and one reset tied to all reg-

isters. Because of the accumulator, the output register is automatically enabled. Multiple sysDSP Blocks can be

spanned to accommodate large multiplications. The accumulator of the sysDSP block is 52 bits deep and addi-

tional LUTs can be used if a larger accumulation is required. If sysDSP blocks are spanned, additional LUT logic

may be required. Select Area/Speed to determine the LUT implementation. The input data format can be selected

as Parallel, Shift or Dynamic. The Shift format can only be enabled if inputs are less than 18 bits. The Shift format

enables a sample/shift register. The Accumsload loads the accumulator with the value from the LD port. This is

required to initialize and load the first value of the accumulation. The Advanced mode, shown in Figure 13-5, allows

finer control over the registers. In the advanced mode, users can control each register with independent clocks,

clock enables and resets. MAC inputs can be from 2 to 72 bits.

Figure 13-4. MAC Mode Basic Set-up

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Lattice Semiconductor Lattice XP2 sysDSP Usage Guide

Figure 13-5. MAC Mode Advanced Set-up

MULTADDSUB Module

The MULTADDSUB GUI configures multiplier addition/subtraction elements to be packed into the primitives

MULT18X18ADDSUBB or MULT9X9ADDSUBB. The Basic mode, shown in Figure 13-6, consists of an optional

one clock, one clock enable and one reset tied to all registers. Multiple sysDSP Blocks can be spanned to accom-

modate large multiplications. If sysDSP blocks are spanned, additional LUT logic may be required. Select

Area/Speed to determine the LUT implementation. The input data format can be selected as Parallel, Shift or

Dynamic. The Shift format can only be enabled if inputs are less than 18 bits. The Shift format enables a sam-

ple/shift register, which is useful in applications such as the FIR filter. The Advanced mode, shown in Figure 13-7,

provides finer control over the registers. In the advanced mode, users can control each register with independent

clocks, clock enables and resets. MULTADDSUB inputs can be from 2 to 72 bits.

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Lattice Semiconductor Lattice XP2 sysDSP Usage Guide

Figure 13-6. MULTADDSUB Mode Basic Set-up

Figure 13-7. MULTADDSUB Mode Advanced Set-up

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Lattice Semiconductor Lattice XP2 sysDSP Usage Guide

MULTADDSUBSUM Module

The MULTADDSUBSUM GUI configures Multiplier Addition/Subtraction Addition elements to be packed into the

primitives MULT18X18ADDSUBSUMB or MULT9X9ADDSUBSUMB. The Basic mode, shown in Figure 13-8, con-

sists of an optional one clock, one clock enable and one reset tied to all registers. Multiple sysDSP Blocks can be

spanned to accommodate large multiplications. If sysDSP blocks are spanned, additional LUT logic may be

required. Select Area/Speed to determine the LUT implementation. The input data format can be selected as Par-

allel, Shift or Dynamic. The Shift format is can only be enabled if inputs are less than 18 bits. The Shift format

enables a sample/shift register, which is useful in applications such as the FIR filter. The Advanced mode, shown in

Figure 13-9, provides finer control over the registers. In the advanced mode, users can control each register with

independent clocks, clock enables and resets. MULTADDSUBSUM inputs can be from 2 to 72 bits.

Figure 13-8. MULTADDSUBSUM Mode Basic Set-up

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Lattice Semiconductor Lattice XP2 sysDSP Usage Guide

Figure 13-9. MULTADDSUBSUM Mode Advance

Figure 13-10. MULTADDSUBSUM Mode Advance

13-9

Lattice Semiconductor Lattice XP2 sysDSP Usage Guide

Targeting the sysDSP Block by Inference

The Inferencing flow enables the design tools to infer sysDSP Blocks from a HDL design. It is important to note that

when using the Inferencing flow, unless the code style matches the sysDSP Block, results will not be optimal. Con-

sider the following Verilog and VHDL examples:

// This Verilog example will be mapped into single MULT18X18MACB with the output register enabled

module mult_acc (dataout, dataax, dataay, clk);

output [16:0] dataout;

input [7:0] dataax, dataay;

input clk;

reg [16:0] dataout;

wire [15:0] multa = dataax * dataay; // 9x9 Multiplier

wire [16:0] adder_out;

assign adder_out = multa + dataout; // Accumulator

always @(posedge clk)

begin

dataout <= adder_out; // Output Register of the Accumulator

end

endmodule

-- This VHDL example will be mapped into single MULT18X18MACB with all the registers enabled

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity mac is

port (clk, reset : in std_logic;

dataax, dataay : in std_logic_vector(8 downto 0);

dataout : out std_logic_vector(17 downto 0));

end;

architecture arch of mac is

signal dataax_reg, dataay_reg : std_logic_vector(8 downto 0);

signal multout, multout_reg : std_logic_vector(17 downto 0);

signal addout : std_logic_vector(17 downto 0);

signal dataout_reg : std_logic_vector(17 downto 0);

begin

dataout <= dataout_reg;

process (clk, reset)

begin

if (reset = ‘1’) then

dataax_reg <= (others => ‘0’);

dataay_reg <= (others => ‘0’);

elsif (clk’event and clk=’1’) then

dataax_reg <= dataax;

dataay_reg <= dataay;

end if;

end process;

multout <= dataax_reg * dataay_reg;

process (clk, reset)

begin

if (reset = ‘1’) then

multout_reg <= (others => ‘0’);

elsif (clk’event and clk=’1’) then

multout_reg <= multout;

end if;

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Lattice Semiconductor Lattice XP2 sysDSP Usage Guide

end process;

addout <= multout_reg + dataout_reg;

process (clk, reset)

begin

if (reset = ‘1’) then

dataout_reg <= (others => ‘0’);

elsif (clk’event and clk=’1’) then

dataout_reg <= addout;

end if;

end process;

end arch;

The above RTL will infer the following block diagram:

Figure 13-11. MULT18X18MACB Block Diagram

This block diagram can be mapped directly into the sysDSP primitives. Note that if a test point were added between

the multiplier and the accumulator, or two output registers, etc. the code could not be mapped into a

MULT18X18MACB of a sysDSP Block. Therefore, options that could be included in a design are input registers,

pipeline registers, etc. For more Inferring design examples refer to EXAMPLES in the ispLEVER software.

Multiplier

Accumulator

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Lattice Semiconductor Lattice XP2 sysDSP Usage Guide

Figure 13-12. MAC18X18MACB Packed into a sysDSP Block

sysDSP Blocks in the Report File

To check the configuration of the sysDSP Blocks in your design you can look at the MAP and Post PAR report files.

The MAP report file shows the mapped sysDSP components/primitives in your design. The Post PAR report file

shows the number of components in each sysDSP Block. The report files that follow show how the inferred MAC

was used.

MAP Report File

. MULT18X18MACB addout_17_0:

Multiplier

Operation Unsigned

Operation Registers CLK CE RST

--------------------------------------------

Input

Pipeline

Operation Registers CLK CE RST

--------------------------------------------

Input

Pipeline

OVERFLOW1

ACCUM1[51:0]

OVERFLOW3

ACCUM3[51:0]

MUI18A0[17:0]

MUI18B0[17:0]

MUI18A3[8:0]

MUI18B3[8:0]

SROA[17:0]*

SROB[17:0]*

CLK[3:0]**

CE[3:0]*

RST[3:0]*

Notes:

*These signals are optional.

**At least one clock is required.

SRIA[17:0]*

SRIB[17:0]*

18x18 - 0

18x18 - 2

Pipe 1 Pipe 0 Pipe 2

18x18 - 1

18x18 - 3

unused

Pipe 3

Out

Reg

Out

Reg

Out

Reg

Out

Reg

52-bit Accum 3 52-bit Accum 1

ACCUMSLOAD[3,1]*

ADDNSUB[3,1]*

SOURCEB[3,1]*

SOURCEA[3,1]*

SIGNEDA[3,1]*

SIGNEDB[3,1]*

+/-

In Reg A 2

In Reg B 2

In Reg A 3

In Reg B 3

In Reg A 0

In Reg B 0

In Reg A1

In Reg B1

SLOAD DATA1[15:0]*

MUI18A2[17:0]

MUI18B2[17:0]

SLOAD DATA3[15:0]*

MUI18A1[17:0]

MUI18B1[17:0]

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Lattice Semiconductor Lattice XP2 sysDSP Usage Guide

AddSub

Operation Add

Operation Registers CLK CE RST

--------------------------------------------

Input

Pipeline

Data

Input Registers CLK CE RST

---------------------------------------------

A CLK0 CE0 RST0

B CLK0 CE0 RST0

Pipeline Registers CLK CE RST

--------------------------------------------

Pipe CLK0 CE0 RST0

Output Register CLK CE RST

--------------------------------------------

Output CLK0 CE0 RST0

Other

GSR ENABLED

Number Of Mapped DSP Components:

--------------------------------

MULT36X36B 0

MULT18X18B 0

MULT18X18MACB 1

MULT18X18ADDSUBB 0

MULT18X18ADDSUBSUMB 0

MULT9X9B 0

MULT9X9ADDSUBB 0

MULT9X9ADDSUBSUMB 0

--------------------------------

Post PAR Report File

DSP Utilization Summary:

DSP Block #: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

# of MULT36X36B

# of MULT18X18B

# of MULT18X18MACB 1

# of MULT18X18ADDSUBB

# of MULT18X18ADDSUBSUMB

# of MULT9X9B

# of MULT9X9ADDSUBB

# of MULT9X9ADDSUBSUMB

DSP Block 1 Component_Type Instance_Name

DSP Block 2 Component_Type Instance_Name

DSP Block 3 Component_Type Instance_Name

DSP Block 4 Component_Type Instance_Name

DSP Block 5 Component_Type Instance_Name

DSP Block 6 Component_Type Instance_Name

DSP Block 7 Component_Type Instance_Name

DSP Block 8 Component_Type Instance_Name

DSP Block 9 Component_Type Instance_Name

R45C81 MULT18X18MACB addout_17_0

DSP Block 10 Component_Type Instance_Name

DSP Block 11 Component_Type Instance_Name

DSP Block 12 Component_Type Instance_Name

DSP Block 13 Component_Type Instance_Name

DSP Block 14 Component_Type Instance_Name

DSP Block 15 Component_Type Instance_Name

DSP Block 16 Component_Type Instance_Name

DSP Block 17 Component_Type Instance_Name

DSP Block 18 Component_Type Instance_Name

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Lattice Semiconductor Lattice XP2 sysDSP Usage Guide

Targeting the sysDSP Block Using Simulink

Simulink Overview

Simulink is a graphical add-on (similar to schematic entry) for Matlab®, which is produced by The MathWorks. For

more information, refer to the Simulink web page at www.mathworks.com/products/simulink/.

Why is Simulink used?

• It allows users to create algorithms using floating point numbers.

• It helps users convert floating point algorithms into fixed point algorithms.

How does Simulink fit into the normal ispLEVER design flow?

• Once you have converted have your algorithm working in fixed point. You can use the Lattice ispDSP Block to

create HDL files, which can be instantiated in your HDL design. Currently there is only support for VHDL.

What does Lattice provide?

• Lattice provides a library of blocks for the Simulink tool, which include Multipliers, Adders, Registers, and other

standard building blocks. Besides the basic building blocks there are a couple of unique Lattice blocks:

Gateways In and Out

Everything between Gateways In and Out represents the HDL code. Everything before a Gateway In is the stim-

ulus your test bench. Everything after the Gateway Out are the signals you will be monitoring in the test bench.

Below is an example. The box on the left contains Gateways In’s and the three boxes on the right contain Gate-

way Outs in Figure 13-13.

Generate

The Generate block is used to convert Fixed point Simulink design into HDL files which can be instantiated in a

HDL design. The Generate Block is identified by the Lattice logo and can be seen in Figure 13-13.

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Lattice Semiconductor Lattice XP2 sysDSP Usage Guide

Figure 13-13. Simulink Design

Targeting the sysDSP Block by Instantiating Primitives

The sysDSP Block can be targeted by instantiating the sysDSP Block primitives into the design. The advantage of

instantiating primitives is that it provides access to all ports and sets all available parameters. The disadvantage of

this flow is that all this customization requires extra coding by the user. Appendix A details the syntax for the sys-

DSP Block primitives.

sysDSP Block Control Signal and Data Signal Descriptions

RST Asynchronous reset of selected registers

SIGNEDA Dynamic signal: 0 = unsigned, 1 = signed

SIGNEDB Dynamic signal: 0 = unsigned, 1 = signed

ACCUMSLOAD Dynamic signal: 0 = accumulate, 1 = load

ADDNSUB Dynamic signal: 0 = subtract, 1 = add

SOURCEA Dynamic signal: 0 = parallel input, 1 = shift input

SOURCEB Dynamic signal: 0 = parallel input, 1 = shift input

Technical Support Assistance

Hotline: 1-800-LATTICE (North America)

+1-503-268-8001 (Outside North America)

e-mail: techsupport@latticesemi.com

Internet: www.latticesemi.com

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Lattice Semiconductor Lattice XP2 sysDSP Usage Guide

Revision History

Date Version Change Summary

February 2007 01.0 Initial release.

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Lattice Semiconductor Lattice XP2 sysDSP Usage Guide

Appendix A. DSP Block Primitives

MULT18X18B

input A17,A16,A15,A14,A13,A12,A11,A10,A9,A8,A7,A6,A5,A4,A3,A2,A1,A0;

input B17,B16,B15,B14,B13,B12,B11,B10,B9,B8,B7,B6,B5,B4,B3,B2,B1,B0;

input SIGNEDA, SIGNEDB, SOURCEA, SOURCEB;

input CE0,CE1,CE2,CE3,CLK0,CLK1,CLK2,CLK3,RST0,RST1,RST2,RST3;

input SRIA17,SRIA16,SRIA15,SRIA14,SRIA13,SRIA12,SRIA11,SRIA10,SRIA9;

input SRIA8,SRIA7,SRIA6,SRIA5,SRIA4,SRIA3,SRIA2,SRIA1,SRIA0;

input SRIB17,SRIB16,SRIB15,SRIB14,SRIB13,SRIB12,SRIB11,SRIB10,SRIB9;

input SRIB8,SRIB7,SRIB6,SRIB5,SRIB4,SRIB3,SRIB2,SRIB1,SRIB0;

output SROA17,SROA16,SROA15,SROA14,SROA13,SROA12,SROA11,SROA10,SROA9;

output SROA8,SROA7,SROA6,SROA5,SROA4,SROA3,SROA2,SROA1,SROA0;

output SROB17,SROB16,SROB15,SROB14,SROB13,SROB12,SROB11,SROB10,SROB9;

output SROB8,SROB7,SROB6,SROB5,SROB4,SROB3,SROB2,SROB1,SROB0;

output P35,P34,P33,P32,P31,P30,P29,P28,P27,P26,P25,P24,P23,P22,P21,P20,P19,P18;

output P17,P16,P15,P14,P13,P12,P11,P10,P9,P8,P7,P6,P5,P4,P3,P2,P1,P0;

parameter REG_INPUTA_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;

parameter REG_INPUTA_CE = “ CE0, CE1, CE2, CE3 “;

parameter REG_INPUTA_RST = “ RST0, RST1, RST2, RST3 “;

parameter REG_INPUTB_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;

parameter REG_INPUTB_CE = = “ CE0, CE1, CE2, CE3 “;

parameter REG_INPUTB_RST = “ RST0, RST1, RST2, RST3 “;

parameter REG_PIPELINE_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;

parameter REG_PIPELINE_CE = “ CE0, CE1, CE2, CE3 “;

parameter REG_PIPELINE_RST = “ RST0, RST1, RST2, RST3 “;

parameter REG_OUTPUT_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;

parameter REG_OUTPUT_CE = “ CE0, CE1, CE2, CE3 “;

parameter REG_OUTPUT_RST = “ RST0, RST1, RST2, RST3 “;

parameter REG_SIGNEDA_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;

parameter REG_SIGNEDA_CE = “ CE0, CE1, CE2, CE3 “;

parameter REG_SIGNEDA_RST = “ RST0, RST1, RST2, RST3 “;

parameter REG_SIGNEDB_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;

parameter REG_SIGNEDB_CE = “ CE0, CE1, CE2, CE3 “;

parameter REG_SIGNEDB_RST = “ RST0, RST1, RST2, RST3 “;

parameter GSR = “ Enabled, Disabled “;

MULT18X18ADDSUBB

input A017,A016,A015,A014,A013,A012,A011,A010,A09;

input A08,A07,A06,A05,A04,A03,A02,A01,A00;

input A117,A116,A115,A114,A113,A112,A111,A110,A19;

input A18,A17,A16,A15,A14,A13,A12,A11,A10;

input B017,B016,B015,B014,B013,B012,B011,B010,B09;

input B08,B07,B06,B05,B04,B03,B02,B01,B00;

input B117,B116,B115,B114,B113,B112,B111,B110,B19;

input B18,B17,B16,B15,B14,B13,B12,B11,B10;

input SIGNEDA, SIGNEDB, SOURCEA0, SOURCEA1, SOURCEB0, SOURCEB1, ADDNSUB;