AN181 - Cirrus Logic, Inc.

P.O. Box 17847, Austin, Texas 78760

(512) 445 7222 FAX: (512) 445 7581

http://www.cirrus.com

AN181

Application Note

USING THE CRYSTAL® CS8900A IN 8-BIT MODE

By James Ayres

Introduction

The CS8900A is a good candidate for designs with

an 8-bit data bus. Because of its small size and

built-in filters the chip will take up a minimum of

board space w hile providing a cost effec tive, high

performance Ethernet connection. This application

note shows how to use the CS8900A in 8 bit mode,

including software information for the programmer

and a typical connection diagram for the design en-

gineer.

References

The designer should familiarize himself with the

Connecting to non-ISA bus sys tems chapter in the

CS8900A Technical Reference Manual, Low cost,

high performance Ethernet Controller for non-

ISA sys tems. This chapter is a reference on how to

easily connect the chip to a non-ISA processor. It

includes diagrams connecting the CS8900A to a

MC68302, a Cirrus Logic CL-PS7111, and a Hita-

chi SH3. That chapter contains most of the data

needed for the design engineer. The data sheet is

the source for functional descriptions of the r egis-

ters, receive operation, transmit operation, timing

etc. Only the 8-bi t specific issues will be covered

in this application note.

Software Drivers

There are many software drivers available for the

CS8900A in 16-bit mode, including VxWorks™,

Psos®, Linux®, Packet Driver and ATI Nucleus.

Source code for the VxWorks, Linux, and Psos are

available on the Cirrus Website. The Linux driver,

in particular, is a good starting point for writing a

custom driver in C . Porti ng any driver for 8-bit op-

eration is the customer’s responsibility.

I/O Ports

In 8 bit mode the CS8900A is accessed through its

eight 16 bit I/O ports.

In a non-ISA system these ports are usually memo-

ry mapped into standard system memory. Please

note that the driver should read or write both bytes

when accessing any CS8900A status or event reg-

ister.

Frame Transmission

Transmission and reception of frames is done

through these data ports. The basic steps in trans-

mitting a frame are 1) bid for buffer space on the

chip by writi ng t he trans m it comm a n d to the TxC -

MD port and the length to TxLength port then

checking the BusSt register. 2) if space is available

begin writing the data, a byte at a time, to Re-

ceive/Transmit data port 0. Refer to the section I/O

Space Operation of the data sheet for more details.

For instance, the CS8900A is at its default I/O lo-

cation of 300h. To transmit a frame that is 81 bytes

in length the driver would first write the transmit

command 00C0h (Start transmitting after all bytes

transferred) to the TxCMD port. This is done by

writing the low order byte, C0h, to 304h then writ-

Offset Type Description

0000h Read/Write Receive/Transmit Data (Port 0)

0002h Read/Write Receive/Transmit Data (Port 1)

0004h Write-only TxCMD (Transmit Command)

0006h Write-only TxLength (Transmit Length)

0008h Read-only Interrupt St atus Queue

000Ah Read/Write PacketPage Pointer

000Ch Read/Write PacketPage Data (Port 0)

000Eh Read/Write PacketPage Data (Port 1)

Table 1. I/O Mode Mapping

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ing the high order byte, 00h, to 305h. Next write

0051h (81 decimal) to the TxLENGTH port. Low

byte, 51h, to 306h then high byte, 00h, to 307h.

Now check to see if transmit space is available.

This is done by checking the BusST register, bit 8.

To check this register you will use the packet page

pointer port and the packet page data port.

Write 0138h to Packet Page Pointer (starts at 30Ah)

then read the Packet Page Data Port 0 (starts at

30Ch). If bit 8 (Rdy4TxNow) is set then you can

start transfer ring data to Transmi t Data Port 0. Do

so in the following manner: write the first byte to

300h, the second byte to 301h, byte 3 to 300h, byte

4 to 301h and so on until the whole frame is written.

The chip will automatically send the frame after the

last byte is written.

Frame Reception

The host is notified of an incoming frame by poll-

ing the Rx E vent R egister. When the host i s a ware

of an incoming frame the software should read the

frame data following these steps (assuming I/O

base 300h):

•read the RxStatus word (same data as RxEvent,

byte 301h first, then low order byte 300h.

Note: it is very important to read the RxStatus

and RxLength high order byte first.

•read the RxLength word (the frame length)

from data port 0. Read this high order byte

301h first, then low order byte 300h.

•begin reading the frame data, 300h then 301h,

300h then 301h until the entire frame has been

transferred to host memory.

Schematic and Layout Review Service

Prevent problems early in the design phase of your

product. Have your sche matic or layout review ed

free of charge by our experts before you build your

board. Call Applications Engineering at (512) 442-

7555 or send e-mail to ethernet@crystal.cir-

rus.com.

Unsupported functions in 8 bit mode

•Interrupts are not supported. Polled mode must

be used.

•The DMA engine only uses 16 bit memory ac-

cesses and does not support 8 bit transfers.

•The packet page pointer has an auto i ncrement

feature that cannot be used in 8 bit mode.

•An EEPROM is not supported. Most 8 bit de-

signs should not require one and can eliminate

the added cost.

Contacting Cirrus Logi c Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/

Crystal is a trademark of Cirrus Logic, Inc.

Linux is a registered trademark of Linus Torvalds

PSOS is register trademark of Integrated System Inc.

VxWorks is a registered trademark of Wind River Systems, Inc.

All other names are trademarks, registered trademarks, or service marks of their respective companies.

Preliminary product i nformation describes pr oducts whi ch are i n producti on, but for whi c h ful l characteriza ti on data is not yet avai l ab le . Advance p roduct infor -

mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information

contained i n this docum ent is accurate and reli able. However , the i nfor mation is sub ject to change with out no tice and i s provi ded “AS IS” without warrant y of

any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringement s of patents or ot h er ri g ht s

of third parties. Thi s document i s the propert y of Cirru s Logic, I nc. and implie s no licen se under patent s, copy rights, trademarks, or trade secre ts. No part of

this publicati o n may be copied, reproduced, st ored in a retr ieval system, or transmitted, in any form or by any means (electro nic, mechanical, photographic, or

otherwise) wi t hou t the prior written consent of Cirrus Lo gi c, I nc. I te ms from any Ci rrus Logic website or disk may be printed for use by t he user . However, no

part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,

photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture

or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing

in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-

marks and service marks can be found at http://www.cirrus.com.

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Typical Connection Diagram

EECS

EEDATAOUT

EESK

SA[10:19]

MEMW

MEMR

IOW

IOR

REFRESH

SBHE

SD[8:15]

INTRQ0

INTRQ1

RXD-

RXD+

TXD-

TXD+

DO-

DO+

CI-

CI+

DI-

DI+

LANLED

LINKLED

EEDATAIN

AEN

RESET

INTRQ2

INTRQ3

DMARQ0

DMACK0

DMARQ1

DMACK1

DMARQ2

DMACK2

MEMCS16

IOCHRDY

68 pF

24.9

Ω, 1%

24.9

Ω, 1%

100

Ω, 1%

RJ45

680

Ω

680

Ω

XTAL1 XTAL2 SLEEP TEST RES

97 98 93

4.99 k

Ω

,1%

20 MHz

Vcc

4.7 k

Ω

CS8900

CHIPSEL

IOCS16

100

ELCS

10 BASE T

Isolation

Transformer

BSTATUS/HCI

Vcc

77 76

0.1 µF

Vcc

SA[0:9]

IOW

IOR

SD[0:7]

CHIPSEL

RESET

SD[0:7]

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4AN181REV1

SAMPLE POLLING ROUTINE

Pseudo Code

#define EventMask = 0xFFC0

#define RegisterMask = 0x003F

#define RxEvent = 0x0004

#define TxEvent = 0x0008

#define BufEvent = 0x000C

Poll-Chip{

unsigned short Event;

Event = Poll-Registers()

While Event <> 0x0000 {

Switch (RegisterMask & Event) {

Case RxEvent:

result = Pr oces s- Rx Event(Event) ;

break;

Case TxEvent:

result = Pr oc es s-T x Ev ent(E vent)

break;

Case BufEvent:

resu lt = Pr oc es s- B ufE vent(Ev ent);

break;

} // End Switch

Event = Poll-Registers()

} // End While

} // End Poll-Chip

Poll-Registers{

unsigned short Event;

Event = Read-RxEventRegister();

If (EventMask & Event) {

return Event;}

Event = Read-TxEventRegister()

If (EventMask & Event) {

return Event;}

Event = Read-BufEventRegister()

If (EventMask & Event) {

return Event;}

Return 0x0000

// End Poll-Registers

}

• Notes •