1
S2091
2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP S2091
®
2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP
FEATURES
• Supports 2.5 Gbps Data Rates
• Fully differential for minimum
jitter accumulation
• TTL Bypass Select
• High speed 50Ω source terminated outputs
• 0.4W Typical power dissipation
• 3.3V power supply
• 20 Pin TSSOP
GENERAL DESCRIPTION
The S2091 is a Port Bypass Circuit (PBC). A single
channel Fibre Channel PBC offers designers maxi-
mum flexibility in FC-AL disk architectures. The
S2091 is designed to minimize jitter accumulation by
providing a high bandwidth fully differential signal
path. Port Bypass circuits are used to provide resil-
iency in Fibre Channel Arbitrated Loop (FC-AL) ar-
chitectures. PBC’s are used within FC-AL disk arrays
to allow for resiliency and hot swapping of FC-AL
drives.
A Port-by-Pass Circuit is a 2:1 Multiplexer with two
modes of operations: Normal and Bypass. In Normal
mode, the disk drive is connected to the loop. In
Bypass mode, the disk drive is either absent or non-
OUT P/N
SEL
DDI P/NDDO P/N
IN P/N
1
0
PBC
Figure 1. S2091 Block Diagram
1LESTUOODD
0NINI
1IDDNI
Table 1. Truth Table
functional and data bypasses to the next available disk
drive. Normal mode is enabled with a High on the SEL
pin and Bypass mode is enable by a Low on the SEL
pin. Direct Attach Fibre Channel Disk Drives have an
“LRC Interlock” signal defined to control the SEL func-
tion. A system diagram showing the S2091 in a single
loop of a disk array is illustrated in Figure 2.
The S2091 can be cascaded with the S3040 (Data
retimer) for arrays of disk drives greater than 4.
Table 1 is a truth table detailing the data flow
through the S2091. Figure 3 shows a timing diagram
of the data relationship in the S2091. The primary
AC parameter of importance is the deterministic jitter
or data eye degradation inserted by the port bypass
circuit. The design for the S2091 minimized jitter ac-
cumulation by using high bandwidth, low skew fully
differential circuits. This provides for symmetric rise
and fall delays as well as noise rejection.
DEVICE
SPECIFICATION
2
2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP
S2091
Figure 2. Functional Block Diagram
Pulldown for Bypass in
Absence of Disk Drive
S2091
bypass
TX
01
Optics
or
Copper
Dual SC
or
DB-9
S2091
Disk
Storage
FC-AL Disk Drive
LRC Interlock
E_STORE
TX
RX
normal
10
S2091
normal
Disk
Storage
FC-AL Disk Drive
LRC Interlock
01
TX
RX
E_STORE
3
S2091
2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP
Figure 3. Timing Waveforms
Figure 4. Differential Voltage
IN P/N
DI P/N
OUT P/N
DO P/N
T
1, 2, 3
VP-P = 2 x single-ended swing
Single-ended swing
4
2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP
S2091
emaNniPleveLO/I#niPnoitpircseD
PNI
NNI
.ffiD
LCEPVL
I6,7.tropCBPmaertsnwodehtmorfstupnilaitnereffiD
PIDD
NIDD
.ffiD
LCEPVL
I3,4.evirdksidlacolehtmorftupnilaireS
LESLTTVLI11ehtfotuptuoehtgnisuacedom"SSAPYB"ehtstceleswoLA
,hgiHnehW.TUOrotroptxenehtotetagaporpottropsuoiverp
suoiverpehtsetuorhcihwedom"LAMRON"stceleslangissiht
ehtotIDD,tupnilacolehtsetuordnaODD,tuptuolacolehtottrop
.TUOrotroptxen
PODD
NODD
.ffiD
LMC
O81,91.evirdksidlacolehtgnivirdtuptuolaireS
PTUO
NTUO
.ffiD
LMC
O41,51.tropCBPmaertspuehtgnivirdtuptuolaireS
CCV,01,2,1
02,71,21
.lanimonV3.3.ylppuSrewoP
DNG,9,8,5
61,31 gnitnuomeidehtotdehcattayllacisiyhperasnipdnuorG.dnuorG tsebroF.htaplamrehtehtfotraptnatropminaeradna,ecafrus aotdetcennocebdluohssnipdnuorglla,ecnamrofreplamreht.elbissopfisaivelpitlumgnisu,enalpdnuorg
Table 2. Pin Assignment and Descriptions
Figure 5. S2091 Pinout Package
20 VCC
19 DDOP
18 DDON
17 VCC
16 GND
15 OUTP
14 OUTN
13 GND
12 VCC
11 SEL
VCC 1
VCC 2
DDIN 3
DDIP 4
GND 5
INN 6
INP 7
GND 8
GND 9
VCC 10
5
S2091
2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP
Figure 6. 20 TSSOP Package
eciveD Θ)riAllitS(aj Θcj
A1902SW/C˚77W/C˚52
Thermal Management
6
2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP
S2091
retemaraPnoitpircseDpyTxaMstinUsnoitidnoC
T
1R
T
1F
emitllafdnaesirataDlaireS
)TUOotNI( 501531sp .sisabelpmasanodetset%08ot%02
001(Ω).enil-ot-enil
T
2R
T
2F
emitllafdnaesirataDlaireS )ODDotNI( 501531sp .sisabelpmasanodetset%08ot%02
001(Ω).enil-ot-enil
T
3R
T
3F
emitllafdnaesirataDlaireS )TUOotIDD( 501051sp .sisabelpmasanodetset%08ot%02
001(Ω).enil-ot-enil
1T otNIyalednoitagaporphguorhtwolF
TUO 51.14.1sn 05.dessapybstiucricllahtiwyaleD.daolmhO
2T otNIyalednoitagaporphguorhtwolF
ODD 51.14.1sn ssapyBrolamroNniCBPhtiwyaleD .daolmhO05.edom
3T IDDyalednoitagaporphguorhtwolF
TUOot 51.14.1sn 05.edomlamroNniCBPhtiwyaleD.daolmhO
T
SMRrettij
)SMR(noitalumuccarettijmodnaR2.24sp
htiwdetalumuccarettijtuptuoSMR -TUOotNImorfedocB01/B8dilav anodetseT.edomssapybniCBP .sisabelpmas
T
JDrettij
)p-p(noitalumuccarettijcitsinimreteD67±sp
detalumuccarettijtuptuocitsinimreteD ,TUOotNImorfedocB01/B8dilavhtiw -reteD.dessapybsegatsCBPhtob toneulavlautcA.noitalumisybdenim fonoitatimilhtdiwdnaboteuddeifirev .tnempiuqetset
Table 3. AC Characteristics (Over recommended operating conditions.)
7
S2091
2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP
retemaraPniMpyTxaMstinU
V(egatloVylppuSrewoP
CC
)5.04+V
V(egatloVtupnICDLCEP
PNI
)5.0- V
CC
5.0+
V
V(egatloVtupnICDLTT
PNI
)5.0- V
CC
5.0+
V
I(tnerruCtuptuOLMC
TUO
)hgiHtuptuoCD(,) 09Am
T(saiBrednUerutarepmeTesaC
C
)55-521˚C
T(erutarepmeTegarotS
GTS
)56-051˚C
egatloVegrahcsiDcitatS0001V
retemaraPniMpyTxaMstinU
V(egatloVylppuSrewoP
CC
)41.3+74.3+V
)T(egnaRerutarepmeTgnitarepOtneibmA04-58+˚C
Table 5. Absolute Maximum Ratings
1
Table 6. Recommended Operating Conditions
1
1. CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied one at a time to devices
without causing permanent damage. Functionality at or above the values listed is not implied. Exposure
to these values for extended periods may affect device reliability.
1. AMCC guarantees the functional and parametric operation of the part under “Recommended Operating
Conditions” (except where specifically noted in the AC and DC parametric tables).
retemaraPnoitpircseDniMpyTxaMstinUsnoitidnoC
V
)LTI(HI
)LTT-LES(egatlovHGIHtupnI0.2CCVV
V
)LTI(LI
)LTT-LES(egatlovWOLtupnI08.0V
I
)LTI(HI
)LTT-LES(tnerrucHGIHtupnI05Aµ
V
NI
V4.2=
I
)LTI(LI
)LTT-LES(tnerrucWOLtupnI005-05-Aµ
V
NI
V5.0=
V
CC
egatloVylppuS41.374.3V
V
CC
%5±V03.3=
I
CC
tnerruCylppuS081032Am V,nepostuptuO
CC
V=
CC
xam
P
D
noitapissiDrewoP4.08.W V,nepostuptuO
CC
V=
CC
xam
∆V
)FD(NI
kaep-ot-kaeplaitnereffidrevieceR N/PIDD&N/PNI,ytivitisnestupni 0030002
Vm
p-p
1
CDyllanretnI.delpuoCCA
Vdesaib
CC
V56.0-
∆V
)OS_L(NTUO
-ot-kaeplaitnereffidtuptuoN/PODD
gniwsegatlovkaep 00010641
Vm
p-p
1
001Ωenil-ot-enil
∆V
)TUO(NTUO
-ot-kaeplaitnereffidtuptuoN/PTUO
gniwsegatlovkaep 00010641
Vm
p-p
1
001Ωenil-ot-enil
Table 4. DC Characteristics (Over recommended operating conditions.)
1. See Figure 4.
8
2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP
S2091
Input Structures
Two input structures exist in this part; TTL and high speed, differential inputs. The LVTTL inputs will interface
with any LVTTL outputs. The high speed, differential inputs can be AC coupled per the FC-PH specification.
Therefore, the high speed, differential input buffers are biased at Vcc -0.65V. Refer to Figure 7 for high speed
differential input termination.
Figure 8. Output
Backplane
S2091 GND
VCC
50Ω
50Ω
Figure 7. Input Termination
S2091
100 Ω
Biased at Vcc -0.65V
9
S2091
2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP
AMCC is a registered trademark of Applied Micro Circuits Corporation.
Copyright ® 1998 Applied Micro Circuits Corporation
September 24, 1998
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied
on is current.
AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it
convey any license under its patent rights nor the rights of others.
AMCC reserves the right to ship devices of higher grade in place of those of lower grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121
Phone: (619) 450-9333 • (800) 755-2622 • Fax: (619) 450-9885
http://www.amcc.com
C
E
R
T
I
F
I
E
D
I
S
O
9
0
0
1
EDARG.ONTRAPEGAKCAP
laicremmoC-S1902POSST02–A
Ordering Information
XXXXX X
Grade Part No. Package
