To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics. The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc. "Standard": 8. 9. 10. 11. 12. Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support. "Specific": Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. User's Manual 16 H8/36912 Group, H8/36902 Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series H8/36912F H8/36902F H8/36912 H8/36911 H8/36902 H8/36901 H8/36900 HD64F36912G HD64F36902G HD64336912G HD64336911G HD64336902G HD64336901G HD64336900G Rev.3.00 2006.09 Rev. 3.00 Sep. 14, 2006 Page ii of xxviii Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Rev. 3.00 Sep. 14, 2006 Page iii of xxviii General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed. Rev. 3.00 Sep. 14, 2006 Page iv of xxviii Configuration of This Manual This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules * CPU and System-Control Modules * On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index Rev. 3.00 Sep. 14, 2006 Page v of xxviii Preface The H8/36912 Group and H8/36902 Group are single-chip microcomputers made up of the highspeed H8/300H CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction set that is compatible with the H8/300 CPU. Target Users: This manual was written for users who will be using the H8/36912 Group and H8/36902 Group in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8/36912 Group and H8/36902 Group to the target users. Refer to the H8/300H Series Software Manual for a detailed description of the instruction set. Notes on reading this manual: * In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. * In order to understand the details of the CPU's functions Read the H8/300H Series Software Manual. * In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 19, List of Registers. Example: Register name: The following notation is used for cases when the same or a similar function, e.g. serial communication interface, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) Bit order: The MSB is on the left and the LSB is on the right. Rev. 3.00 Sep. 14, 2006 Page vi of xxviii Notes: When using an on-chip emulator (E7, E8) for H8/36912, H8/36902 program development and debugging, the following restrictions must be noted. The NMI pin is reserved for the E7 or E8, and cannot be used. Area H'2000 to H'2FFF is used by the E7 or E8, and is not available to the user. Area H'F980 to H'FD7F must on no account be accessed. When the E7 or E8 is used, address breaks can be set as either available to the user or for use by the E7 or E8. If address breaks are set as being used by the E7 or E8, the address break control registers must not be accessed. 5. When the E7 or E8 is used, NMI is an input/output pin (open-drain in output mode). 1. 2. 3. 4. Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ H8/36912 Group and H8/36902 Group manuals: Document Title Document No. H8/36912 Group, H8/36902 Group Hardware Manual This manual H8/300H Series Software Manual REJ09B0213 User's manuals for development tools: Document Title Document No. H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual REJ10B0058 H8S, H8/300 Series Simulator/Debugger User's Manual REJ10B0211 H8S, H8/300 Series High-Performance Embedded Workshop 3 Tutorial REJ10B0024 H8S, H8/300 Series High-Performance Embedded Workshop 3 User's Manual REJ10B0026 Application notes: Document Title Document No. H8S, H8/300 Series C/C++ Compiler Package Application Note REJ05B0464 Single Power Supply F-ZTATTM On-Board Programming REJ05B0520 Rev. 3.00 Sep. 14, 2006 Page vii of xxviii Rev. 3.00 Sep. 14, 2006 Page viii of xxviii Contents Section 1 Overview................................................................................................1 1.1 1.2 1.3 1.4 Features................................................................................................................................. 1 Internal Block Diagram......................................................................................................... 3 Pin Arrangement ................................................................................................................... 5 Pin Functions ........................................................................................................................ 9 Section 2 CPU......................................................................................................11 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Address Space and Memory Map ....................................................................................... 12 Register Configuration........................................................................................................ 14 2.2.1 General Registers................................................................................................ 15 2.2.2 Program Counter (PC) ........................................................................................ 16 2.2.3 Condition-Code Register (CCR)......................................................................... 16 Data Formats....................................................................................................................... 18 2.3.1 General Register Data Formats ........................................................................... 18 2.3.2 Memory Data Formats ........................................................................................ 20 Instruction Set ..................................................................................................................... 21 2.4.1 Table of Instructions Classified by Function ...................................................... 21 2.4.2 Basic Instruction Formats ................................................................................... 30 Addressing Modes and Effective Address Calculation....................................................... 32 2.5.1 Addressing Modes .............................................................................................. 32 2.5.2 Effective Address Calculation ............................................................................ 35 Basic Bus Cycle .................................................................................................................. 37 2.6.1 Access to On-Chip Memory (RAM, ROM)........................................................ 37 2.6.2 On-Chip Peripheral Modules .............................................................................. 38 CPU States .......................................................................................................................... 39 Usage Notes ........................................................................................................................ 40 2.8.1 Notes on Data Access to Empty Areas ............................................................... 40 2.8.2 EEPMOV Instruction.......................................................................................... 40 2.8.3 Bit Manipulation Instruction............................................................................... 40 Section 3 Exception Handling .............................................................................47 3.1 3.2 Exception Sources and Vector Address .............................................................................. 47 Register Descriptions.......................................................................................................... 49 3.2.1 Interrupt Edge Select Register 1 (IEGR1) .......................................................... 49 3.2.2 Interrupt Edge Select Register 2 (IEGR2) .......................................................... 50 3.2.3 Interrupt Enable Register 1 (IENR1) .................................................................. 50 Rev. 3.00 Sep. 14, 2006 Page ix of xxviii 3.3 3.4 3.5 3.2.4 Interrupt Enable Register 2 (IENR2) .................................................................. 51 3.2.5 Interrupt Flag Register 1 (IRR1)......................................................................... 52 3.2.6 Interrupt Flag Register 2 (IRR2)......................................................................... 53 3.2.7 Wakeup Interrupt Flag Register (IWPR) ............................................................ 53 Reset Exception Handling .................................................................................................. 54 Interrupt Exception Handling ............................................................................................. 55 3.4.1 External Interrupts .............................................................................................. 55 3.4.2 Internal Interrupts ............................................................................................... 56 3.4.3 Interrupt Handling Sequence .............................................................................. 57 3.4.4 Interrupt Response Time..................................................................................... 59 Usage Notes ........................................................................................................................ 61 3.5.1 Interrupts after Reset........................................................................................... 61 3.5.2 Notes on Stack Area Use .................................................................................... 61 3.5.3 Notes on Rewriting Port Mode Registers ........................................................... 61 Section 4 Address Break ..................................................................................... 63 4.1 4.2 Register Descriptions.......................................................................................................... 64 4.1.1 Address Break Control Register (ABRKCR) ..................................................... 64 4.1.2 Address Break Status Register (ABRKSR) ........................................................ 66 4.1.3 Break Address Registers (BARH, BARL).......................................................... 66 4.1.4 Break Data Registers (BDRH, BDRL) ............................................................... 66 Operation ............................................................................................................................ 67 Section 5 Clock Pulse Generators ....................................................................... 69 5.1 5.2 5.3 5.4 5.5 5.6 Features............................................................................................................................... 70 Register Descriptions.......................................................................................................... 71 5.2.1 RC Control Register (RCCR) ............................................................................. 71 5.2.2 RC Trimming Data Protect Register (RCTRMDPR).......................................... 72 5.2.3 RC Trimming Data Register (RCTRMDR) ........................................................ 73 5.2.4 Clock Control/Status Register (CKCSR)............................................................ 74 System Clock Select Operation .......................................................................................... 75 5.3.1 Clock Control Operation..................................................................................... 76 5.3.2 Clock Change Timing......................................................................................... 78 Trimming of On-chip Oscillator Frequency ....................................................................... 80 External Oscillators ............................................................................................................ 82 5.5.1 Connecting Crystal Resonator ............................................................................ 82 5.5.2 Connecting Ceramic Resonator .......................................................................... 83 5.5.3 External Clock Input Method.............................................................................. 83 Prescaler.............................................................................................................................. 83 5.6.1 Prescaler S .......................................................................................................... 83 Rev. 3.00 Sep. 14, 2006 Page x of xxviii 5.7 Usage Notes ........................................................................................................................ 84 5.7.1 Note on Resonators............................................................................................. 84 5.7.2 Notes on Board Design ....................................................................................... 84 Section 6 Power-Down Modes ............................................................................85 6.1 6.2 6.3 6.4 6.5 Register Descriptions.......................................................................................................... 85 6.1.1 System Control Register 1 (SYSCR1) ................................................................ 86 6.1.2 System Control Register 2 (SYSCR2) ................................................................ 88 6.1.3 Module Standby Control Register 1 (MSTCR1) ................................................ 89 6.1.4 Module Standby Control Register 2 (MSTCR2) ................................................ 90 Mode Transitions and States of LSI.................................................................................... 91 6.2.1 Sleep Mode ......................................................................................................... 93 6.2.2 Standby Mode ..................................................................................................... 93 6.2.3 Subsleep Mode.................................................................................................... 94 Operating Frequency in Active Mode................................................................................. 94 Direct Transition ................................................................................................................. 94 Module Standby Function................................................................................................... 95 Section 7 ROM ....................................................................................................97 7.1 7.2 7.3 7.4 7.5 Block Configuration ........................................................................................................... 97 Register Descriptions.......................................................................................................... 99 7.2.1 Flash Memory Control Register 1 (FLMCR1).................................................... 99 7.2.2 Flash Memory Control Register 2 (FLMCR2).................................................. 100 7.2.3 Erase Block Register 1 (EBR1) ........................................................................ 101 7.2.4 Flash Memory Enable Register (FENR) ........................................................... 101 On-Board Programming Modes........................................................................................ 102 7.3.1 Boot Mode ........................................................................................................ 102 7.3.2 Programming/Erasing in User Program Mode.................................................. 106 Flash Memory Programming/Erasing............................................................................... 107 7.4.1 Program/Program-Verify .................................................................................. 107 7.4.2 Erase/Erase-Verify............................................................................................ 109 7.4.3 Interrupt Handling when Programming/Erasing Flash Memory....................... 110 Program/Erase Protection ................................................................................................. 112 7.5.1 Hardware Protection ......................................................................................... 112 7.5.2 Software Protection........................................................................................... 112 7.5.3 Error Protection................................................................................................. 112 Section 8 RAM ..................................................................................................115 Rev. 3.00 Sep. 14, 2006 Page xi of xxviii Section 9 I/O Ports............................................................................................. 117 9.1 9.2 9.3 9.4 9.5 9.6 9.7 Port 1................................................................................................................................. 117 9.1.1 Port Mode Register 1 (PMR1) .......................................................................... 118 9.1.2 Port Control Register 1 (PCR1) ........................................................................ 119 9.1.3 Port Data Register 1 (PDR1) ............................................................................ 119 9.1.4 Port Pull-Up Control Register 1 (PUCR1)........................................................ 120 9.1.5 Pin Functions .................................................................................................... 120 Port 2................................................................................................................................. 121 9.2.1 Port Control Register 2 (PCR2) ........................................................................ 122 9.2.2 Port Data Register 2 (PDR2) ............................................................................ 122 9.2.3 Pin Functions .................................................................................................... 123 Port 5................................................................................................................................. 124 9.3.1 Port Mode Register 5 (PMR5) .......................................................................... 125 9.3.2 Port Control Register 5 (PCR5) ........................................................................ 125 9.3.3 Port Data Register 5 (PDR5) ............................................................................ 126 9.3.4 Port Pull-Up Control Register 5 (PUCR5)........................................................ 126 9.3.5 Pin Functions .................................................................................................... 127 Port 7................................................................................................................................. 128 9.4.1 Port Control Register 7 (PCR7) ........................................................................ 128 9.4.2 Port Data Register 7 (PDR7) ............................................................................ 129 9.4.3 Pin Functions .................................................................................................... 129 Port 8................................................................................................................................. 130 9.5.1 Port Control Register 8 (PCR8) ........................................................................ 131 9.5.2 Port Data Register 8 (PDR8) ............................................................................ 131 9.5.3 Pin Functions .................................................................................................... 132 Port B................................................................................................................................ 134 9.6.1 Port Data Register B (PDRB) ........................................................................... 134 9.6.2 Pin Functions .................................................................................................... 135 Port C................................................................................................................................ 136 9.7.1 Port Control Register C (PCRC)....................................................................... 137 9.7.2 Port Data Register C (PDRC) ........................................................................... 137 9.7.3 Pin Functions .................................................................................................... 138 Section 10 Timer B1.......................................................................................... 139 10.1 10.2 Features............................................................................................................................. 139 Register Descriptions........................................................................................................ 140 10.2.1 Timer Mode Register B1 (TMB1) .................................................................... 140 10.2.2 Timer Counter B1 (TCB1)................................................................................ 141 10.2.3 Timer Load Register B1 (TLB1) ...................................................................... 141 Rev. 3.00 Sep. 14, 2006 Page xii of xxviii 10.3 10.4 Operation .......................................................................................................................... 142 10.3.1 Interval Timer Operation .................................................................................. 142 10.3.2 Auto-Reload Timer Operation .......................................................................... 142 Timer B1 Operating Modes .............................................................................................. 143 Section 11 Timer V............................................................................................145 11.1 11.2 11.3 11.4 11.5 11.6 Features............................................................................................................................. 145 Input/Output Pins.............................................................................................................. 147 Register Descriptions........................................................................................................ 147 11.3.1 Timer Counter V (TCNTV) .............................................................................. 147 11.3.2 Time Constant Registers A and B (TCORA, TCORB) .................................... 148 11.3.3 Timer Control Register V0 (TCRV0) ............................................................... 148 11.3.4 Timer Control/Status Register V (TCSRV) ...................................................... 150 11.3.5 Timer Control Register V1 (TCRV1) ............................................................... 151 Operation .......................................................................................................................... 152 11.4.1 Timer V Operation............................................................................................ 152 Timer V Application Examples ........................................................................................ 155 11.5.1 Pulse Output with Arbitrary Duty Cycle........................................................... 155 11.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input .......... 156 Usage Notes ...................................................................................................................... 157 Section 12 Timer W ...........................................................................................159 12.1 12.2 12.3 12.4 12.5 Features............................................................................................................................. 159 Input/Output Pins.............................................................................................................. 162 Register Descriptions........................................................................................................ 162 12.3.1 Timer Mode Register W (TMRW) ................................................................... 163 12.3.2 Timer Control Register W (TCRW) ................................................................. 164 12.3.3 Timer Interrupt Enable Register W (TIERW) .................................................. 165 12.3.4 Timer Status Register W (TSRW) .................................................................... 166 12.3.5 Timer I/O Control Register 0 (TIOR0) ............................................................. 168 12.3.6 Timer I/O Control Register 1 (TIOR1) ............................................................. 169 12.3.7 Timer Counter (TCNT)..................................................................................... 171 12.3.8 General Registers A to D (GRA to GRD)......................................................... 171 Operation .......................................................................................................................... 172 12.4.1 Normal Operation ............................................................................................. 172 12.4.2 PWM Operation................................................................................................ 176 Operation Timing.............................................................................................................. 181 12.5.1 TCNT Count Timing ........................................................................................ 181 12.5.2 Output Compare Output Timing ....................................................................... 182 12.5.3 Input Capture Timing........................................................................................ 183 Rev. 3.00 Sep. 14, 2006 Page xiii of xxviii 12.6 12.5.4 Timing of Counter Clearing by Compare Match .............................................. 183 12.5.5 Buffer Operation Timing .................................................................................. 184 12.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match ............................. 185 12.5.7 Timing of IMFA to IMFD Setting at Input Capture ......................................... 186 12.5.8 Timing of Status Flag Clearing......................................................................... 186 Usage Notes ...................................................................................................................... 187 Section 13 Watchdog Timer.............................................................................. 191 13.1 13.2 13.3 Features............................................................................................................................. 191 Register Descriptions........................................................................................................ 192 13.2.1 Timer Control/Status Register WD (TCSRWD) .............................................. 192 13.2.2 Timer Counter WD (TCWD)............................................................................ 194 13.2.3 Timer Mode Register WD (TMWD) ................................................................ 194 Operation .......................................................................................................................... 195 Section 14 Serial Communication Interface 3 (SCI3)....................................... 197 14.1 14.2 14.3 14.4 14.5 14.6 Features............................................................................................................................. 197 Input/Output Pins.............................................................................................................. 199 Register Descriptions........................................................................................................ 199 14.3.1 Receive Shift Register (RSR) ........................................................................... 200 14.3.2 Receive Data Register (RDR)........................................................................... 200 14.3.3 Transmit Shift Register (TSR) .......................................................................... 200 14.3.4 Transmit Data Register (TDR).......................................................................... 200 14.3.5 Serial Mode Register (SMR) ............................................................................ 201 14.3.6 Serial Control Register 3 (SCR3) ..................................................................... 202 14.3.7 Serial Status Register (SSR) ............................................................................. 204 14.3.8 Bit Rate Register (BRR) ................................................................................... 206 14.3.9 Sampling Mode Register (SPMR) .................................................................... 211 Operation in Asynchronous Mode .................................................................................... 212 14.4.1 Clock................................................................................................................. 212 14.4.2 SCI3 Initialization............................................................................................. 213 14.4.3 Data Transmission ............................................................................................ 214 14.4.4 Serial Data Reception ....................................................................................... 216 Operation in Clocked Synchronous Mode ........................................................................ 219 14.5.1 Clock................................................................................................................. 219 14.5.2 SCI3 Initialization............................................................................................. 220 14.5.3 Serial Data Transmission .................................................................................. 220 14.5.4 Serial Data Reception (Clocked Synchronous Mode) ...................................... 223 14.5.5 Simultaneous Serial Data Transmission and Reception.................................... 225 Multiprocessor Communication Function ........................................................................ 227 Rev. 3.00 Sep. 14, 2006 Page xiv of xxviii 14.7 14.8 14.6.1 Multiprocessor Serial Data Transmission ......................................................... 229 14.6.2 Multiprocessor Serial Data Reception .............................................................. 231 Interrupts........................................................................................................................... 235 Usage Notes ...................................................................................................................... 236 14.8.1 Break Detection and Processing ....................................................................... 236 14.8.2 Mark State and Break Sending.......................................................................... 236 14.8.3 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only).................................................................. 236 14.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ................................................................................................................. 237 Section 15 I2C Bus Interface 2 (IIC2) ................................................................239 15.1 15.2 15.3 15.4 15.5 15.6 15.7 Features............................................................................................................................. 239 Input/Output Pins.............................................................................................................. 241 Register Descriptions........................................................................................................ 242 15.3.1 I2C Bus Control Register 1 (ICCR1)................................................................. 242 15.3.2 I2C Bus Control Register 2 (ICCR2)................................................................. 245 15.3.3 I2C Bus Mode Register (ICMR)........................................................................ 246 15.3.4 I2C Bus Interrupt Enable Register (ICIER) ....................................................... 248 15.3.5 I2C Bus Status Register (ICSR)......................................................................... 250 15.3.6 Slave Address Register (SAR).......................................................................... 252 15.3.7 I2C Bus Transmit Data Register (ICDRT)......................................................... 253 15.3.8 I2C Bus Receive Data Register (ICDRR).......................................................... 253 15.3.9 I2C Bus Shift Register (ICDRS)........................................................................ 253 Operation .......................................................................................................................... 254 15.4.1 I2C Bus Format.................................................................................................. 254 15.4.2 Master Transmit Operation ............................................................................... 255 15.4.3 Master Receive Operation................................................................................. 257 15.4.4 Slave Transmit Operation ................................................................................. 259 15.4.5 Slave Receive Operation................................................................................... 261 15.4.6 Clocked Synchronous Serial Format................................................................. 263 15.4.7 Noise Canceler.................................................................................................. 265 15.4.8 Example of Use................................................................................................. 266 Interrupts........................................................................................................................... 270 Bit Synchronous Circuit.................................................................................................... 271 Usage Notes ...................................................................................................................... 272 15.7.1 Issue (Retransmission) of Start/Stop Conditions .............................................. 272 15.7.2 WAIT Setting in I2C Bus Mode Register (ICMR) ............................................ 272 Rev. 3.00 Sep. 14, 2006 Page xv of xxviii Section 16 A/D Converter ................................................................................. 273 16.1 16.2 16.3 16.4 16.5 16.6 Features............................................................................................................................. 273 Input/Output Pins.............................................................................................................. 275 Register Description ......................................................................................................... 275 16.3.1 A/D Data Registers A to D (ADDRA to ADDRD) .......................................... 275 16.3.2 A/D Control/Status Register (ADCSR) ............................................................ 276 16.3.3 A/D Control Register (ADCR) ......................................................................... 278 Operation .......................................................................................................................... 279 16.4.1 Single Mode...................................................................................................... 279 16.4.2 Scan Mode ........................................................................................................ 279 16.4.3 Input Sampling and A/D Conversion Time ...................................................... 280 16.4.4 External Trigger Input Timing.......................................................................... 281 A/D Conversion Accuracy Definitions ............................................................................. 282 Usage Notes ...................................................................................................................... 284 16.6.1 Permissible Signal Source Impedance .............................................................. 284 16.6.2 Influences on Absolute Accuracy ..................................................................... 284 Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits............................................................................ 285 17.1 17.2 17.3 Features............................................................................................................................. 286 Register Descriptions........................................................................................................ 288 17.2.1 Low-Voltage-Detection Control Register (LVDCR)........................................ 288 17.2.2 Low-Voltage-Detection Status Register (LVDSR)........................................... 290 Operations......................................................................................................................... 291 17.3.1 Power-On Reset Circuit .................................................................................... 291 17.3.2 Low-Voltage Detection Circuit......................................................................... 292 Section 18 Power Supply Circuit ...................................................................... 299 18.1 18.2 When Using Internal Power Supply Step-Down Circuit .................................................. 299 When Not Using Internal Power Supply Step-Down Circuit ........................................... 300 Section 19 List of Registers............................................................................... 301 19.1 19.2 19.3 Register Addresses (Address Order)................................................................................. 302 Register Bits ..................................................................................................................... 306 Register States in Each Operating Mode .......................................................................... 309 Section 20 Electrical Characteristics ................................................................. 313 20.1 20.2 Absolute Maximum Ratings ............................................................................................. 313 Electrical Characteristics (F-ZTATTM Version)................................................................. 314 Rev. 3.00 Sep. 14, 2006 Page xvi of xxviii 20.3 20.4 20.5 20.2.1 Power Supply Voltage and Operating Ranges .................................................. 314 20.2.2 DC Characteristics ............................................................................................ 316 20.2.3 AC Characteristics ............................................................................................ 321 20.2.4 A/D Converter Characteristics .......................................................................... 325 20.2.5 Watchdog Timer Characteristics....................................................................... 326 20.2.6 Power-Supply-Voltage Detection Circuit Characteristics................................. 327 20.2.7 LVDI External Voltage Detection Circuit Characteristics................................ 327 20.2.8 Power-On Reset Characteristics........................................................................ 328 20.2.9 Flash Memory Characteristics .......................................................................... 329 Electrical Characteristics (Masked ROM Version)........................................................... 331 20.3.1 Power Supply Voltage and Operating Ranges .................................................. 331 20.3.2 DC Characteristics ............................................................................................ 333 20.3.3 AC Characteristics ............................................................................................ 338 20.3.4 A/D Converter Characteristics .......................................................................... 342 20.3.5 Watchdog Timer Characteristics....................................................................... 343 20.3.6 Power-Supply-Voltage Detection Circuit Characteristics................................. 344 20.3.7 LVDI External Voltage Detection Circuit Characteristics................................ 344 20.3.8 Power-On Reset Characteristics........................................................................ 345 Operation Timing.............................................................................................................. 346 Output Load Condition ..................................................................................................... 348 Appendix A Instruction Set ...............................................................................349 A.1 A.2 A.3 A.4 Instruction List.................................................................................................................. 349 Operation Code Map......................................................................................................... 364 Number of Execution States ............................................................................................. 367 Combinations of Instructions and Addressing Modes ...................................................... 378 Appendix B I/O Port Block Diagrams ...............................................................379 B.1 B.2 I/O Port Block Diagrams .................................................................................................. 379 Port States in Each Operating State .................................................................................. 394 Appendix C Product Code Lineup.....................................................................395 Appendix D Package Dimensions .....................................................................396 Main Revisions and Additions in this Edition .....................................................399 Index ....................................................................................................................405 Rev. 3.00 Sep. 14, 2006 Page xvii of xxviii Rev. 3.00 Sep. 14, 2006 Page xviii of xxviii Figures Section 1 Figure 1.1 Figure 1.2 Figure 1.3 Figure 1.4 Figure 1.5 Figure 1.6 Overview Internal Block Diagram of H8/36912 Group................................................................. 3 Internal Block Diagram of H8/36902 Group................................................................. 4 Pin Arrangement of H8/36912 Group (FP-32A) ........................................................... 5 Pin Arrangement of H8/36902 Group (FP-32A) ........................................................... 6 Pin Arrangement of H8/36912 Group (FP-32D, 32P4B) .............................................. 7 Pin Arrangement of H8/36902 Group (FP-32D, 32P4B) .............................................. 8 Section 2 CPU Figure 2.1 Memory Map (1) ......................................................................................................... 12 Figure 2.1 Memory Map (2) ......................................................................................................... 13 Figure 2.2 CPU Registers ............................................................................................................. 14 Figure 2.3 Usage of General Registers ......................................................................................... 15 Figure 2.4 Relationship between Stack Pointer and Stack Area ................................................... 16 Figure 2.5 General Register Data Formats (1).............................................................................. 18 Figure 2.5 General Register Data Formats (2).............................................................................. 19 Figure 2.6 Memory Data Formats................................................................................................. 20 Figure 2.7 Instruction Formats...................................................................................................... 31 Figure 2.8 Branch Address Specification in Memory Indirect Mode ........................................... 35 Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 37 Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)..................................... 38 Figure 2.11 CPU Operation States................................................................................................ 39 Figure 2.12 State Transitions ........................................................................................................ 40 Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same Address...................................................................................................................... 41 Section 3 Figure 3.1 Figure 3.2 Figure 3.3 Figure 3.4 Exception Handling Reset Sequence............................................................................................................ 56 Stack Status after Exception Handling ........................................................................ 58 Interrupt Sequence....................................................................................................... 60 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure .............. 61 Section 4 Figure 4.1 Figure 4.2 Figure 4.2 Address Break Block Diagram of Address Break................................................................................ 63 Address Break Interrupt Operation Example (1)......................................................... 67 Address Break Interrupt Operation Example (2)......................................................... 68 Rev. 3.00 Sep. 14, 2006 Page xix of xxviii Section 5 Clock Pulse Generators Figure 5.1 Block Diagram of Clock Pulse Generators.................................................................. 69 Figure 5.2 State Transition of System Clock ................................................................................ 75 Figure 5.3 Flowchart of Clock Switching On-chip Oscillator Clock to External Clock (1) ........ 76 Figure 5.4 Flowchart of Clock Switching External Clock to On-chip Oscillator Clock (2) ......... 77 Figure 5.5 Timing Chart of Switching On-chip Oscillator Clock to External Clock.................... 78 Figure 5.6 Timing Chart to Switch External Clock to On-chip Oscillator Clock ......................... 79 Figure 5.7 Example of Trimming Flow for On-chip Oscillator Frequency .................................. 80 Figure 5.8 Timing Chart of Trimming of On-chip Oscillator Frequency ..................................... 81 Figure 5.9 Example of Connection to Crystal Resonator ............................................................. 82 Figure 5.10 Equivalent Circuit of Crystal Resonator.................................................................... 82 Figure 5.11 Example of Connection to Ceramic Resonator ......................................................... 83 Figure 5.12 Example of External Clock Input .............................................................................. 83 Figure 5.13 Example of Incorrect Board Design .......................................................................... 84 Section 6 Power-Down Modes Figure 6.1 Mode Transition Diagram ........................................................................................... 91 Section 7 Figure 7.1 Figure 7.2 Figure 7.3 Figure 7.4 ROM Flash Memory Block Configuration............................................................................ 98 Programming/Erasing Flowchart Example in User Program Mode.......................... 106 Program/Program-Verify Flowchart ......................................................................... 108 Erase/Erase-Verify Flowchart ................................................................................... 111 Section 9 Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.4 Figure 9.5 Figure 9.6 Figure 9.7 I/O Ports Port 1 Pin Configuration............................................................................................ 117 Port 2 Pin Configuration............................................................................................ 121 Port 5 Pin Configuration............................................................................................ 124 Port 7 Pin Configuration............................................................................................ 128 Port 8 Pin Configuration............................................................................................ 130 Port B Pin Configuration........................................................................................... 134 Port C Pin Configuration........................................................................................... 136 Section 10 Timer B1 Figure 10.1 Block Diagram of Timer B1.................................................................................... 139 Section 11 Figure 11.1 Figure 11.2 Figure 11.3 Figure 11.4 Figure 11.5 Timer V Block Diagram of Timer V ..................................................................................... 146 Increment Timing with Internal Clock .................................................................... 153 Increment Timing with External Clock................................................................... 153 OVF Set Timing ...................................................................................................... 153 CMFA and CMFB Set Timing................................................................................ 154 Rev. 3.00 Sep. 14, 2006 Page xx of xxviii Figure 11.6 TMOV Output Timing ............................................................................................ 154 Figure 11.7 Clear Timing by Compare Match............................................................................ 154 Figure 11.8 Clear Timing by TMRIV Input ............................................................................... 155 Figure 11.9 Pulse Output Example ............................................................................................. 155 Figure 11.10 Example of Pulse Output Synchronized to TRGV Input....................................... 156 Figure 11.11 Contention between TCNTV Write and Clear ...................................................... 157 Figure 11.12 Contention between TCORA Write and Compare Match ..................................... 158 Figure 11.13 Internal Clock Switching and TCNTV Operation ................................................. 158 Section 12 Timer W Figure 12.1 Timer W Block Diagram ......................................................................................... 161 Figure 12.2 Free-Running Counter Operation ............................................................................ 172 Figure 12.3 Periodic Counter Operation..................................................................................... 173 Figure 12.4 0 and 1 Output Example (TOA = 0, TOB = 1)........................................................ 173 Figure 12.5 Toggle Output Example (TOA = 0, TOB = 1) ........................................................ 174 Figure 12.6 Toggle Output Example (TOA = 0, TOB = 1) ........................................................ 174 Figure 12.7 Input Capture Operating Example........................................................................... 175 Figure 12.8 Buffer Operation Example (Input Capture)............................................................. 176 Figure 12.9 PWM Mode Example (1) ........................................................................................ 177 Figure 12.10 PWM Mode Example (2) ...................................................................................... 177 Figure 12.11 Buffer Operation Example (Output Compare) ...................................................... 178 Figure 12.12 PWM Mode Example (TOB, TOC, and TOD = 0: Initial Output Values are Set to 0)............................. 179 Figure 12.13 PWM Mode Example (TOB, TOC, and TOD = 1: Initial Output Values are Set to 1)............................. 180 Figure 12.14 Count Timing for Internal Clock Source ............................................................... 181 Figure 12.15 Count Timing for External Clock Source.............................................................. 181 Figure 12.16 Output Compare Output Timing ........................................................................... 182 Figure 12.17 Input Capture Input Signal Timing........................................................................ 183 Figure 12.18 Timing of Counter Clearing by Compare Match................................................... 183 Figure 12.19 Buffer Operation Timing (Compare Match).......................................................... 184 Figure 12.20 Buffer Operation Timing (Input Capture) ............................................................. 184 Figure 12.21 Timing of IMFA to IMFD Flag Setting at Compare Match .................................. 185 Figure 12.22 Timing of IMFA to IMFD Flag Setting at Input Capture...................................... 186 Figure 12.23 Timing of Status Flag Clearing by CPU................................................................ 186 Figure 12.24 Contention between TCNT Write and Clear ......................................................... 188 Figure 12.25 Internal Clock Switching and TCNT Operation.................................................... 188 Figure 12.26 When Compare Match and Bit Manipulation Instruction to TCRW Occur at the Same Timing ......................................................................................................... 189 Rev. 3.00 Sep. 14, 2006 Page xxi of xxviii Section 13 Watchdog Timer Figure 13.1 Block Diagram of Watchdog Timer ........................................................................ 191 Figure 13.2 Watchdog Timer Operation Example...................................................................... 195 Section 14 Figure 14.1 Figure 14.2 Figure 14.3 Figure 14.4 Serial Communication Interface 3 (SCI3) Block Diagram of SCI3........................................................................................... 198 Block Diagram of Noise Filter Circuit .................................................................... 211 Data Format in Asynchronous Communication ...................................................... 212 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits) ............. 212 Figure 14.5 Sample SCI3 Initialization Flowchart ..................................................................... 213 Figure 14.6 Example of SCI3 Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) ........................................................................... 214 Figure 14.7 Sample Serial Transmission Data Flowchart (Asynchronous Mode)...................... 215 Figure 14.8 Example of SCI3 Reception in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) ........................................................................... 216 Figure 14.9 Sample Serial Reception Data Flowchart (Asynchronous Mode) ........................... 218 Figure 14.10 Data Format in Clocked Synchronous Communication ........................................ 219 Figure 14.11 Example of SCI3 Transmission in Clocked Synchronous Mode .......................... 221 Figure 14.12 Sample Serial Transmission Flowchart (Clocked Synchronous Mode) ................ 222 Figure 14.13 Example of SCI3 Reception in Clocked Synchronous Mode................................ 223 Figure 14.14 Sample Serial Reception Flowchart (Clocked Synchronous Mode)...................... 224 Figure 14.15 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations (Clocked Synchronous Mode)............................................................................... 226 Figure 14.16 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) .......................................... 228 Figure 14.17 Sample Multiprocessor Serial Transmission Flowchart ........................................ 230 Figure 14.18 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 232 Figure 14.18 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 233 Figure 14.19 Example of SCI3 Reception Using Multiprocessor Format (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).............................. 234 Figure 14.20 Receive Data Sampling Timing in Asynchronous Mode ...................................... 237 Section 15 Figure 15.1 Figure 15.2 Figure 15.3 Figure 15.4 Figure 15.5 Figure 15.6 Figure 15.7 I2C Bus Interface 2 (IIC2) Block Diagram of I2C Bus Interface 2..................................................................... 240 External Circuit Connections of I/O Pins ................................................................ 241 I2C Bus Formats ...................................................................................................... 254 I2C Bus Timing........................................................................................................ 254 Master Transmit Mode Operation Timing (1)......................................................... 256 Master Transmit Mode Operation Timing (2)......................................................... 256 Master Receive Mode Operation Timing (1) .......................................................... 258 Rev. 3.00 Sep. 14, 2006 Page xxii of xxviii Figure 15.8 Master Receive Mode Operation Timing (2)........................................................... 259 Figure 15.9 Slave Transmit Mode Operation Timing (1) ........................................................... 260 Figure 15.10 Slave Transmit Mode Operation Timing (2) ......................................................... 261 Figure 15.11 Slave Receive Mode Operation Timing (1)........................................................... 262 Figure 15.12 Slave Receive Mode Operation Timing (2)........................................................... 262 Figure 15.13 Clocked Synchronous Serial Transfer Format....................................................... 263 Figure 15.14 Transmit Mode Operation Timing......................................................................... 264 Figure 15.15 Receive Mode Operation Timing .......................................................................... 265 Figure 15.16 Block Diagram of Noise Canceler......................................................................... 265 Figure 15.17 Sample Flowchart for Master Transmit Mode....................................................... 266 Figure 15.18 Sample Flowchart for Master Receive Mode ........................................................ 267 Figure 15.19 Sample Flowchart for Slave Transmit Mode......................................................... 268 Figure 15.20 Sample Flowchart for Slave Receive Mode .......................................................... 269 Figure 15.21 Timing of Bit Synchronous Circuit ....................................................................... 271 Section 16 Figure 16.1 Figure 16.2 Figure 16.3 Figure 16.4 Figure 16.5 Figure 16.6 A/D Converter Block Diagram of A/D Converter ........................................................................... 274 A/D Conversion Timing .......................................................................................... 280 External Trigger Input Timing ................................................................................ 281 A/D Conversion Accuracy Definitions (1) .............................................................. 283 A/D Conversion Accuracy Definitions (2) .............................................................. 283 Analog Input Circuit Example................................................................................. 284 Section 17 Figure 17.1 Figure 17.2 Figure 17.3 Figure 17.4 Figure 17.5 Figure 17.6 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits Block Diagram around BGR ................................................................................... 286 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit.... 287 Operational Timing of Power-On Reset Circuit...................................................... 292 Operating Timing of LVDR Circuit ........................................................................ 293 Operational Timing of LVDI Circuit....................................................................... 294 Operational Timing of LVDI Circuit (When Compared Voltage is Input through ExtU and ExtD Pins) .......................... 296 Figure 17.7 Timing for Enabling/Disabling of Low-Voltage Detection Circuit......................... 297 Section 18 Power Supply Circuit Figure 18.1 Power Supply Connection when Internal Step-Down Circuit is Used .................... 299 Figure 18.2 Power Supply Connection when Internal Step-Down Circuit is Not Used ............. 300 Section 20 Figure 20.1 Figure 20.2 Figure 20.3 Figure 20.4 Electrical Characteristics System Clock Input Timing..................................................................................... 346 RES Low Width Timing.......................................................................................... 346 Input Timing............................................................................................................ 346 I2C Bus Interface Input/Output Timing ................................................................... 347 Rev. 3.00 Sep. 14, 2006 Page xxiii of xxviii Figure 20.5 SCK3 Input Clock Timing ...................................................................................... 347 Figure 20.6 SCI3 Input/Output Timing in Clocked Synchronous Mode .................................... 348 Figure 20.7 Output Load Circuit ................................................................................................ 348 Appendix Figure B.1 Port 1 Block Diagram (P17) ..................................................................................... 379 Figure B.2 Port 1 Block Diagram (P14) ..................................................................................... 380 Figure B.3 Port 2 Block Diagram (P22) ..................................................................................... 381 Figure B.4 Port 2 Block Diagram (P21) ..................................................................................... 382 Figure B.5 Port 2 Block Diagram (P20) ..................................................................................... 383 Figure B.6 (1) Port 5 Block Diagram (P57, P56) (for H8/36912 Group) ................................... 384 Figure B.6 (2) Port 5 Block Diagram (P57, P56) (for H8/36902 Group) ................................... 385 Figure B.7 Port 5 Block Diagram (P55) ..................................................................................... 386 Figure B.8 Port 5 Block Diagram (P76) ..................................................................................... 387 Figure B.9 Port 7 Block Diagram (P75) ..................................................................................... 388 Figure B.10 Port 7 Block Diagram (P74) ................................................................................... 389 Figure B.11 Port 8 Block Diagram (P84 to P81) ........................................................................ 390 Figure B.12 Port 8 Block Diagram (P80) ................................................................................... 391 Figure B.13 Port B Block Diagram (PB3, PB2) ......................................................................... 392 Figure B.14 Port B Block Diagram (PB1, PB0) ......................................................................... 392 Figure B.15 Port C Block Diagram (PC1).................................................................................. 393 Figure B.16 Port C Block Diagram (PC0).................................................................................. 394 Figure D.1 FP-32D Package Dimensions ................................................................................... 396 Figure D.2 FP-32A Package Dimension..................................................................................... 397 Figure D.3 32P4B Package Dimension ...................................................................................... 398 Rev. 3.00 Sep. 14, 2006 Page xxiv of xxviii Tables Section 1 Overview Table 1.1 Pin Functions ............................................................................................................ 9 Section 2 CPU Table 2.1 Operation Notation ................................................................................................. 21 Table 2.2 Data Transfer Instructions....................................................................................... 22 Table 2.3 Arithmetic Operations Instructions (1) ................................................................... 23 Table 2.3 Arithmetic Operations Instructions (2) ................................................................... 24 Table 2.4 Logic Operations Instructions................................................................................. 25 Table 2.5 Shift Instructions..................................................................................................... 25 Table 2.6 Bit Manipulation Instructions (1)............................................................................ 26 Table 2.6 Bit Manipulation Instructions (2)............................................................................ 27 Table 2.7 Branch Instructions ................................................................................................. 28 Table 2.8 System Control Instructions.................................................................................... 29 Table 2.9 Block Data Transfer Instructions ............................................................................ 30 Table 2.10 Addressing Modes .................................................................................................. 32 Table 2.11 Absolute Address Access Ranges ........................................................................... 34 Table 2.12 Effective Address Calculation (1)........................................................................... 35 Table 2.12 Effective Address Calculation (2)........................................................................... 36 Section 3 Exception Handling Table 3.1 Exception Sources and Vector Address .................................................................. 47 Table 3.2 Interrupt Wait States ............................................................................................... 59 Section 4 Address Break Table 4.1 Access and Data Bus Used ..................................................................................... 65 Section 5 Clock Pulse Generators Table 5.1 Crystal Resonator Parameters ................................................................................. 82 Section 6 Power-Down Modes Table 6.1 Operating Frequency and Wait Time...................................................................... 87 Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling ........ 92 Table 6.3 Internal State in Each Operating Mode................................................................... 92 Section 7 ROM Table 7.1 Setting Programming Modes ................................................................................ 102 Table 7.2 Boot Mode Operation ........................................................................................... 104 Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible ................................................................................................................. 105 Rev. 3.00 Sep. 14, 2006 Page xxv of xxviii Table 7.4 Table 7.5 Table 7.6 Reprogram Data Computation Table .................................................................... 109 Additional-Program Data Computation Table ...................................................... 109 Programming Time ............................................................................................... 109 Section 10 Timer B1 Table 10.1 Timer B1 Operating Modes .................................................................................. 143 Section 11 Timer V Table 11.1 Pin Configuration.................................................................................................. 147 Table 11.2 Clock Signals to Input to TCNTV and Counting Conditions ............................... 149 Section 12 Timer W Table 12.1 Timer W Functions ............................................................................................... 160 Table 12.2 Pin Configuration.................................................................................................. 162 Section 14 Serial Communication Interface 3 (SCI3) Pin Configuration.................................................................................................. 199 Table 14.1 Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode)............ 207 Table 14.3 Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 209 Table 14.4 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode) .............................................................................. 210 Table 14.5 SSR Status Flags and Receive Data Handling ...................................................... 217 Table 14.6 SCI3 Interrupt Requests........................................................................................ 235 Section 15 I2C Bus Interface 2 (IIC2) Table 15.1 Pin Configuration.................................................................................................. 241 Table 15.2 Transfer Rate ........................................................................................................ 244 Table 15.3 Interrupt Requests................................................................................................. 270 Table 15.4 Time for Monitoring SCL..................................................................................... 271 Section 16 A/D Converter Table 16.1 Pin Configuration.................................................................................................. 275 Table 16.2 Analog Input Channels and Corresponding ADDR Registers .............................. 276 Table 16.3 A/D Conversion Time (Single Mode)................................................................... 281 Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits Table 17.1 LVDCR Settings and Select Functions................................................................. 289 Section 20 Electrical Characteristics Table 20.1 Absolute Maximum Ratings ................................................................................. 313 Table 20.2 DC Characteristics (1) .......................................................................................... 316 Table 20.2 DC Characteristics (2) .......................................................................................... 320 Table 20.3 AC Characteristics ................................................................................................ 321 Table 20.4 I2C Bus Interface Timing...................................................................................... 323 Rev. 3.00 Sep. 14, 2006 Page xxvi of xxviii Table 20.5 Table 20.6 Table 20.7 Table 20.8 Table 20.9 Table 20.10 Table 20.11 Table 20.12 Table 20.12 Table 20.13 Table 20.14 Table 20.15 Table 20.16 Table 20.17 Table 20.18 Table 20.19 Table 20.20 Serial Interface (SCI3) Timing ............................................................................. 324 A/D Converter Characteristics .............................................................................. 325 Watchdog Timer Characteristics........................................................................... 326 Power-Supply-Voltage Detection Circuit Characteristics..................................... 327 LVDI External Voltage Detection Circuit Characteristics.................................... 327 Power-On Reset Circuit Characteristics............................................................ 328 Flash Memory Characteristics .......................................................................... 329 DC Characteristics (1)....................................................................................... 333 DC Characteristics (2)....................................................................................... 337 AC Characteristics ............................................................................................ 338 I2C Bus Interface Timing .................................................................................. 340 Serial Interface (SCI3) Timing ......................................................................... 341 A/D Converter Characteristics .......................................................................... 342 Watchdog Timer Characteristics....................................................................... 343 Power-Supply-Voltage Detection Circuit Characteristics................................. 344 LVDI External Voltage Detection Circuit Characteristics................................ 344 Power-On Reset Circuit Characteristics............................................................ 345 Appendix Table A.1 Table A.2 Table A.2 Table A.2 Table A.3 Table A.4 Table A.5 Instruction Set ....................................................................................................... 351 Operation Code Map (1) ....................................................................................... 364 Operation Code Map (2) ....................................................................................... 365 Operation Code Map (3) ....................................................................................... 366 Number of Cycles in Each Instruction.................................................................. 368 Number of Cycles in Each Instruction.................................................................. 369 Combinations of Instructions and Addressing Modes .......................................... 378 Rev. 3.00 Sep. 14, 2006 Page xxvii of xxviii Rev. 3.00 Sep. 14, 2006 Page xxviii of xxviii Section 1 Overview Section 1 Overview 1.1 Features * High-speed H8/300H central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 CPU on an object level Sixteen 16-bit general registers 62 basic instructions * Various peripheral functions Timer B1* (8-bit timer) Timer V (8-bit timer) Timer W (16-bit timer) Watchdog timer SCI3 (Asynchronous or clocked synchronous serial communication interface) 10-bit A/D converter I2C bus interface* (conforms to the Philips I2C bus interface functions) POR/LVD (Power-on reset and low-voltage detection circuits) Address break Note: * Available for the H8/36912 Group only. * On-chip memory Product Classification Type ROM RAM Flash memory version H8/36912F HD64F36912G 8 kbytes 1,536 bytes H8/36902F HD64F36902G 8 kbytes 1,536 bytes H8/36912 HD64336912G 8 kbytes 512 bytes H8/36911 HD64336911G 4 kbytes 256 bytes H8/36902 HD64336902G 8 kbytes 512 bytes H8/36901 HD64336901G 4 kbytes 256 bytes H8/36900 HD64336900G 2 kbytes 256 bytes Remarks TM (F-ZTAT version) Masked ROM version TM Note: F-ZTAT is a trademark of Renesas Technology Corp. Rev. 3.00 Sep. 14, 2006 Page 1 of 408 REJ09B0105-0300 Section 1 Overview * General I/O ports Eighteen I/O pins, including five large-current ports (IOL = 20 mA, @VOL = 1.5 V, -IOH = 4 mA, @VOH = Vcc - 1.0 V) Four input only pins (also used for analog input) * On-chip oscillator Frequency accuracy: 8MHz 1% (Typ.) Vcc = 5.0 V, Ta = 25C (Flash memory version): 8MHz 3% Vcc = 4.0 to 5.0 V, Ta = -20 to 75C 10MHz 4% (Typ.) Vcc = 4.0 to 5.0 V, Ta = -20 to 75C * Supports various power-down modes * Compact package Package Code Body Size Pin Pitch LQFP-32 FP-32A 7.0 x 7.0 mm 0.8 mm SOP-32 FP-32D 11.3 x 20.45 mm 1.27 mm SDIP-32* 32P4B 400 mil 1.78 mm Note: * Flash memory version only Rev. 3.00 Sep. 14, 2006 Page 2 of 408 REJ09B0105-0300 Remarks Section 1 Overview (OSC1) (OSC2) On-chip oscillator CPU H8/300H Timer W SCI3 Port 7 RAM Port 8 Port 2 ROM Timer V IIC2 Timer B1 Watchdog timer A/D converter POR & LVD P84/FTIOD P83/FTIOC P82/FTIOB P81/FTIOA P80/FTCI Port B AVCC PC0/OSC1 PC1/OSC2/CLKOUT Port C P76/TMOV P75/TMCIV P74/TMRIV PB3/AN3/ExtU PB2/AN2/ExtD PB1/AN1 PB0/AN0 P57/SCL P56/SDA P55/WKP5/ADTRG Port 5 P22/TXD P21/RXD P20/SCK3 Port 1 Data bus (lower) P17/IRQ3/TRGV P14/IRQ0 Address bus System clock generator E10T_0* E10T_1* E10T_2* Data bus (upper) NMI TEST RES VCC VCL Internal Block Diagram VSS 1.2 Note: * Can also be used for the E7 or E8 emulator. Figure 1.1 Internal Block Diagram of H8/36912 Group Rev. 3.00 Sep. 14, 2006 Page 3 of 408 REJ09B0105-0300 (OSC1) (OSC2) On-chip oscillator CPU H8/300H Port 7 RAM Timer W SCI3 Timer V Watchdog timer A/D converter POR & LVD Port B AVCC PC0/OSC1 PC1/OSC2/CLKOUT Port C Port 8 Port 2 ROM PB3/AN3/ExtU PB2/AN2/ExtD PB1/AN1 PB0/AN0 P57 P56 P55/WKP5/ADTRG Port 5 P22/TXD P21/RXD P20/SCK3 Port 1 Data bus (lower) P17/IRQ3/TRGV P14/IRQ0 Address bus System clock generator E10T_0* E10T_1* E10T_2* Data bus (upper) NMI TEST RES VCC VCL VSS Section 1 Overview Note: * Can also be used for the E7 or E8 emulator. Figure 1.2 Internal Block Diagram of H8/36902 Group Rev. 3.00 Sep. 14, 2006 Page 4 of 408 REJ09B0105-0300 P76/TMOV P75/TMCIV P74/TMRIV P84/FTIOD P83/FTIOC P82/FTIOB P81/FTIOA P80/FTCI Section 1 Overview P83/FTIOC P82/FTIOB P81/FTIOA P80/FTCI P22/TXD P21/RXD P20/SCK3 P55/WKP5/ADTRG 24 23 22 21 20 19 18 17 Pin Arrangement P84/FTIOD 25 16 P14/IRQ0 P74/TMRIV 26 15 P56/SDA P75/TMCIV 27 14 P57/SCL P76/TMOV 28 13 E10T_2* 12 E10T_1* H8/36912 Group (Top view) 7 8 VCL 9 PC0/OSC1 32 6 PB0/AN0 PC1/OSC2/CLKOUT P17/IRQ3/TRGV 5 10 Vss 31 4 PB1/AN1 TEST E10T_0* 3 11 RES 30 2 PB2/AN2/ExtD Vcc 29 1 PB3/AN3/ExtU AVcc 1.3 NMI Note: * Can also be used for the E7 or E8 emulator. Figure 1.3 Pin Arrangement of H8/36912 Group (FP-32A) Rev. 3.00 Sep. 14, 2006 Page 5 of 408 REJ09B0105-0300 P83/FTIOC P82/FTIOB P81/FTIOA P80/FTCI P22/TXD P21/RXD P20/SCK3 P55/WKP5/ADTRG 24 23 22 21 20 19 18 17 Section 1 Overview P84/FTIOD 25 16 P14/IRQ0 P74/TMRIV 26 15 P56 P75/TMCIV 27 14 P57 P76/TMOV 28 13 E10T_2* 12 E10T_1* H8/36902 Group (Top view) 7 8 PC0/OSC1 VCL 9 6 32 PC1/OSC2/CLKOUT PB0/AN0 5 P17/IRQ3/TRGV Vss 10 4 31 TEST PB1/AN1 3 E10T_0* RES 11 2 30 Vcc PB2/AN2/ExtD 1 29 AVcc PB3/AN3/ExtU NMI Note: * Can also be used for the E7 or E8 emulator. Figure 1.4 Pin Arrangement of H8/36902 Group (FP-32A) Rev. 3.00 Sep. 14, 2006 Page 6 of 408 REJ09B0105-0300 Section 1 Overview PB3/AN3/ExtU 1 32 P76/TMOV PB2/AN2/ExtD 2 31 P75/TMCIV PB1/AN1 3 30 P74/TMRIV PB0/AN0 4 29 P84/FTIOD AVcc 5 28 P83/FTIOC Vcc 6 27 P82/FTIOB RES 7 26 P81/FTIOA TEST 8 H8/36912 Group 25 P80/FTCI Vss 9 (Top view) 24 P22/TXD PC1/OSC2/CLKOUT 10 23 P21/RXD PC0/OSC1 11 22 P20/SCK3 VCL 12 21 P55/WKP5/ADTRG NMI 13 20 P14/IRQ0 P17/IRQ3/TRGV 14 19 P56/SDA E10T_0* 15 18 P57/SCL E10T_1* 16 17 E10T_2* Note: * Can also be used for the E7 or E8 emulator. Figure 1.5 Pin Arrangement of H8/36912 Group (FP-32D, 32P4B) Rev. 3.00 Sep. 14, 2006 Page 7 of 408 REJ09B0105-0300 Section 1 Overview PB3/AN3/ExtU 1 32 P76/TMOV PB2/AN2/ExtD 2 31 P75/TMCIV PB1/AN1 3 30 P74/TMRIV PB0/AN0 4 29 P84/FTIOD AVcc 5 28 P83/FTIOC Vcc 6 27 P82/FTIOB RES 7 26 P81/FTIOA TEST 8 H8/36902 Group 25 P80/FTCI Vss 9 (Top view) 24 P22/TXD PC1/OSC2/CLKOUT 10 23 P21/RXD PC0/OSC1 11 22 P20/SCK3 VCL 12 21 P55/WKP5/ADTRG NMI 13 20 P14/IRQ0 P17/IRQ3/TRGV 14 19 P56 E10T_0* 15 18 P57 E10T_1* 16 17 E10T_2* Note: * Can also be used for the E7 or E8 emulator. Figure 1.6 Pin Arrangement of H8/36902 Group (FP-32D, 32P4B) Rev. 3.00 Sep. 14, 2006 Page 8 of 408 REJ09B0105-0300 Section 1 Overview 1.4 Table 1.1 Pin Functions Pin Functions Pin No. Type Symbol FP-32D, 32P4B FP-32A I/O Functions Power source VCC 6 2 Input Power supply pin. Connect this pin to the system power supply. VSS 9 5 Input Ground pin. Connect this pin to the system power supply (0 V). AVCC 5 1 Input Analog power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply. VCL 12 8 Input Internal step-down power supply pin. Connect a capacitor of around 0.1 F between this pin and the Vss pin for stabilization. OSC1 11 7 Input OSC2/ CLKOUT 10 6 Output These pins are connected to a crystal or ceramic resonator for system clocks, or can be used to input an external clock. When an on-chip oscillator is used, system clocks can be output to OSC2. See section 5, Clock Pulse Generators, for a typical connection. RES 7 3 Input Reset pin. The pull-up resistor (typ. 150 k) is incorporated. When driven low, the chip is reset. TEST 8 4 Input Test pin. Connect this pin to Vss. NMI 13 9 Input Non-maskable interrupt request input pin. Be sure to pull-up by a pull-up resistor. IRQ0, IRQ3 20, 14 16, 10 Input External interrupt request input pins. Can select the rising or falling edge. WKP5 21 17 Input External interrupt request input pin. Can select the rising or falling edge. Clock System control External interrupt Rev. 3.00 Sep. 14, 2006 Page 9 of 408 REJ09B0105-0300 Section 1 Overview Pin No. Type Symbol FP-32D, 32P4B FP-32A I/O Functions Timer V TMOV 32 28 Output TMOV is an output pin for waveforms generated by the output compare function. TMCIV 31 27 Input External event input pin TMRIV 30 26 Input Counter reset input pin TRGV 14 10 Input Counter start trigger input pin FTCI 25 21 Input External event input pin FTIOA to FTIOD 26 to 29 22 to 25 I/O Output compare output/ input capture input/ PWM output common pins SDA 19 15 I/O I2C data I/O pin. NMOS open drain output can directly drive the bus. SCL 18 14 I/O I2C clock I/O pin. NMOS open drain output can directly drive the bus. TXD 24 20 Output Transmit data output pin RXD 23 19 Input Receive data input pin SCK3 22 18 I/O Clock I/O pin AN3 to AN0 1 to 4 29 to 32 Input Analog input pin ADTRG 21 17 Input A/D converter trigger input pin P17, P14 14, 20 10, 16 I/O 2-bit I/O port P22 to P20 24 to 22 20 to 18 I/O 3-bit I/O port P57 to P55 18, 19, 21 14, 15, 17 I/O 3-bit I/O port P76 to P74 32 to 30 28 to 26 I/O 3-bit I/O port P84 to P80 29 to 25 25 to 21 I/O 5-bit I/O port PB3 to PB0 1 to 4 29 to 32 Input 4-bit input port PC1, PC0 10, 11 6, 7 I/O 2-bit I/O port Low voltage detection circuit ExtU, ExtD 1, 2 29, 30 Input External input pins for the detection voltage used in the low-voltage detection circuit E7, E8 E10T_0, E10T_1, E10T_2 15, 16, 17 11, 12, 13 Timer W I2C bus interface 2* Serial communication interface A/D converter I/O ports Note: * Available for the H8/36912 Group only. Rev. 3.00 Sep. 14, 2006 Page 10 of 408 REJ09B0105-0300 Interface pins for the E7 or E8 emulator Section 2 CPU Section 2 CPU This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU, and supports only normal mode, which has a 64-kbyte address space. * Upward-compatible with H8/300 CPUs Can execute H8/300 CPUs object programs Additional eight 16-bit extended registers 32-bit transfer and arithmetic and logic instructions are added Signed multiply and divide instructions are added. * General-register architecture Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers * Sixty-two basic instructions 8/16/32-bit data transfer and arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:24,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 64-kbyte address space * High-speed operation All frequently-used instructions execute in two or four states 8/16/32-bit register-register add/subtract : 2 state 8 x 8-bit register-register multiply : 14 states 16 / 8-bit register-register divide : 14 states 16 x 16-bit register-register multiply : 22 states 32 / 16-bit register-register divide : 22 states * Power-down state Transition to power-down state by SLEEP instruction CPU30H2E_000120030300 Rev. 3.00 Sep. 14, 2006 Page 11 of 408 REJ09B0105-0300 Section 2 CPU 2.1 Address Space and Memory Map The address space of this LSI is 64 kbytes, which includes the program area and the data area. The following two figures show the memory map, respectively. H8/36912F H8/36902F (Flash memory version) H'0000 H'0045 H'0046 Interrupt vector H8/36912 H8/36902 (Masked ROM version) H'0000 H'0045 H'0046 Interrupt vector On-chip ROM (8 kbytes) On-chip ROM (8 kbytes) H'1FFF H'2000 H'2FFF H'1FFF E7 or E8 control program area (4 kbytes) Not used Not used H'F600 H'F77F Internal I/O register H'F600 H'F77F Internal I/O register Not used H'F980 H'FD7F H'FD80 (E7 or E8 work area, for flash memory programming: 1 kbyte) On-chip RAM (1.5 kbytes) Not used H'FD80 On-chip RAM user area (512 bytes) H'FF7F H'FF80 On-chip RAM user area (512 bytes) H'FF7F H'FF80 Internal I/O register H'FFFF Internal I/O register H'FFFF Figure 2.1 Memory Map (1) Rev. 3.00 Sep. 14, 2006 Page 12 of 408 REJ09B0105-0300 Section 2 CPU H8/36911 H8/36901 (Masked ROM version) H'0000 H'0045 H'0046 Interrupt vector H8/36900 (Masked ROM version) H'0000 H'0045 H'0046 Interrupt vector On-chip ROM (2 kbytes) On-chip ROM (4 kbytes) H'07FF H'0FFF Not used Not used H'F600 H'F77F Internal I/O register H'F600 H'F77F Internal I/O register Not used Not used H'FE80 H'FE80 On-chip RAM user area (256 bytes) H'FF7F H'FF80 On-chip RAM user area (256 bytes) H'FF7F H'FF80 Internal I/O register H'FFFF Internal I/O register H'FFFF Figure 2.1 Memory Map (2) Rev. 3.00 Sep. 14, 2006 Page 13 of 408 REJ09B0105-0300 Section 2 CPU 2.2 Register Configuration The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition code register (CCR). General registers (ERn) 15 0 7 0 7 0 ER0 E0 R0H R0L ER1 E1 R1H R1L ER2 E2 R2H R2L ER3 E3 R3H R3L ER4 E4 R4H R4L ER5 E5 R5H R5L ER6 E6 R6H R6L ER7 (SP) E7 R7H R7L Control registers (CR) 23 0 PC 7 6 5 4 3 2 1 0 CCR I UI H U N Z V C [Legend] Stack pointer SP: Program counter PC: CCR: Condition-code register Interrupt mask bit I: User bit UI: H: U: N: Z: V: C: Figure 2.2 CPU Registers Rev. 3.00 Sep. 14, 2006 Page 14 of 408 REJ09B0105-0300 Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag Section 2 CPU 2.2.1 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8-bit registers. The usage of each register can be selected independently. * Address registers * 32-bit registers * 16-bit registers * 8-bit registers E registers (extended registers) (E0 to E7) ER registers (ER0 to ER7) RH registers (R0H to R7H) R registers (R0 to R7) RL registers (R0L to R7L) Figure 2.3 Usage of General Registers Rev. 3.00 Sep. 14, 2006 Page 15 of 408 REJ09B0105-0300 Section 2 CPU General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.4 shows the stack. Free area SP (ER7) Stack area Figure 2.4 Relationship between Stack Pointer and Stack Area 2.2.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0). The PC is initialized when the start address is loaded by the vector address generated during reset exception-handling sequence. 2.2.3 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. The I bit is initialized to 1 by reset exception-handling sequence, but other bits are not initialized. Some instructions leave flag bits unchanged. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. For the action of each instruction on the flag bits, see appendix A.1, Instruction List. Rev. 3.00 Sep. 14, 2006 Page 16 of 408 REJ09B0105-0300 Section 2 CPU Bit Bit Name Initial Value R/W Description 7 I 1 R/W Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. 6 UI Undefined R/W User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. 5 H Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 U Undefined R/W User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. 3 N Undefined R/W Negative Flag Stores the value of the most significant bit of data as a sign bit. 2 Z Undefined R/W Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 1 V Undefined R/W Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. 0 C Undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * Add instructions, to indicate a carry * Subtract instructions, to indicate a borrow * Shift and rotate instructions, to indicate a carry The carry flag is also used as a bit accumulator by bit manipulation instructions. Rev. 3.00 Sep. 14, 2006 Page 17 of 408 REJ09B0105-0300 Section 2 CPU 2.3 Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.3.1 General Register Data Formats Figure 2.5 shows the data formats in general registers. Data Type General Register Data Format 7 RnH 1-bit data 0 Don't care 7 6 5 4 3 2 1 0 7 1-bit data RnL 4-bit BCD data RnH 4-bit BCD data RnL Byte data RnH Don't care 7 4 3 Upper 0 7 6 5 4 3 2 1 0 0 Lower Don't care 7 Don't care 7 4 3 Upper 0 Don't care MSB LSB 7 Byte data RnL Figure 2.5 General Register Data Formats (1) REJ09B0105-0300 0 Don't care MSB Rev. 3.00 Sep. 14, 2006 Page 18 of 408 0 Lower LSB Section 2 CPU Data Type General Register Word data Rn Data Format 15 Word data MSB En 15 MSB Longword data 0 LSB 0 LSB ERn 31 16 15 MSB 0 LSB [Legend] ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.5 General Register Data Formats (2) Rev. 3.00 Sep. 14, 2006 Page 19 of 408 REJ09B0105-0300 Section 2 CPU 2.3.2 Memory Data Formats Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. This also applies to instruction fetches. When ER7 (SP) is used as an address register to access the stack, the operand size should be word or longword. Data Type Address Data Format 7 1-bit data Address L 7 Byte data Address L MSB Word data Address 2M MSB 0 6 5 4 3 2 Address 2N 0 LSB LSB Address 2M+1 Longword data 1 MSB Address 2N+1 Address 2N+2 Address 2N+3 Figure 2.6 Memory Data Formats Rev. 3.00 Sep. 14, 2006 Page 20 of 408 REJ09B0105-0300 LSB Section 2 CPU 2.4 Instruction Set 2.4.1 Table of Instructions Classified by Function The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined below. Table 2.1 Symbol Operation Notation Description Rd General register (destination)* Rs General register (source)* Rn General register* ERn General register (32-bit register or address register) (EAd) Destination operand (EAs) Source operand CCR Condition-code register N N (negative) flag in CCR Z Z (zero) flag in CCR V V (overflow) flag in CCR C C (carry) flag in CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Addition - Subtraction x Multiplication / Division Logical AND Logical OR Logical XOR Move NOT (logical complement) Rev. 3.00 Sep. 14, 2006 Page 21 of 408 REJ09B0105-0300 Section 2 CPU Symbol Description :3/:8/:16/:24 3-, 8-, 16-, or 24-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers/address registers (ER0 to ER7). Table 2.2 Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B (EAs) Rd, Cannot be used in this LSI. MOVTPE B Rs (EAs) Cannot be used in this LSI. POP W/L @SP+ Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. PUSH W/L Rn @-SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP. Note: * Refers to the operand size. B: Byte W: Word L: Longword Rev. 3.00 Sep. 14, 2006 Page 22 of 408 REJ09B0105-0300 Section 2 CPU Table 2.3 Arithmetic Operations Instructions (1) Instruction Size* Function ADD SUB B/W/L Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) ADDX SUBX B Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register. INC DEC B/W/L Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) ADDS SUBS L Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. DAA DAS B Rd decimal adjust Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. MULXU B/W Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. MULXS B/W Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. DIVXU B/W Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. Note: * Refers to the operand size. B: Byte W: Word L: Longword Rev. 3.00 Sep. 14, 2006 Page 23 of 408 REJ09B0105-0300 Section 2 CPU Table 2.3 Arithmetic Operations Instructions (2) Instruction Size* Function DIVXS B/W Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. CMP B/W/L Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. NEG B/W/L 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. EXTU W/L Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. EXTS W/L Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. Note: * Refers to the operand size. B: Byte W: Word L: Longword Rev. 3.00 Sep. 14, 2006 Page 24 of 408 REJ09B0105-0300 Section 2 CPU Table 2.4 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. XOR B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. NOT B/W/L (Rd) (Rd) Takes the one's complement of general register contents. Note: * Refers to the operand size. B: Byte W: Word L: Longword Table 2.5 Shift Instructions Instruction Size* Function SHAL SHAR B/W/L Rd (shift) Rd Performs an arithmetic shift on general register contents. SHLL SHLR B/W/L Rd (shift) Rd Performs a logical shift on general register contents. ROTL ROTR B/W/L Rd (rotate) Rd Rotates general register contents. ROTXL ROTXR B/W/L Rd (rotate) Rd Rotates general register contents through the carry flag. Note: * Refers to the operand size. B: Byte W: Word L: Longword Rev. 3.00 Sep. 14, 2006 Page 25 of 408 REJ09B0105-0300 Section 2 CPU Table 2.6 Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 (<bit-No.> of <EAd>) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 (<bit-No.> of <EAd>) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BNOT B (<bit-No.> of <EAd>) (<bit-No.> of <EAd>) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BTST B (<bit-No.> of <EAd>) Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BAND B C (<bit-No.> of <EAd>) C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIAND B C (<bit-No.> of <EAd>) C ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BOR B C (<bit-No.> of <EAd>) C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIOR B C (<bit-No.> of <EAd>) C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. Note: * Refers to the operand size. B: Byte Rev. 3.00 Sep. 14, 2006 Page 26 of 408 REJ09B0105-0300 Section 2 CPU Table 2.6 Bit Manipulation Instructions (2) Instruction Size* Function BXOR B C (<bit-No.> of <EAd>) C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C (<bit-No.> of <EAd>) C XORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B (<bit-No.> of <EAd>) C Transfers a specified bit in a general register or memory operand to the carry flag. BILD B (<bit-No.> of <EAd>) C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. BST B C (<bit-No.> of <EAd>) Transfers the carry flag value to a specified bit in a general register or memory operand. BIST B C (<bit-No.> of <EAd>) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data. Note: * Refers to the operand size. B: Byte Rev. 3.00 Sep. 14, 2006 Page 27 of 408 REJ09B0105-0300 Section 2 CPU Table 2.7 Branch Instructions Instruction Size Function Bcc* -- Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA(BT) Always (true) Always BRN(BF) Never (false) Never BHI High CZ=0 BLS Low or same CZ=1 BCC(BHS) Carry clear (high or same) C=0 BCS(BLO) Carry set (low) C=1 BNE Not equal Z=0 BEQ Equal Z=1 BVC Overflow clear V=0 BVS Overflow set V=1 BPL Plus N=0 BMI Minus N=1 BGE Greater or equal NV=0 BLT Less than NV=1 BGT Greater than Z(N V) = 0 BLE Less or equal Z(N V) = 1 JMP -- Branches unconditionally to a specified address. BSR -- Branches to a subroutine at a specified address. JSR -- Branches to a subroutine at a specified address. RTS -- Returns from a subroutine Note: * Bcc is the general name for conditional branch instructions. Rev. 3.00 Sep. 14, 2006 Page 28 of 408 REJ09B0105-0300 Section 2 CPU Table 2.8 System Control Instructions Instruction Size* Function TRAPA -- Starts trap-instruction exception handling. RTE -- Returns from an exception-handling routine. SLEEP -- Causes a transition to a power-down state. LDC B/W (EAs) CCR Moves the source operand contents to the CCR. The CCR size is one byte, but in transfer from memory, data is read by word access. STC B/W CCR (EAd), EXR (EAd) Transfers the CCR contents to a destination location. The condition code register size is one byte, but in transfer to memory, data is written by word access. ANDC B CCR #IMM CCR, EXR #IMM EXR Logically ANDs the CCR with immediate data. ORC B CCR #IMM CCR, EXR #IMM EXR Logically ORs the CCR with immediate data. XORC B CCR #IMM CCR, EXR #IMM EXR Logically XORs the CCR with immediate data. NOP -- PC + 2 PC Only increments the program counter. Note: * Refers to the operand size. B: Byte W: Word Rev. 3.00 Sep. 14, 2006 Page 29 of 408 REJ09B0105-0300 Section 2 CPU Table 2.9 Block Data Transfer Instructions Instruction Size Function EEPMOV.B -- if R4L 0 then Repeat @ER5+ @ER6+, R4L-1 R4L Until R4L = 0 else next; EEPMOV.W -- if R4 0 then Repeat @ER5+ @ER6+, R4-1 R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. 2.4.2 Basic Instruction Formats H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.7 shows examples of instruction formats. (1) Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. (2) Register Field Specifies a general register. Address registers are specified by 3 bits, and data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. Rev. 3.00 Sep. 14, 2006 Page 30 of 408 REJ09B0105-0300 Section 2 CPU (3) Effective Address Extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A24-bit address or displacement is treated as a 32-bit data in which the first 8 bits are 0 (H'00). (4) Condition Field Specifies the branching condition of Bcc instructions. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rm rn ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op rn rm MOV.B @(d:16, Rn), Rm EA(disp) (4) Operation field, effective address extension, and condition field op cc EA(disp) BRA d:8 Figure 2.7 Instruction Formats Rev. 3.00 Sep. 14, 2006 Page 31 of 408 REJ09B0105-0300 Section 2 CPU 2.5 Addressing Modes and Effective Address Calculation The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the generated 24-bit address, so the effective address is 16 bits. 2.5.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses a subset of these addressing modes. Addressing modes that can be used differ depending on the instruction. For details, refer to appendix A.4, Combinations of Instructions and Addressing Modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or the absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.10 Addressing Modes No. Addressing Mode Symbol 1 Register direct Rn 2 Register indirect @ERn 3 Register indirect with displacement @(d:16,ERn)/@(d:24,ERn) 4 Register indirect with post-increment Register indirect with pre-decrement @ERn+ @-ERn 5 Absolute address @aa:8/@aa:16/@aa:24 6 Immediate #xx:8/#xx:16/#xx:32 7 Program-counter relative @(d:8,PC)/@(d:16,PC) 8 Memory indirect @@aa:8 (1) Register Direct--Rn The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. Rev. 3.00 Sep. 14, 2006 Page 32 of 408 REJ09B0105-0300 Section 2 CPU (2) Register Indirect--@ERn The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of the operand on memory. (3) Register Indirect with Displacement--@(d:16, ERn) or @(d:24, ERn) A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the lower 24 bits of the sum the address of a memory operand. A 16-bit displacement is sign-extended when added. (4) Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn * Register indirect with post-increment--@ERn+ The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. For the word or longword access, the register value should be even. * Register indirect with pre-decrement--@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the lower 24 bits of the result is the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. For the word or longword access, the register value should be even. (5) Absolute Address--@aa:8, @aa:16, @aa:24 The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24) For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the entire address space. The access ranges of absolute addresses for the group of this LSI are those shown in table 2.11, because the upper 8 bits are ignored. Rev. 3.00 Sep. 14, 2006 Page 33 of 408 REJ09B0105-0300 Section 2 CPU Table 2.11 Absolute Address Access Ranges Absolute Address Access Range 8 bits (@aa:8) H'FF00 to H'FFFF 16 bits (@aa:16) H'0000 to H'FFFF 24 bits (@aa:24) H'0000 to H'FFFF (6) Immediate--#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. (7) Program-Counter Relative--@(d:8, PC) or @(d:16, PC) This mode is used in the BSR instruction. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. (8) Memory Indirect--@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The memory operand is accessed by longword access. The first byte of the memory operand is ignored, generating a 24-bit branch address. Figure 2.8 shows how to specify branch address for in memory indirect mode. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF). Note that the first part of the address range is also the exception vector area. Rev. 3.00 Sep. 14, 2006 Page 34 of 408 REJ09B0105-0300 Section 2 CPU Specified by @aa:8 Dummy Branch address Figure 2.8 Branch Address Specification in Memory Indirect Mode 2.5.2 Effective Address Calculation Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI, the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address. Table 2.12 Effective Address Calculation (1) No 1 Addressing Mode and Instruction Format op 2 Effective Address Calculation Effective Address (EA) Register direct(Rn) rm Operand is general register contents. rn Register indirect(@ERn) 0 31 23 0 23 0 23 0 23 0 General register contents op 3 r Register indirect with displacement @(d:16,ERn) or @(d:24,ERn) 0 31 General register contents op r disp 0 31 Sign extension 4 Register indirect with post-increment or pre-decrement *Register indirect with post-increment @ERn+ op 31 0 General register contents r *Register indirect with pre-decrement @-ERn disp 1, 2, or 4 31 0 General register contents op r 1, 2, or 4 The value to be added or subtracted is 1 when the operand is byte size, 2 for word size, and 4 for longword size. Rev. 3.00 Sep. 14, 2006 Page 35 of 408 REJ09B0105-0300 Section 2 CPU Table 2.12 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address @aa:8 8 7 23 op abs 0 H'FFFF @aa:16 23 op abs 16 15 0 Sign extension @aa:24 op 0 23 abs 6 Immediate #xx:8/#xx:16/#xx:32 op 7 Operand is immediate data. IMM 0 23 Program-counter relative PC contents @(d:8,PC) @(d:16,PC) op disp 23 0 Sign extension 8 disp 23 0 Memory indirect @@aa:8 8 7 23 op abs 0 abs H'0000 15 0 Memory contents [Legend] r, rm,rn : op : disp : IMM : abs : Register field Operation field Displacement Immediate data Absolute address Rev. 3.00 Sep. 14, 2006 Page 36 of 408 REJ09B0105-0300 23 16 15 H'00 0 Section 2 CPU 2.6 Basic Bus Cycle CPU operation is synchronized by a system clock (). The period from a rising edge of to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 Access to On-Chip Memory (RAM, ROM) Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access in byte or word size. Figure 2.9 shows the on-chip memory access cycle. Bus cycle T2 state T1 state Internal address bus Address Internal read signal Internal data bus (read access) Read data Internal write signal Internal data bus (write access) Write data Figure 2.9 On-Chip Memory Access Cycle Rev. 3.00 Sep. 14, 2006 Page 37 of 408 REJ09B0105-0300 Section 2 CPU 2.6.2 On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width and number of accessing states of each register, refer to section 19.1, Register Addresses (Address Order). Registers with 16-bit data bus width can be accessed by word size only. Registers with 8-bit data bus width can be accessed by byte or word size. When a register with 8-bit data bus width is accessed by word size, a bus cycle occurs twice. In two-state access, the operation timing is the same as that for on-chip memory. Figure 2.10 shows the operation timing in the case of three-state access to an on-chip peripheral module. Bus cycle T1 state T2 state T3 state Internal address bus Address Internal read signal Internal data bus (read access) Read data Internal write signal Internal data bus (write access) Write data Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access) Rev. 3.00 Sep. 14, 2006 Page 38 of 408 REJ09B0105-0300 Section 2 CPU 2.7 CPU States There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active mode. In the program halt state there are a sleep mode, and standby mode. These states are shown in figure 2.11. Figure 2.12 shows the state transitions. For details on program execution state and program halt state, refer to section 6, Power-Down Modes. For details on exception processing, refer to section 3, Exception Handling. CPU state Reset state The CPU is initialized Program execution state Active (high speed) mode The CPU executes successive program instructions at high speed, synchronized by the system clock Program halt state A state in which some or all of the chip functions are stopped to conserve power Sleep mode Power-down modes Standby mode Exceptionhandling state A transient state in which the CPU changes the processing flow due to a reset or an interrupt Figure 2.11 CPU Operation States Rev. 3.00 Sep. 14, 2006 Page 39 of 408 REJ09B0105-0300 Section 2 CPU Reset cleared Reset state Exception-handling state Reset occurs Reset occurs Reset occurs Interrupt source Program halt state Interrupt source Exceptionhandling complete Program execution state SLEEP instruction executed Figure 2.12 State Transitions 2.8 Usage Notes 2.8.1 Notes on Data Access to Empty Areas The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to the user. When data is transferred from CPU to empty areas, the transferred data will be lost. This action may also cause the CPU to malfunction. When data is transferred from an empty area to CPU, the contents of the data cannot be guaranteed. 2.8.2 EEPMOV Instruction EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L, which starts from the address indicated by R5, to the address indicated by R6. Set R4L and R6 so that the end address of the destination address (value of R6 + R4L) does not exceed H'FFFF (the value of R6 must not change from H'FFFF to H'0000 during execution). 2.8.3 Bit Manipulation Instruction The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in byte units, manipulate the data of the target bit, and write data to the same address again in byte units. Special care is required when using these instructions in cases where two registers are assigned to the same address or when a bit is directly manipulated for a port, because this may rewrite data of a bit other than the bit to be manipulated. Rev. 3.00 Sep. 14, 2006 Page 40 of 408 REJ09B0105-0300 Section 2 CPU (1) Bit Manipulation for Two Registers Assigned to the Same Address Example 1: Bit manipulation for the timer load register and timer counter (Applicable to timer B1, not available for the H8/36902 Group.) Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same address. When a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations takes place. 1. Data is read in byte units. 2. The CPU sets or resets the bit to be manipulated with the bit manipulation instruction. 3. The written data is written again in byte units to the timer load register. The timer is counting, so the value read is not necessarily the same as the value in the timer load register. As a result, bits other than the intended bit in the timer counter may be modified and the modified value may be written to the timer load register. Read Count clock Timer counter Reload Write Timer load register Internal bus Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same Address Rev. 3.00 Sep. 14, 2006 Page 41 of 408 REJ09B0105-0300 Section 2 CPU Example 2: The BSET instruction is executed for port 5. P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level signal at P50 with a BSET instruction is shown below. [Prior to executing BSET] P57 P56 P55 P54 P53 P52 P51 P50 Input/output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level Low level PCR5 0 0 1 1 1 1 1 1 PDR5 1 0 0 0 0 0 0 0 [BSET instruction executed] BSET #0, @PDR5 The BSET instruction is executed for port 5. [After executing BSET] P57 P56 P55 P54 P53 P52 P51 P50 Input/output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level High level PCR5 0 0 1 1 1 1 1 1 PDR5 0 1 0 0 0 0 0 1 [Description on operation] 1. When the BSET instruction is executed, first the CPU reads port 5. Since P57 and P56 are input pins, the CPU reads the pin states (low-level and high-level input). P55 to P50 are output pins, so the CPU reads the value in PDR5. In this example PDR5 has a value of H'80, but the value read by the CPU is H'40. 2. Next, the CPU sets bit 0 of the read data to 1, changing the PDR5 data to H'41. 3. Finally, the CPU writes H'41 to PDR5, completing execution of BSET. Rev. 3.00 Sep. 14, 2006 Page 42 of 408 REJ09B0105-0300 Section 2 CPU As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level signal. However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem, store a copy of the PDR5 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR5. [Prior to executing BSET] MOV.B MOV.B MOV.B #80, R0L, R0L, R0L @RAM0 @PDR5 The PDR5 value (H'80) is written to a work area in memory (RAM0) as well as to PDR5. P57 P56 P55 P54 P53 P52 P51 P50 Input/output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level Low level PCR5 0 0 1 1 1 1 1 1 PDR5 1 0 0 0 0 0 0 0 RAM0 1 0 0 0 0 0 0 0 [BSET instruction executed] BSET #0, @RAM0 The BSET instruction is executed designating the PDR5 work area (RAM0). [After executing BSET] MOV.B MOV.B @RAM0, R0L R0L, @PDR5 The work area (RAM0) value is written to PDR5. P57 P56 P55 P54 P53 P52 P51 P50 Input/output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level High level PCR5 0 0 1 1 1 1 1 1 PDR5 1 0 0 0 0 0 0 1 RAM0 1 0 0 0 0 0 0 1 Rev. 3.00 Sep. 14, 2006 Page 43 of 408 REJ09B0105-0300 Section 2 CPU (2) Bit Manipulation in a Register Containing a Write-Only Bit Example 3: BCLR instruction executed designating port 5 control register PCR5 P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be input to this input pin. [Prior to executing BCLR] P57 P56 P55 P54 P53 P52 P51 P50 Input/output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level Low level PCR5 0 0 1 1 1 1 1 1 PDR5 1 0 0 0 0 0 0 0 [BCLR instruction executed] BCLR #0, @PCR5 The BCLR instruction is executed for PCR5. [After executing BCLR] P57 P56 P55 P54 P53 P52 P51 P50 Input/output Output Output Output Output Output Output Output Input Pin state Low level High level Low level Low level Low level Low level Low level High level PCR5 1 1 1 1 1 1 1 0 PDR5 1 0 0 0 0 0 0 0 [Description on operation] 1. When the BCLR instruction is executed, first the CPU reads PCR5. Since PCR5 is a write-only register, the CPU reads a value of H'FF, even though the PCR5 value is actually H'3F. 2. Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE. 3. Finally, H'FE is written to PCR5 and BCLR instruction execution ends. Rev. 3.00 Sep. 14, 2006 Page 44 of 408 REJ09B0105-0300 Section 2 CPU As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However, bits 7 and 6 in PCR5 change to 1, so that P57 and P56 change from input pins to output pins. To prevent this problem, store a copy of the PCR5 data in a work area in memory and manipulate data of the bit in the work area, then write this data to PCR5. [Prior to executing BCLR] MOV.B MOV.B MOV.B #3F, R0L, R0L, R0L @RAM0 @PCR5 The PCR5 value (H'3F) is written to a work area in memory (RAM0) as well as to PCR5. P57 P56 P55 P54 P53 P52 P51 P50 Input/output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level Low level PCR5 0 0 1 1 1 1 1 1 PDR5 1 0 0 0 0 0 0 0 RAM0 0 0 1 1 1 1 1 1 [BCLR instruction executed] BCLR #0, @RAM0 The BCLR instructions executed for the PCR5 work area (RAM0). [After executing BCLR] MOV.B MOV.B @RAM0, R0L R0L, @PCR5 The work area (RAM0) value is written to PCR5. P57 P56 P55 P54 P53 P52 P51 P50 Input/output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level High level PCR5 0 0 1 1 1 1 1 0 PDR5 1 0 0 0 0 0 0 0 RAM0 0 0 1 1 1 1 1 0 Rev. 3.00 Sep. 14, 2006 Page 45 of 408 REJ09B0105-0300 Section 2 CPU Rev. 3.00 Sep. 14, 2006 Page 46 of 408 REJ09B0105-0300 Section 3 Exception Handling Section 3 Exception Handling Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts. * Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES pin. The chip is also reset when the watchdog timer overflows, and exception handling starts. Exception handling is the same as exception handling by the RES pin. * Trap Instruction Exception handling starts when a trap instruction (TRAPA) is executed. The TRAPA instruction generates a vector address corresponding to a vector number from 0 to 3, as specified in the instruction code. Exception handling can be executed at all times in the program execution state. * Interrupts External interrupts other than NMI and internal interrupts other than address break are masked by the I bit in CCR, and kept masked while the I bit is set to 1. Exception handling starts when the current instruction or exception handling ends, if an interrupt request has been issued. 3.1 Exception Sources and Vector Address Table 3.1 shows the vector addresses and priority of each exception handling. When more than one interrupt is requested, handling is performed from the interrupt with the highest priority. Table 3.1 Exception Sources and Vector Address Relative Module Exception Sources Vector Number Vector Address Priority RES pin Reset 0 H'0000 to H'0001 High Reserved for system use 1 to 6 H'0002 to H'000D External interrupt pin NMI 7 H'000E to H'000F CPU Trap instruction #0 8 H'0010 to H'0011 Trap instruction #1 9 H'0012 to H'0013 Trap instruction #2 10 H'0014 to H'0015 Trap instruction #3 11 H'0016 to H'0017 Watchdog timer Low Rev. 3.00 Sep. 14, 2006 Page 47 of 408 REJ09B0105-0300 Section 3 Exception Handling Relative Module Exception Sources Vector Number Vector Address Priority Address break Break conditions satisfied 12 H'0018 to H'0019 High CPU Direct transition by executing the SLEEP instruction 13 H'001A to H'001B External interrupt pin IRQ0, low-voltage detection interrupt 14 H'001C to H'001D Reserved for system use 15, 16 H'001E to H'0021 External interrupt pin IRQ3 17 H'0022 to H'0023 WKP 18 H'0024 to H'0025 Reserved for system use 19, 20 H'0026 to H'0029 Timer W Timer W input capture A/ compare match A Timer W input capture B/ compare match B Timer W input capture C/ compare match C Timer W input capture D/ compare match D Timer W overflow 21 H'002A to H'002B Timer V Timer V compare match A Timer V compare match B Timer V overflow 22 H'002C to H'002D SCI3 SCI3 receive data full SCI3 transmit data empty SCI3 transmit end SCI3 receive error 23 H'002E to H'002F IIC2* IIC_2 transmit data empty IIC_2 transmit end IIC_2 receive error 24 H'0030 to H'0031 A/D converter A/D conversion end 25 H'0032 to H'0033 Reserved for system use 26 to 28 H'0034 to H'0039 Timer B1* Timer B1 overflow 29 H'003A to H'003B Reserved for system use 30 to 33 H'003C to H'0043 Clock switch Clock switch (external clock to on-chip oscillator clock) 34 H'0044 to H'0045 Note: * Available for the H8/36912 Group only. Rev. 3.00 Sep. 14, 2006 Page 48 of 408 REJ09B0105-0300 Low Section 3 Exception Handling 3.2 Register Descriptions Interrupts are controlled by the following registers. * * * * * * * Interrupt edge select register 1 (IEGR1) Interrupt edge select register 2 (IEGR2) Interrupt enable register 1 (IENR1) Interrupt enable register 2 (IENR2) Interrupt flag register 1 (IRR1) Interrupt flag register 2 (IRR2) Wakeup interrupt flag register (IWPR) 3.2.1 Interrupt Edge Select Register 1 (IEGR1) IEGR1 selects the direction of an edge that generates interrupt requests of the IRQ3 and IRQ0 pins. Bit Bit Name Initial Value R/W 7 0 - Description Reserved This bit is always read as 0. 6 to 4 All 1 Reserved These bits are always read as 1. 3 IEG3 0 R/W IRQ3 Edge Select 0: Falling edge of IRQ3 pin input is detected 1: Rising edge of IRQ3 pin input is detected 2, 1 All 0 Reserved These bits are always read as 0. 0 IEG0 0 R/W IRQ0 Edge Select 0: Falling edge of IRQ0 pin input is detected 1: Rising edge of IRQ0 pin input is detected Rev. 3.00 Sep. 14, 2006 Page 49 of 408 REJ09B0105-0300 Section 3 Exception Handling 3.2.2 Interrupt Edge Select Register 2 (IEGR2) IEGR2 selects the direction of an edge that generates interrupt requests of the ADTRG and WKP5 pins. Bit Bit Name Initial Value R/W Description 7, 6 All 1 Reserved 5 WPEG5 0 R/W WKP5 Edge Select These bits are always read as 1. 0: Falling edge of WKP5 (ADTRG) pin input is detected 1: Rising edge of WKP5 (ADTRG) pin input is detected 4 to 0 All 0 Reserved These bits are always read as 0. 3.2.3 Interrupt Enable Register 1 (IENR1) IENR1 enables direct transition interrupts and external pin interrupts. Bit Bit Name Initial Value R/W Description 7 IENDT 0 R/W Direct Transfer Interrupt Enable When this bit is set to 1, direct transition interrupt requests are enabled. 6 0 Reserved This bit is always read as 0. 5 IENWP 0 R/W Wakeup Interrupt Enable This bit is an enable bit of the WKP5 pin. When this bit is set to 1, interrupt requests are enabled. 4 1 Reserved This bit is always read as 1. 3 IEN3 0 R/W IRQ3 Interrupt Enable When this bit is set to 1, interrupt requests of the IRQ3 pin are enabled. 2, 1 All 0 Reserved These bits are always read as 0. Rev. 3.00 Sep. 14, 2006 Page 50 of 408 REJ09B0105-0300 Section 3 Exception Handling Bit Bit Name Initial Value R/W Description 0 IEN0 0 R/W IRQ0 Interrupt Enable When this bit is set to 1, interrupt requests of the IRQ0 pin are enabled. 3.2.4 Interrupt Enable Register 2 (IENR2) IENR2 enables timer B1 interrupts. Bit Bit Name Initial Value R/W Description 7 0 Reserved This bit is always read as 0. 6 0 R/W Reserved Although this bit is readable/writable, it should not be set to 1. 5 IENTB1 0 R/W Timer B1 Interrupt Enable When this bit is set to 1, overflow interrupt requests of timer B1 are enabled. 4 to 0 All 1 Reserved These bits are always read as 1. When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in an interrupt flag register, always do so while interrupts are masked (I = 1). If the above clear operations are performed while I = 0, and as a result a conflict arises between the clear instruction and an interrupt request, exception handling for the interrupt will be executed after the clear instruction has been executed. Rev. 3.00 Sep. 14, 2006 Page 51 of 408 REJ09B0105-0300 Section 3 Exception Handling 3.2.5 Interrupt Flag Register 1 (IRR1) IRR1 is a status flag register for direct transition interrupts, and IRQ3 and IRQ0 interrupt requests. Bit Bit Name Initial Value R/W Description 7 IRRDT 0 R/W Direct Transfer Interrupt Request Flag [Setting condition] * When a direct transfer is made by executing a SLEEP instruction while DTON in SYSCR2 is set to 1. [Clearing condition] * 6 0 When IRRDT is cleared by writing 0 Reserved This bit is always read as 0. 5, 4 All 1 Reserved These bits are always read as 1. 3 IRRI3 0 R/W IRQ3 Interrupt Request Flag [Setting condition] * When IRQ3 pin is designated for interrupt input and the designated signal edge is detected [Clearing condition] * 2, 1 All 0 When IRRI3 is cleared by writing 0 Reserved These bits are always read as 0. 0 IRRl0 0 R/W IRQ0 Interrupt Request Flag [Setting condition] * When IRQ0 pin is designated for interrupt input and the designated signal edge is detected [Clearing condition] * Rev. 3.00 Sep. 14, 2006 Page 52 of 408 REJ09B0105-0300 When IRRI0 is cleared by writing 0 Section 3 Exception Handling 3.2.6 Interrupt Flag Register 2 (IRR2) IRR2 is a status flag register for timer B1 interrupt requests. Bit Bit Name Initial Value R/W Description 7 0 Reserved This bit is always read as 0. 6 Reserved 5 IRRTB1 0 R/W Timer B1 Interrupt Request Flag [Setting condition] * When timer B1 overflows [Clearing condition] * 4 to 0 All 1 When IRRTB1 is cleared by writing 0 Reserved These bits are always read as 1. 3.2.7 Wakeup Interrupt Flag Register (IWPR) IWPR is a status flag register for WKP5 interrupt requests. Bit Bit Name Initial Value R/W Description 7, 6 All 1 Reserved These bits are always read as 1. 5 IWPF5 0 R/W WKP5 Interrupt Request Flag [Setting condition] * When WKP5 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] * 4 to 0 All 0 When IWPF5 is cleared by writing 0 Reserved These bits are always read as 0. Rev. 3.00 Sep. 14, 2006 Page 53 of 408 REJ09B0105-0300 Section 3 Exception Handling 3.3 Reset Exception Handling When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure that this LSI is reset at power-up, hold the RES pin low for the specified period. To reset the chip during operation, hold the RES pin low for the specified period. For details, refer to section 17, Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits. When the RES pin goes high after being held low for a certain period, this LSI starts reset exception handling. The reset exception handling sequence is shown in figure 3.1. The reset exception handling sequence is as follows. 1. Set the I bit in the condition code register (CCR) to 1. 2. The CPU generates a reset exception handling vector address (from H'0000 to H'0001), the data in that address is sent to the program counter (PC) as the start address, and program execution starts from that address. Rev. 3.00 Sep. 14, 2006 Page 54 of 408 REJ09B0105-0300 Section 3 Exception Handling 3.4 Interrupt Exception Handling 3.4.1 External Interrupts As external interrupts, there are NMI, IRQ3, IRQ0, and WKP5 interrupts. (1) NMI Interrupt NMI interrupt is requested by input falling edge to the NMI pin. NMI is the highest interrupt, and can always be accepted without depending on the I bit value in CCR. (2) IRQ3 and IRQ0 Interrupts IRQ3 and IRQ0 interrupts are requested by input signals to the IRQ3 and IRQ0 pins. These interrupts are given different vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of the IEG3 and IEG0 bits in IEGR1. When the IRQ3 and IRQ0 pins are designated for interrupt input in PMR1 and the designated signal edge is input, the corresponding bit in IRR1 is set to 1, requesting the CPU of an interrupt. These interrupts can be masked by setting the IEN3 and IEN0 bits in IENR1. (3) WKP Interrupt WKP interrupt is requested by an input signal to the WKP5 pin. This interrupt is detected by either rising edge sensing or falling edge sensing, depending on the setting of the WPEG5 bit in IEGR2. When the WKP5 pin is designated for interrupt input in PMR5 and the designated signal edge is input, the corresponding bit in IWPR is set to 1, requesting the CPU of an interrupt. This interrupt can be masked by setting the IENWP bit in IENR1. Rev. 3.00 Sep. 14, 2006 Page 55 of 408 REJ09B0105-0300 Section 3 Exception Handling ~ Reset cleared ~ Internal address bus (1) (2) ~ ~ RES Initial program instruction prefetch Vector fetch Internal processing Internal write signal ~ Internal data bus (16 bits) ~ Internal read signal (2) (3) (1) Reset exception handling vector address (H'0000) (2) Program start address (3) Initial program instruction Figure 3.1 Reset Sequence 3.4.2 Internal Interrupts Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to enable or disable the interrupt. For direct transfer interrupt requests generated by execution of a SLEEP instruction, this function is included in IRR1 and IENR1. When an on-chip peripheral module requests an interrupt, the corresponding interrupt request status flag is set to 1, requesting the CPU of an interrupt. When this interrupt is accepted, the I bit is set to 1 in CCR. These interrupts can be masked by writing 0 to clear the corresponding enable bit. Rev. 3.00 Sep. 14, 2006 Page 56 of 408 REJ09B0105-0300 Section 3 Exception Handling 3.4.3 Interrupt Handling Sequence Interrupts are controlled by an interrupt controller. Interrupt operation is described as follows. 1. If an interrupt occurs while the NMI or interrupt enable bit is set to 1, an interrupt request signal is sent to the interrupt controller. 2. When multiple interrupt requests are generated, the interrupt controller requests to the CPU for the interrupt handling with the highest priority at that time according to table 3.1. Other interrupt requests are held pending. 3. The CPU accepts the NMI or address break without depending on the I bit value. Other interrupt requests are accepted, if the I bit is cleared to 0 in CCR; if the I bit is set to 1, the interrupt request is held pending. 4. If the CPU accepts the interrupt after processing of the current instruction is completed, interrupt exception handling will begin. First, both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3.2. The PC value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling. 5. Then, the I bit of CCR is set to 1, masking further interrupts excluding the NMI and address break. Upon return from interrupt handling, the values of I bit and other bits in CCR will be restored and returned to the values prior to the start of interrupt exception handling. 6. Next, the CPU generates the vector address corresponding to the accepted interrupt, and transfers the address to PC as a start address of the interrupt handling-routine. Then a program starts executing from the address indicated in PC. Rev. 3.00 Sep. 14, 2006 Page 57 of 408 REJ09B0105-0300 Section 3 Exception Handling Figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip ROM and the stack area is in the on-chip RAM. ~ Reset cleared ~ Internal address bus (1) (2) ~ ~ RES Initial program instruction prefetch Vector fetch Internal processing Internal write signal ~ Internal data bus (16 bits) ~ Internal read signal (2) (3) (1) Reset exception handling vector address (H'0000) (2) Program start address (3) Initial program instruction Figure 3.2 Stack Status after Exception Handling Rev. 3.00 Sep. 14, 2006 Page 58 of 408 REJ09B0105-0300 Section 3 Exception Handling 3.4.4 Interrupt Response Time Table 3.2 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handling-routine is executed. Table 3.2 Interrupt Wait States Item States Total Waiting time for completion of executing instruction* 1 to 23 15 to 37 Saving of PC and CCR to stack 4 Vector fetch 2 Instruction fetch 4 Internal processing 4 Note: * EEPMOV instruction is not included. Rev. 3.00 Sep. 14, 2006 Page 59 of 408 REJ09B0105-0300 REJ09B0105-0300 Rev. 3.00 Sep. 14, 2006 Page 60 of 408 Figure 3.3 Interrupt Sequence (2) (1) (4) Instruction prefetch (3) Internal processing (5) (1) Stack access (6) (7) (9) Vector fetch (8) (1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) (2)(4) Instruction code (not executed) (3) Instruction prefetch address (Instruction is not executed.) (5) SP - 2 (6) SP - 4 (7) CCR (8) Vector address (9) Starting address of interrupt-handling routine (contents of vector) (10) First instruction of interrupt-handling routine Internal data bus (16 bits) Internal write signal Internal read signal Internal address bus Interrupt request signal Interrupt level decision and wait for end of instruction Interrupt is accepted (10) (9) Prefetch instruction of Internal interrupt-handling routine processing Section 3 Exception Handling Section 3 Exception Handling 3.5 Usage Notes 3.5.1 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.W #xx: 16, SP). 3.5.2 Notes on Stack Area Use When word data is accessed, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd address. Use PUSH Rn (MOV.W Rn, @-SP) or POP Rn (MOV.W @SP+, Rn) to save or restore register values. 3.5.3 Notes on Rewriting Port Mode Registers When a port mode register is rewritten to switch the functions of external interrupt pins, IRQ3, IRQ0, and WKP5, the interrupt request flag may be set to 1. When switching a pin function, mask the interrupt before setting the bit in the port mode register. After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the interrupt request flag from 1 to 0. Figure 3.4 shows a port mode register setting and interrupt request flag clearing procedure. CCR I bit 1 Interrupts masked. (Another possibility is to disable the relevant interrupt in interrupt enable register 1.) Set port mode register bit Execute NOP instruction After setting the port mode register bit, first execute at least one instruction (e.g., NOP), then clear the interrupt request flag to 0 Clear interrupt request flag to 0 CCR I bit 0 Interrupt mask cleared Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure Rev. 3.00 Sep. 14, 2006 Page 61 of 408 REJ09B0105-0300 Section 3 Exception Handling Rev. 3.00 Sep. 14, 2006 Page 62 of 408 REJ09B0105-0300 Section 4 Address Break Section 4 Address Break The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR. Break conditions that can be set include instruction execution at a specific address and a combination of access and data at a specific address. With the address break function, the execution start point of a program containing a bug is detected and execution is branched to the correcting program. Figure 4.1 shows a block diagram of the address break. Internal address bus Comparator BARL ABRKCR Interrupt generation control circuit ABRKSR BDRH Internal data bus BARH BDRL Comparator Interrupt [Legend] BARH, BARL: BDRH, BDRL: ABRKCR: ABRKSR: Break address register Break data register Address break control register Address break status register Figure 4.1 Block Diagram of Address Break ABK0001A_000020020200 Rev. 3.00 Sep. 14, 2006 Page 63 of 408 REJ09B0105-0300 Section 4 Address Break 4.1 Register Descriptions Address break has the following registers. * * * * Address break control register (ABRKCR) Address break status register (ABRKSR) Break address register (BARH, BARL) Break data register (BDRH, BDRL) 4.1.1 Address Break Control Register (ABRKCR) ABRKCR sets address break conditions. Bit Bit Name Initial Value R/W Description 7 RTINTE 1 R/W RTE Interrupt Enable When this bit is 0, the interrupt immediately after executing RTE is masked and then one instruction must be executed. When this bit is 1, the interrupt is not masked. 6 CSEL1 0 R/W Condition Select 1 and 0 5 CSEL0 0 R/W These bits set address break conditions. 00: Instruction execution cycle 01: CPU data read cycle 10: CPU data write cycle 11: CPU data read/write cycle 4 ACMP2 0 R/W Address Compare Condition Select 2 to 0 3 ACMP1 0 R/W 2 ACMP0 0 R/W These bits comparison condition between the address set in BAR and the internal address bus. 000: Compares 16-bit addresses 001: Compares upper 12-bit addresses 010: Compares upper 8-bit addresses 011: Compares upper 4-bit addresses 1XX: Reserved (setting prohibited) Rev. 3.00 Sep. 14, 2006 Page 64 of 408 REJ09B0105-0300 Section 4 Address Break Bit Bit Name Initial Value R/W Description 1 DCMP1 0 R/W Data Compare Condition Select 1 and 0 0 DCMP0 0 R/W These bits set the comparison condition between the data set in BDR and the internal data bus. 00: No data comparison 01: Compares lower 8-bit data between BDRL and data bus 10: Compares upper 8-bit data between BDRH and data bus 11: Compares 16-bit data between BDR and data bus [Legend] X: Don't care When an address break is set in the data read cycle or data write cycle, the data bus used will depend on the combination of the byte/word access and address. Table 4.1 shows the access and data bus used. When an I/O register space with an 8-bit data bus width is accessed in word size, a byte access is generated twice. For details on data widths of each register, see section 19.1, Register Addresses (Address Order). Table 4.1 Access and Data Bus Used Word Access Byte Access Even Address Odd Address Even Address Odd Address ROM space Upper 8 bits Lower 8 bits Upper 8 bits Upper 8 bits RAM space Upper 8 bits Lower 8 bits Upper 8 bits Upper 8 bits I/O register with 8-bit data bus Upper 8 bits width Upper 8 bits Upper 8 bits Upper 8 bits I/O register with 16-bit data bus width Lower 8 bits -- -- Upper 8 bits Rev. 3.00 Sep. 14, 2006 Page 65 of 408 REJ09B0105-0300 Section 4 Address Break 4.1.2 Address Break Status Register (ABRKSR) ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit. Bit Bit Name Initial Value R/W Description 7 ABIF 0 R/W Address Break Interrupt Flag [Setting condition] * When the condition set in ABRKCR is satisfied [Clearing condition] * 6 ABIE 0 R/W When 0 is written after ABIF=1 is read Address Break Interrupt Enable When this bit is 1, an address break interrupt request is enabled. 5 to 0 -- All 1 -- Reserved These bits are always read as 1. 4.1.3 Break Address Registers (BARH, BARL) BARH and BARL are 16-bit read/write registers that set the address for generating an address break interrupt. When setting the address break condition to the instruction execution cycle, set the first byte address of the instruction. The initial value of this register is H'FFFF. 4.1.4 Break Data Registers (BDRH, BDRL) BDRH and BDRL are 16-bit read/write registers that set the data for generating an address break interrupt. BDRH is compared with the upper 8-bit data bus. BDRL is compared with the lower 8bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is used for even and odd addresses in the data transmission. Therefore, comparison data must be set in BDRH for byte access. For word access, the data bus used depends on the address. See section 4.1.1, Address Break Control Register (ABRKCR), for details. The initial value of this register is undefined. Rev. 3.00 Sep. 14, 2006 Page 66 of 408 REJ09B0105-0300 Section 4 Address Break 4.2 Operation When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an interrupt request to the CPU. The ABIF bit in ABRKSR is set to 1 by the combination of the address set in BAR, the data set in BDR, and the conditions set in ABRKCR. When the interrupt request is accepted, interrupt exception handling starts after the instruction being executed ends. The address break interrupt is not masked because of the I bit in CCR of the CPU. The following figures show the operation examples of the address break interrupt setting. When the address break is specified in instruction execution cycle Register setting * ABRKCR = H'80 * BAR = H'025A Program 0258 * 025A 025C 0260 0262 : NOP NOP MOV.W @H'025A,R0 NOP NOP : Underline indicates the address to be stacked. NOP NOP MOV MOV instruc- instruc- instruc- instruction tion tion 1 tion 2 Internal prefetch prefetch prefetch prefetch processing Stack save Address bus 0258 025A 025C 025E SP-2 SP-4 Interrupt request Interrupt acceptance Figure 4.2 Address Break Interrupt Operation Example (1) Rev. 3.00 Sep. 14, 2006 Page 67 of 408 REJ09B0105-0300 Section 4 Address Break When the address break is specified in the data read cycle Register setting * ABRKCR = H'A0 * BAR = H'025A Program 0258 025A * 025C 0260 0262 : NOP NOP MOV.W @H'025A,R0 NOP Underline indicates the address NOP to be stacked. : MOV MOV NOP MOV NOP Next instruc- instruc- instruc- instruc- instruc- instruction 1 tion 2 tion tion tion tion Internal Stack prefetch prefetch prefetch execution prefetch prefetch processing save Address bus 025C 025E 0260 025A 0262 0264 SP-2 Interrupt request Interrupt acceptance Figure 4.2 Address Break Interrupt Operation Example (2) Rev. 3.00 Sep. 14, 2006 Page 68 of 408 REJ09B0105-0300 Section 5 Clock Pulse Generators Section 5 Clock Pulse Generators Clock oscillator circuitry (CPG: clock pulse generator) consists of an external oscillator, an onchip oscillator, a duty correction circuit, a clock select circuit, and system clock dividers. Figure 5.1 shows a block diagram of the clock pulse generator. OSC1 OSC2 System clock oscillator OSC Duty correction circuit OSC /8 ROSC On-chip ROSC oscillator Clock divider ROSC/2 RC Clock select circuit System clock divider /16 /32 /64 ROSC/4 Prescaler S (13 bits) /2 to /8192 Figure 5.1 Block Diagram of Clock Pulse Generators The system clock () is a basic clock on which the CPU and on-chip peripheral modules operate. The system clock is divided into /2 to /8192 by prescaler S and the divided clocks are supplied to respective peripheral modules. CPG0200A_000020020200 Rev. 3.00 Sep. 14, 2006 Page 69 of 408 REJ09B0105-0300 Section 5 Clock Pulse Generators 5.1 Features * Choice of two clock sources On-chip oscillator clock External oscillator clock * Choice of two types of on-chip oscillation frequency by the user software 8MHz 10MHz * Frequency trimming Users can adjust the on-chip oscillation frequency by rewriting the trimming registers. * Interrupt can be requested to the CPU when the system clock is changed from the external clock to the on-chip oscillator clock. Rev. 3.00 Sep. 14, 2006 Page 70 of 408 REJ09B0105-0300 Section 5 Clock Pulse Generators 5.2 Register Descriptions Clock oscillators are controlled by the following registers. * * * * RC control register (RCCR) RC trimming data protect register (RCTRMDPR) RC trimming data register (RCTRMDR) Clock control/status register (CKCSR) 5.2.1 RC Control Register (RCCR) RCCR controls the on-chip oscillator. Bit Bit Name Initial Value R/W Description 7 RCSTP 0 R/W On-chip Oscillator Standby The internal on-chip oscillator standby state is entered by setting this bit to 1. 6 FSEL 0 R/W Frequency Select for On-chip Oscillator 0: 8MHz 1: 10MHz 5 VCLSEL 0 R/W Power Supply Select for On-chip Oscillator 0: Selects VBGR 1: Selects VCL When VCL is selected, the accuracy of the on-chip oscillator frequency cannot be guaranteed. 4 to 2 All 0 Reserved These bits are always read as 0. 1 RCPSC1 0 R/W Division Ratio Select for On-chip Oscillator 0 RCPSC0 0 R/W The division ratio of ROSC changes right after rewriting this bit. These bits can be written to only when the CKSTA bit in CKCSR is 0. 0X: ROSC (not divided) 10: ROSC/2 11: ROSC/4 Rev. 3.00 Sep. 14, 2006 Page 71 of 408 REJ09B0105-0300 Section 5 Clock Pulse Generators 5.2.2 RC Trimming Data Protect Register (RCTRMDPR) RCTRMDPR controls RCTRMDPR itself and writing to RCTRMDR. Use the MOV instruction to rewrite this register. Bit manipulation instruction cannot change the settings. Bit Bit Name Initial Value R/W Description 7 WRI 1 W Write Inhibit Only when writing 0 to this bit, this register can be written to. This bit is always read as 1. 6 PRWE 0 R/W Protect Information Write Enable Bits 5 and 4 can be written to when this bit is set to 1. [Setting condition] * When writing 0 to the WRI bit and writing 1 to the PRWE bit [Clearing conditions] 5 LOCKDW 0 R/W * Reset * When writing 0 to the WRI bit and writing 0 to the PRWE bit Trimming Data Register Lock Down The RC trimming data register (RCTRMDR) cannot be written to when this bit is set to 1. Once this bit is set to 1, this register cannot be written to until a reset is input even if 0 is written to this bit. [Setting condition] * When writing 0 to the WRI bit and writing 1 to the LOCKDW bit while the PRWE bit is 1 [Clearing condition] * Rev. 3.00 Sep. 14, 2006 Page 72 of 408 REJ09B0105-0300 Reset Section 5 Clock Pulse Generators Initial Value Bit Bit Name 4 TRMDRWE 0 R/W Description R/W Trimming Date Register Write Enable This register can be written to when the LOCKDW bit is 0 and this bit is 1. [Setting condition] * When writing 0 to the WRI bit while writing 1 to the TRMDRWE bit while the PRWE bit is 1 [Clearing conditions] 3 to 0 All 1 * Reset * When writing 0 to the WRI bit and writing 0 to the TRMDRWE bit while the PRWE bit is 1 Reserved These bits are always read as 1 5.2.3 RC Trimming Data Register (RCTRMDR) RCTRMDR stores the trimming data of the on-chip oscillator frequency. Bit Bit Name Initial Value R/W Description 7 TRMD7 (0)* R/W Trimming Data 6 TRMD6 (0)* R/W 5 TRMD5 (0)* R/W 4 TRMD4 (0)* R/W In the flash memory version, the trimming data is loaded from the flash memory to this register right after a reset. These bits are always read as undefined value. 3 TRMD3 (0)* R/W 2 TRMD2 (0)* R/W 1 TRMD1 0 R 0 TRMD0 0 R As for the masked ROM version, the on-chip oscillator frequency can be trimmed by rewriting these bits. The frequency generated in the on-chip oscillator changes right after rewriting these bits. These bits are initialized to H'00. Frequency variation is expressed as follows (the TRMD7 bit is a sign bit): (Min.) H'80 H'FC H'00 H'04 H'7C (Max.) Note: * The initial value differs from product to product in the flash memory version. Rev. 3.00 Sep. 14, 2006 Page 73 of 408 REJ09B0105-0300 Section 5 Clock Pulse Generators 5.2.4 Clock Control/Status Register (CKCSR) CKCSR selects the port C function, controls switching the system clocks, and indicates the system clock state. Bit Bit Name Initial Value R/W Description 7 PMRC1 0 R/W Port C Function Select 1 and 0 6 PMRC0 0 R/W PMRC1 PMRC0 PC1 PC0 0 I/O 5 0 R/W 0 I/O 1 0 CLKOUT I/O 0 1 I/O OSC1 (external clock input) 1 1 OSC2 OSC1 Reserved Although this bit is readable/writable, it should not be set to 1. 4 OSCSEL 0 R/W LSI Operation Clock Select This bit forcibly selects the system clock of this LSI. 0: Selects the on-chip oscillator clock as the system clock. 1: Selects the external clock as the system clock. 3 CKSWIE 0 R/W Clock Switch Interrupt Enable Setting this bit to 1 enables the clock switch interrupt request. 2 CKSWIF 0 R/W Clock Switch Interrupt Request Flag [Setting condition] * When the external clock is switched to the on-chip oscillator clock [Clearing condition] * 1 1 R When writing 0 after reading 1 Reserved This bit is always read as 1. 0 CKSTA 0 R LSI Operating Clock Status 0: This LSI operates on on-chip oscillator clock. 1: This LSI operates on external clock. Rev. 3.00 Sep. 14, 2006 Page 74 of 408 REJ09B0105-0300 Section 5 Clock Pulse Generators 5.3 System Clock Select Operation Figure 5.2 shows the state transition of the system clock. LSI operates on on-chip oscillator clock Reset state Reset release On-chip oscillator: Operated External oscillator: Halted Switching to on-chip oscillator Switching to external clock On-chip oscillator halted On-chip oscillator: Halted External oscillator: Operated On-chip oscillator: Operated External oscillator: Operated On-chip oscillator operated LSI operates on external oscillator Figure 5.2 State Transition of System Clock Rev. 3.00 Sep. 14, 2006 Page 75 of 408 REJ09B0105-0300 Section 5 Clock Pulse Generators 5.3.1 Clock Control Operation The LSI system clock is generated by the on-chip oscillator clock after a reset. The on-chip oscillator clock is switched to the external clock by the user software. LSI operates on on-chip oscillator RC clock Start (reset) Write 1 to PMRC0 in CKCSR Write 1 to PMRC1 in CKCSR [1] Write 0 to CKSWIE in CKCSR [2] Write 1 to OSCSEL in CKCSR Switched to external clock? (CKSTA in CKCSR is 1) [1] External oscillation starts when pins PC1 and PC0 are selected as external oscillation pins. Write 0 to bit PMRC1 to input the external clock. [2] After writing 1 to the OSCSEL bit, this LSI waits until the oscillation of the external oscillator settles. The correspondence between Nwait, which is the number of wait cycles for oscillation settling, and Nstby, which is the number of wait cycles for oscillation settling when returning from standby mode, is as follows: Nstby Nwait 2 x Nstby Nstby is set by bits STS 2 to 0 in SYSCR1. For details, see section 6.1.1, System Control Register 1 (SYSCR1). [3] While the system is waiting for the external oscillation settling, this LSI is not halted but continues to operate on the on-chip oscillator clock. Read the value of the CKSTA bit in CKCSR to ensure that the system clocks are switched. [3] No Yes LSI operates on external oscillator Figure 5.3 Flowchart of Clock Switching On-chip Oscillator Clock to External Clock (1) Rev. 3.00 Sep. 14, 2006 Page 76 of 408 REJ09B0105-0300 Section 5 Clock Pulse Generators LSI operates on external clock [1] When 0 is written to the OSCSEL bit, this LSI switches the external clock to the on-chip oscillator clock after the stop duration. Seven rising edges of the RC clock after the OSCSEL bit becomes 0 are included in the stop duration. [2] Writing 0 to PMRC0 stops the external oscillation. Start (LSI operates on external clock) Write 0 to RCSTP in RCCR Write 1 to CKSWIE in CKCSR if necessary Write 0 to OSCSEL in CKCSR [1] LSI operates on on-chip oscillator clock When CKSWIE = 1 Exception handling for clock switching Write 0 to PMRC0 in CKCSR if necessary [2] LSI operates on on-chip oscillator Figure 5.4 Flowchart of Clock Switching External Clock to On-chip Oscillator Clock (2) Rev. 3.00 Sep. 14, 2006 Page 77 of 408 REJ09B0105-0300 Section 5 Clock Pulse Generators 5.3.2 Clock Change Timing The timing for changing clocks are shown in figures 5.5 and 5.6. OSC RC OSCSEL PHISTOP (Internal signal) CKSTA On-chip oscillator clock operation halt* External clock operation Wait for external oscillation settling Nwait [Legend] OSC: External clock RC: On-chip oscillator clock : System clock OSCSEL: Bit 4 in CKCSR PHISTOP: System clock stop control signal CKSTA: Bit 0 in CKCSR Note: * The halt duration is the duration from the timing when the clock stops to the first rising edge of the OSC clock after six clock cycles of the RC clock have elapsed. Figure 5.5 Timing Chart of Switching On-chip Oscillator Clock to External Clock Rev. 3.00 Sep. 14, 2006 Page 78 of 408 REJ09B0105-0300 Section 5 Clock Pulse Generators OSC RC OSCSEL PHISTOP (Internal signal) CKSTA CKSWIF halt* External clock operation Wait for external oscillation settling On-chip oscillator clock operation Nwait [Legend] OSC: External clock RC: On-chip oscillator clock : System clock OSCSEL: Bit 4 in CKCSR PHISTOP: System clock stop control signal CKSTA: Bit 0 in CKCSR CKSWIF: Bit 2 in CKCSR Note: * The halt duration is the duration from the timing when the clock stops to the seventh rising edge of the RC clock. Figure 5.6 Timing Chart to Switch External Clock to On-chip Oscillator Clock Rev. 3.00 Sep. 14, 2006 Page 79 of 408 REJ09B0105-0300 Section 5 Clock Pulse Generators 5.4 Trimming of On-chip Oscillator Frequency Users can trim the on-chip oscillator frequency, supplying the external reference pulses with the input capture function in internal timer W. An example of trimming flow and a timing chart are shown in figures 5.7 and 5.8, respectively. Because RCTRMDR is initialized by a reset, when users have trimmed the oscillators, some operations after a reset are necessary, such as trimming it again or saving the trimming value in an external device for later reloading. Start Setting timer W GRA: Input capture GRC: Buffer of GRA Set RCTRMD to H'00 Input reference pulses to pin P81/FTIOA Capture 1 Modify RCTRMDR* Capture 2 Frequency calculation Within desired frequency range? No Yes End Note: * Comparing the difference between the measured frequency and the desired frequency, individual bits of RCTRMDR are decided from the MSB bit by bit. Figure 5.7 Example of Trimming Flow for On-chip Oscillator Frequency Rev. 3.00 Sep. 14, 2006 Page 80 of 408 REJ09B0105-0300 Section 5 Clock Pulse Generators RC FTIOA input capture input tA (s) Timer W TCNT GRA M-1 M N GRC M+1 M N Capture 1 M+ M+ M Capture 2 Figure 5.8 Timing Chart of Trimming of On-chip Oscillator Frequency The on-chip oscillator frequency is gained by the expression below. Since the input-capture input is sampled by the RC clock, the calculated result may include a sampling error of 1 cycle of the RC clock. RC = (M + ) - M (MHz) tA RC: Frequency of on-chip oscillator (MHz) Period of reference clock (s) tA: M: Timer W counter value Rev. 3.00 Sep. 14, 2006 Page 81 of 408 REJ09B0105-0300 Section 5 Clock Pulse Generators 5.5 External Oscillators This LSI has two methods to supply external clock pulses into it: connecting a crystal or ceramic resonator, and an external clock. Oscillation pins OSC1 and OSC2 are common with general ports PC0 and PC1, respectively. To set pins PC0 and PC1 as crystal resonator or external clock input ports, refer to section 5.3, System Clock Select Operation. 5.5.1 Connecting Crystal Resonator Figure 5.9 shows an example of connecting a crystal resonator. An AT-cut parallel-resonance crystal resonator should be used. Figure 5.12 shows the equivalent circuit of a crystal resonator. A resonator having the characteristics given in table 5.1 should be used. C1 PC0/OSC1 C2 C1 = C 2 = 10 to 22 pF PC1/OSC2/CLKOUT Figure 5.9 Example of Connection to Crystal Resonator LS RS CS PC0/OSC1 PC1/OSC2/CLKOUT C0 Figure 5.10 Equivalent Circuit of Crystal Resonator Table 5.1 Crystal Resonator Parameters Frequency (MHz) 2 4 8 10 12 RS (Max.) 500 120 80 60 50 C0 (Max.) Rev. 3.00 Sep. 14, 2006 Page 82 of 408 REJ09B0105-0300 70 pF Section 5 Clock Pulse Generators 5.5.2 Connecting Ceramic Resonator Figure 5.11 shows an example of connecting a ceramic resonator. C1 PC0/OSC1 C2 PC1/OSC2/CLKOUT C1 = C 2 = 5 to 30 pF Figure 5.11 Example of Connection to Ceramic Resonator 5.5.3 External Clock Input Method To use the external clock, input the external clock on pin OSC1. Figure 5.12 shows an example of connection. The duty cycle of the external clock signal must be 45 to 55%. PC0/OSC1 PC1/OSC2/CLKOUT External clock input General port Figure 5.12 Example of External Clock Input 5.6 Prescaler 5.6.1 Prescaler S Prescaler S is a 13-bit counter using the system clock () as its input clock. The outputs, which are divided clocks, are used as internal clocks by the on-chip peripheral modules. Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state. In standby mode and subsleep mode, the system clock pulse generator stops. Prescaler S also stops and is initialized to H'0000. It cannot be read from or written to by the CPU. The outputs from prescaler S is shared by the on-chip peripheral modules. The division ratio can be set separately for each on-chip peripheral module. In active mode and sleep mode, the clock input to prescaler S is a system clock with the division ratio specified by bits MA2 to MA0 in SYSCR2. Rev. 3.00 Sep. 14, 2006 Page 83 of 408 REJ09B0105-0300 Section 5 Clock Pulse Generators 5.7 Usage Notes 5.7.1 Note on Resonators Resonator characteristics are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. Resonator circuit parameters will differ depending on the resonator element, stray capacitance of the PCB, and other factors. Suitable values should be determined in consultation with the resonator element manufacturer. Design the circuit so that the resonator element never receives voltages exceeding its maximum rating. 5.7.2 Notes on Board Design When using a crystal resonator (ceramic resonator), place the resonator and its load capacitors as close as possible to pins OSC1 and OSC2. Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation (see figure 5.13). Prohibited Signal A Signal B C1 PC0/OSC1 C2 PC1/OSC2/CLKOUT Figure 5.13 Example of Incorrect Board Design Rev. 3.00 Sep. 14, 2006 Page 84 of 408 REJ09B0105-0300 Section 6 Power-Down Modes Section 6 Power-Down Modes For operating modes after a reset, this LSI has not only a normal active mode but also three power-down modes in which power consumption is significantly reduced. In addition, there is also a module standby function which reduces power consumption by individually stopping on-chip peripheral modules. * Active mode The CPU and all on-chip peripheral modules are operable on the system clock. The system clock frequency can be selected from osc, osc/8, osc/16, osc/32, and osc/64. * Sleep mode The CPU halts. On-chip peripheral modules are operable on the system clock. * Standby mode The CPU and all on-chip peripheral modules halt. * Subsleep mode The CPU and all on-chip peripheral modules halt. I/O ports keep the same states as before the transition. * Module standby function Independent of the above modes, power consumption can be reduced by halting on-chip peripheral modules that are not used in module units. 6.1 Register Descriptions The registers related to power-down modes are listed below. * * * * System control register 1 (SYSCR1) System control register 2 (SYSCR2) Module standby control register 1 (MSTCR1) Module standby control register 2 (MSTCR2) LPW3003A_000020020200 Rev. 3.00 Sep. 14, 2006 Page 85 of 408 REJ09B0105-0300 Section 6 Power-Down Modes 6.1.1 System Control Register 1 (SYSCR1) SYSCR1 controls the power-down modes, as well as SYSCR2. Bit Bit Name Initial Value R/W Description 7 SSBY 0 R/W Software Standby Specifies the operating mode to be entered after executing the SLEEP instruction. 0: Shifts to sleep mode. 1: Shifts to standby mode. For details, see table 6.2. 6 STS2 0 R/W Standby Timer Select 2 to 0 5 STS1 0 R/W 4 STS0 0 R/W These bits set the wait time from when the system clock oscillator starts functioning until the clock is supplied, in shifting from standby mode, to active mode or sleep mode. During the wait time, this LSI automatically selects the on-chip oscillator clock as its system clock and counts the number of wait states. Select a wait time of 6.5 ms (oscillation stabilization time) or longer, depending on the operating frequency. Table 6.1 shows the relationship between the STS2 to STS0 values and the wait time. When using an external clock, set the wait time to be 100 s or longer in the F-ZTAT version. In the masked ROM version, the minimum value (STS2 = STS1 = STS0 = 1) is recommended. These bits also set the wait states for external oscillation stabilization when system clock is switched from the onchip oscillator clock to the external clock by user software. The relationship between Nwait (number of wait states for oscillation stabilization) and Nstby (number of wait states for recovering to the standby mode) is as follows. Nstby Nwait 2 x Nstby 3 to 0 All 0 Reserved These bits are always read as 0. Rev. 3.00 Sep. 14, 2006 Page 86 of 408 REJ09B0105-0300 Section 6 Power-Down Modes Table 6.1 Operating Frequency and Wait Time Bit Name Operating Frequency STS2 STS1 STS0 Wait Time 10 MHz 8 MHz 5 MHz 4 MHz 2.5 MHz 2 MHz 0 0 0 8,192 states 0.8 1.0 1.6 2.0 3.3 4.1 0 0 1 16,384 states 1.6 2.0 3.3 4.1 6.6 8.2 0 1 0 32,768 states 3.3 4.1 6.6 8.2 13.1 16.4 0 1 1 65,536 states 6.6 8.2 13.1 16.4 26.2 32.8 1 0 0 131,072 states 13.1 16.4 26.2 32.8 52.4 65.5 1 0 1 1,024 states 0.10 0.13 0.21 0.26 0.42 0.51 1 1 0 128 states 0.01 0.02 0.03 0.03 0.05 0.06 1 1 1 16 states 0.00 0.00 0.00 0.00 0.00 0.01 Notes: 1. Time unit is ms. 2. The on-chip oscillator clock counts the wait states, even when the external clock is used as system clock. Rev. 3.00 Sep. 14, 2006 Page 87 of 408 REJ09B0105-0300 Section 6 Power-Down Modes 6.1.2 System Control Register 2 (SYSCR2) SYSCR2 controls the power-down modes, as well as SYSCR1. Bit Bit Name Initial Value R/W Description 7 SMSEL 0 R/W Sleep Mode Selection This bit specifies the mode to be entered after executing the SLEEP instruction, as well as the SSBY bit in SYSCR1. For details, see table 6.2. 6 0 Reserved This bit is always read as 0. 5 DTON 0 R/W Direct Transfer on Flag This bit specifies the mode to be entered after executing the SLEEP instruction, as well as the SSBY bit in SYSCR1. For details, see table 6.2. 4 MA2 0 R/W Active Mode Clock Select 2 to 0 3 MA1 0 R/W 2 MA0 0 R/W These bits select the operating clock frequency in active and sleep modes. The operating clock frequency changes to the set frequency after the SLEEP instruction is executed. 0XX: 1, 0 All 0 100: /8 101: /16 110: /32 111: /64 Reserved These bits are always read as 0. [Legend] X: Don't care Rev. 3.00 Sep. 14, 2006 Page 88 of 408 REJ09B0105-0300 Section 6 Power-Down Modes 6.1.3 Module Standby Control Register 1 (MSTCR1) MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units. Bit Bit Name Initial Value R/W 7 0 Description Reserved This bit is always read as 0. 6 MSTIIC 0 R/W IIC2 Module Standby IIC2 enters standby mode when this bit is set to 1. 5 MSTS3 0 R/W SCI3 Module Standby 4 MSTAD 0 R/W A/D Converter Module Standby SCI3 enters standby mode when this bit is set to 1. A/D converter enters standby mode when this bit is set to 1. 3 MSTWD 0 R/W Watchdog Timer Module Standby Watchdog timer enters standby mode when this bit is set to 1. (When the internal oscillator is selected for the watchdog timer clock, the watchdog timer operates regardless of the setting of this bit.) 2 MSTTW 0 R/W Timer W Module Standby Timer W enters standby mode when this bit is set to 1. 1 MSTTV 0 R/W Timer V Module Standby Timer V enters standby mode when this bit is set to 1. 0 0 Reserved This bit is always read as 0. Rev. 3.00 Sep. 14, 2006 Page 89 of 408 REJ09B0105-0300 Section 6 Power-Down Modes 6.1.4 Module Standby Control Register 2 (MSTCR2) MSTCR2 allows the on-chip peripheral modules to enter a standby state in module units. Bit Bit Name Initial Value R/W Description 7 to 5 All 0 Reserved These bits are always read as 0. 4 MSTTB1 0 R/W Timer B1 Module Standby Timer B1 enters standby mode when this bit is set to 1. 3 to 0 All 0 Reserved These bits are always read as 0. Rev. 3.00 Sep. 14, 2006 Page 90 of 408 REJ09B0105-0300 Section 6 Power-Down Modes 6.2 Mode Transitions and States of LSI Figure 6.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state of the program by executing a SLEEP instruction. Interrupts allow for returning from the program halt state to the program execution state of the program. A direct transition from active mode to active mode changes the operating frequency. RES input enables transitions from a mode to the reset state. Table 6.2 shows the transition conditions of each mode after the SLEEP instruction is executed and a mode to return by an interrupt. Table 6.3 shows the internal states of the LSI in each mode. Reset state Program halt state Program execution state SLEEP instruction Direct transition interrupt SLEEP instruction Sleep mode Active mode Standby mode Interrupt Program halt state Interrupt SLEEP instruction Interrupt Subsleep mode Notes: 1. To make a transition to another mode by an interrupt, make sure interrupt handling is after the interrupt is accepted. 2. Details on the mode transition conditions are given in table 6.2. Figure 6.1 Mode Transition Diagram Rev. 3.00 Sep. 14, 2006 Page 91 of 408 REJ09B0105-0300 Section 6 Power-Down Modes Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling DTON SSBY SMSEL Transition Mode after SLEEP Transition Mode due to Instruction Execution Interrupt 0 0 0 Sleep mode Active mode 0 1 Subsleep mode Active mode 1 X Standby mode Active mode X 0* Active mode (direct transition) -- 1 [Legend] X: Don't care Note: * When a state transition is performed while SMSEL is 1, timer V, SCI3, and the A/D converter are reset, and all registers are set to their initial values. To use these functions after entering active mode, reset the registers. Table 6.3 Internal State in Each Operating Mode Function Active Mode Sleep Mode Subsleep Mode Standby Mode System clock oscillator Functioning Functioning Halted Halted CPU Instructions operations Registers Functioning Halted Halted Halted Functioning Retained Retained Retained RAM Functioning Retained Retained Retained IO ports Functioning Retained Retained Register contents are retained, but output is the high-impedance state. IRQ3, IRQ0 Functioning Functioning Functioning Functioning WKP5 Functioning Functioning Functioning Functioning Peripheral Timer B1 modules Timer V Functioning Functioning Retained Retained Functioning Functioning Reset Reset Timer W Functioning Functioning Retained Retained Watchdog timer Functioning Functioning Retained (Functioning if the internal oscillator is selected as a count clock.) SCI3 Functioning Functioning Reset Reset IIC2 Functioning Functioning Retained Retained A/D converter Functioning Functioning Reset Reset LVD Functioning Functioning Functioning Functioning External interrupts Rev. 3.00 Sep. 14, 2006 Page 92 of 408 REJ09B0105-0300 Section 6 Power-Down Modes 6.2.1 Sleep Mode In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock frequency set by the MA2 to MA0 bits in SYSCR2. CPU register contents are retained. When an interrupt is requested, sleep mode is cleared and the CPU starts interrupt exception handling. Sleep mode is not cleared if the I bit in the condition code register (CCR) is set to 1 or the requested interrupt is disabled by the interrupt enable bit. When the RES pin is driven low in sleep mode, the CPU goes into the reset state and sleep mode is cleared. 6.2.2 Standby Mode In standby mode, the system clock oscillator is halted, and operation of the CPU and on-chip peripheral modules is halted. However, as long as the rated voltage is supplied, the contents of CPU registers, on-chip RAM, and some on-chip peripheral module registers are retained. On-chip RAM contents will be retained as long as the voltage set by the RAM data retention voltage is provided. The I/O ports go to the high-impedance state. Standby mode is cleared by an interrupt. When an interrupt is requested, the on-chip oscillator starts functioning. The external oscillator also starts functioning when used. After the time set by the STS2 to STS0 bits in SYSCR1 has elapsed, standby mode is cleared and the CPU starts interrupt exception handling. Standby mode is not cleared if the I bit in the condition code register (CCR) is set to 1 or the requested interrupt is disabled by the interrupt enable bit. When the RES pin is driven low in standby mode, the on-chip oscillator starts functioning. The system clock is supplied to the entire chip as soon as the on-chip oscillator starts functioning. The RES pin must be kept low for the rated period. On driving the RES pin high, after the oscillation stabilization time set by the power-on reset circuit has elapsed, the internal reset signal is cleared and the CPU starts reset exception handling. Rev. 3.00 Sep. 14, 2006 Page 93 of 408 REJ09B0105-0300 Section 6 Power-Down Modes 6.2.3 Subsleep Mode In subsleep mode, the system clock oscillator is halted, and operation of the CPU and on-chip peripheral modules is halted. However, as long as the rated voltage is supplied, the contents of CPU registers, the on-chip RAM, and some on-chip peripheral module registers are retained. The I/O ports keep the same states as before the transition. Subsleep mode is cleared by an interrupt. When an interrupt is requested, the on-chip oscillator starts functioning. The external oscillator also starts functioning when used. After the time set by the STS2 to STS0 bits in SYSCR1 has elapsed, subsleep mode is cleared and the CPU starts interrupt exception handling. Subsleep mode is not cleared if the I bit in the condition code register (CCR) is set to 1 or the requested interrupt is disabled by the interrupt enable bit. When the RES pin is driven low in subsleep mode, the on-chip oscillator starts functioning. The system clock is supplied to the entire chip as soon as the on-chip oscillator starts functioning. The RES pin must be kept low for the rated period. On driving the RES pin high, after the oscillation stabilization time set by the power-on reset circuit has elapsed, the internal reset signal is cleared and the CPU starts reset exception handling. 6.3 Operating Frequency in Active Mode Operation in active mode is clocked at the frequency designated by the MA2 to MA0 bits in SYSCR2. The operating frequency changes to the set frequency after SLEEP instruction execution. 6.4 Direct Transition The CPU can execute programs in active mode. The operating frequency can be changed by making a transition directly from active mode to active mode. A direct transition can be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1. If the direct transition interrupt is disabled by the interrupt enable register 1, a transition is made instead to sleep mode or subsleep mode. Note that if a direct transition is attempted while the I bit in condition code register (CCR) is set to 1, sleep mode or subsleep mode will be entered though that mode cannot be cleared by means of an interrupt. Rev. 3.00 Sep. 14, 2006 Page 94 of 408 REJ09B0105-0300 Section 6 Power-Down Modes 6.5 Module Standby Function The module standby function can be set to any peripheral module. In module standby mode, the clock supply to the specified module stops and the module enters the power-down mode. Module standby mode enables each on-chip peripheral module to enter the standby state by setting a bit that corresponds to each module in MSTCR1 and MSTCR2 to 1 and cancels the mode by clearing the bit to 0. Rev. 3.00 Sep. 14, 2006 Page 95 of 408 REJ09B0105-0300 Section 6 Power-Down Modes Rev. 3.00 Sep. 14, 2006 Page 96 of 408 REJ09B0105-0300 Section 7 ROM Section 7 ROM The features of the 12-kbyte (including 4 kbytes as the E7 or E8 control program area) flash memory built into the HD64F36912G and HD64F36902G are summarized below. * Programming/erase methods The flash memory is programmed in 64-byte units at a time. Erase is performed in singleblock units. The flash memory is configured as follows: 1 kbyte x 4 blocks and 4 kbytes x 2 blocks. To erase the entire flash memory, each block must be erased in turn. * Reprogramming capability The flash memory can be reprogrammed up to 1,000 times. * On-board programming On-board programming/erasing can be done in boot mode, in which the boot program built into the chip is started to erase or program of the entire flash memory. In normal user program mode, individual blocks can be erased or programmed. * Automatic bit rate adjustment For data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match the transfer bit rate of the host. * Programming/erasing protection Sets software protection against flash memory programming/erasing. 7.1 Block Configuration Figure 7.1 shows the block configuration of 12-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory is divided into 1 kbyte x 4 blocks and 4 kbytes x 2 blocks. Erasing is performed in these units. Programming is performed in 64-byte units starting from an address with lower eight bits H'00, H'40, H'80, or H'C0. ROM3321A_000120030300 Rev. 3.00 Sep. 14, 2006 Page 97 of 408 REJ09B0105-0300 Section 7 ROM Erase unit H'0000 H'0001 H'0002 H'0040 H'0041 H'0042 H'007F H'03C0 H'03C1 H'03C2 H'03FF H'0400 H'0401 H'0402 H'0440 H'0441 H'0442 H'047F H'07C0 H'07C1 H'07C2 H'07FF H'0800 H'0801 H'0802 H'0840 H'0841 H'0842 H'087F H'0BC0 H'0BC1 H'0BC2 H'0BFF H'0C00 H'0C01 H'0C02 H'0C40 H'0C41 H'0C42 Programming unit: 64 bytes H'003F 1 kbyte Erase unit Programming unit: 64 bytes H'043F 1 kbyte Erase unit Programming unit: 64 bytes H'083F 1 kbyte Erase unit Programming unit: 64 bytes H'0C3F H'0C7F 1 kbyte Erase unit H'0FC0 H'0FC1 H'0FC2 H'1000 H'1001 H'1002 H'1040 H'1041 H'1042 H'0FFF Programming unit: 64 bytes H'103F H'107F 4 kbytes Erase unit H'1FC0 H'1FC1 H'1FC2 H'2000 H'2001 H'2002 H'1FFF H'2040 H'2041 H'2042 H'207F H'2FC0 H'2FC1 H'2FC2 H'2FFF Programming unit: 64 bytes H'203F 4 kbytes Figure 7.1 Flash Memory Block Configuration Rev. 3.00 Sep. 14, 2006 Page 98 of 408 REJ09B0105-0300 Section 7 ROM 7.2 Register Descriptions The flash memory has the following registers. * * * * Flash memory control register 1 (FLMCR1) Flash memory control register 2 (FLMCR2) Erase block register 1 (EBR1) Flash memory enable register (FENR) 7.2.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 7.4, Flash Memory Programming/Erasing. Bit Bit Name Initial Value R/W 7 -- 0 -- Description Reserved This bit is always read as 0. 6 SWE 0 R/W Software Write Enable When this bit is set to 1, flash memory programming/erasing is enabled. When this bit is cleared to 0, other FLMCR1 register bits and all EBR1 bits cannot be set. 5 ESU 0 R/W Erase Setup When this bit is set to 1, the flash memory changes to the erase setup state. When it is cleared to 0, the erase setup state is cancelled. Set this bit to 1 before setting the E bit to 1 in FLMCR1. 4 PSU 0 R/W Program Setup When this bit is set to 1, the flash memory changes to the program setup state. When it is cleared to 0, the program setup state is cancelled. Set this bit to 1 before setting the P bit in FLMCR1. 3 EV 0 R/W Erase-Verify When this bit is set to 1, the flash memory changes to erase-verify mode. When it is cleared to 0, erase-verify mode is cancelled. Rev. 3.00 Sep. 14, 2006 Page 99 of 408 REJ09B0105-0300 Section 7 ROM Bit Bit Name Initial Value R/W Description 2 PV 0 R/W Program-Verify When this bit is set to 1, the flash memory changes to program-verify mode. When it is cleared to 0, programverify mode is cancelled. 1 E 0 R/W Erase When this bit is set to 1 while SWE = 1 and ESU = 1, the flash memory changes to erase mode. When it is cleared to 0, erase mode is cancelled. 0 P 0 R/W Program When this bit is set to 1 while SWE = 1 and PSU = 1, the flash memory changes to program mode. When it is cleared to 0, program mode is cancelled. 7.2.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a read-only register, and should not be written to. Bit Bit Name Initial Value R/W Description 7 FLER 0 R Flash Memory Error Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-protection state. See section 7.5.3, Error Protection, for details. 6 to 0 -- All 0 -- Reserved These bits are always read as 0. Rev. 3.00 Sep. 14, 2006 Page 100 of 408 REJ09B0105-0300 Section 7 ROM 7.2.3 Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to be automatically cleared to 0. Bit Bit Name Initial Value R/W Description 7, 6 -- All 0 -- Reserved These bits are always read as 0. 5 EB5 0 R/W When this bit is set to 1, 4 kbytes of H'2000 to H'2FFF will be erased. 4 EB4 0 R/W When this bit is set to 1, 4 kbytes of H'1000 to H'1FFF will be erased. 3 EB3 0 R/W When this bit is set to 1, 1 kbyte of H'0C00 to H'0FFF will be erased. 2 EB2 0 R/W When this bit is set to 1, 1 kbyte of H'0800 to H'0BFF will be erased. 1 EB1 0 R/W When this bit is set to 1, 1 kbyte of H'0400 to H'07FF will be erased. 0 EB0 0 R/W When this bit is set to 1, 1 kbyte of H'0000 to H'03FF will be erased. 7.2.4 Flash Memory Enable Register (FENR) Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers, FLMCR1, FLMCR2, and EBR1. Bit Bit Name Initial Value R/W Description 7 FLSHE 0 R/W Flash Memory Control Register Enable Flash memory control registers can be accessed when this bit is set to 1. Flash memory control registers cannot be accessed when this bit is set to 0. 6 to 0 -- All 0 -- Reserved These bits are always read as 0. Rev. 3.00 Sep. 14, 2006 Page 101 of 408 REJ09B0105-0300 Section 7 ROM 7.3 On-Board Programming Modes There is a mode for programming/erasing of the flash memory; boot mode, which enables onboard programming/erasing. On-board programming/erasing can also be performed in user program mode. At reset-start in reset mode, this LSI changes to a mode depending on the TEST pin settings, NMI pin settings, and input level of each port, as shown in table 7.1. The input level of each pin must be defined four states before the reset ends. When changing to boot mode, the boot program built into this LSI is initiated. The boot program transfers the programming control program from the externally-connected host to on-chip RAM via SCI3. After erasing the entire flash memory, the programming control program is executed. This can be used for programming initial values in the on-board state or for a forcible return when programming/erasing can no longer be done in user program mode. In user program mode, individual blocks can be erased and programmed by branching to the user program/erase control program prepared by the user. Table 7.1 Setting Programming Modes TEST NMI E10T_0 LSI State after Reset End 0 1 X User mode 0 0 1 Boot mode [Legend] X: Don't care 7.3.1 Boot Mode Table 7.2 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 7.4, Flash Memory Programming/Erasing. 2. SCI3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. Rev. 3.00 Sep. 14, 2006 Page 102 of 408 REJ09B0105-0300 Section 7 ROM 3. When the boot program is initiated, the chip measures the low-level period of asynchronous SCI communication data (H'00) transmitted continuously from the host. The chip then calculates the bit rate of transmission from the host, and adjusts the SCI3 bit rate to match that of the host. The reset should end with the RxD pin high. The RxD and TxD pins should be pulled up on the board if necessary. After the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period. 4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the completion of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could not be performed normally, initiate boot mode again by a reset. Depending on the host's transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit rate and system clock frequency of this LSI within the ranges listed in table 7.3. 5. In boot mode, a part of the on-chip RAM area is used by the boot program. The area H'F980 to H'FEEF is the area to which the programming control program is transferred from the host. The boot program area cannot be used until the execution state in boot mode switches to the programming control program. 6. Before branching to the programming control program, the chip terminates transfer operations by SCI3 (by clearing the RE and TE bits in SCR3 to 0), however the adjusted bit rate value remains set in BRR. Therefore, the programming control program can still use it for transfer of write data or verify data with the host. The TxD pin is high (PCR22 = 1, P22 = 1). The contents of the CPU general registers are undefined immediately after branching to the programming control program. These registers must be initialized at the beginning of the programming control program, as the stack pointer (SP), in particular, is used implicitly in subroutine calls, etc. 7. Boot mode can be cleared by a reset. End the reset after driving the reset pin low, waiting at least 20 states, and then setting the TEST pin and NMI pin. Boot mode is also cleared when a WDT overflow occurs. 8. Do not change the TEST pin and NMI pin input levels in boot mode. Rev. 3.00 Sep. 14, 2006 Page 103 of 408 REJ09B0105-0300 Section 7 ROM Boot Mode Operation Host Operation Communication Contents Processing Contents Transfer of number of bytes of programming control program Flash memory erase Bit rate adjustment Boot mode initiation Item Table 7.2 LSI Operation Processing Contents Branches to boot program at reset-start. Boot program initiation Continuously transmits data H'00 at specified bit rate. Transmits data H'55 when data H'00 is received error-free. H'00, H'00 . . . H'00 H'00 H'55 Boot program erase error H'AA reception Transmits number of bytes (N) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte) Transmits 1-byte of programming control program (repeated for N times) H'AA reception H'FF H'AA Upper bytes, lower bytes Echoback H'XX Echoback H'AA * Measures low-level period of receive data H'00. * Calculates bit rate and sets BRR in SCI3. * Transmits data H'00 to host as adjustment end indication. H'55 reception. Checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data H'AA to host. (If erase could not be done, transmits data H'FF to host and aborts operation.) Echobacks the 2-byte data received to host. Echobacks received data to host and also transfers it to RAM. (repeated for N times) Transmits data H'AA to host. Branches to programming control program transferred to on-chip RAM and starts execution. Rev. 3.00 Sep. 14, 2006 Page 104 of 408 REJ09B0105-0300 Section 7 ROM Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of LSI 9,600 bps 8 MHz (on-chip oscillator clock) 4,800 bps 8 MHz (on-chip oscillator clock) 2,400 bps 8 MHz (on-chip oscillator clock) Rev. 3.00 Sep. 14, 2006 Page 105 of 408 REJ09B0105-0300 Section 7 ROM 7.3.2 Programming/Erasing in User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board means of supplying programming data. The flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory. As the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip RAM, as in boot mode. Figure 7.2 shows a sample procedure for programming/erasing in user program mode. Prepare a user program/erase control program in accordance with the description in section 7.4, Flash Memory Programming/Erasing. Reset-start No Program/erase? Yes Transfer user program/erase control program to RAM Branch to flash memory application program Branch to user program/erase control program in RAM Execute user program/erase control program (flash memory rewrite) Branch to flash memory application program Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode Rev. 3.00 Sep. 14, 2006 Page 106 of 408 REJ09B0105-0300 Section 7 ROM 7.4 Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode. The programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. Flash memory programming and erasing should be performed in accordance with the descriptions in section 7.4.1, Program/Program-Verify and section 7.4.2, Erase/Erase-Verify, respectively. 7.4.1 Program/Program-Verify When writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 7.3 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. Programming must be done to an empty address. Do not reprogram an address to which programming has already been performed. 2. Programming should be carried out 64 bytes at a time. A 64-byte data transfer must be performed even if writing fewer than 64 bytes. In this case, H'FF data must be written to the extra addresses. 3. Prepare the following data storage areas in RAM: A 64-byte programming data area, a 64-byte reprogramming data area, and a 64-byte additional-programming data area. Perform reprogramming data computation according to table 7.4, and additional programming data computation according to table 7.5. 4. Consecutively transfer 64 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. The program address and 64-byte data are latched in the flash memory. The lower 8 bits of the start address in the flash memory destination area must be H'00, H'40, H'80, or H'C0. 5. The time during which the P bit is set to 1 is the programming time. Table 7.6 shows the allowable programming times. 6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. An overflow cycle of approximately 6.6 ms is allowed. 7. For a dummy write to a verify address, write 1-byte data H'FF to an even address. Verify data can be read in words from the address to which a dummy write was performed. 8. The maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000. Rev. 3.00 Sep. 14, 2006 Page 107 of 408 REJ09B0105-0300 Section 7 ROM START Write pulse application subroutine *2 Disable WDT Apply Write Pulse Set SWE bit in FLMCR1 WDT enable Wait 1 s Set PSU bit in FLMCR1 Store 64-byte program data in program data area and reprogram data area *1 Wait 50 s n=1 Set P bit in FLMCR1 m= 0 Wait (Wait time = Programming time) Clear P bit in FLMCR1 Write 64-byte data in RAM reprogram data area consecutively to flash memory Wait 5 s Apply Write pulse Clear PSU bit in FLMCR1 Set PV bit in FLMCR1 Wait 4 s Wait 5 s Disable WDT Set block start address as verify address End Sub H'FF dummy write to verify address nn+1 Wait 2 s *1 Read verify data Increment address No Verify data = Write data? m=1 Yes n6? No Yes Additional-programming data computation Reprogram data computation No 64-byte data verification completed? Yes Clear PV bit in FLMCR1 Wait 2 s n 6? No Yes Successively write 64-byte data from additionalprogramming data area in RAM to flash memory Sub-Routine-Call Apply Write Pulse m=0? Yes Clear SWE bit in FLMCR1 No n 1000 ? Wait 100 s Wait 100 s End of programming Programming failure Notes: 1. The RTS instruction must not be used during the following (1) and (2) periods. (1) A period between 64-byte data programming to flash memory and the P bit clearing (2) A period between dummy writing of H'FF to a verify address and verify data reading 2. When WDT is in use, disable it once. Figure 7.3 Program/Program-Verify Flowchart Rev. 3.00 Sep. 14, 2006 Page 108 of 408 REJ09B0105-0300 Yes No Clear SWE bit in FLMCR1 Section 7 ROM Table 7.4 Reprogram Data Computation Table Program Data Verify Data Reprogram Data Comments 0 0 1 Programming completed 0 1 0 Reprogram bit 1 0 1 -- 1 1 1 Remains in erased state Table 7.5 Additional-Program Data Computation Table Reprogram Data Verify Data Additional-Program Data Comments 0 0 0 Additional-program bit 0 1 1 No additional programming 1 0 1 No additional programming 1 1 1 No additional programming n Programming (Number of Writes) Time In Additional Programming Comments 1 to 6 30 10 7 to 1,000 200 -- Table 7.6 Programming Time Note: Time shown in s. 7.4.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 7.4 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register (EBR1). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. An overflow cycle of approximately 19.8 ms is allowed. 5. For a dummy write to a verify address, write 1-byte data H'FF to an even address. Verify data can be read in words from the address to which a dummy write was performed. Rev. 3.00 Sep. 14, 2006 Page 109 of 408 REJ09B0105-0300 Section 7 ROM 6. If the read data is not erased successfully, set erase mode again, and repeat the erase/eraseverify sequence as before. The maximum number of repetitions of the erase/erase-verify sequence is 100. 7.4.3 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including the NMI interrupt, are disabled while flash memory is being programmed or erased, or while the boot program is executing, for the following three reasons: 1. Interrupt during programming/erasing may cause a violation of the programming or erasing algorithm, with the result that normal operation cannot be assured. 2. If interrupt exception handling starts before the vector address is written or during programming/erasing, a correct vector cannot be fetched and the CPU malfunctions. 3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be carried out. Rev. 3.00 Sep. 14, 2006 Page 110 of 408 REJ09B0105-0300 Section 7 ROM Erase start *2 Disable WDT SWE bit 1 Wait 1 s n1 Set EBR1 Enable WDT ESU bit 1 Wait 100 s E bit 1 Wait 10 ms E bit 0 Wait 10 s ESU bit 10 Wait 10 s Disable WDT EV bit 1 Wait 20 s Set block start address as verify address H'FF dummy write to verify address Wait 2 s *1 nn+1 Read verify data No Verify data = all 1s ? Increment address Yes No Last address of block ? Yes No EV bit 0 EV bit 0 Wait 4 s Wait 4s All erase block erased ? n 100 ? Yes Yes No Yes SWE bit 0 SWE bit 0 Wait 100 s Wait 100 s End of erasing Erase failure Notes: 1. The RTS instruction must not be used during a period between dummy writing of H'FF to a verify address and verify data reading. 2. When WDT is in use, disable it once. Figure 7.4 Erase/Erase-Verify Flowchart Rev. 3.00 Sep. 14, 2006 Page 111 of 408 REJ09B0105-0300 Section 7 ROM 7.5 Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subsleep mode or standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), and erase block register 1 (EBR1) are initialized. In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the AC Characteristics section. 7.5.2 Software Protection Software protection can be implemented against programming/erasing of all flash memory blocks by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P or E bit in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase block register 1 (EBR1), erase protection can be set for individual blocks. When EBR1 is set to H'00, erase protection is set for all blocks. 7.5.3 Error Protection In error protection, an error is detected when CPU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. When the following errors are detected during programming/erasing of flash memory, the FLER bit in FLMCR2 is set to 1, and the error protection state is entered. * When the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) * Immediately after exception handling excluding a reset during programming/erasing * When a SLEEP instruction is executed during programming/erasing Rev. 3.00 Sep. 14, 2006 Page 112 of 408 REJ09B0105-0300 Section 7 ROM The FLMCR1, FLMCR2, and EBR1 settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be reentered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. Error protection can be cleared only by a reset. Rev. 3.00 Sep. 14, 2006 Page 113 of 408 REJ09B0105-0300 Section 7 ROM Rev. 3.00 Sep. 14, 2006 Page 114 of 408 REJ09B0105-0300 Section 8 RAM Section 8 RAM The H8/36912F and H8/36902F have 1536 bytes, the H8/36912 and H8/36902 have 512 bytes, and the H8/36911, H8/36901, and H8/36900 have 256 bytes of on-chip high-speed static RAM, respectively. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by the CPU to both byte data and word data. Product Classification Flash memory version Masked ROM version Note: * RAM Size RAM Address H8/36912F 1536 bytes H'F980 to H'FF7F* H8/36902F 1536 bytes H'F980 to H'FF7F* H8/36912, H8/36902 512 bytes H'FD80 to H'FF7F H8/36911, H8/36901 256 bytes H'FE80 to H'FF7F H8/36900 256 bytes H'FE80 to H'FF7F When the E7 or E8 is used, area H'F980 to H'FD7F must not be accessed. RAM0400A_000020020200 Rev. 3.00 Sep. 14, 2006 Page 115 of 408 REJ09B0105-0300 Section 8 RAM Rev. 3.00 Sep. 14, 2006 Page 116 of 408 REJ09B0105-0300 Section 9 I/O Ports Section 9 I/O Ports The LSI of the H8/36912 Group and H8/36902 Group has 18 general I/O ports. Port 8 (P84 to P80) is a large current port, which can drive 20 mA (@VOL = 1.5 V) when a low level signal is output. Any of these ports can become an input port immediately after a reset. They can also be used as I/O pins of the on-chip peripheral modules or external interrupt input pins, and these functions can be switched depending on the register settings. The registers for selecting these functions can be divided into two types: those included in I/O ports and those included in each onchip peripheral module. General I/O ports are comprised of the port control register for controlling inputs/outputs and the port data register for storing output data and can select inputs/outputs in bit units. For functions in each port, see appendix B.1, I/O Port Block Diagrams. For the execution of bit manipulation instructions to the port control register and port data register, see section 2.8.3, Bit Manipulation Instruction. 9.1 Port 1 Port 1 is a general I/O port also functioning as an IRQ interrupt input pin and timer V input pin. Figure 9.1 shows its pin configuration. Port 1 P17/IRQ3/TRGV P14/IRQ0 Figure 9.1 Port 1 Pin Configuration Port 1 has the following registers. * * * * Port mode register 1 (PMR1) Port control register 1 (PCR1) Port data register 1 (PDR1) Port pull-up control register 1 (PUCR1) Rev. 3.00 Sep. 14, 2006 Page 117 of 408 REJ09B0105-0300 Section 9 I/O Ports 9.1.1 Port Mode Register 1 (PMR1) PMR1 switches the functions of pins in port 1 and port 2. Bit Bit Name Initial Value R/W Description 7 IRQ3 0 R/W P17/IRQ3/TRGV Pin Function Switch Selects whether pin P17/IRQ3/TRGV is used as P17 or as IRQ3/TRGV. 0: General I/O port 1: IRQ3/TRGV input pin 6, 5 All 0 Reserved These bits are always read as 0. 4 IRQ0 0 R/W P14/IRQ0 Pin Function Switch Selects whether pin P14/IRQ0 is used as P14 or as IRQ0. 0: General I/O port 1: IRQ0 input pin 3, 2 All 0 Reserved These bits are always read as 0. 1 TXD 0 R/W P22/TXD Pin Function Switch Selects whether pin P22/TXD is used as P22 or as TXD. 0: General I/O port 1: TXD output pin 0 0 Reserved This bit is always read as 0. Rev. 3.00 Sep. 14, 2006 Page 118 of 408 REJ09B0105-0300 Section 9 I/O Ports 9.1.2 Port Control Register 1 (PCR1) PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1. Bit Bit Name Initial Value R/W Description 7 PCR17 0 W 6 5 When the corresponding pin is designated in PMR1 as a general I/O pin, setting a PCR1 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 4 PCR14 0 W Bits 6, 5, and 3 to 0 are reserved. 3 2 1 0 9.1.3 Port Data Register 1 (PDR1) PDR1 is a general I/O port data register of port 1. Bit Bit Name Initial Value R/W Description 7 P17 0 R/W These bits store output data for port 1 pins. 6 1 5 1 4 P14 0 R/W If PDR1 is read while PCR1 bits are set to 1, the value stored in PDR1 are read. If PDR1 is read while PCR1 bits are cleared to 0, the pin states are read regardless of the value stored in PDR1. 3 1 2 1 1 1 0 1 Bits 6, 5, and 3 to 0 are reserved. These bits are always read as 1. Rev. 3.00 Sep. 14, 2006 Page 119 of 408 REJ09B0105-0300 Section 9 I/O Ports 9.1.4 Port Pull-Up Control Register 1 (PUCR1) PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports. Bit Bit Name Initial Value R/W Description 7 PUCR17 0 R/W Only bits for which PCR1 is cleared are valid. 6 1 5 1 4 PUCR14 0 R/W The pull-up MOS of the P17 and P14 pins enter the onstate when these bits are set to 1, while they enter the off-state when these bits are cleared to 0. 3 1 2 1 1 1 0 1 9.1.5 Pin Functions Bits 6, 5, and 3 to 0 are reserved. These bits are always read as 1. The correspondence between the register specification and the port functions is shown below. * P17/IRQ3/TRGV pin Register PMR1 PCR1 Bit Name IRQ3 PCR17 Pin Function 0 P17 input pin 1 P17 output pin X IRQ3 input/TRGV input pin Setting value 0 1 [Legend] X: Don't care Rev. 3.00 Sep. 14, 2006 Page 120 of 408 REJ09B0105-0300 Section 9 I/O Ports * P14/IRQ0 pin Register PMR1 PCR1 Bit Name IRQ0 PCR14 Pin Function 0 P14 input pin 1 P14 output pin X IRQ0 input pin Setting value 0 1 [Legend] X: Don't care 9.2 Port 2 Port 2 is a general I/O port also functioning as a SCI3 I/O pin. Each pin of the port 2 is shown in figure 9.2. The register settings of PMR1 and SCI3 have priority for functions of the pins for both uses. P22/TXD Port 2 P21/RXD P20/SCK3 Figure 9.2 Port 2 Pin Configuration Port 2 has the following registers. * Port control register 2 (PCR2) * Port data register 2 (PDR2) Rev. 3.00 Sep. 14, 2006 Page 121 of 408 REJ09B0105-0300 Section 9 I/O Ports 9.2.1 Port Control Register 2 (PCR2) PCR2 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 2. Bit Bit Name Initial Value R/W Description 7 to 3 Reserved 2 PCR22 0 W 1 PCR21 0 W 0 PCR20 0 W When each of the port 2 pins, P22 to P20, functions as an general I/O port, setting a PCR2 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 9.2.2 Port Data Register 2 (PDR2) PDR2 is a general I/O port data register of port 2. Bit Bit Name Initial Value R/W Description 7 to 3 All 1 Reserved These bits are always read as 1. 2 P22 0 R/W These bits store output data for port 2 pins. 1 P21 0 R/W 0 P20 0 R/W If PDR2 is read while PCR2 bits are set to 1, the value stored in PDR2 is read. If PDR2 is read while PCR2 bits are cleared to 0, the pin states are read regardless of the value stored in PDR2. Rev. 3.00 Sep. 14, 2006 Page 122 of 408 REJ09B0105-0300 Section 9 I/O Ports 9.2.3 Pin Functions The correspondence between the register specification and the port functions is shown below. * P22/TXD pin Register PMR1 PCR2 Bit Name TXD PCR22 Pin Function Setting value 0 0 P22 input pin 1 P22 output pin X TXD output pin 1 [Legend] X: Don't care * P21/RXD pin Register SCR3 PCR2 Bit Name RE PCR21 Pin Function Setting value 0 0 P21 input pin 1 P21 output pin X RXD input pin 1 [Legend] X: Don't care * P20/SCK3 pin Register SCR3 Bit Name CKE1 Setting value 0 SMR PCR2 CKE0 COM PCR20 Pin Function 0 0 0 P20 input pin 1 P20 output pin 0 0 1 X SCK3 output pin 0 1 X X SCK3 output pin 1 X X X SCK3 input pin [Legend] X: Don't care Rev. 3.00 Sep. 14, 2006 Page 123 of 408 REJ09B0105-0300 Section 9 I/O Ports 9.3 Port 5 Port 5 is a general I/O port also functioning as an I2C bus interface I/O pin*, A/D trigger input pin, and wakeup interrupt input pin. Each pin of the port 5 is shown in figure 9.3. The register setting of the I2C bus interface has priority for functions of the P57/SCL and P56/SDA pins. Note: * Supported only by the H8/36912 Group. P57/SCL Port 5 P56/SDA P55/WKP5/ADTRG Figure 9.3 Port 5 Pin Configuration Port 5 has the following registers. * * * * Port mode register 5 (PMR5) Port control register 5 (PCR5) Port data register 5 (PDR5) Port pull-up control register 5 (PUCR5) Rev. 3.00 Sep. 14, 2006 Page 124 of 408 REJ09B0105-0300 Section 9 I/O Ports 9.3.1 Port Mode Register 5 (PMR5) PMR5 switches the functions of pins in port 5. Bit Bit Name Initial Value R/W 7, 6 All 0 Description Reserved These bits are always read as 0. 5 WKP5 0 R/W P55/WKP5/ADTRG Pin Function Switch Selects whether pin P55/WKP5/ADTRG is used as P55 or as WKP5/ADTRG. 0: General I/O port 1: WKP5/ADTRG input pin 4 to 0 All 0 Reserved These bits are always read as 0. 9.3.2 Port Control Register 5 (PCR5) PCR5 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 5. Bit Bit Name Initial Value R/W Description 7 PCR57 0 W 6 PCR56 0 W 5 PCR55 0 W When each of the port 5 pins, P57 to P55, functions as an general I/O port, setting a PCR5 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 4 to 0 Reserved Rev. 3.00 Sep. 14, 2006 Page 125 of 408 REJ09B0105-0300 Section 9 I/O Ports 9.3.3 Port Data Register 5 (PDR5) PDR5 is a general I/O port data register of port 5. Bit Bit Name Initial Value R/W Description 7 P57 0 R/W These bits store output data for port 5 pins. 6 P56 0 R/W 5 P55 0 R/W If PDR5 is read while PCR5 bits are set to 1, the value stored in PDR5 are read. If PDR5 is read while PCR5 bits are cleared to 0, the pin states are read regardless of the value stored in PDR5. 4 to 0 All 1 Reserved These bits are always read as 1. 9.3.4 Port Pull-Up Control Register 5 (PUCR5) PUCR5 controls the pull-up MOS in bit units of the pins set as the input ports. Bit Bit Name Initial Value R/W Description 7, 6 All 0 Reserved These bits are always read as 0. 5 PUCR55 0 R/W Only bits for which PCR5 is cleared are valid. The pull-up MOS of the corresponding pins enter the onstate when this bit is set to 1, while they enter the offstate when this bit is cleared to 0. 4 to 0 All 0 Reserved These bits are always read as 0. Rev. 3.00 Sep. 14, 2006 Page 126 of 408 REJ09B0105-0300 Section 9 I/O Ports 9.3.5 Pin Functions The correspondence between the register specification and the port functions is shown below. * P57/SCL pin Register ICCR PCR5 Bit Name ICE PCR57 Pin Function 0 P57 input pin 1 P57 output pin X SCL I/O pin* Setting value 0 1 [Legend] X: Don't care Note: As the SCL output form is NMOS open-drain, direct bus drive is enabled. * Supported only by the H8/36912 Group. * P56/SDA pin Register ICCR PCR5 Bit Name ICE PCR56 Pin Function 0 P56 input pin 1 P56 output pin X SDA I/O pin* Setting value 0 1 [Legend] X: Don't care Note: As the SDA output form is NMOS open-drain, direct bus drive is enabled. * Supported only by the H8/36912 Group. * P55/WKP5/ADTRG pin Register PMR5 PCR5 Bit Name WKP5 PCR55 Pin Function 0 P55 input pin 1 P55 output pin X WKP5/ADTRG input pin Setting value 0 1 [Legend] X: Don't care Rev. 3.00 Sep. 14, 2006 Page 127 of 408 REJ09B0105-0300 Section 9 I/O Ports 9.4 Port 7 Port 7 is a general I/O port also functioning as a timer V I/O pin. Each pin of the port 7 is shown in figure 9.4. The register setting of TCSRV in timer V has priority for functions of the P76/TMOV pin. The pins, P75/TMCIV and P74/TMRIV, are also functioning as timer V input ports that are connected to the timer V regardless of the register setting of port 7. P76/TMOV Port 7 P75/TMCIV P74/TMRIV Figure 9.4 Port 7 Pin Configuration Port 7 has the following registers. * Port control register 7 (PCR7) * Port data register 7 (PDR7) 9.4.1 Port Control Register 7 (PCR7) PCR7 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 7. Bit Bit Name Initial Value R/W Description 7 Reserved 6 PCR76 0 W 5 PCR75 0 W 4 PCR74 0 W Setting a PCR7 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. Note that the TCSRV setting of the timer V has priority for deciding input/output direction of the P76/TMOV pin. 3 to 0 Rev. 3.00 Sep. 14, 2006 Page 128 of 408 REJ09B0105-0300 Reserved Section 9 I/O Ports 9.4.2 Port Data Register 7 (PDR7) PDR7 is a general I/O port data register of port 7. Bit Bit Name Initial Value R/W 7 1 Description Reserved This bit is always read as 1. 6 P76 0 R/W These bits store output data for port 7 pins. 5 P75 0 R/W 4 P74 0 R/W If PDR7 is read while PCR7 bits are set to 1, the value stored in PDR7 is read. If PDR7 is read while PCR7 bits are cleared to 0, the pin states are read regardless of the value stored in PDR7. 3 to 0 All 1 Reserved These bits are always read as 1. 9.4.3 Pin Functions The correspondence between the register specification and the port functions is shown below. * P76/TMOV pin Register TCSRV Bit Name OS3 to OS0 PCR76 Setting value 0000 Other than the above values PCR7 Pin Function 0 P76 input pin 1 P76 output pin X TMOV output pin [Legend] X: Don't care Rev. 3.00 Sep. 14, 2006 Page 129 of 408 REJ09B0105-0300 Section 9 I/O Ports * P75/TMCIV pin Register PCR7 Bit Name PCR75 Setting value 0 1 Pin Function P75 input/TMCIV input pin P75 output/TMCIV input pin * P74/TMRIV pin Register PCR7 Bit Name PCR74 Setting value 0 1 9.5 Pin Function P74 input/TMRIV input pin P74 output/TMRIV input pin Port 8 Port 8 is a general I/O port also functioning as a timer W I/O pin. Each pin of the port 8 is shown in figure 9.5. The register setting of the timer W has priority for functions of the P84/FTIOD, P83/FTIOC, P82/FTIOB, and P81/FTIOA pins. The P80/FTCI pin also functions as a timer W input port that is connected to the timer W regardless of the register setting of port 8. P84/FTIOD P83/FTIOC Port 8 P82/FTIOB P81/FTIOA P80/FTCI Figure 9.5 Port 8 Pin Configuration Port 8 has the following registers. * Port control register 8 (PCR8) * Port data register 8 (PDR8) Rev. 3.00 Sep. 14, 2006 Page 130 of 408 REJ09B0105-0300 Section 9 I/O Ports 9.5.1 Port Control Register 8 (PCR8) PCR8 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 8. Bit Bit Name Initial Value R/W 7 to 5 Reserved 4 PCR84 0 W 3 PCR83 0 W 2 PCR82 0 W When each of the port 8 pins, P84 to P80, functions as an general I/O port, setting a PCR8 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 1 PCR81 0 W 0 PCR80 0 W 9.5.2 Port Data Register 8 (PDR8) Description PDR8 is a general I/O port data register of port 8. Bit Bit Name Initial Value R/W Description 7 to 5 All 0 Reserved 4 P84 0 R/W These bits store output data for port 8 pins. 3 P83 0 R/W 2 P82 0 R/W 1 P81 0 R/W If PDR8 is read while PCR8 bits are set to 1, the value stored in PDR8 is read. If PDR8 is read while PCR8 bits are cleared to 0, the pin states are read regardless of the value stored in PDR8. 0 P80 0 R/W Rev. 3.00 Sep. 14, 2006 Page 131 of 408 REJ09B0105-0300 Section 9 I/O Ports 9.5.3 Pin Functions The correspondence between the register specification and the port functions is shown below. * P84/FTIOD pin Register TMRW Bit Name PWMD Setting value 0 1 TIOR1 PCR8 IOD2 IOD1 IOD0 PCR84 Pin Function 0 0 0 0 P84 input/FTIOD input pin 1 P84 output/FTIOD input pin 0 0 1 X FTIOD output pin 0 1 X X FTIOD output pin 1 X X 0 P84 input/FTIOD input pin 1 P84 output/FTIOD input pin X PWM output pin X X X [Legend] X: Don't care * P83/FTIOC pin Register TMRW Bit Name PWMC Setting value 0 1 TIOR1 IOC2 IOC1 IOC0 PCR83 Pin Function 0 0 0 0 P83 input/FTIOC input pin 1 P83 output/FTIOC input pin 0 0 1 X FTIOC output pin 0 1 X X FTIOC output pin 1 X X 0 P83 input/FTIOC input pin 1 P83 output/FTIOC input pin X PWM output pin X X [Legend] X: Don't care Rev. 3.00 Sep. 14, 2006 Page 132 of 408 REJ09B0105-0300 PCR8 X Section 9 I/O Ports * P82/FTIOB pin Register TMRW Bit Name PWMB Setting value 0 1 TIOR0 PCR8 IOB2 IOB1 IOB0 PCR82 Pin Function 0 0 0 0 P82 input/FTIOB input pin 1 P82 output/FTIOB input pin 0 0 1 X FTIOB output pin 0 1 X X FTIOB output pin 1 X X 0 P82 input/FTIOB input pin 1 P82 output/FTIOB input pin X PWM output pin X X X [Legend] X: Don't care * P81/FTIOA pin Register Bit Name TIOR0 IOA2 Setting value 0 PCR8 IOA1 IOA0 PCR81 Pin Function 0 0 0 P81 input/FTIOA input pin 1 P81 output/FTIOA input pin 0 0 1 X FTIOA output pin 0 1 X X FTIOA output pin 1 X X 0 P81 input/FTIOA input pin 1 P81 output/FTIOA input pin [Legend] X: Don't care * P80/FTCI pin Register PCR8 Bit Name PCR80 Setting value 0 1 Pin Function P80 input/FTCI input pin P80 output/FTCI input pin Rev. 3.00 Sep. 14, 2006 Page 133 of 408 REJ09B0105-0300 Section 9 I/O Ports 9.6 Port B Port B is an input port also functioning as an A/D converter analog input pin and LVD external comparison voltage input pin. Each pin of the port B is shown in figure 9.6. PB3/AN3/ExtU PB2/AN2/ExtD Port B PB1/AN1 PB0/AN0 Figure 9.6 Port B Pin Configuration Port B has the following register. * Port data register B (PDRB) 9.6.1 Port Data Register B (PDRB) PDRB is a general input-only port data register of port B. Bit Bit Name Initial Value R/W Description 7 to 4 Reserved 3 PB3 R 2 PB2 R The input value of each pin is read by reading this register. 1 PB1 R 0 PB0 R Rev. 3.00 Sep. 14, 2006 Page 134 of 408 REJ09B0105-0300 However, if a port B pin is designated as an analog input channel by ADCSR in A/D converter or external comparison voltage input pin by LVDCR in low-voltage detection circuit, 0 is read. Section 9 I/O Ports 9.6.2 Pin Functions The correspondence between the register specification and the port functions is shown below. * PB3/AN3/ExtU pin Register Bit Name ADCSR CH2 Setting value 0 LVDCR CH1 CH0 1 1 Other than the above values VDDII Pin Function 1 AN3 input pin 0 AN3 input/ExtU input pin 1 PB3 input pin 0 PB3 input/ExtU input pin * PB2/AN2/ExtD pin Register Bit Name ADCSR CH2 LVDCR SCAN CH1 CH0 VDDII Pin Function Setting value 0 0 1 0 1 AN2 input pin 0 1 1 X Other than the above values 0 AN2 input/ExtD input pin 1 PB2 input pin 0 PB2 input/ExtD input pin [Legend] X: Don't care * PB1/AN1 pin Register Bit Name ADCSR CH2 SCAN CH1 CH0 Pin Function Setting value 0 X 0 1 AN1 input pin 0 1 1 X Other than the above values PB1 input pin [Legend] X: Don't care Rev. 3.00 Sep. 14, 2006 Page 135 of 408 REJ09B0105-0300 Section 9 I/O Ports * PB0/AN0 pin Register ADCSR Bit Name CH2 SCAN CH1 CH0 Pin Function Setting value 0 0 0 0 AN0 input pin 0 1 X X Other than the above values PB0 input pin [Legend] X: Don't care 9.7 Port C Port C is a general I/O port also functioning as an external oscillation pin and clock output pin. Each pin of the port C is shown in figure 9.7. The register setting of CKCSR has priority for functions of the pins for both uses. Port C PC1/OSC2/CLKOUT PC0/OSC1 Figure 9.7 Port C Pin Configuration Port C has the following registers. * Port control register C (PCRC) * Port data register C (PDRC) Rev. 3.00 Sep. 14, 2006 Page 136 of 408 REJ09B0105-0300 Section 9 I/O Ports 9.7.1 Port Control Register C (PCRC) PCRC selects inputs/outputs in bit units for pins to be used as general I/O ports of port C. Bit Bit Name Initial Value R/W 7 to 2 Reserved 1 PCRC1 0 W 0 PCRC0 0 W When each of the port C pins, PC1 and PC0, functions as an general I/O port, setting a PCRC bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 9.7.2 Port Data Register C (PDRC) Description PDRC is a general I/O port data register of port C. Bit Bit Name Initial Value R/W Description 7 to 2 Reserved 1 PC1 0 R/W These bits store output data for port C pins. 0 PC0 0 R/W If PDRC is read while PCRC bits are set to 1, the value stored in PDRC is read. If PDRC is read while PCRC bits are cleared to 0, the pin states are read regardless of the value stored in PDRC. Rev. 3.00 Sep. 14, 2006 Page 137 of 408 REJ09B0105-0300 Section 9 I/O Ports 9.7.3 Pin Functions The correspondence between the register specification and the port functions is shown below. * PC1/OSC2/CLKOUT pin Register CKCSR Bit Name PMRC1 PMRC0 Setting value 0 X 1 PCRC PCRC1 Pin Function 0 PC1 input pin 1 PC1 output pin 0 X CLKOUT output pin 1 X OSC2 oscillation pin [Legend] X: Don't care * PC0/OSC1 pin Register CKCSR PCRC Bit Name PMRC0 PCRC0 Pin Function 0 PC0 input pin 1 PC0 output pin X OSC1 oscillation pin Setting value 0 1 [Legend] X: Don't care Rev. 3.00 Sep. 14, 2006 Page 138 of 408 REJ09B0105-0300 Section 10 Timer B1 Section 10 Timer B1 Timer B1 is an 8-bit timer that increments each time a clock pulse is input. This timer has two operating modes, interval and auto reload. Figure 10.1 shows a block diagram of timer B1. 10.1 Features * Selection of seven internal clock sources (/8192, /2048, /512, /256, /64, /16, and /4) * An interrupt is generated when the counter overflows. PSS TCB1 Internal data bus TMB1 TLB1 [Legend] TMB1: TCB1: TLB1: IRRTB1: PSS: Timer mode register B1 Timer counter B1 Timer load register B1 Timer B1 interrupt request flag Prescaler S IRRTB1 Figure 10.1 Block Diagram of Timer B1 TIM08B0A_000020020200 Rev. 3.00 Sep. 14, 2006 Page 139 of 408 REJ09B0105-0300 Section 10 Timer B1 10.2 Register Descriptions The timer B1 has the following registers. * Timer mode register B1 (TMB1) * Timer counter B1 (TCB1) * Timer load register B1 (TLB1) 10.2.1 Timer Mode Register B1 (TMB1) TMB1 selects the auto-reload function and input clock. Bit Bit Name Initial Value R/W Description 7 TMB17 0 R/W Auto-Reload Function Select 0: Interval timer function selected 1: Auto-reload function selected 6 1 R/W Reserved Although this bit is readable/writable, it should not be set to 0. 5 to 3 All 1 Reserved These bits are always read as 1. 2 TMB12 0 R/W Clock Select 1 TMB11 0 R/W 000: Internal clock: /8192 0 TMB10 0 R/W 001: Internal clock: /2048 010: Internal clock: /512 011: Internal clock: /256 100: Internal clock: /64 101: Internal clock: /16 110: Internal clock: /4 111: Reserved (setting prohibited) Rev. 3.00 Sep. 14, 2006 Page 140 of 408 REJ09B0105-0300 Section 10 Timer B1 10.2.2 Timer Counter B1 (TCB1) TCB1 is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMB12 to TMB10 in TMB1. TCB1 values can be read by the CPU at any time. When TCB1 overflows from H'FF to H'00 or to the value set in TLB1, the IRRTB1 flag in IRR2 is set to 1. TCB1 is allocated to the same address as TLB1. 10.2.3 Timer Load Register B1 (TLB1) TLB1 is an 8-bit write-only register for setting the reload value of TCB1. When a reload value is set in TLB1, the same value is loaded into TCB1 as well, and TCB1 starts counting up from that value. When TCB1 overflows during operation in auto-reload mode, the TLB1 value is loaded into TCB1. Accordingly, overflow periods can be set within the range of 1 to 256 input clocks. TLB1 is allocated to the same address as TCB1. Rev. 3.00 Sep. 14, 2006 Page 141 of 408 REJ09B0105-0300 Section 10 Timer B1 10.3 Operation 10.3.1 Interval Timer Operation When bit TMB17 in TMB1 is cleared to 0, timer B1 functions as an 8-bit interval timer. Upon reset, TCB1 is cleared to H'00 and bit TMB17 is cleared to 0, so up-counting and interval timing resume immediately. The operating clock of timer B1 is selected from seven internal clock signals output by prescaler S. The selection is made by the TMB12 to TMB10 bits in TMB1. After the count value in TMB1 reaches H'FF, the next clock signal input causes timer B1 to overflow, setting flag IRRTB1 in IRR2 to 1. If IENTB1 in IENR2 is 1, an interrupt is requested to the CPU. At overflow, TCB1 returns to H'00 and starts counting up again. During interval timer operation (TMB17 = 0), when a value is set in TLB1, the same value is set in TCB1. 10.3.2 Auto-Reload Timer Operation Setting bit TMB17 in TMB1 to 1 causes timer B1 to function as an 8-bit auto-reload timer. When a reload value is set in TLB1, the same value is loaded into TCB1, becoming the value from which TCB1 starts its count. After the count value in TCB1 reaches H'FF, the next clock signal input causes timer B1 to overflow. The TLB1 value is then loaded into TCB1, and the count continues from that value. The overflow period can be set within a range from 1 to 256 input clocks, depending on the TLB1 value. The clock sources and interrupts in auto-reload mode are the same as in interval mode. In autoreload mode (TMB17 = 1), when a new value is set in TLB1, the TLB1 value is also loaded into TCB1. Rev. 3.00 Sep. 14, 2006 Page 142 of 408 REJ09B0105-0300 Section 10 Timer B1 10.4 Timer B1 Operating Modes Table 10.1 shows the timer B1 operating modes. Table 10.1 Timer B1 Operating Modes Operating Mode Reset Active Sleep Subsleep Standby TCB1 Reset Functions Functions Halted Halted Auto-reload Reset Functions Functions Halted Halted Reset Functions Retained Retained Retained TMB1 Interval Rev. 3.00 Sep. 14, 2006 Page 143 of 408 REJ09B0105-0300 Section 10 Timer B1 Rev. 3.00 Sep. 14, 2006 Page 144 of 408 REJ09B0105-0300 Section 11 Timer V Section 11 Timer V Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external events. Comparematch signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle. Counting can be initiated by a trigger input at the TRGV pin, enabling pulse output control to be synchronized to the trigger, with an arbitrary delay from the trigger input. Figure 11.1 shows a block diagram of timer V. 11.1 Features * Choice of seven clock signals is available. Choice of six internal clock sources (/128, /64, /32, /16, /8, /4) or an external clock. * Counter can be cleared by compare match A or B, or by an external reset signal. If the count stop function is selected, the counter can be halted when cleared. * Timer output is controlled by two independent compare match signals, enabling pulse output with an arbitrary duty cycle, PWM output, and other applications. * Three interrupt sources: compare match A, compare match B, timer overflow * Counting can be initiated by trigger input at the TRGV pin. The rising edge, falling edge, or both edges of the TRGV input can be selected. TIM08V0A_000120030300 Rev. 3.00 Sep. 14, 2006 Page 145 of 408 REJ09B0105-0300 Section 11 Timer V TCRV1 TCORB Trigger control TRGV Comparator TCNTV Internal data bus Clock select TMCIV Comparator PSS TCORA TMRIV Clear control TCRV0 Interrupt request control TMOV [Legend] TCORA: TCORB: TCNTV: TCSRV: TCRV0: TCRV1: PSS: CMIA: CMIB: OVI: Output control TCSRV Time constant register A Time constant register B Timer counter V Timer control/status register V Timer control register V0 Timer control register V1 Prescaler S Compare-match interrupt A Compare-match interrupt B Overflow interrupt Figure 11.1 Block Diagram of Timer V Rev. 3.00 Sep. 14, 2006 Page 146 of 408 REJ09B0105-0300 CMIA CMIB OVI Section 11 Timer V 11.2 Input/Output Pins Table 11.1 shows the timer V pin configuration. Table 11.1 Pin Configuration Name Abbreviation I/O Function Timer V output TMOV Output Timer V waveform output Timer V clock input TMCIV Input Clock input to TCNTV Timer V reset input TMRIV Input External input to reset TCNTV Trigger input TRGV Input Trigger input to initiate counting 11.3 Register Descriptions Time V has the following registers. * * * * * * Timer counter V (TCNTV) Timer constant register A (TCORA) Timer constant register B (TCORB) Timer control register V0 (TCRV0) Timer control/status register V (TCSRV) Timer control register V1 (TCRV1) 11.3.1 Timer Counter V (TCNTV) TCNTV is an 8-bit up-counter. The clock source is selected by bits CKS2 to CKS0 in timer control register V0 (TCRV0). The TCNTV value can be read and written by the CPU at any time. TCNTV can be cleared by an external reset input signal, or by compare match A or B. The clearing signal is selected by bits CCLR1 and CCLR0 in TCRV0. When TCNTV overflows, OVF is set to 1 in timer control/status register V (TCSRV). TCNTV is initialized to H'00. Rev. 3.00 Sep. 14, 2006 Page 147 of 408 REJ09B0105-0300 Section 11 Timer V 11.3.2 Time Constant Registers A and B (TCORA, TCORB) TCORA and TCORB have the same function. TCORA and TCORB are 8-bit read/write registers. TCORA and TCNTV are compared at all times. When the TCORA and TCNTV contents match, CMFA is set to 1 in TCSRV. If CMIEA is also set to 1 in TCRV0, a CPU interrupt is requested. Note that they must not be compared during the T3 state of a TCORA write cycle. Timer output from the TMOV pin can be controlled by the identifying signal (compare match A) and the settings of bits OS3 to OS0 in TCSRV. TCORA and TCORB are initialized to H'FF. 11.3.3 Timer Control Register V0 (TCRV0) TCRV0 selects the input clock signals of TCNTV, specifies the clearing conditions of TCNTV, and controls each interrupt request. Bit Bit Name Initial Value R/W Description 7 CMIEB 0 R/W Compare Match Interrupt Enable B When this bit is set to 1, interrupt request from the CMFB bit in TCSRV is enabled. 6 CMIEA 0 R/W Compare Match Interrupt Enable A When this bit is set to 1, interrupt request from the CMFA bit in TCSRV is enabled. 5 OVIE 0 R/W Timer Overflow Interrupt Enable When this bit is set to 1, interrupt request from the OVF bit in TCSRV is enabled. Rev. 3.00 Sep. 14, 2006 Page 148 of 408 REJ09B0105-0300 Section 11 Timer V Bit Bit Name Initial Value R/W Description 4 CCLR1 0 R/W Counter Clear 1 and 0 3 CCLR0 0 R/W These bits specify the clearing conditions of TCNTV. 00: Clearing is disabled 01: Cleared by compare match A 10: Cleared by compare match B 11: Cleared on the rising edge of the TMRIV pin. The operation of TCNTV after clearing depends on TRGE in TCRV1. 2 CKS2 0 R/W Clock Select 2 to 0 1 CKS1 0 R/W 0 CKS0 0 R/W These bits select clock signals to input to TCNTV and the counting condition in combination with ICKS0 in TCRV1. Refer to table 11.2. Table 11.2 Clock Signals to Input to TCNTV and Counting Conditions TCRV0 TCRV1 Bit 2 Bit 1 Bit 0 Bit 0 CKS2 CKS1 CKS0 ICKS0 Description 0 0 0 Clock input prohibited 1 0 Internal clock: counts on /4, falling edge 1 Internal clock: counts on /8, falling edge 0 Internal clock: counts on /16, falling edge 1 Internal clock: counts on /32, falling edge 0 Internal clock: counts on /64, falling edge 1 Internal clock: counts on /128, falling edge 1 0 1 1 0 1 0 Clock input prohibited 1 External clock: counts on rising edge 0 External clock: counts on falling edge 1 External clock: counts on rising and falling edge Rev. 3.00 Sep. 14, 2006 Page 149 of 408 REJ09B0105-0300 Section 11 Timer V 11.3.4 Timer Control/Status Register V (TCSRV) TCSRV indicates the status flag and controls outputs by using a compare match. Bit Bit Name Initial Value R/W Description 7 CMFB 0 R/W Compare Match Flag B [Setting condition] * When the TCNTV value matches the TCORB value [Clearing condition] * 6 CMFA 0 R/W After reading CMFB = 1, cleared by writing 0 to CMFB Compare Match Flag A [Setting condition] * When the TCNTV value matches the TCORA value [Clearing condition] * 5 OVF 0 R/W After reading CMFA = 1, cleared by writing 0 to CMFA Timer Overflow Flag [Setting condition] * When TCNTV overflows from H'FF to H'00 [Clearing condition] * 4 1 After reading OVF = 1, cleared by writing 0 to OVF Reserved This bit is always read as 1. 3 OS3 0 R/W Output Select 3 and 2 2 OS2 0 R/W These bits select an output method for the TMOV pin by the compare match of TCORB and TCNTV. 00: No change 01: 0 output 10: 1 output 11: Output toggles Rev. 3.00 Sep. 14, 2006 Page 150 of 408 REJ09B0105-0300 Section 11 Timer V Bit Bit Name Initial Value R/W Description 1 OS1 0 R/W Output Select 1 and 0 0 OS0 0 R/W These bits select an output method for the TMOV pin by the compare match of TCORA and TCNTV. 00: No change 01: 0 output 10: 1 output 11: Output toggles OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level for compare match A. The two output levels can be controlled independently. After a reset, the timer output is 0 until the first compare match. 11.3.5 Timer Control Register V1 (TCRV1) TCRV1 selects the edge at the TRGV pin, enables TRGV input, and selects the clock input to TCNTV. Bit Bit Name Initial Value R/W Description 7 to 5 All 1 Reserved These bits are always read as 1. 4 TVEG1 0 R/W TRGV Input Edge Select 3 TVEG0 0 R/W These bits select the TRGV input edge. 00: TRGV trigger input is prohibited 01: Rising edge is selected 10: Falling edge is selected 11: Rising and falling edges are both selected 2 TRGE 0 R/W TCNT starts counting up by the input of the edge which is selected by TVEG1 and TVEG0. 0: Disables starting counting-up TCNTV by the input of the TRGV pin and halting counting-up TCNTV when TCNTV is cleared by a compare match. 1: Enables starting counting-up TCNTV by the input of the TRGV pin and halting counting-up TCNTV when TCNTV is cleared by a compare match. Rev. 3.00 Sep. 14, 2006 Page 151 of 408 REJ09B0105-0300 Section 11 Timer V Bit Bit Name Initial Value R/W Description 1 1 Reserved This bit is always read as 1. 0 ICKS0 0 R/W Internal Clock Select 0 This bit selects clock signals to input to TCNTV in combination with CKS2 to CKS0 in TCRV0. Refer to table 11.2. 11.4 Operation 11.4.1 Timer V Operation 1. According to table 11.2, six internal/external clock signals output by prescaler S can be selected as the timer V operating clock signals. When the operating clock signal is selected, TCNTV starts counting-up. Figure 11.2 shows the count timing with an internal clock signal selected, and figure 11.3 shows the count timing with both edges of an external clock signal selected. 2. When TCNTV overflows (changes from H'FF to H'00), the overflow flag (OVF) in TCRV0 will be set. The timing at this time is shown in figure 11.4. An interrupt request is sent to the CPU when OVIE in TCRV0 is 1. 3. TCNTV is constantly compared with TCORA and TCORB. Compare match flag A or B (CMFA or CMFB) is set to 1 when TCNTV matches TCORA or TCORB, respectively. The compare-match signal is generated in the last state in which the values match. Figure 11.5 shows the timing. An interrupt request is generated for the CPU when CMIEA or CMIEB in TCRV0 is 1. 4. When a compare match A or B is generated, the TMOV responds with the output value selected by bits OS3 to OS0 in TCSRV. Figure 11.6 shows the timing when the output is toggled by compare match A. 5. When CCLR1 or CCLR0 in TCRV0 is 01 or 10, TCNTV can be cleared by the corresponding compare match. Figure 11.7 shows the timing. 6. When CCLR1 or CCLR0 in TCRV0 is 11, TCNTV can be cleared by the rising edge of the input of TMRIV pin. A TMRIV input pulse-width of at least 1.5 system clocks is necessary. Figure 11.8 shows the timing. 7. When a counter-clearing source is generated with TRGE in TCRV1 set to 1, the counting-up is halted as soon as TCNTV is cleared. TCNTV resumes counting-up when the edge selected by TVEG1 or TVEG0 in TCRV1 is input from the TGRV pin. Rev. 3.00 Sep. 14, 2006 Page 152 of 408 REJ09B0105-0300 Section 11 Timer V Internal clock TCNTV input clock TCNTV N-1 N N+1 Figure 11.2 Increment Timing with Internal Clock TMCIV (External clock input pin) TCNTV input clock TCNTV N-1 N N+1 Figure 11.3 Increment Timing with External Clock TCNTV H'FF H'00 Overflow signal OVF Figure 11.4 OVF Set Timing Rev. 3.00 Sep. 14, 2006 Page 153 of 408 REJ09B0105-0300 Section 11 Timer V TCNTV N TCORA or TCORB N N+1 Compare match signal CMFA or CMFB Figure 11.5 CMFA and CMFB Set Timing Compare match A signal Timer V output pin Figure 11.6 TMOV Output Timing Compare match A signal TCNTV N H'00 Figure 11.7 Clear Timing by Compare Match Rev. 3.00 Sep. 14, 2006 Page 154 of 408 REJ09B0105-0300 Section 11 Timer V TMRIV (External counter reset input pin) TCNTV reset signal N-1 TCNTV N H'00 Figure 11.8 Clear Timing by TMRIV Input 11.5 Timer V Application Examples 11.5.1 Pulse Output with Arbitrary Duty Cycle Figure 11.9 shows an example of output of pulses with an arbitrary duty cycle. 1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with TCORA. 2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA and to 0 at compare match with TCORB. 3. Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source. 4. With these settings, a waveform is output without further software intervention, with a period determined by TCORA and a pulse width determined by TCORB. TCNTV value H'FF Counter cleared TCORA TCORB H'00 Time TMOV Figure 11.9 Pulse Output Example Rev. 3.00 Sep. 14, 2006 Page 155 of 408 REJ09B0105-0300 Section 11 Timer V 11.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the TRGV input, as shown in figure 11.10. To set up this output: 1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with TCORB. 2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA and to 0 at compare match with TCORB. 3. Set bits TVEG1 and TVEG0 in TCRV1 and set TRGE to select the falling edge of the TRGV input. 4. Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source. 5. After these settings, a pulse waveform will be output without further software intervention, with a delay determined by TCORA from the TRGV input, and a pulse width determined by (TCORB to TCORA). TCNTV value H'FF Counter cleared TCORB TCORA H'00 Time TRGV TMOV Compare match A Compare match B clears TCNTV and halts count-up Compare match A Compare match B clears TCNTV and halts count-up Figure 11.10 Example of Pulse Output Synchronized to TRGV Input Rev. 3.00 Sep. 14, 2006 Page 156 of 408 REJ09B0105-0300 Section 11 Timer V 11.6 Usage Notes The following types of contention or operation can occur in timer V operation. 1. 2. 3. 4. Writing to registers is performed in the T3 state of a TCNTV write cycle. If a TCNTV clear signal is generated in the T3 state of a TCNTV write cycle, as shown in figure 11.11, clearing takes precedence and the write to the counter is not carried out. If counting-up is generated in the T3 state of a TCNTV write cycle, writing takes precedence. If a compare match is generated in the T3 state of a TCORA or TCORB write cycle, the write to TCORA or TCORB takes precedence and the compare match signal is inhibited. Figure 11.12 shows the timing. If compare matches A and B occur simultaneously, any conflict between the output selections for compare match A and compare match B is resolved by the following priority: toggle output > output 1 > output 0. Depending on the timing, TCNTV may be incremented by a switch between different internal clock sources. When TCNTV is internally clocked, an increment pulse is generated from the falling edge of an internal clock signal, that is divided system clock (). Therefore, as shown in figure 11.13 the switch is from a high clock signal to a low clock signal, the switchover is seen as a falling edge, causing TCNTV to increment. TCNTV can also be incremented by a switch between internal and external clocks. TCNTV write cycle by CPU T2 T1 T3 Address TCNTV address Internal write signal Counter clear signal TCNTV N H'00 Figure 11.11 Contention between TCNTV Write and Clear Rev. 3.00 Sep. 14, 2006 Page 157 of 408 REJ09B0105-0300 Section 11 Timer V TCORA write cycle by CPU T2 T1 T3 Address TCORA address Internal write signal TCNTV N N+1 TCORA N M TCORA write data Compare match signal Inhibited Figure 11.12 Contention between TCORA Write and Compare Match Clock before switching Clock after switching Count clock TCNTV N N+1 N+2 Write to CKS1 and CKS0 Figure 11.13 Internal Clock Switching and TCNTV Operation Rev. 3.00 Sep. 14, 2006 Page 158 of 408 REJ09B0105-0300 Section 12 Timer W Section 12 Timer W The timer W has a 16-bit timer having output compare and input capture functions. The timer W can count external events and output pulses with an arbitrary duty cycle by compare match between the timer counter and four general registers. Thus, it can be applied to various systems. 12.1 Features * Selection of five counter clock sources: four internal clocks (, /2, /4, and /8) and an external clock (external events can be counted) * Capability to process up to four pulse outputs or four pulse inputs * Four general registers: Independently assignable output compare or input capture functions Usable as two pairs of registers; one register of each pair operates as a buffer for the output compare or input capture register * Four selectable operating modes: Waveform output by compare match Selections of 0 output, 1 output, or toggle output Input capture function Rising edge, falling edge, or both edges Counter clearing function Counters can be cleared by compare match PWM mode Up to three-phase PWM output can be provided with desired duty ratio. * Any initial timer output value can be set * Five interrupt sources Four compare match/input capture interrupts and an overflow interrupt. TIM08W0A_000020020200 Rev. 3.00 Sep. 14, 2006 Page 159 of 408 REJ09B0105-0300 Section 12 Timer W Table 12.1 summarizes the timer W functions, and figure 12.1 shows a block diagram of the timer W. Table 12.1 Timer W Functions Input/Output Pins Item Counter FTIOC FTIOD Count clock Internal clocks: , /2, /4, /8 External clock: FTCI General registers (output compare/input capture registers) Period GRA specified in GRA GRB GRC (buffer register for GRA in buffer mode) GRD (buffer register for GRB in buffer mode) Counter clearing function GRA compare match GRA compare match -- -- -- Initial output value setting function -- Yes Yes Yes Yes Buffer function -- Yes Yes -- -- 0 -- Yes Yes Yes Yes 1 -- Yes Yes Yes Yes Toggle -- Yes Yes Yes Yes Input capture function -- Yes Yes Yes Yes PWM mode -- -- Yes Yes Yes Interrupt sources Overflow Compare match/input capture Compare match/input capture Compare match/input capture Compare match/input capture Compare match output Rev. 3.00 Sep. 14, 2006 Page 160 of 408 REJ09B0105-0300 FTIOA FTIOB Section 12 Timer W Internal clock: /2 /4 /8 External clock: FTCI FTIOA Clock selector FTIOB FTIOC Control logic FTIOD Comparator TIOR TSRW TIERW TCRW TMRW GRD GRC GRB Bus interface [Legend] TMRW: TCRW: TIERW: TSRW: TIOR: TCNT: GRA: GRB: GRC: GRD: IRRTW: GRA TCNT IRRTW Internal data bus Timer mode register W (8 bits) Timer control register W (8 bits) Timer interrupt enable register W (8 bits) Timer status register W (8 bits) Timer I/O control register (8 bits) Timer counter (16 bits) General register A (input capture/output compare register: 16 bits) General register B (input capture/output compare register: 16 bits) General register C (input capture/output compare register: 16 bits) General register D (input capture/output compare register: 16 bits) Timer W interrupt request Figure 12.1 Timer W Block Diagram Rev. 3.00 Sep. 14, 2006 Page 161 of 408 REJ09B0105-0300 Section 12 Timer W 12.2 Input/Output Pins Table 12.2 summarizes the timer W pins. Table 12.2 Pin Configuration Name Abbreviation Input/Output Function External clock input FTCI Input External clock input pin Input capture/output compare A FTIOA Input/output Output pin for GRA output compare or input pin for GRA input capture Input capture/output compare B FTIOB Input/output Output pin for GRB output compare, input pin for GRB input capture, or PWM output pin in PWM mode Input capture/output compare C FTIOC Input/output Output pin for GRC output compare, input pin for GRC input capture, or PWM output pin in PWM mode Input capture/output compare D FTIOD Input/output Output pin for GRD output compare, input pin for GRD input capture, or PWM output pin in PWM mode 12.3 Register Descriptions The timer W has the following registers. * * * * * * * * * * * Timer mode register W (TMRW) Timer control register W (TCRW) Timer interrupt enable register W (TIERW) Timer status register W (TSRW) Timer I/O control register 0 (TIOR0) Timer I/O control register 1 (TIOR1) Timer counter (TCNT) General register A (GRA) General register B (GRB) General register C (GRC) General register D (GRD) Rev. 3.00 Sep. 14, 2006 Page 162 of 408 REJ09B0105-0300 Section 12 Timer W 12.3.1 Timer Mode Register W (TMRW) TMRW selects the general register functions and the timer output mode. Bit Bit Name Initial Value R/W Description 7 CTS 0 R/W Counter Start The counter operation is halted when this bit is 0, while it can be performed when this bit is 1. 6 1 Reserved This bit is always read as 1. 5 BUFEB 0 R/W Buffer Operation B Selects the GRD function. 0: GRD operates as an input capture/output compare register 1: GRD operates as the buffer register for GRB 4 BUFEA 0 R/W Buffer Operation A Selects the GRC function. 0: GRC operates as an input capture/output compare register 1: GRC operates as the buffer register for GRA 3 1 Reserved This bit is always read as 1. 2 PWMD 0 R/W PWM Mode D Selects the output mode of the FTIOD pin. 0: FTIOD operates normally (output compare output) 1: PWM output 1 PWMC 0 R/W PWM Mode C Selects the output mode of the FTIOC pin. 0: FTIOC operates normally (output compare output) 1: PWM output 0 PWMB 0 R/W PWM Mode B Selects the output mode of the FTIOB pin. 0: FTIOB operates normally (output compare output) 1: PWM output Rev. 3.00 Sep. 14, 2006 Page 163 of 408 REJ09B0105-0300 Section 12 Timer W 12.3.2 Timer Control Register W (TCRW) TCRW selects the timer counter clock source, selects a clearing condition, and specifies the timer output levels. Bit Bit Name Initial Value R/W Description 7 CCLR 0 R/W Counter Clear The TCNT value is cleared by compare match A when this bit is 1. When it is 0, TCNT operates as a freerunning counter. 6 CKS2 0 R/W Clock Select 2 to 0 5 CKS1 0 R/W Select the TCNT clock source. 4 CKS0 0 R/W 000: Internal clock: counts on 001: Internal clock: counts on /2 010: Internal clock: counts on /4 011: Internal clock: counts on /8 1XX: Counts on rising edges of the external event (FTCI) When the internal clock source () is selected, subclock sources are counted in subactive and subsleep modes. 3 TOD 0 R/W Timer Output Level Setting D Sets the output value of the FTIOD pin until the first compare match D is generated. 0: Output value is 0* 1: Output value is 1* 2 TOC 0 R/W Timer Output Level Setting C Sets the output value of the FTIOC pin until the first compare match C is generated. 0: Output value is 0* 1: Output value is 1* 1 TOB 0 R/W Timer Output Level Setting B Sets the output value of the FTIOB pin until the first compare match B is generated. 0: Output value is 0* 1: Output value is 1* Rev. 3.00 Sep. 14, 2006 Page 164 of 408 REJ09B0105-0300 Section 12 Timer W Bit Bit Name Initial Value R/W Description 0 TOA 0 R/W Timer Output Level Setting A Sets the output value of the FTIOA pin until the first compare match A is generated. 0: Output value is 0* 1: Output value is 1* [Legend] X: Don't care Note: * The change of the setting is immediately reflected in the output value. 12.3.3 Timer Interrupt Enable Register W (TIERW) TIERW controls the timer W interrupt request. Bit Bit Name Initial Value R/W Description 7 OVIE 0 R/W Timer Overflow Interrupt Enable When this bit is set to 1, FOVI interrupt requested by OVF flag in TSRW is enabled. 6 to 4 All 1 Reserved These bits are always read as 1. 3 IMIED 0 R/W Input Capture/Compare Match Interrupt Enable D When this bit is set to 1, IMID interrupt requested by IMFD flag in TSRW is enabled. 2 IMIEC 0 R/W Input Capture/Compare Match Interrupt Enable C When this bit is set to 1, IMIC interrupt requested by IMFC flag in TSRW is enabled. 1 IMIEB 0 R/W Input Capture/Compare Match Interrupt Enable B When this bit is set to 1, IMIB interrupt requested by IMFB flag in TSRW is enabled. 0 IMIEA 0 R/W Input Capture/Compare Match Interrupt Enable A When this bit is set to 1, IMIA interrupt requested by IMFA flag in TSRW is enabled. Rev. 3.00 Sep. 14, 2006 Page 165 of 408 REJ09B0105-0300 Section 12 Timer W 12.3.4 Timer Status Register W (TSRW) TSRW shows the status of interrupt requests. Bit Bit Name Initial Value R/W Description 7 OVF 0 R/W Timer Overflow Flag [Setting condition] * When TCNT overflows from H'FFFF to H'0000 [Clearing condition] * 6 to 4 All 1 Read OVF when OVF = 1, then write 0 in OVF Reserved These bits are always read as 1. 3 IMFD 0 R/W Input Capture/Compare Match Flag D [Setting conditions] * TCNT = GRD when GRD functions as an output compare register * The TCNT value is transferred to GRD by an input capture signal when GRD functions as an input capture register [Clearing condition] * 2 IMFC 0 R/W Read IMFD when IMFD = 1, then write 0 in IMFD Input Capture/Compare Match Flag C [Setting conditions] * TCNT = GRC when GRC functions as an output compare register * The TCNT value is transferred to GRC by an input capture signal when GRC functions as an input capture register [Clearing condition] * Rev. 3.00 Sep. 14, 2006 Page 166 of 408 REJ09B0105-0300 Read IMFC when IMFC = 1, then write 0 in IMFC Section 12 Timer W Bit Bit Name Initial Value R/W Description 1 IMFB 0 R/W Input Capture/Compare Match Flag B [Setting conditions] * TCNT = GRB when GRB functions as an output compare register * The TCNT value is transferred to GRB by an input capture signal when GRB functions as an input capture register [Clearing condition] * 0 IMFA 0 R/W Read IMFB when IMFB = 1, then write 0 in IMFB Input Capture/Compare Match Flag A [Setting conditions] * TCNT = GRA when GRA functions as an output compare register * The TCNT value is transferred to GRA by an input capture signal when GRA functions as an input capture register [Clearing condition] * Read IMFA when IMFA = 1, then write 0 in IMFA Rev. 3.00 Sep. 14, 2006 Page 167 of 408 REJ09B0105-0300 Section 12 Timer W 12.3.5 Timer I/O Control Register 0 (TIOR0) TIOR0 selects the functions of GRA and GRB, and specifies the functions of the FTIOA and FTIOB pins. Bit Bit Name Initial Value R/W Description 7 1 Reserved This bit is always read as 1. 6 IOB2 0 R/W I/O Control B2 Selects the GRB function. 0: GRB functions as an output compare register 1: GRB functions as an input capture register 5 IOB1 0 R/W I/O Control B1 and B0 4 IOB0 0 R/W When IOB2 = 0, 00: No output at compare match 01: 0 output to the FTIOB pin at GRB compare match 10: 1 output to the FTIOB pin at GRB compare match 11: Output toggles to the FTIOB pin at GRB compare match When IOB2 = 1, 00: Input capture at rising edge at the FTIOB pin 01: Input capture at falling edge at the FTIOB pin 1X: Input capture at rising and falling edges of the FTIOB pin 3 1 Reserved This bit is always read as 1. 2 IOA2 0 R/W I/O Control A2 Selects the GRA function. 0: GRA functions as an output compare register 1: GRA functions as an input capture register Rev. 3.00 Sep. 14, 2006 Page 168 of 408 REJ09B0105-0300 Section 12 Timer W Bit Bit Name Initial Value R/W Description 1 IOA1 0 R/W I/O Control A1 and A0 0 IOA0 0 R/W When IOA2 = 0, 00: No output at compare match 01: 0 output to the FTIOA pin at GRA compare match 10: 1 output to the FTIOA pin at GRA compare match 11: Output toggles to the FTIOA pin at GRA compare match When IOA2 = 1, 00: Input capture at rising edge of the FTIOA pin 01: Input capture at falling edge of the FTIOA pin 1X: Input capture at rising and falling edges of the FTIOA pin [Legend] X: Don't care 12.3.6 Timer I/O Control Register 1 (TIOR1) TIOR1 selects the functions of GRC and GRD, and specifies the functions of the FTIOC and FTIOD pins. Bit Bit Name Initial Value R/W Description 7 1 Reserved This bit is always read as 1. 6 IOD2 0 R/W I/O Control D2 Selects the GRD function. 0: GRD functions as an output compare register 1: GRD functions as an input capture register When GRB buffer operation has been selected by BUFEB in TMRW, select the same function as GRB. Rev. 3.00 Sep. 14, 2006 Page 169 of 408 REJ09B0105-0300 Section 12 Timer W Bit Bit Name Initial Value R/W Description 5 IOD1 0 R/W I/O Control D1 and D0 4 IOD0 0 R/W When IOD2 = 0, 00: No output at compare match 01: 0 output to the FTIOD pin at GRD compare match 10: 1 output to the FTIOD pin at GRD compare match 11: Output toggles to the FTIOD pin at GRD compare match When IOD2 = 1, 00: Input capture at rising edge at the FTIOD pin 01: Input capture at falling edge at the FTIOD pin 1X: Input capture at rising and falling edges at the FTIOD pin 3 1 Reserved This bit is always read as 1. 2 IOC2 0 R/W I/O Control C2 Selects the GRC function. 0: GRC functions as an output compare register 1: GRC functions as an input capture register When GRA buffer operation has been selected by BUFEA in TMRW, select the same function as GRA. 1 IOC1 0 R/W I/O Control C1 and C0 0 IOC0 0 R/W When IOC2 = 0, 00: No output at compare match 01: 0 output to the FTIOC pin at GRC compare match 10: 1 output to the FTIOC pin at GRC compare match 11: Output toggles to the FTIOC pin at GRC compare match When IOC2 = 1, 00: Input capture to GRC at rising edge of the FTIOC pin 01: Input capture to GRC at falling edge of the FTIOC pin 1X: Input capture to GRC at rising and falling edges of the FTIOC pin [Legend] X: Don't care Rev. 3.00 Sep. 14, 2006 Page 170 of 408 REJ09B0105-0300 Section 12 Timer W 12.3.7 Timer Counter (TCNT) TCNT is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS2 to CKS0 in TCRW. TCNT can be cleared to H'0000 through a compare match with GRA by setting the CCLR in TCRW to 1. When TCNT overflows (changes from H'FFFF to H'0000), the OVF flag in TSRW is set to 1. If OVIE in TIERW is set to 1 at this time, an interrupt request is generated. TCNT must always be read or written in 16-bit units; 8-bit access is not allowed. TCNT is initialized to H'0000 by a reset. 12.3.8 General Registers A to D (GRA to GRD) Each general register is a 16-bit readable/writable register that can function as either an outputcompare register or an input-capture register. The function is selected by settings in TIOR0 and TIOR1. When a general register is used as an input-compare register, its value is constantly compared with the TCNT value. When the two values match (a compare match), the corresponding flag (IMFA, IMFB, IMFC, or IMFD) in TSRW is set to 1. An interrupt request is generated at this time, when IMIEA, IMIEB, IMIEC, or IMIED is set to 1. Compare match output can be selected in TIOR. When a general register is used as an input-capture register, an external input-capture signal is detected and the current TCNT value is stored in the general register. The corresponding flag (IMFA, IMFB, IMFC, or IMFD) in TSRW is set to 1. If the corresponding interrupt-enable bit (IMIEA, IMIEB, IMIEC, or IMIED) in TSRW is set to 1 at this time, an interrupt request is generated. The edge of the input-capture signal is selected in TIOR. GRC and GRD can be used as buffer registers of GRA and GRB, respectively, by setting BUFEA and BUFEB in TMRW. For example, when GRA is set as an output-compare register and GRC is set as the buffer register for GRA, the value in the buffer register GRC is sent to GRA whenever compare match A is generated. When GRA is set as an input-capture register and GRC is set as the buffer register for GRA, the value in TCNT is transferred to GRA and the value in the buffer register GRC is transferred to GRA whenever an input capture is generated. GRA to GRD must be written or read in 16-bit units; 8-bit access is not allowed. GRA to GRD are initialized to H'FFFF by a reset. Rev. 3.00 Sep. 14, 2006 Page 171 of 408 REJ09B0105-0300 Section 12 Timer W 12.4 Operation The timer W has the following operating modes. * Normal Operation * PWM Operation 12.4.1 Normal Operation TCNT performs free-running or periodic counting operations. After a reset, TCNT is set as a freerunning counter. When the CTS bit in TMRW is set to 1, TCNT starts incrementing the count. When the count overflows from H'FFFF to H'0000, the OVF flag in TSRW is set to 1. If the OVIE in TIERW is set to 1, an interrupt request is generated. Figure 12.2 shows free-running counting. TCNT value H'FFFF H'0000 Time CTS bit Flag cleared by software OVF Figure 12.2 Free-Running Counter Operation Rev. 3.00 Sep. 14, 2006 Page 172 of 408 REJ09B0105-0300 Section 12 Timer W Periodic counting operation can be performed when GRA is set as an output compare register and bit CCLR in TCRW is set to 1. When the count matches GRA, TCNT is cleared to H'0000, the IMFA flag in TSRW is set to 1. If the corresponding IMIEA bit in TIERW is set to 1, an interrupt request is generated. TCNT continues counting from H'0000. Figure 12.3 shows periodic counting. TCNT value GRA H'0000 Time CTS bit Flag cleared by software IMFA Figure 12.3 Periodic Counter Operation By setting a general register as an output compare register, compare match A, B, C, or D can cause the output at the FTIOA, FTIOB, FTIOC, or FTIOD pin to output 0, output 1, or toggle. Figure 12.4 shows an example of 0 and 1 output when TCNT operates as a free-running counter, 1 output is selected for compare match A, and 0 output is selected for compare match B. When signal is already at the selected output level, the signal level does not change at compare match. TCNT value H'FFFF GRA GRB Time H'0000 FTIOA FTIOB No change No change No change No change Figure 12.4 0 and 1 Output Example (TOA = 0, TOB = 1) Rev. 3.00 Sep. 14, 2006 Page 173 of 408 REJ09B0105-0300 Section 12 Timer W Figure 12.5 shows an example of toggle output when TCNT operates as a free-running counter, and toggle output is selected for both compare match A and B. TCNT value H'FFFF GRA GRB Time H'0000 FTIOA Toggle output FTIOB Toggle output Figure 12.5 Toggle Output Example (TOA = 0, TOB = 1) Figure 12.6 shows another example of toggle output when TCNT operates as a periodic counter, cleared by compare match A. Toggle output is selected for both compare match A and B. TCNT value Counter cleared by compare match with GRA H'FFFF GRA GRB H'0000 Time FTIOA Toggle output FTIOB Toggle output Figure 12.6 Toggle Output Example (TOA = 0, TOB = 1) Rev. 3.00 Sep. 14, 2006 Page 174 of 408 REJ09B0105-0300 Section 12 Timer W The TCNT value can be captured into a general register (GRA, GRB, GRC, or GRD) when a signal level changes at an input-capture pin (FTIOA, FTIOB, FTIOC, or FTIOD). Capture can take place on the rising edge, falling edge, or both edges. By using the input-capture function, the pulse width and periods can be measured. Figure 12.7 shows an example of input capture when both edges of FTIOA and the falling edge of FTIOB are selected as capture edges. TCNT operates as a free-running counter. TCNT value H'FFFF H'F000 H'AA55 H'55AA H'1000 H'0000 Time FTIOA GRA H'1000 H'F000 H'55AA FTIOB GRB H'AA55 Figure 12.7 Input Capture Operating Example Rev. 3.00 Sep. 14, 2006 Page 175 of 408 REJ09B0105-0300 Section 12 Timer W Figure 12.8 shows an example of buffer operation when the GRA is set as an input-capture register and GRC is set as the buffer register for GRA. TCNT operates as a free-running counter, and FTIOA captures both rising and falling edge of the input signal. Due to the buffer operation, the GRA value is transferred to GRC by input-capture A and the TCNT value is stored in GRA. TCNT value H'FFFF H'DA91 H'5480 H'0245 H'0000 Time FTIOA GRA H'0245 GRC H'5480 H'DA91 H'0245 H'5480 Figure 12.8 Buffer Operation Example (Input Capture) 12.4.2 PWM Operation In PWM mode, PWM waveforms are generated by using GRA as the period register and GRB, GRC, and GRD as duty registers. PWM waveforms are output from the FTIOB, FTIOC, and FTIOD pins. Up to three-phase PWM waveforms can be output. In PWM mode, a general register functions as an output compare register automatically. The output level of each pin depends on the corresponding timer output level set bit (TOB, TOC, and TOD) in TCRW. When TOB is 1, the FTIOB output goes to 1 at compare match A and to 0 at compare match B. When TOB is 0, the FTIOB output goes to 0 at compare match A and to 1 at compare match B. Thus the compare match output level settings in TIOR0 and TIOR1 are ignored for the output pin set to PWM mode. If the same value is set in the cycle register and the duty register, the output does not change when a compare match occurs. Figure 12.9 shows an example of operation in PWM mode. The output signals go to 1 and TCNT is cleared at compare match A, and the output signals go to 0 at compare match B, C, and D (TOB, TOC, and TOD = 1: initial output values are set to 1). Rev. 3.00 Sep. 14, 2006 Page 176 of 408 REJ09B0105-0300 Section 12 Timer W TCNT value Counter cleared by compare match A GRA GRB GRC GRD H'0000 Time FTIOB FTIOC FTIOD Figure 12.9 PWM Mode Example (1) Figure 12.10 shows another example of operation in PWM mode. The output signals go to 0 and TCNT is cleared at compare match A, and the output signals go to 1 at compare match B, C, and D (TOB, TOC, and TOD = 0: initial output values are set to 1). TCNT value Counter cleared by compare match A GRA GRB GRC GRD H'0000 Time FTIOB FTIOC FTIOD Figure 12.10 PWM Mode Example (2) Rev. 3.00 Sep. 14, 2006 Page 177 of 408 REJ09B0105-0300 Section 12 Timer W Figure 12.11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and GRD is set as the buffer register for GRB. TCNT is cleared by compare match A, and FTIOB outputs 1 at compare match B and 0 at compare match A. Due to the buffer operation, the FTIOB output level changes and the value of buffer register GRD is transferred to GRB whenever compare match B occurs. This procedure is repeated every time compare match B occurs. TCNT value GRA GRB H'0520 H'0450 H'0200 Time H'0000 GRD GRB H'0450 H'0200 H'0200 H'0520 H'0450 H'0520 FTIOB Figure 12.11 Buffer Operation Example (Output Compare) Rev. 3.00 Sep. 14, 2006 Page 178 of 408 REJ09B0105-0300 Section 12 Timer W Figures 12.12 and 12.13 show examples of the output of PWM waveforms with duty cycles of 0% and 100%. TCNT value Write to GRB GRA GRB Write to GRB H'0000 Time Duty 0% FTIOB TCNT value Output does not change when cycle register and duty register compare matches occur simultaneously. Write to GRB GRA Write to GRB Write to GRB GRB H'0000 Time Duty 100% FTIOB TCNT value Output does not change when cycle register and duty register compare matches occur simultaneously. Write to GRB GRA Write to GRB Write to GRB GRB H'0000 FTIOB Time Duty 100% Duty 0% Figure 12.12 PWM Mode Example (TOB, TOC, and TOD = 0: Initial Output Values are Set to 0) Rev. 3.00 Sep. 14, 2006 Page 179 of 408 REJ09B0105-0300 Section 12 Timer W TCNT value Write to GRB GRA GRB Write to GRB H'0000 Time Duty 100% FTIOB TCNT value Output does not change when cycle register and duty register compare matches occur simultaneously. Write to GRB GRA Write to GRB Write to GRB GRB H'0000 Time Duty 0% FTIOB TCNT value Output does not change when cycle register and duty register compare matches occur simultaneously. Write to GRB GRA Write to GRB Write to GRB GRB H'0000 Time Duty 0% FTIOB Duty 100% Figure 12.13 PWM Mode Example (TOB, TOC, and TOD = 1: Initial Output Values are Set to 1) Rev. 3.00 Sep. 14, 2006 Page 180 of 408 REJ09B0105-0300 Section 12 Timer W 12.5 Operation Timing 12.5.1 TCNT Count Timing Figure 12.14 shows the TCNT count timing when the internal clock source is selected. Figure 12.15 shows the timing when the external clock source is selected. The pulse width of the external clock signal must be at least two system clock () cycles; shorter pulses will not be counted correctly. Internal clock Rising edge TCNT input clock TCNT N N+1 N+2 Figure 12.14 Count Timing for Internal Clock Source External clock Rising edge Rising edge TCNT input clock TCNT N N+1 N+2 Figure 12.15 Count Timing for External Clock Source Rev. 3.00 Sep. 14, 2006 Page 181 of 408 REJ09B0105-0300 Section 12 Timer W 12.5.2 Output Compare Output Timing The compare match signal is generated in the last state in which TCNT and GR match (when TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the compare match output pin (FTIOA, FTIOB, FTIOC, or FTIOD). When TCNT matches GR, the compare match signal is generated only after the next counter clock pulse is input. Figure 12.16 shows the output compare timing. TCNT input clock TCNT N GRA to GRD N N+1 Compare match signal FTIOA to FTIOD Figure 12.16 Output Compare Output Timing Rev. 3.00 Sep. 14, 2006 Page 182 of 408 REJ09B0105-0300 Section 12 Timer W 12.5.3 Input Capture Timing Input capture on the rising edge, falling edge, or both edges can be selected through settings in TIOR0 and TIOR1. Figure 12.17 shows the timing when the falling edge is selected. The pulse width of the input capture signal must be at least two system clock () cycles; shorter pulses will not be detected correctly. Input capture input Input capture signal N-1 TCNT N N+1 N+2 N GRA to GRD Figure 12.17 Input Capture Input Signal Timing 12.5.4 Timing of Counter Clearing by Compare Match Figure 12.18 shows the timing when the counter is cleared by compare match A. When the GRA value is N, the counter counts from 0 to N, and its cycle is N + 1. Compare match signal TCNT N GRA N H'0000 Figure 12.18 Timing of Counter Clearing by Compare Match Rev. 3.00 Sep. 14, 2006 Page 183 of 408 REJ09B0105-0300 Section 12 Timer W 12.5.5 Buffer Operation Timing Figures 12.19 and 12.20 show the buffer operation timing. Compare match signal TCNT N GRC, GRD M N+1 M GRA, GRB Figure 12.19 Buffer Operation Timing (Compare Match) Input capture signal TCNT N GRA, GRB M GRC, GRD N+1 N N+1 M N Figure 12.20 Buffer Operation Timing (Input Capture) Rev. 3.00 Sep. 14, 2006 Page 184 of 408 REJ09B0105-0300 Section 12 Timer W 12.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TCNT matches the general register. The compare match signal is generated in the last state in which the values match (when TCNT is updated from the matching count to the next count). Therefore, when TCNT matches a general register, the compare match signal is generated only after the next TCNT clock pulse is input. Figure 12.21 shows the timing of the IMFA to IMFD flag setting at compare match. TCNT input clock TCNT N GRA to GRD N N+1 Compare match signal IMFA to IMFD IRRTW Figure 12.21 Timing of IMFA to IMFD Flag Setting at Compare Match Rev. 3.00 Sep. 14, 2006 Page 185 of 408 REJ09B0105-0300 Section 12 Timer W 12.5.7 Timing of IMFA to IMFD Setting at Input Capture If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an input capture occurs. Figure 12.22 shows the timing of the IMFA to IMFD flag setting at input capture. Input capture signal TCNT N N GRA to GRD IMFA to IMFD IRRTW Figure 12.22 Timing of IMFA to IMFD Flag Setting at Input Capture 12.5.8 Timing of Status Flag Clearing When the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared. Figure 12.23 shows the status flag clearing timing. TSRW write cycle T1 T2 TSRW address Address Write signal IMFA to IMFD IRRTW Figure 12.23 Timing of Status Flag Clearing by CPU Rev. 3.00 Sep. 14, 2006 Page 186 of 408 REJ09B0105-0300 Section 12 Timer W 12.6 Usage Notes The following types of contention or operation can occur in timer W operation. 1. The pulse width of the input clock signal and the input capture signal must be at least two system clock () cycles; shorter pulses will not be detected correctly. 2. Writing to registers is performed in the T2 state of a TCNT write cycle. If counter clear signal occurs in the T2 state of a TCNT write cycle, clearing of the counter takes priority and the write is not performed, as shown in figure 12.24. If counting-up is generated in the TCNT write cycle to contend with the TCNT counting-up, writing takes precedence. 3. Depending on the timing, TCNT may be incremented by a switch between different internal clock sources. When TCNT is internally clocked, an increment pulse is generated from the rising edge of an internal clock signal, that is divided system clock (). Therefore, as shown in figure 12.25 the switch is from a low clock signal to a high clock signal, the switchover is seen as a rising edge, causing TCNT to increment. 4. If timer W enters module standby mode while an interrupt request is generated, the interrupt request cannot be cleared. Before entering module standby mode, disable interrupt requests. 5. The TOA to TOD bits in TCRW decide the value of the FTIO pin, which is output until the first compare match occurs. Once a compare match occurs and this compare match changes the values of FTIOA to FTIOD output, the values of the FTIOA to FTIOD pin output and the values read from the TOA to TOD bits may differ. Moreover, when the writing to TCRW and the generation of the compare match A to D occur at the same timing, the writing to TCRW has the priority. Thus, output change due to the compare match is not reflected to the FTIOA to FTIOD pins. Therefore, when bit manipulation instruction is used to write to TCRW, the values of the FTIOA to FTIOD pin output may result in an unexpected result. When TCRW is to be written to while compare match is operating, stop the counter once before accessing to TCRW, read the port 8 state to reflect the values of FTIOA to FTIOD output, to TOA to TOD, and then restart the counter. Figure 12.26 shows an example when the compare match and the bit manipulation instruction to TCRW occur at the same timing. Rev. 3.00 Sep. 14, 2006 Page 187 of 408 REJ09B0105-0300 Section 12 Timer W TCNT write cycle T2 T1 TCNT address Address Write signal Counter clear signal N TCNT H'0000 Figure 12.24 Contention between TCNT Write and Clear Clock before switching Clock after switching Count clock TCNT N N+1 N+2 N+3 The change in signal level at clock switching is assumed to be a rising edge, and TCNT increments the count. Figure 12.25 Internal Clock Switching and TCNT Operation Rev. 3.00 Sep. 14, 2006 Page 188 of 408 REJ09B0105-0300 Section 12 Timer W TCRW has been set to H'06. Compare match B and compare match C are used. The FTIOB pin is in the 1 output state, and is set to the toggle output or the 0 output by compare match B. When BCLR#2, @TCRW is executed to clear the TOC bit (the FTIOC signal is low) and compare match B occurs at the same timing as shown below, the H'02 writing to TCRW has priority and compare match B does not drive the FTIOB signal low; the FTIOB signal remains high. Bit TCRW Set value 7 6 5 4 CCLR 0 CKS2 0 CKS1 0 CKS0 0 3 TOD 0 2 1 0 TOC 1 TOB 1 TOA 0 BCLR#2, @TCRW (1) TCRW read operation: Read H'06 (2) Modify operation: Modify H'06 to H'02 (3) Write operation to TCRW: Write H'02 TCRW write signal Compare match signal B FTIOB pin Expected output Remains high because the 1 writing to TOB has priority Figure 12.26 When Compare Match and Bit Manipulation Instruction to TCRW Occur at the Same Timing Rev. 3.00 Sep. 14, 2006 Page 189 of 408 REJ09B0105-0300 Section 12 Timer W Rev. 3.00 Sep. 14, 2006 Page 190 of 408 REJ09B0105-0300 Section 13 Watchdog Timer Section 13 Watchdog Timer The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. WDT dedicated internal oscillator CLK TCSRWD PSS TCWD Internal data bus The block diagram of the watchdog timer is shown in figure 13.1. TMWD [Legend] TCSRWD: TCWD: PSS: TMWD: Internal reset signal Timer control/status register WD Timer counter WD Prescaler S Timer mode register WD Figure 13.1 Block Diagram of Watchdog Timer 13.1 Features * Selectable from nine counter input clocks. Eight clock sources (/64, /128, /256, /512, /1024, /2048, /4096, and /8192) or the WDT dedicated internal oscillator can be selected as the timer-counter clock. When the WDT dedicated internal oscillator is selected, it can operate as the watchdog timer in any operating mode. * Reset signal generated on counter overflow An overflow period of 1 to 256 times the selected clock can be set. * The watchdog timer is enabled in the initial state. It starts operating after the reset state is canceled. WDT0110A_000020030300 Rev. 3.00 Sep. 14, 2006 Page 191 of 408 REJ09B0105-0300 Section 13 Watchdog Timer 13.2 Register Descriptions The watchdog timer has the following registers. * Timer control/status register WD (TCSRWD) * Timer counter WD (TCWD) * Timer mode register WD (TMWD) 13.2.1 Timer Control/Status Register WD (TCSRWD) TCSRWD performs the TCSRWD and TCWD write control. TCSRWD also controls the watchdog timer operation and indicates the operating state. TCSRWD must be rewritten by using the MOV instruction. The bit manipulation instruction cannot be used to change the setting value. Bit Bit Name Initial Value R/W Description 7 B6WI 1 R/W Bit 6 Write Inhibit The TCWE bit can be written only when the write value of the B6WI bit is 0. This bit is always read as 1. 6 TCWE 0 R/W Timer Counter WD Write Enable TCWD can be written when the TCWE bit is set to 1. When writing data to this bit, the value for bit 7 must be 0. 5 B4WI 1 R/W Bit 4 Write Inhibit The TCSRWE bit can be written only when the write value of the B4WI bit is 0. This bit is always read as 1. 4 TCSRWE 0 R/W Timer Control/Status Register WD Write Enable The WDON and WRST bits can be written when the TCSRWE bit is set to 1. When writing data to this bit, the value for bit 5 must be 0. 3 B2WI 1 R/W Bit 2 Write Inhibit This bit can be written to the WDON bit only when the write value of the B2WI bit is 0. This bit is always read as 1. Rev. 3.00 Sep. 14, 2006 Page 192 of 408 REJ09B0105-0300 Section 13 Watchdog Timer Bit Bit Name Initial Value R/W Description 2 WDON 1 R/W Watchdog Timer On TCWD starts counting up when the WDON bit is set to 1 and halts when the WDON bit is cleared to 0. The watchdog timer is enabled in the initial state. When the watchdog timer is not used, clear the WDON bit to 0. [Setting conditions] * Reset * When 1 is written to the WDON bit and 0 is written to the B2WI bit while the TCSRWE bit = 1 [Clearing conditions] * 1 B0WI 1 R/W When 0 is written to the WDON bit and 0 is written to the B2WI bit while the TCSRWE bit = 1 Bit 0 Write Inhibit This bit can be written to the WRST bit only when the write value of the B0WI bit is 0. This bit is always read as 1. 0 WRST* 0 R/W Watchdog Timer Reset [Setting condition] * When TCWD overflows and an internal reset signal is generated [Clearing conditions] Note: * * Reset by the RES pin * When 0 is written to the WRST bit and 0 is written to the B0WI bit while the TCSRWE bit = 1 The WRST bit cannot be modified to 1. Rev. 3.00 Sep. 14, 2006 Page 193 of 408 REJ09B0105-0300 Section 13 Watchdog Timer 13.2.2 Timer Counter WD (TCWD) TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the internal reset signal is generated and the WRST bit in TCSRWD is set to 1. TCWD is initialized to H'00. 13.2.3 Timer Mode Register WD (TMWD) TMWD selects the input clock. Bit Bit Name Initial Value R/W Description 7 to 4 All 1 Reserved These bits are always read as 1. 3 CKS3 1 R/W Clock Select 3 to 0 2 CKS2 1 R/W Select the clock to be input to TCWD. 1 CKS1 1 R/W 1000: Internal clock: counts on /64 0 CKS0 1 R/W 1001: Internal clock: counts on /128 1010: Internal clock: counts on /256 1011: Internal clock: counts on /512 1100: Internal clock: counts on /1024 1101: Internal clock: counts on /2048 1110: Internal clock: counts on /4096 1111: Internal clock: counts on 8192 0XXX: WDT dedicated internal oscillator For the overflow periods of the WDT dedicated internal oscillator, see section 20, Electrical Characteristics. [Legend] X: Don't care Rev. 3.00 Sep. 14, 2006 Page 194 of 408 REJ09B0105-0300 Section 13 Watchdog Timer 13.3 Operation The watchdog timer is provided with an 8-bit counter. After the reset state is released, TCWD starts counting up. When the TCWD count value overflows H'FF, an internal reset signal is generated. The internal reset signal is output for a period of 256 RC clock cycles. As TCWD is a writable counter, it starts counting from the value set in TCWD. An overflow period in the range of 1 to 256 input clock cycles can therefore be set, according to the TCWD set value. When the watchdog timer is not used, stop TCWD counting by writing 0 to B2WI and WDON simultaneously while the TCSRWE bit in TCSRWD is set to 1. (To stop the watchdog timer, two write accesses to TCSRWD are required.) Figure 13.2 shows an example of watchdog timer operation. Example: With 30ms overflow period when = 4 MHz 4 x 106 8192 x 30 x 10-3 = 14.6 Therefore, 256 - 15 = 241 (H'F1) is set in TCW. TCWD overflow H'FF H'F1 TCWD count value H'00 H'F1 written to TCWD H'F1 written to TCWD Reset generated Internal reset signal 256 RC clock cycles Figure 13.2 Watchdog Timer Operation Example Rev. 3.00 Sep. 14, 2006 Page 195 of 408 REJ09B0105-0300 Section 13 Watchdog Timer Rev. 3.00 Sep. 14, 2006 Page 196 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) Section 14 Serial Communication Interface 3 (SCI3) This LSI includes serial communication interface 3 (SCI3). SCI3 can handle both asynchronous and clocked synchronous serial communication. In asynchronous mode, serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function). Figure 14.1 is a block diagram of SCI3. 14.1 Features * Choice of asynchronous or clocked synchronous serial communication mode * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * On-chip baud rate generator allows any bit rate to be selected * External clock or on-chip baud rate generator can be selected as a transfer clock source. * Six interrupt sources Transmit-end, transmit-data-empty, receive-data-full, overrun error, framing error, and parity error. * Internal noise filter circuit (available for asynchronous serial communication only) Asynchronous mode * * * * * Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Receive error detection: Parity, overrun, and framing errors Break detection: Break can be detected by reading the RXD pin level directly in the case of a framing error SCI0010A_000120030300 Rev. 3.00 Sep. 14, 2006 Page 197 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) Clocked synchronous mode * Data length: 8 bits * Receive error detection: Overrun errors SCK3 External clock Baud rate generator BRC Internal clock (/64,/16, /4, ) BRR Clock Transmit/receive control circuit SCR3 SSR SPMR TXD Noise filter circuit RXD TSR TDR RSR RDR Internal data bus SMR Interrupt request (TEI, TXI, RXI, ERI) [Legend] Receive shift register RSR: Receive data register RDR: Transmit shift register TSR: Transmit data register TDR: Serial mode register SMR: SCR3: Serial control register 3 Serial status register SSR: Bit rate register BRR: Bit rate counter BRC: SPMR: Sampling mode register Figure 14.1 Block Diagram of SCI3 Rev. 3.00 Sep. 14, 2006 Page 198 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) 14.2 Input/Output Pins Table 14.1 shows the SCI3 pin configuration. Table 14.1 Pin Configuration Pin Name Abbreviation I/O Function SCI3 clock SCK3 Input/output SCI3 clock input/output SCI3 receive data input RXD Input SCI3 receive data input SCI3 transmit data output TXD Output SCI3 transmit data output 14.3 Register Descriptions SCI3 has the following registers for each channel. * * * * * * * * * Receive shift register (RSR) Receive data register (RDR) Transmit shift register (TSR) Transmit data register (TDR) Serial mode register (SMR) Serial control register 3 (SCR3) Serial status register (SSR) Bit rate register (BRR) Sampling mode register (SPMR) Rev. 3.00 Sep. 14, 2006 Page 199 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) 14.3.1 Receive Shift Register (RSR) RSR is a shift register that is used to receive serial data input from the RXD pin and convert it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 14.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores received data. When SCI3 has received one frame of serial data, it transfers the received serial data from RSR to RDR, where it is stored. After this, RSR is receive-enabled. As RSR and RDR function as a double buffer in this way, continuous receive operations are possible. After confirming that the RDRF bit in SSR is set to 1, read RDR only once. RDR cannot be written to by the CPU. RDR is initialized to H'00. 14.3.3 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data. To perform serial data transmission, SCI3 first transfers transmit data from TDR to TSR automatically, then sends the data that starts from the LSB to the TXD pin. TSR cannot be directly accessed by the CPU. 14.3.4 Transmit Data Register (TDR) TDR is an 8-bit register that stores data for transmission. When SCI3 detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structure of TDR and TSR enables continuous serial transmission. If the next transmit data has already been written to TDR during transmission of one-frame data, SCI3 transfers the written data to TSR to continue transmission. To achieve reliable serial transmission, write transmit data to TDR only once after confirming that the TDRE bit in SSR is set to 1. TDR is initialized to H'FF. Rev. 3.00 Sep. 14, 2006 Page 200 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) 14.3.5 Serial Mode Register (SMR) SMR is used to set the SCI3's serial transfer format and select the baud rate generator clock source. Bit Bit Name Initial Value R/W Description 7 COM 0 R/W Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. 5 PE 0 R/W Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. 4 PM 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. 3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits For reception, only the first stop bit is checked, regardless of the value in the bit. If the second stop bit is 0, it is treated as the start bit of the next transmit character. 2 MP 0 R/W Multiprocessor Mode When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and PM bit settings are invalid in multiprocessor mode. In clocked synchronous mode, clear this bit to 0. Rev. 3.00 Sep. 14, 2006 Page 201 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 1 CKS1 0 R/W Clock Select 0 and 1 0 CKS0 0 R/W These bits select the clock source for the baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) For the relationship between the bit rate register setting and the baud rate, see section 14.3.8, Bit Rate Register (BRR). n is the decimal representation of the value of n in BRR (see section 14.3.8, Bit Rate Register (BRR)). 14.3.6 Serial Control Register 3 (SCR3) SCR3 is a register that enables or disables SCI3 transfer operations and interrupt requests, and is also used to select the transfer clock source. For details on interrupt requests, refer to section 14.7, Interrupts. Bit Bit Name Initial Value R/W Description 7 TIE 0 R/W Transmit Interrupt Enable When this bit is set to 1, the TXI interrupt request is enabled. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 TE 0 R/W Transmit Enable 4 RE 0 R/W Receive Enable When this bit s set to 1, transmission is enabled. When this bit is set to 1, reception is enabled. Rev. 3.00 Sep. 14, 2006 Page 202 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and OER status flags in SSR is disabled. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, refer to section 14.6, Multiprocessor Communication Function. 2 TEIE 0 R/W Transmit End Interrupt Enable When this bit is set to 1, TEI interrupt request is enabled. 1 CKE1 0 R/W Clock Enable 0 and 1 0 CKE0 0 R/W Selects the clock source. * Asynchronous mode 00: On-chip baud rate generator 01: On-chip baud rate generator Outputs a clock of the same frequency as the bit rate from the SCK3 pin. 10: External clock Inputs a clock with a frequency 16 times the bit rate from the SCK3 pin. 11:Reserved * Clocked synchronous mode 00: On-chip clock (SCK3 pin functions as clock output) 01:Reserved 10: External clock (SCK3 pin functions as clock input) 11:Reserved Rev. 3.00 Sep. 14, 2006 Page 203 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) 14.3.7 Serial Status Register (SSR) SSR is a register containing status flags of SCI3 and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared. Bit Bit Name Initial Value R/W Description 7 TDRE 1 R/W Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] * When the TE bit in SCR3 is 0 * When data is transferred from TDR to TSR [Clearing conditions] 6 RDRF 0 R/W * When 0 is written to TDRE after reading TDRE = 1 * When the transmit data is written to TDR Receive Data Register Full Indicates that the received data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR [Clearing conditions] 5 OER 0 R/W * When 0 is written to RDRF after reading RDRF = 1 * When data is read from RDR Overrun Error [Setting condition] * When an overrun error occurs in reception [Clearing condition] * 4 FER 0 R/W When 0 is written to OER after reading OER = 1 Framing Error [Setting condition] * When a framing error occurs in reception [Clearing condition] * Rev. 3.00 Sep. 14, 2006 Page 204 of 408 REJ09B0105-0300 When 0 is written to FER after reading FER = 1 Section 14 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 3 PER 0 R/W Parity Error [Setting condition] * When a parity error is detected during reception [Clearing condition] * 2 TEND 1 R When 0 is written to PER after reading PER = 1 Transmit End [Setting conditions] * When the TE bit in SCR3 is 0 * When TDRE = 1 at transmission of the last bit of a 1frame serial transmit character [Clearing conditions] 1 MPBR 0 R * When 0 is written to TDRE after reading TDRE = 1 * When the transmit data is written to TDR Multiprocessor Bit Receive MPBR stores the multiprocessor bit in the receive character data. When the RE bit in SCR3 is cleared to 0, its state is retained. 0 MPBT 0 R/W Multiprocessor Bit Transfer MPBT stores the multiprocessor bit to be added to the transmit character data. Rev. 3.00 Sep. 14, 2006 Page 205 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) 14.3.8 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 14.2 shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of SMR in asynchronous mode. Table 14.3 shows the maximum bit rate for each frequency in asynchronous mode. The values shown in both tables 14.2 and 14.3 are values in active (highspeed) mode. Table 14.4 shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of SMR in clocked synchronous mode. The values shown in table 14.5 are values in active (high-speed) mode. The N setting in BRR and error for other operating frequencies and bit rates can be obtained by the following formulas: [Asynchronous Mode] N= 64 x 22n-1 xB x 106 - 1 x 106 - 1 x 100 (N + 1) x B x 64 x 22n-1 Error (%) = [Clocked Synchronous Mode] N= x 106 - 1 8 x 22n-1 x B Legend B: Bit rate (bit/s) N: BRR setting for baud rate generator (0 N 255) : Operating frequency (MHz) n: CSK1 and CSK0 settings in SMR (0 n 3) Rev. 3.00 Sep. 14, 2006 Page 206 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency (MHz) 2 2.097152 2.4576 3 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 1 141 0.03 1 148 -0.04 1 174 -0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 -0.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 -2.48 0 15 0.00 0 19 -2.34 9600 0 6 -6.99 0 6 -2.48 0 7 0.00 0 9 -2.34 19200 0 2 8.51 0 2 13.78 0 3 0.00 0 4 -2.34 31250 0 1 0.00 0 1 4.86 0 1 22.88 0 2 0.00 38400 0 1 -18.62 0 1 -14.67 0 1 0.00 -- -- -- Rev. 3.00 Sep. 14, 2006 Page 207 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) Operating Frequency (MHz) 3.6864 4 4.9152 5 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 -0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 -1.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 0 6 -6.99 0 7 0.00 0 7 1.73 31250 -- -- -- 0 3 0.00 0 4 -1.70 0 4 0.00 38400 0 2 0.00 0 2 8.51 0 3 0.00 0 3 1.73 [Legend] : A setting is available but error occurs Operating Frequency (MHz) 6 6.144 7.3728 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) 110 2 106 -0.44 2 108 0.08 2 130 -0.07 150 2 77 0.16 2 79 0.00 2 95 0.00 300 1 155 0.16 1 159 0.00 1 191 0.00 600 1 77 0.16 1 79 0.00 1 95 0.00 1200 0 155 0.16 0 159 0.00 0 191 0.00 2400 0 77 0.16 0 79 0.00 0 95 0.00 4800 0 38 0.16 0 39 0.00 0 47 0.00 9600 0 19 -2.34 0 19 0.00 0 23 0.00 19200 0 9 -2.34 0 9 0.00 0 11 0.00 31250 0 5 0.00 0 5 2.40 0 6 5.33 38400 0 4 -2.34 0 4 0.00 0 5 0.00 Rev. 3.00 Sep. 14, 2006 Page 208 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) Operating Frequency (MHz) 8 9.8304 10 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) 110 2 141 0.03 2 174 -0.26 2 177 -0.25 150 2 103 0.16 2 127 0.00 2 129 0.16 300 1 207 0.16 1 255 0.00 2 64 0.16 600 1 103 0.16 1 127 0.00 1 129 0.16 1200 0 207 0.16 0 255 0.00 1 64 0.16 2400 0 103 0.16 0 127 0.00 0 129 0.16 4800 0 51 0.16 0 63 0.00 0 64 0.16 9600 0 25 0.16 0 31 0.00 0 32 -1.36 19200 0 12 0.16 0 15 0.00 0 15 1.73 31250 0 7 0.00 0 9 -1.70 0 9 0.00 38400 0 6 -6.99 0 7 0.00 0 7 1.73 Table 14.3 Maximum Bit Rate for Each Frequency (Asynchronous Mode) (MHz) Maximum Bit Rate (bit/s) n N (MHz) Maximum Bit Rate (bit/s) n N 2 62500 0 0 5 156250 0 0 2.097152 65536 0 0 6 187500 0 0 2.4576 76800 0 0 6.144 192000 0 0 3 93750 0 0 7.3728 230400 0 0 3.6864 115200 0 0 8 250000 0 0 4 125000 0 0 9.8304 307200 0 0 4.9152 153600 0 0 10 312500 0 0 Rev. 3.00 Sep. 14, 2006 Page 209 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) Table 14.4 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency (MHz) 2 4 8 10 Bit Rate (bit/s) n N n N n N n N 110 3 70 -- -- -- -- -- -- 250 2 124 2 249 3 124 -- -- 500 1 249 2 124 2 249 -- -- 1k 1 124 1 249 2 124 -- -- 2.5k 0 199 1 99 1 199 1 249 5k 0 99 0 199 1 99 1 124 10k 0 49 0 99 0 199 0 249 25k 0 19 0 39 0 79 0 99 50k 0 9 0 19 0 39 0 49 100k 0 4 0 9 0 19 0 24 250k 0 1 0 3 0 7 0 9 500k 0 0* 0 1 0 3 0 4 0 0* 0 1 -- -- 0 0* -- -- 0 0* 1M 2M 2.5M 4M [Legend] Blank: No setting is available. --: A setting is available but error occurs. *: Continuous transfer is not possible. Rev. 3.00 Sep. 14, 2006 Page 210 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) 14.3.9 Sampling Mode Register (SPMR) SPMR controls the serial communication function. Bit Bit Name Initial Value R/W Description 7 to 3 All 1 Reserved These bits are always read as 1. 2 STDSPM 1 R/W Noise Filter Function Select Selects the noise filter function for the RXD pin in asynchronous mode. 0: Noise filter circuit is enabled 1: Noise filter circuit is disabled 1, 0 All 1 Reserved These bits are always read as 1. * Noise Filter Circuit The RXD input signal is latched through the noise filter circuit. The noise filter circuit comprises a series of three latch circuits and a match detection circuit. The RXD input signal is sampled by the basic clock with the 16 times the transfer clock frequency. If three latch outputs match, its level is transferred to the next stage. If not, the circuit holds the previous value. That is, when the incoming signal holds the same level for three clock cycles, it is regarded as the proper signal. If the levels of the signal is less than three clock cycles, the signal is regarded as a noise. Sampling clock C C RXD input signal D Q Latch D C Q Latch D Q Latch Match detection circuit SPMR (STDSPM) Internal RXD signal shown in figure 14.1 Internal basic clock cycle Sampling clock Figure 14.2 Block Diagram of Noise Filter Circuit Rev. 3.00 Sep. 14, 2006 Page 211 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) 14.4 Operation in Asynchronous Mode Figure 14.3 shows the general format for asynchronous serial communication. One character (or frame) consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). Inside the SCI3, the transmitter and receiver are independent units, enabling full-duplex. Both the transmitter and the receiver also have a doublebuffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer. LSB MSB Serial Start data bit 7 or 8 bits 1 bit 1 Parity bit Transmit/receive data Stop bit Mark state 1 or 2 bits 1 bit, or none One unit of transfer data (character or frame) Figure 14.3 Data Format in Asynchronous Communication 14.4.1 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK3 pin can be selected as the SCI3's serial clock, according to the setting of the COM bit in SMR and the CKE0 and CKE1 bits in SCR3. When an external clock is input at the SCK3 pin, the clock frequency should be 16 times the bit rate used. When SCI3 is operated on an internal clock, the clock can be output from the SCK3 pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 14.4. Clock Serial data 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 character (frame) Figure 14.4 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits) Rev. 3.00 Sep. 14, 2006 Page 212 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) 14.4.2 SCI3 Initialization Before transmitting and receiving data, you should first clear the TE and RE bits in SCR3 to 0, then initialize SCI3 as described below. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and OER flags, or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization. [1] Start initialization When the clock output is selected in asynchronous mode, clock is output immediately after CKE1 and CKE0 settings are made. When the clock output is selected at reception in clocked synchronous mode, clock is output immediately after CKE1, CKE0, and RE are set to 1. Clear TE and RE bits in SCR3 to 0 [1] Set CKE1 and CKE0 bits in SCR3 Set data transfer format in SMR [2] Set value in BRR [3] Wait [2] Set the data transfer format in SMR. [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR3 to 1. RE settings enable the RXD pin to be used. For transmission, set the TXD bit in PMR1 to 1 to enable the TXD output pin to be used. Also set the RIE, TIE, TEIE, and MPIE bits, depending on whether interrupts are required. In asynchronous mode, the bits are marked at transmission and idled at reception to wait for the start bit. No 1-bit interval elapsed? Yes Set TE and RE bits in SCR3 to 1, and set RIE, TIE, TEIE, and MPIE bits. For transmit (TE=1), also set the TxD bit in PMR1. <Initialization completion> [4] Set the clock selection in SCR3. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. For transmission, set the TE bit to 1 and then output 1 for one frame to enable. Figure 14.5 Sample SCI3 Initialization Flowchart Rev. 3.00 Sep. 14, 2006 Page 213 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) 14.4.3 Data Transmission Figure 14.6 shows an example of operation for transmission in asynchronous mode. In transmission, SCI3 operates as described below. 1. SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a TXI interrupt request is generated. Continuous transmission is possible because the TXI interrupt routine writes next transmit data to TDR before transmission of the current transmit data has been completed. 3. SCI3 checks the TDRE flag at the timing for sending the stop bit. 4. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 5. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered, in which 1 is output. If the TEIE bit in SCR3 is set to 1 at this time, a TEI interrupt request is generated. 6. Figure 14.7 shows a sample flowchart for transmission in asynchronous mode. Start bit Serial data 1 0 Transmit data D0 D1 D7 1 frame Parity Stop Start bit bit bit 0/1 1 0 Transmit data D0 D1 D7 Parity Stop bit bit 0/1 Mark state 1 1 1 frame TDRE TEND TXI interrupt LSI operation request generated User processing TDRE flag cleared to 0 TXI interrupt request generated TEI interrupt request generated Data written to TDR Figure 14.6 Example of SCI3 Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) Rev. 3.00 Sep. 14, 2006 Page 214 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) Start transmission [1] Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR [2] Yes All data transmitted? [1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0. [2] To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0. [3] To output a break in serial transmission, after setting PCR to 1 and PDR to 0, clear TxD in PMR1 to 0, then clear the TE bit in SCR3 to 0. No Read TEND flag in SSR No TEND = 1 Yes [3] No Break output? Yes Clear PDR to 0 and set PCR to 1 Clear TE bit in SCR3 to 0 <End> Figure 14.7 Sample Serial Transmission Data Flowchart (Asynchronous Mode) Rev. 3.00 Sep. 14, 2006 Page 215 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) 14.4.4 Serial Data Reception Figure 14.8 shows an example of operation for reception in asynchronous mode. In serial reception, SCI3 operates as described below. 1. SCI3 monitors the communication line. If a start bit is detected, SCI3 performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated. 4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated. 5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is generated. Continuous reception is possible because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has been completed. Start bit Serial data 1 0 Receive data D0 D1 D7 Parity Stop Start bit bit bit 0/1 1 0 1 frame Receive data D0 D1 Parity Stop bit bit D7 0/1 0 Mark state (idle state) 1 1 frame RDRF FER LSI operation RXI request RDRF cleared to 0 0 stop bit detected RDR data read User processing Figure 14.8 Example of SCI3 Reception in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) Rev. 3.00 Sep. 14, 2006 Page 216 of 408 REJ09B0105-0300 ERI request in response to framing error Framing error processing Section 14 Serial Communication Interface 3 (SCI3) Table 14.5 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.9 shows a sample flow chart for serial data reception. Table 14.5 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF* OER FER PER Receive Data Receive Error Type 1 1 0 0 Lost Overrun error 0 0 1 0 Transferred to RDR Framing error 0 0 0 1 Transferred to RDR Parity error 1 1 1 0 Lost Overrun error + framing error 1 1 0 1 Lost Overrun error + parity error 0 0 1 1 Transferred to RDR Framing error + parity error 1 1 1 1 Lost Overrun error + framing error + parity error Note: * The RDRF flag retains the state it had before data reception. Rev. 3.00 Sep. 14, 2006 Page 217 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) Start reception Read OER, PER, and FER flags in SSR [1] Yes OER+PER+FER = 1 [4] No Error processing (Continued on next page) Read RDRF flag in SSR [2] No RDRF = 1 Yes Read receive data in RDR [1] Read the OER, PER, and FER flags in SSR to identify the error. If a receive error occurs, performs the appropriate error processing. [2] Read SSR and check that RDRF = 1, then read the receive data in RDR. The RDRF flag is cleared automatically. [3] To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag and read RDR. The RDRF flag is cleared automatically. [4] If a receive error occurs, read the OER, PER, and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the OER, PER, and FER flags are all cleared to 0. Reception cannot be resumed if any of these flags are set to 1. In the case of a framing error, a break can be detected by reading the value of the input port corresponding to the RxD pin. Yes All data received? [3] No (A) Clear RE bit in SCR3 to 0 <End> Figure 14.9 Sample Serial Reception Data Flowchart (Asynchronous Mode) Rev. 3.00 Sep. 14, 2006 Page 218 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) 14.5 Operation in Clocked Synchronous Mode Figure 14.10 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received synchronous with clock pulses. A single character in the transmit data consists of the 8-bit data starting from the LSB. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the synchronization clock to the next. In clocked synchronous mode, SCI3 receives data in synchronous with the rising edge of the synchronization clock. After 8-bit data is output, the transmission line holds the MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the SCI3, the transmitter and receiver are independent units, enabling fullduplex communication through the use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer. 8-bit One unit of transfer data (character or frame) * * Synchronization clock LSB Bit 0 Serial data MSB Bit 1 Don't care Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Don't care Note: * High except in continuous transfer Figure 14.10 Data Format in Clocked Synchronous Communication 14.5.1 Clock Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK3 pin can be selected, according to the setting of the COM bit in SMR and CKE0 and CKE1 bits in SCR3. When SCI3 is operated on an internal clock, the synchronization clock is output from the SCK3 pin. Eight synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. Rev. 3.00 Sep. 14, 2006 Page 219 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) 14.5.2 SCI3 Initialization Before transmitting and receiving data, SCI3 should be initialized as described in a sample flowchart in figure 14.5. 14.5.3 Serial Data Transmission Figure 14.11 shows an example of SCI3 operation for transmission in clocked synchronous mode. In serial transmission, SCI3 operates as described below. 1. SCI3 monitors the TDRE flag in SSR, and if the flag is 0, SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR3 is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. 3. 8-bit data is sent from the TXD pin synchronized with the output clock when output clock mode has been specified, and synchronized with the input clock when use of an external clock has been specified. Serial data is transmitted sequentially from the LSB (bit 0), from the TXD pin. 4. SCI3 checks the TDRE flag at the timing for sending the MSB (bit 7). 5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains the output state of the last bit. If the TEIE bit in SCR3 is set to 1 at this time, a TEI interrupt request is generated. 7. The SCK3 pin is fixed high at the end of transmission. Rev. 3.00 Sep. 14, 2006 Page 220 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) Figure 14.12 shows a sample flow chart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (OER, FER, or PER) is set to 1. Make sure that the receive error flags are cleared to 0 before starting transmission. Serial clock Serial data Bit 0 Bit 1 1 frame Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 1 frame TDRE TEND LSI TXI interrupt operation request generated TDRE flag cleared to 0 User processing Data written to TDR TXI interrupt request generated TEI interrupt request generated Figure 14.11 Example of SCI3 Transmission in Clocked Synchronous Mode Rev. 3.00 Sep. 14, 2006 Page 221 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) Start transmission [1] [1] Read TDRE flag in SSR No TDRE = 1 Yes [2] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0 and clocks are output to start the data transmission. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. Write transmit data to TDR [2] All data transmitted? Yes No Read TEND flag in SSR No TEND = 1 Yes Clear TE bit in SCR3 to 0 <End> Figure 14.12 Sample Serial Transmission Flowchart (Clocked Synchronous Mode) Rev. 3.00 Sep. 14, 2006 Page 222 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) 14.5.4 Serial Data Reception (Clocked Synchronous Mode) Figure 14.13 shows an example of SCI3 operation for reception in clocked synchronous mode. In serial reception, SCI3 operates as described below. 1. 2. 3. 4. SCI3 performs internal initialization synchronous with a synchronization clock input or output, starts receiving data. SCI3 stores the receive data in RSR. If an overrun error occurs (when reception of the next data is completed while the RDRF flag in SSR is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the RDRF flag remains to be set to 1. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is generated. Serial clock Serial data Bit 7 Bit 0 Bit 7 1 frame Bit 0 Bit 1 Bit 6 Bit 7 1 frame RDRF OER LSI operation User processing RXI interrupt request generated RDRF flag cleared to 0 RDR data read RXI interrupt request generated RDR data has not been read (RDRF = 1) ERI interrupt request generated by overrun error Overrun error processing Figure 14.13 Example of SCI3 Reception in Clocked Synchronous Mode Rev. 3.00 Sep. 14, 2006 Page 223 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.14 shows a sample flow chart for serial data reception. Start reception [1] [1] Read OER flag in SSR [2] Yes OER = 1 [4] No Error processing [3] (Continued below) Read RDRF flag in SSR [2] [4] No RDRF = 1 Yes Read the OER flag in SSR to determine if there is an error. If an overrun error has occurred, execute overrun error processing. Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR. When data is read from RDR, the RDRF flag is automatically cleared to 0. To continue serial reception, before the MSB (bit 7) of the current frame is received, reading the RDRF flag and reading RDR should be finished. When data is read from RDR, the RDRF flag is automatically cleared to 0. If an overrun error occurs, read the OER flag in SSR, and after performing the appropriate error processing, clear the OER flag to 0. Reception cannot be resumed if the OER flag is set to 1. Read receive data in RDR Yes All data received? [3] No Clear RE bit in SCR3 to 0 <End> [4] Error processing Overrun error processing Clear OER flag in SSR to 0 <End> Figure 14.14 Sample Serial Reception Flowchart (Clocked Synchronous Mode) Rev. 3.00 Sep. 14, 2006 Page 224 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) 14.5.5 Simultaneous Serial Data Transmission and Reception Figure 14.15 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that SCI3 has finished reception, clear RE to 0. Then after checking that the RDRF and receive error flags (OER, FER, and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction. Rev. 3.00 Sep. 14, 2006 Page 225 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) [1] Start transmission/reception Read TDRE flag in SSR [1] No TDRE = 1 Yes Write transmit data to TDR Read OER flag in SSR OER = 1 Yes No Read RDRF flag in SSR [2] No [4] RDRF = 1 Yes Overrun error processing Read receive data in RDR Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. [2] Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR. When data is read from RDR, the RDRF flag is automatically cleared to 0. [3] To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. When data is read from RDR, the RDRF flag is automatically cleared to 0. [4] If an overrun error occurs, read the OER flag in SSR, and after performing the appropriate error processing, clear the OER flag to 0. Transmission/reception cannot be resumed if the OER flag is set to 1. For overrun error processing, see figure 14.14. Yes All data received? [3] No Clear TE and RE bits in SCR to 0 <End> Figure 14.15 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations (Clocked Synchronous Mode) Rev. 3.00 Sep. 14, 2006 Page 226 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) 14.6 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles; an ID transmission cycle that specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle; if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 14.16 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends the ID code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose IDs do not match continue to skip data until data with a 1 multiprocessor bit is again received. SCI3 uses the MPIE bit in SCR3 to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags, RDRF, FER, and OER, to 1, are inhibited until data with a 1 multiprocessor bit is received. On reception of a receive character with a 1 multiprocessor bit, the MPBR bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is rendered invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode. Rev. 3.00 Sep. 14, 2006 Page 227 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) Transmitting station Serial transmission line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) (MPB = 0) ID transmission cycle = Data transmission cycle = receiving station Data transmission to specification receiving station specified by ID [Legend] MPB: Multiprocessor bit Figure 14.16 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) Rev. 3.00 Sep. 14, 2006 Page 228 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) 14.6.1 Multiprocessor Serial Data Transmission Figure 14.17 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI3 operations are the same as those in asynchronous mode. Rev. 3.00 Sep. 14, 2006 Page 229 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) Start transmission [1] [1] Read TDRE flag in SSR No TDRE = 1 [2] Yes Set MPBT bit in SSR [3] Write transmit data to TDR Yes [2] Read SSR and check that the TDRE flag is set to 1, set the MPBT bit in SSR to 0 or 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. To output a break in serial transmission, set the port PCR to 1, clear PDR to 0, then clear the TE bit in SCR3 to 0. All data transmitted? No Read TEND flag in SSR No TEND = 1 Yes No Break output? [3] Yes Clear PDR to 0 and set PCR to 1 Clear TE bit in SCR3 to 0 <End> Figure 14.17 Sample Multiprocessor Serial Transmission Flowchart Rev. 3.00 Sep. 14, 2006 Page 230 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) 14.6.2 Multiprocessor Serial Data Reception Figure 14.18 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI3 operations are the same as those in asynchronous mode. Figure 14.19 shows an example of SCI3 operation for multiprocessor format reception. Rev. 3.00 Sep. 14, 2006 Page 231 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) [1] [2] Start reception Set MPIE bit in SCR3 to 1 [1] Read OER and FER flags in SSR [2] [3] Yes FER+OER = 1 No Read RDRF flag in SSR [3] No [4] [5] RDRF = 1 Yes Read receive data in RDR No This station's ID? Set the MPIE bit in SCR3 to 1. Read OER and FER in SSR to check for errors. Receive error processing is performed in cases where a receive error occurs. Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again. When data is read from RDR, the RDRF flag is automatically cleared to 0. Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. If a receive error occurs, read the OER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the OER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value. Yes Read OER and FER flags in SSR Yes FER+OER = 1 No Read RDRF flag in SSR [4] No RDRF = 1 [5] Error processing Yes Read receive data in RDR (Continued on next page) Yes All data received? No [A] Clear RE bit in SCR3 to 0 <End> Figure 14.18 Sample Multiprocessor Serial Reception Flowchart (1) Rev. 3.00 Sep. 14, 2006 Page 232 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) [5] Error processing No OER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No [A] Framing error processing Clear OER, and FER flags in SSR to 0 <End> Figure 14.18 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 3.00 Sep. 14, 2006 Page 233 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) Start bit Serial data 1 0 Receive data (ID1) D0 D1 D7 MPB 1 Stop Start bit bit 1 0 Receive data (Data1) D0 1 frame D1 D7 MPB Stop bit Mark state (idle state) 0 1 1 1 frame MPIE RDRF RDR value ID1 LSI operation RDRF flag cleared to 0 RXI interrupt request MPIE cleared to 0 User processing RXI interrupt request is not generated, and RDR retains its state RDR data read When data is not this station's ID, MPIE is set to 1 again (a) When data does not match this receiver's ID Start bit Serial data 1 0 Receive data (ID2) D0 D1 D7 MPB 1 Stop Start bit bit 1 0 Receive data (Data2) D0 1 frame D1 D7 MPB Stop bit Mark state (idle state) 0 1 1 1 frame MPIE RDRF RDR value ID1 LSI operation User processing ID2 RXI interrupt request MPIE cleared to 0 RDRF flag cleared to 0 RDR data read Data2 RXI interrupt request When data is this station's ID, reception is continued RDRF flag cleared to 0 RDR data read MPIE set to 1 again (b) When data matches this receiver's ID Figure 14.19 Example of SCI3 Reception Using Multiprocessor Format (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev. 3.00 Sep. 14, 2006 Page 234 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) 14.7 Interrupts SCI3 creates the following six interrupt requests: transmission end, transmit data empty, receive data full, and receive errors (overrun error, framing error, and parity error). Table 14.6 shows the interrupt sources. Table 14.6 SCI3 Interrupt Requests Interrupt Requests Abbreviation Interrupt Sources Receive Data Full RXI Setting RDRF in SSR Transmit Data Empty TXI Setting TDRE in SSR Transmission End TEI Setting TEND in SSR Receive Error ERI Setting OER, FER, and PER in SSR The initial value of the TDRE flag in SSR is 1. Thus, when the TIE bit in SCR3 is set to 1 before transferring the transmit data to TDR, a TXI interrupt request is generated even if the transmit data is not ready. The initial value of the TEND flag in SSR is 1. Thus, when the TEIE bit in SCR3 is set to 1 before transferring the transmit data to TDR, a TEI interrupt request is generated even if the transmit data has not been sent. It is possible to make use of the most of these interrupt requests efficiently by transferring the transmit data to TDR in the interrupt routine. To prevent the generation of these interrupt requests (TXI and TEI), set the enable bits (TIE and TEIE) that correspond to these interrupt requests to 1, after transferring the transmit data to TDR. Rev. 3.00 Sep. 14, 2006 Page 235 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) 14.8 Usage Notes 14.8.1 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RXD pin value directly. In a break, the input from the RXD pin becomes all 0s, setting the FER flag, and possibly the PER flag. Note that as SCI3 continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 14.8.2 Mark State and Break Sending When the TXD bit in PMR1 is 1, the TxD pin is used as an I/O port whose direction (input or output) and level are determined by PCR and PDR. This can be used to set the TxD pin to mark state (high level) or send a break during serial data transmission. To maintain the communication line at mark state until TE is set to 1, set PCR and PDR to 1 respectively, and also set the TXD bit to 1. At this time, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial data transmission, first set PCR to 1 and clear PDR to 0, and then set the TXD bit to 1. Regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. 14.8.3 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) Transmission cannot be started when a receive error flag (OER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. Rev. 3.00 Sep. 14, 2006 Page 236 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) 14.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, SCI3 operates on a basic clock with a frequency of 16 times the transfer rate. In reception, SCI3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 14.20. Thus, the reception margin in asynchronous mode is given by formula (1) below. 1 D - 0.5 M = (0.5 - )- - (L - 0.5) F x 100(%) 2N N ... Formula (1) Legend N D L F : Ratio of bit rate to clock (N = 16) : Clock duty (D = 0.5 to 1.0) : Frame length (L = 9 to 12) : Absolute value of clock rate deviation Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in formula (1), the reception margin can be given by the formula. M = {0.5 - 1/(2 x 16)} x 100 [%] = 46.875% However, this is only the computed value, and a margin of 20% to 30% should be allowed for in system design. 16 clocks 8 clocks 0 7 15 0 7 15 0 Internal basic clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 14.20 Receive Data Sampling Timing in Asynchronous Mode Rev. 3.00 Sep. 14, 2006 Page 237 of 408 REJ09B0105-0300 Section 14 Serial Communication Interface 3 (SCI3) Rev. 3.00 Sep. 14, 2006 Page 238 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) Section 15 I2C Bus Interface 2 (IIC2) The I2C bus interface 2 conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that controls the I2C bus differs partly from the Philips configuration, however. Figure 15.1 shows a block diagram of the I2C bus interface 2. Figure 15.2 shows an example of I/O pin connections to external circuits. 15.1 Features * Selection of I2C format or clocked synchronous serial format * Continuous transmission/reception Since the shift register, transmit data register, and receive data register are independent from each other, the continuous transmission/reception can be performed. I2C bus format: * * * * Start and stop conditions generated automatically in master mode Selection of acknowledge output levels when receiving Automatic loading of acknowledge bit when transmitting Bit synchronization/wait function In master mode, the state of SCL is monitored per bit, and the timing is synchronized automatically. If transmission/reception is not yet possible, set the SCL to low until preparations are completed. * Six interrupt sources Transmit data empty (including slave-address match), transmit end, receive data full (including slave-address match), arbitration lost, NACK detection, and stop condition detection * Direct bus drive Two pins, SCL and SDA pins, function as NMOS open-drain outputs when the bus drive function is selected. Clocked synchronous format: * Four interrupt sources Transmit-data-empty, transmit-end, receive-data-full, and overrun error IFIIC10A_000020030300 Rev. 3.00 Sep. 14, 2006 Page 239 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) Transfer clock generation circuit Transmit/ receive control circuit Output control SCL ICCR1 ICCR2 ICMR Internal data bus Noise canceler ICDRT Output control SDA ICDRS SAR Address comparator Noise canceler ICDRR Bus state decision circuit Arbitration decision circuit ICSR ICIER [Legend] ICCR1: ICCR2: ICMR: ICSR: ICIER: ICDRT: ICDRR: ICDRS: SAR: I2C bus control register 1 I2C bus control register 2 I2C bus mode register I2C bus status register I2C bus interrupt enable register I2C bus transmit data register I2C bus receive data register I2C bus shift register Slave address register Interrupt generator Figure 15.1 Block Diagram of I2C Bus Interface 2 Rev. 3.00 Sep. 14, 2006 Page 240 of 408 REJ09B0105-0300 Interrupt request 2 Section 15 I C Bus Interface 2 (IIC2) Vcc SCL in Vcc SCL SCL SDA SDA SDA in SCL SDA SDA out SCL in (Master) SCL SDA SCL out SCL in SCL out SCL out SDA in SDA in SDA out SDA out (Slave 1) (Slave 2) Figure 15.2 External Circuit Connections of I/O Pins 15.2 Input/Output Pins Table 15.1 summarizes the input/output pins used by the I2C bus interface 2. Table 15.1 Pin Configuration Name Abbreviation I/O Function Serial clock SCL I/O I2C serial clock input/output Serial data SDA I/O I2C serial data input/output Rev. 3.00 Sep. 14, 2006 Page 241 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) 15.3 Register Descriptions The I2C bus interface 2 has the following registers. * * * * * * * * * I2C bus control register 1 (ICCR1) I2C bus control register 2 (ICCR2) I2C bus mode register (ICMR) I2C bus interrupt enable register (ICIER) I2C bus status register (ICSR) I2C bus slave address register (SAR) I2C bus transmit data register (ICDRT) I2C bus receive data register (ICDRR) I2C bus shift register (ICDRS) 15.3.1 I2C Bus Control Register 1 (ICCR1) ICCR1 enables or disables the I2C bus interface 2, controls transmission or reception, and selects master or slave mode, transmission or reception, and transfer clock frequency in master mode. Bit Bit Name Initial Value R/W Description 7 ICE I2C Bus Interface Enable 0 R/W 0: This module is halted. (SCL and SDA pins are set to port function.) 1: This bit is enabled for transfer operations. (SCL and SDA pins are bus drive state.) 6 RCVD 0 R/W Reception Disable This bit enables or disables the next operation when TRS is 0 and ICDRR is read. 0: Enables next reception 1: Disables next reception Rev. 3.00 Sep. 14, 2006 Page 242 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 5 MST 0 R/W Master/Slave Select 4 TRS 0 R/W Transmit/Receive Select 2 In master mode with the I C bus format, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode. Modification of the TRS bit should be made between transfer frames. After data receive has been started in slave receive mode, when the first seven bits of the receive data agree with the slave address that is set to SAR and the eighth bit is 1, TRS is automatically set to 1. If an overrun error occurs in master mode with the clock synchronous serial format, MST is cleared to 0 and slave receive mode is entered. Operating modes are described below according to MST and TRS combination. When clocked synchronous serial format is selected and MST is 1, clock is output. 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode 3 to 0 CKS3 to CKS0 All 0 R/W Transfer Clock Select 3 to 0 These bits should be set according to the necessary transfer rate (see table 15.2) in master mode. In slave mode, these bits are used reservation of the set up time in transmit mode. The time is 10tcyc when CKS3 = 0, and 20tcyc when CKS3 = 1. Rev. 3.00 Sep. 14, 2006 Page 243 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) Table 15.2 Transfer Rate Bit 3 Bit 1 Bit 0 CKS3 CKS2 Bit 2 CKS1 CKS0 Clock = 5 MHz = 8 MHz = 10 MHz 0 0 0 /28 179 kHz 286 kHz 357 kHz 1 /40 125 kHz 200 kHz 250 kHz 0 /48 104 kHz 167 kHz 208 kHz 1 /64 78.1 kHz 125 kHz 156 kHz 0 /80 62.5 kHz 100 kHz 125 kHz 1 /100 50.0 kHz 80.0 kHz 100 kHz 0 1 1 0 1 1 0 0 1 1 0 1 0 /112 44.6 kHz 71.4 kHz 89.3 kHz 1 /128 39.1 kHz 62.5 kHz 78.1 kHz 0 /56 89.3 kHz 143 kHz 179 kHz 1 /80 62.5 kHz 100 kHz 125 kHz 0 /96 52.1 kHz 83.3 kHz 104 kHz 1 /128 39.1 kHz 62.5 kHz 78.1 kHz 0 /160 31.3 kHz 50.0 kHz 62.5 kHz 1 /200 25.0 kHz 40.0 kHz 50.0 kHz 0 /224 22.3 kHz 35.7 kHz 44.6 kHz 1 /256 19.5 kHz 31.3 kHz 39.1 kHz Rev. 3.00 Sep. 14, 2006 Page 244 of 408 REJ09B0105-0300 Transfer Rate 2 Section 15 I C Bus Interface 2 (IIC2) 15.3.2 I2C Bus Control Register 2 (ICCR2) ICCR2 issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls reset in the control part of the I2C bus interface 2. Bit Bit Name Initial Value R/W Description 7 BBSY 0 R/W Bus Busy 2 This bit enables to confirm whether the I C bus is occupied or released and to issue start/stop conditions in master mode. With the clocked synchronous serial format, this bit has no meaning. With the I2C bus format, this bit is set to 1 when the SDA level changes from high to low under the condition of SCL = high, assuming that the start condition has been issued. This bit is cleared to 0 when the SDA level changes from low to high under the condition of SCL = high, assuming that the stop condition has been issued. Write 1 to BBSY and 0 to SCP to issue a start condition. Follow this procedure when also re-transmitting a start condition. Write 0 in BBSY and 0 in SCP to issue a stop condition. To issue start/stop conditions, use the MOV instruction. 6 SCP 1 R/W Start/Stop Issue Condition Disable The SCP bit controls the issue of start/stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP. This bit is always read as 1. If 1 is written, the data is not stored. 5 SDAO 1 R/W SDA Output Value Control This bit is used with SDAOP when modifying output level of SDA. This bit should not be manipulated during transfer. 0: When reading, SDA pin outputs low. When writing, SDA pin is changed to output low. 1: When reading, SDA pin outputs high. When writing, SDA pin is changed to output Hi-Z (outputs high by external pull-up resistance). 4 SDAOP 1 R/W SDAO Write Protect This bit controls change of output level of the SDA pin by modifying the SDAO bit. To change the output level, clear SDAO and SDAOP to 0 or set SDAO to 1 and clear SDAOP to 0 by the MOV instruction. This bit is always read as 1. Rev. 3.00 Sep. 14, 2006 Page 245 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 3 SCLO 1 R This bit monitors SCL output level. When SCLO is 1, SCL pin outputs high. When SCLO is 0, SCL pin outputs low. 2 1 Reserved This bit is always read as 1. 1 IICRST 0 R/W IIC Control Part Reset 2 This bit resets the control part except for I C registers. If this bit is set to 1 when hang-up occurs because of 2 2 communication failure during I C operation, I C control part can be reset without setting ports and initializing registers. 0 1 Reserved This bit is always read as 1. 15.3.3 I2C Bus Mode Register (ICMR) ICMR selects whether the MSB or LSB is transferred first, performs master mode wait control, and selects the transfer bit count. Bit Bit Name Initial Value R/W Description 7 MLS 0 R/W MSB-First/LSB-First Select 0: MSB-first 1: LSB-first Set this bit to 0 when the I2C bus format is used. 6 WAIT 0 R/W Wait Insertion Bit In master mode with the I2C bus format, this bit selects whether to insert a wait after data transfer except the acknowledge bit. When WAIT is set to 1, after the fall of the clock for the final data bit, low period is extended for two transfer clocks. If WAIT is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted. 2 The setting of this bit is invalid in slave mode with the I C bus format or with the clocked synchronous serial format. 5, 4 All 1 Reserved These bits are always read as 1. Rev. 3.00 Sep. 14, 2006 Page 246 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 3 BCWP 1 R/W BC Write Protect This bit controls the BC2 to BC0 modifications. When modifying BC2 to BC0, this bit should be cleared to 0 and use the MOV instruction. In clock synchronous serial mode, BC should not be modified. 0: When writing, values of BC2 to BC0 are set. 1: When reading, 1 is always read. When writing, settings of BC2 to BC0 are invalid. 2 BC2 0 R/W Bit Counter 2 to 0 1 BC1 0 0 BC0 0 R/W These bits specify the number of bits to be transferred next. number of transfer bits is R/W When read, the remaining indicated. With the I2C bus format, the data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL pin is low. The value returns to 000 at the end of a data transfer, including the acknowledge bit. With the clock synchronous serial format, these bits should not be modified. 2 I C Bus Format Clock Synchronous Serial Format 000: 9 bits 000: 8 bits 001: 2 bits 001: 1 bits 010: 3 bits 010: 2 bits 011: 4 bits 011: 3 bits 100: 5 bits 100: 4 bits 101: 6 bits 101: 5 bits 110: 7 bits 110: 6 bits 111: 8 bits 111: 7 bits Rev. 3.00 Sep. 14, 2006 Page 247 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) 15.3.4 I2C Bus Interrupt Enable Register (ICIER) ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits to be received. Bit Bit Name Initial Value R/W Description 7 TIE 0 R/W Transmit Interrupt Enable When the TDRE bit in ICSR is set to 1, this bit enables or disables the transmit data empty interrupt (TXI). 0: Transmit data empty interrupt request (TXI) is disabled. 1: Transmit data empty interrupt request (TXI) is enabled. 6 TEIE 0 R/W Transmit End Interrupt Enable This bit enables or disables the transmit end interrupt (TEI) at the rising of the ninth clock while the TDRE bit in ICSR is 1. TEI can be canceled by clearing the TEND bit or the TEIE bit to 0. 0: Transmit end interrupt request (TEI) is disabled. 1: Transmit end interrupt request (TEI) is enabled. 5 RIE 0 R/W Receive Interrupt Enable This bit enables or disables the receive data full interrupt request (RXI) and the overrun error interrupt request (ERI) with the clocked synchronous format, when a receive data is transferred from ICDRS to ICDRR and the RDRF bit in ICSR is set to 1. RXI can be canceled by clearing the RDRF or RIE bit to 0. 0: Receive data full interrupt request (RXI) and overrun error interrupt request (ERI) with the clocked synchronous format are disabled. 1: Receive data full interrupt request (RXI) and overrun error interrupt request (ERI) with the clocked synchronous format are enabled. Rev. 3.00 Sep. 14, 2006 Page 248 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 4 NAKIE 0 R/W NACK Receive Interrupt Enable This bit enables or disables the NACK receive interrupt request (NAKI) and the overrun error (setting of the OVE bit in ICSR) interrupt request (ERI) with the clocked synchronous format, when the NACKF and AL bits in ICSR are set to 1. NAKI can be canceled by clearing the NACKF, OVE, or NAKIE bit to 0. 0: NACK receive interrupt request (NAKI) is disabled. 1: NACK receive interrupt request (NAKI) is enabled. 3 STIE 0 R/W Stop Condition Detection Interrupt Enable 0: Stop condition detection interrupt request (STPI) is disabled. 1: Stop condition detection interrupt request (STPI) is enabled. 2 ACKE 0 R/W Acknowledge Bit Judgement Select 0: The value of the receive acknowledge bit is ignored, and continuous transfer is performed. 1: If the receive acknowledge bit is 1, continuous transfer is halted. 1 ACKBR 0 R Receive Acknowledge In transmit mode, this bit stores the acknowledge data that are returned by the receive device. This bit cannot be modified. 0: Receive acknowledge = 0 1: Receive acknowledge = 1 0 ACKBT 0 R/W Transmit Acknowledge In receive mode, this bit specifies the bit to be sent at the acknowledge timing. 0: 0 is sent at the acknowledge timing. 1: 1 is sent at the acknowledge timing. Rev. 3.00 Sep. 14, 2006 Page 249 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) 15.3.5 I2C Bus Status Register (ICSR) ICSR performs confirmation of interrupt request flags and status. Bit Bit Name Initial Value R/W Description 7 TDRE 0 R/W Transmit Data Register Empty [Setting conditions] * When data is transferred from ICDRT to ICDRS and ICDRT becomes empty * When TRS is set * When a start condition (including re-transfer) has been issued * When transmit mode is entered from receive mode in slave mode [Clearing conditions] 6 TEND 0 * When 0 is written in TDRE after reading TDRE = 1 * When data is written to ICDRT with an instruction R/W Transmit End [Setting conditions] * When the ninth clock of SCL rises with the I C bus format while the TDRE flag is 1 * When the final bit of transmit frame is sent with the clock synchronous serial format 2 [Clearing conditions] 5 RDRF 0 * When 0 is written in TEND after reading TEND = 1 * When data is written to ICDRT with an instruction R/W Receive Data Register Full [Setting condition] * When a receive data is transferred from ICDRS to ICDRR [Clearing conditions] * When 0 is written in RDRF after reading RDRF = 1 * When ICDRR is read with an instruction Rev. 3.00 Sep. 14, 2006 Page 250 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 4 NACKF 0 R/W No Acknowledge Detection Flag [Setting condition] * When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is 1 [Clearing condition] * 3 STOP 0 When 0 is written in NACKF after reading NACKF = 1 R/W Stop Condition Detection Flag [Setting conditions] * In master mode, when a stop condition is detected after frame transfer * In slave mode, when a stop condition is detected after the general call address or the first byte slave address, next to detection of start condition, accords with the address set in SAR [Clearing condition] * 2 AL/OVE 0 When 0 is written in STOP after reading STOP = 1 R/W Arbitration Lost Flag/Overrun Error Flag This flag indicates that arbitration was lost in master mode 2 with the I C bus format and that the final bit has been received while RDRF = 1 with the clocked synchronous format. When two or more master devices attempt to seize the bus 2 at nearly the same time, if the I C bus interface detects data differing from the data it sent, it sets AL to 1 to indicate that the bus has been taken by another master. [Setting conditions] * If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode * When the SDA pin outputs high in master mode while a start condition is detected * When the final bit is received with the clocked synchronous format while RDRF = 1 [Clearing condition] * When 0 is written in AL/OVE after reading AL/OVE=1 Rev. 3.00 Sep. 14, 2006 Page 251 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 1 AAS 0 R/W Slave Address Recognition Flag In slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR. [Setting conditions] * When the slave address is detected in slave receive mode * When the general call address is detected in slave receive mode. [Clearing condition] * 0 ADZ 0 When 0 is written in AAS after reading AAS=1 R/W General Call Address Recognition Flag 2 This bit is valid in I C bus format slave receive mode. [Setting condition] * When the general call address is detected in slave receive mode [Clearing condition] * 15.3.6 When 0 is written in ADZ after reading ADZ=1 Slave Address Register (SAR) SAR selects the communication format and sets the slave address. When the chip is in slave mode with the I2C bus format, if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device. Bit Bit Name Initial Value R/W Description 7 to 1 SVA6 to SVA0 All 0 0 0 FS R/W Slave Address 6 to 0 These bits set a unique address in bits SVA6 to SVA0, differing form the addresses of other slave devices 2 connected to the I C bus. R/W Format Select 2 0: I C bus format is selected. 1: Clocked synchronous serial format is selected. Rev. 3.00 Sep. 14, 2006 Page 252 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) 15.3.7 I2C Bus Transmit Data Register (ICDRT) ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during transferring data of ICDRS, continuous transfer is possible. If the MLS bit of ICMR is set to 1 and when the data is written to ICDRT, the MSB/LSB inverted data is read. The initial value of ICDRT is H'FF. 15.3.8 I2C Bus Receive Data Register (ICDRR) ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR transfers the receive data from ICDRS to ICDRR and the next data can be received. ICDRR is a receive-only register, therefore the CPU cannot write to this register. The initial value of ICDRR is H'FF. 15.3.9 I2C Bus Shift Register (ICDRS) ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from ICDRS to ICDRR after data of one byte is received. This register cannot be read directly from the CPU. Rev. 3.00 Sep. 14, 2006 Page 253 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) 15.4 Operation The I2C bus interface can communicate either in I2C bus mode or clocked synchronous serial mode by setting FS in SAR. 15.4.1 I2C Bus Format Figure 15.3 shows the I2C bus formats. Figure 15.4 shows the I2C bus timing. The first frame following a start condition always consists of 8 bits. (a) I2C bus format (FS = 0) S SLA R/W A DATA A A/A P 1 7 1 1 n 1 1 1 n: Transfer bit count (n = 1 to 8) m: Transfer frame count (m 1) m 1 (b) I2C bus format (Start condition retransmission, FS = 0) S SLA R/W A DATA A/A S SLA R/W A DATA A/A P 1 7 1 1 n1 1 1 7 1 1 n2 1 1 1 m1 1 m2 n1 and n2: Transfer bit count (n1 and n2 = 1 to 8) m1 and m2: Transfer frame count (m1 and m2 1) Figure 15.3 I2C Bus Formats SDA SCL S 1-7 8 9 SLA R/W A 1-7 DATA 8 9 A Figure 15.4 I2C Bus Timing Rev. 3.00 Sep. 14, 2006 Page 254 of 408 REJ09B0105-0300 1-7 DATA 8 9 A P 2 Section 15 I C Bus Interface 2 (IIC2) [Legend] S: Start condition. The master device drives SDA from high to low while SCL is high. SLA: Slave address R/W: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. A: Acknowledge. The receive device drives SDA to low. DATA: Transfer data P: Stop condition. The master device drives SDA from low to high while SCL is high. 15.4.2 Master Transmit Operation In master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For master transmit mode operation timing, refer to figures 15.5 and 15.6. The transmission procedure and operations in master transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2. Read the BBSY flag in ICCR2 to confirm that the bus is free. Set the MST and TRS bits in ICCR1 to select master transmit mode. Then, write 1 to BBSY and 0 to SCP using MOV instruction. (Start condition issued) This generates the start condition. 3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte data show the slave address and R/W) to ICDRT. At this time, TDRE is automatically cleared to 0, and data is transferred from ICDRT to ICDRS. TDRE is set again. 4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1 at the rise of the 9th transmit clock pulse. Read the ACKBR bit in ICIER, and confirm that the slave device has been selected. Then, write second byte data to ICDRT. When ACKBR is 1, the slave device has not been acknowledged, so issue the stop condition. To issue the stop condition, write 0 to BBSY and SCP using MOV instruction. SCL is fixed low until the transmit data is prepared or the stop condition is issued. 5. The transmit data after the second byte is written to ICDRT every time TDRE is set. 6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR = 1) from the receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or NACKF. 7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode. Rev. 3.00 Sep. 14, 2006 Page 255 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) SCL (Master output) 1 2 3 4 5 6 SDA (Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 7 8 Bit 1 Slave address 9 1 Bit 0 Bit 7 2 Bit 6 R/W SDA (Slave output) A TDRE TEND Address + R/W ICDRT ICDRS User processing Data 1 Address + R/W [2] Instruction of start condition issuance Data 2 Data 1 [4] Write data to ICDRT (second byte) [5] Write data to ICDRT (third byte) [3] Write data to ICDRT (first byte) Figure 15.5 Master Transmit Mode Operation Timing (1) SCL (Master output) 9 SDA (Master output) SDA (Slave output) 1 2 3 4 5 6 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 8 9 Bit 0 A/A A TDRE TEND Data n ICDRT ICDRS Data n User [5] Write data to ICDRT processing [6] Issue stop condition. Clear TEND. [7] Set slave receive mode Figure 15.6 Master Transmit Mode Operation Timing (2) Rev. 3.00 Sep. 14, 2006 Page 256 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) 15.4.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. For master receive mode operation timing, refer to figures 15.7 and 15.8. The reception procedure and operations in master receive mode are shown below. 1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master transmit mode to master receive mode. Then, clear the TDRE bit to 0. 2. When ICDRR is read (dummy data read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. The master device outputs the level specified by ACKBT in ICIER to SDA, at the 9th receive clock pulse. 3. After the reception of first frame data is completed, the RDRF bit in ICST is set to 1 at the rise of 9th receive clock pulse. At this time, the receive data is read by reading ICDRR, and RDRF is cleared to 0. 4. The continuous reception is performed by reading ICDRR every time RDRF is set. If 8th receive clock pulse falls after reading ICDRR by the other processing while RDRF is 1, SCL is fixed low until ICDRR is read. 5. If next frame is the last receive data, set the RCVD bit in ICCR1 to 1 before reading ICDRR. This enables the issuance of the stop condition after the next reception. 6. When the RDRF bit is set to 1 at rise of the 9th receive clock pulse, issue the stage condition. 7. When the STOP bit in ICSR is set to 1, read ICDRR. Then clear the RCVD bit to 0. 8. The operation returns to the slave receive mode. Rev. 3.00 Sep. 14, 2006 Page 257 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) Master transmit mode SCL (Master output) Master receive mode 9 1 2 3 4 5 6 7 8 SDA (Master output) 9 1 A SDA (Slave output) A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS RDRF ICDRS Data 1 ICDRR User processing Data 1 [3] Read ICDRR [1] Clear TDRE after clearing TEND and TRS [2] Read ICDRR (dummy read) Figure 15.7 Master Receive Mode Operation Timing (1) Rev. 3.00 Sep. 14, 2006 Page 258 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) SCL (Master output) 9 SDA (Master output) A SDA (Slave output) 1 2 3 4 5 6 7 8 9 A/A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RDRF RCVD ICDRS ICDRR User processing Data n Data n-1 Data n Data n-1 [5] Read ICDRR after setting RCVD [7] Read ICDRR, and clear RCVD [6] Issue stop condition [8] Set slave receive mode Figure 15.8 Master Receive Mode Operation Timing (2) 15.4.4 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. For slave transmit mode operation timing, refer to figures 15.9 and 15.10. The transmission procedure and operations in slave transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches. 2. When the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS and ICSR bits in ICCR1 are set to 1, and the mode changes to slave transmit mode automatically. The continuous transmission is performed by writing transmit data to ICDRT every time TDRE is set. 3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1, with TDRE = 1. When TEND is set, clear TEND. 4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is free. 5. Clear TDRE. Rev. 3.00 Sep. 14, 2006 Page 259 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) Slave transmit mode Slave receive mode SCL (Master output) 9 1 2 3 4 5 6 7 8 SDA (Master output) 9 1 A SCL (Slave output) SDA (Slave output) A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS Data 1 ICDRT ICDRS Data 2 Data 1 Data 3 Data 2 ICDRR User processing [2] Write data to ICDRT (data 1) [2] Write data to ICDRT (data 2) [2] Write data to ICDRT (data 3) Figure 15.9 Slave Transmit Mode Operation Timing (1) Rev. 3.00 Sep. 14, 2006 Page 260 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) Slave receive mode Slave transmit mode SCL (Master output) 9 SDA (Master output) A 1 2 3 4 5 6 7 8 9 A SCL (Slave output) SDA (Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TDRE TEND TRS ICDRT ICDRS Data n ICDRR User processing [3] Clear TEND [4] Read ICDRR (dummy read) after clearing TRS [5] Clear TDRE Figure 15.10 Slave Transmit Mode Operation Timing (2) 15.4.5 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For slave receive mode operation timing, refer to figures 15.11 and 15.12. The reception procedure and operations in slave receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches. 2. When the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the read data show the slave address and R/W, it is not used.) 3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be returned to the master device, is reflected to the next transmit frame. Rev. 3.00 Sep. 14, 2006 Page 261 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) 4. The last byte data is read by reading ICDRR. SCL (Master output) 9 SDA (Master output) 1 2 3 4 5 6 7 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 1 Bit 7 SCL (Slave output) SDA (Slave output) A A RDRF ICDRS Data 1 Data 2 ICDRR User processing Data 1 [2] Read ICDRR [2] Read ICDRR (dummy read) Figure 15.11 Slave Receive Mode Operation Timing (1) SCL (Master output) 9 SDA (Master output) 1 2 3 4 5 6 7 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 SCL (Slave output) SDA (Slave output) A A RDRF ICDRS Data 2 Data 1 ICDRR Data 1 User processing [3] Set ACKBT [3] Read ICDRR [4] Read ICDRR Figure 15.12 Slave Receive Mode Operation Timing (2) Rev. 3.00 Sep. 14, 2006 Page 262 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) 15.4.6 Clocked Synchronous Serial Format This module can be operated with the clocked synchronous serial format, by setting the FS bit in SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When MST is 0, the external clock input is selected. (1) Data Transfer Format: Figure 15.13 shows the clocked synchronous serial transfer format. The transfer data is output from the rise to the fall of the SCL clock, and the data at the rising edge of the SCL clock is guaranteed. The MLS bit in ICMR sets the order of data transfer, in either the MSB first or LSB first. The output level of SDA can be changed during the transfer wait, by the SDAO bit in ICCR2. SCL SDA Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Figure 15.13 Clocked Synchronous Serial Transfer Format (2) Transmit Operation: In transmit mode, transmit data is output from SDA, in synchronization with the fall of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For transmit mode operation timing, refer to figure 15.14. The transmission procedure and operations in transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2. Set the TRS bit in ICCR1 to select the transmit mode. Then, TDRE in ICSR is set. 3. Confirm that TDRE has been set. Then, write the transmit data to ICDRT. The data is transferred from ICDRT to ICDRS, and TDRE is set automatically. The continuous transmission is performed by writing data to ICDRT every time TDRE is set. When changing from transmit mode to receive mode, clear TRS while TDRE is 1. Rev. 3.00 Sep. 14, 2006 Page 263 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) SCL 1 2 7 8 1 7 8 1 SDA (Output) Bit 0 Bit 1 Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0 TRS TDRE Data 1 ICDRT Data 1 ICDRS User processing Data 2 [3] Write data [3] Write data to ICDRT to ICDRT [2] Set TRS Data 3 Data 2 Data 3 [3] Write data to ICDRT [3] Write data to ICDRT Figure 15.14 Transmit Mode Operation Timing (3) Receive Operation: In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For receive mode operation timing, refer to figure 15.15. The reception procedure and operations in receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2. When the transfer clock is output, set MST to 1 to start outputting the receive clock. 3. When the receive operation is completed, data is transferred from ICDRS to ICDRR and RDRF in ICSR is set. When MST = 1, the next byte can be received, so the clock is continually output. The continuous reception is performed by reading ICDRR every time RDRF is set. When the 8th clock is risen while RDRF is 1, the overrun is detected and AL/OVE in ICSR is set. At this time, the previous reception data is retained in ICDRR. 4. To stop receiving when MST = 1, set RCVD in ICCR1 to 1, then read ICDRR. Then, SCL is fixed high after receiving the next byte data. Rev. 3.00 Sep. 14, 2006 Page 264 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) SCL 1 2 7 8 1 7 8 1 2 SDA (Input) Bit 0 Bit 1 Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0 Bit 1 MST TRS RDRF Data 2 Data 1 ICDRS ICDRR Data 3 Data 1 User processing [2] Set MST (when outputting the clock) Data 2 [3] Read ICDRR [3] Read ICDRR Figure 15.15 Receive Mode Operation Timing 15.4.7 Noise Canceler The logic levels at the SCL and SDA pins are routed through the noise canceler before being latched internally. Figure 15.16 shows a block diagram of the noise canceler. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held. Sampling clock C SCL or SDA input signal D C Q Latch Q D Latch March detector Internal SCL or SDA signal System clock period Sampling clock Figure 15.16 Block Diagram of Noise Canceler Rev. 3.00 Sep. 14, 2006 Page 265 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) 15.4.8 Example of Use Flowcharts in respective modes that use the I2C bus interface are shown in figures 15.17 to 15.20. Start [1] Test the status of the SCL and SDA lines. Initialize Read BBSY in ICCR2 No [2] Set master transmit mode. [1] BBSY=0 ? [3] Issue the start candition. Yes Set MST and TRS in ICCR1 to 1. [2] [4] Set the first byte (slave address + R/W) of transmit data. Write 1 to BBSY and 0 to SCP. Write transmit data in ICDRT [3] [5] Wait for 1 byte to be transmitted. [4] [6] Test the acknowledge transferred from the specified slave device. [7] Set the second and subsequent bytes (except for the final byte) of transmit data. Read TEND in ICSR No [5] [8] Wait for ICDRT empty. TEND=1 ? Yes Read ACKBR in ICIER ACKBR=0 ? [9] Set the last byte of transmit data. No Yes No Transmit mode? Yes Write transmit data in ICDRT [6] [10] Wait for last byte to be transmitted. [11] Clear the TEND flag. Mater receive mode [7] [12] Clear the STOP flag. [13] Issue the stop condition. Read TDRE in ICSR No TDRE=1 ? [8] Yes No [14] Wait for the creation of stop condition. [15] Set slave receive mode. Clear TDRE. Last byte? Yes Write transmit data in ICDRT [9] Read TEND in ICSR No [10] TEND=1 ? Yes Clear TEND in ICSR [11] Clear STOP in ICSR [12] Write 0 to BBSY and SCP [13] Read STOP in ICSR No STOP=1 ? Yes Set MST to 1 and TRS to 0 in ICCR1 [14] [15] Clear TDRE in ICSR End Figure 15.17 Sample Flowchart for Master Transmit Mode Rev. 3.00 Sep. 14, 2006 Page 266 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) Mater receive mode [1] Clear TEND, select master receive mode, and then clear TDRE.* Clear TEND in ICSR Clear TRS in ICCR1 to 0 [1] [2] Set acknowledge to the transmit device.* [3] Dummy-read ICDDR.* Clear TDRE in ICSR Clear ACKBT in ICIER to 0 [2] [4] Wait for 1 byte to be received Dummy-read ICDRR [3] [5] Check whether it is the (last receive - 1). Read RDRF in ICSR No RDRF=1 ? [6] Read the receive data last. [4] [7] Set acknowledge of the final byte. Disable continuous reception (RCVD = 1). [8] Read the (final byte - 1) of receive data. Yes Last receive - 1? No Read ICDRR Yes [5] [6] [9] Wait for the last byte to be receive. [10] Clear the STOP flag. [11] Issue the stop condition. [12] Wait for the creation of stop condition. Set ACKBT in ICIER to 1 [7] Set RCVD in ICCR1 to 1 Read ICDRR [13] Read the last byte of receive data. [14] Clear RCVD. [8] [15] Set slave receive mode. Read RDRF in ICSR No RDRF=1 ? Yes Clear STOP in ICSR. Write 0 to BBSY and SCP [9] [10] [11] Read STOP in ICSR No STOP=1 ? [12] Yes Read ICDRR [13] Clear RCVD in ICCR1 to 0 [14] Clear MST in ICCR1 to 0 [15] End Note: Do not activate an interrupt during the execution of steps [1] to [3]. Supplementary explanation: When one byte is received, steps [2] to [6] are skipped after step [1], before jumping to step [7]. The step [8] is dammy-read in ICDRR. Figure 15.18 Sample Flowchart for Master Receive Mode Rev. 3.00 Sep. 14, 2006 Page 267 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) [1] Clear the AAS flag. Slave transmit mode Clear AAS in ICSR [1] Write transmit data in ICDRT [2] [3] Wait for ICDRT empty. [4] Set the last byte of transmit data. [5] Wait for the last byte to be transmitted. Read TDRE in ICSR [3] No [2] Set transmit data for ICDRT (except for the last data). [6] Clear the TEND flag . TDRE=1 ? [7] Set slave receive mode. Yes [8] Dummy-read ICDRR to release the SCL line. Last byte? No Yes [4] [9] Clear the TDRE flag. Write transmit data in ICDRT Read TEND in ICSR [5] No TEND=1 ? Yes Clear TEND in ICSR [6] Clear TRS in ICCR1 to 0 [7] Dummy read ICDRR [8] Clear TDRE in ICSR [9] End Figure 15.19 Sample Flowchart for Slave Transmit Mode Rev. 3.00 Sep. 14, 2006 Page 268 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) Slave receive mode [1] Clear the AAS flag. Clear AAS in ICSR [1] Clear ACKBT in ICIER to 0 [2] Dummy-read ICDRR [3] [2] Set acknowledge to the transmit device. [3] Dummy-read ICDRR. [4] Wait for 1 byte to be received. [5] Check whether it is the (last receive - 1). Read RDRF in ICSR No [4] RDRF=1 ? [6] Read the receive data. [7] Set acknowledge of the last byte. Yes Last receive - 1? No Read ICDRR Yes [8] Read the (last byte - 1) of receive data. [5] [9] Wait the last byte to be received. [6] Set ACKBT in ICIER to 1 [7] Read ICDRR [8] [10] Read for the last byte of receive data. Read RDRF in ICSR No [9] RDRF=1 ? Yes Read ICDRR [10] End Supplementary explanation: When one byte is received, steps [2] to [6] are skipped after step [1], before jumping to step [7]. The step [8] is dammy-read in ICDRR. Figure 15.20 Sample Flowchart for Slave Receive Mode Rev. 3.00 Sep. 14, 2006 Page 269 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) 15.5 Interrupts There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK receive, STOP recognition, and arbitration lost/overrun error. Table 15.3 shows the contents of each interrupt request. Table 15.3 Interrupt Requests Interrupt Request Abbreviation Interrupt Condition Clocked Synchronous 2 I C Mode Mode Transmit Data Empty TXI (TDRE=1) * (TIE=1) { { Transmit End TEI (TEND=1) * (TEIE=1) { { Receive Data Full RXI (RDRF=1) * (RIE=1) { { STOP Recognition STPI (STOP=1) (STIE=1) { x NACK Receive NAKI {(NACKF=1)+(AL=1)} (NAKIE=1) { x { { Arbitration Lost/Overrun Error * * When interrupt conditions described in table 15.3 are 1 and the I bit in CCR is 0, the CPU executes an interrupt exception processing. Interrupt sources should be cleared in the exception processing. TDRE and TEND are automatically cleared to 0 by writing the transmit data to ICDRT. RDRF are automatically cleared to 0 by reading ICDRR. TDRE is set to 1 again at the same time when transmit data is written to ICDRT. When TDRE is cleared to 0, then an excessive data of one byte may be transmitted. Rev. 3.00 Sep. 14, 2006 Page 270 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) 15.6 Bit Synchronous Circuit In master mode, this module has a possibility that high level period may be short in the two states described below. * When SCL is driven to low by the slave device * When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pullup resistance) Therefore, it monitors SCL and communicates by bit with synchronization. Figure 15.21 shows the timing of the bit synchronous circuit and table 15.4 shows the time when SCL output changes from low to Hi-Z then SCL is monitored. SCL monitor timing reference clock VIH SCL Internal SCL Figure 15.21 Timing of Bit Synchronous Circuit Table 15.4 Time for Monitoring SCL CKS3 CKS2 Time for Monitoring SCL 0 0 7.5 tcyc 1 19.5 tcyc 0 17.5 tcyc 1 41.5 tcyc 1 Rev. 3.00 Sep. 14, 2006 Page 271 of 408 REJ09B0105-0300 2 Section 15 I C Bus Interface 2 (IIC2) 15.7 Usage Notes 15.7.1 Issue (Retransmission) of Start/Stop Conditions In master mode, when the start/stop conditions are issued (retransmitted) at the specific timing under the following condition 1 or 2, such conditions may not be output successfully. To avoid this, issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed. Check the SCLO bit in the I2C control register 2 (IICR2) to confirm the fall of the ninth clock. 1. When the rising of SCL falls behind the time specified in section 15.6, Bit Synchronous Circuit, by the load of the SCL bus (load capacitance or pull-up resistance) 2. When the bit synchronous circuit is activated by extending the low period of eighth and ninth clocks, that is driven by the slave device 15.7.2 WAIT Setting in I2C Bus Mode Register (ICMR) If the WAIT bit is set to 1, and the SCL signal is driven low for two or more transfer clocks by the slave device at the eighth and ninth clocks, the high period of ninth clock may be shortened. To avoid this, set the WAIT bit in ICMR to 0. Rev. 3.00 Sep. 14, 2006 Page 272 of 408 REJ09B0105-0300 Section 16 A/D Converter Section 16 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to four analog input channels to be selected. The block diagram of the A/D converter is shown in figure 16.1. 16.1 * * * * * * * * Features 10-bit resolution Four input channels Conversion time: At least 7 s per channel (at 10 MHz operation) Two operating modes Single mode: Single-channel A/D conversion Scan mode: Continuous A/D conversion on 1 to 4 channels Four data registers Conversion results are held in a 16-bit data register for each channel Sample and hold function Two conversion start methods Software External trigger signal Interrupt request An A/D conversion end interrupt request (ADI) can be generated ADCMS32A_000020020200 Rev. 3.00 Sep. 14, 2006 Page 273 of 408 REJ09B0105-0300 Section 16 A/D Converter Internal data bus AVCC AN0 AN1 AN2 AN3 Analog multiplexer 10-bit D/A A D D R A A D D R B A D D R C A D D R D Bus interface Successive approximations register Module data bus A D C S R A D C R + /4 Control circuit Comparator Sample-andhold circuit ADTRG [Legend] ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD: A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D Figure 16.1 Block Diagram of A/D Converter Rev. 3.00 Sep. 14, 2006 Page 274 of 408 REJ09B0105-0300 /8 ADI interrupt request Section 16 A/D Converter 16.2 Input/Output Pins Table 16.1 summarizes the input pins used by the A/D converter. Table 16.1 Pin Configuration Pin Name Symbol I/O Function Analog power supply pin AVCC Input Analog block power supply pin Analog input pin 0 AN0 Input Analog input pins Analog input pin 1 AN1 Input Analog input pin 2 AN2 Input Analog input pin 3 AN3 Input A/D external trigger input pin ADTRG Input 16.3 External trigger input pin for starting A/D conversion Register Description The A/D converter has the following registers. * * * * * * A/D data register A (ADDRA) A/D data register B (ADDRB) A/D data register C (ADDRC) A/D data register D (ADDRD) A/D control/status register (ADCSR) A/D control register (ADCR) 16.3.1 A/D Data Registers A to D (ADDRA to ADDRD) There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown in table 16.2. The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0. The data bus between the CPU and the A/D converter is 8 bits wide. The upper byte can be read directly from the CPU, however the lower byte should be read via a temporary register. The temporary register contents are transferred from the ADDR when the upper byte data is read. Rev. 3.00 Sep. 14, 2006 Page 275 of 408 REJ09B0105-0300 Section 16 A/D Converter Therefore, byte access to ADDR should be done by reading the upper byte first then the lower one. ADDR is initialized to H'0000. Table 16.2 Analog Input Channels and Corresponding ADDR Registers Analog Input Channel A/D Data Register to Be Stored Results of A/D Conversion AN0 ADDRA AN1 ADDRB AN2 ADDRC AN3 ADDRD 16.3.2 A/D Control/Status Register (ADCSR) ADCSR consists of the control bits and conversion end status bits of the A/D converter. Bit Bit Name Initial Value R/W Description 7 ADF 0 R/W A/D End Flag [Setting conditions] * When A/D conversion ends in single mode * When A/D conversion ends on all the channels selected in scan mode [Clearing condition] * 6 ADIE 0 R/W When 0 is written after reading ADF = 1 A/D Interrupt Enable A/D conversion end interrupt (ADI) request enabled by ADF when 1 is set 5 ADST 0 R/W A/D Start Setting this bit to 1 starts A/D conversion. In single mode, this bit is cleared to 0 automatically when conversion on the specified channel is complete. In scan mode, conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or a transition to standby mode. Rev. 3.00 Sep. 14, 2006 Page 276 of 408 REJ09B0105-0300 Section 16 A/D Converter Bit Bit Name Initial Value R/W Description 4 SCAN 0 R/W Scan Mode Selects single mode or scan mode as the A/D conversion operating mode. 0: Single mode 1: Scan mode 3 CKS 0 R/W Clock Select Selects the A/D conversions time 0: Conversion time = 134 states (max.) 1: Conversion time = 70 states (max.) Clear the ADST bit to 0 before switching the conversion time. 2 CH2 0 R/W Channel Select 0 to 2 1 CH1 0 R/W Select analog input channels. 0 CH0 0 R/W When SCAN = 0 When SCAN = 1 000: AN0 000: AN0 001: AN1 001: AN0 to AN1 010: AN2 010: AN0 to AN2 011: AN3 011: AN0 to AN3 Note: When executing the A/D conversion through AN3 or AN2, do not set the VDDII bit in LVDCR to 0. If 0 is set, the A/D conversion accuracy is not guaranteed. Rev. 3.00 Sep. 14, 2006 Page 277 of 408 REJ09B0105-0300 Section 16 A/D Converter 16.3.3 A/D Control Register (ADCR) ADCR enables A/D conversion started by an external trigger signal. Bit Bit Name Initial Value R/W Description 7 TRGE 0 R/W Trigger Enable A/D conversion is started at the falling edge and the rising edge of the external trigger signal (ADTRG) when this bit is set to 1. The selection between the falling edge and rising edge of the external trigger pin (ADTRG) conforms to the WPEG5 bit in the interrupt edge select register 2 (IEGR2) 6 to 4 -- All 1 -- Reserved These bits are always read as 1. 3, 2 -- All 0 R/W Reserved Although these bits are readable/writable, they should not be set to 1. 1 -- 1 R/W Reserved This bit is always read as 1. 0 -- 0 R/W Reserved Although this bit is readable/writable, it should not be set to 1. Rev. 3.00 Sep. 14, 2006 Page 278 of 408 REJ09B0105-0300 Section 16 A/D Converter 16.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 16.4.1 Single Mode In single mode, A/D conversion is performed once for the analog input on the specified single channel as follows: 1. 2. 3. 4. A/D conversion is started from the first channel when the ADST bit in ADCSR is set to 1, according to software or external trigger input. When A/D conversion is completed, the result is transferred to the corresponding A/D data register to the channel. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. The ADST bit remains set to 1 during A/D conversion. When A/D conversion ends, the ADST bit is automatically cleared to 0 and the A/D converter enters the wait state. 16.4.2 Scan Mode In scan mode, A/D conversion is performed sequentially for the analog input on the specified channels (four channels maximum) as follows: 1. When the ADST bit is set to 1 by software, or external trigger input, A/D conversion starts on the first channel in the group. 2. When A/D conversion for each channel is completed, the result is sequentially transferred to the A/D data register corresponding to each channel. 3. When conversion of all the selected channels is completed, the ADF flag in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested. Conversion of the first channel in the group starts again. 4. The ADST bit is not automatically cleared to 0. Steps [2] to [3] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. Rev. 3.00 Sep. 14, 2006 Page 279 of 408 REJ09B0105-0300 Section 16 A/D Converter 16.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) has passed after the ADST bit is set to 1, then starts conversion. Figure 16.2 shows the A/D conversion timing. Table 16.3 shows the A/D conversion time. As indicated in figure 16.2, the A/D conversion time includes tD and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 16.3. In scan mode, the values given in table 16.3 apply to the first conversion time. In the second and subsequent conversions, the conversion time is 128 states (fixed) when CKS = 0 and 66 states (fixed) when CKS = 1. (1) Address (2) Write signal Input sampling timing ADF tD tSPL tCONV [Legend] (1): ADCSR write cycle (2): ADCSR address A/D conversion start delay tD: tSPL: Input sampling time tCONV: A/D conversion time Figure 16.2 A/D Conversion Timing Rev. 3.00 Sep. 14, 2006 Page 280 of 408 REJ09B0105-0300 Section 16 A/D Converter Table 16.3 A/D Conversion Time (Single Mode) CKS = 0 Item Symbol Min. CKS = 1 Typ. Max. Min. Typ. Max. A/D conversion start delay tD 6 -- 9 4 -- 5 Input sampling time tSPL -- 31 -- -- 15 -- A/D conversion time tCONV 131 -- 134 69 -- 70 Note: All values represent the number of states. 16.4.4 External Trigger Input Timing A/D conversion can also be started by an external trigger input. When the TRGE bit is set to 1 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG input pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as when the bit ADST has been set to 1 by software. Figure 16.3 shows the timing. ADTRG Internal trigger signal ADST A/D conversion Figure 16.3 External Trigger Input Timing Rev. 3.00 Sep. 14, 2006 Page 281 of 408 REJ09B0105-0300 Section 16 A/D Converter 16.5 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. * Resolution The number of A/D converter digital output codes * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 16.4). * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (see figure 16.5). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from 1111111110 to 1111111111 (see figure 16.5). * Nonlinearity error The error with respect to the ideal A/D conversion characteristics between zero voltage and full-scale voltage. Does not include offset error, full-scale error, or quantization error. * Absolute accuracy The deviation between the digital value and the analog input value. Includes offset error, fullscale error, quantization error, and nonlinearity error. Rev. 3.00 Sep. 14, 2006 Page 282 of 408 REJ09B0105-0300 Section 16 A/D Converter Digital output Ideal A/D conversion characteristic 111 110 101 100 011 010 Quantization error 001 000 1 8 2 8 3 8 4 8 5 8 6 8 7 FS 8 Analog input voltage Figure 16.4 A/D Conversion Accuracy Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Offset error FS Analog input voltage Figure 16.5 A/D Conversion Accuracy Definitions (2) Rev. 3.00 Sep. 14, 2006 Page 283 of 408 REJ09B0105-0300 Section 16 A/D Converter 16.6 Usage Notes 16.6.1 Permissible Signal Source Impedance This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k, charging may be insufficient and it may not be possible to guarantee A/D conversion accuracy. However, for A/D conversion in single mode with a large capacitance provided externally, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/s or greater) (see figure 16.6). When converting a high-speed analog signal or converting in scan mode, a low-impedance buffer should be inserted. 16.6.2 Influences on Absolute Accuracy Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute accuracy. Be sure to make the connection to an electrically stable GND. Care is also required to ensure that filter circuits do not interfere with digital signals or act as antennas on the mounting board. This LSI Sensor output impedance to 5 k A/D converter equivalent circuit 10 k Sensor input Low-pass filter C to 0.1 F Cin = 15 pF Figure 16.6 Analog Input Circuit Example Rev. 3.00 Sep. 14, 2006 Page 284 of 408 REJ09B0105-0300 20 pF Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits This LSI can include a band-gap circuit (BGR, band-gap regulator), a power-on reset circuit and low-voltage detection circuit. BGR supplies a reference voltage to the on-chip oscillator and low-voltage detection circuit. Figure 17.1 shows the block diagram of how BGR is allocated. The low-voltage detection (LVD) circuit consists of two circuits: LVDI (interrupt by low voltage detection) and LVDR (reset by low voltage detection) circuits. This circuit is used to prevent abnormal operation (program runaway) from occurring due to the power supply voltage fall and to recreate the state before the power supply voltage fall when the power supply voltage rises again. Even if the power supply voltage falls, the unstable state when the power supply voltage falls below the guaranteed operating voltage can be removed by entering standby mode when exceeding the guaranteed operating voltage and during normal operation. Thus, system stability can be improved. If the power supply voltage falls more, the reset state is automatically entered. If the power supply voltage rises again, the reset state is held for a specified period, then active mode is automatically entered. Figure 17.2 is a block diagram of the power-on reset circuit and the low-voltage detection circuit. PSCKT00A_000020020200 Rev. 3.00 Sep. 14, 2006 Page 285 of 408 REJ09B0105-0300 Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits 17.1 Features * BGR circuit Supplies stable reference voltage covering the entire operating voltage range and the operating temperature range. Reduces power consumption when BGR is disabled by setting registers. * Power-on reset circuit Uses an external capacitor to generate an internal reset signal when power is first supplied. * Low-voltage detection circuit LVDR: Monitors the power-supply voltage, and generates an internal reset signal when the voltage falls below a given value. LVDI: Monitors the power-supply voltage, and generates an interrupt when the voltage falls below or rises above respective given values. Two detection levels for reset generation voltage are available: when only the LVDR circuit is used, or when the LVDI and LVDR circuits are both used. VCLSEL Vcc Step-down circuit VCL On-chip oscillator BGRE BGR VBGR RCSTP LVDE [Legend] Vcc: BGRE: VCL: VBGR: VCLSEL: RCSTP: LVDE: LVD (low-voltage detection circuit) Power supply BGR circuit enable signal Internal power supply generated from Vcc by the step-down circuit Reference voltage from BGR Select signal for the source of the on-chip oscillator power supply On-chip oscillator stop signal LVD enable signal Figure 17.1 Block Diagram around BGR Rev. 3.00 Sep. 14, 2006 Page 286 of 408 REJ09B0105-0300 Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits OVF CK PSS R R RES Noise filter circuit Internal reset signal Q S CRES Power-on reset circuit Noise filter circuit External power supply Vcc Vreset VintU VintD ExtD LVDRES LVDINT Interrupt control circuit LVDSR Internal data bus LVDCR Ladder network ExtU VDDII Interrupt request VBGR [Legend] PSS: LVDCR: LVDSR: VBGR: ExtD: ExtU: VDDII: Prescaler S Low-voltage-detection control register Low-voltage-detection status register Reference voltage from BGR Compared voltage for falling external input voltage Compared voltage for rising external input voltage Bit 5 in LVDCR Figure 17.2 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit Rev. 3.00 Sep. 14, 2006 Page 287 of 408 REJ09B0105-0300 Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits 17.2 Register Descriptions The low-voltage detection circuit has the following registers. * Low-voltage-detection control register (LVDCR) * Low-voltage-detection status register (LVDSR) 17.2.1 Low-Voltage-Detection Control Register (LVDCR) LVDCR enables or disables the low-voltage detection circuit and BGR circuit, selects the compared voltage of the LVDI circuit, sets the detection levels for the LVDR circuit, enables or disables the LVDR circuit, and enables or disables generation of an interrupt when the powersupply voltage rises above or falls below the respective levels. Table 17.1 shows the relationship between the LVDCR settings and functions to be selected. LVDCR should be set according to table 17.1. Bit Bit Name Initial Value R/W Description 7 LVDE 1* R/W LVD Enable 0: Low-voltage detection circuit is not used (standby mode) 1: Low-voltage detection circuit is used 6 BGRE 1* R/W BGR Enable 0: BGR circuit is not used (standby mode) 1: BGR circuit is used 5 VDDII 1* R/W LVDR External Compared Voltage Input Inhibit 0: Use external voltage as LVDI compared voltage 1: Use internal voltage as LVDI compared voltage 4 1 Reserved This bit is always read as 1 and cannot be modified. Rev. 3.00 Sep. 14, 2006 Page 288 of 408 REJ09B0105-0300 Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits Bit Bit Name Initial Value R/W Description 3 LVDSEL 0* R/W LVDR Detection Level Select 0: Reset detection voltage is 2.3 V (Typ.) 1: Reset detection voltage is 3.6 V (Typ.) When the falling or rising voltage detection interrupt is used, the reset detection voltage of 2.3 V (Typ.) should be used. When only a reset detection interrupt is used, reset detection voltage of 3.6 V (Typ.) should be used. 2 LVDRE 1* R/W LVDR Enable 0: Disables an LVDR 1: Enables an LVDR 1 LVDDE 0 R/W Voltage-Fall-Interrupt Enable 0: Interrupt on the power-supply voltage falling disabled 1: Interrupt on the power-supply voltage falling enabled 0 LVDUE 0 R/W Voltage-Rise-Interrupt Enable 0: Interrupt on the power-supply voltage rising disabled 1: Interrupt on the power-supply voltage rising enabled Note: * Not initialized by an LVDR but initialized by a power-on reset or a watchdog timer reset. Table 17.1 LVDCR Settings and Select Functions LVDCR Settings LVDE BGRE VDDII LVDSEL LVDRE 0 1 1 *1 1 1 Select Functions LVDDE LVDUE Power-On Reset LVDR LowVoltageDetection Fall Interrupt LowVoltageDetection Rise Interrupt *2 *2 *2 *2 1 1 1 0 0 1 0 0 1 0 1 *2 * * 1 1 * 0 0 1 1 1 1 *1 0 1 1 1 Notes: 1. Set these bits if necessary. 2. Settings are ignored. Rev. 3.00 Sep. 14, 2006 Page 289 of 408 REJ09B0105-0300 Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits 17.2.2 Low-Voltage-Detection Status Register (LVDSR) LVDSR indicates whether the power-supply voltage falls below or rises above the respective given values. Bit Bit Name Initial Value R/W Description 7 to 2 All 1 Reserved These bits are always read as 1 and cannot be modified. 1 LVDDF 0* R/W LVD Power-Supply Voltage Fall Flag [Setting condition] * When the power-supply voltage falls below Vint (D) (Typ. = 3.7 V) [Clearing condition] * 0 LVDUF 0* R/W When writing 0 to this bit after reading it as 1 LVD Power-Supply Voltage Rise Flag [Setting condition] * When the power supply voltage falls below Vint (D) while the LVDUE bit in LVDCR is set to 1 and then rises above Vint (U) (Typ. = 4.0 V) before falling below Vreset1 (Typ. = 2.3 V) [Clearing condition] * Note: * Initialized by an LVDR. Rev. 3.00 Sep. 14, 2006 Page 290 of 408 REJ09B0105-0300 When writing 0 to this bit after reading it as 1 Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits 17.3 Operations 17.3.1 Power-On Reset Circuit Figure 17.3 shows the timing of the operation of the power-on reset circuit. As the power-supply voltage rises, the capacitor which is externally connected to the RES pin is gradually charged via the internal pull-up resistor (Typ. 150 k). While the RES signal is driven low, the prescaler S and the entire chip retains the reset state. When the level on the RES signal reaches the specified value, the prescaler S is released from its reset state and it starts counting. The OVF signal is generated to release the internal reset signal after the prescaler S has counted 131,072 cycles of the clock. The noise filter circuit which removes noise with less than 400 ns (Typ.) is included to prevent the incorrect operation of this LSI caused by noise on the RES signal. To achieve stable operation of this LSI, the power supply needs to rise to its full level and settles within the specified time. The maximum time required for the power supply to rise and settle (tPWON) is determined by the oscillation frequency (fOSC) and capacitance which is connected to RES pin (CRES). Where tPWON is assumed to be the time required to reach 90 % of the full level of the power supply, the power supply circuit should be designed to satisfy the following formula. tPWON (ms) 90 x CRES (F) + 162/fOSC (MHz) (tPWON 3000 ms, CRES 0.22 F, and fOSC = 10 in 2-MHz to 10-MHz operation) Note that the power supply voltage (Vcc) must fall below Vpor = 100 mV to remove charge on the RES pin. After that, it can be risen. To remove charge on the RES pin, it is recommended that the diode should be placed to Vcc. If the power supply voltage (Vcc) rises from the point above Vpor, a power-on reset may not occur. Rev. 3.00 Sep. 14, 2006 Page 291 of 408 REJ09B0105-0300 Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits tPWON Vcc Vpor Vss RES Vss PSS-reset signal OVF Internal reset signal 131,072 cycles PSS counter starts Reset released Figure 17.3 Operational Timing of Power-On Reset Circuit 17.3.2 (1) Low-Voltage Detection Circuit LVDR (Reset by Low Voltage Detection) Circuit Figure 17.4 shows the timing of the operation of the LVDR circuit. The LVDR circuit is enabled after a power-on reset is released. To cancel the LVDR circuit, first the LVDRE bit in LVDCR should be cleared to 0 and then the LVDE bit in LVDCR and, if necessary, the BGRE bit should be cleared to 0. The LVDE and the BGRE bits must not be cleared to 0 simultaneously with the LVDRE bit because incorrect operation may occur. To restart the LVDR circuit, set the LVDE bit and the BGRE bit to 1, wait for 50 s (tLVDON) given by a software timer until the reference voltage and the low-voltage-detection power supply have settled, then set the LVDRE bit to 1. After that, the output settings of ports must be made. When the power-supply voltage falls below the Vreset voltage (2.3 V or 3.6 V (Typ.)), the LVDR circuit clears the LVDRES signal to 0, and resets prescaler S. The low-voltage detection reset state remains in place until a power-on reset is generated. When the power-supply voltage rises above the Vreset voltage again, prescaler S starts counting. It counts 131,072 clock () cycles, and then releases the internal reset signal. In this case, the LVDE, BGRE, VDDII, LVDSEL, and LVDRE bits in LVDCR are not initialized. Note that if the power supply voltage (Vcc) falls below VLVDRmin = 1.0 V and then rises from that point, the low-voltage detection reset may not occur. If the power supply voltage (Vcc) falls below Vpor = 100 mV, a power-on reset occurs. Rev. 3.00 Sep. 14, 2006 Page 292 of 408 REJ09B0105-0300 Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits VCC Vreset VLVDRmin VSS LVDRES PSS-reset signal OVF Internal reset signal 131,072 cycles PSS counter starts Reset released Figure 17.4 Operating Timing of LVDR Circuit (2) Low Voltage Detection Interrupt (LVDI) Circuit (When Internally Generated Voltage is used for Detection) Figure 17.5 shows the timing of the operation of the LVDI circuit. The LVDI circuit is enabled after a power-on reset, however, the interrupt request is disabled. To enable the LVDI, the LVDDF bit and LVDUF bit in LVDSR must be cleared to 0 and then the LVDDE bit or LVDUE bit in LVDCR must be set to 1. After that, the output settings of ports must be made. To cancel the LVDI, follow the procedures written in section 17.3.2 (4), Operating Procedures for Enabling/Disabling LVDR and LVDI Circuits. To restart the LVDI circuit after standby mode, set the LVDE bit to 1, write 1 to VDDII (if necessary), and wait for 50 s (tLVDON) given by a software timer until the reference voltage and the low-voltage detection power supply have settled. Then, clear the LVDDF and LVDUF bits to 0 and set the LVDDE or the LVDUE bit to 1. After that, the output settings of ports must be made. When the power-supply voltage falls below Vint (D) (Typ. = 3.7 V) voltage, the LVDI circuit clears the LVDINT signal to 0 and sets the LVDDF bit to 1. If the LVDDE bit is 1 at this time, an IRQ0 interrupt request is generated. In this case, the necessary data must be saved in the external Rev. 3.00 Sep. 14, 2006 Page 293 of 408 REJ09B0105-0300 Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits EEPROM and a transition to standby mode or subsleep mode must be made. Until this processing is completed, the power supply voltage must be higher than the lower limit of the guaranteed operating voltage. When the power-supply voltage does not fall below the Vreset1 (Typ. = 2.3 V) voltage and rises above the Vint (U) (Typ. = 4.0 V) voltage, the LVDI circuit sets the LVDINT signal to 1. If the LVDUE bit is 1 at this time, the LVDUF bit in LVDSR is set to 1 and an IRQ0 interrupt request is simultaneously generated. If the power supply voltage (Vcc) falls below the Vreset1 (Typ. = 2.3 V) voltage, this LSI enters low voltage detection reset operation (when LVDRE = 1). Vint (U) Vint (D) Vcc Vreset1 VSS LVDINT LVDDE LVDDF LVDUE LVDUF IRQ0 interrupt generated IRQ0 interrupt generated Figure 17.5 Operational Timing of LVDI Circuit Rev. 3.00 Sep. 14, 2006 Page 294 of 408 REJ09B0105-0300 Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits (3) Low Voltage Detection Interrupt (LVDI) Circuit (When Voltages Input via ExtU and ExtD Pins are used for Detection) Figure 17.6 shows the timing of the LVDI circuit. The LVDI circuit is enabled after a power-on reset, however, the interrupt request is disabled. To enable the LVDI, the LVDDF and LVDUF bits in LVDSR must be cleared to 0 and the LVDDE or LVDUE bit in LVDCR must be set to 1. When using external compared voltage, write 0 to the VDDII bit in LVDCR, and wait for 50 s (tLVDON) given by a software timer until the detection circuit has settled. Then clear the LVDDF and LVDUF bits to 0 and set the LVDDE or LVDUE bit to 1. After that, the output settings of ports must be made. The initial value of the external compared voltages input on the ExtU and ExtD pins must be higher than the Vexd voltage. To cancel the LVDI, follow the procedures written in section 17.3.2 (4), Operating Procedures for Enabling/Disabling LVDR and LVDI Circuits. When the external comparison voltage of ExtD pin falls below the Vexd (D) (Typ. = 1.15 V) voltage, the LVDI clears the LVDINT signal to 0 and sets the LVDDF bit in LVDSR to 1. If the LVDDE bit is 1 at this time, an IRQ0 interrupt request is generated. In this case, the necessary data must be saved in the external EEPROM, and a transition to standby mode or subsleep mode must be made. Until this processing is completed, the power supply voltage must be higher than the lower limit of the guaranteed operating voltage. When the power-supply voltage does not fall below the Vreset1 (Typ. = 2.3 V) voltage and the input voltage of the ExtU pin rises above Vexd (Typ. = 1.15 V) voltage, the LVDI circuit sets the LVDINT signal to 1. If the LVDUE bit is 1 at this time, the LVDUF bit in LVDSR is set to 1 and an IRQ0 interrupt request is generated. If the power supply voltage falls below the Vreset1 (Typ. = 2.3 V) voltage, this LSI enters lowvoltage detection reset operation. When the voltages input on the ExtU and ExtD pins are used as the compared voltage, ensure to use the LVDR (reset detection voltage: Typ. = 2.3 V) circuit. Rev. 3.00 Sep. 14, 2006 Page 295 of 408 REJ09B0105-0300 Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits External power supply voltage ExtD input voltage (1) ExtU input voltage (2) Vexd (3) (4) Vreset1 VSS LVDINT LVDDE LVDDF LVDUE LVDUF IRQ0 interrupt generated IRQ0 interrupt generated Figure 17.6 Operational Timing of LVDI Circuit (When Compared Voltage is Input through ExtU and ExtD Pins) Rev. 3.00 Sep. 14, 2006 Page 296 of 408 REJ09B0105-0300 Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits (4) Operating Procedures for Enabling/Disabling LVDR and LVDI Circuits The low-voltage detection circuit is enabled after reset. To enable or disable the low-voltage detection circuit correctly, follow the procedure described below. Figure 17.7 shows the timing for the operation and release of the low-voltage detection circuit. 1. 2. 3. To disable the low-voltage detection circuit, clear all of the LVDRE, LVDDE, and LVDUE bits to 0. Then, clear the LVDE and BGRE bits to 0. Set the VDDII bit in LVDCR if necessary. The LVDE and BGRE bits must not be cleared to 0 at the same timing as the LVDRE, LVDDE, and LVDUE bits because incorrect operation may occur. To enable the low-voltage detection circuit, set the LVDE and BGRE bits in LVDCR to 1. When the voltages input on the ExtU and ExtD pins are used as the compared voltage, clear the LVDDII bit to 0. Wait for 50 s (tLVDON) given by a software timer until the reference voltage and the lowvoltage-detection power supply have settled. Then, clear the LVDDF and LVDUF bits in LVDSR to 0 and set the LVDRE, LVDDE, and LVDUE bits in LVDCR to 1, if necessary. LVDE BGRE VDDII LVDRE LVDDE LVDUE Longer than one instruction operation time tLVDON Figure 17.7 Timing for Enabling/Disabling of Low-Voltage Detection Circuit Rev. 3.00 Sep. 14, 2006 Page 297 of 408 REJ09B0105-0300 Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits Rev. 3.00 Sep. 14, 2006 Page 298 of 408 REJ09B0105-0300 Section 18 Power Supply Circuit Section 18 Power Supply Circuit This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the voltage of the power supply connected to the external VCC pin. As a result, the current consumed when an external power supply is used at 3.0 V or above can be held down to virtually the same low level as when used at approximately 3.0 V. If the external power supply is 3.0 V or below, the internal voltage will be practically the same as the external voltage. It is, of course, also possible to use the same level of external power supply voltage and internal power supply voltage without using the internal power supply step-down circuit. 18.1 When Using Internal Power Supply Step-Down Circuit Connect the external power supply to the VCC pin, and connect a capacitance of approximately 0.1 F between VCL and VSS, as shown in figure 18.1. The internal step-down circuit is made effective simply by adding this external circuit. In the external circuit interface, the external power supply voltage connected to VCC and the GND potential connected to VSS are the reference levels. For example, for port input/output levels, the VCC level is the reference for the high level, and the VSS level is that for the low level. The A/D converter analog power supply is not affected by the internal step-down circuit. VCC Step-down circuit Internal logic VCC = 3.0 to 5.5 V VCL Stabilization capacitance (approx. 0.1 F) Internal power supply VSS Figure 18.1 Power Supply Connection when Internal Step-Down Circuit is Used PSCKT00A_000020020200 Rev. 3.00 Sep. 14, 2006 Page 299 of 408 REJ09B0105-0300 Section 18 Power Supply Circuit 18.2 When Not Using Internal Power Supply Step-Down Circuit When the internal power supply step-down circuit is not used, connect the external power supply to the VCL pin and VCC pin, as shown in figure 18.2. The external power supply is then input directly to the internal power supply. The permissible range for the power supply voltage is 3.0 V to 3.6 V. Operation cannot be guaranteed if a voltage outside this range (less than 3.0 V or more than 3.6 V) is input. VCC Step-down circuit Internal logic VCC = 3.0 to 3.6 V VCL Internal power supply VSS Figure 18.2 Power Supply Connection when Internal Step-Down Circuit is Not Used Rev. 3.00 Sep. 14, 2006 Page 300 of 408 REJ09B0105-0300 Section 19 List of Registers Section 19 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. * * * * Register addresses (address order) Registers are listed from the lower allocation addresses. Registers are classified by functional modules. The data bus width is indicated. The number of access states is indicated. 2. * * * Register bits Bit configurations of the registers are described in the same order as the register addresses. Reserved bits are indicated by in the bit name column. When registers consist of 16 bits, bits are described from the MSB side. 3. Register states in each operating mode * Register states are described in the same order as the register addresses. * The register states described here are for the basic operating modes. If there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module. Rev. 3.00 Sep. 14, 2006 Page 301 of 408 REJ09B0105-0300 Section 19 List of Registers 19.1 Register Addresses (Address Order) The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock. Abbreviation Bit No Module Address Name Low-voltage-detection control register LVDCR 8 H'F730 Low-voltage 8 detection circuit 2 Low-voltage-detection status register LVDSR 8 H'F731 Low-voltage 8 detection circuit 2 Clock control status register CKCSR 8 H'F734 Clock oscillator 8 2 RC control register RCCR 8 H'F735 On-chip oscillator 8 2 RC trimming data protect register RCTRMDPR 8 H'F736 On-chip oscillator 8 2 RC trimming data register RCTRMDR 8 H'F737 On-chip oscillator 8 2 I2C bus control register 1 ICCR1 8 H'F748 IIC2 8 2 I2C bus control register 2 ICCR2 8 H'F749 IIC2 8 2 2 ICMR 8 H'F74A IIC2 8 2 2 ICIER 8 H'F74B IIC2 8 2 2 I C bus status register ICSR 8 H'F74C IIC2 8 2 Slave address register Register Name I C bus mode register I C bus interrupt enable register Data Bus Access Width State SAR 8 H'F74D IIC2 8 2 2 ICDRT 8 H'F74E IIC2 8 2 2 ICDRR 8 H'F74F IIC2 8 2 Timer mode register B1 TMB1 8 H'F760 Timer B1 8 2 Timer counter B1/Timer load register B1 TCB1(R)/ TLB1 (W) 8 H'F761 Timer B1 8 2 Timer mode register W TMRW 8 H'FF80 Timer W 8 2 Timer control register W TCRW 8 H'FF81 Timer W 8 2 Timer interrupt enable register W TIERW 8 H'FF82 Timer W 8 2 Timer status register W 8 H'FF83 Timer W 8 2 I C bus transmit data register I C bus receive data register TSRW Rev. 3.00 Sep. 14, 2006 Page 302 of 408 REJ09B0105-0300 Section 19 List of Registers Register Name Abbreviation Bit No Module Address Name Data Bus Access Width State Timer I/O control register 0 TIOR0 8 H'FF84 Timer W 8 Timer I/O control register 1 TIOR1 8 H'FF85 Timer W 8 Timer counter General register A TCNT GRA 16 16 H'FF86 H'FF88 Timer W Timer W 2 2 1 2 1 2 1 16* 16* General register B GRB 16 H'FF8A Timer W 16* 2 General register C GRC 16 H'FF8C Timer W 16*1 2 H'FF8E Timer W 1 16* 2 General register D GRD 16 Flash memory control register 1 FLMCR1 8 H'FF90 ROM 8 2 Flash memory control register 2 FLMCR2 8 H'FF91 ROM 8 2 Erase block register 1 EBR1 8 H'FF93 ROM 8 2 Flash memory enable register FENR 8 H'FF9B ROM 8 2 Timer control register V0 TCRV0 8 H'FFA0 Timer V 8 3 Timer control/status register V TCSRV 8 H'FFA1 Timer V 8 3 Timer constant register A TCORA 8 H'FFA2 Timer V 8 3 Timer constant register B TCORB 8 H'FFA3 Timer V 8 3 Timer counter V TCNTV 8 H'FFA4 Timer V 8 3 Timer control register V1 TCRV1 8 H'FFA5 Timer V 8 3 Serial mode register SMR 8 H'FFA8 SCI3 8 3 Bit rate register BRR 8 H'FFA9 SCI3 8 3 Serial control register 3 SCR3 8 H'FFAA SCI3 8 3 Transmit data register TDR 8 H'FFAB SCI3 8 3 Serial status register SSR 8 H'FFAC SCI3 8 3 Receive data register RDR 8 H'FFAD SCI3 8 3 Sampling mode register SPMR 8 H'FFAE SCI3 8 3 A/D data register A ADDRA 16 H'FFB0 A/D converter 8 3 A/D data register B ADDRB 16 H'FFB2 A/D converter 8 3 A/D data register C ADDRC 16 H'FFB4 A/D converter 8 3 A/D data register D ADDRD 16 H'FFB6 A/D converter 8 3 A/D control/status register ADCSR 8 H'FFB8 A/D converter 8 3 A/D control register ADCR 8 H'FFB9 A/D converter 8 3 Timer control/status register WD TCSRWD 8 H'FFC0 WDT*2 8 2 Rev. 3.00 Sep. 14, 2006 Page 303 of 408 REJ09B0105-0300 Section 19 List of Registers Register Name Abbreviation Bit No Module Address Name Data Bus Access Width State Timer counter WD TCWD 8 H'FFC1 WDT*2 8 2 2 Timer mode register WD TMWD 8 H'FFC2 WDT* 8 2 Address break control register ABRKCR 8 H'FFC8 Address break 8 2 Address break status register ABRKSR 8 H'FFC9 Address break 8 2 Break address register H BARH 8 H'FFCA Address break 8 2 Break address register L BARL 8 H'FFCB Address break 8 2 Break data register H BDRH 8 H'FFCC Address break 8 2 Break data register L BDRL 8 H'FFCD Address break 8 2 Port pull-up control register 1 PUCR1 8 H'FFD0 I/O port 8 2 Port pull-up control register 5 PUCR5 8 H'FFD1 I/O port 8 2 Port data register 1 PDR1 8 H'FFD4 I/O port 8 2 Port data register 2 PDR2 8 H'FFD5 I/O port 8 2 Port data register 5 PDR5 8 H'FFD8 I/O port 8 2 Port data register 7 PDR7 8 H'FFDA I/O port 8 2 Port data register 8 PDR8 8 H'FFDB I/O port 8 2 Port data register B PDRB 8 H'FFDD I/O port 8 2 Port data register C PDRC 8 H'FFDE I/O port 8 2 Port mode register 1 PMR1 8 H'FFE0 I/O port 8 2 Port mode register 5 PMR5 8 H'FFE1 I/O port 8 2 Port control register 1 PCR1 8 H'FFE4 I/O port 8 2 Port control register 2 PCR2 8 H'FFE5 I/O port 8 2 Port control register 5 PCR5 8 H'FFE8 I/O port 8 2 Port control register 7 PCR7 8 H'FFEA I/O port 8 2 Port control register 8 PCR8 8 H'FFEB I/O port 8 2 Port control register C PCRC 8 H'FFEE I/O port 8 2 System control register 1 SYSCR1 8 H'FFF0 Power-down 8 2 System control register 2 SYSCR2 8 H'FFF1 Power-down 8 2 Interrupt edge select register 1 IEGR1 8 H'FFF2 Interrupts 8 2 Interrupt edge select register 2 IEGR2 8 H'FFF3 Interrupts 8 2 Interrupt enable register 1 IENR1 8 H'FFF4 Interrupts 8 2 Interrupt enable register 2 IENR2 8 H'FFF5 Interrupts 8 2 Rev. 3.00 Sep. 14, 2006 Page 304 of 408 REJ09B0105-0300 Section 19 List of Registers Register Name Abbreviation Bit No Module Address Name Data Bus Access Width State Interrupt flag register 1 IRR1 8 H'FFF6 Interrupts 8 2 Interrupt flag register 2 IRR2 8 H'FFF7 Interrupts 8 2 Wake-up interrupt flag register IWPR 8 H'FFF8 Interrupts 8 2 Module standby control register 1 MSTCR1 8 H'FFF9 Power-down 8 2 Module standby control register 2 MSTCR2 8 H'FFFA Power-down 8 2 Notes: 1. Only word access can be used. 2. WDT: Watchdog timer Rev. 3.00 Sep. 14, 2006 Page 305 of 408 REJ09B0105-0300 Section 19 List of Registers 19.2 Register Bits Register bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit registers are shown as 2 lines. Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 1 Bit 0 Module Name LVDCR LVDE BGRE VDDII -- LVDSEL LVDRE LVDDE LVDUE LVDC LVDSR -- -- -- CKCSR PMRC1 PMRC0 -- -- -- LVDDF OSCSEL CKSWIE CKSWIF -- RCCR RCSTP -- -- -- RCPSC1 RCPSC0 On-chip oscillator -- -- -- Bit 2 -- LVDUF CKSTA FSEL VCLSEL RCTRMDPR WRI PRWE LOCKDW TRMDRWE RCTRMDR TRMD7 TRMD6 TRMD5 TRMD4 TRMD3 TRMD2 TRMD1 TRMD0 ICCR1 ICE RCVD MST TRS CKS3 CKS2 CKS1 CKS0 ICCR2 BBSY SCP SDAO SDAOP SCLO -- IICRST -- ICMR MLS WAIT -- -- BCWP BC2 BC1 BC0 ACKBR -- ICIER TIE TEIE RIE NAKIE STIE ACKE ICSR TDRE TEND RDRF NACKF STOP AL/OVE AAS ADZ SAR SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 FS ICDRT ICDRT7 ICDRT6 ICDRT5 ICDRT4 ICDRT3 ICDRT2 ICDRT1 ICDRT0 ICDRR ICDRR7 ICDRR6 ICDRR5 ICDRR4 ICDRR3 ICDRR2 ICDRR1 ICDRR0 TMB1 TMB17 -- -- -- -- TMB12 TMB11 TMB10 TCB1 (R)/ TLB1 (W) BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 TMRW CTS -- BUFEB BUFEA -- PWMD PWMC PWMB TCRW CCLR CKS2 CKS1 CKS0 TOD TOC TOB TOA TIERW OVIE -- -- -- IMIED IMIEC IMIEB IMIEA SVA0 OVF -- -- -- IMFD IMFC IMFB IMFA TIOR0 -- IOB2 IOB1 IOB0 -- IOA2 IOA1 IOA0 TIOR1 -- IOD2 IOD1 IOD0 -- IOC2 IOC1 IOC0 TCNT TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 GRB TCNT8 TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 GRA15 GRA14 GRA13 GRA12 GRA11 GRA10 GRA9 GRA8 GRA7 GRA6 GRA5 GRA4 GRA3 GRA2 GRA1 GRA0 GRB15 GRB14 GRB13 GRB12 GRB11 GRB10 GRB9 GRB8 GRB7 GRB6 GRB5 GRB4 GRB3 GRB2 GRB1 GRB0 Rev. 3.00 Sep. 14, 2006 Page 306 of 408 REJ09B0105-0300 IIC2 ACKBT TSRW GRA Clock oscillator Timer B1 Timer W Section 19 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name GRC GRC15 GRC14 GRC13 GRC12 GRC11 GRC10 GRC9 GRC8 Timer W GRC7 GRC6 GRC5 GRC4 GRC3 GRC2 GRC1 GRC0 GRD15 GRD14 GRD13 GRD12 GRD11 GRD10 GRD9 GRD8 GRD GRD7 GRD6 GRD5 GRD4 GRD3 GRD2 GRD1 GRD0 FLMCR1 -- SWE ESU PSU EV PV E P FLMCR2 FLER -- -- -- -- -- -- -- EBR1 -- -- EB5 EB4 EB3 EB2 EB1 EB0 FENR FLSHE -- -- -- -- -- -- -- TCRV0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TCSRV CMFB CMFA OVF -- OS3 OS2 OS1 OS0 TCORA TCORA7 TCORA6 TCORA5 TCORA4 TCORA3 TCORA2 TCORA1 TCORA0 ROM Timer V TCORB TCORB7 TCORB6 TCORB5 TCORB4 TCORB3 TCORB2 TCORB1 TCORB0 TCNTV TCNTV7 TCNTV6 TCNTV5 TCNTV4 TCNTV3 TCNTV2 TCNTV1 TCNTV0 TCRV1 -- -- -- TVEG1 TVEG0 TRGE -- ICKS0 SMR COM CHR PE PM STOP MP CKS1 CKS0 BRR BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0 SCR3 TIE RIE TE RE MPIE TEIE CKE1 CKE0 SCI3 TDR TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 SSR TDRE RDRF OER FER PER TEND MPBR MPBT RDR1 RDR RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 SPMR -- -- -- -- -- STDSPM -- -- ADDRA AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- -- -- -- -- -- ADDRB ADDRC ADDRD RDR0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- -- -- -- -- -- AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- -- -- -- -- -- A/D converter AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- -- -- -- -- -- ADCSR ADF ADIE ADST SCAN CKS CH2 CH1 CH0 ADCR TRGE -- -- -- -- -- -- -- TCSRWD B6WI TCWE B4WI TCSRWE B2WI WDON B0WI WRST TCWD TCWD7 TCWD6 TCWD5 TCWD4 TCWD3 TCWD2 TCWD1 TCWD0 TMWD -- -- -- -- CKS3 CKS2 CKS1 CKS0 WDT* Rev. 3.00 Sep. 14, 2006 Page 307 of 408 REJ09B0105-0300 Section 19 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ABRKCR RTINTE CSEL1 CSEL0 ACMP2 ACMP1 ACMP0 DCMP1 DCMP0 ABRKSR ABIF ABIE -- -- -- -- -- -- BARH BARH7 BARH6 BARH5 BARH4 BARH3 BARH2 BARH1 BARH0 BARL BARL7 BARL6 BARL5 BARL4 BARL3 BARL2 BARL1 BARL0 BDRH BDRH7 BDRH6 BDRH5 BDRH4 BDRH3 BDRH2 BDRH1 BDRH0 BDRL BDRL7 BDRL6 BDRL5 BDRL4 BDRL3 PUCR1 PUCR17 -- -- PUCR14 -- PUCR5 -- -- PUCR55 -- -- -- -- -- PDR1 P17 -- -- -- -- -- -- PDR2 -- -- -- -- -- P22 P21 P20 PDR5 P57 P56 P55 -- -- -- -- -- PDR7 -- P76 P75 P74 -- -- -- -- PDR8 -- -- -- P84 P83 P82 P81 P80 P14 BDRL2 BDRL1 BDRL0 -- -- -- PDRB -- -- -- -- PB3 PB2 PB1 PB0 PDRC -- -- -- -- -- -- PC1 PC0 PMR1 IRQ3 -- -- IRQ0 -- -- TXD -- PMR5 -- -- WKP5 -- -- -- -- -- PCR1 PCR17 -- -- PCR14 -- -- -- -- PCR2 -- -- -- -- -- PCR22 PCR21 PCR20 PCR5 PCR57 PCR56 PCR55 -- -- -- -- -- PCR7 -- PCR76 PCR75 PCR74 -- -- -- -- PCR8 -- -- -- PCR84 PCR83 PCR82 PCR81 PCR80 PCRC -- -- -- -- -- -- PCRC1 PCRC0 SYSCR1 SSBY STS2 STS1 STS0 -- -- -- -- SYSCR2 SMSEL -- DTON MA2 MA1 MA0 -- -- IEGR1 -- -- -- -- IEG3 -- -- IEG0 IEGR2 -- -- WPEG5 -- -- -- -- -- IENR1 IENDT -- IENWP -- IEN3 -- -- IEN0 IENR2 -- -- IENTB1 -- -- -- -- -- IRR1 IRRDT -- -- -- IRRI3 -- -- IRRI0 IRR2 -- -- IRRTB1 -- -- -- -- -- IWPR -- -- -- -- MSTTV -- -- -- -- IWPF5 -- -- MSTCR1 -- MSTIIC MSTS3 MSTAD MSTWD MSTTW MSTCR2 -- -- -- MSTTB1 -- Note: * WDT:Watchdog timer Rev. 3.00 Sep. 14, 2006 Page 308 of 408 REJ09B0105-0300 -- Module Name Address break I/O port Power-down Interrupts Power-down Section 19 List of Registers 19.3 Register States in Each Operating Mode Register Name Reset Active Sleep Subsleep Standby Module LVDC LVDCR Initialized -- -- -- -- LVDSR Initialized -- -- -- -- CKCSR Initialized -- -- -- -- Clock oscillator RCCR Initialized -- -- -- -- On-chip oscillation RCTRMDPR Initialized -- -- -- -- RCTRMDR Initialized -- -- -- -- ICCR1 Initialized -- -- -- -- ICCR2 Initialized -- -- -- -- ICMR Initialized -- -- -- -- ICIER Initialized -- -- -- -- ICSR Initialized -- -- -- -- SAR Initialized -- -- -- -- ICDRT Initialized -- -- -- -- ICDRR Initialized -- -- -- -- TMB1 Initialized -- -- -- -- TCB1/TLB1 Initialized -- -- -- -- TMRW Initialized -- -- -- -- TCRW Initialized -- -- -- -- TIERW Initialized -- -- -- -- TSRW Initialized -- -- -- -- TIOR0 Initialized -- -- -- -- TIOR1 Initialized -- -- -- -- IIC2 Timer B1 Timer W TCNT Initialized -- -- -- -- GRA Initialized -- -- -- -- GRB Initialized -- -- -- -- GRC Initialized -- -- -- -- GRD Initialized -- -- -- -- FLMCR1 Initialized -- -- Initialized Initialized FLMCR2 Initialized -- -- Initialized Initialized EBR1 Initialized -- -- Initialized Initialized FENR Initialized -- -- Initialized Initialized TCRV0 Initialized -- -- Initialized Initialized ROM Timer V Rev. 3.00 Sep. 14, 2006 Page 309 of 408 REJ09B0105-0300 Section 19 List of Registers Register Name Reset Active Sleep Subsleep Standby Module TCSRV Initialized -- -- Initialized Initialized Timer V TCORA Initialized -- -- Initialized Initialized TCORB Initialized -- -- Initialized Initialized TCNTV Initialized -- -- Initialized Initialized TCRV1 Initialized -- -- Initialized Initialized SMR Initialized -- -- Initialized Initialized BRR Initialized -- -- Initialized Initialized SCR3 Initialized -- -- Initialized Initialized TDR Initialized -- -- Initialized Initialized SSR Initialized -- -- Initialized Initialized RDR Initialized -- -- Initialized Initialized SPMR Initialized -- -- Initialized Initialized ADDRA Initialized -- -- Initialized Initialized ADDRB Initialized -- -- Initialized Initialized ADDRC Initialized -- -- Initialized Initialized ADDRD Initialized -- -- Initialized Initialized ADCSR Initialized -- -- Initialized Initialized ADCR Initialized -- -- Initialized Initialized TCSRWD Initialized -- -- -- -- TCWD Initialized -- -- -- -- TMWD Initialized -- -- -- -- ABRKCR Initialized -- -- -- -- ABRKSR Initialized -- -- -- -- BARH Initialized -- -- -- -- BARL Initialized -- -- -- -- BDRH Initialized -- -- -- -- BDRL Initialized -- -- -- -- PUCR1 Initialized -- -- -- -- PUCR5 Initialized -- -- -- -- PDR1 Initialized -- -- -- -- PDR2 Initialized -- -- -- -- PDR5 Initialized -- -- -- -- PDR7 Initialized -- -- -- -- PDR8 Initialized -- -- -- -- PDRB Initialized -- -- -- -- Rev. 3.00 Sep. 14, 2006 Page 310 of 408 REJ09B0105-0300 SCI3 A/D converter WDT* Address Break I/O port Section 19 List of Registers Register Name Reset Active Sleep Subsleep Standby Module PDRC Initialized -- -- -- -- I/O port PMR1 Initialized -- -- -- -- PMR5 Initialized -- -- -- -- PCR1 Initialized -- -- -- -- PCR2 Initialized -- -- -- -- PCR5 Initialized -- -- -- -- PCR7 Initialized -- -- -- -- PCR8 Initialized -- -- -- -- PCRC Initialized -- -- -- -- SYSCR1 Initialized -- -- -- -- SYSCR2 Initialized -- -- -- -- IEGR1 Initialized -- -- -- -- IEGR2 Initialized -- -- -- -- IENR1 Initialized -- -- -- -- IENR2 Initialized -- -- -- -- IRR1 Initialized -- -- -- -- IRR2 Initialized -- -- -- -- IWPR Initialized -- -- -- -- MSTCR1 Initialized -- -- -- -- MSTCR2 Initialized -- -- -- -- Note: Power-down Interrupts Power-down is not initialized * WDT: Watchdog timer Rev. 3.00 Sep. 14, 2006 Page 311 of 408 REJ09B0105-0300 Section 19 List of Registers Rev. 3.00 Sep. 14, 2006 Page 312 of 408 REJ09B0105-0300 Section 20 Electrical Characteristics Section 20 Electrical Characteristics 20.1 Absolute Maximum Ratings Table 20.1 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage VCC -0.3 to +7.0 V * Analog power supply voltage AVCC -0.3 to +7.0 V Input voltage VIN Ports other than port B Port B -0.3 to VCC +0.3 V -0.3 to AVCC +0.3 V Operating temperature Topr -20 to +75 C Storage temperature Tstg -55 to +125 C Note: * Permanent damage may result if maximum ratings are exceeded. Normal operation should be under the conditions specified in Electrical Characteristics. Exceeding these values can result in incorrect operation and reduced reliability. Rev. 3.00 Sep. 14, 2006 Page 313 of 408 REJ09B0105-0300 Section 20 Electrical Characteristics 20.2 Electrical Characteristics (F-ZTATTM Version) 20.2.1 Power Supply Voltage and Operating Ranges 1. Supply voltage and external oscillation frequency range osc(MHz) 12.0 2.0 3.0 5.5 Vcc(V) AVcc = 3.0 to 5.5 V * Active mode * Sleep mode 2. Power supply voltage and operating frequency range osc(MHz) (kHz) 12.0 1500 2.0 31.25 3.0 5.5 AVcc = 3.0 to 5.5 V * Active mode * Sleep mode (When MA2 = 0 in SYSCR2) Rev. 3.00 Sep. 14, 2006 Page 314 of 408 REJ09B0105-0300 Vcc(V) 3.0 5.5 Vcc(V) AVcc = 3.0 to 5.5 V * Active mode * Sleep mode (When MA2 = 1 in SYSCR2) Section 20 Electrical Characteristics 3. Analog power supply voltage and A/D converter accuracy guarantee range osc(MHz) 12.0 2.0 3.0 5.5 AVcc(V) Vcc = 3.0 to 5.5 V * Active mode * Sleep mode Rev. 3.00 Sep. 14, 2006 Page 315 of 408 REJ09B0105-0300 Section 20 Electrical Characteristics 20.2.2 DC Characteristics Table 20.2 DC Characteristics (1) VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C unless otherwise indicated. Item Symbol Input high VIH voltage Applicable Pins Test Condition RES, NMI, WKP5, VCC = 4.0 V to 5.5 V IRQ0, IRQ3, ADTRG, TMRIV, TMCIV, FTCI, FTIOA to FTIOD, SCK3, TRGV RXD, SCL, SDA, VCC = 4.0 V to 5.5 V P17, P14, P22 to P20, P57 to P55, P76 to P74, P84 to P80, PC1, PC0 PB3 to PB0 AVCC = 4.0 V to 5.5 V OSC1 Values Min. Typ. Max. Unit VCC x 0.8 -- VCC + 0.3 V VCC x 0.9 -- VCC + 0.3 V VCC x 0.7 -- VCC + 0.3 V VCC x 0.8 -- VCC + 0.3 V AVCC x 0.7 -- AVCC = 3.0 V to 5.5 V AVCC x 0.8 -- AVCC + 0.3 V VCC = 4.0 V to 5.5 V VCC - 0.5 VCC + 0.3 V VCC + 0.3 V -- VCC - 0.3 Input low voltage VIL RES, NMI, WKP5, VCC = 4.0 V to 5.5 V IRQ0, IRQ3, ADTRG, TMRIV, TMCIV, FTCI, FTIOA to FTIOD, SCK3, TRGV -0.3 -- VCC x 0.2 V -0.3 -- VCC x 0.1 V RXD, SCL, SDA, P17, P14, P22 to P20, P57 to P55, P76 to P74, P84 to P80, PC1, PC0 -0.3 -- VCC x 0.3 V -0.3 -- VCC x 0.2 V PB3 to PB0 OSC1 VCC = 4.0 V to 5.5 V AVCC = 4.0 V to 5.5 V -0.3 -- AVCC x 0.3 V AVCC = 3.0 V to 5.5 V -0.3 -- AVCC x 0.2 VCC = 4.0 V to 5.5 V -0.3 -- 0.5 V -0.3 -- 0.3 V Rev. 3.00 Sep. 14, 2006 Page 316 of 408 REJ09B0105-0300 AVCC + 0.3 V Notes Section 20 Electrical Characteristics Item Symbol Output high voltage VOH Applicable Pins P17, P14, P22 to P20, P55, P76 to P74, P84 to P80, PC1, PC0 P56, P57 Values Test Condition Min. VCC = 4.0 V to 5.5 V Typ. Max. Unit VCC - 1.0 -- -- V -IOH = 0.1 mA VCC - 0.5 -- -- V VCC = 4.0 V to 5.5 V VCC - 2.5 -- -- V VCC - 2.2 -- -- V -- -- 0.6 V IOL = 0.4 mA -- -- 0.4 V VCC = 4.0 V to 5.5 V -- -- 1.5 V -- -- 1.0 V -- -- 0.4 V IOL = 0.4 mA -- -- 0.4 V VCC = 4.0 V to 5.5 V -- -- 0.6 V Notes -IOH = 4 mA -IOH = 0.1 mA VCC = 3.0 V to 4.0 V -IOH = 0.1 mA Output low VOL voltage P17, P14, P22 to P20, P57 to P55, P76 to P74, PC1, PC0 P84 to P80 VCC = 4.0 V to 5.5 V IOL = 1.6 mA IOL = 20.0 mA VCC = 4.0 V to 5.5 V IOL = 10.0 mA VCC = 4.0 V to 5.5 V IOL = 1.6 mA SCL, SDA IOL = 6.0 mA IOL = 3.0 mA Input/ output leakage current | IIL | -- -- 0.4 V VIN = 0.5 V to OSC1, NMI, WKP5, (VCC - 0.5 V) IRQ0, IRQ3, ADTRG, TRGV, TMRIV, TMCIV, FTCI, FTIOA to FTIOD, RXD, SCK3, SCL, SDA -- -- 1.0 A P17, P14, P22 to P20, P57 to P55, P76 to P74, P84 to P80, PC1, PC0 VIN = 0.5 V to (VCC - 0.5 V) -- -- 1.0 A PB3 to PB0 VIN = 0.5 V to (AVCC - 0.5 V) -- -- 1.0 A Rev. 3.00 Sep. 14, 2006 Page 317 of 408 REJ09B0105-0300 Section 20 Electrical Characteristics Item Symbol Applicable Pins Pull-up MOS current -Ip P17, P14, P55 Input capacitance Cin Test Condition Values Min. Typ. Max. Unit VCC = 5.0 V, VIN = 0.0 V 50.0 -- 300.0 A VCC = 3.0 V, VIN = 0.0 V -- 60.0 -- A All input pins except power supply pins f = 1 MHz, VIN = 0.0 V, Ta = 25C -- -- 15.0 pF Active IOPE1 mode current consumption VCC Active mode 1 VCC = 5.0 V, fOSC = 12 MHz -- 12.0 18.0 mA * Active mode 1 VCC = 3.0 V, fOSC = 12 MHz -- 9.6 -- mA Reference value* IOPE2 VCC Active mode 2 VCC = 5.0 V, fOSC = 12 MHz -- 2.0 2.5 mA * Active mode 2 VCC = 3.0 V, fOSC = 12 MHz -- 1.5 -- mA Reference value* Sleep mode 1 VCC = 5.0 V, fOSC = 12 MHz -- 7.2 12.0 mA * Sleep mode 1 VCC = 3.0 V, fOSC = 12 MHz -- 6.0 -- mA Reference value* Sleep mode 2 VCC = 5.0 V, fOSC = 12 MHz -- 1.8 2.2 mA * Sleep mode 2 VCC = 3.0 V, fOSC = 12 MHz -- 1.4 -- mA Reference value* Sleep ISLEEP1 mode current consumption VCC ISLEEP2 VCC Notes Reference value Subsleep ISUBSP mode current consumption VCC VCC = 5.0 V LVDE = 0, BGRE = 0 -- -- 5.0 A * ISTBY Standby mode current consumption VCC LVDE = 0, BGRE = 0 -- -- 5.0 A * Rev. 3.00 Sep. 14, 2006 Page 318 of 408 REJ09B0105-0300 Section 20 Electrical Characteristics Item Symbol RAM data VRAM retaining voltage Note: * Applicable Pins Test Condition VCC Values Min. Typ. Max. Unit 2.0 -- -- V Notes Pin states during current consumption measurement are given below (excluding current in the pull-up MOS transistors and output buffers). Mode RES Pin Active mode 1 VCC Oscillator Pins Operates VCC VCC System clock: Crystal or ceramic resonator, and on-chip oscillator VCC -- VCC Only timers operate VCC CPU and timers both stop Only timers operate (/64) Sleep mode 2 Subsleep mode Standby mode Other Pins Operates (/64) Active mode 2 Sleep mode 1 Internal State Rev. 3.00 Sep. 14, 2006 Page 319 of 408 REJ09B0105-0300 Section 20 Electrical Characteristics Table 20.2 DC Characteristics (2) VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise indicated. Item Application Symbol Pins Allowable output low IOL current (per pin) Allowable output low IOL current (total) Allowable output high I -IOH I current (per pin) Values Typ. Max. Unit VCC = 4.0 V to 5.5 V -- Output pins except P84 to P80, SCL, and SDA -- 2.0 mA P84 to P80 -- -- 20.0 mA Output pins except P84 to P80, SCL, and SDA -- -- 0.5 mA P84 to P80 -- -- 10.0 mA Min. SCL, SDA -- -- 6.0 mA VCC = 4.0 V to 5.5 V -- Output pins except P84 to P80, SCL, and SDA -- 40.0 mA P84 to P80, SCL, and SDA -- -- 80.0 mA Output pins except P84 to P80, SCL, and SDA -- -- 20.0 mA P84 to P80, SCL, and SDA -- -- 40.0 mA Output pins except P56, P57 VCC = 4.0 V to 5.5 V -- -- 4.0 mA -- -- 0.2 mA P56, P57 VCC = 4.0 V to 5.5 V -- -- 2.0 mA Allowable output high I -IOH I All output pins current (total) Rev. 3.00 Sep. 14, 2006 Page 320 of 408 REJ09B0105-0300 Test Condition -- -- 0.2 mA VCC = 4.0 V to 5.5 V -- -- 40.0 mA -- -- 8.0 mA Section 20 Electrical Characteristics 20.2.3 AC Characteristics Table 20.3 AC Characteristics VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified. Applicable Symbol Pins Item System clock fOSC oscillation frequency System clock () cycle tcyc time OSC1, OSC2 Instruction cycle time Test Condition Values Reference Min. Typ. Max. Unit Figure 2.0 -- 12.0 MHz 1 -- 64 tOSC -- -- 32.0 s 2 -- -- tcyc 1 * Figure 20.1 Oscillation stabilization trc time (crystal resonator) OSC1, OSC2 -- -- 10.0 ms Oscillation stabilization trc time (ceramic resonator) OSC1, OSC2 -- -- 5.0 ms External clock high width tCPH OSC1 35.0 -- -- ns External clock low width tCPL OSC1 35.0 -- -- ns External clock rise time tCPr OSC1 -- -- 15.0 ns External clock fall time tCPf OSC1 -- -- 15.0 ns RES pin low width* tREL RES 2500 -- -- ns Figure 20.2 NMI pin high width tIHNMI NMI 1500 -- -- ns Figure 20.3 NMI pin low width tILNMI NMI 1500 -- -- ns Input pin high width tIH IRQ0 , IRQ3, WKP5, TMCIV, TMRIV, TRGV, ADTRG, FTCI, FTIOA to FTIOD 2 -- -- tcyc Input pin low width tIL IRQ0, IRQ3, WKP5, TMCIV, TMRIV, TRGV, ADTRG, FTCI, FTIOA to FTIOD 2 -- -- tcyc 4 Figure 20.1 Figure 20.3 Rev. 3.00 Sep. 14, 2006 Page 321 of 408 REJ09B0105-0300 Section 20 Electrical Characteristics Item Applicable Symbol Pins On-chip oscillator fRC 2 oscillation frequency * Test Condition VCC = 5.0 V Ta = 25C FSEL = 0, VCLSEL = 0 Values Reference Typ. Max. Unit Figure Min. 3 7.92* 8.0 VCC = 4.0 V to 5.5 V 7.76 FSEL = 0, VCLSEL = 0 3 VCC = 4.0 V to 5.5 V 9.6* FSEL = 1, VCLSEL = 0 8.0 3 8.08* MHz 8.24 MHz 3 10.0 10.4* MHz Notes: 1. Determined by MA2 to MA0 in system control register 2 (SYSCR2). 2. For the oscillation frequency of the masked ROM version, refer to the electrical characteristics specified separately. 3. The values are for reference. 4. Except when power-on reset circuit is used. Rev. 3.00 Sep. 14, 2006 Page 322 of 408 REJ09B0105-0300 Section 20 Electrical Characteristics Table 20.4 I2C Bus Interface Timing VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated. Item Applicable Test Symbol Pins Condition Min. SCL input cycle time tSCL SCL input high pulse width tSCLH SCL input low pulse width tSCLL Values Max. Reference Unit Figure 12tcyc + 600 ns 3tcyc + 300 ns 5tcyc + 300 ns SCL and SDA input fall tSf time 300 ns SCL and SDA input spike pulse removal time tSP 1tcyc ns SDA input bus-free time tBUF 5tcyc ns Start condition input hold time tSTAH 3tcyc ns Retransmission start condition input setup time tSTAS 3tcyc ns Setup time for stop condition input tSTOS 3tcyc ns Data input setup time tSDAS 1tcyc+ 20 ns Data input hold time tSDAH 0 ns Capacitive load of SCL and SDA cb 0 400 pF SCL and SDA output fall time tSf 250 ns 300 ns VCC = 4.0 to 5.5 V Typ. Figure 20.4 Rev. 3.00 Sep. 14, 2006 Page 323 of 408 REJ09B0105-0300 Section 20 Electrical Characteristics Table 20.5 Serial Interface (SCI3) Timing VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified. Item Input clock cycle Asynchronous Symbol Applicable Pins tscyc SCK3 Clocked synchronous Test Condition Values Min. Typ. Max. Unit 4 -- -- tcyc 6 -- -- tcyc Input clock pulse width tSCKW SCK3 0.4 -- 0.6 tscyc Transmit data delay time (clocked synchronous) tTXD TXD -- -- 1 tcyc Receive data setup time (clocked synchronous) tRXS RXD 83.3 -- -- ns Receive data hold time (clocked synchronous) tRXH RXD 83.3 -- -- ns Rev. 3.00 Sep. 14, 2006 Page 324 of 408 REJ09B0105-0300 Reference Figure Figure 20.5 Figure 20.6 Section 20 Electrical Characteristics 20.2.4 A/D Converter Characteristics Table 20.6 A/D Converter Characteristics VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified. Values Item Symbol Applicable Test Pins Condition Analog power supply voltage AVCC AVCC 3.0 VCC 5.5 Analog input voltage AVIN AN3 to AN0 VSS - 0.3 -- AVCC + V 0.3 Analog power supply current AIOPE AVCC -- 2.0 mA AISTOP1 AVCC -- 50 -- A * Reference value AISTOP2 AVCC -- -- 5.0 A * Analog input capacitance CAIN AN3 to AN0 -- -- 30.0 pF Allowable signal source impedance AN3 to AN0 -- -- 5.0 k 10 10 10 bit -- -- tcyc -- 7.5 LSB Resolution (data length) Conversion time (single mode) Nonlinearity error Min. Typ. Max. Unit Notes V * AVCC = 5.0 V -- fOSC = 12 MHz RAIN AVCC = 3.0 V 134 to 5.5 V -- Offset error -- -- 7.5 LSB Full-scale error -- -- 7.5 LSB Quantization error -- -- 0.5 LSB Absolute accuracy -- -- 8.0 LSB AVCC = 4.0 V 70 to 5.5 V -- -- tcyc -- -- 7.5 LSB Conversion time (single mode) Nonlinearity error 1 Offset error -- -- 7.5 LSB Full-scale error -- -- 7.5 LSB Quantization error -- -- 0.5 LSB Absolute accuracy -- -- 8.0 LSB 2 3 Rev. 3.00 Sep. 14, 2006 Page 325 of 408 REJ09B0105-0300 Section 20 Electrical Characteristics Item Symbol Applicable Pins Conversion time (single mode) Test Condition Values Min. AVCC = 4.0 V 134 to 5.5 V Typ. Max. Unit -- -- tcyc Nonlinearity error -- -- 3.5 LSB Offset error -- -- 3.5 LSB Full-scale error -- -- 3.5 LSB Quantization error -- -- 0.5 LSB Absolute accuracy -- -- 4.0 LSB Notes Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle. 3. AISTOP2 is the current at reset and in standby and subsleep modes while the A/D converter is idle. 20.2.5 Watchdog Timer Characteristics Table 20.7 Watchdog Timer Characteristics VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified. Item Symbol Internal oscillator overflow time tOVF Note: * Applicable Pins Test Condition Values Min. Typ. Max. Unit Notes 0.2 0.4 -- s * Shows the time to count from 0 to 255, at which point an internal reset is generated, when the internal oscillator is selected. Rev. 3.00 Sep. 14, 2006 Page 326 of 408 REJ09B0105-0300 Section 20 Electrical Characteristics 20.2.6 Power-Supply-Voltage Detection Circuit Characteristics Table 20.8 Power-Supply-Voltage Detection Circuit Characteristics VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated. Values Item Symbol Test Condition Min. Typ. Max. Unit Power-supply falling detection voltage Vint(D) LVDSEL = 0 3.3 3.7 4.3 V Power-supply rising detection voltage Vint(U) LVDSEL = 0 3.6 4.0 4.5 V Reset detection voltage 1*1 Vreset1 LVDSEL = 0 2.0 2.3 2.7 V Reset detection voltage 2*2 Vreset2 LVDSEL = 1 3.0 3.6 4.2 V Lower-limit voltage of LVDR 3 operation* VLVDRmin 1.0 -- -- V LVD stabilization time tLVDON 50 -- -- s -- 350 A Current consumption in standby ISTBY mode LVDE = 1, BGRE = 1 Vcc = 5.0 V Notes: 1. This voltage should be used when the falling and rising voltage detection function is used. 2. Select the low-voltage reset 2 when only the low-voltage detection reset is used. 3. When the power-supply voltage (Vcc) falls below VLVDRmin = 1.0 V and then rises, a reset may not occur. Therefore sufficient evaluation is required. 20.2.7 LVDI External Voltage Detection Circuit Characteristics Table 20.9 LVDI External Voltage Detection Circuit Characteristics Vcc = 4.5 to 5.5 V, AVcc = 3.0 to 5.5 V, VSS= 0.0 V, Ta = -20 to +75C Item Symbol ExtD/ExtU input detection voltage ExtD/ExtU input voltage range Test Condition Values Min. Typ. Max. Unit Vexd 0.85 1.15 1.45 V VextD/U VextD > VextU -0.3 -- Lower voltage, V either AVcc + 0.3 or Vcc + 0.3 Rev. 3.00 Sep. 14, 2006 Page 327 of 408 REJ09B0105-0300 Section 20 Electrical Characteristics 20.2.8 Power-On Reset Characteristics Table 20.10 Power-On Reset Circuit Characteristics VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated. Test Condition Values Item Symbol Min. Typ. Max. Unit Pull-up resistance of RES pin RRES 100 150 -- k Power-on reset start voltage* Vpor -- -- 100 mV Note: * The power-supply voltage (Vcc) must fall below Vpor = 100 mV and then rise after charge of the RES pin is removed completely. In order to remove charge of the RES pin, it is recommended that the diode be placed in the Vcc side. If the power-supply voltage (Vcc) rises from the point over 100 mV, a power-on reset may not occur. Rev. 3.00 Sep. 14, 2006 Page 328 of 408 REJ09B0105-0300 Section 20 Electrical Characteristics 20.2.9 Flash Memory Characteristics Table 20.11 Flash Memory Characteristics VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified. Test Condition Values Item Symbol Min. Typ. Max. Unit Programming time (per 128 bytes)*1*2*4 tP -- 7 200 ms tE -- 100 1200 ms 1 3 6 Erase time (per block) * * * Reprogramming count NWEC 1000 10000 -- Times Programming Wait time after SWE 1 bit setting* x 1 -- -- s Wait time after PSU bit setting*1 y 50 -- -- s Wait time after P bit 1 4 setting* * z1 1n6 28 30 32 s z2 7 n 1000 198 200 202 s z3 Additionalprogramming 8 10 12 s Wait time after P bit clear*1 5 -- -- s Wait time after PSU 1 bit clear* 5 -- -- s Wait time after PV 1 bit setting* 4 -- -- s Wait time after dummy write*1 2 -- -- s Wait time after PV 1 bit clear* 2 -- -- s Wait time after SWE 1 bit clear* 100 -- -- s -- -- 1000 Times Maximum N programming count*1*4*5 Rev. 3.00 Sep. 14, 2006 Page 329 of 408 REJ09B0105-0300 Section 20 Electrical Characteristics Min. Typ. Max. Unit Wait time after SWE 1 bit setting* x 1 -- -- s Wait time after ESU bit setting*1 y 100 -- -- s Wait time after E bit 1 6 setting* * z 10 -- 100 ms Wait time after E bit 1 clear* 10 -- -- s Wait time after ESU bit clear*1 10 -- -- s Wait time after EV 1 bit setting* 20 -- -- s Wait time after 1 dummy write* 2 -- -- s Wait time after EV bit clear*1 4 -- -- s Wait time after SWE 1 bit clear* 100 -- -- s Maximum erase count*1*6*7 N -- -- 120 Times Item Erase Values Test Symbol Condition Notes: 1. Make the time settings in accordance with the program/erase algorithms. 2. The programming time for 64 bytes. (Indicates the total time for which the P bit in flash memory control register 1 (FLMCR1) is set. The program-verify time is not included.) 3. The time required to erase one block. (Indicates the time for which the E bit in flash memory control register 1 (FLMCR1) is set. The erase-verify time is not included.) 4. Programming time maximum value (tP (max.)) = wait time after P bit setting (z) x maximum programming count (N) 5. Set the maximum programming count (N) according to the actual set values of z1, z2, and z3, so that it does not exceed the programming time maximum value (tP (max.)). The wait time after P bit setting (z1, z2) should be changed as follows according to the value of the programming count (n). Programming count (n) 1n6 z1 = 30 s 7 n 1000 z2 = 200 s 6. Erase time maximum value (tE (max.)) = wait time after E bit setting (z) x maximum erase count (N) 7. Set the maximum erase count (N) according to the actual set value of (z), so that it does not exceed the erase time maximum value (tE (max.)). Rev. 3.00 Sep. 14, 2006 Page 330 of 408 REJ09B0105-0300 Section 20 Electrical Characteristics 20.3 Electrical Characteristics (Masked ROM Version) 20.3.1 Power Supply Voltage and Operating Ranges 1. Supply voltage and external oscillation frequency range osc(MHz) 12.0 2.0 2.7 5.5 Vcc(V) AVcc = 2.7 to 5.5 V * Active mode * Sleep mode 2. Power supply voltage and operating frequency range osc(MHz) (kHz) 12.0 1500 2.0 31.25 2.7 5.5 Vcc(V) AVcc = 2.7 to 5.5 V * Active mode * Sleep mode (When MA2 = 0 in SYSCR2) 2.7 5.5 Vcc(V) AVcc = 2.7 to 5.5 V * Active mode * Sleep mode (When MA2 = 1 in SYSCR2) Rev. 3.00 Sep. 14, 2006 Page 331 of 408 REJ09B0105-0300 Section 20 Electrical Characteristics 3. Analog power supply voltage and A/D converter accuracy guarantee range osc(MHz) 12.0 2.0 2.7 Vcc = 2.7 to 5.5 V * Active mode * Sleep mode Rev. 3.00 Sep. 14, 2006 Page 332 of 408 REJ09B0105-0300 5.5 AVcc(V) Section 20 Electrical Characteristics 20.3.2 DC Characteristics Table 20.12 DC Characteristics (1) VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C unless otherwise indicated. Item Applicable Symbol Pins Input high VIH voltage Test Condition RES, NMI, WKP5, VCC = 4.0 V to 5.5 V IRQ0, IRQ3, ADTRG, TMRIV, TMCIV, FTCI, FTIOA to FTIOD, SCK3, TRGV RXD, SCL, SDA, VCC = 4.0 V to 5.5 V P17, P14, P22 to P20, P57 to P55, P76 to P74, P84 to P80, PC1, PC0 PB3 to PB0 AVCC = 4.0 V to 5.5 V OSC1 Values Min. Typ. Max. Unit VCC x 0.8 -- VCC + 0.3 V VCC x 0.9 -- VCC + 0.3 V VCC x 0.7 -- VCC + 0.3 V VCC x 0.8 -- VCC + 0.3 V AVCC x 0.7 -- AVCC x 0.8 -- AVCC + 0.3 V VCC = 4.0 V to 5.5 V VCC - 0.5 VCC + 0.3 V VCC + 0.3 V VCC - 0.3 Input low voltage VIL AVCC + 0.3 V AVCC = 2.7 V to 5.5 V -- RES, NMI, WKP5, VCC = 4.0 V to 5.5 V IRQ0, IRQ3, ADTRG, TMRIV, TMCIV, FTCI, FTIOA to FTIOD, SCK3, TRGV -0.3 -- VCC x 0.2 V -0.3 -- VCC x 0.1 V RXD, SCL, SDA, P17, P14, P22 to P20, P57 to P55, P76 to P74, P84 to P80, PC1, PC0 -0.3 -- VCC x 0.3 V -0.3 -- VCC x 0.2 V PB3 to PB0 OSC1 VCC = 4.0 V to 5.5 V Notes AVCC = 4.0 V to 5.5 V -0.3 -- AVCC x 0.3 V AVCC = 2.7 V to 5.5 V -0.3 -- AVCC x 0.2 VCC = 4.0 V to 5.5 V -0.3 -- 0.5 V -0.3 -- 0.3 V Rev. 3.00 Sep. 14, 2006 Page 333 of 408 REJ09B0105-0300 Section 20 Electrical Characteristics Item Symbol Output high voltage VOH Applicable Pins P17, P14, P22 to P20, P55, P76 to P74, P84 to P80, PC1, PC0 P56, P57 Test Condition Min. Typ. Max. Unit VCC - 1.0 -- -- V -IOH = 0.1 mA VCC - 0.5 -- -- V VCC = 4.0 V to 5.5 V VCC - 2.5 -- -- V VCC - 2.2 -- -- V -- -- 0.6 V IOL = 0.4 mA -- -- 0.4 V VCC = 4.0 V to 5.5 V -- -- 1.5 V -- -- 1.0 V -- -- 0.4 V IOL = 0.4 mA -- -- 0.4 V VCC = 4.0 V to 5.5 V -- -- 0.6 V VCC = 4.0 V to 5.5 V -IOH = 4 mA -IOH = 0.1 mA VCC = 2.7 V to 4.0 V -IOH = 0.1 mA Output low VOL voltage P17, P14, P22 to P20, P57 to P55, P76 to P74, PC1, PC0 P84 to P80 Values VCC = 4.0 V to 5.5 V IOL = 1.6 mA IOL = 20.0 mA VCC = 4.0 V to 5.5 V IOL = 10.0 mA VCC = 4.0 V to 5.5 V IOL = 1.6 mA SCL, SDA IOL = 6.0 mA IOL = 3.0 mA Input/ output leakage current | IIL | -- -- 0.4 V VIN = 0.5 V to OSC1, NMI, WKP5, (VCC - 0.5 V) IRQ0, IRQ3, ADTRG, TRGV, TMRIV, TMCIV, FTCI, FTIOA to FTIOD, RXD, SCK3, SCL, SDA -- -- 1.0 A P17, P14, P22 to P20, P57 to P55, P76 to P74, P84 to P80, PC1, PC0 VIN = 0.5 V to (VCC - 0.5 V) -- -- 1.0 A PB3 to PB0 VIN = 0.5 V to (AVCC - 0.5 V) -- -- 1.0 A Rev. 3.00 Sep. 14, 2006 Page 334 of 408 REJ09B0105-0300 Notes Section 20 Electrical Characteristics Item Symbol Applicable Pins Pull-up MOS current -Ip P17, P14, P55 Input capacitance Cin Test Condition Values Min. Typ. VCC = 5.0 V, VIN = 0.0 V 50.0 -- 300.0 A VCC = 2.7 V, VIN = 0.0 V -- 60.0 -- A All input pins except power supply pins f = 1 MHz, VIN = 0.0 V, Ta = 25C -- -- 15.0 pF Active IOPE1 mode current consumption VCC Active mode 1 VCC = 5.0 V, fOSC = 12 MHz -- 12.0 18.0 mA * Active mode 1 VCC = 2.7 V, fOSC = 12 MHz -- 9.6 -- mA Reference value* IOPE2 VCC Active mode 2 VCC = 5.0 V, fOSC = 12 MHz -- 2.0 2.5 mA * Active mode 2 VCC = 2.7 V, fOSC = 12 MHz -- 1.5 -- mA Reference value* Sleep mode 1 VCC = 5.0 V, fOSC = 12 MHz -- 7.2 12.0 mA * Sleep mode 1 VCC = 2.7 V, fOSC = 12 MHz -- 6.0 -- mA Reference value* Sleep mode 2 VCC = 5.0 V, fOSC = 12 MHz -- 1.8 2.2 mA * Sleep mode 2 VCC = 2.7 V, fOSC = 12 MHz -- 1.4 -- mA Reference value* Sleep ISLEEP1 mode current consumption VCC ISLEEP2 VCC Max. Unit Notes Reference value Subsleep ISUBSP mode current consumption VCC VCC = 5.0 V LVDE = 0, BGRE = 0 -- -- 5.0 A * ISTBY Standby mode current consumption VCC LVDE = 0, BGRE = 0 -- -- 5.0 A * Rev. 3.00 Sep. 14, 2006 Page 335 of 408 REJ09B0105-0300 Section 20 Electrical Characteristics Item Symbol RAM data VRAM retaining voltage Note: * Applicable Pins Test Condition VCC Values Min. Typ. 2.0 -- Max. -- Unit Notes V Pin states during current consumption measurement are given below (excluding current in the pull-up MOS transistors and output buffers). Mode RES Pin Internal State Other Pins Oscillator Pins Active mode 1 VCC Operates VCC VCC System clock: Crystal or ceramic resonator, and on-chip oscillator VCC -- Operates (/64) Active mode 2 Sleep mode 1 VCC Only timers operate VCC CPU and timers both stop Only timers operate (/64) Sleep mode 2 Subsleep mode Standby mode Rev. 3.00 Sep. 14, 2006 Page 336 of 408 REJ09B0105-0300 Section 20 Electrical Characteristics Table 20.12 DC Characteristics (2) VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise indicated. Item Symbol Allowable output low IOL current (per pin) Test Condition Output pins except P84 to P80, SCL, and SDA VCC = 4.0 V to 5.5 V -- Allowable output high I -IOH I current (per pin) Allowable output high I -IOH I current (total) Min. Typ. Max. Unit -- 2.0 mA P84 to P80 -- -- 20.0 mA Output pins except P84 to P80, SCL, and SDA -- -- 0.5 mA P84 to P80 -- -- 10.0 mA SCL, SDA Allowable output low IOL current (total) Values Application Pins -- -- 6.0 mA VCC = 4.0 V to 5.5 V -- -- 40.0 mA P84 to P80, SCL, and SDA -- -- 80.0 mA Output pins except P84 to P80, SCL, and SDA -- -- 20.0 mA P84 to P80, SCL, and SDA -- -- 40.0 mA Output pins except P56, P57 VCC = 4.0 V to 5.5 V -- -- 4.0 mA -- -- 0.2 mA P56, P57 VCC = 4.0 V to 5.5 V -- -- 2.0 mA -- -- 0.2 mA All output pins VCC = 4.0 V to 5.5 V -- -- 40.0 mA -- -- 8.0 mA Output pins except P84 to P80, SCL, and SDA Rev. 3.00 Sep. 14, 2006 Page 337 of 408 REJ09B0105-0300 Section 20 Electrical Characteristics 20.3.3 AC Characteristics Table 20.13 AC Characteristics VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified. Item Symbol Applicable Pins System clock oscillation frequency System clock () cycle time fOSC OSC1, OSC2 Test Condition tcyc Instruction cycle time Values Min. Typ. Max. Unit 2.0 -- 12.0 MHz 1 -- 64 tOSC -- -- 32.0 s 2 -- -- tcyc Reference Figure * Figure 20.1 trc OSC1, OSC2 -- -- 10.0 ms trc Oscillation stabilization time (ceramic resonator) OSC1, OSC2 -- -- 5.0 ms External clock high tCPH width OSC1 35.0 -- -- ns External clock low width tCPL OSC1 35.0 -- -- ns External clock rise time tCPr OSC1 -- -- 15.0 ns External clock fall time tCPf OSC1 -- -- 15.0 ns RES pin low width* tREL RES 2500 -- -- ns Figure 20.2 NMI pin high width tIHNMI NMI 1500 -- -- ns Figure 20.3 NMI pin low width NMI 1500 -- -- ns IRQ0 , IRQ3, WKP5,TMCIV, TMRIV, TRGV, ADTRG, FTCI, FTIOA to FTIOD 2 -- -- tcyc Oscillation stabilization time (crystal resonator) tILNMI Input pin high width tIH Note: * Except when power-on reset circuit is used. Rev. 3.00 Sep. 14, 2006 Page 338 of 408 REJ09B0105-0300 Figure 20.1 Figure 20.3 Section 20 Electrical Characteristics Item Symbol Input pin low width tIL On-chip oscillator oscillation frequency Notes: * fRC Applicable Pins Test Condition Values Min. Typ. Max. Unit Reference Figure 2 -- -- tcyc Figure 20.3 VCC = 4.0 V to 5.5 V FSEL = 0, VCLSEL = 0 7.6 8.0 8.4 MHz VCC = 4.0 V to 5.5 V FSEL = 1, VCLSEL = 0 9.4 10.0 10.6 MHz IRQ0, IRQ3, WKP5, TMCIV, TMRIV, TRGV, ADTRG, FTCI, FTIOA to FTIOD Determined by MA2 to MA0 in system control register 2 (SYSCR2). Rev. 3.00 Sep. 14, 2006 Page 339 of 408 REJ09B0105-0300 Section 20 Electrical Characteristics Table 20.14 I2C Bus Interface Timing VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated. Applicable Pins Test Condition Min. Values Reference Max. Unit Figure Item Symbol SCL input cycle time tSCL 12tcyc + 600 ns SCL input high pulse width tSCLH 3tcyc + 300 ns SCL input low pulse width tSCLL 5tcyc + 300 ns SCL and SDA input fall time tSf 300 ns SCL and SDA input spike pulse removal time tSP 1tcyc ns SDA input bus-free time tBUF 5tcyc ns Start condition input hold time tSTAH 3tcyc ns Retransmission start condition input setup time tSTAS 3tcyc ns Setup time for stop condition input tSTOS 3tcyc ns Data input setup time tSDAS 1tcyc+ 20 ns Data input hold time tSDAH 0 ns Capacitive load of SCL and SDA cb 0 400 pF SCL and SDA output fall time tSf VCC = 4.0 to 5.5 V 250 ns 300 ns Rev. 3.00 Sep. 14, 2006 Page 340 of 408 REJ09B0105-0300 Typ. Figure 20.4 Section 20 Electrical Characteristics Table 20.15 Serial Interface (SCI3) Timing VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified. Item Input clock cycle Asynchronous Symbol Applicable Pins tscyc SCK3 Clocked synchronous Test Condition Values Min. Typ. Max. Unit 4 -- -- tcyc 6 -- -- tcyc Input clock pulse width tSCKW SCK3 0.4 -- 0.6 tscyc Transmit data delay time (clocked synchronous) tTXD TXD -- -- 1 tcyc Receive data setup time (clocked synchronous)s tRXS RXD 83.3 -- -- ns Receive data hold time (clocked synchronous) tRXH RXD 83.3 -- -- ns Reference Figure Figure 20.5 Figure 20.6 Rev. 3.00 Sep. 14, 2006 Page 341 of 408 REJ09B0105-0300 Section 20 Electrical Characteristics 20.3.4 A/D Converter Characteristics Table 20.16 A/D Converter Characteristics VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified. Item Applicable Symbol Pins Test Condition Values Min. Typ. Max. Unit Notes VCC V * Analog power supply voltage AVCC AVCC 2.7 Analog input voltage AVIN AN3 to AN0 VSS - 0.3 -- AVCC + 0.3 V Analog power supply current AIOPE AVCC -- -- 2.0 mA AVCC = 5.0 V 5.5 1 fOSC = 12 MHz 2 AISTOP1 AVCC -- 50 -- A * Reference value AISTOP2 AVCC -- -- 5.0 A * Analog input capacitance CAIN AN3 to AN0 -- -- 30.0 pF Allowable signal source impedance RAIN AN3 to AN0 -- -- 5.0 k 10 10 10 bit 134 -- -- tcyc -- -- 7.5 LSB Resolution (data length) Conversion time (single mode) AVCC = 2.7 V to 5.5 V Nonlinearity error Offset error -- -- 7.5 LSB Full-scale error -- -- 7.5 LSB Quantization error -- -- 0.5 LSB Absolute accuracy -- -- 8.0 LSB 70 -- -- tcyc -- -- 7.5 LSB Conversion time (single mode) Nonlinearity error AVCC = 4.0 V to 5.5 V Offset error -- -- 7.5 LSB Full-scale error -- -- 7.5 LSB Quantization error -- -- 0.5 LSB Absolute accuracy -- -- 8.0 LSB Rev. 3.00 Sep. 14, 2006 Page 342 of 408 REJ09B0105-0300 3 Section 20 Electrical Characteristics Item Symbol Applicable Test Pins Condition Conversion time (single mode) AVCC = 4.0 V to 5.5 V Values Min. Typ. Max. Unit 134 -- -- tcyc Nonlinearity error -- -- 3.5 LSB Offset error -- -- 3.5 LSB Full-scale error -- -- 3.5 LSB Quantization error -- -- 0.5 LSB Absolute accuracy -- -- 4.0 LSB Notes Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle. 3. AISTOP2 is the current at reset and in standby and subsleep modes while the A/D converter is idle. 20.3.5 Watchdog Timer Characteristics Table 20.17 Watchdog Timer Characteristics VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified. Item Symbol Internal oscillator overflow time tOVF Note: * Applicable Test Condition Min. Pins 0.2 Values Typ. Max. Unit Notes 0.4 -- s * Shows the time to count from 0 to 255, at which point an internal reset is generated, when the internal oscillator is selected. Rev. 3.00 Sep. 14, 2006 Page 343 of 408 REJ09B0105-0300 Section 20 Electrical Characteristics 20.3.6 Power-Supply-Voltage Detection Circuit Characteristics Table 20.18 Power-Supply-Voltage Detection Circuit Characteristics VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated. Values Item Symbol Test Condition Typ. Max. Unit Power-supply falling detection voltage Vint(D) LVDSEL = 0 3.3 3.7 4.3 V Power-supply rising detection voltage Vint(U) LVDSEL = 0 3.6 4.0 4.5 V Reset detection voltage 1*1 Vreset1 LVDSEL = 0 2.0 2.3 2.7 V Reset detection voltage 2*2 Vreset2 LVDSEL = 1 3.0 3.6 4.2 V Lower-limit voltage of LVDR 3 operation* VLVDRmin 1.0 -- -- V LVD stabilization time tLVDON 50 -- -- s Current consumption in standby mode ISTBY -- 350 A LVDE = 1, BGRE = 1 Vcc = 5.0 V Min. Notes: 1. This voltage should be used when the falling and rising voltage detection function is used. 2. Select the low-voltage reset 2 when only the low-voltage detection reset is used. 3. When the power-supply voltage (Vcc) falls below VLVDRmin = 1.0 V and then rises, a reset may not occur. Therefore sufficient evaluation is required. 20.3.7 LVDI External Voltage Detection Circuit Characteristics Table 20.19 LVDI External Voltage Detection Circuit Characteristics Vcc = 4.5 to 5.5 V, AVcc = 2.7 to 5.5 V, VSS= 0.0 V, Ta = -20 to +75C Item Symbol ExtD/ExtU input detection voltage ExtD/ExtU input voltage range Test Condition Min. Typ. Max. Unit Vexd 0.85 1.15 1.45 V VextD/U VextD > VextU -0.3 -- Lower voltage, V either AVcc + 0.3 or Vcc + 0.3 Rev. 3.00 Sep. 14, 2006 Page 344 of 408 REJ09B0105-0300 Values Section 20 Electrical Characteristics 20.3.8 Power-On Reset Characteristics Table 20.20 Power-On Reset Circuit Characteristics VSS = 0.0 V, Ta = -20 to +75C, unless otherwise indicated. Test Condition Values Item Symbol Min. Typ. Max. Unit Pull-up resistance of RES pin RRES 100 150 -- k Power-on reset start voltage* Vpor -- -- 100 mV Note: * The power-supply voltage (Vcc) must fall below Vpor = 100 mV and then rise after charge of the RES pin is removed completely. In order to remove charge of the RES pin, it is recommended that the diode be placed in the Vcc side. If the power-supply voltage (Vcc) rises from the point over 100 mV, a power-on reset may not occur. Rev. 3.00 Sep. 14, 2006 Page 345 of 408 REJ09B0105-0300 Section 20 Electrical Characteristics 20.4 Operation Timing tOSC VIH VIL OSC1 tCPH tCPL tCPr tCPf Figure 20.1 System Clock Input Timing Vcc Vcc x 0.7 OSC1 tREL RES VIL VIL tREL Figure 20.2 RES Low Width Timing IRQ0, IRQ3 WKP5, NMI ADTRG FTCI, FTIOA VIH VIL FTIOB, FTIOC tIL tIH FTIOD TMCIV, TMRIV TRGV Figure 20.3 Input Timing Rev. 3.00 Sep. 14, 2006 Page 346 of 408 REJ09B0105-0300 Section 20 Electrical Characteristics VIH SDA VIL tBUF tSTAH tSCLH tSTAS tSP tSTOS SCL P* S* tSf Sr* tSCLL P* tSDAS tSr tSCL tSDAH Note: * S, P, and Sr represent the following: S: Start condition P: Stop comdition Sr: Retransmission start condition Figure 20.4 I2C Bus Interface Input/Output Timing tSCKW SCK3 tscyc Figure 20.5 SCK3 Input Clock Timing Rev. 3.00 Sep. 14, 2006 Page 347 of 408 REJ09B0105-0300 Section 20 Electrical Characteristics t scyc VIH or VOH * VIL or VOL * SCK3 t TXD VOH* TXD (transmit data) VOL * t RXS t RXH RXD (receive data) Note: * Output timing reference levels Output high: VOH = 2.0 V Output low: VOL= 0.8 V Load conditions are shown in figure 20.7. Figure 20.6 SCI3 Input/Output Timing in Clocked Synchronous Mode 20.5 Output Load Condition VCC 2.4 k LSI output pin 30 pF 12 k Figure 20.7 Output Load Circuit Rev. 3.00 Sep. 14, 2006 Page 348 of 408 REJ09B0105-0300 Appendix Appendix A Instruction Set A.1 Instruction List * Operand Notation Symbol Description Rd General (destination*) register Rs General (source*) register Rn General register* ERd General destination register (address register or 32-bit register) ERs General source register (address register or 32-bit register) ERn General register (32-bit register) (EAd) Destination operand (EAs) Source operand PC Program counter SP Stack pointer CCR Condition-code register N N (negative) flag in CCR Z Z (zero) flag in CCR V V (overflow) flag in CCR C C (carry) flag in CCR disp Displacement Transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right + Addition of the operands on both sides - Subtraction of the operand on the right from the operand on the left x Multiplication of the operands on both sides / Division of the operand on the left by the operand on the right Logical AND of the operands on both sides Logical OR of the operands on both sides Logical exclusive OR of the operands on both sides NOT (logical complement) Rev. 3.00 Sep. 14, 2006 Page 349 of 408 REJ09B0105-0300 Appendix Symbol Description ( ), < > Contents of operand Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers (R0 to R7 and E0 to E7). Symbol Description * Condition Code Notation Changed according to execution result * Undetermined (no guaranteed value) 0 Cleared to 0 1 Set to 1 -- Not affected by execution of the instruction Varies depending on conditions, described in notes Rev. 3.00 Sep. 14, 2006 Page 350 of 408 REJ09B0105-0300 Appendix Table A.1 Instruction Set * Data transfer instructions Condition Code MOV.B @(d:16, ERs), Rd B 4 @(d:16, ERs) Rd8 -- -- MOV.B @(d:24, ERs), Rd B 8 @(d:24, ERs) Rd8 -- -- MOV.B @ERs+, Rd B @ERs Rd8 ERs32+1 ERs32 -- -- MOV.B @aa:8, Rd B 2 @aa:8 Rd8 -- -- MOV.B @aa:16, Rd B 4 @aa:16 Rd8 -- -- MOV.B @aa:24, Rd B 6 @aa:24 Rd8 -- -- MOV.B Rs, @ERd B Rs8 @ERd -- -- MOV.B Rs, @(d:16, ERd) B 4 Rs8 @(d:16, ERd) -- -- MOV.B Rs, @(d:24, ERd) B 8 Rs8 @(d:24, ERd) -- -- MOV.B Rs, @-ERd B ERd32-1 ERd32 Rs8 @ERd -- -- MOV.B Rs, @aa:8 B 2 Rs8 @aa:8 -- -- MOV.B Rs, @aa:16 B 4 Rs8 @aa:16 -- -- MOV.B Rs, @aa:24 B 6 Rs8 @aa:24 -- -- MOV.W #xx:16, Rd W 4 #xx:16 Rd16 -- -- MOV.W Rs, Rd W Rs16 Rd16 -- -- MOV.W @ERs, Rd W @ERs Rd16 -- -- 2 2 2 2 2 2 MOV.W @(d:16, ERs), Rd W 4 @(d:16, ERs) Rd16 -- -- MOV.W @(d:24, ERs), Rd W 8 @(d:24, ERs) Rd16 -- -- @ERs Rd16 ERs32+2 @ERd32 -- -- MOV.W @ERs+, Rd W MOV.W @aa:16, Rd W 4 @aa:16 Rd16 -- -- MOV.W @aa:24, Rd W 6 @aa:24 Rd16 -- -- MOV.W Rs, @ERd W Rs16 @ERd -- -- 2 2 MOV.W Rs, @(d:16, ERd) W 4 Rs16 @(d:16, ERd) -- -- MOV.W Rs, @(d:24, ERd) W 8 Rs16 @(d:24, ERd) -- -- 0 -- 0 -- 0 -- Advanced -- -- B @ERs Rd8 MOV.B @ERs, Rd 2 -- -- B C 0 -- Rs8 Rd8 MOV.B Rs, Rd V Z I N -- -- H #xx:8 Rd8 Normal -- @@aa @(d, PC) Operation @aa @-ERn/@ERn+ @(d, ERn) @ERn 2 Rn B No. of States*1 MOV MOV.B #xx:8, Rd #xx Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) 2 0 -- 2 0 -- 4 0 -- 6 0 -- 10 0 -- 6 4 0 -- 6 0 -- 8 0 -- 4 0 -- 6 0 -- 10 0 -- 6 4 0 -- 6 0 -- 8 0 -- 4 0 -- 2 0 -- 4 0 -- 6 0 -- 10 0 -- 6 6 0 -- 8 0 -- 4 0 -- 6 0 -- 10 Rev. 3.00 Sep. 14, 2006 Page 351 of 408 REJ09B0105-0300 Appendix No. of States*1 Condition Code -- -- @(d:24, ERs) ERd32 -- -- @ERs ERd32 ERs32+4 ERs32 -- -- 6 @aa:16 ERd32 -- -- 8 @aa:24 ERd32 -- -- ERs32 @ERd -- -- ERs32 @(d:16, ERd) -- -- ERs32 @(d:24, ERd) -- -- ERd32-4 ERd32 ERs32 @ERd -- -- 6 ERs32 @aa:16 -- -- 8 ERs32 @aa:24 -- -- 0 -- 0 -- POP POP.W Rn W 2 @SP Rn16 SP+2 SP -- -- POP.L ERn L 4 @SP ERn32 SP+4 SP -- -- 0 -- PUSH PUSH.W Rn W 2 SP-2 SP Rn16 @SP -- -- 0 -- PUSH.L ERn L 4 SP-4 SP ERn32 @SP -- -- 0 -- MOVFPE @aa:16, Rd B W MOV.W Rs, @aa:16 W MOV.W Rs, @aa:24 W MOV.L #xx:32, Rd L MOV.L ERs, ERd L MOV.L @ERs, ERd L MOV.L @(d:16, ERs), ERd L 6 MOV.L @(d:24, ERs), ERd L 10 MOV.L @ERs+, ERd L MOV.L @aa:16, ERd L MOV.L @aa:24, ERd L MOV.L ERs, @ERd L MOV.L ERs, @(d:16, ERd) L 6 MOV.L ERs, @(d:24, ERd) L 10 MOV.L ERs, @-ERd L MOV.L ERs, @aa:16 L MOV.L ERs, @aa:24 L MOVFPE MOVTPE MOVTPE Rs, @aa:16 2 6 2 4 4 4 6 6 0 -- 8 0 -- 6 0 -- 2 0 -- 8 0 -- 10 0 -- 14 0 -- 10 10 0 -- 12 0 -- 8 0 -- 10 0 -- 14 0 -- 10 10 0 -- 12 0 -- 6 10 6 10 4 Cannot be used in this LSI Cannot be used in this LSI 4 Cannot be used in this LSI Cannot be used in this LSI B Rev. 3.00 Sep. 14, 2006 Page 352 of 408 REJ09B0105-0300 4 Advanced @(d:16, ERs) ERd32 -- -- @ERs ERd32 -- -- ERs32 ERd32 -- -- #xx:32 Rd32 0 -- -- -- -- -- Rs16 @aa:24 Rs16 @aa:16 6 C 4 V Z I N -- -- H ERd32-2 ERd32 Rs16 @ERd 0 -- MOV MOV.W Rs, @-ERd Normal -- @@aa @(d, PC) Operation @aa @-ERn/@ERn+ @(d, ERn) @ERn Rn #xx Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) Appendix * Arithmetic instructions No. of States*1 Condition Code Z V C -- (2) ERd32+ERs32 ERd32 -- (2) (3) Rd16+Rs16 Rd16 -- (1) ERd32+#xx:32 ERd32 2 Rd8+#xx:8 +C Rd8 -- 2 B 2 Rd8+Rs8 +C Rd8 -- ADDS ADDS.L #1, ERd L 2 ERd32+1 ERd32 -- -- -- -- -- -- 2 ADDS.L #2, ERd L 2 ERd32+2 ERd32 -- -- -- -- -- -- 2 ADDS.L #4, ERd L 2 ERd32+4 ERd32 -- -- -- -- -- -- 2 INC.B Rd B 2 Rd8+1 Rd8 -- -- INC.W #1, Rd W 2 Rd16+1 Rd16 -- -- INC.W #2, Rd W 2 Rd16+2 Rd16 -- -- INC.L #1, ERd L 2 ERd32+1 ERd32 -- -- INC.L #2, ERd L 2 ERd32+2 ERd32 -- -- DAA DAA Rd B 2 Rd8 decimal adjust Rd8 -- * SUB SUB.B Rs, Rd B 2 Rd8-Rs8 Rd8 -- SUB.W #xx:16, Rd W 4 Rd16-#xx:16 Rd16 -- (1) SUB.W Rs, Rd W Rd16-Rs16 Rd16 -- (1) SUB.L #xx:32, ERd L SUB.L ERs, ERd L W 4 ADD.W Rs, Rd W ADD.L #xx:32, ERd L ADD.L ERs, ERd L ADDX ADDX.B #xx:8, Rd ADDX.B Rs, Rd 6 2 (3) 2 6 2 -- 2 -- 2 -- 2 -- 2 -- 2 * B 2 Rd8-Rs8-C Rd8 -- SUBS SUBS.L #1, ERd L 2 ERd32-1 ERd32 -- -- -- -- -- -- 2 SUBS.L #2, ERd L 2 ERd32-2 ERd32 -- -- -- -- -- -- 2 SUBS.L #4, ERd L 2 ERd32-4 ERd32 -- -- -- -- -- -- 2 B 2 Rd8-1 Rd8 -- -- DEC.W #1, Rd W 2 Rd16-1 Rd16 -- -- DEC.W #2, Rd W 2 Rd16-2 Rd16 -- -- 2 ERd32-ERs32 ERd32 -- (2) Rd8-#xx:8-C Rd8 -- (3) (3) DEC DEC.B Rd 2 SUBX.B Rs, Rd B ERd32-#xx:32 ERd32 -- (2) 6 SUBX SUBX.B #xx:8, Rd 2 2 2 2 4 INC B 2 2 ADD.W #xx:16, Rd 2 B ADD.B Rs, Rd ADD ADD.B #xx:8, Rd -- (1) Rd16+#xx:16 Rd16 2 -- Rd8+Rs8 Rd8 -- Advanced N I Rd8+#xx:8 Rd8 Normal H -- @@aa @(d, PC) Operation @aa @-ERn/@ERn+ @(d, ERn) 2 @ERn B Rn #xx Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) 4 2 6 2 2 2 -- 2 -- 2 -- 2 Rev. 3.00 Sep. 14, 2006 Page 353 of 408 REJ09B0105-0300 Appendix No. of States*1 Condition Code Advanced V C ERd32-1 ERd32 -- -- L 2 ERd32-2 ERd32 -- -- -- 2 DAS.Rd B 2 Rd8 decimal adjust Rd8 -- * 2 DEC.L #2, ERd -- * -- 2 B 2 Rd8 x Rs8 Rd16 (unsigned multiplication) -- -- -- -- -- -- 14 W 2 Rd16 x Rs16 ERd32 (unsigned multiplication) -- -- -- -- -- -- 22 B 4 Rd8 x Rs8 Rd16 (signed multiplication) -- -- W 4 Rd16 x Rs16 ERd32 (signed multiplication) -- -- B 2 W DIVXU DIVXU. B Rs, Rd DIVXU. W Rs, ERd DIVXS DIVXS. B Rs, Rd DIVXS. W Rs, ERd CMP CMP.B #xx:8, Rd 16 -- -- 24 Rd16 / Rs8 Rd16 (RdH: remainder, RdL: quotient) (unsigned division) -- -- (6) (7) -- -- 14 2 ERd32 / Rs16 ERd32 (Ed: remainder, Rd: quotient) (unsigned division) -- -- (6) (7) -- -- 22 B 4 Rd16 / Rs8 Rd16 (RdH: remainder, RdL: quotient) (signed division) -- -- (8) (7) -- -- 16 W 4 ERd32 / Rs16 ERd32 (Ed: remainder, Rd: quotient) (signed division) -- -- (8) (7) -- -- 24 Rd8-#xx:8 -- Rd8-Rs8 -- Rd16-#xx:16 -- (1) Rd16-Rs16 -- (1) ERd32-#xx:32 -- (2) ERd32-ERs32 -- (2) B 2 CMP.B Rs, Rd B CMP.W #xx:16, Rd W 4 CMP.W Rs, Rd W CMP.L #xx:32, ERd L CMP.L ERs, ERd L 2 2 6 2 Rev. 3.00 Sep. 14, 2006 Page 354 of 408 REJ09B0105-0300 MULXS. W Rs, ERd -- -- MULXS MULXS. B Rs, Rd MULXU. W Rs, ERd MULXU MULXU. B Rs, Rd DAS I Normal Z 2 N L H DEC DEC.L #1, ERd -- @@aa @(d, PC) Operation @aa @-ERn/@ERn+ @(d, ERn) @ERn Rn #xx Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) 2 2 4 2 4 2 Appendix No. of States*1 L 0-ERd32 ERd32 2 -- EXTU EXTU.W Rd W 0 (<bits 15 to 8> of Rd16) 2 -- -- 0 L 0 (<bits 31 to 16> of ERd32) 2 -- -- 0 W (<bit 7> of Rd16) (<bits 15 to 8> of Rd16) 2 -- -- L (<bit 15> of ERd32) (<bits 31 to 16> of ERd32) 2 -- -- Advanced NEG.L ERd Normal -- 2 C W 0-Rd16 Rd16 EXTS.L ERd V 2 0 -- 2 NEG.W Rd EXTS EXTS.W Rd Z 0 -- 2 -- 0 -- 2 H 2 EXTU.L ERd N I B 0-Rd8 Rd8 NEG NEG.B Rd -- @@aa @(d, PC) Condition Code @aa @-ERn/@ERn+ @(d, ERn) @ERn Rn Operation #xx Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) 0 -- 2 2 2 Rev. 3.00 Sep. 14, 2006 Page 355 of 408 REJ09B0105-0300 Appendix * Logic instructions AND.B Rs, Rd B AND.W #xx:16, Rd W 4 AND.W Rs, Rd W AND.L #xx:32, ERd L AND.L ERs, ERd L OR.B #xx:8, Rd B OR.B Rs, Rd B OR.W #xx:16, Rd W 4 OR.W Rs, Rd W OR.L #xx:32, ERd L OR.L ERs, ERd L XOR.B #xx:8, Rd B XOR.B Rs, Rd B XOR.W #xx:16, Rd W 4 XOR.W Rs, Rd W XOR.L #xx:32, ERd L XOR.L ERs, ERd L 4 ERd32ERs32 ERd32 -- -- NOT.B Rd B 2 Rd8 Rd8 -- -- NOT.W Rd W 2 Rd16 Rd16 -- -- NOT.L ERd L 2 Rd32 Rd32 -- -- Z Rd8Rs8 Rd8 -- -- Rd16#xx:16 Rd16 -- -- Rd16Rs16 Rd16 -- -- 4 2 2 2 6 4 2 2 2 ERd32ERs32 ERd32 -- -- Rd8#xx:8 Rd8 -- -- Rd8Rs8 Rd8 -- -- Rd16#xx:16 Rd16 -- -- Rd16Rs16 Rd16 -- -- ERd32#xx:32 ERd32 -- -- ERd32ERs32 ERd32 -- -- Rd8#xx:8 Rd8 -- -- Rd8Rs8 Rd8 -- -- Rd16#xx:16 Rd16 -- -- Rd16Rs16 Rd16 -- -- ERd32#xx:32 ERd32 -- -- 6 V C Advanced I Normal -- @@aa @(d, PC) @aa N -- -- ERd32#xx:32 ERd32 -- -- 6 Rev. 3.00 Sep. 14, 2006 Page 356 of 408 REJ09B0105-0300 H Rd8#xx:8 Rd8 2 Operation NOT 2 @(d, ERn) 2 @ERn B Rn #xx XOR Condition Code Operand Size OR No. of States*1 AND.B #xx:8, Rd Mnemonic AND @-ERn/@ERn+ Addressing Mode and Instruction Length (bytes) 0 -- 2 0 -- 2 0 -- 4 0 -- 2 0 -- 6 0 -- 4 0 -- 2 0 -- 2 0 -- 4 0 -- 2 0 -- 6 0 -- 4 0 -- 2 0 -- 2 0 -- 4 0 -- 2 0 -- 6 0 -- 4 0 -- 2 0 -- 2 0 -- 2 Appendix * Shift instructions W 2 SHAL.L ERd L 2 SHAR SHAR.B Rd B 2 SHAR.W Rd W 2 SHAR.L ERd L 2 SHLL SHLL.B Rd B 2 SHLL.W Rd W 2 SHLL.L ERd L 2 SHLR SHLR.B Rd B 2 SHLR.W Rd W 2 SHLR.L ERd L 2 ROTXL ROTXL.B Rd B 2 ROTXL.W Rd W 2 ROTXL.L ERd L 2 B 2 ROTXR.W Rd W 2 ROTXR.L ERd L 2 ROTL ROTL.B Rd B 2 ROTL.W Rd W 2 ROTL.L ERd L 2 ROTR ROTR.B Rd B 2 ROTR.W Rd W 2 ROTR.L ERd L 2 ROTXR ROTXR.B Rd 0 MSB LSB V C -- -- -- -- -- -- C MSB -- -- LSB -- -- -- -- C 0 LSB MSB -- -- -- -- -- -- 0 C MSB LSB -- -- -- -- -- -- C -- -- MSB LSB -- -- -- -- C LSB MSB -- -- -- -- -- -- C -- -- MSB LSB -- -- -- -- C MSB LSB -- -- -- -- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Advanced Z Normal -- @@aa @(d, PC) @aa @-ERn/@ERn+ @(d, ERn) I C N SHAL.W Rd H -- -- 2 Condition Code Operation B No. of States*1 SHAL SHAL.B Rd @ERn Rn #xx Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 3.00 Sep. 14, 2006 Page 357 of 408 REJ09B0105-0300 Appendix * Bit manipulation instructions B BSET #xx:3, @aa:8 B BSET Rn, Rd B BSET Rn, @ERd B BSET Rn, @aa:8 B B BCLR #xx:3, @ERd B BCLR #xx:3, @aa:8 B BCLR Rn, Rd B BCLR Rn, @ERd B BCLR Rn, @aa:8 B BNOT BNOT #xx:3, Rd B BNOT #xx:3, @ERd B BNOT #xx:3, @aa:8 B BNOT Rn, Rd B BNOT Rn, @ERd B BNOT Rn, @aa:8 B BTST BTST #xx:3, Rd B BTST #xx:3, @ERd B BTST #xx:3, @aa:8 B BTST Rn, Rd B BTST Rn, @ERd B BTST Rn, @aa:8 B BLD #xx:3, Rd B 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 H N Z V C Advanced I Normal -- @@aa @(d, PC) @aa @-ERn/@ERn+ @(d, ERn) @ERn Rn 2 Rev. 3.00 Sep. 14, 2006 Page 358 of 408 REJ09B0105-0300 Condition Code Operation (#xx:3 of Rd8) 1 -- -- -- -- -- -- 2 (#xx:3 of @ERd) 1 -- -- -- -- -- -- 8 (#xx:3 of @aa:8) 1 -- -- -- -- -- -- 8 (Rn8 of Rd8) 1 -- -- -- -- -- -- 2 (Rn8 of @ERd) 1 -- -- -- -- -- -- 8 (Rn8 of @aa:8) 1 -- -- -- -- -- -- 8 (#xx:3 of Rd8) 0 -- -- -- -- -- -- 2 (#xx:3 of @ERd) 0 -- -- -- -- -- -- 8 (#xx:3 of @aa:8) 0 -- -- -- -- -- -- 8 (Rn8 of Rd8) 0 -- -- -- -- -- -- 2 (Rn8 of @ERd) 0 -- -- -- -- -- -- 8 (Rn8 of @aa:8) 0 -- -- -- -- -- -- 8 (#xx:3 of Rd8) (#xx:3 of Rd8) -- -- -- -- -- -- 2 (#xx:3 of @ERd) (#xx:3 of @ERd) -- -- -- -- -- -- 8 (#xx:3 of @aa:8) (#xx:3 of @aa:8) -- -- -- -- -- -- 8 (Rn8 of Rd8) (Rn8 of Rd8) -- -- -- -- -- -- 2 (Rn8 of @ERd) (Rn8 of @ERd) -- -- -- -- -- -- 8 (Rn8 of @aa:8) (Rn8 of @aa:8) -- -- -- -- -- -- 8 (#xx:3 of Rd8) Z -- -- -- (#xx:3 of @ERd) Z -- -- -- (#xx:3 of @aa:8) Z -- -- -- (Rn8 of @Rd8) Z -- -- -- (Rn8 of @ERd) Z -- -- -- (Rn8 of @aa:8) Z -- -- -- (#xx:3 of Rd8) C -- -- -- -- -- -- -- 2 -- -- 6 -- -- 6 -- -- 2 -- -- 6 -- -- 6 BSET #xx:3, @ERd BCLR BCLR #xx:3, Rd BLD B No. of States*1 BSET BSET #xx:3, Rd #xx Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) 2 Appendix B BLD #xx:3, @aa:8 B BILD BILD #xx:3, Rd B BILD #xx:3, @ERd B BILD #xx:3, @aa:8 B BST #xx:3, Rd B BST #xx:3, @ERd B BIST BST #xx:3, @aa:8 B BST BIST #xx:3, Rd B BIST #xx:3, @ERd B BIST #xx:3, @aa:8 B BAND BAND #xx:3, Rd B BAND #xx:3, @ERd B BIAND BAND #xx:3, @aa:8 B BOR BIAND #xx:3, Rd B BIAND #xx:3, @ERd B BIAND #xx:3, @aa:8 B BOR #xx:3, Rd B BOR #xx:3, @ERd B BOR #xx:3, @aa:8 B BIOR BIOR #xx:3, Rd B BIOR #xx:3, @ERd B BIOR #xx:3, @aa:8 B BXOR BXOR #xx:3, Rd B BXOR #xx:3, @ERd B BXOR #xx:3, @aa:8 B BIXOR BIXOR #xx:3, Rd B BIXOR #xx:3, @ERd B BIXOR #xx:3, @aa:8 B 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 H N Z V C (#xx:3 of @ERd) C -- -- -- -- -- 6 (#xx:3 of @aa:8) C -- -- -- -- -- (#xx:3 of Rd8) C -- -- -- -- -- (#xx:3 of @ERd) C -- -- -- -- -- (#xx:3 of @aa:8) C -- -- -- -- -- C (#xx:3 of Rd8) -- -- -- -- -- -- 2 C (#xx:3 of @ERd24) -- -- -- -- -- -- 8 C (#xx:3 of @aa:8) -- -- -- -- -- -- 8 C (#xx:3 of Rd8) -- -- -- -- -- -- 2 C (#xx:3 of @ERd24) -- -- -- -- -- -- 8 C (#xx:3 of @aa:8) -- -- -- -- -- -- 8 C(#xx:3 of Rd8) C -- -- -- -- -- 2 C(#xx:3 of @ERd24) C -- -- -- -- -- C(#xx:3 of @aa:8) C -- -- -- -- -- C (#xx:3 of Rd8) C -- -- -- -- -- C (#xx:3 of @ERd24) C -- -- -- -- -- C (#xx:3 of @aa:8) C -- -- -- -- -- C(#xx:3 of Rd8) C -- -- -- -- -- C(#xx:3 of @ERd24) C -- -- -- -- -- C(#xx:3 of @aa:8) C -- -- -- -- -- C (#xx:3 of Rd8) C -- -- -- -- -- C (#xx:3 of @ERd24) C -- -- -- -- -- C (#xx:3 of @aa:8) C -- -- -- -- -- C(#xx:3 of Rd8) C -- -- -- -- -- C(#xx:3 of @ERd24) C -- -- -- -- -- C(#xx:3 of @aa:8) C -- -- -- -- -- C (#xx:3 of Rd8) C -- -- -- -- -- C (#xx:3 of @ERd24) C -- -- -- -- -- 4 4 Advanced I Normal -- @@aa @(d, PC) @aa @-ERn/@ERn+ @(d, ERn) @ERn Rn Condition Code Operation BLD #xx:3, @ERd No. of States*1 BLD #xx Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) C (#xx:3 of @aa:8) C -- -- -- -- -- 6 2 6 6 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 Rev. 3.00 Sep. 14, 2006 Page 359 of 408 REJ09B0105-0300 Appendix * Branching instructions Bcc Condition Code -- 2 BRA d:16 (BT d:16) -- 4 BRN d:8 (BF d:8) -- 2 BRN d:16 (BF d:16) -- 4 BHI d:8 -- 2 BHI d:16 -- 4 BLS d:8 -- 2 BLS d:16 -- 4 BCC d:8 (BHS d:8) -- 2 BCC d:16 (BHS d:16) -- 4 BCS d:8 (BLO d:8) -- 2 BCS d:16 (BLO d:16) -- 4 BNE d:8 -- 2 BNE d:16 -- 4 BEQ d:8 -- 2 BEQ d:16 -- 4 BVC d:8 -- 2 BVC d:16 -- 4 BVS d:8 -- 2 BVS d:16 -- 4 BPL d:8 -- 2 BPL d:16 -- 4 BMI d:8 -- 2 BMI d:16 -- 4 BGE d:8 -- 2 BGE d:16 -- 4 BLT d:8 -- 2 BLT d:16 -- 4 BGT d:8 -- 2 BGT d:16 -- 4 BLE d:8 -- 2 BLE d:16 -- 4 REJ09B0105-0300 If condition Always is true then PC PC+d Never else next; CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV = 0 NV = 1 Z (NV) = 0 Z (NV) = 1 I H N Z V C Advanced Branch Condition Normal -- @@aa @(d, PC) BRA d:8 (BT d:8) Rev. 3.00 Sep. 14, 2006 Page 360 of 408 No. of States*1 Operation @aa @-ERn/@ERn+ @(d, ERn) @ERn Rn #xx Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 -- -- -- -- -- -- 4 -- -- -- -- -- -- 6 Appendix JMP BSR JSR RTS JMP @ERn -- JMP @aa:24 -- JMP @@aa:8 -- BSR d:8 -- BSR d:16 -- JSR @ERn -- JSR @aa:24 -- JSR @@aa:8 -- RTS -- No. of States*1 Condition Code H N Z V C Advanced I Normal -- @@aa @(d, PC) Operation @aa @-ERn/@ERn+ @(d, ERn) @ERn Rn #xx Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) PC ERn -- -- -- -- -- -- PC aa:24 -- -- -- -- -- -- PC @aa:8 -- -- -- -- -- -- 8 10 2 PC @-SP PC PC+d:8 -- -- -- -- -- -- 6 8 4 PC @-SP PC PC+d:16 -- -- -- -- -- -- 8 10 PC @-SP PC ERn -- -- -- -- -- -- 6 8 PC @-SP PC aa:24 -- -- -- -- -- -- 8 10 PC @-SP PC @aa:8 -- -- -- -- -- -- 8 12 2 PC @SP+ -- -- -- -- -- -- 8 10 2 4 2 2 4 2 4 6 Rev. 3.00 Sep. 14, 2006 Page 361 of 408 REJ09B0105-0300 Appendix * System control instructions No. of States*1 Condition Code Normal Advanced -- CCR @SP+ PC @SP+ 10 -- Transition to powerdown state -- -- -- -- -- -- 2 #xx:8 CCR 2 C V Z N LDC #xx:8, CCR B LDC Rs, CCR B LDC @ERs, CCR W LDC @(d:16, ERs), CCR W 6 @(d:16, ERs) CCR LDC @(d:24, ERs), CCR W 10 @(d:24, ERs) CCR LDC @ERs+, CCR W LDC @aa:16, CCR W 6 @aa:16 CCR LDC @aa:24, CCR W 8 @aa:24 CCR CCR Rd8 CCR @ERd -- -- -- -- -- -- 6 6 8 12 8 @ERs CCR ERs32+2 ERs32 10 -- -- -- -- -- -- 2 8 W 6 CCR @(d:16, ERd) -- -- -- -- -- -- 8 STC CCR, @(d:24, ERd) W 10 CCR @(d:24, ERd) -- -- -- -- -- -- 12 STC CCR, @-ERd W ERd32-2 ERd32 CCR @ERd -- -- -- -- -- -- 8 STC CCR, @aa:16 W 6 CCR @aa:16 -- -- -- -- -- -- 8 STC CCR, @aa:24 W 8 CCR @aa:24 -- -- -- -- -- -- 10 ANDC ANDC #xx:8, CCR B 2 CCR#xx:8 CCR 2 B 2 CCR#xx:8 CCR B 2 CCR#xx:8 CCR -- -- -- -- -- -- 2 ORC ORC #xx:8, CCR XORC XORC #xx:8, CCR NOP NOP 4 4 -- Rev. 3.00 Sep. 14, 2006 Page 362 of 408 REJ09B0105-0300 2 PC PC+2 STC CCR, @(d:16, ERd) 2 W B STC CCR, @ERd STC STC CCR, Rd 4 2 @ERs CCR 4 Rs8 CCR 2 2 LDC H SLEEP SLEEP @@aa RTE RTE @(d, PC) 16 @aa 1 -- -- -- -- -- 14 @ERn 2 PC @-SP CCR @-SP <vector> PC Rn -- #xx I TRAPA TRAPA #x:2 Operation -- @-ERn/@ERn+ @(d, ERn) Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) 2 2 Appendix * Block transfer instructions EEPMOV No. of States*1 H N Z V C Normal -- @@aa @(d, PC) I EEPMOV. B -- 4 if R4L 0 then repeat @R5 @R6 R5+1 R5 R6+1 R6 R4L-1 R4L until R4L=0 else next -- -- -- -- -- -- 8+ 4n*2 EEPMOV. W -- 4 if R4 0 then repeat @R5 @R6 R5+1 R5 R6+1 R6 R4-1 R4 until R4=0 else next -- -- -- -- -- -- 8+ 4n*2 Advanced Condition Code Operation @aa @-ERn/@ERn+ @(d, ERn) @ERn Rn #xx Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) Notes: 1. The number of states in cases where the instruction code and its operands are located in on-chip memory is shown here. For other cases see appendix A.3, Number of Execution States. 2. n is the value set in register R4L or R4. (1) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. (2) Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. (3) Retains its previous value when the result is zero; otherwise cleared to 0. (4) Set to 1 when the adjustment produces a carry; otherwise retains its previous value. (5) The number of states required for execution of an instruction that transfers data in synchronization with the E clock is variable. (6) Set to 1 when the divisor is negative; otherwise cleared to 0. (7) Set to 1 when the divisor is zero; otherwise cleared to 0. (8) Set to 1 when the quotient is negative; otherwise cleared to 0. Rev. 3.00 Sep. 14, 2006 Page 363 of 408 REJ09B0105-0300 REJ09B0105-0300 Rev. 3.00 Sep. 14, 2006 Page 364 of 408 MULXU 5 STC LDC 3 SUBX OR XOR AND MOV C D E F BILD BIST BLD BST TRAPA BEQ B BIAND BAND AND RTE BNE CMP BIXOR BXOR XOR BSR BCS A BIOR BOR OR RTS BCC MOV.B Table A-2 (2) LDC 7 ADDX BTST DIVXU BLS AND.B ANDC 6 9 BCLR MULXU BHI XOR.B XORC 5 ADD BNOT DIVXU BRN OR.B ORC 4 8 7 BSET BRA 6 2 1 Table A-2 (2) Table A-2 Table A-2 Table A-2 Table A-2 (2) (2) (2) (2) NOP 4 3 2 1 0 0 MOV BVS 9 A B JMP BPL BMI MOV Table A-2 Table A-2 (2) (2) Table A-2 Table A-2 (2) (2) Table A-2 Table A-2 EEPMOV (2) (2) SUB ADD Table A-2 (2) BVC 8 BSR BGE C CMP MOV Instruction when most significant bit of BH is 1. Instruction when most significant bit of BH is 0. JSR BGT SUBX ADDX E Table A-2 (3) BLT D F BLE Table A-2 (2) Table A-2 (2) Table A.2 AL 1st byte 2nd byte AH AL BH BL A.2 AH Instruction code: Appendix Operation Code Map Operation Code Map (1) MOV 7A BRA 58 MOV DAS 1F 79 SUBS 1B 1 ADD ADD BRN NOT 17 DEC ROTXR 13 1A ROTXL 12 DAA 0F SHLR ADDS 0B 11 INC 0A SHLL MOV 01 10 0 CMP CMP BHI 2 SUB SUB BLS NOT ROTXR ROTXL SHLR SHLL 3 4 OR OR BCC LDC/STC 1st byte 2nd byte AH AL BH BL XOR XOR BCS DEC EXTU INC 5 AND AND BNE 6 BEQ DEC EXTU INC 7 BVC SUB NEG 9 BVS ROTR ROTL SHAR SHAL ADDS SLEEP 8 BPL A MOV BMI NEG CMP SUB ROTR ROTL SHAR C D BGE BLT DEC EXTS INC Table A-2 Table A-2 (3) (3) ADD SHAL B BGT E BLE DEC EXTS INC Table A-2 (3) F Table A.2 BH AH AL Instruction code: Appendix Operation Code Map (2) Rev. 3.00 Sep. 14, 2006 Page 365 of 408 REJ09B0105-0300 REJ09B0105-0300 Rev. 3.00 Sep. 14, 2006 Page 366 of 408 DIVXS 3 BSET 7Faa7 * 2 BNOT BNOT BCLR BCLR Notes: 1. r is the register designation field. 2. aa is the absolute address field. BSET 7Faa6 * 2 BTST BCLR 7Eaa7 * 2 BNOT BTST BSET 7Dr07 * 1 7Eaa6 * 2 BSET 7Dr06 * 1 BTST BCLR MULXS 2 7Cr07 * 1 BNOT DIVXS 1 BTST MULXS 0 7Cr06 * 1 01F06 01D05 01C05 01406 CL BIOR BOR BIOR BOR OR 4 BIXOR BXOR BIXOR BXOR XOR 5 BIAND BAND BIAND BAND AND 6 7 BIST BILD BST BLD BIST BILD BST BLD 1st byte 2nd byte 3rd byte 4th byte AH AL BH BL CH CL DH DL 8 LDC STC 9 A LDC STC B C LDC STC D E LDC STC F Instruction when most significant bit of DH is 1. Instruction when most significant bit of DH is 0. Table A.2 AH ALBH BLCH Instruction code: Appendix Operation Code Map (3) Appendix A.3 Number of Execution States The status of execution for each instruction of the H8/300H CPU and the method of calculating the number of states required for instruction execution are shown below. Table A.4 shows the number of cycles of each type occurring in each instruction, such as instruction fetch and data read/write. Table A.3 shows the number of states required for each cycle. The total number of states required for execution of an instruction can be calculated by the following expression: Execution states = I x SI + J x SJ + K x SK + L x SL + M x SM + N x SN Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed. BSET #0, @FF00 From table A.4: I = L = 2, J = K = M = N= 0 From table A.3: SI = 2, SL = 2 Number of states required for execution = 2 x 2 + 2 x 2 = 8 When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and on-chip RAM is used for stack area. JSR @@ 30 From table A.4: I = 2, J = K = 1, L=M=N=0 From table A.3: SI = SJ = SK = 2 Number of states required for execution = 2 x 2 + 1 x 2+ 1 x 2 = 8 Rev. 3.00 Sep. 14, 2006 Page 367 of 408 REJ09B0105-0300 Appendix Table A.3 Number of Cycles in Each Instruction Access Location Execution Status (Instruction Cycle) On-Chip Memory On-Chip Peripheral Module 2 -- Instruction fetch SI Branch address read SJ Stack operation SK Byte data access SL 2 or 3* Word data access SM 2 or 3* Internal operation SN Note: * 1 Depends on which on-chip peripheral module is accessed. See section 19.1, Register Addresses (Address Order). Rev. 3.00 Sep. 14, 2006 Page 368 of 408 REJ09B0105-0300 Appendix Table A.4 Number of Cycles in Each Instruction Instruction Mnemonic Instruction Fetch I ADD ADD.B #xx:8, Rd 1 ADD.B Rs, Rd 1 ADD.W #xx:16, Rd 2 ADD.W Rs, Rd 1 ADD.L #xx:32, ERd 3 ADD.L ERs, ERd 1 ADDS ADDS #1/2/4, ERd 1 ADDX ADDX #xx:8, Rd 1 ADDX Rs, Rd 1 Branch Stack Addr. Read Operation J K Byte Data Access L AND.B #xx:8, Rd 1 AND.B Rs, Rd 1 AND.W #xx:16, Rd 2 AND.W Rs, Rd 1 AND.L #xx:32, ERd 3 AND.L ERs, ERd 2 ANDC ANDC #xx:8, CCR 1 BAND BAND #xx:3, Rd 1 BAND #xx:3, @ERd 2 1 BAND #xx:3, @aa:8 2 1 BRA d:8 (BT d:8) 2 BRN d:8 (BF d:8) 2 BHI d:8 2 BLS d:8 2 BCC d:8 (BHS d:8) 2 BCS d:8 (BLO d:8) 2 BNE d:8 2 BEQ d:8 2 BVC d:8 2 BVS d:8 2 BPL d:8 2 BMI d:8 2 BGE d:8 2 AND Bcc Word Data Access M Internal Operation N Rev. 3.00 Sep. 14, 2006 Page 369 of 408 REJ09B0105-0300 Appendix Instruction Mnemonic Instruction Fetch I Bcc BLT d:8 2 BGT d:8 2 BLE d:8 2 BRA d:16(BT d:16) 2 2 BRN d:16(BF d:16) 2 2 BHI d:16 2 2 BLS d:16 2 2 BCC d:16(BHS d:16) 2 2 BCS d:16(BLO d:16) 2 2 BNE d:16 2 2 BEQ d:16 2 2 BVC d:16 2 2 BVS d:16 2 2 BPL d:16 2 2 BMI d:16 2 2 BGE d:16 2 2 BLT d:16 2 2 BGT d:16 2 2 BLE d:16 2 2 BCLR #xx:3, Rd 1 BCLR #xx:3, @ERd 2 2 BCLR #xx:3, @aa:8 2 2 BCLR Rn, Rd 1 BCLR Rn, @ERd 2 2 BCLR Rn, @aa:8 2 2 BIAND #xx:3, Rd 1 BIAND #xx:3, @ERd 2 1 1 BCLR BIAND BILD Branch Stack Addr. Read Operation J K Byte Data Access L BIAND #xx:3, @aa:8 2 BILD #xx:3, Rd 1 BILD #xx:3, @ERd 2 1 BILD #xx:3, @aa:8 2 1 Rev. 3.00 Sep. 14, 2006 Page 370 of 408 REJ09B0105-0300 Word Data Access M Internal Operation N Appendix Instruction Mnemonic Instruction Fetch I BIOR BIOR #xx:8, Rd 1 BIOR #xx:8, @ERd 2 1 BIOR #xx:8, @aa:8 2 1 BIST #xx:3, Rd 1 BIST #xx:3, @ERd 2 2 BIST #xx:3, @aa:8 2 2 BIXOR #xx:3, Rd 1 BIXOR #xx:3, @ERd 2 1 BIXOR #xx:3, @aa:8 2 1 BIST BIXOR BLD BNOT BOR BSET BSR BST Branch Stack Addr. Read Operation J K Byte Data Access L BLD #xx:3, Rd 1 BLD #xx:3, @ERd 2 1 BLD #xx:3, @aa:8 2 1 BNOT #xx:3, Rd 1 BNOT #xx:3, @ERd 2 2 BNOT #xx:3, @aa:8 2 2 BNOT Rn, Rd 1 BNOT Rn, @ERd 2 2 BNOT Rn, @aa:8 2 2 BOR #xx:3, Rd 1 BOR #xx:3, @ERd 2 1 BOR #xx:3, @aa:8 2 1 BSET #xx:3, Rd 1 BSET #xx:3, @ERd 2 2 BSET #xx:3, @aa:8 2 2 BSET Rn, Rd 1 BSET Rn, @ERd 2 BSET Rn, @aa:8 2 BSR d:8 2 1 BSR d:16 2 1 BST #xx:3, Rd 1 BST #xx:3, @ERd 2 2 BST #xx:3, @aa:8 2 2 Word Data Access M Internal Operation N 2 2 2 Rev. 3.00 Sep. 14, 2006 Page 371 of 408 REJ09B0105-0300 Appendix Instruction Mnemonic Instruction Fetch I BTST BXOR CMP BTST #xx:3, Rd 1 2 1 BTST #xx:3, @aa:8 2 1 BTST Rn, Rd 1 BTST Rn, @ERd 2 1 BTST Rn, @aa:8 2 1 BXOR #xx:3, Rd 1 BXOR #xx:3, @ERd 2 1 BXOR #xx:3, @aa:8 2 1 CMP.B #xx:8, Rd 1 1 CMP.W #xx:16, Rd 2 CMP.W Rs, Rd 1 CMP.L #xx:32, ERd 3 CMP.L ERs, ERd 1 DAA DAA Rd 1 DAS DAS Rd 1 DUVXS DIVXU EEPMOV EXTS EXTU Byte Data Access L BTST #xx:3, @ERd CMP.B Rs, Rd DEC Branch Stack Addr. Read Operation J K Word Data Access M Internal Operation N DEC.B Rd 1 DEC.W #1/2, Rd 1 DEC.L #1/2, ERd 1 DIVXS.B Rs, Rd 2 12 DIVXS.W Rs, ERd 2 20 DIVXU.B Rs, Rd 1 12 DIVXU.W Rs, ERd 1 20 EEPMOV.B 2 2n+2*1 EEPMOV.W 2 2n+2*1 EXTS.W Rd 1 EXTS.L ERd 1 EXTU.W Rd 1 EXTU.L ERd 1 Rev. 3.00 Sep. 14, 2006 Page 372 of 408 REJ09B0105-0300 Appendix Instruction Mnemonic Instruction Fetch I INC JMP JSR LDC MOV Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M INC.B Rd 1 INC.W #1/2, Rd 1 INC.L #1/2, ERd 1 JMP @ERn 2 JMP @aa:24 2 JMP @@aa:8 2 JSR @ERn 2 JSR @aa:24 2 JSR @@aa:8 2 LDC #xx:8, CCR 1 LDC Rs, CCR 1 LDC@ERs, CCR 2 1 LDC@(d:16, ERs), CCR 3 1 LDC@(d:24,ERs), CCR 5 1 LDC@ERs+, CCR 2 1 LDC@aa:16, CCR 3 1 LDC@aa:24, CCR 4 1 MOV.B #xx:8, Rd 1 MOV.B Rs, Rd 1 MOV.B @ERs, Rd 1 1 MOV.B @(d:16, ERs), Rd 2 1 MOV.B @(d:24, ERs), Rd 4 1 MOV.B @ERs+, Rd 1 1 MOV.B @aa:8, Rd 1 1 MOV.B @aa:16, Rd 2 1 MOV.B @aa:24, Rd 3 1 MOV.B Rs, @Erd 1 1 MOV.B Rs, @(d:16, ERd) 2 1 MOV.B Rs, @(d:24, ERd) 4 1 MOV.B Rs, @-ERd 1 1 MOV.B Rs, @aa:8 1 1 Internal Operation N 2 1 2 1 2 1 1 1 2 2 2 Rev. 3.00 Sep. 14, 2006 Page 373 of 408 REJ09B0105-0300 Appendix Instruction Mnemonic Instruction Fetch I MOV MOV.B Rs, @aa:16 2 1 MOV.B Rs, @aa:24 3 1 MOV.W #xx:16, Rd 2 MOV.W Rs, Rd 1 MOV.W @ERs, Rd 1 1 MOV.W @(d:16,ERs), Rd 2 1 MOV.W @(d:24,ERs), Rd 4 1 MOV.W @ERs+, Rd 1 1 MOV.W @aa:16, Rd 2 1 MOV.W @aa:24, Rd 3 1 MOV.W Rs, @ERd 1 1 MOV.W Rs, @(d:16,ERd) 2 1 MOV.W Rs, @(d:24,ERd) 4 1 MOV.W Rs, @-ERd 1 1 MOV.W Rs, @aa:16 2 1 MOV.W Rs, @aa:24 3 1 MOV.L #xx:32, ERd 3 MOV.L ERs, ERd 1 MOV.L @ERs, ERd 2 2 MOV.L @(d:16,ERs), ERd 3 2 MOV.L @(d:24,ERs), ERd 5 2 MOV.L @ERs+, ERd 2 2 MOV.L @aa:16, ERd 3 2 MOV.L @aa:24, ERd 4 2 MOV.L ERs,@ERd 2 2 MOV.L ERs, @(d:16,ERd) 3 2 MOV.L ERs, @(d:24,ERd) 5 2 MOV.L ERs, @-ERd 2 2 MOV.L ERs, @aa:16 3 2 MOV.L ERs, @aa:24 4 2 MOV 2 Branch Stack Addr. Read Operation J K Byte Data Access L MOVFPE MOVFPE @aa:16, Rd* 2 1 MOVTPE 2 2 1 MOVTPE Rs,@aa:16* Rev. 3.00 Sep. 14, 2006 Page 374 of 408 REJ09B0105-0300 Word Data Access M Internal Operation N 2 2 2 2 Appendix Instruction Mnemonic Instruction Fetch I MULXS MULXU NEG 12 2 20 MULXU.B Rs, Rd 1 12 MULXU.W Rs, ERd 1 20 NEG.B Rd 1 NEG.W Rd 1 NEG.L ERd 1 NOP 1 1 NOT.W Rd 1 NOT.L ERd 1 PUSH ROTL ROTR ROTXL Internal Operation N 2 NOT.B Rd POP Word Data Access M MULXS.B Rs, Rd NOT ORC Byte Data Access L MULXS.W Rs, ERd NOP OR Branch Stack Addr. Read Operation J K OR.B #xx:8, Rd 1 OR.B Rs, Rd 1 OR.W #xx:16, Rd 2 OR.W Rs, Rd 1 OR.L #xx:32, ERd 3 OR.L ERs, ERd 2 ORC #xx:8, CCR 1 POP.W Rn 1 1 2 POP.L ERn 2 2 2 PUSH.W Rn 1 1 2 PUSH.L ERn 2 2 2 ROTL.B Rd 1 ROTL.W Rd 1 ROTL.L ERd 1 ROTR.B Rd 1 ROTR.W Rd 1 ROTR.L ERd 1 ROTXL.B Rd 1 ROTXL.W Rd 1 ROTXL.L ERd 1 Rev. 3.00 Sep. 14, 2006 Page 375 of 408 REJ09B0105-0300 Appendix Instruction Mnemonic Instruction Fetch I ROTXR ROTXR.B Rd 1 ROTXR.W Rd 1 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N ROTXR.L ERd 1 RTE RTE 2 2 2 RTS RTS 2 1 2 SHAL SHAR SHLL SHLR SHAL.B Rd 1 SHAL.W Rd 1 SHAL.L ERd 1 SHAR.B Rd 1 SHAR.W Rd 1 SHAR.L ERd 1 SHLL.B Rd 1 SHLL.W Rd 1 SHLL.L ERd 1 SHLR.B Rd 1 SHLR.W Rd 1 SHLR.L ERd 1 SLEEP SLEEP 1 STC STC CCR, Rd 1 STC CCR, @ERd 2 1 STC CCR, @(d:16,ERd) 3 1 STC CCR, @(d:24,ERd) 5 1 STC CCR,@-ERd 2 1 STC CCR, @aa:16 3 1 1 SUB SUBS STC CCR, @aa:24 4 SUB.B Rs, Rd 1 SUB.W #xx:16, Rd 2 SUB.W Rs, Rd 1 SUB.L #xx:32, ERd 3 SUB.L ERs, ERd 1 SUBS #1/2/4, ERd 1 Rev. 3.00 Sep. 14, 2006 Page 376 of 408 REJ09B0105-0300 2 Appendix Instruction Mnemonic Instruction Fetch I SUBX TRAPA XOR XORC SUBX #xx:8, Rd 1 SUBX. Rs, Rd 1 TRAPA #xx:2 2 XOR.B #xx:8, Rd 1 XOR.B Rs, Rd 1 XOR.W #xx:16, Rd 2 XOR.W Rs, Rd 1 XOR.L #xx:32, ERd 3 XOR.L ERs, ERd 2 XORC #xx:8, CCR 1 Branch Stack Addr. Read Operation J K 1 2 Byte Data Access L Word Data Access M Internal Operation N 4 Notes: 1. n: Specified value in R4L and R4. The source and destination operands are accessed n+1 times respectively. 2. Cannot be used in this LSI. Rev. 3.00 Sep. 14, 2006 Page 377 of 408 REJ09B0105-0300 Appendix A.4 Combinations of Instructions and Addressing Modes Table A.5 Combinations of Instructions and Addressing Modes @@aa:8 -- -- -- -- -- -- -- WL -- BWL BWL -- @(d:16.PC) -- -- -- @aa:24 -- -- -- B @aa:16 -- -- -- @aa:8 @ERn+/@ERn @(d:24.ERn) @ERn BWL BWL BWL BWL BWL BWL -- -- -- -- -- -- -- -- -- -- -- -- @(d:8.PC) Data MOV transfer POP, PUSH instructions MOVFPE, Rn Instructions #xx Functions @(d:16.ERn) Addressing Mode MOVTPE BWL BWL WL BWL B B -- L -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BWL B BW DIVXS NEG -- BWL -- -- -- -- -- -- -- -- -- -- -- EXTU, EXTS AND, OR, XOR -- -- WL BWL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- NOT Shift operations -- -- BWL BWL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit manipulations Branching BCC, BSR instructions JMP, JSR -- -- -- B -- B -- -- -- -- -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- W -- -- -- W -- -- -- W -- -- -- W -- -- -- -- -- -- -- W -- -- -- W -- -- -- -- -- -- -- -- -- -- -- -- -- B B -- W -- W -- W -- W -- -- -- W -- W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BW Arithmetic operations ADD, CMP SUB ADDX, SUBX ADDS, SUBS INC, DEC DAA, DAS MULXU, -- -- -- MULXS, DIVXU, Logical operations RTS System TRAPA control RTE instructions SLEEP LDC STC ANDC, ORC, XORC NOP Block data transfer instructions -- -- -- -- B Rev. 3.00 Sep. 14, 2006 Page 378 of 408 REJ09B0105-0300 Appendix Appendix B I/O Port Block Diagrams B.1 I/O Port Block Diagrams RES goes low in a reset, and SBY goes low in a reset and in standby mode. Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR IRQ TRGV [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.1 Port 1 Block Diagram (P17) Rev. 3.00 Sep. 14, 2006 Page 379 of 408 REJ09B0105-0300 Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR IRQ [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.2 Port 1 Block Diagram (P14) Rev. 3.00 Sep. 14, 2006 Page 380 of 408 REJ09B0105-0300 Appendix Internal data bus SBY PMR PDR PCR SCI3 TXD [Legend] PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.3 Port 2 Block Diagram (P22) Rev. 3.00 Sep. 14, 2006 Page 381 of 408 REJ09B0105-0300 Appendix SBY Internal data bus PDR PCR SCI3 RE RXD [Legend] PDR: Port data register PCR: Port control register Figure B.4 Port 2 Block Diagram (P21) Rev. 3.00 Sep. 14, 2006 Page 382 of 408 REJ09B0105-0300 Appendix SBY SCI3 SCKIE SCKOE Internal data bus PDR PCR SCKO SCKI [Legend] PDR: Port data register PCR: Port control register Figure B.5 Port 2 Block Diagram (P20) Rev. 3.00 Sep. 14, 2006 Page 383 of 408 REJ09B0105-0300 Appendix Internal data bus SBY PDR PCR IIC2 ICE SDAO/SCLO SDAI/SCLI [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.6 (1) Port 5 Block Diagram (P57, P56) (for H8/36912 Group) Rev. 3.00 Sep. 14, 2006 Page 384 of 408 REJ09B0105-0300 Appendix Internal data bus SBY PDR PCR [Legend] PDR: PCR: Portdata register Portcontrol register Figure B.6 (2) Port 5 Block Diagram (P57, P56) (for H8/36902 Group) Rev. 3.00 Sep. 14, 2006 Page 385 of 408 REJ09B0105-0300 Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR WKP ADTRG [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.7 Port 5 Block Diagram (P55) Rev. 3.00 Sep. 14, 2006 Page 386 of 408 REJ09B0105-0300 Appendix Internal data bus SBY Timer V OS3 OS2 OS1 OS0 PDR PCR TMOV [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.8 Port 5 Block Diagram (P76) Rev. 3.00 Sep. 14, 2006 Page 387 of 408 REJ09B0105-0300 Appendix Internal data bus SBY PDR PCR Timer V TMCIV [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.9 Port 7 Block Diagram (P75) Rev. 3.00 Sep. 14, 2006 Page 388 of 408 REJ09B0105-0300 Appendix Internal data bus SBY PDR PCR Timer V TMRIV [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.10 Port 7 Block Diagram (P74) Rev. 3.00 Sep. 14, 2006 Page 389 of 408 REJ09B0105-0300 Appendix Internal data bus SBY Timer W Output control signal A to D PDR PCR FTIOA to D [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.11 Port 8 Block Diagram (P84 to P81) Rev. 3.00 Sep. 14, 2006 Page 390 of 408 REJ09B0105-0300 Appendix Internal data bus SBY PDR PCR Timer W FTCI [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.12 Port 8 Block Diagram (P80) Rev. 3.00 Sep. 14, 2006 Page 391 of 408 REJ09B0105-0300 Appendix Internal data bus A/D converter CH3 to CH0 SCAN VIN DEC Low voltage detection circuit VDDII ExtD, ExtU [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.13 Port B Block Diagram (PB3, PB2) Internal data bus A/D converter SCAN CH3 to CH0 DEC VIN Figure B.14 Port B Block Diagram (PB1, PB0) Rev. 3.00 Sep. 14, 2006 Page 392 of 408 REJ09B0105-0300 Appendix SBY Internal data bus CPG PDR PCR PMRC1 PMRC0 XTALI [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.15 Port C Block Diagram (PC1) Rev. 3.00 Sep. 14, 2006 Page 393 of 408 REJ09B0105-0300 Appendix SBY Internal data bus PDR PCR CPG PMRC0 EXTALI [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.16 Port C Block Diagram (PC0) B.2 Port States in Each Operating State Port Reset Active Sleep Subsleep Standby P17, P14 High impedance Functioning Retained Retained High impedance* P22 to P20 High impedance Functioning Retained Retained High impedance P57 to P55 High impedance Functioning Retained Retained High impedance* P76 to P74 High impedance Functioning Retained Retained High impedance P84 to P80 High impedance Functioning Retained Retained High impedance PB3 to PB0 High impedance High impedance High impedance Retained High impedance PC1, PC0 High impedance Functioning Retained Retained High impedance Note: * High level output when the pull-up MOS is in on state. Rev. 3.00 Sep. 14, 2006 Page 394 of 408 REJ09B0105-0300 Appendix Appendix C Product Code Lineup Product Type Product Code Model Marking Package Code H8/36912 Flash memory version HD64F36912G HD64F36912GFH LQFP-32 (FP-32A) HD64F36912GTP SOP-32 (FP-32D) Masked ROM version HD64336912G H8/36911 Masked ROM version HD64336911G H8/36902 Flash memory version HD64F36902G Masked ROM version HD64336902G H8/36901 Masked ROM version HD64336901G H8/36900 Masked ROM version HD64336900G HD64F36912GP SDIP-32 (32P4B) HD64336912G (***) FH LQFP-32 (FP-32A) HD64336912G (***) TP SOP-32 (FP-32D) HD64336911G (***) FH LQFP-32 (FP-32A) HD64336911G (***) TP SOP-32 (FP-32D) HD64F36902GFH LQFP-32 (FP-32A) HD64F36902GTP SOP-32 (FP-32D) HD64F36902GP SDIP-32 (32P4B) HD64336902G (***) FH LQFP-32 (FP-32A) HD64336902G (***) TP SOP-32 (FP-32D) HD64336901G (***) FH LQFP-32 (FP-32A) HD64336901G (***) TP SOP-32 (FP-32D) HD64336900G (***) FH LQFP-32 (FP-32A) HD64336900G (***) TP SOP-32 (FP-32D) [Legend] (***): ROM code Rev. 3.00 Sep. 14, 2006 Page 395 of 408 REJ09B0105-0300 Appendix Appendix D Package Dimensions The package dimensions that are shows in the Renesas Semiconductor Packages Data Book have priority. Unit: mm 20.45 20.95 Max 17 11.30 32 1 1.27 *0.40 0.08 0.38 0.06 0.10 0.15 M *Dimension including the plating thickness Base material dimension 0.12 0.15 +- 0.10 0.20 0.04 1.00 Max *0.22 0.05 3.00 Max 16 14.14 0.30 1.42 0 - 8 0.80 0.20 Package Code JEDEC JEITA Mass (reference value) Figure D.1 FP-32D Package Dimensions Rev. 3.00 Sep. 14, 2006 Page 396 of 408 REJ09B0105-0300 FP-32D Conforms -- 1.3 g Appendix Unit: mm 9.0 0.2 7 17 25 16 32 9 1 0. 8 24 8 0.70 0.5 0.1 0.10 0.15 0. 04 *0.17 0. 05 1.40 1. 0 1.70Max 0 .20 M Package Code *Dimension including the plating thickness Base material dimension 0 ~ 10 0.10 0. 07 * 0.35 0.05 0.37 0.05 JEDEC JEITA Mass (reference value) FP-32A FP-32AV -- -- 0.2 g Figure D.2 FP-32A Package Dimension Rev. 3.00 Sep. 14, 2006 Page 397 of 408 REJ09B0105-0300 Appendix 17 1 16 E 32 e1 C Unit: mm L A1 A A2 D e b1 b b2 SEATING PLANE Symbol A A1 A2 b b1 b2 c D E e e1 L Dimension in Millmeters Nom Min Max 5.08 - - - - 0.51 - 3.8 - 0.55 0.45 0.35 1.3 1.0 0.9 1.03 0.73 0.63 0.34 0.27 0.22 28.2 28.0 27.8 9.05 8.9 8.75 - 1.778 - - 10.16 - - - 3.0 15 - 0 Package Code JEDEC JEITA Mass (reference value) Figure D.3 32P4B Package Dimension Rev. 3.00 Sep. 14, 2006 Page 398 of 408 REJ09B0105-0300 32P4B -- -- 2.2 Main Revisions and Additions in this Edition Item Page Revision (See Manual for Details) Preface When using an on-chip emulator (E7, E8) for H8/36912, H8/36902 program development and debugging, the following restrictions must be noted. 1.The NMI pin is reserved for the E7 or E8, and cannot be used. 2.Area H'2000 to H'2FFF is used by the E7 or E8, and is not available to the user. 3.Area H'F980 to H'FD7F must on no account be accessed. 4.When the E7 or E8 is used, address breaks can be set as either available to the user or for use by the E7 or E8. If address breaks are set as being used by the E7 or E8, the address break control registers must not be accessed. 5.When the E7 or E8 is used, NMI is an input/output pin (opendrain in output mode). 1.1 Features 1 2 2 2 * On-chip memory Product Classification Remarks Masked ROM version H8/36912 Under planning H8/36911 Under planning H8/36902 Under planning H8/36901 Under planning H8/36900 Under planning On-chip oscillator Frequency accuracy: 8MHz 1% (Typ.) Vcc = 5.0 V, Ta = 25C (Flash memory version): 8MHz 3% Vcc = 4.0 to 5.0 V, Ta = -20 to 75C 10MHz 4% (Typ.) Vcc = 4.0 to 5.0 V, Ta = -20 to 75C Package Code LQFP-32 FP-32A SOP-32 FP-32D SDIP-32 32P4B * Compact package Package LQFP-32 SOP-32 SDIP-32* Note: * Flash memory version only Rev. 3.00 Sep. 14, 2006 Page 399 of 408 REJ09B0105-0300 (OSC1) (OSC2) Figure 1.2 Internal Block Diagram of H8/36902 Group E10T_0* E10T_1* E10T_2* CPU H8/300H On-chip oscillator Address bus System clock generator bus (upper) NMI TEST RES VCL Figure 1.1 Internal Block 3, 4 Diagram of H8/36912 Group VCC Page Revision (See Manual for Details) VSS Item Data bus (lower) Port C PB3/AN3/ExtU PB2/AN2/ExtD PB1/AN1 PB0/AN0 AVCC PC0/OSC1 PC1/OSC2/CLKOUT Port B Note: * Can also be used for the E7 or E8 emulator. 28 29 PB2/AN2/ExtD 13 E10T_2* 12 E10T_1* 30 11 E10T_0* PB1/AN1 31 10 P17/IRQ3/TRGV PB0/AN0 32 9 H8/36912 Group Figure 1.5 Pin Arrangement 7, 8 of H8/36912 Group (FP-32D, 32P4B), Figure 1.6 Pin Arrangement of H8/36902 Group (FP-32D, 32P4B) Table 1.1 Pin Functions E10T_0* 15 18 P57/SCL E10T_1* 16 17 E10T_2* Note: * Can also be used for the E7 or E8 emulator. 9, 10 Pin No. Type Symbol E7, E8 E10T_0, E10T_1, E10T_2 Section 2 CPU 11 8 7 Note: * Can also be used for the E7 or E8 emulator. NMI VCL 6 PC0/OSC1 4 5 3 RES TEST Vss 2 PC1/OSC2/CLKOUT 1 (Top view) Vcc Figure 1.4 Pin Arrangement of H8/36902 Group (FP-32A) P76/TMOV PB3/AN3/ExtU AVcc Figure 1.3 Pin Arrangement 5, 6 of H8/36912 Group (FP-32A) * FP-32D, 32P4B FP-32A Functions 15, 16, 17 11, 12, 13 Interface pins for the E7 or E8 emulator High-speed operation All frequently-used instructions execute in two or four states Figure 2.1 Memory Map (1) 12 H'0000 H'0045 H'0046 H'1FFF H'2000 H'2FFF H8/36912F H8/36902F (Flash memory version) Interrupt vector H'0000 H'0045 H'0046 H8/36912 H8/36902 (Masked ROM version (under planning)) Interrupt vector H'1FFF E7 or E8 control program area (4 kbytes) Not used Not used H'F980 Rev. 3.00 Sep. 14, 2006 Page 400 of 408 REJ09B0105-0300 (E7 or E8 work area, for flash memory programming: 1 kbyte) Not used Item Page Revision (See Manual for Details) Figure 2.1 Memory Map (2) 13 H8/36911 H8/36901 (Masked ROM version (under planning)) H'0000 H'0045 H'0046 Table 3.1 Exception Sources 48 and Vector Address H8/36900 (Masked ROM version (under planning)) H'0000 H'0045 H'0046 Interrupt vector Interrupt vector Relative Module Exception Sources IIC2* IIC_2 transmit data empty IIC_2 transmit end IIC_2 receive error Timer B1* Timer B1 overflow Note: * Available for the H8/36912 Group only. Figure 5.1 Block Diagram of 69 Clock Pulse Generators System OSC1 clock OSC2 Duty correction circuit OSC oscillator ROSC On-chip oscillator ROSC Clock divider ROSC/2 ROSC/4 5.2.1 RC Control Register (RCCR) 71 Bit Bit Name Description 1 RCPSC1 Division Ratio Select for On-chip Oscillator 0 RCPSC0 The division ratio of ROSC changes right after rewriting this bit. These bits can be written to only when the CKSTA bit in CKCSR is 0. 0X: ROSC (not divided) 10: ROSC/2 11: ROSC /4 5.2.2 RC Trimming Data Protect Register (RCTRMDPR) 73 Bit Bit Name Description 4 TRMDRWE Trimming Date Register Write Enable This register can be written to when the LOCKDW bit is 0 and this bit is 1. [Setting condition] * When writing 0 to the WRI bit while writing 1 to the TRMDRWE bit while the PRWE bit is 1 [Clearing conditions] * Reset * When writing 0 to the WRI bit and writing 0 to the TRMDRWE bit while the PRWE bit is 1 Rev. 3.00 Sep. 14, 2006 Page 401 of 408 REJ09B0105-0300 Item Page Revision (See Manual for Details) 5.2.3 RC Trimming Data Register (RCTRMDR) 73 5.2.4 Clock Control/Status Register (CKCSR) 74 Figure 5.5 Timing Chart of 78 Switching On-chip Oscillator Clock to External Clock Table 5.1 Crystal Resonator 82 Parameters Bit Bit Name Description 7 TRMD7 Trimming Data 6 TRMD6 5 TRMD5 4 TRMD4 In the flash memory version, the trimming data is loaded from the flash memory to this register right after a reset. These bits are always read as undefined value. 3 TRMD3 2 TRMD2 1 TRMD1 0 TRMD0 Bit Bit Name Description 7 PMRC1 6 PMRC0 As for the masked ROM version (under planning), the on-chip oscillator frequency can be trimmed by rewriting these bits. Port C Function Select 1 and 0 Note: * The halt duration is the duration from the timing when the clock stops to the first rising edge of the OSC clock after six clock cycles of the RC clock have elapsed. Frequency (MHz) 12 50 RS (Max.) Section 7 ROM 97 The features of the 12-kbyte (including 4 kbytes as the E7 or E8 control program area) flash memory built into the HD64F36912G and HD64F36902G are summarized below. Figure 7.1 Flash Memory Block Configuration 98 Programming unit: 64 kbytes Table 7.3 System Clock 105 Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Figure 7.4 Erase/EraseVerify Flowchart Host Bit Rate System Clock Frequency Range of LSI 9600bps 8 MHz (on-chip oscillator clock) 4800bps 8 MHz (on-chip oscillator clock) 2400bps 8 MHz (on-chip oscillator clock) 111 Read verify data No Increment address Verify data = all 1s ? Yes Section 8 RAM 115 Rev. 3.00 Sep. 14, 2006 Page 402 of 408 REJ09B0105-0300 Note: * When the E7 or E8 is used, area H'F980 to H'FD7F must not be accessed. Item Page Revision (See Manual for Details) 13.2.1 Timer Control/Status Register WD (TCSRWD) 192 Bit Bit Name Description 4 TCSRWE Timer Control/Status Register WD Write Enable The WDON and WRST bits can be written when the TCSRWE bit is set to 1. When writing data to this bit, the value for bit 5 must be 0. 14.8.2 Mark State and Break 236 Sending 15.3.5 I2C Bus Status Register (ICSR) 251 Replaced Bit Bit Name Description 3 STOP Stop Condition Detection Flag [Setting conditions] * In master mode, when a stop condition is detected after frame transfer * In slave mode, when a stop condition is detected after the general call address or the first byte slave address, next to detection of start condition, accords with the address set in SAR ...... Figure 15.15 Receive Mode Operation Timing 265 SCL 7 8 1 2 SDA (Input) Bit 6 Bit 7 Bit 0 Bit 1 MST 15.7 Usage Notes 272 16.3.1 A/D Data Registers A 276 to D (ADDRA to ADDRD) Figure 17.2 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit 287 20.3 Electrical Characteristics (Masked ROM Version) 331 Added There are four 16-bit read-only ADDR registers; ...... Therefore, byte access to ADDR should be done by reading the upper byte first then the lower one. ADDR is initialized to H'0000. RES CRES 20.3 Electrical Characteristics (Masked ROM Version) [Preliminary] The guarantee value for the electrical characteristics of masked ROM version is preliminary. 20.3.1 Power Supply Voltage and Operating Ranges Rev. 3.00 Sep. 14, 2006 Page 403 of 408 REJ09B0105-0300 Item Page Revision (See Manual for Details) Table 20.13 AC Characteristics 339 Symbol Min. Typ. Max. On-chip oscillator oscillation frequency fRC 7.6 8.0 8.4 9.4 10.0 10.6 Appendix C Product Code Lineup 395 Z V C * -- -- DAA Rd B 2 Rd8 decimal adjust Rd8 -- * Package Code HD64F36912GFH LQFP-32 (FP-32A) HD64F36912GTP SOP-32 (FP-32D) HD64F36912GP SDIP-32 (32P4B) HD64336912G(***) FH LQFP-32 (FP-32A) HD64336912G(***) TP SOP-32 (FP-32D) HD64336912G(***) P SDIP-32 (32P4B) HD64336911G(***) FH LQFP-32 (FP-32A) HD64336911G(***) TP SOP-32 (FP-32D) HD64336911G(***) P SDIP-32 (32P4B) HD64F36902GFH LQFP-32 (FP-32A) Masked ROM version Flash memory version Masked ROM version H8/36901 H8/36900 Masked ROM version Masked ROM version HD64F36902GTP SOP-32 (FP-32D) HD64F36902GP SDIP-32 (32P4B) HD64336902G(***) FH LQFP-32 (FP-32A) HD64336902G(***) TP SOP-32 (FP-32D) HD64336902G(***) P SDIP-32 (32P4B) HD64336901G(***) FH LQFP-32 (FP-32A) HD64336901G(***) TP SOP-32 (FP-32D) HD64336901G(***) P SDIP-32 (32P4B) HD64336900G(***) FH LQFP-32 (FP-32A) HD64336900G(***) TP SOP-32 (FP-32D) HD64336900G(***) P SDIP-32 (32P4B) Package Code 32P4B JEDEC -- JEITA -- Mass (reference value) 2.2 2 2 Model Marking Flash memory version Advanced N -- @@aa @(d, PC) @aa H -- ERd32+2 ERd32 H8/36912 H8/36902 REJ09B0105-0300 I Rd8+#xx:8 Rd8 2 Product Type H8/36911 Rev. 3.00 Sep. 14, 2006 Page 404 of 408 Condition Code Operation L Masked ROM version Figure D.3 32P4B Package 398 Dimension @-ERn/@ERn+ 2 No. of States*1 INC.L #2, ERd ADD ADD.B #xx:8, Rd DAA B @(d, ERn) Mnemonic @ERn Arithmetic instructions Rn Addressing Mode and Instruction Length (bytes) Normal 353 #xx * Item Operand Size Table A.1 Instruction Set Values 2 Index A A/D converter ......................................... 273 A/D conversion time........................... 280 External trigger input.......................... 281 Sample-and-hold circuit...................... 280 Scan mode........................................... 279 Single mode ........................................ 279 Acknowledge .......................................... 255 Address break ........................................... 63 Addressing modes Absolute address................................... 33 Immediate ............................................. 34 Memory indirect ................................... 34 Program-counter relative ...................... 34 Register direct....................................... 32 Register indirect.................................... 33 Register indirect with displacement...... 33 Register indirect with post-increment... 33 Register indirect with pre-decrement.... 33 B Bit Synchronous Circuit ......................... 271 C Clock pulse generators System Prescaler S................................ 83 Clocked Synchronous Serial Format ...... 263 Condition field.......................................... 31 Condition-code register (CCR)................. 16 CPU .......................................................... 11 E Effective address....................................... 35 Effective address extension ...................... 31 Exception handling ................................... 47 Reset exception handling ...................... 54 Stack status ........................................... 58 Trap instruction..................................... 47 F Flash memory ........................................... 97 Boot mode........................................... 102 Boot program ...................................... 102 Erase/erase-verify ............................... 109 Erasing units ......................................... 97 Error protection................................... 112 Hardware protection............................ 112 Program/program-verify ..................... 107 Programming units................................ 97 Programming/erasing in user program mode.................................................... 106 Software protection............................. 112 G General registers ....................................... 15 I I/O ports .................................................. 117 I/O port block diagrams ...................... 379 I2C Bus Format ....................................... 254 I2C Bus Interface 2 (IIC2)....................... 239 Instruction set............................................ 21 Arithmetic operations instructions ........ 23 Bit Manipulation instructions................ 26 Block data transfer instructions............. 30 Branch instructions ............................... 28 Data Transfer instructions..................... 22 Logic Operations instructions ............... 25 Rev. 3.00 Sep. 14, 2006 Page 405 of 408 REJ09B0105-0300 Shift Instructions .................................. 25 System control instructions................... 29 Internal power supply step-down circuit...................................................... 299 Interrupt Internal interrupts ................................. 56 Interrupt response time ......................... 59 IRQ3 to IRQ0 interrupts ....................... 55 NMI interrupt........................................ 55 WKP5 to WKP0 interrupts ................... 55 L Low-voltage detection circuit ................. 285 LVDI .............................................. 293, 295 LVDI (interrupt by low voltage detect) circuit.............................................. 293, 295 LVDR ..................................................... 292 LVDR (reset by low voltage detect) circuit...................................................... 292 M Memory map ............................................ 12 Module standby function .......................... 95 N Noise Canceler........................................ 265 O On-board programming modes............... 102 Operation field.......................................... 30 P Package....................................................... 2 Package dimensions................................ 396 Rev. 3.00 Sep. 14, 2006 Page 406 of 408 REJ09B0105-0300 Power-down modes................................... 85 Sleep mode............................................ 93 Standby mode ....................................... 93 Subsleep mode ...................................... 94 Power-on reset ........................................ 285 Power-on reset circuit ............................. 291 Product code lineup ................................ 395 Program counter (PC) ............................... 16 PWM operation....................................... 176 R Register ABRKCR...................... 64, 304, 308, 310 ABRKSR ...................... 66, 304, 308, 310 ADCR ......................... 278, 303, 307, 310 ADCSR ....................... 276, 303, 307, 310 ADDRA ...................... 275, 303, 307, 310 ADDRB ...................... 275, 303, 307, 310 ADDRC ...................... 275, 303, 307, 310 ADDRD ...................... 275, 303, 307, 310 BARH ........................... 66, 304, 308, 310 BARL............................ 66, 304, 308, 310 BDRH ........................... 66, 304, 308, 310 BDRL............................ 66, 304, 308, 310 BRR ............................ 206, 303, 307, 310 EBR1........................... 101, 303, 307, 309 FENR .......................... 101, 303, 307, 309 FLMCR1....................... 99, 303, 307, 309 FLMCR2..................... 100, 303, 307, 309 GRA............................ 171, 303, 306, 309 GRB ............................ 171, 303, 306, 309 GRC ............................ 171, 303, 307, 309 GRD............................ 171, 303, 307, 309 ICCR1 ......................... 242, 302, 306, 309 ICCR2 ......................... 245, 302, 306, 309 ICDRR ........................ 253, 302, 306, 309 ICDRS................................................. 253 ICDRT ........................ 253, 302, 306, 309 ICIER.......................... 248, 302, 306, 309 ICMR.......................... 246, 302, 306, 309 ICSR ........................... 250, 302, 306, 309 IEGR1........................... 49, 304, 308, 311 IEGR2........................... 50, 304, 308, 311 IENR1........................... 50, 304, 308, 311 IRR1 ............................. 52, 305, 308, 311 IWPR ............................ 53, 305, 308, 311 LVDCR....................... 288, 302, 306, 309 LVDSR ....................... 290, 302, 306, 309 MSTCR1....................... 89, 305, 308, 311 MSTCR2....................... 90, 305, 308, 311 PCR1........................... 119, 304, 308, 311 PCR2........................... 122, 304, 308, 311 PCR5........................... 125, 304, 308, 311 PCR7........................... 128, 304, 308, 311 PCR8........................... 131, 304, 308, 311 PDR1 .......................... 119, 304, 308, 310 PDR2 .......................... 122, 304, 308, 310 PDR5 .......................... 126, 304, 308, 310 PDR7 .......................... 129, 304, 308, 310 PDR8 .......................... 131, 304, 308, 310 PDRB.......................... 134, 304, 308, 310 PMR1.......................... 118, 304, 308, 311 PMR5.......................... 125, 304, 308, 311 PUCR1........................ 120, 304, 308, 310 PUCR5........................ 126, 304, 308, 310 RDR............................ 200, 303, 307, 310 RSR..................................................... 200 SAR ............................ 252, 302, 306, 309 SCR3........................... 202, 303, 307, 310 SMR............................ 201, 303, 307, 310 SPMR ......................... 211, 303, 307, 310 SSR ............................. 204, 303, 307, 310 SYSCR1 ....................... 86, 304, 308, 311 SYSCR2 ....................... 88, 304, 308, 311 TCB1 .......................... 141, 302, 306, 309 TCNT.................................. 171, 306, 309 TCNTV....................... 147, 303, 307, 310 TCORA....................... 148, 303, 307, 310 TCORB ....................... 148, 303, 307, 310 TCRV0........................ 148, 303, 307, 309 TCRV1........................ 151, 303, 307, 310 TCRW......................... 164, 302, 306, 309 TCSRV........................ 150, 303, 307, 310 TCSRWD.................... 192, 303, 307, 310 TCWD......................... 194, 304, 307, 310 TDR ............................ 200, 303, 307, 310 TIERW........................ 165, 302, 306, 309 TIOR0 ......................... 168, 303, 306, 309 TIOR1 ......................... 169, 303, 306, 309 TLB1................................................... 141 TMB1.......................... 140, 302, 306, 309 TMRW ........................ 163, 302, 306, 309 TMWD........................ 194, 304, 307, 310 TSR ..................................................... 200 TSRW ......................... 166, 302, 306, 309 Register field............................................. 30 S Serial communication interface 3 (SCI3) ..................................................... 197 Asynchronous mode............................ 212 Bit rate................................................. 206 Break................................................... 236 Clocked synchronous mode ................ 219 Framing error ...................................... 216 Multiprocessor communication function ............................................... 227 Overrun error ...................................... 216 Parity error .......................................... 216 Slave address........................................... 255 Stack pointer (SP) ..................................... 16 Start condition......................................... 255 Stop condition ......................................... 255 System clocks ........................................... 69 Rev. 3.00 Sep. 14, 2006 Page 407 of 408 REJ09B0105-0300 T Timer B1................................................. 139 Auto-reload timer operation ............... 142 Interval timer operation ...................... 142 Timer V .................................................. 145 Timer W ................................................. 159 Transfer Rate .......................................... 244 Rev. 3.00 Sep. 14, 2006 Page 408 of 408 REJ09B0105-0300 V Vector address........................................... 47 W Watchdog timer....................................... 191 Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8/36912 Group, H8/36902 Group Publication Date: Rev.1.00, Nov. 07, 2003 Rev.3.00, Sep. 14, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. 2006. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 Colophon 6.0 H8/36912 Group, H8/36902 Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0105-0300