SCLS404F − APRIL 1998 − REVISED DECEMBER 2005
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D2-V to 5.5-V VCC Operation
DMax tpd of 9.5 ns at 5 V
DTypical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
DTypical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
DSupport Mixed-Mode Voltage Operation on
All Ports
DInternal Look-Ahead for Fast Counting
DCarry Output for n-Bit Cascading
DSynchronous Counting
DSynchronously Programmable
DIoff Supports Partial-Power-Down Mode
Operation
DLatch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
DESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
The ’LV161A devices are 4-bit synchronous
binary counters designed for 2-V to 5.5-V VCC
operation.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
SOIC − D
Tube of 40 SN74LV161AD
LV161A
SOIC − D Reel of 2500 SN74LV161ADR LV161A
SOP − NS Reel of 2000 SN74LV161ANSR 74LV161A
−40°C to 85°C
SSOP − DB Reel of 2000 SN74LV161ADBR LV161A
−40°C to 85°CTube of 90 SN74LV161APW
TSSOP − PW Reel of 2000 SN74LV161APWR LV161A
TSSOP − PW
Reel of 250 SN74LV161APWT
LV161A
TVSOP − DGV Reel of 2000 SN74LV161ADGVR LV161A
CDIP − J Tube of 25 SNJ54LV161AJ SNJ54LV161AJ
−55°C to 125°CCFP − W Tube of 150 SNJ54LV161AW SNJ54LV161AW
−55 C to 125 C
LCCC − FK Tube of 55 SNJ54LV161AFK SNJ54LV161AFK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright 2005, Texas Instruments Incorporated
!"#$ $%$ &
$'("%$ !((#$ % ' )!*+%$ %#, &(! $'("
)#'%$ )#( # #(" ' #-% $(!"#$ %$%( .%((%$/,
&(!$ )(#$0 # $ $##%(+/ $+!# #$0 ' %++
)%(%"##(,
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LV161A ...J OR W PACKAGE
SN74LV161A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
SN54LV161A . . . FK PACKAGE
(TOP VIEW)
NC − No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
CLK
A
B
C
D
ENP
GND
VCC
RCO
QA
QB
QC
QD
ENT
LOAD
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
QA
QB
NC
QC
QD
A
B
NC
C
D
CLK
CLR
NC
LOAD
ENT RCO
ENP
GND
NC VCC
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed
counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the
outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and
internal gating. This mode of operation eliminates the output counting spikes that normally are associated with
synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising
(positive-going) edge of the clock waveform.
These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As
presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs
to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function for the ’LV161A devices is asynchronous. A low level at the clear (CLR) input sets all four
of the flip-flop outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO).
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the
level of CLK.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
INPUTS OUTPUTS
FUNCTION
CLR LOAD ENP ENT CLK QA QB QC QD FUNCTION
L X X X X L L L L Reset to “0”
HLXX↑AB C D Preset Data
HHXL↑No Change No Count
HHLX↑No Change No Count
HHHH↑Count up Count
H X X X ↑No Change No Count
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1
9
10
7
3
15
14
CLR
LOAD
ENT
ENP
CLK
A
RCO
QA
†For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown
on the logic diagram of the D/T flip-flops.
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
M1
G2
G4
3D
4R
1, 2T/1C3
4
13
B
QB
M1
G2
G4
3D
4R
1, 2T/1C3
5
12
C
QC
M1
G2
G4
3D
4R
1, 2T/1C3
6
11
D
QD
M1
G2
G4
3D
4R
1, 2T/1C3
2
LD†
CK†
CK
R
LD
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol, each D/T flip-flop
M1LD (Load)
Q (Output)
G2TE (Toggle Enable)
CK (Clock) G4
3D
4R
1, 2T/1C3
D (Inverted Data)
R (Inverted Reset)
logic diagram, each D/T flip-flop (positive logic)
TG
TG
TG
TG
TG
TG
CK
LD
TE
LD†
LD†
D
R
CK†
CK†
CK†
CK†
Q
†The origins of LD and CK are shown in the overall logic diagram of the device.
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical clear, preset, count, and inhibit sequence
The following sequence is illustrated below:
1. Clear outputs to zero (asynchronous)
2. Preset to binary 12
3. Count to 13, 14, 15, 0, 1, and 2
4. Inhibit
A
Data
Inputs
Data
Outputs
CLR
LOAD
B
C
D
CLK
ENP
ENT
RCO
QA
QB
QC
QD
Async
Clear
Sync
Clear Preset
Count Inhibit
12 13 14 15 0 1 2
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range applied in high or low state, VO (see Notes 1 and 2) −0.5 V to VCC + 0.5 V. . . . . . . . . .
Voltage range applied to any output in the power-off state, VO (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) −20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package 82°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
SN54LV161A SN74LV161A
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 2 5.5 2 5.5 V
VCC = 2 V 1.5 1.5
VIH
High-level input voltage
VCC = 2.3 V to 2.7 V VCC ×0.7 VCC ×0.7
V
VIH High-level input voltage VCC = 3 V to 3.6 V VCC ×0.7 VCC ×0.7 V
VCC = 4.5 V to 5.5 V VCC ×0.7 VCC ×0.7
VCC = 2 V 0.5 0.5
VIL
Low-level input voltage
VCC = 2.3 V to 2.7 V VCC ×0.3 VCC ×0.3
V
VIL Low-level input voltage VCC = 3 V to 3.6 V VCC ×0.3 VCC ×0.3 V
VCC = 4.5 V to 5.5 V VCC ×0.3 VCC ×0.3
VIInput voltage 0 5.5 0 5.5 V
VOOutput voltage 0 VCC 0 VCC V
VCC = 2 V −50 −50 µA
IOH
High-level output current
VCC = 2.3 V to 2.7 V −2 −2
IOH High-level output current VCC = 3 V to 3.6 V −6 −6 mA
VCC = 4.5 V to 5.5 V −12 −12
mA
VCC = 2 V 50 50 µA
IOL
Low-level output current
VCC = 2.3 V to 2.7 V 2 2
IOL Low-level output current VCC = 3 V to 3.6 V 6 6 mA
VCC = 4.5 V to 5.5 V 12 12
mA
VCC = 2.3 V to 2.7 V 0 200 0 200
∆t/∆vInput transition rise or fall rate VCC = 3 V to 3.6 V 0 100 0 100 ns/V
∆t/∆v
Input transition rise or fall rate
VCC = 4.5 V to 5.5 V 0 20 0 20
ns/V
TAOperating free-air temperature −55 125 −40 85 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
SN54LV161A SN74LV161A
UNIT
PARAMETER
TEST CONDITIONS
VCC MIN TYP MAX MIN TYP MAX
UNIT
IOH = −50 µA2 V to 5.5 V VCC−0.1 VCC−0.1
VOH
IOH = −2 mA 2.3 V 2 2
V
VOH IOH = −6 mA 3 V 2.48 2.48 V
IOH = −12 mA 4.5 V 3.8 3.8
IOL = 50 µA2 V to 5.5 V 0.1 0.1
VOL
IOL = 2 mA 2.3 V 0.4 0.4
V
VOL IOL = 6 mA 3 V 0.44 0.44 V
IOL = 12 mA 4.5 V 0.55 0.55
IIVI = 5.5 V or GND 0 to 5.5 V ±1±1µA
ICC VI = VCC or GND, IO = 0 5.5 V 20 20 µA
Ioff VI or VO = 0 to 5.5 V 0 5 5 µA
CiVI = VCC or GND 3.3 V 1.8 1.8 pF
& & $'("%$ $#($ )(! $ # '("%1# (
#0$ )%# ' #1#+)"#$, %(%#( %% %$ #(
)#'%$ %(# #0$ 0%+, #-% $(!"#$ (##(1# # (0
%$0# ( $$!# ## )(! .! $#,
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ±0.2 V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54LV161A SN74LV161A
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
tw
Pulse duration
CLK high or low 7 7 7
ns
twPulse duration CLR low 7 7 7 ns
CLR 4.5 4.5 4.5
tsu
Setup time before CLK↑
Data (A, B, C, and D) 7.5 8.5 8.5
ns
tsu Setup time before CLK↑ENP, ENT 9.5 11 11 ns
LOAD low 10 11.5 11.5
thHold time, all synchronous inputs after CLK↑1.5 1.5 1.5 ns
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ±0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54LV161A SN74LV161A
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
tw
Pulse duration
CLK high or low 5 5 5
ns
twPulse duration CLR low 5 5 5 ns
CLR 2.5 2.5 2.5
tsu
Setup time before CLK↑
Data (A, B, C, and D) 5.5 6.5 6.5
ns
tsu Setup time before CLK↑ENP, ENT 7.5 9 9 ns
LOAD low 8 9.5 9.5
thHold time, all synchronous inputs after CLK↑1 1 1 ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V ±0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54LV161A SN74LV161A
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
tw
Pulse duration
CLK high or low 5 5 5
ns
twPulse duration CLR low 5 5 5 ns
CLR 1.5 1.5 1.5
tsu
Setup time before CLK↑
Data (A, B, C, and D) 4.5 4.5 4.5
ns
tsu Setup time before CLK↑ENP, ENT 5 6 6 ns
LOAD low 5 6 6
thHold time, all synchronous inputs after CLK↑1 1 1 ns
& & $'("%$ $#($ )(! $ # '("%1# (
#0$ )%# ' #1#+)"#$, %(%#( %% %$ #(
)#'%$ %(# #0$ 0%+, #-% $(!"#$ (##(1# # (0
%$0# ( $$!# ## )(! .! $#,
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25°C SN54LV161A SN74LV161A
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE MIN TYP MAX MIN MAX MIN MAX
UNIT
fmax
CL = 15 pF 50* 125* 40* 40
MHz
fmax CL = 50 pF 30 95 25 25 MHz
Q7.9* 16.2* 1* 19.5* 1 19.5
tpd
CLK RCO
(count mode) 8.9* 17* 1* 20.5* 1 20.5
tpd
CLK
RCO
(preset mode) CL = 15 pF 11.9* 20.6* 1* 24.5* 1 24.5 ns
ENT RCO
L
8.3* 15.7* 1* 19* 1 19
tPHL
CLR
Q8.8* 17* 1* 20.5* 1 20.5
tPHL CLR RCO 9.8* 16.6* 1* 20* 1 20
Q10.5 19.2 1 22.5 1 22.5
tpd
CLK RCO
(count mode) 11.7 20 1 23.5 1 23.5
tpd
CLK
RCO
(preset mode) CL = 50 pF 14.5 23.6 1 27.5 1 27.5 ns
ENT RCO
L
11 18.7 1 22 1 22
tPHL
CLR
Q11.4 20 1 23.5 1 23.5
t
PHL
CLR
RCO 12.6 19.6 1 23 1 23
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
& & $'("%$ $#($ )(! $ # '("%1# (
#0$ )%# ' #1#+)"#$, %(%#( %% %$ #(
)#'%$ %(# #0$ 0%+, #-% $(!"#$ (##(1# # (0
%$0# ( $$!# ## )(! .! $#,
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25°C SN54LV161A SN74LV161A
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE MIN TYP MAX MIN MAX MIN MAX
UNIT
fmax
CL = 15 pF* 80* 165* 70* 70
MHz
fmax CL = 50 pF 55 125 50 50 MHz
Q6 12.8 1* 15* 1 15
tpd*
CLK RCO
(count mode) 6.7 13.6 1* 16* 1 16
tpd*
CLK
RCO
(preset mode) CL = 15 pF 8.6 17.2 1* 20* 1 20 ns
ENT RCO
L
6.2 12.3 1* 14.5* 1 14.5
tPHL*
CLR
Q6.5 13.6 1* 16* 1 16
tPHL*CLR RCO 7.2 13.2 1* 15.5* 1 15.5
Q7.8 16.3 1 18.5 1 18.5
tpd
CLK RCO
(count mode) 8.7 17.1 1 19.5 1 19.5
tpd
CLK
RCO
(preset mode) CL = 50 pF 10.6 20.7 1 23.5 1 23.5 ns
ENT RCO
L
8.3 15.8 1 18 1 18
tPHL
CLR
Q8.4 17.1 1 19.5 1 19.5
t
PHL
CLR
RCO 9.2 16.7 1 19 1 19
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25°C SN54LV161A SN74LV161A
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE MIN TYP MAX MIN MAX MIN MAX
UNIT
fmax
CL = 15 pF 135* 220 115* 115
MHz
fmax CL = 50 pF 95 165 85 85 MHz
Q4.5* 8.1* 1* 9.5* 1 9.5
tpd
CLK RCO
(count mode) 5.1* 8.1* 1* 9.5* 1 9.5
tpd
CLK
RCO
(preset mode) CL = 15 pF 6.3* 10.3* 1* 12* 1 12 ns
ENT RCO
L
4.8* 8.1* 1* 9.5* 1 9.5
tPHL
CLR
Q4.9* 9* 1* 10.5* 1 10.5
tPHL CLR RCO 5.5* 8.6* 1* 10* 1 10
Q5.9 10.1 1 11.5 1 11.5
tpd
CLK RCO
(count mode) 6.6 10.1 1 11.5 1 11.5
tpd
CLK
RCO
(preset mode) CL = 50 pF 7.8 12.3 1 14 1 14 ns
ENT RCO
L
6.1 10.1 1 11.5 1 11.5
tPHL
CLR
Q6.3 11 1 12.5 1 12.5
t
PHL
CLR
RCO 6.9 10.6 1 12 1 12
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5)
PARAMETER
SN74LV161A
UNIT
PARAMETER
MIN TYP MAX
UNIT
VOL(P) Quiet output, maximum dynamic VOL 0.3 0.8 V
VOL(V) Quiet output, minimum dynamic VOL −0.2 −0.8 V
VOH(V) Quiet output, minimum dynamic VOH 3 V
VIH(D) High-level dynamic input voltage 2.31 V
VIL(D) Low-level dynamic input voltage 0.99 V
NOTE 5: Characteristics are for surface-mount packages only.
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS VCC TYP UNIT
Cpd
Power dissipation capacitance
CL = 50 pF,
f = 10 MHz
3.3 V 23.6
pF
C
pd
Power dissipation capacitance
C
L
= 50 pF,
f = 10 MHz
5 V 25.8
pF
& & $'("%$ $#($ )(! $ # '("%1# (
#0$ )%# ' #1#+)"#$, %(%#( %% %$ #(
)#'%$ %(# #0$ 0%+, #-% $(!"#$ (##(1# # (0
%$0# ( $$!# ## )(! .! $#,
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
VCC
VCC
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VCC
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
Waveform 1
S1 at VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈VCC
0 V
50% VCC VOL + 0.3 V
50% VCC ≈0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
TEST S1
VCC
0 V
50% VCC
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
From Output
Under Test CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1
V
CC
RL = 1 kΩ
GND
From Output
Under Test CL
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
50% VCC
50% VCC 50% VCC
50% VCC
50% VCC 50% VCC
50% VCC 50% VCC
VOH − 0.3 V
Figure 1. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74LV161AD ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV161ADBR ACTIVE SSOP DB 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV161ADBRE4 ACTIVE SSOP DB 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV161ADBRG4 ACTIVE SSOP DB 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV161ADE4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV161ADG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV161ADGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV161ADGVRE4 ACTIVE TVSOP DGV 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV161ADGVRG4 ACTIVE TVSOP DGV 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV161ADR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV161ADRE4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV161ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV161ANSR ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV161ANSRE4 ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV161ANSRG4 ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV161APW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV161APWE4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV161APWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV161APWR ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV161APWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV161APWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV161APWT ACTIVE TSSOP PW 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV161APWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV161APWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LV161ADBR SSOP DB 16 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
SN74LV161ADGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
SN74LV161ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74LV161ANSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74LV161APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LV161APWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LV161ADBR SSOP DB 16 2000 367.0 367.0 38.0
SN74LV161ADGVR TVSOP DGV 16 2000 367.0 367.0 35.0
SN74LV161ADR SOIC D 16 2500 333.2 345.9 28.6
SN74LV161ANSR SO NS 16 2000 367.0 367.0 38.0
SN74LV161APWR TSSOP PW 16 2000 367.0 367.0 35.0
SN74LV161APWT TSSOP PW 16 250 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
