LINE SCAN SENSORS
DALSAIL-P1
ImageSensors
The IL-P1 sets new line scan standards. Its unprecedented
design and fabrication sophistication has produced superior
performance:highblueresponseandlowimagelag,twotaps
for high line rates, low-voltage clocks—and DALSA’s stan-
dard 100% fill factor.
Features
n
2 taps @ 25MHz data rate per tap
n
Line rates to 87kHz
n
Low voltage clocks (<5V)
n
10µm (H) x 10µm (V) pixels, 100% fill factor
n
512, 1024, 2048, or 4096 pixels
n
Antiblooming and exposure control
n
Highly sensitive, with responsivity reaching
12V/(µJ/cm2)
Description
Physical Characteristics
IL-P1
Pixel dimensions 10µm x 10µm
Active area 10µm x 5.1 / 10.2 / 20.5 / 41mm
Active pixels per line 512 / 1024 / 2048 / 4096
Isolation pixels per line 14
Shielded pixels per line 32
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32 RST
31 VOD
30 OS2
29 VSS
28 CR1B
27 CR2B
26 VBB
25 VSS
24 VSTOR
23 CR2S
22 CR1S
21 VBB
20 VBB
19 VHIGH
18
17 VDD
VHIGH
VLOW 1
VDD 2
OS1 3
VSET 4
CRLAST 5
CR1S 6
CR2S 7
TCK 8
PR 9
VPR 10
CR1B 11
CR2B 12
VLOW 13
VHIGH 14
VHIGH 15
NC 16
Pin Symbol Name
1,13 VLOW Low Bias Voltage
2,18 VDD Amplifier Supply Voltage
3 OS1 Output Signal 1
4 VSET Output Node Set Gate Voltage
5 CRLAST Readout Clock, Last storage phase
6, 22 CR1S Readout Clock, Phase 1—Storage Phase
7, 23 CR2S Readout Clock, Phase 2Storage Phase
8 TCK Transfer Clock
9 PR Pixel Reset Clock
10 VPR Pixel Reset Drain Voltage
11, 28 CR1B Readout Clock, Phase 1Barrier Phase
12, 27 CR2B Readout Clock, Phase 2—Barrier Phase
14, 15, 17, 19 VHIGH High Bias Voltage
16 NC No Connection
20, 21, 26 VBB Substrate Bias Voltage
24 VSTOR Storage Well Voltage
25, 29 VSS Ground Reference
30 OS2 Output Signal 2
31 VOD Output Reset Drain Voltage
32 RST Output Reset Clock
Table 1. IL-P1 Pin Functional Description
DALSA’sIL-P1seriesoflinearCCDimagesensorsusepro-
prietarytechnologytoprovidetwooutputsat25MHzeach.
The series employs buried channel CCD shift registers to
maximize output speed and reduce noise. The sensor has a
dynamic range of >3200:1 and provides output which is lin-
ear for the operating range of light input. The IL-P1’s expo-
sure control allows integration times shorter than the
readout time. Proprietary DALSA image sensor architec-
ture provides low image lag pixels and high blue response.
The IL-P1 sensor’s superior performance makes it ideally
suited for applications requiring maximum speed and high
resolution, such as:
n
High performance document scanning
n
Inspection
n
Optical character recognition
Functional Description
The IL-P1 sensor is composed of three main functional
groups: photodiodes in which the signal charge packets are
generated, two CCD readout shift registers, and two out-
put amplifiers where the charge packets are converted to
voltage pulses.
Detection
The IL-P1 series includes sensors with 512, 1024, 2048,
4096pixelswithactive imaging area lengths of 5, 10,20, and
41mm, respectively. Photoelements are 10µm square for a
photosensitive area of 100µm2and a 1:1 aspect ratio. Light
incident on these photoelements is converted into charge
packetswhose size (i.e., numberof electrons)is linearlyde-
pendent on the light intensity and the integration time. The
chargeiscollectedintoaseparatestoragewell(VSTOR)ad-
jacent to each photoelement. This helps to minimize both
image lag and nonuniformities associated with the use of
pixel reset.
Withexposurecontrol disabled, integration time isthe pe-
riodbetweensuccessive pulses of the transfer (TCK)clock.
Integration time can be further reduced with electronic ex-
posure control using the pixel reset (PR) clock. The pixel
reset clock resets not the photoelements themselves but
the storage well adjacent to each photoelement. When PR
is clocked, the integration time becomes the duration be-
tween the falling edge of the PR clock and the rising edge of
the TCK clock.
When PR is clocked, the PR pulse must be damped to pro-
duce a smooth PR pulse. If PR switches too rapidly, the uni-
formity of the OSn signals will be affected by the PR clock
feedthrough.
2
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N Photoelements (10µmx10µm)4I32 S 4I 32 S
CCD Readout Shift Register
CCD Readout Shift Register
5I
5I
4I
4I
TCK
PR
VPR
VSTOR
CR1S,CR2S,
CR1B,CR2B,CRLAST
CR1S,CR2S,
CR1B,CR2B,CRLAST
VSET
VBB
RST
VOD
VSS
VDD
OS1
32 S
4I Light-shielded pixels
N = 512,1024,
2048,or 4096
Isolation pixels
OS2
StorageWell with Exposure Control and Reset Structure
StorageWell with Exposure Control and Reset Structure
Relative position of package Pin 1
1
Figure 1. IL-P1 Block Diagram
Clock Drivers Min. # Required 1
Voltage Speed PR 2off PR on
Low High 3 3
High Low 1 2
1. Redundant clock drivers may be required to drive
the CCD input capacitance. Refer to Figure 7 for
details.
2. PR = Pixel Reset (exposure control).
Table 2. # of Clock Drivers Required
DC Biases # Required 1
Regulated? PR 2off PR on
Yes 10 9
No 3 3
1. Refer to Figure 7 for details.
2. PR = Pixel Reset (exposure control).
Table 3. # of DC Biases Required
Antiblooming is always present when biases fall within the
specified operating conditions. By adjusting VSTOR how-
ever, the user has the added flexibility of selecting the anti-
blooming level (the signal level beyond which additional
signal charges are drained away). A higher VSTOR bias re-
sults in a higher antiblooming level.
Transfer
The TCK clock controls the transfer of electrons from the
storage well into two discrete readout registers for alter-
nating odd/even pixel readout. Transfer is from the storage
wells into the CR1 phases of the readout registers. The
readout registers are then used to serially shift the charge
packetstothetwohigh-speedlow-noiseoutputamplifiers.
The two readout registers are pseudo-2-phase buried-
channel CCD shift registers. The CR1x and CR2x phases
are complements of each other. Each of these two phases
hasastorage(CRxS)andabarrier(CRxB)gate.Thestorage
and barrier gates of each phase are clocked in phase (i.e.,
CR1Sis clockedinphase withCR1B,andCR2S isclockedin
phasewith CR2B).Theonlydifferencebetweenthestorage
and barrier phase clocks is the bias levels applied to these
clocks. AC-coupling and then DC-shifting the CRxS phases
will produce the CRxB phases.
The final storage electrode of each readout register is con-
nected separately to CRLAST. CRLAST should be clocked
in phase with CR1.
All CR clocks operate with 50% duty cycle.
Unlike CR1 and CR2, the CRLAST pin is connected to only
twoCCDgates,oneforeachofthetwoCCDshiftregisters
on each side. Consequently, the CRLAST capacitance is
muchsmaller thantheCR1or CR2capacitance.Toprevent
CRLASTfromswitchingmuchfasterthanCR1andCR2,we
recommend that a 100Ωresistor be connected in series
with CRLAST. The CRLAST clock should preferably have a
slower rise and fall time than CR1 and CR2.
Additionaldetailsondrivingthe sensorareprovided onFig-
ure 7.
Output
The signal charge packets from the readout shift registers
are transferred serially from the last readout gate
(CRLAST), over the set gate (VSET), to a floating sense
nodediffusion.Thesetgateisolatesthesensenodediffusion
from the last readout gate and the rest of the readout shift
register. As signal charge accumulates on the floating node
diffusion,thepotentialofthisdiffusiondecreases.Thefloat-
ing node diffusion is connected to the input of a 2.5-stage
low-noise amplifier, producing an output signal voltage on
the amplifier output (OSn). The floating diffusion is cleared
of signal charge by the reset gate (RST) in preparation for
the next signal charge packet. The voltage level of the float-
ingdiffusionaftereachresetisdeterminedbytheoutputre-
set drain voltage (VOD). AC coupling the output is
recommended to eliminate the DC offset.
Each of the output signals (OSn) requires an off-chip load
drawingapproximately8mAofloadcurrent.If the sensor is
running at greater than 35MHz data rate, or if the load ca-
pacitance (CLOAD) is greater than 10pF, larger load current
(upto the 18mAlimit)mayberequired. As theloadcurrent
increases, the amplifier bandwidth increases. The amplifier
can also drive larger capacitive loads when the load current
is larger. We recommend however that just enough band-
width be used since larger bandwidth also results in in-
creased noise.
If an off-chip current load is not available, each of the ampli-
fier outputs (OSn) can be connected to a 1.2kΩload resis-
tor. The use of a passive (resistive) load reduces the
amplifiergain,resultingin lower responsivity and saturation
output signal.
The variations in charge conversion efficiency among the
various outputs of the sensor, along with component varia-
tions in the drive electronics, result in output gain mis-
match. To match outputs, we recommend that the camera
electronics incorporate a gain correction of up to 15%.
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Parameter Unit Min. Max.
Storage Temp °C -20 80
Operating Temp °C -20 60
Voltage on CR1x, CR2x, CRLAST, RST, VSET,
VSTOR, TCK, PR with respect to VBB V -10 18
Voltage on OSn, VDD, VOD, VSS, VPR, VHIGH,
VLOW with respect to VBB V018
Voltage on OSn with respect to VSS V VDD-8 VDD+1
Amplifier Load Current (ILOAD) mA per output 20
WARNING:
Exceeding these values will void product warranty and may damage the device.
Table 4. IL-P1 Absolute Maximum Ratings
CAUTION! These devices are sensitive to damage from electrostatic discharge (ESD). The leads
should be shorted together during storage or handling to prevent damage to the device.
Input Characteristics:
Capacitance to VBB 1Unit Typical
512 1024 2048 4096
from CR1S, CR2S1pF 90 130 220 400
from CR1B, CR2B2pF 100 140 240 440
from CRLAST pF 12 12 12 12
from RST pF 10 10 10 10
from PR pF 40 60 110 200
from TCK pF 70 110 200 370
Output Characteristics:
Output Impedance (ROUT)4Ω180Ωwith ILOAD = 8mA
Amplifier Supply Current (IDD)5mA 36mA with ILOAD = 8mA
DC Output Offset (VOS) 6V 10V with ILOAD = 8mA
Notes:
1. Using 1V pk-pk 1MHz signal with +5V DC offset.
2. The two CR1S pins (pins 6 and 22) are internally connected, as are the two CR2S pins (pins 7 and 23).
3. The two CR1B pins (pins 11 and 28) are not internally connected, nor are the two CR2B pins (pins 12 and 27).
Capacitance values indicated refer to the total capacitance of the two CRxB pins.
4. In general, ROUT (Ω) ~ 520 * (ILOAD)-0.5, ILOAD in mA.
5. In general, IDD (mA) = 2 * (10 + ILOAD), ILOAD in mA.
6. In general, VOFFSET (V) = 0.003 * (ILOAD)2- 0.22 * (ILOAD) + 11.5, ILOAD in mA.
Table 5. IL-P1 Input/Output Characteristics
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Symbol Description Unit Min. Rec. 1Max.
ILOAD 2Load current to each output (OSn) mA 7.5 8.0 18.0
VDD Amplifier supply voltage V 14.0 14.0 15.0
VOD Output reset drain voltage V 11.0 11.3 VDD - 2
VSET Output node set gate voltage V CRLAST offset
+0.5 0 CRLAST offset
+1.0
VSTOR 3Storage well voltage V -1 0 0.2
VPR Pixel reset drain voltage V 13 14 15
VBB Substrate bias V -3 -2 -1
VLOW 4Low bias voltage V VBB 0 0
VHIGH High bias voltage V 13 14 15
VSS Ground Reference V 0
Notes:
1. Selecting a bias that deviates significantly from the recommended value can cause the recommended value of
another bias to fall outside the Min. and Max. bias range. If this occurs, ignore the recommended value and ensure
that each of the biases falls within its own Min. and Max. range.
2. ILOAD needs to be > 10mA only if ƒRST > 35MHz or CLOAD > 10pF.
3. VSTOR may be adjusted to affect the antiblooming level. VSAT decreases by ∼418mV for every 1.0V reduction in
VSTOR.
4. If your implementation uses separate digital and analog grounds, connect VLOW to the digital ground.
Table 6. IL-P1 DC Operating Conditions
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Symbol Description
Unit Min. Rec. Max.
CRx All CR Clocks swing* V 4.5 5.0 6.5
CRxS Readout Register Clocks
(storage phase) offset* V 0 0 0.5
CRxB Readout Register Clocks
(barrier phase) offset V -(CRx swing)+1.5 -3.0 -(CRx swing)+2.5
CRLAST Readout Register Clocks
(last storage phase) offset V CRxB offset+1.5 -0.8 CRxB offset+2.5
RST Reset Clock offset V VOD-RST swing-6.8 -0.5 0
swing V 4.8 5.5 6.5
TCK Transfer Clock offset V VBB 0 0
swing V VSTOR+5.0 8 10
PR Pixel Reset Clock offset V 0.5 1.2 VSTOR+1.5
swing V VSTOR+4.5 8 10
ƒRST Data rate per output MHz 25 40
ƒDATA Effective data rate MHz 50 80
ƒLINE Line rate 0512 kHz 87.3 137.5
1024 46.1 73.1
2048 23.7 37.8
4096 12.0 19.2
Notes:
1. Selecting a bias that deviates significantly from the recommended value
can cause the recommended value of another bias to fall outside the Min.
and Max. bias range. If this occurs, ignore the recommended value and
ensure that each of the biases falls within its own Min. and Max. range.
Table 7. IL-P1 AC Operating Conditions
Offset
Swing
*
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Life SupportApplications
These products are not designed for use in life support appliances,devices,or systems where malfunction of these
products can reasonably be expected to result in personal injury. DALSA customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify DALSA for any damages resulting from such
improper use or sale.
Specification Unit Min. Typ. Max.
Saturation Output Voltage (VSAT) mV 700 900 1100
rms Noise mV 0.28 0.31
Wavelength of Peak Responsivity nm 700
Peak Responsivity V/(µJ/cm2) 11.0 12.0 13.5
Dynamic Range 2250:1 3200:1 3900:1
Charge Conversion Efficiency (CCE) µV/e-4.7 5.0 5.3
Noise Equivalent Exposure (NEE) pJ/cm221 23 28
Saturation Equivalent Exposure (SEE) nJ/cm252 75
Full Well Capacity ke-132 180
Fixed Pattern Noise (FPN) 1,2 pk-pk
PR exposure control disabled mV
mV 0.5
2.0 1.0
5.0
Photoresponse Non-Uniformity (PRNU) 3,4
%OS
PR exposure control disabled 8 pixel local neighborhood 2.2 6.0
Global 3.5 8.5
PR exposure control enabled 8 pixel local neighborhood 2.5 6.5
Global 3.8 8.8
Charge Transfer Efficiency (CTE) (readout register) 0.99999 0.999999
First Field Lag 5mV 11.5
Dark Signal, Integration time = 84µs mV 0.15 0.5
Notes:
1. Maximum peak-to-peak variation of all outputs.
2. Due to its general purpose design, DALSA's camera and sensor evaluation hardware provides an output that cannot
be used to directly measure low FPN.
3. The peak-to-peak variation is measured at ~50% SEE.
4. With output gain mismatch correction.
5. Lag is measured at VSAT with
LINE = 10kHz.
Test Conditions:
n
Operating temperature = 35°C.
n
ƒRST = data rate per output = 25MHz.
n
ILOAD = 8mA.
n
CLOAD = 10pF.
n
Tungsten halogen light source, black body color temperature 3200K, filtered with 750nm IR cutoff filter.
n
See Sensor Measurement Definitions (doc# 03-36-00149) for specification definitions.
Table 8. IL-P1 Performance Specifications
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Responsivity [V/( J/cm )]µ2
Wavelength (nm)
0
2
1000
800600400 500 700 900
4
6
10
12
14
8
Responsivity
40 W/cmµ2
400 W/cmµ2100 W/cmµ2
100
(%)
Signal Output
Saturation Output
0
20
40
60
80
IntegrationTime (ms) 1.00.80.60.40.2
Output vs.IntegrationTime
(@700nm)
Figure 2. Performance Measurements
Symbol Description Unit Min. Rec. Max.
tCR Period of CRx clocks
t1Integration time (PR disabled)
t2Integration time (PR enabled)
t3TCK to first valid pixel pixels 23 23
t4Overclock pixels pixels 0 23
t5CRxB falling edge to CRxS falling edge ns 0 0 0.25tCR
t6CR1B falling edge to CRLAST falling edge ns 0 0 0.25tCR
t7TCK high overlap with CR1S high ns 200 300
t8TCK falling edge to CR1S falling edge ns 2
t9CRLAST rising to RST rising edge ns 0 0.5tCR - t11 0.5tCR - t11
t10 RST falling edge to CRLAST falling edge ns 0 0 0.5tCR-t11
t11 RST pulse width (FWHM)1ns 5 5 0.25tCR
t12 CR1x and CR2x rise and fall time ns 2 5 0.25tCR
t13 CRLAST rise and fall time ns t12 t12 + 1 0.25tCR
Notes:
1. Full Width Half Maximum
Table 9. IL-P1 Timing Parameters
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TCK
RST
OSn
CR2x
CRLAST
CR1x
Line 1 Line 2
Active Pixels Line 3
t1
PR t
tt
2
33
t4
Figure 3. IL-P1 Overall Timing
TCK
RST
CR2S
CR2B
CRLAST
CR1S
CR1B t5
t5
t6t7t9
t10
t8
tCR
t12 t12
t11
t13 t13
OSn Overclock
Pixel Overclock
Pixel Isolation
Pixel Isolation
Pixel
Figure 4. IL-P1 Detailed Readout Register Timing
n+
n+ n+
VD
D
VODRST
VSETCRLASTCR1BCR2SCR2S CR2BCR2B
TCK
PRVPR Pixel
VSTOR
CR1SCR1S CR1BCR1B
OS
VSS
Figure 5. IL-P1 Gate Structure Diagram
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RST
TCK
OS1
OS2
CR2x
CRLAST
CR1x
I
S
OC
Isolation Pixel.
Light-Shielded Pixel.
Overclock Pixel.
Sample video
I1
I1
I5
I5
S1
S1
Pixel
1
Pixel
2
Pixel
3
Pixel
4
Pixel
N-3
Pixel
N-2
Pixel
N-1
Pixel
N
S16
S16
OC
OC
OC
OC
OC
OC
I5 I8 I9
I9
S17
S17
S32
S32
I10
I10
I14
I14
I5 I8
I6
I6
Figure 6. IL-P1 Readout Register Timing
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High-speed
Low-voltage
Clock Drivers
Low-speed
High-voltage
Clock Drivers
Regulated
DC Bias Non-Critical
DC Bias Possible
Interface
Circuitry
CRLAST
CR1S
CR1B,
CR2B
CR2S
RST
TCK
PR
VPR
VLOW
VHIGH
VOD
VDD
VSS
VBB
VSET
VSTOR
OSx
(PIN 5)5
(PINS 6,22)3,4
(PINS 11,28)3,4
(PINS 12,27)4
(PINS 7,23)3,4
(PIN 32)
(PIN 8)
(PIN 9)
(PINS 14,15,17,19)
(PIN 31)
(PINS 2,18)
(PINS 25,29)
(PINS 20,21,26)
(PIN 4)
(PIN 24)
(PINS 3,30)
(PINS 1,13)
(PIN 10)
VPR
VLOW
VHIGH
VDD6
VSS
VBB
VSET
ILOAD
BIAS
OSx Buffer
VOD
CR2 =
2CR1
CR11
RST
TCK
PR
(with
exposure
control)
PR
(without
exposure
control)
CRLAST
BIAS
CRxB-
BIAS
VSTOR7
10kΩ
10kΩ
10kΩ
1kΩ
100nF
100nF
100nF
10kΩ
IL-P1
511Ω
100Ω
Figure 7. IL-P1 Sensor Operation Connections
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1. Clock drivers are designed to drive only up to a maximum capacitance (CMAX) at a given clock frequency. If the total
capacitances of CRLAST, CR1S, and CR1B (see Table 5) exceed CMAX, more than one CR1 driver is required.
2. Clock drivers are designed to drive only up to a maximum capacitance (CMAX) at a given clock frequency. If the total
capacitances of CR2S and CR2B (see Table 5) exceed CMAX, more than one CR2 driver is required.
3. Both pins should be connected to clock drivers, though not necessarily to the same clock driver. If more than one
clock driver is used, it is acceptable to drive each pin from separate drivers.
4. Although the sensors are sufficiently robust that the rise and fall times of CRxS and CRxB do not need to be very
closely matched, performance is more optimal, particularly with the 4096-pixel part, if attempts are made to match
the CRxS and CRxB rise and fall times. If more than one CRx clock driver is used, time constants are more closely
matched if the sensor is driven using either one of the following configurations:
a. Drive the CRxS pins with n CRx drivers. Tie the CRxB pins together. Drive the CRxB pins with a separate set
of n CRx drivers.
b. Drive the CRxS pins with 2n CRx drivers. Drive each CRxB pin separately with separate sets of n CRx
drivers.
c. Connect a 10Ωresistor in series with CRxS. Drive the CRxS pins with n CRx clock drivers. Connect a 20Ω
resistor in series with each CRxB pin. Drive each CRxB pin with separate sets of n CRx drivers.
Note that the CRxS pins are internally connected together, while the CRxB pins are not.
5. CRLAST should not have a fall time that is much faster than the fall time of CR1B. Unlike CR1B however, the
CRLAST pin is connected to only two CCD gates, one for each of the CCD shift registers. Consequently, the
CRLAST capacitance is much smaller than the CR2B capacitance. This is not an issue if the CRLAST clock is tapped
from CR1. However, if CRLAST is being driven from a separate driver, we recommend that a 150Ωresistor be
connected in series with CRLAST.
6. Need to source IDD = 2 * (10 + ILOAD) mA.
7. May have an optional antiblooming level adjustment.
Notes to Figure 7.
ISO 9001DALSA maintains a registered quality system meeting the ISO 9001 standard.
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Pin 1
Pin 32
Pin 16
Pin 17
1.250±0.012 [31.8±0.3]
1.050±0.005 [26.7±0.1]
0.070±0.005 [1.8±0.1]
0.495±0.005 [12.6±0.1]
0.050±0.010 [1.3±0.3]
0.500±0.010 [12.7±0.3]
0.140±0.020 [3.6±0.5]
0.018±0.002 [0.5±0.1]
0.020±0.002 [0.5±0.1]
0.038±0.002 [1.0±0.1]
0.010±0.001 [0.3±0.0]
0.030±0.003 [0.8±0.1] 0.040±0.004 [1.0±0.1]
0.110±0.011 [2.8±0.3]
0.625±0.010[15.9±0.3]
0.100±0.010[2.5±0.3]
0.248±0.002 [6.3±0.1]
NOTE: THE DIE IS PLACED INTHE MIDDLE OFTHE
PACKAGE ±0.010[±0.3]
0.119 [3.0]
0.015±0.002 [0.4±0.1]
UNITS:IN.[mm]
Figure 8. IL-P1 Package Dimensions
0512
Pin 1
Pin 32
Pin 16
Pin 17
1.250±0.012 [31.8±0.3]
1.050±0.005 [26.7±0.1]
0.070±0.005 [1.8±0.1]
0.495±0.005 [12.6±0.1]
0.050±0.010 [1.3±0.3]
0.500±0.010 [12.7±0.3]
0.140±0.020 [3.6±0.5]
0.018±0.002 [0.5±0.1]
0.020±0.002 [0.5±0.1]
0.038±0.002 [1.0±0.1]
0.010±0.001 [0.3±0.0]
0.030±0.003 [0.8±0.1] 0.040±0.004 [1.0±0.1]
0.110±0.011 [2.8±0.3]
0.625±0.010[15.9±0.3]
0.100±0.010[2.5±0.3]
0.248±0.002 [6.3±0.1]
NOTE: THE DIE IS PLACED INTHE MIDDLE OFTHE
PACKAGE ±0.010[±0.3]
0.119 [3.0]
0.015±0.002 [0.4±0.1]
UNITS:IN.[mm]
1024
14
DALSA INC.: Phone: 519-886-6000 Fax: 519-886-8023 03-36-00134-05
ISO 9001 DALSA EUROPE: Phone: +49-8142-46770 Fax: +49-8142-467746 www.dalsa.com
IL-P1
Line Scan Sensors For product information and updates visitwww.dalsa.com
Pin 32 Pin 17
Pin 16
Pin 1
PACKAGE ±0.010[±0.3]
NOTE:THE DIE IS PLACED INTHE MIDDLE OFTHE
0.625±0.010[15.9±0.3]
0.100±0.010[2.5±0.3]
0.500±0.010 [12.7±0.3]
0.050±0.010 [1.3±0.3]
0.070±0.002 [1.8±0.1]
1.050±0.002 [26.7±0.1]
0.495±0.002 [12.6±0.1]
0.248±0.010 [6.3±0.3]
0.140±0.020 [3.6±0.5]
1.250±0.012 [31.8±0.3]
0.018±0.002[0.5±0.1]
0.038±0.002 [1.0±0.1]
0.020±0.002 [0.5±0.1]
0.020±0.001 [0.5±0.0]
0.030±0.003 [0.8±0.1] 0.040±0.004 [1.0±0.1]
0.110±0.011 [2.8±0.3]
0.119 [3.0]
0.015±0.002 [0.4±0.1]
UNITS:IN.[mm]
Pin 25
Pin 1 Pin 8
Pin 32 Pin 17
Pin 16Pin 9
Pin 24
PACKAGE ±0.010[±0.3]
NOTE:THE DIE IS PLACED INTHE MIDDLE OFTHE
0.043±0.010
[1.1±0.3] 1.128±0.010 [28.7±0.3]
0.248±0.010
[6.3±0.3]
0.500±0.010
[12.7±0.3]
0.070±0.005 [1.8±0.1]2.170±0.005 [55.1±0.1]
0.495±0.005
[12.6±0.1]
0.050±0.010 [1.3±0.3]
0.140±0.020 [3.6±0.5]
0.018±0.002
[0.5±0.1]
0.038±0.002 [1.0±0.1]
0.020±0.002 [0.5±0.1]
0.010±0.001 [0.3±0.0]
0.030±0.003 [0.8±0.1] 0.040±0.004 [1.0±0.
0.110±0.011 [2.8±0.
3
2.256±0.012 [57.3±0.3]
0.015±0.002 [0.4±0.1]
0.119 [3.0]
UNITS:IN.[mm]
2048
4096
