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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM53602-Q1

LM53603-Q1

SNVSA42B –JUNE 2015–REVISED MAY 2016

LM53603-Q1 (3 A), LM53602-Q1 (2 A) 3.5 V to 36 V Wide-V

Synchronous 2.1 MHz Step-

Down Converters for Automotive Applications

1 Features

1• The LM53603-Q1, LM53602-Q1 are available as

AEC-Q1-Qualified Automotive Grade Products

With Following Results:

– Device Temperature Grade 1: -40°C to +125°C

Ambient Operating Range

– Device HBM ESD Classification Level 1C

– Device CDM ESD Classification Level C4B

• 3 A or 2 A maximum load current

• Input Voltage Range from 3.5 V to 36 V:

Transients to 42 V

• Output Voltage Options: 5 V, 3.3 V, ADJ

• 2.1 MHz Fixed Switching Frequency

• ±2% Output Voltage Tolerance

• –40°C to 150°C Junction Temperature Range

• 1.7 µA Shutdown Current (typical)

• 24 µA Input Supply Current at No Load (typical)

• No external Feed-back Divider Required for 5 V or

3.3 V output

• Reset Output With Filter and Delay

• Automatic Light Load Mode for Improved

Efficiency

• User-Selectable Forced PWM mode (FPWM)

• Built-in Loop Compensation, Soft-start, Current

Limit, Thermal Shutdown, UVLO, and External

Frequency Synchronization

• Thermally Enhanced 16-lead Package:

5mmx4.4mmx1mm

2 Applications

• Navigation/GPS

• Instrument Cluster

• ADAS, Infotainment, HUD

3 Description

The LM53603-Q1, LM53602-Q1 buck regulators are

specifically designed for automotive applications,

providing an output voltage of 5 V or 3.3 V (with ADJ

option) at 3 A or 2 A, from an input voltage of up to

36 V. Advanced high-speed circuitry allows the

device to regulate from an input of up to 20 V, while

providing an output of 5 V at a switching frequency of

2.1 MHz. The innovative architecture allows the

device to regulate a 3.3 V output from an input

voltage of only 3.5 V. All aspects of this product are

optimized for the automotive customer. An input

voltage range up to 36 V, with transient tolerance up

to 42 V, eases input surge protection design. An open

drain reset output, with filtering and delay, provides a

true indication of system status. This feature negates

the requirement for an additional supervisory

component, saving cost and board space. Seamless

transition between PWM and PFM modes, along with

a no-load operating current of only 24 µA, ensures

high efficiency and superior transient response at all

loads.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

LM53603-Q1

LM53602-Q1 HTSSOP (16) 5.00 mm x 4.40 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Simplified Schematic Automotive Power Supply with 5 V, 3 A Output

LM53602-Q1

LM53603-Q1

SNVSA42B –JUNE 2015–REVISED MAY 2016

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Device Comparison Table..................................... 3

6 Pin Configuration and Functions......................... 3

7 Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 4

7.2 ESD Ratings.............................................................. 4

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 6

7.6 System Characteristics ............................................. 7

7.7 Timing Requirements................................................ 8

7.8 Typical Characteristics.............................................. 9

8 Detailed Description............................................ 10

8.1 Overview ................................................................ 10

8.2 Functional Block Diagram....................................... 10

8.3 Feature Description................................................. 11

8.4 Device Functional Modes........................................ 15

9 Application and Implementation ........................ 18

9.1 Application Information............................................ 18

9.2 Typical Applications ................................................ 18

9.3 Do's and Don't's...................................................... 28

10 Power Supply Recommendations ..................... 29

11 Layout................................................................... 30

11.1 Layout Guidelines ................................................. 30

11.2 Layout Example .................................................... 32

12 Device and Documentation Support................. 33

12.1 Device Support .................................................... 33

12.2 Documentation Support ........................................ 33

12.3 Related Links ........................................................ 33

12.4 Community Resources.......................................... 33

12.5 Trademarks........................................................... 34

12.6 Electrostatic Discharge Caution............................ 34

12.7 Glossary................................................................ 34

13 Mechanical, Packaging, and Orderable

Information........................................................... 34

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (June 2015) to Revision B Page

• Added Automotive Features .................................................................................................................................................. 1

• changed representation of RESET threshold for clarity (physical parameter unchanged) .................................................... 6

• added CFF recommendation table for ADJ version ............................................................................................................ 20

• Corrected saturation current for some of the recommended inductors in the table "Recommended Inductors" ................ 22

• Added recommendation for CVCC: use of X7R component is highly recommended ......................................................... 22

• Added Cboot recommended rating of 10V in the CBOOT section ...................................................................................... 22

• added power dissipation curve for 5Vout and 3.3Vout ........................................................................................................ 23

• added layout recommendation for CVCC and CBIAS ......................................................................................................... 30

Changes from Original (June 2015) to Revision A Page

• Changed - Thermal Information, Board drawing on Page 1, Power Dissipation curves, RESET thresholds, maximum

recommended distances for VCC and Bias capacitors and added in a table for Cff. ........................................................... 1

• Changed product preview to full data sheet .......................................................................................................................... 1

PGND

VIN

CBOOT

VCC

BIAS

SYNC

FPWM

8 9

AGND

N/C

RESET

(17)

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5 Device Comparison Table

PART NUMBER PACKAGE MAXIMUM OUTPUT CURRENT

LM53603-Q1 HTSSOP (16) 3 A

LM53602-Q1 HTSSOP (16) 2 A

(1) O = Output, I = Input, G = Ground, P = Power

6 Pin Configuration and Functions

PWP Package

16-Lead HTSSOP

Top View

Pin Functions

PIN I/O(1) DESCRIPTION

NAME NO.

SW 1,2 P Regulator switch node. Connect to power inductor. Connect pins 1 and 2 directly together at the PCB.

CBOOT 3 P Bootstrap supply input for gate drivers. Connect a high quality 470 nF capacitor from this pin to SW.

VCC 4 O Internal 3.15 V regulator output. Used as supply to internal control circuits. Do not connect to any

external loads. Can be used as logic supply for control inputs. Connect a high quality 3.3 µF capacitor

from this pin to GND.

BIAS 5 P Input to internal voltage regulator. Connect to output voltage point. Do not ground. Connect a high

quality 0.1 µF capacitor from this pin to GND.

SYNC 6 I Synchronization input to regulator. Used to synchronize the regulator switching frequency to the system

clock. When not used connect to GND; do not float.

FPWM 7 I Mode control input to regulator. High = forced PWM (FPWM). Low = auto mode; automatic transition

between PFM and PWM. Do not float.

RESET 8 O Open drain reset output. Connect to suitable voltage supply through a current limiting resistor. High =

power OK. Low = fault. RESET will go low when EN = low.

FB 9 I Feedback input to regulator. Connect to output voltage sense point for fixed 5 V and 3.3 V output.

Connect to feedback divider tap point for ADJ option. Do not float or ground.

AGND 10 G Analog ground for regulator and system. All electrical parameters are measured with respect to this pin.

Connect to EP and PGND on PCB.

EN 11 I Enable input to the regulator. High = ON. Low = OFF. Can be connected directly to VIN. Do not float.

VIN 12, 13 P Input supply to the regulator. Connect a high quality bypass capacitor(s) from this pin to PGND.

Connect pins 12 and 13 directly together at the PCB.

N/C 14 - This pin has no connection to the device.

PGND 15, 16 G Power ground to internal low side MOSFET. Connect to AGND and system ground. Connect pins 15

and 16 directly together at the PCB.

EP 17 G Exposed die attach paddle. Connect to ground plane for adequate heat sinking and noise reduction.

LM53602-Q1

LM53603-Q1

SNVSA42B –JUNE 2015–REVISED MAY 2016

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Values given

are D.C.

(2) A maximum of 42 V can be sustained at this pin for a duration of ≤500 ms at a duty cycle of ≤0.01%.

(3) Transients on this pin, not exceeding –3 V or +40 V, can be tolerated for a duration of ≤100 ns. For transients between 40 V and 42 V,

see note (2).

(4) Positive current flows into this pin.

(5) A transient voltage of ±2 V can be sustained for ≤1 µs.

7 Specifications

7.1 Absolute Maximum Ratings

over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted)(1)

PARAMETER MIN MAX UNIT

VIN to AGND, PGND(2) –0.3 40 V

SW to AGND, PGND(3) –0.3 VIN + 0.3 V

CBOOT to SW –0.3 3.6 V

EN to AGND, PGND(2) –0.3 40 V

BIAS to AGND, PGND –0.3 16 V

FB to AGND, PGND : fixed 5 V and 3.3 V –0.3 16 V

FB to AGND, PGND : ADJ –0.3 5.5 V

RESET to AGND, PGND –0.3 8 V

SYNC, FPWM, to AGND, PGND –0.3 5.5 V

VCC to AGND, PGND –0.3 4.2 V

RESET Pin Current(4) –0.1 1.2 mA

AGND to PGND(5) –0.3 0.3 V

Storage temperature, Tstg –40 150 °C

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic discharge

Human-body model (HBM), per AEC Q100-002(1) VIN, SW, CBOOT ±1500

EN, BIAS, RESET, FB,

SYNC, PWM, VCC ±2500

Charged-device model (CDM), per AEC Q100-011 CBOOT, VCC, BIAS, SYNC,

FPWM, EN, VIN ±750

SW, RESET, FB, PGND ±500

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) See System Characteristics for details of input voltage range.

(3) Under no conditions should the output voltage be allowed to fall below zero volts.

(4) The maximum recommended output voltage is 6 V. An extended output voltage range to 10 V is possible with changes to the typical

application schematic. Also, some system specifications will not be achieved for output voltages greater than 6 V. Consult the factory for

further information.

(5) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

7.3 Recommended Operating Conditions

over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted)(1)

MIN NOM MAX UNIT

Input voltage(2) 3.9 36 V

Output voltage : Fixed 5 V(3) 0 5 V

Output voltage : Fixed 3.3 V(3) 0 3.3 V

Output voltage adjustment range: ADJ(3)(4) 3.3 6 V

Output current for LM53603-Q1 0 3 A

Output current for LM53602-Q1 0 2 A

RESET pin current 0 1 mA

Operating junction temperature(5) –40 150 °C

(1) The values given in this table are only valid for comparison with other packages and cannot be used for design purposes. These values

were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do not represent the performance

obtained in an actual application. For design information please see the Maximum Ambient Temperature section. For more information

about traditional and new thermal metrics, see the "Semiconductor and IC Package Thermal Metrics application report, SPRA953, and

the Using New Thermal Metrics applications report, SB VA025.

7.4 Thermal Information

THERMAL METRIC(1)

LM53603-Q1,

LM63602-Q1 UNIT

PWP (HTSSOP)

16 PINS

RθJA Junction-to-ambient thermal resistance 42.5 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 22.6 °C/W

RθJB Junction-to-board thermal resistance 16.2 °C/W

ψJT Junction-to-top characterization parameter 0.6 °C/W

ψJB Junction-to-board characterization parameter 16.0 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance 1.1 °C/W

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SNVSA42B –JUNE 2015–REVISED MAY 2016

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(1) MIN and MAX limits are 100% production tested at 25°C. Limits over the operating temperature range are verified through correlation

using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

(2) This is the input voltage at which the device will start to operate ("rising"). The device will shutdown when the input voltage goes below

this value minus the hysteresis.

(3) This is the current used by the device, open loop. It does not represent the total input current of the system when in regulation. See

"Isupply" in System Characteristics

(4) The FB pin is set to 5.5 V for this test.

(5) Below this voltage on the EN input, the device will shut down completely.

7.5 Electrical Characteristics

Limits apply to the recommended operating junction temperature range of –40°C to 150°C, unless otherwise noted. Minimum

and maximum limits are verified through test, design, or statistical correlation. Typical values represent the most likely

parametric norm at TJ= 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions

apply: VIN = 13.5 V.

PARAMETER TEST CONDITIONS MIN(1) TYP MAX(1) UNIT

VFB Initial reference voltage accuracy

for 5 V and 3.3 V options

VIN = 3.8 V to 36 V, FPWM,

TJ= 25°C –1% 1%

VIN = 3.8 V to 36 V, FPWM –1.25% 1.25%

VREF Reference voltage for ADJ option

VIN = 3.8 V to 36 V, FPWM,

TJ= 25°C 0.993 1 1.007 V

VIN = 3.8 V to 36 V, FPWM,

TJ= -40°C to 125°C 0.99 1 1.01

VIN-operate Minimum input voltage to

operate(2)

Rising 3.2 3.95 VFalling 2.9 3.55

Hysteresis, below 0.34

IQOperating quiescent current;

measured at VIN pin.(3)(4) VBIAS = 5 V,

TJ= -40°C to 125°C 8 13 µA

ISD Shutdown quiescent current;

measured at VIN pin.

EN ≤0.4 V, TJ= 25°C 1.7 µAEN ≤0.4 V, TJ= 85°C 2.8

EN ≤0.4 V, TJ= 125°C 3.5

IBCurrent into the BIAS pin(4) VBIAS = 5 V, FPWM = 3.3 V 47 78 µA

IEN Current into EN pin VIN = VEN = 13.5 V 2.3 µA

RFB Resistance from FB to AGND 5 V option 1.5 MΩ

Resistance from FB to AGND 3.3 V option 1 MΩ

IFB Bias current into FB pin ADJ option 10 nA

VRESET

RESET upper threshold voltage Rising, % of nominal Vout 105% 107% 110%

RESET lower threshold voltage Falling, % of nominal Vout 92% 94% 96.5%

RESET lower threshold voltage

with respect to output voltage Falling, % actual Vout 94.5% 95.7%

VRESET-

Hyst RESET hysteresis as a percent of

output voltage set point 1.5%

VMIN Minimum input voltage for proper

RESET function 50 µA pull-up to RESET pin, VEN = 0 V,

TJ= 25°C 1.5 V

VOL Low level RESET pin output

voltage

50 µA pull-up to RESET pin, Vin = 1.5

V, EN = 0 V 0.4

0.5 mA pull-up to RESET pin, Vin = 13.5

V, EN = 0 V 0.4

1 mA pull-up to RESET pin, Vin = 13.5

V, EN = 3.3 V 0.4

VEN Enable input threshold voltage Rising 1.7 2 V

Hysteresis, below 0.45 0.55

VEN-off Enable input threshold for full

shutdown(5) EN input voltage required for complete

shutdown of the regulator, falling. 0.8 V

VLOGIC Logic input levels on FPWM and

SYNC pins VIH 1.5 V

VIL 0.4

IHS High side switch current limit LM53603-Q1 4.5 6.2 A

LM53602-Q1 2.4 4.4

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Electrical Characteristics (continued)

Limits apply to the recommended operating junction temperature range of –40°C to 150°C, unless otherwise noted. Minimum

and maximum limits are verified through test, design, or statistical correlation. Typical values represent the most likely

parametric norm at TJ= 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions

apply: VIN = 13.5 V.

PARAMETER TEST CONDITIONS MIN(1) TYP MAX(1) UNIT

(6) See the Current Limit section for an explanation of valley current limit.

ILS Low side switch current limit(6) LM53603-Q1 3 3.6 4.3 A

LM53602-Q1 2 2.4 2.8

IZC Zero-cross current limit FPWM = 0 V -0.02 A

INEG Negative current limit FPWM = 3.3 V -1.5 A

Rdson Power switch on-resistance High side MOSFET resistance 135 290 mΩ

Low side MOSFET resistance 60 125

FSW Switching frequency VIN = 3.8 V to 18 V 1.85 2.1 2.35 MHz

VIN = 36 V 1.2

FSYNC Synchronizing frequency range 1.9 2.1 2.3 MHz

VCC Internal VCC voltage VBIAS = 3.3 V 3.15 V

TSD Thermal shutdown thresholds Rising 162 178 °C

Hysteresis, below 18

(1) This parameter is valid once the input voltage has risen above VIN-operate and the device has started up.

(2) Includes current into the EN pin. See Input Supply Current section.

7.6 System Characteristics

The following specifications apply only to the typical application circuit, shown in Figure 15 with nominal component values.

Typical values represent the most likely parametric norm at TJ= 25°C, and are provided for reference purposes only. The

parameters in this table are not guaranteed.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIN-MIN Minimum input voltage for Vout to

stay within ±2% of regulation. (1) VOUT = 3.3 V, IOUT = 3 A 3.9 V

VOUT = 3.3 V, IOUT = 1 A 3.55

Regulation

Line Regulation VOUT = 5 V, VIN = 8 V to 36 V, IOUT = 3 A 7 mV

VOUT = 3.3 V, VIN = 6 V to 36 V, IOUT = 3

Load Regulation : Auto Mode

VOUT = 5 V, VIN = 12 V, IOUT = 10 µA to 3

A77 mV

VOUT = 3.3 V, VIN = 12 V, IOUT = 10 µA to

3 A 53

Load Regulation : FPWM Mode

VOUT = 5 V, VIN = 12 V, IOUT = 10 µA to 3

A12 mV

VOUT = 3.3 V, VIN = 12 V, IOUT = 10 µA to

3 A 9

ISUPPLY Input supply current when in

regulation.(2) VIN = 13.5 V, VOUT = 3.3 V, IOUT = 0 A 24 µA

VIN = 13.5 V, VOUT = 5 V, IOUT = 0 A 34

VDROP Dropout voltage (VIN – VOUT)

5 V Option:

VOUT = 4.95 V, IOUT = 3 A, FSW < 1.85

MHz 0.7

5 V Option:

VOUT = 5 V, IOUT = 3 A, FSW = 1.85 MHz 1.8

3.3 V Option:

VOUT = 3.27 V, IOUT = 3 A, FSW < 1.85

MHz 0.65

3.3 V Option:

VOUT = 3.3 V, IOUT = 3 A, FSW = 1.85

MHz 1.8

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(1) This is the time from the rising edge of EN to the time that the soft-start ramp begins.

7.7 Timing Requirements

Limits apply to the recommended operating junction temperature range of –40°C to 150°C, unless otherwise noted. Minimum

and maximum limits are verified through test, design, or statistical correlation. Typical values represent the most likely

parametric norm at TJ= 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions

apply: VIN = 13.5 V. MIN NOM MAX UNIT

TON Minimum switch on-time, VIN = 20 V 50 80 ns

TOFF Minimum switch off-time, VIN = 3.8 V 125 200 ns

TRESET-act Delay time to RESET high signal 2 3 4 ms

TRESET-filter Glitch filter time for RESET function 12 25 45 µs

TSS Soft-start time 1 2 3 ms

TEN Turn-on delay, CVCC = 1 µF, Tj=25 °C(1) 0.7 0.8 ms

TWShort circuit wait time. ("Hiccup" time) 5.5 ms

Input Voltage (V)

Short Circuit Current (A)

0 5 10 15 20 25 30 35 40

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

D006

-40°C

27°C

125°C

Input Voltage (V)

Shutdown Current (µA)

0 5 10 15 20 25 30 35 40

D003

-40°C

25°C

125°C

Input Voltage (V)

Peak Current Limit (A)

0 5 10 15 20 25 30 35 40

D004

-40°C

27°C

125°C

Input Voltage (V)

Valley Current Limit (A)

0 5 10 15 20 25 30 35 40

3.05

3.1

3.15

3.2

3.25

3.3

3.35

3.4

3.45

3.5

D005

-40°C

27°C

125°C

Temperature (°C)

Refrence Voltage (V)

-60 -40 -20 0 20 40 60 80 100 120 140

0.98

0.985

0.99

0.995

1.005

1.01

1.015

1.02

D001

Temperature (°C)

Frequency (MHz)

-60 -40 -20 0 20 40 60 80 100 120 140

1.8

1.85

1.9

1.95

2.05

2.1

2.15

2.2

D002

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7.8 Typical Characteristics

Unless otherwise specified the following conditions apply: VIN = 12 V, TA= 25°C. Specified temperatures are ambient.

Figure 1. Reference Voltage for ADJ Device Figure 2. Switching Frequency

Figure 3. High Side Peak Current Limit for LM53603-Q1 Figure 4. Low Side Valley Current Limit for LM53603-Q1

Figure 5. Short Circuit Output Current for LM53603-Q1 Figure 6. Shutdown Current

CONTROL

LOGIC DRIVER

HS CURRENT

SENSE

LS CURRENT

SENSE

OSCILLATOR

PWM

COMP.

ERROR

AMPLIFIER

MODE

LOGIC

RESET

CONTROL

VIN

PGND

FPWM

INT. REG.

BIAS

BIASVCC

CBOOT

SYNC

AGND

* = Not used in -ADJ

RESET

1.0V

Reference



ENABLE

LOGIC

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8 Detailed Description

8.1 Overview

The LM5360x family of devices are synchronous current mode buck regulators designed specifically for the

automotive market. The regulator automatically switches between PWM and PFM depending on load. At heavy

loads the device operates in PWM at a switching frequency of 2.1 MHz. The regulator's oscillator can also be

synchronized to an external system clock. At input voltages above about 20 V, the switching frequency reduces

to maintain regulation during conditions of abnormally high battery voltage. At light loads the mode changes to

PFM, with diode emulation allowing DCM. This reduces input supply current and keeps the efficiency high. The

user can also choose to lock the mode in PWM (FPWM) so that the switching frequency remains constant

regardless of load.

A RESET flag is provided to indicate when the output voltage is near its regulation point. This feature includes

filtering and a delay before asserting. This helps to prevent false flag operation during output voltage transients.

Please note that, throughout this data sheet, references to the LM53603-Q1 apply equally to the LM53602-Q1.

The difference between the two devices is the maximum output current and specified MOSFET current limits.

8.2 Functional Block Diagram

VOUT

RESET

High = Power Good

Low = Fault

94%

93%

107%

106%

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8.3 Feature Description

8.3.1 RESET Flag Output

The RESET function, built-in to the LM53603-Q1, has special features not found in the ordinary power-good

function. A glitch filter prevents false flag operation for short excursions in the output voltage, such as during line

and load transients. Furthermore, there is a delay between the point at which the output voltage is within

specified limits and the flag asserts "power-good". Since the RESET comparator and the regulation loop share

the same reference, the thresholds will track with the output voltage. This allows the LM53603-Q1 to be specified

with a 96.5% maximum threshold, while at the same time specifying a 95% threshold with respect to the actual

output voltage for that device. This allows tighter tolerance than is possible with an external supervisor device.

The net result is a more accurate power-good function while expanding the system allowance for transients, etc.

RESET operation can best be understood by reference to Figure 7 and Figure 8. The values for the various filter

and delay times can be found in the Timing Requirements table. Output voltage excursions lasting less than

TRESET-filter, will not trip RESET. Once the output voltage is within the prescribed limits, a delay of TRESET-act is

imposed before RESET goes high.

This output consists of an open drain NMOS; requiring an external pull-up resistor to a suitable logic supply. It

can also be pulled-up to either VCC or VOUT, through an appropriate resistor, as desired. If this function is not

needed, the pin should be left floating or grounded. When EN is pulled low, the flag output will also be forced

low. With EN low, RESET will remain valid as long as the input voltage is ≥1.5 V. The maximum current into this

pin should be limited to 1 mA, while the maximum voltage should be less than 8 V.

Figure 7. Static RESET Operation

94%

VOUT

93%

RESET

Treset_act Treset_act

< Treset_filter

Treset_filter

Glitches do not cause false operation nor reset timer

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Feature Description (continued)

Figure 8. RESET Timing Behavior

8.3.2 Enable and Start-up

Start-up and shutdown of the LM53603-Q1 are controlled by the EN input. Applying a voltage of ≥2V will activate

the device, while a voltage of ≤0.8V is required to shut it down. The EN input may also be connected directly to

the input voltage supply, if this feature is not needed. This input must not be left floating. The LM53603-Q1

utilizes a reference based soft-start, that prevents output voltage overshoots and large inrush currents as the

regulator is starting-up. A typical start-up waveform is shown in Figure 9 along with typical timings.

 

OUT

OUTIN

max

OUT V

LF2 VV

II ˜

˜˜





2 ms/div

Inductor Current

500mA/div

RESET

VOUT

TSS

TEN

1ms/div

Treset_act

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Feature Description (continued)

Figure 9. Typical Start-up Waveform

8.3.3 Current Limit

The LM53603-Q1 incorporates valley current limit for normal overloads and for short circuit protection. In

addition, the low side switch is also protected from excessive negative current when the device is in FPWM

mode. Finally, a high side peak current limit is employed for protection of the top NMOS FET.

During overloads the low side current limit, ILS (see Electrical Characteristics), determines the maximum load

current that the LM53603-Q1 can supply. When the low side switch turns on, the inductor current begins to ramp

down. If the current does not fall below ILS , before the next turn-on cycle, then that cycle is skipped and the low

side FET is left on until the current falls below ILS. This is somewhat different than the more typical peak current

limit, and results in Equation 1 for the maximum load current.

(1)

If the above situation persists for more than about 64 clock cycles, the device turns off both high and low side

switches for approximately 5.5 ms (see TWin Timing Requirements). If the overload is still present after the

"hiccup" time, another 64 cycles is counted and the process is repeated. If the current limit is not tripped for two

consecutive clock cycles, the counter is reset. Figure 10 shows the inductor current with a hard short on the

output. The "hiccup" time allows the inductor current to fall to zero, resetting the inductor volt-second balance.

This is the method used for short circuit protection and keeps the power dissipation low during a fault. Of course

the output current is greatly reduced in this condition (see Typical Characteristics). A typical short circuit transient

and recovery is shown in Figure 11.

§˜



OUT

ENQIN R

III

2 ms/div

Iinductor, 500mA/div

2 ms/div1ms/div

VOUT, 2V/div

Iinductor, 2A/div

5ms/div

Short Applied Short Removed

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Feature Description (continued)

Figure 10. Inductor Current Bursts in Short Circuit Figure 11. Short Circuit Transient and Recovery

The high side current limit trips when the peak inductor current reaches IHS (see Electrical Characteristics). This

is a cycle-by-cycle current limit and does not produce any frequency or current fold-back. It is meant to protect

the high side MOSFET from excessive current. Under some conditions, such as high input voltage, this current

limit may trip before the low side protection. The peak value of this current limit will vary with duty-cycle.

In FPWM mode, the inductor current is allowed to go negative. Should this current exceed INEG, the low side

switch is turned off until the next clock cycle. This is used to protect the low side switch from excessive negative

current. When the device is in AUTO mode, the negative current limit is increased to about 0 A; IZC. This allows

the device to operate in DCM.

8.3.4 Synchronizing Input

The internal clock of the LM53603-Q1 can be synchronized to a system clock through the SYNC input. This input

recognizes a valid high level as that ≥1.5 V, and a valid low as that ≤0.4 V. The frequency synchronization

signal should be in the range of 1.9 MHz to 2.3 MHz with a duty cycle of from 10% to 90%. The internal clock is

synced to the rising edge of the external clock. If this input is not used, it should be grounded. The maximum

voltage on this input is 5.5 V; and should not be allowed to float. See the Device Functional Modes section to

determine which modes are valid for synchronizing the clock.

8.3.5 Input Supply Current

The LM53603-Q1 is designed to have very low input supply current when regulating light loads. One way this is

achieved is by powering much of the internal circuitry from the output. The BIAS pin is the input to the LDO that

powers the majority of the control circuits. By connecting the BIAS input to the output of the regulator, this current

acts as a small load on the output. This current is reduced by the ratio of VOUT/VIN, just like any other load.

Another advantage of the LM53603-Q1 is that the feed-back divider is integrated into the device. This allows the

use of much larger resistors than can be used externally; >> 100 kΩ. This results in much lower divider current

than is possible with external resistors. Equation 2 can be used to estimate the total input supply current when

the device is regulating with no external loads. The terms of the equation are as follows:

• IIN: Input supply current with no load.

• IQ: Device quiescent current, see Electrical Characteristics.

• IEN: Current into EN pin; see Electrical Characteristics.

• IB: Current into BIAS pin; see Electrical Characteristics.

• K: ≈0.9

(2)

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Feature Description (continued)

Equation 2 can be used as a guide to indicate how the various terms affect the input supply current. The

Application Curves show measured values for the input supply current for both 3.3 V and 5 V output voltage

versions.

8.3.6 UVLO and TSD

The LM53603-Q1 incorporates an input undervoltage lockout (UVLO) function. The device will accept an EN

command when the input voltage rises above about 3.64 V and shuts down when the input falls below about 3.3

V. See the Electrical Characteristics table under "VIN-operate" for detailed specifications.

Thermal shutdown is provided to protect the device from excessive temperature. When the junction temperature

reaches about 162°C, the device will shut down; re-start occurs at a temperature of about 144ºC.

8.4 Device Functional Modes

Please refer to Table 1 and the following paragraphs for a detailed description of the functional modes for the

LM53603-Q1. These modes are controlled by the FPWM input as shown in Table 1. This input can be controlled

by any compatible logic, and the mode changed while the regulator is operating. If it is desired to lock the mode

for a given application, the input can be either connected to ground, a logic supply, or the VCC pin, as desired.

The maximum input voltage on this pin is 5.5 V; and it should not be allowed to float.

Table 1. Mode Selection

FPWM INPUT VOLTAGE OPERATING MODE

> 1.5 V Forced PWM: The regulator operates as a constant frequency, current mode, full-

synchronous converter for all loads; without diode emulation.

< 0.4 V AUTO: The regulator will move between PFM and PWM as the load current changes,

utilizing diode-emulation-mode to allow DCM (see the Glossary).

8.4.1 AUTO Mode

In AUTO mode the device moves between PWM and PFM as the load changes. At light loads the regulator

operates in PFM . At higher loads the mode changes to PWM. The load currents for which the devices moves

from PWM to PFM can be found in the Application Curves.

In PWM , the converter operates as a constant frequency, current mode, full synchronous converter using PWM

to regulate the output voltage. While operating in this mode the output voltage is regulated by switching at a

constant frequency and modulating the duty cycle to control the power to the load. This provides excellent line

and load regulation and low output voltage ripple. When in PWM the converter will synchronize to any valid clock

signal on the SYNC input (see Drop-Out and Input Voltage Frequency Fold-Back).

In PFM the high side FET is turned on in a burst of one or more cycles to provide energy to the load. The

frequency of these bursts is adjusted to regulate the output, while diode emulation is used to maximize efficiency

(see the ). This mode provides high light load efficiency by reducing the amount of input supply current required

to regulate the output voltage at small loadsGlossary. This trades off very good light load efficiency for larger

output voltage ripple and variable switching frequency. Also, a small increase in the output voltage will occur in

PFM. The actual switching frequency and output voltage ripple will depend on the input voltage, output voltage,

and load. Typical switching waveforms for PFM are shown in Figure 12 . See the Application Curves for output

voltage variation in AUTO mode. The SYNC input is ignored during PFM operation.

A unique feature of this device, is that a minimum input voltage is required for the regulator to switch from PWM

to PFM at light load. This feature is a consequence of the advanced architecture employed to provide high

efficiency at light loads. Figure 13 indicates typical values of input voltage required to switch modes at no-load.

Also, once the regulator switches to PFM, at light load, it will remain in that mode if the input voltage is reduced.

Temperature (°C)

Input Voltage (V)

-60 -40 -20 0 20 40 60 80 100 120 140

3.5

4.5

5.5

6.5

7.5

D023

3.3 V

5 V

2 ms/div

SW, 5V/div

Iinductor, 500mA/div

VOUT, 50mV/div

10µs/div

LM53602-Q1

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Figure 12. Typical PFM Switching Waveforms

Figure 13. Input Voltage for Mode Change

8.4.2 FPWM Mode

With a logic high on the FPWM input, the device is locked in PWM mode. This operation is maintained, even at

no-load, by allowing the inductor current to reverse its normal direction. This mode trades off reduced light load

efficiency for low output voltage ripple, tight output voltage regulation, and constant switching frequency. In this

mode, a negative current limit of INEG is imposed to prevent damage to the regulators low side FET. When in

FPWM the converter will synchronize to any valid clock signal on the SYNC input (see Drop-Out and Input

Voltage Frequency Fold-Back).

4.2

4.4

4.6

4.8

5.2

4 4.5 5 5.5 6 6.5 7

Output Voltage (V)

Input Voltage (V)

C003

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8.4.3 Drop-Out

One of the parameters that influences the drop-out performance of a buck regulator is the minimum off-time. As

the input voltage is reduced, to near the output voltage, the off-time of the high side switch starts to approach the

minimum value (see Timing Requirements). Beyond this point the switching may become erratic and/or the

output voltage will fall out of regulation. To avoid this problem, the LM53603-Q1 automatically reduces the

switching frequency to increase the effective duty cycle. This results in two specifications regarding drop-out

voltage, as shown in the System Characteristics table. One specification indicates when the switching frequency

drops to 1.85 MHz; avoiding the A.M. radio band. The other specification indicates when the output voltage has

fallen to 1% of nominal. See the Application Curves for typical values of drop-out. The overall drop-out

characteristic for the 5 V option, can be seen in Figure 14. The SYNC input is ignored during frequency fold-back

in drop-out.

Figure 14. Overall Drop-out Characteristic

VOUT = 5V

8.4.4 Input Voltage Frequency Fold-Back

At higher input voltages the on-time of the high side switch becomes small. When the minimum is reached (see

Timing Requirements), the switching may become erratic and/or the output voltage will fall out of regulation. To

avoid this behavior, the LM53603-Q1 automatically reduces the switching frequency at input voltages above

about 20 V (see Application Curves). In this way the device avoids the minimum on-time restriction and maintains

regulation at abnormally high battery voltages. The SYNC input is ignored during frequency fold-back at high

input voltages.

VIN

RESET

VCC

SYNC

FPWM

AGND

PGND

CBOOT

BIAS

LM53603

VIN VOUT

CBOOT

COUT

CIN

CVCC

CBIAS

RBIAS

3x 10µF

3x 22µF

2.2 µH

0.47 µF

0.1 µF

3 Ÿ

3.3 µF

6V to 36V 5V or 3.3V

10nF

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI's customers are

responsible for determining the suitability of components for their purposes. Customers

should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The LM53603-Q1 and LM53602-Q1 are step-down DC-DC converters, typically used to convert a higher DC

voltage to a lower DC voltage with a maximum output current of either 3 A or 2 A. The following design

procedure can be used to select components for the LM53603-Q1 or LM53602-Q1. Alternately, the WEBENCH®

Design Tool may be used to generate a complete design. This tool utilizes an iterative design procedure and has

access to a comprehensive database of components. This allows the tool to create an optimized design and

allows the user to experiment with various design options.

9.2 Typical Applications

Figure 15 shows the minimum required application circuit for the fixed output voltage versions, while Figure 16

shows the connections for complete processor control of the LM53603-Q1. Please refer to these figures while

following the design procedures. Table 2 provides an example of typical design requirements.

Figure 15. Typical Automotive Power Supply Schematic

VIN

RESET

VCC

SYNC

FPWM

AGND

PGND

CBOOT

BIAS

LM53603

VIN

VOUT

CBOOT

COUT

CIN

CVCC

CBIAS

RBIAS

3x 10µF

3x 22µF

2.2 µH

0.47 µF

0.1 µF

3 Ÿ

3.3 µF

µC

100 kŸ

6V to 36V

3.3V or 5V

10nF

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Typical Applications (continued)

Figure 16. Full Featured Automotive Power Supply Schematic

9.2.1 Design Parameters

There are a few design parameters to take into account. Most of those choices will decide which version of the

device to use. The desired output current will steer the designer toward a LM53602 type or LM53603 type part. If

the output voltage is 3.3 V or 5 V, a fixed output version of the device can be used. Any other voltage level within

the tolerance of the part can be achieved by using an adjustable version of the device. Most but not all

parameters are independent of the of the IC choice. The output filter components (inductor and output

capacitors) might vary with the choice of output voltage, especially for output voltages higher than 5 V. Please

refer to Detailed Design Procedure for help in choosing these components

Table 2. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE

Input voltage 12 V

Output voltage 5 V

Maximum output current 3A

9.2.2 Detailed Design Procedure

The following detailed design procedure applies to Figure 15,Figure 16, and Figure 45.

9.2.2.1 Setting the Output Voltage

For the fixed output voltage versions, the FB input is connected directly to the output voltage node. Preferably,

near the top of the output capacitor. If the feed-back point is located further away from the output capacitors (that

is, remote sensing), then a small 100 nF capacitor may be needed at the sensing point.

For output voltages other than 5 V or 3.3 V, a feed-back divider is required. For the ADJ version of the device,

the regulator holds the FB pin at 1.0 V. The range of adjustable output voltage can be found in the

Recommended Operating Conditions.Equation 3 can be used to determine RFBB for a desired output voltage

and a given RFBT. Usually RFBT is limited to a maximum value of 100 kΩ.



˜ V1V V1

RR OUT

FBTFBB

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(1) 16V X7R capacitors used : C3225X7R1C226M250AC (TDK)

(3)

In addition a feed-forward capacitor CFF may be required to optimize the transient response. For output voltages

greater than 6 V, the WEBENCH Design Tool can be used to optimize the design. Recommended CFF values for

some cases are given in the table below. It is important to note that these values provide a first approximation

only and need to be verified for each application by the designer.

Table 3. Recommended CFFcapacitors

VOUT COUT (nominal)(1) L RFBT RFBB CFF

3.2V 44µF 2.2µH 69.8kΩ31.6kΩ33pF

3.2V 110µF 2.2µH 69.8kΩ31.6kΩ120pF

5.1V 44µF 2.2µH 80.6kΩ19.6kΩ33pF

5.1V 110µF 2.2µH 80.6kΩ19.6kΩ220pF

8V 66µF 4.7µH 86.6kΩ12.4kΩ120pF

8V 100µF 4.7µH 86.6kΩ12.4kΩ220pF

10V 66µF 4.7µH 90.9kΩ10.0kΩ120pF

9.2.2.2 Output Capacitors

The LM53603-Q1 is designed to work with low ESR ceramic capacitors. The effective value of these capacitors

is defined as the actual capacitance under voltage bias and temperature. All ceramic capacitors have a large

voltage coefficient, in addition to normal tolerances and temperature coefficients. Under D.C. bias, the

capacitance value drops considerably. Larger case sizes and/or higher voltage capacitors are better in this

regard. To help mitigate these effects, multiple small capacitors can be used in parallel to bring the minimum

effective capacitance up to the desired value. This can also ease the RMS current requirements on a single

capacitor. Table 4 shows the nominal and minimum values of total output capacitance recommended for the

LM53603-Q1. The values shown also provide a starting point for other output voltages, when using the ADJ

option. Also shown are the measured values of effective capacitance for the indicated capacitor. More output

capacitance can be used to improve transient performance and reduce output voltage ripple.

In practice, the output capacitor has the most influence on the transient response and loop phase margin. Load

transient testing and Bode plots are the best way to validate any given design, and should always be completed

before the application goes into production. A careful study of temperature and bias voltage variation of any

candidate ceramic capacitor should be made in order to ensure that the minimum value of effective capacitance

is provided. The best way to obtain an optimum design is to use the Texas Instruments WEBENCH Design Tool.

In ADJ applications the feed-forward capacitor, CFF, provides another degree of freedom when stabilizing and

optimizing the design. Application report Optimizing Transient Response of Internally Compensated dc-dc

Converters With Feedforward Capacitor (SLVA289) should prove helpful when adjusting the feed-forward

capacitor.

In addition to the capacitance shown in Table 4, a small ceramic capacitor placed on the output can help to

reduce high frequency noise. Small case size ceramic capacitors in the range of 1 nF to 100 nF can be very

helpful in reducing spikes on the output caused by inductor parasitics.

The maximum value of total output capacitance should be limited to between 300 µF and 400 µF. Large values

of output capacitance can prevent the regulator from starting-up correctly and adversely effect the loop stability. If

values in the range given above, or greater, are to be used, then a careful study of start-up at full load and loop

stability must be performed.

IOUT

RMS #

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(1) Measured at indicated VOUT at 25°C.

(2) The following components were used: CFF = 47 pF, RFBT = 100 kΩ, RFBB = 11 kΩ, L = 4. 7 µH.

Table 4. Recommended Output Capacitors

OUTPUT

VOLTAGE NOMINAL OUTPUT CAPACITANCE MINIMUM OUTPUT CAPACITANCE PART NUMBER

(MANUFACTURER)

RATED

CAPACITANCE MEASURED

CAPACITANCE(1) RATED

CAPACITANCE MEASURED

CAPACITANCE(1)

3.3 V 3 x 22 µF 63 µF 2 x 22 µF 42 µF C3225X7R1C226M250AC (TDK)

5 V 3 x 22 µF 60 µF 2 x 22 µF 40 µF C3225X7R1C226M250AC (TDK)

6 V 3 x 22 µF 59 µF 2 x 22 µF 39 µF C3225X7R1C226M250AC (TDK)

10 V(2) 3 x 22 µF 48 µF 2 x 22 µF 32 µF C3225X7R1C226M250AC (TDK)

(1) Measured at 14V and 25°C.

9.2.2.3 Input Capacitors

The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying ripple

current and isolating switching noise from other circuits. Table 5 shows the nominal and minimum values of total

input capacitance recommenced for the LM53603-Q1. Also shown are the measured values of effective

capacitance for the indicated capacitor. In addition, small high frequency bypass capacitors connected directly

between the VIN and PGND pins are very helpful in reducing noise spikes and aid in reducing conducted EMI. It

is recommenced that a small case size 10 nF ceramic capacitor be placed across the input, as close as possible

to the device (see Figure 47). Additional high frequency capacitors can be used to help manage conducted EMI

or voltage spike issues that may be encountered.

Table 5. Recommended Input Capacitors

NOMINAL INPUT CAPACITANCE MINIMUM INPUT CAPACITANCE PART NUMBER (MANUFACTURER)

RATED

CAPACITANCE MEASURED

CAPACITANCE (1) RATED

CAPACITANCE MEASURED

CAPACITANCE(1)

3 x 10 µF 22.5 µF 2 x 10 µF 15 µF CL32B106KBJNNNE (Samsung)

Many times it is desirable to use an electrolytic capacitor on the input, in parallel with the ceramics. This is

especially true if longs leads/traces are used to connect the input supply to the regulator. The moderate ESR of

this capacitor can help damp any ringing on the input supply caused by long power leads. The use of this

additional capacitor will also help with voltage dips caused by input supplies with unusually high impedance.

Most of the input switching current passes through the ceramic input capacitor(s). The approximate RMS value of

this current can be calculated from Equation 4 and should be checked against the manufacturers' maximum

ratings.

(4)

9.2.2.4 Inductor

The LM53603-Q1 and LM53602-Q1 are optimized for a nominal inductance of 2.2 µH for the 5 V and 3.3 V

versions. This gives a ripple current that is approximately 20% to 30% of the full load current of 3 A. For output

voltages greater than 5 V, a proportionally larger inductor can be used. This will keep the ratio of inductor current

slope to internal compensating slope constant.

The most important inductor parameters are saturation current and parasitic resistance. Inductors with a

saturation current of between 5 A and 6 A are appropriate for most applications, when using the LM53603-Q1.

For the LM53602-Q1, inductors with a saturation current of between 4 A and 5 A are appropriate. Of course the

inductor parasitic resistance should be as low as possible to reduce losses at heavy loads. Table 6 gives a list of

several possible inductors that can be used with the LM53603-Q1.

 

OUTJA

OUT V1

1R TT

I˜

K



LM53602-Q1

LM53603-Q1

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Table 6. Recommenced Inductors

MANUFACTURER PART NUMBER SATURATION

CURRENT D.C. RESISTANCE

Würth 7440650022 6 A 15 mΩ

Coilcraft DO3316T-222MLB 7.8 A 11 mΩ

Coiltronics MPI4040R3-2R2-R 7.9 A 48 mΩ

Vishay IHLP2525CZER2R2M01 14 A 18 mΩ

Vishay IHLP2525BDER2R2M01 14 A 28 mΩ

Coilcraft XAL6030-222ME 16 A 13 mΩ

9.2.2.5 VCC

The VCC pin is the output of the internal LDO, used to supply the control circuits of the LM53603-Q1. This output

requires a 3.3 µF to 4.7µF, ceramic capacitor connected from VCC to GND for proper operation. An X7R device

with a rating of 10 V is highly recommended. In general this output should not be loaded with any external

circuitry. However, it can be used to supply a logic level to the FPWM input, or for the pull-up resistor used with

the RESET output (see Figure 16 ). The nominal output of the LDO is 3.15 V.

9.2.2.6 BIAS

The BIAS pin is the input to the internal LDO. As mentioned in Input Supply Current, this input is connected to

VOUT in order to provide the lowest possible supply current at light loads. Since this input is connected directly to

the output, it should be protected from negative voltage transients. Such transients may occur when the output is

shorted at the end of a long PCB trace or cable. If this is likely, in a given application, then a small resistor

should be placed in series between the BIAS input and VOUT, as shown in Figure 15. The resistor should be

sized to limit the current out of the BIAS pin to <100 mA. Values in the range of 2 Ωto 5 Ωare usually sufficient.

Values greater than 5 Ωare not recommended. As a rough estimate, assume that the full negative transient will

appear across RBIAS, and design for a current of < 100 mA. In severe cases, a Schottky diode can be placed in

parallel with the output to limit the transient voltage and current.

9.2.2.7 CBOOT

The LM53603-Q1 requires a "boot-strap" capacitor between the CBOOT pin and the SW pin. This capacitor

stores energy that is used to supply the gate drivers for the power MOSFETs. A ceramic capacitor of 0.47 µF,

≥6.3 V is required. A 10V rated capacitor or higher is highly recommended.

9.2.2.8 Maximum Ambient Temperature

As with any power conversion device, the LM53603-Q1 will dissipate internal power while operating. The effect of

this power dissipation is to raise the internal temperature of the converter, above ambient. The internal die

temperature (TJ) is a function of the ambient temperature, the power loss and the effective thermal resistance,

RθJA of the device and PCB combination. The maximum internal die temperature for the LM53603-Q1 is 150°C,

thus establishing a limit on the maximum device power dissipation and therefore load current at high ambient

temperatures. Equation 5 shows the relationships between the important parameters.

(5)

It is easy to see that larger ambient temperatures (TA) and larger values of RθJA will reduce the maximum

available output current. As stated in SPRA953, the values given in the Thermal Information table are not valid

for design purposes and must not be used to estimate the thermal performance of the application. The values

reported in that table were measured under a specific set of conditions that are never obtained in an actual

application. The effective RθJA is a critical parameter and depends on many factors such as power dissipation, air

temperature, PCB area, copper heat-sink area, number of thermal vias under the package, air flow, and adjacent

component placement. The LM53603-Q1 utilizes an advanced package with a heat spreading pad (EP) on the

bottom. This must be soldered directly to the PCB copper ground plane to provide an effective heat-sink, as well

as a proper electrical connection. The resources found in Table 9 can be used as a guide to optimal thermal

PCB design and estimating RθJA for a given application environment. A typical example of RθJA versus copper

board area is shown in Figure 17. The copper area in this graph is that for each layer of a four layer board; the

Output Current (A)

Power Dissipation (W)

0.5 1 1.5 2 2.5 3

0.5

1.5

2.5

D032

7 Vin

12 Vin

18 Vin

Output Current (A)

Power Dissipation (W)

0.5 1 1.5 2 2.5 3

0.5

1.5

2.5

D033

7 Vin

12 Vin

18 Vin

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

80 90 100 110 120 130 140 150

Output Current (A)

Ambient Temperature (C)

LM53603,

3.3V

LM53603,

LM53602,

3.3V

LM53602,

C006

Board Area (mm2)

Theta JA (C/W)

0 500 1000 1500 2000 2500 3000

D024

0.5 W

1 W

2 W

LM53602-Q1

LM53603-Q1

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SNVSA42B –JUNE 2015–REVISED MAY 2016

Product Folder Links: LM53602-Q1 LM53603-Q1

inner layers are 1 oz. (35µm), while the outer layers are 2 oz. (70µm). A typical curve of maximum load current

versus ambient temperature, for both the LM53603-Q1 and LM53602-Q1, is shown in Figure 18. This data was

taken with the device soldered to a PCB with an RθJA of about 17°C/W and an input voltage of 12 V. It must be

remembered that the data shown in these graphs are for illustration only and the actual performance in any given

application will depend on all of the factors mentioned above.

Figure 17. RθJA versus Copper Board Area

Figure 18. Maximum Output Current versus Ambient

Temperature

RθJA = 17°C/W, VIN = 12V

Figure 19. IC Power Dissipation versus Output Current for

3.3V output Figure 20. IC Power Dissipation versus Output Current for

5V output

Output Current (A)

Drop-out Voltage (V)

0 0.5 1 1.5 2 2.5 3 3.5

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

D011

-40°C

27°C

105°C

Output Current (A)

Drop-out Voltage (V)

0 0.5 1 1.5 2 2.5 3 3.5

0.5

1.5

2.5

D012

-40°C

27°C

105°C

Input Voltage (V)

Supply Current (µA)

0 5 10 15 20 25 30 35 40

D014

-40°C

25°C

105°C

Input Voltage (V)

Output Current (A)

0 2 4 6 8 10 12 14 16 18 20

0.05

0.1

0.15

0.2

0.25

0.3

0.35

D013

Output Current (A)

Efficiency

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

0.00001 0.0001 0.001 0.01 0.1 1 3

D028

12 VIN

18 VIN

7 VIN

Output Current (A)

Output Voltage (V)

0 0.5 1 1.5 2 2.5 3 3.5

4.97

4.98

4.99

5.01

5.02

5.03

5.04

5.05

5.06

5.07

5.08

D008

7 V

12 V

18 V

36 V

LM53602-Q1

LM53603-Q1

SNVSA42B –JUNE 2015–REVISED MAY 2016

www.ti.com

Product Folder Links: LM53602-Q1 LM53603-Q1

9.2.3 Application Curves

The following characteristics apply only to the circuit of Figure 15.These parameters are not tested and

represent typical performance only. Unless otherwise stated, the following conditions apply: VIN = 12 V, TA=

25°C.

VOUT = 5 V AUTO

Inductor = XAL6030-222ME

Figure 21. Efficiency

VOUT = 5 V AUTO

Figure 22. Load and Line Regulation

VOUT = 5 V AUTO IOUT = 0 A

Figure 23. Input Supply Current

VOUT = 5 V

Figure 24. Load Current for Mode Change

VOUT = 5 V

Figure 25. Drop-out for –1% Regulation

VOUT = 5 V

Figure 26. Drop-out for ≥1.85 MHz

50µs/div

VOUT, 100mV/div

Output Current, 1A/div

Iinductor, 1A/div

VOUT, 100mV/div

FPWM, 4v/div

2ms/div

1ms/div

Iinductor, 1A/div

VOUT, 2V/div

EN, 3V/div

RESET, 4V/div

50µs/div

VOUT, 100mV/div

Output Current, 1A/div

Output Current (A)

Switching Frequency (Hz)

1E-6 1E-5 0.0001 0.001 0.01 0.1 1 10

100

1000

10000

100000

1000000

10000000

D031

6 V

12 V

18 V

36 V

Input Voltage (V)

Frequency (Hz)

0 5 10 15 20 25 30 35 40

500000

1000000

1500000

2000000

2500000

D026

0 A

2 A

3 A

LM53602-Q1

LM53603-Q1

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SNVSA42B –JUNE 2015–REVISED MAY 2016

Product Folder Links: LM53602-Q1 LM53603-Q1

The following characteristics apply only to the circuit of Figure 15.These parameters are not tested and

represent typical performance only. Unless otherwise stated, the following conditions apply: VIN = 12 V, TA=

25°C.

VOUT = 5 V AUTO

Figure 27. Switching Frequency vs. Load Current

VOUT = 5 V FPWM

Figure 28. Switching Frequency vs. Input Voltage

VOUT = 5 V IOUT = 0 A AUTO

Figure 29. Start-up

VOUT = 5 V IOUT = 0 A to 3 A, TR= TF= 1 µs AUTO

Figure 30. Load Transients

VOUT = 5 V IOUT = 0 A to 3 A, TR= TF= 1 µs FPWM

Figure 31. Load Transient

VOUT = 5 V IOUT = 1 mA

Figure 32. Mode Change Transient

Output Current (A)

Drop-out Voltage (V)

0 0.5 1 1.5 2 2.5 3 3.5

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

D019

-40°C

27°C

105°C

Output Current (A)

Drop-out Voltage (V)

0 0.5 1 1.5 2 2.5 3 3.5

0.5

1.5

2.5

D020

-40°C

27°C

105°C

Input Voltage (V)

Supply Current (µA)

0 5 10 15 20 25 30 35 40

D022

-40°C

25°C

105°C

Input Voltage (V)

Output Current (A)

0 2 4 6 8 10 12 14 16 18 20

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

D021

Output Current (A)

Efficiency

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

0.00001 0.0001 0.001 0.01 0.1 1 3

D029

12 VIN

18 VIN

7 VIN

Output Current (A)

Output Voltage (V)

0 0.5 1 1.5 2 2.5 3 3.5

3.27

3.28

3.29

3.3

3.31

3.32

3.33

3.34

3.35

3.36

D016

6 V

12 V

18 V

36 V

LM53602-Q1

LM53603-Q1

SNVSA42B –JUNE 2015–REVISED MAY 2016

www.ti.com

Product Folder Links: LM53602-Q1 LM53603-Q1

The following characteristics apply only to the circuit of Figure 15.These parameters are not tested and

represent typical performance only. Unless otherwise stated, the following conditions apply: VIN = 12 V, TA=

25°C.

VOUT = 3.3 V AUTO

Inductor = XAL6030-222ME

Figure 33. Efficiency

VOUT = 3.3 V AUTO

Figure 34. Load and Line Regulation

VOUT = 3.3 V AUTO IOUT = 0 A

Figure 35. Input Supply Current

VOUT = 3.3 V

Figure 36. Load Current for Mode Change

VOUT = 3.3 V

Figure 37. Drop-out for –1% Regulation

VOUT = 3.3 V

Figure 38. Drop-out for ≥1.85 MHz

FPWM, 4v/div

VOUT, 100mV/div

Iinductor, 1A/div

2ms/div

50µs/div

VOUT, 100mV/div

Output Current, 1A/div

50µs/div Output Current, 1A/div

VOUT, 100mV/div

1ms/div

EN, 3V/div

VOUT, 2V/div

Iinductor, 1A/div

RESET, 4V/div

Output Current (A)

Switching Frequency (Hz)

1E-5 0.0001 0.001 0.01 0.1 1 101E-6

100

1000

10000

100000

1000000

10000000

D030

6 V

12 V

18 V

36 V

Input Voltage (V)

Frequency (Hz)

0 5 10 15 20 25 30 35 40

500000

1000000

1500000

2000000

2500000

D027

0 A

2 A

3 A

LM53602-Q1

LM53603-Q1

www.ti.com

SNVSA42B –JUNE 2015–REVISED MAY 2016

Product Folder Links: LM53602-Q1 LM53603-Q1

The following characteristics apply only to the circuit of Figure 15.These parameters are not tested and

represent typical performance only. Unless otherwise stated, the following conditions apply: VIN = 12 V, TA=

25°C.

VOUT = 3.3 V AUTO

Figure 39. Switching Frequency vs. Load Current

VOUT = 3.3 V FPWM

Figure 40. Switching Frequency vs. Input Voltage

VOUT = 3.3 V AUTO IOUT = 0 A

Figure 41. Start-up

VOUT = 3.3 V IOUT = 0 A to 3 A, TR= TF= 1 µs AUTO

Figure 42. Load Transient

VOUT = 3.3 V IOUT = 0 A to 3 A, TR= TF= 1 µs FPWM

Figure 43. Load Transient VOUT = 3.3 V IOUT = 1 mA

Figure 44. Mode Change Transient

VIN

RESET

VCC

SYNC

FPWM

AGND

PGND

CBOOT

BIAS

LM53603

VIN VOUT

CBOOT

COUT

CIN

CVCC

CBIAS RBIAS

3x 10µF

3x 22µF

4.7 µH

0.47 µF

0.1 µF 3 Ÿ

3.3 µF

CFF

RFBT

RFBB

100 kŸ

11 kŸ

12V to 36V 10V @ 3A

47 pF

10nF

LM53602-Q1

LM53603-Q1

SNVSA42B –JUNE 2015–REVISED MAY 2016

www.ti.com

Product Folder Links: LM53602-Q1 LM53603-Q1

9.2.4 Additional Application Circuit

Figure 45 shows a typical example of a design with an output voltage of 10 V; while Table 7 gives typical design

parameters. Please refer to Detailed Design Procedure for the design procedure.

Figure 45. Typical Adjustable Output Automotive Power Supply Schematic

CD/DVD/Blu-ray Disc™ Motor Drive Applications

VOUT = 10 V

9.2.4.1 Design Parameters for Typical Adjustable Output Automotive Power Supply

There are a few design parameters to take into account. Most of those choices will decide which version of

the device to use. The desired output current will steer the designer toward a LM53602 type or LM53603

type part. Most but not all parameters are independent of the of the IC choice. The output filter components

(inductor and output capacitors) might vary with the choice of output voltage, especially for output voltages

higher than 5 V. Refer to Detailed Design Procedure for details on choosing the components for the

application.

Table 7. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE

Input Voltage 12 V

Output Voltage 10 V

Maximum Output Current 3 A

9.3 Do's and Don't's

•Don't: Exceed the Absolute Maximum Ratings.

•Don't: Exceed the ESD Ratings.

•Don't: Exceed the Recommended Operating Conditions.

•Don't: Allow the EN, FPWM or SYNC input to float.

•Don't: Allow the output voltage to exceed the input voltage, nor go below ground.

•Don't: Use the thermal data given in the Thermal Information table to design your application.

•Do: Follow all of the guidelines and/or suggestions found in this data sheet, before committing your design to

production. TI Application Engineers are ready to help critique your design and PCB layout to help make your

project a success.

•Do: Refer to the helpful documents found in Table 9 and Table 8.

K˜

OUTOUT

IN VIV

LM53602-Q1

LM53603-Q1

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SNVSA42B –JUNE 2015–REVISED MAY 2016

Product Folder Links: LM53602-Q1 LM53603-Q1

10 Power Supply Recommendations

The characteristics of the input supply must be compatible with the Absolute Maximum Ratings and

Recommended Operating Conditions found in this data sheet. In addition, the input supply must be capable of

delivering the required input current to the loaded regulator. The average input current can be estimated with

Equation 6, where ηis the efficiency.

(6)

If the regulator is connected to the input supply through long wires or PCB traces, special care is required to

achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse

effect on the operation of the regulator. The parasitic inductance, in combination with the low ESR ceramic input

capacitors, can form an under-damped resonant circuit. This circuit may cause over-voltage transients at the VIN

pin, each time the input supply is cycled on and off. The parasitic resistance will cause the voltage at the VIN pin

to dip when the load on the regulator is switched on, or exhibits a transient. If the regulator is operating close to

the minimum input voltage, this dip may cause the device to shutdown and/or reset. The best way to solve these

kinds of issues is to reduce the distance from the input supply to the regulator and/or use an aluminum or

tantalum input capacitor in parallel with the ceramics. The moderate ESR of these types of capacitors will help to

damp the input resonant circuit and reduce any voltage overshoots. A value in the range of 20 µF to 100 µF is

usually sufficient to provide input damping and help to hold the input voltage steady during large load transients.

Sometimes, for other system considerations, an input filter is used in front of the regulator. This can lead to

instability, as well as some of the effects mentioned above, unless it is designed carefully. The user guide Simple

Success with Conducted EMI for DC-DC Converters,SNVA489, provides helpful suggestions when designing an

input filter for any switching regulator

In some cases a Transient Voltage Suppressor (TVS) is used on the input of regulators. One class of this device

has a "snap-back" V-I characteristic (thyristor type). The use of a device with this type of characteristic is not

recommend. When the TVS "fires", the clamping voltage drops to a very low value. If this holding voltage is less

than the output voltage of the regulator, the output capacitors will be discharged through the regulator back to the

input. This uncontrolled current flow could damage the regulator.

LM53602-Q1

LM53603-Q1

SNVSA42B –JUNE 2015–REVISED MAY 2016

www.ti.com

Product Folder Links: LM53602-Q1 LM53603-Q1

11 Layout

11.1 Layout Guidelines

The PCB layout of any DC-DC converter is critical to the optimal performance of the design. Bad PCB layout can

disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad PCB

layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore,

the EMI performance of the regulator is dependent on the PCB layout, to a great extent. In a buck converter, the

most critical PCB feature is the loop formed by the input capacitor and power ground, as shown in Figure 46.

This loop carries fast transient currents that can cause large transient voltages when reacting with the trace

inductance. These unwanted transient voltages will disrupt the proper operation of the converter. Because of this,

the traces in this loop should be wide and short, and the loop area as small as possible to reduce the parasitic

inductance. Figure 47 shows a recommended layout for the critical components of the LM53603-Q1. This PCB

layout is a good guide for any specific application. The following important guidelines should also be followed:

1. Place the input capacitor(s) CIN as close as possible to the VIN and PGND terminals. VIN and GND

are on the same side of the device, simplifying the input capacitor placement.

2. Place bypass capacitors for VCC and BIAS close to their respective pins. These components must be

placed close to the device and routed with short/wide traces to the pins and ground. The trace from BIAS to

VOUT should be ≥10mils wide. BIAS and VCC capacitors should be place within 4mm of the BIAS and VCC

pin (160mils) .

3. Use wide traces for the CBOOT capacitor. CBOOT should be placed close to the device with short/wide

traces to the CBOOT and SW pins.

4. Place the feedback divider as close as possible to the FB pin on the device. If a feedback divider and

CFF are used, they should be close to the device, while the length of the trace from VOUT to the divider can

be somewhat longer. However, this latter trace should not be routed near any noise sources that can

capacitively couple to the FB input.

5. Use at least one ground plane in one of the middle layers. This plane will act as a noise shield and also

act as a heat dissipation path.

6. Connect the EP pad to the GND plane. This pad acts as a heat-sink connection and a ground connection

for the regulator. It must be solidly connected to a ground plane. The integrity of this connection has a direct

bearing on the effective RθJA.

7. Provide wide paths for VIN, VOUT and GND. Making these paths as wide as possible reduces any voltage

drops on the input or output paths of the converter and maximizes efficiency.

8. Provide enough PCB area for proper heat-sinking. As stated in the Maximum Ambient Temperature

section, enough copper area must be used to ensures a low RθJA, commensurate with the maximum load

current and ambient temperature. The top and bottom PCB layers should be made with two ounce copper;

and no less than one ounce. Use an array of heat-sinking vias to connect the exposed pad (EP) to the

ground plane on the bottom PCB layer. If the PCB has multiple copper layers (recommended), these thermal

vias can also be connected to the inner layer heat-spreading ground planes.

9. Keep switch area small. The copper area connecting the SW pin to the inductor should be kept as short

and wide as possible. At the same time the total area of this node should be minimized to help mitigate

radiated EMI.

10. The resources in Table 8 provide additional important guidelines.

Table 8. PCB Layout Resources

TITLE LINK

AN-1149 Layout Guidelines for Switching Power Supplies SNVA021

AN-1229 Simple Switcher PCB Layout Guidelines SNVA054

Constructing Your Power Supply- Layout Considerations SLUP230

SNVA721 Low Radiated EMI Layout Made SIMPLE with LM4360x and

LM4600x SNVA721

CIN

VIN

GND

LM53602-Q1

LM53603-Q1

www.ti.com

SNVSA42B –JUNE 2015–REVISED MAY 2016

Product Folder Links: LM53602-Q1 LM53603-Q1

Figure 46. Current Loops with Fast Transients

11.1.1 Ground and Thermal Plane Considerations

As mentioned above, it is recommended to use one of the middle layers as a solid ground plane. A ground plane

provides shielding for sensitive circuits and traces. It also provides a quiet reference potential for the control

circuitry. The AGND and PGND pins should be connected to the ground plane using vias right next to the bypass

capacitors. PGND pins are connected to the source of the internal low side MOSFET switch. They should be

connected directly to the grounds of the input and output capacitors. The PGND net contains noise at the

switching frequency and may bounce due to load variations. The PGND trace, as well as PVIN and SW traces,

should be constrained to one side of the ground plane. The other side of the ground plane contains much less

noise and should be used for sensitive routes.

It is recommended to provide adequate device heat sinking by utilizing the exposed pad (EP) of the IC as the

primary thermal path. Use a minimum 4 by 4 array of 10 mil thermal vias to connect the EP to the system ground

plane for heat sinking. The vias should be evenly distributed under the exposed pad. Use as much copper as

possible for system ground plane on the top and bottom layers for the best heat dissipation. It is recommended

to use a four-layer board with the copper thickness, starting from the top, as: 2 oz / 1 oz / 1 oz / 2 oz. A four layer

board with enough copper thickness and proper layout provides low current conduction impedance, proper

shielding and lower thermal resistance.

Table 9. Resources for Thermal PCB Design

TITLE LINK

AN-2020 Thermal Design By Insight, Not Hindsight SNVA419

AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Pad

Packages SNVA183

SPRA953B Semiconductor and IC Package Thermal Metrics SPRA953

SNVA719 Thermal Design made Simple with LM43603 and LM43602 SNVA719

SLMA002 PowerPAD™ Thermally Enhanced Package SLMA002

SLMA004 PowerPAD Made Easy SLMA004

SBVA025 Using New Thermal Metrics SBVA025

VIN VOUTGND

COUT

Top Trace

GND

HEATSINK

INDUCTOR

SYNC

FPWM

RESET

RFBB

RFBT

CBIAS

CVCC

CBOOT

GND

HEATSINK GND

HEATSINK

COUT

CIN

Bottom Trace VIA to Ground Plane

Rbias

LM53602-Q1

LM53603-Q1

SNVSA42B –JUNE 2015–REVISED MAY 2016

www.ti.com

Product Folder Links: LM53602-Q1 LM53603-Q1

11.2 Layout Example

Figure 47. PCB Layout Example

LM53602-Q1

LM53603-Q1

www.ti.com

SNVSA42B –JUNE 2015–REVISED MAY 2016

Product Folder Links: LM53602-Q1 LM53603-Q1

12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation see the following:

•Using New Thermal Metrics applications report (SBVA025).

•Optimizing Transient Response of Internally Compensated dc-dc Converters With Feedforward Capacitor

(SLVA289).

•Simple Success with Conducted EMI for DC-DC Converters (SNVA489).

• AN-1149 Layout Guidelines for Switching Power Supplies SNVA021

• AN-1229 Simple Switcher PCB Layout Guidelines SNVA054

•Constructing Your Power Supply- Layout Considerations SLUP230

•Low Radiated EMI Layout Made SIMPLE with LM4360x and LM4600x SNVA721

• AN-2020 Thermal Design By Insight, Not Hindsight SNVA419

• AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages SNVA183

•Semiconductor and IC Package Thermal Metrics SPRA953

•Thermal Design made Simple with LM43603 and LM43602 SNVA719

•PowerPAD™ Thermally Enhanced Package SLMA002

•PowerPAD Made Easy SLMA004

•Using New Thermal Metrics SBVA025

12.3 Related Links

Table 10 lists quick access links. Categories include technical documents, support and community resources,

tools and software, and quick access to sample or buy.

Table 10. Related Links

PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL

DOCUMENTS TOOLS &

SOFTWARE SUPPORT &

COMMUNITY

LM53602-Q1 Click here Click here Click here Click here Click here

LM53603-Q1 Click here Click here Click here Click here Click here

12.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

LM53602-Q1

LM53603-Q1

SNVSA42B –JUNE 2015–REVISED MAY 2016

www.ti.com

Product Folder Links: LM53602-Q1 LM53603-Q1

12.5 Trademarks

PowerPAD, E2E are trademarks of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

Blu-ray Disc is a trademark of Blu-ray Disk Association.

All other trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.7 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 18-Mar-2016

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LM536023QPWPRQ1 ACTIVE HTSSOP PWP 16 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 150 L536023

LM536023QPWPTQ1 ACTIVE HTSSOP PWP 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 150 L536023

LM536025QPWPRQ1 ACTIVE HTSSOP PWP 16 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 150 L536025

LM536025QPWPTQ1 ACTIVE HTSSOP PWP 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 150 L536025

LM53602AQPWPRQ1 ACTIVE HTSSOP PWP 16 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 150 L53602A

LM53602AQPWPTQ1 ACTIVE HTSSOP PWP 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 150 L53602A

LM536033QPWPRQ1 ACTIVE HTSSOP PWP 16 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 150 L536033

LM536033QPWPTQ1 ACTIVE HTSSOP PWP 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 150 L536033

LM536035QPWPRQ1 ACTIVE HTSSOP PWP 16 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 150 L536035

LM536035QPWPTQ1 ACTIVE HTSSOP PWP 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 150 L536035

LM53603AQPWPRQ1 ACTIVE HTSSOP PWP 16 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 150 L53603A

LM53603AQPWPTQ1 ACTIVE HTSSOP PWP 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 150 L53603A

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

PACKAGE OPTION ADDENDUM

www.ti.com 18-Mar-2016

Addendum-Page 2

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LM536023QPWPRQ1 HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

LM536023QPWPTQ1 HTSSOP PWP 16 250 180.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

LM536025QPWPRQ1 HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

LM536025QPWPTQ1 HTSSOP PWP 16 250 180.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

LM53602AQPWPRQ1 HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

LM53602AQPWPTQ1 HTSSOP PWP 16 250 180.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

LM536033QPWPRQ1 HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

LM536033QPWPTQ1 HTSSOP PWP 16 250 180.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

LM536035QPWPRQ1 HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

LM536035QPWPTQ1 HTSSOP PWP 16 250 180.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

LM53603AQPWPRQ1 HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

LM53603AQPWPTQ1 HTSSOP PWP 16 250 180.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Aug-2016

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM536023QPWPRQ1 HTSSOP PWP 16 2000 367.0 367.0 38.0

LM536023QPWPTQ1 HTSSOP PWP 16 250 210.0 185.0 35.0

LM536025QPWPRQ1 HTSSOP PWP 16 2000 367.0 367.0 38.0

LM536025QPWPTQ1 HTSSOP PWP 16 250 210.0 185.0 35.0

LM53602AQPWPRQ1 HTSSOP PWP 16 2000 367.0 367.0 38.0

LM53602AQPWPTQ1 HTSSOP PWP 16 250 210.0 185.0 35.0

LM536033QPWPRQ1 HTSSOP PWP 16 2000 367.0 367.0 38.0

LM536033QPWPTQ1 HTSSOP PWP 16 250 210.0 185.0 35.0

LM536035QPWPRQ1 HTSSOP PWP 16 2000 367.0 367.0 38.0

LM536035QPWPTQ1 HTSSOP PWP 16 250 210.0 185.0 35.0

LM53603AQPWPRQ1 HTSSOP PWP 16 2000 367.0 367.0 38.0

LM53603AQPWPTQ1 HTSSOP PWP 16 250 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Aug-2016

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

TYP

6.6

6.2

14X 0.65

16X 0.30

0.19

4.55

(0.15) TYP

0 - 8 0.15

0.05

1.2 MAX

3.40

2.68

2.48

1.75

4X 0.18 MAX

NOTE 5

4X (0.3)

NOTE 5

2X (0.95)

0.25

GAGE PLANE

0.75

0.50

NOTE 3

5.1

4.9

B4.5

4.3

PowerPAD TSSOP - 1.2 mm max heightPWP0016D

PLASTIC SMALL OUTLINE

4223219/A 08/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

5. Features may differ and may not be present.

PowerPAD is a trademark of Texas Instruments.

116

0.1 C A B

PIN 1 ID AREA

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.250

THERMAL

PAD

www.ti.com

EXAMPLE BOARD LAYOUT

(5.8)

0.05 MAX

AROUND 0.05 MIN

AROUND

16X (1.5)

16X (0.45)

14X (0.65)

(R0.05) TYP

(2.48)

(3.4)

NOTE 9

(5)

NOTE 9

( 0.2) TYP

VIA

(0.65) TYP

(1.3 TYP)

(1.1 TYP)

PowerPAD TSSOP - 1.2 mm max heightPWP0016D

PLASTIC SMALL OUTLINE

4223219/A 08/2016

SYMM

SEE DETAILS

LAND PATTERN EXAMPLE

SCALE:10X

METAL COVERED

BY SOLDER MASK

SOLDER MASK

DEFINED PAD

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED SOLDER MASK DETAILS

NOT TO SCALE

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

16X (1.5)

16X (0.45)

(2.48)

(3.4)

BASED ON

0.125 THICK

STENCIL

(5.8)

14X (0.65)

(R0.05) TYP

PowerPAD TSSOP - 1.2 mm max heightPWP0016D

PLASTIC SMALL OUTLINE

4223219/A 08/2016

2.1 X 2.870.175 2.26 X 3.10.15 2.48 X 3.4 (SHOWN)0.125 2.77 X 3.80.1

SOLDER STENCIL

OPENING

STENCIL

THICKNESS

NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

11. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:10X

SYMM

BASED ON

0.125 THICK

STENCIL

BY SOLDER MASK

METAL COVERED SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

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Mouser Electronics

Authorized Distributor

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LM536023QPWPTQ1