DS07-13704-4E
FUJITSU SEMICONDUCTOR
DATA SHEET
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX
MB90590/590G
Series
MB90591/F591A/594/594G/F594A/F594G
MB90V590A/V590G
■
■■
■DESCRIPTION
The MB90590/590G series with two FULL-CAN*1 interfaces and FLASH R OM is especially designed f or automo-
tiv e and industrial applications. Its main f eatures are tw o on board CAN Interf aces , which conf orm to V2.0 Part A
and P art B , while supporting a very flexib le message buff er scheme and so off ering more functions than a normal
full CAN approach.
The instruction set of F2MC-16LX CPU core inherits an AT architecture of the F2MC*2 family with additional
instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions,
and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long
word data.
The MB90590/590G series has peripheral resources of 8/10-bit A/D con verters, U AR T (SCI), e xtended I/O serial
interface, 8/16-bit PPG timer, I/O timer (input capture (ICU), output compare (OCU)), stepping motor controller,
and sound generator.
*1: Controller Area Network (CAN) - License of Robert Bosch GmbH
*2: F2MC stands for FUJITSU Flexible Microcontroller.
■
■■
■FEATURES
•Clock
Embedded PLL clock multiplication circuit
Operating cloc k (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation
(at oscillation of 4 MHz, 4 MHz to 16 MHz).
Minimum instruction ex ecution time: 62.5 ns (operation at oscillation of 4 MHz, four times the oscillation clock,
VCC of 5.0 V)
(Continued)
■
■■
■PACKAGE
100-pin Plastic QFP
(FPT-100P-M06)
MB90590/590G Series
2
(Continued)
• Instruction set to optimize controller applications
Rich data types (bit, byte, word, long word)
Rich addressing mode (23 types)
Enhanced signed multiplication/division instruction and RETI instruction functions
Enhanced precision calculation realized by the 32-bit accumulator
• Instruction set designed for high level language (C language) and multi-task operations
Adoption of system stack pointer
Enhanced pointer indirect instructions
Barrel shift instructions
• Program patch function (for two address pointers)
• Enhanced execution speed: 4-byte instruction queue
• Enhanced interrupt function: 8 levels, 34 factors
• Automatic data transmission function independent of CPU operation
Extended intelligent I/O service function (EI2OS): Up to 10 channels
• Embedded ROM size and types
Mask ROM: 256 Kbytes/384 Kbytes
Flash ROM: 256 Kbytes/384 Kbytes
Embedded RAM size: 6 Kbytes/8 Kbytes
•Flash ROM
Supports automatic programming, Embedded Algorithm TM*
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory
Erase can be performed on each block
Block protection with external programming voltage
• Low-power consumption (stand-by) mode
Sleep mode (mode in which CPU operating clock is stopped)
Stop mode (mode in which oscillation is stopped)
CPU intermittent operation mode
Clock mode
Hardware stand-by mode
•Process
0.5µm CMOS technology
• I/O port
General-pur pose I/O ports: 78 ports
•Timer
Watchdog timer: 1 channel
8/16-bit PPG timer: 8/16-bit × 6 channels
16-bit re-load timer: 2 channels
• 16-bit I/O timer
16-bit free-run timer: 1 channel
Input capture: 6 channels
Output compare: 6 channels
• Extended I/O serial interface: 1 channel
• UART (3 channels)
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized (with start/stop bit) transmission can be selectively used.
• Stepping motor controller (4 channels)
MB90590/590G Series
3
• External interrupt circuit (8 channels)
A module for starting an extended intelligent I/O service (EI2OS) and generating an exter nal interr upt which
is triggered by an external input.
• Delayed interrupt generation module
Generates an interrupt request for switching tasks.
• 8/10-bit A/D converter (8 channels)
8/10-bit resolution can be selectively used.
Starting by an external trigger input.
• FULL-CAN interfaces: 2
Conforming to Version 2.0 Part A and Part B
Flexible message buffering (mailbox and FIFO buffering can be mixed)
• Sound generator
• 18-bit Time-base counter
• Clock timer: 1 channel
• External bus interface: Maximum address space 16 Mbytes
*: Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
MB90590/590G Series
4
■
■■
■PRODUCT LINEUP
(Continued)
Features MB90591/594/594G MB90F591A/F594A/F594G MB90V590A/V590G
Classification Mask ROM product Flash ROM product Evaluation product
ROM size 384/256 Kbytes 384/256 Kbytes
Boot block
Hard-wired reset vector None
RAM size 8/6 Kbytes 8/6 Kbytes 8 Kbytes
Emulator-specific power
supply *1None
CPU functions
The number of instructions: 340
Instruction bit length: 8 bits, 16 bits
Instruction length: 1 byte to 7 bytes
Data bit length: 1 bit, 8 bits, 16 bits
Minimum execution time: 62.5 ns (at machine clock frequency of 16 MHz)
Interrupt processing time: 1.5 µs
(at machine clock frequency of 16 MHz, minimum value)
UART (3 channels)
Clock synchronized transmission (500 Kbps / 1 Mbps / 2 Mbps)
Clock asynchronized transmission (4808/5208/9615/10417/19230/38460/62500
/500000 bps at machine clock frequency of 16 MHz)
Transmission can be performed by bi-directional serial transmission or by master/
slave connection.
8/10-bit A/D converter
Conversion precision: 8/10-bit can be selectively used.
Number of inputs: 8
One-shot conversion mode (converts selected channel once only)
Scan conversion mode (converts two or more successive channels and can program
up to 8 channels)
Continuous conversion mode (converts selected channel continuously)
Stop conversion mode (converts selected channel and stop operation repeatedly)
8/16-bit PPG timers
(6 channels)
Number of channels: 6 (8/16-bit × 6 channels)
PPG operation of 8-bit or 16-bit
A pulse wave of given intervals and given duty ratios can be output.
Pulse interval: fsys, fsys/21, fsys/22, fsys/23, fsys/24, 128µs
(at oscillation of 4 MHz, fsys = system clock frequency of 16 MHz, fosc = oscillation
clock frequency)
16-bit Reload timer Number of channels: 2
Operation clock frequency: fsys/21, fsys/23, fsys/25 (fsys = System clock frequency)
Supports External Event Count function
16-bit
I/O
timer
16-bit
Output compares Number of channels: 6 (8/16-bit × 6 channels)
Pin input factor: A match signal of compare register
Input captures Number of channels: 6
Rewriting a register value upon a pin input (rising, falling, or both edges)
MB90590/590G Series
5
(Continued)
*1:It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used.
Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power Pin) about details.
*2:Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)
Features MB90591/594/594G MB90F591A/F594A/F594G MB90V590A/V590G
CAN Interface
Number of channels: 2
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID’s
Supports multiple messages
Flexible configuration of acceptance filtering:
Full bit compare / Full bit mask / Two partial bit masks
Supports up to 1Mbps
CAN bit timing setting:
MB90xxx:TSEG2 ≥ RSJW+2TQ
MB90xxxG:TSEG2 ≥ RSJW
Stepping motor controller
(4 channels) Four high current outputs for each channel
Synchronized two 8-bit PWM’s for each channel
External interrupt circuit Number of inputs: 8
Started by a rising edge, a falling edge, an “H” level input, or an “L” level input.
Sound generator 8-bit PWM signal is mixed with tone frequency from 8-bit reload counter
PWM frequency: 62.5K, 31.2K, 15.6K, 7.8KHz (at System clock = 16MHz)
Tone frequency: PWM frequency / 2 / (reload value + 1)
Extended I/O serial
interface
Clock synchronized transmission (31.25K/62.5K/125K/500K/1Mbps at machine clock
frequency of 16 MHz)
LSB first/MSB first
Clock timer Directly operates with the system clock
Read/Write accessible Second/Minute/Hour registers
Watchdog timer Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(at oscillation of 4 MHz, minimum value)
Flash Memory
Supports automatic programming, Embedded Algorithm TM and
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Hard-wired reset vector available in order to point to a fixed boot sector in Flash
Memory
Boot block configuration
Erase can be performed on each block
Block protection with external programming voltage
Flash Writer from Minato Electronics Inc.
Low-power consumption
(stand-by) mode Sleep/stop/CPU intermittent operation/clock timer/hardware stand-by
Process CMOS
Power supply voltage for
operation*2
5 V±10 % (MB90V590A, MB90F594A, MB90594, MB90V590G,
MB90F594G, MB90594G)
5 V±5 % (MB90F591A, MB90591)
Package QFP-100 PGA-256
MB90590/590G Series
6
■
■■
■PIN ASSIGNMENT
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50 Vss
P17/SGA
P16/SGO
P15/TX1
P14/RX1
P13/OUT5
P12/OUT4
P11/OUT3
P07/OUT1
P06/OUT0
P05/IN5
P04/IN4
P03/IN3
P02/IN2
P01/IN1
P00/IN0
Vcc
X1
X0
P10/OUT2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
2
3
4
5
6
7
9
8
MD1
MD0
P57/TOT/WOT
P56/TIN
P67/AN7
P66/AN6
P65/AN5
P64/AN4
Vss
P63/AN3
P62/AN2
P61/AN1
P60/AN0
AVss
AVRL
AVRH
AVcc
P55/PPG5/ADTG
P54/PPG4
P53/PPG3
P95/INT3
P94/INT2
P93/INT1
RST
P92/INT0
P91/RX0
P90/TX0
DVSS
P87/PWM2M3
P86/PWM2P3
P85/PWM1M3
P84/PWM1P3
DVCC
P83/PWM2M2
P82/PWM2P2
P81/PWM1M2
P80/PWM1P2
DVSS
P77/PWM2M1
P76/PWM2P1
P75/PWM1M1
P74/PWM1P1
DVCC
P73/PWM2M0
P72/PWM2P0
P71/PWM1M0
P70/PWM1P0
DVSS
HST
MD2
P20
P21
P22
P23
P24/INT4
P25/INT5
P26/INT6
P27/INT7
P30
P31
P52/PPG2
P51/PPG1
P50/PPG0
C
P47/SOT3
P46/SCK3
P45/SCIN3
Vcc
P44/SIN2
P43/SCK2
P42/SOT2
P41/SOT1
P40/SCK1
P37/SIN1
P36/SIN0
P35/SCK0
P34/SOT0
P33
P32
Vss
(Top view)
(FPT-100P-M06)
MB90590/590G Series
7
■
■■
■PIN DESCRIPTION
(Continued)
No. Pin name Circuit type Function
82 X0 A Oscillator pin
83 X1
77 RST B Reset input
52 HST C Hardware standby input
85 to 90 P00 to P05 DGeneral purpose IO
IN0 to IN5 Inputs for the Input Captures
91 to 96
P06 to P07
P10 to P13 D
General purpose IO
OUT0 to OUT5 Outputs for the Output Compares.
To enable the signal outputs, the corresponding bits of the Port Direc-
tion registers should be set to “1”.
97 P14 DGeneral purpose IO
RX1 RX input for CAN Interface 1
98
P15
D
General purpose IO
TX1 TX output for CAN Interface 1.
To enable the signal output, the corresponding bit of the Port Direction
register should be set to “1”.
99
P16
D
General purpose IO
SGO SGO output for the Sound Generator.
To enable the signal output, the corresponding bit of the Port Direction
register should be set to “1”.
100
P17
D
General purpose IO
SGA SGA output for the Sound Generator.
To enable the signal output, the corresponding bit of the Port Direction
register should be set to “1”.
1 to 4 P20 to P23 D General purpose IO
5 to 8 P24 to P27 DGeneral purpose IO
INT4 to INT7 External interrupt input for INT4 to INT7
9 to 10 P30 to P31 D General purpose IO
12 to 13 P32 to P33 D General purpose IO
14
P34
D
General purpose IO
SOT0 SOT output for UART 0.
To enable the signal output, the corresponding bit of the Port Direction
register should be set to “1”.
15
P35
D
General purpose IO
SCK0 SCK input/output for UART 0.
To enable the signal output, the corresponding bit of the Port Direction
register should be set to “1”.
MB90590/590G Series
8
(Continued)
No. Pin name Circuit type Function
16 P36 DGeneral purpose IO
SIN0 SIN input for UART 0
17 P37 DGeneral purpose IO
SIN1 SIN input for UART 1
18 P40 DGeneral purpose IO
SCK1 SCK input/output for UART 1
19 P41 DGeneral purpose IO
SOT1 SOT output for UART 1
20 P42 DGeneral purpose IO
SOT2 SOT output for UART 2
21 P43 DGeneral purpose IO
SCK2 SCK input/output for UART 2
22 P44 DGeneral purpose IO
SIN2 SIN input for UART 2
24 P45 DGeneral purpose IO
SIN3 SIN input for the Serial IO
25 P46 DGeneral purpose IO
SCK3 SCK input/output for the Serial IO
26 P47 DGeneral purpose IO
SOT3 SOT output for the Serial IO
28 to 33
P50 to P55
D
General purpose IO
PPG0 to
PPG5,
ADTG
Outputs for the Programmable Pulse Generators.
Pin number 33 is also shared with ADTG input for the external trigger
of the A/D Converter.
38 to 41 P60 to P63 EGeneral purpose IO
AN0 to AN3 Inputs for the A/D Converter
43 to 46 P64 to P67 EGeneral purpose IO
AN4 to AN7 Inputs for the A/D Converter
47 P56 DGeneral purpose IO
TIN TIN input for the 16-bit Reload Timers
48
P57
D
General purpose IO
TOT/WOT
TOT output for the 16-bit Reload Timers and WOT output for the
Watch Timer. Only one of three output enable flags in these periph-
eral blocks can be set at a time. Otherwise the output signal has no
meaning.
MB90590/590G Series
9
(Continued)
No. Pin name Circuit type Function
54 to 57
P70 to P73
F
General purpose IO
PWM1P0
PWM1M0
PWM2P0
PWM2M0
Output for Stepping Motor Controller channel 0.
59 to 62
P74 to P77
F
General purpose IO
PWM1P1
PWM1M1
PWM2P1
PWM2M1
Output for Stepping Motor Controller channel 1.
64 to 67
P80 to P83
F
General purpose IO
PWM1P2
PWM1M2
PWM2P2
PWM2M2
Output for Stepping Motor Controller channel 2.
69 to 72
P84 to P87
F
General purpose IO
PWM1P3
PWM1M3
PWM2P3
PWM2M3
Output for Stepping Motor Controller channel 3.
74 P90 DGeneral purpose IO
TX0 TX output for CAN Interface 0
75 P91 DGeneral purpose IO
RX0 RX input for CAN Interface 0
76 P92 DGeneral purpose IO
INT0 External interrupt input for INT0
78 P93 DGeneral purpose IO
INT1 External interrupt input for INT1
79 P94 DGeneral purpose IO
INT2 External interrupt input for INT2
80 P95 DGeneral purpose IO
INT3 External interrupt input for INT3
58, 68 DVCC Dedicated power supply pins for the high current output buffers
(Pin No. 54 to 72)
53, 63, 73 DVSS Dedicated ground pins for the high current output buffers
(Pin No. 54 to 72)
34 AVCC Power
supply
Power supply for analog circuit pin
When turning this power supply on or off, always be sure to first apply
electric potential equal to or greater than AVCC to VCC.
37 AVSS Power
supply Ground level for analog circuit
MB90590/590G Series
10
(Continued)
No. Pin name Circuit type Function
35 AVRH Power
supply
Reference voltage input pin for analog circuit
When turning this power supply on or off, always be sure to first apply
electric potential equal to or greater than AVRH to AVCC.
36 AVRL Power
supply Reference voltage input pin for analog circuit
49, 50 MD0, MD1 C Operating mode selection input pins
Connect directly to VCC or VSS.
51 MD2 G Operating mode selection input pin
Connect directly to VCC or VSS.
27 C This is the power supply stabilization capacitor pin. It should be con-
nected externally to an 0.1 µF ceramic capacitor.
23, 84 VCC Power
supply Power supply (5.0 V) input pin for digital circuit
11,42,81 VSS Power
supply Power supply (GND) input pin for digital circuit
MB90590/590G Series
11
■
■■
■I/O CIRCUIT TYPE
(Continued)
Circuit Type Circuit Remarks
A
• Oscillation feedback resistor:
1 MΩ approx.
B
• Hysteresis input with pull-up resistor:
50 kΩ approx.
C
• Hysteresis input
D
•CMOS output
• Hysteresis input
X1
X0
Standby control signal
Oscillation feedback
resistor
HYS
R (pull-up)
R
HYS
R
HYS
VCC
P-ch
N-ch
R
MB90590/590G Series
12
Circuit Type Circuit Remarks
E
•CMOS output
• Hysteresis input
• Analog input
F
• CMOS high current output
• Hysteresis input
G
• Hysteresis input with pull-down resistor:
50 kΩ approx.
• Flash version does not have pull-down
resistor.
Analog input
HYS
P-ch
N-ch
R
Vcc
P-ch
N-ch
HYS
High current
P-ch
N-ch
R
HYS
R
R (pull-down)
MB90590/590G Series
13
■
■■
■HANDLING DEVICES
(1)Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions:
• A voltage higher than Vcc or lower than Vss is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between Vcc and Vss.
• The AVcc power supply is applied before the Vcc voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
F or the same reason, also be careful not to let the analog power-supply v oltage (AVCC, A VRH) e xceed the digital
power-supply voltage.
(2)Treatment of unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the
de vice. Therefor they must be pulled up or pulled do wn through resistors. In this case those resistors should be
more than 2 kΩ.
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
(3)Using external clock
To use external clock, drive X0 pin only and leave X1 pin unconnected.
Below is a diagram of how to use external clock.
Using external clock
X0
X1
MB90590/590G Series
MB90590/590G Series
14
(4)Power supply pins (Vcc/Vss)
In products with multiple VCC or VSS pins, pins with the same potential are internally connected in the device to
avoid abnor mal operations including latch-up. However, you must connect the pins to an external power and a
ground line to lo wer the electro-magnetic emission le vel to pre v ent abnormal operation of strobe signals caused
by the rise in the ground level, and to conform to the total current rating.
Make sure to connect VCC and VSS pins via lowest impedance to power lines.
It is recommended to provide a bypass capacitor of around 0.1 µF between VCC and VSS pin near the device.
(5) Pull-up/down resistors
The MB90590/590G Series does not support internal pull-up/down resistors. Use external components where
needed.
(6) Crystal Oscillator Circuit
Noises around X0 or X1 pins may cause abnormal operations. Mak e sure to provide bypass capacitors via the
shortest distances from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure
that lines of oscillation circuits do not cross the lines of other circuits.
A printed circuit board artwork surrounding the X0 and X1 pins with a ground area for stabilizing the operation
is highly recommended.
(7) Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D conv erter power supply (AVCC, AVRH, A VRL) and analog inputs (AN0 to AN7) after
turning-on the digital power supply (VCC).
Turn-off the digital power after tur ning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage does not exceed AVRH or AVCC (tur ning on/off the analog and digital power supplies simulta-
neously is acceptable).
(8) Connection of Unused Pins of A/D Converter
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = VSS.
Vcc
Vss
Vss
Vcc
Vss
Vcc
MB90590/590G
Series
Vcc Vss
Vcc
Vss
MB90590/590G Series
15
(9) N.C. Pin
The N.C. (internally connected) pin must be opened for use.
(10) Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50
µs or more (0.2 V to 2.7 V).
(11) Indeterminate outputs from ports 0 and 1
During oscillation setting time of step-down circuit (during a power-on reset) after the power is turned on, the
outputs from ports 0 and 1 become following state.
•If RST
pin is “H”, the outputs become indeterminate.
•If RST pin is “L”, the outputs become high-impedance.
Pay attention to the port output timing shown as follow. Oscillation setting time*2
Power-on reset*1
Vcc (Power-supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Oscillation clock signal
KA (internal operation clock A) signal
KB (internal operation clock B) signal
PORT (port output) signal Period of indeterminated
*1:Power-on reset time: Period of “clock frequency × 217” (Clock frequency of 16 MHz: 8.19 ms)
*2:Oscillation setting time: Period of “clock frequency × 218” (Clock frequency of 16 MHz: 16.38ms)
RST pin is “H”
Oscillation setting time∗2
Power-on reset∗1
Vcc (Power-supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Oscillation clock signal
KA (internal operation clock A) signal
KB (internal operation clock B) signal
PORT (port output) signal High-impedance
*1:Power-on reset time: Period of “clock frequency × 217” (Clock frequency of 16 MHz: 8.19 ms)
*2:Oscillation setting time: Period of “clock frequency × 218” (Clock frequency of 16 MHz: 16.38ms)
RST pin is “L”
MB90590/590G Series
16
(12) Initialization
The de vice contains internal registers which are initialized only b y a power-on reset. To initialize these registers ,
please turn on the power again.
(13) Directions of “DIV A, Ri” and “DIVW A, RWi” instructions
In the Signed multiplication and division instructions (“DIV A, Ri” and “DIVW A, RWi”), the va lue of the corre-
sponding bank register (DTB, ADB, USB, SSB) is set in “00 H”.
If the values of the corresponding bank registers (DTB,ADB,USB,SSB) are set to other than “00 H”, the remainder
by the execution result of the instruction is not stored in the register of the instruction operand.
(14) Using REALOS
The use of EI2OS is not possible with the REALOS real time operating system.
MB90590/590G Series
17
■
■■
■BLOCK DIAGRAM
RAM 6/8 K
ROM/Flash
UART 3ch
Prescaler × 3
Watch
10-bit ADC
8ch
Sound
Generator
16-bit
Clock
Controller
16-bit Input
Capture
6ch
16-bit Output
Compare
4ch
CAN
2ch
External
Interrupt
8/16-bit
PPG
6ch
F2MC-16LX
CPU
F2MC-16 Bus
X0,X1
RST
HST
SOT0 to SOT2
SCK0 to SCK2
SIN0 to SIN2
AVCC
AVSS
AN0 to AN7
AVRH
AVRL
ADTG
SGO
SGA
IN0 to IN5
OUT0 to OUT5
PPG0 to PPG5
RX0, RX1
TX0, TX1
INT0 to INT7
Serial I/O
Prescaler
SOT3
SCK3
SIN3
SMC
4ch
PWM1M0 to PWM1M3
PWM1P0 to PWM1P3
PWM2M0 to PWM2M3
PWM2P0 to PWM2P3
DVCC
DVSS
256 K/384 K
16-bit Reload
TIN
TOT/WOT Timer 2ch
Timer
IO Timer
Circuit 8ch
MB90590/590G Series
18
■
■■
■MEMORY SPACE
The memory space of the MB90590/590G Series is shown below
Memory space map
Note: The ROM data of bank FF is reflected in the upper address of bank 00, realizing effe ctive use of the C
compiler small model. The low er 16-bit of bank FF and the lower 16-bit of bank 00 are assigned to the same
address, enabling reference of the table on the ROM without stating “far”.
For example, if an attempt has been made to access 00C000H , the contents of the ROM at FFC000H are
accessed. Since the ROM area of the FF bank exceeds 48 Kbytes, the whole area cannot be reflected in
the image for the 00 bank. The ROM data at FF4000H to FFFFFFH looks, therefore, as if it were the image
f or 004000H to 00FFFFH. Thus, it is recommended that the ROM data tab le be stored in the area of FF4000H
to FFFFFFH.
MB90V590A/V590G MB90594/F594A/
594G/F594G MB90591/F591A
FFFFFFH
FF0000HROM (FF bank) FFFFFFH
FF0000HROM (FF bank) FFFFFFH
FF0000HROM (FF bank)
FEFFFFH
FE0000HROM (FE bank) FEFFFFH
FE0000HROM (FE bank) FEFFFFH
FE0000HROM (FE bank)
FDFFFFH
FD0000HROM (FD bank) FDFFFFH
FD0000HROM (FD bank) FDFFFFH
FD0000HROM (FD bank)
FCFFFFH
FC0000HROM (FC bank) FCFFFFH
FC0000HROM (FC bank) FCFFFFH
FC0000H
FBFFFFH
FB0000HROM (FB bank) FBFFFFH
FB0000HROM (FB bank)
FAFFFFH
FA0000HROM (FA bank) FAFFFFH
FA0000HROM (FA bank)
F9FFFFH
F90000HROM (F9 bank) F9FFFFH
F90000HROM (F9 bank)
00FFFFH
004000H
ROM
(Image of FF bank) 00FFFFH
004000H
ROM
(Image of FF bank) 00FFFFH
004000H
ROM
(Image of FF bank)
0028FFH
002100HRAM 2K 0028FFH
002100HRAM 2K
0020FFH0020FFH
001FFFH
001900HPeripheral 001FFFH
001900HPeripheral 001FFFH
001900HPeripheral
0018FFH
000100H
RAM 6K
0018FFH
000100H
RAM 6K
0018FFH
000100H
RAM 6K
0000BFH
000000HPeripheral 0000BFH
000000HPeripheral 0000BFH
000000HPeripheral
MB90590/590G Series
19
■
■■
■I/O MAP
(Continued)
Address Register Abbreviation Access Peripheral Initial value
00HPort 0 Data Register PDR0 R/W Port 0 XXXXXXXXB
01HPort 1 Data Register PDR1 R/W Port 1 XXXXXXXXB
02HPort 2 Data Register PDR2 R/W Port 2 XXXXXXXXB
03HPort 3 Data Register PDR3 R/W Port 3 XXXXXXXXB
04HPort 4 Data Register PDR4 R/W Port 4 XXXXXXXXB
05HPort 5 Data Register PDR5 R/W Port 5 XXXXXXXXB
06HPort 6 Data Register PDR6 R/W Port 6 XXXXXXXXB
07HPort 7 Data Register PDR7 R/W Port 7 XXXXXXXXB
08HPort 8 Data Register PDR8 R/W Port 8 XXXXXXXXB
09HPort 9 Data Register PDR9 R/W Port 9 _ _ XXXXXXB
0AH to 0FHReserved
10HPort 0 Direction Register DDR0 R/W Port 0 0 0 0 0 0 0 0 0B
11HPort 1 Direction Register DDR1 R/W Port 1 0 0 0 0 0 0 0 0B
12HPort 2 Direction Register DDR2 R/W Port 2 0 0 0 0 0 0 0 0B
13HPort 3 Direction Register DDR3 R/W Port 3 0 0 0 0 0 0 0 0B
14HPort 4 Direction Register DDR4 R/W Port 4 0 0 0 0 0 0 0 0B
15HPort 5 Direction Register DDR5 R/W Port 5 0 0 0 0 0 0 0 0B
16HPort 6 Direction Register DDR6 R/W Port 6 0 0 0 0 0 0 0 0B
17HPort 7 Direction Register DDR7 R/W Port 7 0 0 0 0 0 0 0 0B
18HPort 8 Direction Register DDR8 R/W Port 8 0 0 0 0 0 0 0 0B
19HPort 9 Direction Register DDR9 R/W Port 9 _ _ 0 0 0 0 0 0B
1AHReserved
1BHAnalog Input Enable Register ADER R/W Port 6, A/D 1 1 1 1 1 1 1 1B
1CH to 1FHReserved
20HSerial Mode Control Register 0 UMC0 R/W
UART0
0 0 0 0 0 1 0 0B
21HSerial Status Register 0 USR0 R/W 0 0 0 1 0 0 0 0B
22HSerial Input/Output Data Register 0 UIDR0/
UODR0 R/W XXXXXXXXB
23HRate and Data Register 0 URD0 R/W 0 0 0 0 0 0 0XB
24HSerial Mode Control Register 1 UMC1 R/W
UART1
0 0 0 0 0 1 0 0B
25HSerial Status Register 1 USR1 R/W 0 0 0 1 0 0 0 0B
26HSerial Input/Output Data Register 1 UIDR1/
UODR1 R/W XXXXXXXXB
27HRate and Data Register 1 URD1 R/W 0 0 0 0 0 0 0XB
MB90590/590G Series
20
(Continued)
Address Register Abbreviation Access Peripheral Initial value
28HSerial Mode Control Register 2 UMC2 R/W
UART2
0 0 0 0 0 1 0 0B
29HSerial Status Register 2 USR2 R/W 0 0 0 1 0 0 0 0B
2AHSerial Input/Output Data
Register 2 UIDR2/
UODR2 R/W XXXXXXXXB
2BHRate and Data Register 2 URD2 R/W 0 0 0 0 0 0 0XB
2CHSerial Mode Control Register
(low-order) SMCS R/W
Serial IO
_ _ _ _0 0 0 0B
2DHSerial Mode Control Register
(high-order) SMCS R/W 0 0 0 0 0 0 1 0B
2EHSerial Data Register SDR R/W XXXXXXXXB
2FHEdge Selector Register SES R/W _ _ _ _ _ _ _0B
30HExternal Interrupt Enable Register ENIR R/W
External Interrupt
0 0 0 0 0 0 0 0B
31HExternal Interrupt Request Register EIRR R/W XXXXXXXXB
32HExternal Interrupt Level Register ELVR R/W 0 0 0 0 0 0 0 0B
33HExternal Interrupt Level Register ELVR R/W 0 0 0 0 0 0 0 0B
34HA/D Control Status Register 0 ADCS0 R/W
A/D Converter
0 0 0 0 0 0 0 0B
35HA/D Control Status Register 1 ADCS1 R/W 0 0 0 0 0 0 0 0B
36HA/D Data Register 0 ADCR0 R XXXXXXXXB
37HA/D Data Register 1 ADCR1 R/W 0 0 0 0 1 0 XXB
38HPPG0 Operation Mode Control Register PPGC0 R/W 16-bit Programmable
Pulse
Generator 0/1
0 _ 0 0 0 _ _ 1B
39HPPG1 Operation Mode Control Register PPGC1 R/W 0 _ 0 0 0 0 0 1B
3AHPPG0,1 Output Pin Control Register PPG01 R/W 0 0 0 0 0 0 0 0B
3BHReserved
3CHPPG2 Operation Mode Control Register PPGC2 R/W 16-bit Programmable
Pulse
Generator 2/3
0 _ 0 0 0 _ _1B
3DHPPG3 Operation Mode Control Register PPGC3 R/W 0 _ 0 0 0 0 0 1B
3EHPPG2,3 Output Pin Control Register PPG23 R/W 0 0 0 0 0 0 0 0B
3FHReserved
40HPPG4 Operation Mode Control Register PPGC4 R/W 16-bit Programmable
Pulse
Generator 4/5
0 _ 0 0 0 _ _ 1B
41HPPG5 Operation Mode Control Register PPGC5 R/W 0 _ 0 0 0 0 0 1B
42HPPG4,5 Output Pin Control Register PPG45 R/W 0 0 0 0 0 0 0 0B
43HReserved
44HPPG6 Operation Mode Control Register PPGC6 R/W 16-bit Programmable
Pulse
Generator 6/7
0 _ 0 0 0 _ _ 1B
45HPPG7 Operation Mode Control Register PPGC7 R/W 0 _ 0 0 0 0 0 1B
46HPPG6,7 Output Pin Control Register PPG67 R/W 0 0 0 0 0 0 0 0B
47HReserved
MB90590/590G Series
21
(Continued)
Address Register Abbreviation Access Peripheral Initial value
48HPPG8 Operation Mode Control Register PPGC8 R/W 16-bit Programmable
Pulse
Generator 8/9
0 _ 0 0 0 _ _ 1B
49HPPG9 Operation Mode Control Register PPGC9 R/W 0 _ 0 0 0 0 0 1B
4AHPPG8,9 Output Pin Control Register PPG89 R/W 0 0 0 0 0 0 0 0B
4BHReserved
4CHPPGA Operation Mode Control Register PPGCA R/W 16-bit Programmable
Pulse
Generator A/B
0 _ 0 0 0 _ _ 1B
4DHPPGB Operation Mode Control Register PPGCB R/W 0 _ 0 0 0 0 0 1B
4EHPPGA,B Output Pin Control Register PPGAB R/W 0 0 0 0 0 0 0 0B
4FHReserved
50HTimer Control Status Register 0
(low-order) TMCSR0 R/W 16-bit Reload Timer 0 0 0 0 0 0 0 0 0B
51HTimer Control Status Register 0
(high-order) TMCSR0 R/W _ _ _ _ 0 0 0 0B
52HTimer Control Status Register 1
(low-order) TMCSR1 R/W 16-bit Reload Timer 1 0 0 0 0 0 0 0 0B
53HTimer Control Status Register 1
(high-order) TMCSR1 R/W _ _ _ _ 0 0 0 0B
54HInput Capture Control Status
Register 0/1 ICS01 R/W Input Capture 0/1 0 0 0 0 0 0 0 0B
55HInput Capture Control Status
Register 2/3 ICS23 R/W Input Capture 2/3 0 0 0 0 0 0 0 0B
56HInput Capture Control Status
Register 4/5 ICS45 R/W Input Capture 4/5 0 0 0 0 0 0 0 0B
57HReserved
58HOutput Compare Control Status
Register 0 OCS0 R/W Output Compare 0/1 0 0 0 0 _ _ 0 0B
59HOutput Compare Control Status
Register 1 OCS1 R/W _ _ _0 0 0 0 0B
5AHOutput Compare Control Status
Register 2 OCS2 R/W Output Compare 2/3 0 0 0 0 _ _ 0 0B
5BHOutput Compare Control Status
Register 3 OCS3 R/W _ _ _ 0 0 0 0 0B
5CHOutput Compare Control Status
Register 4 OCS4 R/W Output Compare 4/5 0 0 0 0 _ _ 0 0B
5DHOutput Compare Control Status
Register 5 OCS5 R/W _ _ _ 0 0 0 0 0B
5EHSound Control Register (low-order) SGCR R/W Sound Generator 0 0 0 0 0 0 0 0B
5FHSound Control Register (high-order) SGCR R/W 0 _ _ _ _ _ _ 0B
MB90590/590G Series
22
(Continued)
Address Register Abbreviation Access Peripheral Initial value
60HWatch Timer Control Register
(low-order) WTCR R/W Watch Timer 0 0 0 _ _ 0 0 0B
61HWatch Timer Control Register
(high-order) WTCR R/W 0 0 0 0 0 0 0 0B
62HPWM Control Register 0 PWC0 R/W Stepping Motor
Controller 0 0 0 0 0 0 _ _ 0B
63HReserved
64HPWM Control Register 1 PWC1 R/W Stepping Motor
Controller 1 0 0 0 0 0 _ _ 0B
65HReserved
66HPWM Control Register 2 PWC2 R/W Stepping Motor
Controller 2 0 0 0 0 0 _ _ 0B
67HReserved
68HPWM Control Register 3 PWC3 R/W Stepping Motor
Controller 3 0 0 0 0 0 _ _ 0B
69H to 6CHReserved
6DHSerial IO Prescaler Register CDCR R/W Prescaler (Serial IO) 0 XXX 1 1 1 1B
6EHTimer Control Status Register TCCS R/W I/O Timer 0 0 0 0 0 0 0 0B
6FHROM Mirror Function Select
Register ROMM W ROM Mirror XXXXXXX1B
70H to 8FHReserved for CAN Interface 0/1. Refer to section about CAN Controller
90H to 9DHReserved
9EHProgram Address Detection
Control Status Register PACSR R/W Address Match
Detection Function 0 0 0 0 0 0 0 0B
9FHDelayed Interrupt/Release Register DIRR R/W Delayed Interrupt _ _ _ _ _ _ _ 0B
A0HLow Power Mode Control Register LPMCR R/W Low Power Controller 0 0 0 1 1 0 0 0B
A1HClock Selection Register CKSCR R/W Low Power Controller 1 1 1 1 1 1 0 0B
A2H to A7HReserved
A8HWatchdog Timer Control Register WDTC R/W Watchdog Timer XXXXX 1 1 1B
A9HTime Base Timer Control Register TBTC R/W Time Base Timer 1 - - 0 0 1 0 0B
AAH to ADHReserved
AEH
Flash Memory Control Status
Register
(Flash product only.
Otherwise reserved)
FMCS R/W Flash Memory 0 0 0 X 0 0 0 0B
AFHReserved
MB90590/590G Series
23
(Continued)
Address Register Abbreviation Access Peripheral Initial value
B0HInterrupt Control Register 00 ICR00 R/W
Interrupt controller
0 0 0 0 0 1 1 1B
B1HInterrupt Control Register 01 ICR01 R/W 0 0 0 0 0 1 1 1B
B2HInterrupt Control Register 02 ICR02 R/W 0 0 0 0 0 1 1 1B
B3HInterrupt Control Register 03 ICR03 R/W 0 0 0 0 0 1 1 1B
B4HInterrupt Control Register 04 ICR04 R/W 0 0 0 0 0 1 1 1B
B5HInterrupt Control Register 05 ICR05 R/W 0 0 0 0 0 1 1 1B
B6HInterrupt Control Register 06 ICR06 R/W 0 0 0 0 0 1 1 1B
B7HInterrupt Control Register 07 ICR07 R/W 0 0 0 0 0 1 1 1B
B8HInterrupt Control Register 08 ICR08 R/W 0 0 0 0 0 1 1 1B
B9HInterrupt Control Register 09 ICR09 R/W 0 0 0 0 0 1 1 1B
BAHInterrupt Control Register 10 ICR10 R/W 0 0 0 0 0 1 1 1B
BBHInterrupt Control Register 11 ICR11 R/W 0 0 0 0 0 1 1 1B
BCHInterrupt Control Register 12 ICR12 R/W 0 0 0 0 0 1 1 1B
BDHInterrupt Control Register 13 ICR13 R/W 0 0 0 0 0 1 1 1B
BEHInterrupt Control Register 14 ICR14 R/W 0 0 0 0 0 1 1 1B
BFHInterrupt Control Register 15 ICR15 R/W 0 0 0 0 0 1 1 1B
C0H to
FFHReserved
1900HReload L Register PRLL0 R/W 16-bit Programmable
Pulse
Generator 0/1
XXXXXXXXB
1901HReload H Register PRLH0 R/W XXXXXXXXB
1902HReload L Register PRLL1 R/W XXXXXXXXB
1903HReload H Register PRLH1 R/W XXXXXXXXB
1904HReload L Register PRLL2 R/W 16-bit Programmable
Pulse
Generator 2/3
XXXXXXXXB
1905HReload H Register PRLH2 R/W XXXXXXXXB
1906HReload L Register PRLL3 R/W XXXXXXXXB
1907HReload H Register PRLH3 R/W XXXXXXXXB
1908HReload L Register PRLL4 R/W 16-bit Programmable
Pulse
Generator 4/5
XXXXXXXXB
1909HReload H Register PRLH4 R/W XXXXXXXXB
190AHReload L Register PRLL5 R/W XXXXXXXXB
190BHReload H Register PRLH5 R/W XXXXXXXXB
190CHReload L Register PRLL6 R/W 16-bit Programmable
Pulse
Generator 6/7
XXXXXXXXB
190DHReload H Register PRLH6 R/W XXXXXXXXB
190EHReload L Register PRLL7 R/W XXXXXXXXB
190FHReload H Register PRLH7 R/W XXXXXXXXB
MB90590/590G Series
24
(Continued)
Address Register Abbreviation Access Peripheral Initial value
1910HReload L Register PRLL8 R/W 16-bit Programmable
Pulse
Generator 8/9
XXXXXXXXB
1911HReload H Register PRLH8 R/W XXXXXXXXB
1912HReload L Register PRLL9 R/W XXXXXXXXB
1913HReload H Register PRLH9 R/W XXXXXXXXB
1914HReload L Register PRLLA R/W 16-bit Programmable
Pulse
Generator A/B
XXXXXXXXB
1915HReload H Register PRLHA R/W XXXXXXXXB
1916HReload L Register PRLLB R/W XXXXXXXXB
1917HReload H Register PRLHB R/W XXXXXXXXB
1918H to 191FHReserved
1920HInput Capture Register 0
(low-order) IPCP0 R
Input Capture 0/1
XXXXXXXXB
1921HInput Capture Register 0
(high-order) IPCP0 R XXXXXXXXB
1922HInput Capture Register 1
(low-order) IPCP1 R XXXXXXXXB
1923HInput Capture Register 1
(high-order) IPCP1 R XXXXXXXXB
1924HInput Capture Register 2
(low-order) IPCP2 R
Input Capture 2/3
XXXXXXXXB
1925HInput Capture Register 2
(high-order) IPCP2 R XXXXXXXXB
1926HInput Capture Register 3
(low-order) IPCP3 R XXXXXXXXB
1927HInput Capture Register 3
(high-order) IPCP3 R XXXXXXXXB
1928HInput Capture Register 4
(low-order) IPCP4 R
Input Capture 4/5
XXXXXXXXB
1929HInput Capture Register 4
(high-order) IPCP4 R XXXXXXXXB
192AHInput Capture Register 5
(low-order) IPCP5 R XXXXXXXXB
192BHInput Capture Register 5
(high-order) IPCP5 R XXXXXXXXB
192CH to 192FHReserved
MB90590/590G Series
25
(Continued)
Address Register Abbreviation Access Peripheral Initial value
1930HOutput Compare Register 0
(low-order) OCCP0 R/W
Output Compare
0/1
XXXXXXXXB
1931HOutput Compare Register 0
(high-order) OCCP0 R/W XXXXXXXXB
1932HOutput Compare Register 1
(low-order) OCCP1 R/W XXXXXXXXB
1933HOutput Compare Register 1
(high-order) OCCP1 R/W XXXXXXXXB
1934HOutput Compare Register 2
(low-order) OCCP2 R/W
Output Compare
2/3
XXXXXXXXB
1935HOutput Compare Register 2
(high-order) OCCP2 R/W XXXXXXXXB
1936HOutput Compare Register 3
(low-order) OCCP3 R/W XXXXXXXXB
1937HOutput Compare Register 3
(high-order) OCCP3 R/W XXXXXXXXB
1938HOutput Compare Register 4
(low-order) OCCP4 R/W
Output Compare
4/5
XXXXXXXXB
1939HOutput Compare Register 4
(high-order) OCCP4 R/W XXXXXXXXB
193AHOutput Compare Register 5
(low-order) OCCP5 R/W XXXXXXXXB
193BHOutput Compare Register 5
(high-order) OCCP5 R/W XXXXXXXXB
193CH to 193FHReserved
1940HTimer 0/Reload Register 0
(low-order) TMR0/
TMRLR0 R/W 16-bit Reload
Timer 0
XXXXXXXXB
1941HTimer 0/Reload Register 0
(high-order) TMR0/
TMRLR0 R/W XXXXXXXXB
1942HTimer 1/Reload Register 1
(low-order) TMR1/
TMRLR1 R/W 16-bit Reload
Timer 1
XXXXXXXXB
1943HTimer 1/Reload Register 1
(high-order) TMR1/
TMRLR1 R/W XXXXXXXXB
1944HTimer Data Register (low-order) TCDT R/W IO Timer 0 0 0 0 0 0 0 0 B
1945HTimer Data Register (high-order) TCDT R/W 0 0 0 0 0 0 0 0 B
1946HFrequency Data Register SGFR R/W
Sound Generator
XXXXXXXXB
1947HAmplitude Data Register SGAR R/W XXXXXXXXB
1948HDecrement Grade Register SGDR R/W XXXXXXXXB
1949HTone Count Register SGTR R/W XXXXXXXXB
MB90590/590G Series
26
(Continued)
Address Register Abbreviation Access Peripheral Initial value
194AHSub-second Data Register
(low-order) WTBR R/W
Watch Timer
XXXXXXXXB
194BHSub-second Data Register
(middle-order) WTBR R/W XXXXXXXXB
194CHSub-second Data Register
(high-order) WTBR R/W _ _ _ XXXXXB
194DHSecond Data Register WTSR R/W _ _ 0 0 0 0 0 0 B
194EHMinute Data Register WTMR R/W Watch Timer _ _ 0 0 0 0 0 0 B
194FHHour Data Register WTHR R/W _ _ _ 0 0 0 0 0 B
1950HPWM1 Compare Register 0 PWC10 R/W
Stepping Motor
Controller 0
XXXXXXXXB
1951HPWM2 Compare Register 0 PWC20 R/W XXXXXXXXB
1952HPWM1 Select Register 0 PWS10 R/W _ _ 0 0 0 0 0 0 B
1953HPWM2 Select Register 0 PWS20 R/W _ 0 0 0 0 0 0 0 B
1954HPWM1 Compare Register 1 PWC11 R/W
Stepping Motor
Controller 1
XXXXXXXXB
1955HPWM2 Compare Register 1 PWC21 R/W XXXXXXXXB
1956HPWM1 Select Register 1 PWS11 R/W _ _ 0 0 0 0 0 0 B
1957HPWM2 Select Register 1 PWS21 R/W _ 0 0 0 0 0 0 0 B
1958HPWM1 Compare Register 2 PWC12 R/W
Stepping Motor
Controller 2
XXXXXXXXB
1959HPWM2 Compare Register 2 PWC22 R/W XXXXXXXXB
195AHPWM1 Select Register 2 PWS12 R/W _ _ 0 0 0 0 0 0 B
195BHPWM2 Select Register 2 PWS22 R/W _ 0 0 0 0 0 0 0 B
195CHPWM1 Compare Register 3 PWC13 R/W
Stepping Motor
Controller 3
XXXXXXXXB
195DHPWM2 Compare Register 3 PWC23 R/W XXXXXXXXB
195EHPWM1 Select Register 3 PWS13 R/W _ _ 0 0 0 0 0 0 B
195FHPWM2 Select Register 3 PWS23 R/W _0 0 0 0 0 0 0 B
1960H to 19FFHReserved
1A00H to 1AFFHReserved for CAN Interface 0. Refer to section about CAN Controller
1B00H to 1BFFHReserved for CAN Interface 1. Refer to section about CAN Controller
1C00H to 1CFFHReserved for CAN Interface 0. Refer to section about CAN Controller
1D00H to 1DFFHReserved for CAN Interface 1. Refer to section about CAN Controller
1E00H to 1EFFHReserved
MB90590/590G Series
27
(Continued)
Note: Initial value of “_” represents unused bit; “X” represents unknown value.
Addresses in the rage 0000H to 00FFH, which are not listed in the table, are reserved for the primary functions
of the MCU . A read access to these reserved addresses results in reading “X”, and an y write access should
not be performed.
Address Register Abbreviation Access Peripheral Initial value
1FF0HProgram Address Detection
Register 0 (low-order) PADR0 R/W
Address Match
Detection
Function
XXXXXXXX B
1FF1HProgram Address Detection
Register 0 (middle-order) PADR0 R/W XXXXXXXX B
1FF2HProgram Address Detection
Register 0 (high-order) PADR0 R/W XXXXXXXX B
1FF3HProgram Address Detection
Register 1 (low-order) PADR1 R/W XXXXXXXX B
1FF4HProgram Address Detection
Register 1 (middle-order) PADR1 R/W XXXXXXXX B
1FF5HProgram Address Detection
Register 1 (high-order) PADR1 R/W XXXXXXXX B
1FF6H to 1FFFHReserved
MB90590/590G Series
28
■
■■
■CAN CONTROLLERS
The CAN controller has the following features:
• Conforms to CAN Specification Version 2.0 Part A and B
- Supports transmission/reception in standard frame and extended frame formats
• Supports transmission of data frames by receiving remote frames
• 16 transmitting/receiving message buffers
- 29-bit ID and 8-byte data
- Multi-level message buffer configuration
• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message
buffer as 1D acceptance mask
- Two acceptance mask registers in either standard frame format or extended frame formats
• Bit rate programmable from 10 Kbit/s to 2 Mbit/s (when input clock is at 16 MHz)
List of Control Registers
Address Register Abbreviation Access Initial Value
CAN0 CAN1
000070H000080HMessage buffer valid register BVALR R/W 00000000 00000000B
000071H000081H
000072H000082HTransmit request register TREQR R/W 00000000 00000000B
000073H000083H
000074H000084HTransmit cancel register TCANR W 00000000 00000000B
000075H000085H
000076H000086HTransmit complete register TCR R/W 00000000 00000000B
000077H000087H
000078H000088HReceive complete register RCR R/W 00000000 00000000B
000079H000089H
00007AH00008AHRemote request receiving register RRTRR R/W 00000000 00000000B
00007BH00008BH
00007CH00008CHReceive overrun register ROVRR R/W 00000000 00000000B
00007DH00008DH
00007EH00008EHReceive interrupt enable register RIER R/W 00000000 00000000B
00007FH00008FH
MB90590/590G Series
29
List of Control Registers
Address Register Abbreviation Access Initial Value
CAN0 CAN1
001C00H001D00HControl status register CSR R/W, R 00---000 0----0-1B
001C01H001D01H
001C02H001D02HLast event indicator register LEIR R/W -------- 000-0000B
001C03H001D03H
001C04H001D04HReceive/transmit error counter RTEC R 00000000 00000000B
001C05H001D05H
001C06H001D06HBit timing register BTR R/W -1111111 11111111B
001C07H001D07H
001C08H001D08HIDE register IDER R/W XXXXXXXX
XXXXXXXXB
001C09H001D09H
001C0AH001D0AHTransmit RTR register TRTRR R/W 00000000 00000000B
001C0BH001D0BH
001C0CH001D0CHRemote frame receive waiting register RFWTR R/W XXXXXXXX
XXXXXXXXB
001C0DH001D0DH
001C0EH001D0EHTransmit interrupt enable register TIER R/W 00000000 00000000B
001C0FH001D0FH
001C10H001D10H
Acceptance mask select register AMSR R/W
XXXXXXXX
XXXXXXXXB
001C11H001D11H
001C12H001D12HXXXXXXXX
XXXXXXXXB
001C13H001D13H
001C14H001D14H
Acceptance mask register 0 AMR0 R/W
XXXXXXXX
XXXXXXXXB
001C15H001D15H
001C16H001D16HXXXXX--- XXXXXXXXB
001C17H001D17H
001C18H001D18H
Acceptance mask register 1 AMR1 R/W
XXXXXXXX
XXXXXXXXB
001C19H001D19H
001C1AH001D1AHXXXXX--- XXXXXXXXB
001C1BH001D1BH
MB90590/590G Series
30
List of Message Buffers (ID Registers)
(Continued)
Address Register Abbreviation Access Initial Value
CAN0 CAN1
001A20H001B20H
ID register 0 IDR0 R/W
XXXXXXXX XXXXXXXXB
001A21H001B21H
001A22H001B22HXXXXX--- XXXXXXXXB
001A23H001B23H
001A24H001B24H
ID register 1 IDR1 R/W
XXXXXXXX XXXXXXXXB
001A25H001B25H
001A26H001B26HXXXXX--- XXXXXXXXB
001A27H001B27H
001A28H001B28H
ID register 2 IDR2 R/W
XXXXXXXX XXXXXXXXB
001A29H001B29H
001A2AH001B2AHXXXXX--- XXXXXXXXB
001A2BH001B2BH
001A2CH001B2CH
ID register 3 IDR3 R/W
XXXXXXXX XXXXXXXXB
001A2DH001B2DH
001A2EH001B2EHXXXXX--- XXXXXXXXB
001A2FH001B2FH
001A30H001B30H
ID register 4 IDR4 R/W
XXXXXXXX XXXXXXXXB
001A31H001B31H
001A32H001B32HXXXXX--- XXXXXXXXB
001A33H001B33H
001A34H001B34H
ID register 5 IDR5 R/W
XXXXXXXX XXXXXXXXB
001A35H001B35H
001A36H001B36HXXXXX--- XXXXXXXXB
001A37H001B37H
001A38H001B38H
ID register 6 IDR6 R/W
XXXXXXXX XXXXXXXXB
001A39H001B39H
001A3AH001B3AHXXXXX--- XXXXXXXXB
001A3BH001B3BH
001A3CH001B3CH
ID register 7 IDR7 R/W
XXXXXXXX XXXXXXXXB
001A3DH001B3DH
001A3EH001B3EHXXXXX--- XXXXXXXXB
001A3FH001B3FH
MB90590/590G Series
31
(Continued)
Address Register Abbreviation Access Initial Value
CAN0 CAN1
001A40H001B40H
ID register 8 IDR8 R/W
XXXXXXXX XXXXXXXXB
001A41H001B41H
001A42H001B42HXXXXX--- XXXXXXXXB
001A43FH001B43H
001A44H001B44H
ID register 9 IDR9 R/W
XXXXXXXX XXXXXXXXB
001A45H001B45H
001A46H001B46HXXXXX--- XXXXXXXXB
001A47H001B47H
001A48H001B48H
ID register 10 IDR10 R/W
XXXXXXXX XXXXXXXXB
001A49H001B49H
001A4AH001B4AHXXXXX--- XXXXXXXXB
001A4BH001B4BH
001A4CH001B4CH
ID register 11 IDR11 R/W
XXXXXXXX XXXXXXXXB
001A4DH001B4DH
001A4EH001B4EHXXXXX--- XXXXXXXXB
001A4FH001B4FH
001A50H001B50H
ID register 12 IDR12 R/W
XXXXXXXX XXXXXXXXB
001A51H001B51H
001A52H001B52HXXXXX--- XXXXXXXXB
001A53H001B53H
001A54H001B54H
ID register 13 IDR13 R/W
XXXXXXXX XXXXXXXXB
001A55H001B55H
001A56H001B56HXXXXX--- XXXXXXXXB
001A57H001B57H
001A58H001B58H
ID register 14 IDR14 R/W
XXXXXXXX XXXXXXXXB
001A59H001B59H
001A5AH001B5AHXXXXX--- XXXXXXXXB
001A5BH001B5BH
001A5CH001B5CH
ID register 15 IDR15 R/W
XXXXXXXX XXXXXXXXB
001A5DH001B5DH
001A5EH001B5EHXXXXX--- XXXXXXXXB
001A5FH001B5FH
MB90590/590G Series
32
List of Message Buffers (DLC Registers and Data Registers)
(Continued)
Address Register Abbreviation Access Initial Value
CAN0 CAN1
001A60H001B60HDLC register 0 DLCR0 R/W ----XXXXB
001A61H001B61H
001A62H001B62HDLC register 1 DLCR1 R/W ----XXXXB
001A63H001B63H
001A64H001B64HDLC register 2 DLCR2 R/W ----XXXXB
001A65H001B65H
001A66H001B66HDLC register 3 DLCR3 R/W ----XXXXB
001A67H001B67H
001A68H001B68HDLC register 4 DLCR4 R/W ----XXXXB
001A69H001B69H
001A6AH001B6AHDLC register 5 DLCR5 R/W ----XXXXB
001A6BH001B6BH
001A6CH001B6CHDLC register 6 DLCR6 R/W ----XXXXB
001A6DH001B6DH
001A6EH001B6EHDLC register 7 DLCR7 R/W ----XXXXB
001A6FH001B6FH
001A70H001B70HDLC register 8 DLCR8 R/W ----XXXX
001A71H001B71H
001A72H001B72HDLC register 9 DLCR9 R/W ----XXXXB
001A73H001B73H
001A74H001B74HDLC register 10 DLCR10 R/W ----XXXXB
001A75H001B75H
001A76H001B76HDLC register 11 DLCR11 R/W ----XXXXB
001A77H001B77H
001A78H001B78HDLC register 12 DLCR12 R/W ----XXXXB
001A79H001B79H
001A7AH001B7AHDLC register 13 DLCR13 R/W ----XXXXB
001A7BH001B7BH
001A7CH001B7CHDLC register 14 DLCR14 R/W ----XXXXB
001A7DH001B7DH
001A7EH001B7EHDLC register 15 DLCR15 R/W ----XXXXB
001A7FH001B7FH
001A80H
to
001A87H
001B80H
to
001B87HData register 0 (8 bytes) DTR0 R/W XXXXXXXXB
to
XXXXXXXXB
MB90590/590G Series
33
(Continued)
Address Register Abbreviation Access Initial Value
CAN0 CAN1
001A88H
to
001A8FH
001B88H
to
001B8FHData register 1 (8 bytes) DTR1 R/W XXXXXXXXB
to
XXXXXXXXB
001A90H
to
001A97H
001B90H
to
001B97HData register 2 (8 bytes) DTR2 R/W XXXXXXXXB
to
XXXXXXXXB
001A98H
to
001A9FH
001B98H
to
001B9FHData register 3 (8 bytes) DTR3 R/W XXXXXXXXB
to
XXXXXXXXB
001AA0H
to
001AA7H
001BA0H
to
001BA7HData register 4 (8 bytes) DTR4 R/W XXXXXXXXB
to
XXXXXXXXB
001AA8H
to
001AAFH
001BA8H
to
001BAFHData register 5 (8 bytes) DTR5 R/W XXXXXXXXB
to
XXXXXXXXB
001AB0H
to
001AB7H
001BB0H
to
001BB7HData register 6 (8 bytes) DTR6 R/W XXXXXXXXB
to
XXXXXXXXB
001AB8H
to
001ABFH
001BB8H
to
001BBFH
Data register 7 (8 bytes) DTR7 R/W XXXXXXXXB
to
XXXXXXXXB
001AC0H
to
001AC7H
001BC0H
to
001BC7HData register 8 (8 bytes) DTR8 R/W XXXXXXXXB
to
XXXXXXXXB
001AC8H
to
001ACFH
001BC8H
to
001BCFHData register 9 (8 bytes) DTR9 R/W XXXXXXXXB
to
XXXXXXXXB
001AD0H
to
001AD7H
001BD0H
to
001BD7HData register 10 (8 bytes) DTR10 R/W XXXXXXXXB
to
XXXXXXXXB
001AD8H
to
001ADFH
001BD8H
to
001BDFHData register 11 (8 bytes) DTR11 R/W XXXXXXXXB
to
XXXXXXXXB
001AE0H
to
001AE7H
001BE0H
to
001BE7HData register 12 (8 bytes) DTR12 R/W XXXXXXXXB
to
XXXXXXXXB
001AE8H
to
001AEFH
001BE8H
to
001BEFHData register 13 (8 bytes) DTR13 R/W XXXXXXXXB
to
XXXXXXXXB
001AF0H
to
001AF7H
001BF0H
to
001BF7HData register 14 (8 bytes) DTR14 R/W XXXXXXXXB
to
XXXXXXXXB
001AF8H
to
001AFFH
001BF8H
to
001BFFHData register 15 (8 bytes) DTR15 R/W XXXXXXXXB
to
XXXXXXXXB
MB90590/590G Series
34
■
■■
■INTERRUPT MAP
Interrupt cause I2OS
clear Interrupt vector Interrupt control register
Number Address Number Address
Reset N/A # 08 FFFFDCH
INT9 instruction N/A # 09 FFFFD8H
Exception N/A # 10 FFFFD4H
Time Base Timer N/A # 11 FFFFD0HICR00 0000B0H
External Interrupt (INT0 to INT7) *1 # 12 FFFFCCH
CAN 0 RX N/A # 13 FFFFC8HICR01 0000B1H
CAN 0 TX/NS N/A # 14 FFFFC4H
CAN 1 RX N/A # 15 FFFFC0HICR02 0000B2H
CAN 1 TX/NS N/A # 16 FFFFBCH
8/16 bit PPG 0/1 N/A # 17 FFFFB8HICR03 0000B3H
8/16 bit PPG 2/3 N/A # 18 FFFFB4H
8/16 bit PPG 4/5 N/A # 19 FFFFB0HICR04 0000B4H
8/16 bit PPG 6/7 N/A # 20 FFFFACH
8/16 bit PPG 8/9 N/A # 21 FFFFA8HICR05 0000B5H
8/16 bit PPG A/B N/A # 22 FFFFA4H
16-bit Reload Timer 0 *1 # 23 FFFFA0HICR06 0000B6H
16-bit Reload Timer 1 *1 # 24 FFFF9CH
Input Capture 0/1 *1 # 25 FFFF98HICR07 0000B7H
Output compare 0/1 *1 # 26 FFFF94H
Input Capture 2/3 *1 # 27 FFFF90HICR08 0000B8H
Output Compare 2/3 *1 # 28 FFFF8CH
Input Capture 4/5 *1 # 29 FFFF88HICR09 0000B9H
Output Compare 4/5 *1 # 30 FFFF84H
8/10 bit A/D Converter *1 # 31 FFFF80HICR10 0000BAH
I/O Timer/Watch Timer N/A # 32 FFFF7CH
Serial I/O *1 # 33 FFFF78HICR11 0000BBH
Sound Generator N/A # 34 FFFF74H
UART 0 RX *2 # 35 FFFF70HICR12 0000BCH
UART 0 TX *1 # 36 FFFF6CH
UART 1 RX *2 # 37 FFFF68HICR13 0000BDH
UART 1 TX *1 # 38 FFFF64H
UART 2 RX *2 # 39 FFFF60HICR14 0000BEH
UART 2 TX *1 # 40 FFFF5CH
Flash Memory N/A # 41 FFFF58HICR15 0000BFH
Delayed interrupt N/A # 42 FFFF54H
MB90590/590G Series
35
*1:The interrupt request flag is cleared by the I2OS interrupt clear signal.
*2:The interrupt request flag is cleared by the I2OS interrupt clear signal. A stop request is available.
N/A:The interrupt request flag is not cleared by the I2OS interrupt clear signal.
Note:•For a peripheral module with two interrupt for a single interrupt number, both interrupt request flags are
cleared by the I2OS interrupt clear signal.
•At the end of I2OS, the I2OS clear signal will be asserted for all the interrupt flags assigned to the same in-
terrupt number. If one interrupt flag starts the I2OS and in the meantime another interrupt flag is set by a
hardware event, the later event is lost because the flag is cleared by the I2OS clear signal caused by the
first event. So it is recommended not to use the I2OS for this interrupt number.
•If I2OS is enabled, I2OS is initiated when one of the two interrupt signals in the same interrupt control register
(ICR) is asserted. This means that different interrupt sources share the same I2OS Descriptor which should
be unique for each interrupt source. For this reason, when one interrupt source uses the I2OS, the other
interrupt should be disabled.
MB90590/590G Series
36
■
■■
■ELECTRICAL CHARACTERISTICS
1. Absolute Maximu m Ratings (VSS = AVSS = 0.0 V)
*1:AVCC, AVRL and AVRL should not exceed VCC and AVRL should not exceed AVRH.
*2:VI and VO should not exceed VCC + 0.3V. VI should not exceed the specified ratings. However if the maximum
current to/from an input is limited by some means with e xternal components, the ICLAMP rating supersedes the VI
rating.
*3:The maximum output current is a peak value for a corresponding pin.
*4:Average output current is an average current value observed for a 100 ms period for a corresponding pin.
*5:Total average current is an average current value observed for a 100 ms period for all corresponding pins.
Note: Average output current = operating current × operating efficiency
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Parameter Symbol Rating Unit Remarks
Min. Max.
Power supply voltage
VCC VSS − 0.3 VSS + 6.0 V
AVCC VSS − 0.3 VSS + 6.0 V VCC = AVCC *1
AVRH,
AVRL VSS − 0.3 VSS + 6.0 V AVCC ≥ AVRH/L, AVRH ≥ AVRL *1
DVCC VSS − 0.3 VSS + 6.0 V VCC ≥ DVCC
Input voltage VIVSS − 0.3 VSS + 6.0 V *2
Output voltage VOVSS − 0.3 VSS + 6.0 V *2
Clamp Current ICLAMP −2.0 2.0 mA
"L" level max. output current IOL1 — 15 mA Normal output *3
"L" level avg. output current IOLAV1 — 4 mA Normal output, average value *4
"L" level max. output current IOL2 — 40 mA High current output *3
"L" level avg. output current IOLAV2 — 30 mA High current output, average value *4
"L" level max. overall output current
∑IOL1 — 100 mA Total normal output
"L" level max. overall output current
∑IOL2 330 mA Total high current output
"L" level avg. overall output current
∑IOLAV1 — 50 mA Total normal output, average value *5
"L" level avg. overall output current
∑IOLAV2 250 mA
Total high current output, average value
*5
"H" level max. output current IOH1 — –15 mA Normal output *3
"H" level avg. output current IOHAV1 — –4 mA Normal output, average value *4
"H" level max. output current IOH2 — –40 mA High current output *3
"H" level avg. output current IOHAV2 — –30 mA High current output, average value *4
"H" level max. overall output current
∑IOH1 — –100 mA Total normal output
"H" level max. overall output current
∑IOH2 — –330 mA Total high current output
"H" level avg. overall output current
∑IOHAV1 — –50 mA Total normal output, average value *5
"H" level avg. overall output current
∑IOHAV2 — –250 mA
Total high current output, average value
*5
Power consumption PD— 500 mW MB90F594A, MB90F591A, MB90F594G
— 400 mW MB90594, MB90591, MB90594G
Operating temperature TA–40 +85 °C
Storage temperature TSTG –55 +150 °C
MB90590/590G Series
37
2. Recommended Conditions (VSS = AVSS = 0.0 V)
*: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to
be connected to the VCC pin must have a capacitance value higher than CS.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter Symbol Value Unit Remarks
Min. Typ. Max.
Power supply voltage VCC
AVCC
4.5 5.0 5.5 V Under normal operation MB90V590A
MB90V590G
MB90F594A
MB90F594G
MB90594
MB90594G
3.0 — 5.5 V Maintains RAM data in
stop mode
4.75 5.0 5.25 V Under normal operation MB90F591A
MB90591
3.0 — 5.25 V Maintains RAM data in
stop mode
Smooth capacitor CS0.022 0.1 1.0 µF*
Operating temperature TA–40 — +85 °C
C
CS
•C Pin Connection Diagram
MB90590/590G Series
38
3. DC Characteristics (MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G:
VCC = 5.0 V±10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
(MB90F591A, MB90591: VCC = 5.0 V±5 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
*: Current values are tentative and subject to change without notice according to improvements in the character-
istics. The power supply current testing conditions are when using the external clock.
(Continued)
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Typ. Max.
Input H
voltage VIHS CMOS hys-
teresis input — 0.8 VCC —VCC +0.3 V
VIHM MD input — VCC – 0.3 — VCC +0.3 V
Input L
voltage VILS CMOS hys-
teresis input —VSS – 0.3 — 0.6VCC V
VILM MD input — VSS – 0.3 — VSS + 0.3 V
Output H
voltage
VOH1 Normal
output VCC = 4.5 V,
IOH1 = –4.0 mA VCC – 0.5 — — V
VOH2 High current
output VCC = 4.5 V,
IOH2 = –30.0 mA VCC – 0.5 — — V
Output L
voltage
VOL1 Normal
output VCC = 4.5 V,
IOL1 = 4.0 mA ——0.4V
VOL2 High current
output VCC = 4.5 V,
IOL2 = 30.0 mA ——0.5V
Input leak
current IIL —VCC = 5.5 V,
VSS < VI < VCC –5 — 5 µA
Analog input
leak current IIAL AN0 to AN7 VCC = 5.5 V,
AVSS < VI < AVCC –1 — 1 µA
Power
supply
current *
ICC
VCC
VCC = 5.0 V±10%,
Internal frequency:
16 MHz,
At normal opera-
tion.
—3760mA
MB90594/594G
—5080mA
MB90F594A/F594G
—5080mA
MB90F591A
—4560mA
MB90591
ICCS
VCC = 5.0 V±10%,
Internal frequency:
16 MHz,
At Sleep mode.
—1320mA
MB90594/594G
—1523mA
MB90F594A/F594G
—1523mA
MB90F591A
—1523mA
MB90591
ICTS
VCC = 5.0 V±10%,
Internal frequency:
2 MHz,
At Timer mode
—0.30.6mA
MB90594/594G
— 0.35 0.6 mA MB90F594A/F594G
— 0.35 0.6 mA MB90F591A
— 0.35 0.6 mA MB90591
ICCH VCC = 5.0 V±10%,
At Stop mode,
TA = 25°C
—520µAMB90594/594G
—520µAMB90F594A/F594G
—520µAMB90F591A
—520µAMB90591
MB90590/590G Series
39
(Continued)
(MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G:
VCC = 5.0 V±10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
(MB90F591A, MB90591: VCC = 5.0 V±5 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Typ. Max.
Input
capacity CIN
Other than C,
AVCC, AVSS,
AVRH,
AVRL, VCC,
VSS, DVCC,
DVSS,
P70 to P87
——515pF
P70 to P87 — — 15 30 pF
MB90590/590G Series
40
4. AC Characteristics
(1) Cloc k Timing (MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G:
VCC = 5.0 V±10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
(MB90F591A, MB90591: VCC = 5.0 V±5 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
*: Frequency deviation indicates the maximum frequency diff erence from the target frequency when using a multi-
plied clock.
Example of Oscillation circuit
Parameter Symbol Pin
name Value Unit Remarks
Min. Typ. Max.
Oscillation frequency fCX0, X1 3 — 5 MHz When using an oscillation circuit.
3 — 16 MHz When using an external clock.
Oscillation cycle time tCYL X0, X1 200 — 333 ns When using an oscillation circuit.
62.5 — 333 ns When using an external clock.
Frequency deviation with PLL* ∆f———5%
Input clock pulse width PWH, PWL X0 10 — — ns Duty ratio is about 30 to 70%.
Input clock rise and fall time tCR, tCF X0 — — 5 ns When using external clock
Machine clock frequency fCP —1.5—16MHz
Machine clock cycle time tCP — 62.5 — 666 ns
Flash read cycle time t CYCFL —— 2 tCP — ns When Flash is accessed by CPU
+α
Central frequency f
O
−α
∆fα
fo
------ 100%×=
tCYL
PWH
tCF
PWL
tCR
0.8 VCC
0.2 VCC
X0
•Clock Timing
X0 X1
R
C1 C2
MB90590/590G Series
41
• Guaranteed operation range
Guaranteed PLL operation range
(MB90F591A, MB90591)
Guaranteed operation range (MB90V590A, MB90F594A, MB90594,
MB90V590G, MB90F594G, MB90594G)
Guaranteed operation range (MB90F591A, MB90591)
Guaranteed PLL operation range
(MB90V590A, MB90F594A, MB90594,
MB90V590G, MB90F594G, MB90594G)
5.5
5.25
4.75
4.5
3.0
Power supply voltage
VCC (V)
1.5 8 16
Machine clock fCP (MHz)
16
12
4
9
8
3 4 8 16
Machine clock
fCP (MHz)
External clock fC (MHz)*
• External clock frequency and machine clock frequency
×4×3×2×1
×1/2
(PLL off)
*: When using the oscillation circuit, the maximum oscillation clock frequency is 5 MHz.
MB90590/590G Series
42
(2) Reset and Hardware Standby Input
(MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G:
VCC = 5.0 V±10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
(MB90F591A, MB90591: VCC = 5.0 V±5 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
*1:“tcp” represents one cycle time of the machine clock.
No reset can fully initialize the Flash Memory if it is performing the automatic algorithm.
*2:Oscillation time of oscillator is time that the amplitude reached the 90%.
In the crystal oscillator, the oscillation time is between sev eral ms to tens of ms . In FAR / ceramic oscillator, the
oscillation time is between hundreds of µs to several ms. In the external clock, the oscillation time is 0 ms.
Parameter Symbol Pin name Value Unit Remarks
Min. Max.
Reset input time tRSTL RST 16 tCP*1— ns Under normal operation
Oscillation time of
oscillator*2 + 16 tCP*1— ms In stop mode
Hardware standby input time tHSTL HST 16 tCP*1— ns Under normal operation
0.6 VCC
RST
HST
tRSTL, tHSTL
0.6 VCC
Under Normal Operation
tRSTL
0.6VCC 0.6VCC
RST
X0
16 tCP
Internal operation clock
Internal reset
Oscillation time of
oscillator Oscillation setting time
Instruction execution
90% of
amplitude
In Stop Mode
MB90590/590G Series
43
(3) Power On Reset (MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G:
VCC = 5.0 V±10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
(MB90F591A, MB90591: VCC = 5.0 V±5 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Note • VCC must be kept lower than 0.2 V before power-on.
• The above values are used for creating a power-on reset.
• Some registers in the de vice are initializ ed only upon a po wer-on reset. To initialize these register, turn on
the power supply using the above values.
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Max.
Power on rise time tRVCC —0.05 30 ms
Power off time tOFF VCC 50 — ms Due to repetitive operation
tR
2.7 V
0.2 V
VCC
0.2 V0.2 V
tOFF
Sudden changes in the power supply voltage may cause a power-on reset.
To change the power supply voltage while the device is in operation, it is recommended to
raise the voltage smoothly to suppress fluctuations as shown below.
In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1
V or fewer per second, however, you can use the PLL clock.
VCC
VSS
3V
RAM data being held
It is recommended to keep the
rising speed of the supply voltage
at 50 mV/ms or slower.
MB90590/590G Series
44
(4) UART0/1/2, Serial I/O (MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G:
VCC = 5.0 V±10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
(MB90F591A, MB90591: VCC = 5.0 V±5 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
*: tCP is the machine cycle (Unit: ns)
Notes: • AC characteristic in CLK synchronized mode.
• CL is load capacity value of pins when testing.
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Max.
Serial clock cycle time tSCYC SCK0 to SCK3
Internal clock opera-
tion output pins are
CL = 80 pF + 1 TTL.
8 tCP*— ns
SCK ↓ ⇒ SOT delay time tSLOV SCK0 to SCK3,
SOT0 to SOT3 –80 80 ns
Valid SIN ⇒ SCK ↑tIVSH SCK0 to SCK3,
SIN0 to SIN3 100 — ns
SCK ↑ ⇒ Valid SIN hold time tSHIX SCK0 to SCK3,
SIN0 to SIN3 60 — ns
Serial clock "H" pulse width tSHSL SCK0 to SCK3
External clock oper-
ation output pins are
CL = 80 pF + 1 TTL.
4 tCP —ns
Serial clock "L" pulse width tSLSH SCK0 to SCK3 4 tCP —ns
SCK ↓ ⇒ SOT delay time tSLOV SCK0 to SCK3,
SOT0 to SOT3 — 150 ns
Valid SIN ⇒ SCK ↑tIVSH SCK0 to SCK3,
SIN0 to SIN3 60 — ns
SCK ↑ ⇒ Valid SIN hold time tSHIX SCK0 to SCK3,
SIN0 to SIN3 60 — ns
SCK 2.4 V
tSCYC
0.8 V
SOT 0.8 V
2.4 V
0.8 V
tSLOV
SIN 0.6 VCC
0.8 VCC
tIVSH
0.6 VCC
0.8 VCC
tSHIX
• Internal Shift Clock Mode
MB90590/590G Series
45
(5)Timer Input Timing (MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G:
VCC = 5.0 V±10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
(MB90F591A, MB90591: VCC = 5.0 V±5 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Max.
Input pulse width tTIWH TIN0 —4 tCP — ns Under normal operation
tTIWL IN0 to IN5 1 — µs In stop mode
SCK 0.8 VCC
tSLSH
0.6 VCC
SOT 0.8 V
2.4 V
tSLOV
SIN 0.6 VCC
0.8 VCC
tIVSH
0.6 VCC
0.8 VCC
tSHIX
0.8 VCC
0.6 VCC
tSHSL
• External Shift Clock Mode
0.6 VCC
0.8 VCC
tTIWH
0.6 VCC
0.8 VCC
tTIWL
•Timer Input Timing
MB90590/590G Series
46
(6)Trigger Input Timing (MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G:
VCC = 5.0 V±10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
(MB90F591A, MB90591: VCC = 5.0 V±5 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
(7) Slew Rate High Current Outputs (MB90F591A, MB90591, MB90594G and MB90F594G only)
(MB90F594G, MB90594G: VCC = 5.0 V±10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
(MB90F591A, MB90591: VCC = 5.0 V±5 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Max.
Input pulse width tTRGH
tTRGL INT0 to
INT7, ADTG —5 tCP —ns
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Max.
Output Rise/Fall time tR2
tF2 Port P70 to P77,
Port P80 to P87 —1540ns
0.6 VCC
0.8 VCC
tTRGH
0.6 VCC
0.8 VCC
tTRGL
• Trigger Input Timing
• Slew Rate Output Timing
VH
VL
tR2
VH
VL
tF2
VH = VOL2 + 0.1 × (VOH2 − VOL2)
VL = VOL2 + 0.9 × (VOH2 − VOL2)
MB90590/590G Series
47
5. A/D Converter
(MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G:
VCC = AVCC = 5.0 V±10 %, VSS = AVSS = 0.0 V, 3.0 V ≤ AVR+ − AVR-, TA = −40 °C to +85 °C)
(MB90F591A, MB90591: VCC = AVCC = 5.0 V±5 %, VSS = AVSS = 0.0 V, 3.0 V ≤ AVR+ − AVR-, TA = −40 °C to +85 °C)
*: When not operating A/D converter, this is the current (VCC = AVCC = AVRH = 5.0 V) when the CPU is stopped.
Parameter Symbol Pin name Value Unit Remarks
Min. Typ. Max.
Resolution — — — — 10 bit
Conversion error — — — — ±5.0 LSB
Nonlinearity error — — — — ±2.5 LSB
Differential linearity
error —— — —±1.9 LSB
Zero transition voltage VOT AN0 to AN7 AVRL
– 3.5 LSB AVRL
+ 0.5 LSB AVRL
+ 4.5 LSB mV
Full scale transition voltage VFST AN0 to AN7 AVRH
– 6.5 LSB AVRH
– 1.5 LSB AVRH
+ 1.5 LSB mV
Compare time — — 352tCP ——ns
Internal
frequency :
16 MHz
Sampling time — — 64tCP ——ns
Internal
frequency :
16 MHz
Analog port input current IAIN AN0 to AN7 -1 — +1 µA
Analog input voltage range VAIN AN0 to AN7 AVRL — AVRH V
Reference voltage range — AVRH AVRL + 2.7 — AVCC V
— AVRL 0 — AVRH – 2.7 V
Power supply current IAAVCC —5—mA
IAH AVCC —— 5µA*
Reference voltage current IRAVRH — 400 600 µA
MB90594
MB90V590A
MB90V590G
MB90F594A
MB90F594G
MB90F591A
— 140 600 µAMB90594G
MB90591
IRH AVRH — — 5 µA*
Offset between input
channels — AN0 to AN7 — — 4 LSB
MB90590/590G Series
48
6. A/D Converter Glossary
Resolution: Analog changes that are identifiable with the A/D converter
Linearity error: The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00
0000 0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual
conversion characteristics
Differential linearity error:The deviation of input voltage needed to change the output code by 1 LSB from the
theoretical value
Total error :The total error is defined as a difference between the actual value and the theoretical value, which
includes zero-transition error/full-scale transition error and linearity error.
(Continued)
Total error
3FF
3FE
3FD
004
003
002
001
Analog inputAVRL AVRH
Actual conversion
value
Digital output
VNT
(measured value)
0.5 LSB
Actual conversion
characteristics
Theoretical
characteristics
0.5 LSB
{1 LSB × (N – 1) + 0.5 LSB}
[V]
AVRH – AVRL
1024
1 LSB = (Theoretical value)
VOT (Theoretical value) = AVRL + 0.5 LSB[V]
VFST (Theoretical value) = AVRH – 1.5 LSB[V]
Total error for digital output N [LSB]
VNT – {1 LSB × (N – 1) + 0.5 LSB}
1 LSB
=
VNT: Voltage at a transition of digital output from (N – 1) to N
MB90590/590G Series
49
(Continued)
7. Notes on Using A/D Converter
Select the output impedance v alue for the e xternal circuit of analog input according to the follo wing conditions ,:
• Output impedance values of the external circuit of 15 kΩ or lower are recommended.
• When capacitors are connected to external pins, the capacitance of several thousand times the internal
capacitor v alue is recommended to minimized the eff ect of v oltage distribution between the e xternal capacitor
and internal capacitor.
When the output impedance of the external circuit is too high, the sampling period f or analog voltages ma y not
be sufficient (sampling period = 4.00 µs @machine clock of 16 MHz).
•Error
The smaller the | AVRH − AVRL |, the greater the error would become relatively.
Linearity error
3FF
3FE
3FD
004
003
002
001
Analog inputAVRL AVRH Analog inputAVRL AVRH
Actual conversion
characteristics
VOT (measured value)
VFST
(measured value)
Actual conversion
value
VNT
{1 LSB × (N – 1)+ VOT}
Theoretical
characteristics
Digital output
Digital output
Differential linearity error
Theoretical characteristics
V(N + 1)T
(measured value)
Actual conversion
value
VNT (measured value)
Actual conversion value
Linearity error of
digital output N
VOT: Voltage at transition of digital output from “000H” to “001H”
VFST: Voltage at transition of digital output from “3FEH” to “3FFH”
[LSB]
VNT – {1 LSB × (N – 1) + VOT}
1 LSB
=
[V]
VFST – VOT
1022
=
1 LSB
– 1 LSB [LSB]
V(N + 1)T – VNT
1 LSB
=
Differential linearity error
of digital N
N + 1
N
N – 1
N – 2
(measured value)
Comparator
Analog input
30 pF Max.
3.2 kΩ Max.
• Equipment of analog input circuit model
Note: Listed values must be considered as standards.
MB90590/590G Series
50
■
■■
■ORDERING INFORMATION
Part number Package Remarks
MB90594PF
MB90591PF
MB90594GPF
MB90F594GPF
MB90F594APF
MB90F591APF
100-pin Plastic QFP
(FPT-100P-M06)
MB90V590ACR
MB90V590GCR 256-pin Ceramic PGA
(PGA-256C-A01) For evaluation
MB90590/590G Series
51
■
■■
■PACKAGE DIMENSION
100-pin plastic QFP
(FPT-100P-M06)
Dimensions in mm (inches)
C
2000 FUJITSU LIMITED F100008-3C-3
"A"
"B"
0.53(.021)MAX
0.18(.007)MAX
Details of "A" part
0 10°
Details of "B" part
12.35(.486)
REF 16.30±0.40
(.642±.016)
0.05(.002)MIN
(STAND OFF)
0.15±0.05(.006±.002)
INDEX
23.90±0.40(.941±.016)
20.00±0.20(.787±.008)
17.90±0.4014.00±0.20
(.551±.008) (.705±.016)
0.13(.005) M
18.85(.742)REF
22.30±0.40(.878±.016)
130
31
50
5180
81
100
0.25(.010)
0.30(.012)
0.65(.0256)TYP 0.30±0.10
(.012±.004)
LEAD No.
0.80±0.20
(.031±.008)
3.35(.132)MAX
(Mounting height)
0.10(.004)
MB90590/590G Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Marketing Division
Electronic Devices
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Korea
Tel: +82-2-3484-7100
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F0104
FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, and
manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use,
and household use, but are not designed, developed and
manufactured as contemplated (1) for use accompanying fatal risks
or dangers that, unless extremely high safety is secured, could have
a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
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satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have inherently a certain rate of failure.
You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
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