ispLSI ® 1048
In-System Programmable High Density PLD
1
USE ispLSI 1048EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
1048_06
Functional Block Diagram
Output Routing Pool
Output Routing Pool
F7 F6 F5 F4 F3 F2 F1 F0
B0 B1 B2 B3 B4 B5 B6 B7
A0
A1
A2
A3
A4
A5
A6
A7
Output Routing Pool
Output Routing Pool
Output Routing Pool CLK
E7 E6 E5 E4 E3 E2 E1 E0
C0 C1 C2 C3 C4 C5 C6 C7
D7
D6
D5
D4
D3
D2
D1
D0
Output Routing Pool
Logic
Array
DQ
DQ
DQ
DQ
Global Routing Pool (GRP) GLB
Description
The ispLSI 1048 is a High-Density Programmable Logic
Device which contain 288 Registers, 96 Universal I/O
pins, ten Dedicated Input pins, four Dedicated Clock
Input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 1048 features 5-Volt in-system
programming and in-system diagnostic capabilities. It is
the first device which offers non-volatile reprogrammability
of the logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 1048 devices is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. F7 (see figure 1). There are a total of 48 GLBs in the
ispLSI 1048 device. Each GLB has 18 inputs, a program-
mable AND/OR/XOR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
other GLB on the device.
Features
• HIGH-DENSITY PROGRAMMABLE LOGIC
— 8000 PLD Gates
— 96 I/O Pins, Ten Dedicated Inputs
— 288 Registers
— High-Speed Global Interconnects
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— Security Cell Prevents Unauthorized Copying
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 80 MHz Maximum Operating Frequency
— fmax = 50 MHz for Industrial Devices
— tpd = 15 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile E2CMOS Technology
— 100% Tested
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable™ (ISP™) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEX-
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2000
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
Specifications ispLSI 1048
2
USE ispLSI 1048EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
The device also has 96 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered in-
put, latched input, output or bi-directional
I/O pin with 3-state control. Additionally, all outputs are
polarity selectable, active high or active low. The signal
levels are TTL compatible voltages and the output drivers
can source 4 mA or sink 8 mA.
Eight GLBs, 16 I/O cells, two dedicated inputs (one
dedicated input in Megablock B and E) and one ORP are
connected together to make a Megablock (see figure 1).
The outputs of the eight GLBs are connected to a set of
16 universal I/O cells by the ORP. The ispLSI 1048
device contains six of these Megablocks.
The GRP has as its inputs the outputs from all of the GLBs
and all of the inputs from the bi-directional I/O cells. All of
these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 1048 device are selected using the
Clock Distribution Network. Four dedicated clockpins
(Y0, Y1, Y2 and Y3) are brought into the distribution
network, and five clock outputs (CLK 0, CLK 1, CLK 2,
IOCLK 0 and IOCLK 1) are provided to route clocks to the
GLBs and I/O cells. The Clock Distribution Network can
also be driven from a special clock GLB (D0 on the
ispLSI 1048 device). The logic of this GLB allows the user
to create an internal clock from a combination of internal
signals within the device.
Functional Block Diagram
Figure 1. ispLSI 1048 Functional Block Diagram
Output Routing Pool (ORP)
B0 B1 B2 B3 B4 B5 B6 B7
Output Routing Pool (ORP)
C0 C1 C2 C3 C4 C5 C6 C7
Output Routing Pool (ORP)
F7 F6 F5 F4 F3 F2 F1 F0
Input Bus
Output Routing Pool (ORP)
E7 E6 E5 E4 E3 E2 E1 E0
Input Bus
A0
A1
A2
A3
A4
A5
A6
A7
Output Routing Pool (ORP)
Generic
Logic Blocks
(GLBs)
Megablock
Input Bus
Global
Routing
Pool
(GRP)
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
Clock
Distribution
Network
D7
D6
D5
D4
D3
D2
D1
D0
Output Routing Pool (ORP)
I/O
94
I/O
95 I/O
93 I/O
92 I/O
91 I/O
90 I/O
89I/O
88 I/O
87 I/O
86 I/O
85 I/O
84 I/O
83 I/O
82 I/O
81 I/O
80 IN
11 I/O
78
I/O
79 I/O
77 I/O
76 I/O
75 I/O
74 I/O
73I/O
72 I/O
71 I/O
70 I/O
69 I/O
68 I/O
67 I/O
66 I/O
65 I/O
64 IN
8
IN
10
I/O
17
I/O
16 I/O
18 I/O
19 I/O
20 I/O
21 I/O
22 I/O
23 I/O
24 I/O
25 I/O
26 I/O
27 I/O
28 I/O
29 I/O
30 I/O
31
SDO/
IN3 Y
0Y
1Y
2Y
3
I/O
33
I/O
32 I/O
34 I/O
35 I/O
36 I/O
37 I/O
38 I/O
39 I/O
40 I/O
41 I/O
42 I/O
43 I/O
44 I/O
45 I/O
46 I/O
47
SCLK/
IN 5
IN
4
IN 7
IN 6
I/O
6
I/O
6
I/O
6
I/O
6
I/O
5
I/O
5
I/O
5
I/O
5
I/O
5
I/O
5
I/O
5
I/O
5
I/O
5
I/O
5
I/O
4
I/O
4
I/O 0
I/O 1
I/O 2
I/O 3
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
SDI/IN 0
M
ODE/IN 1
I/O 4
I/O 5
ispEN
RESET
Input Bus Input Bus
lnput Bus
0139F(1)-48-isp
Specifications ispLSI 1048
3
USE ispLSI 1048EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
Absolute Maximum Ratings 1
Supply Voltage Vcc .................................. -0.5 to +7.0V
Input Voltage Applied........................-2.5 to VCC +1.0V
Off-State Output Voltage Applied .....-2.5 to VCC +1.0V
Storage Temperature................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
Commercial TA = 0°C to +70°C
Industrial TA = -40°C to +85°C
Input Low Voltage
Input High Voltage
V
V
PARAMETERSYMBOL MIN. MAX. UNITS
5.25
5.5
0.8
Vcc + 1
VIL
VIH
4.75
4.5
0
2.0
VCC Supply Voltage V
Capacitance (TA=25oC, f=1.0 MHz)
SYMBOL PARAMETER MAXIMUM
1
UNITS TEST CONDITIONS
C
1
Dedicated Input Capacitance 8 pf VCC=5.0V, VIN=2.0V
C
2
I/O and Clock Capacitance 10 pf VCC=5.0V, VI/O, VY=2.0V
1. Guaranteed but not 100% tested.
Data Retention Specifications
Table 2- 0008B
PARAMETER
Data Retention MINIMUM MAXIMUM UNITS
Erase/Reprogram Cycles 20
10000 —
—Years
Cycles
Specifications ispLSI 1048
4
USE ispLSI 1048EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
Switching Test Conditions
DC Electrical Characteristics
Over Recommended Operating Conditions
Figure 2. Test Load
+ 5V
R1
R2CL
*
Device
Output Test
Point
*
CL includes Test Fixture and Probe Capacitance.
Input Pulse Levels GND to 3.0V
Input Rise and Fall Time ≤ 3ns 10% to 90%
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V
Output Load See figure 2
3-state levels are measured 0.5V from steady-state
active level.
Table 2
-
0003
Output Load Conditions (see figure 2)
T est Condition R1 R2 CL
A 470Ω390Ω35pF
B Active High 390Ω35pF
Active Low 470Ω390Ω35pF
Active High to Z 390Ω5pF
Cat VOH - 0.5V
Active Low to Z 470Ω390Ω5pF
at VOL + 0.5V
∞
∞
0.4
–
-10
10
-150
-150
-200
235
260
V
V
µA
µA
µA
µA
mA
mA
mA
SYMBOL
V
OL
V
OH
I
IL
I
IH
I
IL-isp
I
IL-PU
I
OS
1
I
CC
2,4
Output Low Voltage
Output High Voltage
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
isp Input Low Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
Operating Power Supply Current
I
OL
=8 mA
I
OH
=-4 mA
0V ≤ V
IN
≤ V
IL
(MAX.)
3.5V ≤ V
IN
≤ V
CC
0V ≤ V
IN
≤ V
IL
(MAX.)
0V ≤ V
IN
≤ V
IL
V
CC
= 5V, V
OUT
= 0.5V
V
IL
= 0.5V, V
IH
= 3.0V Commercial
f
TOGGLE
= 1 MHz Industrial
CONDITION MIN. UNITS
MAX.TYP.
3
–
–
–
–
–
–
–
165
165
–
2.4
–
–
–
–
–
–
–
1. One output at a time for a maximum duration of one second. V
out
= 0.5V was selected to avoid test problems by tester ground
degradation. Characterized but not 100% tested.
2. Measured using twelve 16-bit counters.
3. T ypical values are at V
CC
= 5V and T
A
= 25oC.
4. Maximum I
CC
varies widely with specific device configuration and operating frequency. Refer to the Power Consumption sec-
tion of this datasheet and Thermal Management section of this Lattice Semiconductor Data Book or CD-ROM to estimate maximum
I
CC
.
PARAMETER
Table 2- 0007A-48-isp
Specifications ispLSI 1048
5
USE ispLSI 1048EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
18
23
–
–
–
–
12
–
–
14
–
17
–
20
20
–
–
–
–
–
–
71.4
41.7
83
9
–
0
12
–
0
–
10
–
–
6
6
2
6.5
15
20
–
–
–
–
10
–
–
12
–
17
–
18
18
–
–
–
–
1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-Bit loadable counter using GRP feedback.
4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
5. Reference Switching Test Conditions section.
MIN. MAX.
Data Propagation Delay, 4PT bypass, ORP bypass
Data Propagation Delay, Worst Case Path
Clock Frequency with Internal Feedback
3
Clock Frequency with External Feedback
Clock Frequency, Max Toggle
4
GLB Reg. Setup Time before Clock, 4PT bypass
GLB Reg. Clock to Output Delay, ORP bypass
GLB Reg.
Hold Time after Clock, 4 PT bypass
GLB Reg. Setup Time before Clock
GLB Reg. Clock to Output Delay
GLB Reg. Hold Time after Clock
Ext. Reset Pin to Output Delay
Ext. Reset Pulse Duration
Input to Output Enable
Input to Output Disable
Ext. Sync. Clock Pulse Duration, High
Ext. Sync. Clock Pulse Duration, Low
I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3)
I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tpd1
tpd2
fmax (Int.)
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
ten
tdis
twh
twl
tsu5
th5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
A
A
A
–
–
–
A
–
–
–
–
A
–
B
C
–
–
–
–
DESCRIPTION
1
PARAMETER #
2
UNITS
TEST
5
COND.
1
tsu2 + tco1
( )
MIN.
–
–
53.6
31.3
71.4
12
–
0
16
–
0
–
13
–
–
7
7
2.7
8.7
24
30.7
–
–
–
–
16
–
–
18.7
–
22.7
–
26.7
26.7
–
–
–
–
-50
MIN. MAX.
–
–
80
50
100
7
–
0
10
–
0
–
10
–
–
5
5
2
6.5
-80
Table 2- 0030A-48/80,70,50
MAX.
-70
External Timing Parameters
Over Recommended Operating Conditions
Specifications ispLSI 1048
6
USE ispLSI 1048EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
Internal Timing Parameters1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
8.1
0.9
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2.0
8.0
–
–
–
–
4.6
–
–
4.0
5.3
–
–
3.9
4.6
8.0
3.3
4.0
5.3
6.7
8.0
21.3
8.6
9.3
10.0
12.7
1.3
–
–
3.3
3.3
13.3
11.9
9.9
4.7
2.0
MIN. MAX.
DESCRIPTIONPARAMETER UNITS
-50
Inputs
tiobp
tiolat
tiosu
tioh
tioco
tior
tdin
GRP
tgrp1
tgrp4
tgrp8
tgrp12
tgrp16
tgrp48
GLB
t4ptbp
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgr
tptre
tptoe
tptck
ORP
torp
torpbp
#
2
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
I/O Register Bypass
I/O Latch Delay
I/O Register Setup Time before Clock
I/O Register Hold Time after Clock
I/O Register Clock to Out Delay
I/O Register Reset to Out Delay
Dedicated Input Delay
GRP Delay, 1 GLB Load
GRP Delay, 4 GLB Loads
GRP Delay, 8 GLB Loads
GRP Delay, 12 GLB Loads
GRP Delay, 16 GLB Loads
GRP Delay, 48 GLB Loads
4 Product Term Bypass Path Delay
1 Product Term/XOR Path Delay
20 Product Term/XOR Path Delay
XOR Adjacent Path Delay
3
GLB Register Bypass Delay
GLB Register Setup Time before Clock
GLB Register Hold Time after Clock
GLB Register Clock to Output Delay
GLB Register Reset to Output Delay
GLB Product Term Reset to Register Delay
GLB Product Term Output Enable to I/O Cell Delay
GLB Product Term Clock Delay
ORP Delay
ORP Bypass Delay
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
–
–
6.0
0.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1.5
6.0
–
–
–
–
3.5
–
–
3.0
4.0
–
–
3.0
3.5
6.0
2.5
3.0
4.0
5.0
6.0
16.0
6.5
7.0
7.5
9.5
1.0
–
–
2.5
2.5
10.0
9.0
7.5
3.5
1.5
MIN. MAX.
-70
–
–
5.3
1.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.8
5.0
–
–
–
–
2.9
–
–
2.5
3.3
–
–
2.5
2.9
5.0
2.1
2.5
3.3
4.2
5.0
13.3
5.4
6.5
7.6
8.4
0.8
–
–
2.1
2.1
8.3
8.8
6.3
3.2
1.3
MIN. MAX.
-80
Table 2- 0036A-48/80,70,50.eps
Specifications ispLSI 1048
7
USE ispLSI 1048EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
Internal Timing Parameters1
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
–
6.7
5.3
1.3
5.3
1.3
–
4.0
6.7
6.7
6.7
8.0
6.6
8.0
6.6
10.6
Outputs
tob
toen
todis
Clocks
tgy0
tgy1/2
tgcp
tioy2/3
tiocp
Global Reset
tgr
47
48
49
50
51
52
53
54
55
Output Buffer Delay
I/O Cell OE to Output Enabled
I/O Cell OE to Output Disabled
Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
Clock Delay, Y1 or Y2 to Global GLB Clock Line
Clock Delay, Clock GLB to Global GLB Clock Line
Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
Clock Delay, Clock GLB to I/O Cell Global Clock Line
Global Reset to GLB and I/O Registers
MIN. MAX.
DESCRIPTIONPARAMETER UNITS
-50
#2
–
–
–
5.0
4.0
1.0
4.0
1.0
–
3.0
5.0
5.0
5.0
6.0
5.0
6.0
5.0
8.0
MIN. MAX.
-70
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
–
–
–
4.2
3.3
0.8
3.3
0.8
–
2.5
4.2
4.2
4.2
5.0
4.2
5.0
4.2
9.2
MIN. MAX.
-80
Specifications ispLSI 1048
8
USE ispLSI 1048EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
ispLSI 1048 Timing Model
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
Feedback
4 PT Bypass
20 PT
XOR Delays
Control
PTs
GRP
Loading
Delay
Input
Register
Clock
Distribution
I/O Pin
(Input)
Y0
Y1,2,3
DQ
GRP 4 GLB Reg Bypass ORP Bypass
DQ
RST
RE
OE
CK
I/O Reg Bypass
I/O CellORPGLBGRPI/O Cell
#21 - 25 #27, 29,
30, 31, 32
#28 #33
#34, 35, 36
#51, 52,
53, 54 #42, 43,
44
#50
#45
#46
Reset
Ded. In #26
#20
RST
#55
#55
#37
#38, 39,
40, 41
#48, 49
#47
Derivations of tsu, th and tco from the Product Term Clock
1
t
su = Logic + Reg su - Clock (min)
=
(t
iobp +
t
grp4 +
t
20ptxor
)
+
(t
gsu
) - (t
iobp +
t
grp4 +
t
ptck(min)
)
=
(
#20 + #28 + #35
)
+
(
#38
) - (
#20 + #28 + #44
)
5.5 ns = (3.0 + 3.0 + 7.5) + (1.5) - (3.0 + 3.0 + 3.5)
t
h = Clock (max) + Reg h - Logic
=
(t
iobp +
t
grp4 +
t
ptck(max)
)
+
(t
gh
) - (t
iobp +
t
grp4 +
t
20ptxor
)
=
(
#20 + #28 + #44
)
+
(
#39
) - (
#20 + #28 + #35
)
6.0 ns = (3.0 + 3.0 + 7.5) + (6.0) - (3.0 + 3.0 + 7.5)
t
co = Clock (max) + Reg co + Output
=
(t
iobp +
t
grp4 +
t
ptck(max)
)
+
(t
gco
)
+
(t
orp +
t
ob
)
=
(
#20 + #28 + #44
)
+
(
#40
)
+
(
#45 + #47
)
22.5 ns = (3.0 + 3.0 +7.5) + (2.5) + (3.5 + 3.0)
Derivations of
tsu, th and tco from the Clock GLB
1
t
su = Logic + Reg su - Clock (min)
=
(t
iobp +
t
grp4 +
t
20ptxor
)
+
(t
gsu
) - (t
gy0(min) +
t
gco +
t
gcp(min)
)
=
(
#20 + #28 + #35
)
+
(
#38
) - (
#50 + #40 + #52
)
6.5 ns = (3.0 + 3.0 + 7.5) + (1.5) - (5.0 + 2.5 + 1.0)
t
h = Clock (max) + Reg h - Logic
=
(t
gy0(max) +
t
gco +
t
gcp(max)
)
+
(t
gh
) - (t
iobp +
t
grp4 +
t
20ptxor
)
=
(
#50 + #40 + #52
)
+
(
#39
) - (
#20 + #28 + #35
)
5.0 ns = (5.0 + 2.5 + 5.0) + (6.0) - (3.0 + 3.0 + 7.5)
t
co = Clock (max) + Reg co + Output
=
(t
gy0(max) +
t
gco +
t
gcp(max)
)
+
(t
gco
)
+
(t
orp +
t
ob
)
=
(
#50 + #40 + #52
)
+
(
#40
)
+
(
#45 + #47
)
21.5 ns = (5.0 + 2.5 + 5.0) + (2.5) + (3.5 + 3.0)
1. Calculations are based upon timing specifications for the ispLSI 1048-70.
Specifications ispLSI 1048
9
USE ispLSI 1048EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
Maximum GRP Delay vs GLB Loads
ispLSI 1048-70
ispLSI 1048-50
0126A-48-80-isp
ispLSI 1048-80
1
2
3
4 8 12 16
GLB Loads
GRP Delay (ns)
4
5
6
0
7
8
Power Consumption
Power consumption in the ispLSI 1048 device depends
on two primary factors: the speed at which the device is
operating, and the number of Product Terms used. Fig-
ure 3 shows the relationship between power and operat-
ing speed.
50
100
150
200
250
0 10203040506070
f
max (MHz)
I
CC (mA)
Notes: Configuration of Twelve 16-bit Counters
Typical Current at 5V, 25¡C
ispLSI 1048
80
0127A-48-80-isp
ICC can be estimated for the ispLSI 1048 using the following equation:
ICC = 73 + (# of PTs * 0.23) + (# of nets * Max. freq * 0.010) where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 2 GLB loads on
average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the
program in the device, the actual ICC should be verified.
Figure 3. Typical Device Power Consumption vs fmax
Specifications ispLSI 1048
10
USE ispLSI 1048EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
Pin Description
Input – Dedicated in-system programming enable input pin. This pin
is brought low to enable the programming mode. The MODE, SDI,
SDO and SCLK options become active.
Input – This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as an input
pin to load programming data into the device. SDI/IN 0 also is used as
one of the two control pins for the isp state machine.
Input – This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as a pin to
control the operation of the isp state machine.
Input/Output – This pin performs two functions. It is a dedicated input
pin when ispEN is logic high. When ispEN is logic low, it functions as
an output pin to read serial shift register data.
Input – This pin performs two functions. It is a dedicated input when
ispEN is logic high. When ispEN is logic low, it functions as a clock pin
for the Serial Shift Register.
Active Low (0) Reset pin which resets all of the GLB and I/O registers
in the device.
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
Ground (GND)
V
CC
GND 46, 76,106, 16
VCC 15, 45, 77, 107
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
I/O 0 - I/O 5 20, 21, 22, 23, 24, 25,
I/O 6 - I/O 11 26, 27, 28, 29, 30, 31,
I/O 12 - I/O 17 32, 33, 34, 35, 36, 37,
I/O 18 - I/O 23 38, 39, 40, 41, 42, 43,
I/O 24 - I/O 29 49, 50, 51, 52, 53, 54,
I/O 30 - I/O 35 55, 56, 57, 58, 59, 60,
I/O 36 - I/O 41 61, 62, 63, 64, 65, 66,
I/O 42 - I/O 47 67, 68, 69, 70, 71, 72,
I/O 48 - I/O 53 80, 81, 82, 83, 84, 85,
I/O 54 - I/O 59 86, 87, 88, 89, 90, 91,
I/O 60 - I/O 65 92, 93, 94, 95, 96, 97,
I/O 66 - I/O 71 98, 99,100,101,102,103,
I/O 72 - I/O 77 109,110,111,112,113,114,
I/O 78 - I/O 83 115,116,117,118,119,120,
I/O 84 - I/O 89 1, 2, 3, 4 5, 6,
I/O 90 - I/O 95 7, 8, 9, 10, 11, 12
IN 4 48,
IN 6 - IN 11 79,104,105, –108, 13 Dedicated input pins to the device. (IN 2 and IN 9 not available)
RESET 18
Y0 14
Y1 78
Y2 75
Y3 74
Table 2- 0002C-48-isp
DESCRIPTIONNAME PQFP PIN NUMBERS
ispEN 17
SDI/IN 0
1
19
MODE/IN 1
1
44
SDO/IN 3
1
47
SCLK/IN 5
1
73
1. Pins have dual function capability.
Specifications ispLSI 1048
11
USE ispLSI 1048EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
Pin Configuration
ispLSI 1048 120-Pin PQFP Pinout Diagram
I/O 84
I/O 85
I/O 86
I/O 87
I/O 88
I/O 89
I/O 90
I/O 91
I/O 92
I/O 93
I/O 94
I/O 95
IN 11
Y0
VCC
GND
1ispEN
RESET
1SDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
IN 6
Y1
VCC
GND
Y2
Y3
IN 5/SCLK1
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
I/O 83
I/O 82
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
IN 10
VCC
GND
IN 8
IN 7
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
1MODE/IN 1
VCC
GND
1SDO/IN 3
IN 4
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
72
71
70
69
68
67
66
65
64
62
61
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
63
73
ispLSI 1048
Top View
0124 -48-isp
1. Pins have dual function capability.
Specifications ispLSI 1048
12
USE ispLSI 1048EA FOR NEW
COMMERCIAL & INDUSTRIAL
DESIGNS
t
pd (ns)
f
max (MHz) Ordering Number Package
70 18 ispLSI 1048-70LQ 120-Pin PQFP
50 24 120-Pin PQFP
COMMERCIAL
t
pd (ns)
f
max (MHz) Ordering Number Package
INDUSTRIAL
50 24 ispLSI 1048-50LQI 120-Pin PQFP
Family
ispLSI
ispLSI
Family
ispLSI 1048-50LQ
Table 2- 0041A-48-isp
80 15 ispLSI 1048-80LQ 120-Pin PQFP
Device Number
Grade
Blank = Commercial
I = Industrial
1048 XX X X X
Speed
80 = 80 MHz fmax
70 = 70 MHz fmax
50 = 50 MHz fmax
Power
L = Low
Package
Q = PQFP
—
Device Family
0212-80B-isp1048
ispLSI
ispLSI 1048 Ordering Information
Part Number Description
