Integrated
Circuit
Systems, Inc.
General Description Features
ICS9248-61
0283C—07/10/06
Block Diagram
Frequency Timing Generator for Pentium II Systems
Pin Configuration
28 pin SSOP
Pentium is a trademark on Intel Corporation.
• Generates the following system clocks:
- 2 CPU(2.5V) up to 100MHz.
- 7 PCI(3.3V) @ 33.3MHz (Includes one free running).
- 2 REF clks Fixed (3.3V) 14.318MHz.
• - 1 48MHz, (3.3V) fixed.
• Skew characteristics:
- CPU – CPU<175ps
- PCI – PCI < 250ps
- PCI_E (early) – PCI = 2.1ns
- CPU(early) – PCI = 1.5ns – 4ns
• Supports Spread Spectrum modulation for CPU and PCI
clocks, 0.5% down spread
• Efficient Power management scheme through stop clocks
and power down modes.
• Uses external 14.318MHz crystal, no external load cap
required for CL=18pF crystal.
• 28 pin 209mil SSOP .
The ICS9248-61 is the Main clock solution for Notebook
designs using the Intel 440BX style chipset. Along with an
SDRAM buffer such as the ICS9179-03, it provides all
necessary clock signals for such a system.
Spread spectrum may be enabled by driving pin 26, SPREAD#
active (Low) at power-on. Spread spectrum typically reduces
system EMI by 8dB to 10dB. This simplifies EMI qualification
without resorting to board design iterations or costly shielding.
The ICS9248-61 employs a proprietary closed loop design,
which tightly controls the percentage of spreading over
process and temperature variations.
Power Groups
GNDR/C = REFCLK, CORE, Crystal
VDDCOR = Core
GNDLCPU, VDDCPU = CPU
GND48, VDD48 = 48MHz
VDDPCI, GNDPCI - PCICLK, PCICLK_F, PCICLK_E
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
2
ICS9248-61
0283C—07/10/06
Pin Descriptions
Pin number Pin name Type Description
2 X1 Input 14.318 MHz crystal input
3 X2 Output 14.318 MHz crystal output
4 PCICLK_F Output 3.3 V free running PCI clock output, will not be stopped by the PCI_STOP#
7 GNDPCI Power Ground for PCI clock outputs
8 VDDPCI Power 3.3 V power for the PCI clock outputs
12 PCICLK_E Output Early PCICLK output, offset from other PCICLKs, stopped by PCI-STOP#
13 VDD48 Power 3.3 V power for 48 MHz clocks
SEL 100_66# Input
on power-on control for the frequency of clocks at the CPU & PCICLK output pins. If
logic "0" is used the 66.6 MHz frequency is selected. If Logic "1" is used, the 100
MHz frequency is selected. The PCI clock is multiplexed to run at 33.3 MHz for both
selects
48MHz Output Fixed 48MHz clock
15 GND48 Power Ground for 48 MHz clocks
16 DIV4# Input Active low input, enables the CPUCLK and the PCICLK to run at 1/4 of the regular
frequecies
17 PD# Input
Asynchronous active low input pin used to power down the device into a low power
state. The internal clocks are disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 3ms.
18 CPU_STOP# Input
Asynchronous active low input pin used to stop the CPUCLK in active low state, all
other clocks will continue to run. The CPUCLK will have a "Turnon " latency of at
least 3 CPU clocks.
19 VDDCOR Input 3.3 V power for the core
20 PCI-STOP# Input Synchronous active low input used to stop the PCICLK in active low state. It will not
effect PCICLK_F or any other outputs.
21 GNDR/C Input Ground for REFCLK, Crystal & Core
22 GNDLCPU Power Ground for the CPU and Host clock outputs
25 VDDLCPU Power 2.5 V power for the CPU and Host clock outputs
26 SPREAD# Output power-on spread spectrum enable option. Active low = spread spectrum clocking
enable. Active high = spread spectrum clocking disable.
28 VDDR Input 3.3 V power for the REFCLK and crystal clock outputs
1,27 REF(0:1) Output 3.3V, 14.318 MHz reference clock output.
23,24 CPUCLK (0:1) 0utput 2.5 V CPU and Host clock outputs
5,6,9,10, 11 PCICLK (1:4) Output 3.3 V PCI clock outputs, generating timing requirements
14
3
ICS9248-61
0283C—07/10/06
Frequency Table
Power Management
ICS9248-61 Power Management Requirements
Clock Enable Configuration
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power
up and power down operations using the PD# pin will not cause clocks of a short or longer pulse than that of the running clock.
The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry .
Board routing and signal loading may have a large impact on the initial clock distortion also.
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only .
The REF will be stopped independant of these.
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4
ICS9248-61
0283C—07/10/06
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-61. It is used to turn off the PCICLK (0:4) clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-61 internally . The minimum that the PCICLK (0:4) clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK (0:4) clocks. PCICLK (0:4) clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK (0:4) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the ICS9248-61. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100
CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a low
state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs
and CPUCLK off latency is less than 4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside
the ICS9248-61.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
5
ICS9248-61
0283C—07/10/06
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal is synchronized internally by the ICS9248-61 prior to its control action of
powering down the clock synthesizer . Internal clocks will not be running after the device is put in power down state. When PD#
is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the crystal oscillator. The power on
latency is guaranteed to be less than 3 ms. The power down latency is less than three CPUCLK cycles. PCI_STOP# and
CPU_STOP# are don’t care signals during the power down operations.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9248.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
6
ICS9248-61
0283C—07/10/06
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability .
Elect rical Characteristics - Input/ Supply/Comm o n O utput Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Voltage VIH 2V
DD+0.3 V
Input Low Voltage VIL VSS-0.3 0.8 V
Input High Current IIH VI
N
= VDD 0.1 5 µA
Input Low Current IIL1 VI
N
= 0 V; Inputs with no pull-up resistors -5 2.0 µA
Input Low Current IIL2 VI
N
= 0 V; Inputs with pull-up resistors -200 -100 µA
Operating IDD3.3OP66 C
L
= 0 pF; Select @ 66MHz 60 180 mA
Supply Current IDD3.3OP100 C
L
= 0 pF; Select @ 100MHz 66 180 mA
Power Down Supply
Current IDD3.3PD
CL = 0 pF;
With input address to Vdd or GND 70 600
µ
A
Input frequency FiVDD = 3.3 V; 11 14.318 16 MHz
CI
N
Logic Inputs 5 pF
CINX X1 & X2 pins 27 36 45 pF
Transition Time1Ttrans To 1st crossing of target Freq. 3 ms
Clk Stabilization1TSTAB From VDD = 3.3 V to 1% target Freq. 3 ms
Skew1TCPU-PCI1 VT = 1.5 V; 1.5 2.4 4 ns
1Guaranteed by design, not 100% tested in production.
Input Capacitance1
Electrical Charact erist ics - Input /Supply/Comm on O utput Paramet ers
TA = 0 - 70C; Supply Volta ge VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless othe rwise state d)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Operating IDD2.5OP66 CL = 0 pF; Select @ 66.8 MHz 16 72 mA
Suppl y Current IDD2.5OP100 CL = 0 pF; Select @ 100 MHz 23 100 mA
Skew1tCPU-PCI2 VT = 1.5 V; VTL = 1.25 V 1.5 3 4 ns
1Guarant e e d by de sign, not 100% t e st e d in production.
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ICS9248-61
0283C—07/10/06
Elect rical C haracteristic s - CPUCLK
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Voltage VOH2 B IOH = -12.0 mA 2 2.3 V
Output Low Voltage VOL2 B IOL = 12 mA 0.2 0.4 V
Output High Current IOH2 B VOH = 1.7 V -41 -19 mA
Output Low Current IOL2 B VOL = 0.7 V 19 37 mA
Rise Time tr2B1VOL = 0.4 V, VOH = 2.0 V 1.25 1.6 ns
Fall Time tf2B1VOH = 2.0 V, VOL = 0.4 V 1 1.6 ns
Duty Cycle dt2B1VT = 1.25 V 454855%
Skew tsk2B1VT = 1.25 V 30 175 ps
Jitter, Cycle-to-cycle tjcyc-cyc2B1VT = 1.25 V 150 250 ps
Jitter, One Sigma tj1s2B1VT = 1.25 V 40 150 ps
Jitter, Absolute tjabs2B1VT = 1.25 V -250 140 +250 ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Volta ge VOH1 IOH = -1 1 mA 2.4 3 .1 V
Output L ow Voltage VOL1 IOL = 9.4 mA 0.1 0.4 V
Output High Current IOH1 VOH = 2.0 V -62 -22 mA
Output Low Current IOL1 VOL = 0.8 V 16 57 mA
Rise Time1tr1 VOL = 0.4 V, VOH = 2 .4 V 1 .5 2 ns
Fall Ti me1tf1 VOH = 2.4 V, VOL = 0 .4 V 1 .1 2 ns
Duty Cycle1dt1 VT = 1.5 V 45 50 55 %
Skew1tsk1 VT = 1.5 V 140 500 ps
Jitter, Cycle-to-cycle tjcyc-cyc1 VT = 1.25 V 250 500 ps
Jitter , O ne Si gma1tj1s1 VT = 1.5 V 17 150 ps
J itter, Absolute1tjabs1 VT = 1.5 V -250 70 250 ps
1Gua ranteed by de sign, not 100% t e sted in production.
8
ICS9248-61
0283C—07/10/06
Elect rical C haracteri sti c s - REF/48MHz
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 2 0 pF (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Volta ge VOH5 IOH = -1 2 mA 2.6 3.1 V
Output L ow Voltage VOL5 IOL = 9 mA 0.17 0.4 V
Output High Current IOH5 VOH = 2.0 V -44 -22 mA
Output Low Current IOL5 VOL = 0.8 V 16 42 mA
Rise Time1tr5 VOL = 0.4 V, VOH = 2 .4 V 1 .4 4 ns
Fall Ti me1tf5 VOH = 2.4 V, VOL = 0 .4 V 1 .1 4 ns
Duty Cycle1dt5 VT = 1.5 V 45 53 55 %
Jitter , O ne Si gma1tj1s5 VT = 1.5 V 1 3 %
J itter, Absolute1tjabs5 VT = 1.5 V 35%
1Gua ranteed by design, not 100% t e sted in production.
9
ICS9248-61
0283C—07/10/06
LOBMYS NOMMOC SNOISNEMID SNOITAIRAV D
.NIM.MON.XAMN .NIM.MON.XAM
A860.0370.0870.041932.0442.0942.0
1A200.0500.0800.061932.0442.0942.0
2A660.0860.0070.002872.0482.0982.0
b0
10.0210.0510.042813.0323.0823.0
c400.0600.0800.082793.0204.0704.0
DsnoitairaVeeS03793.0204.0704.0
E502.0902.0212.0
eCSB6520.0
H10
3.0703.0113.0
L520.0030.0730.0
NsnoitairaVeeS
∝
°0°4°8
Dimensions in inches
Ordering Information
ICS9248F-61LF
Lead Free, RoHS Compliant
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y F - PPP LF
SSOP Package
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
