HUF75329D3ST - Fairchild Semiconductor

HUF75329D3, HUF75329D3S

20A, 55 V, 0.026 Ohm, N-Channel Ultr aFET

Power MOSFETs

These N-Channel power MOSFETs

are manufactured using the

inno vat ive UltraFET ® process . This

advanced process technology

achieves the lowest possible on-resistance per silicon area,

resulting in outstandi ng performance . This device is capa ble

of withstanding high ene r gy in the ava lan che mode an d the

diode exhibits very low reverse recovery time and stored

charge. It was designed for use in applications where power

efficiency is important, such as switching regulators,

switching converters, motor drivers, relay drivers, low-

v oltage bus switches, and power manag em ent in portable

and battery-operated products.

Formerly developmental type TA75329.

Features

• 20A, 55V

• Simulation Models

- Tempera ture C ompens ated P SPICE® and SABER™

Models

- SPICE and SABER Thermal Impedance Models

A vailable on the WEB at: www.f airchildsemi.com

• Peak Current vs Pulse Wi dth Curve

• UIS Rating Curve

• Related Literature

- TB334, “G uid eli ne s for Soldering Surface Mount

Components to PC Boards”

Symbol

Packaging

Product reliability information can be found at http://www.fairchildsemi.com/products/disc rete/reliability/index.html

For severe environments, see our Autom otive HUFA series.

All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 an d QS9000 quality systems c e rtification.

Ordering Information

PART NUMBER PACKAGE BRAND

HUF75329D3 TO-251AA 75329D

HUF75329D3S TO-252AA 75329D

NOTE: When ordering, use the entire part number . Add the suffix T to

obtain the TO-252AA variant in tape and reel, e.g., HUF75329D3ST.

JEDEC TO-251AA JEDEC TO-252AA

DRAIN

(FLANGE) DRAIN

SOURCE

GATE DRAIN

(FLANGE)

GATE

SOURCE

Data Sheet December 2001

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . VDSS 55 V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . VDGR 55 V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20 V

Drain Current

Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 20

Figure 4 A

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Figure 6

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

0.86 W

W/oC

Operating and Storage Temperature . . . . . . . . . . . . . . . . . .TJ, TSTG -55 to 175 oC

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . TL

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . Tpkg 300

260

CAUTION: Str esses above those l isted in “A bsolute Maximu m Rating s” may cause per manent d amage to t he device. This is a str ess onl y rating and operation o f the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. TJ = 25oC to 150oC.

Electrical Specifications TC = 25oC, Unles s Otherwise Spec ified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

OFF STATE SPECIFICATIONS

Drain to Source B reakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 11) 55 - - V

Zero Gate Vo ltage Drain C urrent IDSS VDS = 50V, VGS = 0V - - 1 µA

VDS = 45V, VGS = 0V, TC = 150oC--250µA

Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA

ON STATE SPECIFICATIONS

Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 10) 2 - 4 V

Drain to Source On Resist ance rDS(ON) ID = 20A, VGS = 10V (Figure 9) - 0.022 0.026 Ω

THERMAL SPECIFICATIONS

Thermal Resistance Junction to Case RθJC (Figure 3) - - 1.17 oC/W

Thermal Resistance Junction to Ambient RθJA TO-251, TO-252 - - 100 oC/W

SWITCHING SPECIFICATIONS (VGS = 10V)

Turn-On Time tON VDD = 30V, ID ≅ 20A,

RL = 1.5Ω, VGS = 10V,

RGS = 9.1Ω

- - 60 ns

Turn-On De lay Time td(ON) -7-ns

Rise Time tr-30- ns

Turn-Off De lay Time td(OFF) -10- ns

Fall Time tf-33- ns

Turn-Off T ime tOFF - - 65 ns

GATE CHARGE SPECIFICATIONS

Total Gate Charge Qg(TOT) VGS = 0V to 20V VDD = 30V,

ID ≅ 20A,

RL = 1.5Ω

Ig(REF) = 1.0mA

(Figure 13)

-5065nC

Gate Charge at 10V Qg(10) VGS = 0V to 10V - 32 40 nC

Threshold Gate Charge Qg(TH) VGS = 0 V to 2V - 2.0 2.5 nC

Gate to Source Gate C harge Qgs -5-nC

Reverse Transfer Capacitance Qgd -13-nC

HUF75329D3, HUF75329D3S

CAPACITANCE SPECIFICATIONS

Input Capacitance CISS VDS = 25V, VGS = 0V,

f = 1MHz

(Figure 12)

- 1060 - pF

Output Capacitance COSS - 405 - pF

Reverse Transfer Capacitance CRSS -95-pF

Electrical Specifications TC = 25oC, Unles s Otherwise Spec ified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNI TS

Source to D rain Diode Volt age VSD ISD = 20A - - 1.25 V

Reverse Recovery Time trr ISD = 20A, dISD/dt = 100A/µs--68ns

Reverse Recovered Charge QRR ISD = 20A, dISD/dt = 100A/µs - - 120 nC

Typical Performance Curves

FIGURE 1. NORMALIZED PO WER DISSIPA TI ON vs CASE

TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

TC, CASE TEMPERATURE (oC)

POWER DISSIPATION MULTIPLIER

00 25 50 75 100 150

0.2

0.4

0.6

0.8

1.0

1.2

125 17

ID, DRAIN CURRENT (A)

TC, CASE TEMPERATURE (oC)

50 75 100 125 150 17

025

t, RECTANGULAR PULSE DURATION (s)

SINGLE PULSE

NOTES:

DUTY FACTOR: D = t1/t2

PEAK TJ = PDM x ZθJC x RθJC + TC

PDM

t1t2

DUTY CYCLE - DESCENDING ORDER

0.5

0.2

0.1

0.05

0.01

0.02

10-4 10-3 10-2 10-1 100101

10-5

0.1

0.01

ZθJC, NORMALIZED

THERMAL IMPEDANCE

HUF75329D3, HUF75329D3S

FIGURE 4. PEAK CURRENT CAPABILITY

FIGURE 5. FORWARD BIAS SAFE OPERATING AREA NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY

FIGURE 7. SATURATION CHARACTERISTICS FIGURE 8. TRANSFER CHARA C TERISTICS

Typical Performance Curves (Continued)

101

100

10-1

10-2

10-3

10-4

10-5

100

1000 TC = 25oC

I = I25 175 - TC

150

FOR TEMPERATURES

ABOVE 25oC DERATE PEAK

CURRENT AS FOLLOWS:

VGS = 1 0V

IDM, PEAK CURRENT (A)

t, PULSE WIDTH (s)

TRANSCONDUCTANCE

MAY LIMIT CURRENT

IN THIS REGION

100

500

10 100

1120

VDS, DRAIN TO SOURCE VO LTAGE (V)

ID, DRAIN CURRENT (A)

TJ = MAX RATED

TC = 25oC

100µs

10ms

1ms

VDSS(MAX) = 55V

LIMITED BY rDS(ON)

AREA MAY BE

OPERATION IN THIS

110

100

0.01

200

IAS, AVALANCHE CURRENT (A)

tAV, TIME IN AVALANCHE (ms)

tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)

If R = 0

If R ≠ 0

tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]

STAR TING TJ = 25oC

STAR TING TJ = 150oC

0.1 10

023

, DRAIN CURRENT (A)

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 10V

VGS = 20V

PULSE DURATION = 80

TC = 25oC

VGS = 5V

VGS = 8 V

100

VGS = 6V

VGS = 7 V

DUTY CYCLE = 0.5% MAX

0 3.0 4.5 6.0 7.

1.5

, DRAIN CURRENT (A)

VGS, GATE TO SOURCE VOLTAGE (V)

25oCVDD = 15V

100

-55oC

175oC

PULSE DURATION = 80

DUTY CYCLE = 0.5% M AX

HUF75329D3, HUF75329D3S

FIGURE 9. NORMALIZED DRAIN T O SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE FIGURE 10. NORMALIZED GATE THRESHOLD V OLT AGE vs

JUNCTION TEMPERATURE

FIGURE 11. NORMALIZED DRAIN T O SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.

FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT

Typical Performance Curves (Continued)

1.0

1.5

2.0

2.5

-40 0 40 80 120 160 200

0.5-80

NORMALIZED DRAIN TO SOURCE

TJ, JUNCTION TEMPERATURE (oC)

ON RESISTANCE

PULSE DURATION = 80µs

VGS = 10V, ID = 20A

DUTY CYCLE = 0.5% MAX

0.8

1.0

1.2

-40 0 40 80 120 160 200

0.6

-80

NORMALIZED GATE

TJ, JUNCTION TEMPERATURE (oC)

THRESHOLD VO LTAGE

VGS = VDS, ID = 250µA

0.4

0.9

1.0

1.1

1.2

-40 0 40 80 120 160 200-80

TJ, JUNCTION TEMPERATURE (oC)

NORMALIZED DRAIN TO SOURCE

ID = 250µA

BREAKDOWN VOLTAGE

0.8

1200

600

00 1020304050

C, CAPACITANCE (pF)

900

VDS, DRAIN TO SOURCE VOLTAG E (V)

300

CISS

COSS

CRSS

1500 VGS = 0V, f = 1MHz

CISS = CGS + CGD

CRSS = CGD

COSS ≈ CDS + CGD

VGS, GATE TO SOURCE VOLTAGE (V)

VDD = 30V

15 20 3

Qg, GATE CHARGE (nC)

510

ID = 20A

ID = 12.5A

ID = 5A

WAVEFORMS IN

DESCENDING ORDER:

25 30

HUF75329D3, HUF75329D3S

Test Circuits and Wavef orms

FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS

FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORM

FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS

VGS

0.01Ω

IAS

VDS

VDD

DUT

VARY tP TO OBTAIN

REQUIRED PE AK IAS

VDD

VDS

BVDSS

IAS

tAV

VGS +

VDS

VDD

DUT

IG(REF)

VDD

Qg(TH)

VGS = 2V

Qg(10)

VGS = 10V

Qg(TOT)

VGS = 20

VDS

VGS

g(REF)

Qgs Qgd

VGS

RGS DUT

-VDD

VDS

VGS

tON

td(ON)

90%

10%

VDS 90%

10%

td(OFF)

tOFF

90%

50%

10% PULSE WIDTH

VGS

HUF75329D3, HUF75329D3S

PSPICE Ele ctrical Model

.SUBCKT HUF75329D 2 1 3 ; rev 6/19/97

CA 12 8 1.72e-9

CB 15 14 1.52e-9

CIN 6 8 9.61e-10

DBODY 7 5 DBODYMOD

DBRE AK 5 11 DB REAK MOD

DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 58.13

EDS 14 8 5 8 1

EGS 13 8 6 8 1

ESG 6 10 6 8 1

EVTH R ES 6 21 19 8 1

EVTEMP 20 6 18 22 1

IT 8 17 1

LDRA IN 2 5 1e- 9

LGATE 1 9 2.86e-9

LSOURCE 3 7 2.69e-9

MMED 16 6 8 8 MMEDMOD

MSTRO 16 6 8 8 MSTROMOD

MWEAK 16 21 8 8 MWEAKMOD

RBREAK 17 18 RBREAKMOD 1

RDRAIN 50 16 RDRAINMOD 1e-3

RGATE 9 20 1.52

RLDRAIN 2 5 10

RLGATE 1 9 26.9

RLSOURCE 3 7 28.6

RSLC1 5 51 RSLCMOD 1e-6

RSLC2 5 50 1e3

RSOURCE 8 7 RSOURCEMOD 13.85e-3

RVTHRES 22 8 RVTHRESMOD 1

RVTE M P 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1AMOD

S1B 13 12 13 8 S1BMOD

S2A 6 15 14 13 S2AMOD

S2B 13 15 14 13 S 2 BMOD

VBAT 22 1 9 DC 1

ESL C 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*135),3.5))}

.MODEL DBOD YMOD D (IS = 7.50e-13 RS = 5.05e-3 TRS1 = 2.21e-3 TRS2 = 1.02e-6 CJO = 1.51e-9 TT = 4.05e-8 M = 0 .5)

.MODEL DBREAKMOD D (RS = 2.14e- 1TRS1 = 9.62e- 4TRS2 = 1.23e-6)

.MODEL DPLC APMOD D (CJO = 13.5e-1 0IS = 1e-3 0N = 10 M = 0 .85)

.MODEL MMEDMOD NMOS (VTO = 3.25 KP = 2.50 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.52)

.MODEL MSTROMOD NMOS (VTO = 3.80 KP = 70.0 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)

.MODEL MWEA KM OD NMOS (VTO = 2 . 91 K P = 0.06 IS = 1e-30 N = 10 TO X = 1 L = 1u W = 1u RG = 15.2 RS = 0 . 1 )

.MODEL RBREAK MOD RES (TC1 = 1.05e - 3TC2 = 1.94e-7)

.MODEL RDRAINMOD RES (TC1 = 8.04e-2 TC2 = 1.37e-4)

.MODEL RSLCMOD RES (TC1 = 4.83e-3 TC2 = 1.16e-6)

.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)

.MODEL RVTHRESMOD RE S (TC = -3.43e-3 TC2 = -1.63e-5)

.MODEL RVTEMPMO D RE S (TC1 = -1.35e- 3TC2 = 1.16e-6)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -7.90 VOFF= -4.90)

.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.90 VOFF= -7.90)

.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.50 VOFF= 2.50)

.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.50 VOFF= -0.50)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPI CE Sub-Circuit for the Power MOSFET Featuring Gl obal

Temperature Options; IEEE Power Electronics Special ist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

RBREAK

RVTEMP

VBAT

RVTHRES

17 18

S1A

S1B

S2A

S2B

CA CB

EGS EDS

814

MWEAK

EBREAK DBODY

RSOURCE

SOURCE

LSOURCE

RLSOURCE

CIN

RDRAIN

EVTHRES 16

MMED

MSTRO

DRAIN

LDRAIN

RLDRAIN

DBREAK

DPLCAP

ESLC

RSLC1

RSLC2

GATE RGATE EVTEMP

ESG

LGATE

RLGATE 20

HUF75329D3, HUF75329D3S

SABER Electrical Model

REV June 1997

template huf75329d n2, n1, n3

electrical n2, n1, n3

{

var i iscl

d..model dbodymod = (is = 7.50e-13, cjo = 1.51e-9, tt = 4.05 e-8, m = 0.5)

d..model dbreakmod = ()

d..model dplcapmod = (cjo = 13.5e-10, is = 1e-30, n = 10, m = 0.85)

m..model mmedmod = (type=_n, vto = 3.25, kp = 2.50, is = 1e-30, tox = 1)

m..model mstrongmod = (type= _n, vto = 3.80, kp = 70, is = 1e-30, tox = 1)

m..model mweakmod = (type=_n, vto = 2.91, kp = 0.06, is = 1e-30, tox = 1)

sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -7.90, voff = -4.90)

sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -4.90, voff = -7.90)

sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.50, voff = 2.50)

sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 2.50, voff = -0.50)

c.ca n12 n8 = 1.72e-9

c.cb n15 n14 = 1.52e-9

c.cin n6 n8 = 9.61e-10

d.dbody n7 n71 = model=dbodymod

d.dbreak n72 n11 = model=dbreakmod

d.dplcap n10 n5 = model=dpl capmod

i.it n8 n17 = 1

l.ldrain n2 n5 = 1e-9

l.lgate n1 n9 = 2.86e-9

l.lsourc e n3 n7 = 2.69e-9

k.k1 i(l.lgate) i(l.lsource) = l(l.lgat e), l(l.lsource), 0.0085

m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u

m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u

m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u

res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = 1.94e-7

res.rdbody n71 n5 = 5.05e-3, tc1 = 2.21e-3, tc2 = 1.02e-6

res.rdbreak n72 n5 = 2.14e-1, tc1 = 9.62e-4, tc2 = 1.23e-6

res.rdrain n50 n16 = 1e-3, tc1 = 8.04e-2, tc2 = 1.37e-4

res.rgate n9 n20 = 1.52

res.r ldrain n2 n5 = 10

res.rlgate n1 n9 = 26.9

res.rlsource n3 n7 = 28.6

res.rs lc1 n5 n51 = 1e-6, tc1 = 4.83e-3, tc2 = 1.16e-6

res.r slc2 n5 n50 = 1e3

res.rs ource n8 n7 = 13.85e-3, tc1 = 0, tc2 = 0

res.rv temp n18 n19 = 1, tc1 = -1.35e-3, tc2 = 1.16e-6

res.rvthres n22 n8 = 1, tc1 = -3.43e-3, tc2 = -1.63e-5

spe.ebreak n11 n7 n17 n18 = 58.13

spe.e ds n14 n8 n5 n8 = 1

spe.e gs n13 n8 n6 n8 = 1

spe.esg n6 n10 n6 n8 = 1

spe.evtemp n20 n6 n18 n22 = 1

spe.evthres n6 n21 n19 n8 = 1

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod

sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod

sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod

sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc = 1

equations {

i (n51->n50) + = iscl

iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs (v(n5,n51)*1e6/135))** 3.5))

}

RBREAK

RVTEMP

VBAT

RVTHRES

17 18

S1A

S1B

S2A

S2B

CA CB

EGS EDS

814

MWEAK

EBREAK DBODY

RSOURCE

SOURC

LSOURCE

RLSOURCE

CIN

RDRAIN

EVTHRES 16

MMED

MSTRO

DRAIN

LDRAIN

RLDRAIN

DBREAK

DPLCAP

ISCL

RSLC1

RSLC2

GATE RGATE EVTEMP

ESG

LGATE

RLGATE 20

RDBODY

RDBREAK

HUF75329D3, HUF75329D3S

SPICE Thermal Model

REV 23 February 1999

HUF75329D

CTHERM1 th 6 2.80e-3

CTHERM2 6 5 1 .00e-2

CTHERM3 5 4 6 .80e-3

CTHERM4 4 3 7 .00e-3

CTHERM5 3 2 1 .60e-2

CTHERM6 2 tl 15.55

RTHERM1 th 6 7.94e-3

RTHERM2 6 5 1 .98e-2

RTHERM3 5 4 5 .57e-2

RTHERM4 4 3 3 .13e-1

RTHERM5 3 2 4 .71e-1

RTHERM6 2 tl 6.26e-2

SABER Thermal Model

SABER thermal model HUF75329D

template thermal_model th tl

thermal_c th, tl

{

ctherm.ctherm 1 t h 6 = 2.80e-3

ctherm.ctherm 2 6 5 = 1.00e-2

ctherm.ctherm 3 5 4 = 6.80e-3

ctherm.ctherm 4 4 3 = 7.00e-3

ctherm.ctherm 5 3 2 = 1.60e-2

ctherm.ctherm6 2 tl = 15.55

rtherm.rtherm1 th 6 = 7.94e-3

rtherm.rtherm2 6 5 = 1.98e-2

rtherm.rtherm3 5 4 = 5.57e-2

rtherm.rtherm4 4 3 = 3.13e-1

rtherm.rtherm5 3 2 = 4.71e-1

rtherm.rtherm6 2 t l = 6.26e- 2

}

RTHERM4

RTHERM6

RTHERM5

RTHERM3

RTHERM2

RTHERM1

CTHERM4

CTHERM6

CTHERM5

CTHERM3

CTHERM2

CTHERM1

th JUNCTION

CASE

HUF75329D3, HUF75329D3S

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER

NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD

DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT

OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT

RIGHTS, NOR THE RIGHTS OF OTHERS.

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is

not intended to be an exhaustive list of all such trademarks.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant into

the body, or (b) support or sustain life, or (c) whose

failure to perform when properly used in accordance

with instructions for use provided in the labeling, can be

reasonably expected to result in significant injury to the

user.

2. A critical component is any component of a life

support device or system whose failure to perform can

be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or

effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Obsolete

This datasheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

This datasheet contains preliminary data, and

supplementary data will be published at a later date.

Fairchild Semiconductor reserves the right to make

changes at any time without notice in order to improve

design.

This datasheet contains final specifications. Fairchild

Semiconductor reserves the right to make changes at

any time without notice in order to improve design.

This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.

The datasheet is printed for reference information only.

Formative or

In Design

First Production

Full Production

Not In Production

OPTOLOGIC™

OPTOPLANAR™

PACMAN™

POP™

Power247™

PowerTrench

QFET™

QS™

QT Optoelectronics™

Quiet Series™

SILENT SWITCHER

FAST

FASTr™

FRFET™

GlobalOptoisolator™

GTO™

HiSeC™

ISOPLANAR™

LittleFET™

MicroFET™

MicroPak™

MICROWIRE™

Rev. H4



ACEx™

Bottomless™

CoolFET™

CROSSVOLT™

DenseTrench™

DOME™

EcoSPARK™

E2CMOSTM

EnSignaTM

FACT™

FACT Quiet Series™

SMART START™

STAR*POWER™

Stealth™

SuperSOT™-3

SuperSOT™-6

SuperSOT™-8

SyncFET™

TinyLogic™

TruTranslation™

UHC™

UltraFET



STAR*POWER is used under license

VCX™