ANALOG | Le?M0s DEVICES 12-Bit Sampling ADC AD7870 1.1 Scope. This specification covers the detail requirement for a monolithic CMOS 12-bit sampling analog-to-digital converter. It features 100 ksps throughput, on board buried Zener reference and specified dynamic pa- rameters. 1.2 Part Number. The complete part number per Table 1 of this specification is as follows: Device Part Number -1 AD7870S(X\/883B -2 AD7870T(X)/883B 1.2.3 Case Outline. See Appendix 1 of General Specification ADI-M-1000: package outline: (X) Package Description Q Q24 24-Pin Cerdip E E-28A 28-Contact LCC 1.3 Absolute Maximum Ratings. (T, = +25C unless otherwise noted) Positive Supply Voltage (Vpp) to AGND ..... cee eee eee -0.3 V to +7.0 V Negative Supply Voltage (Vg,) to AGND ......... 0... 0c ee eee eee eee +0.3 V to -7.0V AGND to DGND ... 0c ene tee eee nee eees -0.3 V to Vpp +0.3 V Analog Input Range (Vix) to AGND 0... ee eee eee -15.0V to +15.0V Voltage Reference Output (REF OUT) to AGND ... 0... 0.2 ce eee 0 V to Vpp Digital Input Voltage to DGND ...........0.. 02. eee eee tees -0.3 V to Vpp +0.3 V Digital Output Voltage to DGND 0.0.0... eee eee ees 0.3 V to Vpp +0.3 V Thermal Resistance, Junction-to-Case (Ojo)... cece eee eee See MIL-M-38510, Appendix C Thermal Resistance, Junction-to-Ambient (Oj,) ... 6 ce eee ce teen ees 120C/W Maximum Power Dissipation (Pp) to +75C 2... eee cette eee 450 mW Lead Temperature (Soldering 10 sec)... 2... cece ee teeter eee eaes +300C Storage Temperature Range (Tsyg) .. 6. eee tenes -65C to +150C 1.4 Recommended Operating Conditions. Positive Supply Voltage Range (Vpp)....----- 2. cece eee eee eee +4.75 V de to +5.25 V de Negative Supply Voltage Range (Vg)... eee ee eee ee 4.75 V de to 5.25 V dc Analog Input Range ....... 0.0.0. ec eee ee cee ene eee eee eee -3.0V to +3.0V Ambient Operating Temperature Range .......... 0000 cece ets ee ee teaees ~55C to +125C 1.5 Thermal Characteristics. Thermal Resistance @;, = 35C/W for Q-24 and E-28A 8;4 = 120C/AW for Q-24 and E-28A REV. B ANALOG-TO-DIGITAL CONVERTERS 6-153 ANALOG-TO-DIGITAL CONVERTERS a~ AD7870SPECIFICATIONS Table 1. | Sub Test Condition 7/Comments Limit Group 55C <= Ty = +125C Test Symbol Device | Min | Max | 1 unless otherwise noted Units Signal-to-Noise* Ratio SNR All 69 4, 5,6 Vyy = 10 KHz Sine Wave dB fsampce = 100 kHz Total Harmonic Distortion THD Alt -7 4, 5,6 Vpp = +4.75 V, Vsg = 5.25 V dB Peak Harmonic PH All 78 4, 5,6 dB Intermodulation Distortion IMD? All -78 4,5, 6 fa = 9 kHz; fb = 9.5 kHz; dB (2nd Order Terms) fgsampte = 50 kHz Intermodulation Distortion IMD? Vopp = +4.75 V, Vss = -5.25V (3rd Order Terms) Track/Hold Acquisition Time* lace All 2 4, 5, 6 Vop = +4.75 V, Vsg = 5.25 V ps Integral Linearity Error LE -2 +1 1, 2, 3 Vopp = +4.75 V, Vss = 5.25 V LSB Differential Linearity Error DLE -2 +1 1, 2,3 Vpp = +4.75 V, Vss = 5.25 V LSB Bipolar Zero Error BZE All +5 1, 2, 3 Vpp = +4.75 V, Vsg = 5.25 V LSB Positive Full-Scale Error? PFSE All +5 1, 2,3 Vpp = +4.75 V, Vss = 5.25 V LSB Negative Full-Scale Error NFSE All +5 1, 2,3 Vpp = +4.75 V, Vss = 5.25 V LSB Minimum Resolution for Which No Missing Codes Are Guaranteed NMC All 12 1, 2,3 Vpp = +4.75 V, Vss = 5.25 V Bits Analog Input Voltage Vin All +3 1, 2,3 Vpp = +4.75 V, Vss = 5.25 V v Analog Input Current lin All +500 | 1, 2,3 Vpp = +5.25 V, Vsg = 5.25 V pA Voltage Reference Output VReF All 2.99 | 3.01 1 Vpp = +5 V; Vss = -5 V v Voltage Reference Output dREF/dT | -1 +60 2,3 Vpp = +5 V; Vss = -5 V ppm/C T ffici emperature Coefficient 3 35 Reference Load Sensitivity AREF All +1 1, 2, 3 Vpp = +5 V3 Vss = SV mV Reference Load Not Changed During Conversion. Reference Load Current Change (0-500 1A) Digital Input High Voltage Vins All 2.4 7,8 Vpp = +4.75 V, Vss = 5.25 V Vv Digital Input Low Voltage Vin All 0.8 7,8 Vpp = +4.75 V, Vss = 75.25 V v Digital Input Current In All +10 1, 2,3 Vpp = +5.25 V, Vsg = 5.25 V pa Digital Input Capacitance* Cw All 10 4 Vpp = +5 V; Vsgs = -5 V pF Digital Output High Voltage Von All 4.0 1, 2, 3 Isource = 40 HA Vv Vpp = +4.75 V, Vss = 5.0 V Digital Output Low Voltage VoL All 0.4 1, 2,3 Iginx = 1.6 mA Vv Vpp = +4.75 V, Vss = 5.0 V Floating State Leakage Current Ike All +10 1, 2,3 DB11-DB0, pa Vpp = +5.25 V, Vss = -5.25 V Floating State Output Capacitance? | Copr All 15 4 Vpp = +5 V; Vss = -5 V pF Conversion Time tconv All 8.0 9,10, 11 | fore = +2.5 MHz ps (External Clock) Vpp = +5 V, Vsg = -5S V Conversion Time tconv All 7.0 9.0 9,10, 11 | Vpp = +5 V, Vss = -5 V ps (Internal Clock) 6-154 ANALOG-TO-DIGITAL CONVERTERS REV. BAD7870 Sub Test Condition! ?/Comments Limit Group 58C = Ty, = +125C Test Symbol Device | Min | Max | 1 unless otherwise noted Units Positive Supply Current from Vpp Ipp All 13 Vop = +5.25 V, Vgs = 5.25 V mA Negative Supply Current from Vss5 Isg All 6 1, 2,3 Vpp = +5.25 V, Vsg = 5.25 V mA CONVST Pulse Width t4 All 50 9, 10, 11 ns CS to RD Setup t* All 0 9, 10, 11 | Mode 1 ns RD Pulse Width ty All 75 9, 10, 11 ns CS to RD Hold tt All 0 9,10, 11 | Mode 1 ns RD to INT Delay ts? All 70 9, 10, 11 ns Data Access Time After RD tg All 70 9, 10, 11 | Note 8 ns Bus Relinquish Time After RD ty All 5 50 9, 10,11 | Note 9 ns HBEN to RD Setup t,' All 0 9, 10, 11 ns HBEN to RD Hold t,* All 0 9, 10, 11 ns SSTRB to SCLK Falling Edge Setup | t,, All 100 9, 10, 11 ns SCLK Cycle ty All 370 9, 10,11 | Note 10 ns SCLK to Valid Data Delay tit All 150 9,10, 11 | C, = 35 pF ns SCLK Rising Edge to SSTRB 3" All 20 100 | 9, 10, 11 ns Bus Relinquish Time After SCLK tia? All 10 100 9, 10, 11 ns CS to RD Setup t54 All 60 9,10, 11 | Mode 2 ns CS to BUSY Propagation Delay tis! All 120 9, 10, 11 ns Data Setup Time Prior to BUSY tu, All 200 9, 10, 1 ns CS to RD Hold tha All 0 9,10, 11 | Mode 2 ns HBEN to CS Setup tis" All 0 9, 10, 11 ns HBEN to CS Hold tao" All 0 9, 10, 11 ns NOTES 'Vop = +4.75 V to +5.25 V; Vos = 4.75 V or 5.25 V; AGND = DGND = 0 V. Parts are guaranteed over this supply range. Unless otherwise stated tests are done at Von = 5 V; Vgg = ~5 V. *fox = 2.5 MHz. *SNR calculation includes distortion and noise components. Measured only at initial design characterization and after design or process changes which might affect this parameter. These limits are guaranteed even though they are not tested. 5Measured with respect to internal refernece and includes bipolar offset error. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. "Serial timing is measured with a 4.7 kQ pull-up resistor on SDATA and SSTRB and a 2k? pull-up on SCLK. The capacitance on all three outputs is 35 pF. sts is measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V. t, is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2. SCLK mark/space ratio measured from a voltage level of 1.6 V is 40/60 to 60/40. USDATA will drive higher capacitive loads but this will add the t,, since it increases the external RC time circuit (4.7 kQJIC_) and hence the time to reach 2.4 Vv. REV. B ANALOG-TO-DIGITAL CONVERTERS 6-155 ANALOG-TO-DIGITAL CONVERTERS aAD7870 3.2.1 Functional Block Diagram and Terminal Assignments. CLK ( 12/B/CLK CONVST Q Package (DIP) a [a] BUSYINT [2 | exk [3] DBi1/HBEN [4 | pB10/SSTAB [5 | opascrk [6 | pesspata [7 | pB7/Low [8 | pBeLow [2 | pasLow [10] peaLow [11 DGND [12 S AD7870 TOP VIEW (Not to Seale) j2a] CS 123] CONVST [22] 12/6/CLK 21] Veg 20} Vin [19] REF OUT [1a] AGND 7] 16] 5} 14] 13] Yoo DBO/DBB DB1/0B9 DB2/DB10 OBYDB11 AGND 3v REFERENCE | COUNTER } CONTROL t Loaic Le} PARALLEL | | | NIERE ACE AD7870 cS AD Busy 0811 DBO DGND Vag INT E Package (LCC) DBIV/HBEN 5 25 Vag DBIWSSTAB 6 24 Vy DBOSCLK 7 23 REF OUT NC 8 22 NC DB&SDATA 8 21 AGND DB7/LOW 10 20 Von DB6/LOW 11 19 DBO/DBS 3.2.4 Microcircuit Technology Group. This microcircuit is covered by technology group (81). 6-156 ANALOG-TO-DIGITAL CONVERTERS REV. BAD7870 4.2.1 Life Test/Burn-In Circuit. Steady state life test is per MIL-STD-883 Method 1005. Burn-in is per MIL-STD-883 Method 1015 test condition (B). 00 90000 r-q-4--------------------+----+-----~~__.--4 -t-t-4. - ! STEP AND I ! REPEAT CIRCUIT t 4x7 _ al _ I ! , 7 | a0 w n= [a | ausvinr cowvst [2s }H 4K7 I _ 1 I HWA T 3 | eux raecux | 22 ' \ TR 1 [4] obtieen Veg | 21 WW 1 __ I i [5] DB10/SSTRB Yw | 20] WA, i ' 470A ! | [6] DES/SCLK REF OUT 9] \ WY | [7] DBa/SDATA AGND 1a +e 1warr ' o 1 AA 1 Ee [s | OB7/LOW Yoo [17 } Ar rc ( I LL [2 | DBe/LOW DBO/DBS +6] > I ! [59] DBS/LOW DB1/OB9 15 | 5 t [a] DB4/LOW DB2DB10 14] 1 oO I l i 12] DGND 083/0B11 3] \ ni i AD7870 1 E I i O I l 1 1 5 TY ------- ed -4-4 tC 5 ALL RESISTORS ARE 1/4 WATT om o UNLESS OTHERWISE STATED. 000 a 4 8 28 F 3 3 oS o> > ie) F a \ / ZF v TEST POINTS | AD7870 Edge Connections (DIP) REV. B ANALOG-TO-DIGITAL CONVERTERS 6-157AD7870 rr eH AD7870 Edge Connections (LCC} 6-158 ANALOG-TO-DIGITAL CONVERTERS o0 990909 STEP AND REPEAT IRCU O.1pF _I If > eo e a|gl ?I8 -|g 47R cy AAA DB11/HBEN WY 1 WATT DB10/SSTRB AN 470R AD7870 TOP VIEW (Not to Scale) AAA vVV 47R + WATT 0.1uF iL 1 ALL RESISTORS ARE 1/4 WATT 00 UNLESS OTHERWISE STATED. O000 a Zaaq j 8 > > Sz a \ Vv TEST POINTS REV. BAD7870 REV. B TO OUTPUT PIN a. High Z to Vou b. High Z to Vo, Figure 1. Load Circuits 2.0V a4, Vow to High Z b. Vo, to High Z Figure 2. Load Circuits ANALOG-TO-DIGITAL CONVERTERS | ANALOG-TO-DIGITAL CONVERTERS 6-159