LTC1669
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BLOCK DIAGRAM
FEATURES
APPLICATIONS
DESCRIPTION
10-Bit Rail-to-Rail
Micropower DAC with
I2C Interface
The LTC
®
1669 is a 10-bit voltage output DAC with true
buffered rail-to-rail output voltage capability. It operates
from a single supply with a range of 2.7V to 5.5V. The
reference for the DAC is selectable between the supply
voltage or an internal bandgap reference. Selecting the
internal bandgap reference will set the full-scale output
voltage range to 2.5V. Selecting the supply as the reference
sets the output voltage range to the supply voltage.
The part features a simple 2-wire serial interface compat-
ible with I2C that allows communication between many
devices. The internal data registers are double buffered to
allow for simultaneous update of several devices at once.
The DAC can be put in low current power-down mode for
use in power conscious systems.
Power-on reset ensures the DAC output is at 0V when
power is initially applied, and all internal registers are
cleared. The LTC1669 is pin-for-pin compatible with the
LTC1663.
For SMBus-compatible designs, please refer to the
LTC1663.
Differential Nonlinearity (DNL)
n Micropower 10-Bit DAC in SOT-23
n
Low Operating Current: 60μA
n
Ultralow Power Shutdown Mode: 12μA
n
2-Wire Serial Interface Compatible
with I2C™
n
Selectable Internal Reference or Ratiometric to
V
CC
n
Maximum DNL Error: 0.75LSB
n
8 User Selectable Addresses (MSOP Package)
n
Single 2.7V to 5.5V Operation
n
Buffered True Rail-to-Rail Voltage Output
n
Power-On Reset
n
1.5V VIL and 2.1V VIH for SDA and SCL
n Small 5-Lead TSOT-23 and 8-Lead MSOP Packages
n Digital Calibration
n
Offset/Gain Adjustment
n
Industrial Process Control
n
Automatic Test Equipment
n
Arbitrary Function Generators
n Battery-Powered Data Conversion Products L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
10-BIT
DAC LATCH
INPUT
LATCH
2-WIRE INTERFACE
SDA
AD0
(6)
MSOP
PACKAGE
ONLY
(2)
(3)
AD1
AD2
SCL
1 (1) 5 (4)
GND
2 (7)
VOUT 3 (8)
1669 BD
VCC
1.25V
4 (5)
BANDGAP
REFERENCE
REFERENCE
SELECT
COMMAND
LATCH
NOTE: PIN NUMBERS IN PARENTHESES REFER TO THE MSOP PACKAGE
10-BIT BUFFERED VOUT DAC
CODE
0
–1.0
ERROR (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
156 512 640
1669 G02
–0.6
0.6
0.8
0.2
28 384 768 896 1024
VREF = VCC = 5V
TA = 25°C
LTC1669
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ABSOLUTE MAXIMUM RATINGS
VCC to GND .............................................. –0.3V to 7.5V
SDA, SCL ................................................. –0.3V to 7.5V
AD0, AD1, AD2 (MSOP Only) ........–0.3V to (VCC + 0.3V)
VOUT .............................................–0.3V to (VCC + 0.3V)
(Note 1)
1
2
3
4
SDA
AD1
AD2
SCL
8
7
6
5
VOUT
GND
AD0
VCC
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 150°C/W
SDA 1
GND 2
TOP VIEW
S5 PACKAGE
5-LEAD PLASTIC SOT-23
VOUT 3
5 SCL
4 VCC
TJMAX = 125°C, θJA = 250°C/W
PIN CONFIGURATION
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC1669CMS8#PBF LTC1669CMS8#TRPBF LTAHV 8-Lead Plastic MSOP 0°C to 70°C
LTC1669IMS8#PBF LTC1669IMS8#TRPBF LTAHX 8-Lead Plastic MSOP –40°C to 85°C
LTC1669-8CMS8#PBF LTC1669-8CMS8#TRPBF LTAHT 8-Lead Plastic MSOP 0°C to 70°C
LTC1669-8IMS8#PBF LTC1669-8IMS8#TRPBF LTAHU 8-Lead Plastic MSOP –40°C to 85°C
TAPE AND REEL (MINI) TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC1669CS5#TRMPBF LTC1669CS5#TRPBF LTAHW 5-Lead Plastic TSOT-23 0°C to 70°C
LTC1669-1CS5#TRMPBF LTC1669-1CS5#TRPBF LTAHR 5-Lead Plastic TSOT-23 0°C to 70°C
TRM = 500 pieces.
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
Consult LTC Marketing for information on lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
Operating Temperature Range
LTC1669C ............................................... 0°C to 70°C
LTC1669I............................................. –40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................. 300°C
LTC1669
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ELECTRICAL CHARACTERISTICS
The ● denotes specifi cations which apply over the full operating tempera-
ture range, otherwise specifi cations are at TA = 25°C. VCC = 2.7V to 5.5V, VCC set as reference, VOUT unloaded, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DAC
Resolution l10 Bits
Monotonicity (Note 2) l10 Bits
DNL Differential Nonlinearity Guaranteed Monotonic (Note 2) l±0.2 ±0.75 LSB
INL Integral Nonlinearity (Note 2) l±0.5 ±2.5 LSB
VOS Offset Error Measured at Code 20 l±10 ±30 mV
VOSTC Offset Error Temperature Coeffi cient ±15 μV/°C
FSE Full-Scale Error Reference Set to VCC
Reference Set to Internal Bandgap
l
l
±3
±3
±15
±15
LSB
LSB
VOUT DAC Output Span Reference Set to VCC
Reference Set to Internal Bandgap
0 to VCC
0 to 2.5
V
V
VFSTC Full-Scale Voltage Temperature
Coeffi cient
Reference Set to VCC
Reference Set to Internal Bandgap
±30
±50
μV/°C
μV/°C
PSRR Power Supply Rejection Ratio Reference Set to Internal Bandgap,
Code = 1023
±0.4 LSB/V
Power Supply
VCC Positive Supply Voltage l2.7 5.5 V
ICC Supply Current VCC = 3V (Note 3)
VCC = 5V (Note 3)
l
l
60
75
100
125
μA
μA
ISD Supply Current in Shutdown Mode (Note 3) l12 24 μA
Op Amp DC Performance
Short-Circuit Current (Sourcing) VOUT Shorted to GND, Input Code = 1023 l25 100 mA
Short-Circuit Current (Sinking) VOUT Shorted to VCC, Input Code = 0 l30 120 mA
Output Impedance to GND Input Code = 0, VCC = 5V
Input Code = 0, VCC = 5V
In Shutdown Mode
65
150
500
Ω
Ω
kΩ
Output Impedance to VCC Input Code = 1023, VCC = 5V
Input Code = 1023, VCC = 5V
80
120
Ω
Ω
AC Performance
Voltage Output Slew Rate Rising (Notes 4, 5)
Falling (Notes 4, 5)
0.75
0.25
V/μs
V/μs
Voltage Output Settling Time To ±0.5LSB (Notes 4, 5) 30 μs
Digital Feedthrough 0.75 nV•s
Digital-to-Analog Glitch Impulse 1LSB Change Around Major Carry 70 nV•s
Digital Inputs SCL, SDAs
VIH High Level Input Voltage l2.1 V
VIL Low Level Input Voltage l1.5 V
VLT H Logic Threshold Voltage 1.8 V
ILEAK Digital Input Leakage VCC = 5.5V and 0V, VIN = GND to VCC l±1 μA
CIN Digital Input Capacitance (Note 7) l10 pF
Digital Output SDA
VOL Digital Output Low Voltage IPULLUP = 3mA l0.4 V
LTC1669
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ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Nonlinearity and monotonicity are defi ned from code 20 to code
1003 (full scale). See Applications Information.
The ● denotes specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at TA = 25°C. VCC = 2.7V to 5.5V, VCC set as reference, VOUT unloaded, unless otherwise noted.
Note 3: Digital inputs at 0V or VCC.
Note 4: Load is 10kΩ in parallel with 100pF.
Note 5: VCC = VREF = 5V. DAC switched between 0.1VFS and 0.9VFS,
i.e., codes k = 102 and k = 922.
Note 6: All values are referenced to VIH and VIL levels.
Note 7: Guaranteed by design and not subject to test.
SYMBOL PARAMETER MIN TYP MAX UNITS
Timing Characteristics (Notes 6, 7)
fSCL Clock Operating Frequency ●100 kHz
tBUF Bus Free Time Between Stop and Start Condition ●4.7 μs
tHD, STA Hold Time After (Repeated) Start Condition ●4μs
tSU, STA Repeated Start Condition Setup Time ●4.7 μs
tSU, STO Stop Condition Setup Time ●4μs
tHD, DAT (IN) Data Hold Time (Input) ●0ns
tHD, DAT (OUT) Data Hold Time (Output) ●225 500 3450 ns
tSU, DAT Data Setup Time ●250 ns
tLOW Clock Low Period ●4.7 μs
tHIGH Clock High Period ●4μs
tfClock, Data Fall Time ●20 300 ns
trClock, Data Rise Time ●20 1000 ns
TIMING CHARACTERISTICS
The ● denotes specifi cations which apply over the full operating tempera-
ture range, otherwise specifi cations are at TA = 25°C. VCC = 2.7V to 5.5V, VCC set as reference, VOUT unloaded, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Address Inputs AD0, AD1, AD2 (MSOP Only)
IUP Address Pin Pull-Up Current VIN = 0V l0.5 1.5 μA
VIH High Level Input Voltage lVCC – 0.3 V
VIL Low Level Input Voltage l0.8 V
LTC1669
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Integral Nonlinearity (INL) Differential Nonlinearity (DNL)
Source and Sink Current
Capability with VCC = 5V
Large-Signal Step Response Midscale Glitch Load Regulation vs Output Current
CODE
0
–1.0
ERROR (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
156 512 640
1669 G01
–0.6
0.6
0.8
0.2
28 384 768 896 1024
VREF = VCC = 5V
TA = 25°C
CODE
0
–1.0
ERROR (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
156 512 640
1669 G02
–0.6
0.6
0.8
0.2
28 384 768 896 1024
VREF = VCC = 5V
TA = 25°C
OUTPUT CURRENT SOURCE/SINK (mA)
01 3
OUTPUT VOLTAGE (V)
3.0
4.0
5.0
4.5
3.5
2.5
1.5
0.5
8
1669 G03
2.0
1.0
0246
579
10
DAC CODE = 1023
DAC CODE = 0
TA = 25°C
5
5
0
4
3
2
VOUT
(VOLTS)
SDA
(VOLTS)
1
0
1669 G04
CODE = 990
CODE = 32
5μs/DIV
VCC = 5V
RL = 4.7k
CL = 100pF
TA = 25°C
5V
0V
VOUT
10mV/DIV
SDA
1669 G05
2μs/DIV
VCC = 5V
RL = 4.7k
CL = 100pF
TA = 25°C
CODE = 512 TO 511
IOUT (mA)
–4
–1.0
ΔVOUT (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
–2 01
1669 G06
–0.6
0.6
0.8
0.2
–3 –1 234
VCC = VREF = 5V
VOUT = 2.5V
CODE = 512
TA = 25°C
SOURCE SINK
TYPICAL PERFORMANCE CHARACTERISTICS
Load Regulation vs Output Current
Offset Error Voltage vs
Temperature
Full-Scale Output Voltage vs
Temperature
IOUT (mA)
–1.0
–1.0
ΔVOUT (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
–0.6 –0.4 00.2
1669 G07
–0.6
0.6
0.8
0.2
–0.8 –0.2 0.60.4 0.8 1.0
VCC = VREF = 3V
VOUT = 1.5V
CODE = 512
TA = 25°C
SOURCE SINK
TEMPERATURE (°C)
–60
OFFSET ERROR VOLTAGE (mV)
5
4
3
2
1
0
–1
–2
–3
–4
–5
–20 20 40
1669 G08
–40 0 60 80 100
TEMPERATURE (°C)
–60
OUTPUT VOLTAGE (V)
2.510
2.508
2.506
2.504
2.502
2.500
2.498
2.496
2.494
2.492
2.490
–20 20 40
1669 G09
–40 0 60 80 100
REFERENCE SET TO
INTERNAL BANDGAP
LTC1669
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PIN FUNCTIONS
SDA (Pin 1, Pin 1 on SOT-23): Serial Data Bidirectional
Pin. Data is shifted into the SDA pin and acknowledged
by the SDA pin. High impedance pin while data is shifted
in. Open-drain N-channel output during acknowledgment.
Requires a pull-up resistor or current source to VCC.
AD1 (Pin 2): Slave Address Select Bit 1. Tie this pin to
either VCC or GND to modify the corresponding bit of the
LTC1669’s slave address.
AD2 (Pin 3): Slave Address Select Bit 2. Tie this pin to
either VCC or GND to modify the corresponding bit of the
LTC1669’s slave address.
SCL (Pin 4, Pin 5 on SOT-23): Serial Clock Input Pin.
Data is shifted into the SDA pin at the rising edges of the
clock. This high impedance pin requires a pull-up resistor
or current source to VCC.
VCC (Pin 5, Pin 4 on SOT-23): Power Supply. 2.7V ≤ VCC
≤ 5.5V. Also used as the reference voltage input when the
part is programmed to use VCC as the reference.
AD0 (Pin 6): Slave Address Select Bit 0. Tie this pin to
either VCC or GND to modify the corresponding bit of the
LTC1669’s slave address.
GND (Pin 7, Pin 2 on SOT-23): System Ground.
VOUT (Pin 8, Pin 3 on SOT-23): Voltage Output. Buffered
rail-to-rail DAC output.
LTC1669
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Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
two adjacent codes. The DNL error between any two codes
is calculated as follows:
DNL = (ΔVOUT – LSB)/LSB
Where ΔVOUT is the measured voltage difference between
two adjacent codes.
Digital Feedthrough: The glitch that appears at the ana-
log output caused by AC coupling from the digital inputs
when they change state. The area of the glitch is specifi ed
in (nV)(sec).
Full-Scale Error (FSE): The deviation of the actual full-scale
voltage from ideal. FSE includes the effects of offset and
gain errors (see Applications Information).
Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve (Endpoint INL). Because the output cannot go
below zero, the linearity is measured between full scale
and the lowest code that guarantees the output will be
greater than zero. The INL error at a given input code is
calculated as follows:
INL = [VOUT – VOS – (VFS – VOS)(code/1023)]/LSB
Where VOUT is the output voltage of the DAC measured
at the given input code.
Least Signifi cant Bit (LSB): The ideal voltage difference
between two successive codes.
LSB = VREF/1024
Resolution (n): Defi nes the number of DAC output states
(2n) that divide the full-scale range. Resolution does not
imply linearity.
Voltage Offset Error (VOS): Nominally, the voltage at the
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Applications Information).
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
DEFINITIONS
LTC1669
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TIMING DIAGRAM
Typical LTC1669 Input Waveform—Programming DAC Output for Full Scale (AD2 to AD0 Set High)
ACK ACK
123
ADDRESS
456789123456789123456789123456789
FULL-SCALE
VOLTAGE
ZERO-SCALE
VOLTAGE
1669 TA02
01001110
0 1 0 0 AD2 AD1 AD0 WR
XXXXX000
XXXXXBGSDSY
11111111
D7 D6 D5 D4 D3 D2 D1 D0
XXXXXX11
XXXXXXD9D8
ACK
STOPSTART
SDA
SCL
VOUT
NOTE: X = DON’T CARE
ACK
COMMAND LS DATA MS DATA
tSU, DAT
tHD, STA
tHD, DAT
SDA
SCL
tSU, STA
tHD, STA tSU, STO
1669 TD
tBUF
tLOW
tHIGH
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
trtf
LTC1669
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APPLICATIONS INFORMATION
Serial Digital Interface
The LTC1669 communicates with a host (master) using
the standard 2-wire interface. The Timing Diagram shows
the timing relationship of the signals on the bus. The two
bus lines, SDA and SCL, must be high when the bus is
not in use. External pull-up resistors or current sources,
such as the LTC1694 SMBus/I2C Accelerator, are required
on these lines.
The LTC1669 is a receive-only (slave) device. The master
can communicate with the LTC1669 using the Quick Com-
mand, Send Byte or Write Word protocols as explained
later.
The START and STOP Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a communica-
tion to a slave device by transmitting a START condition.
A START condition is generated by transitioning SDA
from high to low while SCL is high.
When the master has fi nished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while
SCL is high. The bus is then free for communication with
another I2C device.
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the latest
byte of information was received. The Acknowledge related
clock pulse is generated by the master. The master releases
the SDA line (HIGH) during the Acknowledge clock pulse.
The slave-receiver must pull down the SDA line during the
Acknowledge clock pulse so that it remains a stable LOW
during the HIGH period of this clock pulse.
Write Word Protocol
The master initiates communication with the LTC1669 with
a START condition and a 7-bit address followed by the Write
Bit (Wr) = 0. The LTC1669 acknowledges and the master
delivers the command byte. The LTC1669 acknowledges
and latches the command byte into the command byte
input register. The master then delivers the least signifi cant
data byte. Again the LTC1669 acknowledges and the data
is latched into the least signifi cant data byte input register.
The master then delivers the most signifi cant data byte.
The LTC1669 acknowledges once more and latches the
data into the most signifi cant data byte input register.
Lastly, the master terminates the communication with a
STOP condition. On the reception of the STOP condition,
the LTC1669 transfers the input register information to
output registers and the DAC output is updated.
Slave Address (MSOP Package Only)
The LTC1669 can respond to one of eight 7-bit addresses.
The fi rst 4 bits (MSBs) have been factory programmed to
0100. The fi rst 4 bits of the LTC1669-8 have been factory
programmed to 0011. The three address bits, AD2, AD1
and AD0 are programmed by the user and determine the
LSBs of the slave address, as shown in the table below:
LTC1669 LTC-1669-8
AD2 AD1 AD0 0100 xxx 0011 xxx
L L L 0100 000 0011 000
L L H 0100 001 0011 001
L H L 0100 010 0011 010
L H H 0100 011 0011 011
H L L 0100 100 0011 100
H L H 0100 101 0011 101
H H L 0100 110 0011 110
H H H 0100 111 0011 111
Write Word Protocol Used by the LTC1669
Command Byte ASlave Address AWr LSData Byte A MSData Byte A PS
81711818
1669 TA03
111
S = Start Condition, Wr = Write Bit = 0, A = Acknowledge, P = Stop Condition
LTC1669
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APPLICATIONS INFORMATION
Slave Address (SOT-23 Package)
The slave address for the SOT-23 package has been
factory programmed to be “0100 000” (LTC
1669
) and
“0100 001” (LTC
1669
-1). If another address is required,
please consult the factory.
Command Byte
76543210
XXXXXBGSDSY
SY 1
0
Allows update on Acknowledge of SYNC Address only
Update on Stop condition only (Power-On Default)
SD 1
0
Puts the device in power-down mode
Puts the device in standard operating mode
(Power-On Default)
BG 1
0
Selects the internal bandgap reference
Selects the supply as the reference (Power-On Default)
X X Don’t Care
The stop condition normally initiates the update of the
DAC’s output latches. Simultaneous update of more than
one DAC or other devices on the bus can be achieved by
reissuing new start bit, address, command and data bytes
before issuing a fi nal stop condition (which will update
all the devices). An alternate way to achieve simultaneous
LTC1669 updates is to override the stop condition update
by setting the “SY” bit of the command byte. Setting this
bit sets the device to update the DAC output latches only
at the reception of a SYNC address quick command. The
actual update occurs on the rising edge of SCL during the
Acknowledge. In this way, all devices can update on the
reception of the SYNC address quick command instead
of the STOP condition.
A Shutdown (SD) bit = HIGH will put the device in a low
power state but retain all data latch information. Shutdown
will occur at the reception of a STOP condition. This way
shutdown could be synchronized to other devices. The
output impedance of the DAC will go to a high impedance
state (≈500kΩ to GND).
The Bandgap (BG) bit when set to “0” selects the DAC
supply voltage as its voltage reference. The full-scale
output of the DAC with this setting is equal to the supply
voltage. When the BG bit is set to “1,” the internal bandgap
reference (≈1.25V) is selected as the DAC’s reference. The
full-scale output voltage for this setting is 2.5V.
Data Bytes
Least Signifi cant Data Byte
76543210
D7 D6 D5 D4 D3 D2 D1 D0
Most Signifi cant Data Byte
76543210
XXXXXXD9D8
X = Don’t care
Send Byte Protocol
The Send Byte protocol used on the LTC1669 is actually a
subset of the Write Word protocol described previously.
The Send Byte protocol can only be used to send the
command byte information to the LTC1669.
Command Byte ASlave Address AWr PS
811711
1669 TA04
1
S = Start Condition, Wr = Write Bit, A = Acknowledge, P = Stop Condition
The Send Byte protocol is also used whenever the Write
Word protocol is interrupted for any reason. Reception of
a START or STOP condition after the Acknowledge of the
command byte, but before the Acknowledge of the last
data byte, will cause both data bytes to be ignored and
the command byte to be accepted.
Reception of a START or STOP condition before the Ac-
knowledge of the command byte will cause the interrupted
command byte to be ignored.
LTC1669
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APPLICATIONS INFORMATION
SYNC Address/Quick Command
In addition to the slave address, the LTC1669 has an address
that can be shared by other devices so that they may be
updated synchronously. The address is called to the SYNC
address and uses the quick command protocol.
The SYNC Address is 1111 110
Ack StopStart 1111 110 SY/CLR
1171
1669 TA05
1
SYNC Address
SY/CLR 1
0
Update output latches on rising edge of SCL during
Acknowledge of SYNC Address
Clear all internal latches on rising edge of SCL during
Acknowledge of SYNC Address
The SY/CLR bit set high only has meaning when the “SY”
bit of the command byte was previously set HIGH. On
the otherhand, the SY/CLR bit set LOW will always clear
the part, independent of the state of the “SY” bit in the
command byte.
Voltage Output
The output amplifi er contained in the LTC1669 can source
or sink up to 5mA. The output stage swings to within a
few millivolts of either supply rail when unloaded and
has an equivalent output resistance of 85Ω when driving
a load to the rails. The output amplifi er is stable driving
capacitive loads up to 1000pF.
A small resistor placed in series with the output can be
used to achieve stability for any load capacitance greater
than 1000pF. For example, a 0.1μF load can be driven
by the LTC1669 if a 110Ω series resistance is used. The
phase margin of the resulting circuit is 45° and increases
monotonically from this point if larger values of resistance,
capacitance or both are substituted for the values given.
Rail-to-Rail Output Considerations
As in any rail-to-rail device, the output is limited to volt-
ages within the supply range.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 1b.
Similarly, limiting can occur near full scale when VCC is
used as the reference. If VREF = VCC and the DAC full-scale
error (FSE) is positive, the output for the highest codes
limits at VCC as shown in Figure 1c. No full-scale limiting
can occur if the internal reference is used.
Offset and linearity are defi ned and tested over the region
of the DAC transfer function where no output limiting can
occur.
Internal Reference
In applications where a predictable output is required
that is independent of supply voltage, the LTC1669 has a
user-selectable internal reference. Selecting the internal
reference will set the full-scale output voltage to 2.5V. This
can be useful in applications where the supply voltage is
poorly regulated.
Using the LT
®
1460 Micropower Series Reference as a
Power Supply for the LTC1669
In applications where the advantages of using the internal
reference are required but the full-scale range needs to
be greater than 2.5V, an external series reference can be
used. The LT1460 is ideal for use as a power supply for
the LTC1669 and can provide 3V, 3.3V and 5V full-scale
output voltage ranges. The LT1460 provides accuracy, noise
immunity and extended supply range to the LTC1669 when
the LTC1669 is operated ratiometric to VCC. Since both
parts are available in SOT-23 packages, the PC board space
for this application is extremely small. See Figure 2.
LTC1669
12
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APPLICATIONS INFORMATION
Figure 1. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC
1669 F01
INPUT CODE
(b)
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
5120 1023
INPUT CODE
OUTPUT
VOLTAGE
(a)
VREF = VCC
VREF = VCC
(c)
INPUT CODE
OUTPUT
VOLTAGE
POSITIVE
FSE
LTC1669
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APPLICATIONS INFORMATION
Figure 2. LT1460 As Power Supply for the LTC1669
IN
0.1μF
1
5 (4)
1 (1)
2
4 (5)
2 (7)LTC1669 PIN NUMBERS IN PARENTHESES
REFER TO MSOP PACKAGE
3 (8)
3
3.9V TO 20V 3V
OUT
TO
μP
SCL
1669 F02
VCC
GND
SDA
OUTLTC1669 0V ≤ VOUT ≤ 3V
GND
LT1460S3-3
0.01μF
+
LTC1669
14
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S5 Package
5-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1635)
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.30 – 0.45 TYP
5 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3) S5 TSOT-23 0302
PIN ONE
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 – 0.90
1.00 MAX
0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.62
MAX
0.95
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
PACKAGE DESCRIPTION
LTC1669
15
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
MSOP (MS8) 0603
0.53 ± 0.152
(.021 ± .006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.127 ± 0.076
(.005 ± .003)
0.86
(.034)
REF
0.65
(.0256)
BSC
0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
12
34
4.90 ± 0.152
(.193 ± .006)
8765
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
0.52
(.0205)
REF
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 ± 0.038
(.0165 ± .0015)
TYP
0.65
(.0256)
BSC
LTC1669
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2007
LT 1007 REV A • PRINTED IN USA
RELATED PARTS
TYPICAL APPLICATION
Program Up to 16 Control Outputs Per BUS and Place Them Where They Are Needed
+
SCL
AD0
AD1
AD2
LTC1669CMS8
VCC
VOUT CONTROL
OUTPUT 0
0V ≤ VOUT0 < VCC
0.1μF
0.1μF
1
2
5
7
5
8
7
7
5
8
8
5
4
4
1
6
2
3GND
+
SCL
AD0
AD1
AD2
LTC1669CMS8
VCC
VOUT CONTROL
OUTPUT 1
0V ≤ VOUT1 < VCC
0.1μF
GND
+
SCL
AD0
AD1
AD2
LTC1669-8CMS8
VCC
VOUT CONTROL
OUTPUT 15
0V ≤ VOUT15 < VCC
0.1μF
GND
1669 TA06
SMBus 1
LTC1694
SMBus 2
GND
VCC
VCC = 2.7V TO 5.5V
TO OTHER I2C
DEVICES
+
SCL
μP
SDA
SDA
1
4
6
2
3
SDA
1
4
6
2
3
SDA
PART NUMBER DESCRIPTION COMMENTS
LTC1694 SMBus/I2C Accelerator Dual SMBus Accelerator with Active AC and DC Pull-Up Current Sources
LTC1694-1 SMBus/I2C Accelerator Dual SMBus Accelerator with Active AC Pull-Up Current Only
DACs
LTC1659 Single Rail-to-Rail 12-Bit VOUT DAC in 8-Lead MSOP
Package. VCC = 2.7V to 5.5V
Low Power Multiplying VOUT DAC. Output Swings from GND to REF. REF
Input Can Be Tied to VCC. 3-Wire Interface.
LTC1660/LTC1664 Octal/Quad 10-Bit VOUT DACs in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V Micropower Rail-to-Rail Output. 3-Wire Interface.
LTC1661 Dual 10-Bit VOUT in 8-Lead MSOP Package VCC = 2.7V to 5.5V Micropower Rail-to-Rail Output. 3-Wire Interface.
LTC1663 10-Bit VOUT in SOT-23, SMBUS Interface Pin Compatible with LTC1669
ADCs
LTC1285/LTC1288 8-Pin SO, 3V Micropower ADCs 1- or 2-Channel, Autoshutdown
LTC1286/LTC1298 8-Pin SO, 5V Micropower ADCs 1- or 2-Channel, Autoshutdown
