DS2432P-W09+1T - Maxim Integrated Products, Inc.

PRELIMINARY

1 of 17 060608

FEATURES

 1128 Bits of 5V EEPROM Memory

Partitioned Into Four Pages of 256 Bits, a

64-Bit Write-Only Secret, and Up to Five

General-Purpose Read/Write Registers

 On-Chip 512-Bit ISO/IEC 10118-3 SHA-1

Engine to Compute 160-Bit Message

Authentication Codes (MACs) and to

Generate Secrets

 Write Access Requires Knowledge of the

Secret and the Capability of Computing and

Transmitting a 160-Bit MAC as

Authorization

 Secret and Data Memory Can Be Write

Protected (All or Page 0 Only) or Put in

EPROM-Emulation Mode (“Write to 0”,

Page 1)

 Unique, Factory-Lasered and Tested 64-Bit

Registration Number Assures Absolute

Traceability Because No Two Parts Are Alike

 Built-In Multidrop Controller Ensures

Compatibility with Other 1-Wire® Net

Products

 Reduces Control, Address, Data, and Power

to a Single Data Pin

 Directly Connects to a Single Port Pin of a

Microprocessor and Communicates at Up to

16.3kbps

 Overdrive Mode Boosts Communication

Speed to 142kbps

 Low-Cost 6-Lead TSOC Surface-Mount

Package or Solder-Bumped UCSP™ Package

 Reads and Writes Over a Wide Voltage

Range of 2.8V to 5.25V from -40°C to +85°C

PIN CONFIGURATIONS

TSOC

(150 mils)

6 NC

5 NC

4 NC

GND 1

1- Wire 2

NC 3

UCSP

(TOP VIEW WITH LASER

MARK, CONTACTS NOT

VISIBLE)

A2 = 1-WIRE

A3 = GND

ALL OTHER BUMPS: NC

yywwrr = DATE/REVISION

###xx = LOT NUMBER

REFER TO THE PACKAGE RELIABILITY REPORT FOR

IMPORTANT GUIDELINES ON QUALIFIED USAGE CONDITIONS.

1 2 3 4

A1 MARK

S2432

yywwrr

##xx

ORDERING INFORMATION

PART TEMP

RANGE PIN-

PACKAGE

DS2432P+ -40°C to +85°C 6 TSOC

DS2432P+T&R -40°C to +85°C 6 TSOC

DS2432X+ -40°C to +85°C 8 UCSP (10k

pcs, T&R)

DS2432X-S+ -40°C to +85°C 8 UCSP (2.5k

pcs, T&R)

+Denotes a lead(Pb)-free/RoHS-compliant package.

T&R = Tape and reel.

Request Full Data Sheet at:

www.maxim-ic.com/fullds/DS2432

1-Wire is a registered trademark of Maxim Integrated Products, Inc.

DS2432

1Kb Protected 1-Wire EEPROM

with SHA-1 Engine

ABRIDGED DATA SHEET

www.maxim-ic.com

TOP VIEW

PRELIMINARY

ABRIDGED DATA SHEET DS2432

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DESCRIPTION

The DS2432 combines 1024 bits of EEPROM, a 64-bit secret, an 8-byte register/control page with up to

five user read/write bytes, a 512-bit SHA-1 engine, and a fully-featured 1-Wire interface in a single chip.

Each DS2432 has its own 64-bit ROM registration number that is factory lasered into the chip to provide

a guaranteed unique identity for absolute traceability. Data is transferred serially via the 1-Wire protocol,

which requires only a single data lead and a ground return. The DS2432 has an additional memory area

called the scratchpad that acts as a buffer when writing to the main memory, the register page or when

installing a new secret. Data is first written to the scratchpad from where it can be read back. After the

data has been verified, a copy scratchpad command will transfer the data to its final memory location,

provided that the DS2432 receives a matching 160-Bit MAC. The computation of the MAC involves the

secret and additional data stored in the DS2432 including the device’s registration number. Only a new

secret can be loaded without providing a MAC. The SHA-1 engine can also be activated to compute

160-bit message authentication codes (MAC) when reading a memory page or to compute a new secret,

instead of loading it. Applications of the DS2432 include intellectual property security, after-market

management of consumables, and tamper-proof data carriers.

OVERVIEW

The block diagram in Figure 1 shows the relationships between the major control and memory sections of

the DS2432. The DS2432 has five main data components: 1) 64-bit lasered ROM, 2) 64-bit scratchpad, 3)

four 32-byte pages of EEPROM, 4) 64-bit register page, 5) 64-bit Secrets Memory, and 6) a 512-bit

SHA-1 Engine (SHA = Secure Hash Algorithm). The hierarchical structure of the 1-Wire protocol is

shown in Figure 2. The bus master must first provide one of the seven ROM Function Commands, 1)

Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5) Resume Communication, 6) Overdrive-

Skip ROM or 7) Overdrive-Match ROM. Upon completion of an Overdrive ROM command byte

executed at regular speed, the device will enter Overdrive mode where all subsequent communication

occurs at a higher speed. The protocol required for these ROM function commands is described in Figure

9. After a ROM function command is successfully executed, the memory and SHA-1 functions become

accessible and the master may provide any one of the seven memory function commands. The protocol

for these memory function commands is described in Figure 7*. All data is read and written least

significant bit first.

* For Figure 7, refer to the full version of the data sheet.

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ABRIDGED DATA SHEET DS2432

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DS2432 BLOCK DIAGRAM Figure 1

PARASITE POWER

1-Wire net

64-bit

Lasered ROM

1-Wire

Function Control

Secrets Memory

64 bits

64-bit

Scratchpad

Data Memory

4 Pages of

256 bits each

CRC16

Generator

Memory and

SHA Function

Control Unit

512-bit

Secure Hash

Algorithm

Engine

64 bits

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ABRIDGED DATA SHEET DS2432

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64-BIT LASERED ROM

Each DS2432 contains a unique ROM code that is 64 bits long. The first eight bits are a 1-Wire family

code. The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits. (See

Figure 3.) The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and

XOR gates as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about the

1-Wire Cyclic Redundancy Check is available in Application Note 27. The shift register bits are

initialized to zero. Then starting with the least significant bit of the family code, one bit at a time is

shifted in. After the 8th bit of the family code has been entered, then the serial number is entered. After the

48th bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the

eight bits of CRC should return the shift register to all zeros.

HIERARCHCAL STRUCTURE FOR 1-Wire PROTOCOL Figure 2

1-Wire net Other

Devices

BUS

Master

DS2432

Available

Commands:

Command

Level: Data Field

Affected:

1-Wire ROM Function

Commands (see Figure 9)

DS2432-specific

Memory Function

Commands (see Figure 7)

Read ROM

Match ROM

Search ROM

Skip ROM

Resume

Overdrive Sk ip

Overdrive Match

64-bit Reg. #, RC-Flag

RC-Flag

RC-Flag, OD-Flag

64-bit Reg. #, RC-Flag, OD-Flag

For details see the full

version of the data sheet.

64-BIT LASERED ROM Figure 3

MSB LSB

8-Bit CRC Code 48-Bit Serial Number 8-Bit Family Code*

MSB LSB MSB LSB MSB LSB

*For the actual Family Code value, refer to the full version of the data sheet.

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ABRIDGED DATA SHEET DS2432

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1-Wire CRC GENERATOR Figure 4

X0X1X2X3X4X5X6X7X8

Polynomial = X8 + X5 + X4 + 1

1st

STAGE 2nd

STAGE 3rd

STAGE 4th

STAGE 6th

STAGE

5th

STAGE 7th

STAGE 8th

STAGE

INPUT DATA

MEMORY MAP

The DS2432 has four memory areas: data memory, secrets memory, register page with special function

registers and user-bytes, and a scratchpad. The data memory is organized in pages of 32 bytes. Secret,

memory, loading the initial secret or when writing to the register page. For further details (including

Figure 5) refer to the full version of the data sheet.

ADDRESS REGISTERS AND TRANSFER STATUS

The DS2432 employs three address registers: TA1, TA2 and E/S (Figure 6). These registers are common

to many other 1-Wire devices but operate slightly differently with the DS2432. Registers TA1 and TA2

must be loaded with the target address to which the data will be written or from which data will be read.

Since the scratchpad of the DS2432 is designed to accept data in blocks of eight bytes only, the lower

three bits of TA1 will be forced to 0 and the lower three bits of the E/S register (Ending Offset) will

always read 1. This indicates that all the data in the scratchpad will be used for a subsequent copying into

main memory or secret. Bit 5 of the E/S register, called PF or “partial byte flag”, is a logic-1 if the

number of data bits sent by the master is not an integer multiple of 8 or if the data in the scratchpad is not

valid due to a loss of power. A valid write to the scratchpad will clear the PF bit. Bits 3, 4 and 6 have no

function; they always read 1. The Partial Flag supports the master checking the data integrity after a

Write command. The highest valued bit of the E/S register, called AA or Authorization Accepted, acts as

a flag to indicate that the data stored in the scratchpad has already been copied to the target memory

address. Writing data to the scratchpad clears this flag.

ADDRESS REGISTERS Figure 6

Bit # 7 6 5 4 3 2 1 0

Target Address (TA1) T7 T6 T5 T4 T3 T2

(0) T1

(0) T0

(0)

Target Address (TA2) T15 T14 T13 T12 T11 T10 T9 T8

Ending Address with

Data Status (E/S)

(Read Only) AA 1 PF 1 1 E2

(1) E1

(1) E0

(1)

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WRITING WITH VERIFICATION

To write data to the DS2432, the scratchpad has to be used as intermediate storage. First the master issues

the Write Scratchpad command to specify the desired target address, followed by the data to be written to

the scratchpad. Note that writes to data memory must be performed on 8-byte boundaries with the 3 LSBs

of the target address (T2..T0) equal to 000b. If T2..T0 are sent with non-zero values, the device will set

these bits to zero and will write to the modified address upon completion of the command sequence. In

addition, the entire 8-byte scratchpad will be copied to memory when commanded, therefore eight bytes

of data should be written into the scratchpad to ensure that the data to be copied is known. Under certain

conditions (see the Write Scratchpad command) the master will receive an inverted CRC16 of the

command, address (actual address sent) and data at the end of the write scratchpad command sequence.

Note that the CRC is calculated based on the actual target address sent and not the modified address in the

case of a non-zero T2..T0. Knowing this CRC value, the master can compare it to the value it has

calculated itself to decide if the communication was successful and proceed to the Copy Scratchpad

command. If the master could not receive the CRC16, it should send the Read Scratchpad command to

verify data integrity. As preamble to the scratchpad data, the DS2432 repeats the target address TA1 and

TA2 and sends the contents of the E/S register. If the PF flag is set, data did not arrive correctly in the

scratchpad or there was a loss of power since data was last written to the scratchpad. The master does not

need to continue reading; it can start a new trial to write data to the scratchpad. Similarly, a set AA flag

together with a cleared PF flag indicates that the device did not recognize the Write command. If

everything went correctly, both flags are cleared. Now the master can continue reading and verifying

every data byte. After the master has verified the data, it can send the Copy Scratchpad command, for

example. This command must be followed exactly by the data of the three address registers TA1, TA2

and E/S. The master should obtain the contents of these registers by reading the scratchpad.

MEMORY AND SHA FUNCTION COMMANDS

This section describes the commands and flow charts to use the memory and SHA-1 engine of the device.

It includes Tables 1 to 4 and Figure 7. Please refer to th e full version of the data sheet.

SHA-1 COMPUTATION ALGORITHM

The SHA computation is adapted from the Secure Hash Standard SHA-1 document as it can be

downloaded from the NIST website (http://www.itl.nist.gov/fipspubs/fip180-1.htm). Further details are

found in the full version of the data sheet.

1-Wire BUS SYSTEM

The 1-Wire bus is a system, which has a single bus master and one or more slaves. In all instances the

DS2432 is a slave device. The bus master is typically a microcontroller. The discussion of this bus system

is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling

(signal types and timing). A 1-Wire protocol defines bus transactions in terms of the bus state during

specific time slots that are initiated on the falling edge of sync pulses from the bus master.

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HARDWARE CONFIGURATION

The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to

drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open

drain or 3-state outputs. The 1-Wire port of the DS2432 is open drain with an internal circuit equivalent

to that shown in Figure 8. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. At

regular speed the 1-Wire bus has a maximum data rate of 16.3kbps. The speed can be boosted to 142kbps

by activating the Overdrive Mode. The DS2432 requires a 1-Wire pullup resistor of maximum 2.2 k for

executing any of its memory and SHA function commands at any speed. When communicating with

several DS2432 simultaneously, e.g., to install the same secret in several devices, the resistor should be

bypassed by a low-impedance pullup to VPUP while the device transfers data from the scratchpad to the

EEPROM.

The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus

MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low

for more than 16 µs (Overdrive Speed) or more than 120 µs (regular speed), one or more devices on the

bus may be reset.

HARDWARE CONFIGURATION Figure 8

Open Drain

Port Pin

RX = RECEIVE

TX = TRANSMIT 100 

MOSFET

VPUP

TX TX

DATA

RPUP

BUS MASTER DS2432 1-Wire PORT

TRANSACTION SEQUENCE

The protocol for accessing the DS2432 via the 1-Wire port is as follows:

 Initialization

 ROM Function Command

 Memory or SHA Function Command

 Transaction/Data

INITIALIZATION

All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence

consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the

slave(s). The presence pulse lets the bus master know that the DS2432 is on the bus and is ready to

operate. For more details, see the 1-Wire Signaling section.

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ABRIDGED DATA SHEET DS2432

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ROM FUNCTION COMMANDS

Once the bus master has detected a presence, it can issue one of the seven ROM function commands that

the DS2432 supports. All ROM function commands are eight bits long. A list of these commands follows

(refer to flowchart in Figure 9):

Read ROM [33h]

This command allows the bus master to read the DS2432’s 8-bit family code, unique 48-bit serial

number, and 8-bit CRC. This command should only be used if there is a single slave on the bus. If more

than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same

time (open drain will produce a wired-AND result). The resultant family code and 48-bit serial number

read by the master will be invalid.

Match ROM [55h]

The match ROM command, followed by a 64-bit registration number, allows the bus master to address a

specific DS2432 on a multidrop bus. Only the DS2432 that exactly matches the 64-bit registration

number will respond to the following memory function command. All other slaves will wait for a reset

pulse. This command can be used with a single or multiple devices on the bus.

Search ROM [F0h]

When a system is initially brought up, the bus master might not know the number of devices on the

1-Wire bus or their 64-bit registration numbers. The search ROM command allows the bus master to use

a process of elimination to identify the 64-bit numbers of all slave devices on the bus. The search ROM

process is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write

the desired value of that bit. The bus master performs this 3-step routine on each bit of the registration

number. After one complete pass, the bus master knows the 64-bit number of one device. Additional

passes will identify the registration numbers of the remaining devices. Refer to Application Note 187 for

a detailed discussion of a search ROM, including an actual example.

Skip ROM [CCh]

This command can save time in a single drop bus system by allowing the bus master to access the

memory and SHA functions without providing the 64-bit registration number. If more than one slave is

present on the bus and, for example, a read command is issued following the Skip ROM command, data

collision will occur on the bus as multiple slaves transmit simultaneously (open-drain pulldowns will

produce a wired-AND result).

Overdrive Skip ROM [3Ch]

On a single-drop bus this command can save time by allowing the bus master to access the memory and

SHA functions without providing the 64-bit registration number. Unlike the normal Skip ROM command

the Overdrive Skip ROM sets the DS2432 in the Overdrive Mode (OD = 1). All communication

following this command code has to occur at Overdrive Speed until a reset pulse of minimum 480 µs

duration resets all devices on the bus to regular speed (OD = 0).

When issued on a multidrop bus this command will set all Overdrive-supporting devices into Ov erdrive

mode. To subsequently address a specific Overdrive-supporting device, a reset pulse at Overdrive speed

has to be issued followed by a Match ROM or Search ROM command sequence. This will speed up the

search process. If more than one Overdrive-supporting slave is present on the bus and the Overdrive Skip

ROM command is followed by a read command, data collision will occur on the bus as multiple slaves

transmit simultaneously (open drain pulldowns will produce a wired-AND result).

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ABRIDGED DATA SHEET DS2432

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ROM FUNCTIONS FLOW CHART Figure 9

From Figure 9

2nd Part

To Memory Functions

Flow Chart (Figure 7)

Master TX Bit 0

Master TX Bit 63

Master TX Bit 1

Bit 63

Match ?

RC = 0

DS2432 TX Bit 0

Master TX Bit 0

DS2432 TX Bit 1

Master TX Bit 1

DS2432 TX Bit 63

Master TX Bit 63

RC = 1

Bit 1

Match ?

Bit 0

Match ?

Bit 63

Match ?

RC = 0

RC = 1

Bit 1

Match ?

Bit 0

Match ?

RC = 0

DS2432 TX

CRC Byte

DS2432 TX

Serial Number

(6 By tes)

DS2432 TX

Family Code

(1 By te)

RC = 0

To Figure 9

2nd Part

F0h

Search ROM

Command ?

55h

Match ROM

Command ? N

CCh

Skip ROM

Command ?

33h

Read ROM

Command ?

To Figure 9

2nd Part

From Memory Functions

Flow Chart (Figure 9)

Bus Master TX ROM

Function Command DS2432 TX

Presence Pu lse

Reset Pulse ? N

OD = 0

Bus Master TX

Reset Pulse From Figure 9, 2n

Part

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ABRIDGED DATA SHEET DS2432

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ROM FUNCTIONS FLOW CHART (continued) Figure 9

To Figure 9

1st Part

From Figure 9

1st Part

From Figure 9

1st Part

To Figur e 9, 1s

Part

A5h

Resume

Command ?

RC = 1 ?

3Ch

Overdrive

Skip ROM ?

RC = 0 ; OD = 1

Master

TX Reset ?

Master

TX Reset ?

Master TX Bit 0

Master TX Bit 63

Master TX Bit 1

Bit 63

Match ?

RC = 0 ; OD = 1

RC = 1

Bit 1

Match ?

Bit 0

Match ?

69h

Overdrive Matc h

ROM ?

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ABRIDGED DATA SHEET DS2432

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Overdrive Match ROM [69h]

The Overdrive Match ROM command, followed by a 64-bit registration number transmitted at Overdrive

Speed, allows the bus master to address a specific DS2432 on a multidrop bus and to simultaneously set it

in Overdrive Mode. Only the DS2432 that exactly matches the 64-bit number will respond to the

subsequent memory or SHA function command. Slaves already in Overdrive mode from a previous

Overdrive Skip or a successful Overdrive Match command will remain in Overdrive mode. All Over-

drive-capable slaves will return to regular speed at the next Reset Pulse of minimum 480 µs duration. The

Overdrive Match ROM command can be used with a single or multiple devices on the bus.

Resume Command [A5h]

In a typical application the DS2432 needs to be accessed several times to write a full 32-byte page. In a

multidrop environment this means that the 64-bit registration number of a Match ROM command has to

be repeated for every access. To maximize the data throughput in a multidrop environment the Resume

Command function was implemented. This function checks the status of the RC bit and, if it is set,

directly transfers control to the Memory and SHA functions, similar to a Skip ROM command. The only

way to set the RC bit is through successfully executing the Match ROM, Search ROM or Overdrive

Match ROM command. Once the RC bit is set, the device can repeatedly be accessed through the Resume

Command function. Accessing another device on the bus will clear the RC bit, preventing two or more

devices from simultaneously responding to the Resume Command function.

1-Wire SIGNALING

The DS2432 requires strict protocols to ensure data integrity. The protocol consists of four types of sig-

naling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1 and Read Data.

Except for the presence pulse the bus master initiates all these signals. The DS2432 can communicate at

two different speeds, regular speed and Overdrive Speed. If not explicitly set into the Overdrive mode,

the DS2432 will communicate at regular speed. While in Overdrive Mode the fast timing applies to all

waveforms.

The initialization sequence required to begin any communication with the DS2432 is shown in Figure 10.

A Reset Pulse followed by a Presence Pulse indicates the DS2432 is ready to send or receive data. The

bus master transmits (TX) a reset pulse (tRSTL, minimum 480 µs at regular speed, 48 µs at Overdrive

Speed). The bus master then releases the line and goes into receive mode (RX). The 1-Wire bus is pulled

to a high state via the pullup resistor. After detecting the rising edge on the data pin, the DS2432 waits

(tPDH, 15-60 µs at regular speed, 2-6 µs at Overdrive speed) and then transmits the Presence Pulse (tPDL,

60-240 µs at regular speed, 8-24 µs at Overdrive Speed). A Reset Pulse of 480 µs or longer will exit the

Overdrive Mode returning the device to regular speed. If the DS2432 is in Overdrive Mode and the Reset

Pulse is no longer than 80 µs the device will remain in Overdrive Mode.

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INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 10

VPULLUP

VPULLUP MIN

VIH MIN

VIL MA

RESISTOR MASTER DS2432

tRSTL tPDL

tRSTH

tPDH

MASTER TX “RESET PULSE” MASTER RX “PRESENCE PULSE”

Read/Write Time Slots

The definitions of write and read time slots are illustrated in Figure 11. The master initiates all time slots

by driving the data line low. The falling edge of the data line synchronizes the DS2432 to the master by

triggering an internal delay circuit. During write time slots, the delay circuit determines when the DS2432

will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit

determines how long the DS2432 will hold the data line low. If the data bit is a “1”, the DS2432 will not

hold the data line low at all.

READ/WRITE TIMING DIAGRAM Figure 11

Write-one Time Slot

VPULLUP

VPULLUP MIN

VIH MIN

VIL MA

tLOW1

15 µs

(OD: 2 µs) 60 µs

(OD: 6 µs)

DS2432

Sampling Window

tREC tSLOT

RESISTOR

MASTER

Write-zero Time Slot

VPULLUP

VPULLUP MIN

VIH MIN

VIL MA

RESISTOR

MASTER

tLOW0

15 µs

(OD: 2 µs) 60 µs

(OD: 6 µs)

DS2432

Sampling Window

tREC tSLOT

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READ/WRITE TIMING DIAGRAM Figure 11 (continued)

Read-data Time Slot

PULLUP

IH M IN

PULLUP MIN

IL MAX

LOWR

tREC

tSLOT

MASTER *

SAMPLING

WINDOW

tRDV

tRELEASE

RESISTOR MASTER DS2432

*The optimal sampling point for the master is as close as possible to the end time of the tRDV period

without exceeding tRDV. For the case of a Read-one time slot, this maximizes the amount of time for the

pullup resistor to recover the line to a high level. For a Read-zero time slot it ensures that a read will

occur before the fastest 1-Wire device releases the line (tRELEASE = 0).

CRC GENERATION

With the DS2432 there are two different types of CRCs (Cyclic Redundancy Checks). One CRC is an

8-bit type. It is computed at the factory and lasered into the most significant byte of the 64-bit ROM. The

equivalent polynomial function of this CRC is X8 + X5 + X4 + 1. To determine whether the ROM data has

been read without error the bus master can compute the CRC value from the first 56 bits of the 64-bit

ROM and compare it to the value read from the DS2432. This 8-bit CRC is received in the true form

(non-inverted) when reading the ROM.

The other CRC is a 16-bit type, which is used for error detection with Memory and SHA-1 function

commands. For details (including Figure 12), refer to the full version of the data sheet.

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ABSOLUTE MAXIMUM RATINGS

Voltage Range on Any Pin Relative to Ground -0.5V to +5.5V

Operating Temperature Range -40C to +85C

Storage Temperature Range -55C to +125C

Soldering Temperature Refer to the IPC/JEDEC J-STD-020 Specification.

This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect

reliability.

DC ELECTRICAL CHARACTERISTICS (TA = -40°C to +85°C.)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

1-Wire Pullup Voltage VPUP 2.8 5.25 V 1, 2

1-Wire Input High VIH 2.2 V 1, 7

1-Wire Input Low VIL -0.3 TBD V 1, 8

1-Wire Output Low at 4mA VOL 0.4 V 1

Input Load Current IL 5

A 3

Programming Current ILPROG 500 A 9

SHA-1 Computation Current ICSHA Refer to the full version of data sheet.

CAPACITANCE (TA = +25°C.)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

1-Wire I/O CIN/OUT 100 800 pF 5

EEPROM (VPUP = 5.0V, TA = +25°C.)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Write/Erase Cycles NCYCLE 50k —

Data Retention (at 85°C) tDRET 10 years

AC ELECTRICAL CHARACTERISTICS

REGULAR SPEED (VPUP = 2.8V to 5.25V, TA = -40°C to +85°C.)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Time Slot tSLOT 60 120

s

Write 1 Low Time tLOW1 1 15

s

Write 0 Low Time tLOW0 60 120

s

Read Low Time tLOWR 1 15

s

Read Data Valid tRDV 15

s 10

Release Time tRELEASE 0 15 45 s

Read Data Setup tSU 1

s 4

Recovery Time tREC 1 s

Reset High Time tRSTH 480 s

Reset Low Time tRSTL 480 s 6

Presence Detect High tPDHIGH 15 60 s

Presence Detect Low tPDLOW 60 240 s

Programming Time tPROG 10 ms

SHA Computation Time tCSHA Refer to the full version of data sheet.

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AC ELECTRICAL CHARACTERISTICS

OVERDRIVE SPEED (VPUP = 2.8V to 5.25V, TA = -40°C to +85°C.)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Time Slot tSLOT 6 16 µs

Write 1 Low Time tLOW1 1 2 µs

Write 0 Low Time tLOW0 6 16 µs

Read Low Time tLOWR 1 2 µs

Read Data Valid tRDV 2 µs 10

Release Time tRELEASE 0 1.5 4 µs

Read Data Setup tSU 1 µs 4

Recovery Time tREC 1 µs

Reset High Time tRSTH 48 µs

Reset Low Time tRSTL 48 80 µs

Presence Detect High tPDHIGH 2 6 µs

Presence Detect Low tPDLOW 8 24 µs

Programming Time tPROG 10 ms

SHA Computation Time tCSHA Refer to the full version of data sheet.

NOTES:

1. All voltages are referenced to ground.

2. VPUP = external pullup voltage, see Figure 8.

3. Input load is to ground.

4. Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is

guaranteed to be valid within 1 µs of this falling edge.

5. Capacitance on the data pin could be 800 pF when power is first applied. If a 5 k resistor is used to

pull up the data line to VPUP, 5 µs after power has been applied the parasite capacitance will not affect

normal communications.

6. The reset low time (tRSTL) should be restricted to a maximum of 960 µs, to allow interrupt signaling,

otherwise, it could mask or conceal interrupt pulses.

7. VIH is a function of the external pullup resistor and VPUP.

8. Under certain low voltage conditions VILMAX may have to be reduced to as much as 0.5V to always

guarantee a Presence Pulse. VIL is a function of VPUP and the reset low time.

9. During write operations to the EEPROM the voltage on the 1-Wire bus must not fall below 2.8V. The

EEPROM write cycle takes max. 10 ms.

10. The optimal sampling point for the master is as close as possible to the end time of the tRDV period

without exceeding tRDV. For the case of a Read-one time slot, this maximizes the amount of time for

the pullup resistor to recover the line to a high level. For a Read-zero time slot it ensures that a read

will occur before the f astest 1-Wire device releases the line (tRELEASE = 0).

PRELIMINARY

ABRIDGED DATA SHEET DS2432

PACKAGE INFORMATION

For the latest package outline info rmation and land patterns, go to www.maxim-ic.com/packages.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

6 TSOC D6+1 21-0382

8 UCSP BR823+1 21-0373

16 of 17

PRELIMINARY

ABRIDGED DATA SHEET DS2432

17 of 17

Maxim/Dallas Semiconductor cannot assume responsibili ty for use of any circ uitr y o ther than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.

No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.

REVISION HISTORY

REVISION

DATE DESCRIPTION PAGES

CHANGED

040907 Initial release. —

Removed the leaded parts from the Ordering Information table and

corrected package name from CSP to UCSPR. 1

Removed 64-Bit Registration Number from Overdrive Skip ROM in

Figure 2. 4

Removed reference to tamper detect register (does not exist). 7

In Figure 8, changed “5A typ” to “IL”. 7

In the DC Electrical Characteristics table, added the 1-W ire Pullup

Voltage parameter (VPUP) (moved from the headline into the table) and

removed the 1-Wire Output High parameter (VOH). In the EEPROM table,

added (at +85C) to the Data Retention parameter.

Added Package Information section. 16

060608

Minor nontechnical corrections to the text (various pages). 1, 2, 4, 8, 15