MC10E111FNR2 - ON Semiconductor

November, 2006 − Rev. 16

1Publication Order Number:

MC10E111/D

MC10E111, MC100E111

5VECL 1:9 Differential

Clock Driver

Description

The MC10E/100E111 is a low skew 1-to-9 differential driver,

designed with clock distribution in mind. It accepts one signal input,

which can be either differential or else single-ended if the VBB output

is used. The signal is fanned out to 9 identical differential outputs. An

enable input is also provided. A HIGH disables the device by forcing

all Q outputs LOW and all Q outputs HIGH.

The device is specifically designed, modeled and produced with low

skew as the key goal. Optimal design and layout serve to minimize

gate to gate skew within-device, and empirical modeling is used to

determine process control limits that ensure consistent tpd

distributions from lot to lot. The net result is a dependable, guaranteed

low skew device.

The lowest TPD delay time results from terminating only one output

pair, and the greatest TPD delay time results from terminating all the

output pairs. This shift is about 10 – 20 pS in TPD. The skew between

any two output pairs within a device is typically about 25 nS. If other

output pairs are not terminated, the lowest TPD delay time results

from both output pairs and the skew is typically 25 nS. When all

outputs are terminated, the greatest TPD (delay time) occurs and all

outputs display about the same 10 – 20 pS increase in TPD, so the

relative skew between any two output pairs remains about 25 nS.

The VBB pin, an internally generated voltage supply, is available to

this device only. For single-ended input conditions, the unused

differential input is connected to VBB as a switching reference voltage.

VBB may also rebias AC coupled inputs. When used, decouple VBB

and VCC via a 0.01 mF capacitor and limit current sourcing or sinking

to 0.5 mA. When not used, VBB should be left open.

The 100 Series contains temperature compensation.

Features

•Guaranteed Skew Spec

•Differential Design

•VBB Output

•PECL Mode Operating Range: VCC = 4.2 V to 5.7 V

with VEE = 0 V

•NECL Mode Operating Range: VCC = 0 V

with VEE = −4.2 V to −5.7 V

•Internal Input 50 KW Pulldown Resistors

•ESD Protection: Human Body Model; > 3 kV

•Meets or Exceeds JEDEC Standard EIA/JESD78 IC

Latchup Test

•Moisture Sensitivity Level:

Pb = 1

Pb−Free = 3

For Additional Information, see Application Note

AND8003/D

•Flammability Rating: UL 94 V−0 @ 0.125 in,

Oxygen Index: 28 to 34

•Transistor Count = 178 devices

•Pb−Free Packages are Available*

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

MARKING DIAGRAM*

xxx = 10 or 100

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

G= Pb−Free Package

PLCC−28

FN SUFFIX

CASE 776

MCxxxE111G

AWLYYWW

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*For additional marking information, refer to

Application Note AND8002/D.

See detailed ordering and shipping information in the package

dimensions section on page 8 of this data sheet.

ORDERING INFORMATION

MC10E111, MC100E111

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567891011

25 24 23 22 21 20 19

VEE

VCC

VBB

VCCO

Pinout: 28-Lead PLCC

(Top View)

Q0Q0Q1VCCO Q1Q2Q2

Q8Q7Q6

Q8VCCO Q7Q6

Warning: All VCC, VCCO, and VEE pins must be exter-

nally connected to Power Supply to guarantee proper

operation.

* All VCC and VCCO pins are tied together on the die.

Figure 1. 28−Lead Pinout

Table 1. PIN DESCRIPTION

PIN FUNCTION

IN, IN

Q0, Q0−Q8, Q8

VBB

VCC, VCCO

VEE

ECL Differential Input Pair

ECL Enable

ECL Differential Outputs

Reference Voltage Output

Positive Supply

Negative Supply

No Connect

VBB

Figure 2. Logic Symbol

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Table 2. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

VCC PECL Mode Power Supply VEE = 0 V 8 V

VIPECL Mode Input Voltage

NECL Mode Input Voltage

VEE = 0 V

VCC = 0 V

VI v VCC

VI w VEE

−6

Iout Output Current Continuous

Surge

100

IBB VBB Sink/Source $0.5 mA

TAOperating Temperature Range −40 to +85 °C

Tstg Storage Temperature Range −65 to +150 °C

qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

PLCC−28

63.5

43.5

°C/W

qJC Thermal Resistance (Junction−to−Case) Standard Board PLCC−28 22 to 26 °C/W

Tsol Wave Solder Pb

Pb−Free

265

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may

affect device reliability.

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Table 3. 10E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 1)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current 41 60 42 60 43 60 mA

VOH Output HIGH Voltage (Note 2) 3920 4030 4110 4020 4105 4190 4090 4185 4280 mV

VOL Output LOW Voltage (Note 2) 3050 3230 3350 3050 3210 3370 3050 3227 3405 mV

VIH Input HIGH Voltage (Single−Ended) 3870 4030 4190 3870 4030 4190 3940 4110 4280 mV

VIL Input LOW Voltage (Single−Ended) 3050 3285 3520 3050 3285 3520 3050 3302 3555 mV

VBB Output Voltage Reference 3.6 3.73 3.65 3.75 3.69 3.90 V

VIHCMR Input HIGH Voltage Common Mode Range

(Differential Configuration) (Note 3)

3.4 4.6 3.4 4.6 3.4 4.6 V

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current 0.5 0.5 0.25 0.3 0.2 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.

2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.

3. VIHCMR min and max vary 1:1 with VCC.

Table 4. 10E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = −5.0 V (Note 4)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current 41 60 42 60 43 60 mA

VOH Output HIGH Voltage (Note 5) −1080 −970 −890 −980 −895 −810 −910 −815 −720 mV

VOL Output LOW Voltage (Note 5) −1950 −1770 −1650 −1950 −1790 −1630 −1950 −1773 −1595 mV

VIH Input HIGH Voltage (Single−Ended) −1130 −970 −810 −1130 −970 −810 −1060 −890 −720 mV

VIL Input LOW Voltage (Single−Ended) −1950 −1715 −1480 −1950 −1715 −1480 −1950 −1698 −1445 mV

VBB Output Voltage Reference −1.40 −1.27 −1.35 −1.25 −1.31 −1.19 V

VIHCMR Input HIGH Voltage Common Mode

Range (Differential Configuration)

(Note 6)

−1.6 −0.4 −1.6 −0.4 1.6 −0.4 V

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current 0.5 0.5 0.065 0.3 0.2 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

4. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.

5. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.

6. VIHCMR min and max vary 1:1 with VCC.

MC10E111, MC100E111

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Table 5. 100E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 7)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current 40 60 45 60 50 69 mA

VOH Output HIGH Voltage (Note 8) 3975 4020 4120 3975 4020 4120 3975 4020 4120 mV

VOL Output LOW Voltage (Note 8) 3190 3300 3380 3190 3300 3380 3190 3300 3380 mV

VIH Input HIGH Voltage (Single−Ended) 3835 3975 4120 3835 3975 4120 3835 3975 4120 mV

VIL Input LOW Voltage (Single−Ended) 3190 3355 3525 3190 3355 3525 3190 3355 3525 mV

VBB Output Voltage Reference 3.64 3.75 3.62 3.74 3.62 3.74 V

VIHCMR Input HIGH Voltage Common Mode Range

(Differential Configuration) (Note 9)

3.4 4.6 3.4 4.6 3.4 4.6 V

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current 0.5 0.5 0.25 0.5 0.2 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

7. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.

8. Outputs are terminated through a 50 W resistor to VCC − 2.0 V

9. VIHCMR min and max vary 1:1 with VCC.

Table 6. 100E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = −5.0 V (Note 10)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current 40 60 45 60 50 69 mA

VOH Output HIGH Voltage (Note 11) −1025 −980 −880 −1025 −980 −880 −1025 −980 −880 mV

VOL Output LOW Voltage (Note 11) −1810 −1700 −1620 −1810 −1700 −1620 −1810 −1700 −1620 mV

VIH Input HIGH Voltage (Single−Ended) −1165 −1025 −880 −1165 −1025 −880 −1165 −1025 −880 mV

VIL Input LOW Voltage (Single−Ended) −1810 −1645 −1475 −1810 −1645 −1475 −1810 −1645 −1475 mV

VBB Output Voltage Reference −1.38 −1.25 −1.38 −1.26 −1.38 −1.26 V

VIHCMR Input HIGH Voltage Common Mode

Range (Differential Configuration)

(Note 12)

−1.6 −0.4 −1.6 −0.4 −1.6 −0.4 V

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current 0.5 0.5 0.25 0.5 0.2 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

10.Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.

11. Outputs are terminated through a 50 W resistor to VCC − 2.0 V

12.VIHCMR min and max vary 1:1 with VCC.

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Table 7. AC CHARACTERISTICS VCCx = 5.0 V; VEE= 0.0 V or VCCx = 0.0 V; VEE= −5.0 V (Note 13)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

fMAX Maximum Toggle Frequency 800 800 800 MHz

tPLH

tPHL

Propagation Delay to Output

IN (Diff) (Note 14)

IN (SE) (Note 15)

Enable (Note 16)

Disable (Note 16)

430

380

400

630

680

900

430

380

450

630

680

850

430

380

450

630

680

850

tsSetup Time (Note 17) EN to IN 250 0 200 0 200 0 ps

tHHold Time (Note 18) IN to EN 50 −200 0 −200 0 −200 ps

tRRelease Time (Note 19) EN to IN 350 100 300 100 300 100 ps

tskew Within-Device Skew (Note 20) 25 75 25 50 25 50 ps

tJITTER Random Clock Jitter (RMS) < 1 < 2 < 1 < 2 < 1 < 2 ps

VPP Minimum Input Swing 50 50 50 mV

tr, tfRise/Fall Time 250 450 650 275 375 600 275 375 600 ps

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification

limit values are applied individually under normal operating conditions and not valid simultaneously.

13.10 Series: VEE can vary −0.46 V / +0.06 V.

100 Series: VEE can vary −0.46 / +0.8 V.

14. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of

the differential output signals.

15.The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.

16.Enable is defined as the propagation delay from the 50% point of a negative transition on EN to the 50% point of a positive transition

on Q (or a negative transition on Q). Disable is defined as the propagation delay from the 50% point of a positive transition on EN to the

50% point of a negative transition on Q (or a positive transition on Q).

17. The setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater

than $75 mV to that IN/IN transition (Figure 3).

18.The hold time is the minimum time that EN must remain asserted after a negative going IN or a positive going IN to prevent an output

response greater than $75 mV to that IN/IN transition (Figure 4).

19. The release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets

the specified IN to Q propagation delay and output transition times (Figure 5).

20.The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.

Figure 3. Setup Time

≤75mV

Figure 4. Hold Time

Figure 5. Release Time

EN 50%

50%

MC10E111, MC100E111

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100

200

300

400

500

600

700

800

900

0 300 600 900 1200 1500 1800 2100 2400

Figure 6. Fmax/Jitter

FREQUENCY (MHz)

(JITTER)

ÉÉÉÉÉÉÉÉ

VOUTpp (mV)

JITTEROUT ps (RMS)

ÉÉ

ÉÉÉÉÉÉÉ

ÉÉÉ

Figure 7. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020/D − Termination of ECL Logic Devices.)

Driver

Device

Receiver

Device

Q D

Zo = 50 W

50 W50 W

VTT

VTT = VCC − 2.0 V

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ORDERING INFORMATION

Device Package Shipping†

MC10E111FN PLCC−28 37 Units / Rail

MC10E111FNG PLCC−28

(Pb−Free)

37 Units / Rail

MC10E111FNR2 PLCC−28 500 / Tape & Reel

MC10E111FNR2G PLCC−28

(Pb−Free)

500 / Tape & Reel

MC100E111FN PLCC−28 37 Units / Rail

MC100E111FNG PLCC−28

(Pb−Free)

37 Units / Rail

MC100E111FNR2 PLCC−28 500 / Tape & Reel

MC100E111FNR2G PLCC−28

(Pb−Free)

500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

Resource Reference of Application Notes

AN1405/D −ECL Clock Distribution Techniques

AN1406/D −Designing with PECL (ECL at +5.0 V)

AN1503/D −ECLinPSt I/O SPiCE Modeling Kit

AN1504/D −Metastability and the ECLinPS Family

AN1568/D −Interfacing Between LVDS and ECL

AN1672/D −The ECL Translator Guide

AND8001/D −Odd Number Counters Design

AND8002/D −Marking and Date Codes

AND8020/D −Termination of ECL Logic Devices

AND8066/D −Interfacing with ECLinPS

AND8090/D −AC Characteristics of ECL Devices

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PACKAGE DIMENSIONS

PLCC−28

FN SUFFIX

PLASTIC PLCC PACKAGE

CASE 776−02

ISSUE E

−N−

−M−

−L−

Y BRK

28 1

VIEW S

L−M

0.010 (0.250) N S

L−M

0.007 (0.180) N S

0.004 (0.100)

SEATING

PLANE

L−M

0.007 (0.180) N S

−T−

L−M

0.010 (0.250) N S

L−M

0.007 (0.180) N S

L−M

0.007 (0.180) N S

G1X

VIEW D−D

L−M

0.007 (0.180) N S

VIEW S

L−M

0.007 (0.180) N S

NOTES:

1. DATUMS −L−, −M−, AND −N− DETERMINED

WHERE TOP OF LEAD SHOULDER EXITS

PLASTIC BODY AT MOLD PARTING LINE.

2. DIMENSION G1, TRUE POSITION TO BE

MEASURED AT DATUM −T−, SEATING PLANE.

3. DIMENSIONS R AND U DO NOT INCLUDE

MOLD FLASH. ALLOWABLE MOLD FLASH IS

0.010 (0.250) PER SIDE.

4. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

5. CONTROLLING DIMENSION: INCH.

6. THE PACKAGE TOP MAY BE SMALLER THAN

THE PACKAGE BOTTOM BY UP TO 0.012

(0.300). DIMENSIONS R AND U ARE

DETERMINED AT THE OUTERMOST

EXTREMES OF THE PLASTIC BODY

EXCLUSIVE OF MOLD FLASH, TIE BAR

BURRS, GATE BURRS AND INTERLEAD

FLASH, BUT INCLUDING ANY MISMATCH

BETWEEN THE TOP AND BOTTOM OF THE

PLASTIC BODY.

7. DIMENSION H DOES NOT INCLUDE DAMBAR

PROTRUSION OR INTRUSION. THE DAMBAR

PROTRUSION(S) SHALL NOT CAUSE THE H

DIMENSION TO BE GREATER THAN 0.037

(0.940). THE DAMBAR INTRUSION(S) SHALL

NOT CAUSE THE H DIMENSION TO BE

SMALLER THAN 0.025 (0.635).

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.485 0.495 12.32 12.57

B0.485 0.495 12.32 12.57

C0.165 0.180 4.20 4.57

E0.090 0.110 2.29 2.79

F0.013 0.019 0.33 0.48

G0.050 BSC 1.27 BSC

H0.026 0.032 0.66 0.81

J0.020 −−− 0.51 −−−

K0.025 −−− 0.64 −−−

R0.450 0.456 11.43 11.58

U0.450 0.456 11.43 11.58

V0.042 0.048 1.07 1.21

W0.042 0.048 1.07 1.21

X0.042 0.056 1.07 1.42

Y−−− 0.020 −−− 0.50

Z2 10 2 10

G1 0.410 0.430 10.42 10.92

K1 0.040 −−− 1.02 −−−

__ __

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

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Phone: 81−3−5773−3850

MC10E111/D

ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).

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