Atmel SAM R21E / SAM R21G SMART ARM-Based Wireless Microcontroller DATASHEET Description The Atmel(R) | SMARTTM SAM R21 is a series of low-power microcontrollers using the 32-bit ARM(R) Cortex(R)-M0+ processor and an integrated ultra-low power 2.4GHz ISM band transceiver. SAM R21 devices are available in 32- and 48-pin packages with up to 256KB Flash, 32KB of SRAM and are operating at a maximum frequency of 48MHz and reach 2.46 Coremark/MHz. They are designed for simple and intuitive migration with identical peripheral modules, hex compatible code, identical linear address map and pin compatible migration paths between all devices in the product series. All devices include intelligent and flexible peripherals, Atmel Event System for inter-peripheral signaling, and support for capacitive touch button, slider and wheel user interfaces. The Atmel SAM R21 devices provide the following features: In-system programmable Flash, optional 512KB serial Flash,12-channel direct memory access (DMA) controller, 12-channel Event System, programmable interrupt controller, up to 28 programmable I/O pins, ultra-low power 2.4GHz ISM band transceiver with a data rate of 250kb/s, 32-bit real-time clock and calendar, three 16-bit Timer/Counters (TC) and three 16-bit Timer/Counters for Control (TCC), where each TC can be configured to perform frequency and waveform generation, accurate program execution timing or input capture with time and frequency measurement of digital signals. The TCs can operate in 8- or 16-bit mode, selected TCs can be cascaded to form a 32-bit TC, and the three Timer/Counters for Control have extended functions optimized for motor, lighting and other control applications. The series provide one full-speed USB 2.0 embedded host and device interface; up to five Serial Communication Modules (SERCOM) that each can be configured to act as an USART, UART, SPI, I2C up 3.4MHz and LIN slave; up to eight channel 350ksps 12-bit ADC with programmable gain and optional oversampling and decimation supporting up to 16-bit resolution, two analog comparators with window mode, Peripheral Touch Controller supporting up to 48 buttons, sliders, wheels and proximity sensing; programmable Watchdog Timer, brown-out detector and power-on reset and two-pin Serial Wire Debug (SWD) program and debug interface. All devices have accurate and low-power external and internal oscillators. All oscillators can be used as a source for the system clock. Different clock domains can be independently configured to run at different frequencies, enabling power saving by running each peripheral at its optimal clock frequency, and thus maintaining a high CPU frequency while reducing power consumption. The SAM R21 devices have two software-selectable sleep modes, idle and standby. In idle mode the CPU is stopped while all other functions can be kept running. In standby all clocks and functions are stopped expect those selected to continue running. The device supports SleepWalking, which is the module's ability to wake itself up and wake up its own clock, and hence perform predefined tasks without waking up the CPU. The CPU can then be only woken on a need basis, e.g. a threshold is crossed or a result is ready. The Event System supports synchronous and asynchronous events, allowing peripherals to receive, react to and send events even in standby mode. The Flash program memory can be reprogrammed in-system through the SWD interface. The same interface can be used for non-intrusive on-chip debug of application code. A boot loader running in the device can use any communication interface to download and upgrade the application program in the Flash memory. The SAM R21 devices are supported with a full suite of program and system development tools, including C compilers, macro assemblers, program debugger/simulators, programmers and evaluation kits. Atmel-42223G-SAM-R21_Datasheet-05/2016 SMART Features z Processor z ARM Cortex-M0+ CPU running at up to 48MHz z Single-cycle hardware multiplier z Micro Trace Buffer (MTB) z Memories z 768(1)/256/128/64KB in-system self-programmable Flash z 32/16/8KB SRAM z System z Power-on reset (POR) and brown-out detection (BOD) z Internal and external clock options with 48MHz Digital Frequency Locked Loop (DFLL48M) and 48MHz to 96MHz Fractional Digital Phase Locked Loop (FDPLL96M) z External Interrupt Controller (EIC) z Up to 15 external interrupts z One non-maskable interrupt z Two-pin Serial Wire Debug (SWD) programming, test and debugging interface z Low Power z Idle and standby sleep modes z SleepWalking peripherals z Peripherals z 12-channel Direct Memory Access Controller (DMAC) z 12-channel Event System z Integrated Ultra Low Power Transceiver for 2.4GHz ISM Band z Supported PSDU Data rates: 250kb/s, 500kb/s, 1000kb/s and 2000kb/s(2) z -99dBm RX Sensitivity; TX Output Power up to +4dBm z Hardware Assisted MAC (Auto-Acknowledge, Auto-Retry) z SFD-Detection; Spreading; De-Spreading; Framing; CRC-16 Computation z Antenna Diversity and TX/RX Control z 128 Byte TX/RX Frame Buffer z Integrated 16MHz Crystal Oscillator (external crystal needed) z PLL synthesizer with 5 MHz and 500 kHz channel spacing for 2.4GHz ISM band z Hardware Security (AES, True Random Generator) z Three 16-bit Timer/Counters (TC), configurable as either: z One 16-bit TC with compare/capture channels z One 8-bit TC with compare/capture channels z One 32-bit TC with compare/capture channels, by using two TCs z Three 16-bit Timer/Counters for Control (TCC), with extended functions: z Up to four compare channels with optional complementary output z Generation of synchronized pulse width modulation (PWM) pattern across port pins z Deterministic fault protection, fast decay and configurable dead-time between complementary output z Dithering that increase resolution with up to 5 bit and reduce quantization error z 32-bit Real Time Counter (RTC) with clock/calendar function z Watchdog Timer (WDT) z CRC-32 generator z One full-speed (12Mbps) Universal Serial Bus (USB) 2.0 interface z Embedded host and device function z Eight endpoints z Up to five Serial Communication Interfaces (SERCOM), each configurable to operate as either: z USART with full-duplex and single-wire half-duplex configuration z I2C up to 3.4MHz z SPI z LIN slave z One 12-bit, 350ksps Analog-to-Digital Converter (ADC) with up to eight external channels z Differential and single-ended input z 1/2x to 16x programmable gain stage z Automatic offset and gain error compensation z Oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution z Two Analog Comparators (AC) with window compare function z Peripheral Touch Controller (PTC) z 48-channel capacitive touch and proximity sensing z I/O and Package z 16/28 programmable I/O pins z 32-pin and 48-pin QFN Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 2 z Operating Voltage z 1.8V - 3.6V z Temperature Range z -40C to 85C Industrial z -40C to 125C Industrial Notes: 1. 2. Only applicable for SAM R21E19: 256KB embedded + 512KB serial Flash. High data rates (500kb/s, 1000kb/s and 2000kb/s) only applicable for T=-40C to 85C. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 3 1. Configuration Summary SAM R21G SAM R21E Pins 48 32 General Purpose I/O-pins (GPIOs) 28 16 Flash 256/128/64KB 256/128/64KB SRAM 32/16/8KB 32/16/8KB Timer Counter (TC) instances 3 3 Waveform output channels per TC instance 2 2 Timer Counter for Control (TCC) instances 3 3 4/4/2 4/4/2 DMA channels 12 12 USB interface 1 1 5+1(1) 4+1(1) No No Analog-to-Digital Converter (ADC) channels 8 4 Analog Comparators (AC) 2 2 Digital-to-Analog Converter (DAC) channels No No Real-Time Counter (RTC) Yes Yes 1 1 1 32-bit value or 2 16-bit values 1 32-bit value or 2 16-bit values External Interrupt lines 15 14 Peripheral Touch Controller (PTC) X and Y lines 8x6 6x2 Waveform output channels per TCC Serial Communication Interface (SERCOM) instances Inter-IC Sound (I2S) interface RTC alarms RTC compare values Maximum CPU frequency 48MHz Packages QFN QFN 32.768kHz crystal oscillator (XOSC32K) Yes No Oscillators 16MHz crystal oscillator for 2.4GHz TRX (XOSCRF) 0.4-32MHz crystal oscillator (XOSC) 32.768kHz internal oscillator (OSC32K) 32kHz ultra-low-power internal oscillator (OSCULP32K) 8MHz high-accuracy internal oscillator (OSC8M) 48MHz Digital Frequency Locked Loop (DFLL48M) 96MHz Fractional Digital Phased Locked Loop (FDPLL96M) Event System channels 12 12 SW Debug Interface Yes Yes Watchdog Timer (WDT) Yes Yes Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 4 Note: 1. SERCOM4 is internally connected to the AT86RF233. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 5 2. Ordering Information ATSAMR 21 E 16 A - M U T Product Family Package Carrier SAMR = SoC Microcontroller with RF No character = Tray (Default) T = Tape and Reel Product Series 21 = Cortex M0+ CPU, USB Package Grade U = -40 - 85C Matte Sn Plating F = -40 - 125C Matte Sn Plating Pin Count E = 32 Pins G = 48 Pins Package Type Flash Memory M = QFN 19 = 256KB + 512KB 18 = 256KB 17 = 128KB 16 = 64KB Device Variant A = Default Variant 2.1 SAM R21E Ordering Code FLASH (bytes) SRAM (bytes) Package ATSAMR21E16A-MF ATSAMR21E16A-MFT ATSAMR21E16A-MU Tray 64K 8K QFN32 ATSAMR21E16A-MUT ATSAMR21E17A-MU 128K 16K QFN32 ATSAMR21E19A-MFT Note: 1. Tray Tray 256K 32K QFN32 ATSAMR21E18A-MUT ATSAMR21E19A-MF Tape & Reel Tape & Reel ATSAMR21E18A-MF ATSAMR21E18A-MU Tray Tray ATSAMR21E17A-MUT ATSAMR21E18A-MFT Tape & Reel Tape & Reel ATSAMR21E17A-MF ATSAMR21E17A-MFT Carrier Type Tape & Reel Tray Tape & Reel 256K + 512K(1) 32K QFN32 Tray Tape & Reel Serial Flash MX25V4006EWSK. For more information, see http://www.macronix.com. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 6 2.2 SAM R21G Ordering Code FLASH (bytes) SRAM (bytes) Package ATSAMR21G16A-MF ATSAMR21G16A-MFT ATSAMR21G16A-MU Tray 64K 8K QFN48 ATSAMR21G16A-MUT ATSAMR21G17A-MU 128K 16K QFN48 ATSAMR21G18A-MUT Tape & Reel Tray Tape & Reel ATSAMR21G18A-MF ATSAMR21G18A-MU Tray Tray ATSAMR21G17A-MUT ATSAMR21G18A-MFT Tape & Reel Tape & Reel ATSAMR21G17A-MF ATSAMR21G17A-MFT Carrier Type Tray 256K 32K QFN48 Tape & Reel Tray Tape & Reel Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 7 Block Diagrams 3.1 MCU Block Diagram SWCLK CORTEX-M0+ PROCESSOR Fmax 48 MHz SERIAL WIRE SWDIO MEMORY TRACE BUFFER IOBUS DEVICE SERVICE UNIT M 256/128/64KB NVM 32/16/8KB RAM NVM CONTROLLER Cache SRAM CONTROLLER M S S S AHB-APB BRIDGE B S AHB-APB BRIDGE A DMA 5x 6 SERCOM x SERCOM OSCULP32K OSC32K XOSC32K 3 x TIMER / COUNTER 8 x Timer Counter FDPLL96M POWER MANAGER CLOCK CONTROLLER RESETN RESET CONTROLLER SLEEP CONTROLLER GENERIC CLOCK CONTROLLER (3) GCLK_IO[n] REAL TIME COUNTER WATCHDOG TIMER EXTINT[15..1] NMI DMA EVENT SYSTEM XOSC PAD0 PAD1 PAD2 PAD3 DMA OSC8M DFLL48M XIN XOUT DM SOF 1KHZ PERIPHERAL ACCESS CONTROLLER VREF (4) XIN32 XOUT32 DP AHB-APB BRIDGE C SYSTEM CONTROLLER PORT USB FS DEVICE MINI-HOST S PERIPHERAL ACCESS CONTROLLER BOD33 DMA M HIGH SPEED BUS MATRIX PERIPHERAL ACCESS CONTROLLER S 3x TIMER / COUNTER FOR CONTROL DMA 8-CHANNEL 12-bit ADC 350KSPS 2 ANALOG COMPARATORS PERIPHERAL TOUCH CONTROLLER WO0 WO1 PORT 3. WO0 WO1 (2) WOn AIN[n] (3) VREFB AIN[3..0] X[7..0] Y[5..0] EXTERNAL INTERRUPT CONTROLLER Notes: 1. Some products have different number of SERCOM instances, Timer/Counter instances, PTC signals and ADC signals. Refer to "Ordering Information" on page 6 for details. 2. The three TCC instances have different configurations, including the number of Waveform Output (WO) lines. Refer to "Peripherals Configuration Summary" on page 43 for details. 3. Refer to the PORT Function Multiplexing Table 5-1 for details about the available GCLK_IO and ADC signals. 4. Only available for SAM R21G. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 8 SAM R21 Interconnection PA08 PA09 GNDANA RFP RFP FECTRL0..1 AVSS RFN GNDANA AVSS PA12(2) PA13(2) PA14 PA15 RFN 2.4 GHz RF front-end circuit FECTRL2..5 DIG3 2.4GHz TRX (analog) DIG4 (1) DVSS AVSS DVDD DVDD DVREG AVREG TRX (digital) DEVDD VDDIO GNDANA AVDD AVDD EVDD VDDANA DIG1 AVSS Control Logic DIG2 /SEL IRQ PB31 PB00 PAD1 MOSI PB30 PAD2 MISO PAD0 GENERIC CLOCK PC19 SCLK PC18 GCLK_IO1(4) PAD3 CLKM PC16 PA20 PB15 XOSC RF SPI (Slave) SLP_TR PORT GNDANA XTAL1 RSTN SERCOM 4(3) DIG1..4 EXTINT0 XTAL1 XTAL2 XTAL2 AT86RF233 ADC AC EXTERNAL INTERRUPT CONTROLLER RFCTRL PTC Notes: PAD3 XOSC 32K SAMD21 SCLK PB23 PAD2 PB22 SO CS# SI PA22 PA12 WP# GND PA00 VCC HOLD# VDDIN VDDCORE (1) PAD1 SERCOM 5 PA23 PORT PAD0 VREG GND 3.2 MX25V4006(5) SAMR21 1. Paddle connected to digital ground DVSS, GND. 2. Only available for SAM R21G. 3. Dedicated SERCOM4 alternate pin function mapping for internally connected AT86RF233. 4. Die revision A uses GCLK_IO5. 5. Only available for SAM R21E19. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 9 Pinout 4.1 SAM R21G - QFN48 48 47 46 45 44 43 42 41 40 39 38 37 PB03 PB02 PA31 PA30 VDDIN VDDCORE GND PA28 RESET PA27 PB23 PB22 4. 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 VDDIO GND PA25 PA24 PA23 PA22 DVDD GND PA19 PA18 PA17 PA16 VDDIO GND PA08 PA09 GNDANA RFP RFN GNDANA PA12 PA13 PA14 PA15 13 14 15 16 17 18 19 20 21 22 23 24 PA00 PA01 XTAL2 XTAL1 GNDANA VDDANA AVDD GNDANA PA04 PA05 PA06 PA07 OSCILLATOR GROUND INPUT SUPPLY REGULATED OUTPUT SUPPLY RESET PIN Note: RF PIN DIGITAL PIN ANALOG PIN DIGITAL PIN/ OSCILLATOR The large center pad underneath the QFN package is made of metal and internally connected to GND. It should be soldered and connected to the digital ground on the board to ensure good mechanical stability. It is not recommended to use the exposed paddle as a replacement of the regular GND pin. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 10 SAM R21E - QFN32 32 31 30 29 28 27 26 25 PA31 PA30 VDDIN VDDCORE GND PA28 RESET PA27 4.2 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 VDDIO PA25 PA24 DVDD PA19 PA18 PA17 PA16 OSCILLATOR GROUND PA08 PA09 GNDANA RFP RFN GNDANA PA14 PA15 9 10 11 12 13 14 15 16 XTAL2 XTAL1 GNDANA VDDANA AVDD GNDANA PA06 PA07 INPUT SUPPLY RESET PIN REGULATED OUTPUT SUPPLY Note: RF PIN DIGITAL PIN ANALOG PIN DIGITAL PIN/ OSCILLATOR The large center pad underneath the QFN package is made of metal and internally connected to GND. It should be soldered and connected to the digital ground on the board to ensure good mechanical stability. It is not recommended to use the exposed paddle as a replacement of the regular GND pin. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 11 5. I/O Multiplexing and Considerations 5.1 Multiplexed Signals Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned to one of the peripheral functions A, B, C, D, E, F, G or H. To enable a peripheral function on a pin, the Peripheral Multiplexer Enable bit in the Pin Configuration register corresponding to that pin (PINCFGn.PMUXEN, n = 0..31) in the PORT must be written to one. The selection of peripheral function A to H is done by writing to the Peripheral Multiplexing Odd and Even bits in the Peripheral Multiplexing register (PMUXn.PMUXE/O) in the PORT. Table 5-1 describes the peripheral signals multiplexed to the PORT I/O pins. Table 5-1. PORT Function Multiplexing Pin A SAMR21 SAMR21 E G I/O Pin Supply Type EIC B(1)(2) REF ADC C AC PTC D SERCOM SERCOM(1)(2) ALT E F G H TC TCC FECTRL TCC SERCOM COM AC/ GCLK SERCOM1/ TCC2/WO[0] PAD[0] 1 PA00 VDDANA 2 PA01 VDDANA EXTINT[1] 9 PA04 VDDANA EXTINT[4] 10 PA05 VDDANA 7 11 8 SERCOM1/ TCC2/WO[1] PAD[1] ADC/ VREFB AIN[4] AIN[0] Y[2] SERCOM0/ TCC0/WO[0] PAD[0] EXTINT[5] AIN[5] AIN[1] Y[3] SERCOM0/ TCC0/WO[1] PAD[1] PA06 VDDANA EXTINT[6] AIN[6] AIN[2] Y[4] SERCOM0/ TCC1/WO[0] PAD[2] 12 PA07 VDDANA EXTINT[7] AIN[7] AIN[3] Y[5] SERCOM0/ TCC1/WO[1] PAD[3] 9 15 PA08 VDDIO I2C NMI AIN[16] X[0] SERCOM0/ SERCOM2/ TCC0/WO[0] FECTRL[0] PAD[0] PAD[0] 10 16 PA09 VDDIO I2C EXTINT[9] AIN[17] X[1] SERCOM0/ SERCOM2/ TCC0/WO[1] FECTRL[1] PAD[1] PAD[1] 21 PA12 VDDIO I2C EXTINT[12] SERCOM2/ PAD[0] TCC2/WO[0] FECTRL[2] AC/ CMP[0] 22 PA13 VDDIO I2C EXTINT[13] SERCOM2/ PAD[1] TCC2/WO[1] FECTRL[3] AC/ CMP[1] 15 23 PA14 VDDIO EXTINT[14] SERCOM2/ PAD[2] TC3/WO[0] FECTRL[4] GCLK_IO[0] 16 24 PA15 VDDIO EXTINT[15] SERCOM2/ PAD[3] TC3/WO[1] FECTRL[5] GCLK_IO[1] 17 25 PA16 VDDIO I2C 18 26 PA17 VDDIO I2C 19 27 PA18 20 28 X[4] SERCOM1/ SERCOM3/ TCC2/WO[0] PAD[0] PAD[0] TCC0/ WO[0] GCLK_IO[2] EXTINT[1] X[5] SERCOM1/ SERCOM3/ TCC2/WO[1] PAD[1] PAD[1] TCC0/ WO[1] GCLK_IO[3] VDDIO EXTINT[2] X[6] SERCOM1/ SERCOM3/ PAD[2] PAD[2] TC3/WO[0] TCC0/ WO[2] AC/ CMP[0] PA19 VDDIO EXTINT[3] X[7] SERCOM1/ SERCOM3/ PAD[3] PAD[3] TC3/WO[1] TCC0/ WO[3] AC/ CMP[1] 31 PA22 VDDIO I2C EXTINT[6] X[10] SERCOM3/ SERCOM5/ PAD[0] PAD[0] TC4/WO[0] TCC0/ WO[4] GCLK_IO[6] 32 PA23 VDDIO I2C EXTINT[7] X[11] SERCOM3/ SERCOM5/ PAD[1] PAD[1] TC4/WO[1] TCC0/ WO[5] USB/ GCLK_IO[7] SOF1kHz 22 33 PA24 VDDIO EXTINT[12] SERCOM3/ SERCOM5/ PAD[2] PAD[2] TC5/WO[0] TCC1/ WO[2] USB_DM 23 34 PA25 VDDIO EXTINT[13] SERCOM3/ SERCOM5/ PAD[3] PAD[3] TC5/WO[1] TCC1/ WO[3] USB_DP Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 12 Table 5-1. PORT Function Multiplexing (Continued) Pin A SAMR21 SAMR21 E G I/O Pin Supply Type EIC B(1)(2) REF ADC C AC D SERCOM SERCOM(1)(2) ALT PTC E F G H TC TCC FECTRL TCC SERCOM COM AC/ GCLK 37 PB22 VDDIO EXTINT[6] SERCOM5/ PAD[2] GCLK_IO[0] 38 PB23 VDDIO EXTINT[7] SERCOM5/ PAD[3] GCLK_IO[1] 25 39 PA27 VDDIO EXTINT[15] SERCOM3/ PAD[0] GCLK_IO[0] 27 41 PA28 VDDIO EXTINT[8] SERCOM3/ PAD[1] GCLK_IO[0] 31 45 PA30 VDDIO EXTINT[10] SERCOM1/ TCC1/WO[0] PAD[2] SWCLK 32 46 PA31 VDDIO EXTINT[11] SERCOM1/ TCC1/WO[1] PAD[3] SWDIO(3) 47 PB02 VDDANA EXTINT[2] AIN[10] Y[8] SERCOM5/ PAD[0] 48 PB03 VDDANA EXTINT[3] AIN[11] Y[9] SERCOM5/ PAD[1] Notes: 1. 2. 3. 5.2 GCLK_IO[0] All analog pin functions are on peripheral function B. Peripheral function B must be selected to disable the digital control of the pin. Only some pins can be used in SERCOM I2C mode. See the Type column for using a SERCOM pin in I2C mode. Refer to "Electrical Characteristics" on page 1055 for details on the I2C pin characteristics. This function is only activated in the presence of a debugger. Internal Multiplexed Signals PA20, PB00, PB15, PB30, PB31, PC16, PC18 and PC19 are by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned to one of the peripheral functions A, B, C, D, E, F, G or H. To enable a peripheral function on a pin, the Peripheral Multiplexer Enable bit in the Pin Configuration register corresponding to that pin (PINCFGn.PMUXEN, n = 0-31) in the PORT must be written to one. The selection of peripheral function A to H is done by writing to the Peripheral Multiplexing Odd and Even bits in the Peripheral Multiplexing register (PMUXn.PMUXE/O) in the PORT. PA10, PA11, PB16 and PB17 cannot be configured as output ports. These ports are always connected to the RFCTRL inputs. A B C D SERCOM SERCOMALT E F G H TC FECTRL TCC SERCOM COM AC/ GCLK Internal Signal I/O Pin Supply Type EIC DIG3 PA10 VDDIO Input EXTINT[10] DIG4 PA11 VDDIO Input EXTINT[11] SLP_TR PA20 VDDIO I/O IRQ PB00 VDDANA I/O RSTN PB15 VDDIO I/O DIG1 PB16 VDDIO Input EXTINT[0] DIG2 PB17 VDDIO Input EXTINT[1] MOSI PB30 VDDIO I/O SERCOM4/ PAD[2] SEL PB31 VDDIO I/O SERCOM4/ PAD[1] REF ADC AC PTC EXTINT[0] Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 13 A Internal Signal B SERCOM H TC FECTRL TCC SERCOM COM AC/ GCLK PC16 VDDIO I/O GCLK/ IO[1](1) SCLK PC18 VDDIO I/O SERCOM4/ PAD[3] MISO PC19 VDDIO I/O SERCOM4/ PAD[0] 5.3.1 Oscillator Pinout PTC G CLKM Other Functions AC F I/O Pin 5.3 ADC SERCOMALT E Type 1. REF D Supply Note: EIC C Die revision A uses GCLK/IO[5]. The oscillators are not mapped to the normal PORT functions and their multiplexing are controlled by registers in the System Controller (SYSCTRL). Refer to "SYSCTRL - System Controller" on page 143 for more information. Oscillator Supply XOSC VDDIO XOSC32K VDDANA Signal I/O Pin XIN PA14 XOUT PA15 XIN32 PA00 XOUT32 PA01 The integrated AT86RF233 16 MHz crystal oscillator is directly connected to pins and has no multiplexing functionality. Oscillator XOSCRF 5.3.2 Supply EVDD/VDDANA Signal I/O Pin XTAL1 XTAL1 XTAL2 XTAL2 Serial Wire Debug Interface Pinout Only the SWCLK pin is mapped to the normal PORT functions. A debugger cold-plugging or hot-plugging detection will automatically switch the SWDIO port to the SWDIO function. Refer to "DSU - Device Service Unit" on page 45 for more information. Signal Supply I/O Pin SWCLK VDDIO PA30 SWDIO VDDIO PA31 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 14 5.3.3 General Circuit Description The Atmel AT86RF233 single-chip radio transceiver provides a complete radio transceiver interface between an antenna and the SAM D21 microcontroller. It comprises the analog radio, digital modulation and demodulation including time and frequency synchronization, as well as data buffering. A single 128-byte TRX buffer stores receive or transmit data. Communication between transmitter and receiver is based on direct sequence spread spectrum with different modulation schemes and spreading codes. The AT86RF233 block diagram is shown in Figure 5-1. Figure 5-1. AT86RF233 Block Diagram ext. PA and Power Control DIG3/4 PA XOSCRF PLL AVREG Configuration Registers TX Data TX BBP /SEL DVREG SPI (Slave) RFP Frame Buffer FTN, BATMON MISO MOSI SCLK RFN LNA PPF BPF Limiter ADC RX BBP AES IRQ CLKM DIG2 AGC AD DIG1/2 Analog Domain /RST RSSI Control Logic SLP_TR Antenna Diversity Digital Domain The number of external components is minimized such that only the antenna, the crystal and decoupling capacitors are required. The bidirectional differential antenna pins (RFP, RFN) are used for transmission and reception, thus no external antenna switch is needed. Control of an external power amplifier is supported by two digital control signals (differential operation). The received RF signal at SAM R21 pin 13/19 (RFN) and pin 12/18 (RFP) is differentially fed through the low-noise amplifier (LNA) to the RF filter (PPF) to generate a complex signal, driving the integrated channel filter (BPF). The limiting amplifier provides sufficient gain to drive the succeeding analog-to-digital converter (ADC) and generates a digital RSSI signal. The ADC output signal is sampled by the digital base band receiver (RX BBP). The transmit modulation scheme is offset-QPSK (O-QPSK) with half-sine pulse shaping and 32-length block coding (spreading) according to [1], [2] and [3]. The modulation signal is generated in the digital transmitter (TX BBP) and applied to the fractional-N frequency synthesis (PLL), to ensure the coherent phase modulation required for demodulation of O-QPSK signals. The frequency-modulated signal is fed to the power amplifier (PA). Two on-chip low-dropout voltage regulators (A|DVREG) provide regulated analog and digital 1.8V supply outputs. An internal 128-byte RAM for RX and TX (Frame Buffer) buffers the data to be transmitted or the received data. The configuration of the internal AT86RF233, reading and writing of Frame Buffer is controlled by the SPI interface and additional control lines. The AT86RF233 further contains comprehensive hardware-MAC support (Extended Operating Mode) and a security engine (AES) to improve the overall system power efficiency and timing. The stand-alone 128-bit AES engine can be Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 15 accessed in parallel to all PHY operational transactions and states using the SPI interface, except during SLEEP and DEEP_SLEEP states. For long-range applications or to improve the reliability of a RF connection the RF performance can further be improved by using an external RF front-end or Antenna Diversity. Both operation modes are supported by the AT86RF233 with dedicated control signals DIG1, ..., DIG4 which can be activated as alternate pin output functions FECTRL[0..5] by the integrated microcontroller. Additional features of the Extended Feature Set, see "AT86RF233 Extended Feature Set" on page 1005, are provided to simplify the interaction between radio transceiver and microcontroller. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 16 5.4 Analog and RF Pins 5.4.1 Supply and Ground Pins 5.4.1.1 EVDD, DEVDD EVDD and DEVDD are analog and digital supply voltage pins of the AT86RF233 radio transceiver. 5.4.1.2 AVDD, DVDD AVDD and DVDD are outputs of the internal voltage regulators and require bypass capacitors for stable operation. The voltage regulators are controlled independently by the radio transceivers state machine and are activated depending on the current radio transceiver state. The voltage regulators can be configured for external supply; for details, refer to "Voltage Regulators (AVREG, DVREG)" on page 983. 5.4.1.3 AVSS, DVSS AVSS and DVSS are analog and digital ground pins respectively. The analog and digital power domains should be separated on the PCB. 5.4.2 RF Pins 5.4.2.1 RFN, RFP A differential RF port (RFP/RFN) provides common-mode rejection to suppress the switching noise of the internal digital signal processing blocks. At board-level, the differential RF layout ensures high receiver sensitivity by reducing spurious emissions originated from other digital ICs such as a microcontroller. The RF port is designed for a 100 differential load. A DC path between the RF pins is allowed; a DC path to ground or supply voltage is not allowed. A simplified schematic of the RF front end is shown in Figure 5-2. Figure 5-2. Simplified RF Front-end Schematic. 3&% $7 5) 9 0 /1$ 5; 3$ 7; &0 )HHGEDFN 5;7; The RF port DC values depend on the operating state; refer to "AT86RF233 Operating Modes" on page 902. In TRX_OFF state, when the analog front-end is disabled (see "TRX_OFF - Clock State" on page 904), the RF pins are pulled to ground, preventing a floating voltage larger than 1.8V which is not allowed for the internal circuitry. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 17 In transmit mode, a control loop provides a common-mode voltage of 0.9V. Transistor M0 is off, allowing the PA to set the common-mode voltage. The common-mode capacitance at each pin to ground shall be < 30pF to ensure the stability of this common-mode feedback loop. In receive mode, the RF port provides a low-impedance path to ground when transistor M0, (see Figure 5-2) pulls the inductor center tap to ground. A DC voltage drop of 20mV across the on-chip inductor can be measured at the RF pins. 5.4.3 Crystal Oscillator Pins 5.4.3.1 XTAL1, XTAL2 The pin 2/4 (XTAL1) of SAM R21 is the input of the reference oscillator amplifier (XOSCRF), the pin 1/3 (XTAL2) is the output. A detailed description of the crystal oscillator setup and the related XTAL1/XTAL2 pin configuration can be found in "Crystal Oscillator (XOSCRF)" on page 989. When using an external clock reference signal, XTAL1 shall be used as input pin. For further details, refer to "External Reference Frequency Setup" on page 990. 5.4.4 Analog Pin Summary Table 5-2. Analog Pin Behavior - DC values Pin RFP/RFN Values and Conditions Description VDC = 0.9V (BUSY_TX) DC level at pins RFP/RFN for various transceiver states. VDC = 20mV (receive states) AC coupling is required if a circuitry with a DC path to ground or supply is used. Serial capacitance and capacitance of each pin to ground must be < 30pF. VDC = 0mV (otherwise) XTAL1/XTAL2 DVDD VDC = 0.9V at both pins CPAR = 3pF Parasitic capacitance (CPAR) of the pins must be considered as additional load capacitance to the crystal. VDC = 1.8V (all states, except SLEEP and DEEP_SLEEP) DC level at pin DVDD for various transceiver states. VDC = 0mV (DEEP_SLEEP) Supply pins (voltage regulator output) for the digital 1.8V voltage domain. The outputs shall be bypassed by 100nF. VDC = 1.5V (SLEEP) AVDD VDC = 1.8V (all states, except P_ON, SLEEP, DEEP_SLEEP, RESET, and TRX_OFF) VDC = 0mV (otherwise) 5.5 DC level at pins XTAL1/XTAL2 for various transceiver states. DC level at pin AVDD for various transceiver states. Supply pin (voltage regulator output) for the analog 1.8V voltage domain. The outputs shall be bypassed by 100nF. Digital I/O Signals The AT86RF233 provides a digital microcontroller interface. The interface comprises a slave SPI (/SEL, SCLK, MOSI, and MISO) and additional control signals (CLKM, IRQ, SLP_TR, /RST, and DIG2). The microcontroller interface is described in detail in "AT86RF233 Microcontroller Interface" on page 883. Additional digital output signals DIG1, ..., DIG4 are provided to control external blocks, that is for Antenna Diversity RF switch control or as an RX/TX Indicator, see "Antenna Diversity" on page 1020 and "RX/TX Indicator" on page 1025 respectively. 5.5.1 Driver Strength Settings The driver strength of all digital output signals (MISO, IRQ, DIG1,..., DIG4 and CLKM) to the microcontroller are fixed. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 18 5.5.2 Pull-up and Pull-down Configuration Pulling transistors are internally connected to all digital inputs from the microcontroller in radio transceiver states P_ON (including reset during P_ON) and DEEP_SLEEP, refer to "P_ON - Power-On after VDD" on page 903 and "DEEP_SLEEP - Deep Sleep State" on page 904. Table 5-3 summarizes the pull-up and pull-down configuration. Table 5-3. Note: 1. Pull-Up / Pull-Down Configuration of Digital Input Signals from the Microcontroller Signal H = pull-up, L = pull-down /RST H /SEL H SCLK L MOSI L SLP_TR(1)) L Except SLP_TR pin for DEEP_SLEEP state. In all other radio transceiver states, including RESET, no pull-up or pull-down transistors are connected to any of the digital inputs mentioned in Table 5-3. In all other states, external circuitry should guaranty defined levels at all input pins. Floating input signals may cause unexpected functionality and increased power consumption, for example in SLEEP state. If the additional digital output signals DIG1, ..., DIG4 are not activated, they are pulled-down to digital ground (DIG1/DIG2) or analog ground (DIG3/DIG4). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 19 ADC VDDIN GND VDDIO Power Domain Overview VDDCORE 6.1 GNDANA Power Supply and Start-Up Considerations VDDANA 6. VOLTAGE REGULATOR PB[31:10] OSC8M PA[13:8] BOD12 XOSC PA[7:4] PA[15:14] AC PA[31:16] PB[3:2] PTC Digital Logic (CPU, peripherals) PA[1:0] XOSC32K POR DFLL48M OSC32K OSCULP32K 6.2 Power Supply Considerations 6.2.1 Power Supplies FDPLL96M BOD33 The Atmel(R) SAM R21 has several different power supply pins: z VDDIO: Powers I/O lines, OSC8M and XOSC. Voltage is 1.8V to 3.6V. z VDDIN: Powers I/O lines, the internal regulator and the stacked 512KB serial Flash. Voltage is 1.8V to 3.6V. z VDDANA: Powers I/O lines and the ADC, AC, PTC, OSCULP32K, OSC32K, XOSC32K. Voltage is 1.8V to 3.6V. z VDDCORE: Internal regulated voltage output. Powers the core, memories, peripherals, DFLL48M and FDPLL96M. Voltage is 1.2V. The same voltage must be applied to both VDDIN, VDDIO and VDDANA. This common voltage is referred to as VDD in the datasheet. The ground pins, GND, are common to VDDCORE, VDDIO and VDDIN. The ground pin for VDDANA is GNDANA. For decoupling recommendations for the different power supplies, refer to the schematic checklist. Refer to "Schematic Checklist" on page 1112 for details. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 20 6.2.2 Voltage Regulator The SAM R21 voltage regulator has two different modes: 6.2.3 z Normal mode: To be used when the CPU and peripherals are running z Low Power (LP) mode: To be used when the regulator draws small static current. It can be used in standby mode Typical Powering Schematics The SAM R21 uses a single supply from 1.8V to 3.6V. The following figure shows the recommended power supply connection. Figure 6-1. Power Supply Connection SAM R21 Main Supply (1.8V -- 3.6V) VDDIO VDDANA VDDIN VDDCORE GND DVDD GNDANA AVDD 6.2.4 Power-Up Sequence 6.2.4.1 Minimum Rise Rate The integrated power-on reset (POR) circuitry monitoring the VDDANA power supply requires a minimum rise rate. Refer to the "Electrical Characteristics" on page 1055 for details. 6.2.4.2 Maximum Rise Rate The rise rate of the power supply must not exceed the values described in Electrical Characteristics. Refer to the "Electrical Characteristics" on page 1055 for details. 6.3 Power-Up This section summarizes the power-up sequence of the SAM R21. The behavior after power-up is controlled by the Power Manager. Refer to "PM - Power Manager" on page 112 for details. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 21 6.3.1 Starting of Clocks After power-up, the device is set to its initial state and kept in reset, until the power has stabilized throughout the device. Once the power has stabilized, the device will use a 1MHz clock. This clock is derived from the 8MHz Internal Oscillator (OSC8M), which is divided by eight and used as a clock source for generic clock generator 0. Generic clock generator 0 is the main clock for the Power Manager (PM). Some synchronous system clocks are active, allowing software execution. Refer to the "Clock Mask Register" section in "PM - Power Manager" on page 112 for the list of default peripheral clocks running. Synchronous system clocks that are running are by default not divided and receive a 1MHz clock through generic clock generator 0. Other generic clocks are disabled except GCLK_WDT, which is used by the Watchdog Timer (WDT). 6.3.2 I/O Pins After power-up, the I/O pins are tri-stated. 6.3.3 Fetching of Initial Instructions After reset has been released, the CPU starts fetching PC and SP values from the reset address, which is 0x00000000. This address points to the first executable address in the internal flash. The code read from the internal flash is free to configure the clock system and clock sources. Refer to "PM - Power Manager" on page 112, "GCLK - Generic Clock Controller" on page 90 and "SYSCTRL - System Controller" on page 143 for details. Refer to the ARM Architecture Reference Manual for more information on CPU startup (http://www.arm.com). 6.4 Power-On Reset and Brown-Out Detector The SAM R21 embeds three features to monitor, warn and/or reset the device: 6.4.1 z POR: Power-on reset on VDDANA z BOD33: Brown-out detector on VDDANA z BOD12: Voltage Regulator Internal Brown-out detector on VDDCORE. The Voltage Regulator Internal BOD is calibrated in production and its calibration configuration is stored in the NVM User Row. This configuration should not be changed if the user row is written to assure the correct behavior of the BOD12. Power-On Reset on VDDANA POR monitors VDDANA. It is always activated and monitors voltage at startup and also during all the sleep modes. If VDDANA goes below the threshold voltage, the entire chip is reset. 6.4.2 Brown-Out Detector on VDDANA BOD33 monitors VDDANA. Refer to "SYSCTRL - System Controller" on page 143 for details. 6.4.3 Brown-Out Detector on VDDCORE Once the device has started up, BOD12 monitors the internal VDDCORE. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 22 7. Product Mapping Figure 7-1. Atmel | SMART SAM R21 Product Mapping Global Memory Space 0x00000000 Code 0x00000000 Internal Flash Code 0x20000000 AHB-APB Bridge C 0x00400000 0x42000000 Reserved SRAM PAC2 0x42000400 0x1FFFFFFF 0x22008000 EVSYS Undefined 0x40000000 0x42000800 SRAM SERCOM0 0x42000C00 0x20000000 Peripherals SERCOM1 Internal SRAM 0x42001000 SERCOM2 0x20008000 0x43000000 0x42001400 SERCOM3 Reserved 0x60000000 AHB-APB 0x42001800 SERCOM4 0x40000000 0x60000200 0x42001C00 AHB-APB Bridge A Undefined SERCOM5 0x42002000 TCC0 0x41000000 AHB-APB Bridge B Reserved (1) 0x42002400 TCC1 0x42002800 0xFFFFFFFF 0x42000000 TCC2 AHB-APB Bridge C 0x42002C00 TC3 0x42FFFFFF 0x42003000 TC4 0x42003400 AHB-APB Bridge A 0x41002000 0x41004000 0x41004400 0x41004800 0x41005000 0x41006000 PTC 0x42005000 MTB EIC Reserved Reserved 0x42005400 0x41004700 0x40001C00 Reserved 0x42004C00 USB RTC 0x40001800 AC 0x42004800 DMAC WDT 0x40001400 ADC 0x42004400 PORT GCLK 0x40001000 Reserved 0x42004000 NVMCTRL SYSCTRL 0x40000C00 Reserved 0x42003C00 DSU PM 0x40000800 0x40FFFFFF 0x42003800 PAC1 PAC0 0x40000400 TC5 AHB-APB Bridge B 0x41000000 0x40000000 Reserved 0x41FFFFFF RFCTRL 0x42005800 Reserved Note 1. SERCOM4 is internally connected to the AT86RF233. 0x40FFFFFF This figure represents the full configuration of the Atmel | SMART SAM R21 with maximum Flash and SRAM capabilities and a full set of peripherals. Refer to the "Configuration Summary" on page 4 for details. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 23 8. Memories 8.1 Embedded Memories 8.2 z Internal high-speed flash z Internal high-speed RAM, single-cycle access at full speed z Stacked 512KB serial Flash (SAMR21E19A) Physical Memory Map The High-Speed bus is implemented as a bus matrix. All High-Speed bus addresses are fixed, and they are never remapped in any way, even during boot. The 32-bit physical address space is mapped as follow: Table 8-1. SAM R21 physical memory map(1) Size Memory Start address SAMR21x19 SAMR21x18 SAMR21x17 SAMR21x16 Embedded Flash 0x00000000 256Kbytes 256Kbytes 128Kbytes 64Kbytes Embedded SRAM 0x20000000 32Kbytes 32Kbytes 16Kbytes 8Kbytes Peripheral Bridge A 0x40000000 64Kbytes 64Kbytes 64Kbytes 64Kbytes Peripheral Bridge B 0x41000000 64Kbytes 64Kbytes 64Kbytes 64Kbytes Peripheral Bridge C 0x42000000 64Kbytes 64Kbytes 64Kbytes 64Kbytes Note: 1. Table 8-2. x = G or E. Refer to "Ordering Information" on page 6 for details. Flash memory parameters(1) Device Flash size Number of pages Page size SAMR21x19(3) 256Kbytes 4096 64 bytes SAMR21x18 256Kbytes 4096 64 bytes SAMR21x17 128Kbytes 2046 64 bytes SAMR21x16 64Kbytes 1024 64 bytes Note: 1. x = G or E. Refer to "Ordering Information" on page 6 for details. 2. The number of pages (NVMP) and page size (PSZ) can be read from the NVM Pages and Page Size bits in the NVM Parameter register in the NVMCTRL (PARAM.NVMP and PARAM.PSZ, respectively). Refer to PARAM for details. 3. The Flash memory parameters refers to the embedded memories: SAMR21x19 shares same embedded memories as SAMR21x18. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 24 8.3 NVM Calibration and Auxiliary Space The device calibration data are stored in different sections of the NVM calibration and auxiliary space presented in Figure 8-1. Figure 8-1. Calibration and Auxiliary Space AUX1 0x00806040 800000 Calibration and auxiliary space Area 4: Software calibration area (256bits) NVM base address + 0x00800000 0x00806020 Area 4 offset add Area 3: Reserved (128bits) NVM base address + NVM size 0x00806010 NVM main address space 0x00806008 Area 2: Device configuration area (64 bits) Area 2 offset ad Area 1: Reserved (64 bits) 0x00806000 000000 Area 3 offset ad Area 1 address NVM Base Address AUX1 0x00806000 AUX1 offset address 0x00804000 AUX0 - NVM User Row 0x00800000 Automatic calibration row AUX0 offset address Calibration and auxiliary space address offset The values from the automatic calibration row are loaded into their respective registers at startup. 8.3.1 NVM User Row Mapping The NVM User Row contains calibration data that are automatically read at device power on. The NVM User Row can be read at address 0x804000. To write the NVM User Row refer to "NVMCTRL - Non-Volatile Memory Controller" on page 350. Note that when writing to the user row the values do not get loaded by the other modules on the device until a device reset occurs. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 25 Table 8-3. 8.3.2 NVM User Row Mapping Bit Position Name Usage 2:0 BOOTPROT 3 Reserved 6:4 EEPROM 7 Reserved 13:8 BOD33 Level BOD33 Threshold Level at power on. Refer to BOD33 register. Default value = 7. 14 BOD33 Enable BOD33 Enable at power on . Refer to BOD33 register. Default value = 1. 16:15 BOD33 Action BOD33 Action at power on. Refer to BOD33 register. Default value = 1. 24:17 Reserved 25 WDT Enable WDT Enable at power on. Refer to WDT CTRL register. Default value = 0. 26 WDT Always-On WDT Always-On at power on. Refer to WDT CTRL register. Default value = 0. 30:27 WDT Period WDT Period at power on. Refer to WDT CONFIG register. Default value = 0x0B. 34:31 WDT Window WDT Window mode time-out at power on. Refer to WDT CONFIG register. Default value = 0x05. 38:35 WDT EWOFFSET WDT Early Warning Interrupt Time Offset at power on. Refer to WDT EWCTRL register. Default value = 0x0B. 39 WDT WEN WDT Timer Window Mode Enable at power on. Refer to WDT CTRL register. Default value = 0. 40 BOD33 Hysteresis BOD33 Hysteresis configuration at power on. Refer to BOD33 register. Default value = 0. 41 Reserved 47:42 Reserved 63:48 LOCK Used to select one of eight different bootloader sizes. Refer to "NVMCTRL - Non-Volatile Memory Controller" on page 350. Default value = 7. Used to select one of eight different EEPROM sizes. Refer to "NVMCTRL - Non-Volatile Memory Controller" on page 350. Default value = 7. Voltage Regulator Internal BOD (BOD12) configuration. These bits are written in production and must not be changed. Default value = 0x70. Voltage Regulator Internal BOD(BOD12) configuration. This bit is written in production and must not be changed. Default value = 0. NVM Region Lock Bits. Refer to "NVMCTRL - Non-Volatile Memory Controller" on page 350. Default value = 0xFFFF. NVM Software Calibration Area Mapping The NVM Software Calibration Area contains calibration data that are measured and written during production test. These calibration values should be read by the application software and written back to the corresponding register. The NVM Software Calibration Area can be read at address 0x806020. The NVM Software Calibration Area can not be written. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 26 Table 8-4. 8.3.3 NVM Software Calibration Area Mapping Bit Position Name Description 2:0 Reserved 14:3 Reserved 26:15 Reserved 34:27 ADC LINEARITY ADC Linearity Calibration. Should be written to CALIB register. 37:35 ADC BIASCAL ADC Bias Calibration. Should be written to CALIB register. 44:38 OSC32K CAL OSC32KCalibration. Should be written to OSC32K register. 49:45 USB TRANSN USB TRANSN calibration value. Should be written to PADCAL register. 54:50 USB TRANSP USB TRANSP calibration value. Should be written to PADCAL register. 57:55 USB TRIM USB TRIM calibration value. Should be written to the PADCAL register. 63:58 DFLL48M COARSE CAL DFLL48M Coarse calibration value. Should be written to DFLLVAL register. 73:64 DFLL48M FINE CAL DFLL48M Fine calibration value. Should be written to DFLLVAL register. 127:74 Reserved Serial Number Each device has a unique 128-bit serial number which is a concatenation of four 32-bit words contained at the following addresses: Word 0: 0x0080A00C Word 1: 0x0080A040 Word 2: 0x0080A044 Word 3: 0x0080A048 The uniqueness of the serial number is guaranteed only when using all 128 bits. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 27 9. Processor And Architecture 9.1 Cortex M0+ Processor The Atmel | SMART SAM R21 implements the ARM(R) CortexTM-M0+ processor, based on the ARMv6 Architecture and Thumb(R)-2 ISA. The Cortex M0+ is 100% instruction set compatible with its predecessor, the Cortex-M0 core, and upward compatible to Cortex-M3 and M4 cores. The ARM Cortex-M0+ implemented is revision r0p1. For more information refer to www.arm.com. 9.1.1 Cortex M0+ Configuration Table 9-1. Cortex M0+ Configuration Features Configurable option Atmel | SMART SAM R21 configuration Interrupts External interrupts 0-32 28 Data endianness Little-endian or big-endian Little-endian SysTick timer Present or absent Present Number of watchpoint comparators 0, 1, 2 2 Number of breakpoint comparators 0, 1, 2, 3, 4 4 Halting debug support Present or absent Present Multiplier Fast or small Fast (single cycle) Single-cycle I/O port Present or absent Present Wake-up interrupt controller Supported or not supported Not supported Vector Table Offset Register Present or absent Present Unprivileged/Privileged support Present or absent Absent(1) Memory Protection Unit Not present or 8-region Not present Reset all registers Present or absent Absent Instruction fetch width 16-bit only or mostly 32-bit 32-bit Note: 1. All software run in privileged mode only. The ARM Cortex-M0+ core has two bus interfaces: 9.1.2 z Single 32-bit AMBA-3 AHB-Lite system interface that provides connections to peripherals and all system memory, which includes flash and RAM. z Single 32-bit I/O port bus interfacing to the PORT with 1-cycle loads and stores. Cortex-M0+ Peripherals z System Control Space (SCS) z z The processor provides debug through registers in the SCS. Refer to the Cortex-M0+ Technical Reference Manual for details (www.arm.com). System Timer (SysTick) z The System Timer is a 24-bit timer that extends the functionality of both the processor and the NVIC. Refer to the Cortex-M0+ Technical Reference Manual for details (www.arm.com). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 28 z Nested Vectored Interrupt Controller (NVIC) z z System Control Block (SCB) z z The System Control Block provides system implementation information, and system control. This includes configuration, control, and reporting of the system exceptions. Refer to the Cortex-M0+ Devices Generic User Guide for details (www.arm.com). Micro Trace Buffer (MTB) z 9.1.3 External interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts. Software can set the priority of each interrupt. The NVIC and the Cortex-M0+ processor core are closely coupled, providing low latency interrupt processing and efficient processing of late arriving interrupts. Refer to "Nested Vector Interrupt Controller" on page 29 and the Cortex-M0+ Technical Reference Manual for details (www.arm.com). The CoreSight MTB-M0+ (MTB) provides a simple execution trace capability to the Cortex-M0+ processor. Refer to section "Micro Trace Buffer" on page 31 and the CoreSight MTB-M0+ Technical Reference Manual for details (www.arm.com). Cortex-M0+ Address Map Table 9-2. Cortex-M0+ Address Map Address Peripheral 0xE000E000 System Control Space (SCS) 0xE000E010 System Timer (SysTick) 0xE000E100 Nested Vectored Interrupt Controller (NVIC) 0xE000ED00 System Control Block (SCB) 0x41006000 (see also "Product Mapping" on page 23) Micro Trace Buffer (MTB) 9.1.4 I/O Interface 9.1.4.1 Overview Because accesses to the AMBA(R) AHB-LiteTM and the single cycle I/O interface can be made concurrently, the CortexM0+ processor can fetch the next instructions while accessing the I/Os. This enables single cycle I/O accesses to be sustained for as long as needed. Refer to "CPU Local Bus" on page 375 for more information. 9.1.4.2 Description Direct access to PORT registers. 9.2 Nested Vector Interrupt Controller 9.2.1 Overview The Nested Vectored Interrupt Controller (NVIC) in the SAM R21 supports 32 interrupt lines with four different priority levels. For more details, refer to the Cortex-M0+ Technical Reference Manual (www.arm.com). 9.2.2 Interrupt Line Mapping Each of the 28 interrupt lines is connected to one peripheral instance, as shown in the table below. Each peripheral can have one or more interrupt flags, located in the peripheral's Interrupt Flag Status and Clear (INTFLAG) register. The interrupt flag is set when the interrupt condition occurs. Each interrupt in the peripheral can be individually enabled by writing a one to the corresponding bit in the peripheral's Interrupt Enable Set (INTENSET) register, and disabled by Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 29 writing a one to the corresponding bit in the peripheral's Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated from the peripheral when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt requests for one peripheral are ORed together on system level, generating one interrupt request for each peripheral. An interrupt request will set the corresponding interrupt pending bit in the NVIC interrupt pending registers (SETPEND/CLRPEND bits in ISPR/ICPR). For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt enable register (SETENA/CLRENA bits in ISER/ICER). The NVIC interrupt priority registers IPR0-IPR7 provide a priority field for each interrupt. Table 9-3. Interrupt Line Mapping Peripheral Source EIC NMI - External Interrupt Controller NVIC Line NMI PM - Power Manager 0 SYSCTRL - System Control 1 WDT - Watchdog Timer 2 RTC - Real Time Counter 3 EIC - External Interrupt Controller 4 NVMCTRL - Non-Volatile Memory Controller 5 DMAC - Direct Memory Access Controller 6 USB - Universal Serial Bus 7 EVSYS - Event System 8 SERCOM0 - Serial Communication Interface 0 9 SERCOM1 - Serial Communication Interface 1 10 SERCOM2 - Serial Communication Interface 2 11 SERCOM3 - Serial Communication Interface 3 12 SERCOM4 - Serial Communication Interface 4 13 SERCOM5 - Serial Communication Interface 5 14 TCC0 - Timer Counter for Control 0 15 TCC1 - Timer Counter for Control 1 16 TCC2 - Timer Counter for Control 2 17 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 30 Table 9-3. Interrupt Line Mapping (Continued) Peripheral Source TC3 - Timer Counter 3 18 TC4 - Timer Counter 4 19 TC5 - Timer Counter 5 20 Reserved 21 Reserved 22 ADC - Analog-to-Digital Converter 23 AC - Analog Comparator 24 Reserved 25 PTC - Peripheral Touch Controller 26 Reserved 27 9.3 Micro Trace Buffer 9.3.1 Features 9.3.2 NVIC Line z Program flow tracing for the Cortex-M0+ processor z MTB SRAM can be used for both trace and general purpose storage by the processor z The position and size of the trace buffer in SRAM is configurable by software z CoreSight compliant Overview When enabled, the MTB records changes in program flow, reported by the Cortex-M0+ processor over the execution trace interface shared between the Cortex-M0+ processor and the CoreSight MTB-M0+. This information is stored as trace packets in the SRAM by the MTB. An off-chip debugger can extract the trace information using the Debug Access Port to read the trace information from the SRAM. The debugger can then reconstruct the program flow from this information. The MTB simultaneously stores trace information into the SRAM, and gives the processor access to the SRAM. The MTB ensures that trace write accesses have priority over processor accesses. The execution trace packet consists of a pair of 32-bit words that the MTB generates when it detects the processor PC value changes non-sequentially. A non-sequential PC change can occur during branch instructions or during exception entry. See the CoreSight MTB-M0+ Technical Reference Manual for more details on the MTB execution trace packet format. Tracing is enabled when the MASTER.EN bit in the Master Trace Control Register is 1. There are various ways to set the bit to 1 to start tracing, or to 0 to stop tracing. See the CoreSight Cortex-M0+ Technical Reference Manual for more details on the Trace start and stop and for a detailed description of the MTB's MASTER register. The MTB can be programmed to stop tracing automatically when the memory fills to a specified watermark level or to start or stop tracing by writing directly to the MASTER.EN bit. If the watermark mechanism is not being used and the trace buffer overflows, then the buffer wraps around overwriting previous trace packets. The base address of the MTB registers is 0x41006000; this address is also written in the CoreSight ROM Table. The offset of each register from the base address is fixed and as defined by the CoreSight MTB-M0+ Technical Reference Manual. The MTB has 4 programmable registers to control the behavior of the trace features: Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 31 z POSITION: Contains the trace write pointer and the wrap bit, z MASTER: Contains the main trace enable bit and other trace control fields, z FLOW: Contains the WATERMARK address and the AUTOSTOP and AUTOHALT control bits, z BASE: Indicates where the SRAM is located in the processor memory map. This register is provided to enable auto discovery of the MTB SRAM location, by a debug agent. See the CoreSight MTB-M0+ Technical Reference Manual for a detailed description of these registers. 9.4 High-Speed Bus System 9.4.1 Features High-Speed Bus Matrix has the following features: z Symmetric crossbar bus switch implementation z Allows concurrent accesses from different masters to different slaves z 32-bit data bus z Operation at a one-to-one clock frequency with the bus masters Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 32 Configuration Multi-Slave MASTERS Table 9-4. CM0+ 0 DSU DSU 1 DMACDSU Data 2 DMAC Data DSU MASTER ID CM0+ 3 DMAC Fetch AHB-APB Bridge C 2 DMAC WB AHB-APB Bridge B 1 USB AHB-APB Bridge A 0 SRAM MTB Internal Flash High-Speed Bus SLAVES Priviledged SRAM-access MASTERS 9.4.2 0 1 2 3 4 4 5 5 6 6 SLAVE ID SRAM PORT ID MTB USB DMAC WB DMAC Fetch Bus Matrix Masters Bus Matrix Masters Master ID CM0+ - Cortex M0+ Processor 0 DSU - Device Service Unit 1 DMAC - Direct Memory Access Controller / Data Access 2 Table 9-5. Bus Matrix Slaves Bus Matrix Slaves Slave ID Internal Flash Memory 0 AHB-APB Bridge A 1 AHB-APB Bridge B 2 AHB-APB Bridge C 3 SRAM Port 4 - CM0+ Access 4 SRAM Port 5 - DMAC Data Access 5 SRAM Port 6 - DSU Access 6 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 33 Table 9-6. 9.4.3 SRAM Port Connection SRAM Port Connection Port ID Connection Type MTB - Micro Trace Buffer 0 Direct USB - Universal Serial Bus 1 Direct DMAC - Direct Memory Access Controller - Write-Back Access 2 Direct DMAC - Direct Memory Access Controller - Fetch Access 3 Direct CM0+ - Cortex M0+ Processor 4 Bus Matrix DMAC - Direct Memory Access Controller - Data Access 5 Bus Matrix DSU - Device Service Unit 6 Bus Matrix SRAM Quality of Service To ensure that masters with latency requirements get sufficient priority when accessing RAM, the different masters can be configured to have a given priority for different type of access. The Quality of Service (QoS) level is independently selected for each master accessing the RAM. For any access to the RAM the RAM also receives the QoS level. The QoS levels and their corresponding bit values for the QoS level configuration is shown in Table 9-7. Table 9-7. Value Quality of Service Name Description 00 DISABLE Background (no sensitive operation) 01 LOW Sensitive Bandwidth 10 MEDIUM Sensitive Latency 11 HIGH Critical Latency If a master is configured with QoS level 0x00 or 0x01 there will be minimum one cycle latency for the RAM access. The priority order for concurrent accesses are decided by two factors. First the QoS level for the master and then a static priority given by table nn-mm (table: SRAM port connection) where the lowest port ID has the highest static priority. The MTB has fixed QoS level 3 and the DSU has fixed QoS level 1. The CPU QoS level can be written/read at address 0x41007110, bits [1:0]. Its reset value is 0x0. Refer to different master QOSCTRL registers for configuring QoS for the other masters (USB, DMAC). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 34 9.5 AHB-APB Bridge The AHB-APB bridge is an AHB slave, providing an interface between the high-speed AHB domain and the low-power APB domain. It is used to provide access to the programmable control registers of peripherals (see "Product Mapping" on page 23). AHB-APB bridge is based on AMBA APB Protocol Specification V2.0 (ref. as APB4) including: z Wait state support z Error reporting z Transaction protection z Sparse data transfer (byte, half-word and word) Additional enhancements: z Address and data cycles merged into a single cycle z Sparse data transfer also apply to read access to operate the AHB-APB bridge, the clock (CLK_HPBx_AHB) must be enabled. See "PM - Power Manager" on page 112 for details. Figure 9-1. APB Write Access. T0 T1 T2 PCLK PADDR T3 T0 T2 T3 T4 T5 PCLK Addr 1 PADDR PWRITE PWRITE PSEL PSEL PENABLE PENABLE PWDATA T1 Data 1 PREADY PWDATA Addr 1 Data 1 PREADY No wait states Wait states Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 35 Figure 9-2. APB Read Access. T0 T1 T2 T3 T0 PCLK PADDR T2 T3 T4 T5 PCLK Addr 1 PADDR PWRITE PWRITE PSEL PSEL PENABLE PENABLE PRDATA T1 Data 1 PREADY Addr 1 PRDATA Data 1 PREADY No wait states 9.6 PAC - Peripheral Access Controller 9.6.1 Overview Wait states There is one PAC associated with each AHB-APB bridge. The PAC can provide write protection for registers of each peripheral connected on the same bridge. The PAC peripheral bus clock (CLK_PACx_APB) can be enabled and disabled in the Power Manager. CLK_PAC0_APB and CLK_PAC1_APB are enabled are reset. CLK_PAC2_APB is disabled at reset. Refer to "PM - Power Manager" on page 112 for details. The PAC will continue to operate in any sleep mode where the selected clock source is running. Write-protection does not apply for debugger access. When the debugger makes an access to a peripheral, writeprotection is ignored so that the debugger can update the register. Write-protect registers allow the user to disable a selected peripheral's write-protection without doing a read-modify-write operation. These registers are mapped into two I/O memory locations, one for clearing and one for setting the register bits. Writing a one to a bit in the Write Protect Clear register (WPCLR) will clear the corresponding bit in both registers (WPCLR and WPSET) and disable the write-protection for the corresponding peripheral, while writing a one to a bit in the Write Protect Set (WPSET) register will set the corresponding bit in both registers (WPCLR and WPSET) and enable the write-protection for the corresponding peripheral. Both registers (WPCLR and WPSET) will return the same value when read. If a peripheral is write-protected, and if a write access is performed, data will not be written, and the peripheral will return an access error (CPU exception). The PAC also offers a safety feature for correct program execution, with a CPU exception generated on double writeprotection or double unprotection of a peripheral. If a peripheral n is write-protected and a write to one in WPSET[n] is detected, the PAC returns an error. This can be used to ensure that the application follows the intended program flow by always following a write-protect with an unprotect, and vice versa. However, in applications where a write-protected peripheral is used in several contexts, e.g., interrupts, care should be taken so that either the interrupt can not happen while the main application or other interrupt levels manipulate the write-protection status, or when the interrupt handler needs to unprotect the peripheral, based on the current protection status, by reading WPSET. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 36 9.6.2 Register Description Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Refer to "Product Mapping" on page 23 for PAC locations. 9.6.2.1 PAC0 Register Description Write Protect Clear Name: WPCLR Offset: 0x00 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 EIC RTC WDT GCLK SYSCTRL PM Access R R/W R/W R/W R/W R/W R/W R Reset 0 0 0 0 0 0 0 0 z Bits 31:7 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 6:1 - EIC, RTC, WDT, GCLK, SYSCTRL, PM: Write Protect Disable 0: Write-protection is disabled. 1: Write-protection is enabled. Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write Protect bits for the corresponding peripherals. z Bit 0 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 37 Write Protect Set Name: WPSET Offset: 0x04 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 EIC RTC WDT GCLK SYSCTRL PM Access R R/W R/W R/W R/W R/W R/W R Reset 0 0 0 0 0 0 0 0 z Bits 31:7 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 6:1 - EIC, RTC, WDT, GCLK, SYSCTRL, PM: Write Protect Enable 0: Write-protection is disabled. 1: Write-protection is enabled. Writing a zero to these bits has no effect. Writing a one to these bits will set the Write Protect bit for the corresponding peripherals. z Bit 0 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 38 9.6.2.2 PAC1 Register Description Write Protect Clear Name: WPCLR Offset: 0x00 Reset: 0x00000002 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MTB USB DMAC PORT NVMCTRL DSU Access R R/W R/W R/W R/W R/W R/W R Reset 0 0 0 0 0 0 1 0 z Bits 31:7 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 6:1 - MTB, USB, DMAC, PORT, NVMCTRL, DSU: Write Protect 0: Write-protection is disabled. 1: Write-protection is enabled. Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals. z Bit 0 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 39 Write Protect Set Name: WPSET Offset: 0x04 Reset: 0x00000002 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MTB USB DMAC PORT NVMCTRL DSU Access R R/W R/W R/W R/W R/W R/W R Reset 0 0 0 0 0 0 1 0 z Bits 31:7 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 6:1 - MTB, USB, DMAC, PORT, NVMCTRL, DSU: Write Protect 0: Write-protection is disabled. 1: Write-protection is enabled. Writing a zero to these bits has no effect. Writing a one to these bits will set the Write Protect bit for the corresponding peripherals. z Bit 0 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 40 9.6.2.3 PAC2 Register Description Write Protect Clear Name: WPCLR Offset: 0x00 Reset: 0x00800000 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 AC ADC RFCTRL PTC Access R R R/W R R/W R R/W R/W Reset 1 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 TC5 TC4 TC3 TCC2 TCC1 TCC0 Access R R R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS R/W R/W R/W R/W R/W R/W R/W R 0 0 0 0 0 0 0 0 Access Reset z Bits 31:20 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to reset value when this register is written. These bits will always return reset value when read. z Bits 21,19,17:16,13:1 - RFCTRL, PTC, AC, ADC, TC5, TC4, TC3, TCC2, TCC1, TCC0, SERCOM5, SERCOM4, SERCOM3, SERCOM2, SERCOM1, SERCOM0, EVSYS: Write Protect 0: Write-protection is disabled. 1: Write-protection is enabled. Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals. z Bit 18,15,14,0 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 41 Write Protect Set Name: WPSET Offset: 0x04 Reset: 0x00800000 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 AC ADC RFCTRL PTC Access R R R/W R R/W R R/W R/W Reset 1 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 TC5 TC4 TC3 TCC2 TCC1 TCC0 Access R R R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS R/W R/W R/W R/W R/W R/W R/W R 0 0 0 0 0 0 0 0 Access Reset z Bits 31:20 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to reset value when this register is written. These bits will always return reset value when read. z Bits 21,19,17:16,13:1 - RFCTRL, PTC, AC, ADC, TC5, TC4, TC3, TCC2, TCC1, TCC0, SERCOM5, SERCOM4, SERCOM3, SERCOM2, SERCOM1, SERCOM0, EVSYS: Write Protect 0: Write-protection is disabled. 1: Write-protection is enabled. Writing a zero to these bits has no effect. Writing a one to these bits will set the Write Protect bit for the corresponding peripherals. z Bit 18,15,14,0 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 42 10. Peripherals Configuration Summary Table 10-1. Peripherals Configuration Summary AHB Clock Peripheral Name Base Address AHB-APB Bridge A 0x40000000 PAC0 0x40000000 PM 0x40000400 SYSCTRL 0x40000800 GCLK 0x40000C00 WDT 0x40001000 RTC IRQ Line Index Enabled at Reset 0 Y 0 Index Enabled at Reset 0 Y 1 Y Generic Clock Index 0: DFLL48M reference 1: FDPLL96M clk source 2: FDPLL96M 32kHz PAC Events DMA Index Prot at Reset 1 N Y 2 N Y 3 N Y User Generator Index SleepWalking 2 Y 3 Y 2 4 Y 3 4 N 0x40001400 3 5 Y 4 5 N 1: CMP0/ALARM0 2: CMP1 3: OVF 4-11: PER0-7 Y EIC 0x40001800 NMI, 4 6 Y 5 6 N 12-27: EXTINT0-15 Y AHB-APB Bridge B 0x41000000 PAC1 0x41000000 0 Y DSU 0x41002000 NVMCTRL 0x41004000 1 APB Clock 1 Y 3 Y 1 Y 1 Y 5 4 Y 2 Y 2 N [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 PORT 0x41004400 3 Y 3 N DMAC 0x41004800 6 5 Y 4 Y 4 N USB 0x41005000 7 6 Y 5 Y 5 N 6 N MTB 0x41006000 AHB-APB Bridge C 0x42000000 PAC2 0x42000000 EVSYS 0x42000400 SERCOM0 2 6 0-3: CH0-3 30-33: CH0-3 Y Y 0 N 8 1 N 7-18: one per CHANNEL 1 N 0x42000800 9 2 N 20: CORE 19: SLOW 2 N 1: RX 2: TX Y SERCOM1 0x42000C00 10 3 N 21: CORE 19: SLOW 3 N 3: RX 4: TX Y SERCOM2 0x42001000 11 4 N 22: CORE 19: SLOW 4 N 5: RX 6: TX Y Y 43 Table 10-1. Peripherals Configuration Summary AHB Clock Peripheral Name Base Address IRQ Line Index Enabled at Reset APB Clock Index Enabled at Reset Generic Clock Index PAC Index Events Prot at Reset User Generator DMA Index SleepWalking N 7: RX 8: TX Y SERCOM3 0x42001400 12 5 N 23: CORE 19: SLOW SERCOM4 0x42001800 13 6 N 24: CORE 19: SLOW 6 N 9: RX 10: TX Y SERCOM5 0x42001C00 14 7 N 25: CORE 19: SLOW 7 N 11: RX 12: TX Y TCC0 0x42002000 15 8 N 26 8 N 4-5: EV0-1 6-9: MC0-3 34: OVF 35: TRG 36: CNT 37-40: MC0-3 13: OVF 14-17: MC0-3 Y N 10-11: EV0-1 12-13: MC0-1 41: OVF 42: TRG 43: CNT 44-45: MC0-1 18: OVF 19-20: MC0-1 Y 46: OVF 47: TRG 48: CNT 49-50: MC0-1 21: OVF 22-23: MC0-1 Y TCC1 0x42002400 16 9 N 26 5 9 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 TCC2 0x42002800 17 10 N 27 10 N 14-15: EV0-1 16-17: MC0-1 TC3 0x42002C00 18 11 N 27 11 N 18: EV 51: OVF 52-53: MC0-1 24: OVF 25-26: MC0-1 Y TC4 0x42003000 19 12 N 28 12 N 19: EV 54: OVF 55-56: MCX0-1 27: OVF 28-29: MC0-1 Y TC5 0x42003400 20 13 N 28 13 N 20: EV 57: OVF 58-59: MC0-1 30: OVF 31-32: MC0-1 Y ADC 0x42004000 23 16 Y 30 16 N 23: START 24: SYNC 66: RESRDY 67: WINMON 39: RESRDY Y AC 0x42004400 24 17 N 31: DIG 32: ANA 17 N 25-26: SOC0-1 68-69: COMP0-1 70: WIN0 PTC 0x42004C00 26 19 N 34 19 N 28: STCONV 72: EOC 73: WCOMP RFCTRL 0x42005400 21 N 21 N Y 44 11. DSU - Device Service Unit 11.1 Overview The Device Service Unit (DSU) provides a means to detect debugger probes. This enables the ARM Debug Access Port (DAP) to have control over multiplexed debug pads and CPU reset. The DSU also provides system-level services to debug adapters in an ARM debug system. It implements a CoreSight Debug ROM that provides device identification as well as identification of other debug components in the system. Hence, it complies with the ARM Peripheral Identification specification. The DSU also provides system services to applications that need memory testing, as required for IEC60730 Class B compliance, for example. The DSU can be accessed simultaneously by a debugger and the CPU, as it is connected on the High-Speed Bus Matrix. For security reasons, some of the DSU features will be limited or unavailable when the device is protected by the NVMCTRL security bit (refer to "Security Bit" on page 356). 11.2 Features z CPU reset extension z Debugger probe detection (Cold- and Hot-Plugging) z Chip-Erase command and status z 32-bit cyclic redundancy check (CRC32) of any memory accessible through the bus matrix z ARM(R) CoreSightTM compliant device identification z Two debug communications channels z Debug access port security filter z Onboard memory built-in self-test (MBIST) 11.3 Block Diagram Figure 11-1. DSU Bock Diagram DSU debugger_present RESET SWCLK DEBUGGER PROBE INTERFACE cpu_reset_extension CPU DAP AHB-AP DAP SECURITY FILTER NVMCTRL DBG CORESIGHT ROM PORT M S CRC-32 SWDIO MBIST M HIGH-SPEED HIGH-SPEE BUS US MATRIX M MATR CHIP ERASE Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 45 11.4 Signal Description Signal Name Type Description RESET Digital Input External reset SWCLK Digital Input SW clock SWDIO Digital I/O SW bidirectional data pin Refer to "I/O Multiplexing and Considerations" on page 12 for details on the pin mapping for this peripheral. 11.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 11.5.1 I/O Lines The SWCLK pin is by default assigned to the DSU module to allow debugger probe detection and the condition to stretch the CPU reset phase. For more information, refer to "Debugger Probe Detection" on page 47. The Hot-Plugging feature depends on the PORT configuration. If the SWCLK pin function is changed in the PORT or if the PORT_MUX is disabled, the Hot-Plugging feature is disabled until a power-reset or an external reset. 11.5.2 Power Management The DSU will continue to operate in any sleep mode where the selected source clock is running. Refer to "PM - Power Manager" on page 112 for details on the different sleep modes. 11.5.3 Clocks The DSU bus clocks (CLK_DSU_APB and CLK_DSU_AHB) can be enabled and disabled in the Power Manager. For more information on the CLK_DSU_APB and CLK_DSU_AHB clock masks, refer to "PM - Power Manager" on page 112. 11.5.4 DMA Not applicable. 11.5.5 Interrupts Not applicable. 11.5.6 Events Not applicable. 11.5.7 Register Access Protection All registers with write access are optionally write-protected by the Peripheral Access Controller (PAC), except the following registers: z Debug Communication Channel 0 register (DCC0) z Debug Communication Channel 1 register (DCC1) Write-protection is denoted by the Write-Protection property in the register description. Write-protection does not apply for accesses through an external debugger. Refer to "PAC - Peripheral Access Controller" on page 36 for details. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 46 11.5.8 Analog Connections Not applicable. 11.6 Debug Operation 11.6.1 Principle of Operation The DSU provides basic services to allow on-chip debug using the ARM Debug Access Port and the ARM processor debug resources: z CPU reset extension z Debugger probe detection For more details on the ARM debug components, refer to the ARM Debug Interface v5Architecture Specification. 11.6.2 CPU Reset Extension "CPU reset extension" refers to the extension of the reset phase of the CPU core after the external reset is released. This ensures that the CPU is not executing code at startup while a debugger connects to the system. It is detected on a RESET release event when SWCLK is low. At startup, SWCLK is internally pulled up to avoid false detection of a debugger if SWCLK is left unconnected. When the CPU is held in the reset extension phase, the CPU Reset Extension bit (CRSTEXT) of the Status A register (STATUSA.CRSTEXT) is set. To release the CPU, write a one to STATUSA.CRSTEXT. STATUSA.CRSTEXT will then be set to zero. Writing a zero to STATUSA.CRSTEXT has no effect. For security reasons, it is not possible to release the CPU reset extension when the device is protected by the NVMCTRL security bit (refer to "Security Bit" on page 356). Trying to do so sets the Protection Error bit (PERR) of the Status A register (STATUSA.PERR). Figure 11-2. Typical CPU Reset Extension Set and Clear Timing Diagram SWCLK RESET DSU CRSTEXT Clear CPU reset extension CPU_STATE reset running 11.6.3 Debugger Probe Detection 11.6.3.1 Cold-Plugging Cold-Plugging is the detection of a debugger when the system is in reset. Cold-Plugging is detected when the CPU reset extension is requested, as described above. 11.6.3.2 Hot-Plugging Hot-Plugging is the detection of a debugger probe when the system is not in reset. Hot-Plugging is not possible under reset because the detector is reset when POR or RESET are asserted. Hot-Plugging is active when a SWCLK falling edge is detected. The SWCLK pad is multiplexed with other functions and the user must ensure that its default function is assigned to the debug system. If the SWCLK function is changed, the Hot-Plugging feature is disabled until a power- Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 47 reset or external reset occurs. Availability of the Hot-Plugging feature can be read from the Hot-Plugging Enable bit of the Status B register (STATUSB.HPE). Figure 11-3. Hot-Plugging Detection Timing Diagram SWCLK RESET CPU_STATE reset running Hot-Plugging The presence of a debugger probe is detected when either Hot-Plugging or Cold-Plugging is detected. Once detected, the Debugger Present bit of the Status B register (STATUSB.DBGPRES) is set. For security reasons, Hot-Plugging is not available when the device is protected by the NVMCTRL security bit (refer to "Security Bit" on page 356). This detection requires that pads are correctly powered. Thus, at cold startup, this detection cannot be done until POR is released. If the device is protected, Cold-Plugging is the only way to detect a debugger probe, and so the external reset timing must be longer than the POR timing. If external reset is deasserted before POR release, the user must retry the procedure above until it gets connected to the device. 11.7 Chip-Erase Chip-Erase consists of removing all sensitive information stored in the chip and clearing the NVMCTRL security bit (refer to "Security Bit" on page 356). Hence, all volatile memories and the flash array (including the EEPROM emulation area) will be erased. The flash auxiliary rows, including the user row, will not be erased. When the device is protected, the debugger must reset the device in order to be detected. This ensures that internal registers are reset after the protected state is removed. The Chip-Erase operation is triggered by writing a one to the Chip-Erase bit in the Control register (CTRL.CE). This command will be discarded if the DSU is protected by the Peripheral Access Controller (PAC). Once issued, the module clears volatile memories prior to erasing the flash array. To ensure that the Chip-Erase operation is completed, check the Done bit of the Status A register (STATUSA.DONE). The Chip-Erase operation depends on clocks and power management features that can be altered by the CPU. For that reason, it is recommended to issue a ChipErase after a Cold-Plugging procedure to ensure that the device is in a known and safe state. The recommended sequence is as follows: 1. 2. 11.8 Issue the Cold-Plugging procedure (refer to "Cold-Plugging" on page 47). The device then: 1. Detects the debugger probe 2. Holds the CPU in reset Issue the Chip-Erase command by writing a one to CTRL.CE. The device then: 1. Clears the system volatile memories 2. Erases the whole flash array (including the EEPROM emulation area, not including auxiliary rows) 3. Erases the lock row, removing the NVMCTRL security bit protection 3. Check for completion by polling STATUSA.DONE (read as one when completed). 4. Reset the device to let the NVMCTRL update fuses. Programming Programming of the flash or RAM memories is available when the device is not protected by the NVMCTRL security bit (refer to "Security Bit" on page 356). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 48 11.9 1. At power up, RESET is driven low by a debugger. The on-chip regulator holds the system in a POR state until the input supply is above the POR threshold (refer to "Power-On Reset (POR) Characteristics" on page 1069). The system continues to be held in this static state until the internally regulated supplies have reached a safe operating state. 2. The PM starts, clocks are switched to the slow clock (Core Clock, System Clock, Flash Clock and any Bus Clocks that do not have clock gate control). Internal resets are maintained due to the external reset. 3. The debugger maintains a low level on SWCLK. Releasing RESET results in a debugger Cold-Plugging procedure. 4. The debugger generates a clock signal on the SWCLK pin, the Debug Access Port (DAP) receives a clock. 5. The CPU remains in reset due to the Cold-Plugging procedure; meanwhile, the rest of the system is released. 6. A Chip-Erase is issued to ensure that the flash is fully erased prior to programming. 7. Programming is available through the AHB-AP. 8. After operation is completed, the chip can be restarted either by asserting RESET, toggling power or writing a one to the Status A register CPU Reset Phase Extension bit (STATUSA.CRSTEXT). Make sure that the SWCLK pin is high when releasing RESET to prevent extending the CPU reset. Intellectual Property Protection Intellectual property protection consists of restricting access to internal memories from external tools when the device is protected, and is accomplished by setting the NVMCTRL security bit (refer to "Security Bit" on page 356). This protected state can be removed by issuing a Chip-Erase (refer to "Chip-Erase" on page 48). When the device is protected, read/write accesses using the AHB-AP are limited to the DSU address range and DSU commands are restricted. The DSU implements a security filter that monitors the AHB transactions generated by the ARM AHB-AP inside the DAP. If the device is protected, then AHB-AP read/write accesses outside the DSU external address range are discarded, causing an error response that sets the ARM AHB-AP sticky error bits (refer to the ARM Debug Interface v5 Architecture Specification on http://www.arm.com). The DSU is intended to be accessed either: z Internally from the CPU, without any limitation, even when the device is protected z Externally from a debug adapter, with some restrictions when the device is protected For security reasons, DSU features have limitations when used from a debug adapter. To differentiate external accesses from internal ones, the first 0x100 bytes of the DSU register map have been replicated at offset 0x100: z The first 0x100 bytes form the internal address range z The next 0x100 bytes form the external address range When the device is protected, the DAP can only issue MEM-AP accesses in the DSU address range limited to the 0x1000x2000 offset range. The DSU operating registers are located in the 0x00-0xFF area and remapped in 0x100-0x1FF to differentiate accesses coming from a debugger and the CPU. If the device is protected and an access is issued in the region 0x100-0x1FF, it is subject to security restrictions. For more information, refer to Table 11-1. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 49 Figure 11-4. APB Memory Mapping 0x0000 DSU operating registers 0x00FC 0x0100 0x01FD Internal address range (cannot be accessed from debug tools when the device is protected by the NVMCTRL security bit) Replicated DSU operating registers Empty External address range (can be accessed from debug tools with some restrictions) 0x1000 DSU CoreSight ROM 0x1FFC Some features not activated by APB transactions are not available when the device is protected: Table 11-1. Feature Availability Under Protection Features Availability When the Device is Protected CPU reset extension Yes Debugger Cold-Plugging Yes Debugger Hot-Plugging No 11.10 Device Identification Device identification relies on the ARM CoreSight component identification scheme, which allows the chip to be identified as an ATMEL device implementing a DSU. The DSU contains identification registers to differentiate the device. 11.10.1 CoreSight Identification A system-level ARM CoreSight ROM table is present in the device to identify the vendor and the chip identification method. Its address is provided in the MEM-AP BASE register inside the ARM Debug Access Port. The CoreSight ROM implements a 64-bit conceptual ID composed as follows from the PID0 to PID7 CoreSight ROM Table registers: Figure 11-5. Conceptual 64-Bit Peripheral ID Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 50 Table 11-2. Conceptual 64-Bit Peripheral ID Bit Descriptions Field Size JEP-106 CC code 4 Atmel continuation code: 0x0 JEP-106 ID code 7 Atmel device ID: 0x1F 4KB count 4 Indicates that the CoreSight component is a ROM: 0x0 PID4 RevAnd 4 Not used; read as 0 PID3 CUSMOD 4 Not used; read as 0 PID3 PARTNUM 12 Contains 0xCD0 to indicate that DSU is present 4 DSU revision (starts at 0x0 and increments by 1 at both major and minor revisions). Identifies DSU identification method variants. If 0x0, this indicates that device identification can be completed by reading the Device Identification register (DID) REVISION Description Location PID4 PID1+PID2 PID0+PID1 PID3 For more information, refer to the ARM Debug Interface Version 5 Architecture Specification. 11.10.2 DSU Chip Identification Method: The DSU DID register identifies the device by implementing the following information: z Processor identification z Product family identification z Product series identification z Device select 11.11 Functional Description 11.11.1 Principle of Operation The DSU provides memory services such as CRC32 or MBIST that require almost the same interface. Hence, the Address, Length and Data registers are shared. They must be configured first; then a command can be issued by writing the Control register. When a command is ongoing, other commands are discarded until the current operation is completed. Hence, the user must wait for the STATUSA.DONE bit to be set prior to issuing another one. 11.11.2 Basic Operation 11.11.2.1 Initialization The module is enabled by enabling its clocks. For more details, refer to "Clocks" on page 46. The DSU registers can be write-protected. Refer to "PAC - Peripheral Access Controller" on page 36. 11.11.2.2 Operation from a debug adapter Debug adapters should access the DSU registers in the external address range 0x100 - 0x2000. If the device is protected by the NVMCTRL security bit (refer to "Security Bit" on page 356), accessing the first 0x100 bytes causes the system to return an error (refer to "Intellectual Property Protection" on page 49). 11.11.2.3 Operation from the CPU There are no restrictions when accessing DSU registers from the CPU. However, the user should access DSU registers in the internal address range (0x0 - 0x100) to avoid external security restrictions (refer to "Intellectual Property Protection" on page 49). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 51 11.11.3 32-bit Cyclic Redundancy Check (CRC32) The DSU unit provides support for calculating a cyclic redundancy check (CRC32) value for a memory area (including flash and AHB RAM). When the CRC32 command is issued from: z The internal range, the CRC32 can be operated at any memory location z The external range, the CRC32 operation is restricted; DATA, ADDR and LENGTH values are forced (see below) Table 11-3. AMOD Bit Descriptions when Operating CRC32 AMOD[1:0] Short Name 0 ARRAY 1 EEPROM 2-3 Reserved External Range Restrictions CRC32 is restricted to the full flash array area (EEPROM emulation area not included) DATA forced to 0xFFFFFFFF before calculation (no seed) CRC32 of the whole EEPROM emulation area DATA forced to 0xFFFFFFFF before calculation (no seed) The algorithm employed is the industry standard CRC32 algorithm using the generator polynomial 0xEDB88320 (reversed representation). 11.11.3.1 Starting CRC32 Calculation CRC32 calculation for a memory range is started after writing the start address into the Address register (ADDR) and the size of the memory range into the Length register (LENGTH). Both must be word-aligned. The initial value used for the CRC32 calculation must be written to the Data register. This value will usually be 0xFFFFFFFF, but can be, for example, the result of a previous CRC32 calculation if generating a common CRC32 of separate memory blocks. Once completed, the calculated CRC32 value can be read out of the Data register. The read value must be complemented to match standard CRC32 implementations or kept non-inverted if used as starting point for subsequent CRC32 calculations. If the device is in protected state by the NVMCTRL security bit (refer to "Security Bit" on page 356), it is only possible to calculate the CRC32 of the whole flash array when operated from the external address space. In most cases, this area will be the entire onboard non-volatile memory. The Address, Length and Data registers will be forced to predefined values once the CRC32 operation is started, and values written by the user are ignored. This allows the user to verify the contents of a protected device. The actual test is started by writing a one in the 32-bit Cyclic Redundancy Check bit of the Control register (CTRL.CRC). A running CRC32 operation can be canceled by resetting the module (writing a one to CTRL.SWRST). 11.11.3.2 Interpreting the Results The user should monitor the Status A register. When the operation is completed, STATUSA.DONE is set. Then the Bus Error bit of the Status A register (STATUSA.BERR) must be read to ensure that no bus error occurred. 11.11.4 Debug Communication Channels The Debug Communication Channels (DCCO and DCC1) consist of a pair of registers with associated handshake logic, accessible by both CPU and debugger even if the device is protected by the NVMCTRL security bit (refer to "Security Bit" on page 356). The registers can be used to exchange data between the CPU and the debugger, during run time as well as in debug mode. This enables the user to build a custom debug protocol using only these registers. The DCC0 and DCC1 registers are accessible when the protected state is active. When the device is protected, however, it is not possible to connect a debugger while the CPU is running (STATUSA.CRSTEXT is not writable and the CPU is held under reset). Dirty bits in the status registers indicate whether a new value has been written in DCC0 or DCC1. These bits,DCC0D and DCC1D, are located in the STATUSB registers. They are automatically set on write and cleared on Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 52 read. The DCC0 and DCC1 registers are shared with the onboard memory testing logic (MBIST). Accordingly, DCC0 and DCC1 must not be used while performing MBIST operations. 11.11.5 Testing of Onboard Memories (MBIST) The DSU implements a feature for automatic testing of memory also known as MBIST. This is primarily intended for production test of onboard memories. MBIST cannot be operated from the external address range when the device is protected by the NVMCTRL security bit (refer to "Security Bit" on page 356). If a MBIST command is issued when the device is protected, a protection error is reported in the Protection Error bit in the Status A register (STATUSA.PERR). 1. Algorithm The algorithm used for testing is a type of March algorithm called "March LR". This algorithm is able to detect a wide range of memory defects, while still keeping a linear run time. The algorithm is: 1. Write entire memory to 0, in any order. 2. Bit for bit read 0, write 1, in descending order. 3. Bit for bit read 1, write 0, read 0, write 1, in ascending order. 4. Bit for bit read 1, write 0, in ascending order. 5. Bit for bit read 0, write 1, read 1, write 0, in ascending order. 6. Read 0 from entire memory, in ascending order. The specific implementation used has a run time of O(14n) where n is the number of bits in the RAM. The detected faults are: 2. z Address decoder faults z Stuck-at faults z Transition faults z Coupling faults z Linked Coupling faults z Stuck-open faults Starting MBIST To test a memory, you need to write the start address of the memory to the ADDR.ADDR bit group, and the size of the memory into the Length register. See "Physical Memory Map" on page 24 to know which memories are available, and which address they are at. For best test coverage, an entire physical memory block should be tested at once. It is possible to test only a subset of a memory, but the test coverage will then be somewhat lower. The actual test is started by writing a one to CTRL.MBIST. A running MBIST operation can be canceled by writing a one to CTRL.SWRST. 3. Interpreting the Results The tester should monitor the STATUSA register. When the operation is completed, STATUSA.DONE is set. There are three different modes: z ADDR.AMOD=0: exit-on-error (default) In this mode, the algorithm terminates either when a fault is detected or on successful completion. In both cases, STATUSA.DONE is set. If an error was detected, STATUSA.FAIL will be set. User then can read the DATA and ADDR registers to locate the fault. Refer to "Locating Errors" on page 53. z ADDR.AMOD=1: pause-on-error In this mode, the MBIST algorithm is paused when an error is detected. In such a situation, only STATUSA.FAIL is asserted. The state machine waits for user to clear STATUSA.FAIL by writing a one in STATUSA.FAIL to resume. Prior to resuming, user can read the DATA and ADDR registers to locate the fault. Refer to "Locating Errors" on page 53. 4. Locating Errors If the test stops with STATUSA.FAIL set, one or more bits failed the test. The test stops at the first detected error. The position of the failing bit can be found by reading the following registers: Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 53 z ADDR: Address of the word containing the failing bit. z DATA: contains data to identify which bit failed, and during which phase of the test it failed. The DATA register will in this case contains the following bit groups: Table 11-4. DATA bits Description When MBIST Operation Returns An Error Bit 31 30 29 28 27 26 25 24 Bit 23 22 21 20 19 18 17 16 Bit 15 14 13 12 11 10 9 8 phase Bit 7 6 5 4 3 2 1 0 bit_index z bit_index: contains the bit number of the failing bit z phase: indicates which phase of the test failed and the cause of the error. See Table 11-5 on page 54. Table 11-5. MBIST Operation Phases Phase Test Actions 0 Write all bits to zero. This phase cannot fail. 1 Read 0, write 1, increment address 2 Read 1, write 0 3 Read 0, write 1, decrement address 4 Read 1, write 0, decrement address 5 Read 0, write 1 6 Read 1, write 0, decrement address 7 Read all zeros. bit_index is not used 11.11.6 System Services Availability When Accessed Externally External access: Access performed in the DSU address offset 0x200-0x1FFF range. Internal access: Access performed in the DSU address offset 0x0-0x100 range. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 54 Table 11-6. Available Features When Operated From The External Address Range and Device is Protected Availability From The External Address Range and Device is Protected Features Chip-Erase command and status CRC32 Yes Yes, only full array or full EEPROM CoreSight Compliant Device identification Yes Debug communication channels Yes Testing of onboard memories (MBIST) Yes STATUSA.CRSTEXT clearing No (STATUSA.PERR is set when attempting to do so) Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 55 11.12 Register Summary Table 11-7. Register Summary Offset Name Bit Pos. 0x0000 CTRL 7:0 CE 0x0001 STATUSA 7:0 PERR FAIL BERR CRSTEXT DONE 0x0002 STATUSB 7:0 HPE DCCD1 DCCD0 DBGPRES PROT 0x0003 Reserved MBIST 0x0004 7:0 0x0005 15:8 ADDR[13:6] 23:16 ADDR[21:14] 31:24 ADDR[29:22] 0x0006 ADDR 0x0007 7:0 0x0009 15:8 LENGTH[13:6] 23:16 LENGTH[21:14] 31:24 LENGTH[29:22] 0x000A 0x000B LENGTH[5:0] 0x000C 7:0 DATA[7:0] 0x000D 15:8 DATA[15:8] 0x000E DATA 23:16 DATA[23:16] 0x000F 31:24 DATA[31:24] 0x0010 7:0 DATA[7:0] 0x0011 15:8 DATA[15:8] 23:16 DATA[23:16] 0x0013 31:24 DATA[31:24] 0x0014 7:0 DATA[7:0] 0x0012 0x0015 0x0016 DCC0 DCC1 0x0017 15:8 DATA[15:8] 23:16 DATA[23:16] 31:24 DATA[31:24] 0x0018 7:0 0x0019 15:8 0x001A DID 0x001B 0x001C ... 0x00FF 23:16 31:24 REVISION[3:0] SERIES[5:0] FAMILY PROCESSOR[3:0] FAMILY[4:1] External address range: Replicates the 0x00:0xFF address range, Gives access to the same resources but with security restrictions when the device is protected. This address range is the only one accessible externally (using the ARM DAP) when the device is protected. Reserved 0x1000 0x1001 DEVSEL[7:0] DIE[3:0] Reserved 0x0100 ... 0x01FF 0x0200 ... 0x0FFF SWRST ADDR[5:0] 0x0008 LENGTH CRC 7:0 ENTRY0 15:8 FMT EPRES ADDOFF[3:0] 0x1002 23:16 ADDOFF[11:4] 0x1003 31:24 ADDOFF[19:12] Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 56 Offset Name 0x1004 0x1005 Bit Pos. 7:0 ENTRY1 15:8 FMT ADDOFF[3:0] 0x1006 23:16 ADDOFF[11:4] 0x1007 31:24 ADDOFF[19:12] 0x1008 7:0 END[7:0] 0x1009 0x100A END 0x100B 0x100C ... 0x1FCB 0x1FCE 15:8 END[15:8] 23:16 END[23:16] 31:24 END[31:24] Reserved 0x1FCC 0x1FCD 7:0 MEMTYPE 23:16 31:24 0x1FD0 7:0 0x1FD1 23:16 Reserved 7:0 0x1FE1 23:16 31:24 0x1FE4 7:0 0x1FE5 15:8 PID1 31:24 0x1FE8 7:0 0x1FE9 JEPU JEPIDCH[2:0] 31:24 0x1FEC 7:0 15:8 PID3 31:24 0x1FF0 7:0 0x1FF1 REVAND[3:0] CUSMOD[3:0] 23:16 0x1FEF 0x1FF3 REVISION[3:0] 23:16 0x1FED 0x1FF2 PARTNBH[3:0] 15:8 PID2 0x1FEB 0x1FEE JEPIDCL[3:0] 23:16 0x1FE7 0x1FEA PARTNBL[7:0] 15:8 PID0 0x1FE3 0x1FE6 JEPCC[3:0] 31:24 0x1FE0 0x1FE2 FKBC[3:0] 15:8 PID4 0x1FD3 0x1FD4 ... 0x1FDF SMEMP 15:8 0x1FCF 0x1FD2 EPRES PREAMBLEB0[7:0] 15:8 CID0 23:16 31:24 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 57 Offset Name Bit Pos. 0x1FF4 7:0 0x1FF5 15:8 0x1FF6 CID1 31:24 0x1FF8 7:0 0x1FFA 23:16 31:24 0x1FFC 7:0 0x1FFD 15:8 0x1FFF PREAMBLEB2[7:0] 15:8 CID2 0x1FFB 0x1FFE PREAMBLE[3:0] 23:16 0x1FF7 0x1FF9 CCLASS[3:0] CID3 PREAMBLEB3[7:0] 23:16 31:24 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 58 11.13 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write protection is denoted by the Write-Protected property in each individual register description. Refer to "Register Access Protection" on page 46 for details. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 59 11.13.1 Control Name: CTRL Offset: 0x0000 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 CE MBIST CRC 1 0 SWRST Access R R R W W W R W Reset 0 0 0 0 0 0 0 0 z Bits 7:5 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 4 - CE: Chip Erase Writing a zero to this bit has no effect. Writing a one to this bit starts the Chip-Erase operation. z Bit 3 - MBIST: Memory Built-In Self-Test Writing a zero to this bit has no effect. Writing a one to this bit starts the memory BIST algorithm. z Bit 2 - CRC: 32-bit Cyclic Redundancy Check Writing a zero to this bit has no effect. Writing a one to this bit starts the cyclic redundancy check algorithm. z Bit 1 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 0 - SWRST: Software Reset Writing a zero to this bit has no effect. Writing a one to this bit resets the module. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 60 11.13.2 Status A Name: STATUSA Offset: 0x0001 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 PERR FAIL BERR CRSTEXT DONE Access R R R R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:5 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 4 - PERR: Protection Error Writing a zero to this bit has no effect. Writing a one to this bit clears the Protection Error bit. This bit is set when a command that is not allowed in protected state is issued. z Bit 3 - FAIL: Failure Writing a zero to this bit has no effect. Writing a one to this bit clears the Failure bit. This bit is set when a DSU operation failure is detected. z Bit 2 - BERR: Bus Error Writing a zero to this bit has no effect. Writing a one to this bit clears the Bus Error bit. This bit is set when a bus error is detected. z Bit 1 - CRSTEXT: CPU Reset Phase Extension Writing a zero to this bit has no effect. Writing a one to this bit clears the CPU Reset Phase Extension bit. This bit is set when a debug adapter Cold-Plugging is detected, which extends the CPU reset phase. z Bit 0 - DONE: Done Writing a zero to this bit has no effect. Writing a one to this bit clears the Done bit. This bit is set when a DSU operation is completed. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 61 11.13.3 Status B Name: STATUSB Offset: 0x0002 Reset: 0x1X Property: Write-Protected Bit 7 6 5 4 3 2 1 0 HPE DCCD1 DCCD0 DBGPRES PROT Access R R R R R R R R Reset 0 0 0 1 0 0 X X z Bits 7:5 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 4 - HPE: Hot-Plugging Enable Writing a zero to this bit has no effect. Writing a one to this bit has no effect. This bit is set when Hot-Plugging is enabled. This bit is cleared when Hot-Plugging is disabled. This is the case when the SWCLK function is changed. Only a power-reset or a external reset can set it again. z Bits 3:2 - DCCDx [x=1..0]: Debug Communication Channel x Dirty Writing a zero to this bit has no effect. Writing a one to this bit has no effect. This bit is set when DCCx is written. This bit is cleared when DCCx is read. z Bit 1 - DBGPRES: Debugger Present Writing a zero to this bit has no effect. Writing a one to this bit has no effect. This bit is set when a debugger probe is detected. This bit is never cleared. z Bit 0 - PROT: Protected Writing a zero to this bit has no effect. Writing a one to this bit has no effect. This bit is set at powerup when the device is protected. This bit is never cleared. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 62 11.13.4 Address Name: ADDR Offset: 0x0004 Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 ADDR[29:22] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 ADDR[21:14] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 ADDR[13:6] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADDR[5:0] Access Reset R/W R/W R/W R/W R/W R/W R R 0 0 0 0 0 0 0 0 z Bits 31:2 - ADDR[29:0]: Address Initial word start address needed for memory operations. z Bits 1:0 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 63 11.13.5 Length Name: LENGTH Offset: 0x0008 Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 LENGTH[29:22] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 LENGTH[21:14] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 LENGTH[13:6] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 LENGTH[5:0] Access Reset R/W R/W R/W R/W R/W R/W R R 0 0 0 0 0 0 0 0 z Bits 31:2 - LENGTH[29:0]: Length Length in words needed for memory operations. z Bits 1:0 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 64 11.13.6 Data Name: DATA Offset: 0x000C Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 DATA[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DATA[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DATA[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 31:0 - DATA[31:0]: Data Memory operation initial value or result value. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 65 11.13.7 Debug Communication Channel n Name: DCCn Offset: 0x0010+n*0x4 [n=0..1] Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 DATA[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DATA[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DATA[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 31:0 - DATA[31:0]: Data Data register. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 66 11.13.8 Device Identification The information in this register is related to the ordering code. Refer to the "Ordering Information" on page 6 for details. Name: DID Offset: 0x0018 Reset: - Property: Write-Protected Bit 31 30 29 28 27 26 PROCESSOR[3:0] 25 24 FAMILY[4:1] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 FAMILY SERIES[5:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DIE[3:0] REVISION[3:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DEVSEL[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 31:28 - PROCESSOR[3:0]: Processor The value of this field defines the processor used on the device. For this device, the value of this field is 0x1, corresponding to the ARM Cortex-M0+ processor. z Bits 27:23 - FAMILY[4:0]: Product Family The value of this field corresponds to the Product Family part of the ordering code. For this device, the value of this field is 0x0, corresponding to the SAM D family of base line microcontrollers. z Bit 22 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 21:16 - SERIES[5:0]: Product Series The value of this field corresponds to the Product Series part of the ordering code. For this device, the value of this field is 0x01, corresponding to a product with the Cortex-M0+ processor with DMA and USB features. z Bits 15:12 - DIE[3:0]: Die Identification Identifies the die in the family. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 67 z Bits 11:8 - REVISION[3:0]: Revision Identifies the die revision number. z Bits 7:0 - DEVSEL[7:0]: Device Select DEVSEL is used to identify a device within a product family and product series. The value corresponds to the Flash memory density, pin count and device variant parts of the ordering code. Refer to "Ordering Information" on page 6 for details. Table 11-8. Device Selection DEVSEL Device Flash 0x00 - 0x17 Pincount Reserved 0x18 SAMR21E19A 256KB+512KB(1) 32KB 32 0x19 SAMR21G18A 256KB 32KB 48 0x1A SAMR21G17A 128KB 32KB 48 0x1B SAMR21G16A 64KB 16KB 48 0x1C SAMR21E18A 256KB 32KB 32 0x1D SAMR21E17A 128K 32KB 32 0x1E SAMR21E16A 64KB 16KB 32 0x1F-0xFF Note: RAM 1. Reserved Serial Flash MX25V4006EWSK. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 68 11.13.9 Coresight ROM Table Entry n Name: ENTRYn Offset: 0x1000+n*0x4 [n=0..1] Reset: 0xXXXXX00X Property: Write-Protected Bit 31 30 29 28 27 26 25 24 ADDOFF[19:12] Access R R R R R R R R Reset X X X X X X X X Bit 23 22 21 20 19 18 17 16 ADDOFF[11:4] Access R R R R R R R R Reset X X X X X X X X Bit 15 14 13 12 11 10 9 8 ADDOFF[3:0] Access R R R R R R R R Reset X X X X 0 0 0 0 Bit 7 6 5 4 3 2 1 0 FMT EPRES Access R R R R R R R R Reset 0 0 0 0 0 0 1 X z Bits 31:12 - ADDOFF[19:0]: Address Offset The base address of the component, relative to the base address of this ROM table. z Bits 11:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 1 - FMT: Format Always read as one, indicates a 32-bit ROM table. z Bit 0 - EPRES: Entry Present This bit indicates whether an entry is present at this location in the ROM table. This bit is set at powerup if the device is not protected indicating that the entry is not present. This bit is cleared at powerup if the device is not protected indicating that the entry is present. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 69 11.13.10Coresight ROM Table End Name: END Offset: 0x1008 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 END[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 END[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 END[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 END[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 31:0 - END[31:0]: End Marker Indicates the end of the CoreSight ROM table entries. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 70 11.13.11Coresight ROM Table Memory Type Name: MEMTYPE Offset: 0x1FCC Reset: 0x0000000X Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SMEMP Access R R R R R R R R Reset 0 0 0 0 0 0 0 X z Bits 31:1 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 0 - SMEMP: System Memory Present This bit indicates whether system memory is present on the bus that connects to the ROM table. This bit is set at powerup if the device is not protected indicating that the system memory is accessible from a debug adapter. This bit is cleared at powerup if the device is protected indicating that the system memory is not accessible from a debug adapter. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 71 11.13.12Peripheral Identification 4 Name: PID4 Offset: 0x1FD0 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 FKBC[3:0] JEPCC[3:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 31:8 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 7:4 - FKBC[3:0]: 4KB Count These bits will always return zero when read, indicating that this debug component occupies one 4KB block. z Bits 3:0 - JEPCC[3:0]: JEP-106 Continuation Code These bits will always return zero when read, indicating a Atmel device. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 72 11.13.13Peripheral Identification 0 Name: PID0 Offset: 0x1FE0 Reset: 0x000000D0 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PARTNBL[7:0] Access R R R R R R R R Reset 1 1 0 1 0 0 0 0 z Bits 31:8 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 7:0 - PARTNBL[7:0]: Part Number Low These bits will always return 0xD0 when read, indicating that this device implements a DSU module instance. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 73 11.13.14Peripheral Identification 1 Name: PID1 Offset: 0x1FE4 Reset: 0x000000FC Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 JEPIDCL[3:0] PARTNBH[3:0] Access R R R R R R R R Reset 1 1 1 1 1 1 0 0 z Bits 31:8 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 7:4 - JEPIDCL[3:0]: Low part of the JEP-106 Identity Code These bits will always return 0xF when read, indicating a Atmel device (Atmel JEP-106 identity code is 0x1F). z Bits 3:0 - PARTNBH[3:0]: Part Number High These bits will always return 0xC when read, indicating that this device implements a DSU module instance. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 74 11.13.15Peripheral Identification 2 Name: PID2 Offset: 0x1FE8 Reset: 0x00000009 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 REVISION[3:0] JEPU JEPIDCH[2:0] Access R R R R R R R R Reset 0 0 0 0 1 0 0 1 z Bits 31:8 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 7:4 - REVISION[3:0]: Revision Number Revision of the peripheral. Starts at 0x0 and increments by one at both major and minor revisions. z Bit 3 - JEPU: JEP-106 Identity Code is used This bit will always return one when read, indicating that JEP-106 code is used. z Bits 2:0 - JEPIDCH[2:0]: JEP-106 Identity Code High These bits will always return 0x1 when read, indicating an Atmel device (Atmel JEP-106 identity code is 0x1F). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 75 11.13.16Peripheral Identification 3 Name: PID3 Offset: 0x1FEC Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 REVAND[3:0] CUSMOD[3:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 31:8 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 7:4 - REVAND[3:0]: Revision Number These bits will always return 0x0 when read. z Bits 3:0 - CUSMOD[3:0]: ARM CUSMOD These bits will always return 0x0 when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 76 11.13.17Component Identification 0 Name: CID0 Offset: 0x1FF0 Reset: 0x0000000D Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PREAMBLEB0[7:0] Access R R R R R R R R Reset 0 0 0 0 1 1 0 1 z Bits 31:8 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 7:0 - PREAMBLEB0[7:0]: Preamble Byte 0 These bits will always return 0xD when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 77 11.13.18Component Identification 1 Name: CID1 Offset: 0x1FF4 Reset: 0x00000010 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CCLASS[3:0] PREAMBLE[3:0] Access R R R R R R R R Reset 0 0 0 1 0 0 0 0 z Bits 31:8 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 7:4 - CCLASS[3:0]: Component Class These bits will always return 0x1 when read indicating that this ARM CoreSight component is ROM table (refer to the ARM Debug Interface v5 Architecture Specification at http://www.arm.com). z Bits 3:0 - PREAMBLE[3:0]: Preamble These bits will always return 0x0 when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 78 11.13.19Component Identification 2 Name: CID2 Offset: 0x1FF8 Reset: 0x00000005 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PREAMBLEB2[7:0] Access R R R R R R R R Reset 0 0 0 0 0 1 0 1 z Bits 31:8 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 7:0 - PREAMBLEB2[7:0]: Preamble Byte 2 These bits will always return 0x05 when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 79 11.13.20Component Identification 3 Name: CID3 Offset: 0x1FFC Reset: 0x000000B1 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PREAMBLEB3[7:0] Access R R R R R R R R Reset 1 0 1 1 0 0 0 1 z Bits 31:8 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 7:0 - PREAMBLEB3[7:0]: Preamble Byte 3 These bits will always return 0xB1 when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 80 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 81 12. Clock System This chapter only aims to summarize the clock distribution and terminology in the SAM R21 device. It will not explain every detail of its configuration. For in-depth documentation, see the referenced module chapters. 12.1 Clock Distribution Figure 12-1. Clock distribution PM SYSCTRL GCLK XOSC GCLK Generator 0 GCLK Multiplexer 0 (DFLL48M Reference) GCLK Generator 1 GCLK Multiplexer 1 OSCULP32K OSC32K GCLK_MAIN _ N XOSC32K Synchronous Clock Controller Peripheral 0 Generic Clocks OSC8M GCLK Generator x DFLL48M FDPLL96M GCLK Multiplexer y Peripheral z AHB/APB System Clocks The clock system on the SAM R21 consists of: z Clock sources, controlled by SYSCTRL z z z A Clock source is the base clock signal used in the system. Example clock sources are the internal 8MHz oscillator (OSC8M), External crystal oscillator (XOSC) and the Digital frequency locked loop (DFLL48M). Generic Clock Controller (GCLK) which controls the clock distribution system, made up of: z Generic Clock generators: A programmable prescaler, that can use any of the system clock sources as its source clock. The Generic Clock Generator 0, also called GCLK_MAIN, is the clock feeding the Power Manager used to generate synchronous clocks. z Generic Clocks: Typically the clock input of a peripheral on the system. The generic clocks, through the Generic Clock Multiplexer, can use any of the Generic Clock generators as its clock source. Multiple instances of a peripheral will typically have a separate generic clock for each instance. The DFLL48M clock input (when multiplying another clock source) is generic clock 0. Power Manager (PM) z The PM controls synchronous clocks on the system. This includes the CPU, bus clocks (APB, AHB) as well as the synchronous (to the CPU) user interfaces of the peripherals. It contains clock masks that can turn on/off the user interface of a peripheral as well as prescalers for the CPU and bus clocks. Figure 12-2 shows an example where SERCOM0 is clocked by the DFLL48M in open loop mode. The DFLL48M is enabled, the Generic Clock Generator 1 uses the DFLL48M as its clock source, and the generic clock 20, also called GCLK_SERCOM0_CORE, that is connected to SERCOM0 uses generator 1 as its source. The SERCOM0 interface, clocked by CLK_SERCOM0_APB, has been unmasked in the APBC Mask register in the PM. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 82 Figure 12-2. Example of SERCOM clock PM Synchronous Clock Controller SYSCTRL DFLL48M 12.2 CLK_SERCOM0_APB GCLK Generic Clock Generator 1 Generic Clock Multiplexer 20 GCLK_SERCOM0_CORE SERCOM 0 Synchronous and Asynchronous Clocks As the CPU and the peripherals can be clocked from different clock sources, possibly with widely different clock speeds, some peripheral accesses by the CPU needs to be synchronized between the different clock domains. In these cases the peripheral includes a SYNCBUSY status flag that can be used to check if a sync operation is in progress. As the nature of the synchronization might vary between different peripherals, detailed description for each peripheral can be found in the sub-chapter "synchronization" for each peripheral where this is necessary. In the datasheet references to synchronous clocks are referring to the CPU and bus clocks, while asynchronous clocks are clock generated by generic clocks. 12.3 Register Synchronization There are two different register synchronization schemes implemented on this device: some modules use a common synchronizer register synchronization scheme, while other modules use a distributed synchronizer register synchronization scheme. The modules using a common synchronizer register synchronization scheme are: GCLK, WDT, RTC, EIC, TC, ADC, AC, DAC. The modules using a distributed synchronizer register synchronization scheme are: SERCOM USART, SERCOM SPI, SERCOM I2C, TCC, USB. 12.3.1 Common Synchronizer Register Synchronization 12.3.1.1 Overview All peripherals are composed of one digital bus interface, which is connected to the APB or AHB bus and clocked using a corresponding synchronous clock, and one core clock, which is clocked using a generic clock. Access between these clock domains must be synchronized. As this mechanism is implemented in hardware the synchronization process takes place even if the different clocks domains are clocked from the same source and on the same frequency. All registers in the bus interface are accessible without synchronization. All core registers in the generic clock domain must be synchronized when written. Some core registers must be synchronized when read. Registers that need synchronization has this denoted in each individual register description. Two properties are used: write-synchronization and readsynchronization. A common synchronizer is used for all registers in one peripheral, as shown in Figure 12-3. Therefore, only one register per peripheral can be synchronized at a time. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 83 Figure 12-3. Synchronization Asynchronous Domain (generic clock) Synchronous Domain (CLK_APB) Sync Non Synced reg Peripheral bus INTFLAG Write-Synced reg SYNCBUSY STATUS READREQ Synchronizer Write-Synced reg R/W-Synced reg 12.3.1.2 Write-Synchronization The write-synchronization is triggered by a write to any generic clock core register. The Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set when the write-synchronization starts and cleared when the writesynchronization is complete. Refer to "Synchronization Delay" on page 86 for details on the synchronization delay. When the write-synchronization is ongoing (STATUS.SYNCBUSY is one), any of the following actions will cause the peripheral bus to stall until the synchronization is complete: z Writing a generic clock core register z Reading a read-synchronized core register z Reading the register that is being written (and thus triggered the synchronization) Core registers without read-synchronization will remain static once they have been written and synchronized, and can be read while the synchronization is ongoing without causing the peripheral bus to stall. APB registers can also be read while the synchronization is ongoing without causing the peripheral bus to stall. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 84 12.3.1.3 Read-Synchronization Reading a read-synchronized core register will cause the peripheral bus to stall immediately until the readsynchronization is complete. STATUS.SYNCBUSY will not be set. Refer to "Synchronization Delay" on page 86 for details on the synchronization delay. Note that reading a read-synchronized core register while STATUS.SYNCBUSY is one will cause the peripheral bus to stall twice; first because of the ongoing synchronization, and then again because reading a read-synchronized core register will cause the peripheral bus to stall immediately. 12.3.1.4 Completion of synchronization The user can either poll STATUS.SYNCBUSY or use the Synchronisation Ready interrupt (if available) to check when the synchronization is complete. It is also possible to perform the next read/write operation and wait, as this next operation will be started once the previous write/read operation is synchronized and/or complete. 12.3.1.5 Read Request The read request functionality is only available to peripherals that have the Read Request register (READREQ) implemented. Refer to the register description of individual peripheral chapters for details. To avoid forcing the peripheral bus to stall when reading read-synchronized core registers, the read request mechanism can be used. Basic Read Request Writing a one to the Read Request bit in the Read Request register (READREQ.RREQ) will request readsynchronization of the register specified in the Address bits in READREQ (READREQ.ADDR) and set STATUS.SYNCBUSY. When read-synchronization is complete, STATUS.SYNCBUSY is cleared. The readsynchronized value is then available for reading without delay until READREQ.RREQ is written to one again. The address to use is the offset to the peripheral's base address of the register that should be synchronized. Continuous Read Request Writing a one to the Read Continuously bit in READREQ (READREQ.RCONT) will force continuous readsynchronization of the register specified in READREQ.ADDR. The latest value is always available for reading without stalling the bus, as the synchronization mechanism is continuously synchronizing the given value. SYNCBUSY is set for the first synchronization, but not for the subsequent synchronizations. If another synchronization is attempted, i.e. by executing a write-operation of a write-synchronized register, the read request will be stopped, and will have to be manually restarted. Note that continuous read-synchronization is paused in sleep modes where the generic clock is not running. This means that a new read request is required if the value is needed immediately after exiting sleep. 12.3.1.6 Enable Write-Synchronization Writing to the Enable bit in the Control register (CTRL.ENABLE) will also trigger write-synchronization and set STATUS.SYNCBUSY. CTRL.ENABLE will read its new value immediately after being written. The Synchronisation Ready interrupt (if available) cannot be used for Enable write-synchronization. When the enable write-synchronization is ongoing (STATUS.SYNCBUSY is one), attempt to do any of the following will cause the peripheral bus to stall until the enable synchronization is complete: z Writing a core register z Writing an APB register z Reading a read-synchronized core register APB registers can be read while the enable write-synchronization is ongoing without causing the peripheral bus to stall. 12.3.1.7 Software Reset Write-Synchronization Writing a one to the Software Reset bit in CTRL (CTRL.SWRST) will also trigger write-synchronization and set STATUS.SYNCBUSY. When writing a one to the CTRL.SWRST bit it will immediately read as one. CTRL.SWRST and STATUS.SYNCBUSY will be cleared by hardware when the peripheral has been reset. Writing a zero to the Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 85 CTRL.SWRST bit has no effect. The Synchronisation Ready interrupt (if available) cannot be used for Software Reset write-synchronization. When the software reset is in progress (STATUS.SYNCBUSY and CTRL.SWRST are one), attempt to do any of the following will cause the peripheral bus to stall until the Software Reset synchronization and the reset is complete: z Writing a core register z Writing an APB register z Reading a read-synchronized register APB registers can be read while the software reset is being write-synchronized without causing the peripheral bus to stall. 12.3.1.8 Synchronization Delay The synchronization will delay the write or read access duration by a delay D, given by the equation: 5 P GCLK + 2 P APB < D < 6 P GCLK + 3 P APB Where P GCLK is the period of the generic clock and P APB is the period of the peripheral bus clock. A normal peripheral bus register access duration is 2 P APB . 12.3.2 Distributed Synchronizer Register Synchronization 12.3.2.1 Overview All peripherals are composed of one digital bus interface, which is connected to the APB or AHB bus and clocked using a corresponding synchronous clock, and one core clock, which is clocked using a generic clock. Access between these clock domains must be synchronized. As this mechanism is implemented in hardware the synchronization process takes place even if the different clocks domains are clocked from the same source and on the same frequency. All registers in the bus interface are accessible without synchronization. All core registers in the generic clock domain must be synchronized when written. Some core registers must be synchronized when read. Registers that need synchronization has this denoted in each individual register description. 12.3.2.2 General Write synchronization Inside the same module, each core register, denoted by the Write-Synchronized property, use its own synchronization mechanism so that writing to different core registers can be done without waiting for the end of synchronization of previous core register access. To write again to the same core register in the same module, user must wait for the end of synchronization or the write will be discarded. For each core register, that can be written, a synchronization status bit is associated Example: REGA, REGB are 8-bit core registers. REGC is 16-bit core register. Offset Register 0x00 REGA 0x01 REGB 0x02 0x03 REGC Since synchronization is per register, user can write REGA (8-bit access) then immediately write REGB (8-bit access) without error. User can write REGC (16-bit access) without affecting REGA or REGB. But if user writes REGC in two consecutives 8-bit accesses, second write will be discarded and generate an error. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 86 When user makes a 32-bit access to offset 0x00, all registers are written but REGA, REGB, REGC can be updated at a different time because of independent write synchronization 12.3.2.3 General read synchronization Before any read of a core register, the user must check that the related bit in SYNCBUSY register is cleared. Read access to core register is always immediate but the return value is reliable only if a synchonization of this core register is not going. 12.3.2.4 Completion of synchronization The user can either poll SYNCBUSY register or use the Synchronisation Ready interrupt (if available) to check when the synchronization is complete. 12.3.2.5 Enable Write-Synchronization Writing to the Enable bit in the Control register (CTRL.ENABLE) will also trigger write-synchronization and set SYNCBUSY.ENABLE. CTRL.ENABLE will read its new value immediately after being written. The Synchronisation Ready interrupt (if available) cannot be used for Enable write-synchronization. 12.3.2.6 Software Reset Write-Synchronization Writing a one to the Software Reset bit in CTRL (CTRL.SWRST) will also trigger write-synchronization and set SYNCBUSY.SWRST. When writing a one to the CTRL.SWRST bit it will immediately read as one. CTRL.SWRST and SYNCBUSY.SWRST will be cleared by hardware when the peripheral has been reset. Writing a zero to the CTRL.SWRST bit has no effect. The Synchronisation Ready interrupt (if available) cannot be used for Software Reset write-synchronization. 12.3.2.7 Synchronization Delay The synchronization will delay the write or read access duration by a delay D, given by the equation: 5 P GCLK + 2 P APB < D < 6 P GCLK + 3 P APB Where P GCLK is the period of the generic clock and P APB is the period of the peripheral bus clock. A normal peripheral bus register access duration is 2 P APB . 12.4 Enabling a Peripheral To enable a peripheral clocked by a generic clock, the following parts of the system needs to be configured: z A running clock source. z A clock from the Generic Clock Generator must be configured to use one of the running clock sources, and the generator must be enabled. z The generic clock, through the Generic Clock Multiplexer, that connects to the peripheral needs to be configured with a running clock from the Generic Clock Generator, and the generic clock must be enabled. z The user interface of the peripheral needs to be unmasked in the PM. If this is not done the peripheral registers will read as all 0's and any writes to the peripheral will be discarded. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 87 12.5 On-demand, Clock Requests Figure 12-4. Clock request routing Clock request DFLL48M Generic Clock Generator ENABLE GENEN RUNSTDBY RUNSTDBY Clock request Generic Clock Multiplexer Clock request Peripheral CLKEN ENABLE RUNSTDBY ONDEMAND All the clock sources in the system can be run in an on-demand mode, where the clock source is in a stopped state when no peripherals are requesting the clock source. Clock requests propagate from the peripheral, via the GCLK, to the clock source. If one or more peripheral is using a clock source, the clock source will be started/kept running. As soon as the clock source is no longer needed and no peripheral have an active request the clock source will be stopped until requested again. For the clock request to reach the clock source, the peripheral, the generic clock and the clock from the Generic Clock Generator in-between must be enabled. The time taken from a clock request being asserted to the clock source being ready is dependent on the clock source startup time, clock source frequency as well as the divider used in the Generic Clock Generator. The total startup time from a clock request to the clock is available for the peripheral is: Delay_start_max = Clock source startup time + 2 * clock source periods + 2 * divided clock source periods Delay_start_min = Clock source startup time + 1 * clock source period + 1 * divided clock source period The delay for shutting down the clock source when there is no longer an active request is: Delay_stop_min = 1 * divided clock source period + 1 * clock source period Delay_stop_max = 2 * divided clock source periods + 2 * clock source periods The On-Demand principle can be disabled individually for each clock source by clearing the ONDEMAND bit located in each clock source controller. The clock is always running whatever is the clock request. This has the effect to remove the clock source startup time at the cost of the power consumption. In standby mode, the clock request mechanism is still working if the modules are configured to run in standby mode (RUNSTDBY bit). 12.6 Power Consumption vs Speed Due to the nature of the asynchronous clocking of the peripherals there are some considerations that needs to be taken if either targeting a low-power or a fast-acting system. If clocking a peripheral with a very low clock, the active power consumption of the peripheral will be lower. At the same time the synchronization to the synchronous (CPU) clock domain is dependent on the peripheral clock speed, and will be longer with a slower peripheral clock; giving lower response time and more time waiting for the synchronization to complete. 12.7 Clocks after Reset On any reset the synchronous clocks start to their initial state: z OSC8M is enabled and divided by 8 z GCLK_MAIN uses OSC8M as source z CPU and BUS clocks are undivided On a power reset the GCLK starts to their initial state: z All generic clock generators disabled except: z the generator 0 (GCLK_MAIN) using OSC8M as source, with no division z the generator 2 using OSCULP32K as source, with no division Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 88 z All generic clocks disabled except: z the WDT generic clock using the generator 2 as source On a user reset the GCLK starts to their initial state, except for: z generic clocks that are write-locked (WRTLOCK is written to one prior to reset or the WDT generic clock if the WDT Always-On at power on bit set in the NVM User Row) z The generic clock dedicated to the RTC if the RTC generic clock is enabled On any reset the clock sources are reset to their initial state except the 32KHz clock sources which are reset only by a power reset. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 89 13. GCLK - Generic Clock Controller 13.1 Overview Several peripherals may require specific clock frequencies to operate correctly. The Generic Clock Controller consists of number of generic clock generators and generic clock multiplexers that can provide a wide range of clock frequencies. The generic clock generators can be set to use different external and internal clock sources. The selected clock can be divided down in the generic clock generator. The outputs from the generic clock generators are used as clock sources for the generic clock multiplexers, which select one of the sources to generate a generic clock (GCLK_PERIPHERAL), as shown in Figure 13-2. The number of generic clocks, m, depends on how many peripherals the device has. 13.2 Features z Provides generic clocks z Wide frequency range z Clock source for the generator can be changed on the fly 13.3 Block Diagram The Generic Clock Controller can be seen in the clocking diagram, which is shown in Figure 13-1 . Figure 13-1. Device Clocking Diagram GENERIC CLOCK CONTROLLER SYSCTRL Generic Clock Generator XOSC OSCULP32K OSC32K Generic Clock Multiplexer XOSC32K GCLK_PERIPHERAL OSC8M DFLL48M FDPLL96M Clock Divider & Masker Clock Gate PERIPHERALS GCLK_IO GCLK_MAIN PM The Generic Clock Controller block diagram is shown in Figure 13-2. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 90 Figure 13-2. Generic Clock Controller Block Diagram(1) Generic Clock Generator 0 Clock Sources GCLK_MAIN GCLKGEN[0] Clock Divider & Masker GCLK_IO[0] (I/O input) Generic Clock Multiplexer 0 GCLK_PERIPHERAL[0] Clock Gate Generic Clock Generator 1 Generic Clock Multiplexer 1 Clock Divider & Masker GCLK_IO[1] (I/O input) GCLK_IO[0] (I/O output) GCLK_IO[1] (I/O output) GCLKGEN[1] GCLK_PERIPHERAL[1] Clock Gate Generic Clock Generator n Clock Divider & Masker GCLK_IO[n] (I/O input) GCLK_IO[n] (I/O output) GCLKGEN[n] Generic Clock Multiplexer m Clock Gate GCLK_PERIPHERAL[m] GCLKGEN[n:0] Note: 13.4 1. If the GENCTRL.SRC=GCLKIN the GCLK_IO is set as an input. Signal Description Table 13-1. Signal Description Signal Name GCLK_IO[7:0] Type Description Digital I/O Source clock when input Generic clock when output Refer to "I/O Multiplexing and Considerations" on page 12 for details on the pin mapping for this peripheral. One signal can be mapped on several pins. 13.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 13.5.1 I/O Lines Using the Generic Clock Controller's I/O lines requires the I/O pins to be configured. Refer to "PORT" on page 373 for details. 13.5.2 Power Management The Generic Clock Controller can operate in all sleep modes, if required. Refer to Table 14-4 for details on the different sleep modes. 13.5.3 Clocks The Generic Clock Controller bus clock (CLK_GCLK_APB) can be enabled and disabled in the Power Manager, and the default state of CLK_GCLK_APB can be found in the Peripheral Clock Masking section in APBAMASK. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 91 13.5.4 DMA Not applicable. 13.5.5 Interrupts Not applicable. 13.5.6 Events Not applicable. 13.5.7 Debug Operation Not applicable. 13.5.8 Register Access Protection All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protection property in the register description. When the CPU is halted in debug mode or the CPU reset is extended, all write-protection is automatically disabled. Write-protection does not apply for accesses through an external debugger. Refer to "PAC - Peripheral Access Controller" on page 36 for details. 13.5.9 Analog Connections Not applicable. 13.6 Functional Description 13.6.1 Principle of Operation The GCLK module is comprised of eight generic clock generators sourcing m generic clock multiplexers. A clock source selected as input to one of the generic clock generators can be used directly, or it can be prescaled in the generic clock generator before the generator output is used as input to one or more of the generic clock multiplexers. A generic clock multiplexer provides a generic clock to a peripheral (GCLK_PERIPHERAL). A generic clock can act as the clock to one or several of peripherals. 13.6.2 Basic Operation 13.6.2.1 Initialization Before a generic clock is enabled, the clock source of its generic clock generator should be enabled. The generic clock must be configured as outlined by the following steps: 1. The generic clock generator division factor must be set by performing a single 32-bit write to the Generic Clock Generator Division register (GENDIV): z The generic clock generator that will be selected as the source of the generic clock must be written to the ID bit group (GENDIV.ID). z The division factor must be written to the DIV bit group (GENDIV.DIV) Refer to GENDIV register for details. 2. The generic clock generator must be enabled by performing a single 32-bit write to the Generic Clock Generator Control register (GENCTRL): z The generic clock generator that will be selected as the source of the generic clock must be written to the ID bit group (GENCTRL.ID) z The generic clock generator must be enabled by writing a one to the GENEN bit (GENCTRL.GENEN) Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 92 Refer to GENCTRL register for details. 3. The generic clock must be configured by performing a single 16-bit write to the Generic Clock Control register (CLKCTRL): z The generic clock that will be configured must be written to the ID bit group (CLKCTRL.ID) z The generic clock generator used as the source of the generic clock must be written to the GEN bit group (CLKCTRL.GEN) Refer to CLKCTRL register for details. 13.6.2.2 Enabling, Disabling and Resetting The GCLK module has no enable/disable bit to enable or disable the whole module. The GCLK is reset by writing a one to the Software Reset bit in the Control register (CTRL.SWRST). All registers in the GCLK will be reset to their initial state except for generic clocks and associated generators that have their Write Lock bit written to one. Refer to "Configuration Lock" on page 95 for details. 13.6.2.3 Generic Clock Generator Each generic clock generator (GCLKGEN) can be set to run from one of eight different clock sources except GCLKGEN[1] which can be set to run from one of seven sources. GCLKGEN[1] can act as source to the other generic clock generators but can not act as source to itself. Each generic clock generator GCLKGEN[x] can be connected to one specific GCLK_IO[x] pin. The GCLK_IO[x] can be set to act as source to GCLKGEN[x] or GCLK_IO[x] can be set up to output the clock generated by GCLKGEN[x]. The selected source (GCLKGENSRC see Figure 13-3) can optionally be divided. Each generic clock generator can be independently enabled and disabled. Each GCLKGEN clock can then be used as a clock source for the generic clock multiplexers. Each generic clock is allocated to one or several peripherals. GCLKGEN[0], is used as GCLK_MAIN for the synchronous clock controller inside the Power Manager. Refer to "PM - Power Manager" on page 112 for details on the synchronous clock generation. Figure 13-3. Generic Clock Generator GCLKGENSRC Clock Sources 0 Clock Gate DIVIDER GCLK_IO[x] GCLKGEN[x] 1 GENCTRL.GENEN GENCTRL.DIVSEL GENCTRL.SRC GENDIV.DIV 13.6.2.4 Enabling a Generic Clock Generator A generic clock generator is enabled by writing a one to the Generic Clock Generator Enable bit in the Generic Clock Generator Control register (GENCTRL.GENEN). 13.6.2.5 Disabling a Generic Clock Generator A generic clock generator is disabled by writing a zero to GENCTRL.GENEN. When GENCTRL.GENEN is read as zero, the GCLKGEN clock is disabled and clock gated. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 93 13.6.2.6 Selecting a Clock Source for the Generic Clock Generator Each generic clock generator can individually select a clock source by writing to the Source Select bit group in GENCTRL (GENCTRL.SRC). Changing from one clock source, A, to another clock source, B, can be done on the fly. If clock source B is not ready, the generic clock generator will continue running with clock source A. As soon as clock source B is ready, however, the generic clock generator will switch to it. During the switching, the generic clock generator holds clock requests to clock sources A and B and then releases the clock source A request when the switch is done. The available clock sources are device dependent (usually the crystal oscillators, RC oscillators, PLL and DFLL clocks). GCLKGEN[1] can be used as a common source for all the generic clock generators except generic clock generator 1. 13.6.2.7 Changing Clock Frequency The selected generic clock generator source, GENCLKSRC can optionally be divided by writing a division factor in the Division Factor bit group in the Generic Clock Generator Division register (GENDIV.DIV). Depending on the value of the Divide Selection bit in GENCTRL (GENCTRL.DIVSEL), it can be interpreted in two ways by the integer divider. Note that the number of DIV bits for each generic clock generator is device dependent. Refer to Table 13-11 for details. 13.6.2.8 Duty Cycle When dividing a clock with an odd division factor, the duty-cycle will not be 50/50. Writing a one to the Improve Duty Cycle bit in GENCTRL (GENCTRL.IDC) will result in a 50/50 duty cycle. 13.6.2.9 Generic Clock Output on I/O Pins Each Generic Clock Generator's output can be directed to a GCLK_IO pin. If the Output Enable bit in GENCTRL (GENCTRL.OE) is one and the generic clock generator is enabled (GENCTRL.GENEN is one), the generic clock generator requests its clock source and the GCLKGEN clock is output to a GCLK_IO pin. If GENCTRL.OE is zero, GCLK_IO is set according to the Output Off Value bit. If the Output Off Value bit in GENCTRL (GENCTRL.OOV) is zero, the output clock will be low when generic clock generator is turned off. If GENCTRL.OOV is one, the output clock will be high when generic clock generator is turned off. In standby mode, if the clock is output (GENCTRL.OE is one), the clock on the GCLK_IO pin is frozen to the OOV value if the Run In Standby bit in GENCTRL (GENCTRL.RUNSTDBY) is zero. If GENCTRL.RUNSTDBY is one, the GCLKGEN clock is kept running and output to GCLK_IO. 13.6.3 Generic Clock Figure 13-4. Generic Clock Multiplexer GCLKGEN[0] GCLKGEN[1] GCLKGEN[2] GCLKGEN[n] Clock Gate GCLK_PERIPHERAL CLKCTRL.CLKEN CLKCTRL.GEN 13.6.3.1 Enabling a Generic Clock Before a generic clock is enabled, one of the generic clock generators must be selected as the source for the generic clock by writing to CLKCTRL.GEN. The clock source selection is individually set for each generic clock. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 94 When a generic clock generator has been selected, the generic clock is enabled by writing a one to the Clock Enable bit in CLKCTRL (CLKCTRL.CLKEN). The CLKCTRL.CLKEN bit must be synchronized to the generic clock domain. CLKCTRL.CLKEN will continue to read as its previous state until the synchronization is complete. 13.6.3.2 Disabling a Generic Clock A generic clock is disabled by writing a zero to CLKCTRL.CLKEN. The SYNCBUSY bit will be cleared when this writesynchronization is complete. CLKCTRL.CLKEN will continue to read as its previous state until the synchronization is complete. When the generic clock is disabled, the generic clock is clock gated. 13.6.3.3 Selecting a Clock Source for the Generic Clock When changing a generic clock source by writing to CLKCTRL.GEN, the generic clock must be disabled before being reenabled with the new clock source setting. This prevents glitches during the transition: 1. Write a zero to CLKCTRL.CLKEN 2. Wait until CLKCTRL.CLKEN reads as zero 3. Change the source of the generic clock by writing CLKCTRL.GEN 4. Re-enable the generic clock by writing a one to CLKCTRL.CLKEN 13.6.3.4 Configuration Lock The generic clock configuration is locked for further write accesses by writing the Write Lock bit (WRTLOCK) in the CLKCTRL register. All writes to the CLKCTRL register will be ignored. It can only be unlocked by a power reset. The generic clock generator sources of a locked generic clock are also locked. The corresponding GENCTRL and GENDIV are locked, and can be unlocked only by a power reset. There is one exception concerning the GCLKGEN[0]. As it is used as GCLK_MAIN, it can not be locked. It is reset by any reset to startup with a known configuration. The SWRST can not unlock the registers. 13.6.4 Additional Features 13.6.4.1 Indirect Access The Generic Clock Generator Control and Division registers (GENCTRL and GENDIV) and the Generic Clock Control register (CLKCTRL) are indirectly addressed as shown in Figure 13-5. Figure 13-5. GCLK Indirect Access User Interface Generic Clock Generator [i] GENCTRL GENDIV CLKCTRL GENCTRL.ID=i GENCTRL GENDIV.ID=i GENDIV CLKCTRL.ID=j Generic Clock[j] CLKCTRL Writing these registers is done by setting the corresponding ID bit group. To read a register, the user must write the ID of the channel, i, in the corresponding register. The value of the register for the corresponding ID is available in the user interface by a read access. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 95 For example, the sequence to read the GENCTRL register of generic clock generator i is: 1. Do an 8-bit write of the i value to GENCTRL.ID 2. Read GENCTRL 13.6.4.2 Generic Clock Enable after Reset The Generic Clock Controller must be able to provide a generic clock to some specific peripherals after a reset. That means that the configuration of the generic clock generators and generic clocks after reset is device-dependent. Refer to Table 13-9 and Table 13-10 for details on GENCTRL reset. Refer to Table 13-13 and Table 13-14 for details on GENDIV reset. Refer to Table 13-5 and Table 13-6 for details on CLKCTRL reset. 13.6.5 Sleep Mode Operation 13.6.5.1 SleepWalking The GCLK module supports the SleepWalking feature. During a sleep mode where the generic clocks are stopped, a peripheral that needs its generic clock to execute a process must request it from the Generic Clock Controller. The Generic Clock Controller will receive this request and then determine which generic clock generator is involved and which clock source needs to be awakened. It then wakes up the clock source, enables the generic clock generator and generic clock stages successively and delivers the generic clock to the peripheral. 13.6.5.2 Run in Standby Mode In standby mode, the GCLK can continuously output the generic clock generator output to GCLK_IO. Refer to "Generic Clock Output on I/O Pins" on page 94 for details. 13.6.6 Synchronization Due to the asynchronicity between CLK_GCLK_APB and GCLKGENSRC some registers must be synchronized when accessed. A register can require: z Synchronization when written z Synchronization when read z Synchronization when written and read z No synchronization When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is stalled. The following registers need synchronization when written: z Generic Clock Generator Control register (GENCTRL) z Generic Clock Generator Division register (GENDIV) z Control register (CTRL) Write-synchronization is denoted by the Write-Synchronization property in the register description. Refer to "Register Synchronization" on page 83 for further details. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 96 13.7 Register Summary Table 13-2. Register Summary Offset Name Bit Pos. 0x0 CTRL 7:0 0x1 STATUS 7:0 0x2 0x3 CLKCTRL 0x4 0x5 0x6 SWRST SYNCBUSY 7:0 15:8 ID[5:0] WRTLOCK GEN[3:0] CLKEN ID[3:0] 7:0 GENCTRL 0x7 SRC[4:0] 15:8 23:16 RUNSTDBY DIVSEL OE 0x8 7:0 0x9 15:8 DIV[7:0] 23:16 DIV[15:8] 0xA 0xB OOV IDC GENEN 31:24 GENDIV ID[3:0] 31:24 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 97 13.8 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-protected property in each individual register description. Refer to "Register Access Protection" on page 92 for details. Some registers require synchronization when read and/or written. Synchronization is denoted by the Write-Synchronized or the Read-Synchronized property in each individual register description. Refer to "Synchronization" on page 96 for details. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 98 13.8.1 Control Name: CTRL Offset: 0x0 Reset: 0x00 Property: Write-Protected, Write-Synchronized Bit 7 6 5 4 3 2 1 0 SWRST Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:1 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 0 - SWRST: Software Reset 0: There is no reset operation ongoing. 1: There is a reset operation ongoing. Writing a zero to this bit has no effect. Writing a one to this bit resets all registers in the GCLK to their initial state after a power reset, except for generic clocks and associated generators that have their WRTLOCK bit in CLKCTRL read as one. Refer to Table 13-9 for details on GENCTRL reset. Refer to Table 13-13 for details on GENDIV reset. Refer to Table 13-5 for details on CLKCTRL reset. Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete. CTRL.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 99 13.8.2 Status Name: STATUS Offset: 0x1 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 SYNCBUSY Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bit 7 - SYNCBUSY: Synchronization Busy Status This bit is cleared when the synchronization of registers between the clock domains is complete. This bit is set when the synchronization of registers between clock domains is started. z Bits 6:0 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 100 13.8.3 Generic Clock Control This register allows the user to configure one of the generic clocks, as specified in the CLKCTRL.ID bit group. To write to the CLKCTRL register, do a 16-bit write with all configurations and the ID. To read the CLKCTRL register, first do an 8-bit write to the CLKCTRL.ID bit group with the ID of the generic clock whose configuration is to be read, and then read the CLKCTRL register. Name: CLKCTRL Offset: 0x2 Reset: 0x0000 Property: Write-Protected Bit 15 14 WRTLOCK CLKEN R/W R/W R R R/W Reset 0 0 0 0 Bit 7 6 5 4 Access 13 12 11 10 9 8 R/W R/W R/W 0 0 0 0 3 2 1 0 GEN[3:0] ID[5:0] Access R R R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bit 15 - WRTLOCK: Write Lock When this bit is written, it will lock from further writes the generic clock pointed to by CLKCTRL.ID, the generic clock generator pointed to in CLKCTRL.GEN and the division factor used in the generic clock generator. It can only be unlocked by a power reset. One exception to this is generic clock generator 0, which cannot be locked. 0: The generic clock and the associated generic clock generator and division factor are not locked. 1: The generic clock and the associated generic clock generator and division factor are locked. z Bit 14 - CLKEN: Clock Enable This bit is used to enable and disable a generic clock. 0: The generic clock is disabled. 1: The generic clock is enabled. z Bits 13:12 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 11:8 - GEN[3:0]: Generic Clock Generator Table 13-3. Generic Clock Generator GEN[3:0] Name Description 0x0 GCLKGEN0 Generic clock generator 0 0x1 GCLKGEN1 Generic clock generator 1 0x2 GCLKGEN2 Generic clock generator 2 0x3 GCLKGEN3 Generic clock generator 3 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 101 Table 13-3. Generic Clock Generator (Continued) GEN[3:0] Name Description 0x4 GCLKGEN4 Generic clock generator 4 0x5 GCLKGEN5 Generic clock generator 5 0x6 GCLKGEN6 Generic clock generator 6 0x7 GCLKGEN7 Generic clock generator 7 0x8 GCLKGEN8 Generic clock generator 8 0x9-0xF Reserved z Bits 7:6 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 5:0 - ID[5:0]: Generic Clock Selection ID These bits select the generic clock that will be configured. The value of the ID bit group versus module instance is shown in Table 13-4. Table 13-4. Generic Clock Selection ID Value Name Description 0x00 GCLK_DFLL48M_REF DFLL48M Reference 0x01 GCLK_DPLL FDPLL96M input clock source for reference 0x02 GCLK_DPLL_32K FDPLL96M 32kHz clock for FDPLL96M internal lock timer 0x03 GCLK_WDT WDT 0x04 GCLK_RTC RTC 0x05 GCLK_EIC EIC 0x06 GCLK_USB USB 0x07 GCLK_EVSYS_CHANNEL_0 EVSYS_CHANNEL_0 0x08 GCLK_EVSYS_CHANNEL_1 EVSYS_CHANNEL_1 0x09 GCLK_EVSYS_CHANNEL_2 EVSYS_CHANNEL_2 0x0A GCLK_EVSYS_CHANNEL_3 EVSYS_CHANNEL_3 0x0B GCLK_EVSYS_CHANNEL_4 EVSYS_CHANNEL_4 0x0C GCLK_EVSYS_CHANNEL_5 EVSYS_CHANNEL_5 0x0D GCLK_EVSYS_CHANNEL_6 EVSYS_CHANNEL_6 0x0E GCLK_EVSYS_CHANNEL_7 EVSYS_CHANNEL_7 0x0F GCLK_EVSYS_CHANNEL_8 EVSYS_CHANNEL_8 0x10 GCLK_EVSYS_CHANNEL_9 EVSYS_CHANNEL_9 0x11 GCLK_EVSYS_CHANNEL_10 EVSYS_CHANNEL_10 0x12 GCLK_EVSYS_CHANNEL_11 EVSYS_CHANNEL_11 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 102 Table 13-4. Generic Clock Selection ID (Continued) Value Name Description 0x13 GCLK_SERCOMx_SLOW SERCOMx_SLOW 0x14 GCLK_SERCOM0_CORE SERCOM0_CORE 0x15 GCLK_SERCOM1_CORE SERCOM1_CORE 0x16 GCLK_SERCOM2_CORE SERCOM2_CORE 0x17 GCLK_SERCOM3_CORE SERCOM3_CORE 0x18 GCLK_SERCOM4_CORE SERCOM4_CORE 0x19 GCLK_SERCOM5_CORE SERCOM5_CORE 0x1A GCLK_TCC0, GCLK_TCC1 TCC0,TCC1 0x1B GCLK_TCC2, GCLK_TC3 TCC2,TC3 0x1C GCLK_TC4, GCLK_TC5 TC4,TC5 0x1D Reserved 0x1E GCLK_ADC ADC 0x1F GCLK_AC_DIG AC_DIG 0x20 GCLK_AC_ANA AC_ANA 0x21 Reserved 0x22 GCLK_PTC PTCReserved 0x23 Reserved 0x24 Reserved 0x25-0x3F Reserved A power reset will reset the CLKCTRL register for all IDs, including the RTC. If the WRTLOCK bit of the corresponding ID is zero and the ID is not the RTC, a user reset will reset the CLKCTRL register for this ID. After a power reset, the reset value of the CLKCTRL register versus module instance is as shown in Table 13-5. Table 13-5. CLKCTRL Reset Value after a Power Reset Module Instance Reset Value after Power Reset CLKCTRL.GEN CLKCTRL.CLKEN CLKCTRL.WRTLOCK 0x00 0x00 0x00 WDT 0x02 0x01 if WDT Enable bit in NVM User Row written to one 0x00 if WDT Enable bit in NVM User Row written to zero 0x01 if WDT Always-On bit in NVM User Row written to one 0x00 if WDT Always-On bit in NVM User Row written to zero Others 0x00 0x00 0x00 RTC Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 103 After a user reset, the reset value of the CLKCTRL register versus module instance is as shown in Table 13-6. Table 13-6. CLKCTRL Reset Value after a User Reset Module Instance Reset Value after a User Reset CLKCTRL.GEN CLCTRL.CLKEN CLKCTRL.WRTLOCK 0x00 if WRTLOCK=0 and CLKEN=0 No change if WRTLOCK=1 or CLKEN=1 0x00 if WRTLOCK=0 and CLKEN=0 No change if WRTLOCK=1 or CLKEN=1 No change WDT 0x02 if WRTLOCK=0 No change if WRTLOCK=1 If WRTLOCK=0 0x01 if WDT Enable bit in NVM User Row written to one 0x00 if WDT Enable bit in NVM User Row written to zero If WRTLOCK=1 no change No change Others 0x00 if WRTLOCK=0 No change if WRTLOCK=1 0x00 if WRTLOCK=0 No change if WRTLOCK=1 No change RTC Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 104 13.8.4 Generic Clock Generator Control This register allows the user to configure one of the generic clock generators, as specified in the GENCTRL.ID bit group. To write to the GENCTRL register, do a 32-bit write with all configurations and the ID. To read the GENCTRL register, first do an 8-bit write to the GENCTRL.ID bit group with the ID of the generic clock generator whose configuration is to be read, and then read the GENCTRL register. Name: GENCTRL Offset: 0x4 Reset: 0x00000000 Property: Write-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 RUNSTDBY DIVSEL OE OOV IDC GENEN Access R R R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 SRC[4:0] Access R R R R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ID[3:0] Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 31:22 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 21 - RUNSTDBY: Run in Standby This bit is used to keep the generic clock generator running when it is configured to be output to its dedicated GCLK_IO pin. If GENCTRL.OE is zero, this bit has no effect and the generic clock generator will only be running if a peripheral requires the clock. 0: The generic clock generator is stopped in standby and the GCLK_IO pin state (one or zero) will be dependent on the setting in GENCTRL.OOV. 1: The generic clock generator is kept running and output to its dedicated GCLK_IO pin during standby mode. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 105 z Bit 20 - DIVSEL: Divide Selection This bit is used to decide how the clock source used by the generic clock generator will be divided. If the clock source should not be divided, the DIVSEL bit must be zero and the GENDIV.DIV value for the corresponding generic clock generator must be zero or one. 0: The generic clock generator equals the clock source divided by GENDIV.DIV. 1: The generic clock generator equals the clock source divided by 2^(GENDIV.DIV+1). z Bit 19 - OE: Output Enable This bit is used to enable output of the generated clock to GCLK_IO when GCLK_IO is not selected as a source in the GENCLK.SRC bit group. 0: The generic clock generator is not output. 1: The generic clock generator is output to the corresponding GCLK_IO, unless the corresponding GCLK_IO is selected as a source in the GENCLK.SRC bit group. z Bit 18 - OOV: Output Off Value This bit is used to control the value of GCLK_IO when GCLK_IO is not selected as a source in the GENCLK.SRC bit group. 0: The GCLK_IO will be zero when the generic clock generator is turned off or when the OE bit is zero. 1: The GCLK_IO will be one when the generic clock generator is turned off or when the OE bit is zero. z Bit 17 - IDC: Improve Duty Cycle This bit is used to improve the duty cycle of the generic clock generator when odd division factors are used. 0: The generic clock generator duty cycle is not 50/50 for odd division factors. 1: The generic clock generator duty cycle is 50/50. z Bit 16 - GENEN: Generic Clock Generator Enable This bit is used to enable and disable the generic clock generator. 0: The generic clock generator is disabled. 1: The generic clock generator is enabled. z Bits 15:13 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 12:8 - SRC[4:0]: Source Select These bits define the clock source to be used as the source for the generic clock generator, as shown in Table 137. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 106 Table 13-7. Source Select Value Name Description 0x00 XOSC XOSC oscillator output 0x01 GCLKIN Generator input pad 0x02 GCLKGEN1 Generic clock generator 1 output 0x03 OSCULP32K OSCULP32K oscillator output 0x04 OSC32K OSC32K oscillator output 0x05 XOSC32K XOSC32K oscillator output 0x06 OSC8M OSC8M oscillator output 0x07 DFLL48M DFLL48M output 0x08 FDPLL96M FDPLL96M output 0x09-0x1F Reserved Reserved for future use z Bits 7:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 3:0 - ID[3:0]: Generic Clock Generator Selection These bits select the generic clock generator that will be configured or read. The value of the ID bit group versus which generic clock generator is configured is shown in Table 13-8. Table 13-8. Generic Clock Generator Selection Value Name Description 0x0 GCLKGEN0 Generic clock generator 0 0x1 GCLKGEN1 Generic clock generator 1 0x2 GCLKGEN2 Generic clock generator 2 0x3 GCLKGEN3 Generic clock generator 3 0x4 GCLKGEN4 Generic clock generator 4 0x5 GCLKGEN5 Generic clock generator 5 0x6 GCLKGEN6 Generic clock generator 6 0x7 GCLKGEN7 Generic clock generator 7 0x8 GCLKGEN8 Generic clock generator 8 0x9-0xF Reserved A power reset will reset the GENCTRL register for all IDs, including the generic clock generator used by the RTC. If a generic clock generator ID other than generic clock generator 0 is not a source of a "locked" generic clock or a source of the RTC generic clock, a user reset will reset the GENCTRL for this ID. After a power reset, the reset value of the GENCTRL register is as shown in Table 13-9. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 107 Table 13-9. GENCTRL Reset Value after a Power Reset GCLK Generator ID Reset Value after a Power Reset 0x00 0x00010600 0x01 0x00000001 0x02 0x00010302 0x03 0x00000003 0x04 0x00000004 0x05 0x00000005 0x06 0x00000006 0x07 0x00000007 0x08 0x00000008 After a user reset, the reset value of the GENCTRL register is as shown in Table 13-10. Table 13-10. GENCTRL Reset Value after a User Reset GCLK Generator ID Reset Value after a User Reset 0x00 0x00010600 0x01 0x00000001 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one 0x02 0x00010302 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one 0x03 0x00000003 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one 0x04 0x00000004 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one 0x05 0x00000005 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one 0x06 0x00000006 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one 0x07 0x00000007 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one 0x08 0x00000008 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 108 13.8.5 Generic Clock Generator Division This register allows the user to configure one of the generic clock generators, as specified in the GENDIV.ID bit group. To write to the GENDIV register, do a 32-bit write with all configurations and the ID. To read the GENDIV register, first do an 8-bit write to the GENDIV.ID bit group with the ID of the generic clock generator whose configuration is to be read, and then read the GENDIV register. Name: GENDIV Offset: 0x8 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DIV[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DIV[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ID[3:0] Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 31:24 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 23:8 - DIV[15:0]: Division Factor These bits apply a division on each selected generic clock generator. The number of DIV bits each generator has can be seen in Table 13-11. Writes to bits above the specified number will be ignored. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 109 Table 13-11. Division Factor Generator Division Factor Bits Generic clock generator 0 8 division factor bits - DIV[7:0] Generic clock generator 1 16 division factor bits - DIV[15:0] Generic clock generators 2 5 division factor bits - DIV[4:0] Generic clock generators 3 - 8 8 division factor bits - DIV[7:0] z Bits 7:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 3:0 - ID[3:0]: Generic Clock Generator Selection These bits select the generic clock generator on which the division factor will be applied, as shown in Table 13-12. Table 13-12. Generic Clock Generator Selection Values Description 0x0 Generic clock generator 0 0x1 Generic clock generator 1 0x2 Generic clock generator 2 0x3 Generic clock generator 3 0x4 Generic clock generator 4 0x5 Generic clock generator 5 0x6 Generic clock generator 6 0x7 Generic clock generator 7 0x8 Generic clock generator 8 0x9-0xF Reserved A power reset will reset the GENDIV register for all IDs, including the generic clock generator used by the RTC. If a generic clock generator ID other than generic clock generator 0 is not a source of a "locked" generic clock or a source of the RTC generic clock, a user reset will reset the GENDIV for this ID. After a power reset, the reset value of the GENDIV register is as shown in Table 13-13. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 110 Table 13-13. GENDIV Reset value after a Power Reset GCLK Generator ID Reset Value after a Power Reset 0x00 0x00000000 0x01 0x00000001 0x02 0x00000002 0x03 0x00000003 0x04 0x00000004 0x05 0x00000005 0x06 0x00000006 0x07 0x00000007 0x08 0x00000008 After a user reset, the reset value of the GENDIV register is as shown in Table 13-14. Table 13-14. GENDIV Reset Value after a User Reset GCLK Generator ID Reset Value after a User Reset 0x00 0x00000000 0x01 0x00000001 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one 0x02 0x00000002 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one 0x03 0x00000003 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one 0x04 0x00000004 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one 0x05 0x00000005 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one 0x06 0x00000006 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one 0x07 0x00000007 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one 0x08 0x00000008 if the generator is not used by the RTC and not a source of a 'locked' generic clock No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 111 14. 14.1 PM - Power Manager Overview The Power Manager (PM) controls the reset, clock generation and sleep modes of the microcontroller. Utilizing a main clock chosen from a large number of clock sources from the GCLK, the clock controller provides synchronous system clocks to the CPU and the modules connected to the AHB and the APBx bus. The synchronous system clocks are divided into a number of clock domains; one for the CPU and AHB and one for each APBx. Any synchronous system clock can be changed at run-time during normal operation. The clock domains can run at different speeds, enabling the user to save power by running peripherals at a relatively low clock frequency, while maintaining high CPU performance. In addition, the clock can be masked for individual modules, enabling the user to minimize power consumption. Before entering the STANDBY sleep mode the user must make sure that a significant amount of clocks and peripherals are disabled, so that the voltage regulator is not overloaded. This is because during STANDBY sleep mode the internal voltage regulator will be in low power mode. Various sleep modes and clock gating are provided in order to fit power consumption requirements. This enables the microcontroller to stop unused modules to save power. In ACTIVE mode, the CPU is executing application code. When the device enters a sleep mode, program execution is stopped and some modules and clock domains are automatically switched off by the PM according to the sleep mode. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals and all enabled reset sources can restore the microcontroller from a sleep mode to ACTIVE mode. The PM also contains a reset controller, which collects all possible reset sources. It issues a microcontroller reset and sets the device to its initial state, and allows the reset source to be identified by software. 14.2 Features z Reset control Reset the microcontroller and set it to an initial state according to the reset source Multiple reset sources z Power reset sources: POR, BOD12, BOD33 z User reset sources: External reset (RESET), Watchdog Timer reset, software reset z Reset status register for reading the reset source from the application code z z z Clock control Controls CPU, AHB and APB system clocks z Multiple clock sources and division factor from GCLK z Clock prescaler with 1x to 128x division z Safe run-time clock switching from GCLK z Module-level clock gating through maskable peripheral clocks z z Power management control z z Sleep modes: IDLE, STANDBY SleepWalking support on GCLK clocks Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 112 14.3 Block Diagram Figure 14-1. PM Block Diagram POWER MANAGER CLK_APB GCLK SYNCHRONOUS CLOCK CONTROLLER CLK_AHB PERIPHERALS CLK_CPU SLEEP MODE CONTROLLER CPU BOD12 USER RESET BOD33 POWER RESET POR WDT RESET CONTROLLER CPU RESET RESET SOURCES 14.4 Signal Description Signal Name Type Description RESET Digital input External reset Refer to "I/O Multiplexing and Considerations" on page 12 for details on the pin mapping for this peripheral. One signal can be mapped on several pins. 14.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 14.5.1 I/O Lines Not applicable. 14.5.2 Power Management Not applicable. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 113 14.5.3 Clocks The PM bus clock (CLK_PM_APB) can be enabled and disabled in the power manager, and the default state of CLK_PM_APB can be found in Table 14-1. If this clock is disabled in the Power Manager, it can only be re-enabled by a reset. A generic clock (GCLK_MAIN) is required to generate the main clock. The clock source for GCLK_MAIN is configured by default in the Generic Clock Controller, and can be re-configured by the user if needed. Refer to "GCLK - Generic Clock Controller" on page 90 for details. 14.5.3.1 Main Clock The main clock (CLK_MAIN) is the common source for the synchronous clocks. This is fed into the common 8-bit prescaler that is used to generate synchronous clocks to the CPU, AHB and APBx modules. 14.5.3.2 CPU Clock The CPU clock (CLK_CPU) is routed to the CPU. Halting the CPU clock inhibits the CPU from executing instructions. 14.5.3.3 AHB Clock The AHB clock (CLK_AHB) is the root clock source used by peripherals requiring an AHB clock. The AHB clock is always synchronous to the CPU clock and has the same frequency, but may run even when the CPU clock is turned off. A clock gate is inserted from the common AHB clock to any AHB clock of a peripheral. 14.5.3.4 APBx Clocks The APBx clock (CLK_APBX) is the root clock source used by modules requiring a clock on the APBx bus. The APBx clock is always synchronous to the CPU clock, but can be divided by a prescaler, and will run even when the CPU clock is turned off. A clock gater is inserted from the common APB clock to any APBx clock of a module on APBx bus. 14.5.4 DMA Not applicable. 14.5.5 Interrupts The interrupt request line is connected to the Interrupt Controller. Using the PM interrupt requires the Interrupt Controller to be configured first. Refer to "Nested Vector Interrupt Controller" on page 29 for details. 14.5.6 Events Not applicable. 14.5.7 Debug Operation When the CPU is halted in debug mode, the PM continues normal operation. In sleep mode, the clocks generated from the PM are kept running to allow the debugger accessing any modules. As a consequence, power measurements are not possible in debug mode. 14.5.8 Register Access Protection All registers with write access are optionally write-protected by the Peripheral Access Controller (PAC), except the following registers: z Interrupt Flag register (INTFLAG). Refer to INTFLAG for details z Reset Cause register (RCAUSE). Refer to RCAUSE for details Write-protection is denoted by the Write-Protection property in the register description. Write-protection does not apply for accesses through an external debugger. Refer to "PAC - Peripheral Access Controller" on page 36 for details. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 114 14.5.9 Analog Connections Not applicable. 14.6 Functional Description 14.6.1 Principle of Operation 14.6.1.1 Synchronous Clocks The GCLK_MAIN clock from GCLK module provides the source for the main clock, which is the common root for the synchronous clocks for the CPU and APBx modules. The main clock is divided by an 8-bit prescaler, and each of the derived clocks can run from any tapping off this prescaler or the undivided main clock, as long as fCPU fAPBx. The synchronous clock source can be changed on the fly to respond to varying load in the application. The clocks for each module in each synchronous clock domain can be individually masked to avoid power consumption in inactive modules. Depending on the sleep mode, some clock domains can be turned off (see Table 14-4 on page 119). 14.6.1.2 Reset Controller The Reset Controller collects the various reset sources and generates reset for the device. The device contains a poweron-reset (POR) detector, which keeps the system reset until power is stable. This eliminates the need for external reset circuitry to guarantee stable operation when powering up the device. 14.6.1.3 Sleep Mode Controller In ACTIVE mode, all clock domains are active, allowing software execution and peripheral operation. The PM Sleep Mode Controller allows the user to choose between different sleep modes depending on application requirements, to save power (see Table 14-4 on page 119). 14.6.2 Basic Operation 14.6.2.1 Initialization After a power-on reset, the PM is enabled and the Reset Cause (RCAUSE - refer to RCAUSE for details) register indicates the POR source. The default clock source of the GCLK_MAIN clock is started and calibrated before the CPU starts running. The GCLK_MAIN clock is selected as the main clock without any division on the prescaler. The device is in the ACTIVE mode. By default, only the necessary clocks are enabled (see Table 14-1). 14.6.2.2 Enabling, Disabling and Resetting The PM module is always enabled and can not be reset. 14.6.2.3 Selecting the Main Clock Source Refer to "GCLK - Generic Clock Controller" on page 90 for details on how to configure the main clock source. 14.6.2.4 Selecting the Synchronous Clock Division Ratio The main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks. By default, the synchronous clocks run on the undivided main clock. The user can select a prescaler division for the CPU clock by writing the CPU Prescaler Selection bits in the CPU Select register (CPUSEL.CPUDIV), resulting in a CPU clock frequency determined by this equation: f main f CPU = ---------------------CPUDIV 2 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 115 Similarly, the clock for the APBx can be divided by writing their respective registers (APBxSEL.APBxDIV). To ensure correct operation, frequencies must be selected so that fCPU fAPBx. Also, frequencies must never exceed the specified maximum frequency for each clock domain. Note that the AHB clock is always equal to the CPU clock. CPUSEL and APBxSEL can be written without halting or disabling peripheral modules. Writing CPUSEL and APBxSEL allows a new clock setting to be written to all synchronous clocks at the same time. It is possible to keep one or more clocks unchanged. This way, it is possible to, for example, scale the CPU speed according to the required performance, while keeping the APBx frequency constant. Figure 14-2. Synchronous Clock Selection and Prescaler Sleep Controller Sleep mode APBCMASK Clock gate APBCDIV APBBDIV Clock gate Clock gate Clock gate CLK_APBB CLK_PERIPHERAL_APBB_n CLK_PERIPHERAL_APBB_1 CLK_PERIPHERAL_APBB_0 APBAMASK Clock gate GCLK_MAIN CLK_PERIPHERAL_APBC_n CLK_PERIPHERAL_APBC_1 CLK_PERIPHERAL_APBC_0 APBBMASK Clock gate GCLK Clock gate Clock gate Clock gate CLK_APBC Clock gate Clock gate Clock gate CLK_PERIPHERAL_APBA_n CLK_PERIPHERAL_APBA_1 CLK_PERIPHERAL_APBA_0 Clock gate Clock gate Clock gate CLK_PERIPHERAL_AHB_n CLK_PERIPHERAL_AHB_1 CLK_PERIPHERAL_AHB_0 CLK_APBA CLK_MAIN APBADIV Prescaler AHBMASK Clock gate CLK_AHB Clock gate CLK_CPU CPUDIV 14.6.2.5 Clock Ready Flag There is a slight delay from when CPUSEL and APBxSEL are written until the new clock setting becomes effective. During this interval, the Clock Ready flag in the Interrupt Flag Status and Clear register (INTFLAG.CKRDY) will read as zero. If CKRDY in the INTENSET register is written to one, the Power Manager interrupt can be triggered when the new clock setting is effective. CPUSEL must not be re-written while CKRDY is zero, or the system may become unstable or hang. 14.6.2.6 Peripheral Clock Masking It is possible to disable or enable the clock for a peripheral in the AHB or APBx clock domain by writing the corresponding bit in the Clock Mask register (APBxMASK - refer to APBAMASK for details) to zero or one. Refer to Table 14-1 for the default state of each of the peripheral clocks. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 116 Table 14-1. Peripheral Clock Default State Peripheral Clock Default State CLK_PAC0_APB Enabled CLK_PM_APB Enabled CLK_SYSCTRL_APB Enabled CLK_GCLK_APB Enabled CLK_WDT_APB Enabled CLK_RTC_APB Enabled CLK_EIC_APB Enabled CLK_PAC1_APB Enabled CLK_DSU_APB Enabled CLK_NVMCTRL_APB Enabled CLK_PORT_APB Enabled CLK_HMATRIX_APB Enabled CLK_PAC2_APB Disabled CLK_SERCOMx_APB Disabled CLK_TCx_APB Disabled CLK_ADC_APB Enabled CLK_AC_APB Disabled CLK_PTC_APB Disabled CLK_USB_APB Enabled CLK_DMAC_APB Enabled CLK_TCC_APB Disabled CLK_RFCTRL_APB Disabled When the APB clock for a module is not provided its registers cannot be read or written. The module can be re-enabled later by writing the corresponding mask bit to one. A module may be connected to several clock domains (for instance, AHB and APB), in which case it will have several mask bits. Note that clocks should only be switched off if it is certain that the module will not be used. Switching off the clock for the NVM Controller (NVMCTRL) will cause a problem if the CPU needs to read from the flash memory. Switching off the clock to the Power Manager (PM), which contains the mask registers, or the corresponding APBx bridge, will make it impossible to write the mask registers again. In this case, they can only be re-enabled by a system reset. 14.6.2.7 Reset Controller The latest reset cause is available in RCAUSE, and can be read during the application boot sequence in order to determine proper action. There are two groups of reset sources: z Power Reset: Resets caused by an electrical issue. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 117 z User Reset: Resets caused by the application. The table below lists the parts of the device that are reset, depending on the reset type. Table 14-2. Effects of the Different Reset Events Power Reset User Reset POR, BOD12, BOD33 External Reset WDT Reset, SysResetReq RTC All the 32kHz sources WDT with ALWAYSON feature Generic Clock with WRTLOCK feature Y N N Debug logic Y Y N Others Y Y Y The external reset is generated when pulling the RESET pin low. This pin has an internal pull-up, and does not need to be driven externally during normal operation. The POR, BOD12 and BOD33 reset sources are generated by their corresponding module in the System Controller Interface (SYSCTRL). The WDT reset is generated by the Watchdog Timer. The System Reset Request (SysResetReq) is a software reset generated by the CPU when asserting the SYSRESETREQ bit located in the Reset Control register of the CPU (See the ARM(R) Cortex(R) Technical Reference Manual on http://www.arm.com). Figure 14-3. Reset Controller RESET CONTROLLER BOD12 BOD33 POR RTC 32kHz clock sources WDT with ALWAYSON Generic Clock with WRTLOCK Debug Logic RESET WDT Others CPU RESET SOURCES RCAUSE Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 118 14.6.2.8 Sleep Mode Controller Sleep mode is activated by the Wait For Interrupt instruction (WFI). The Idle bits in the Sleep Mode register (SLEEP.IDLE) and the SLEEPDEEP bit of the System Control register of the CPU should be used as argument to select the level of the sleep mode. There are two main types of sleep mode: z IDLE mode: The CPU is stopped. Optionally, some synchronous clock domains are stopped, depending on the IDLE argument. Regulator operates in normal mode. z STANDBY mode: All clock sources are stopped, except those where the RUNSTDBY bit is set. Regulator operates in low-power mode. Before entering standby mode the user must make sure that a significant amount of clocks and peripherals are disabled, so that the voltage regulator is not overloaded. Table 14-3. Sleep Mode Entry and Exit Table Mode Level 0 IDLE 1 2 1. 2. Wake-Up Sources Synchronous(2) (APB, AHB), asynchronous(1) SCR.SLEEPDEEP = 0 SLEEP.IDLE=Level WFI Synchronous (APB), asynchronous Asynchronous SCR.SLEEPDEEP = 1 WFI STANDBY Notes: Mode Entry Asynchronous Asynchronous: interrupt generated on generic clock or external clock or external event. Synchronous: interrupt generated on the APB clock. Table 14-4. Sleep Mode Overview Sleep Mode CPU Clock AHB Clock APB Clock Oscillators ONDEMAND = 0 ONDEMAND = 1 RUNSTDBY=0 RUNSTDBY=1 RUNSTDBY=0 RUNSTDBY=1 Main Clock Regulator Mode RAM Mode Idle 0 Stop Run Run Run Run Run if requested Run if requested Run Normal Normal Idle 1 Stop Stop Run Run Run Run if requested Run if requested Run Normal Normal Idle 2 Stop Stop Stop Run Run Run if requested Run if requested Run Normal Normal Standby Stop Stop Stop Stop Run Stop Run if requested Stop Low power Low power IDLE Mode The IDLE modes allow power optimization with the fastest wake-up time. The CPU is stopped. To further reduce power consumption, the user can disable the clocking of modules and clock sources by configuring the SLEEP.IDLE bit group. The module will be halted regardless of the bit settings of the mask registers in the Power Manager (PM.AHBMASK, PM.APBxMASK). Regulator operates in normal mode. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 119 z Entering IDLE mode: The IDLE mode is entered by executing the WFI instruction. Additionally, if the SLEEPONEXIT bit in the ARM Cortex System Control register (SCR) is set, the IDLE mode will also be entered when the CPU exits the lowest priority ISR. This mechanism can be useful for applications that only require the processor to run when an interrupt occurs. Before entering the IDLE mode, the user must configure the IDLE mode configuration bit group and must write a zero to the SCR.SLEEPDEEP bit. z Exiting IDLE mode: The processor wakes the system up when it detects the occurrence of any interrupt that is not masked in the NVIC Controller with sufficient priority to cause exception entry. The system goes back to the ACTIVE mode. The CPU and affected modules are restarted. STANDBY Mode The STANDBY mode allows achieving very low power consumption. In this mode, all clocks are stopped except those which are kept running if requested by a running module or have the ONDEMAND bit set to zero. For example, the RTC can operate in STANDBY mode. In this case, its Generic Clock clock source will also be enabled. The regulator and the RAM operate in low-power mode. A SLEEPONEXIT feature is also available. z Entering STANDBY mode: This mode is entered by executing the WFI instruction with the SCR.SLEEPDEEP bit of the CPU is written to 1. z Exiting STANDBY mode: Any peripheral able to generate an asynchronous interrupt can wake up the system. For example, a module running on a Generic clock can trigger an interrupt. When the enabled asynchronous wake-up event occurs and the system is woken up, the device will either execute the interrupt service routine or continue the normal program execution according to the Priority Mask Register (PRIMASK) configuration of the CPU. 14.6.3 SleepWalking SleepWalking is the capability for a device to temporarily wakeup clocks for peripheral to perform a task without wakingup the CPU in STANDBY sleep mode. At the end of the sleepwalking task, the device can either be waken-up by an interrupt (from a peripheral involved in SleepWalking) or enter again into STANDBY sleep mode. In Atmel | SMART SAM R21 devices, SleepWalking is supported only on GCLK clocks by using the on-demand clock principle of the clock sources. Refer to "On-demand, Clock Requests" on page 88 for more details. 14.6.4 DMA Operation Not applicable. 14.6.5 Interrupts The peripheral has the following interrupt sources: z Clock Ready flag Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the peripheral is reset. An interrupt flag is cleared by writing a one to the corresponding bit in the INTFLAG register. Each peripheral can have one interrupt request line per interrupt source or one common interrupt request line for all the interrupt sources. Refer to "Nested Vector Interrupt Controller" on page 29 for details. If the peripheral has one common interrupt request line for all the interrupt sources, the user must read the INTFLAG register to determine which interrupt condition is present. 14.6.6 Events Not applicable. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 120 14.6.7 Sleep Mode Operation In all IDLE sleep modes, the power manager is still running on the selected main clock. In STANDDBY sleep mode, the power manager is frozen and is able to go back to ACTIVE mode upon any asynchronous interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 121 14.7 Register Summary Table 14-5. Register Summary Offset Name Bit Pos. 0x00 CTRL 7:0 0x01 SLEEP 7:0 0x02 ... 0x07 Reserved 0x08 CPUSEL 7:0 CPUDIV[2:0] IDLE[1:0] 0x09 APBASEL 7:0 APBADIV[2:0] 0x0A APBBSEL 7:0 APBBDIV[2:0] 0x0B APBCSEL 7:0 APBCDIV[2:0] 0x0C ... 0x13 Reserved 0x14 0x15 0x16 7:0 AHBMASK 0x17 USB DMAC NVMCTRL DSU HPB2 HPB1 HPB0 EIC RTC WDT GCLK SYSCTRL PM PAC0 USB DMAC PORT NVMCTRL DSU PAC1 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS PAC2 15:8 TC5 TC4 TC3 TCC2 TCC1 TCC0 23:16 RFCTRL AC ADC 15:8 23:16 31:24 0x18 7:0 0x19 15:8 0x1A APBAMASK 0x1B 23:16 31:24 0x1C 7:0 0x1D 15:8 0x1E APBBMASK 23:16 0x1F 31:24 0x20 7:0 0x21 0x22 APBCMASK 0x23 SERCOM5 SERCOM4 PTC 31:24 0x24 ... 0x33 Reserved 0x34 INTENCLR 7:0 CKRDY 0x35 INTENSET 7:0 CKRDY 0x36 INTFLAG 7:0 CKRDY 0x37 Reserved 0x38 RCAUSE 7:0 SYST WDT EXT BOD33 BOD12 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 POR 122 14.8 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Exception for APBASEL, APBBSEL and APBCSEL: These registers must only be accessed with 8-bit access. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protected property in each individual register description. Refer to "Register Access Protection" on page 114 for details. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 123 14.8.1 Control Name: CTRL Offset: 0x00 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 7:0 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 124 14.8.2 Sleep Mode Name: SLEEP Offset: 0x01 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 IDLE[1:0] Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 1:0 - IDLE[1:0]: Idle Mode Configuration These bits select the Idle mode configuration after a WFI instruction. Table 14-6. Idle Mode Configuration IDLE[1:0] Name 0x0 CPU The CPU clock domain is stopped 0x1 AHB The CPU and AHB clock domains are stopped 0x2 APB The CPU, AHB and APB clock domains are stopped 0x3 Description Reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 125 14.8.3 CPU Clock Select Name: CPUSEL Offset: 0x08 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 CPUDIV[2:0] Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 2:0 - CPUDIV[2:0]: CPU Prescaler Selection These bits define the division ratio of the main clock prescaler (2n). Table 14-7. CPU Prescaler Selection CPUDIV[2:0] Name Description 0x0 DIV1 Divide by 1 0x1 DIV2 Divide by 2 0x2 DIV4 Divide by 4 0x3 DIV8 Divide by 8 0x4 DIV16 Divide by 16 0x5 DIV32 Divide by 32 0x6 DIV64 Divide by 64 0x7 DIV128 Divide by 128 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 126 14.8.4 APBA Clock Select Name: APBASEL Offset: 0x09 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 APBADIV[2:0] Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 2:0 - APBADIV[2:0]: APBA Prescaler Selection These bits define the division ratio of the APBA clock prescaler (2n). Table 14-8. APBA Prescaler Selection APBADIV[2:0] Name Description 0x0 DIV1 Divide by 1 0x1 DIV2 Divide by 2 0x2 DIV4 Divide by 4 0x3 DIV8 Divide by 8 0x4 DIV16 Divide by 16 0x5 DIV32 Divide by 32 0x6 DIV64 Divide by 64 0x7 DIV128 Divide by 128 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 127 14.8.5 APBB Clock Select Name: APBBSEL Offset: 0x0A Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 APBBDIV[2:0] Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 2:0 - APBBDIV[2:0]: APBB Prescaler Selection These bits define the division ratio of the APBB clock prescaler (2n). Table 14-9. APBB Prescaler Selection APBBDIV[2:0] Name Description 0x0 DIV1 Divide by 1 0x1 DIV2 Divide by 2 0x2 DIV4 Divide by 4 0x3 DIV8 Divide by 8 0x4 DIV16 Divide by 16 0x5 DIV32 Divide by 32 0x6 DIV64 Divide by 64 0x7 DIV128 Divide by 128 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 128 14.8.6 APBC Clock Select Name: APBCSEL Offset: 0x0B Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 APBCDIV[2:0] Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 2:0 - APBCDIV[2:0]: APBC Prescaler Selection These bits define the division ratio of the APBC clock prescaler (2n). Table 14-10. APBC Prescaler Selection APBCDIV[2:0] Name Description 0x0 DIV1 Divide by 1 0x1 DIV2 Divide by 2 0x2 DIV4 Divide by 4 0x3 DIV8 Divide by 8 0x4 DIV16 Divide by 16 0x5 DIV32 Divide by 32 0x6 DIV64 Divide by 64 0x7 DIV128 Divide by 128 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 129 14.8.7 AHB Mask Name: AHBMASK Offset: 0x14 Reset: 0x0000007F Property: Write-Protected Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 USB DMAC NVMCTRL DSU HPB2 HPB1 HPB0 Access R R/W R/W R/W R/W R/W R/W R/W Reset 0 1 1 1 1 1 1 1 z Bits 31:7 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 6 - USB: USB AHB Clock Mask 0: The AHB clock for the USB is stopped. 1: The AHB clock for the USB is enabled. z Bit 5 - DMAC: DMAC AHB Clock Mask 0: The AHB clock for the DMAC is stopped. 1: The AHB clock for the DMAC is enabled. z Bit 4 - NVMCTRL: NVMCTRL AHB Clock Mask 0: The AHB clock for the NVMCTRL is stopped. 1: The AHB clock for the NVMCTRL is enabled. z Bit 3 - DSU: DSU AHB Clock Mask 0: The AHB clock for the DSU is stopped. 1: The AHB clock for the DSU is enabled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 130 z Bit 2 - HPB2: HPB2 AHB Clock Mask 0: The AHB clock for the HPB2 is stopped. 1: The AHB clock for the HPB2 is enabled. z Bit 1 - HPB1: HPB1 AHB Clock Mask 0: The AHB clock for the HPB1 is stopped. 1: The AHB clock for the HPB1 is enabled. z Bit 0 - HPB0: HPB0 AHB Clock Mask 0: The AHB clock for the HPB0 is stopped. 1: The AHB clock for the HPB0 is enabled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 131 14.8.8 APBA Mask Name: APBAMASK Offset: 0x18 Reset: 0x0000007F Property: Write-Protected Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 EIC RTC WDT GCLK SYSCTRL PM PAC0 Access R R/W R/W R/W R/W R/W R/W R/W Reset 0 1 1 1 1 1 1 1 z Bits 31:7 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 6 - EIC: EIC APB Clock Enable 0: The APBA clock for the EIC is stopped. 1: The APBA clock for the EIC is enabled. z Bit 5 - RTC: RTC APB Clock Enable 0: The APBA clock for the RTC is stopped. 1: The APBA clock for the RTC is enabled. z Bit 4 - WDT: WDT APB Clock Enable 0: The APBA clock for the WDT is stopped. 1: The APBA clock for the WDT is enabled. z Bit 3 - GCLK: GCLK APB Clock Enable 0: The APBA clock for the GCLK is stopped. 1: The APBA clock for the GCLK is enabled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 132 z Bit 2 - SYSCTRL: SYSCTRL APB Clock Enable 0: The APBA clock for the SYSCTRL is stopped. 1: The APBA clock for the SYSCTRL is enabled. z Bit 1 - PM: PM APB Clock Enable 0: The APBA clock for the PM is stopped. 1: The APBA clock for the PM is enabled. z Bit 0 - PAC0: PAC0 APB Clock Enable 0: The APBA clock for the PAC0 is stopped. 1: The APBA clock for the PAC0 is enabled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 133 14.8.9 APBB Mask Name: APBBMASK Offset: 0x1C Reset: 0x0000007F Property: Write-Protected Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 USB DMAC PORT NVMCTRL DSU PAC1 Access R R R/W R/W R/W R/W R/W R/W Reset 0 0 1 1 1 1 1 1 z Bits 31:6 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 5 - USB: USB APB Clock Enable 0: The APBB clock for the USB is stopped. 1: The APBB clock for the USB is enabled. z Bit 4 - DMAC: DMAC APB Clock Enable 0: The APBB clock for the DMAC is stopped. 1: The APBB clock for the DMAC is enabled. z Bit 3 - PORT: PORT APB Clock Enable 0: The APBB clock for the PORT is stopped. 1: The APBB clock for the PORT is enabled. z Bit 2 - NVMCTRL: NVMCTRL APB Clock Enable 0: The APBB clock for the NVMCTRL is stopped. 1: The APBB clock for the NVMCTRL is enabled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 134 z Bit 1 - DSU: DSU APB Clock Enable 0: The APBB clock for the DSU is stopped. 1: The APBB clock for the DSU is enabled. z Bit 0 - PAC1: PAC1 APB Clock Enable 0: The APBB clock for the PAC1 is stopped. 1: The APBB clock for the PAC1 is enabled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 135 14.8.10 APBC Mask Name: APBCMASK Offset: 0x20 Reset: 0x00010000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 AC ADC RFCTRL PTC Access R R R/W R R/W R R/W R/W Reset 0 0 0 0 0 0 0 1 Bit 15 14 13 12 11 10 9 8 TC5 TC4 TC3 TCC2 TCC1 TCC0 Access R R R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS PAC2 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Access Reset z Bits 31:22 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 21 - RFCTRL: RFCTRL APB Clock Enable 0: The APBC clock for the RFCTRL is stopped. 1: The APBC clock for the RFCTRL is enabled. z Bit 20 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 19 - PTC: PTC APB Clock Enable 0: The APBC clock for the PTC is stopped. 1: The APBC clock for the PTC is enabled. z Bit 18 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 136 z Bit 17 - AC: AC APB Clock Enable 0: The APBC clock for the AC is stopped. 1: The APBC clock for the AC is enabled. z Bit 16 - ADC: ADC APB Clock Enable 0: The APBC clock for the ADC is stopped. 1: The APBC clock for the ADC is enabled. z Bits 15:14 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 13 - TC5: TC5 APB Clock Enable 0: The APBC clock for the TC5 is stopped. 1: The APBC clock for the TC5 is enabled. z Bit 12 - TC4: TC4 APB Clock Enable 0: The APBC clock for the TC4 is stopped. 1: The APBC clock for the TC4 is enabled. z Bit 11 - TC3: TC3 APB Clock Enable 0: The APBC clock for the TC3 is stopped. 1: The APBC clock for the TC3 is enabled. z Bit 10 - TCC2: TCC2 APB Clock Enable 0: The APBC clock for the TCC2 is stopped. 1: The APBC clock for the TCC2 is enabled. z Bit 9 - TCC1: TCC1 APB Clock Enable 0: The APBC clock for the TCC1 is stopped. 1: The APBC clock for the TCC1 is enabled. z Bit 8 - TCC0: TCC0 APB Clock Enable 0: The APBC clock for the TCC0 is stopped. 1: The APBC clock for the TCC0 is enabled. z Bit 7 - SERCOM5: SERCOM5 APB Clock Enable 0: The APBC clock for the SERCOM5 is stopped. 1: The APBC clock for the SERCOM5 is enabled. z Bit 6 - SERCOM4: SERCOM4 APB Clock Enable 0: The APBC clock for the SERCOM4 is stopped. 1: The APBC clock for the SERCOM4 is enabled. z Bit 5 - SERCOM3: SERCOM3 APB Clock Enable 0: The APBC clock for the SERCOM3 is stopped. 1: The APBC clock for the SERCOM3 is enabled. z Bit 4 - SERCOM2: SERCOM2 APB Clock Enable 0: The APBC clock for the SERCOM2 is stopped. 1: The APBC clock for the SERCOM2 is enabled. z Bit 3 - SERCOM1: SERCOM1 APB Clock Enable 0: The APBC clock for the SERCOM1 is stopped. 1: The APBC clock for the SERCOM1 is enabled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 137 z Bit 2 - SERCOM0: SERCOM0 APB Clock Enable 0: The APBC clock for the SERCOM0 is stopped. 1: The APBC clock for the SERCOM0 is enabled. z Bit 1 - EVSYS: EVSYS APB Clock Enable 0: The APBC clock for the EVSYS is stopped. 1: The APBC clock for the EVSYS is enabled. z Bit 0 - PAC2: PAC2 APB Clock Enable 0: The APBC clock for the PAC2 is stopped. 1: The APBC clock for the PAC2 is enabled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 138 14.8.11 Interrupt Enable Clear This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register. Name: INTENCLR Offset: 0x34 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 CKRDY Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:1 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 0 - CKRDY: Clock Ready Interrupt Enable 0: The Clock Ready interrupt is disabled. 1: The Clock Ready interrupt is enabled and will generate an interrupt request when the Clock Ready Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Clock Ready Interrupt Enable bit and the corresponding interrupt request. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 139 14.8.12 Interrupt Enable Set This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Name: INTENSET Offset: 0x35 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 CKRDY Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:1 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 0 - CKRDY: Clock Ready Interrupt Enable 0: The Clock Ready interrupt is disabled. 1: The Clock Ready interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Clock Ready Interrupt Enable bit and enable the Clock Ready interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 140 14.8.13 Interrupt Flag Status and Clear Name: INTFLAG Offset: 0x36 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 CKRDY Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:1 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 0 - CKRDY: Clock Ready This flag is cleared by writing a one to the flag. This flag is set when the synchronous CPU and APBx clocks have frequencies as indicated in the CPUSEL and APBxSEL registers, and will generate an interrupt if INTENCLR/SET.CKRDY is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Clock Ready Interrupt flag. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 141 14.8.14 Reset Cause Name: RCAUSE Offset: 0x38 Reset: 0x01 Property: - Bit 7 6 5 4 SYST WDT EXT 3 2 1 0 BOD33 BOD12 POR Access R R R R R R R R Reset 0 0 0 0 0 0 0 1 z Bit 7 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 6 - SYST: System Reset Request This bit is set if a system reset request has been performed. Refer to the Cortex processor documentation for more details. z Bit 5 - WDT: Watchdog Reset This flag is set if a Watchdog Timer reset occurs. z Bit 4 - EXT: External Reset This flag is set if an external reset occurs. z Bit 3 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 2 - BOD33: Brown Out 33 Detector Reset This flag is set if a BOD33 reset occurs. z Bit 1 - BOD12: Brown Out 12 Detector Reset This flag is set if a BOD12 reset occurs. z Bit 0 - POR: Power On Reset This flag is set if a POR occurs. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 142 15. 15.1 SYSCTRL - System Controller Overview The System Controller (SYSCTRL) provides a user interface to the clock sources, brown out detectors, on-chip voltage regulator and voltage reference of the device. Through the interface registers, it is possible to enable, disable, calibrate and monitor the SYSCTRL sub-peripherals. All sub-peripheral statuses are collected in the Power and Clocks Status register (PCLKSR - refer to PCLKSR). They can additionally trigger interrupts upon status changes via the INTENSET (INTENSET), INTENCLR (INTENCLR) and INTFLAG (INTFLAG) registers. Additionally, BOD33 interrupts can be used to wake up the device from standby mode upon a programmed brown-out detection. 15.2 Features z 0.4-32MHz Crystal Oscillator (XOSC) Tunable gain control Programmable start-up time z Crystal or external input clock on XIN I/O z z z 32.768kHz Crystal Oscillator (XOSC32K) Automatic or manual gain control Programmable start-up time z Crystal or external input clock on XIN32 I/O z z z 32.768kHz High Accuracy Internal Oscillator (OSC32K) z z Frequency fine tuning Programmable start-up time z 32.768kHz Ultra Low Power Internal Oscillator (OSCULP32K) Ultra low power, always-on oscillator Frequency fine tuning z Calibration value loaded from Flash Factory Calibration at reset z z z 8MHz Internal Oscillator (OSC8M) Fast startup Output frequency fine tuning z 4/2/1MHz divided output frequencies available z Calibration value loaded from Flash Factory Calibration at reset z z z Digital Frequency Locked Loop (DFLL48M) Internal oscillator with no external components 48MHz output frequency z Operates standalone as a high-frequency programmable oscillator in open loop mode z Operates as an accurate frequency multiplier against a known frequency in closed loop mode z z z Fractional Digital Phase Locked Loop (FDPLL96M) 48MHz to 96MHz output clock frequency 32KHz to 2MHz input reference clock frequency range z Three possible sources for the reference clock z Adjustable proportional integral controller z Fractional part used to achieve 1/16th of reference clock step z z z 3.3V Brown-Out Detector (BOD33) Programmable threshold Threshold value loaded from Flash User Calibration at startup z Triggers resets or interrupts z Operating modes: z Continuous mode z z Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 143 z z Sampled mode for low power applications (programmable refresh frequency) Hysteresis z Internal Voltage Regulator system (VREG) Operating modes: z Normal mode z Low-power mode z With an internal non-configurable Brown-out detector (BOD12) z z Voltage Reference System (VREF) Bandgap voltage generator with programmable calibration value Temperature sensor z Bandgap calibration value loaded from Flash Factory Calibration at startup z z 15.3 Block Diagram Figure 15-1. SYSCTRL Block Diagram SYSCTRL XOSC XOSC32K OSC32K OSCILLATORS CONTROL OSCULP32K OSC8M DFLL48M FDPLL96M POWER MONITOR CONTROL BOD33 VOLTAGE REFERENCE CONTROL VOLTAGE REFERENCE SYSTEM STATUS (PCLKSR register) INTERRUPTS GENERATOR Interrupts Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 144 15.4 Signal Description Signal Name Types XIN Analog Input XOUT Analog Output XIN32 Analog Input XOUT32 Analog Output Description Multipurpose Crystal Oscillator or external clock generator input External Multipurpose Crystal Oscillator output 32kHz Crystal Oscillator or external clock generator input 32kHz Crystal Oscillator output The I/O lines are automatically selected when XOSC or XOSC32K are enabled. Refer to "Oscillator Pinout" on page 14. 15.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 15.5.1 I/O Lines I/O lines are configured by SYSCTRL when either XOSC or XOSC32K are enabled, and need no user configuration. 15.5.2 Power Management The SYSCTRL can continue to operate in any sleep mode where the selected source clock is running. The SYSCTRL interrupts can be used to wake up the device from sleep modes. The events can trigger other operations in the system without exiting sleep modes. Refer to "PM - Power Manager" on page 112 for details on the different sleep modes. 15.5.3 Clocks The SYSCTRL gathers controls for all device oscillators and provides clock sources to the Generic Clock Controller (GCLK). The available clock sources are: XOSC, XOSC32K, OSC32K, OSCULP32K, OSC8M, DFLL48M and FDPLL96M. The SYSCTRL bus clock (CLK_SYSCTRL_APB) can be enabled and disabled in the Power Manager, and the default state of CLK_SYSCTRL_APB can be found in the Peripheral Clock Masking section in the "PM - Power Manager" on page 112. The clock used by BOD33in sampled mode is asynchronous to the user interface clock (CLK_SYSCTRL_APB). Likewise, the DFLL48M control logic uses the DFLL oscillator output, which is also asynchronous to the user interface clock (CLK_SYSCTRL_APB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. Refer to "Synchronization" on page 159 for further details. 15.5.4 Interrupts The interrupt request line is connected to the Interrupt Controller. Using the SYSCTRL interrupts requires the Interrupt Controller to be configured first. Refer to "Nested Vector Interrupt Controller" on page 29 for details. 15.5.5 Debug Operation When the CPU is halted in debug mode, the SYSCTRL continues normal operation. If the SYSCTRL is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. If a debugger connection is detected by the system, BOD33 reset will be blocked. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 145 15.5.6 Register Access Protection All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the following registers: z Interrupt Flag Status and Clear register (INTFLAG - refer to INTFLAG) Write-protection is denoted by the Write-Protection property in the register description. When the CPU is halted in debug mode, all write-protection is automatically disabled. Write-protection does not apply for accesses through an external debugger. Refer to "PAC - Peripheral Access Controller" on page 36 for details. 15.5.7 Analog Connections When used, the 32.768kHz crystal must be connected between the XIN32 and XOUT32 pins, and the 0.4-32MHz crystal must be connected between the XIN and XOUT pins, along with any required load capacitors. For details on recommended oscillator characteristics and capacitor load, refer to the "Electrical Characteristics" on page 1055 for details. 15.6 Functional Description 15.6.1 Principle of Operation XOSC, XOSC32K, OSC32K, OSCULP32K, OSC8M, DFLL48M, FDPLL96M, BOD33, and VREF are configured via SYSCTRL control registers. Through this interface, the sub-peripherals are enabled, disabled or have their calibration values updated. The Power and Clocks Status register gathers different status signals coming from the sub-peripherals controlled by the SYSCTRL. The status signals can be used to generate system interrupts, and in some cases wake up the system from standby mode, provided the corresponding interrupt is enabled. The oscillator must be enabled to run. The oscillator is enabled by writing a one to the ENABLE bit in the respective oscillator control register, and disabled by writing a zero to the oscillator control register. In idle mode, the default operation of the oscillator is to run only when requested by a peripheral. In standby mode, the default operation of the oscillator is to stop. This behavior can be changed by the user, see below for details. The behavior of the oscillators in the different sleep modes is shown in Table 15-1 on page 146 Table 15-1. Behavior of the Oscillators Oscillator Idle 0, 1, 2 Standby XOSC Run on request Stop XOSC32K Run on request Stop OSC32K Run on request Stop OSCULP32K Run Run OSC8M Run on request Stop DFLL48M Run on request Stop FDPLL96M Run on request Stop To force an oscillator to always run in idle mode, and not only when requested by a peripheral, the oscillator ONDEMAND bit must be written to zero. The default value of this bit is one, and thus the default operation in idle mode is to run only when requested by a peripheral. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 146 To force the oscillator to run in standby mode, the RUNSTDBY bit must be written to one. The oscillator will then run in standby mode when requested by a peripheral (ONDEMAND is one). To force an oscillator to always run in standby mode, and not only when requested by a peripheral, the ONDEMAND bit must be written to zero and RUNSTDBY must be written to one. Table 15-2 on page 147 shows the behavior in the different sleep modes, depending on the settings of ONDEMAND and RUNSTDBY. Table 15-2. Behavior in the different sleep modes Sleep mode ONDEMAND RUNSTDBY Behavior Idle 0, 1, 2 0 X Run Idle 0, 1, 2 1 X Run when requested by a peripheral Standby 0 0 Stop Standby 0 1 Run Standby 1 0 Stop Standby 1 1 Run when requested by a peripheral Note that this does not apply to the OSCULP32K oscillator, which is always running and cannot be disabled. 15.6.2 External Multipurpose Crystal Oscillator (XOSC) Operation The XOSC can operate in two different modes: z External clock, with an external clock signal connected to the XIN pin z Crystal oscillator, with an external 0.4-32MHz crystal The XOSC can be used as a clock source for generic clock generators, as described in the "GCLK - Generic Clock Controller" on page 90. At reset, the XOSC is disabled, and the XIN/XOUT pins can be used as General Purpose I/O (GPIO) pins or by other peripherals in the system. When XOSC is enabled, the operating mode determines the GPIO usage. When in crystal oscillator mode, the XIN and XOUT pins are controlled by the SYSCTRL, and GPIO functions are overridden on both pins. When in external clock mode, only the XIN pin will be overridden and controlled by the SYSCTRL, while the XOUT pin can still be used as a GPIO pin. The XOSC is enabled by writing a one to the Enable bit in the External Multipurpose Crystal Oscillator Control register (XOSC.ENABLE). To enable the XOSC as a crystal oscillator, a one must be written to the XTAL Enable bit (XOSC.XTALEN). If XOSC.XTALEN is zero, external clock input will be enabled. When in crystal oscillator mode (XOSC.XTALEN is one), the External Multipurpose Crystal Oscillator Gain (XOSC.GAIN) must be set to match the external crystal oscillator frequency. If the External Multipurpose Crystal Oscillator Automatic Amplitude Gain Control (XOSC.AMPGC) is one, the oscillator amplitude will be automatically adjusted, and in most cases result in a lower power consumption. The XOSC will behave differently in different sleep modes based on the settings of XOSC.RUNSTDBY, XOSC.ONDEMAND and XOSC.ENABLE: Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 147 XOSC.RUNSTDBY XOSC.ONDEMAND XOSC.ENABLE Sleep Behavior - - 0 Disabled 0 0 1 Always run in IDLE sleep modes. Disabled in STANDBY sleep mode. 0 1 1 Only run in IDLE sleep modes if requested by a peripheral. Disabled in STANDBY sleep mode. 1 0 1 Always run in IDLE and STANDBY sleep modes. 1 1 1 Only run in IDLE or STANDBY sleep modes if requested by a peripheral. After a hard reset, or when waking up from a sleep mode where the XOSC was disabled, the XOSC will need a certain amount of time to stabilize on the correct frequency. This start-up time can be configured by changing the Oscillator Start-Up Time bit group (XOSC.STARTUP) in the External Multipurpose Crystal Oscillator Control register. During the start-up time, the oscillator output is masked to ensure that no unstable clock propagates to the digital logic. The External Multipurpose Crystal Oscillator Ready bit in the Power and Clock Status register (PCLKSR.XOSCRDY) is set when the user-selected startup time is over. An interrupt is generated on a zero-to-one transition on PCLKSR.XOSCRDY if the External Multipurpose Crystal Oscillator Ready bit in the Interrupt Enable Set register (INTENSET.XOSCRDY) is set. Note: Do not enter standby mode when an oscillator is in startup: Wait for the OSCxRDY bit in SYSCTRL.PCLKSR register to be set before going into standby mode. 15.6.3 32kHz External Crystal Oscillator (XOSC32K) Operation The XOSC32K can operate in two different modes: z External clock, with an external clock signal connected to XIN32 z Crystal oscillator, with an external 32.768kHz crystal connected between XIN32 and XOUT32 The XOSC32K can be used as a source for generic clock generators, as described in the "GCLK - Generic Clock Controller" on page 90. At power-on reset (POR) the XOSC32K is disabled, and the XIN32/XOUT32 pins can be used as General Purpose I/O (GPIO) pins or by other peripherals in the system. When XOSC32K is enabled, the operating mode determines the GPIO usage. When in crystal oscillator mode, XIN32 and XOUT32 are controlled by the SYSCTRL, and GPIO functions are overridden on both pins. When in external clock mode, only the XIN32 pin will be overridden and controlled by the SYSCTRL, while the XOUT32 pin can still be used as a GPIO pin. The external clock or crystal oscillator is enabled by writing a one to the Enable bit (XOSC32K.ENABLE) in the 32kHz External Crystal Oscillator Control register. To enable the XOSC32K as a crystal oscillator, a one must be written to the XTAL Enable bit (XOSC32K.XTALEN). If XOSC32K.XTALEN is zero, external clock input will be enabled. The oscillator is disabled by writing a zero to the Enable bit (XOSC32K.ENABLE) in the 32kHz External Crystal Oscillator Control register while keeping the other bits unchanged. Writing to the XOSC32K.ENABLE bit while writing to other bits may result in unpredictable behavior. The oscillator remains enabled in all sleep modes if it has been enabled beforehand. The start-up time of the 32kHz External Crystal Oscillator is selected by writing to the Oscillator Start-Up Time bit group (XOSC32K.STARTUP) in the in the 32kHz External Crystal Oscillator Control register. The SYSCTRL masks the oscillator output during the start-up time to ensure that no unstable clock propagates to the digital logic. The 32kHz External Crystal Oscillator Ready bit (PCLKSR.XOSC32KRDY) in the Power and Clock Status register is set when the user-selected startup time is over. An interrupt is generated on a zero-to-one transition of PCLKSR.XOSC32KRDY if the 32kHz External Crystal Oscillator Ready bit (INTENSET.XOSC32KRDY) in the Interrupt Enable Set Register is set. As a crystal oscillator usually requires a very long start-up time (up to one second), the 32kHz External Crystal Oscillator will keep running across resets, except for power-on reset (POR). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 148 XOSC32K can provide two clock outputs when connected to a crystal. The XOSC32K has a 32.768kHz output enabled by writing a one to the 32kHz External Crystal Oscillator 32kHz Output Enable bit (XOSC32K.EN32K) in the 32kHz External Crystal Oscillator Control register. XOSC32K.EN32K is only usable when XIN32 is connected to a crystal, and not when an external digital clock is applied on XIN32. Note: Do not enter standby mode when an oscillator is in startup: Wait for the OSCxRDY bit in SYSCTRL.PCLKSR register to be set before going into standby mode. 15.6.4 32kHz Internal Oscillator (OSC32K) Operation The OSC32K provides a tunable, low-speed and low-power clock source. The OSC32K can be used as a source for the generic clock generators, as described in the "GCLK - Generic Clock Controller" on page 90. The OSC32K is disabled by default. The OSC32K is enabled by writing a one to the 32kHz Internal Oscillator Enable bit (OSC32K.ENABLE) in the 32kHz Internal Oscillator Control register. It is disabled by writing a zero to OSC32K.ENABLE. The OSC32K has a 32.768kHz output enabled by writing a one to the 32kHz Internal Oscillator 32kHz Output Enable bit (OSC32K.EN32K). The frequency of the OSC32K oscillator is controlled by the value in the 32kHz Internal Oscillator Calibration bits (OSC32K.CALIB) in the 32kHz Internal Oscillator Control register. The OSC32K.CALIB value must be written by the user. Flash Factory Calibration values are stored in the NVM Software Calibration Area (refer to "NVM Software Calibration Area Mapping" on page 26). When writing to the Calibration bits, the user must wait for the PCLKSR.OSC32KRDY bit to go high before the value is committed to the oscillator. 15.6.5 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Operation The OSCULP32K provides a tunable, low-speed and ultra-low-power clock source. The OSCULP32K is factorycalibrated under typical voltage and temperature conditions. The OSCULP32K should be preferred to the OSC32K whenever the power requirements are prevalent over frequency stability and accuracy. The OSCULP32K can be used as a source for the generic clock generators, as described in the "GCLK - Generic Clock Controller" on page 90. The OSCULP32K is enabled by default after a power-on reset (POR) and will always run except during POR. The OSCULP32K has a 32.768kHz output and a 1.024kHz output that are always running. The frequency of the OSCULP32K oscillator is controlled by the value in the 32kHz Ultra Low Power Internal Oscillator Calibration bits (OSCULP32K.CALIB) in the 32kHz Ultra Low Power Internal Oscillator Control register. OSCULP32K.CALIB is automatically loaded from Flash Factory Calibration during startup, and is used to compensate for process variation, as described in the "Electrical Characteristics" on page 1055. The calibration value can be overridden by the user by writing to OSCULP32K.CALIB. 15.6.6 8MHz Internal Oscillator (OSC8M) Operation OSC8M is an internal oscillator operating in open-loop mode and generating an 8MHz frequency. The OSC8M is factorycalibrated under typical voltage and temperature conditions. OSC8M is the default clock source that is used after a power-on reset (POR). The OSC8M can be used as a source for the generic clock generators, as described in the "GCLK - Generic Clock Controller" on page 90. In order to enable OSC8M, the Oscillator Enable bit in the OSC8M Control register (OSC8M.ENABLE) must be written to one. OSC8M will not be enabled until OSC8M.ENABLE is set. In order to disable OSC8M, OSC8M.ENABLE must be written to zero. OSC8M will not be disabled until OSC8M is cleared. The frequency of the OSC8M oscillator is controlled by the value in the calibration bits (OSC8M.CALIB) in the OSC8M Control register. CALIB is automatically loaded from Flash Factory Calibration during startup, and is used to compensate for process variation, as described in the "Electrical Characteristics" on page 1055. The user can control the oscillation frequency by writing to the Frequency Range (FRANGE) and Calibration (CALIB) bit groups in the 8MHz RC Oscillator Control register (OSC8M). It is not recommended to update the FRANGE and CALIB Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 149 bits when the OSC8M is enabled. As this is in open-loop mode, the frequency will be voltage, temperature and process dependent. Refer to the "Electrical Characteristics" on page 1055 for details. OSC8M is automatically switched off in certain sleep modes to reduce power consumption, as described in the "PM - Power Manager" on page 112. 15.6.7 Digital Frequency Locked Loop (DFLL48M) Operation The DFLL48M can operate in both open-loop mode and closed-loop mode. In closed-loop mode, a low-frequency clock with high accuracy can be used as the reference clock to get high accuracy on the output clock (CLK_DFLL48M). The DFLL48M can be used as a source for the generic clock generators, as described in the "GCLK - Generic Clock Controller" on page 90. 15.6.7.1 Basic Operation Open-Loop Operation After any reset, the open-loop mode is selected. When operating in open-loop mode, the output frequency of the DFLL48M will be determined by the values written to the DFLL Coarse Value bit group and the DFLL Fine Value bit group (DFLLVAL.COARSE and DFLLVAL.FINE) in the DFLL Value register. Using "DFLL48M COARSE CAL" value from "NVM User Row Mapping" on page 25 in DFLL.COARSE helps to output a frequency close to 48 MHz. It is possible to change the values of DFLLVAL.COARSE and DFLLVAL.FINE and thereby the output frequency of the DFLL48M output clock, CLK_DFLL48M, while the DFLL48M is enabled and in use. CLK_DFLL48M is ready to be used when PCLKSR.DFLLRDY is set after enabling the DFLL48M. Closed-Loop Operation In closed-loop operation, the output frequency is continuously regulated against a reference clock. Once the multiplication factor is set, the oscillator fine tuning is automatically adjusted. The DFLL48M must be correctly configured before closed-loop operation can be enabled. After enabling the DFLL48M, it must be configured in the following way: 1. Enable and select a reference clock (CLK_DFLL48M_REF). CLK_DFLL48M_REF is Generic Clock Channel 0 (GCLK_DFLL48M_REF). Refer to "GCLK - Generic Clock Controller" on page 90 for details. 2. Select the maximum step size allowed in finding the Coarse and Fine values by writing the appropriate values to the DFLL Coarse Maximum Step and DFLL Fine Maximum Step bit groups (DFLLMUL.CSTEP and DFLLMUL.FSTEP) in the DFLL Multiplier register. A small step size will ensure low overshoot on the output frequency, but will typically result in longer lock times. A high value might give a large overshoot, but will typically provide faster locking. DFLLMUL.CSTEP and DFLLMUL.FSTEP should not be higher than 50% of the maximum value of DFLLVAL.COARSE and DFLLVAL.FINE, respectively. 3. Select the multiplication factor in the DFLL Multiply Factor bit group (DFLLMUL.MUL) in the DFLL Multiplier register. Care must be taken when choosing DFLLMUL.MUL so that the output frequency does not exceed the maximum frequency of the DFLL. If the target frequency is below the minimum frequency of the DFLL48M, the output frequency will be equal to the DFLL minimum frequency. 4. Start the closed loop mode by writing a one to the DFLL Mode Selection bit (DFLLCTRL.MODE) in the DFLL Control register. The frequency of CLK_DFLL48M (Fclkdfll48m) is given by: F clkdfll48m = DFLLMUL.MUL x F clkdfll48mref where Fclkdfll48mref is the frequency of the reference clock (CLK_DFLL48M_REF). DFLLVAL.COARSE and DFLLVAL.FINE are read-only in closed-loop mode, and are controlled by the frequency tuner to meet user specified frequency. In closed-loop mode, the value in DFLLVAL.COARSE is used by the frequency tuner as a starting point for Coarse. Writing DFLLVAL.COARSE to a value close to the final value before entering closed-loop mode will reduce the time needed to get a lock on Coarse. Using "DFLL48M COARSE CAL" from "NVM User Row Mapping" on page 25 for DFLL.COARSE will start DFLL with a frequency close to 48 MHz. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 150 Following Software sequence should be followed while using the same. 1. load "DFLL48M COARSE CAL" from "NVM User Row Mapping" on page 25 in DFLL.COARSE register 2. Set DFLLCTRL.BPLCKC bit 3. Start DFLL close loop This procedure will reduce DFLL Lock time to DFLL Fine lock time. Frequency Locking The locking of the frequency in closed-loop mode is divided into two stages. In the first, coarse stage, the control logic quickly finds the correct value for DFLLVAL.COARSE and sets the output frequency to a value close to the correct frequency. On coarse lock, the DFLL Locked on Coarse Value bit (PCLKSR.DFLLLOCKC) in the Power and Clocks Status register will be set. In the second, fine stage, the control logic tunes the value in DFLLVAL.FINE so that the output frequency is very close to the desired frequency. On fine lock, the DFLL Locked on Fine Value bit (PCLKSR.DFLLLOCKF) in the Power and Clocks Status register will be set. Interrupts are generated by both PCLKSR.DFLLLOCKC and PCLKSR.DFLLLOCKF if INTENSET.DFLLOCKC or INTENSET.DFLLOCKF are written to one. CLK_DFLL48M is ready to be used when the DFLL Ready bit (PCLKSR.DFLLRDY) in the Power and Clocks Status register is set, but the accuracy of the output frequency depends on which locks are set. For lock times, refer to the "Electrical Characteristics" on page 1055. Frequency Error Measurement The ratio between CLK_DFLL48M_REF and CLK48M_DFLL is measured automatically when the DFLL48M is in closedloop mode. The difference between this ratio and the value in DFLLMUL.MUL is stored in the DFLL Multiplication Ratio Difference bit group(DFLLVAL.DIFF) in the DFLL Value register. The relative error on CLK_DFLL48M compared to the target frequency is calculated as follows: DIFF ERROR = -------------MUL Drift Compensation If the Stable DFLL Frequency bit (DFLLCTRL.STABLE) in the DFLL Control register is zero, the frequency tuner will automatically compensate for drift in the CLK_DFLL48M without losing either of the locks. This means that DFLLVAL.FINE can change after every measurement of CLK_DFLL48M. The DFLLVAL.FINE value overflows or underflows can occur in close loop mode when the clock source reference drifts or is unstable. This will set the DFLL Out Of Bounds bit (PCLKSR.DFLLOOB) in the Power and Clocks Status register. To avoid this error, the reference clock in close loop mode must be stable, an external oscillator is recommended and internal oscillator forbidden. The better choice is to use an XOSC32K. Reference Clock Stop Detection If CLK_DFLL48M_REF stops or is running at a very low frequency (slower than CLK_DFLL48M/(2 * MULMAX)), the DFLL Reference Clock Stopped bit (PCLKSR.DFLLRCS) in the Power and Clocks Status register will be set. Detecting a stopped reference clock can take a long time, on the order of 217 CLK_DFLL48M cycles. When the reference clock is stopped, the DFLL48M will operate as if in open-loop mode. Closed-loop mode operation will automatically resume if the CLK_DFLL48M_REF is restarted. An interrupt is generated on a zero-to-one transition on PCLKSR.DFLLRCS if the DFLL Reference Clock Stopped bit (INTENSET.DFLLRCS) in the Interrupt Enable Set register is set. 15.6.7.2 Additional Features Dealing with Delay in the DFLL in Closed-Loop Mode The time from selecting a new CLK_DFLL48M frequency until this frequency is output by the DFLL48M can be up to several microseconds. If the value in DFLLMUL.MUL is small, this can lead to instability in the DFLL48M locking mechanism, which can prevent the DFLL48M from achieving locks. To avoid this, a chill cycle, during which the Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 151 CLK_DFLL48M frequency is not measured, can be enabled. The chill cycle is enabled by default, but can be disabled by writing a one to the DFLL Chill Cycle Disable bit (DFLLCTRL.CCDIS) in the DFLL Control register. Enabling chill cycles might double the lock time. Another solution to this problem consists of using less strict lock requirements. This is called Quick Lock (QL), which is also enabled by default, but it can be disabled by writing a one to the Quick Lock Disable bit (DFLLCTRL.QLDIS) in the DFLL Control register. The Quick Lock might lead to a larger spread in the output frequency than chill cycles, but the average output frequency is the same. USB Clock Recovery Mode USB Clock Recovery mode can be used to create the 48MHz USB clock from the USB Start Of Frame (SOF). The mode is enabled by writing a one to the USB Clock Recovery Mode bit in DFLL Control register (DFLLCTRL.USBCRM). The SOF signal from USB device will be used as reference clock (CLK_DFLL_REF), ignoring the selected generic clock reference. When the USB device is connected, a SOF will be sent every 1ms, thus DFLLMUL.MUL bits should be written to 0xBB80 to obtain a 48MHz clock. In USB clock recovery mode, the DFLLCTRL.BPLCKC bit state is ignored and the value stored in the DFLLVAL.COARSE will be used as COARSE final value. The lock procedure will also go instantaneously to the fine lock search. The COARSE calibration value can be loaded from NVM OTP row by software. DFLLCTRL.QLDIS bit must be cleared and DFLLCTRL.CCDIS should be set to speed up the lock phase. The DFLLCTRL.STABLE bit state is ignored to let an auto jitter reduction mechanism working instead. Wake from Sleep Modes DFLL48M can optionally reset its lock bits when it is disabled. This is configured by the Lose Lock After Wake bit (DFLLCTRL.LLAW) in the DFLL Control register. If DFLLCTRL.LLAW is zero, the DFLL48M will be re-enabled and start running with the same configuration as before being disabled, even if the reference clock is not available. The locks will not be lost. When the reference clock has restarted, the Fine tracking will quickly compensate for any frequency drift during sleep if DFLLCTRL.STABLE is zero. If DFLLCTRL.LLAW is one when the DFLL is turned off, the DFLL48M will lose all its locks, and needs to regain these through the full lock sequence. Accuracy There are three main factors that determine the accuracy of Fclkdfll48m. These can be tuned to obtain maximum accuracy when fine lock is achieved. z Fine resolution: The frequency step between two Fine values. This is relatively smaller for high output frequencies. z Resolution of the measurement: If the resolution of the measured Fclkdfll48m is low, i.e., the ratio between the CLK_DFLL48M frequency and the CLK_DFLL48M_REF frequency is small, then the DFLL48M might lock at a frequency that is lower than the targeted frequency. It is recommended to use a reference clock frequency of 32kHz or lower to avoid this issue for low target frequencies. z The accuracy of the reference clock. 15.6.8 FDPLL96M - Fractional Digital Phase-Locked Loop Controller 15.6.8.1 Overview The FDPLL96M controller allows flexible interface to the core digital function of the Digital Phase Locked Loop (DPLL). The FDPLL96M integrates a digital filter with a proportional integral controller, a Time-to-Digital Converter (TDC), a test mode controller, a Digitally Controlled Oscillator (DCO) and a PLL controller. It also provides a fractional multiplier of frequency N between the input and output frequency. The CLK_FDPLL96M_REF is the DPLL input clock reference. The selectable sources for the reference clock are XOSC32K, XOSC and GCLK_DPLL. The path between XOSC and input multiplexer integrates a clock divider. The selected clock must be configured and enabled before using the FDPLL96M. If the GCLK is selected as reference clock, it must be configured and enabled in the Generic Clock Controller before using the FDPLL96M. Refer to "GCLK - Generic Clock Controller" on page 90 for details.If the GCLK_DPLL is selected as the source for the CLK_FDPLL96M_REF, care must be taken to make sure the source for this GCLK is within the valid frequency range for the FDPLL96M. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 152 The XOSC source can be divided inside the FDPLL96M. The user must make sure that the programmable clock divider and XOSC frequency provides a valid CLK_FDPLL96M_REF clock frequency that meets the FDPLL96M input frequency range. The output clock of the FDPLL96M is CLK_FDPLL96M. The state of the CLK_FDPLL96M clock only depends on the FDPLL96M internal control of the final clock gater CG. The FDPLL96M requires a 32kHz clock from the GCLK when the FDPLL96M internal lock timer is used. This clock must be configured and enabled in the Generic Clock Controller before using the FDPLL96M. Refer to "GCLK - Generic Clock Controller" on page 90 for details. Table 15-3. Generic Clock Input for FDPLL96M Generic Clock FDPLL96M FDPLL96M 32kHz clock GCLK_DPLL_32K for internal lock timer FDPLL96M GCLK_DPLL for CLK_FDPLL96M_REF 15.6.8.2 Block Diagram Figure 15-2. FDPLL96M Block Diagram GCLK_DPLL_32K XOSC32K GCLK_DPLL %JWJEFS XOSC CLK_FDPLL96M_REF TDC CK Digital Filter DCO $( User Interface CLK_FDPLL96M /N 15.6.8.3 Principle of Operation The task of the FDPLL96M is to maintain coherence between the input reference clock signal (CLK_FDPLL96M_REF) and the respective output frequency CK via phase comparison. The FDPLL96M supports three independent sources of clocks XOSC32K, XOSC and GCLK_DPLL. When the FDPLL96M is enabled, the relationship between the reference clock (CLK_FDPLL96M_REF) frequency and the output clock (CLK_FDPLL96M) frequency is defined below. LDRFRAC f clk_fdpll96m = f clk_fdpll96m_ref x LDR + 1 + ---------------------------- 16 Where LDR is the loop divider ratio integer part, LDRFRAC is the loop divider ratio fractional part, fckrx is the frequency of the selected reference clock and fck is the frequency of the FDPLL96M output clock. As previously stated a clock divider exist between XOSC and CLK_FDPLL96M_REF. The frequency between the two clocks is defined below. 1 f clk_fdpll96m_ref = f xosc x ---------------------------------- 2 x ( DIV + 1 ) Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 153 When the FDPLL96M is disabled, the output clock is reset. If the loop divider ratio fractional part (DPLLRATIO.LDRFRAC) field is reset, the FDPLL96M works in integer mode, otherwise the fractional mode is activated. It shall be noted that fractional part has a negative impact on the jitter of the FDPLL96M. Example (integer mode only): assuming fckr = 32kHz and fck = 48MHz, the multiplication ratio is 1500. It means that LDR shall be set to 1499. Example (fractional mode): assuming fckr = 32 kHz and fck = 48.006MHz, the multiplication ratio is 1500.1875 (1500 + 3/16). Thus LDR is set to 1499 and LDRFRAC to 3. 15.6.8.4 Initialization, Enabling, Disabling and Resetting The FDPLL96M is enabled by writing a one to the Enable bit in the DPLL Control A register (DPLLCTRLA.ENABLE). The FDPLL96M is disabled by writing a zero to DPLLCTRLA.ENABLE. The frequency of the FDPLL96M output clock CK is stable when the module is enabled and when the DPLL Lock Status bit in the DPLL Status register (DPLLSTATUS.LOCK) bit is set. When DPLLCTRLB.LTIME is different from 0, a user defined lock time is used to validate the lock operation. In this case the lock time is constant. If DPLLCTRLB.LTIME is reset, the lock signal is linked with the status bit of the DPLL, the lock time vary depending on the filter selection and final target frequency. When DPLLCTRLB.WUF is set, the wake up fast mode is activated. In that mode the clock gating cell is enabled at the end of the startup time. At that time, the final frequency is not stable as it is still in the acquisition period, but it allows to save several milliseconds. After first acquisition, DPLLCTRLB.LBYPASS indicates if the Lock signal is discarded from the control of the clock gater generating the output clock CLK_FDPLL96M. Table 15-4. CLK_FDPLL96M behavior from startup to first edge detection. WUF LTIME 0 0 0 Not Equal To Zero 1 X CLK_FDPLL96M Behavior Normal Mode: First Edge when lock is asserted Lock Timer Timeout mode: First Edge when the timer downcounts to 0. Wake Up Fast Mode: First Edge when CK is active (startup time) Table 15-5. CLK_FDPLL96M behavior after First Edge detection. LBYPASS CLK_FDPLL96M Behavior 0 Normal Mode: the CLK_FDPLL96M is turned off when lock signal is low. 1 Lock Bypass Mode: the CLK_FDPLL96M is always running, lock is irrelevant. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 154 Figure 15-3. CK and CLK_FDPLL96M Off Mode to Running Mode CKRx ENABLE CK CLK_FDPLL96M LOCK UTUBSUVQ@UJNF UMPDL@UJNF $,45"#-& Figure 15-4. CK and CLK_FDPLL96M Off Mode to Running Mode when Wake-Up Fast is Activated CKRx ENABLE CK CLK_FDPLL96M LOCK UTUBSUVQ@UJNF UMPDL@UJNF $,45"#-& Figure 15-5. CK and CLK_FDPLL96M Running Mode to Off Mode CKRx ENABLE CK CLK_FDPLL96M LOCK 15.6.8.5 Reference Clock Switching When a software operation requires reference clock switching, the normal operation is to disable the FDPLL96M, modify the DPLLCTRLB.REFCLK to select the desired reference source and activate the FDPLL96M again. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 155 15.6.8.6 Loop Divider Ratio updates The FDPLL96M supports on-the-fly update of the DPLLRATIO register, so it is allowed to modify the loop divider ratio and the loop divider ratio fractional part when the FDPLL96M is enabled. At that time, the DPLLSTATUS.LOCK bit is cleared and set again by hardware when the output frequency reached a stable state. The DPLL Lock Fail bit in the Interrupt Flag Status and Clear register (INTFLAG.DPLLLCK) is set when a falling edge has been detected. The flag is cleared when the software write a one to the interrupt flag bit location. Figure 15-6. RATIOCTRL Register Update Operation CKRx LDR LDRFRAC mult0 mult1 CK CLK_FDPLL96M LOCK LOCKL 15.6.8.7 Digital Filter Selection The PLL digital filter (PI controller) is automatically adjusted in order to provide a good compromise between stability and jitter. Nevertheless a software operation can override the filter setting using the DPLLCTRLB.FILTER field. The DPLLCTRLB.LPEN field can be use to bypass the TDC module. 15.6.9 3.3V Brown-Out Detector Operation The 3.3V BOD monitors the 3.3V VDDANA supply (BOD33). It supports continuous or sampling modes. The threshold value action (reset the device or generate an interrupt), the Hysteresis configuration, as well as the enable/disable settings are loaded from Flash User Calibration at startup, and can be overridden by writing to the corresponding BOD33 register bit groups. 15.6.9.1 3.3V Brown-Out Detector (BOD33) The 3.3V Brown-Out Detector (BOD33) monitors the VDDANA supply and compares the voltage with the brown-out threshold level set in the BOD33 Level bit group (BOD33.LEVEL) in the BOD33 register. The BOD33 can generate either an interrupt or a reset when VDDANA crosses below the brown-out threshold level. The BOD33 detection status can be read from the BOD33 Detection bit (PCLKSR.BOD33DET) in the Power and Clocks Status register. At startup or at power-on reset (POR), the BOD33 register values are loaded from the Flash User Row. Refer to "NVM User Row Mapping" on page 25 for more details. 15.6.9.2 Continuous Mode When the BOD33 Mode bit (BOD33.MODE) in the BOD33 register is written to zero and the BOD33 is enabled, the BOD33 operates in continuous mode. In this mode, the BOD33 is continuously monitoring the VDDANA supply voltage. Continuous mode is the default mode for BOD33. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 156 15.6.9.3 Sampling Mode The sampling mode is a low-power mode where the BOD33 is being repeatedly enabled on a sampling clock's ticks. The BOD33 will monitor the supply voltage for a short period of time and then go to a low-power disabled state until the next sampling clock tick. Sampling mode is enabled by writing one to BOD33.MODE. The frequency of the clock ticks (Fclksampling) is controlled by the BOD33 Prescaler Select bit group (BOD33.PSEL) in the BOD33 register. F clkprescaler F clksampling = -----------------------------2 ( PSEL + 1 ) The prescaler signal (Fclkprescaler) is a 1kHz clock, output from the32kHz Ultra Low Power Oscillator, OSCULP32K. As the sampling mode clock is different from the APB clock domain, synchronization among the clocks is necessary. Figure 15-7 shows a block diagram of the sampling mode. The BOD33Synchronization Ready bits (PCLKSR.B33SRDY) in the Power and Clocks Status register show the synchronization ready status of the synchronizer. Writing attempts to the BOD33 register are ignored while PCLKSR.B33SRDY is zero. Figure 15-7. Sampling Mode Block diagram USER INTERFACE REGISTERS (APB clock domain) PSEL CEN PRESCALER (clk_prescaler domain) SYNCHRONIZER MODE CLK_SAMPLING ENABLE CLK_APB CLK_PRESCALER The BOD33 Clock Enable bit (BOD33.CEN) in the BOD33 register should always be disabled before changing the prescaler value. To change the prescaler value for the BOD33 during sampling mode, the following steps need to be taken: 1. Wait until the PCLKSR.B33SRDY bit is set. 2. Write the selected value to the BOD33.PSEL bit group. 15.6.9.4 Hysteresis The hysteresis functionality can be used in both continuous and sampling mode. Writing a one to the BOD33 Hysteresis bit (BOD33.HYST) in the BOD33 register will add hysteresis to the BOD33 threshold level. 15.6.10 Voltage Reference System Operation The Voltage Reference System (VREF) consists of a Bandgap Reference Voltage Generator and a temperature sensor. The Bandgap Reference Voltage Generator is factory-calibrated under typical voltage and temperature conditions. At reset, the VREF.CAL register value is loaded from Flash Factory Calibration. The temperature sensor can be used to get an absolute temperature in the temperature range of CMIN to CMAX degrees Celsius. The sensor will output a linear voltage proportional to the temperature. The output voltage and Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 157 temperature range are located in the "Electrical Characteristics" on page 1055. To calculate the temperature from a measured voltage, the following formula can be used: temperature C MIN + ( Vmes - Vout MAX ) -----------------------------------voltage 15.6.10.1 User Control of the Voltage Reference System To enable the temperature sensor, write a one the Temperature Sensor Enable bit (VREF.TSEN) in the VREF register. The temperature sensor can be redirected to the ADC for conversion. The Bandgap Reference Voltage Generator output can also be routed to the ADC if the Bandgap Output Enable bit (VREF.BGOUTEN) in the VREF register is set. The Bandgap Reference Voltage Generator output level is determined by the CALIB bit group (VREF.CALIB) value in the VREF register.The default calibration value can be overridden by the user by writing to the CALIB bit group. 15.6.11 Internal Voltage Regulator System (VREG) The embedded Voltage Regulator (VREG) is an internal voltage regulator that supplies the core and digital logic. The regulator has two operating modes: z a normal operating mode: used when the CPU and peripherals are running z a low-power operating mode: used when the regulator draws small static current. By default, this mode is used in standby sleep mode. It is possible to have the voltage regulator operate in normal mode when the chip is in standby sleep mode: this is done by setting the VREG.RUNSTDBY bit. The low-power operating mode has two possible configurations in standby sleep mode: z a low drive configuration, this is the default setting (the VREG.FORCELDO bit is cleared), z a high drive configuration: this setting is required for higher loads in standby sleep mode (case where several modules are up despite the standby mode). To activate this configuration, the FORCELDO bit (VREG.FORCELDO) in the VREG register must be set. The internal voltage regulator system contains an internal brown-out detector(BOD12) on VDDCORE. BOD12 is calibrated in production and its calibration configuration is stored in the NVM User Row. This configuration must not be changed to assure the correct behavior of the BOD12. The BOD12 can generate either an interrupt or a reset when VDDCORE crosses below the preset brown-out level. The BOD12 is always disabled in standby sleep mode. 15.6.12 DMA Operation Not applicable. 15.6.13 Interrupts The SYSCTRL has the following interrupt sources: z z z z z z z z z z z z z XOSCRDY - Multipurpose Crystal Oscillator Ready: A "0-to-1" transition on the PCLKSR.XOSCRDY bit is detected XOSC32KRDY - 32kHz Crystal Oscillator Ready: A "0-to-1" transition on the PCLKSR.XOSC32KRDY bit is detected OSC32KRDY - 32kHz Internal Oscillator Ready: A "0-to-1" transition on the PCLKSR.OSC32KRDY bit is detected OSC8MRDY - 8MHz Internal Oscillator Ready: A "0-to-1" transition on the PCLKSR.OSC8MRDY bit is detected DFLLRDY - DFLL48M Ready: A "0-to-1" transition on the PCLKSR.DFLLRDY bit is detected DFLLOOB - DFLL48M Out Of Boundaries: A "0-to-1" transition on the PCLKSR.DFLLOOB bit is detected DFLLLOCKF - DFLL48M Fine Lock: A "0-to-1" transition on the PCLKSR.DFLLLOCKF bit is detected DFLLLOCKC - DFLL48M Coarse Lock: A "0-to-1" transition on the PCLKSR.DFLLLOCKC bit is detected DFLLRCS - DFLL48M Reference Clock has Stopped: A "0-to-1" transition on the PCLKSR.DFLLRCS bit is detected BOD33RDY - BOD33 Ready: A "0-to-1" transition on the PCLKSR.BOD33RDY bit is detected BOD33DET - BOD33 Detection: A "0-to-1" transition on the PCLKSR.BOD33DET bit is detected. This is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. B33SRDY - BOD33 Synchronization Ready: A "0-to-1" transition on the PCLKSR.B33SRDY bit is detected PLL Lock (LOCK): Indicates that the DPLL Lock bit is asserted. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 158 z z PLL Lock Lost (LOCKL): Indicates that a falling edge has been detected on the Lock bit during normal operation mode. PLL Lock Timer Timeout (LTTO): This interrupt flag indicates that the software defined time DPLLCTRLB.LTIME has elapsed since the start of the FDPLL96M. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the SYSCTRL is reset. See Interrupt Flag Status and Clear (INTFLAG) register for details on how to clear interrupt flags. All interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt request to the NVIC. Refer to "Nested Vector Interrupt Controller" on page 29 for details. The user must read the INTFLAG register to determine which interrupt condition is present. Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to "Nested Vector Interrupt Controller" on page 29 for details. 15.6.14 Synchronization Due to the multiple clock domains, values in the DFLL48M control registers need to be synchronized to other clock domains. The status of this synchronization can be read from the Power and Clocks Status register (PCLKSR). Before writing to any of the DFLL48M control registers, the user must check that the DFLL Ready bit (PCLKSR.DFLLRDY) in PCLKSR is set to one. When this bit is set, the DFLL48M can be configured and CLK_DFLL48M is ready to be used. Any write to any of the DFLL48M control registers while DFLLRDY is zero will be ignored. An interrupt is generated on a zeroto-one transition of DFLLRDY if the DFLLRDY bit (INTENSET.DFLLDY) in the Interrupt Enable Set register is set. In order to read from any of the DFLL48M configuration registers, the user must request a read synchronization by writing a one to DFLLSYNC.READREQ. The registers can be read only when PCLKSR.DFLLRDY is set. If DFLLSYNC.READREQ is not written before a read, a synchronization will be started, and the bus will be halted until the synchronization is complete. Reading the DFLL48M registers when the DFLL48M is disabled will not halt the bus. The prescaler counter used to trigger one-shot brown-out detections also operates asynchronously from the peripheral bus. As a consequence, the prescaler registers require synchronization when written or read. The synchronization results in a delay from when the initialization of the write or read operation begins until the operation is complete. The write-synchronization is triggered by a write to the BOD33 control register. The Synchronization Ready bit (PCLKSR.B33SRDY) in the PCLKSR register will be cleared when the write-synchronization starts and set when the write-synchronization is complete. When the write-synchronization is ongoing (PCLKSR.B33SRDYis zero), an attempt to do any of the following will cause the peripheral bus to stall until the synchronization is complete: z Writing to the BOD33control register z Reading the BOD33 control register that was written The user can either poll PCLKSR.B33SRDY or use the INTENSET.B33SRDY interrupts to check when the synchronization is complete. It is also possible to perform the next read/write operation and wait, as this next operation will be completed after the ongoing read/write operation is synchronized. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 159 15.7 Register Summary Table 15-6. Register Summary Offset Name Bit Pos. 0x00 7:0 DFLLLCKC 0x01 15:8 DPLLLCKR 0x02 INTENCLR 0x03 31:24 7:0 DFLLLCKC 15:8 DPLLLCKR 0x06 INTENSET 0x07 7:0 DFLLLCKC 15:8 DPLLLCKR INTFLAG 0x0B 31:24 7:0 DFLLLCKC 15:8 DPLLLCKR 0x0D PCLKSR 0x0F 0x11 XOSC Reserved 0x13 Reserved 0x15 XOSC32K 0x16 Reserved 0x17 Reserved 0x18 0x19 0x1A OSC32K OSCULP32K 0x1D ... 0x1F Reserved 0x20 OSC8M 0x23 0x24 0x25 DFLLRCS DPLLLTO DPLLLCKF DFLLLCKF DFLLOOB DFLLRDY OSC8MRDY OSC32KRDY XOSC32KRDY XOSCRDY B33SRDY BOD33DET BOD33RDY DFLLRCS DPLLLTO DPLLLCKF DFLLLCKF DFLLOOB DFLLRDY OSC8MRDY OSC32KRDY XOSC32KRDY XOSCRDY B33SRDY BOD33DET BOD33RDY DFLLRCS DPLLLTO DPLLLCKF DFLLLCKF DFLLOOB DFLLRDY OSC8MRDY OSC32KRDY XOSC32KRDY XOSCRDY B33SRDY BOD33DET BOD33RDY DFLLRCS DPLLLTO DPLLLCKF 7:0 ONDEMAND RUNSTDBY 15:8 7:0 XTALEN STARTUP[3:0] ONDEMAND RUNSTDBY AMPGC AAMPEN 15:8 EN32K GAIN[2:0] XTALEN WRTLOCK ONDEMAND ENABLE STARTUP[2:0] RUNSTDBY EN32K 15:8 ENABLE WRTLOCK ENABLE STARTUP[2:0] CALIB[6:0] 23:16 31:24 0x1C 0x21 XOSCRDY BOD33RDY 23:16 7:0 0x1B 0x22 XOSC32KRDY BOD33DET 31:24 0x12 0x14 OSC32KRDY B33SRDY 23:16 0x0C 0x10 OSC8MRDY 23:16 0x09 0x0E DFLLRDY 31:24 0x08 0x0A DFLLOOB 23:16 0x04 0x05 DFLLLCKF 7:0 WRTLOCK 7:0 ONDEMAND 0x26 Reserved 0x27 Reserved RUNSTDBY ENABLE 15:8 PRESC[1:0] 23:16 31:24 DFLLCTRL CALIB[4:0] 7:0 15:8 CALIB[7:0] FRANGE[1:0] ONDEMAND RUNSTDBY CALIB[11:8] USBCRM LLAW STABLE MODE ENABLE WAITLOCK BPLCKC QLDIS CCDIS Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 160 Offset Name Bit Pos. 0x28 7:0 0x29 15:8 0x2A DFLLVAL 0x2B FINE[7:0] COARSE[5:0] FINE[9:8] 23:16 DIFF[7:0] 31:24 DIFF[15:8] 0x2C 7:0 MUL[7:0] 0x2D 15:8 MUL[15:8] 0x2E DFLLMUL 0x2F 23:16 0x30 DFLLSYNC 0x31 ... 0x33 Reserved 7:0 0x34 7:0 0x35 15:8 0x36 BOD33 0x37 0x38 ... 0x3B 0x3C 0x3D VREG 0x3F Reserved RUNSTDBY ACTION[1:0] HYST ENABLE PSEL[3:0] CEN MODE LEVEL[5:0] 7:0 7:0 15:8 VREF 0x43 RUNSTDBY 15:8 0x41 FORCELDO BGOUTEN 23:16 DPLLCTRLA 0x45 ... 0x47 Reserved 0x48 7:0 CALIB[10:8] ONDEMAND ENABLE RUNSTDBY 7:0 0x49 DPLLRATIO 0x4B TSEN CALIB[7:0] 31:24 0x44 LDR[7:0] 15:8 LDR[11:8] 23:16 LDRFRAC[3:0] 31:24 0x4C 7:0 0x4D 15:8 DPLLCTRLB 0x4F 0x50 READREQ 23:16 0x40 0x4E FSTEP[9:8] Reserved Reserved 0x4A CSTEP[5:0] 31:24 0x3E 0x42 FSTEP[7:0] 31:24 23:16 REFCLK[1:0] WUF LPEN LBYPASS DIV[7:0] 31:24 DPLLSTATUS 7:0 FILTER[1:0] LTIME[2:0] DIV[10:8] DIV ENABLE CLKRDY Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 LOCK 161 15.8 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protected property in each individual register description. Refer to "Register Access Protection" on page 146 and the "PAC - Peripheral Access Controller" on page 36 for details. Some registers require synchronization when read and/or written. Synchronization is denoted by the Synchronized property in each individual register description. Refer to "Synchronization" on page 159 for details. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 162 15.8.1 Interrupt Enable Clear This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Name: INTENCLR Offset: 0x00 Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DPLLLTO DPLLLCKF Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 B33SRDY BOD33DET BOD33RDY DFLLRCS DPLLLCKR Access R/W R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DFLLLCKC DFLLLCKF DFLLOOB DFLLRDY OSC8MRDY OSC32KRDY XOSC32KRDY XOSCRDY R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Access Reset z Bits 31:18 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 17 - DPLLLTO: DPLL Lock Timeout Interrupt Enable 0: The DPLL Lock Timeout interrupt is disabled. 1: The DPLL Lock Timeout interrupt is enabled, and an interrupt request will be generated when the DPLL Lock Timeout Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the DPLL Lock Timeout Interrupt Enable bit, which disables the DPLL Lock Timeout interrupt. z Bit 16 - DPLLLCKF: DPLL Lock Fall Interrupt Enable 0: The DPLL Lock Fall interrupt is disabled. 1: The DPLL Lock Fall interrupt is enabled, and an interrupt request will be generated when the DPLL Lock Fall Interrupt flag is set. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 163 Writing a zero to this bit has no effect. Writing a one to this bit will clear the DPLL Lock Fall Interrupt Enable bit, which disables the DPLL Lock Fall interrupt. z Bit 15 - DPLLLCKR: DPLL Lock Rise Interrupt Enable 0: The DPLL Lock Rise interrupt is disabled. 1: The DPLL Lock Rise interrupt is enabled, and an interrupt request will be generated when the DPLL Lock Rise Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the DPLL Lock Rise Interrupt Enable bit, which disables the DPLL Lock Rise interrupt. z Bits 14:12 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 11 - B33SRDY: BOD33 Synchronization Ready Interrupt Enable 0: The BOD33 Synchronization Ready interrupt is disabled. 1: The BOD33 Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the BOD33 Synchronization Ready Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the BOD33 Synchronization Ready Interrupt Enable bit, which disables the BOD33 Synchronization Ready interrupt. z Bit 10 - BOD33DET: BOD33 Detection Interrupt Enable 0: The BOD33 Detection interrupt is disabled. 1: The BOD33 Detection interrupt is enabled, and an interrupt request will be generated when the BOD33 Detection Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the BOD33 Detection Interrupt Enable bit, which disables the BOD33 Detection interrupt. z Bit 9 - BOD33RDY: BOD33 Ready Interrupt Enable 0: The BOD33 Ready interrupt is disabled. 1: The BOD33 Ready interrupt is enabled, and an interrupt request will be generated when the BOD33 Ready Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the BOD33 Ready Interrupt Enable bit, which disables the BOD33 Ready interrupt. z Bit 8 - DFLLRCS: DFLL Reference Clock Stopped Interrupt Enable 0: The DFLL Reference Clock Stopped interrupt is disabled. 1: The DFLL Reference Clock Stopped interrupt is enabled, and an interrupt request will be generated when the DFLL Reference Clock Stopped Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the DFLL Reference Clock Stopped Interrupt Enable bit, which disables the DFLL Reference Clock Stopped interrupt. z Bit 7 - DFLLLCKC: DFLL Lock Coarse Interrupt Enable 0: The DFLL Lock Coarse interrupt is disabled. 1: The DFLL Lock Coarse interrupt is enabled, and an interrupt request will be generated when the DFLL Lock Coarse Interrupt flag is set. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 164 Writing a zero to this bit has no effect. Writing a one to this bit will clear the DFLL Lock Coarse Interrupt Enable bit, which disables the DFLL Lock Coarse interrupt. z Bit 6 - DFLLLCKF: DFLL Lock Fine Interrupt Enable 0: The DFLL Lock Fine interrupt is disabled. 1: The DFLL Lock Fine interrupt is enabled, and an interrupt request will be generated when the DFLL Lock Fine Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the DFLL Lock Fine Interrupt Enable bit, which disables the DFLL Lock Fine interrupt. z Bit 5 - DFLLOOB: DFLL Out Of Bounds Interrupt Enable 0: The DFLL Out Of Bounds interrupt is disabled. 1: The DFLL Out Of Bounds interrupt is enabled, and an interrupt request will be generated when the DFLL Out Of Bounds Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the DFLL Out Of Bounds Interrupt Enable bit, which disables the DFLL Out Of Bounds interrupt. z Bit 4 - DFLLRDY: DFLL Ready Interrupt Enable 0: The DFLL Ready interrupt is disabled. 1: The DFLL Ready interrupt is enabled, and an interrupt request will be generated when the DFLL Ready Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the DFLL Ready Interrupt Enable bit, which disables the DFLL Ready interrupt. z Bit 3 - OSC8MRDY: OSC8M Ready Interrupt Enable 0: The OSC8M Ready interrupt is disabled. 1: The OSC8M Ready interrupt is enabled, and an interrupt request will be generated when the OSC8M Ready Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the OSC8M Ready Interrupt Enable bit, which disables the OSC8M Ready interrupt. z Bit 2 - OSC32KRDY: OSC32K Ready Interrupt Enable 0: The OSC32K Ready interrupt is disabled. 1: The OSC32K Ready interrupt is enabled, and an interrupt request will be generated when the OSC32K Ready Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the OSC32K Ready Interrupt Enable bit, which disables the OSC32K Ready interrupt. z Bit 1 - XOSC32KRDY: XOSC32K Ready Interrupt Enable 0: The XOSC32K Ready interrupt is disabled. 1: The XOSC32K Ready interrupt is enabled, and an interrupt request will be generated when the XOSC32K Ready Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the XOSC32K Ready Interrupt Enable bit, which disables the XOSC32K Ready interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 165 z Bit 0 - XOSCRDY: XOSC Ready Interrupt Enable 0: The XOSC Ready interrupt is disabled. 1: The XOSC Ready interrupt is enabled, and an interrupt request will be generated when the XOSC Ready Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the XOSC Ready Interrupt Enable bit, which disables the XOSC Ready interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 166 15.8.2 Interrupt Enable Set This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Name: INTENSET Offset: 0x04 Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DPLLLTO DPLLLCKF Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 B33SRDY BOD33DET BOD33RDY DFLLRCS DPLLLCKR Access R/W R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DFLLLCKC DFLLLCKF DFLLOOB DFLLRDY OSC8MRDY OSC32KRDY XOSC32KRDY XOSCRDY R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Access Reset z Bits 31:18 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 17 - DPLLLTO: DPLL Lock Timeout Interrupt Enable 0: The DPLL Lock Timeout interrupt is disabled. 1: The DPLL Lock Timeout interrupt is enabled, and an interrupt request will be generated when the DPLL Lock Timeout Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will set the DPLL Lock Timeout Interrupt Enable bit, which enables the DPLL Lock Timeout interrupt. z Bit 16 - DPLLLCKF: DPLL Lock Fall Interrupt Enable 0: The DPLL Lock Fall interrupt is disabled. 1: The DPLL Lock Fall interrupt is enabled, and an interrupt request will be generated when the DPLL Lock Fall Interrupt flag is set. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 167 Writing a zero to this bit has no effect. Writing a one to this bit will set the DPLL Lock Fall Interrupt Enable bit, which enables the DPLL Lock Fall interrupt. z Bit 15 - DPLLLCKR: DPLL Lock Rise Interrupt Enable 0: The DPLL Lock Rise interrupt is disabled. 1: The DPLL Lock Rise interrupt is enabled, and an interrupt request will be generated when the DPLL Lock Rise Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will set the DPLL Lock Rise Interrupt Enable bit, which enables the DPLL Lock Rise interrupt. z Bits 14:12 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 11 - B33SRDY: BOD33 Synchronization Ready Interrupt Enable 0: The BOD33 Synchronization Ready interrupt is disabled. 1: The BOD33 Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the BOD33 Synchronization Ready Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will set the BOD33 Synchronization Ready Interrupt Enable bit, which enables the BOD33 Synchronization Ready interrupt. z Bit 10 - BOD33DET: BOD33 Detection Interrupt Enable 0: The BOD33 Detection interrupt is disabled. 1: The BOD33 Detection interrupt is enabled, and an interrupt request will be generated when the BOD33 Detection Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will set the BOD33 Detection Interrupt Enable bit, which enables the BOD33 Detection interrupt. z Bit 9 - BOD33RDY: BOD33 Ready Interrupt Enable 0: The BOD33 Ready interrupt is disabled. 1: The BOD33 Ready interrupt is enabled, and an interrupt request will be generated when the BOD33 Ready Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will set the BOD33 Ready Interrupt Enable bit, which enables the BOD33 Ready interrupt. z Bit 8 - DFLLRCS: DFLL Reference Clock Stopped Interrupt Enable 0: The DFLL Reference Clock Stopped interrupt is disabled. 1: The DFLL Reference Clock Stopped interrupt is enabled, and an interrupt request will be generated when the DFLL Reference Clock Stopped Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will set the DFLL Reference Clock Stopped Interrupt Enable bit, which enables the DFLL Reference Clock Stopped interrupt. z Bit 7 - DFLLLCKC: DFLL Lock Coarse Interrupt Enable 0: The DFLL Lock Coarse interrupt is disabled. 1: The DFLL Lock Coarse interrupt is enabled, and an interrupt request will be generated when the DFLL Lock Coarse Interrupt flag is set. Writing a zero to this bit has no effect. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 168 Writing a one to this bit will set the DFLL Lock Coarse Interrupt Enable bit, which enables the DFLL Lock Coarse interrupt. z Bit 6 - DFLLLCKF: DFLL Lock Fine Interrupt Enable 0: The DFLL Lock Fine interrupt is disabled. 1: The DFLL Lock Fine interrupt is enabled, and an interrupt request will be generated when the DFLL Lock Fine Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will set the DFLL Lock Fine Interrupt Disable/Enable bit, disable the DFLL Lock Fine interrupt and set the corresponding interrupt request. z Bit 5 - DFLLOOB: DFLL Out Of Bounds Interrupt Enable 0: The DFLL Out Of Bounds interrupt is disabled. 1: The DFLL Out Of Bounds interrupt is enabled, and an interrupt request will be generated when the DFLL Out Of Bounds Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will set the DFLL Out Of Bounds Interrupt Enable bit, which enables the DFLL Out Of Bounds interrupt. z Bit 4 - DFLLRDY: DFLL Ready Interrupt Enable 0: The DFLL Ready interrupt is disabled. 1: The DFLL Ready interrupt is enabled, and an interrupt request will be generated when the DFLL Ready Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will set the DFLL Ready Interrupt Enable bit, which enables the DFLL Ready interrupt and set the corresponding interrupt request. z Bit 3 - OSC8MRDY: OSC8M Ready Interrupt Enable 0: The OSC8M Ready interrupt is disabled. 1: The OSC8M Ready interrupt is enabled, and an interrupt request will be generated when the OSC8M Ready Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will set the OSC8M Ready Interrupt Enable bit, which enables the OSC8M Ready interrupt. z Bit 2 - OSC32KRDY: OSC32K Ready Interrupt Enable 0: The OSC32K Ready interrupt is disabled. 1: The OSC32K Ready interrupt is enabled, and an interrupt request will be generated when the OSC32K Ready Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will set the OSC32K Ready Interrupt Enable bit, which enables the OSC32K Ready interrupt. z Bit 1 - XOSC32KRDY: XOSC32K Ready Interrupt Enable 0: The XOSC32K Ready interrupt is disabled. 1: The XOSC32K Ready interrupt is enabled, and an interrupt request will be generated when the XOSC32K Ready Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will set the XOSC32K Ready Interrupt Enable bit, which enables the XOSC32K Ready interrupt. z Bit 0 - XOSCRDY: XOSC Ready Interrupt Enable 0: The XOSC Ready interrupt is disabled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 169 1: The XOSC Ready interrupt is enabled, and an interrupt request will be generated when the XOSC Ready Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will set the XOSC Ready Interrupt Enable bit, which enables the XOSC Ready interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 170 15.8.3 Interrupt Flag Status and Clear Name: INTFLAG Offset: 0x08 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DPLLLTO DPLLLCKF Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 B33SRDY BOD33DET BOD33RDY DFLLRCS DPLLLCKR Access R/W R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DFLLLCKC DFLLLCKF DFLLOOB DFLLRDY OSC8MRDY OSC32KRDY XOSC32KRDY XOSCRDY R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Access Reset Note: Depending on the fuse settings, various bits of the INTFLAG register can be set to one at startup. Therefore the user should clear those bits before using the corresponding interrupts. z Bits 31:18 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 17 - DPLLLTO: DPLL Lock Timeout This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the DPLL Lock Timeout bit in the Status register (PCLKSR.DPLLLTO) and will generate an interrupt request if INTENSET.DPLLLTO is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the DPLL Lock Timeout interrupt flag. z Bit 16 - DPLLLCKF: DPLL Lock Fall This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the DPLL Lock Fall bit in the Status register (PCLKSR.DPLLLCKF) and will generate an interrupt request if INTENSET.DPLLLCKF is one. Writing a zero to this bit has no effect. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 171 Writing a one to this bit clears the DPLL Lock Fall interrupt flag. z Bit 15 - DPLLLCKR: DPLL Lock Rise This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the DPLL Lock Rise bit in the Status register (PCLKSR.DPLLLCKR) and will generate an interrupt request if INTENSET.DPLLLCKR is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the DPLL Lock Rise interrupt flag. z Bits 14:12 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 11 - B33SRDY: BOD33 Synchronization Ready This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the BOD33 Synchronization Ready bit in the Status register (PCLKSR.B33SRDY) and will generate an interrupt request if INTENSET.B33SRDY is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the BOD33 Synchronization Ready interrupt flag z Bit 10 - BOD33DET: BOD33 Detection This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the BOD33 Detection bit in the Status register (PCLKSR.BOD33DET) and will generate an interrupt request if INTENSET.BOD33DET is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the BOD33 Detection interrupt flag. z Bit 9 - BOD33RDY: BOD33 Ready This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the BOD33 Ready bit in the Status register (PCLKSR.BOD33RDY) and will generate an interrupt request if INTENSET.BOD33RDY is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the BOD33 Ready interrupt flag. z Bit 8 - DFLLRCS: DFLL Reference Clock Stopped This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the DFLL Reference Clock Stopped bit in the Status register (PCLKSR.DFLLRCS) and will generate an interrupt request if INTENSET.DFLLRCS is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the DFLL Reference Clock Stopped interrupt flag. z Bit 7 - DFLLLCKC: DFLL Lock Coarse This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the DFLL Lock Coarse bit in the Status register (PCLKSR.DFLLLCKC) and will generate an interrupt request if INTENSET.DFLLLCKC is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the DFLL Lock Coarse interrupt flag. z Bit 6 - DFLLLCKF: DFLL Lock Fine This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the DFLL Lock Fine bit in the Status register (PCLKSR.DFLLLCKF) and will generate an interrupt request if INTENSET.DFLLLCKF is one. Writing a zero to this bit has no effect. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 172 Writing a one to this bit clears the DFLL Lock Fine interrupt flag. z Bit 5 - DFLLOOB: DFLL Out Of Bounds This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the DFLL Out Of Bounds bit in the Status register (PCLKSR.DFLLOOB) and will generate an interrupt request if INTENSET.DFLLOOB is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the DFLL Out Of Bounds interrupt flag. z Bit 4 - DFLLRDY: DFLL Ready This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the DFLL Ready bit in the Status register (PCLKSR.DFLLRDY) and will generate an interrupt request if INTENSET.DFLLRDY is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the DFLL Ready interrupt flag. z Bit 3 - OSC8MRDY: OSC8M Ready This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the OSC8M Ready bit in the Status register (PCLKSR.OSC8MRDY) and will generate an interrupt request if INTENSET.OSC8MRDY is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the OSC8M Ready interrupt flag. z Bit 2 - OSC32KRDY: OSC32K Ready This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the OSC32K Ready bit in the Status register (PCLKSR.OSC32KRDY) and will generate an interrupt request if INTENSET.OSC32KRDY is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the OSC32K Ready interrupt flag. z Bit 1 - XOSC32KRDY: XOSC32K Ready This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the XOSC32K Ready bit in the Status register (PCLKSR.XOSC32KRDY) and will generate an interrupt request if INTENSET.XOSC32KRDY is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the XOSC32K Ready interrupt flag. z Bit 0 - XOSCRDY: XOSC Ready This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the XOSC Ready bit in the Status register (PCLKSR.XOSCRDY) and will generate an interrupt request if INTENSET.XOSCRDY is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the XOSC Ready interrupt flag. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 173 15.8.4 Power and Clocks Status Name: PCLKSR Offset: 0x0C Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DPLLLTO DPLLLCKF Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 B33SRDY BOD33DET BOD33RDY DFLLRCS DPLLLCKR Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DFLLLCKC DFLLLCKF DFLLOOB DFLLRDY OSC8MRDY OSC32KRDY XOSC32KRDY XOSCRDY Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 31:18 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 17 - DPLLLTO: DPLL Lock Timeout 0: DPLL Lock time-out not detected. 1: DPLL Lock time-out detected. z Bit 16 - DPLLLCKF: DPLL Lock Fall 0: DPLL Lock fall edge not detected. 1: DPLL Lock fall edge detected. z Bit 15 - DPLLLCKR: DPLL Lock Rise 0: DPLL Lock rise edge not detected. 1: DPLL Lock fall edge detected. z Bits 14:12 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 174 z Bit 11 - B33SRDY: BOD33 Synchronization Ready 0: BOD33 synchronization is complete. 1: BOD33 synchronization is ongoing. z Bit 10 - BOD33DET: BOD33 Detection 0: No BOD33 detection. 1: BOD33 has detected that the I/O power supply is going below the BOD33 reference value. z Bit 9 - BOD33RDY: BOD33 Ready 0: BOD33 is not ready. 1: BOD33 is ready. z Bit 8 - DFLLRCS: DFLL Reference Clock Stopped 0: DFLL reference clock is running. 1: DFLL reference clock has stopped. z Bit 7 - DFLLLCKC: DFLL Lock Coarse 0: No DFLL coarse lock detected. 1: DFLL coarse lock detected. z Bit 6 - DFLLLCKF: DFLL Lock Fine 0: No DFLL fine lock detected. 1: DFLL fine lock detected. z Bit 5 - DFLLOOB: DFLL Out Of Bounds 0: No DFLL Out Of Bounds detected. 1: DFLL Out Of Bounds detected. z Bit 4 - DFLLRDY: DFLL Ready 0: The Synchronization is ongoing. 1: The Synchronization is complete. This bit is cleared when the synchronization of registers between clock domains is complete. This bit is set when the synchronization of registers between clock domains is started. z Bit 3 - OSC8MRDY: OSC8M Ready 0: OSC8M is not ready. 1: OSC8M is stable and ready to be used as a clock source. z Bit 2 - OSC32KRDY: OSC32K Ready 0: OSC32K is not ready. 1: OSC32K is stable and ready to be used as a clock source. z Bit 1 - XOSC32KRDY: XOSC32K Ready 0: XOSC32K is not ready. 1: XOSC32K is stable and ready to be used as a clock source. z Bit 0 - XOSCRDY: XOSC Ready 0: XOSC is not ready. 1: XOSC is stable and ready to be used as a clock source. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 175 15.8.5 External Multipurpose Crystal Oscillator (XOSC) Control Name: XOSC Offset: 0x10 Reset: 0x0080 Property: Write-Protected Bit 15 14 13 12 STARTUP[3:0] Access 11 10 AMPGC 9 8 GAIN[2:0] R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY XTALEN ENABLE R/W R/W R R R R/W R/W R 1 0 0 0 0 0 0 0 Access Reset z Bits 15:12 - STARTUP[3:0]: Start-Up Time These bits select start-up time for the oscillator according to the table below. The OSCULP32K oscillator is used to clock the start-up counter. Table 15-7. Start-UpTime for External Multipurpose Crystal Oscillator STARTUP[3:0] Number of OSCULP32K Clock Cycles Number of XOSC Clock Cycles Approximate Equivalent Time(1)(2)(3) 0x0 1 3 31s 0x1 2 3 61s 0x2 4 3 122s 0x3 8 3 244s 0x4 16 3 488s 0x5 32 3 977s Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 176 Table 15-7. Start-UpTime for External Multipurpose Crystal Oscillator (Continued) STARTUP[3:0] Number of OSCULP32K Clock Cycles Number of XOSC Clock Cycles Approximate Equivalent Time(1)(2)(3) 0x6 64 3 1953s 0x7 128 3 3906s 0x8 256 3 7813s 0x9 512 3 15625s 0xA 1024 3 31250s 0xB 2048 3 62500s 0xC 4096 3 125000s 0xD 8192 3 250000s 0xE 16384 3 500000s 0xF 32768 3 1000000s Notes: 1. z Number of cycles for the start-up counter 2. Number of cycles for the synchronization delay, before PCLKSR.XOSCRDY is set. 3. Actual start-up time is n OSCULP32K cycles + 3 XOSC cycles, but given the time neglects the 3 XOSC cycles. Bit 11 - AMPGC: Automatic Amplitude Gain Control 0: The automatic amplitude gain control is disabled. 1: The automatic amplitude gain control is enabled. Amplitude gain will be automatically adjusted during Crystal Oscillator operation. z Bits 10:8 - GAIN[2:0]: Oscillator Gain These bits select the gain for the oscillator. The listed maximum frequencies are recommendations, and might vary based on capacitive load and crystal characteristics. Setting this bit group has no effect when the Automatic Amplitude Gain Control is active. Table 15-8. Oscillator Gain GAIN[2:0] 0x0 2MHz 0x1 4MHz 0x2 8MHz 0x3 16MHz 0x4 30MHz 0x5-0x7 z Recommended Max Frequency Reserved Bit 7 - ONDEMAND: On Demand Control The On Demand operation mode allows an oscillator to be enabled or disabled, depending on peripheral clock requests. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 177 In On Demand operation mode, i.e., if the XOSC.ONDEMAND bit has been previously written to one, the oscillator will be running only when requested by a peripheral. If there is no peripheral requesting the oscillator s clock source, the oscillator will be in a disabled state. If On Demand is disabled, the oscillator will always be running when enabled. In standby sleep mode, the On Demand operation is still active if the XOSC.RUNSTDBY bit is one. If XOSC.RUNSTDBY is zero, the oscillator is disabled. 0: The oscillator is always on, if enabled. 1: The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. The oscillator is disabled if no peripheral is requesting the clock source. z Bit 6 - RUNSTDBY: Run in Standby This bit controls how the XOSC behaves during standby sleep mode: 0: The oscillator is disabled in standby sleep mode. 1: The oscillator is not stopped in standby sleep mode. If XOSC.ONDEMAND is one, the clock source will be running when a peripheral is requesting the clock. If XOSC.ONDEMAND is zero, the clock source will always be running in standby sleep mode. z Bits 5:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 2 - XTALEN: Crystal Oscillator Enable This bit controls the connections between the I/O pads and the external clock or crystal oscillator: 0: External clock connected on XIN. XOUT can be used as general-purpose I/O. 1: Crystal connected to XIN/XOUT. z Bit 1 - ENABLE: Oscillator Enable 0: The oscillator is disabled. 1: The oscillator is enabled. z Bit 0 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 178 15.8.6 32kHz External Crystal Oscillator (XOSC32K) Control Name: XOSC32K Offset: 0x14 Reset: 0x0080 Property: Write-Protected Bit 15 14 13 12 11 10 WRTLOCK 9 8 STARTUP[2:0] Access R R R R/W R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY AAMPEN EN32K XTALEN ENABLE R/W R/W R/W R R/W R/W R/W R 1 0 0 0 0 0 0 0 Access Reset z Bits 15:13 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 12 - WRTLOCK: Write Lock This bit locks the XOSC32K register for future writes to fix the XOSC32K configuration. 0: The XOSC32K configuration is not locked. 1: The XOSC32K configuration is locked. z Bit 11 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 10:8 - STARTUP[2:0]: Oscillator Start-Up Time These bits select the start-up time for the oscillator according to Table 15-9. The OSCULP32K oscillator is used to clock the start-up counter. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 179 Table 15-9. Start-Up Time for 32kHz External Crystal Oscillator STARTUP[2:0] Number of OSCULP32K Clock Cycles Number of XOSC32K Clock Cycles Approximate Equivalent Time (OSCULP = 32kHz)(1)(2)(3) 0x0 1 3 122s 0x1 32 3 1068s 0x2 2048 3 62592s 0x3 4096 3 125092s 0x4 16384 3 500092s 0x5 32768 3 1000092s 0x6 65536 3 2000092s 0x7 131072 3 4000092s Notes: 1. z Number of cycles for the start-up counter. 2. Number of cycles for the synchronization delay, before PCLKSR.XOSC32KRDY is set. 3. Start-up time is n OSCULP32K cycles + 3 XOSC32K cycles. Bit 7 - ONDEMAND: On Demand Control The On Demand operation mode allows an oscillator to be enabled or disabled depending on peripheral clock requests. In On Demand operation mode, i.e., if the ONDEMAND bit has been previously written to one, the oscillator will only be running when requested by a peripheral. If there is no peripheral requesting the oscillator s clock source, the oscillator will be in a disabled state. If On Demand is disabled the oscillator will always be running when enabled. In standby sleep mode, the On Demand operation is still active if the XOSC32K.RUNSTDBY bit is one. If XOSC32K.RUNSTDBY is zero, the oscillator is disabled. 0: The oscillator is always on, if enabled. 1: The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. The oscillator is disabled if no peripheral is requesting the clock source. z Bit 6 - RUNSTDBY: Run in Standby This bit controls how the XOSC32K behaves during standby sleep mode: 0: The oscillator is disabled in standby sleep mode. 1: The oscillator is not stopped in standby sleep mode. If XOSC32K.ONDEMAND is one, the clock source will be running when a peripheral is requesting the clock. If XOSC32K.ONDEMAND is zero, the clock source will always be running in standby sleep mode. z Bit 5 - AAMPEN: Automatic Amplitude Control Enable 0: The automatic amplitude control for the crystal oscillator is disabled. 1: The automatic amplitude control for the crystal oscillator is enabled. z Bit 4 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 180 z Bit 3 - EN32K: 32kHz Output Enable 0: The 32kHz output is disabled. 1: The 32kHz output is enabled. z Bit 2 - XTALEN: Crystal Oscillator Enable This bit controls the connections between the I/O pads and the external clock or crystal oscillator: 0: External clock connected on XIN32. XOUT32 can be used as general-purpose I/O. 1: Crystal connected to XIN32/XOUT32. z Bit 1 - ENABLE: Oscillator Enable 0: The oscillator is disabled. 1: The oscillator is enabled. z Bit 0 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 181 15.8.7 32kHz Internal Oscillator (OSC32K) Control Name: OSC32K Offset: 0x18 Reset: 0x003F0080 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 CALIB[6:0] Access R R/W R/W R/W R/W R/W R/W R/W Reset 0 0 1 1 1 1 1 1 Bit 15 14 13 12 11 10 9 8 WRTLOCK STARTUP[2:0] Access R R R R/W R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY EN32K ENABLE R/W R/W R R R R/W R/W R 1 0 0 0 0 0 0 0 Access Reset z Bits 31:23 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 22:16 - CALIB[6:0]: Oscillator Calibration These bits control the oscillator calibration. This value must be written by the user. Factory calibration values can be loaded from the non-volatile memory. Refer to "NVM Software Calibration Area Mapping" on page 26. z Bits 15:13 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 12 - WRTLOCK: Write Lock This bit locks the OSC32K register for future writes to fix the OSC32K configuration. 0: The OSC32K configuration is not locked. 1: The OSC32K configuration is locked. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 182 z Bit 11 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 10:8 - STARTUP[2:0]: Oscillator Start-Up Time These bits select start-up time for the oscillator according to Table 15-10. The OSCULP32K oscillator is used as input clock to the startup counter. Table 15-10. Start-Up Time for 32kHz Internal Oscillator STARTUP[2:0] Number of OSC32K clock cycles Approximate Equivalent Time (OSCULP= 32 kHz)(1)(2)(3) 0x0 3 92s 0x1 4 122s 0x2 6 183s 0x3 10 305s 0x4 18 549s 0x5 34 1038s 0x6 66 2014s 0x7 130 3967s Notes: 1. z Number of cycles for the start-up counter. 2. Number of cycles for the synchronization delay, before PCLKSR.OSC32KRDY is set. 3. Start-up time is n OSC32K cycles + 2 OSC32K cycles. Bit 7 - ONDEMAND: On Demand Control The On Demand operation mode allows an oscillator to be enabled or disabled depending on peripheral clock requests. In On Demand operation mode, i.e., if the ONDEMAND bit has been previously written to one, the oscillator will only be running when requested by a peripheral. If there is no peripheral requesting the oscillator s clock source, the oscillator will be in a disabled state. If On Demand is disabled the oscillator will always be running when enabled. In standby sleep mode, the On Demand operation is still active if the OSC32K.RUNSTDBY bit is one. If OSC32K.RUNSTDBY is zero, the oscillator is disabled. 0: The oscillator is always on, if enabled. 1: The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. The oscillator is disabled if no peripheral is requesting the clock source. z Bit 6 - RUNSTDBY: Run in Standby This bit controls how the OSC32K behaves during standby sleep mode: 0: The oscillator is disabled in standby sleep mode. 1: The oscillator is not stopped in standby sleep mode. If OSC32K.ONDEMAND is one, the clock source will be running when a peripheral is requesting the clock. If OSC32K.ONDEMAND is zero, the clock source will always be running in standby sleep mode. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 183 z Bits 5:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 3 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 2 - EN32K: 32kHz Output Enable 0: The 32kHz output is disabled. 1: The 32kHz output is enabled. z Bit 1 - ENABLE: Oscillator Enable 0: The oscillator is disabled. 1: The oscillator is enabled. z Bit 0 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 184 15.8.8 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control Name: OSCULP32K Offset: 0x1C Reset: 0xXX Property: Write-Protected Bit 7 6 5 4 3 WRTLOCK Access Reset z 2 1 0 CALIB[4:0] R/W R R R/W R/W R/W R/W R/W 0 0 0 X X X X X Bit 7 - WRTLOCK: Write Lock This bit locks the OSCULP32K register for future writes to fix the OSCULP32K configuration. 0: The OSCULP32K configuration is not locked. 1: The OSCULP32K configuration is locked. z Bits 6:5 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 4:0 - CALIB[4:0]: Oscillator Calibration These bits control the oscillator calibration. These bits are loaded from Flash Calibration at startup. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 185 15.8.9 8MHz Internal Oscillator (OSC8M) Control Name: OSC8M Offset: 0x20 Reset: 0xXXXX0382 Property: Write-Protected Bit 31 30 29 28 27 26 FRANGE[1:0] Access 25 24 CALIB[11:8] R/W R/W R R R/W R/W R/W R/W Reset X X 0 0 X X X X Bit 23 22 21 20 19 18 17 16 CALIB[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset X X X X X X X X Bit 15 14 13 12 11 10 9 8 PRESC[1:0] Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 1 1 Bit 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY R/W R/W R R R R R/W R 1 0 0 0 0 0 1 0 Access Reset z ENABLE Bits 31:30 - FRANGE[1:0]: Oscillator Frequency Range These bits control the oscillator frequency range according to the table below. These bits are loaded from Flash Calibration at startup. Table 15-11. Oscillator Frequency Range FRANGE[1:0] z Description 0x0 4 to 6MHz 0x1 6 to 8MHz 0x2 8 to 11MHz 0x3 11 to 15MHz Bits 29:28 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 186 z Bits 27:16 - CALIB[11:0]: Oscillator Calibration These bits control the oscillator calibration. The calibration field is split in two: CALIB[11:6] is for temperature calibration CALIB[5:0] is for overall process calibration These bits are loaded from Flash Calibration at startup. z Bits 15:10 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 9:8 - PRESC[1:0]: Oscillator Prescaler These bits select the oscillator prescaler factor setting according to the table below. Table 15-12. Oscillator Prescaler PRESC[1:0] z Description 0x0 1 0x1 2 0x2 4 0x3 8 Bit 7 - ONDEMAND: On Demand Control The On Demand operation mode allows an oscillator to be enabled or disabled depending on peripheral clock requests. In On Demand operation mode, i.e., if the ONDEMAND bit has been previously written to one, the oscillator will only be running when requested by a peripheral. If there is no peripheral requesting the oscillator s clock source, the oscillator will be in a disabled state. If On Demand is disabled the oscillator will always be running when enabled. In standby sleep mode, the On Demand operation is still active if the OSC8M.RUNSTDBY bit is one. If OSC8M.RUNSTDBY is zero, the oscillator is disabled. 0: The oscillator is always on, if enabled. 1: The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. The oscillator is disabled if no peripheral is requesting the clock source. z Bit 6 - RUNSTDBY: Run in Standby This bit controls how the OSC8M behaves during standby sleep mode: 0: The oscillator is disabled in standby sleep mode. 1: The oscillator is not stopped in standby sleep mode. If OSC8M.ONDEMAND is one, the clock source will be running when a peripheral is requesting the clock. If OSC8M.ONDEMAND is zero, the clock source will always be running in standby sleep mode. z Bits 5:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 1 - ENABLE: Oscillator Enable 0: The oscillator is disabled or being enabled. 1: The oscillator is enabled or being disabled. The user must ensure that the OSC8M is fully disabled before enabling it, and that the OSC8M is fully enabled before disabling it by reading OSC8M.ENABLE. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 187 z Bit 0 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 188 15.8.10 DFLL48M Control Name: DFLLCTRL Offset: 0x24 Reset: 0x0080 Property: Write-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 WAITLOCK BPLCKC QLDIS CCDIS Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY USBCRM LLAW STABLE MODE ENABLE R/W R/W R/W R/W R/W R/W R/W R 1 0 0 0 0 0 0 0 Access Reset z Bits 15:12 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 11 - WAITLOCK: Wait Lock This bit controls the DFLL output clock, depending on lock status: 0: Output clock before the DFLL is locked. 1: Output clock when DFLL is locked. z Bit 10 - BPLCKC: Bypass Coarse Lock This bit controls the coarse lock procedure: 0: Bypass coarse lock is disabled. 1: Bypass coarse lock is enabled. z Bit 9 - QLDIS: Quick Lock Disable 0: Quick Lock is enabled. 1: Quick Lock is disabled. z Bit 8 - CCDIS: Chill Cycle Disable 0: Chill Cycle is enabled. 1: Chill Cycle is disabled. z Bit 7 - ONDEMAND: On Demand Control The On Demand operation mode allows an oscillator to be enabled or disabled depending on peripheral clock requests. In On Demand operation mode, i.e., if the ONDEMAND bit has been previously written to one, the oscillator will only be running when requested by a peripheral. If there is no peripheral requesting the oscillator s clock source, the oscillator will be in a disabled state. If On Demand is disabled the oscillator will always be running when enabled. In standby sleep mode, the On Demand operation is still active if the DFLLCTRL.RUNSTDBY bit is one. If DFLLCTRL.RUNSTDBY is zero, the oscillator is disabled. 0: The oscillator is always on, if enabled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 189 1: The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. The oscillator is disabled if no peripheral is requesting the clock source. z Bit 6 - RUNSTDBY: Run in Standby This bit controls how the DFLL behaves during standby sleep mode: 0: The oscillator is disabled in standby sleep mode. 1: The oscillator is not stopped in standby sleep mode. If DFLLCTRL.ONDEMAND is one, the clock source will be running when a peripheral is requesting the clock. If DFLLCTRL.ONDEMAND is zero, the clock source will always be running in standby sleep mode. z Bit 5 - USBCRM: USB Clock Recovery Mode 0: USB Clock Recovery Mode is disabled. 1: USB Clock Recovery Mode is enabled. z Bit 4 - LLAW: Lose Lock After Wake 0: Locks will not be lost after waking up from sleep modes if the DFLL clock has been stopped. 1: Locks will be lost after waking up from sleep modes if the DFLL clock has been stopped. z Bit 3 - STABLE: Stable DFLL Frequency 0: FINE calibration tracks changes in output frequency. 1: FINE calibration register value will be fixed after a fine lock. z Bit 2 - MODE: Operating Mode Selection 0: The DFLL operates in open-loop operation. 1: The DFLL operates in closed-loop operation. z Bit 1 - ENABLE: DFLL Enable 0: The DFLL oscillator is disabled. 1: The DFLL oscillator is enabled. Due to synchronization, there is delay from updating the register until the peripheral is enabled/disabled. The value written to DFLLCTRL.ENABLE will read back immediately after written. z Bit 0 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 190 15.8.11 DFLL48M Value Name: DFLLVAL Offset: 0x28 Reset: 0x00000000 Property: Read-Synchronized, Write-Protected Bit 31 30 29 28 27 26 25 24 DIFF[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DIFF[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 COARSE[5:0] Access FINE[9:8] R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 FINE[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 31:16 - DIFF[15:0]: Multiplication Ratio Difference In closed-loop mode (DFLLCTRL.MODE is written to one), this bit group indicates the difference between the ideal number of DFLL cycles and the counted number of cycles. This value is not updated in open-loop mode, and should be considered invalid in that case. z Bits 15:10 - COARSE[5:0]: Coarse Value Set the value of the Coarse Calibration register. In closed-loop mode, this field is read-only. z Bits 9:0 - FINE[9:0]: Fine Value Set the value of the Fine Calibration register. In closed-loop mode, this field is read-only. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 191 15.8.12 DFLL48M Multiplier Name: DFLLMUL Offset: 0x2C Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 CSTEP[5:0] Access 24 FSTEP[9:8] R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 FSTEP[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 MUL[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MUL[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 31:26 - CSTEP[5:0]: Coarse Maximum Step This bit group indicates the maximum step size allowed during coarse adjustment in closed-loop mode. When adjusting to a new frequency, the expected output frequency overshoot depends on this step size. z Bits 25:16 - FSTEP[9:0]: Fine Maximum Step This bit group indicates the maximum step size allowed during fine adjustment in closed-loop mode. When adjusting to a new frequency, the expected output frequency overshoot depends on this step size. z Bits 15:0 - MUL[15:0]: DFLL Multiply Factor This field determines the ratio of the CLK_DFLL output frequency to the CLK_DFLL_REF input frequency. Writing to the MUL bits will cause locks to be lost and the fine calibration value to be reset to its midpoint. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 192 15.8.13 DFLL48M Synchronization Name: DFLLSYNC Offset: 0x30 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 READREQ Access W R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bit 7 - READREQ: Read Request To be able to read the current value of DFLLVAL in closed-loop mode, this bit should be written to one. The updated value is available in DFLLVAL when PCLKSR.DFLLRDY is set. z Bits 6:0 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 193 15.8.14 3.3V Brown-Out Detector (BOD33) Control Name: BOD33 Offset: 0x34 Reset: 0x00XX00XX Property: Write-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 LEVEL[5:0] Access R R R/W R/W R/W R/W R/W R/W Reset 0 0 X X X X X X Bit 15 14 13 12 11 10 9 8 CEN MODE PSEL[3:0] Access R/W R/W R/W R/W R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 HYST ENABLE RUNSTDBY ACTION[1:0] Access R R/W R R/W R/W R/W R/W R Reset 0 0 0 X X X X 0 z Bits 31:22 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 21:16 - LEVEL[5:0]: BOD33 Threshold Level This field sets the triggering voltage threshold for the BOD33. See the "Electrical Characteristics" on page 1055 for actual voltage levels. Note that any change to the LEVEL field of the BOD33 register should be done when the BOD33 is disabled in order to avoid spurious resets or interrupts. These bits are loaded from Flash User Row at startup. Refer to "NVM User Row Mapping" on page 25 for more details. z Bits 15:12 - PSEL[3:0]: Prescaler Select Selects the prescaler divide-by output for the BOD33 sampling mode according to the table below. The input clock comes from the OSCULP32K 1kHz output. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 194 Table 15-13. Prescaler Select PSEL[3:0] Name Description 0x0 DIV2 Divide clock by 2 0x1 DIV4 Divide clock by 4 0x2 DIV8 Divide clock by 8 0x3 DIV16 Divide clock by 16 0x4 DIV32 Divide clock by 32 0x5 DIV64 Divide clock by 64 0x6 DIV128 Divide clock by 128 0x7 DIV256 Divide clock by 256 0x8 DIV512 Divide clock by 512 0x9 DIV1K Divide clock by 1024 0xA DIV2K Divide clock by 2048 0xB DIV4K Divide clock by 4096 0xC DIV8K Divide clock by 8192 0xD DIV16K Divide clock by 16384 0xE DIV32K Divide clock by 32768 0xF DIV64K Divide clock by 65536 z Bits 11:10 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 9 - CEN: Clock Enable 0: The BOD33 sampling clock is either disabled and stopped, or enabled but not yet stable. 1: The BOD33 sampling clock is either enabled and stable, or disabled but not yet stopped. Writing a zero to this bit will stop the BOD33 sampling clock. Writing a one to this bit will start the BOD33 sampling clock. z Bit 8 - MODE: Operation Mode 0: The BOD33 operates in continuous mode. 1: The BOD33 operates in sampling mode. z Bit 7 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 6 - RUNSTDBY: Run in Standby 0: The BOD33 is disabled in standby sleep mode. 1: The BOD33 is enabled in standby sleep mode. z Bit 5 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 195 z Bits 4:3 - ACTION[1:0]: BOD33 Action These bits are used to select the BOD33 action when the supply voltage crosses below the BOD33 threshold. These bits are loaded from Flash User Row at startup. Refer to "NVM User Row Mapping" on page 25 for more details. Table 15-14. BOD33 Action ACTION[1:0] Name 0x0 NONE No action 0x1 RESET The BOD33 generates a reset 0x2 INTERRUPT 0x3 z Description The BOD33 generates an interrupt Reserved Bit 2 - HYST: Hysteresis This bit indicates whether hysteresis is enabled for the BOD33 threshold voltage: 0: No hysteresis. 1: Hysteresis enabled. This bit is loaded from Flash User Row at startup. Refer to "NVM User Row Mapping" on page 25 for more details. z Bit 1 - ENABLE: Enable 0: BOD33 is disabled. 1: BOD33 is enabled. This bit is loaded from Flash User Row at startup. Refer to "NVM User Row Mapping" on page 25 for more details. z Bit 0 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 196 15.8.15 Voltage Regulator System (VREG) Control Name: VREG Offset: 0x3C Reset: 0x0X00 Property: Write-Protected Bit 15 14 13 12 11 10 9 8 FORCELDO Access R R R/W R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RUNSTDBY Access R R/W R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 15:14 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 13 - FORCELDO: Force LDO Voltage Regulator 0: The voltage regulator is in low power and low drive configuration in standby sleep mode. 1: The voltage regulator is in low power and high drive configuration in standby sleep mode. z Bits 12:7 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 6 - RUNSTDBY: Run in Standby 0: The voltage regulator is in low power configuration in standby sleep mode. 1: The voltage regulator is in normal configuration in standby sleep mode. z Bits 5:0 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 197 15.8.16 Voltage References System (VREF) Control Name: VREF Offset: 0x40 Reset: 0x0XXX0000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 CALIB[10:8] Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 X X X Bit 23 22 21 20 19 18 17 16 CALIB[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset X X X X X X X X Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BGOUTEN TSEN Access R R R R R R/W R/W R Reset 0 0 0 0 0 0 0 0 z Bits 31:27 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 26:16 - CALIB[10:0]: Bandgap Voltage Generator Calibration These bits are used to calibrate the output level of the bandgap voltage reference. These bits are loaded from Flash Calibration Row at startup. z Bits 15:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 2 - BGOUTEN: Bandgap Output Enable 0: The bandgap output is not available as an ADC input channel. 1: The bandgap output is routed to an ADC input channel. z Bit 1 - TSEN: Temperature Sensor Enable 0: Temperature sensor is disabled. 1: Temperature sensor is enabled and routed to an ADC input channel. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 198 z Bit 0 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 199 15.8.17 DPLL Control A Name: DPLLCTRLA Offset: 0x44 Reset: 0x80 Property: Write-Protected Bit Access Reset z 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY R/W R/W R R R R R/W R 1 0 0 0 0 0 0 0 ENABLE Bit 7 - ONDEMAND: On Demand Clock Activation 0: The DPLL is always on when enabled. 1: The DPLL is activated only when a peripheral request the DPLL as a source clock. The DPLLCTRLA.ENABLE bit must be one to validate that operation, otherwise the peripheral request has no effect. z Bit 6 - RUNSTDBY: Run in Standby 0: The DPLL is disabled in standby sleep mode. 1: The DPLL is not stopped in standby sleep mode. z Bits 5:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 1 - ENABLE: DPLL Enable 0: The DPLL is disabled. 1: The DPLL is enabled. The software operation of enabling or disabling the DPLL takes a few clock cycles, so check the DPLLSTATUS.ENABLE status bit to identify when the DPLL is successfully activated or disabled. z Bit 0 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 200 15.8.18 DPLL Ratio Control Name: DPLLRATIO Offset: 0x48 Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 LDRFRAC[3:0] Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 LDR[11:8] Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 LDR[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 31:20 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 19:16 - LDRFRAC[3:0]: Loop Divider Ratio Fractional Part Write this field with the fractional part of the frequency multiplier. z Bits 15:12 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 11:0 - LDR[11:0]: Loop Divider Ratio Write this field with the integer part of the frequency multiplier. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 201 15.8.19 DPLL Control B Name: DPLLCTRLB Offset: 0x4C Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 DIV[10:8] Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DIV[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 LBYPASS LTIME[2:0] Access R R R R/W R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 WUF LPEN REFCLK[1:0] FILTER[1:0] Access R R R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 31:27 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 26:16 - DIV[10:0]: Clock Divider These bits are used to set the XOSC clock source division factor. Refer to "Principle of Operation" on page 153. z Bits 15:13 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 12 - LBYPASS: Lock Bypass 0: Normal Mode: the CLK_FDPLL96M is turned off when lock signal is low. 1: Lock Bypass Mode: the CLK_FDPLL96M is always running, lock is irrelevant. z Bit 11 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 202 z Bits 10:8 - LTIME[2:0]: Lock Time These bits select Lock Timeout. Table 15-15. Lock Time LTIME[2:0] Name 0x0 DEFAULT 0x1-0x3 Description No time-out Reserved 0x4 8MS Time-out if no lock within 8 ms 0x5 9MS Time-out if no lock within 9 ms 0x6 10MS Time-out if no lock within 10 ms 0x7 11MS Time-out if no lock within 11 ms z Bits 7:6 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 5:4 - REFCLK[1:0]: Reference Clock Selection These bits select the CLK_FDPLL96M_REF source. Table 15-16. Reference Clock Selection REFCLK[1:0] Name 0x0 XOSC32 0x1 XOSC 0x2 GCLK_DPLL 0x3 z Description XOSC32 clock reference XOSC clock reference GCLK_DPLL clock reference Reserved Bit 3 - WUF: Wake Up Fast 0: DPLL CK output is gated until complete startup time and lock time. 1: DPLL CK output is gated until startup time only. z Bit 2 - LPEN: Low-Power Enable 0: The time to digital converter is selected. 1: The time to digital converter is not selected, this will improve power consumption but increase the output jitter. z Bits 1:0 - FILTER[1:0]: Proportional Integral Filter Selection These bits select the DPLL filter type. Table 15-17. Proportional Integral Filter Selection FILTER[1:0] Name Description 0x0 DEFAULT 0x1 LBFILT Low bandwidth filter 0x2 HBFILT High bandwidth filter 0x3 HDFILT High damping filter Default filter mode Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 203 15.8.20 DPLL Status Name: DPLLSTATUS Offset: 0x50 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 DIV ENABLE CLKRDY LOCK Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 7:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 3 - DIV: Divider Enable 0: The reference clock divider is disabled. 1: The reference clock divider is enabled. z Bit 2 - ENABLE: DPLL Enable 0: The DPLL is disabled. 1: The DPLL is enabled. z Bit 1 - CLKRDY: Output Clock Ready 0: The DPLL output clock is off 1: The DPLL output clock in on. z Bit 0 - LOCK: DPLL Lock Status 0: The DPLL Lock signal is cleared. 1: The DPLL Lock signal is asserted. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 204 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 205 16. WDT - Watchdog Timer 16.1 Overview The Watchdog Timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover from error situations such as runaway or deadlocked code. The WDT is configured to a predefined time-out period, and is constantly running when enabled. If the WDT is not cleared within the time-out period, it will issue a system reset. An early-warning interrupt is available to indicate an upcoming watchdog time-out condition. The window mode makes it possible to define a time slot (or window) inside the total time-out period during which the WDT must be cleared. If the WDT is cleared outside this window, either too early or too late, a system reset will be issued. Compared to the normal mode, this can also catch situations where a code error causes the WDT to be cleared frequently. When enabled, the WDT will run in active mode and all sleep modes. It is asynchronous and runs from a CPUindependent clock source.The WDT will continue operation and issue a system reset or interrupt even if the main clocks fail. 16.2 Features z Issues a system reset if the Watchdog Timer is not cleared before its time-out period z Early Warning interrupt generation z Asynchronous operation from dedicated oscillator z Two types of operation: z z Normal mode Window mode z Selectable time-out periods, from 8 cycles to 16,000 cycles in normal mode or 16 cycles to 32,000 cycles in window mode z Always-on capability 16.3 Block Diagram Figure 16-1. WDT Block Diagram 0xA5 0 CLEAR GCLK_WDT COUNT PER/WINDOW/EWOFFSET Early Warning Interrupt Reset Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 206 16.4 Signal Description Not applicable. 16.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 16.5.1 I/O Lines Not applicable. 16.5.2 Power Management The WDT can continue to operate in any sleep mode where the selected source clock is running. The WDT interrupts can be used to wake up the device from sleep modes. The events can trigger other operations in the system without exiting sleep modes. Refer to "PM - Power Manager" on page 112 for details on the different sleep modes. 16.5.3 Clocks The WDT bus clock (CLK_WDT_APB) is enabled by default, and can be enabled and disabled in the Power Manager. Refer to "PM - Power Manager" on page 112 for details. A generic clock (GCLK_WDT) is required to clock the WDT. This clock must be configured and enabled in the Generic Clock Controller before using the WDT. Refer to "GCLK - Generic Clock Controller" on page 90 for details. This generic clock is asynchronous to the user interface clock (CLK_WDT_APB). Due to this asynchronicity, accessing certain registers will require synchronization between the clock domains. Refer to "Synchronization" on page 212 for further details. GCLK_WDT is intended to be sourced from the clock of the internal ultra-low-power (ULP) oscillator. Due to the ultralow-power design, the oscillator is not very accurate, and so the exact time-out period may vary from device to device. This variation must be kept in mind when designing software that uses the WDT to ensure that the time-out periods used are valid for all devices. For more information on ULP oscillator accuracy, consult the "Ultra Low Power Internal 32kHz RC Oscillator (OSCULP32K) Characteristics" on page 1088. GCLK_WDT can also be clocked from other sources if a more accurate clock is needed, but at the cost of higher power consumption. 16.5.4 DMA Not applicable. 16.5.5 Interrupts The interrupt request line is connected to the Interrupt Controller. Using the WDT interrupts requires the Interrupt Controller to be configured first. Refer to "Nested Vector Interrupt Controller" on page 29 for details. 16.5.6 Events Not applicable. 16.5.7 Debug Operation When the CPU is halted in debug mode, the WDT will halt normal operation. If the WDT is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. The WDT can be forced to halt operation during debugging. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 207 16.5.8 Register Access Protection All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the following registers: z Interrupt Flag Status and Clear register (INTFLAG) Write-protection is denoted by the Write-Protection property in the register description. When the CPU is halted in debug mode, all write-protection is automatically disabled. Write-protection does not apply for accesses through an external debugger. Refer to "PAC - Peripheral Access Controller" on page 36 for details. 16.5.9 Analog Connections Not applicable. 16.6 Functional Description 16.6.1 Principle of Operation The Watchdog Timer (WDT) is a system for monitoring correct program operation, making it possible to recover from error situations such as runaway code by issuing a reset. When enabled, the WDT is a constantly running timer that is configured to a predefined time-out period. Before the end of the time-out period, the WDT should be reconfigured. The WDT has two modes of operation, normal and window. Additionally, the user can enable Early Warning interrupt generation in each of the modes. The description for each of the basic modes is given below. The settings in the Control register (CTRL) and the Interrupt Enable register (INTENCLR/SET - refer to INTENCLR) determine the mode of operation, as illustrated in Table 16-1. The WDT operating modes are determined by settings of Enable bit in CTRL register (CTRL.ENABLE), Window Mode Enable bit in CTRL register (CTRL.WEN) and Early Warning Interrupt Enable bit in INTENSET/INTENCLR registers (INTENSET.EW/ EW.INTENCLR.EW) Table 16-1. WDT Operating Modes CTRL.ENABLE CTRL.WEN INTENSET.EW Mode 0 x x Stopped 1 0 0 Normal 1 0 1 Normal with Early Warning interrupt 1 1 0 Window 1 1 1 Window with Early Warning interrupt 16.6.2 Basic Operation 16.6.2.1 Initialization The following bits are enable-protected: z Window Mode Enable in the Control register (CTRL.WEN) z Always-On in the Control register (CTRL-ALWAYSON) The following registers are enable-protected: z Configuration register (CONFIG) z Early Warning Interrupt Control register (EWCTRL) Any writes to these bits or registers when the WDT is enabled or is being enabled (CTRL.ENABLE is one) will be discarded. Writes to these registers while the WDT is being disabled will be completed after the disabling is complete. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 208 Enable-protection is denoted by the Enable-Protected property in the register description. Initialization of the WDT can be done only while the WDT is disabled. Normal Mode z Defining the required Time-Out Period bits in the Configuration register (CONFIG.PER). Normal Mode with Early Warning interrupt z Defining the required Time-Out Period bits in the Configuration register (CONFIG.PER). z Defining Early Warning Interrupt Time Offset bits in the Early Warning Interrupt Control register (EWCTRL. EWOFFSET). z Setting Early Warning Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.EW). Window Mode z Defining Time-Out Period bits in the Configuration register (CONFIG.PER). z Defining Window Mode Time-Out Period bits in the Configuration register (CONFIG.WINDOW). z Setting Window Enable bit in the Control register (CTRL.WEN). Window Mode with Early Warning interrupt z Defining Time-Out Period bits in the Configuration register (CONFIG.PER). z Defining Window Mode Time-Out Period bits in the Configuration register (CONFIG.WINDOW). z Setting Window Enable bit in the Control register (CTRL.WEN). z Defining Early Warning Interrupt Time Offset bits in the Early Warning Interrupt Control register (EWCTRL. EWOFFSET). z Setting Early Warning Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.EW). 16.6.2.2 Configurable Reset Values On a power-on reset, some registers will be loaded with initial values from the NVM User Row. Refer to "NVM User Row Mapping" on page 25 for more details. This encompasses the following bits and bit groups: z Enable bit in the Control register (CTRL.ENABLE) z Always-On bit in the Control register (CTRL.ALWAYSON) z Watchdog Timer Windows Mode Enable bit in the Control register (CTRL.WEN) z Watchdog Timer Windows Mode Time-Out Period bits in the Configuration register (CONFIG.WINDOW) z Time-Out Period in the Configuration register (CONFIG.PER) z Early Warning Interrupt Time Offset bits in the Early Warning Interrupt Control register (EWCTRL.EWOFFSET) For more information about fuse locations, see "NVM User Row Mapping" on page 25. 16.6.2.3 Enabling and Disabling The WDT is enabled by writing a one to the Enable bit in the Control register (CTRL.ENABLE). The WDT is disabled by writing a zero to CTRL.ENABLE. The WDT can be disabled only while the Always-On bit in the Control register (CTRL.ALWAYSON) is zero. 16.6.2.4 Normal Mode In normal-mode operation, the length of a time-out period is configured in CONFIG.PER. The WDT is enabled by writing a one to the Enable bit in the Control register (CTRL.ENABLE). Once enabled, if the WDT is not cleared from the application code before the time-out occurs, the WDT will issue a system reset. There are 12 possible WDT time-out (TOWDT) periods, selectable from 8ms to 16s, and the WDT can be cleared at any time during the time-out period. A new Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 209 WDT time-out period will be started each time the WDT is cleared by writing 0xA5 to the Clear register (CLEAR). Writing any value other than 0xA5 to CLEAR will issue an immediate system reset. By default, WDT issues a system reset upon a time-out, and the early warning interrupt is disabled. If an early warning interrupt is required, the Early Warning Interrupt Enable bit in the Interrupt Enable register (INTENSET.EW) must be enabled. Writing a one to the Early Warning Interrupt bit in the Interrupt Enable Set register (INTENSET.EW) enables the interrupt, and writing a one to the Early Warning Interrupt bit in the Interrupt Enable Clear register (INTENCLR.EW) disables the interrupt. If the Early Warning Interrupt is enabled, an interrupt is generated prior to a watchdog time-out condition. In normal mode, the Early Warning Offset bits in the Early Warning Interrupt Control register (EWCTRL.EWOFFSET) define the time where the early warning interrupt occurs. The normal-mode operation is illustrated in Figure 16-2. The Early Warning Offset bits define the number of GCLK_WDT clocks before the interrupt is generated, relative to the start of the watchdog time-out period. For example, if the WDT is operating in normal mode with CONFIG.PER = 0x2 and EWCTRL.EWOFFSET = 0x1, the Early Warning interrupt is generated 16 GCLK_WDT clock cycles from the start of the watchdog time-out period, and the watchdog time-out system reset is generated 32 GCLK_WDT clock cycles from the start of the watchdog time-out period. The user must take caution when programming the Early Warning Offset bits. If these bits define an Early Warning interrupt generation time greater than the watchdog time-out period, the watchdog time-out system reset is generated prior to the Early Warning interrupt. Thus, the Early Warning interrupt will never be generated. Figure 16-2. Normal-Mode Operation System Reset WDT Count Timely WDT Clear PER[3:0]=1 WDT Timeout Early Warning Interrupt EWOFFSET[3:0]=0 5 10 15 20 25 30 TOWDT 35 t [ms] 16.6.2.5 Window Mode In window-mode operation, the WDT uses two different time-out periods, a closed window time-out period (TOWDTW) and the normal, or open, time-out period (TOWDT). The closed window time-out period defines a duration from 8ms to 16s where the WDT cannot be reset. If the WDT is cleared during this period, the WDT will issue a system reset. The normal WDT time-out period, which is also from 8ms to 16s, defines the duration of the open period during which the WDT can be cleared. The open period will always follow the closed period, and so the total duration of the time-out period is the sum of the closed window and the open window time-out periods. The closed window is defined by the Window Period bits in the Configuration register (CONFIG.WINDOW), and the open window is defined by the Period bits in the Configuration register (CONFIG.PER). By default, the WDT issues a system reset upon a time-out and the Early Warning interrupt is disabled. If an Early Warning interrupt is required, INTENCLR/SET.EW must be set. Writing a one to INTENSET.EW enables the interrupt, and writing a one to INTENCLR.EW disables the interrupt. If the Early Warning interrupt is enabled in window mode, the interrupt is generated at the start of the open window period. In a typical application where the system is in sleep mode, it can use this interrupt to wake up and clear the Watchdog Timer, after which the system can perform other tasks or return to sleep mode. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 210 The window mode operation is illustrated in Figure 16-3. Figure 16-3. Window-Mode Operation WDT Count Timely WDT Clear Open PER[3:0]=0 Early Warning Interrupt Early WDT Clear Closed WINDOW[3:0]=0 WDT Timeout 5 10 15 20 TOWDTW 25 30 TOWDT 35 t [ms] 16.6.3 Additional Features 16.6.3.1 Always-On Mode The always-on mode is enabled by writing a one to the Always-On bit in the Control register (CTRL.ALWAYSON). When the always-on mode is enabled, the WDT runs continuously, regardless of the state of CTRL.ENABLE. Once written, the Always-On bit can only be cleared by a power-on reset. The Configuration (CONFIG) and Early Warning Control (EWCTRL) registers are read-only registers while the CTRL.ALWAYSON bit is set. Thus, the time period configuration bits (CONFIG.PER, CONFIG.WINDOW, EWCTRL.EWOFFSET) of the WDT cannot be changed. Enabling or disabling window-mode operation by writing the Window Enable bit (CTRL.WEN) is allowed while in the always-on mode, but note that CONFIG.PER cannot be changed. The Interrupt Clear and Interrupt Set registers are accessible in the always-on mode. The Early Warning interrupt can still be enabled or disabled while in the always-on mode, but note that EWCTRL.EWOFFSET cannot be changed. Table 16-2 shows the operation of the WDT when CTRL.ALWAYSON is set. Table 16-2. WDT Operating Modes With Always-On CTRL.WEN INTENSET.EW Mode 0 0 Always-on and normal mode 0 1 Always-on and normal mode with Early Warning interrupt 1 0 Always-on and window mode 1 1 Always-on and window mode with Early Warning interrupt 16.6.4 Interrupts The WDT has the following interrupt sources: z Early Warning (EW): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 211 corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the WDT is reset. See INTFLAG for details on how to clear interrupt flags. The WDT has one common interrupt request line for all the interrupt sources. The user must read INTFLAG to determine which interrupt condition is present. Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to "Nested Vector Interrupt Controller" on page 29 for details. 16.6.5 Synchronization Due to the asynchronicity between CLK_WDT_APB and GCLK_WDT some registers must be synchronized when accessed. A register can require: z Synchronization when written z Synchronization when read z Synchronization when written and read z No synchronization When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. The Synchronization Ready interrupt can be used to signal when synchronization is complete. This can be accessed via the Synchronization Ready Interrupt Flag in the Interrupt Flag Status and Clear register (INTFLAG.SYNCRDY). If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is stalled. The following registers need synchronization when written: z Control register (CTRL) z Clear register (CLEAR) Write-synchronization is denoted by the Write-Synchronized property in the register description. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 212 16.7 Register Summary Table 16-3. Register Summary Offset Name Bit Pos. 0x0 CTRL 7:0 0x1 CONFIG 7:0 0x2 EWCTRL 7:0 0x3 Reserved ALWAYSON WEN WINDOW[3:0] ENABLE PER[3:0] EWOFFSET[3:0] 0x4 INTENCLR 7:0 EW 0x5 INTENSET 7:0 EW 0x6 INTFLAG 7:0 EW 0x7 STATUS 7:0 0x8 CLEAR 7:0 SYNCBUSY CLEAR[7:0] Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 213 16.8 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protected property in each individual register description. Please refer to "Register Access Protection" on page 208 for details. Some registers require synchronization when read and/or written. Synchronization is denoted by the Write-Synchronized or the Read-Synchronized property in each individual register description. Please refer to "Synchronization" on page 212 for details. Some registers are enable-protected, meaning they can be written only when the WDT is disabled. Enable-protection is denoted by the Enable-Protected property in each individual register description. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 214 16.8.1 Control Name: CTRL Offset: 0x0 Reset: 0xXX Property: Enable-Protected, Write-Protected, Write-Synchronized Bit 7 6 5 4 3 ALWAYSON Access 1 WEN ENABLE 0 R/W R R R R R/W R/W R X 0 0 0 0 X X 0 Reset z 2 Bit 7 - ALWAYSON: Always-On This bit allows the WDT to run continuously. After being written to one, this bit cannot be written to zero, and the WDT will remain enabled until a power-on reset is received. When this bit is one, the Control register (CTRL), the Configuration register (CONFIG) and the Early Warning Control register (EWCTRL) will be read-only, and any writes to these registers are not allowed. Writing a zero to this bit has no effect. 0: The WDT is enabled and disabled through the ENABLE bit. 1: The WDT is enabled and can only be disabled by a power-on reset (POR). This bit is not enable-protected. This bit is loaded from NVM User Row at startup. Refer to "NVM User Row Mapping" on page 25 for more details. z Bits 6:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 2 - WEN: Watchdog Timer Window Mode Enable This bit enables window mode. This bit can only be written when CTRL.ENABLE is zero or CTRL.ALWAYSON is one: z When CTRL.ALWAYSON=0, this bit is enable-protected by CTRL.ENABLE. z When CTRL.ALWAYSON=1 this bit is not enable-protected by CTRL.ENABLE. The initial value of this bit is loaded from Flash Calibration. 0: Window mode is disabled (normal operation). 1: Window mode is enabled. This bit is loaded from NVM User Row at startup. Refer to "NVM User Row Mapping" on page 25 for more details. z Bit 1 - ENABLE: Enable This bit enables or disables the WDT. Can only be written while CTRL.ALWAYSON is zero. 0: The WDT is disabled. 1: The WDT is enabled. Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete. This bit is not enable-protected. This bit is loaded from NVM User Row at startup. Refer to "NVM User Row Mapping" on page 25 for more details. z Bit 0 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 215 16.8.2 Configuration Name: CONFIG Offset: 0x1 Reset: 0xXX Property: Enable-Protected, Write-Protected, Write-Synchronized Bit 7 6 5 4 3 2 WINDOW[3:0] Access Reset z 1 0 PER[3:0] R/W R/W R/W R/W R/W R/W R/W R/W X X X X X X X X Bits 7:4 - WINDOW[3:0]: Window Mode Time-Out Period In window mode, these bits determine the watchdog closed window period as a number of oscillator cycles. The closed window periods are defined in Table 16-4. These bits are loaded from NVM User Row at startup. Refer to "NVM User Row Mapping" on page 25 for more details. Table 16-4. Window Mode Time-Out Period WINDOW[3:0] 0x0 8 clock cycles 0x1 16 clock cycles 0x2 32 clock cycles 0x3 64 clock cycles 0x4 128 clock cycles 0x5 256 clock cycles 0x6 512 clock cycles 0x7 1024 clock cycles 0x8 2048 clock cycles 0x9 4096 clock cycles 0xA 8192 clock cycles 0xB 16384 clock cycles 0xC-0xF z Description Reserved Bits 3:0 - PER[3:0]: Time-Out Period These bits determine the watchdog time-out period as a number of GCLK_WDT clock cycles. In window mode operation, these bits define the open window period. The different typical time-out periods are found in Table 16-5. These bits are loaded from NVM User Row at startup. Refer to "NVM User Row Mapping" on page 25 for more details. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 216 Table 16-5. Time-Out Period PER[3:0] Description 0x0 8 clock cycles 0x1 16 clock cycles 0x2 32 clock cycles 0x3 64 clock cycles 0x4 128 clock cycles 0x5 256 clock cycles 0x6 512 clock cycles 0x7 1024 clock cycles 0x8 2048 clock cycles 0x9 4096 clock cycles 0xA 8192 clock cycles 0xB 16384 clock cycles 0xC-0xF Reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 217 16.8.3 Early Warning Interrupt Control Name: EWCTRL Offset: 0x2 Reset: 0x0X Property: Enable-Protected, Write-Protected Bit 7 6 5 4 3 2 1 0 EWOFFSET[3:0] Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 X X X X z Bits 7:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 3:0 - EWOFFSET[3:0]: Early Warning Interrupt Time Offset These bits determine the number of GCLK_WDT clocks in the offset from the start of the watchdog time-out period to when the Early Warning interrupt is generated. The Early Warning Offset is defined in Table 16-6. These bits are loaded from NVM User Row at startup. Refer to "NVM User Row Mapping" on page 25 for more details. Table 16-6. Early Warning Interrupt Time Offset EWOFFSET[3:0] Description 0x0 8 clock cycles 0x1 16 clock cycles 0x2 32 clock cycles 0x3 64 clock cycles 0x4 128 clock cycles 0x5 256 clock cycles 0x6 512 clock cycles 0x7 1024 clock cycles 0x8 2048 clock cycles 0x9 4096 clock cycles 0xA 8192 clock cycles 0xB 16384 clock cycles 0xC-0xF Reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 218 16.8.4 Interrupt Enable Clear This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Name: INTENCLR Offset: 0x4 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 EW Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:1 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 0 - EW: Early Warning Interrupt Enable 0: The Early Warning interrupt is disabled. 1: The Early Warning interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit disables the Early Warning interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 219 16.8.5 Interrupt Enable Set This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Name: INTENSET Offset: 0x5 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 EW Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:1 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 0 - EW: Early Warning Interrupt Enable 0: The Early Warning interrupt is disabled. 1: The Early Warning interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit enables the Early Warning interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 220 16.8.6 Interrupt Flag Status and Clear Name: INTFLAG Offset: 0x6 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 EW Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:1 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 0 - EW: Early Warning This flag is set when an Early Warning interrupt occurs, as defined by the EWOFFSET bit group in EWCTRL. Writing a zero to this bit has no effect. Writing a one to this bit clears the Early Warning interrupt flag. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 221 16.8.7 Status Name: STATUS Offset: 0x7 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 SYNCBUSY Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bit 7 - SYNCBUSY: Synchronization Busy This bit is cleared when the synchronization of registers between clock domains is complete. This bit is set when the synchronization of registers between clock domains is started. z Bits 6:0 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 222 16.8.8 Clear Name: CLEAR Offset: 0x8 Reset: 0x00 Property: Write-Protected, Write-Synchronized Bit 7 6 5 4 3 2 1 0 CLEAR[7:0] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 z Bits 7:0 - CLEAR[7:0]: Watchdog Clear Writing 0xA5 to this register will clear the Watchdog Timer and the watchdog time-out period is restarted. Writing any other value will issue an immediate system reset. Table 16-7. Watchdog Clear CLEAR[7:0] Name 0x0-0xA4 0xA5 0xA6-0xFF Description Reserved KEY Clear Key Reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 223 17. 17.1 RTC - Real-Time Counter Overview The Real-Time Counter (RTC) is a 32-bit counter with a 10-bit programmable prescaler that typically runs continuously to keep track of time. The RTC can wake up the device from sleep modes using the alarm/compare wake up, periodic wake up or overflow wake up mechanisms. The RTC is typically clocked by the 1.024kHz output from the 32.768kHz High-Accuracy Internal Crystal Oscillator(OSC32K) and this is the configuration optimized for the lowest power consumption. The faster 32.768kHz output can be selected if the RTC needs a resolution higher than 1ms. The RTC can also be clocked from other sources, selectable through the Generic Clock module (GCLK). The RTC can generate periodic peripheral events from outputs of the prescaler, as well as alarm/compare interrupts and peripheral events, which can trigger at any counter value. Additionally, the timer can trigger an overflow interrupt and peripheral event, and be reset on the occurrence of an alarm/compare match. This allows periodic interrupts and peripheral events at very long and accurate intervals. The 10-bit programmable prescaler can scale down the clock source, and so a wide range of resolutions and time-out periods can be configured. With a 32.768kHz clock source, the minimum counter tick interval is 30.5s, and time-out periods can range up to 36 hours. With the counter tick interval configured to 1s, the maximum time-out period is more than 136 years. 17.2 Features z 32-bit counter with 10-bit prescaler z Multiple clock sources z 32-bit or 16-bit Counter mode z One 32-bit or two 16-bit compare values z Clock/Calendar mode Time in seconds, minutes and hours (12/24) Date in day of month, month and year z Leap year correction z z z Digital prescaler correction/tuning for increased accuracy z Overflow, alarm/compare match and prescaler interrupts and events z 17.3 Optional clear on alarm/compare match Block Diagram Figure 17-1. RTC Block Diagram (Mode 0 -- 32-Bit Counter) 0 MATCHCLR GCLK_RTC 10-bit Prescaler CLK_RTC_CNT Overflow COUNT 32 = Periodic Events Compare n 32 COMPn Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 224 Figure 17-2. RTC Block Diagram (Mode 1 -- 16-Bit Counter) 0 GCLK_RTC 10-bit Prescaler CLK_RTC_CNT COUNT = 16 Overflow 16 Periodic Events PER = Compare n 16 COMPn Figure 17-3. RTC Block Diagram (Mode 2 -- Clock/Calendar) 0 MATCHCLR GCLK_RTC 10-bit Prescaler CLK_RTC_CNT 32 Y/M/D H:M:S 32 Y/M/D H:M:S = MASKn Periodic Events 17.4 Overflow CLOCK Alarm n ALARMn Signal Description Not applicable. 17.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 17.5.1 I/O Lines Not applicable. 17.5.2 Power Management The RTC can continue to operate in any sleep mode. The RTC interrupts can be used to wake up the device from sleep modes. The events can trigger other operations in the system without exiting sleep modes. Refer to "PM - Power Manager" on page 112 for details on the different sleep modes. The RTC will be reset only at power-on (POR) or by writing a one to the Software Reset bit in the Control register (CTRL.SWRST). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 225 17.5.3 Clocks The RTC bus clock (CLK_RTC_APB) can be enabled and disabled in the Power Manager, and the default state of CLK_RTC_APB can be found in the Peripheral Clock Masking section in the "PM - Power Manager" on page 112. A generic clock (GCLK_RTC) is required to clock the RTC. This clock must be configured and enabled in the Generic Clock Controller before using the RTC. Refer to "GCLK - Generic Clock Controller" on page 90 for details. This generic clock is asynchronous to the user interface clock (CLK_RTC_APB). Due to this asynchronicity, accessing certain registers will require synchronization between the clock domains. Refer to "Synchronization" on page 231 for further details. The RTC should never be used with the generic clock generator 0. 17.5.4 DMA Not applicable. 17.5.5 Interrupts The interrupt request line is connected to the Interrupt Controller. Using the RTC interrupts requires the Interrupt Controller to be configured first. Refer to "Nested Vector Interrupt Controller" on page 29 for details. 17.5.6 Events To use the RTC event functionality, the corresponding events need to be configured in the event system. Refer to "EVSYS - Event System" on page 400 for details. 17.5.7 Debug Operation When the CPU is halted in debug mode the RTC will halt normal operation. The RTC can be forced to continue operation during debugging. Refer to the Debug Control (DBGCTRL) register for details. 17.5.8 Register Access Protection All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the following registers: z Interrupt Flag Status and Clear register ( INTFLAG) z Read Request register (READREQ) z Status register (STATUS) z Debug register (DBGCTRL) Write-protection is denoted by the Write-Protection property in the register description. When the CPU is halted in debug mode, all write-protection is automatically disabled. Write-protection does not apply for accesses through an external debugger. Refer to "PAC - Peripheral Access Controller" on page 36 for details. 17.5.9 Analog Connections A 32.768kHz crystal can be connected to the XIN32 and XOUT32 pins, along with any required load capacitors. For details on recommended crystal characteristics and load capacitors, refer to "Electrical Characteristics" on page 1055 for details. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 226 17.6 Functional Description 17.6.1 Principle of Operation The RTC keeps track of time in the system and enables periodic events, as well as interrupts and events at a specified time. The RTC consists of a 10-bit prescaler that feeds a 32-bit counter. The actual format of the 32-bit counter depends on the RTC operating mode. 17.6.2 Basic Operation 17.6.2.1 Initialization The following bits are enable-protected, meaning that they can only be written when the RTC is disabled (CTRL.ENABLE is zero): z Operating Mode bits in the Control register (CTRL.MODE) z Prescaler bits in the Control register (CTRL.PRESCALER) z Clear on Match bit in the Control register (CTRL.MATCHCLR) z Clock Representation bit in the Control register (CTRL.CLKREP) The following register is enable-protected: z Event Control register (EVCTRL) Any writes to these bits or registers when the RTC is enabled or being enabled (CTRL.ENABLE is one) will be discarded. Writes to these bits or registers while the RTC is being disabled will be completed after the disabling is complete. Enable-protection is denoted by the Enable-Protection property in the register description. Before the RTC is enabled, it must be configured, as outlined by the following steps: z RTC operation mode must be selected by writing the Operating Mode bit group in the Control register (CTRL.MODE) z Clock representation must be selected by writing the Clock Representation bit in the Control register (CTRL.CLKREP) z Prescaler value must be selected by writing the Prescaler bit group in the Control register (CTRL.PRESCALER) The RTC prescaler divides down the source clock for the RTC counter. The frequency of the RTC clock (CLK_RTC_CNT) is given by the following formula: f GCLK_RTC f CLK_RTC_CNT = ---------------------------PRESCALER 2 The frequency of the generic clock, GCLK_RTC, is given by fGCLK_RTC, and fCLK_RTC_CNT is the frequency of the internal prescaled RTC clock, CLK_RTC_CNT. Note that in the Clock/Calendar mode, the prescaler must be configured to provide a 1Hz clock to the counter for correct operation. 17.6.2.2 Enabling, Disabling and Resetting The RTC is enabled by writing a one to the Enable bit in the Control register (CTRL.ENABLE). The RTC is disabled by writing a zero to CTRL.ENABLE. The RTC should be disabled before resetting it. The RTC is reset by writing a one to the Software Reset bit in the Control register (CTRL.SWRST). All registers in the RTC, except DBGCTRL, will be reset to their initial state, and the RTC will be disabled. Refer to the CTRL register for details. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 227 17.6.3 Operating Modes The RTC counter supports three RTC operating modes: 32-bit Counter, 16-bit Counter and Clock/Calendar. The operating mode is selected by writing to the Operating Mode bit group in the Control register (CTRL.MODE). 17.6.3.1 32-Bit Counter (Mode 0) When the RTC Operating Mode bits in the Control register (CTRL.MODE) are zero, the counter operates in 32-bit Counter mode. The block diagram of this mode is shown in Figure 17-1. When the RTC is enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. The counter will increment until it reaches the top value of 0xFFFFFFFF, and then wrap to 0x00000000. This sets the Overflow interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.OVF). The RTC counter value can be read from or written to the Counter Value register (COUNT) in 32-bit format. The counter value is continuously compared with the 32-bit Compare register (COMP0). When a compare match occurs, the Compare 0interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMP0) is set on the next 0-to-1 transition of CLK_RTC_CNT. If the Clear on Match bit in the Control register (CTRL.MATCHCLR) is one, the counter is cleared on the next counter cycle when a compare match with COMP0 occurs. This allows the RTC to generate periodic interrupts or events with longer periods than are possible with the prescaler events. Note that when CTRL.MATCHCLR is one, INTFLAG.CMP0 and INTFLAG.OVF will both be set simultaneously on a compare match with COMP0. 17.6.3.2 16-Bit Counter (Mode 1) When CTRL.MODE is one, the counter operates in 16-bit Counter mode as shown in Figure 17-2. When the RTC is enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. In 16-bit Counter mode, the 16-bit Period register (PER) holds the maximum value of the counter. The counter will increment until it reaches the PER value, and then wrap to 0x0000. This sets the Overflow interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.OVF). The RTC counter value can be read from or written to the Counter Value register (COUNT) in 16-bit format. The counter value is continuously compared with the 16-bit Compare registers (COMPn, n=0-1). When a compare match occurs, the Compare n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn, n=0-1) is set on the next 0-to-1 transition of CLK_RTC_CNT. 17.6.3.3 Clock/Calendar (Mode 2) When CTRL.MODE is two, the counter operates in Clock/Calendar mode, as shown in Figure 17-3. When the RTC is enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. The selected clock source and RTC prescaler must be configured to provide a 1Hz clock to the counter for correct operation in this mode. The time and date can be read from or written to the Clock Value register (CLOCK) in a 32-bit time/date format. Time is represented as: z Seconds z Minutes z Hours Hours can be represented in either 12- or 24-hour format, selected by the Clock Representation bit in the Control register (CTRL.CLKREP). This bit can be changed only while the RTC is disabled. Date is represented as: z Day as the numeric day of the month (starting at 1) z Month as the numeric month of the year (1 = January, 2 = February, etc.) z Year as a value counting the offset from a reference value that must be defined in software The date is automatically adjusted for leap years, assuming every year divisible by 4 is a leap year. Therefore, the reference value must be a leap year, e.g. 2000. The RTC will increment until it reaches the top value of 23:59:59 December 31st of year 63, and then wrap to 00:00:00 January 1st of year 0. This will set the Overflow interrupt flag in the Interrupt Flag Status and Clear registers (INTFLAG.OVF). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 228 The clock value is continuously compared with the 32-bit Alarm register (ALARM0). When an alarm match occurs, the Alarm 0 Interrupt flag in the Interrupt Flag Status and Clear registers (INTFLAG.ALARMn0) is set on the next 0-to-1 transition of CLK_RTC_CNT. A valid alarm match depends on the setting of the Alarm Mask Selection bits in the Alarm 0 Mask register (MASK0.SEL). These bits determine which time/date fields of the clock and alarm values are valid for comparison and which are ignored. If the Clear on Match bit in the Control register (CTRL.MATCHCLR) is one, the counter is cleared on the next counter cycle when an alarm match with ALARM0 occurs. This allows the RTC to generate periodic interrupts or events with longer periods than are possible with the prescaler events (see "Periodic Events" on page 229). Note that when CTRL.MATCHCLR is one, INTFLAG.ALARM0 and INTFLAG.OVF will both be set simultaneously on an alarm match with ALARM0. 17.6.4 Additional Features 17.6.4.1 Periodic Events The RTC prescaler can generate events at periodic intervals, allowing flexible system tick creation. Any of the upper eight bits of the prescaler (bits 2 to 9) can be the source of an event. When one of the Periodic Event Output bits in the Event Control register (EVCTRL.PEREOn) is one, an event is generated on the 0-to1 transition of the related bit in the prescaler, resulting in a periodic event frequency of: f PERIODIC = f GCLK _ RTC 2 n +3 fGCLK_RTC is the frequency of the internal prescaler clock, GCLK_RTC, and n is the position of the EVCTRL.PEREOn bit. For example, PEREO will generate an event every 8 GCLK_RTC cycles, PEREO1 every 16 cycles, etc. This is shown in Figure 17-4. Periodic events are independent of the prescaler setting used by the RTC counter, except if CTRL.PRESCALER is zero. Then, no periodic events will be generated. Figure 17-4. Example Periodic Events GCLK_RTC PEREO0 PEREO1 PEREO2 PEREO3 PEREO4 17.6.4.2 Frequency Correction The RTC Frequency Correction module employs periodic counter corrections to compensate for a too-slow or too-fast oscillator. Frequency correction requires that CTRL.PRESCALER is greater than 1. The digital correction circuit adds or subtracts cycles from the RTC prescaler to adjust the frequency in approximately 1PPM steps. Digital correction is achieved by adding or skipping a single count in the prescaler once every 1024 GCLK_RTC cycles. The Value bit group in the Frequency Correction register (FREQCORR.VALUE) determines the number of times the adjustment is applied over 976 of these periods. The resulting correction is as follows: 6 FREQCORR.VALUE Correction in PPM = ----------------------------------------------------- 10 PPM 1024 976 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 229 This results in a resolution of 1.0006PPM. The Sign bit in the Frequency Correction register (FREQCORR.SIGN) determines the direction of the correction. A positive value will speed up the frequency, and a negative value will slow down the frequency. Digital correction also affects the generation of the periodic events from the prescaler. When the correction is applied at the end of the correction cycle period, the interval between the previous periodic event and the next occurrence may also be shortened or lengthened depending on the correction value. 17.6.5 DMA Operation Not applicable. 17.6.6 Interrupts The RTC has the following interrupt sources: z Overflow (INTFLAG.OVF): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. z Compare n (INTFLAG.CMPn): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. z Alarm n (INTFLAG.ALARMn): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. z Synchronization Ready (INTFLAG.SYNCRDY): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the RTC is reset. See INTFLAG for details on how to clear interrupt flags. The RTC has one common interrupt request line for all the interrupt sources. The user must read INTFLAG to determine which interrupt condition is present. Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to "Nested Vector Interrupt Controller" on page 29 for details. 17.6.7 Events The RTC can generate the following output events, which are generated in the same way as the corresponding interrupts: z Overflow (OVF) z Period n (PERn) z Compare n (CMPn) z Alarm n (ALARMn) Output events must be enabled to be generated. Writing a one to an Event Output bit in the Event Control register (EVCTRL.xxEO) enables the corresponding output event. Writing a zero to this bit disables the corresponding output event. Refer to "EVSYS - Event System" on page 400 for details. 17.6.8 Sleep Mode Operation The RTC will continue to operate in any sleep mode where the source clock is active. The RTC interrupts can be used to wake up the device from a sleep mode, or the RTC events can trigger other operations in the system without exiting the sleep mode. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 230 An interrupt request will be generated after the wake-up if the Interrupt Controller is configured accordingly. Otherwise the CPU will wake up directly, without triggering an interrupt. In this case, the CPU will continue executing from the instruction following the entry into sleep. The periodic events can also wake up the CPU through the interrupt function of the Event System. In this case, the event must be enabled and connected to an event channel with its interrupt enabled. See "EVSYS - Event System" on page 400 for more information. 17.6.9 Synchronization Due to the asynchronicity between CLK_RTC_APB and GCLK_RTC some registers must be synchronized when accessed. A register can require: z Synchronization when written z Synchronization when read z Synchronization when written and read z No synchronization When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. The Synchronization Ready interrupt can be used to signal when synchronization is complete. This can be accessed via the Synchronization Ready Interrupt Flag in the Interrupt Flag Status and Clear register (INTFLAG.SYNCRDY). If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is stalled. The following bits need synchronization when written: z Software Reset bit in the Control register (CTRL.SWRST) z Enable bit in the Control register (CTRL.ENABLE) The following registers need synchronization when written: z The Counter Value register (COUNT) z The Clock Value register (CLOCK) z The Counter Period register (PER) z The Compare n Value registers (COMPn) z The Alarm n Value registers (ALARMn) z The Frequency Correction register (FREQCORR) z The Alarm n Mask register (MASKn) Write-synchronization is denoted by the Write-Synchronization property in the register description. The following registers need synchronization when read: z The Counter Value register (COUNT) z The Clock Value register (CLOCK) Read-synchronization is denoted by the Read-Synchronization property in the register description. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 231 17.7 Register Summary The register mapping depends on the Operating Mode bits in the Control register (CTRL.MODE). The register summary is presented for each of the three modes. Table 17-1. MODE0 - Mode Register Summary Offset 0x00 0x01 0x02 0x03 0x04 0x05 Name CTRL READREQ EVCTRL Bit Pos. 7:0 MATCHCLR MODE[1:0] ENABLE SWRST PRESCALER[3:0] 15:8 ADDR[5:0] 7:0 15:8 RREQ RCONT PEREO6 7:0 PEREO7 15:8 OVFEO PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 CMPEO0 0x06 INTENCLR 7:0 OVF SYNCRDY CMP0 0x07 INTENSET 7:0 OVF SYNCRDY CMP0 0x08 INTFLAG 7:0 OVF SYNCRDY CMP0 0x09 Reserved 0x0A STATUS 7:0 SYNCBUSY 0x0B DBGCTRL 7:0 0x0C FREQCORR 7:0 0x0D ... 0x0F Reserved DBGRUN SIGN VALUE[6:0] 0x10 7:0 COUNT[7:0] 0x11 15:8 COUNT[15:8] 23:16 COUNT[23:16] 31:24 COUNT[31:24] 7:0 COMP[7:0] 0x12 COUNT 0x13 0x14 ... 0x17 Reserved 0x18 0x19 0x1A COMP0 0x1B 15:8 COMP[15:8] 23:16 COMP[23:16] 31:24 COMP[31:24] Table 17-2. MODE1 - Mode Register Summary Offset 0x00 0x01 0x02 0x03 0x04 0x05 Name CTRL READREQ EVCTRL Bit Pos. 7:0 MODE[1:0] ENABLE SWRST PRESCALER[3:0] 15:8 ADDR[5:0] 7:0 15:8 RREQ RCONT PEREO6 7:0 PEREO7 15:8 OVFEO PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 CMPEO1 CMPEO0 0x06 INTENCLR 7:0 OVF SYNCRDY CMP1 CMP0 0x07 INTENSET 7:0 OVF SYNCRDY CMP1 CMP0 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 232 Offset Name Bit Pos. 0x08 INTFLAG 7:0 OVF SYNCBUSY 0x09 Reserved 0x0A STATUS 7:0 0x0B DBGCTRL 7:0 0x0C FREQCORR 7:0 0x0D ... 0x0F Reserved 0x10 0x11 COUNT 0x12 Reserved 0x13 Reserved 0x14 0x15 PER 0x16 Reserved 0x17 Reserved 0x18 0x19 0x1A 0x1B COMP0 COMP1 SYNCRDY CMP1 CMP0 DBGRUN SIGN VALUE[6:0] 7:0 COUNT[7:0] 15:8 COUNT[15:8] 7:0 PER[7:0] 15:8 PER[15:8] 7:0 COMP[7:0] 15:8 COMP[15:8] 7:0 COMP[7:0] 15:8 COMP[15:8] Table 17-3. MODE2 - Mode Register Summary Offset 0x00 0x01 0x02 0x03 0x04 0x05 Name CTRL READREQ EVCTRL Bit Pos. 7:0 MATCHCLR CLKREP MODE[1:0] ENABLE SWRST PRESCALER[3:0] 15:8 ADDR[5:0] 7:0 15:8 RREQ RCONT 7:0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 15:8 OVFEO 0x06 INTENCLR 7:0 OVF SYNCRDY ALARM0 0x07 INTENSET 7:0 OVF SYNCRDY ALARM0 0x08 INTFLAG 7:0 OVF SYNCRDY ALARM0 0x09 Reserved 0x0A STATUS 7:0 SYNCBUSY 0x0B DBGCTRL 7:0 0x0C FREQCORR 7:0 0x0D ... 0x0F Reserved 0x10 0x11 0x12 0x13 7:0 CLOCK ALARMEO0 DBGRUN SIGN MINUTE[1:0] 15:8 23:16 31:24 VALUE[6:0] SECOND[5:0] HOUR[3:0] MINUTE[5:2] MONTH[1:0] DAY[4:0] YEAR[5:0] HOUR[4] MONTH[3:2] Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 233 Offset Name 0x14 ... 0x17 Reserved 0x18 0x19 0x1A 7:0 ALARM0 0x1B 0x1C Bit Pos. 15:8 23:16 31:24 MASK MINUTE[1:0] 7:0 SECOND[5:0] HOUR[3:0] MINUTE[5:2] MONTH[1:0] DAY[4:0] YEAR[5:0] HOUR[4] MONTH[3:2] SEL[2:0] Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 234 17.8 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protected property in each individual register description. Please refer to "Register Access Protection" on page 226 for details. Some registers require synchronization when read and/or written. Synchronization is denoted by the Write-Synchronized or the Read-Synchronized property in each individual register description. Please refer to "Synchronization" on page 231 for details. Some registers are enable-protected, meaning they can only be written when the RTC is disabled. Enable-protection is denoted by the Enable-Protected property in each individual register description. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 235 17.8.1 Control - MODE0 Name: CTRL Offset: 0x00 Reset: 0x0000 Property: Enable-Protected, Write-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 PRESCALER[3:0] Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ENABLE SWRST MATCHCLR Access Reset MODE[1:0] R/W R R R R/W R/W R/W W 0 0 0 0 0 0 0 0 z Bits 15:12 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 11:8 - PRESCALER[3:0]: Prescaler These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock (CLK_RTC_CNT). These bits are not synchronized. Table 17-4. Prescaler PRESCALER[3:0] Name 0x0 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x2 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x3 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x4 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x5 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x6 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x7 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x8 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x9 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xA DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xB-0xF Description Reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 236 z Bit 7 - MATCHCLR: Clear on Match This bit is valid only in Mode 0 and Mode 2. 0: The counter is not cleared on a Compare/Alarm 0 match. 1: The counter is cleared on a Compare/Alarm 0 match. This bit is not synchronized. z Bits 6:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 3:2 - MODE[1:0]: Operating Mode These bits define the operating mode of the RTC. These bits are not synchronized. Table 17-5. Operating Mode MODE[1:0] Name 0x0 COUNT32 Mode 0: 32-bit Counter 0x1 COUNT16 Mode 1: 16-bit Counter 0x2 CLOCK Mode 2: Clock/Calendar 0x3 z Description Reserved Bit 1 - ENABLE: Enable 0: The peripheral is disabled or being disabled. 1: The peripheral is enabled or being enabled. Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete. This bit is not enable-protected. z Bit 0 - SWRST: Software Reset 0: There is no reset operation ongoing. 1: The reset operation is ongoing. Writing a zero to this bit has no effect. Writing a one to this bit resets all registers in the RTC, except DBGCTRL, to their initial state, and the RTC will be disabled. Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete. CTRL.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete. This bit is not enable-protected. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 237 17.8.2 Control - MODE1 Name: CTRL Offset: 0x00 Reset: 0x0000 Property: Enable-Protected, Write-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 PRESCALER[3:0] Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ENABLE SWRST MODE[1:0] Access R R R R R/W R/W R/W W Reset 0 0 0 0 0 0 0 0 z Bits 15:12 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 11:8 - PRESCALER[3:0]: Prescaler These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock (CLK_RTC_CNT). These bits are not synchronized. Table 17-6. Prescaler PRESCALER[3:0] Name 0x0 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x2 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x3 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x4 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x5 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x6 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x7 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x8 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x9 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xA DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xB-0xF Description Reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 238 z Bits 7:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 3:2 - MODE[1:0]: Operating Mode These bits define the operating mode of the RTC. These bits are not synchronized. Table 17-7. Operating Mode MODE[1:0] Name 0x0 COUNT32 Mode 0: 32-bit Counter 0x1 COUNT16 Mode 1: 16-bit Counter 0x2 CLOCK Mode 2: Clock/Calendar 0x3 z Description Reserved Bit 1 - ENABLE: Enable 0: The peripheral is disabled or being disabled. 1: The peripheral is enabled or being enabled. Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete. This bit is not enable-protected. z Bit 0 - SWRST: Software Reset 0: There is no reset operation ongoing. 1: The reset operation is ongoing. Writing a zero to this bit has no effect. Writing a one to this bit resets all registers in the RTC, except DBGCTRL, to their initial state, and the RTC will be disabled. Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete. CTRL.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete. This bit is not enable-protected. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 239 17.8.3 Control - MODE2 Name: CTRL Offset: 0x00 Reset: 0x0000 Property: Enable-Protected, Write-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 PRESCALER[3:0] Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MATCHCLR CLKREP ENABLE SWRST R/W R/W R R R/W R/W R/W W 0 0 0 0 0 0 0 0 Access Reset MODE[1:0] z Bits 15:12 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 11:8 - PRESCALER[3:0]: Prescaler These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock (CLK_RTC_CNT). These bits are not synchronized. Table 17-8. Prescaler PRESCALER[3:0] Name 0x0 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x2 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x3 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x4 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x5 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x6 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x7 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x8 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x9 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xA DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xB-0xF Description Reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 240 z Bit 7 - MATCHCLR: Clear on Match This bit is valid only in Mode 0 and Mode 2. This bit can be written only when the peripheral is disabled. 0: The counter is not cleared on a Compare/Alarm 0 match. 1: The counter is cleared on a Compare/Alarm 0 match. This bit is not synchronized. z Bit 6 - CLKREP: Clock Representation This bit is valid only in Mode 2 and determines how the hours are represented in the Clock Value (CLOCK) register. This bit can be written only when the peripheral is disabled. 0: 24 Hour 1: 12 Hour (AM/PM) This bit is not synchronized. z Bits 5:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 3:2 - MODE[1:0]: Operating Mode These bits define the operating mode of the RTC. These bits are not synchronized. Table 17-9. Operating Mode MODE[1:0] Name 0x0 COUNT32 Mode 0: 32-bit Counter 0x1 COUNT16 Mode 1: 16-bit Counter 0x2 CLOCK Mode 2: Clock/Calendar 0x3 z Description Reserved Bit 1 - ENABLE: Enable 0: The peripheral is disabled or being disabled. 1: The peripheral is enabled or being enabled. Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete. This bit is not enable-protected. z Bit 0 - SWRST: Software Reset 0: There is no reset operation ongoing. 1: The reset operation is ongoing. Writing a zero to this bit has no effect. Writing a one to this bit resets all registers in the RTC, except DBGCTRL, to their initial state, and the RTC will be disabled. Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete. CTRL.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete. This bit is not enable-protected. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 241 17.8.4 Read Request Name: READREQ Offset: 0x02 Reset: 0x0010 Property: - Bit 15 14 13 12 11 10 9 8 RREQ RCONT Access W R/W R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADDR[5:0] Access R R R R R R R R Reset 0 0 0 1 0 0 0 0 z Bit 15 - RREQ: Read Request Writing a zero to this bit has no effect. Writing a one to this bit requests synchronization of the register pointed to by the Address bit group (READREQ.ADDR) and sets the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY). z Bit 14 - RCONT: Read Continuously Writing a zero to this bit disables continuous synchronization. Writing a one to this bit enables continuous synchronization of the register pointed to by READREQ.ADDR. The register value will be synchronized automatically every time the register is updated. READREQ.RCONT prevents READREQ.RREQ from clearing automatically. This bit is cleared when the register pointed to by READREQ.ADDR is written. z Bits 13:6 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 5:0 - ADDR[5:0]: Address These bits select the offset of the register that needs read synchronization. In the RTC only COUNT and CLOCK, which share the same address, are available for read synchronization. Therefore, ADDR is a read-only constant of 0x10. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 242 17.8.5 Event Control - MODE0 Name: EVCTRL Offset: 0x04 Reset: 0x0000 Property: Enable-Protected, Write-Protected Bit 15 14 13 12 11 10 9 OVFEO Access 8 CMPEO0 R/W R R R R R R R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Access Reset z Bit 15 - OVFEO: Overflow Event Output Enable 0: Overflow event is disabled and will not be generated. 1: Overflow event is enabled and will be generated for every overflow. z Bits 14:9 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 8 - CMPEO: Compare 0 Event Output Enable 0: Compare 0 event is disabled and will not be generated. 1: Compare 0 event is enabled and will be generated for every compare match. z Bits 7:0 - PEREOx [x=7..0]: Periodic Interval x Event Output Enable 0: Periodic Interval x event is disabled and will not be generated. 1: Periodic Interval x event is enabled and will be generated. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 243 17.8.6 Event Control - MODE1 Name: EVCTRL Offset: 0x04 Reset: 0x0000 Property: Enable-Protected, Write-Protected Bit 15 14 13 12 11 10 OVFEO Access 9 8 CMPEO1 CMPEO0 R/W R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Access Reset z Bit 15 - OVFEO: Overflow Event Output Enable 0: Overflow event is disabled and will not be generated. 1: Overflow event is enabled and will be generated for every overflow. z Bits 14:10 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 9:8 - CMPEOx [x=1..0]: Compare x Event Output Enable 0: Compare x event is disabled and will not be generated. 1: Compare x event is enabled and will be generated for every compare match. z Bits 7:0 - PEREOx [x=7..0]: Periodic Interval x Event Output Enable 0: Periodic Interval x event is disabled and will not be generated. 1: Periodic Interval x event is enabled and will be generated. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 244 17.8.7 Event Control - MODE2 Name: EVCTRL Offset: 0x04 Reset: 0x0000 Property: Enable-Protected, Write-Protected Bit 15 14 13 12 11 10 9 OVFEO Access 8 ALARMEO0 R/W R R R R R R R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Access Reset z Bit 15 - OVFEO: Overflow Event Output Enable 0: Overflow event is disabled and will not be generated. 1: Overflow event is enabled and will be generated for every overflow. z Bits 14:9 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 8 - ALARMEO: Alarm 0 Event Output Enable 0: Alarm 0 event is disabled and will not be generated. 1: Alarm 0 event is enabled and will be generated for every alarm. z Bits 7:0 - PEREOx [x=7..0]: Periodic Interval x Event Output Enable 0: Periodic Interval x event is disabled and will not be generated. 1: Periodic Interval x event is enabled and will be generated. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 245 17.8.8 Interrupt Enable Clear - MODE0 This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Name: INTENCLR Offset: 0x06 Reset: 0x00 Property: Write-Protected Bit Access Reset z 7 6 5 4 3 2 1 0 OVF SYNCRDY R/W R/W R R R R R R/W 0 0 0 0 0 0 0 0 CMP0 Bit 7 - OVF: Overflow Interrupt Enable 0: The Overflow interrupt is disabled. 1: The Overflow interrupt is enabled, and an interrupt request will be generated when the Overflow interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Overflow Interrupt Enable bit and disable the corresponding interrupt. z Bit 6 - SYNCRDY: Synchronization Ready Interrupt Enable 0: The Synchronization Ready interrupt is disabled. 1: The Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the Synchronization Ready interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Synchronization Ready Interrupt Enable bit and disable the corresponding interrupt. z Bits 5:1 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 0 - CMP: Compare 0 Interrupt Enable 0: The Compare 0 interrupt is disabled. 1: The Compare 0 interrupt is enabled, and an interrupt request will be generated when the Compare x interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Compare 0 Interrupt Enable bit and disable the corresponding interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 246 17.8.9 Interrupt Enable Clear - MODE1 Name: INTENCLR Offset: 0x06 Reset: 0x00 Property: Write-Protected Bit Access Reset z 7 6 5 4 3 OVF SYNCRDY R/W R/W R R R 0 0 0 0 0 2 1 0 CMP1 CMP0 R R/W R/W 0 0 0 Bit 7 - OVF: Overflow Interrupt Enable 0: The Overflow interrupt is disabled. 1: The Overflow interrupt is enabled, and an interrupt request will be generated when the Overflow interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Overflow Interrupt Enable bit and disable the corresponding interrupt. z Bit 6 - SYNCRDY: Synchronization Ready Interrupt Enable 0: The Synchronization Ready interrupt is disabled. 1: The Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the Synchronization Ready interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Synchronization Ready Interrupt Enable bit and disable the corresponding interrupt. z Bits 5:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 1:0 - CMPx [x=1..0]: Compare x Interrupt Enable 0: The Compare x interrupt is disabled. 1: The Compare x interrupt is enabled, and an interrupt request will be generated when the Compare x interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Compare x Interrupt Enable bit and disable the corresponding interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 247 17.8.10 Interrupt Enable Clear - MODE2 Name: INTENCLR Offset: 0x06 Reset: 0x00 Property: Write-Protected Bit Access Reset z 7 6 5 4 3 2 1 0 OVF SYNCRDY R/W R/W R R R R R R/W 0 0 0 0 0 0 0 0 ALARM0 Bit 7 - OVF: Overflow Interrupt Enable 0: The Overflow interrupt is disabled. 1: The Overflow interrupt is enabled, and an interrupt request will be generated when the Overflow interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Overflow Interrupt Enable bit and disable the corresponding interrupt. z Bit 6 - SYNCRDY: Synchronization Ready Interrupt Enable 0: The synchronization ready interrupt is disabled. 1: The synchronization ready interrupt is enabled, and an interrupt request will be generated when the Synchronization Ready interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Synchronization Ready Interrupt Enable bit and disable the corresponding interrupt. z Bits 5:1 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 0 - ALARM: Alarm 0 Interrupt Enable 0: The Alarm 0 interrupt is disabled. 1: The Alarm 0 interrupt is enabled, and an interrupt request will be generated when the Alarm 0 interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit disables the Alarm 0 interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 248 17.8.11 Interrupt Enable Set - MODE0 This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Name: INTENSET Offset: 0x07 Reset: 0x00 Property: Write-Protected Bit Access Reset z 7 6 5 4 3 2 1 0 OVF SYNCRDY R/W R/W R R R R R R/W 0 0 0 0 0 0 0 0 CMP0 Bit 7 - OVF: Overflow Interrupt Enable 0: The overflow interrupt is disabled. 1: The overflow interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Overflow Interrupt Enable bit and enable the Overflow interrupt. z Bit 6 - SYNCRDY: Synchronization Ready Interrupt Enable 0: The synchronization ready interrupt is disabled. 1: The synchronization ready interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Synchronization Ready Interrupt Enable bit and enable the Synchronization Ready interrupt. z Bits 5:1 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 0 - CMP: Compare 0 Interrupt Enable 0: The compare 0 interrupt is disabled. 1: The compare 0 interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Compare 0 Interrupt Enable bit and enable the Compare 0 interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 249 17.8.12 Interrupt Enable Set - MODE1 Name: INTENSET Offset: 0x07 Reset: 0x00 Property: Write-Protected Bit Access Reset z 7 6 5 4 3 OVF SYNCRDY R/W R/W R R R 0 0 0 0 0 2 1 0 CMP1 CMP0 R R/W R/W 0 0 0 Bit 7 - OVF: Overflow Interrupt Enable 0: The overflow interrupt is disabled. 1: The overflow interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Overflow interrupt bit and enable the Overflow interrupt. z Bit 6 - SYNCRDY: Synchronization Ready Interrupt Enable 0: The synchronization ready interrupt is disabled. 1: The synchronization ready interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Synchronization Ready Interrupt Enable bit and enable the Synchronization Ready interrupt. z Bits 5:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 1:0 - CMPx [x=1..0]: Compare x Interrupt Enable 0: The compare x interrupt is disabled. 1: The compare x interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Compare x Interrupt Enable bit and enable the Compare x interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 250 17.8.13 Interrupt Enable Set - MODE2 Name: INTENSET Offset: 0x07 Reset: 0x00 Property: Write-Protected Bit Access Reset z 7 6 5 4 3 2 1 0 OVF SYNCRDY R/W R/W R R R R R R/W 0 0 0 0 0 0 0 0 ALARM0 Bit 7 - OVF: Overflow Interrupt Enable 0: The overflow interrupt is disabled. 1: The overflow interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Overflow Interrupt Enable bit and enable the Overflow interrupt. z Bit 6 - SYNCRDY: Synchronization Ready Interrupt Enable 0: The synchronization ready interrupt is disabled. 1: The synchronization ready interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Synchronization Ready Interrupt bit and enable the Synchronization Ready interrupt. z Bits 5:1 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 0 - ALARM: Alarm 0 Interrupt Enable 0: The alarm 0 interrupt is disabled. 1: The alarm 0 interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Alarm 0 Interrupt Enable bit and enable the Alarm 0 interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 251 17.8.14 Interrupt Flag Status and Clear - MODE0 Name: INTFLAG Offset: 0x08 Reset: 0x00 Property: - Bit Access Reset z 7 6 5 4 3 2 1 0 OVF SYNCRDY R/W R/W R R R R R R/W 0 0 0 0 0 0 0 0 CMP0 Bit 7 - OVF: Overflow This flag is cleared by writing a one to the flag. This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be generated if INTENCLR/SET.OVF is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Overflow interrupt flag. z Bit 6 - SYNCRDY: Synchronization Ready This flag is cleared by writing a one to the flag. This flag is set on a 1-to-0 transition of the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY), except when caused by enable or software reset, and an interrupt request will be generated if INTENCLR/SET.SYNCRDY is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Synchronization Ready interrupt flag. z Bits 5:1 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 0 - CMP: Compare 0 This flag is cleared by writing a one to the flag. This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition, and an interrupt request will be generated if INTENCLR/SET.CMP0 is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Compare 0 interrupt flag. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 252 17.8.15 Interrupt Flag Status and Clear - MODE1 Name: INTFLAG Offset: 0x08 Reset: 0x00 Property: - Bit Access Reset z 7 6 5 4 3 OVF SYNCRDY R/W R/W R R R 0 0 0 0 0 2 1 0 CMP1 CMP0 R R/W R/W 0 0 0 Bit 7 - OVF: Overflow This flag is cleared by writing a one to the flag. This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be generated if INTENCLR/SET.OVF is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Overflow interrupt flag. z Bit 6 - SYNCRDY: Synchronization Ready This flag is cleared by writing a one to the flag. This flag is set on a 1-to-0 transition of the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY), except when caused by enable or software reset, and an interrupt request will be generated if INTENCLR/SET.SYNCRDY is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Synchronization Ready interrupt flag. z Bits 5:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 1:0 - CMPx [x=1..0]: Compare x This flag is cleared by writing a one to the flag. This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition and an interrupt request will be generated if INTENCLR/SET.CMPx is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Compare x interrupt flag. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 253 17.8.16 Interrupt Flag Status and Clear - MODE2 Name: INTFLAG Offset: 0x08 Reset: 0x00 Property: - Bit Access Reset z 7 6 5 4 3 2 1 0 OVF SYNCRDY R/W R/W R R R R R R/W 0 0 0 0 0 0 0 0 ALARM0 Bit 7 - OVF: Overflow This flag is cleared by writing a one to the flag. This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be generated if INTENCLR/SET.OVF is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Overflow interrupt flag. z Bit 6 - SYNCRDY: Synchronization Ready This flag is cleared by writing a one to the flag. This flag is set on a 1-to-0 transition of the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY), except when caused by enable or software reset, and an interrupt request will be generated if INTENCLR/SET.SYNCRDY is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Synchronization Ready interrupt flag. z Bits 5:1 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 0 - ALARM: Alarm 0 This flag is cleared by writing a one to the flag. This flag is set on the next CLK_RTC_CNT cycle after a match with ALARM0 condition occurs, and an interrupt request will be generated if INTENCLR/SET.ALARM0 is also one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Alarm 0 interrupt flag. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 254 17.8.17 Status Name: STATUS Offset: 0x0A Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 SYNCBUSY Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bit 7 - SYNCBUSY: Synchronization Busy This bit is cleared when the synchronization of registers between the clock domains is complete. This bit is set when the synchronization of registers between clock domains is started. z Bits 6:0 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 255 17.8.18 Debug Control Name: DBGCTRL Offset: 0x0B Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 DBGRUN Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:1 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 0 - DBGRUN: Run During Debug This bit is not reset by a software reset. Writing a zero to this bit causes the RTC to halt during debug mode. Writing a one to this bit allows the RTC to continue normal operation during debug mode. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 256 17.8.19 Frequency Correction Name: FREQCORR Offset: 0x0C Reset: 0x00 Property: Write-Protected, Write-Synchronized Bit 7 6 5 4 SIGN Access Reset z 3 2 1 0 VALUE[6:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 - SIGN: Correction Sign 0: The correction value is positive, i.e., frequency will be increased. 1: The correction value is negative, i.e., frequency will be decreased. z Bits 6:0 - VALUE[6:0]: Correction Value These bits define the amount of correction applied to the RTC prescaler. 0: Correction is disabled and the RTC frequency is unchanged. 1-127: The RTC frequency is adjusted according to the value. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 257 17.8.20 Counter Value - MODE0 Name: COUNT Offset: 0x10 Reset: 0x00000000 Property: Read-Synchronized, Write-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 COUNT[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 COUNT[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 COUNT[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COUNT[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 31:0 - COUNT[31:0]: Counter Value These bits define the value of the 32-bit RTC counter. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 258 17.8.21 Counter Value - MODE1 Name: COUNT Offset: 0x10 Reset: 0x0000 Property: Read-Synchronized, Write-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 COUNT[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COUNT[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 15:0 - COUNT[15:0]: Counter Value These bits define the value of the 16-bit RTC counter. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 259 17.8.22 Clock Value - MODE2 Name: CLOCK Offset: 0x10 Reset: 0x00000000 Property: Read-Synchronized, Write-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 YEAR[5:0] Access 24 MONTH[3:2] R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 MONTH[1:0] Access DAY[4:0] HOUR[4] R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 HOUR[3:0] Access MINUTE[5:2] R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MINUTE[1:0] Access Reset z SECOND[5:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 31:26 - YEAR[5:0]: Year The year offset with respect to the reference year (defined in software). The year is considered a leap year if YEAR[1:0] is zero. z Bits 25:22 - MONTH[3:0]: Month 1 - January 2 - February ... 12 - December z Bits 21:17 - DAY[4:0]: Day Day starts at 1 and ends at 28, 29, 30 or 31, depending on the month and year. z Bits 16:12 - HOUR[4:0]: Hour When CTRL.CLKREP is zero, the Hour bit group is in 24-hour format, with values 0-23. When CTRL.CLKREP is one, HOUR[3:0] has values 1-12 and HOUR[4] represents AM (0) or PM (1). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 260 Table 17-10. Hour HOUR[4:0] CLOCK.HOUR[4] 0 CLOCK.HOUR[3:0] 0x00 - 0x17 Hour (0 - 23) 0x18 - 0x1F Reserved 0x0 0 1 1 z Bits 11:6 - MINUTE[5:0]: Minute 0 - 59. z Bits 5:0 - SECOND[5:0]: Second 0- 59. Description Reserved 0x1 - 0xC AM Hour (1 - 12) 0xD - 0xF Reserved 0x0 Reserved 0x1 - 0xC PM Hour (1 - 12) 0xF - 0xF Reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 261 17.8.23 Counter Period - MODE1 Name: PER Offset: 0x14 Reset: 0x0000 Property: Write-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 PER[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PER[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 15:0 - PER[15:0]: Counter Period These bits define the value of the 16-bit RTC period. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 262 17.8.24 Compare n Value - MODE0 Name: COMP Offset: 0x18 Reset: 0x00000000 Property: Write-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 COMP[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 COMP[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 COMP[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COMP[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 31:0 - COMP[31:0]: Compare Value The 32-bit value of COMPn is continuously compared with the 32-bit COUNT value. When a match occurs, the Compare n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn) is set on the next counter cycle, and the counter value is cleared if CTRL.MATCHCLR is one. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 263 17.8.25 Compare n Value - MODE1 Name: COMPn Offset: 0x18+n*0x2 [n=0..1] Reset: 0x0000 Property: Write-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 COMP[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COMP[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 15:0 - COMP[15:0]: Compare Value The 16-bit value of COMPn is continuously compared with the 16-bit COUNT value. When a match occurs, the Compare n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn) is set on the next counter cycle. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 264 17.8.26 Alarm 0 Value - MODE2 Name: ALARM0 Offset: 0x18 Reset: 0x00000000 Property: Write-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 YEAR[5:0] Access 24 MONTH[3:2] R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 MONTH[1:0] Access DAY[4:0] HOUR[4] R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 HOUR[3:0] Access MINUTE[5:2] R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MINUTE[1:0] Access Reset SECOND[5:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 The 32-bit value of ALARM0 is continuously compared with the 32-bit CLOCK value, based on the masking set by MASKn.SEL. When a match occurs, the Alarm 0 interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.ALARMn) is set on the next counter cycle, and the counter is cleared if CTRL.MATCHCLR is one. z Bits 31:26 - YEAR[5:0]: Year The alarm year. Years are only matched if MASKn.SEL is 6. z Bits 25:22 - MONTH[3:0]: Month The alarm month. Months are matched only if MASKn.SEL is greater than 4. z Bits 21:17 - DAY[4:0]: Day The alarm day. Days are matched only if MASKn.SEL is greater than 3. z Bits 16:12 - HOUR[4:0]: Hour The alarm hour. Hours are matched only if MASKn.SEL is greater than 2. z Bits 11:6 - MINUTE[5:0]: Minute The alarm minute. Minutes are matched only if MASKn.SEL is greater than 1. z Bits 5:0 - SECOND[5:0]: Second The alarm second. Seconds are matched only if MASKn.SEL is greater than 0. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 265 17.8.27 Alarm n Mask - MODE2 Name: MASK Offset: 0x1C Reset: 0x00 Property: Write-Protected, Write-Synchronized Bit 7 6 5 4 3 2 1 0 SEL[2:0] Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 2:0 - SEL[2:0]: Alarm Mask Selection These bits define which bit groups of Alarm n are valid. Table 17-11. Alarm Mask Selection SEL[2:0] Name 0x0 OFF 0x1 SS 0x2 MMSS 0x3 HHMMSS 0x4 DDHHMMSS 0x5 MMDDHHMMSS 0x6 YYMMDDHHMMSS 0x7 Description Alarm Disabled Match seconds only Match seconds and minutes only Match seconds, minutes, and hours only Match seconds, minutes, hours, and days only Match seconds, minutes, hours, days, and months only Match seconds, minutes, hours, days, months, and years Reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 266 18. DMAC - Direct Memory Access Controller 18.1 Overview The Direct Memory Access Controller (DMAC) contains both a Direct Memory Access engine and a Cyclic Redundancy Check (CRC) engine. The DMAC can transfer data between memories and peripherals, and thus off-load these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU time. With access to all peripherals, the DMAC can handle automatic transfer of data between communication modules. For the DMA part of the DMAC, it has several DMA channels which all can receive different types of transfer triggers, which will result in transfer requests from the DMA channels to the arbiter. Refer to Figure 18-1. The arbiter will grant one DMA channel at a time to act as the active channel. When the active channel has been granted, the fetch engine of the DMAC will fetch a transfer descriptor from SRAM into the internal memory of the active channel, before the active channel starts its data transmission. A DMA channel's data transfer can be interrupted by a higher prioritized channel. The DMAC will write back the updated transfer descriptor from the internal memory of the active channel to SRAM, before the higher prioritized channel gets to start its transfer. Once a DMA channel is done with its transfer optionally interrupts and events can be generated. As one can see from Figure 18-1, the DMAC has four bus interfaces. The data transfer bus, which is used for performing the actual DMA transfer is an AHB master interface. The AHB/APB Bridge bus is an APB slave interface and is the bus used when writing and reading the I/O registers of the DMAC. The descriptor fetch bus is an AHB master interface and is used by the fetch engine, to fetch transfer descriptors from SRAM before a transfer can be started or continued. At last there is the write-back bus, which is an AHB master interface and it is used to write the transfer descriptor back to SRAM. As mentioned, the DMAC also has a CRC module available. This can be used by software to detect an accidental error in the transferred data and to take corrective action, such as requesting the data to be sent again or simply not using the incorrect data. 18.2 Features z Data transfer between Peripheral to peripheral Peripheral to memory z Memory to peripheral z Memory to memory z z z Transfer trigger sources Software Events from Event System z Dedicated requests from peripherals z z z SRAM based transfer descriptors z z Single transfer using one descriptor Multi-buffer or circular buffer modes by linking multiple descriptors z 12 channels Enable 12 independent transfers Automatic descriptor fetch for each channel z Suspend/resume operation support for each channel z z z Flexible arbitration scheme z z 4 configurable priority levels for each channel Fixed or round-robin priority scheme within each priority level z From 1 to 256kB data transfer in a single block transfer z Multiple addressing modes z z Static Configurable increment scheme Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 267 z Optional interrupt generation On block transfer complete On error detection z On channel suspend z z z 4 event inputs One event input for each of the 4 least significant DMA channels Can be selected to trigger normal transfers, periodic transfers or conditional transfers z Can be selected to suspend or resume channel operation z z z 4 event outputs z z One output event for each of the 4 least significant DMA channels Selectable generation on AHB, burst, block or transaction transfer complete z Error management supported by write-back function z Dedicated Write-Back memory section for each channel to store ongoing descriptor transfer z CRC polynomial software selectable to z z 18.3 CRC-16 (CRC-CCITT) CRC-32 (IEEE 802.3) Block Diagram Figure 18-1. DMAC Block Diagram CPU M AHB/APB Bridge SRAM Descriptor Fetch M Data Transfer S S Write-back HIGH SPEED BUS MATRIX DMAC MASTER Fetch Engine DMA Channels Channel n Transfer Triggers n Channel 1 Channel 0 Interrupts Arbiter Active Channel Interrupt / Events Events CRC Engine 18.4 Signal Description Not applicable. 18.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 268 18.5.1 I/O Lines Not applicable. 18.5.2 Power Management The DMAC will continue to operate in any sleep mode where the selected source clock is running. The DMAC's interrupts can be used to wake up the device from sleep modes. Events connected to the event system can trigger other operations in the system without exiting sleep modes. Refer to "PM - Power Manager" on page 112 for details on the different sleep modes. On hardware or software reset, all registers are set to their reset value. 18.5.3 Clocks The DMAC bus clock (CLK_DMAC_APB) can be enabled and disabled in the power manager, and the default state of CLK_DMAC_APB can be found in "Peripheral Clock Masking" on page 116. An AHB clock (CLK_DMAC_AHB) is required to clock the DMAC. This clock must be configured and enabled in the power manager before using the DMAC, and the default state of CLK_DMAC_AHB can be found in "Peripheral Clock Masking" on page 116. This bus clock (CLK_DMAC_APB) is always synchronous to the module clock (CLK_DMAC_AHB), but can be divided by a prescaler and may run even when the module clock is turned off. 18.5.4 DMA Not applicable. 18.5.5 Interrupts The interrupt request line is connected to the interrupt controller. Using the DMAC interrupts requires the interrupt controller to be configured first. Refer to "Nested Vector Interrupt Controller" on page 29 for details. 18.5.6 Events The events are connected to the event system. Refer to "EVSYS - Event System" on page 400 for details on how to configure the Event System. 18.5.7 Debug Operation When the CPU is halted in debug mode the DMAC will halt normal operation. The DMAC can be forced to continue operation during debugging. Refer to DBGCTRL for details. 18.5.8 Register Access Protection All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the following registers: z Interrupt Pending (INTPEND) register z Channel ID (CHID) register z Channel Interrupt Flag Status and Clear (CHINTFLAG) register Write-protection is denoted by the Write-Protected property in the register description. Write-protection does not apply to accesses through an external debugger. Refer to "PAC - Peripheral Access Controller" on page 36 for details. 18.5.9 Analog Connections Not applicable. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 269 18.6 Functional Description 18.6.1 Principle of Operation The DMAC consists of a DMA module and a CRC module. 18.6.1.1 DMA The DMAC can, without interaction from the CPU, transfer data between peripherals and memories. The data transferred by the DMAC are called transactions, and these transactions can be split into smaller data transfers. Figure 18-2 shows the relationship between the different transfer sizes. Figure 18-2. DMA Transfer Sizes Link Enabled Beat transfer Link Enabled Burst transfer Link Enabled Block transfer DMA transaction z Beat transfer: Defined as the size of one data transfer bus access, and the size is selected by writing the Beat Size bit group in the Block Transfer Control register (BTCTRL.BEATSIZE) z Burst transfer: Defined as n beat transfers, where n will differ from one device family to another. For this device family, n is 1. A burst transfer is atomic, and cannot be interrupted. z Block transfer: The amount of data one transfer descriptor can transfer, and the amount can range from 1 to 64k beats. In contrast to the burst transfer, a block transfer can be interrupted. z Transaction: The DMAC can link several transfer descriptors by having the first descriptor pointing to the second and so forth, as shown in Figure 18-2. A DMA transaction is defined as all block transfers within a linked list, being completed. A transfer descriptor describes how a block transfer should be carried out by the DMAC, and it must remain in SRAM. For further details on the transfer descriptor refer to "Transfer Descriptors" on page 272. Figure 18-2 shows several block transfers linked together, which are called linked descriptors. For further information about linked descriptors, refer to "Linked Descriptors" on page 279. A DMA transfer is initiated by an incoming transfer trigger on one of the DMA channels. This trigger can be configured to be either a software trigger, an event trigger or one of the dedicated peripheral triggers. The transfer trigger will result in a DMA transfer request from the specific channel to the arbiter, and if there are several DMA channels with pending transfer requests, the arbiter has to choose which channel to grant access to become the active channel. The DMA channel granted access as the active channel will carry out the transaction as configured in the transfer descriptor. The DMA channel can be interrupted by a higher prioritized channel after each burst transfer, but will resume its block transfer when it is granted access as the active channel again. For each beat transfer an optional output event can be generated, and for each block transfer optional interrupts and an optional output event can be generated. When a transaction is completed, dependent of the configuration, the DMA channel will either be suspended or disabled. 18.6.1.2 CRC The internal CRC supports two commonly used CRC polynomials; CRC-16 (CRC-CCITT) and CRC-32 (IEEE 802.3). It can be used with selectable DMA channel or independently, with I/O interface. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 270 18.6.2 Basic Operation 18.6.2.1 Initialization The following DMAC registers are enable-protected, meaning that they can only be written when the DMAC is disabled (CTRL.DMAENABLE is zero): z Descriptor Base Memory Address (BASEADDR) register z Write-Back Memory Base Address (WRBADDR) register The following DMAC bit is enable-protected, meaning that it can only be written when both the DMAC and CRC are disabled (CTRL.DMAENABLE and CTRL.CRCENABLE is zero): z Software Reset bit in Control register (CTRL.SWRST) The following DMA channel register is enable-protected, meaning that it can only be written when the corresponding DMA channel is disabled (CHCTRLA.ENABLE is zero): z Channel Control B (CHCTRLB) register, except the Command (CHCTRLB.CMD) and Channel Arbitration Level (CHCTRLB.LVL) bits The following DMA channel bit is enable-protected, meaning that it can only be written when the corresponding DMA channel is disabled: z Channel Software Reset bit in Channel Control A register (CHCTRLA.SWRST) The following CRC registers are enable-protected, meaning that they can only be written when the CRC is disabled (CTRL.CRCENABLE is zero): z CRC Control (CRCCTRL) register z CRC Checksum (CRCCHKSUM) register Enable-protection is denoted by the Enable-Protected property in the register description. Before the DMAC is enabled, it must be configured, as outlined by the following steps: z The SRAM address of where the descriptor memory section is located must be written to the Description Base Address (BASEADDR) register z The SRAM address of where the write-back section should be located must be written to the Write-Back Memory Base Address (WRBADDR) register z Priority level x of the arbiter can be enabled by writing a one to the Priority Level x Enable bit in the Control register(CTRL.LVLENx) Before a DMA channel is enabled, the DMA channel and the corresponding first transfer descriptor must be configured, as outlined by the following steps: z z DMA channel configurations z The channel number of the DMA channel to configure must be written to the Channel ID (CHID) register z Trigger action must be selected by writing the Trigger Action bit group in the Channel Control B register (CHCTRLB.TRIGACT) z Trigger source must be selected by writing the Trigger Source bit group in the Channel Control B register (CHCTRLB.TRIGSRC) Transfer Descriptor z The size of each access of the data transfer bus must be selected by writing the Beat Size bit group in the Block Transfer Control register (BTCTRL.BEATSIZE) z The transfer descriptor must be made valid by writing a one to the Valid bit in the Block Transfer Control register (BTCTRL.VALID) z Number of beats in the block transfer must be selected by writing the Block Transfer Count (BTCNT) register z Source address for the block transfer must be selected by writing the Block Transfer Source Address (SRCADDR) register Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 271 z Destination address for the block transfer must be selected by writing the Block Transfer Destination Address (DSTADDR) register If CRC calculation is needed the CRC module must be configured before it is enabled, as outlined by the following steps: z CRC input source must selected by writing the CRC Input Source bit group in the CRC Control register (CRCCTRL.CRCSRC) z Type of CRC calculation must be selected by writing the CRC Polynomial Type bit group in the CRC Control register (CRCCTRL.CRCPOLY) z If I/O is chosen as input source, the beat size must be selected by writing the CRC Beat Size bit group in the CRC Control register (CRCCTRL.CRCBEATSIZE) 18.6.2.2 Enabling, Disabling and Resetting The DMAC is enabled by writing a one to the DMA Enable bit in the Control register (CTRL.DMAENABLE). The DMAC is disabled by writing a zero to CTRL.DMAENABLE. A DMA channel is enabled by writing a one to Enable bit in the Channel Control A register (CHCTRLA.ENABLE), after writing the corresponding channel id to the Channel ID bit group in the Channel ID register (CHID.ID). A DMA channel is disabled by writing a zero to CHCTRLA.ENABLE. The CRC is enabled by writing a one to the CRC Enable bit in the Control register (CTRL.CRCENABLE). The CRC is disabled by writing a zero to CTRL.CRCENABLE. The DMAC is reset by writing a one to the Software Reset bit in the Control register (CTRL.SWRST), when the DMAC and CRC are disabled. All registers in the DMAC, except DBGCTRL, will be reset to their initial state. A DMA channel is reset by writing a one to the Software Reset bit in the Channel Control A register (CHCTRLA.SWRST), after writing the corresponding channel id to the Channel ID bit group in the Channel ID register (CHID.ID). The channel registers will be reset to their initial state. The corresponding DMA channel must be disabled in order for the reset to take effect. 18.6.2.3 Transfer Descriptors Together with the channel configurations the transfer descriptors decides how a block transfer should be executed. Before a DMA channel is enabled (CHCTRLA.ENABLE is written to one), and receives a transfer trigger, its first transfer descriptor has to be initialized and valid (BTCTRL.VALID). The first transfer descriptor describes the first block transfer of a transaction. For further details on the content of a transfer descriptor, refer to "Block Transfer Control" on page 324. All transfer descriptors must reside in SRAM and the addresses stored in the Descriptor Memory Section Base Address (BASEADDR) and Write-Back Memory Section Base Address (WRBADDR) registers tells the DMAC where to find the descriptor memory section and the write-back memory section. The descriptor memory section is where the DMAC expects to find the first transfer descriptors for all DMA channels. As BASEADDR points only to the first transfer descriptor of channel 0, refer to Figure 18-3, all first transfer descriptors must be stored in a contiguous memory section, where the transfer descriptors must be ordered according to their channel number. Figure 18-3 shows an example of linked descriptors on DMA channel 0. For further details on linked descriptors, refer to "Linked Descriptors" on page 279. The write-back memory section is the section where the DMAC stores the transfer descriptors for the ongoing block transfers. WRBADDR points to the ongoing transfer descriptor of channel 0. All ongoing transfer descriptors will be stored in a contiguous memory section where the transfer descriptors are ordered according to their channel number. Figure 18-3 shows an example of linked descriptors on DMA channel 0. For further details on linked descriptors, refer to "Linked Descriptors" on page 279. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 272 Figure 18-3. Memory Sections 0x00000000 DSTADDR DESCADDR Channel 0 - Last Descriptor SRCADDR BTCNT BTCTRL DESCADDR DSTADDR DESCADDR Channel 0 - Descriptor n-1 SRCADDR BTCNT BTCTRL Descriptor Section Channel n - First Descriptor DESCADDR BASEADDR Channel 2 - First Descriptor Channel 1 - First Descriptor Channel 0 - First Descriptor DSTADDR SRCADDR BTCNT BTCTRL Write-Back Section Channel n Ongoing Descriptor WRBADDR Channel 2 Ongoing Descriptor Channel 1 Ongoing Descriptor Channel 0 Ongoing Descriptor Device Memory Space Undefined Undefined Undefined Undefined Undefined The size of the descriptor and write-back memory sections is dependant on most significant enabled DMA channel, as shown below: Size = 128bits ( MostSignificantEnabledChannelNumber + 1 ) For memory optimization, it is recommended to always use the less significant DMA channels if not all channels are required. The descriptor and write-back memory sections can either be two separate memory sections, or they can share memory section (BASEADDR=WRBADDR). The benefit of having them in two separate sections, is that the same transaction for a channel can be repeated without having to modify the first transfer descriptor. The benefit of having descriptor memory and write-back memory in the same section is that it requires less SRAM. In addition, the latency from fetching the first descriptor of a transaction to the first burst transfer is executed, is reduced. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 273 18.6.2.4 Arbitration If a DMA channel is enabled and not suspended when it receives a transfer trigger, it will send a transfer request to the arbiter. When the arbiter receives the transfer request it will include the DMA channel in the queue of channels having pending transfers, and the corresponding Pending Channel x bit in the Pending Channels registers (PENDCH.PENDCHx) will be set. Dependent of the arbitration scheme, the arbiter will choose which DMA channel will be the next active channel. Refer to Figure 18-4. The active channel is the DMA channel being granted access to perform its next burst transfer. When the arbiter has granted a DMA channel access to the DMAC, the corresponding PENDCH.PENDCHx will be cleared. Depending on if the upcoming burst transfer is the first for the transfer request or not, the corresponding Busy Channel x bit in the Busy Channels register (BUSYCH.BUSYCHx) will either be set or remain one. When the channel has performed its granted burst transfer(s) it will either be fed into the queue of channels with pending transfers, set to be waiting for a new transfer trigger, it will be suspended or it will be disabled. This depends on the channel and block transfer configuration. If the DMA channel is fed into the queue of channels with pending transfers, the corresponding BUSYCH.BUSYCHx will remain one. If the DMA channel is set to wait for a new transfer trigger, suspended or disabled, the corresponding BUSYCH.BUSYCHx will be cleared. If a DMA channel is suspended while it has a pending transfer, it will be removed from the queue of pending channels, but the corresponding PENDCH.PENDCHx will remain set. When the same DMA channel is resumed, it will be added to the queue of pending channels again. If a DMA channel gets disabled(CHCTRLA.ENABLE is zero) while it has a pending transfer, it will be removed from the queue of pending channels, and the corresponding PENDCH.PENDCHx will be cleared. Figure 18-4. Arbiter Overview Arbiter Channel Enable Channel Pending Channel 0 Priority decoder Channel Suspend Channel Priority Level Channel Burst Done Burst Done Transfer Request Channel Enable Channel Number Channel Suspend Channel N Active Channel Channel Pending Channel Priority Level Channel Burst Done Level Enable CTRL.LVLENx ACTIVE.LVLEXx PRICTRLx.LVLPRI When a channel level is pending or the channel is transferring data, the corresponding Level Executing bit is set in the Active Channel and Levels register (ACTIVE.LVLEXx). Each DMA channel supports a 4-level priority scheme. The priority level for a channel is configured by writing to the Channel Arbitration Level bit group in the Channel Control B register(CHCTRLB.LVL). As long as all priority levels are enabled, a channel with lower priority level number will have priority over a channel with higher priority level number. A priority level is enabled by writing the Priority Level x Enable bit in the Control register(CTRL.LVLENx) to one, for the corresponding level. Within each priority level the DMAC's arbiter can be configured to prioritize statically or dynamically. For the arbiter to perform static arbitration within a priority level, the Level x Round-Robin Scheduling Enable bit in the Priority Control 0 register (PRICTRL0.RRLVLENx) has to be written to zero. When static arbitration is enabled (PRICTRL0.RRLVLENx is zero), the arbiter will prioritize a low channel number over a high channel number as shown in Figure 18-5. When using Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 274 the static scheme there is a risk of high channel numbers never being granted access as the active channel. This can be avoided using a dynamic arbitration scheme. Figure 18-5. Static Priority Lowest Channel Channel 0 Highest Priority . . . Channel x Channel x+1 . . . Highest Channel Channel N Lowest Priority The dynamic arbitration scheme available in the DMAC is round-robin. Round-robin arbitration is enabled by writing PRICTRL0.RRLVLENx to one, for a given priority level x. With the round-robin scheme, the channel number of the last channel being granted access will have the lowest priority the next time the arbiter has to grant access to a channel within the same priority level, as shown in Figure 18-6. The channel number of the last channel being granted access as the active channel, will be stored in the Level x Channel Priority Number bit group in the Priority Control 0 register(PRICTRL0.LVLPRIx), for the corresponding priority level. Figure 18-6. Round-Robin Scheduling Channel x last acknowledged request Channel (x+1) last acknowledged request Channel 0 Channel 0 . . . . . . Channel x Channel x+1 . . . Channel N Lowest Priority Highest Priority Channel x Channel x+1 Channel x+2 Lowest Priority Highest Priority . . . Channel N 18.6.2.5 Data Transmission Before the DMAC can perform a data transmission, a DMA channel has to be configured and enabled, its corresponding transfer descriptor has to be initialized and the arbiter has to grant the DMA channel access as the active channel. Once the arbiter has granted a DMA channel access as the active channel (refer to Figure 18-1) the transfer descriptor for the DMA channel will be fetched from SRAM using the fetch bus, and stored in the internal memory for the active channel. Depending on if it is a new or ongoing block transfer, the transfer descriptor will either be fetched from the descriptor memory section (BASEADDR) or the write-back memory section (WRBADDR). By using the data transfer bus, the DMAC will read the data from the current source address and write it to the current destination address. For further details on how the current source and destination addresses are calculated, refer to "Addressing" on page 277. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 275 The arbitration procedure is performed after each burst transfer. If the current DMA channel is granted access again, the block transfer counter (BTCNT) of the internal transfer descriptor will be decremented with the number of beats in a burst, and the active channel will perform a new burst transfer. If a different DMA channel than the current active channel is granted access, the BTCNT of the internal transfer descriptor will be decremented with the number of beats in a burst. The block transfer counter value will be written to the write-back section before the transfer descriptor of the newly granted DMA channel is fetched into the internal memory of the active channel. The optional output event, Beat, will be generated if configured and enabled. When a block transfer has come to its end, BTCNT has reached zero, the Valid bit in the Block Transfer Control register will be written to zero in the internal transfer descriptor for the active channel before the entire transfer descriptor is written to the write-back memory. The optional interrupts, Channel Transfer Complete and Channel Suspend, and the optional output event, Block, will be generated if configured and enabled. If it was the last block transfer in a transaction, Next Address (DESCADDR) register will hold the value 0x00000000, and the DMA channel will either be suspended or disabled, depending on the configuration in the Block Action bit group in the Block Transfer Control register(BTCTRL.BLOCKACT). If the transaction has further block transfers pending, DESCADDR will hold the SRAM address to the next transfer descriptor to be fetched. The DMAC will fetch the next descriptor into the internal memory of the active channel and write its content to the write-back section for the channel, before the arbiter gets to choose the next active channel. 18.6.2.6 Transfer Triggers and Actions A DMA transfer can be started only when a DMA transfer request is detected. A transfer request can be triggered from software, from peripheral, or from an event. There are dedicated Trigger Source selections for each DMA Channel Control B (CHCTRLB.TRIGSRC). The trigger actions are available in the Trigger Action bit group in the Channel Control B register (CHCTRLB.TRIGACT). By default, a trigger starts a block transfer operation. If a single descriptor is defined for a channel, the channel is automatically disabled when a block transfer is complete. If a list of linked descriptors is defined for a channel, the channel is automatically disabled if the last descriptor in the list is executed or the channel will be waiting for the next block transfer trigger if the list still has descriptors to execute. When enabled again, the channel will wait for the next block transfer trigger. It is also possible to select the trigger to start beat or transaction transfers instead of a block transfer. If the trigger source generates a transfer request during an ongoing transfer, this will be kept pending (CHSTATUS.PEND is one), and the transfer can start when the ongoing one is done. Only one pending transfer can be kept, and so if the trigger source generates more transfer requests when one is already pending, these will be lost. All channels pending status flags are also available in the Pending Channels register (PENDCH). When the transfer starts, the corresponding Channel Busy status flag is set in Channel Status register (CHSTATUS.BUSY). When the trigger action is complete, the Channel Busy status flag is cleared. All channels busy status flags are also available in the Busy Channels register (BUSYCH) in DMAC. Figure 18-7 on page 277 shows an example where triggers are used with two linked block descriptors. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 276 Figure 18-7. Trigger Action and Transfers Beat Trigger Action CHENn Trigger Lost Trigger PENDCHn BUSYCHn Block Transfer Data Transfer BEAT Block Transfer BEAT BEAT BEAT BEAT BEAT BEAT BEAT BEAT BEAT Block Trigger Action CHENn Trigger Lost Trigger PENDCHn BUSYCHn Block Transfer Data Transfer BEAT Block Transfer BEAT BEAT BEAT Transaction Trigger Action CHENn Trigger Lost Trigger PENDCHn BUSYCHn Block Transfer Data Transfer BEAT Block Transfer BEAT BEAT BEAT 18.6.2.7 Addressing For the DMAC to know from where to where it should transfer the data, each block transfer needs to have a source and destination address defined. The source address can be set by writing the Transfer Source Address (SRCADDR) register, and the destination address can be set by writing the Transfer Destination Address (SRCADDR) register. The addressing of this DMAC module can be static or incremental, for either source or destination of a block transfer, or both. Incrementation for the source address of a block transfer is enabled by writing the Source Address Incrementation Enable bit in the Block Transfer Control register (BTCTRL.SRCINC) to one. The step size of the incrementation is configurable and can be chosen by writing the Step Selection bit in the Block Transfer Control Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 277 register(BTCTRL.STEPSEL) to one, and the Address Increment Step Size bit group in the Block Transfer Control register (BTCTRL.STEPSIZE), to the desired step size. If BTCTRL.STEPSEL is zero, the step size for the source incrementation will be the size of one beat. When source address incrementation is configured (BTCTRL.SRCINC is one), SRCADDR must be set to the source address of the last beat transfer in the block transfer. The source address should be calculated as follows: SRCADDR = SRCADDR START + BTCNT ( BEATSIZE + 1 ) 2 STEPSIZE , where BTCTRL.STEPSEL is one SRCADDR = SRCADDR START + BTCNT ( BEATSIZE + 1 ) , where BTCTRL.STEPSEL is zero z SRCADDRSTART is the source address of the first beat transfer in the block transfer z BTCNT is the initial number of beats remaining in the block transfer z BEATSIZE is the configured number of bytes in a beat z STEPSIZE is the configured number of beats for each incrementation Figure 18-8 shows an example where DMA channel 0 is configured to increment the source address by one beat (BTCTRL.SRCINC is one) after each beat transfer, and DMA channel 1 is configured to increment source address by two beats (BTCTRL.SRCINC is one, BTCTRL.STEPSEL is one, and BTCTRL.STEPSIZE is 0x1). As the destination address for both channels are peripherals, destination incrementation is disabled(BTCTRL.DSTINC is zero). Figure 18-8. Source Address Increment SRC Data Buffer a b c d e DMA Channel 0 DMA Channel 1 {a,b} {c,e} PERIPHERAL 0 PERIPHERAL 1 f Incrementation for the destination address of a block transfer is enabled by writing the Destination Address Incrementation Enable bit in the Block Transfer Control register (BTCTRL.DSTINC) to one. The step size of the incrementation is configurable and can be chosen by writing BTCTRL.STEPSEL to zero, and BTCTRL.STEPSIZE to the desired step size. If BTCTRL.STEPSEL is one, the step size for the destination incrementation will be the size of one beat. When destination address incrementation is configured (BTCTRL.DSTINC is one), SRCADDR must be set to the destination address of the last beat transfer in the block transfer. The destination address should be calculated as follows: DSTADDR = DSTADDR START + BTCNT ( BEATSIZE + 1 ) 2 STEPSIZE , where BTCTRL.STEPSEL is zero DSTADDR = DSTADDR START + BTCNT ( BEATSIZE + 1 ) , where BTCTRL.STEPSEL is one z DSTADDRSTART is the destination address of the first beat transfer in the block transfer z BTCNT is the initial number of beats remaining in the block transfer z BEATSIZE is the configured number of bytes in a beat z STEPSIZE is the configured number of beats for each incrementation Figure 18-9 shows an example where DMA channel 0 is configured to increment destination address by one beat (BTCTRL.DSTINC is one) and DMA channel 1 is configured to increment destination address by two beats (BTCTRL.DSTINC is one, BTCTRL.STEPSEL is zero, and BTCTRL.STEPSIZE is 0x1). As the source address for both channels are peripherals, source incrementation is disabled(BTCTRL.SRCINC is zero). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 278 Figure 18-9. Destination Address Increment DST Data Buffer a PERIPHERAL 0 PERIPHERAL 1 {a,b} {c,d} DMA Channel 0 DMA Channel 1 b c d 18.6.2.8 Error Handling If a bus error is received from AHB slave during a DMA data transfer, the corresponding active channel is disabled and the corresponding Channel Transfer Error Interrupt flag in the Channel Interrupt Status and Clear register (CHINTFLAG.TERR) is set. If transfer error interrupt is enabled, optional error interrupt is generated. The transfer counter will not be decremented and its current value is written-back in the write-back memory section before the channel is disabled. When the DMAC fetches an invalid descriptor (BTCTRL.VALID is zero) or when the channel is resumed and the DMA fetches the next descriptor with null address (DESCADDR is 0x00000000), the corresponding channel operation is suspended, the Channel Suspend Interrupt Flag in the Channel Interrupt Flag Status and Clear register (CHINTFLAG.SUSP) is set and the Channel Fetch Error bit in the Channel Status register (CHSTATUS.FERR) is set. If enabled, optional suspend interrupt is generated. 18.6.3 Additional Features 18.6.3.1 Linked Descriptors A transaction can either consist of a single block transfer, or it can consist of several block transfers. When a transaction consist of several block transfers it is called linked descriptors. Figure 18-3 shows how linked descriptors work. When the first block transfer is completed on DMA channel 0, the DMAC fetches the next transfer descriptor which is pointed to by the value stored in the Next Descriptor Address (DESCADDR) register, in the first transfer descriptor. Fetching the next transfer descriptor (DESCADDR) is continued until the last transfer descriptor. When the block transfer for the last transfer descriptor is executed and DESCADDR=0x00000000, the transaction is terminated. For further details on how the next descriptor is fetched from SRAM, refer to "Data Transmission" on page 275. Adding Descriptor to the End of a List To add a new descriptor at the end of the descriptor list, create the descriptor in SRAM, with DESCADDR=0x00000000 indicating it is the new last descriptor in the list, and modify the DESCADDR value of the current last descriptor to the address of the newly created descriptor. Modifying a Descriptor in a List In order to add descriptors to a list, the following actions must be performed: 1. Before enabling a channel, the Suspend interrupt must be enabled 2. Reserve memory space addresses to configure a new descriptor 3. Configure the new descriptor z Set the next descriptor address (DESCADDR) z Set the destination address (DSTADDR) z Set the source address (SRCADDR) z Configure the block transfer control (BTCTRL) including z Optionally enable the Suspend block action z Set the descriptor VALID bit 4. In the existing list and for the descriptor which has to be updated, set the VALID bit to zero 5. Read DESCADDR from the Write-Back memory Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 279 z z 6. If the DMA has not already fetched the descriptor which requires changes: z Update the DESCADDR location of the descriptor from the List z Optionally clear the Suspend block action z Set the descriptor VALID bit to one z Optionally enable the Resume software command If the DMA is executing the same descriptor as the one which requires changes: z Set the Channel Suspend software command and wait for the Suspend interrupt z Update the Write-Back next descriptor address (DESCRADDR) z Clear the interrupt sources and set the Resume software command z Update the DESCADDR location of the descriptor from the List z Optionally clear the Suspend block action z Set the descriptor VALID bit to one Go to step 3 if needed Adding a Descriptor Between Existing Descriptors To insert a descriptor C between 2 existing descriptors (A & B), the descriptor currently executed by the DMA must be identified. 1. If DMA is executing descriptor B, descriptor C cannot be inserted. 2. If DMA has not started to execute descriptor A, follow the steps: 3. a. Set the descriptor A VALID bit to 0 b. Set the DESCADDR value of descriptor A to point descriptor C instead of descriptor B c. Set the DESCADDR value of descriptor C to point descriptor B d. Set the descriptor A VALID bit to 1. If DMA is executing descriptor A, a. Apply the software suspend command to the channel and b. Perform steps 2a through 2d Apply the software resume command to the channel. 18.6.3.2 Channel Suspend The channel operation can be suspended at anytime by software, by setting the Suspend command in Command bit field of Channel Control B register (CHCTRLB.CMD). When the ongoing burst transfer is completed, the channel operation is suspended and the suspend command is automatically cleared. It is also possible to suspend a channel operation after a block transfer completes. The software must set the Suspend Block Action in the corresponding Block Transfer Control location (BTCTRL.BLOCKACT). When the block transfer is completed, the channel operation is suspended. The channel is kept enabled, can receive transfer triggers, but it will be removed from the arbitration scheme. The channel will automatically suspend the operation if an invalid transfer control descriptor is fetched from system memory (BTCTRL.VALID=0). The Channel Fetch Error bit in the Channel Status register (CHSTATUS.FERR) is set when an invalid descriptor is fetched. Only an enabled channel can be suspended. If the channel is disabled when suspended, the internal suspend command is cleared. When suspended, the Channel Suspend Interrupt flag in the Channel Interrupt Status and Clear register (CHINTFLAG.SUSP) is set and optional suspend interrupt is generated. For more details on transfer descriptors, refer to "Transfer Descriptors" on page 272. 18.6.3.3 Channel Resume and Next Suspend Skip A channel operation can be resumed by software by setting the Resume command in Command bitfield of Channel Control B register (CHCTRLB.CMD). If the channel is already suspended, the channel operation resumes from where it previously stopped when the Resume command is detected. When the Resume command is issued before the channel is suspended, the next suspend action is skipped and the channel continues the normal operation. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 280 Figure 18-10.Channel Suspend/Resume Operation CHENn Descriptor 0 (suspend disabled) Memory Descriptor Descriptor 1 (suspend enabled) Descriptor 2 (suspend enabled) Descriptor 3 (last) Channel suspended Fetch Transfer Block Transfer 0 Block Transfer 1 Block Transfer 2 Block Transfer 3 Resume Command Suspend skipped 18.6.3.4 Event Input Actions The event input actions are available only for channels supporting event inputs. For details on channels with event input support, refer to Table 22-6 and Table 22-4. The Event Actions bits in the Channel Control B register (CHCTRLB.EVACT) specify the actions the DMA will take on an input event. Before using event actions, the event controller must be configured first and the corresponding Channel Event Input Enable bit (CHCTRLB.EVIE) must be set. The DMA supports only resynchronized events. For details on how to configure the resynchronized event path, refer to the Event System. Normal transfer: When this event action is selected for a channel, the event input is used to trigger a beat or burst transfer on peripherals. The transfer trigger is selected by setting the Trigger Source bits in Channel Control B register to zero (CHCTRLB.TRIGSRC). The event is acknowledged as soon as the event is received. When received, the Channel Pending status bit is set (CHSTATUS.PEND). If the event is received while the channel is pending, the event trigger is lost. Figure 18-11 shows an example where beat transfers are enabled by internal events. Figure 18-11.Beat Event Trigger Action CHENn Peripheral Trigger Trigger Lost Event PENDCHn BUSYCHn Block Transfer Data Transfer BEAT Block Transfer BEAT BEAT BEAT BEAT BEAT Periodic transfers: When this event action is selected for a channel, the event input is used to trigger a transfer on peripherals with pending transfer requests. This type of event is intended to be used with peripheral triggers for example, for timed communication protocols or periodic transfers between peripherals, as examples. The peripheral trigger is selected by the Trigger Source bits in the Channel Control B register (CHCTRLB.TRIGSRC). The event is acknowledged as soon as the event is received. The peripheral trigger request is stored internally when the previous trigger action is completed (i.e. channel is not pending) and when an active event is received. If the peripheral trigger is active, the DMA will wait for an event before the peripheral trigger is internally registered. When both event and peripheral transfer trigger are active, the Channel Pending status bit is set (CHSTATUS.PEND). A software trigger will now trigger a transfer. Figure 18-12 shows an example where the peripheral beat transfers are enabled by periodic events. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 281 Figure 18-12.Periodic Event with Beat Peripheral Triggers Trigger Lost Trigger Lost Event Peripheral Trigger PENDCHn Block Transfer Data Transfer BEAT Conditional transfer: When the conditional transfer event action is selected, the event input is used to trigger a conditional transfer on peripherals with pending transfer requests. As example, this type of event can be used for peripheral to peripheral transfers, where one peripheral is source of event and the second peripheral is source of DMA trigger. The peripheral Trigger Source must be set in Channel Control B register (CHCTRLB.TRIGSRC). Each peripheral trigger is stored internally when the event is received. When the peripheral trigger is stored internally, the Channel Pending status bit is set (CHSTATUS.PEND) and the event is acknowledged. A software trigger will now trigger a transfer. Figure 18-13 shows an example where conditional event is enabled with peripheral beat trigger requests. Figure 18-13.Conditional Event with Beat Peripheral Triggers Event Peripheral Trigger PENDCHn Data Transfer Block Transfer BEAT BEAT Conditional block transfer: When the conditional block event action is selected, the event input is used to trigger a conditional block transfer on peripherals. The peripheral Trigger Source must be set in Channel Control B register (CHCTRLB.TRIGSRC). Before starting transfers within a block, an event must be received. When received, the event is acknowledged when the block transfer is completed. A software trigger will trigger a transfer. Figure 18-14 shows an example where conditional event block transfer is enabled with peripheral beat trigger requests. Figure 18-14.Conditional Block Transfer with Beat Peripheral Triggers Event Peripheral Trigger PENDCHn Block Transfer Data Transfer Block Transfer BEAT BEAT BEAT BEAT Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 282 Channel suspend: When the channel suspend event action is selected, the event input is used to suspend an ongoing channel operation. The event is acknowledged when the current AHB access is completed. For further details on channel suspend, refer to "Channel Suspend" on page 280. Channel resume: When the channel resume event action is selected, the event input is used to resume a suspended channel operation. The event is acknowledged as soon as the event is received and the Channel Suspend Interrupt Flag (CHINTFLAG.SUSP) is cleared. For further details on channel suspend, refer to "Channel Suspend" on page 280. Skip next block suspend: This event can be used to skip the next block suspend action. If the channel is suspended before the event rises, the channel operation is resumed and the event is acknowledged. If the event rises before a suspend block action is detected, the event is kept until the next block suspend detection. When the block transfer is completed, the channel continues the operation (not suspended) and the event is acknowledged. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 283 18.6.3.5 Event Output Selections The event output selections are available only for channels supporting event outputs. The pulse width of an event output from a channel is one AHB clock cycle. The Channel Event Output Enable can be set in Control B register (CHCTRLB.EVOE). The Event Output Selection is available in each Descriptor Block Control location (BTCTRL.EVOSEL). It is possible to generate events after each beat, burst or block transfer. To enable an event when the transaction is complete, the block event selection must be set in the last transfer descriptor only. Figure 18-15 shows an example where the event output generation is enabled in the first block transfer, and disabled in the second block. Figure 18-15.Event Output Generation Beat Event Output Block Transfer Data Transfer Block Transfer BEAT BEAT BEAT BEAT Event Output Block Event Output Block Transfer Data Transfer BEAT Block Transfer BEAT BEAT BEAT Event Output 18.6.3.6 Aborting Transfers Transfers on any channel can be gracefully aborted by software, by disabling the corresponding DMA channel. It is also possible to abort all ongoing or pending transfers, by disabling the DMAC. When DMAC disable request is detected: z Active channel with ongoing transfers will be disabled when the ongoing beat access is completed and the WriteBack memory section is updated. This prevents transfer corruption before the channel is disabled. z All other enabled channels will be disabled in the next clock cycle. The corresponding Channel Enable bit in the Channel Control A register (CHCTRLA.ENABLE) is read as zero when the channel is disabled. The corresponding DMAC Enable bit in the Control register (CTRL.DMAENABLE) is read as zero when the entire DMAC module is disabled. 18.6.3.7 CRC Operation A cyclic redundancy check (CRC) is an error detection technique used to find accidental errors in data. It is commonly used to determine whether the data during a transmission, or data present in data and programme memories has been corrupted or not. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be appended to the data and used as a checksum. When the same data are later received or read, the device or application repeats the calculation. If the new CRC result does not match the one calculated earlier, the block contains a data error. The application will then detect this and may take a corrective action, such as requesting the data to be sent again or simply not using the incorrect data. Typically, a CRC-n applied to a data block of arbitrary length will detect any single error burst not longer than n bits (any single alteration that spans no more than n bits of the data), and will detect the fraction 1-2-n of all longer error bursts. The Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 284 CRC module in DMAC supports two commonly used CRC polynomials: CRC-16 (CRC-CCITT) and CRC-32 (IEEE 802.3). z z CRC-16: z Polynomial: x16 + x12 + x5+1 z Hex value: 0x1021 CRC-32: z Polynomial: x32 +x26+x23 +x22 +x16 +x12 +x11 +x10 +x8 +x7 +x5 +x4 +x2 +x+1 z Hex value: 0x04C11DB7 The data source for the CRC module must be selected in software as either the DMA channels or the APB bus interface. The CRC module then takes data input from the selected source and generates a checksum based on these data. The checksum is available in the CRC Checksum register (CRCCHKSUM). When CRC-32 polynomial is used, the final checksum read is bit reversed and complemented, as shown in Figure 18-16 on page 285. The CRC polynomial to be used is configurable, and the default setting is CRC-16. The CRC module operates on byte only. When the DMA is used as data source for the CRC module, the DMA channel beat size setting will be used. When used with APB bus interface, the application must set the CRC Beat Size bit field of CRC Control register (CRCCTRL.CRCBEATSIZE). 8-, 16- or 32-bit bus transfer access type is supported. The corresponding number of bytes will be written in the CRCDATAIN register and the CRC module will operate on the input data in a byte by byte manner. Figure 18-16.CRC Generator Block Diagram DMAC Channels CRCDATAIN CRCCTRL 8 16 8 CRC-16 32 CRC-32 crc32 CHECKSUM bit-reverse + complement Checksum read CRC on DMA data: CRC-16 or CRC-32 calculations can be performed on data passing through any DMA channel. Once a DMA channel is selected as the source, the CRC module will continuously generate the CRC on the data passing through the DMA channel. The checksum is available for readout once the DMA transaction is completed or aborted. A CRC can also be generated on SRAM, Flash or I/O memory by passing these data through a DMA channel. If the latter is done, the destination register for the DMA data can be the data input (CRCDATAIN) register in the CRC module. CRC using the I/O interface: Before using the CRC module with the I/O interface, the application must set the CRC Beat Size bits in the CRC Control register (CRCCTRL.CRCBEATSIZE). 8/16/32-bit bus transfer type can be selected. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 285 CRC can be performed on any data by loading them into the CRC module using the CPU and writing the data to the CRCDATAIN register. Using this method, an arbitrary number of bytes can be written to the register by the CPU, and CRC is done continuously for each byte. This means if a 32-bit data is written to the CRCDATAIN register the CRC module takes 4 cycles to calculate the CRC. The CRC complete is signaled by the CRCBUSY bit in the CRCSTATUS register. New data can be written only when CRCBUSY flag is not set. 18.6.4 DMA Operation Not applicable. 18.6.5 Interrupts The DMAC has the following interrupt sources: z Transfer Complete (TCMPL): Indicates that a block transfer is completed on the corresponding channel. Refer to "Data Transmission" on page 275 for details. z Transfer Error (TERR): Indicates that a bus error has occurred during a burst transfer, or that an invalid descriptor has been fetched. Refer to "Error Handling" on page 279 for details. z Channel Suspend (SUSP): Indicates that the corresponding channel has been suspended. Refer to "Channel Suspend" on page 280 and "Data Transmission" on page 275 for details. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Channel Interrupt Flag Status and Clear (CHINTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one to the corresponding bit in the Channel Interrupt Enable Set (CHINTENSET) register, and disabled by writing a one to the corresponding bit in the Channel Interrupt Enable Clear (CHINTENCLR) register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, the DMAC is reset or the corresponding DMA channel is reset. See CHINTFLAG for details on how to clear interrupt flags. All interrupt requests are ORed together on system level to generate one combined interrupt request to the NVIC. Refer to "Nested Vector Interrupt Controller" on page 29 for details. The user must read the Channel Interrupt Status (INTSTATUS) register to identify the channels with pending interrupts and must read the Channel Interrupt Flag Status and Clear (CHINTFLAG) register to determine which interrupt condition is present for the corresponding channel. It is also possible to read the Interrupt Pending register (INTPEND), which provides the lowest channel number with pending interrupt and the respective interrupt flags. Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to "Nested Vector Interrupt Controller" on page 29 for details. 18.6.6 Events The DMAC can generate the following output events: z Channel (CH): Generated when a block transfer for a given channel has been completed, or when a beat transfer within a block transfer for a given channel has been completed. Refer to "Event Output Selections" on page 284 for details. Writing a one to the Channel Control B Event Output Enable bit (CHCTRLB.EVOE) enables the corresponding output event configured in the Event Output Selection bit group in the Block Transfer Control register (BTCTRL.EVOSEL). Writing a zero to CHCTRLB.EVOE disables the corresponding output event. Refer to "EVSYS - Event System" on page 400 for details on configuring the event system. The DMAC can take the following actions on an input event: z Transfer and Periodic Transfer Trigger (TRIG): normal transfer or periodic transfers on peripherals are enabled z Conditional Transfer Trigger (CTRIG): conditional transfers on peripherals are enabled z Conditional Block Transfer Trigger (CBLOCK): conditional block transfers on peripherals are enabled z Channel Suspend Operation (SUSPEND): suspend a channel operation z Channel Resume Operation (RESUME): resume a suspended channel operation Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 286 z Skip Next Block Suspend Action (SSKIP): skip the next block suspend transfer condition Writing a one to the Channel Control B Event Input Enable bit (CHCTRLB.EVIE) enables the corresponding action on input event. Writing a zero to this bit disables the corresponding action on input event. Note that several actions can be enabled for incoming events. If several events are connected to the peripheral, any enabled action will be taken for any of the incoming events. For further details on event input actions, refer to "Event Input Actions" on page 281. Refer to the Event System chapter for details on configuring the event system. 18.6.7 Sleep Mode Operation In standby sleep mode, the DMAC will be internally disabled, but maintains its current configuration. 18.6.8 Synchronization Not applicable. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 287 18.7 Register Summary Table 18-1. DMAC Register Summary Offset 0x00 0x01 0x02 0x03 Name CTRL CRCCTRL Bit Pos. 7:0 15:8 CRCDATAIN[7:0] 23:16 CRCDATAIN[23:16] 0x07 31:24 CRCDATAIN[31:24] 0x08 7:0 CRCCHKSUM[7:0] 0x0B 15:8 CRCCHKSUM[15:8] 23:16 CRCCHKSUM[23:16] 31:24 CRCCHKSUM[31:24] 0x0C CRCSTATUS 7:0 0x0D DBGCTRL 7:0 0x0E QOSCTRL 7:0 0x0F Reserved 0x10 7:0 0x11 15:8 0x12 SWTRIGCTRL LVLEN0 CRCSRC[5:0] CRCDATAIN[15:8] CRCCHKSUM LVLEN1 15:8 7:0 0x09 LVLEN2 CRCPOLY[1:0] 15:8 0x0A SWRST LVLEN3 0x05 CRCDATAIN DMAENABLE 7:0 0x04 0x06 CRCENABLE CRCBEATSIZE[1:0] CRCZERO DBGRUN DQOS SWTRIG7 SWTRIG6 SWTRIG5 FQOS SWTRIG4 WRQOS SWTRIG3 SWTRIG2 SWTRIG1 SWTRIG0 SWTRIG11 SWTRIG10 SWTRIG9 SWTRIG8 23:16 0x13 31:24 0x14 7:0 RRLVLEN0 LVLPRI0[3:0] 15:8 RRLVLEN1 LVLPRI1[3:0] 23:16 RRLVLEN2 LVLPRI2[3:0] 31:24 RRLVLEN3 LVLPRI3[3:0] 0x15 0x16 PRICTRL0 0x17 0x18 ... 0x1F 0x20 0x21 Reserved INTPEND 0x22 Reserved 0x23 Reserved 0x24 0x25 0x26 7:0 15:8 PEND BUSY FERR 7:0 CHINT7 CHINT6 CHINT5 CHINT4 SUSP TCMPL TERR CHINT3 CHINT2 CHINT1 CHINT0 CHINT11 CHINT10 CHINT9 CHINT8 BUSYCH3 BUSYCH2 BUSYCH1 BUSYCH0 BUSYCH11 BUSYCH10 BUSYCH9 BUSYCH8 23:16 31:24 0x28 7:0 0x29 15:8 0x2B ID[3:0] 15:8 INTSTATUS 0x27 0x2A CRCBUSY BUSYCH BUSYCH7 BUSYCH6 BUSYCH5 BUSYCH4 23:16 31:24 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 288 Offset Name Bit Pos. 0x2C 7:0 0x2D 15:8 0x2E PENDCH 0x2F PENDCH7 PENDCH6 PENDCH5 PENDCH4 PENDCH3 PENDCH2 PENDCH1 PENDCH0 PENDCH11 PENDCH10 PENDCH9 PENDCH8 LVLEX3 LVLEX2 LVLEX1 LVLEX0 ENABLE SWRST 23:16 31:24 0x30 7:0 0x31 15:8 ACTIVE ABUSY ID[4:0] 0x32 23:16 BTCNT[7:0] 0x33 31:24 BTCNT[15:8] 0x34 7:0 BASEADDR[7:0] 0x35 15:8 BASEADDR[15:8] 0x36 BASEADDR 23:16 BASEADDR[23:16] 0x37 31:24 BASEADDR[31:24] 0x38 7:0 WRBADDR[7:0] 0x39 0x3A WRBADDR 0x3B 0x3C ... 0x3E 15:8 WRBADDR[15:8] 23:16 WRBADDR[23:16] 31:24 WRBADDR[31:24] Reserved 0x3F CHID 7:0 0x40 CHCTRLA 7:0 0x41 ... 0x43 Reserved 0x44 7:0 0x45 15:8 0x46 CHCTRLB 0x47 23:16 ID[3:0] LVL[1:0] EVOE EVIE EVACT[2:0] TRIGSRC[5:0] TRIGACT[1:0] 31:24 0x48 ... 0x4B Reserved CMD[1:0] 0x4C CHINTENCLR 7:0 SUSP TCMPL TERR 0x4D CHINTENSET 7:0 SUSP TCMPL TERR 0x4E CHINTFLAG 7:0 SUSP TCMPL TERR 0x4F CHSTATUS 7:0 FERR BUSY PEND Table 18-2. DMAC SRAM Register Summary - Descriptor/Write-Back Memory Section Offset 0x00 0x01 0x02 0x03 Name BTCTRL BTCNT Bit Pos. 7:0 15:8 BLOCKACT[1:0] STEPSIZE[2:0] STEPSEL DSTINC 7:0 BTCNT[7:0] 15:8 BTCNT[15:8] EVOSEL[1:0] SRCINC VALID BEATSIZE[1:0] Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 289 Offset Name Bit Pos. 0x04 7:0 SRCADDR[7:0] 0x05 15:8 SRCADDR[15:8] 23:16 SRCADDR[23:16] 31:24 SRCADDR[31:24] 0x06 SRCADDR 0x07 0x08 7:0 DSTADDR[7:0] 0x09 15:8 DSTADDR[15:8] 0x0A DSTADDR 23:16 DSTADDR[23:16] 0x0B 31:24 DSTADDR[31:24] 0x0C 7:0 DESCADDR[7:0] 0x0D 0x0E 0x0F DESCADDR 15:8 DESCADDR[15:8] 23:16 DESCADDR[23:16] 31:24 DESCADDR[31:24] Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 290 18.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protected property in each individual register description. Please refer to "Register Access Protection" on page 269 for details. Some registers are enable-protected, meaning they can only be written when the DMAC is disabled. Enable-protection is denoted by the Enable-Protected property in each individual register description. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 291 18.8.1 DMAC Registers 18.8.1.1 Control Name: CTRL Offset: 0x00 Reset: 0x0000 Property: Enable-Protected, Write-Protected Bit 15 14 13 12 11 10 9 8 LVLEN3 LVLEN2 LVLEN1 LVLEN0 Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CRCENABLE DMAENABLE SWRST Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 15:12 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 11:8 - LVLENx [x=3..0]: Priority Level x Enable 0: Transfer requests for Priority level x will not be handled. 1: Transfer requests for Priority level x will be handled. When this bit is set, all requests with the corresponding level will be fed into the arbiter block. When cleared, all requests with the corresponding level will be ignored. For details on arbitration schemes, refer to "Arbitration" on page 274 section. These bits are not enable-protected. z Bits 7:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 2 - CRCENABLE: CRC Enable 0: The CRC module is disabled. 1: The CRC module is enabled. Writing a zero to this bit will disable the CRC module if the CRC Status Busy bit in the CRC Status register (CRCSTATUS.CRCBUSY) is zero. If the CRCSTATUS.CRCBUSY is one, the write will be ignored and the CRC module will not be disabled. Writing a one to this bit will enable the CRC module. This bit is not enable-protected. z Bit 1 - DMAENABLE: DMA Enable 0: The peripheral is disabled. 1: The peripheral is enabled. Writing a zero to this bit during an ongoing transfer, the bit will not be cleared until the internal data transfer buffer is empty and the DMA transfer is aborted. The internal data transfer buffer will be empty once the ongoing burst transfer is completed. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 292 Writing a one to this bit will enable the DMA module. This bit is not enable-protected. z Bit 0 - SWRST: Software Reset 0: There is no reset operation ongoing. 1: The reset operation is ongoing. Writing a zero to this bit has no effect. Writing a one to this bit when both the DMAC and the CRC module are disabled (DMAENABLE and CRCENABLE is zero), resets all registers in the DMAC, except DBGCTRL, to their initial state If either the DMAC or CRC module is enabled, the reset request will be ignored and the DMAC will return an access error. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 293 18.8.1.2 CRC Control Name: CRCCTRL Offset: 0x02 Reset: 0x0000 Property: Enable-Protected, Write-Protected Bit 15 14 13 12 11 10 9 8 CRCSRC[5:0] Access R R R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CRCPOLY[1:0] CRCBEATSIZE[1:0] Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 15:14 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 13:8 - CRCSRC[5:0]: CRC Input Source These bits select the input source for generating the CRC, as shown in Table 18-3. The selected source is locked until either the CRC generation is completed or the CRC module is disabled. This means the CRCSRC cannot be modified when the CRC operation is ongoing. The lock is signaled by the CRCBUSY status bit. CRC generation complete is generated and signaled from the selected source when used with the DMA channel. Table 18-3. CRC Input Source CRCSRC[5:0] Name 0x0 NOACT 0x1 IO 0x2-0x1F 0x20-0x3F Description No action I/O interface Reserved CHN DMA channel n z Bits 7:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 3:2 - CRCPOLY[1:0]: CRC Polynomial Type These bits select the CRC polynomial type, as shown in Table 18-4. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 294 Table 18-4. CRC Polynomial Type CRCPOLY[1:0] Name 0x0 CRC16 CRC-16 (CRC-CCITT) 0x1 CRC32 CRC32 (IEEE 802.3) 0x2-0x3 z Description Reserved Bits 1:0 - CRCBEATSIZE[1:0]: CRC Beat Size These bits define the size of the data transfer for each bus access when the CRC is used with I/O interface, as shown in Table 18-5. Table 18-5. CRC Beat Size CRCBEATSIZE[1:0] Name 0x0 BYTE 0x1 HWORD 0x2 WORD 0x3 Description Byte bus access Half-word bus access Word bus access Reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 295 18.8.1.3 CRC Data Input Name: CRCDATAIN Offset: 0x04 Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 CRCDATAIN[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 CRCDATAIN[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 CRCDATAIN[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CRCDATAIN[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 31:0 - CRCDATAIN[31:0]: CRC Data Input These bits store the data for which the CRC checksum is computed. After the CRCDATAIN register has been written, the number of cycles for the new CRC checksum to be ready is dependent of the configuration of the CRC Beat Size bit group in the CRC Control register(CRCCTRL.CRCBEATSIZE). Each byte needs one clock cycle to be calculated. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 296 18.8.1.4 CRC Checksum The CRCCHKSUM represents the 16- or 32-bit checksum value and the generated CRC. Name: CRCCHKSUM Offset: 0x08 Reset: 0x00000000 Property: Enable-Protected, Write-Protected Bit 31 30 29 28 27 26 25 24 CRCCHKSUM[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 CRCCHKSUM[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 CRCCHKSUM[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CRCCHKSUM[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 31:0 - CRCCHKSUM[31:0]: CRC Checksum These bits store the generated CRC result. The 16 MSB bits are always read zero when CRC-16 is enabled. These bits should only be read when CRC Module Busy bit in the CRC Status register (CRCSTATUS.BUSY) is zero. If CRC-16 is selected and CRCSTATUS.BUSY is zero (CRC generation is completed), this bit group will contain a valid checksum. If CRC-32 is selected and CRCSTATUS.BUSY is zero (CRC generation is completed), this bit group will contain a valid reversed checksum. Bit 31 is swapped with bit 0, bit 30 with bit 1, etc. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 297 18.8.1.5 CRC Status Name: CRCSTATUS Offset: 0x0C Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 CRCZERO CRCBUSY Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 1 - CRCZERO: CRC Zero This bit is cleared when a new CRC source is selected. This bit is set when the CRC generation is complete and the CRC Checksum is zero. z Bit 0 - CRCBUSY: CRC Module Busy When used with an I/O interface (CRCCTRL.CRCSRC is 0x1), this bit is cleared by writing a one to it. When used with an I/O interface (CRCCTRL.CRCSRC is 0x1), this bit is set when the CRC Data Input (CRCDATAIN) register is written. When used with a DMA channel (CRCCTRL.CRCSRC is 0x20 to 0x3F), this bit is cleared when the corresponding DMA channel is disabled. When used with a DMA channel (CRCCTRL.CRCSRC is 0x20 to 0x3F), this bit is set when the corresponding DMA channel is enabled. Writing a zero to this bit has no effect. When used with an I/O interface(CRCCTRL.CRCSRC is 0x1), writing a one to this bit will clear the CRC Module Busy bit. When used with a DMA channel, writing a one to this bit has no effect. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 298 18.8.1.6 Debug Control Name: DBGCTRL Offset: 0x0D Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 DBGRUN Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:1 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 0 - DBGRUN: Debug Run This bit is not reset by a software reset. This bit controls the functionality when the CPU is halted by an external debugger. 0: The DMAC is halted when the CPU is halted by an external debugger. 1: The DMAC continues normal operation when the CPU is halted by an external debugger. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 299 18.8.1.7 QOS Control Name: QOSCTRL Offset: 0x0E Reset: 0x15 Property: Enable-Protected, Write-Protected Bit 7 6 5 4 3 DQOS[1:0] 2 1 FQOS[1:0] 0 WBQOS[1:0] Access R R R/W R/W R/W R/W R/W R/W Reset 0 0 0 1 0 1 0 1 z Bits 7:6 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 5:4 - DQOS[1:0]: DATA Quality of Service These bits define the SRAM quality of service of the DMAC DATA master. Refer to "SRAM Quality of Service" on page 34. z Bits 3:2 - FQOS[1:0]: Fetch Quality of Service These bits define the SRAM quality of service of the DMAC Fetch master. Refer to "SRAM Quality of Service" on page 34. z Bits 1:0 - WBQOS[1:0]: WB Quality of Service These bits define the SRAM quality of service of the DMAC WB master. Refer to "SRAM Quality of Service" on page 34. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 300 18.8.1.8 Software Trigger Control Name: SWTRIGCTRL Offset: 0x10 Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 SWTRIG11 SWTRIG10 SWTRIG9 SWTRIG8 Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SWTRIG7 SWTRIG6 SWTRIG5 SWTRIG4 SWTRIG3 SWTRIG2 SWTRIG1 SWTRIG0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Access Reset z Bits 31:12 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 11:0 - SWTRIGx [x=11..0]: Channel x Software Trigger This bit is cleared when the Channel Pending bit in the Channel Status register (CHSTATUS.PEND) for the corresponding channel is set, or by writing a one to it. This bit is set if CHSTATUS.PEND is already one, when writing a one to this bit. Writing a zero to this bit will clear the bit. Writing a one to this bit will generate a DMA software trigger on channel x, if CHSTATUS.PEND is zero for channel x. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 301 18.8.1.9 Priority Control 0 Name: PRICTRL0 Offset: 0x14 Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 RRLVLEN3 Access 25 24 LVLPRI3[3:0] R/W R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 RRLVLEN2 Access LVLPRI2[3:0] R/W R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 RRLVLEN1 Access LVLPRI1[3:0] R/W R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RRLVLEN0 Access Reset z LVLPRI0[3:0] R/W R R R R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 31 - RRLVLEN3: Level 3 Round-Robin Scheduling Enable 0: Static scheduling scheme for channels with level 3 priority. 1: Round-robin scheduling scheme for channels with level 3 priority. For details on scheduling schemes, refer to "Arbitration" on page 274. z Bits 30:28 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 27:24 - LVLPRI3[3:0]: Level 3 Channel Priority Number When round-robin arbitration is enabled (PRICTRL0.RRLVLEN3 is one) for priority level 3, this register holds the channel number of the last DMA channel being granted access as the active channel with priority level 3. When static arbitration is enabled (PRICTRL0.RRLVLEN3 is zero) for priority level 3, and the value of this bit group is non-zero, it will not affect the static priority scheme. If the value of this bit group is x, channel x will have the highest priority. The priority will decrease as the channel number increases from x to n, where n is the maximum number of channels. Channel n has higher priority than channel 0, and the priority will continue to decrease from channel 0 to channel (x-1). This bit group is not reset when round-robin scheduling gets disabled (PRICTRL0.RRLVLEN3 written to zero). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 302 z Bit 23 - RRLVLEN2: Level 2 Round-Robin Scheduling Enable 0: Static scheduling scheme for channels with level 2 priority. 1: Round-robin scheduling scheme for channels with level 2 priority. For details on scheduling schemes, refer to "Arbitration" on page 274. z Bits 22:20 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 19:16 - LVLPRI2[3:0]: Level 2 Channel Priority Number When round-robin arbitration is enabled (PRICTRL0.RRLVLEN2 is one) for priority level 2, this register holds the channel number of the last DMA channel being granted access as the active channel with priority level 2. When static arbitration is enabled (PRICTRL0.RRLVLEN2 is zero) for priority level 2, and the value of this bit group is non-zero, it will not affect the static priority scheme. If the value of this bit group is x, channel x will have the highest priority. The priority will decrease as the channel number increases from x to n, where n is the maximum number of channels. Channel n has higher priority than channel 0, and the priority will continue to decrease from channel 0 to channel (x-1). This bit group is not reset when round-robin scheduling gets disabled (PRICTRL0.RRLVLEN2 written to zero). z Bit 15 - RRLVLEN1: Level 1 Round-Robin Scheduling Enable 0: Static scheduling scheme for channels with level 1 priority. 1: Round-robin scheduling scheme for channels with level 1 priority. For details on scheduling schemes, refer to "Arbitration" on page 274. z Bits 14:12 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 11:8 - LVLPRI1[3:0]: Level 1 Channel Priority Number When round-robin arbitration is enabled (PRICTRL0.RRLVLEN1 is one) for priority level 1, this register holds the channel number of the last DMA channel being granted access as the active channel with priority level 1. When static arbitration is enabled (PRICTRL0.RRLVLEN1 is zero) for priority level 1, and the value of this bit group is non-zero, it will not affect the static priority scheme. If the value of this bit group is x, channel x will have the highest priority. The priority will decrease as the channel number increases from x to n, where n is the maximum number of channels. Channel n has higher priority than channel 0, and the priority will continue to decrease from channel 0 to channel (x-1). This bit group is not reset when round-robin scheduling gets disabled (PRICTRL0.RRLVLEN1 written to zero). z Bit 7 - RRLVLEN0: Level 0 Round-Robin Scheduling Enable 0: Static scheduling scheme for channels with level 0 priority. 1: Round-robin scheduling scheme for channels with level 0 priority. For details on scheduling schemes, refer to "Arbitration" on page 274. z Bits 6:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 3:0 - LVLPRI0[3:0]: Level 0 Channel Priority Number When round-robin arbitration is enabled (PRICTRL0.RRLVLEN0 is one) for priority level 0, this register holds the channel number of the last DMA channel being granted access as the active channel with priority level 0. When static arbitration is enabled (PRICTRL0.RRLVLEN0 is zero) for priority level 0, and the value of this bit group is non-zero, it will not affect the static priority scheme. If the value of this bit group is x, channel x will have the highest priority. The priority will decrease as the channel number increases from x to n, where n is the maxi- Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 303 mum number of channels. Channel n has higher priority than channel 0, and the priority will continue to decrease from channel 0 to channel (x-1). This bit group is not reset when round-robin scheduling gets disabled (PRICTRL0.RRLVLEN0 written to zero). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 304 18.8.1.10 Interrupt Pending This register allows the user to identify the lowest DMA channel with pending interrupt. Name: INTPEND Offset: 0x20 Reset: 0x0000 Property: - Bit 15 14 13 12 PEND BUSY FERR Access R R R R Reset 0 0 0 Bit 7 6 5 11 10 9 8 SUSP TCMPL TERR R R/W R/W R/W 0 0 0 0 0 4 3 2 1 0 ID[3:0] Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bit 15 - PEND: Pending This bit is read one when the channel selected by Channel ID field (ID) is pending. z Bit 14 - BUSY: Busy This bit is read one when the channel selected by Channel ID field (ID) is busy. z Bit 13 - FERR: Fetch Error This bit is read one when the channel selected by Channel ID field (ID) fetched an invalid descriptor. z Bits 12:11 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 10 - SUSP: Channel Suspend This bit is read one when the channel selected by Channel ID field (ID) has pending Suspend interrupt. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Channel ID (ID) Suspend interrupt flag. z Bit 9 - TCMPL: Transfer Complete This bit is read one when the channel selected by Channel ID field (ID) has pending Transfer Complete interrupt. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Channel ID (ID) Transfer Complete interrupt flag. z Bit 8 - TERR: Transfer Error This bit is read one when the channel selected by Channel ID field (ID) has pending Transfer Error interrupt. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Channel ID (ID) Transfer Error interrupt flag. z Bits 7:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 305 z Bits 3:0 - ID[3:0]: Channel ID These bits store the lowest channel number with pending interrupts. The number is valid if Suspend (SUSP), Transfer Complete (TCMPL) or Transfer Error (TERR) bits are set. The Channel ID field is refreshed when a new channel (with channel number less than the current one) with pending interrupts is detected, or when the application clears the corresponding channel interrupt sources. When no pending channels interrupts are available, these bits will always return zero value when read. When the bits are written, indirect access to the corresponding Channel Interrupt Flag register is enabled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 306 18.8.1.11 Interrupt Status Name: INTSTATUS Offset: 0x24 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 CHINT11 CHINT10 CHINT9 CHINT8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CHINT7 CHINT6 CHINT5 CHINT4 CHINT3 CHINT2 CHINT1 CHINT0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 31:12 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 11:0 - CHINTx [x=11..0]: Channel x Pending Interrupt This bit is set when Channel x has pending interrupt. This bit is cleared when the corresponding Channel x interrupts are disabled or the interrupts sources are cleared. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 307 18.8.1.12 Busy Channels Name: BUSYCH Offset: 0x28 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 BUSYCH11 BUSYCH10 BUSYCH9 BUSYCH8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BUSYCH7 BUSYCH6 BUSYCH5 BUSYCH4 BUSYCH3 BUSYCH2 BUSYCH1 BUSYCH0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 31:12 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 11:0 - BUSYCHx [x=11..0]: Busy Channel x This bit is cleared when the channel trigger action for DMA channel x is complete, when a bus error for DMA channel x is detected, or when DMA channel x is disabled. This bit is set when DMA channel x starts a DMA transfer. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 308 18.8.1.13 Pending Channels Name: PENDCH Offset: 0x2C Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 PENDCH11 PENDCH10 PENDCH9 PENDCH8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PENDCH7 PENDCH6 PENDCH5 PENDCH4 PENDCH3 PENDCH2 PENDCH1 PENDCH0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 31:12 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 11:0 - PENDCHx [x=11..0]: Pending Channel x This bit is cleared when trigger execution defined by channel trigger action settings for DMA channel x is started, when a bus error for DMA channel x is detected or when DMA channel x is disabled. For details on trigger action settings, refer to Table 18-7. This bit is set when a transfer is pending on DMA channel x. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 309 18.8.1.14 Active Channel and Levels Name: ACTIVE Offset: 0x30 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 BTCNT[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 BTCNT[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 ABUSY ID[4:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 LVLEX3 LVLEX2 LVLEX1 LVLEX0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 31:16 - BTCNT[15:0]: Active Channel Block Transfer Count These bits hold the 16-bit block transfer count of the ongoing transfer. This value is stored in the active channel and written back in the corresponding Write-Back channel memory location when the arbiter grants a new channel access. The value is valid only when the active channel active busy flag (ABUSY) is set. z Bit 15 - ABUSY: Active Channel Busy This bit is cleared when the active transfer count is written back in the Write-Back memory section. This flag is set when the next descriptor transfer count is read from the Write-Back memory section. z Bits 14:13 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 12:8 - ID[4:0]: Active Channel ID These bits hold the channel index currently stored in the active channel registers. The value is updated each time the arbiter grants a new channel transfer access request. z Bits 7:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 310 z Bits 3:0 - LVLEXx [x=3..0]: Level x Channel Trigger Request Executing This bit is set when a level-x channel trigger request is executing or pending. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 311 18.8.1.15 Descriptor Memory Section Base Address Name: BASEADDR Offset: 0x34 Reset: 0x00000000 Property: Enable-Protected, Write-Protected Bit 31 30 29 28 27 26 25 24 BASEADDR[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 BASEADDR[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 BASEADDR[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BASEADDR[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 31:0 - BASEADDR[31:0]: Descriptor Memory Base Address These bits store the Descriptor memory section base address. The value must be 128-bit aligned. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 312 18.8.1.16 Write-Back Memory Section Base Address Name: WRBADDR Offset: 0x38 Reset: 0x00000000 Property: Enable-Protected, Write-Protected Bit 31 30 29 28 27 26 25 24 WRBADDR[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 WRBADDR[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 WRBADDR[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 WRBADDR[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 31:0 - WRBADDR[31:0]: Write-Back Memory Base Address These bits store the Write-Back memory base address. The value must be 128-bit aligned. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 313 18.8.1.17 Channel ID Name: CHID Offset: 0x3F Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 ID[3:0] Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 3:0 - ID[3:0]: Channel ID These bits define the channel number that will be accessed. Before reading or writing a channel register, the channel ID bit group must be written first. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 314 18.8.1.18 Channel Control A Name: CHCTRLA Offset: 0x40 Reset: 0x00 Property: Enable-Protected, Write-Protected Bit 7 6 5 4 3 2 1 0 ENABLE SWRST Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 1 - ENABLE: Channel Enable 0: DMA channel is disabled. 1: DMA channel is enabled. Writing a zero to this bit during an ongoing transfer, the bit will not be cleared until the internal data transfer buffer is empty and the DMA transfer is aborted. The internal data transfer buffer will be empty once the ongoing burst transfer is completed. Writing a one to this bit will enable the DMA channel. This bit is not enable-protected. z Bit 0 - SWRST: Channel Software Reset 0: There is no reset operation ongoing. 1: The reset operation is ongoing. Writing a zero to this bit has no effect. Writing a one to this bit resets the channel registers to their initial state. The bit can be set when the channel is disabled (ENABLE = 0). Writing a one to this bit will be ignored as long as the channel is enabled (ENABLE = 1). This bit is automatically cleared when the reset is completed. Writing a one to this bit when the corresponding DMA channel is disabled (ENABLE is zero), resets all registers for the corresponding DMA channel to their initial state If the corresponding DMA channel is enabled, the reset request will be ignored. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 315 18.8.1.19 Channel Control B Name: CHCTRLB Offset: 0x44 Reset: 0x00000000 Property: Enable-Protected, Write-Protected Bit 31 30 29 28 27 26 25 24 CMD[1:0] Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 TRIGACT[1:0] Access R/W R/W R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 TRIGSRC[5:0] Access R R R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 EVOE EVIE LVL[1:0] EVACT[2:0] Access R R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 31:26 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 25:24 - CMD[1:0]: Software Command These bits define the software commands, as shown in Table 18-6. These bits are not enable-protected. Table 18-6. Software Command CMD[1:0] Name 0x0 NOACT 0x1 SUSPEND Channel suspend operation 0x2 RESUME Channel resume operation 0x3 Description No action Reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 316 z Bits 23:22 - TRIGACT[1:0]: Trigger Action These bits define the trigger action used for a transfer, as shown in Table 18-7. Table 18-7. Trigger Action TRIGACT[1:0] Name 0x0 BLOCK Description One trigger required for each block transfer 0x1 Reserved 0x2 BEAT One trigger required for each beat transfer 0x3 TRANSACTION One trigger required for each transaction z Bits 21:14 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 13:8 - TRIGSRC[5:0]: Peripheral Trigger Source These bits define the peripheral trigger which is source of the transfer. For details on trigger selection and trigger modes, refer to "Transfer Triggers and Actions" on page 276 and Table 18-7. Table 18-8. Peripheral Trigger Source Value Name Description 0x00 DISABLE 0x01 SERCOM0 RX SERCOM0 RX Trigger 0x02 SERCOM0 TX SERCOM0 TX Trigger 0x03 SERCOM1 RX SERCOM1 RX Trigger 0x04 SERCOM1 TX SERCOM1 TX Trigger 0x05 SERCOM2 RX SERCOM2 RX Trigger 0x06 SERCOM2 TX SERCOM2 TX Trigger 0x07 SERCOM3 RX SERCOM3 RX Trigger 0x08 SERCOM3 TX SERCOM3 TX Trigger 0x09 SERCOM4 RX SERCOM4 RX Trigger 0x0A SERCOM4 TX SERCOM4 TX Trigger 0x0B SERCOM5 RX SERCOM5 RX Trigger 0x0C SERCOM5 TX SERCOM5 TX Trigger 0x0D TCC0 OVF TCC0 Overflow Trigger 0x0E TCC0 MC0 TCC0 Match/Compare 0 Trigger 0x0F TCC0 MC1 TCC0 Match/Compare 1 Trigger 0x10 TCC0 MC2 TCC0 Match/Compare 2 Trigger 0x11 TCC0 MC3 TCC0 Match/Compare 3 Trigger 0x12 TCC1 OVF TCC1 Overflow Trigger Only software/event triggers Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 317 Table 18-8. Peripheral Trigger Source (Continued) Value Name Description 0x13 TCC1 MC0 TCC1 Match/Compare 0 Trigger 0x14 TCC1 MC1 TCC1 Match/Compare 1 Trigger 0x15 TCC2 OVF TCC2 Overflow Trigger 0x16 TCC2 MC0 TCC2 Match/Compare 0 Trigger 0x17 TCC2 MC1 TCC2 Match/Compare 1 Trigger 0x18 TC3 OVF TC3 Overflow Trigger 0x19 TC3 MC0 TC3 Match/Compare 0 Trigger 0x1A TC3 MC1 TC3 Match/Compare 1 Trigger 0x1B TC4 OVF TC4 Overflow Trigger 0x1C TC4 MC0 TC4 Match/Compare 0 Trigger 0x1D TC4 MC1 TC4 Match/Compare 1 Trigger 0x1E TC5 OVF TC5 Overflow Trigger 0x1F TC5 MC0 TC5 Match/Compare 0 Trigger 0x20 TC5 MC1 TC5 Match/Compare 1 Trigger 0x21 Reserved 0x22 Reserved 0x23 Reserved 0x24 Reserved 0x25 Reserved 0x26 Reserved 0x27 0x28 - 0x2C ADC RESRDY ADC Result Ready Trigger Reserved z Bit 7 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 6:5 - LVL[1:0]: Channel Arbitration Level These bits define the arbitration level used for the DMA channel. The available levels are shown in Table 18-9, where a high level has priority over a low level. For further details on arbitration schemes, refer to "Arbitration" on page 274. These bits are not enable-protected. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 318 Table 18-9. Channel Arbitration Level LVL[1:0] Name 0x0 LVL0 Channel Priority Level 0 0x1 LVL1 Channel Priority Level 1 0x2 LVL2 Channel Priority Level 2 0x3 LVL3 Channel Priority Level 3 0x4-0x7 z Description Reserved Bit 4 - EVOE: Channel Event Output Enable This bit indicates if the Channel event generation is enabled. The event will be generated for every condition defined in the descriptor Event Output Selection (BTCTRL.EVOSEL). 0: Channel event generation is disabled. 1: Channel event generation is enabled. This bit is available only on channels with event output support. Refer to Table 22-6 and Table 22-4 for details. z Bit 3 - EVIE: Channel Event Input Enable 0: Channel event action will not be executed on any incoming event. 1: Channel event action will be executed on any incoming event. This bit is available only on channels with event input support. Refer to Table 22-6 and Table 22-4 for details. z Bits 2:0 - EVACT[2:0]: Event Input Action These bits define the event input action, as shown in Table 18-10. The action is executed only if the corresponding EVIE bit in CHCTRLB register of the channel is set. For details on event actions, refer to "Event Input Actions" on page 281. These bits are available only for channels with event input support. Refer to Table 22-6 and Table 22-4 for details. Table 18-10. Event Input Action EVACT[2:0] Name 0x0 NOACT 0x1 TRIG 0x2 CTRIG Conditional transfer trigger 0x3 CBLOCK Conditional block transfer 0x4 SUSPEND Channel suspend operation 0x5 RESUME Channel resume operation 0x6 SSKIP 0x7 Description No action Transfer and periodic transfer trigger Skip next block suspend action Reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 319 18.8.1.20 Channel Interrupt Enable Clear This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Channel Interrupt Enable Set (CHINTENSET) register. Name: CHINTENCLR Offset: 0x4C Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 SUSP TCMPL TERR Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 2 - SUSP: Channel Suspend Interrupt Enable 0: The Channel Suspend interrupt is disabled. 1: The Channel Suspend interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Channel Suspend Interrupt Enable bit, which disables the Channel Suspend interrupt. z Bit 1 - TCMPL: Transfer Complete Interrupt Enable 0: The Channel Transfer Complete interrupt is disabled. When block action is set to none, the TCMPL flag will not be set when a block transfer is completed. 1: The Channel Transfer Complete interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Channel Transfer Complete Interrupt Enable bit, which disables the Channel Transfer Complete interrupt. z Bit 0 - TERR: Transfer Error Interrupt Enable 0: The Channel Transfer Error interrupt is disabled. 1: The Channel Transfer Error interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Channel Transfer Error Interrupt Enable bit, which disables the Channel Transfer Error interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 320 18.8.1.21 Channel Interrupt Enable Set This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Channel Interrupt Enable Clear (CHINTENCLR) register. Name: CHINTENSET Offset: 0x4D Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 SUSP TCMPL TERR Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 2 - SUSP: Channel Suspend Interrupt Enable 0: The Channel Suspend interrupt is disabled. 1: The Channel Suspend interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Channel Suspend Interrupt Enable bit, which enables the Channel Suspend interrupt. z Bit 1 - TCMPL: Transfer Complete Interrupt Enable 0: The Channel Transfer Complete interrupt is disabled. 1: The Channel Transfer Complete interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Channel Transfer Complete Interrupt Enable bit, which enables the Channel Transfer Complete interrupt. z Bit 0 - TERR: Transfer Error Interrupt Enable 0: The Channel Transfer Error interrupt is disabled. 1: The Channel Transfer Error interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Channel Transfer Error Interrupt Enable bit, which enables the Channel Transfer Error interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 321 18.8.1.22 Channel Interrupt Flag Status and Clear Name: CHINTFLAG Offset: 0x4E Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 SUSP TCMPL TERR Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 2 - SUSP: Channel Suspend This flag is cleared by writing a one to it. This bit is set when a block transfer with suspend block action is completed, when a software suspend command is executed, when a suspend event is received or when an invalid descriptor is fetched by the DMA. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Channel Suspend interrupt flag for the corresponding channel. For details on available software commands, refer to Table 18-6. For details on available event input actions, refer to Table 18-10. For details on available block actions, refer to Table 18-14. z Bit 1 - TCMPL: Transfer Complete This flag is cleared by writing a one to it. This flag is set when a block transfer is completed and the corresponding interrupt block action is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Transfer Complete interrupt flag for the corresponding channel. z Bit 0 - TERR: Transfer Error This flag is cleared by writing a one to it. This flag is set when a bus error is detected during a beat transfer or when the DMAC fetches an invalid descriptor. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Transfer Error interrupt flag for the corresponding channel. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 322 18.8.1.23 Channel Status Name: CHSTATUS Offset: 0x4F Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 FERR BUSY PEND Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 7:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 2 - FERR: Fetch Error This bit is cleared when the software resume command is executed. This bit is set when an invalid descriptor is fetched. z Bit 1 - BUSY: Channel Busy This bit is cleared when the channel trigger action is complete, when a bus error is detected or when the channel is disabled. This bit is set when the DMA channel starts a DMA transfer. z Bit 0 - PEND: Channel Pending This bit is cleared when trigger execution defined by channel trigger action settings is started, when a bus error is detected or when the channel is disabled. For details on trigger action settings, refer to Table 18-7. This bit is set when a transfer is pending on the DMA channel. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 323 18.8.2 DMAC SRAM Registers 18.8.2.1 Block Transfer Control The BTCTRL register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10 Name: BTCTRL Offset: 0x00 Bit 15 14 13 STEPSIZE[2:0] Bit 7 6 12 11 10 STEPSEL DSTINC SRCINC 4 3 2 5 BLOCKACT[1:0] z 9 8 BEATSIZE[1:0] 1 EVOSEL[1:0] 0 VALID Bits 15:13 - STEPSIZE[2:0]: Address Increment Step Size These bits select the address increment step size, as shown in Table 18-11. The setting apply to source or destination address, depending on STEPSEL setting. Table 18-11. Address Increment Step Size z STEPSIZE[2:0] Name Description 0x0 X1 Next ADDR <- ADDR + BEATSIZE * 1 0x1 X2 Next ADDR <- ADDR + BEATSIZE * 2 0x2 X4 Next ADDR <- ADDR + BEATSIZE * 4 0x3 X8 Next ADDR <- ADDR + BEATSIZE * 8 0x4 X16 Next ADDR <- ADDR + BEATSIZE * 16 0x5 X32 Next ADDR <- ADDR + BEATSIZE * 32 0x6 X64 Next ADDR <- ADDR + BEATSIZE * 64 0x7 X128 Next ADDR <- ADDR + BEATSIZE * 128 Bit 12 - STEPSEL: Step Selection This bit selects if source or destination addresses are using the step size settings, according to Table 18-12. Table 18-12. Step Selection z STEPSEL Name Description 0x0 DST Step size settings apply to the destination address 0x1 SRC Step size settings apply to the source address Bit 11 - DSTINC: Destination Address Increment Enable 0: The Destination Address Increment is disabled. 1: The Destination Address Increment is enabled. Writing a zero to this bit will disable the destination address incrementation. The address will be kept fixed during the data transfer. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 324 Writing a one to this bit will enable the destination address incrementation. By default, the destination address is incremented by 1. If the STEPSEL bit is cleared, flexible step-size settings are available in the STEPSIZE register, as shown in Table 18-11. z Bit 10 - SRCINC: Source Address Increment Enable 0: The Source Address Increment is disabled. 1: The Source Address Increment is enabled. Writing a zero to this bit will disable the source address incrementation. The address will be kept fixed during the data transfer. Writing a one to this bit will enable the source address incrementation. By default, the source address is incremented by 1. If the STEPSEL bit is set, flexible step-size settings are available in the STEPSIZE register, as shown in Table 18-11. z Bits 9:8 - BEATSIZE[1:0]: Beat Size These bits define the size of one beat, as shown in Table 18-13. A beat is the size of one data transfer bus access, and the setting apply to both read and write accesses. Table 18-13. Beat Size BEATSIZE[1:0] Name 0x0 BYTE 8-bit access 0x1 HWORD 16-bit access 0x2 WORD 32-bit access 0x3 Description Reserved z Bits 7:5 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 4:3 - BLOCKACT[1:0]: Block Action These bits define what actions the DMAC should take after a block transfer has completed. The available actions are listed in Table 18-14. Table 18-14. Block Action z BLOCKACT[1:0] Name 0x0 NOACT 0x1 INT 0x2 SUSPEND 0x3 BOTH Description No action Channel in normal operation and block interrupt Channel suspend operation is completed Both channel suspend operation and block interrupt Bits 2:1 - EVOSEL[1:0]: Event Output Selection These bits define the event output selection, as shown in Table 18-15. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 325 Table 18-15. Event Output Selection EVOSEL[1:0] Name 0x0 DISABLE 0x1 BLOCK 0x2 0x3 z Description Event generation disabled Event strobe when block transfer complete Reserved BEAT Event strobe when beat transfer complete Bit 0 - VALID: Descriptor Valid 0: The descriptor is not valid. 1: The descriptor is valid. Writing a zero to this bit in the Descriptor or Write-Back memory will suspend the DMA channel operation when fetching the corresponding descriptor. The bit is automatically cleared in the Write-Back memory section when channel is aborted, when an error is detected during the block transfer, or when the block transfer is completed. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 326 18.8.2.2 Block Transfer Count The BTCNT register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10 Name: BTCNT Offset: 0x02 Bit 15 14 13 12 11 10 9 8 3 2 1 0 BTCNT[15:8] Bit 7 6 5 4 BTCNT[7:0] z Bits 15:0 - BTCNT[15:0]: Block Transfer Count This bit group holds the 16-bit block transfer count. During a transfer, the internal counter value is decremented by one after each beat transfer. The internal counter is written to the corresponding write-back memory section for the DMA channel when the DMA channel loses priority, is suspended or gets disabled. The DMA channel can be disabled by a complete transfer, a transfer error or by software. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 327 18.8.2.3 Transfer Source Address The SRCADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10 Name: SRCADDR Offset: 0x04 Bit 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 SRCADDR[31:24] Bit 23 22 21 20 19 SRCADDR[23:16] Bit 15 14 13 12 11 SRCADDR[15:8] Bit 7 6 5 4 3 SRCADDR[7:0] z Bits 31:0 - SRCADDR[31:0]: Transfer Source Address This bit group holds the source address corresponding to the last beat transfer address in the block transfer. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 328 18.8.2.4 Transfer Destination Address The DSTADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10 Name: DSTADDR Offset: 0x08 Bit 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 DSTADDR[31:24] Bit 23 22 21 20 19 DSTADDR[23:16] Bit 15 14 13 12 11 DSTADDR[15:8] Bit 7 6 5 4 3 DSTADDR[7:0] z Bits 31:0 - DSTADDR[31:0]: Transfer Destination Address This bit group holds the destination address corresponding to the last beat transfer address in the block transfer. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 329 18.8.2.5 Next Descriptor Address The DESCADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10 Name: DESCADDR Offset: 0x0C Bit 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 DESCADDR[31:24] Bit 23 22 21 20 19 DESCADDR[23:16] Bit 15 14 13 12 11 DESCADDR[15:8] Bit 7 6 5 4 3 DESCADDR[7:0] z Bits 31:0 - DESCADDR[31:0]: Next Descriptor Address This bit group holds the SRAM address of the next descriptor. The value must be 128-bit aligned. If the value of this SRAM register is 0x00000000, the transaction will be terminated when the DMAC tries to load the next transfer descriptor. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 330 19. EIC - External Interrupt Controller 19.1 Overview The External Interrupt Controller (EIC) allows external pins to be configured as interrupt lines. Each interrupt line can be individually masked and can generate an interrupt on rising, falling or both edges, or on high or low levels. Each external pin has a configurable filter to remove spikes. Each external pin can also be configured to be asynchronous in order to wake up the device from sleep modes where all clocks have been disabled. External pins can also generate an event. A separate non-maskable interrupt (NMI) is also supported. It has properties similar to the other external interrupts, but is connected to the NMI request of the CPU, enabling it to interrupt any other interrupt mode. 19.2 19.3 Features z 15 external pins, plus one non-maskable pin z Dedicated interrupt line for each pin z Individually maskable interrupt lines z Interrupt on rising, falling or both edges z Interrupt on high or low levels z Asynchronous interrupts for sleep modes without clock z Filtering of external pins z Event generation z Configurable wake-up for sleep modes Block Diagram Figure 19-1. EIC Block Diagram FILTENx SENSEx[2:0] intreq_extint[x] Interrupt EXTINTx Filter Edge/Level Detection inwake_extint[x] Wake evt_extint[x] Event NMIFILTEN NMISENSE[2:0] intreq_nmi Interrupt NMI Filter Edge/Level Detection inwake_nmi Wake Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 331 19.4 Signal Description Signal Name Type Description EXTINT[15..1] Digital Input External interrupt pin NMI Digital Input Non-maskable interrupt pin Refer to "I/O Multiplexing and Considerations" on page 12 for details on the pin mapping for this peripheral. One signal can be mapped on several pins. 19.5 Product Dependencies In order to use this EIC, other parts of the system must be configured correctly, as described below. 19.5.1 I/O Lines Using the EIC's I/O lines requires the I/O pins to be configured. Refer to "PORT" on page 373 for details. 19.5.2 Power Management All interrupts are available in all sleep modes, but the EIC can be configured to automatically mask some interrupts in order to prevent device wake-up. The EIC will continue to operate in any sleep mode where the selected source clock is running. The EIC's interrupts can be used to wake up the device from sleep modes. Events connected to the Event System can trigger other operations in the system without exiting sleep modes. Refer to "PM - Power Manager" on page 112 for details on the different sleep modes. 19.5.3 Clocks The EIC bus clock (CLK_EIC_APB) can be enabled and disabled in the Power Manager, and the default state of CLK_EIC_APB can be found in the Peripheral Clock Masking section in "PM - Power Manager" on page 112. A generic clock (GCLK_EIC) is required to clock the peripheral. This clock must be configured and enabled in the Generic Clock Controller before using the peripheral. Refer to "GCLK - Generic Clock Controller" on page 90 for details. This generic clock is asynchronous to the user interface clock (CLK_EIC_APB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. Refer to "Synchronization" on page 336 for further details. 19.5.4 DMA Not applicable. 19.5.5 Interrupts There are two interrupt request lines, one for the external interrupts (EXTINT) and one for non-maskable interrupt (NMI). The EXTINT interrupt request line is connected to the interrupt controller. Using the EIC interrupt requires the interrupt controller to be configured first. Refer to "Nested Vector Interrupt Controller" on page 29 for details. The NMI interrupt request line is also connected to the interrupt controller, but does not require the interrupt to be configured. 19.5.6 Events The events are connected to the Event System. Using the events requires the Event System to be configured first. The External Interrupt Controller generates events as pulses. Refer to "EVSYS - Event System" on page 400 for details. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 332 19.5.7 Debug Operation When the CPU is halted in debug mode, the EIC continues normal operation. If the EIC is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 19.5.8 Register Access Protection All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the following registers: z Interrupt Flag Status and Clear register (INTFLAG - refer to INTFLAG) z Non-Maskable Interrupt Flag Status and Clear register (NMIFLAG - refer to NMIFLAG) Write-protection is denoted by the Write-Protected property in the register description. Write-protection does not apply to accesses through an external debugger. Refer to "PAC - Peripheral Access Controller" on page 36 for details. 19.5.9 Analog Connections Not applicable. 19.6 Functional Description 19.6.1 Principle of Operation The EIC detects edge or level condition to generate interrupts to the CPU Interrupt Controller or events to the Event System. Each external interrupt pin (EXTINT) can be filtered using majority vote filtering, clocked by generic clock GCLK_EIC. 19.6.2 Basic Operation 19.6.2.1 Initialization The EIC must be initialized in the following order: 1. Enable CLK_EIC_APB 2. If edge detection or filtering is required, GCLK_EIC must be enabled 3. Write the EIC configuration registers (EVCTRL, WAKEUP, CONFIGy) 4. Enable the EIC When NMI is used, GCLK_EIC must be enabled after EIC configuration (NMICTRL). 19.6.2.2 Enabling, Disabling and Resetting The EIC is enabled by writing a one to the Enable bit in the Control register (CTRL.ENABLE). The EIC is disabled by writing a zero to CTRL.ENABLE. The EIC is reset by writing a one to the Software Reset bit in the Control register (CTRL.SWRST). All registers in the EIC will be reset to their initial state, and the EIC will be disabled. Refer to CTRL register for details. 19.6.3 External Pin Processing Each external pin can be configured to generate an interrupt/event on edge detection (rising, falling or both edges) or level detection (high or low). The sense of external pins is configured by writing the Interrupt Sense x bits in the Config y register (CONFIGy.SENSEx). The corresponding interrupt flag (INTFLAG.EXTINT[x]) in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition is met (CONFIGy.SENSEx must be different from zero). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 333 When the interrupt has been cleared in edge-sensitive mode, INTFLAG.EXTINT[x] will only be set if a new interrupt condition is met. In level-sensitive mode, when interrupt has been cleared, INTFLAG.EXTINT[x] will be set immediately if the EXTINTx pin still matches the interrupt condition. Each external pin can be filtered by a majority vote filtering, clocked by GCLK_EIC. Filtering is enabled if bit Filter Enable x in the Configuration y register (CONFIGy.FILTENx) is written to one. The majority vote filter samples the external pin three times with GCLK_EIC and outputs the value when two or more samples are equal. Table 19-1. Majority Vote Filter Samples [0, 1, 2] Filter Output [0,0,0] 0 [0,0,1] 0 [0,1,0] 0 [0,1,1] 1 [1,0,0] 0 [1,0,1] 1 [1,1,0] 1 [1,1,1] 1 When an external interrupt is configured for level detection, or if filtering is disabled, detection is made asynchronously, and GCLK_EIC is not required. If filtering or edge detection is enabled, the EIC automatically requests the GCLK_EIC to operate (GCLK_EIC must be enabled in the GCLK module, see "GCLK - Generic Clock Controller" on page 90 for details). If level detection is enabled, GCLK_EIC is not required, but interrupt and events can still be generated. Figure 19-2. Interrupt Detections GCLK_EIC CLK_EIC_APB EXTINTx intreq_extint[x] (level detection / no filter) intreq_extint[x] (level detection / filter) No interrupt intreq_extint[x] (edge detection / no filter) intreq_extint[x] (edge detection / filter) No interrupt clear INTFLAG.EXTINT[x] The detection delay depends on the detection mode. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 334 Table 19-2. Interrupt Latency Detection Mode Latency (Worst Case) Level without filter 3 CLK_EIC_APB periods Level with filter 4 GCLK_EIC periods + 3 CLK_EIC_APB periods Edge without filter 4 GCLK_EIC periods + 3 CLK_EIC_APB periods Edge with filter 6 GCLK_EIC periods + 3 CLK_EIC_APB periods 19.6.4 Additional Features The non-maskable interrupt pin can also generate an interrupt on edge or level detection, but it is configured with the dedicated NMI Control register (NMICTRL - refer to NMICTRL). To select the sense for NMI, write to the NMISENSE bit group in the NMI Control register (NMICTRL.NMISENSE). NMI filtering is enabled by writing a one to the NMI Filter Enable bit (NMICTRL.NMIFILTEN). NMI detection is enabled only by the NMICTRL.NMISENSE value, and the EIC is not required to be enabled. After reset, NMI is configured to no detection mode. When an NMI is detected, the non-maskable interrupt flag in the NMI Flag Status and Clear register is set (NMIFLAG.NMI). NMI interrupt generation is always enabled, and NMIFLAG.NMI generates an interrupt request when set. 19.6.5 DMA Operation Not applicable. 19.6.6 Interrupts The EIC has the following interrupt sources: z External interrupt pin (EXTINTx). This is an asynchronous interrupt if the corresponding WAKEUP register bit is set, and can be used to wake-up the device from any sleep mode. See "Basic Operation" on page 333 z Non-maskable interrupt pin (NMI). This is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. See "Additional Features" on page 335 Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when an interrupt condition occurs (NMIFLAG for NMI). Each interrupt, except NMI, can be individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the EIC is reset. See the INTFLAG register for details on how to clear interrupt flags. The EIC has one common interrupt request line for all the interrupt sources (except the NMI interrupt request line). Refer to "Processor And Architecture" on page 28 for details. The user must read the INTFLAG (or NMIFLAG) register to determine which interrupt condition is present. Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to "Processor And Architecture" on page 28 for details. 19.6.7 Events The EIC can generate the following output events: z External event from pin (EXTINTx). Writing a one to an Event Output Control register (EVCTRLEXTINTEO) enables the corresponding output event. Writing a zero to this bit disables the corresponding output event. Refer to "EVSYS - Event System" on page 400 for details on configuring the Event System. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 335 When the condition on pin EXTINTx matches the configuration in the CONFIGy register, the corresponding event is generated, if enabled. 19.6.8 Sleep Mode Operation In sleep modes, an EXTINTx pin can wake up the device if the corresponding condition matches the configuration in CONFIGy register. Writing a one to a Wake-Up Enable bit (WAKEUP.WAKEUPEN[x]) enables the wake-up from pin EXTINTx. Writing a zero to a Wake-Up Enable bit (WAKEUP.WAKEUPEN[x]) disables the wake-up from pin EXTINTx. Using WAKEUPEN[x]=1 with INTENSET=0 is not recommended. Figure 19-3. Wake-Up Operation Example (High-Level Detection, No Filter, WAKEUPEN[x]=1) CLK_EIC_APB EXTINTx intwake_extint[x] intreq_extint[x] clear INTFLAG.EXTINT[x] return to sleep mode 19.6.9 Synchronization Due to the asynchronicity between CLK_EIC_APB and GCLK_EIC, some registers must be synchronized when accessed. A register can require: z Synchronization when written z Synchronization when read z Synchronization when written and read z No synchronization When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All operations will complete successfully, but the CPU will be stalled, and interrupts will be pending as long as the bus is stalled. The following bits need synchronization when written: z Software Reset bit in the Control register (CTRL.SWRST) z Enable bit in the Control register (CTRL.ENABLE) No register needs synchronization when written. No register needs synchronization when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 336 19.7 Register Summary Table 19-3. Register Summary Offset Name Bit Pos. 0x00 CTRL 7:0 0x01 STATUS 7:0 0x02 NMICTRL 7:0 0x03 NMIFLAG 7:0 ENABLE SWRST SYNCBUSY NMIFILTEN NMISENSE[2:0] NMI 0x04 7:0 EXTINTEO7 EXTINTEO6 EXTINTEO5 EXTINTEO4 EXTINTEO3 EXTINTEO2 EXTINTEO1 EXTINTEO0 0x05 15:8 EXTINTEO15 EXTINTEO14 EXTINTEO13 EXTINTEO12 EXTINTEO11 EXTINTEO10 EXTINTEO9 EXTINTEO8 EXTINTEO17 EXTINTEO16 0x06 EVCTRL 0x07 23:16 31:24 0x08 7:0 EXTINT7 EXTINT6 EXTINT5 EXTINT4 EXTINT3 EXTINT2 EXTINT1 EXTINT0 0x09 15:8 EXTINT15 EXTINT14 EXTINT13 EXTINT12 EXTINT11 EXTINT10 EXTINT9 EXTINT8 EXTINT17 EXTINT16 EXTINT1 EXTINT0 0x0A INTENCLR 23:16 0x0B 31:24 0x0C 7:0 EXTINT7 EXTINT6 EXTINT5 EXTINT4 EXTINT3 EXTINT2 15:8 EXTINT15 EXTINT14 EXTINT13 EXTINT12 EXTINT11 EXTINT10 0x0D 0x0E INTENSET 23:16 0x0F 31:24 0x10 7:0 EXTINT7 EXTINT6 EXTINT5 EXTINT4 EXTINT3 EXTINT2 15:8 EXTINT15 EXTINT14 EXTINT13 EXTINT12 EXTINT11 EXTINT10 0x11 0x12 INTFLAG 0x13 23:16 EXTINT9 EXTINT8 EXTINT17 EXTINT16 EXTINT1 EXTINT0 EXTINT9 EXTINT8 EXTINT17 EXTINT16 31:24 0x14 7:0 WAKEUPEN7 WAKEUPEN6 WAKEUPEN5 WAKEUPEN4 WAKEUPEN3 WAKEUPEN2 WAKEUPEN1 WAKEUPEN0 0x15 15:8 WAKEUPEN15 WAKEUPEN14 WAKEUPEN13 WAKEUPEN12 WAKEUPEN11 WAKEUPEN10 WAKEUPEN9 WAKEUPEN8 WAKEUPEN17 WAKEUPEN16 0x16 WAKEUP 0x17 23:16 31:24 0x18 7:0 FILTEN1 SENSE1[2:0] FILTEN0 SENSE0[2:0] 0x19 15:8 FILTEN3 SENSE3[2:0] FILTEN2 SENSE2[2:0] 23:16 FILTEN5 SENSE5[2:0] FILTEN4 SENSE4[2:0] 31:24 FILTEN7 SENSE7[2:0] FILTEN6 SENSE6[2:0] 0x1A CONFIG0 0x1B 0x1C 7:0 FILTEN9 SENSE9[2:0] FILTEN8 SENSE8[2:0] 0x1D 15:8 FILTEN11 SENSE11[2:0] FILTEN10 SENSE10[2:0] SENSE12[2:0] 0x1E CONFIG1 23:16 FILTEN13 SENSE13[2:0] FILTEN12 0x1F 31:24 FILTEN15 SENSE15[2:0] FILTEN14 SENSE14[2:0] 0x20 7:0 FILTEN25 SENSE25[2:0] FILTEN24 SENSE24[2:0] 0x21 0x22 0x23 CONFIG2 15:8 FILTEN27 SENSE27[2:0] FILTEN26 SENSE26[2:0] 23:16 FILTEN29 SENSE29[2:0] FILTEN28 SENSE28[2:0] 31:24 FILTEN31 SENSE31[2:0] FILTEN30 SENSE30[2:0] Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 337 19.8 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-protected property in each individual register description. Refer to "Register Access Protection" on page 333 for details. Some registers require synchronization when read and/or written. Synchronization is denoted by the Synchronized property in each individual register description. Refer to "Synchronization" on page 336 for details. Some registers are enable-protected, meaning they can be written only when the EIC is disabled. Enable-protection is denoted by the Enabled-Protected property in each individual register description. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 338 19.8.1 Control Name: CTRL Offset: 0x00 Reset: 0x00 Property: Write-Protected, Write-Synchronized Bit 7 6 5 4 3 2 1 0 ENABLE SWRST Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 1 - ENABLE: Enable 0: The EIC is disabled. 1: The EIC is enabled. Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete. z Bit 0 - SWRST: Software Reset 0: There is no ongoing reset operation. 1: The reset operation is ongoing. Writing a zero to this bit has no effect. Writing a one to this bit resets all registers in the EIC to their initial state, and the EIC will be disabled. Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write operation will be discarded. Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete. CTRL.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 339 19.8.2 Status Name: STATUS Offset: 0x01 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 SYNCBUSY Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bit 7 - SYNCBUSY: Synchronization Busy This bit is cleared when the synchronization of registers between the clock domains is complete. This bit is set when the synchronization of registers between clock domains is started. z Bits 6:0 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 340 19.8.3 Non-Maskable Interrupt Control Name: NMICTRL Offset: 0x02 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 NMIFILTEN 1 0 NMISENSE[2:0] Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 3 - NMIFILTEN: Non-Maskable Interrupt Filter Enable 0: NMI filter is disabled. 1: NMI filter is enabled. z Bits 2:0 - NMISENSE[2:0]: Non-Maskable Interrupt Sense These bits define on which edge or level the NMI triggers. Table 19-4. Non-Maskable Interrupt Sense NMISENSE[2:0] Name 0x0 NONE No detection 0x1 RISE Rising-edge detection 0x2 FALL Falling-edge detection 0x3 BOTH Both-edges detection 0x4 HIGH High-level detection 0x5 LOW Low-level detection 0x6-0x7 Description Reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 341 19.8.4 Non-Maskable Interrupt Flag Status and Clear Name: NMIFLAG Offset: 0x03 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 NMI Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:1 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 0 - NMI: Non-Maskable Interrupt This flag is cleared by writing a one to it. This flag is set when the NMI pin matches the NMI sense configuration, and will generate an interrupt request. Writing a zero to this bit has no effect. Writing a one to this bit clears the non-maskable interrupt flag. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 342 19.8.5 Event Control Name: EVCTRL Offset: 0x04 Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 EXTINTEO17 EXTINTEO16 Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 EXTINTEO15 EXTINTEO14 EXTINTEO13 EXTINTEO12 EXTINTEO11 EXTINTEO10 EXTINTEO9 EXTINTEO8 R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 EXTINTEO7 EXTINTEO6 EXTINTEO5 EXTINTEO4 EXTINTEO3 EXTINTEO2 EXTINTEO1 EXTINTEO0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Access Access Reset z Bits 31:18 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 17:0 - EXTINTEOx [x=17..0]: External Interrupt x Event Output Enable These bits indicate whether the event associated with the EXTINTx pin is enabled or not to generated for every detection. 0: Event from pin EXTINTx is disabled. 1: Event from pin EXTINTx is enabled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 343 19.8.6 Interrupt Enable Clear This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Name: INTENCLR Offset: 0x08 Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 EXTINT17 EXTINT16 Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 EXTINT15 EXTINT14 EXTINT13 EXTINT12 EXTINT11 EXTINT10 EXTINT9 EXTINT8 R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 EXTINT7 EXTINT6 EXTINT5 EXTINT4 EXTINT3 EXTINT2 EXTINT1 EXTINT0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Access Access Reset z Bits 31:18 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 17:0 - EXTINTx [x=17..0]: External Interrupt x Enable 0: The external interrupt x is disabled. 1: The external interrupt x is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the External Interrupt x Enable bit, which enables the external interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 344 19.8.7 Interrupt Enable Set This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Name: INTENSET Offset: 0x0C Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 EXTINT17 EXTINT16 Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 EXTINT15 EXTINT14 EXTINT13 EXTINT12 EXTINT11 EXTINT10 EXTINT9 EXTINT8 R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 EXTINT7 EXTINT6 EXTINT5 EXTINT4 EXTINT3 EXTINT2 EXTINT1 EXTINT0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Access Access Reset z Bits 31:18 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 17:0 - EXTINTx [x=17..0]: External Interrupt x Enable 0: The external interrupt x is disabled. 1: The external interrupt x is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the External Interrupt x Enable bit, which enables the external interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 345 19.8.8 Interrupt Flag Status and Clear Name: INTFLAG Offset: 0x10 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 EXTINT17 EXTINT16 Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 EXTINT15 EXTINT14 EXTINT13 EXTINT12 EXTINT11 EXTINT10 EXTINT9 EXTINT8 R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 EXTINT7 EXTINT6 EXTINT5 EXTINT4 EXTINT3 EXTINT2 EXTINT1 EXTINT0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Access Access Reset z Bits 31:18 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 17:0 - EXTINTx [x=17..0]: External Interrupt x This flag is cleared by writing a one to it. This flag is set when EXTINTx pin matches the external interrupt sense configuration and will generate an interrupt request if INTENCLR/SET.EXTINT[x] is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the External Interrupt x flag. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 346 19.8.9 Wake-Up Enable Name: WAKEUP Offset: 0x14 Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 WAKEUPEN17 WAKEUPEN16 Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 WAKEUPEN15 WAKEUPEN14 WAKEUPEN13 WAKEUPEN12 WAKEUPEN11 WAKEUPEN10 WAKEUPEN9 WAKEUPEN8 R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 WAKEUPEN7 WAKEUPEN6 WAKEUPEN5 WAKEUPEN4 WAKEUPEN3 WAKEUPEN2 WAKEUPEN1 WAKEUPEN0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Access Access Reset z Bits 31:18 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 17:0 - WAKEUPENx [x=17..0]: External Interrupt x Wake-up Enable This bit enables or disables wake-up from sleep modes when the EXTINTx pin matches the external interrupt sense configuration. 0: Wake-up from the EXTINTx pin is disabled. 1: Wake-up from the EXTINTx pin is enabled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 347 19.8.10 Configuration n Name: CONFIGn Offset: 0x18+n*0x4 [n=0..2] Reset: 0x00000000 Property: Write-Protected Bit 31 30 FILTEN7 Access 29 28 27 SENSE7[2:0] 26 FILTEN6 25 24 SENSE6[2:0] R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 FILTEN5 Access SENSE5[2:0] FILTEN4 SENSE4[2:0] R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 FILTEN3 Access SENSE3[2:0] FILTEN2 SENSE2[2:0] R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 FILTEN1 Access Reset z SENSE1[2:0] FILTEN0 SENSE0[2:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 31, 27, 23, 19, 15, 11, 7 - FILTENx: Filter 0 Enable 0: Filter is disabled for EXTINT[n*8+x] input. 1: Filter is enabled for EXTINT[n*8+x] input. z Bits 30:28, 26:24, 22:20, 18:16, 14:12, 10:8, 6:4 - SENSEx: Input Sense 0 Configuration These bits define on which edge or level the interrupt or event for EXTINT[n*8+x] will be generated. Table 19-5. Input Sense 0 Configuration SENSE0[2:0] Name Description 0x0 NONE No detection 0x1 RISE Rising-edge detection 0x2 FALL Falling-edge detection 0x3 BOTH Both-edges detection Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 348 SENSE0[2:0] Name 0x4 HIGH High-level detection 0x5 LOW Low-level detection 0x6-0x7 Description Reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 349 20. NVMCTRL - Non-Volatile Memory Controller 20.1 Overview Non-volatile memory (NVM) is a reprogrammable flash memory that retains program and data storage even with power off. The NVM Controller (NVMCTRL) connects to the AHB and APB bus interfaces for system access to the NVM block. The AHB interface is used for reads and writes to the NVM block, while the APB interface is used for commands and configuration. 20.2 Features z 32-bit AHB interface for reads and writes z All NVM sections are memory mapped to the AHB, including calibration and system configuration z 32-bit APB interface for commands and control z Programmable wait states for read optimization z 16 regions can be individually protected or unprotected z Additional protection for boot loader z Supports device protection through a security bit z Interface to Power Manager for power-down of flash blocks in sleep modes z Can optionally wake up on exit from sleep or on first access z Direct-mapped cache 20.3 Block Diagram Figure 20-1. Block Diagram NVMCTRL AHB Cache NVM Interface APB 20.4 NVM Block Command and Control Signal Description Not applicable Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 350 20.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 20.5.1 Power Management The NVMCTRL will continue to operate in any sleep mode where the selected source clock is running. The NVMCTRL's interrupts can be used to wake up the device from sleep modes. Refer to "PM - Power Manager" on page 112 for details on the different sleep modes. The Power Manager will automatically put the NVM block into a low-power state when entering sleep mode. This is based on the Control B register (CTRLB - refer to CTRLB) SLEEPPRM bit setting. Read the CTRLB register description for more details. 20.5.2 Clocks Two synchronous clocks are used by the NVMCTRL. One is provided by the AHB bus (CLK_NVMCTRL_AHB) and the other is provided by the APB bus (CLK_NVMCTRL_APB). For higher system frequencies, a programmable number of wait states can be used to optimize performance. When changing the AHB bus frequency, the user must ensure that the NVM Controller is configured with the proper number of wait states. Refer to the "Electrical Characteristics" on page 1055 for the exact number of wait states to be used for a particular frequency range. 20.5.3 Interrupts The NVM Controller interrupt request line is connected to the interrupt controller. Using the NVMCTRL interrupt requires the interrupt controller to be programmed first. Refer to "Nested Vector Interrupt Controller" on page 29 for details. 20.5.4 Debug Operation When an external debugger forces the CPU into debug mode, the peripheral continues normal operation. Access to the NVM block can be protected by the security bit. In this case, the NVM block will not be accessible. See "Security Bit" on page 356 for details. 20.5.5 Register Access Protection All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the following registers: z Interrupt Flag Status and Clear register (INTFLAG - refer to INTFLAG) z Status register (STATUS - refer to STATUS) Write-protection is denoted by the Write-Protected property in the register description. Write-protection does not apply for accesses through an external debugger. When the CPU is halted in debug mode, all write-protection is automatically disabled. Refer to "PAC - Peripheral Access Controller" on page 36 for details. 20.5.6 Analog Connections Not applicable. 20.6 Functional Description 20.6.1 Principle of Operation The NVM Controller is a slave on the AHB and APB buses. It responds to commands, read requests and write requests, based on user configuration. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 351 20.6.2 Basic Operations 20.6.2.1 Initialization After power up, the NVM Controller goes through a power-up sequence. During this time, access to the NVM Controller from the AHB bus is halted. Upon power-up completion, the NVM Controller is operational without any need for user configuration. 20.6.2.2 Enabling, Disabling and Resetting Not applicable. 20.6.3 Memory Organization Refer to "Physical Memory Map" on page 24 for memory sizes and addresses for each device. The NVM is organized into rows, where each row contains four pages, as shown in Figure 20-2. The NVM has a rowerase granularity, while the write granularity is by page. In other words, a single row erase will erase all four pages in the row, while four write operations are used to write the complete row. Figure 20-2. Row Organization Row n Page (n * 4) + 3 Page (n * 4) + 2 Page (n * 4) + 1 Page (n * 4) + 0 The NVM block contains a calibration and auxiliary space that is memory mapped. Refer to Figure 20-3 for details. The calibration and auxiliary space contains factory calibration and system configuration information. This space can be read from the AHB bus in the same way as the main NVM main address space. In addition, a boot loader section can be allocated at the beginning of the main array, and an EEPROM emulation area can be allocated at the end of the NVM main address space. Figure 20-3. NVM Memory Organization Calibration and Auxillary Space NVM Base Address + 0x00800000 NVM Base Address + NVM Size NVM Main Address Space NVM Base Address The lower rows in the NVM main address space can be allocated as a boot loader section by using the BOOTPROT fuses, and the upper rows can be allocated to EEPROM emulation, as shown in Figure 20-4. The boot loader section is protected by the lock bit(s) corresponding to this address space and by the BOOTPROT[2:0] fuse. The EEPROM rows Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 352 can be written regardless of the region lock status. The number of rows protected by BOOTPROT and the number of rows allocated to EEPROM emulation are given in Table 20-2 and Table 20-3, respectively. Figure 20-4. EEPROM Emulation and Boot Loader Allocation NVM Base Address + NVM size EEPROM Emulation allocation NVM Base Address + NVM size - EEPROM size Program allocation NVM Base Address + BOOTPROT size BOOT allocation NVM Base Address 20.6.4 Region Lock Bits The NVM block is grouped into 16 equally sized regions. The region size is dependent on the flash memory size, and is given in the table below. Each region has a dedicated lock bit preventing writing and erasing pages in the region. After production, all regions will be unlocked. Table 20-1. Region Size Memory Size [KB] Region Size [KB] 256 16 128 8 64 4 32 2 To lock or unlock a region, the Lock Region and Unlock Region commands are provided. Writing one of these commands will temporarily lock/unlock the region containing the address loaded in the ADDR register. ADDR can be written by software, or the automatically loaded value from a write operation can be used. The new setting will stay in effect until the next reset, or the setting can be changed again using the lock and unlock commands. The current status of the lock can be determined by reading the LOCK register. To change the default lock/unlock setting for a region, the user configuration section of the auxiliary space must be written using the Write Auxiliary Page command. Writing to the auxiliary space will take effect after the next reset. Therefore, a boot of the device is needed for changes in the lock/unlock setting to take effect. See "Physical Memory Map" on page 24 for calibration and auxiliary space address mapping. 20.6.5 Command and Data Interface The NVM Controller is addressable from the APB bus, while the NVM main address space is addressable from the AHB bus. Read and automatic page write operations are performed by addressing the NVM main address space directly, Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 353 while other operations such as manual page writes and row erase must be performed by issuing commands through the NVM Controller. To issue a command, the CTRLA.CMD bits must be written along with the CTRLA.CMDEX value. When a command is issued, INTFLAG.READY will be cleared until the command has completed. Any commands written while INTFLAG.READY is low will be ignored. Read the CTRLA register description for more details. The CTRLB register must be used to control the power reduction mode, read wait states and the write mode. 20.6.5.1 NVM Read Reading from the NVM main address space is performed via the AHB bus by addressing the NVM main address space or auxiliary address space directly. Read data is available after the configured number of read wait states (CTRLB.RWS) set in the NVM Controller, has passed. The number of cycles data are delayed to the AHB bus is determined by the read wait states. Examples of using zero and one wait states are shown in Figure 20-5. Figure 20-5. Read Wait State Examples 0 Wait States AHB Command Rd 0 Idle Rd 1 AHB Slave Ready Data 0 AHB Slave Data Data 1 1 Wait State AHB Command Rd 0 Rd 1 Idle AHB Slave Ready AHB Slave Data Data 0 Data 1 20.6.5.2 NVM Write The NVM Controller requires that an erase must be done before programming. The entire NVM main address space can be erased by a debugger Chip Erase command. Alternatively, rows can be individually erased by the Erase Row command. After programming, the region that the page resides in can be locked to prevent spurious write or erase sequences. Locking is performed on a per-region basis, and so locking a region locks all pages inside the region. Data to be written to the NVM block are first written and stored in an internal buffer called the page buffer. The page buffer contains the same number of bytes as an NVM page. Writes to the page buffer must be 16 or 32 bits. 8-bit writes to the page buffer is not allowed, and will cause a system exception. Writing to the NVM block via the AHB bus is performed by a load operation to the page buffer. For each AHB bus write, the address is stored in the ADDR register. After the page buffer has been loaded with the required number of bytes, the page can be written to the addressed location by setting CMD to Write Page and setting the key value to CMDEX. The LOAD bit in the STATUS register indicates whether the page buffer has been loaded or not. Before writing the page to memory, the accessed row must be erased. Automatic page writes are enabled by writing the manual write bit to zero (CTRLB.MANW=0). This will trigger a write operation to the page addressed by ADDR when the last location of the page is written. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 354 Because the address is automatically stored in ADDR during the I/O bus write operation, the last given address will be present in the ADDR register. There is no need to load the ADDR register manually, unless a different page in memory is to be written. Procedure for Manual Page Writes (MANW=1) The row to be written must be erased before the write command is given. z Write to the page buffer by addressing the NVM main address space directly z Write the page buffer to memory: CMD=Write Page and CMDEX z The READY bit in the INTFLAG register will be low while programming is in progress, and access through the AHB will be stalled Procedure for Automatic Page Writes (MANW=0) The row to be written must be erased before the last write to the page buffer is performed. Note that partially written pages must be written with a manual write. z Write to the page buffer by addressing the NVM main address space directly. z z When the last location in the page buffer is written, the page is automatically written to NVM main address space. INTFLAG.READY will be zero while programming is in progress and access through the AHB will be stalled. 20.6.5.3 Page Buffer Clear The page buffer is automatically cleared to all ones after a page write is performed. If a partial page has been written and it is desired to clear the contents of the page buffer, the Page Buffer Clear command can be used. 20.6.5.4 Erase Row Before a page can be written, the row that contains the page must be erased. The Erase Row command can be used to erase the desired row. Erasing the row sets all bits to one. If the row resides in a region that is locked, the erase will not be performed and the Lock Error bit in the Status register (STATUS.LOCKE) will be set. Procedure for Erase Row z Write the address of the row to erase ADDR. Any address within the row can be used. z Issue an Erase Row command. 20.6.5.5 Lock and Unlock Region These commands are used to lock and unlock regions as detailed in section "Region Lock Bits" on page 353. 20.6.5.6 Set and Clear Power Reduction Mode The NVM Controller and block can be taken in and out of power reduction mode through the set and clear power reduction mode commands. When the NVM Controller and block are in power reduction mode, the Power Reduction Mode bit in the Status register (STATUS.PRM) is set. 20.6.6 NVM User Configuration The NVM user configuration resides in the auxiliary space. See "Physical Memory Map" on page 24 for calibration and auxiliary space address mapping. The bootloader resides in the main array starting at offset zero. The allocated boot loader section is protected against write. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 355 Table 20-2. Boot Loader Size BOOTPROT [2:0] Rows Protected by BOOTPROT Boot Loader Size in Bytes 7 None 0 6 2 512 5 4 1024 4 8 2048 3 16 4096 2 32 8192 1 64 16384 0 128 32768 The EEPROM bits indicates the Flash size reserved for EEPROM emulation according to the Table 20-3. EEPROM resides in the upper rows of the NVM main address space and are writable, regardless of the region lock status. Table 20-3. Flash size for EEPROM emulation Note: EEPROM[2:0] Rows Allocated to EEPROM EEPROM Size in Bytes for EEPROM emulation(1) 7 None 0 6 1 256 5 2 512 4 4 1024 3 8 2048 2 16 4096 1 32 8192 0 64 16384 1. the actual size of the EEPROM depends on the emulation software. For more information see Application Note AT03265 20.6.7 Security Bit The security bit allows the entire chip to be locked from external access for code security. The security bit can be written by a dedicated command, Set Security Bit (SSB). Once set, the only way to clear the security bit is through a debugger Chip Erase command. After issuing the SSB command, the PROGE error bit can be checked. Refer to "DSU - Device Service Unit" on page 45 for details. 20.6.8 Cache The NVM Controller cache reduces the device power consumption and improves system performance when wait states are required. It is a direct-mapped cache that implements 8 lines of 64 bits (i.e., 64 bytes). NVM Controller cache can be enabled by writing a zero in the CACHEDIS bit in the CTRLB register (CTRLB.CACHEDIS). Cache can be configured to three different modes using the READMODE bit group in the CTRLB register. Refer to CTRLB register description for more details. The INVALL command can be issued through the CTRLA register to invalidate all cache lines. Commands affecting NVM content automatically invalidate cache lines. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 356 20.7 Register Summary Table 20-4. Register Summary Offset 0x00 0x01 Name CTRLA 0x02 Reserved 0x03 Reserved Bit Pos. 7:0 15:8 0x04 7:0 0x05 15:8 0x06 CTRLB CMD[6:0] CMDEX[7:0] MANW RWS[3:0] SLEEPPRM[1:0] 23:16 CACHEDIS 0x07 31:24 0x08 7:0 NVMP[7:0] 15:8 NVMP[15:8] 0x09 0x0A PARAM 0x0B INTENCLR 0x0D ... 0x0F Reserved 0x10 INTENSET 0x11 ... 0x13 Reserved 0x14 INTFLAG 0x15 ... 0x17 Reserved 0x19 PSZ[2:0] 31:24 0x0C 0x18 23:16 STATUS 0x1A Reserved 0x1B Reserved 7:0 ERROR READY 7:0 ERROR READY 7:0 ERROR READY LOAD PRM 7:0 NVME LOCKE SB 7:0 ADDR[7:0] 0x1D 15:8 ADDR[15:8] ADDR 0x1F 0x20 0x21 PROGE 15:8 0x1C 0x1E READMODE[1:0] 23:16 ADDR[21:16] 31:24 LOCK 7:0 LOCK[7:0] 15:8 LOCK[15:8] Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 357 20.8 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protected property in each individual register description. Refer to the "Register Access Protection" on page 351 and the "PAC - Peripheral Access Controller" on page 36 for details. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 358 20.8.1 Control A Name: CTRLA Offset: 0x00 Reset: 0x0000 Property: Write-Protected Bit 15 14 13 12 11 10 9 8 CMDEX[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CMD[6:0] Access R R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 15:8 - CMDEX[7:0]: Command Execution This bit group should be written with the key value 0xA5 to enable the command written to CMD to be executed. If the bit group is written with a different key value, the write is not performed and the PROGE status bit is set. PROGE is also set if the a previously written command is not complete. The key value must be written at the same time as CMD. If a command is issued through the APB bus on the same cycle as an AHB bus access, the AHB bus access will be given priority. The command will then be executed when the NVM block and the AHB bus are idle. The READY status must be one when the command is issued. Bit 0 of the CMDEX bit group will read back as one until the command is issued. Table 20-5. Command Execution CMDEX[7:0] Name 0x0-0xA4 0xA5 0xA6-0xFF Description Reserved KEY Execution Key Reserved z Bit 7 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 6:0 - CMD[6:0]: Command These bits define the command to be executed when the CMDEX key is written, as shown in Table 20-6. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 359 Table 20-6. Command CMD[6:0] Name 0x00-0x01 - 0x02 ER 0x03 - 0x04 WP Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. EAR Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. 0x06 WAP Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. 0x07-0x09 - 0x0A SF 0x0B-0x0E - 0x0F WL 0x10-0x3F - 0x40 LR Lock Region - Locks the region containing the address location in the ADDR register. 0x41 UR Unlock Region - Unlocks the region containing the address location in the ADDR register. 0x42 SPRM Sets the power reduction mode. 0x43 CPRM Clears the power reduction mode. 0x44 PBC Page Buffer Clear - Clears the page buffer. 0x45 SSB Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. 0x46 INVALL 0x47-0x7F - 0x05 Description Reserved Erase Row - Erases the row addressed by the ADDR register. Reserved Reserved Security Flow Command Reserved Write lockbits Reserved Invalidates all cache lines. Reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 360 20.8.2 Control B Name: CTRLB Offset: 0x04 Reset: 0x00000080 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 CACHEDIS READMODE[1:0] Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 SLEEPPRM[1:0] Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MANW Access Reset RWS[3:0] R/W R R R/W R/W R/W R/W R 0 0 0 0 0 0 0 0 z Bits 31:19 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 18 - CACHEDIS: Cache Disable This bit is used to disable the cache. 0: The cache is enabled. 1: The cache is disabled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 361 z Bits 17:16 - READMODE[1:0]: NVMCTRL Read Mode Table 20-7. NVMCTRL Read Mode READMODE[1:0] Name Description 0x0 NO_MISS_PENALTY The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. 0x1 0x2 LOW_POWER DETERMINISTIC 0x3 Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. Reserved z Bits 15:10 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 9:8 - SLEEPPRM[1:0]: Power Reduction Mode during Sleep Indicates the power reduction mode during sleep. Table 20-8. Power Reduction Mode during Sleep SLEEPPRM[1:0] Name 0x0 WAKEONACCESS NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. 0x1 WAKEUPINSTANT NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. 0x2 0x3 z Description Reserved DISABLED Auto power reduction disabled. Bit 7 - MANW: Manual Write 0: Writing to the last word in the page buffer will initiate a write operation to the page addressed by the last write operation. This includes writes to memory and auxiliary rows. 1: Write commands must be issued through the CMD register. z Bits 6:5 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 4:1 - RWS[3:0]: NVM Read Wait States These bits give the number of wait states for a read operation. Zero indicates zero wait states, one indicates one wait state, etc., up to 15 wait states. This register is initialized to 0 wait states. Software can change this value based on the NVM access time and system frequency. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 362 z Bit 0 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 363 20.8.3 NVM Parameter Name: PARAM Offset: 0x08 Reset: 0x000XXXXX Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 PSZ[2:0] Access R R R R R R R R Reset 0 0 0 0 0 X X X Bit 15 14 13 12 11 10 9 8 NVMP[15:8] Access R R R R R R R R Reset X X X X X X X X Bit 7 6 5 4 3 2 1 0 NVMP[7:0] Access R R R R R R R R Reset X X X X X X X X z Bits 31:19 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 18:16 - PSZ[2:0]: Page Size Indicates the page size. Not all device families will provide all the page sizes indicated in the table. Table 20-9. Page Size PSZ[2:0] Name Description 0x0 8 8 bytes 0x1 16 16 bytes 0x2 32 32 bytes 0x3 64 64 bytes 0x4 128 128 bytes Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 364 z PSZ[2:0] Name Description 0x5 256 256 bytes 0x6 512 512 bytes 0x7 1024 1024 bytes Bits 15:0 - NVMP[15:0]: NVM Pages Indicates the number of pages in the NVM main address space. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 365 20.8.4 Interrupt Enable Clear This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Name: INTENCLR Offset: 0x0C Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 ERROR READY Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 1 - ERROR: Error Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit clears the ERROR interrupt enable. This bit will read as the current value of the ERROR interrupt enable. z Bit 0 - READY: NVM Ready Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit clears the READY interrupt enable. This bit will read as the current value of the READY interrupt enable. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 366 20.8.5 Interrupt Enable Set This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Name: INTENSET Offset: 0x10 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 ERROR READY Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 1 - ERROR: Error Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit sets the ERROR interrupt enable. This bit will read as the current value of the ERROR interrupt enable. z Bit 0 - READY: NVM Ready Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit sets the READY interrupt enable. This bit will read as the current value of the READY interrupt enable. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 367 20.8.6 Interrupt Flag Status and Clear Name: INTFLAG Offset: 0x14 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 ERROR READY Access R R R R R R R/W R Reset 0 0 0 0 0 0 0 0 z Bits 7:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 1 - ERROR: Error This flag is set on the occurrence of an NVME, LOCKE or PROGE error. 0: No errors have been received since the last clear. 1: At least one error has occurred since the last clear. This bit can be cleared by writing a one to its bit location. z Bit 0 - READY: NVM Ready 0: The NVM controller is busy programming or erasing. 1: The NVM controller is ready to accept a new command. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 368 20.8.7 Status Name: STATUS Offset: 0x18 Reset: 0x0X00 Property: - Bit 15 14 13 12 11 10 9 8 SB Access R R R R R R R R Reset 0 0 0 0 0 0 0 X Bit 7 6 5 4 3 2 1 0 NVME LOCKE PROGE LOAD PRM Access R R R R/W R/W R/W R/W R Reset 0 0 0 0 0 0 0 0 z Bits 15:9 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 8 - SB: Security Bit Status 0: The Security bit is inactive. 1: The Security bit is active. z Bits 7:5 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 4 - NVME: NVM Error 0: No programming or erase errors have been received from the NVM controller since this bit was last cleared. 1: At least one error has been registered from the NVM Controller since this bit was last cleared. This bit can be cleared by writing a one to its bit location. z Bit 3 - LOCKE: Lock Error Status 0: No programming of any locked lock region has happened since this bit was last cleared. 1: Programming of at least one locked lock region has happened since this bit was last cleared. This bit can be cleared by writing a one to its bit location. z Bit 2 - PROGE: Programming Error Status 0: No invalid commands or bad keywords were written in the NVM Command register since this bit was last cleared. 1: An invalid command and/or a bad keyword was/were written in the NVM Command register since this bit was last cleared. This bit can be cleared by writing a one to its bit location. z Bit 1 - LOAD: NVM Page Buffer Active Loading This bit indicates that the NVM page buffer has been loaded with one or more words. Immediately after an NVM load has been performed, this flag is set, and it remains set until a page write or a page buffer clear (PBCLR) command is given. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 369 This bit can be cleared by writing a one to its bit location. z Bit 0 - PRM: Power Reduction Mode This bit indicates the current NVM power reduction state. The NVM block can be set in power reduction mode in two ways: through the command interface or automatically when entering sleep with SLEEPPRM set accordingly. PRM can be cleared in three ways: through AHB access to the NVM block, through the command interface (SPRM and CPRM) or when exiting sleep with SLEEPPRM set accordingly. 0: NVM is not in power reduction mode. 1: NVM is in power reduction mode. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 370 20.8.8 Address Name: ADDR Offset: 0x1C Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 ADDR[21:16] Access R R R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 ADDR[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADDR[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 31:22 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 21:0 - ADDR[21:0]: NVM Address ADDR drives the hardware (16-bit) address to the NVM when a command is executed using CMDEX. 8-bit addresses must be shifted one bit to the right before writing to this register. This register is automatically updated when writing to the page buffer, and can also be manually written. This register holds the address offset for the section addressed. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 371 20.8.9 Lock Section Name: LOCK Offset: 0x20 Reset: - Property: - Bit 15 14 13 12 11 10 9 8 LOCK[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 LOCK[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 15:0 - LOCK[15:0]: Region Lock Bits In order to set or clear these bits, the CMD register must be used. 0: The corresponding lock region is locked. 1: The corresponding lock region is not locked. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 372 21. PORT 21.1 Overview The Port (PORT) controls the I/O pins of the microcontroller. The I/O pins are organized in a series of groups, collectively referred to as a port group, and each group can have up to 32 pins that can be configured and controlled individually or as a group. Each pin may either be used for general-purpose I/O under direct application control or assigned to an embedded device peripheral. When used for general-purpose I/O, each pin can be configured as input or output, with highly configurable driver and pull settings. All I/O pins have true read-modify-write functionality when used for general-purpose I/O; the direction or the output value of one or more pins may be changed (set, reset or toggled) without unintentionally changing the state of any other pins in the same port group via a single, atomic 8-, 16- or 32-bit write. The PORT is connected to the high-speed bus matrix through an AHB/APB bridge. The Pin Direction, Data Output Value and Data Input Value registers may also be accessed using the low-latency CPU local bus (IOBUS; ARM(R) single-cycle I/O port). 21.2 Features z Selectable input and output configuration individually for each pin z Software-controlled multiplexing of peripheral functions on I/O pins z Flexible pin configuration through a dedicated Pin Configuration register z Configurable output driver and pull settings: z z Totem-pole (push-pull) Pull configuration z Configurable input buffer and pull settings: Internal pull-up or pull-down Input sampling criteria z Input buffer can be disabled if not needed for lower power consumption z z z Read-modify-write support for pin configuration, output value and pin direction Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 373 21.3 Block Diagram Figure 21-1. PORT Block Diagram PORT Peripheral Mux Select Control and Status Port Line Interface Pin Line Interface IP Line Interface I/O PINS Analog Pin Connections PERIPHERALS Digital Controls of Analog Blocks ANALOG BLOCKS 21.4 Signal Description Signal Name Type Description Pxy Digital I/O General-purpose I/O pin y Refer to "I/O Multiplexing and Considerations" on page 12 for details on the pin mapping for this peripheral. One signal can be mapped on several pins. 21.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 21.5.1 I/O Lines The I/O lines of the PORT are mapped to pins of the physical device package according to a simple naming scheme. Each port group of up to 32 pins is assigned a letter identifier, starting with A, that monotonically increases through the alphabet for each subsequent port group. Within each port group, each pin is assigned a numerical identifier according to its bit position. The resulting PORT pins are mapped as Pxy, where x=A, B, C,... and y=00, 01, ..., 31 to uniquely identify each pin in the device, e.g., PA24, PC03, etc. Each pin may have one or more peripheral multiplexer settings, which allow the pin to be routed internally to a dedicated peripheral function. When enabled, the selected peripheral is given control over the output state of the pin, as well as the ability to read the current physical pin state. Refer to "I/O Multiplexing and Considerations" on page 12 for details. Device-specific configurations may result in some pins (and the corresponding Pxy pin) not being implemented. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 374 21.5.2 Power Management During reset, all PORT lines are configured as inputs with input buffers, output buffers and pull disabled. If the PORT peripheral is shut down, the latches contained in the I/O block will retain their current configuration, such as the output value and pull settings. However, the PORT configuration registers and input synchronizers will lose their contents, and these will not be restored when PORT is powered up again. The user must, therefore, reconfigure the PORT peripheral at power up to ensure it is in a well-defined state before use. The PORT will continue to operate in any sleep mode where the selected module source clock is running. 21.5.3 Clocks The PORT bus clock (CLK_PORT_APB) can be enabled and disabled in the Power Manager, and the default state of CLK_PORT_APB can be found in the Peripheral Clock Masking section in the "PM - Power Manager" on page 112. The PORT is fed by two different clocks: a CPU main clock, which allows the CPU to access the PORT through the lowlatency CPU local bus (IOBUS), and an APB clock, which is a divided clock of the CPU main clock and allows the CPU to access the PORT registers through the high-speed matrix and the AHB/APB bridge. IOBUS accesses have priority over APB accesses. The latter must insert wait states in the event of concurrent PORT accesses. The PORT input synchronizers use the CPU main clock so that the resynchronization delay is minimized with respect to the APB clock. 21.5.4 DMA Not applicable. 21.5.5 Interrupts Not applicable. 21.5.6 Events Not applicable. 21.5.7 Debug Operation When the CPU is halted in debug mode, the PORT continues normal operation. If the PORT is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 21.5.8 Register Access Protection All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protected property in the register description. When the CPU is halted in debug mode, all write-protection is automatically disabled. Write-protection does not apply for accesses through an external debugger. Refer to "PAC - Peripheral Access Controller" on page 36 for details. 21.5.9 Analog Connections Analog functions are connected directly between the analog blocks and the I/O pins using analog buses. However, selecting an analog peripheral function for a given pin will disable the corresponding digital features of the pin. 21.5.10 CPU Local Bus The CPU local bus (IOBUS) is an interface that connects the CPU directly to the PORT. It is a single-cycle bus interface, and does not support wait states. It supports byte, half word and word sizes. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 375 The CPU accesses the PORT module through the IOBUS when it performs read or write from address 0x60000000. The PORT register map is equivalent to the one described in the register description section. This bus is generally used for low latency. The Data Direction (DIR) and Data Output Value (OUT) registers can be read, written, set, cleared or toggled using this bus, and the Data Input Value (IN) registers can be read. Since the IOBUS cannot wait for IN register resynchronization, the Control register (CTRL) must be configured to enable continuous sampling of all pins that will need to be read via the IOBUS to prevent stale data from being read. 21.6 Functional Description Figure 21-2. Overview of the PORT ... PADy PORTx PULLEN PULLENy Pull Resistor APB Bus PG OUT OUTy PORT MULTIPLEXER DIRy PADy VDD OE NG INEN INENy IN INy Synchronizer ... Input to Other Modules Analog Input/Output 21.6.1 Principle of Operation The I/O pins of the device are controlled by reads and writes of the PORT peripheral registers. For each port pin, a corresponding bit in the Data Direction (DIR) and Data Output Value (OUT) registers are used to enable that pin as an output and to define the output state. The direction of each pin in a port group is configured via the DIR register. If a bit in DIR is written to one, the corresponding pin is configured as an output pin. If a bit in DIR is written to zero, the corresponding pin is configured as an input pin. When the direction is set as output, the corresponding bit in the OUT register is used to set the level of the pin. If bit y of OUT is written to one, pin y is driven high. If bit y of OUT is written to zero, pin y is driven low. Additional pin configuration can be set by writing to the Pin Configuration (PINCFG0) registers. The Data Input Value bit (IN) is used to read the port pin with resynchronization to the PORT clock. By default, these input synchronizers are clocked only when an input value read is requested in order to reduce power consumption. Input value can always be read, whether the pin is configured as input or output, except if digital input is disabled by writing a zero to the INEN bit in the Pin Configuration registers (PINCFGy). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 376 The PORT also allows peripheral functions to be connected to individual I/O pins by writing a one to the corresponding PMUXEN bit in the PINCFGy registers and by writing the chosen selection to the Peripheral Multiplexing registers (PMUX0) for that pin. This will override the connection between the PORT and that I/O pin, and connect the selected peripheral line interface to the pin instead of the PORT line interface. Each group of up to 32 pins is controlled by a set of registers, as described in Figure 21-3. This set of registers is duplicated for each group of pins, with increasing base addresses. Figure 21-3. Overview of the Peripheral Functions Multiplexing PORT x bit y Port x bit y PINCFG PMUXEN Port x bit y Data+Config Port x bit y PMUX[3:0] Port y Peripheral Mux Enable Port y Line Interface 0 Port y PMUX Select Pin y Pin y Line Interface Periph Line 0 0 Periph Line 1 1 1 Peripheral Line Interface to be muxed to Pin y Periph Line 15 15 21.6.2 Basic Operation 21.6.2.1 Initialization After reset, all standard-function device I/O pins are connected to the PORT with outputs tri-stated and input buffers disabled, even if no clocks are running. Specific pins, such as the ones used for connection to a debugger, may be configured differently, as required by their special function. Each I/O pin y can be configured and accessed by reading or writing PORT registers. Because PORT registers are grouped into sets of registers for each group of up to 32 pins, the base address of the register set for pin y is at byte address PORT + (y/32) * 0x80. (y%32) will be used as the index within each register of that register set. To use pin y as an output, configure it as output by writing the (y%32) bit in the DIR register to one. To avoid disturbing the configuration of other pins in that group, this can also be done by writing the (y%32) bit in the DIRSET register to one. The desired output value can be set by writing the (y%32) bit to that value in register OUT. Similarly, writing one to a bit in Data Output Value Set (OUTSET) register will set the corresponding bit in Data Output Value (OUT) register to one. Writing one to a bit in Data Output Value Clear (OUTCLR) register will set the corresponding bit in Data Output Value (OUT) register to zero. Writing one to a bit in Data Output Value Toggle (OUTTGL) register will toggle the corresponding bit in Data Output Value (OUT) register. To use pin y as an input, configure it as input by writing the (y%32) bit in the DIR register to zero. To avoid disturbing the configuration of other pins in that group, this can also be done by writing the (y%32) bit in DIRCLR register to one. The desired input value can be read from the (y%32) bit in register IN as soon as the INEN bit in the Pin Configuration register (PINCFGy) is written to one. Refer to "I/O Multiplexing and Considerations" on page 12 for details on pin configuration. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 377 By default, the input synchronizer is clocked only when an input read is requested, which will delay the read operation by two CLK_PORT cycles. To remove that delay, the input synchronizers for each group of eight pins can be configured to be always active, but this comes at the expense of higher power consumption. This is controlled by writing a one to the corresponding SAMPLINGn bit group of the CTRL register, where n = (y%32) / 8. To use pin y as one of the available peripheral functions for that pin, configure it by writing a one to the corresponding PMUXEN bit of the PINCFGy register. The PINCFGy register for pin y is at byte offset (PINCFG0 + (y%32)). The peripheral function can be selected by writing to the PMUXO or PMUXE bit group in the PMUXn register. The PMUXO/PMUXE bit group is at byte offset (PMUX0 + (y%32) / 2), in bits 3:0 if y is even and in bits 7:4 if y is odd. The chosen peripheral must also be configured and enabled. 21.6.3 I/O Pin Configuration The Pin Configuration register (PINCFGy) is used for additional I/O pin configuration. A pin can be set in a totem-pole or pull configuration. Because pull configuration is done through the Pin Configuration register, all intermediate PORT states during switching of pin direction and pin values are avoided. The I/O pin configurations are described further in this chapter, and summarized in Table 21-1. 21.6.3.1 Pin Configurations Summary Table 21-1. Pin Configurations Summary DIR INEN PULLEN OUT Configuration 0 0 0 X Reset or analog I/O; all digital disabled 0 0 1 0 Pull-down; input disabled 0 0 1 1 Pull-up; input disabled 0 1 0 X Input 0 1 1 0 Input with pull-down 0 1 1 1 Input with pull-up 1 0 X X Output; input disabled 1 1 X X Output; input enabled 21.6.3.2 Input Configuration Figure 21-4. I/O Configuration - Standard Input PULLEN PULLEN INEN DIR 0 1 0 DIR OUT IN INEN Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 378 Figure 21-5. I/O Configuration - Input with Pull PULLEN PULLEN INEN DIR 1 1 0 DIR OUT IN INEN Note that when pull is enabled, the pull value is defined by the OUTx value. 21.6.3.3 Totem-Pole Output When configured for totem-pole (push-pull) output, the pin is driven low or high according to the corresponding bit setting in the OUT register. In this configuration, there is no current limitation for sink or source other than what the pin is capable of. If the pin is configured for input, the pin will float if no external pull is connected. Note, that enabling the output driver automatically disables pull. Figure 21-6. I/O Configuration - Totem-Pole Output with Disabled Input PULLEN PULLEN INEN DIR 0 0 1 PULLEN INEN DIR 0 1 1 DIR OUT IN INEN Figure 21-7. I/O Configuration - Totem-Pole Output with Enabled Input PULLEN DIR OUT IN INEN Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 379 Figure 21-8. I/O Configuration - Output with Pull PULLEN PULLEN INEN DIR 1 0 0 DIR OUT IN INEN 21.6.3.4 Digital Functionality Disabled Figure 21-9. I/O Configuration - Reset or Analog I/O: Digital Output, Input and Pull Disabled PULLEN PULLEN INEN DIR 0 0 0 DIR OUT IN INEN Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 380 21.7 Register Summary The I/O pins are organized in groups with up to 32 pins. Group 0 consists of the PA pins, group 1 the PB pins, etc. Each group has its own set of registers. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, while the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Table 21-2. Register Summary Offset Name 0x00 0x01 0x02 Bit Pos. 7:0 DIR DIR[7:0] 15:8 DIR[15:8] 23:16 DIR[23:16] 0x03 31:24 DIR[31:24] 0x04 7:0 DIRCLR[7:0] 15:8 DIRCLR[15:8] 23:16 DIRCLR[23:16] 31:24 DIRCLR[31:24] 0x05 0x06 DIRCLR 0x07 0x08 7:0 DIRSET[7:0] 0x09 15:8 DIRSET[15:8] 23:16 DIRSET[23:16] 31:24 DIRSET[31:24] 0x0A DIRSET 0x0B 0x0C 7:0 DIRTGL[7:0] 0x0D 15:8 DIRTGL[15:8] 23:16 DIRTGL[23:16] 0x0F 31:24 DIRTGL[31:24] 0x10 7:0 OUT[7:0] 0x0E 0x11 0x12 DIRTGL OUT 15:8 OUT[15:8] 23:16 OUT[23:16] 0x13 31:24 OUT[31:24] 0x14 7:0 OUTCLR[7:0] 15:8 OUTCLR[15:8] 23:16 OUTCLR[23:16] 31:24 OUTCLR[31:24] 0x15 0x16 OUTCLR 0x17 0x18 7:0 OUTSET[7:0] 0x19 15:8 OUTSET[15:8] 23:16 OUTSET[23:16] 31:24 OUTSET[31:24] 0x1A OUTSET 0x1B 0x1C 7:0 OUTTGL[7:0] 0x1D 15:8 OUTTGL[15:8] 23:16 OUTTGL[23:16] 0x1F 31:24 OUTTGL[31:24] 0x20 7:0 IN[7:0] 0x1E 0x21 0x22 OUTTGL IN 15:8 IN[15:8] 23:16 IN[23:16] 0x23 31:24 IN[31:24] 0x24 7:0 SAMPLING[7:0] 15:8 SAMPLING[15:8] 23:16 SAMPLING[23:16] 31:24 SAMPLING[31:24] 0x25 0x26 0x27 CTRL Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 381 Offset Name Bit Pos. 0x28 7:0 PINMASK[7:0] 0x29 15:8 PINMASK[15:8] 0x2A WRCONFIG 0x2B 23:16 31:24 DRVSTR HWSEL WRPINCFG PULLEN WRPMUX INEN PMUX[3:0] 0x2C ... 0x2F Reserved 0x30 PMUX0 7:0 PMUXO[3:0] PMUXE[3:0] 0x31 PMUX1 7:0 PMUXO[3:0] PMUXE[3:0] PMUXO[3:0] PMUXE[3:0] ... .. ... 0x3F PMUX15 7:0 PMUXEN 0x40 PINCFG0 7:0 DRVSTR PULLEN INEN PMUXEN 0x41 PINCFG1 7:0 DRVSTR PULLEN INEN PMUXEN ... ... ... 0x5F PINCFG31 7:0 DRVSTR PULLEN INEN PMUXEN 0x60 ... 0x7F Reserved 0x80 ... 0x17D repeated 2 times from DIR Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 382 21.8 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protected property in each individual register description. Refer to "Register Access Protection" on page 375 for details. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 383 21.8.1 Data Direction Name: DIR Offset: 0x00+x*0x80 [x=0..2] Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 DIR[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DIR[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DIR[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DIR[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 31:0 - DIR[31:0]: Port Data Direction These bits set the data direction for the individual I/O pins in the PORT group. 0: The corresponding I/O pin in the group is configured as an input. 1: The corresponding I/O pin in the group is configured as an output. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 384 21.8.2 Data Direction Clear This register allows the user to set one or more I/O pins as an input, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Toggle (DIRTGL) and Data Direction Set (DIRSET) registers. Name: DIRCLR Offset: 0x04+x*0x80 [x=0..2] Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 DIRCLR[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DIRCLR[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DIRCLR[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DIRCLR[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 31:0 - DIRCLR[31:0]: Port Data Direction Clear 0: The I/O pin direction is cleared. 1: The I/O pin direction is set. Writing a zero to a bit has no effect. Writing a one to a bit will clear the corresponding bit in the DIR register, which configures the I/O pin as an input. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 385 21.8.3 Data Direction Set This register allows the user to set one or more I/O pins as an output, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Toggle (DIRTGL) and Data Direction Clear (DIRCLR) registers. Name: DIRSET Offset: 0x08+x*0x80 [x=0..2] Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 DIRSET[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DIRSET[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DIRSET[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DIRSET[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 31:0 - DIRSET[31:0]: Port Data Direction Set 0: The I/O pin direction is cleared. 1: The I/O pin direction is set. Writing a zero to a bit has no effect. Writing a one to a bit will set the corresponding bit in the DIR register, which configures the I/O pin as an output. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 386 21.8.4 Data Direction Toggle This register allows the user to toggle the direction of one or more I/O pins, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Set (DIRSET) and Data Direction Clear (DIRCLR) registers. Name: DIRTGL Offset: 0x0C+x*0x80 [x=0..2] Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 DIRTGL[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DIRTGL[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DIRTGL[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DIRTGL[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 31:0 - DIRTGL[31:0]: Port Data Direction Toggle 0: The I/O pin direction is cleared. 1: The I/O pin direction is set. Writing a zero to a bit has no effect. Writing a one to a bit will toggle the corresponding bit in the DIR register, which reverses the direction of the I/O pin. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 387 21.8.5 Data Output Value This register sets the data output drive value for the individual I/O pins in the PORT. Name: OUT Offset: 0x10+x*0x80 [x=0..2] Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 OUT[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 OUT[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 OUT[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OUT[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 31:0 - OUT[31:0]: Port Data Output Value These bits set the logical output drive level of I/O pins configured as outputs via the Data Direction register (DIR). For pins configured as inputs via the Data Direction register (DIR) with pull enabled via the Pull Enable register (PULLEN), these bits will set the input pull direction. 0: The I/O pin output is driven low, or the input is connected to an internal pull-down. 1: The I/O pin output is driven high, or the input is connected to an internal pull-up. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 388 21.8.6 Data Output Value Clear This register allows the user to set one or more output I/O pin drive levels low, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Toggle (OUTTGL) and Data Output Value Set (OUTSET) registers. Name: OUTCLR Offset: 0x14+x*0x80 [x=0..2] Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 OUTCLR[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 OUTCLR[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 OUTCLR[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OUTCLR[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 31:0 - OUTCLR[31:0]: Port Data Output Value Clear 0: The I/O pin output is driven low. 1: The I/O pin output is driven high. Writing a zero to a bit has no effect. Writing a one to a bit will clear the corresponding bit in the OUT register, which sets the output drive level low for I/O pins configured as outputs via the Data Direction register (DIR). For pins configured as inputs via the Data Direction register (DIR) and with pull enabled via the Pull Enable register (PULLEN), these bits will set the input pull direction to an internal pull-down. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 389 21.8.7 Data Output Value Set This register allows the user to set one or more output I/O pin drive levels high, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Toggle (OUTTGL) and Data Output Value Clear (OUTCLR) registers. Name: OUTSET Offset: 0x18+x*0x80 [x=0..2] Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 OUTSET[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 OUTSET[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 OUTSET[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OUTSET[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 31:0 - OUTSET[31:0]: Port Data Output Value Set 0: The I/O pin output is driven low. 1: The I/O pin output is driven high. Writing a zero to a bit has no effect. Writing a one to a bit will set the corresponding bit in the OUT register, which sets the output drive level high for I/O pins configured as outputs via the Data Direction register (DIR). For pins configured as inputs via the Data Direction register (DIR) and with pull enabled via the Pull Enable register (PULLEN), these bits will set the input pull direction to an internal pull-up. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 390 21.8.8 Data Output Value Toggle This register allows the user to toggle the drive level of one or more output I/O pins, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Set (OUTSET) and Data Output Value Clear (OUTCLR) registers. Name: OUTTGL Offset: 0x1C+x*0x80 [x=0..2] Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 OUTTGL[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 OUTTGL[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 OUTTGL[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OUTTGL[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 31:0 - OUTTGL[31:0]: Port Data Output Value Toggle 0: The I/O pin output is driven low. 1: The I/O pin output is driven high. Writing a zero to a bit has no effect. Writing a one to a bit will toggle the corresponding bit in the OUT register, which inverts the output drive level for I/O pins configured as outputs via the Data Direction register (DIR). For pins configured as inputs via the Data Direction register (DIR) and with pull enabled via the Pull Enable register (PULLEN), these bits will toggle the input pull direction. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 391 21.8.9 Data Input Value Name: IN Offset: 0x20+x*0x80 [x=0..2] Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 IN[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 IN[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 IN[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 IN[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 31:0 - IN[31:0]: Port Data Input Value These bits are cleared when the corresponding I/O pin input sampler detects a logical low level on the input pin. These bits are set when the corresponding I/O pin input sampler detects a logical high level on the input pin. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 392 21.8.10 Control Name: CTRL Offset: 0x24+x*0x80 [x=0..2] Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 SAMPLING[31:24] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 SAMPLING[23:16] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 SAMPLING[15:8] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SAMPLING[7:0] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 z Bits 31:0 - SAMPLING[31:0]: Input Sampling Mode Configures the input sampling functionality of the I/O pin input samplers for pins configured as inputs via the Data Direction register (DIR). 0: The I/O pin input synchronizer is disabled. 1: The I/O pin input synchronizer is enabled. The input samplers are enabled and disabled in sub-groups of eight. Thus, if any pins within a byte request continuous sampling, all pins in that eight pin sub-group will be continuously sampled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 393 21.8.11 Write Configuration This write-only register is used to configure several pins simultaneously with the same configuration and/or peripheral multiplexing. In order to avoid the side effect of non-atomic access, 8-bit or 16-bit writes to this register will have no effect. Reading this register always returns zero. Name: WRCONFIG Offset: 0x28+x*0x80 [x=0..2] Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 HWSEL WRPINCFG Access W W R W W Reset 0 0 0 0 Bit 23 22 21 20 26 25 24 W W W 0 0 0 0 19 18 17 16 PULLEN INEN PMUXEN WRPMUX PMUX[3:0] DRVSTR Access R W R R R W W W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 PINMASK[15:8] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PINMASK[7:0] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 z Bit 31 - HWSEL: Half-Word Select This bit selects the half-word field of a 32-pin group to be reconfigured in the atomic write operation. 0: The lower 16 pins of the PORT group will be configured. 1: The upper 16 pins of the PORT group will be configured. This bit will always read as zero. z Bit 30 - WRPINCFG: Write PINCFG This bit determines whether the atomic write operation will update the Pin Configuration register (PINCFGy) or not for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits. 0: The PINCFGy registers of the selected pins will not be updated. 1: The PINCFGy registers of the selected pins will be updated. Writing a zero to this bit has no effect. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 394 Writing a one to this bit updates the configuration of the selected pins with the written WRCONFIG.DRVSTR, WRCONFIG.SLEWLIM, WRCONFIG.ODRAIN, WRCONFIG.PULLEN, WRCONFIG.INEN, WRCONFIG.PMUXEN and WRCONFIG.PINMASK values. This bit will always read as zero. z Bit 29 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 28 - WRPMUX: Write PMUX This bit determines whether the atomic write operation will update the Peripheral Multiplexing register (PMUXn) or not for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits. 0: The PMUXn registers of the selected pins will not be updated. 1: The PMUXn registers of the selected pins will be updated. Writing a zero to this bit has no effect. Writing a one to this bit updates the pin multiplexer configuration of the selected pins with the written WRCONFIG.PMUX value. This bit will always read as zero. z Bits 27:24 - PMUX[3:0]: Peripheral Multiplexing These bits determine the new value written to the Peripheral Multiplexing register (PMUXn) for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPMUX bit is set. These bits will always read as zero. z Bit 23 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 22 - DRVSTR: Output Driver Strength Selection This bit determines the new value written to PINCFGy.DRVSTR for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits the WRCONFIG.WRPINCFG bit is set. This bit will always read as zero. z Bits 21:19 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 18 - PULLEN: Pull Enable This bit determines the new value written to PINCFGy.PULLEN for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits when the WRCONFIG.WRPINCFG bit is set. This bit will always read as zero. z Bit 17 - INEN: Input Enable This bit determines the new value written to PINCFGy.DRVSTR for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits when the WRCONFIG.WRPINCFG bit is set. This bit will always read as zero. z Bit 16 - PMUXEN: Peripheral Multiplexer Enable This bit determines the new value written to PINCFGy.PMUXEN for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits when the WRCONFIG.WRPINCFG bit is set. This bit will always read as zero. z Bits 15:0 - PINMASK[15:0]: Pin Mask for Multiple Pin Configuration These bits select the pins to be configured within the half-word group selected by the WRCONFIG.HWSEL bit. 0: The configuration of the corresponding I/O pin in the half-word group will be left unchanged. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 395 1: The configuration of the corresponding I/O pin in the half-word pin group will be updated. These bits will always read as zero. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 396 21.8.12 Peripheral Multiplexing n There are up to 16 Peripheral Multiplexing registers in each group, one for every set of two subsequent I/O lines. The n denotes the number of the set of I/O lines, while the x denotes the number of the group. Name: PMUXn Offset: 0x30+n [n=0..15]+x*0x80 [x=0..2] Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 PMUXO[3:0] Access Reset z 1 0 PMUXE[3:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:4 - PMUXO[3:0]: Peripheral Multiplexing Odd These bits select the peripheral function for odd-numbered pins (2*n + 1) of a PORT group, if the corresponding PINCFGy.PMUXEN bit is one. Not all possible values for this selection may be valid. For more details, refer to "I/O Multiplexing and Considerations" on page 12. Table 21-3. Peripheral Multiplexing Odd PMUXO[3:0] Name 0x0 A Peripheral function A selected 0x1 B Peripheral function B selected 0x2 C Peripheral function C selected 0x3 D Peripheral function D selected 0x4 E Peripheral function E selected 0x5 F Peripheral function F selected 0x6 G Peripheral function G selected 0x7 H Peripheral function H selected 0x8-0xF z Description Reserved Bits 3:0 - PMUXE[3:0]: Peripheral Multiplexing Even These bits select the peripheral function for even-numbered pins (2*n) of a PORT group, if the corresponding PINCFGy.PMUXEN bit is one. Not all possible values for this selection may be valid. For more details, refer to "I/O Multiplexing and Considerations" on page 12. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 397 Table 21-4. Peripheral Multiplexing Even PMUXE[3:0] Name 0x0 A Peripheral function A selected 0x1 B Peripheral function B selected 0x2 C Peripheral function C selected 0x3 D Peripheral function D selected 0x4 E Peripheral function E selected 0x5 F Peripheral function F selected 0x6 G Peripheral function G selected 0x7 H Peripheral function H selected 0x8-0xF Description Reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 398 21.8.13 Pin Configuration n There are up to 32 Pin Configuration registers in each group, one for each I/O line. The n denotes the number of the I/O line, while the x denotes the number of the Port group. Name: PINCFGn Offset: 0x40+n*0x1 [n=0..31]+x*0x80 [x=0..2] Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 DRVSTR 2 1 0 PULLEN INEN PMUXEN Access R R/W R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bit 7 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 6 - DRVSTR: Output Driver Strength Selection This bit controls the output driver strength of an I/O pin configured as an output. 0: Pin drive strength is set to normal drive strength. 1: Pin drive strength is set to stronger drive strength. z Bits 5:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 2 - PULLEN: Pull Enable This bit enables the internal pull-up or pull-down resistor of an I/O pin configured as an input. 0: Internal pull resistor is disabled, and the input is in a high-impedance configuration. 1: Internal pull resistor is enabled, and the input is driven to a defined logic level in the absence of external input. z Bit 1 - INEN: Input Enable This bit controls the input buffer of an I/O pin configured as either an input or output. 0: Input buffer for the I/O pin is disabled, and the input value will not be sampled. 1: Input buffer for the I/O pin is enabled, and the input value will be sampled when required. Writing a zero to this bit disables the input buffer completely, preventing read-back of the physical pin state when the pin is configured as either an input or output. z Bit 0 - PMUXEN: Peripheral Multiplexer Enable This bit enables or disables the peripheral multiplexer selection set in the Peripheral Multiplexing register (PMUXn) to enable or disable alternative peripheral control over an I/O pin direction and output drive value. 0: The peripheral multiplexer selection is disabled, and the PORT registers control the direction and output drive value. 1: The peripheral multiplexer selection is enabled, and the selected peripheral controls the direction and output drive value. Writing a zero to this bit allows the PORT to control the pad direction via the Data Direction register (DIR) and output drive value via the Data Output Value register (OUT). The peripheral multiplexer value in PMUXn is ignored. Writing a one to this bit enables the peripheral selection in PMUXn to control the pad. In this configuration, the physical pin state may still be read from the Data Input Value register (IN) if PINCFGy.INEN is set. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 399 22. EVSYS - Event System 22.1 Overview The Event System (EVSYS) allows autonomous, low-latency and configurable communication between peripherals. Several peripherals can be configured to emit and/or respond to signals known as events. The exact condition to generate an event, or the action taken upon receiving an event, is specific to each module. Peripherals that respond to events are called event users. Peripherals that emit events are called event generators. A peripheral can have one or more event generators and can have one or more event users. Communication is made without CPU intervention and without consuming system resources such as bus or RAM bandwidth. This reduces the load on the CPU and other system resources, compared to a traditional interrupt-based system. 22.2 Features z System for direct peripheral-to-peripheral communication and signaling z 12 configurable event channels, where each channel can: z z Be connected to any event generator Provide a pure asynchronous, resynchronized or synchronous path z 71 event generators z 26 event users z Configurable edge detector z Peripherals can be event generators, event users or both z SleepWalking and interrupt generation while operating in sleep modes z Software event generation z Each event user can choose which event channel to connect to Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 400 22.3 Block Diagram Figure 22-1. Event System Block Diagram EVSYS EVENT CHANNELS PERIPHERALS USER MUX GENERATOR EVENTS PERIPHERALS USERS EVENTS CLOCK REQUESTS GCLK 22.4 Signal Description Not applicable. 22.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 22.5.1 I/O Lines Not applicable. 22.5.2 Power Management The EVSYS can be used to wake up the CPU from all sleep modes, even if the clock used by the EVSYS channel and the EVSYS bus clock are disabled. Refer to "PM - Power Manager" on page 112 for details on the different sleep modes. In all sleep modes where the clock for the EVSYS is stopped, the device can wake up the EVSYS clock. 22.5.3 Clocks The EVSYS bus clock (CLK_EVSYS_APB) can be enabled and disabled in the Power Manager, and the default state of CLK_EVSYS_APB can be found in the Peripheral Clock Masking section in "PM - Power Manager" on page 112. Each EVSYS channel has a dedicated generic clock (GCLK_EVSYS_CHANNELx). These are used for detection and propagation of events for each channel. These clocks must be configured and enabled in the generic clock controller before using the EVSYS. Refer to "Enabling a Generic Clock" on page 94 for details. 22.5.4 DMA Not applicable. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 401 22.5.5 Interrupts The interrupt request line is connected to the interrupt controller. Using the EVSYS interrupts requires the interrupt controller to be configured first. Refer to "Nested Vector Interrupt Controller" on page 29 for details. 22.5.6 Events Not applicable. 22.5.7 Debug Operation When the CPU is halted in debug mode, the EVSYS continues normal operation. If the EVSYS is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 22.5.8 Register Access Protection All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the following register: z Interrupt Flag Status and Clear register (INTFLAG) Write-protection is denoted by the Write-Protected property in the register description. Write-protection does not apply for accesses through an external debugger. Refer to "PAC - Peripheral Access Controller" on page 36 for details. 22.5.9 Analog Connections Not applicable. 22.6 Functional Description 22.6.1 Principle of Operation The EVSYS allows for communication between peripherals via events. Peripherals that respond to events (event users) are connected to multiplexers which have all event channels as input. Each each event channel can be configured to route signals from any peripheral emitting events (event generator) to one or more event users. 22.6.2 Basic Operation 22.6.2.1 Initialization The peripheral that is to act as event generator must be configured to be able to generate events. The peripheral to act as event user must be configured to handle incoming events. When this has been done, the event system is ready to be configured. The configuration must follow this order: 1. Configure the event user by performing a single 16-bit write to the User Multiplexer register (USER) with: 1.1. The channel to be connected to a user is written to the Channel bit group (USER.CHANNEL) 1.2. The user to connect the channel is written to the User bit group (USER.USER) 2. Configure the channel by performing a single 32-bit write to the Channel (CHANNEL) register with: 2.1. The channel to be configured is written to the Channel Selection bit group (CHANNEL.CHANNEL) 2.2. The path to be used is written to the Path Selection bit group (CHANNEL.PATH) 2.3. The type of edge detection to use on the channel is written to the Edge Selection bit group (CHANNEL.EDGSEL) 2.4. The event generator to be used is written to the Event Generator bit group (CHANNEL.EVGEN) 22.6.2.2 Enabling, Disabling and Resetting The EVSYS is always enabled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 402 The EVSYS is reset by writing a one to the Software Reset bit in the Control register (CTRL.SWRST). All registers in the EVSYS will be reset to their initial state and any ongoing events will be canceled. Refer to the CTRL register for details. 22.6.2.3 Channel Path There are three different ways to propagate the event provided by an event generator: z Asynchronous path z Synchronous path z Resynchronized path Figure 22-2. Channel CLOCK_REQUEST_m CHANNEL m SLEEPWALKING DETECTOR ASYNC GENERATORS EVENTS SYNC CHANNEL_EVT_m EDGE DETECTION PERIPHERALS RESYNC CHANNEL.SWEVT CHANNEL.EDGSEL CHANNEL.PATH CHANNEL.EVGEN The path is selected by writing to the Path Selection bit group in the Channel register (CHANNEL.PATH). Asynchronous Path When using the asynchronous path, the events are propagated from the event generator to the event user with no intervention from the event system. This means that if the GCLK_EVSYS_CHANNELx for the channel used is inactive, the event will still be propagated to the user. Events propagated in the asynchronous path cannot generate any interrupts, and no channel status bits will indicate the state of the channel. No edge detection is available; this must be handled in the event user. When the event generator and the event user share the same generic clock, using the asynchronous path will propagate the event with the least amount of latency. Synchronous Path Synchronous path can be used when the event generator and event user share the same generic clock generator and also if event user supports synchronous path. If event user doesn't support synchronous path, asynchronous path has to be selected. If they do not share the same generic clock generator, a logic change from the event generator to the event channel might not be detected in the channel, which means that the event will not be propagated to the event user. When using the synchronous path, the channel is capable of generating interrupts. The channel status bits in the Channel Status register (CHSTATUS) are also updated and available for use. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 403 If the Generic Clocks Request bit in the Control register (CTRL.GCLKREQ) is zero, the channel operates in SleepWalking mode and request the configured generic clock only when an event is to be propagated through the channel. If CTRL.GCLKREQ is one, the generic clock will always be on for the configured channel. Resynchronized Path The resynchronized path should be used when the event generator and the event channel do not share the same generic clock generator. When the resynchronized path is used, resynchronization of the event from the event generator is done in the channel. When the resynchronized path is used, the channel is capable of generating interrupts. The channel status bits in the Channel Status register (CHSTATUS) are also updated and available for use. If the Generic Clocks Request bit in the Control register (CTRL.GCLKREQ) is zero, the channel operates in SleepWalking mode and request the configured generic clock only when an event is to be propagated through the channel. If CTRL.GCLKREQ is one, the generic clock will always be on for the configured channel. 22.6.2.4 User Multiplexer Setup Each user multiplexer is dedicated to one event user. A user multiplexer receives all event channel outputs and must be configured to select one of these channels. The user must always be configured before the channel is configured. A full list of selectable users can be found in the User Multiplexer register (USER) description. Refer to Table 22-6 for details. To configure a user multiplexer, the USER register must be written in a single 16-bit write. It is possible to read out the configuration of a user by first selecting the user by writing to USER.USER using an 8-bit write and then performing a read of the 16-bit USER register. Figure 22-3. User MUX CHANNEL_EVT_0 CHANNEL_EVT_1 CHANNEL_EVT_m USER MUX USER.CHANNEL USER_EVT_x USER_EVT_y PERIPHERAL A USER_EVT_z PERIPHERAL B 22.6.2.5 Channel Setup The channel to be used with an event user must be configured with an event generator. The path of the channel should be configured, and when using a synchronous path or resynchronized path, the edge selection should be configured. All these configurations are available in the Channel register (CHANNEL). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 404 To configure a channel, the Channel register must be written in a single 32-bit write. It is possible to read out the configuration of a channel by first selecting the channel by writing to CHANNEL.CHANNEL using a, 8-bit write, and then performing a read of the CHANNEL register. Event Generators The event generator is selected by writing to the Event Generator bit group in the Channel register (CHANNEL.EVGEN). A full list of selectable generators can be found in the CHANNEL register description. Refer to Table 22-4 for details. The channels are not connected to any of the event generators (CHANNEL.EVGEN = 0x00) by default. 22.6.2.6 Edge Detection When synchronous or resynchronized paths are used, edge detection must be used. The event system can perform edge detection in three different ways: z Generate an event only on the rising edge z Generate an event only on the falling edge z Generate an event on rising and falling edges. Edge detection is selected by writing to the Edge Selection bit group in the Channel register (CHANNEL.EDGSEL). If the generator event is a pulse, both edges cannot be selected. Use the rising edge or falling edge detection methods, depending on the generator event default level. 22.6.2.7 Channel Status The Channel Status register (CHSTATUS) contains the status of the channels when a synchronous or resynchronized path is in use. There are two different status bits in CHSTATUS for each of the available channels: The Channel x Busy bit in the Channel Status register (CHSTATUS.CHBUSYx) is set to one if an event on the corresponding channel x has not been handled by all event users connected to that channel. The CHSTATUS.USRRDYx bit is set to one if all event users connected to the corresponding channel x are ready to handle incoming events on that channel. 22.6.2.8 Software Event A software event can be initiated on a channel by writing a one to the Software Event bit in the Channel register (CHANNEL.SWEVT) at the same time as writing the Channel bits (CHANNEL.CHANNEL). This will generate a software event on the selected channel. The software event can be used for application debugging, and functions like any event generator. To use the software event, the event path must be configured to either a synchronous path or resynchronized path (CHANNEL.PATH = 0x0 or 0x1), edge detection must be configured to rising-edge detection (CHANNEL.EDGSEL= 0x1) and the Generic Clock Request bit must be set to one (CTRL.GCLKREQ=0x1). 22.6.3 Interrupts The EVSYS has the following interrupt sources: z Overrun Channel x (OVRx): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. z Event Detected Channel x (EVDx): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the EVSYS is reset. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 405 See the INTFLAG register for details on how to clear interrupt flags. The EVSYS has one common interrupt request line for all the interrupt sources. The user must read the INTFLAG register to determine which interrupt condition is present. Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to "Nested Vector Interrupt Controller" on page 29 for details. 22.6.3.1 The Overrun Channel x Interrupt The Overrun Channel x interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.OVRx) is set and the optional interrupt is generated in the following two cases: z At least one of the event users on channel x is not ready when a new event occurs. Event user will not be ready if that user is disabled or not able to handle the incoming event. z An event occurs when the previous event on channel x has not yet been handled by all event users. This can happen when an user is handling event slowly which means that a new event is generated when previous one is already pending INTFLAG.OVRx will be set when using a synchronous or resynchronized path, but not when using an asynchronous path. 22.6.3.2 The Event Detected Channel x Interrupt The Event Detected Channel x interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.EVDx) is set when an event coming from the event generator configured on channel x is detected. INTFLAG.EVDx will be set when using a synchronous and resynchronized path, but not when using an asynchronous path. 22.6.4 Sleep Mode Operation The EVSYS can generate interrupts to wake up the device from any sleep mode. Some event generators can generate an event when the system clock is stopped. The generic clock (GCLK_EVSYS_CHANNELx) for this channel will be restarted if the channel uses a synchronized path or a resynchronized path, without waking the system from sleep. The clock remains active only as long as necessary to handle the event. After the event has been handled, the clock will be turned off and the system will remain in the original sleep mode. This is known as SleepWalking. When an asynchronous path is used, there is no need for the clock to be activated for the event to be propagated to the user. On a software reset, all registers are set to their reset values and any ongoing events are canceled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 406 22.7 Register Summary Table 22-1. Register Summary Offset Name Bit Pos. 0x00 CTRL 7:0 0x01 ... 0x03 Reserved 0x04 0x05 0x06 0x09 SWRST 7:0 CHANNEL 0x07 0x08 GCLKREQ CHANNEL[3:0] 15:8 SWEVT 23:16 EVGEN[6:0] 31:24 USER 0x0A Reserved 0x0B Reserved EDGSEL[1:0] 7:0 USER[4:0] 15:8 CHANNEL[4:0] PATH[1:0] 0x0C 7:0 USRRDY7 USRRDY6 USRRDY5 USRRDY4 USRRDY3 USRRDY2 USRRDY1 USRRDY0 0x0D 15:8 CHBUSY7 CHBUSY6 CHBUSY5 CHBUSY4 CHBUSY3 CHBUSY2 CHBUSY1 CHBUSY0 23:16 USRRDY11 USRRDY10 USRRDY9 USRRDY8 31:24 CHBUSY11 CHBUSY10 CHBUSY9 CHBUSY8 0x0E CHSTATUS 0x0F 0x10 7:0 OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0 0x11 15:8 EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0 23:16 OVR11 OVR10 OVR9 OVR8 31:24 EVD11 EVD10 EVD9 EVD8 0x12 INTENCLR 0x13 0x14 7:0 OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0 0x15 15:8 EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0 OVR11 OVR10 OVR9 OVR8 EVD11 EVD10 EVD9 EVD8 OVR3 OVR2 OVR1 OVR0 0x16 INTENSET 23:16 0x17 31:24 0x18 7:0 OVR7 OVR6 OVR5 OVR4 15:8 EVD7 EVD6 EVD5 EVD4 0x19 0x1A 0x1B INTFLAG EVD3 EVD2 EVD1 EVD0 23:16 OVR11 OVR10 OVR9 OVR8 31:24 EVD11 EVD10 EVD9 EVD8 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 407 22.8 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protected property in each individual register description. Refer to "Register Access Protection" on page 402 and "PAC - Peripheral Access Controller" on page 36 for details. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 408 22.8.1 Control Name: CTRL Offset: 0x00 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 GCLKREQ 0 SWRST Access R R R R/W R R R W Reset 0 0 0 0 0 0 0 0 z Bits 7:5 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 4 - GCLKREQ: Generic Clock Requests This bit is used to determine whether the generic clocks used for the different channels should be on all the time or only when an event needs the generic clock. Events propagated through asynchronous paths will not need a generic clock. 0: Generic clock is requested and turned on only if an event is detected. 1: Generic clock for a channel is always on. z Bits 3:1 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 0 - SWRST: Software Reset Writing a `0' to this bit has no effect. Writing a `1' to this bit resets all registers in the EVSYS to their initial state. Note: Before applying a Software Reset it is recommended to disable the event generators. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 409 22.8.2 Channel This register allows the user to configure the channel specified in the CHANNEL bit group. To write to this register, do a single 32-bit write of all the configuration and channel selection data. To read from this register, first do an 8-bit write to the CHANNEL.CHANNEL bit group specifying the channel configuration to be read, and then read the Channel register (CHANNEL). Name: CHANNEL Offset: 0x04 Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 EDGSEL[1:0] 24 PATH[1:0] Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 EVGEN[6:0] Access R R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 SWEVT Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CHANNEL[3:0] Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 31:28 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 27:26 - EDGSEL[1:0]: Edge Detection Selection These bits set the type of edge detection to be used on the channel. These bits must be written to zero when using the asynchronous path. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 410 Table 22-2. Edge Detection Selection z EDGSEL[1:0] Name 0x0 NO_EVT_OUTPUT 0x1 RISING_EDGE 0x2 FALLING_EDGE 0x3 BOTH_EDGES Description No event output when using the resynchronized or synchronous path Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path Bits 25:24 - PATH[1:0]: Path Selection These bits are used to choose the path to be used by the selected channel. The path choice can be limited by the channel source, see Table 22-6. Table 22-3. Path Selection PATH[1:0] Name 0x0 SYNCHRONOUS 0x1 RESYNCHRONIZED 0x2 ASYNCHRONOUS 0x3 Description Synchronous path Resynchronized path Asynchronous path Reserved z Bit 23 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 22:16 - EVGEN[6:0]: Event Generator Selection These bits are used to choose which event generator to connect to the selected channel. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 411 Table 22-4. Event Generator Selection Value Event Generator Description 0x00 NONE No event generator selected 0x01 RTC CMP0 Compare 0 (mode 0 and 1) or Alarm 0 (mode 2) 0x02 RTC CMP1 Compare 1 0x03 RTC OVF Overflow 0x04 RTC PER0 Period 0 0x05 RTC PER1 Period 1 0x06 RTC PER2 Period 2 0x07 RTC PER3 Period 3 0x08 RTC PER4 Period 4 0x09 RTC PER5 Period 5 0x0A RTC PER6 Period 6 0x0B RTC PER7 Period 7 0x0C Reserved 0x0D EIC EXTINT1 External Interrupt 1 0x0E EIC EXTINT2 External Interrupt 2 0x0F EIC EXTINT3 External Interrupt 3 0x10 EIC EXTINT4 External Interrupt 4 0x11 EIC EXTINT5 External Interrupt 5 0x12 EIC EXTINT6 External Interrupt 6 0x13 EIC EXTINT7 External Interrupt 7 0x14 EIC EXTINT8 External Interrupt 8 0x15 EIC EXTINT9 External Interrupt 9 0x16 EIC EXTINT10 External Interrupt 10 0x17 EIC EXTINT11 External Interrupt 11 0x18 EIC EXTINT12 External Interrupt 12 0x19 EIC EXTINT13 External Interrupt 13 0x1A EIC EXTINT14 External Interrupt 14 0x1B EIC EXTINT15 External Interrupt 15 0x1C Reserved 0x1D Reserved 0x1E DMAC CH0 Channel 0 0x1F DMAC CH1 Channel 1 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 412 Table 22-4. Event Generator Selection (Continued) Value Event Generator Description 0x20 DMAC CH2 Channel 2 0x21 DMAC CH3 Channel 3 0x22 TCC0 OVF Overflow 0x23 TCC0 TRG Trig 0x24 TCC0 CNT Counter 0x25 TCC0_MCX0 Match/Capture 0 0x26 TCC0_MCX1 Match/Capture 1 0x27 TCC0_MCX2 Match/Capture 2 0x28 TCC0_MCX3 Match/Capture 3 0x29 TCC1 OVF Overflow 0x2A TCC1 TRG Trig 0x2B TCC1 CNT Counter 0x2C TCC1_MCX0 Match/Capture 0 0x2D TCC1_MCX1 Match/Capture 1 0x2E TCC2 OVF Overflow 0x2F TCC2 TRG Trig 0x30 TCC2 CNT Counter 0x31 TCC2_MCX0 Match/Capture 0 0x32 TCC2_MCX1 Match/Capture 1 0x33 TC3 OVF Overflow/Underflow 0x34 TC3 MC0 Match/Capture 0 0x35 TC3 MC1 Match/Capture 1 0x36 TC4 OVF Overflow/Underflow 0x37 TC4 MC0 Match/Capture 0 0x38 TC4 MC1 Match/Capture 1 0x39 TC5 OVF Overflow/Underflow 0x3A TC5 MC0 Match/Capture 0 0x3B TC5 MC1 Match/Capture 1 0x3C Reserved 0x3D Reserved 0x3E Reserved 0x3F Reserved 0x40 Reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 413 Table 22-4. Event Generator Selection (Continued) Value Event Generator Description 0x41 Reserved 0x42 ADC RESRDY Result Ready 0x43 ADC WINMON Window Monitor 0x44 AC COMP0 Comparator 0 0x45 AC COMP1 Comparator 1 0x46 AC WIN0 Window 0 0x47 Reserved 0x48 PTC EOCReserved End of Conversion 0x49 PTC WCOMPReserved Window Comparator 0x4A AC1 COMP0 Comparator 0 0x4B AC1 COMP1 Comparator 1 0x4C AC1 WIN0 Window 0 0x4AD-0x7F Reserved z Bits 15:9 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 8 - SWEVT: Software Event This bit is used to insert a software event on the channel selected by the CHANNEL.CHANNEL bit group. This bit has the same behavior similar to an event. This bit must be written together with CHANNEL.CHANNELusing a 16-bit write. Writing a zero to this bit has no effect. Writing a one to this bit will trigger a software event for the corresponding channel. This bit will always return zero when read. z Bits 7:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 3:0 - CHANNEL[3:0]: Channel Selection These bits are used to select the channel to be set up or read from. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 414 22.8.3 User Multiplexer This register is used to configure a specified event user. To write to this register, do a single 16-bit write of all the configuration and event user selection data. To read from this register, first do an 8-bit write to the USER.USER bit group specifying the event user configuration to be read, and then read USER. Name: USER Offset: 0x08 Reset: 0x0000 Property: Write-Protected Bit 15 14 13 12 11 10 9 8 CHANNEL[4:0] Access R R R R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 USER[4:0] Access R R R R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 15:13 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 12:8 - CHANNEL[4:0]: Channel Event Selection These bits are used to select the channel to connect to the event user. Note that to select channel n, the value (n+1) must be written to the USER.CHANNEL bit group. Table 22-5. Channel Event Selection CHANNEL[4:0] 0x0 0x1-0xC 0xD-0xFF Channel Number No Channel Output Selected Channel n-1 selected Reserved z Bits 7:5 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 4:0 - USER[4:0]: User Multiplexer Selection These bits select the event user to be configured with a channel, or the event user to read the channel value from. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 415 Table 22-6. User Multiplexer Selection USER[7:0] User Multiplexer Description Path Type 0x00 DMAC CH0 Channel 0 Resynchronized path only 0x01 DMAC CH1 Channel 1 Resynchronized path only 0x02 DMAC CH2 Channel 2 Resynchronized path only 0x03 DMAC CH3 Channel 3 Resynchronized path only 0x04 TCC0 EV0 Asynchronous, synchronous and resynchronized paths 0x05 TCC0 EV1 Asynchronous, synchronous and resynchronized paths 0x06 TCC0 MC0 Match/Capture 0 Asynchronous, synchronous and resynchronized paths 0x07 TCC0 MC1 Match/Capture 1 Asynchronous, synchronous and resynchronized paths 0x08 TCC0 MC2 Match/Capture 2 Asynchronous, synchronous and resynchronized paths 0x09 TCC0 MC3 Match/Capture 3 Asynchronous, synchronous and resynchronized paths 0x0A TCC1 EV0 Asynchronous, synchronous and resynchronized paths 0x0B TCC1 EV1 Asynchronous, synchronous and resynchronized paths 0x0C TCC1 MC0 Match/Capture 0 Asynchronous, synchronous and resynchronized paths 0x0D TCC1 MC1 Match/Capture 1 Asynchronous, synchronous and resynchronized paths 0x0E TCC2 EV0 Asynchronous, synchronous and resynchronized paths 0x0F TCC2 EV1 Asynchronous, synchronous and resynchronized paths 0x10 TCC2 MC0 Match/Capture 0 Asynchronous, synchronous and resynchronized paths 0x11 TCC2 MC1 Match/Capture 1 Asynchronous, synchronous and resynchronized paths 0x12 TC3 Asynchronous, synchronous and resynchronized paths 0x13 TC4 Asynchronous, synchronous and resynchronized paths 0x14 TC5 Asynchronous, synchronous and resynchronized paths 0x15 Reserved Reserved 0x16 Reserved Reserved 0x17 ADC START ADC start conversion Asynchronous path only 0x18 ADC SYNC Flush ADC Asynchronous path only 0x19 AC COMP0 Start comparator 0 Asynchronous path only 0x1A AC COMP1 Start comparator 1 Asynchronous path only 0x1B Reserved 0x1C PTC STCONVReserved PTC start conversion Asynchronous path onlyReserved 0x1D AC1 COMP0 Start comparator 0 Asynchronous path only 0x1E AC1 COMP1 Start comparator 1 Asynchronous path only 0x1D-0x1F Reserved Reserved Reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 416 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 417 22.8.4 Channel Status Name: CHSTATUS Offset: 0x0C Reset: 0x000F00FF Property: - Bit 31 30 29 28 27 26 25 24 CHBUSY11 CHBUSY10 CHBUSY9 CHBUSY8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 USRRDY11 USRRDY10 USRRDY9 USRRDY8 Access R R R R R R R R Reset 0 0 0 0 1 1 1 1 Bit 15 14 13 12 11 10 9 8 CHBUSY7 CHBUSY6 CHBUSY5 CHBUSY4 CHBUSY3 CHBUSY2 CHBUSY1 CHBUSY0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 USRRDY7 USRRDY6 USRRDY5 USRRDY4 USRRDY3 USRRDY2 USRRDY1 USRRDY0 Access R R R R R R R R Reset 1 1 1 1 1 1 1 1 z Bits 31:28 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 27:24 - CHBUSYx [x=11..8]: Channel x Busy This bit is cleared when channel x is idle This bit is set if an event on channel x has not been handled by all event users connected to channel x. z Bits 23:20 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 19:16 - USRRDYx [x=11..8]: Channel x User Ready This bit is cleared when at least one of the event users connected to the channel is not ready. This bit is set when all event users connected to channel x are ready to handle incoming events on channel x. z Bits 15:8 - CHBUSYx [x=7..0]: Channel x Busy This bit is cleared when channel x is idle This bit is set if an event on channel x has not been handled by all event users connected to channel x. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 418 z Bits 7:0 - USRRDYx [x=7..0]: Channel x User Ready This bit is cleared when at least one of the event users connected to the channel is not ready. This bit is set when all event users connected to channel x are ready to handle incoming events on channel x. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 419 22.8.5 Interrupt Enable Clear This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Name: INTENCLR Offset: 0x10 Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 EVD11 EVD10 EVD9 EVD8 Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 OVR11 OVR10 OVR9 OVR8 Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0 R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Access Access Reset z Bits 31:28 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 27:24 - EVDx [x=11..8]: Channel x Event Detection Interrupt Enable 0: The Event Detected Channel x interrupt is disabled. 1: The Event Detected Channel x interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Event Detected Channel x Interrupt Enable bit, which disables the Event Detected Channel x interrupt. z Bits 23:20 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 19:16 - OVRx [x=11..8]: Channel x Overrun Interrupt Enable 0: The Overrun Channel x interrupt is disabled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 420 1: The Overrun Channel x interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Overrun Channel x Interrupt Enable bit, which disables the Overrun Channel x interrupt. z Bits 15:8 - EVDx [x=7..0]: Channel x Event Detection Interrupt Enable 0: The Event Detected Channel x interrupt is disabled. 1: The Event Detected Channel x interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Event Detected Channel x Interrupt Enable bit, which disables the Event Detected Channel x interrupt. z Bits 7:0 - OVRx [x=7..0]: Channel x Overrun Interrupt Enable 0: The Overrun Channel x interrupt is disabled. 1: The Overrun Channel x interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Overrun Channel x Interrupt Enable bit, which disables the Overrun Channel x interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 421 22.8.6 Interrupt Enable Set This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Name: INTENSET Offset: 0x14 Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 EVD11 EVD10 EVD9 EVD8 Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 OVR11 OVR10 OVR9 OVR8 Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0 R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Access Access Reset z Bits 31:28 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 27:24 - EVDx [x=11..8]: Channel x Event Detection Interrupt Enable 0: The Event Detected Channel x interrupt is disabled. 1: The Event Detected Channel x interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Event Detected Channel x Interrupt Enable bit, which enables the Event Detected Channel x interrupt. z Bits 23:20 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 19:16 - OVRx [x=11..8]: Channel x Overrun Interrupt Enable 0: The Overrun Channel x interrupt is disabled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 422 1: The Overrun Channel x interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Overrun Channel x Interrupt Enable bit, which enables the Overrun Channel x interrupt. z Bits 15:8 - EVDx [x=7..0]: Channel x Event Detection Interrupt Enable 0: The Event Detected Channel x interrupt is disabled. 1: The Event Detected Channel x interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Event Detected Channel x Interrupt Enable bit, which enables the Event Detected Channel x interrupt. z Bits 7:0 - OVRx [x=7..0]: Channel x Overrun Interrupt Enable 0: The Overrun Channel x interrupt is disabled. 1: The Overrun Channel x interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Overrun Channel x Interrupt Enable bit, which enables the Overrun Channel x interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 423 22.8.7 Interrupt Flag Status and Clear Name: INTFLAG Offset: 0x18 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 EVD11 EVD10 EVD9 EVD8 Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 OVR11 OVR10 OVR9 OVR8 Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0 R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Access Access Reset z Bits 31:28 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 27:24 - EVDx [x=11..8]: Channel x Event Detection This flag is set on the next CLK_EVSYS_APB cycle when an event is being propagated through the channel, and an interrupt request will be generated if INTENCLR/SET.EVDx is one. When the event channel path is asynchronous, the EVDx interrupt flag will not be set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Event Detected Channel n interrupt flag. z Bits 23:20 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 19:16 - OVRx [x=11..8]: Channel x Overrun This flag is set on the next CLK_EVSYS cycle after an overrun channel condition occurs, and an interrupt request will be generated if INTENCLR/SET.OVRx is one. When the event channel path is asynchronous, the OVRx interrupt flag will not be set. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 424 Writing a zero to this bit has no effect. Writing a one to this bit will clear the Overrun Channel x interrupt flag. z Bits 15:8 - EVDx [x=7..0]: Channel x Event Detection This flag is set on the next CLK_EVSYS_APB cycle when an event is being propagated through the channel, and an interrupt request will be generated if INTENCLR/SET.EVDx is one. When the event channel path is asynchronous, the EVDx interrupt flag will not be set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Event Detected Channel n interrupt flag. z Bits 7:0 - OVRx [x=7..0]: Channel x Overrun This flag is set on the next CLK_EVSYS cycle after an overrun channel condition occurs, and an interrupt request will be generated if INTENCLR/SET.OVRx is one. When the event channel path is asynchronous, the OVRx interrupt flag will not be set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Overrun Channel x interrupt flag. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 425 23. SERCOM - Serial Communication Interface 23.1 Overview The serial communication interface (SERCOM) can be configured to support a number of modes; I2C, SPI, and USART. Once configured and enabled, all SERCOM resources are dedicated to the selected mode. The SERCOM serial engine consists of a transmitter and receiver, baud-rate generator and address matching functionality. It can be configured to use the internal generic clock or an external clock, making operation in all sleep modes possible. 23.2 Features z Combined interface configurable as one of the following: I2C - Two-wire serial interface z SMBusTM compatible. z SPI - Serial peripheral interface z USART - Universal synchronous and asynchronous serial receiver and transmitter z z Single transmit buffer and double receive buffer z Baud-rate generator z Address match/mask logic z Operational in all sleep modes z Can be used with DMA 23.3 Block Diagram Figure 23-1. SERCOM Block Diagram SERCOM Register Interface CONTROL/STATUS Mode Specific TX/RX DATA BAUD/ADDR Serial Engine Mode n Mode 1 Baud Rate Generator Transmitter PAD[3:0] Mode 0 Address Match Receiver 23.4 Signal Description See the respective SERCOM mode chapters for details: z "SERCOM USART - SERCOM Universal Synchronous and Asynchronous Receiver and Transmitter" on page 434 z "SERCOM SPI - SERCOM Serial Peripheral Interface" on page 472 z "SERCOM I2C - SERCOM Inter-Integrated Circuit" on page 505 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 426 23.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 23.5.1 I/O Lines Using the SERCOM I/O lines requires the I/O pins to be configured using port configuration (PORT). Refer to "PORT" on page 373 for details. From Figure 23-1 one can see that the SERCOM has four internal pads, PAD[3:0]. The signals from I2C, SPI and USART are routed through these SERCOM pads via a multiplexer. The configuration of the multiplexer is available from the different SERCOM modes. Refer to the mode specific chapters for details: z "SERCOM USART - SERCOM Universal Synchronous and Asynchronous Receiver and Transmitter" on page 434 z "SERCOM SPI - SERCOM Serial Peripheral Interface" on page 472 z "SERCOM I2C - SERCOM Inter-Integrated Circuit" on page 505 23.5.2 Power Management The SERCOM can operate in any sleep mode.SERCOM interrupts can be used to wake up the device from sleep modes. Refer to "PM - Power Manager" on page 112 for details on the different sleep modes. 23.5.3 Clocks The SERCOM bus clock (CLK_SERCOMx_APB) is enabled by default, and can be enabled and disabled in the Power Manager. Refer to "PM - Power Manager" on page 112 for details. Two generic clocks are used by the SERCOM: GCLK_SERCOMx_CORE and GCLK_SERCOMx_SLOW. The core clock (GCLK_SERCOMx_CORE) is required to clock the SERCOM while operating as a master, while the slow clock (GCLK_SERCOMx_SLOW) is only required for certain functions. See specific mode chapters for details. These clocks must be configured and enabled in the Generic Clock Controller (GCLK) before using the SERCOM. Refer to "GCLK - Generic Clock Controller" on page 90 for details. These generic clocks are asynchronous to the user interface clock (CLK_SERCOMx_APB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. Refer to "Synchronization" on page 433 for further details. 23.5.4 DMA The DMA request lines are connected to the DMA controller (DMAC). Using the SERCOM DMA requests, requires the DMA controller to be configured first. Refer to "DMAC - Direct Memory Access Controller" on page 267 for details. 23.5.5 Interrupts The interrupt request line is connected to the Interrupt Controller. Using the SERCOM interrupts requires the Interrupt Controller to be configured first. Refer to "Nested Vector Interrupt Controller" on page 29 for details. 23.5.6 Events Not applicable. 23.5.7 Debug Operation When the CPU is halted in debug mode, the SERCOM continues normal operation. If the SERCOM is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. The SERCOM can be forced to halt operation during debugging. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 427 23.5.8 Register Access Protection All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the following registers: z Interrupt Flag Status and Clear register (INTFLAG) z Address register (ADDR) z Data register (DATA) Write-protection is denoted by the Write-Protection property in the register description. When the CPU is halted in debug mode, all write-protection is automatically disabled. Refer to "PAC - Peripheral Access Controller" on page 36 for details. 23.5.9 Analog Connections Not applicable. 23.6 Functional Description 23.6.1 Principle of Operation The basic structure of the SERCOM serial engine is shown in Figure 23-2. Fields shown in capital letters are synchronous to the system clock and accessible by the CPU, while fields with lowercase letters can be configured to run on the GCLK_SERCOMx_CORE clock or an external clock. Figure 23-2. SERCOM Serial Engine Transmitter Selectable Internal Clk (GCLK) Ext Clk BAUD Address Match TX DATA ADDR/ADDRMASK baud rate generator 1/- /2- /16 tx shift register Receiver rx shift register == status Baud Rate Generator STATUS rx buffer RX DATA The transmitter consists of a single write buffer and a shift register. The receiver consists of a two-level receive buffer and a shift register. The baud-rate generator is capable of running on the GCLK_SERCOMx_CORE clock or an external clock. Address matching logic is included for SPI and I2C operation. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 428 23.6.2 Basic Operation 23.6.2.1 Initialization The SERCOM must be configured to the desired mode by writing to the Operating Mode bits in the Control A register (CTRLA.MODE). Refer to Figure 23-1 for details. Table 23-1. SERCOM Modes CTRLA.MODE Description 0x0 USART with external clock 0x1 USART with internal clock 0x2 SPI in slave operation 0x3 SPI in master operation 0x4 I2C slave operation 0x5 I2C master operation 0x6-0x7 Reserved For further initialization information, see the respective SERCOM mode chapters. 23.6.2.2 Enabling, Disabling and Resetting The SERCOM is enabled by writing a one to the Enable bit in the Control A register (CTRLA.ENABLE). The SERCOM is disabled by writing a zero to CTRLA.ENABLE. The SERCOM is reset by writing a one to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in the SERCOM, except DBGCTRL, will be reset to their initial state, and the SERCOM will be disabled. Refer to the CTRLA register descriptions for details. 23.6.2.3 Clock Generation - Baud-Rate Generator The baud-rate generator, as shown in Figure 23-3, is used for internal clock generation for asynchronous and synchronous communication. The generated output frequency (fBAUD) is determined by the Baud register (BAUD) setting and the baud reference frequency (fREF). The baud reference clock is the serial engine clock, and it can be internal or external. For asynchronous operation, the /16 (divide-by-16) output is used when transmitting and the /1 (divide-by-1) output is used when receiving. For synchronous operation the /2 (divide-by-2) output is used. This functionality is automatically configured, depending on the selected operating mode. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 429 Figure 23-3. Baud Rate Generator Selectable Internal Clk (GCLK) Baud Rate Generator 1 Ext Clk fref Base Period 0 /2 /1 CTRLA.MODE[0] /8 /2 /16 0 Tx Clk 1 1 CTRLA.MODE 0 1 Clock Recovery Rx Clk 0 Table 23-2 contains equations for calculating the baud rate (in bits per second) and for calculating the BAUD register value for each mode of operation. For asynchronous operation there are two different modes. Using the arithmetic mode, the BAUD register value is 16 bits (0 to 65,535). Using the fractional mode, the BAUD register is 13 bits, while the fractional adjustment is 3 bits. In this mode the BAUD setting must be greater than or equal to 1. For synchronous mode, the BAUD register value is 8 bits (0 to 255). Table 23-2. Baud Rate Equations Operating Mode Asynchronous Arithmetic Asynchronous Fractional Synchronous Condition f f f BAUD BAUD BAUD Baud Rate (Bits Per Second) f REF S f REF S f REF 2 f f f BAUD BAUD BAUD = = = f REF S BAUD Register Value Calculation (1 - BAUD / 65,536 ) f REF S ( BAUD + ( FP / 8)) f BAUD = 65,5361 - S BAUD = BAUD = REF 2( BAUD + 1) f - REF Sx f f 2 f REF BAUD f f BAUD REF FP 8 -1 BAUD S - Number of samples per bit. Can be 16, 8, or 3. The Asynchronous Fractional option is used for auto-baud detection. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 430 The baud rate error is represented by the following formula: ExpectedBaudRate Error = 1 - ActualBaudRate Asynchronous Arithmetic Mode BAUD Value Selection The formula given for fBAUD calculates the average frequency over 65,536 fREF cycles. Although the BAUD register can be set to any value between 0 and 65,536, the values that will change the average frequency of fBAUD over a single frame are more constrained. The BAUD register values that will affect the average frequency over a single frame lead to an integer increase in the cycles per frame (CPF) CPF = f f REF (D + S ) BAUD where z D represent the data bits per frame z S represent the sum of start and first stop bits, if present Table 23-3 shows the BAUD register value versus baud frequency at a serial engine frequency of 48MHz. This assumes a D value of 8 bits and an S value of 2 bits (10 bits, including start and stop bits). Table 23-3. BAUD Register Value vs. Baud Frequency BAUD Register Value Serial Engine CPF fBAUD at 48MHz Serial Engine Frequency (fREF) 0 - 406 160 3MHz 407 - 808 161 2.981MHz 809 - 1205 162 2.963MHz 65206 31775 15.11kHz 65207 31871 15.06kHz 65208 31969 15.01kHz ... Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 431 23.6.3 Additional Features 23.6.3.1 Address Match and Mask The SERCOM address match and mask feature is capable of matching one address with a mask, two unique addresses or a range of addresses, based on the mode selected. The match uses seven or eight bits, depending on the mode. Address With Mask An address written to the Address bits in the Address register (ADDR.ADDR) with a mask written to the Address Mask bits in the Address register (ADDR.ADDRMASK) will yield an address match. All bits that are masked are not included in the match. Note that setting the ADDR.ADDRMASK to all zeros will match a single unique address, while setting ADDR.ADDRMASK to all ones will result in all addresses being accepted. Figure 23-4. Address With Mask ADDR ADDRMASK == Match rx shift register Two Unique Addresses The two addresses written to ADDR and ADDRMASK will cause a match. Figure 23-5. Two Unique Addresses ADDR == Match rx shift register == ADDRMASK Address Range The range of addresses between and including ADDR.ADDR and ADDR.ADDRMASK will cause a match. ADDR.ADDR and ADDR.ADDRMASK can be set to any two addresses, with ADDR.ADDR acting as the upper limit and ADDR.ADDRMASK acting as the lower limit. Figure 23-6. Address Range ADDRMASK rx shift register ADDR == Match 23.6.4 DMA Operation Not applicable. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 432 23.6.5 Interrupts Interrupt sources are mode-specific. See the respective SERCOM mode chapters for details. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the SERCOM is reset. See the register description for details on how to clear interrupt flags. The SERCOM has one common interrupt request line for all the interrupt sources. The user must read the INTFLAG register to determine which interrupt condition is present. Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to "Nested Vector Interrupt Controller" on page 29 for details. 23.6.6 Events Not applicable. 23.6.7 Sleep Mode Operation The peripheral can operate in any sleep mode where the selected serial clock is running. This clock can be external or generated by the internal baud-rate generator. The SERCOM interrupts can be used to wake up the device from sleep modes. Refer to the different SERCOM mode chapters for details. 23.6.8 Synchronization Due to the asynchronicity between CLK_SERCOMx_APB and GCLK_SERCOMx_CORE, some registers must be synchronized when accessed. A register can require: z Synchronization when written z Synchronization when read z Synchronization when written and read z No synchronization When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. The Synchronization Ready interrupt can be used to signal when synchronization is complete. If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is stalled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 433 24. SERCOM USART - SERCOM Universal Synchronous and Asynchronous Receiver and Transmitter 24.1 Overview The universal synchronous and asynchronous receiver and transmitter (USART) is one of the available modes in the Serial Communication Interface (SERCOM). Refer to "SERCOM - Serial Communication Interface" on page 426 for details. The USART uses the SERCOM transmitter and receiver configured as shown in Figure 24-1. Fields shown in capital letters are synchronous to the CLK_SERCOMx_APB and accessible by the CPU, while fields with lowercase letters can be configured to run on the internal generic clock or an external clock. The transmitter consists of a single write buffer, a shift register and control logic for handling different frame formats. The write buffer allows continuous data transmission without any delay between frames. The receiver consists of a two-level receive buffer and a shift register. Status information for the received data is available for error checking. Data and clock recovery units ensure robust synchronization and noise filtering during asynchronous data reception. 24.2 Features z Full-duplex operation z Asynchronous (with clock reconstruction) or synchronous operation z Internal or external clock source for asynchronous and synchronous operation z Baud-rate generator z Supports serial frames with 5, 6, 7, 8 or 9 data bits and 1 or 2 stop bits z Odd or even parity generation and parity check z Selectable LSB- or MSB-first data transfer z Buffer overflow and frame error detection z Noise filtering, including false start-bit detection and digital low-pass filter z Collision detection z Can operate in all sleep modes z Operation at speeds up to half the system clock for internally generated clocks z Operation at speeds up to the system clock for externally generated clocks z RTS and CTS flow control z IrDA modulation and demodulation up to 115.2 kbps z LIN slave support z Auto-baud and break character detection z Start-of-frame detection z Can be used with DMA Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 434 24.3 Block Diagram Figure 24-1. USART Block Diagram BAUD Internal Clk (GCLK) TX DATA baud rate generator /1 - /2 - /16 tx shift register TxD rx shift register RxD XCK Signal name 24.4 status rx buffer STATUS RX DATA Signal Description Signal Name Type Description PAD[3:0] Digital I/O General SERCOM pins Please refer to "I/O Multiplexing and Considerations" on page 12 for details on the pin mapping for this peripheral. One signal can be mapped on several pins. 24.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 24.5.1 I/O Lines Using the USART's I/O lines requires the I/O pins to be configured using port configuration (PORT). Refer to "PORT" on page 373 for details. When the SERCOM is used in USART mode, the pins should be configured according to Table 24-1. If the receiver or transmitter is disabled, these pins can be used for other purposes. Table 24-1. USART Pin Configuration Pin Pin Configuration TxD Output RxD Input XCK Output or input Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 435 The combined configuration of PORT and the Transmit Data Pinout and Receive Data Pinout bit groups (refer to the Control A register description) will define the physical position of the USART signals in Table 24-1. 24.5.2 Power Management The USART can continue to operate in any sleep mode where the selected source clock is running. The USART interrupts can be used to wake up the device from sleep modes. The events can trigger other operations in the system without exiting sleep modes. Refer to "PM - Power Manager" on page 112 for details on the different sleep modes. 24.5.3 Clocks The SERCOM bus clock (CLK_SERCOMx_APB, where x represents the specific SERCOM instance number) can be enabled and disabled in the Power Manager, and the default state of CLK_SERCOMx_APB can be found in the Peripheral Clock Masking section in "PM - Power Manager" on page 112. A generic clock (GCLK_SERCOMx_CORE) is required to clock the SERCOMx_CORE. This clock must be configured and enabled in the Generic Clock Controller before using the SERCOMx_CORE. Refer to "GCLK - Generic Clock Controller" on page 90 for details. This generic clock is asynchronous to the bus clock (CLK_SERCOMx_APB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. Refer to "Synchronization" on page 446 for further details. 24.5.4 DMA The DMA request lines are connected to the DMA controller (DMAC). Using the SERCOM DMA requests, requires the DMA controller to be configured first. Refer to "DMAC - Direct Memory Access Controller" on page 267 for details.. 24.5.5 Interrupts The interrupt request line is connected to the Interrupt Controller. Using the USART interrupts requires the Interrupt Controller to be configured first. Refer to "Nested Vector Interrupt Controller" on page 29 for details. 24.5.6 Events Not applicable. 24.5.7 Debug Operation When the CPU is halted in debug mode, the USART continues normal operation. If the USART is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. The USART can be forced to halt operation during debugging. Refer to DBGCTRL for details. 24.5.8 Register Access Protection All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the following registers: z Interrupt Flag Status and Clear register (INTFLAG) z Status register (STATUS) z Data register (DATA) Write-protection is denoted by the Write-Protection property in the register description. When the CPU is halted in debug mode, all write-protection is automatically disabled. Write-protection does not apply for accesses through an external debugger. Refer to "PAC - Peripheral Access Controller" on page 36 for details. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 436 24.5.9 Analog Connections Not applicable. 24.6 Functional Description 24.6.1 Principle of Operation The USART uses three communication lines for data transfer: z RxD for receiving z TxD for transmitting z XCK for the transmission clock in synchronous operation USART data transfer is frame based, where a serial frame consists of: z 1 start bit z 5, 6, 7, 8 or 9 data bits z MSB or LSB first z No, even or odd parity bit z 1 or 2 stop bits A frame starts with the start bit followed by one character of data bits. If enabled, the parity bit is inserted after the data bits and before the first stop bit. One frame can be directly followed by a new frame, or the communication line can return to the idle (high) state. Figure 24-2 illustrates the possible frame formats. Bits inside brackets are optional. Figure 24-2. Frame Formats Frame (IDLE) St 0 1 2 3 4 [5] [6] [7] [8] [P] Sp1 [Sp2] (St/IDLE) St Start bit; always low (n) Data bits; 0 to 8 P Parity bit; odd or even Sp Stop bit; always high IDLE No transfers on the communication line; always high in this state 24.6.2 Basic Operation 24.6.2.1 Initialization The following registers are enable-protected, meaning they can only be written when the USART is disabled (CTRL.ENABLE is zero): z Control A register (CTRLA), except the Enable (ENABLE) and Software Reset (SWRST) bits z Control B register (CTRLB), except the Receiver Enable (RXEN) and Transmitter Enable (TXEN) bits z Baud register (BAUD) Any writes to these registers when the USART is enabled or is being enabled (CTRL.ENABLE is one) will be discarded. Writes to these registers) while the peripheral is being disabled will be completed after the disabling is complete. Before the USART is enabled, it must be configured, as outlined in the following steps: z USART mode with external or internal clock must be selected first by writing 0x0 or 0x1 to the Operating Mode bit group in the Control A register (CTRLA.MODE) Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 437 z Communication mode (asynchronous or synchronous) must be selected by writing to the Communication Mode bit in the Control A register (CTRLA.CMODE) z SERCOM pad to use for the receiver must be selected by writing to the Receive Data Pinout bit group in the Control A register (CTRLA.RXPO) z SERCOM pads to use for the transmitter and external clock must be selected by writing to the Transmit Data Pinout bit in the Control A register (CTRLA.TXPO) z Character size must be selected by writing to the Character Size bit group in the Control B register (CTRLB.CHSIZE) z MSB- or LSB-first data transmission must be selected by writing to the Data Order bit in the Control A register (CTRLA.DORD) z When parity mode is to be used, even or odd parity must be selected by writing to the Parity Mode bit in the Control B register (CTRLB.PMODE) and enabled by writing 0x1 to the Frame Format bit group in the Control A register (CTRLA.FORM) z Number of stop bits must be selected by writing to the Stop Bit Mode bit in the Control B register (CTRLB.SBMODE) z When using an internal clock, the Baud register (BAUD) must be written to generate the desired baud rate z The transmitter and receiver can be enabled by writing ones to the Receiver Enable and Transmitter Enable bits in the Control B register (CTRLB.RXEN and CTRLB.TXEN) 24.6.2.2 Enabling, Disabling and Resetting The USART is enabled by writing a one to the Enable bit in the Control A register (CTRLA.ENABLE). The USART is disabled by writing a zero to CTRLA.ENABLE. The USART is reset by writing a one to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in the USART, except DBGCTRL, will be reset to their initial state, and the USART will be disabled. Refer to the CTRLA register for details. 24.6.2.3 Clock Generation and Selection For both synchronous and asynchronous modes, the clock used for shifting and sampling data can be generated internally by the SERCOM baud-rate generator or supplied externally through the XCK line. Synchronous mode is selected by writing a one to the Communication Mode bit in the Control A register (CTRLA.CMODE) and asynchronous mode is selected by writing a zero to CTRLA.CMODE. The internal clock source is selected by writing 0x1 to the Operation Mode bit group in the Control A register (CTRLA.MODE) and the external clock source is selected by writing 0x0 to CTRLA.MODE. The SERCOM baud-rate generator is configured as shown in Figure 24-3. When CTRLA.CMODE is zero, the baud-rate generator is automatically set to asynchronous mode and the 16-bit Baud register value is used. When CTRLA.CMODE is one, the baud-rate generator is automatically set to synchronous mode and the eight LSBs of the Baud register are used. Refer to "Clock Generation - Baud-Rate Generator" on page 429 for details on configuring the baud rate. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 438 Figure 24-3. Clock Generation Internal C lk (G C LK ) B au d R ate G enerator 1 0 B ase Period C T R LA .M O D E [0] /2 /1 /8 /2 /16 0 Tx C lk 1 1 XCK C TR LA .C M O D E 0 1 R x C lk 0 Synchronous Clock Operation When synchronous mode is used, the CTRLA.MODE bit group controls whether the transmission clock (XCK line) is an input or output. The dependency between the clock edges and data sampling or data change is the same for internal and external clocks. Data input on the RxD pin is sampled at the opposite XCK clock edge as data is driven on the TxD pin. The Clock Polarity bit in the Control A register (CTRLA.CPOL) selects which XCK clock edge is used for RxD sampling and which is used for TxD change. As shown in Figure 24-4, when CTRLA.CPOL is zero, the data will be changed on the rising XCK edge and sampled on the falling XCK edge. If CTRLA.CPOL is one, the data will be changed on the falling edge of XCK and sampled on the rising edge of XCK. Figure 24-4. Synchronous Mode XCK Timing Change XCK CTRLA.CPOL=1 RxD / TxD Sample Change XCK CTRLA.CPOL=0 RxD / TxD Sample When the clock is provided through XCK (CTRLA.MODE is 0x0), the shift registers operate directly on the XCK clock. This means that XCK is not synchronized with the system clock and, therefore, can operate at frequencies up to the system frequency. 24.6.2.4 Data Register The USART Transmit Data register (TxDATA) and USART Receive Data register(RxDATA) share the same I/O address, referred to as the Data register (DATA). Writing the DATA register will update the Transmit Data register. Reading the DATA register will return the contents of the Receive Data register. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 439 24.6.2.5 Data Transmission A data transmission is initiated by loading the DATA register with the data to be sent. The data in TxDATA is moved to the shift register when the shift register is empty and ready to send a new frame. When the shift register is loaded with data, one complete frame will be transmitted. The Transmit Complete interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC) is set, and the optional interrupt is generated, when the entire frame plus stop bit(s) have been shifted out and there is no new data written to the DATA register. The DATA register should only be written when the Data Register Empty flag in the Interrupt Flag Status and Clear register (INTFLAG.DRE) is set, which indicates that the register is empty and ready for new data. Disabling the Transmitter Disabling the transmitter will not become effective until any ongoing and pending transmissions are completed, i.e., when the transmit shift register and TxDATA do not contain data to be transmitted. The transmitter is disabled by writing a zero to the Transmitter Enable bit in the Control B register (CTRLB.TXEN). 24.6.2.6 Data Reception The receiver starts data reception when a valid start bit is detected. Each bit that follows the start bit will be sampled at the baud rate or XCK clock, and shifted into the receive shift register until the first stop bit of a frame is received. When the first stop bit is received and a complete serial frame is present in the receive shift register, the contents of the shift register will be moved into the two-level receive buffer. The Receive Complete interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.RXC) is set, and the optional interrupt is generated. A second stop bit will be ignored by the receiver. The received data can be read by reading the DATA register. DATA should not be read unless the Receive Complete interrupt flag is set. Disabling the Receiver Disabling the receiver by writing a zero to the Receiver Enable bit in the Control B register (CTRLB.RXEN) will flush the two-level receive buffer, and data from ongoing receptions will be lost. Error Bits The USART receiver has three error bits. The Frame Error (FERR), Buffer Overflow (BUFOVF) and Parity Error (PERR) bits can be read from the Status (STATUS) register. Upon error detection, the corresponding bit will be set until it is cleared by writing a one to it. These bits are also automatically cleared when the receiver is disabled. There are two methods for buffer overflow notification. When the immediate buffer overflow notification bit (CTRLA.IBON) is set, STATUS.BUFOVF is raised immediately upon buffer overflow. Software can then empty the receive FIFO by reading RxDATA until the receive complete interrupt flag (INTFLAG.RXC) goes low. When CTRLA.IBON is zero, the buffer overflow condition travels with data through the receive FIFO. After the received data is read, STATUS.BUFOVF will be set along with INTFLAG.RXC. Asynchronous Data Reception The USART includes a clock recovery and data recovery unit for handling asynchronous data reception. The clock recovery logic is used to synchronize the incoming asynchronous serial frames at the RxD pin to the internally generated baud-rate clock. The data recovery logic samples and applies a low-pass filter to each incoming bit, thereby improving the noise immunity of the receiver. The asynchronous reception operational range depends on the accuracy of the internal baud-rate clock, the rate of the incoming frames and the frame size (in number of bits). Asynchronous Operational Range The operational range of the receiver depends on the difference between the received bit rate and the internally generated baud rate. If the baud rate of an external transmitter is too high or too low compared to the internally generated baud rate, the receiver will not be able to synchronize the frames to the start bit. There are two possible sources for a mismatch in baud rate. The reference clock will always have some minor instability. In addition, the baud-rate generator can not always do an exact division of the reference clock frequency to get the baud Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 440 rate desired. In this case, the BAUD register value should be selected to give the lowest possible error. Refer to "Asynchronous Arithmetic Mode BAUD Value Selection" on page 431 for details. Recommended maximum receiver baud-rate errors for various character sizes are shown in the table below. Table 24-2. Asynchronous Receiver Error for x16 Oversampling D (Data bits + Parity) RSLOW(%) RFAST(%) Max Total Error (%) Recommended Max Rx Error (%) 5 94.12 107.69 +5.88/-7.69 2.5 6 94.92 106.67 +5.08/-6.67 2.0 7 95.52 105.88 +4.48/-5.88 2.0 8 96.00 105.26 +4.00/-5.26 2.0 9 96.39 104.76 +3.61/-4.76 1.5 10 96.70 104.35 +3.30/-4.35 1.5 The recommended maximum receiver baud-rate error assumes that the receiver and transmitter equally divide the maximum total error. The following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate: R SLOW = 16( D + 1) 16( D + 1) + 6 R FAST = 16( D + 2) 16( D + 1) + 8 where: z S is the number of samples per bit (S = 16, 8 or 3) z SF is the first sample number used for majority voting (SF = 7, 3, or 2) when CTRLA.SAMPA=0. z SM is the middle sample number used for majority voting (SM = 8, 4, or 2) when CTRLA.SAMPA=0. z D is the sum of character size and parity size (D = 5 to 10 bits) z RSLOW is the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate z RFAST is the ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate 24.6.3 Additional Features 24.6.3.1 Parity Even or odd parity can be selected for error checking by writing 0x1 to the Frame Format bit group in the Control A register (CTRLA.FORM). If even parity is selected by writing a zero to the Parity Mode bit in the Control B register (CTRLB.PMODE), the parity bit of the outgoing frame is set to one if the number of data bits that are one is odd (making the total number of ones even). If odd parity is selected by writing a one to CTRLB.PMODE, the parity bit of the outgoing frame is set to one if the number of data bits that are one is even (making the total number of ones odd). When parity checking is enabled, the parity checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit of the corresponding frame. If a parity error is detected, the Parity Error bit in the Status register (STATUS.PERR) is set. 24.6.3.2 Hardware Handshaking The USART features an out-of-band hardware handshaking flow control mechanism, implemented by connecting the RTS and CTS pins with the remote device, as shown in Figure 24-5. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 441 Figure 24-5. Connection with a Remote Device for Hardware Handshaking USART Remote Device TXD RXD RXD TXD CTS RTS CTS RTS Hardware handshaking is only available with the following configuration: z USART with internal clock (CTRLA.MODE = 1). z Asynchronous mode (CTRLA.CMODE = 0). z Flow control pinout (CTRLA.TXPO = 2). The receiver drives its RTS pin high when disabled, or when the receive FIFO is full. This indicates to the remote device that it must stop transmitting after the ongoing transmission is complete. Enabling and disabling the receiver by writing RXEN will set/clear the RTS pin after a synchronization delay. When the receive FIFO goes full, RTS is immediately set and the frame that is currently being received will be stored in the shift register until the receive FIFO is no longer full. Figure 24-6. Receiver Behavior when Operating with Hardware Handshaking RXD RXEN RTS Rx FIFO Full The current CTS level is available in the STATUS register (STATUS.CTS). Character transmission will only start if CTS is low. When CTS goes high, the transmitter will stop transmitting after the ongoing transmission is complete. Figure 24-7. Transmitter Behavior when Operating with Hardware Handshaking CTS TXD 24.6.3.3 IrDA Modulation and Demodulation IrDA modulation and demodulation is available with the following configuration. When enabled, transmission and reception is IrDA compliant up to 115.2 kb/s. z IrDA encoding enabled (CTRLB.ENC=1). z Asynchronous mode (CTRLA.CMODE = 0). z 16x sample rate (CTRLA.SAMPR[0] = 0). During transmission, each low bit is transmitted as a high pulse with width as 3/16 of the baud rate period as illustrated in Figure 24-8. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 442 Figure 24-8. IrDA Transmit Encoding 1 baud clock TXD IrDA encoded TXD 3/16 baud clock The reception decoder has two main functions. The first is to synchronize the incoming data to the IrDA baud rate counter. Synchronization is performed at the start of each zero pulse. The second function is to decode incoming Rx data. If a pulse width meets the minimum length set by configuration (RXPL.RXPL), it is accepted. When the baud rate counter reaches its middle value (1/2 bit length), it is transferred to the receiver. Figure 24-9 illustrates reception where RXPL.RXPL is set to 19. This indicates that the pulse width should be at least 20 SE clock cycles. When assuming BAUD = 0xE666 or 160 SE cycles per bit, this corresponds to 2/16 baud clock as minimum pulse width required. In this case the first bit is accepted as a zero, the second bit is a one, and the third bit is also a one. A low pulse is rejected since it does not meet the minimum requirement of 2/16 baud clock. Figure 24-9. IrDA Receive Decoding Baud clock 0 0.5 1.5 1 2.5 2 IrDA encoded RXD RXD 20 SE clock cycles Note that the polarity of the transmitter and receiver are opposite. During transmission, a zero bit is transmitted as a one pulse. During reception, an accepted zero pulse is received as a zero bit. 24.6.3.4 Break Character Detection and Auto-baud Break character detection and auto-baud are available with the following configuration: z Auto-baud frame format (CTRLA.FORM = 0x04 or 0x05) z Asynchronous mode (CTRLA.CMODE = 0). z 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1). The auto-baud follows the LIN format. All LIN Frames start with a Break Field followed by a Sync Field. The USART uses a break detection threshold of greater than 11 nominal bit times at the configured baud rate. At any time, if more than 11 consecutive dominant bits are detected on the bus, the USART detects a Break Field. When a Break Field has been detected, the Receive Break interrupt flag (INTFLAG.RXBRK) is set and the USART expects the Sync Field character to be 0x55. This field is used to update the actual baud rate in order to stay synchronized. If the received Sync character is not 0x55, then the Inconsistent Sync Field error flag (STATUS.ISF) is set along with the Error interrupt flag (INTFLAG.ERROR) and the baud rate is unchanged. Figure 24-10.LIN Break and Sync Fields Break Field Sync Field 8 bit times Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 443 After a break field is detected and the start bit of the Sync Field is detected, a counter is started. The counter is then incremented for the next 8 bit times of the Sync Field. At the end of these 8 bit times, the counter is stopped. At this moment, the 13 most significant bits of the counter (value divided by 8) gives the new clock divider (BAUD.BAUD) and the 3 least significant bits of this value (the remainder) gives the new Fractional Part (BAUD.FP). When the Sync Field has been received, the clock divider (BAUD.BAUD) and the Fractional Part (BAUD.FP) are updated in the Baud Rate Generator register (BAUD) after a synchronization delay. After the Break and Sync Fields, n characters of data can be received. 24.6.3.5 Collision Detection When the receiver and transmitter are connected either through pin configuration or externally, transmit collision can be detected by setting the Collision Detection Enable bit (CTRLB.COLDEN). For collision to be detected, the receiver and transmitter must be enabled (CTRLB.RXEN=1 and CTRLB.TXEN=1). Collision detection is performed for each bit transmitted by checking the received value vs the transmit value as shown in Figure 24-11. While the transmitter is idle (no transmission in progress), characters can be received on RxD without triggering a collision. Figure 24-11.Collision Checking 8-bit character, single stop bit TXD RXD Collision checked Figure 24-12 shows the conditions for a collision detection. In this case, the start bit and the first data bit are received with the same value as transmitted. The second received data bit is found to be different than the transmitted bit at the detection point which indicates a collision. Figure 24-12.Collision Detected Collision checked and ok Tri-state TXD RXD TXEN Collision detected When a collision is detected, the USART automatically follows this sequence: z The current transfer is aborted. z The transmit buffer is flushed. z The transmitter is disabled (CTRLB.TXEN=0). z z This commences immediately and is complete after synchronization time. The CTRLB Synchronization Busy bit (SYNCBUSY.CTRLB) will be set until this is complete. z This results in the TxD pin being tri-stated. The Collision Detected bit (STATUS.COLL) is set along with the Error interrupt flag (INTFLAG.ERROR). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 444 z Since the transmit buffer no longer contains data, the Transmit Complete interrupt flag (INTFLAG.TXC) is set. After a collision, software must manually enable the transmitter before continuing. Software must ensure CTRLB Synchronization Busy bit (SYNCBUSY.CTRLB) is not asserted before re-enabling the transmitter. 24.6.3.6 Loop-back Mode By configuring the Receive Data Pinout (CTRLA.RXPO) and Transmit Data Pinout (CTRLA.TXPO) to use the same data pins for transmit and receive, loop-back is achieved. The loop-back is through the pad, so the signal is also available externally. 24.6.3.7 Start-of-Frame Detection The USART start-of-frame detector can wake up the CPU when it detects a start bit. In standby sleep mode, the internal fast startup oscillator must be selected as the GCLK_SERCOMx_CORE source. When a 1-to-0 transition is detected on RxD, the 8MHz Internal Oscillator is powered up and the USART clock is enabled. After startup, the rest of the data frame can be received, provided that the baud rate is slow enough in relation to the fast startup internal oscillator start-up time. Refer to "Electrical Characteristics" on page 1055 for details. The startup time of this oscillator varies with supply voltage and temperature. The USART start-of-frame detection works both in asynchronous and synchronous modes. It is enabled by writing a one to the Start of Frame Detection Enable bit in the Control B register (CTRLB.SFDE). If the Receive Start Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.RXS) is set, the Receive Start interrupt is generated immediately when a start is detected. When using start-of-frame detection without the Receive Start interrupt, start detection will force the 8MHz Internal Oscillator and USART clock active while the frame is being received, but the CPU will not wakeup until the Receive Complete interrupt is generated, if enabled. 24.6.3.8 Sample Adjustment In asynchronous mode (CTRLA.CMODE=0), three samples in the middle are used to determine the value based on majority voting. The three samples used for voting can be selected using the Sample Adjustment bit field in Control A register (CTRLA.SAMPA). When CTRLA.SAMPA is set to zero, samples 7-8-9 are used for 16x over sampling and samples 3-4-5 are used for 8x over sampling. 24.6.4 DMA, Interrupts and Events Table 24-3. Module Request for SERCOM USART Condition Interrupt request Data Register Empty x Transmit Complete x Receive Complete x Receive Start x Clear to Send Input Change x Receive Break x Error x Event output Event input DMA request DMA request is cleared x When data is written x When data is read 24.6.4.1 DMA Operation The USART generates the following DMA requests. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 445 z Data received (RX): The request is set when data is available in the receive FIFO. The request is cleared when DATA is read. z Data transmit (TX): The request is set when the transmit buffer (TX DATA) is empty. The request is cleared when DATA is written. 24.6.4.2 Interrupts The USART has the following interrupt sources: z Error (ERROR): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. z Received Break (RXBRK): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. z Clear to Send Input Change (CTSIC): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. z Receive Start (RXS): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. z Receive Complete (RXC): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. z Transmit Complete (TXC): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. z Data Register Empty (DRE): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the USART is reset. See the register description for details on how to clear interrupt flags. The USART has one common interrupt request line for all the interrupt sources. The user must read INTFLAG to determine which interrupt condition is present. Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to "Nested Vector Interrupt Controller" on page 29 for details. 24.6.4.3 Events Not applicable. 24.6.5 Sleep Mode Operation When using internal clocking, writing the Run In Standby bit in the Control A register (CTRLA.RUNSTDBY) to one will allow GCLK_SERCOMx_CORE to be enabled in all sleep modes. Any interrupt can wake up the device. When using external clocking, writing a one to CTRLA.RUNSTDBY will allow the Receive Start or Receive Complete interrupt.to wake up the device. If CTRLA.RUNSTDBY is zero, the internal clock will be disabled when any ongoing transfer is finished. A Receive Start or Transfer Complete interrupt can wake up the device. When using external clocking, this will be disconnected when any ongoing transfer is finished, and all reception will be dropped. 24.6.6 Synchronization Due to the asynchronicity between CLK_SERCOMx_APB and GCLK_SERCOMx_CORE, some registers must be synchronized when accessed. A register can require: z Synchronization when written z Synchronization when read Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 446 z Synchronization when written and read z No synchronization When executing an operation that requires synchronization, the corresponding Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY) will be set immediately, and cleared when synchronization is complete. If an operation that requires synchronization is executed while the corresponding SYNCBUSY bit is one, a peripheral bus error is generated. The following bits need synchronization when written: z Software Reset bit in the Control A register (CTRLA.SWRST). SYNCBUSY.SWRST is set to one while synchronization is in progress. z Enable bit in the Control A register (CTRLA.ENABLE). SYNCBUSY.ENABLE is set to one while synchronization is in progress. z Receiver Enable bit in the Control B register (CTRLB.RXEN). SYNCBUSY.CTRLB is set to one while synchronization is in progress. z Transmitter Enable bit in the Control B register (CTRLB.TXEN). SYNCBUSY.CTRLB is set to one while synchronization is in progress. Synchronization is denoted by the Write-Synchronized property in the register description. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 447 24.7 Register Summary Table 24-4. Register Summary Offset Name 0x00 Bit Pos. 7:0 0x01 RUNSTDBY MODE[2:0] ENABLE SWRST SAMPR[2:0] 15:8 IBON CTRLA 0x02 23:16 0x03 31:24 DORD 0x04 7:0 SBMODE 0x05 CTRLB 15:8 0x06 23:16 0x07 31:24 0x08 Reserved 0x09 Reserved 0x0A Reserved 0x0B Reserved 0x0C SAMPA[1:0] RXPO[1:0] CPOL TXPO[1:0] CMODE FORM[3:0] CHSIZE[2:0] PMODE ENC 7:0 SFDE COLDEN RXEN TXEN BAUD[7:0] BAUD 0x0D 15:8 0x0E RXPL 0x0F Reserved 0x10 Reserved 0x11 Reserved 0x12 Reserved 0x13 Reserved 0x14 INTENCLR 0x15 Reserved 0x16 INTENSET 0x17 Reserved 0x18 INTFLAG 0x19 Reserved 0x1A FP[2:0]/BAUD[15:13] BAUD[12:8] 7:0 RXPL[7:0] 7:0 ERROR RXBRK CTSIC RXS RXC TXC DRE 7:0 ERROR RXBRK CTSIC RXS RXC TXC DRE 7:0 ERROR RXBRK CTSIC RXS RXC TXC DRE COLL ISF CTS BUFOVF FERR PERR CTRLB ENABLE SWRST 7:0 STATUS 0x1B 15:8 0x1C 7:0 0x1D 15:8 SYNCBUSY 0x1E 23:16 0x1F 31:24 0x20 Reserved 0x21 Reserved 0x22 Reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 448 Offset Name 0x23 Reserved 0x24 Reserved 0x25 Reserved 0x26 Reserved 0x27 Reserved 0x28 Bit Pos. 7:0 DATA[7:0] DATA 0x29 0x2A Reserved 0x2B Reserved 0x2C Reserved 0x2D Reserved 0x2E Reserved 0x2F Reserved 0x30 DBGCTRL 15:8 DATA[8] 7:0 DBGSTOP Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 449 24.8 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protected property in each individual register description. Refer to "Register Access Protection" on page 436 for details. Some registers require synchronization when read and/or written. Synchronization is denoted by the Synchronized property in each individual register description. Refer to "Synchronization" on page 446 for details. Some registers are enable-protected, meaning they can only be written when the USART is disabled. Enable-protection is denoted by the Enable-Protected property in each individual register description. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 450 24.8.1 Control A Name: CTRLA Offset: 0x00 Reset: 0x00000000 Property: Enable-Protected, Write-Protected, Write-Synchronized Bit 31 30 29 28 DORD CPOL CMODE 27 26 25 24 FORM[3:0] Access R R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 SAMPA[1:0] Access TXPO[1:0] RXPO[1:0] R/W R/W R/W R/W R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 IBON SAMPR[2:0] Access R/W R/W R/W R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ENABLE SWRST MODE[2:0] RUNSTDBY Access Reset R/W R R R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bit 31 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 30 - DORD: Data Order This bit indicates the data order when a character is shifted out from the Data register. 0: MSB is transmitted first. 1: LSB is transmitted first. This bit is not synchronized. z Bit 29 - CPOL: Clock Polarity This bit indicates the relationship between data output change and data input sampling in synchronous mode. This bit is not synchronized. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 451 Table 24-5. Clock Polarity z CPOL TxD Change RxD Sample 0x0 Rising XCK edge Falling XCK edge 0x1 Falling XCK edge Rising XCK edge Bit 28 - CMODE: Communication Mode This bit indicates asynchronous or synchronous communication. 0: Asynchronous communication. 1: Synchronous communication. This bit is not synchronized. z Bits 27:24 - FORM[3:0]: Frame Format These bits define the frame format. These bits are not synchronized. Table 24-6. Frame Format FORM[3:0] Description 0x0 USART frame 0x1 USART frame with parity 0x2-0x3 Reserved 0x4 Auto-baud -- break detection and auto-baud. 0x5 Auto-baud -- break detection and auto-baud with parity 0x6-0xF Reserved z Bits 23:22 - SAMPA[1:0]: Sample Adjustment These bits define the sample adjustment. These bits are not synchronized. Table 24-7. Sample Adjustment SAMPA[1:0] 16x Over-sampling (CTRLA.SAMPR=0 or 1) 8x Over-sampling (CTRLA.SAMPR=2 or 3) 0x0 7-8-9 3-4-5 0x1 9-10-11 4-5-6 0x2 11-12-13 5-6-7 0x3 13-14-15 6-7-8 z Bits 21:20 - RXPO[1:0]: Receive Data Pinout These bits define the receive data (RxD) pin configuration. These bits are not synchronized. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 452 Table 24-8. Receive Data Pinout RXPO[1:0] Name Description 0x0 PAD[0] SERCOM PAD[0] is used for data reception 0x1 PAD[1] SERCOM PAD[1] is used for data reception 0x2 PAD[2] SERCOM PAD[2] is used for data reception 0x3 PAD[3] SERCOM PAD[3] is used for data reception z Bits 19:18 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 17:16 - TXPO[1:0]: Transmit Data Pinout These bits define the transmit data (TxD) and XCK pin configurations. This bit is not synchronized. Table 24-9. Transmit Data Pinout TXPO TxD Pin Location XCK Pin Location (When Applicable) RTS CTS 0x0 SERCOM PAD[0] SERCOM PAD[1] N/A N/A 0x1 SERCOM PAD[2] SERCOM PAD[3] N/A N/A 0x2 SERCOM PAD[0] N/A SERCOM PAD[2] SERCOM PAD[3] 0x3 Reserved z Bits 15:13 - SAMPR[2:0]: Sample Rate These bits define the sample rate. These bits are not synchronized. Table 24-10. Sample Rate SAMPR[2:0] Description 0x0 16x over-sampling using arithmetic baud rate generation. 0x1 16x over-sampling using fractional baud rate generation. 0x2 8x over-sampling using arithmetic baud rate generation. 0x3 8x over-sampling using fractional baud rate generation. 0x4 3x over-sampling using arithmetic baud rate generation. 0x5-0x7 Reserved z Bits 12:9 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 8 - IBON: Immediate Buffer Overflow Notification This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is asserted when a buffer overflow occurs. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 453 0: STATUS.BUFOVF is asserted when it occurs in the data stream. 1: STATUS.BUFOVF is asserted immediately upon buffer overflow. z Bit 7 - RUNSTDBY: Run In Standby This bit defines the functionality in standby sleep mode. This bit is not synchronized. Table 24-11. Run In Standby RUNSTDBY External Clock Internal Clock 0x0 External clock is disconnected when ongoing transfer is finished. All reception is dropped. Generic clock is disabled when ongoing transfer is finished. The device can wake up on Receive Start or Transfer Complete interrupt. 0x1 Wake on Receive Start or Receive Complete interrupt. Generic clock is enabled in all sleep modes. Any interrupt can wake up the device. z Bits 6:5 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 4:2 - MODE: Operating Mode These bits must be written to 0x0 or 0x1 to select the USART serial communication interface of the SERCOM. 0x0: USART with external clock. 0x1: USART with internal clock. These bits are not synchronized. z Bit 1 - ENABLE: Enable 0: The peripheral is disabled or being disabled. 1: The peripheral is enabled or being enabled. Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE is cleared when the operation is complete. This bit is not enable-protected. z Bit 0 - SWRST: Software Reset 0: There is no reset operation ongoing. 1: The reset operation is ongoing. Writing a zero to this bit has no effect. Writing a one to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled. Writing a one to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register will return the reset value of the register. Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete. This bit is not enable-protected. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 454 24.8.2 Control B Name: CTRLB Offset: 0x04 Reset: 0x00000000 Property: Enable-Protected, Write-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 RXEN TXEN Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 ENC SFDE COLDEN PMODE Access R R R/W R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SBMODE CHSIZE[2:0] Access R R/W R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 31:18 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 17 - RXEN: Receiver Enable 0: The receiver is disabled or being enabled. 1: The receiver is enabled or will be enabled when the USART is enabled. Writing a zero to this bit will disable the USART receiver. Disabling the receiver will flush the receive buffer and clear the FERR, PERR and BUFOVF bits in the STATUS register. Writing a one to CTRLB.RXEN when the USART is disabled will set CTRLB.RXEN immediately. When the USART is enabled, CTRLB.RXEN will be cleared, and SYNCBUSY.CTRLB will be set and remain set until the receiver is enabled. When the receiver is enabled, CTRLB.RXEN will read back as one. Writing a one to CTRLB.RXEN when the USART is enabled will set SYNCBUSY.CTRLB, which will remain set until the receiver is enabled, and CTRLB.RXEN will read back as one. This bit is not enable-protected. z Bit 16 - TXEN: Transmitter Enable 0: The transmitter is disabled or being enabled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 455 1: The transmitter is enabled or will be enabled when the USART is enabled. Writing a zero to this bit will disable the USART transmitter. Disabling the transmitter will not become effective until ongoing and pending transmissions are completed. Writing a one to CTRLB.TXEN when the USART is disabled will set CTRLB.TXEN immediately. When the USART is enabled, CTRLB.TXEN will be cleared, and SYNCBUSY.CTRLB will be set and remain set until the transmitter is enabled. When the transmitter is enabled, CTRLB.TXEN will read back as one. Writing a one to CTRLB.TXEN when the USART is enabled will set SYNCBUSY.CTRLB, which will remain set until the receiver is enabled, and CTRLB.TXEN will read back as one. This bit is not enable-protected. z Bits 15:14 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 13 - PMODE: Parity Mode This bit selects the type of parity used when parity is enabled (CTRLA.FORM is one). The transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and parity bit, compare it to the parity mode and, if a mismatch is detected, STATUS.PERR will be set. 0: Even parity. 1: Odd parity. This bit is not synchronized. z Bits 12:11 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 10 - ENC: Encoding Format This bit selects the data encoding format. 0: Data is not encoded. 1: Data is IrDA encoded. This bit is not synchronized. z Bit 9 - SFDE: Start of Frame Detection Enable This bit controls whether the start-of-frame detector will wake up the device when a start bit is detected on the RxD line, according to the table below. This bit is not synchronized. SFDE INTENSET.RXS INTENSET.RXC Description 0 X X Start-of-frame detection disabled. 1 0 0 Reserved 1 0 1 Start-of-frame detection enabled. RXC wakes up the device from all sleep modes. 1 1 0 Start-of-frame detection enabled. RXS wakes up the device from all sleep modes. 1 1 1 Start-of-frame detection enabled. Both RXC and RXS wake up the device from all sleep modes. z Bit 8 -- COLDEN: Collision Detection Enable This bit enables collision detection. 0: Collision detection is not enabled. 1: Collision detection is enabled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 456 This bit is not synchronized. z Bit 7 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 6 - SBMODE: Stop Bit Mode This bit selects the number of stop bits transmitted. 0: One stop bit. 1: Two stop bits. This bit is not synchronized. z Bits 5:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 2:0 - CHSIZE[2:0]: Character Size These bits select the number of bits in a character. These bits are not synchronized. Table 24-12. Character Size CHSIZE[2:0] Description 0x0 8 bits 0x1 9 bits 0x2-0x4 Reserved 0x5 5 bits 0x6 6 bits 0x7 7 bits Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 457 24.8.3 Baud Name: BAUD Offset: 0x0C Reset: 0x0000 Property: Enable-Protected, Write-Protected Bit 15 14 13 12 11 FP[2:0]/BAUD[15:13] Access 10 9 8 BAUD[12:8] R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BAUD[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Arithmetic Baud Rate Generation (CTRLA.SAMPR[0]=0) z Bits 15:0 - BAUD[15:0]: Baud Value These bits control the clock generation, as described in the SERCOM Baud Rate section. Fractional Baud Rate Generation (CTRLA.SAMPR[0]=1) z Bits 15:13 - FP[2:0]: Fractional Part These bits control the clock generation, as described in the SERCOM Baud Rate section. z Bits 15:0 - BAUD[12:0]: Baud Value These bits control the clock generation, as described in the SERCOM Baud Rate section. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 458 24.8.4 Receive Pulse Length Register Name: RXPL Offset: 0x0E Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 RXPL[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - RXPL[7:0]: Receive Pulse Length When the encoding format is set to IrDA (CTRLB.ENC=1), these bits control the minimum pulse length that is required for a pulse to be accepted by the IrDA receiver with regards to the serial engine clock period. PULSE ( RXPL + 1) x SE per Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 459 24.8.5 Interrupt Enable Clear This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Name: INTENCLR Offset: 0x14 Reset: 0x00 Property: Write-Protected Bit 7 6 ERROR Access Reset z 5 4 3 2 1 0 RXBRK CTSIC RXS RXC TXC DRE R/W R R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7- ERROR: Error Interrupt Enable 0: Error interrupt is disabled. 1: Error interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt. z Bit 6 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 5 - RXBRK: Receive Break Interrupt Enable 0: Receive Break interrupt is disabled. 1: Receive Break interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Receive Break Interrupt Enable bit, which disables the Receive Break interrupt. z Bit 4 - CTSIC: Clear to Send Input Change Interrupt Enable 0: Clear To Send Input Change interrupt is disabled. 1: Clear To Send Input Change interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Clear To Send Input Change Interrupt Enable bit, which disables the Clear To Send Input Change interrupt. z Bit 3 - RXS: Receive Start Interrupt Enable 0: Receive Start interrupt is disabled. 1: Receive Start interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Receive Start Interrupt Enable bit, which disables the Receive Start interrupt. z Bit 2 - RXC: Receive Complete Interrupt Enable 0: Receive Complete interrupt is disabled. 1: Receive Complete interrupt is enabled. Writing a zero to this bit has no effect. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 460 Writing a one to this bit will clear the Receive Complete Interrupt Enable bit, which disables the Receive Complete interrupt. z Bit 1 - TXC: Transmit Complete Interrupt Enable 0: Transmit Complete interrupt is disabled. 1: Transmit Complete interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Transmit Complete Interrupt Enable bit, which disables the Receive Complete interrupt. z Bit 0 - DRE: Data Register Empty Interrupt Enable 0: Data Register Empty interrupt is disabled. 1: Data Register Empty interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Data Register Empty Interrupt Enable bit, which disables the Data Register Empty interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 461 24.8.6 Interrupt Enable Set This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR) . Name: INTENSET Offset: 0x16 Reset: 0x00 Property: Write-Protected Bit 7 6 ERROR Access Reset z 5 4 3 2 1 0 RXBRK CTSIC RXS RXC TXC DRE R/W R R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 - ERROR: Error Interrupt Enable 0: Error interrupt is disabled. 1: Error interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt. z Bits 6 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 5- RXBRK: Receive Break Interrupt Enable 0: Receive Break interrupt is disabled. 1: Receive Break interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Receive Break Interrupt Enable bit, which enables the Receive Break interrupt. z Bit 4 - CTSIC: Clear to Send Input Change Interrupt Enable 0: Clear To Send Input Change interrupt is disabled. 1: Clear To Send Input Change interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Clear To Send Input Change Interrupt Enable bit, which enables the Clear To Send Input Change interrupt. z Bit 3 - RXS: Receive Start Interrupt Enable 0: Receive Start interrupt is disabled. 1: Receive Start interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Receive Start Interrupt Enable bit, which enables the Receive Start interrupt. z Bit 2 - RXC: Receive Complete Interrupt Enable 0: Receive Complete interrupt is disabled. 1: Receive Complete interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Receive Complete Interrupt Enable bit, which enables the Receive Complete interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 462 z Bit 1- TXC: Transmit Complete Interrupt Enable 0: Transmit Complete interrupt is disabled. 1: Transmit Complete interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Transmit Complete Interrupt Enable bit, which enables the Transmit Complete interrupt. z Bit 0 - DRE: Data Register Empty Interrupt Enable 0: Data Register Empty interrupt is disabled. 1: Data Register Empty interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Data Register Empty Interrupt Enable bit, which enables the Data Register Empty interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 463 24.8.7 Interrupt Flag Status and Clear Name: INTFLAG Offset: 0x18 Reset: 0x00 Property: Bit 7 6 ERROR Access Reset z 5 4 3 2 1 0 RXBRK CTSIC RXS RXC TXC DRE R/W R R/W R/W R/W R R/W R 0 0 0 0 0 0 0 0 Bit 7- ERROR: Error This flag is cleared by writing a one to it. This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STATUS register. Errors that will set this flag are COLL, ISF, BUFOVF, FERR, and PERR.Writing a zero to this bit has no effect. Writing a one to this bit will clear the flag. z Bits 6 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 5 - RXBRK: Receive Break This flag is cleared by writing a one to it. This flag is set when auto-baud is enabled (CTRLA.FORM) and a break character is received. Writing a zero to this bit has no effect. Writing a one to this bit will clear the flag. z Bit 4 - CTSIC: Clear to Send Input Change This flag is cleared by writing a one to it. This flag is set when a change is detected on the CTS pin. Writing a zero to this bit has no effect. Writing a one to this bit will clear the flag. z Bit 3 - RXS: Receive Start This flag is cleared by writing a one to it. This flag is set when a start condition is detected on the RxD line and start-of-frame detection is enabled (CTRLB.SFDE is one). Writing a zero to this bit has no effect. Writing a one to this bit will clear the Receive Start interrupt flag. z Bit 2 - RXC: Receive Complete This flag is cleared by reading the Data register (DATA) or by disabling the receiver. This flag is set when there are unread data in DATA. Writing a zero to this bit has no effect. Writing a one to this bit has no effect. z Bit 1 - TXC: Transmit Complete This flag is cleared by writing a one to it or by writing new data to DATA. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 464 This flag is set when the entire frame in the transmit shift register has been shifted out and there are no new data in DATA. Writing a zero to this bit has no effect. Writing a one to this bit will clear the flag. z Bit 0 - DRE: Data Register Empty This flag is cleared by writing new data to DATA. This flag is set when DATA is empty and ready to be written. Writing a zero to this bit has no effect. Writing a one to this bit has no effect. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 465 24.8.8 Status Name: STATUS Offset: 0x1A Reset: 0x0000 Property: Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COLL ISF CTS BUFOVF FERR PERR Access R R R/W R/W R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 15:6 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 5 - COLL: Collision Detected This bit is cleared by writing a one to the bit or by disabling the receiver. This bit is set when collision detection is enabled (CTRLB.COLDEN) and a collision is detected. Writing a zero to this bit has no effect. Writing a one to this bit will clear it. z Bit 4 - ISF: Inconsistent Sync Field This bit is cleared by writing a one to the bit or by disabling the receiver. This bit is set when the frame format is set to auto-baud (CTRLA.FORM) and a sync field not equal to 0x55 is received. Writing a zero to this bit has no effect. Writing a one to this bit will clear it. z Bit 3 - CTS: Clear to Send This bit indicates the current level of the CTS pin when flow control is enabled (CTRLA.TXPO). Writing a zero to this bit has no effect. Writing a one to this bit has no effect. z Bit 2 - BUFOVF: Buffer Overflow Reading this bit before reading the Data register will indicate the error status of the next character to be read. This bit is cleared by writing a one to the bit or by disabling the receiver. This bit is set when a buffer overflow condition is detected. A buffer overflow occurs when the receive buffer is full, there is a new character waiting in the receive shift register and a new start bit is detected. Writing a zero to this bit has no effect. Writing a one to this bit will clear it. z Bit 1 - FERR: Frame Error Reading this bit before reading the Data register will indicate the error status of the next character to be read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 466 This bit is cleared by writing a one to the bit or by disabling the receiver. This bit is set if the received character had a frame error, i.e., when the first stop bit is zero. Writing a zero to this bit has no effect. Writing a one to this bit will clear it. z Bit 0 - PERR: Parity Error Reading this bit before reading the Data register will indicate the error status of the next character to be read. This bit is cleared by writing a one to the bit or by disabling the receiver. This bit is set if parity checking is enabled (CTRLA.FORM is 0x1 or 0x5) and a parity error is detected. Writing a zero to this bit has no effect. Writing a one to this bit will clear it. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 467 24.8.9 Synchronization Busy Name: SYNCBUSY Offset: 0x1C Reset: 0x00000000 Property: Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CTRLB ENABLE SWRST Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 31:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 2- CTRLB: CTRLB Synchronization Busy Writing CTRLB when the SERCOM is enabled requires synchronization. When written, the SYNCBUSY.CTRLB bit will be set until synchronization is complete. If CTRLB is written while SYNCBUSY.CTRLB is asserted, an APB error will be generated. 0: CTRLB synchronization is not busy. 1: CTRLB synchronization is busy. z Bit 1 - ENABLE: SERCOM Enable Synchronization Busy Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the SYNCBUSY.ENABLE bit will be set until synchronization is complete. Writes to any register (except for CTRLA.SWRST) while enable synchronization is on-going will be discarded and an APB error will be generated. 0: Enable synchronization is not busy. 1: Enable synchronization is busy. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 468 z Bit 0 - SWRST: Software Reset Synchronization Busy Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the SYNCBUSY.SWRST bit will be set until synchronization is complete. Writes to any register while synchronization is on-going will be discarded and an APB error will be generated. 0: SWRST synchronization is not busy. 1: SWRST synchronization is busy. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 469 24.8.10 Data Name: DATA Offset: 0x28 Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 9 8 DATA[8] Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 15:9 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 8:0 - DATA[8:0]: Data Reading these bits will return the contents of the Receive Data register. The register should be read only when the Receive Complete Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.RXC) is set. The status bits in STATUS should be read before reading the DATA value in order to get any corresponding error. Writing these bits will write the Transmit Data register. This register should be written only when the Data Register Empty Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.DRE) is set. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 470 24.8.11 Debug Control Name: DBGCTRL Offset: 0x30 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 DBGSTOP Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:1 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 0 - DBGSTOP: Debug Stop Mode This bit controls the baud-rate generator functionality when the CPU is halted by an external debugger. 0: The baud-rate generator continues normal operation when the CPU is halted by an external debugger. 1: The baud-rate generator is halted when the CPU is halted by an external debugger. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 471 25. SERCOM SPI - SERCOM Serial Peripheral Interface 25.1 Overview The serial peripheral interface (SPI) is one of the available modes in the Serial Communication Interface (SERCOM). Refer to "SERCOM - Serial Communication Interface" on page 426 for details. The SPI uses the SERCOM transmitter and receiver configured as shown in "Full-Duplex SPI Master Slave Interconnection" on page 472. Each side, master and slave, depicts a separate SPI containing a shift register, a transmit buffer and two receive buffers. In addition, the SPI master uses the SERCOM baud-rate generator, while the SPI slave can use the SERCOM address match logic. Fields shown in capital letters are synchronous to CLK_SERCOMx_APB and accessible by the CPU, while fields with lowercase letters are synchronous to the SCK clock. 25.2 Features z Full-duplex, four-wire interface (MISO, MOSI, SCK, _SS) z Single-buffered transmitter, double-buffered receiver z Supports all four SPI modes of operation z Single data direction operation allows alternate function on MISO or MOSI pin z Selectable LSB- or MSB-first data transfer z Can be used with DMA z Master operation: Serial clock speed up to half the system clock 8-bit clock generator z Hardware controlled _SS z z z Slave operation: Serial clock speed up to the system clock Optional 8-bit address match operation z Operation in all sleep modes z Wake on _SS transition z z 25.3 Block Diagram Figure 25-1. Full-Duplex SPI Master Slave Interconnection Master BAUD Slave Tx DATA Tx DATA ADDR/ADDRMASK SCK _SS baud rate generator MISO shift register shift register MOSI 25.4 rx buffer rx buffer Rx DATA Rx DATA == Address Match Signal Description Signal Name Type Description PAD[3:0] Digital I/O General SERCOM pins Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 472 Refer to "I/O Multiplexing and Considerations" on page 12 for details on the pin mapping for this peripheral. One signal can be mapped to one of several pins. 25.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 25.5.1 I/O Lines Using the SERCOM's I/O lines requires the I/O pins to be configured using port configuration (PORT). Refer to "PORT" on page 373 for details. When the SERCOM is configured for SPI operation, the pins should be configured according to Table 25-1. If the receiver is disabled, the data input pin can be used for other purposes. In master mode the slave select line (_SS) is hardware controlled when Master Slave Select Enable (CTRLB.MSSEN) is set to one. Table 25-1. SPI Pin Configuration Pin Master SPI Slave SPI MOSI Output Input MISO Input Output SCK Output Input _SS Output (CTRLB.MSSEN=1) Input The combined configuration of PORT and the Data In/Data Out and Data Out Pinout bit groups in Control A register will define the physical position of the SPI signals in Table 25-1. 25.5.2 Power Management The SPI can continue to operate in any sleep mode. The SPI interrupts can be used to wake up the device from sleep modes. Refer to "PM - Power Manager" on page 112 for details on the different sleep modes. 25.5.3 Clocks The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Power Manager, and the default state of CLK_SERCOMx_APB can be found in the Peripheral Clock Masking section in the "PM - Power Manager" on page 112. A generic clock (GCLK_SERCOMx_CORE) is required to clock the SPI. This clock must be configured and enabled in the Generic Clock Controller before using the SPI. Refer to "GCLK - Generic Clock Controller" on page 90 for details. This generic clock is asynchronous to the bus clock (CLK_SERCOMx_APB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. Refer to "Synchronization" on page 482 for further details. 25.5.4 DMA The DMA request lines are connected to the DMA controller (DMAC). Using the SERCOM DMA requests, requires the DMA controller to be configured first. Refer to "DMAC - Direct Memory Access Controller" on page 267 for details. 25.5.5 Interrupts The interrupt request line is connected to the Interrupt Controller. Using the SPI, interrupts requires the Interrupt Controller to be configured first. Refer to "Nested Vector Interrupt Controller" on page 29 for details. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 473 25.5.6 Events Not applicable. 25.5.7 Debug Operation When the CPU is halted in debug mode, the SPI continues normal operation. If the SPI is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. The SPI can be forced to halt operation during debugging. Refer to the Debug Control (DBGCTRL) register for details. 25.5.8 Register Access Protection All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the following registers: z Interrupt Flag Clear and Status register (INTFLAG) z Status register (STATUS) z Data register (DATA) Write-protection is denoted by the Write-Protection property in the register description. When the CPU is halted in debug mode, all write-protection is automatically disabled. Write-protection does not apply for accesses through an external debugger. Refer to "PAC - Peripheral Access Controller" on page 36 for details. 25.5.9 Analog Connections Not applicable. 25.6 Functional Description 25.6.1 Principle of Operation The SPI is a high-speed synchronous data transfer interface. It allows fast communication between the device and peripheral devices. The SPI can operate as master or slave. As master, the SPI initiates and controls all data transactions. The SPI is single buffered for transmitting and double buffered for receiving. When transmitting data, the Data register can be loaded with the next character to be transmitted while the current transmission is in progress. For receiving, this means that the data is transferred to the two-level receive buffer upon reception, and the receiver is ready for a new character. The SPI transaction format is shown in Figure 25-2, where each transaction can contain one or more characters. The character size is configurable, and can be either 8 or 9 bits. Figure 25-2. SPI Transaction Format Transaction Character MOSI/MISO Character 0 Character 1 Character 2 _SS The SPI master must initiate a transaction by pulling low the slave select line (_SS) of the desired slave. The master and slave prepare data to be sent in their respective shift registers, and the master generates the serial clock on the SCK line. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 474 Data are always shifted from master to slave on the master output, slave input line (MOSI), and from slave to master on the master input, slave output line (MISO). The master signals the end of the transaction by pulling the _SS line high. As each character is shifted out from the master, another character is shifted in from the slave. 25.6.2 Basic Operation 25.6.2.1 Initialization The following registers are enable-protected, meaning that they can only be written when the SPI is disabled (CTRL.ENABLE is zero): z Control A register (CTRLA), except Enable (CTRLA.ENABLE) and Software Reset (CTRLA.SWRST) z Control B register (CTRLB), except Receiver Enable (CTRLB.RXEN) z Baud register (BAUD) z Address register (ADDR) Any writes to these registers when the SPI is enabled or is being enabled (CTRLA.ENABLE is one) will be discarded. Writes to these registers while the SPI is being disabled will be completed after the disabling is complete. Enable-protection is denoted by the Enable-Protection property in the register description. Before the SPI is enabled, it must be configured, as outlined by the following steps: z SPI mode in master or slave operation must be selected by writing 0x2 or 0x3 to the Operating Mode bit group in the Control A register (CTRLA.MODE) z Transfer mode must be selected by writing the Clock Polarity bit and the Clock Phase bit in the Control A register (CTRLA.CPOL and CTRLA.CPHA) z Transaction format must be selected by writing the Frame Format bit group in the Control A register (CTRLA.FORM) z SERCOM pad to use for the receiver must be selected by writing the Data In Pinout bit group in the Control A register (CTRLA.DIPO) z SERCOM pads to use for the transmitter, slave select and serial clock must be selected by writing the Data Out Pinout bit group in the Control A register (CTRLA.DOPO) z Character size must be selected by writing the Character Size bit group in the Control B register (CTRLB.CHSIZE) z Data direction must be selected by writing the Data Order bit in the Control A register (CTRLA.DORD) z If the SPI is used in master mode, the Baud register (BAUD) must be written to generate the desired baud rate z If the SPI is used in master mode and Hardware SS control is required, the Master Slave Select Enable bit in CTRLB register (CTRLB.MSSEN) should be set to 1. z The receiver can be enabled by writing a one to the Receiver Enable bit in the Control B register (CTRLB.RXEN) 25.6.2.2 Enabling, Disabling and Resetting The SPI is enabled by writing a one to the Enable bit in the Control A register (CTRLA.ENABLE). The SPI is disabled by writing a zero to CTRLA.ENABLE. The SPI is reset by writing a one to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in the SPI, except DBGCTRL, will be reset to their initial state, and the SPI will be disabled. Refer to CTRLA for details. 25.6.2.3 Clock Generation In SPI master operation (CTRLA.MODE is 0x3), the serial clock (SCK) is generated internally using the SERCOM baudrate generator. When used in SPI mode, the baud-rate generator is set to synchronous mode, and the 8-bit Baud register (BAUD) value is used to generate SCK, clocking the shift register. Refer to "Clock Generation - Baud-Rate Generator" on page 429 for more details. In SPI slave operation (CTRLA.MODE is 0x2), the clock is provided by an external master on the SCK pin. This clock is used to directly clock the SPI shift register. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 475 25.6.2.4 Data Register The SPI Transmit Data register (TxDATA) and SPI Receive Data register (RxDATA) share the same I/O address, referred to as the SPI Data register (DATA). Writing the DATA register will update the Transmit Data register. Reading the DATA register will return the contents of the Receive Data register. 25.6.2.5 SPI Transfer Modes There are four combinations of SCK phase and polarity with respect to the serial data. The SPI data transfer modes are shown in Table 25-2 and Figure 25-3. SCK phase is selected by the Clock Phase bit in the Control A register (CTRLA.CPHA). SCK polarity is selected by the Clock Polarity bit in the Control A register (CTRLA.CPOL). Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for the data signals to stabilize. Table 25-2. SPI Transfer Modes Mode CPOL CPHA Leading Edge Trailing Edge 0 0 0 Rising, sample Falling, setup 1 0 1 Rising, setup Falling, sample 2 1 0 Falling, sample Rising, setup 3 1 1 Falling, setup Rising, sample Leading edge is the first clock edge in a clock cycle, while trailing edge is the second clock edge in a clock cycle. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 476 Figure 25-3. SPI Transfer Modes Mode 0 Mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB LSB first (DORD = 1) LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB Mode 1 Mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS 25.6.2.6 Transferring Data Master When configured as a master (CTRLA.MODE is 0x3), if Master Slave Select Enable (CTRLB.MSSEN) is set to zero the _SS line can be located at any general purpose I/O pin, and must be configured as an output. When the SPI is ready for a data transaction, software must pull the _SS line low. If Master Slave Enable Select (CTRLB.MSSEN) is set to one, hardware controls the _SS line. When writing a character to the Data register (DATA), the character will be transferred to the shift register when the shift register is empty. Once the contents of TxDATA have been transferred to the shift register, the Data Register Empty flag in the Interrupt Flag Status and Clear register (INTFLAG.DRE) is set, and a new character can be written to DATA. As each character is shifted out from the master, another character is shifted in from the slave. If the receiver is enabled (CTRLA.RXEN is one), the contents of the shift register will be transferred to the two-level receive buffer. The transfer takes place in the same clock cycle as the last data bit is shifted in, and the Receive Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.RXC) will be set. The received data can be retrieved by reading DATA. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 477 When the last character has been transmitted and there is no valid data in DATA, the Transmit Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC) is set. When the transaction is finished, the master must indicate this to the slave by pulling the _SS line high. If Master Slave Select Enable (CTRLB.MSSEN) is set to zero, the software must pull the _SS line high. Slave When configured as a slave (CTRLA.MODE is 0x2), the SPI interface will remain inactive, with the MISO line tri-stated as long as the _SS pin is pulled high. Software may update the contents of DATA at any time, as long as the Data Register Empty flag in the Interrupt Status and Clear register (INTFLAG.DRE) is set. When _SS is pulled low and SCK is running, the slave will sample and shift out data according to the transaction mode set. When the contents of TxDATA have been loaded into the shift register, INTFLAG.DRE is set, and new data can be written to DATA. Similar to the master, the slave will receive one character for each character transmitted. On the same clock cycle as the last data bit of a character is received, the character will be transferred into the two-level receive buffer. The received character can be retrieved from DATA when Receive Complete interrupt flag (INTFLAG.RXC) is set. When the master pulls the _SS line high, the transaction is done and the Transmit Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC) is set. Once DATA is written, it takes up to three SCK clock cycles before the content of DATA is ready to be loaded into the shift register. When the content of DATA is ready to be loaded, this will happen on the next character boundary. As a consequence, the first character transferred in a SPI transaction will not be the content of DATA. This can be avoided by using the preloading feature. Refer to "Preloading of the Slave Shift Register" on page 479. When transmitting several characters in one SPI transaction, the data has to be written to DATA while there are at least three SCK clock cycles left in the current character transmission. If this criteria is not met, then the previous character received will be transmitted. After the DATA register is empty, it takes three CLK_SERCOM_APB cycles for INTFLAG.DRE to be set. 25.6.2.7 Receiver Error Bit The SPI receiver has one error bit: the Buffer Overflow bit (BUFOVF), which can be read from the Status register (STATUS). Upon error detection, the bit will be set until it is cleared by writing a one to it. The bit is also automatically cleared when the receiver is disabled. There are two methods for buffer overflow notification. When the immediate buffer overflow notification bit (CTRLA.IBON) is set, STATUS.BUFOVF is set immediately upon buffer overflow. Software can then empty the receive FIFO by reading RxDATA until the receive complete interrupt flag (INTFLAG.RXC) goes low. When CTRLA.IBON is zero, the buffer overflow condition travels with data through the receive FIFO. After the received data is read, STATUS.BUFOVF and INTFLAG.ERROR will be set along with INTFLAG.RXC, and RxDATA will be zero. 25.6.3 Additional Features 25.6.3.1 Address Recognition When the SPI is configured for slave operation (CTRLA.MODE is 0x2) with address recognition (CTRLA.FORM is 0x2), the SERCOM address recognition logic is enabled. When address recognition is enabled, the first character in a transaction is checked for an address match. If there is a match, then the Receive Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.RXC) is set, the MISO output is enabled and the transaction is processed. If there is no match, the transaction is ignored. If the device is in sleep mode, an address match can wake up the device in order to process the transaction. If the address does not match, then the complete transaction is ignored. If a 9-bit frame format is selected, only the lower 8 bits of the shift register are checked against the Address register (ADDR). Refer to "Address Match and Mask" on page 432 for further details. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 478 25.6.3.2 Preloading of the Slave Shift Register When starting a transaction, the slave will first transmit the contents of the shift register before loading new data from DATA. The first character sent can be either the reset value of the shift register (if this is the first transmission since the last reset) or the last character in the previous transmission. Preloading can be used to preload data to the shift register while _SS is high and eliminate sending a dummy character when starting a transaction. In order to guarantee enough set-up time before the first SCK edge, enough time must be given between _SS going low and the first SCK sampling edge, as shown in Figure 25-4. Preloading is enabled by setting the Slave Data Preload Enable bit in the Control B register (CTRLB.PLOADEN). Figure 25-4. Timing Using Preloading Required _SS to SCK time using PRELOADEN _SS _SS synchronized to system domain SCK Synchronization to system domain MISO to SCK setup time Only one data character written to DATA will be preloaded into the shift register while the synchronized _SS signal (see Figure 25-4) is high. The next character written to DATA before _SS is pulled low will be stored in DATA until transfer begins. If the shift register is not preloaded, the current contents of the shift register will be shifted out. 25.6.3.3 Master with Several Slaves Master with multiple slaves in parallel feature is available only when Master Slave Select Enable (CTRLB.MSSEN) is set to zero and hardware _SS control is disabled. If the bus consists of several SPI slaves, an SPI master can use general purpose I/O pins to control the _SS line to each of the slaves on the bus, as shown in Figure 25-5. In this configuration, the single selected SPI slave will drive the tri-state MISO line. Figure 25-5. Multiple Slaves in Parallel shift register SPI Master MOSI MISO SCK _SS[0] MOSI MISO SCK _SS shift register _SS[n-1] MOSI MISO SCK _SS shift register SPI Slave 0 SPI Slave n-1 An alternate configuration is shown in Figure 25-6. In this configuration, all n attached slaves are connected in series. A common _SS line is provided to all slaves, enabling them simultaneously. The master must shift n characters for a complete transaction. Depending on the Master Slave Select Enable bit (CTRLB.MSSEN), _SS line is controlled either by hardware or by user software and normal GPIO Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 479 Figure 25-6. Multiple Slaves in Series shift register SPI Master MOSI MISO SCK _SS MOSI MISO SCK _SS shift register MOSI MISO SCK _SS shift register SPI Slave 0 SPI Slave n-1 25.6.3.4 Loop-back Mode By configuring the Data In Pinout (CTRLA.DIPO) and Data Out Pinout (CTRLA.DOPO) to use the same data pins for transmit and receive, loop-back is achieved. The loop-back is through the pad, so the signal is also available externally. 25.6.3.5 Hardware Controlled _SS In master mode, a single _SS chip select can be controlled by hardware by setting the Master Slave Select Enable (CTRLB.MSSEN) bit to one. In this mode, the _SS pin is driven low for a minimum of one baud cycle before transmission begins, and stays low for a minimum of one baud cycle after transmission completes. If back-to-back frames are transmitted, the _SS pin will always be driven high for a minimum of one baud cycle between frames. In Figure 25-7, the time T is between one and two baud cycles depending on the SPI transfer mode. Figure 25-7. Hardware Controlled _SS T T T T T _SS SCK T = 1 to 2 baud cycles When MSSEN is set to zero, the _SS pin(s) is/are controlled by user software and normal GPIO. 25.6.3.6 Slave Select Low Detection In slave mode the SPI is capable of waking the CPU when the slave select (_SS) goes low. When the Slave Select Low Detect is enabled (CTRLB.SSDE=1), a high to low transition will set the Slave Select Low interrupt flag (INTFLAG.SSL) and the device will wake if applicable. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 480 25.6.4 DMA, Interrupts and Events Table 25-3. Module Request for SERCOM SPI Condition Interrupt request Data Register Empty x Transmit Complete x Receive Complete x Slave Select low x Error x Event output Event input DMA request DMA request is cleared x When data is written x When data is read 25.6.4.1 DMA Operation The SPI generates the following DMA requests: z Data received (RX): The request is set when data is available in the receive FIFO. The request is cleared when DATA is read. z Data transmit (TX): The request is set when the transmit buffer (TX DATA) is empty. The request is cleared when DATA is written. 25.6.4.2 Interrupts The SPI has the following interrupt sources: z Error (ERROR): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. z Slave Select Low (SSL): his is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. z Receive Complete (RXC): his is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. z Transmit Complete (TXC): his is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. z Data Register Empty (DRE): his is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the SPI is reset. See the register description for details on how to clear interrupt flags. The SPI has one common interrupt request line for all the interrupt sources. The user must read INTFLAG to determine which interrupt condition is present. Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to "Nested Vector Interrupt Controller" on page 29 for details. For details on clearing interrupt flags, refer to INTFLAG. 25.6.4.3 Events Not applicable. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 481 25.6.5 Sleep Mode Operation During master operation, the generic clock will continue to run in idle sleep mode. If the Run In Standby bit in the Control A register (CTRLA.RUNSTDBY) is one, the GCLK_SERCOM_CORE will also be enabled in standby sleep mode. Any interrupt can wake up the device. If CTRLA.RUNSTDBY is zero during master operation, GLK_SERCOMx_CORE will be disabled when the ongoing transaction is finished. Any interrupt can wake up the device. During slave operation, writing a one to CTRLA.RUNSTDBY will allow the Receive Complete interrupt to wake up the device. If CTRLA.RUNSTDBY is zero during slave operation, all reception will be dropped, including the ongoing transaction. 25.6.6 Synchronization Due to the asynchronicity between CLK_SERCOMx_APB and GCLK_SERCOMx_CORE, some registers must be synchronized when accessed. A register can require: z Synchronization when written z Synchronization when read z Synchronization when written and read z No synchronization When executing an operation that requires synchronization, the corresponding Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY) will be set immediately, and cleared when synchronization is complete. If an operation that requires synchronization is executed while the corresponding SYNCBUSY bit is one, a peripheral bus error is generated. The following bits need synchronization when written: z Software Reset bit in the Control A register (CTRLA.SWRST). SYNCBUSY.SWRST is set to one while synchronization is in progress. z Enable bit in the Control A register (CTRLA.ENABLE). SYNCBUSY.ENABLE is set to one while synchronization is in progress. z Receiver Enable bit in the Control B register (CTRLB.RXEN). SYNCBUSY.CTRLB is set to one while synchronization is in progress. CTRLB.RXEN behaves somewhat differently than described above. Refer to CTRLB for details. Write-synchronization is denoted by the Write-Synchronized property in the register description. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 482 25.7 Offset Register Summary Name 0x00 Bit Pos. 7:0 0x01 RUNSTDBY MODE[2:0] ENABLE SWRST IBON 15:8 CTRLA DIPO[1:0] 0x02 23:16 0x03 31:24 DORD 0x04 7:0 PLOADEN 0x05 15:8 AMODE[1:0] CPOL DOPO[1:0] CPHA FORM[3:0] CHSIZE[2:0] MSSEN SSDE CTRLB 0x06 23:16 0x07 31:24 0x08 Reserved 0x09 Reserved 0x0A Reserved 0x0B Reserved 0x0C BAUD 0x0D Reserved 0x0E Reserved 0x0F Reserved 0x10 Reserved 0x11 Reserved 0x12 Reserved 0x13 Reserved 0x14 INTENCLR 0x15 Reserved 0x16 INTENSET 0x17 Reserved 0x18 INTFLAG 0x19 Reserved 0x1A RXEN 7:0 BAUD[7:0] 7:0 ERROR SSL RXC TXC DRE 7:0 ERROR SSL RXC TXC DRE 7:0 ERROR SSL RXC TXC DRE ENABLE SWRST 7:0 BUFOVF STATUS 0x1B 15:8 0x1C 7:0 0x1D CTRLB 15:8 SYNCBUSY 0x1E 23:16 0x1F 31:24 0x20 Reserved 0x21 Reserved 0x22 Reserved 0x23 Reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 483 Offset Name 0x24 Bit Pos. 7:0 0x25 ADDR[7:0] 15:8 ADDR 0x26 23:16 0x27 31:24 0x28 7:0 ADDRMASK[7:0] DATA[7:0] DATA 0x29 0x2A Reserved 0x2B Reserved 0x2C Reserved 0x2D Reserved 0x2E Reserved 0x2F Reserved 0x30 DBGCTRL 15:8 DATA[8] 7:0 DBGSTOP Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 484 25.8 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protected property in each individual register description. Refer to "Register Access Protection" on page 474 for details. Some registers require synchronization when read and/or written. Write-synchronization is denoted by the WriteSynchronized property in each individual register description. Refer to "Synchronization" on page 482 for details. Some registers are enable-protected, meaning they can only be written when the USART is disabled. Enable-protection is denoted by the Enable-Protected property in each individual register description. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 485 25.8.1 Control A Name: CTRLA Offset: 0x00 Reset: 0x00000000 Property: Write-Protected, Enable-Protected, Write-Synchronized Bit 31 30 29 28 DORD CPOL CPHA 27 26 25 24 FORM[3:0] Access R R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DIPO[1:0] DOPO[1:0] Access R R R/W R/W R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 IBON Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ENABLE SWRST MODE[2:0] RUNSTDBY Access Reset R/W R R R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bit 31 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 30 - DORD: Data Order This bit indicates the data order when a character is shifted out from the Data register. 0: MSB is transferred first. 1: LSB is transferred first. This bit is not synchronized. z Bit 29 - CPOL: Clock Polarity In combination with the Clock Phase bit (CPHA), this bit determines the SPI transfer mode. 0: SCK is low when idle. The leading edge of a clock cycle is a rising edge, while the trailing edge is a falling edge. 1: SCK is high when idle. The leading edge of a clock cycle is a falling edge, while the trailing edge is a rising edge. This bit is not synchronized. z Bit 28 - CPHA: Clock Phase In combination with the Clock Polarity bit (CPOL), this bit determines the SPI transfer mode. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 486 0: The data is sampled on a leading SCK edge and changed on a trailing SCK edge. 1: The data is sampled on a trailing SCK edge and changed on a leading SCK edge. This bit is not synchronized. Table 25-4. SPI Transfer Modes Mode CPOL CPHA Leading Edge Trailing Edge 0x0 0 0 Rising, sample Falling, change 0x1 0 1 Rising, change Falling, sample 0x2 1 0 Falling, sample Rising, change 0x3 1 1 Falling, change Rising, sample z Bits 27:24 - FORM[3:0]: Frame Format Table 25-5 shows the various frame formats supported by the SPI. When a frame format with address is selected, the first byte received is checked against the ADDR register. Table 25-5. Frame Format FORM[3:0] Name Description 0x0 SPI SPI frame 0x1 - Reserved 0x2 SPI_ADDR SPI frame with address 0x3-0xF - Reserved z Bits 23:22 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 21:20 - DIPO[1:0]: Data In Pinout These bits define the data in (DI) pad configurations. In master operation, DI is MISO. In slave operation, DI is MOSI. These bits are not synchronized. Table 25-6. Data In Pinout DIPO[1:0] Name Description 0x0 PAD[0] SERCOM PAD[0] is used as data input 0x1 PAD[1] SERCOM PAD[1] is used as data input 0x2 PAD[2] SERCOM PAD[2] is used as data input 0x3 PAD[3] SERCOM PAD[3] is used as data input z Bits 19:18 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 487 z Bit 17:16 - DOPO: Data Out Pinout This bit defines the available pad configurations for data out (DO) and the serial clock (SCK). In slave operation, the slave select line (_SS) is controlled by DOPO, while in master operation the _SS line is controlled by the port configuration. In master operation, DO is MOSI. In slave operation, DO is MISO. These bits are not synchronized. Table 25-7. Data Out Pinout DOPO DO SCK Slave_SS Master_SS 0x0 PAD[0] PAD[1] PAD[2] System configuration 0x1 PAD[2] PAD[3] PAD[1] System configuration 0x2 PAD[3] PAD[1] PAD[2] System configuration 0x3 PAD[0] PAD[3] PAD[1] System configuration z Bits 15:9 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 8 - IBON: Immediate Buffer Overflow Notification This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is asserted when a buffer overflow occurs. 0: STATUS.BUFOVF is asserted when it occurs in the data stream. 1: STATUS.BUFOVF is asserted immediately upon buffer overflow. This bit is not synchronized. z Bit 7 - RUNSTDBY: Run In Standby This bit defines the functionality in standby sleep mode. These bits are not synchronized. Table 25-8. Run In Standby Configuration RUNSTDBY Slave Master 0x0 Disabled. All reception is dropped, including the ongoing transaction. Generic clock is disabled when ongoing transaction is finished. All interrupts can wake up the device. 0x1 Wake on Receive Complete interrupt. Generic clock is enabled while in sleep modes. All interrupts can wake up the device. z Bits 6:5 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 4:2 - MODE: Operating Mode These bits must be written to 0x2 or 0x3 to select the SPI serial communication interface of the SERCOM. 0x2: SPI slave operation 0x3: SPI master operation These bits are not synchronized. z Bit 1 - ENABLE: Enable 0: The peripheral is disabled or being disabled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 488 1: The peripheral is enabled or being enabled. Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately and the Synchronization Enable Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE is cleared when the operation is complete. This bit is not enable-protected. z Bit 0 - SWRST: Software Reset 0: There is no reset operation ongoing. 1: The reset operation is ongoing. Writing a zero to this bit has no effect. Writing a one to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled. Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register will return the reset value of the register. Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY. SWRST will both be cleared when the reset is complete. This bit is not enable-protected. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 489 25.8.2 Control B Name: CTRLB Offset: 0x04 Reset: 0x00000000 Property: Write-Protected, Enable-Protected Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 RXEN Access R R R R R R R/W R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 MSSEN AMODE[1:0] Access SSDE R/W R/W R/W R R R R/W R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PLOADEN CHSIZE[2:0] Access R R/W R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 31:18 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 17 - RXEN: Receiver Enable 0: The receiver is disabled or being enabled. 1: The receiver is enabled or it will be enabled when SPI is enabled. Writing a zero to this bit will disable the SPI receiver immediately. The receive buffer will be flushed, data from ongoing receptions will be lost and STATUS.BUFOVF will be cleared. Writing a one to CTRLB.RXEN when the SPI is disabled will set CTRLB.RXEN immediately. When the SPI is enabled, CTRLB.RXEN will be cleared, SYNCBUSY.CTRLB will be set and remain set until the receiver is enabled. When the receiver is enabled CTRLB.RXEN will read back as one. Writing a one to CTRLB.RXEN when the SPI is enabled will set SYNCBUSY.CTRLB, which will remain set until the receiver is enabled, and CTRLB.RXEN will read back as one. This bit is not enable-protected. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 490 z Bit 16 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 15:14 - AMODE: Address Mode These bits set the slave addressing mode when the frame format (CTRLA.FORM) with address is used. They are unused in master mode. Table 25-9. Address Mode AMODE[1:0] Name Description 0x0 MASK ADDRMASK is used as a mask to the ADDR register 0x1 2_ADDRS The slave responds to the two unique addresses in ADDR and ADDRMASK 0x2 RANGE The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit 0x3 z Reserved Bit 13 - MSSEN: Master Slave Select Enable This bit enables hardware slave select (_SS) control. 0: Hardware _SS control is disabled. 1: Hardware _SS control is enabled. z Bits 12:10 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 9 - SSDE: Slave Select Low Detect Enable This bit enables wake up when the slave select (_SS) pin transitions from high to low. 0: _SS low detector is disabled. 1: _SS low detector is enabled. z Bits 8:7 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 6 - PLOADEN: Slave Data Preload Enable Setting this bit will enable preloading of the slave shift register when there is no transfer in progress. If the _SS line is high when DATA is written, it will be transferred immediately to the shift register. z Bits 5:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 2:0 - CHSIZE[2:0]: Character Size Table 25-10. Character Size CHSIZE[2:0] Name Description 0x0 8BIT 8 bits 0x1 9BIT 9 bits 0x2-0x7 Reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 491 25.8.3 Baud Rate Name: BAUD Offset: 0x0C Reset: 0x00 Property: Write-Protected, Enable-Protected Bit 7 6 5 4 3 2 1 0 BAUD[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - BAUD: Baud Register These bits control the clock generation, as described in the SERCOM "Clock Generation - Baud-Rate Generator" on page 429. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 492 25.8.4 Interrupt Enable Clear This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Name: INTENCLR Offset: 0x14 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 ERROR Access Reset z 3 2 1 0 SSL RXC TXC DRE R/W R R R R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7- ERROR: Error Interrupt Enable 0: Error interrupt is disabled. 1: Error interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt. z Bits 6:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 3- SSL: Slave Select Low Interrupt Enable 0: Slave Select Low interrupt is disabled. 1: Slave Select Low interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Slave Select Low Interrupt Enable bit, which disables the Slave Select Low interrupt. z Bit 2 - RXC: Receive Complete Interrupt Enable 0: Receive Complete interrupt is disabled. 1: Receive Complete interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Receive Complete Interrupt Enable bit, which disables the Receive Complete interrupt. z Bit 1 - TXC: Transmit Complete Interrupt Enable 0: Transmit Complete interrupt is disabled. 1: Transmit Complete interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Transmit Complete Interrupt Enable bit, which disable the Transmit Complete interrupt. z Bit 0 - DRE: Data Register Empty Interrupt Enable 0: Data Register Empty interrupt is disabled. 1: Data Register Empty interrupt is enabled. Writing a zero to this bit has no effect. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 493 Writing a one to this bit will clear the Data Register Empty Interrupt Enable bit, which disables the Data Register Empty interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 494 25.8.5 Interrupt Enable Set This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Name: INTENSET Offset: 0x16 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 ERROR Access Reset z 3 2 1 0 SSL RXC TXC DRE R/W R R R R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 - ERROR: Error Interrupt Enable 0: Error interrupt is disabled. 1: Error interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt. z Bits 6:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 3 - SSL: Slave Select Low Interrupt Enable 0: Slave Select Low interrupt is disabled. 1: Slave Select Low interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Slave Select Low Interrupt Enable bit, which enables the Slave Select Low interrupt. z Bit 2 - RXC: Receive Complete Interrupt Enable 0: Receive Complete interrupt is disabled. 1: Receive Complete interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Receive Complete Interrupt Enable bit, which enables the Receive Complete interrupt. z Bit 1 - TXC: Transmit Complete Interrupt Enable 0: Transmit Complete interrupt is disabled. 1: Transmit Complete interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Transmit Complete Interrupt Enable bit, which enables the Transmit Complete interrupt. z Bit 0 - DRE: Data Register Empty Interrupt Enable 0: Data Register Empty interrupt is disabled. 1: Data Register Empty interrupt is enabled. Writing a zero to this bit has no effect. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 495 Writing a one to this bit will set the Data Register Empty Interrupt Enable bit, which enables the Data Register Empty interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 496 25.8.6 Interrupt Flag Status and Clear Name: INTFLAG Offset: 0x18 Reset: 0x00 Property: - Bit 7 6 5 4 ERROR Access Reset z 3 2 1 0 SSL RXC TXC DRE R/W R R R R/W R R/W R 0 0 0 0 0 0 0 0 Bit 7 - ERROR: Error This flag is cleared by writing a one to it. This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STATUS register. The BUFOVF error will set this interrupt flag. Writing a zero to this bit has no effect. Writing a one to this bit will clear the flag. z Bits 6:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 3 - SSL: Slave Select Low This flag is cleared by writing a one to it. This bit is set when a high to low transition is detected on the _SS pin in slave mode and Slave Select Low Detect (CTRLB.SSDE) is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the flag. z Bit 2 - RXC: Receive Complete This flag is cleared by reading the Data (DATA) register or by disabling the receiver. This flag is set when there are unread data in the receive buffer. If address matching is enabled, the first data received in a transaction will be an address. Writing a zero to this bit has no effect. Writing a one to this bit has no effect. z Bit 1 - TXC: Transmit Complete This flag is cleared by writing a one to it or by writing new data to DATA. In master mode, this flag is set when the data have been shifted out and there are no new data in DATA. In slave mode, this flag is set when the _SS pin is pulled high. If address matching is enabled, this flag is only set if the transaction was initiated with an address match. Writing a zero to this bit has no effect. Writing a one to this bit will clear the flag. z Bit 0 - DRE: Data Register Empty This flag is cleared by writing new data to DATA. This flag is set when DATA is empty and ready for new data to transmit. Writing a zero to this bit has no effect. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 497 Writing a one to this bit has no effect. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 498 25.8.7 Status Name: STATUS Offset: 0x1A Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BUFOVF Access R R R R R R/W R R Reset 0 0 0 0 0 0 0 0 z Bits 15:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 2 - BUFOVF: Buffer Overflow Reading this bit before reading DATA will indicate the error status of the next character to be read. This bit is cleared by writing a one to the bit or by disabling the receiver. This bit is set when a buffer overflow condition is detected. An overflow condition occurs if the two-level receive buffer is full when the last bit of the incoming character is shifted into the shift register. All characters shifted into the shift registers before the overflow condition is eliminated by reading DATA will be lost. When set, the corresponding RxDATA will be 0. Writing a zero to this bit has no effect. Writing a one to this bit will clear it. z Bits 1:0 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 499 25.8.8 Synchronization Busy Name: SYNCBUSY Offset: 0x1C Reset: 0x00000000 Property: Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CTRLB ENABLE SWRST Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 31:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 2- CTRLB: CTRLB Synchronization Busy Writing CTRLB when the SERCOM is enabled requires synchronization. When written, the SYNCBUSY.CTRLB bit will be set until synchronization is complete. If CTRLB is written while SYNCBUSY.CTRLB is asserted, an APB error will be generated. 0: CTRLB synchronization is not busy. 1: CTRLB synchronization is busy. z Bit 1 - ENABLE: SERCOM Enable Synchronization Busy Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the SYNCBUSY.ENABLE bit will be set until synchronization is complete. Writes to any register (except for CTRLA.SWRST) while enable synchronization is on-going will be discarded and an APB error will be generated. 0: Enable synchronization is not busy. 1: Enable synchronization is busy. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 500 z Bit 0 - SWRST: Software Reset Synchronization Busy Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the SYNCBUSY.SWRST bit will be set until synchronization is complete. Writes to any register while synchronization is on-going will be discarded and an APB error will be generated. 0: SWRST synchronization is not busy. 1: SWRST synchronization is busy. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 501 25.8.9 Address Name: ADDR Offset: 0x24 Reset: 0x00000000 Property: Write-Protected, Enable-Protected Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 ADDRMASK[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADDR[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 31:24 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 23:16 - ADDRMASK[7:0]: Address Mask These bits hold the address mask when the transaction format (CTRLA.FORM) with address is used. z Bits 15:8 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 7:0 - ADDR[7:0]: Address These bits hold the address when the transaction format (CTRLA.FORM) with address is used. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 502 25.8.10 Data Name: DATA Offset: 0x28 Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 9 8 DATA[8] Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 15:9 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 8:0 - DATA[8:0]: Data Reading these bits will return the contents of the receive data buffer. The register should be read only when the Receive Complete Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.RXC) is set. Writing these bits will write the transmit data buffer. This register should be written only when the Data Register Empty Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.DRE) is set. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 503 25.8.11 Debug Control Name: DBGCTRL Offset: 0x30 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 DBGSTOP Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:1 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 0 - DBGSTOP: Debug Stop Mode This bit controls the functionality when the CPU is halted by an external debugger. 0: The baud-rate generator continues normal operation when the CPU is halted by an external debugger. 1: The baud-rate generator is halted when the CPU is halted by an external debugger. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 504 26. SERCOM I2C - SERCOM Inter-Integrated Circuit 26.1 Overview The inter-integrated circuit (I2C) interface is one of the available modes in the serial communication interface (SERCOM). Refer to "SERCOM - Serial Communication Interface" on page 426 for details. The I2C interface uses the SERCOM transmitter and receiver configured as shown in Figure 26-1. Fields shown in capital letters are registers accessible by the CPU, while lowercase fields are internal to the SERCOM. Each side, master and slave, depicts a separate I2C interface containing a shift register, a transmit buffer and a receive buffer. In addition, the I2C master uses the SERCOM baud-rate generator, while the I2C slave uses the SERCOM address match logic. 26.2 Features z Master or slave operation z Can be used with DMA z Philips I2C compatible z SMBusTM compatible z PMBus compatible z 100kHz and 400kHz, 1MHz and 3.4MHz support at low system clock frequencies z Physical interface includes: z z Slew-rate limited outputs Filtered inputs z Slave operation: Operation in all sleep modes Wake-up on address match z 7-bit and 10-bit Address match in hardware for: z Unique address and/or 7-bit general call address z Address range z Two unique addresses can be used with DMA z z 26.3 Block Diagram Figure 26-1. I2C Single-Master Single-Slave Interconnection Master BAUD Tx DATA 0 baud rate generator Slave Tx DATA SCL ADDR/ADDRMASK 0 SCL low o hold SCL low hold shift register shift register 0 Rx DATA SDA 0 Rx DATA == Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 505 26.4 Signal Description Signal Name Type Description PAD[0] Digital I/O SDA PAD[1] Digital I/O SCL PAD[2] Digital I/O SDA_OUT (4-wire) PAD[3] Digital I/O SDC_OUT (4-wire) Refer to "I/O Multiplexing and Considerations" on page 12 for details on the pin mapping for this peripheral. One signal can be mapped on several pins. Note that not all the pins are I2C pins. Refer to Table 5-1 for details on the pin type for each pin. 26.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 26.5.1 I/O Lines Using the SERCOM's I/O lines requires the I/O pins to be configured. Refer to "PORT" on page 373 for details. 26.5.2 Power Management The I2C will continue to operate in any sleep mode where the selected source clock is running. I2C interrupts can be used to wake up the device from sleep modes. The events can trigger other operations in the system without exiting sleep modes. Refer to "PM - Power Manager" on page 112 for details on the different sleep modes. 26.5.3 Clocks The SERCOM bus clock (CLK_SERCOMx_APB, where i represents the specific SERCOM instance number) is enabled by default, and can be enabled and disabled in the Power Manager. Refer to "PM - Power Manager" on page 112 for details. The SERCOM bus clock (CLK_SERCOMx_APB) is enabled by default, and can be enabled and disabled in the Power Manager. Refer to "PM - Power Manager" on page 112 for details. Two generic clocks are used by the SERCOM (GCLK_SERCOMx_CORE and GCLK_SERCOM_SLOW). The core clock (GCLK_SERCOMx_CORE) is required to clock the SERCOM while operating as a master, while the slow clock (GCLK_SERCOM_SLOW) is required only for certain functions. These clocks must be configured and enabled in the Generic Clock Controller (GCLK) before using the SERCOM. Refer to "GCLK - Generic Clock Controller" on page 90 for details. These generic clocks are asynchronous to the SERCOM bus clock (CLK_SERCOMx_APB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. Refer to the "Synchronization" on page 524 section for further details. 26.5.4 DMA The DMA request lines are connected to the DMA controller (DMAC). Using the SERCOM DMA requests, requires the DMA controller to be configured first. Refer to "DMAC - Direct Memory Access Controller" on page 267 for details. 26.5.5 Interrupts The interrupt request line is connected to the Interrupt Controller. Using the I2C interrupts requires the Interrupt Controller to be configured first. Refer to "Nested Vector Interrupt Controller" on page 29 for details. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 506 26.5.6 Events Not applicable. 26.5.7 Debug Operation When the CPU is halted in debug mode, the I2C interface continues normal operation. If the I2C interface is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. The I2C interface can be forced to halt operation during debugging. Refer to the DBGCTRL register for details. 26.5.8 Register Access Protection All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the following registers: z Interrupt Flag Status and Clear register (INTFLAG) z Status register (STATUS) z Address register (ADDR) z Data register (DATA) Write-protection is denoted by the Write-Protected property in the register description. Write-protection does not apply to accesses through en external debugger. Refer to"PAC - Peripheral Access Controller" on page 36 for details. 26.5.9 Analog Connections Not applicable. 26.6 Functional Description 26.6.1 Principle of Operation The I2C interface uses two physical lines for communication: z Serial Data Line (SDA) for packet transfer z Serial Clock Line (SCL) for the bus clock A transaction starts with the start condition, followed by a 7-bit address and a direction bit (read or write) sent from the I2C master. The addressed I2C slave will then acknowledge (ACK) the address, and data packet transactions can commence. Every 9-bit data packet consists of 8 data bits followed by a one-bit reply indicating whether the data was acknowledged or not. In the event that a data packet is not acknowledged (NACK), whether sent from the I2C slave or master, it will be up to the I2C master to either terminate the connection by issuing the stop condition, or send a repeated start if more data is to be transceived. Figure 26-2 illustrates the possible transaction formats and Figure 26-3 explains the legend used. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 507 Figure 26-2. Basic I2C Transaction Diagram SDA SCL 6 ... 0 S ADDRESS S 7 ... 0 R/W ADDRESS ACK R/W A 7 ... 0 DATA ACK DATA A DATA P ACK/NACK DATA A/A P Direction Address Packet Data Packet #0 Data Packet #1 Transaction Figure 26-3. Transaction Diagram Syntax Bus Driver: Master Drives Bus S START Condition Slave Drives Bus Sr Repeated START Condition Either Master or Slave Drives Bus P STOP Condition Data Packet Direction: R Master Read "1" W Special Bus Conditions Acknowledge: A Acknowledge (ACK) "0" Master Write "0" A Not Acknowledge (NACK) "1" 26.6.2 Basic Operation 26.6.2.1 Initialization The following registers are enable-protected, meaning they can be written only when the I2C interface is disabled (CTRLA.ENABLE is zero): z Control A register (CTRLA), except Enable (CTRLA.ENABLE) and Software Reset (CTRLA.SWRST) z Control B register (CTRLB), except Acknowledge Action (CTRLB.ACKACT) and Command (CTRLB.CMD) z Baud Rate register (BAUD) z Address register (ADDR) while in slave operation Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 508 Any writes to these bits or registers when the I2C interface is enabled or is being enabled (CTRLA.ENABLE is one) will be discarded. Writes to these registers while the I2C interface is being disabled will be completed after the disabling is complete. Enable-protection is denoted by the Enable-Protection property in the register description. Before the I2C interface is enabled, it must be configured as outlined by the following steps: I2C mode in master or slave operation must be selected by writing 0x4 or 0x5 to the Operating Mode bit group in the Control A register (CTRLA.MODE) z SCL low time-out can be enabled by writing to the SCL Low Time-Out bit in the Control A register (CTRLA.LOWTOUT) z In master operation, the inactive bus time-out can be set in the Inactive Time-Out bit group in the Control A register (CTRLA.INACTOUT) z Hold time for SDA can be set in the SDA Hold Time bit group in the Control A register (CTRLA.SDAHOLD) z Smart operation can be enabled by writing to the Smart Mode Enable bit in the Control B register (CTRLB.SMEN) z In slave operation, the address match configuration must be set in the Address Mode bit group in the Control B register (CTRLB.AMODE) z In slave operation, the addresses must be set, according to the selected address configuration, in the Address and Address Mask bit groups in the Address register (ADDR.ADDR and ADDR.ADDRMASK) z In master operation, the Baud Rate register (BAUD) must be written to generate the desired baud rate 26.6.2.2 Enabling, Disabling and Resetting The I2C interface is enabled by writing a one to the Enable bit in the Control A register (CTRLA.ENABLE). The I2C interface is disabled by writing a zero to CTRLA.ENABLE. The I2C interface is reset by writing a one to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in the I2C interface, except DBGCTRL, will be reset to their initial state, and the I2C interface will be disabled. Refer to CTRLA for details. 26.6.2.3 I2C Bus State Logic The bus state logic includes several logic blocks that continuously monitor the activity on the I2C bus lines in all sleep modes. The start and stop detectors and the bit counter are all essential in the process of determining the current bus state. The bus state is determined according to the state diagram shown in Figure 26-4. Software can get the current bus state by reading the Master Bus State bits in the Status register (STATUS.BUSSTATE). The value of STATUS.BUSSTATE in the figure is shown in binary. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 509 Figure 26-4. Bus State Diagram RESET UNKNOWN (0b00) P + Timeout Sr S IDLE (0b01) BUSY (0b11) P + Timeout Command P Write ADDR (S) Arbitration Lost OWNER (0b10) Write ADDR(Sr) The bus state machine is active when the I2C master is enabled. After the I2C master has been enabled, the bus state is unknown. From the unknown state, the bus state machine can be forced to enter the idle state by writing to STATUS.BUSSTATE accordingly. However, if no action is taken by software, the bus state will become idle if a stop condition is detected on the bus. If the inactive bus time-out is enabled, the bus state will change from unknown to idle on the occurrence of a time-out. Note that after a known bus state is established, the bus state logic will not re-enter the unknown state from either of the other states. When the bus is idle it is ready for a new transaction. If a start condition is issued on the bus by another I2C master in a multimaster setup, the bus becomes busy until a stop condition is detected. The stop condition will cause the bus to reenter the IDLE state. If the inactive bus time-out (SMBus) is enabled, the bus state will change from busy to idle on the occurrence of a time-out. If a start condition is generated internally by writing the Address bit group in the Address register (ADDR.ADDR) while in idle state, the owner state is entered. If the complete transaction was performed without interference, i.e., arbitration not lost, the I2C master is allowed to issue a stop condition, which in turn will cause a change of the bus state back to idle. However, if a packet collision is detected when in the owner state, the arbitration is assumed lost and the bus state becomes busy until a stop condition is detected. A repeated start condition will change the bus state only if arbitration is lost while issuing a repeated start. 26.6.2.4 Clock Generation (Standard-mode, Fast-mode and Fast-mode Plus Transfers) The Master I2C clock (SCL) frequency is determined by a number of factors. The low (TLOW) and high (T_HIGH) times are determined by the Baud Rate register (BAUD), while the rise (TRISE) and fall (TFALL) times are determined by the bus topology. Because of the wired-AND logic of the bus, TFALL will be considered as part of TLOW. Likewise, TRISE will be in a state between TLOW and THIGH until a high state has been detected. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 510 Figure 26-5. SCL Timing TRISE P TLOW S Sr SCL THIGH TBUF TFALL SDA THD;STA TSU;STO TSU;STA The following parameters are timed using the SCL low time period. This comes from the Master Baud Rate Low bit group in the Baud Rate register (BAUD.BAUDLOW) when non-zero, or the Master Baud Rate bit group in the Baud Rate register (BAUD.BAUD) when BAUD.BAUDLOW is zero. z TLOW - Low period of SCL clock z TSU;STO - Set-up time for stop condition z TBUF - Bus free time between stop and start conditions z THD;STA - Hold time (repeated) start condition z TSU;STA - Set-up time for repeated start condition z THIGH is timed using the SCL high time count from BAUD.BAUD z TRISE is determined by the bus impedance; for internal pull-ups. Refer to "Electrical Characteristics" on page 1055 for details. z TFALL is determined by the open-drain current limit and bus impedance; can typically be regarded as zero. Refer to "Electrical Characteristics" on page 1055 for details. The SCL frequency is given by: f SCL = 1 TLOW + THIGH + TRISE When BAUD.BAUDLOW is zero, the BAUD.BAUD value is used to time both SCL high and SCL low. In this case the following formula will give the SCL frequency: f SCL = f GCLK 2(5 + BAUD) + f GCLK TRISE When BAUD.BAUDLOW is non-zero, the following formula is used to determine the SCL frequency: f SCL = f GCLK 10 + BAUD + BAUDLOW + f GCLK TRISE Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 511 When BAUDLOW is non-zero, the following formula can be used to determine the SCL frequency: f SCL = f GCLK 10 + BAUD + BAUDLOW + f GCLK TRISE The following formulas can be used to determine the SCL TLOW and THIGH times: T low T HIGH BAUD.BAUDLOW + 5 f GCLK = = BAUD.BAUD + 5 f GCLK For Fast-mode Plus the nominal high to low SCL ratio is 1 to 2 and BAUD should be set accordingly. At a minimum, BAUD.BAUD and/or BAUD.BAUDLOW must be non-zero. 26.6.2.5 Master Clock Generation (High-speed mode Transfer) For High-speed mode transfers, there is no SCL synchronization, so the SCL frequency is determined by the GCLK frequency and the High-speed BAUD setting. When HSBAUDLOW is zero, the HSBAUD value is used to time both SCL high and SCL low. In this case the following formula can be used to determine the SCL frequency. f SCL = f GCLK 2(1 + HSBAUD ) When HSBAUDLOW is non-zero, the following formula can be used to determine the SCL frequency. f SCL = f GCLK 2 + HSBAUD + HSBAUDLOW For High-speed the nominal high to low SCL ratio is 1 to 2 and HSBAUD should be set accordingly. At a minimum, BAUD.BAUD and/or BAUD.BAUDLOW must be non-zero. 26.6.2.6 I2C Master Operation The I2C master is byte-oriented and interrupt based. The number of interrupts generated is kept at a minimum by automatic handling of most events. Auto-triggering of operations and a special smart mode, which can be enabled by writing a one to the Smart Mode Enable bit in the Control A register (CTRLA.SMEN), are included to reduce software driver complexity and code size. The I2C master has two interrupt strategies. When SCL Stretch Mode (CTRLA.SCLSM) is set to zero, SCL is stretched before or after the acknowledge bit . In this mode the I2C master operates according to the behavior diagram shown in Figure 26-6. The circles with a capital letter M followed by a number (M1, M2... etc.) indicate which node in the figure the bus logic can jump to based on software or hardware interaction. This diagram is used as reference for the description of the I2C master operation throughout the document. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 512 Figure 26-6. I2C Master Behavioral Diagram (SCLSM=0) APPLICATION MASTER WRITE INTERRUPT + SCL HOLD M1 M2 BUSY S W P M3 IDLE S Wait for IDLE M4 ADDRESS R/W BUSY S W R/W A S W P S W Sr W A M1 BUSY M2 IDLE M3 S W BUSY DATA M4 A/A MASTER READ INTERRUPT+ SCL HOLD S W S W Software interaction A BUSY The master provides data on the bus A/A Addressed slave provides data on the bus A/A Sr P IDLE M4 M2 M3 A/A R A DATA In the second strategy (SCLSM=1), interrupts only occur after the ACK bit as shown in Figure 26-7. This strategy can be used when it is not necessary to check DATA before acknowledging. Note that setting SCLSM to 1 is required for High-speed mode. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 513 Figure 26-7. I2C Master Behavioral Diagram (SCLSM=1) APPLICATION MASTER WRITE INTERRUPT + SCL HOLD M1 M2 BUSY S W P M3 IDLE S Wait for IDLE M4 ADDRESS R/W BUSY S W R/W A S W P S W Sr W A M1 BUSY M2 IDLE S W M3 BUSY DATA M4 A/A MASTER READ INTERRUPT+ SCL HOLD S W S W Software interaction BUSY The master provides data on the bus P Addressed slave provides data on the bus Sr R A IDLE M4 M2 M3 DATA A/A Transmitting Address Packets The I2C master starts a bus transaction by writing ADDR.ADDR with the I2C slave address and the direction bit. If the bus is busy, the I2C master will wait until the bus becomes idle before continuing the operation. When the bus is idle, the I2C master will issue a start condition on the bus. The I2C master will then transmit an address packet using the address written to ADDR.ADDR. After the address packet has been transmitted by the I2C master, one of four cases will arise, based on arbitration and transfer direction. Case 1: Arbitration lost or bus error during address packet transmission If arbitration was lost during transmission of the address packet, the Master on Bus bit in the Interrupt Flag register (INTFLAG.MB) and the Arbitration Lost bit in the Status register (STATUS.ARBLOST) are both set. Serial data output to SDA is disabled, and the SCL is released, which disables clock stretching. In effect the I2C master is no longer allowed to perform any operation on the bus until the bus is idle again. A bus error will behave similarly to the arbitration lost condition. In this case, the MB interrupt flag and Master Bus Error bit in the Status register (STATUS.BUSERR) are both set in addition to STATUS.ARBLOST. The Master Received Not Acknowledge bit in the Status register (STATUS.RXNACK) will always contain the last successfully received acknowledge or not acknowledge indication. In this case, software will typically inform the application code of the condition and then clear the interrupt flag before exiting the interrupt routine. No other flags have to be cleared at this point, because all flags will be cleared automatically the next time the ADDR.ADDR register is written. Case 2: Address packet transmit complete - No ACK received If no I2C slave device responds to the address packet, then the INTFLAG.MB interrupt flag is set and STATUS.RXNACK is set. The clock hold is active at this point, preventing further activity on the bus. The missing ACK response can indicate that the I2C slave is busy with other tasks or sleeping and, therefore, not able to respond. In this event, the next step can be either issuing a stop condition (recommended) or resending the address Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 514 packet by using a repeated start condition. However, the reason for the missing acknowledge can be that an invalid I2C slave address has been used or that the I2C slave is for some reason disconnected or faulty. If using SMBus logic, the slave must ACK the address, and hence no action means the slave is not available on the bus. Case 3: Address packet transmit complete - Write packet, Master on Bus set If the I2C master receives an acknowledge response from the I2C slave, INTFLAG.MB is set and STATUS.RXNACK is cleared. The clock hold is active at this point, preventing further activity on the bus. In this case, the software implementation becomes highly protocol dependent. Three possible actions can enable the I2C operation to continue. The three options are: z The data transmit operation is initiated by writing the data byte to be transmitted into DATA.DATA. z Transmit a new address packet by writing ADDR.ADDR. A repeated start condition will automatically be inserted before the address packet. z Issue a stop condition, consequently terminating the transaction. Case 4: Address packet transmit complete - Read packet, Slave on Bus set If the I2C master receives an ACK from the I2C slave, the I2C master proceeds to receive the next byte of data from the I2C slave. When the first data byte is received, the Slave on Bus bit in the Interrupt Flag register (INTFLAG.SB) is set and STATUS.RXNACK is cleared. The clock hold is active at this point, preventing further activity on the bus. In this case, the software implementation becomes highly protocol dependent. Three possible actions can enable the I2C operation to continue. The three options are: z Let the I2C master continue to read data by first acknowledging the data received. This is automatically done when reading DATA.DATA if the smart mode is enabled. z Transmit a new address packet. z Terminate the transaction by issuing a stop condition. An ACK or NACK will be automatically transmitted for the last two alternatives if smart mode is enabled. The Acknowledge Action bit in the Control B register (CTRLB.ACKACT) determines whether ACK or NACK should be sent. Transmitting Data Packets When an address packet with direction set to write has been successfully transmitted, INTFLAG.MB will be set and the I2C master can start transmitting data by writing to DATA.DATA. The I2C master transmits data via the I2C bus while continuously monitoring for packet collisions. If a collision is detected, the I2C master looses arbitration and STATUS.ARBLOST is set. If the transmit was successful, the I2C master automatically receives an ACK bit from the I2C slave and STATUS.RXNACK will be cleared. INTFLAG.MB will be set in both cases, regardless of arbitration outcome. Testing STATUS.ARBLOST and handling the arbitration lost condition in the beginning of the I2C Master on Bus interrupt is recommended. This can be done, as there is no difference between handling address and data packet arbitration. STATUS.RXNACK must be checked for each data packet transmitted before the next data packet transmission can commence. The I2C master is not allowed to continue transmitting data packets if a NACK is given from the I2C slave. Receiving Data Packets (SCLSM=0) When INTFLAG.SB is set, the I2C master will already have received one data packet. The I2C master must respond by sending either an ACK or NACK. Sending a NACK might not be successfully executed as arbitration can be lost during the transmission. In this case, a loss of arbitration will cause INTFLAG.SB to not be set on completion. Instead, INTFLAG.MB will be used to indicate a change in arbitration. Handling of lost arbitration is the same as for data bit transmission. Receiving Data Packets (SCLSM=1) When INTFLAG.SB is set, the I2C master will already have received one data packet and transmitted the ACKACT bit. At this point the ACKACT must be set to the correct value for the next ACK bit, and the transaction can continue by reading DATA and issuing a command if not in smart mode. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 515 High-speed Mode High-speed transfers are a multi-step process as shown in Figure 26-8. First, a master code (0000 1nnn where nnn is a unique master code) is transmitted in Full-speed mode, followed by a NACK since no slave should acknowledge. Arbitration is performed only during the Full-speed Master Code phase. The master code is transmitted by writing the master code to the address register (ADDR) with the high-speed bit (ADDR.HS) written to zero. After the Master Code and NACK have been transmitted, the master write interrupt will be asserted. At this point, the slave address can be written to the ADDR register with the ADDR.HS bit set to one. The master will then generate a repeated start followed by the slave address in High-speed mode. The bus will remain in High-speed mode until a stop is generated. If a repeated start is desired, the ADDR.HS bit must again be written to 1 along with the new address to be transmitted. Figure 26-8. High Speed Transfer F/S-mode S Hs-mode Master Code A Sr R/W A ADDRESS F/S-mode DATA A/A P Hs-mode continues N Data Packets Sr ADDRESS Transmitting in High-speed mode requires the I2C master to be configured in High-speed mode (SPEED=0b10) and the SCL clock stretch mode (SCLSM) bit set to one. 10-Bit Addressing When 10-bit addressing is enabled (TENBITEN=1) and the ADDR register is written, the two address bytes will be transmitted as shown in Figure 26-9. The addressed slave acknowledges the two address bytes and the transaction continues. Regardless of whether the transaction is a read or write, the master must start by sending the 10-bit address with the read/write bit (ADDR.ADDR[0]) equal to zero. If the master receives a NACK after the first byte, then the write interrupt flag will be raised and the NACK bit will be set. If the first byte is acknowledged by one or more slaves, then the master will proceed to transmit the second address byte and the master will first see the write interrupt flag after the second byte is transmitted. If the transaction is a read, the 10-bit address transmission must be followed by a repeated start and the first 7 bits of the address with the read/write bit equal to 1. Figure 26-9. 10-Bit Address Transmission for a Read Transaction MASTER WRITE INTERRUPT 1 S 11110 addr[9:8] W A addr[7:0] A S W Sr 11110 addr[9:8] R A This implies the following procedure for a 10-bit read operation: z Write ADDR.ADDR[10:1] with the 10-bit address. ADDR.TENBITEN must be set (can be written simultaneously with ADDR) and read/write bit (ADDR.ADDR[0]) equal to 0. z When the master write interrupt is asserted, write ADDR[7:0] register to "11110 address[9:8] 1". ADDR.TENBITEN must be cleared (can be written simultaneously with ADDR). z Proceed to transmit data. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 516 26.6.2.7 I2C Slave Operation The I2C slave is byte-oriented and interrupt-based. The number of interrupts generated is kept at a minimum by automatic handling of most events. Auto triggering of operations and a special smart mode, which can be enabled by writing a 1 to the Smart Mode Enable bit in the Control A register (CTRLA.SMEN), are included to reduce software's complexity and code size. The I2C slave has two interrupt strategies. When SCL Stretch Mode (CTRLA.SCLSM) is set to zero, SCL is stretched before or after the acknowledge bit. In this mode, the I2C slave operates according to the behavior diagram shown in Figure 26-10. The circles with a capital S followed by a number (S1, S2... etc.) indicate which node in the figure the bus logic can jump to based on software or hardware interaction. This diagram is used as reference for the description of the I2C slave operation throughout the document. Figure 26-10.I2C Slave Behavioral Diagram (SCLSM=0) SLAVE ADDRESS INTERRUPT S1 S3 S2 S A ADDRESS R S W SLAVE DATA INTERRUPT S1 S2 Sr S3 S W A A P S1 P S2 Sr S3 DATA A/A SLAVE STOP INTERRUPT W Interrupt on STOP Condition Enabled S W S W A DATA S W A/A S W Software interaction The master provides data on the bus Addressed slave provides data on the bus In the second strategy (SCLSM=1), interrupts only occur after the ACK bit as shown in Figure 26-11. This strategy can be used when it is not necessary to check DATA before acknowledging. For master reads, an address and data interrupt will be issued simultaneously after the address acknowledge, while for master writes, the first data interrupt will be seen after the first data byte has been received by the slave and the acknowledge bit has been sent to the master. Note that setting SCLSM to 1 is required for High-speed mode. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 517 Figure 26-11.Slave Behavioral Diagram (SCLSM=1) SLAVE ADDRESS INTERRUPT S1 S3 S2 S ADDRESS R A/A SLAVE DATA INTERRUPT in Master read mode ) SLAVE DATA INTERRUPT S W P S2 Sr S3 DATA P S2 Sr S3 A/A SLAVE STOP INTERRUPT W Interrupt on STOP Condition Enabled S W A/A S W DATA A/A S W S W Software interaction The master provides data on the bus Addressed slave provides data on the bus Receiving Address Packets (SCLSM=0) When SCLSM is zero, the I2C slave stretches the SCL line according to Figure 26-10. When the I2C slave is properly configured, it will wait for a start condition to be detected. When a start condition is detected, the successive address packet will be received and checked by the address match logic. If the received address is not a match, the packet is rejected and the I2C slave waits for a new start condition. The I2C slave Address Match bit in the Interrupt Flag register (INTFLAG.AMATCH) is set when a start condition followed by a valid address packet is detected. SCL will be stretched until the I2C slave clears INTFLAG.AMATCH. Because the I2C slave holds the clock by forcing SCL low, the software is given unlimited time to respond to the address. The direction of a transaction is determined by reading the Read / Write Direction bit in the Status register (STATUS.DIR), and the bit will be updated only when a valid address packet is received. If the Transmit Collision bit in the Status register (STATUS.COLL) is set, this indicates that the last packet addressed to the I2C slave had a packet collision. A collision causes the SDA and SCL lines to be released without any notification to software. The next AMATCH interrupt is, therefore, the first indication of the previous packet's collision. Collisions are intended to follow the SMBus Address Resolution Protocol (ARP). After the address packet has been received from the I2C master, one of two cases will arise based on transfer direction. Case 1: Address packet accepted - Read flag set The STATUS.DIR bit is one, indicating an I2C master read operation. The SCL line is forced low, stretching the bus clock. If an ACK is sent, I2C slave hardware will set the Data Ready bit in the Interrupt Flag register (INTFLAG.DRDY), indicating data are needed for transmit. If not acknowledge is sent, the I2C slave will wait for a new start condition and address match. Typically, software will immediately acknowledge the address packet by sending an ACK/NACK bit. The I2C slave command CTRLB.CMD = 3 can be used for both read and write operation as the command execution is dependent on the STATUS.DIR bit. Writing a one to INTFLAG.AMATCH will also cause an ACK/NACK to be sent corresponding to the CTRLB.ACKACT bit. Case 2: Address packet accepted - Write flag set The STATUS.DIR bit is cleared, indicating an I2C master write operation. The SCL line is forced low, stretching the bus clock. If an ACK is sent, the I2C slave will wait for data to be received. Data, repeated start or stop can be received. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 518 If not acknowledge is sent, the I2C slave will wait for a new start condition and address match. Typically, software will immediately acknowledge the address packet by sending an ACK/NACK bit. The I2C slave command CTRLB.CMD = 3 can be used for both read and write operation as the command execution is dependent on STATUS.DIR. Writing a one to INTFLAG.AMATCH will also cause an ACK/NACK to be sent corresponding to the CTRLB.ACKACT bit. Receiving Address Packets (SCLSM=1) When SCLSM is one, the I2C slave only stretches the SCL line after an acknowledge according to Figure 26-11. When the I2C slave is properly configured, it will wait for a start condition to be detected. When a start condition is detected, the successive address packet will be received and checked by the address match logic. If the received address is not a match, the packet is rejected and the I2C slave waits for a new start condition. If the address matches, the acknowledge action (CTRLB.ACKACT) is automatically sent and the Address Match bit in the Interrupt Flag register (INTFLAG.AMATCH) is set. SCL will be stretched until the I2C slave clears INTFLAG.AMATCH. Because the I2C slave holds the clock by forcing SCL low, the software is given unlimited time to respond to the address. The direction of a transaction is determined by reading the Read / Write Direction bit in the Status register (STATUS.DIR), and the bit will be updated only when a valid address packet is received. If the Transmit Collision bit in the Status register (STATUS.COLL) is set, this indicates that the last packet addressed to the I2C slave had a packet collision. A collision causes the SDA and SCL lines to be released without any notification to software. The next AMATCH interrupt is, therefore, the first indication of the previous packet's collision. Collisions are intended to follow the SMBus Address Resolution Protocol (ARP). After the address packet has been received from the I2C master, a one can be written to INTFLAG.AMATCH to clear it. Receiving and Transmitting Data Packets (SCLSM=0) After the I2C slave has received an address packet, it will respond according to the direction either by waiting for the data packet to be received or by starting to send a data packet by writing to DATA.DATA. When a data packet is received or sent, INTFLAG.DRDY will be set. Then, if the I2C slave was receiving data, it will send an acknowledge according to CTRLB.ACKACT. Case 1: Data received INTFLAG.DRDY is set, and SCL is held low pending SW interaction. Case 2: Data sent When a byte transmission is successfully completed, the INTFLAG.DRDY interrupt flag is set. If NACK is received, the I2C slave must expect a stop or a repeated start to be received. The I2C slave must release the data line to allow the I2C master to generate a stop or repeated start. Upon stop detection, the Stop Received bit in the Interrupt Flag register (INTFLAG.PREC) will be set and the I2C slave will return to the idle state. High Speed Mode When the I2C slave is configured in High-speed mode (CTRLA.SPEED=0x2) with SCLSM set to one, switching between Full-speed and High-speed modes is automatic. When the slave recognizes a START followed by a master code transmission and a NACK, it automatically switches to High-speed mode and sets the High-speed status bit (STATUS.HS). The slave will then remain in High-speed mode until a STOP is received. 10-Bit Addressing When 10-bit addressing is enabled (ADDR.TENBITEN=1) the two address bytes following a START will be checked against the 10-bit slave address recognition. The first byte of the address will always be acknowledged and the second byte will raise the address interrupt flag as shown in Figure 26-12. If the transaction is a write, then the 10-bit address will be followed by N data bytes. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 519 If the operation is a read, the 10-bit address will be followed by a repeated START and reception of "11110 ADDR[9:8] 1" and the second address interrupt will be received with the DIR bit set. The slave matches on the second address as it remembers that is was addressed by the previous 10-bit address. Figure 26-12.10-bit Addressing SLAVE ADDRESS INTERRUPT SLAVE ADDRESS INTERRUPT S 11110 addr[9:8] W A S W addr[7:0] A Sr 11110 addr[9:8] R S W PMBus Group Command When the group command bit is set (CTRLB.GCMD) and 7-bit addressing is used, a STOP interrupt will be generated if the slave has been addressed since the last STOP condition. The group command protocol is used to send commands to more than one device. The commands are sent in one continuous transmission with a single STOP condition at the end. When the STOP condition is detected by the slaves addressed during the group command, they all begin executing the command they received. Figure 26-13 shows an example where this slave is addressed by ADDRESS 1. This slave is addressed after a repeated START condition. There can be multiple slaves addressed before and after, then at the end of the group command, a single STOP is generated by the master. At this point a STOP interrupt is asserted. Figure 26-13.PMBus Group Command Example Command/Data S ADDRESS 0 W n Bytes A A SLAVE DATA INTERRUPT SLAVE ADDRESS INTERRUPT Command/Data Sr ADDRESS 1 (this slave) S W W A S W n Bytes A SLAVE STOP INTERRUPT Command/Data Sr ADDRESS 2 W A n Bytes A P S W 26.6.3 Additional Features 26.6.3.1 SMBus The I2C hardware incorporates three hardware SCL low time-outs which allows a time-out to occur for SMBus SCL low time-out, master extend time-out, and slave extend time-out. These time-outs are driven by the GCLK_SERCOM_SLOW clock. The GCLK_SERCOM_SLOW clock is used to accurately time the time-out and must be configured to used a 32kHz oscillator. The I2C interface also allows for an SMBus compatible SDA hold time. z TTIMEOUT: SCL low time of 25-35 ms. - Measured for a single SCL low period. Enabled by bit CTRLA.LOWTOUTEN. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 520 z TLOW:SEXT:Cumulative clock low extend time of 25 ms - Measured as the cumulative SCL low extend time by a slave device in a single message from the initial START to the STOP. Enabled by bit CTRLA.SEXTTOEN. z TLOW:MEXT: Cumulative clock low extend time of 10 ms. - Measured as the cumulative SCL low extend time by the master device within a single byte from START-to-ACK, ACK-to-ACK, or ACK-to-STOP. Enabled by bit (CTRLA.MEXTTOEN. 26.6.3.2 Smart Mode The I2C interface incorporates a special smart mode that simplifies application code and minimizes the user interaction needed to keep hold of the I2C protocol. The smart mode accomplishes this by letting the reading of DATA.DATA automatically issue an ACK or NACK based on the state of CTRLB.ACKACT. 26.6.3.3 4-Wire Mode Setting the Pin Usage bit in the Control A register (CTRLA.PINOUT) for master or slave to 4-wire mode enables operation as shown in Figure 26-14. In this mode, the internal I2C tri-state drivers are bypassed, and an external, I2Ccompliant tri-state driver is needed when connecting to an I2C bus. Figure 26-14.I2C Pad Interface SCL_OUT/ SDA_OUT SCL_OUT/ SDA_OUT pad PINOUT I2C Driver SCL/SDA pad SCL_IN/ SDA_IN PINOUT 26.6.3.4 Quick Command Setting the Quick Command Enable bit in the Control B register (CTRLB.QCEN) enables quick command. When quick command is enabled, the corresponding interrupt flag is set immediately after the slave acknowledges the address. At this point, the software can either issue a stop command or a repeated start by writing CTRLB.CMD or ADDR.ADDR. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 521 26.6.4 DMA, Interrupts and Events Table 26-1. Module Request for SERCOM I2C Slave Condition Data Ready Interrupt request Event output Event input DMA request DMA request is cleared x Data received (Slave receive mode) x when data is read Data needed for transmit (Slave transmit mode) x when data is written Address Match x Stop received x Error x Table 26-2. Module Request for SERCOM I2C Master Condition Interrupt request Master on Bus x Slave on Bus x Event output Event input DMA request DMA request is cleared Data received (Master receive mode) x when data is read Data needed for transmit (Master transmit mode) x when data is written Error x 26.6.4.1 DMA Operation Smart mode (CTRLB.SMEN) must be enabled for DMA operation. Slave DMA When using the I2C slave with DMA, an address match will cause the address interrupt flag (INTFLAG.ADDRMATCH) to be raised. After the interrupt has been serviced, data transfer will be performed through DMA. The I2C slave generates the following requests: z Write data received (RX): The request is set when master write data is received. The request is cleared when DATA is read. z Read data needed for transmit (TX): The request is set when data is needed for a master read operation. The request is cleared when DATA is written. Master DMA When using the I2C master with DMA, the ADDR register must be written with the desired address (ADDR.ADDR), transaction length (ADDR.LEN), and transaction length enable (ADDR.LENEN). When ADDR.LENEN is written to 1 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 522 along with ADDR.ADDR, ADDR.LEN determines the number of data bytes in the transaction from 0 to 255. DMA is then used to transfer ADDR.LEN bytes followed by an automatically generated NACK (for master reads) and a STOP. If a NACK is received by the slave for a master write transaction before ADDR.LEN bytes, a STOP will be automatically generated and the length error (STATUS.LENERR) will be raised along with the INTFLAG.ERROR interrupt. The I2C master generates the following requests: z Read data received (RX): The request is set when master read data is received. The request is cleared when DATA is read. z Write data needed for transmit (TX): The request is set when data is needed for a master write operation. The request is cleared when DATA is written. 26.6.4.2 Interrupts The I2C slave has the following interrupt sources: z Error (ERROR): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. z Data Ready (DRDY): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. z Address Match (AMATCH): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. z Stop Received (PREC): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. The I2C master has the following interrupt sources: z Error (ERROR): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. z Slave on Bus (SB): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. z Master on Bus (MB): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the I2C is reset. See INTFLAG for details on how to clear interrupt flags. The I2C has one common interrupt request line for all the interrupt sources. The user must read INTFLAG to determine which interrupt condition is present. Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to "Nested Vector Interrupt Controller" on page 29 for details. 26.6.4.3 Events Not applicable. 26.6.5 Sleep Mode Operation During I2C master operation, the generic clock (GCLK_SERCOMx_CORE) will continue to run in idle sleep mode. If the Run In Standby bit in the Control A register (CTRLA.RUNSTDBY) is one, the GLK_SERCOMx_CORE will also run in standby sleep mode. Any interrupt can wake up the device. If CTRLA.RUNSTDBY is zero during I2C master operation, the GLK_SERCOMx_CORE will be disabled when an ongoing transaction is finished. Any interrupt can wake up the device. During I2C slave operation, writing a one to CTRLA.RUNSTDBY will allow the Address Match interrupt to wake up the device. In I2C slave operation, all receptions will be dropped when CTRLA.RUNSTDBY is zero. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 523 26.6.6 Synchronization Due to the asynchronicity between CLK_SERCOMx_APB and GCLK_SERCOMx_CORE, some registers must be synchronized when accessed. A register can require: z Synchronization when written z Synchronization when read z Synchronization when written and read z No synchronization When executing an operation that requires synchronization, the corresponding Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY) will be set immediately, and cleared when synchronization is complete. If an operation that requires synchronization is executed while the corresponding SYNCBUSY bit is one, a peripheral bus error is generated. The following bits need synchronization when written: z Software Reset bit in the Control A register (CTRLA.SWRST). SYNCBUSY.SWRST is set to one while synchronization is in progress. z Enable bit in the Control A register (CTRLA.ENABLE). SYNCBUSY.ENABLE is set to one while synchronization is in progress. z Write to Bus State bits in the Status register (STATUS.BUSSTATE). SYNCBUSY.SYSOP is set to one while synchronization is in progress. z Address bits in the Address register (ADDR.ADDR) when in master operation. SYNCBUSY.SYSOP is set to one while synchronization is in progress. z Data (DATA) when in master operation. SYNCBUSY.SYSOP is set to one while synchronization is in progress. Write-synchronization is denoted by the Write-Synchronized property in the register description. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 524 26.7 Register Summary Table 26-3. Register Summary - Slave Mode Offset Name Bit Pos. 0x00 7:0 0x01 15:8 RUNSTDBY MODE[2:0]=100 ENABLE SWRST CTRLA 0x02 23:16 0x03 31:24 0x04 7:0 0x05 15:8 SEXTTOEN SDAHOLD[1:0] LOWTOUT PINOUT SCLSM AMODE[1:0] SPEED[1:0] AACKEN GCMD SMEN CTRLB 0x06 23:16 0x07 31:24 0x08 Reserved ... Reserved 0x13 Reserved 0x14 INTENCLR 0x15 Reserved 0x16 INTENSET 0x17 Reserved 0x18 INTFLAG 0x19 Reserved 0x1A ACKACT CMD[1:0] 7:0 ERROR DRDY AMATCH PREC 7:0 ERROR DRDY AMATCH PREC 7:0 ERROR DRDY AMATCH PREC 7:0 CLKHOLD RXNACK COLL BUSERR 15:8 SYNCBUSY HS SEXTTOUT LOWTOUT SR DIR STATUS 0x1B Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 525 Table 26-3. Register Summary - Slave Mode (Continued) Offset Name Bit Pos. 0x1C 7:0 0x1D 15:8 ENABLE SWRST SYNCBUSY 0x1E 23:16 0x1F 31:24 0x20 Reserved 0x21 Reserved 0x22 Reserved 0x23 Reserved 0x24 7:0 0x25 15:8 ADDR[6:0] TENBITEN GENCEN ADDR[9:7] ADDR 0x26 23:16 0x27 31:24 0x28 7:0 ADDRMASK[6:0] ADDRMASK[9:7] DATA[7:0] DATA 0x29 15:8 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 526 Table 26-4. Register Summary - Master Mode Offset Name Bit Pos 0x00 7:0 0x01 15:8 RUNSTDBY MODE[2:0]=101 ENABLE SWRST CTRLA 0x02 23:16 0x03 31:24 0x04 7:0 0x05 SEXTTOEN MEXTTOEN SDAHOLD[1:0] LOWTOUT INACTOUT[1:0] PINOUT SCLSM SPEED[1:0] 15:8 QCEN SMEN CTRLB 0x06 23:16 0x07 31:24 0x08 Reserved 0x09 Reserved 0x0A Reserved 0x0B Reserved ACKACT 0x0C 7:0 BAUD[7:0] 0x0D 15:8 BAUDLOW[7:0] 0x0E 23:16 HSBAUD[7:0] 0x0F 31:24 HSBAUDLOW[7:0] CMD[1:0] BAUD 0x10 Reserved 0x11 Reserved 0x12 Reserved 0x13 Reserved 0x14 INTENCLR 7:0 ERROR SB Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 MB 527 Table 26-4. Register Summary - Master Mode (Continued) Offset Name 0x15 Reserved 0x16 INTENSET 0x17 Reserved 0x18 INTFLAG 0x19 Reserved 0x1A Bit Pos 7:0 ERROR SB MB 7:0 ERROR SB MB 7:0 CLKHOLD RXNACK ARBLOST BUSERR LOWTOUT BUSSTATE[1:0] STATUS 0x1B 15:8 LENERR SEXTTOUT MEXTTOUT 0x1C 7:0 SYSOP ENABLE SWRST 0x1D 15:8 SYNCBUS Y 0x1E 23:16 0x1F 31:24 0x20 Reserved 0x21 Reserved 0x22 Reserved 0x23 Reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 528 Table 26-4. Register Summary - Master Mode (Continued) Offset Name Bit Pos 0x24 7:0 0x25 15:8 ADDR[7:0] TENBITEN HS LENEN ADDR[10:8] ADDR 0x26 23:16 0x27 31:24 0x28 7:0 LEN[7:0] DATA[7:0] DATA 0x29 15:8 0x2A Reserved ... Reserved 0x2F Reserved 0x30 DBGCTRL 7:0 DBGSTOP Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 529 26.8 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protected property in each individual register description. Please refer to"Register Access Protection" on page 507 for details. Some registers require synchronization when read and/or written. Synchronization is denoted by the Write-Synchronized or the Read-Synchronized property in each individual register description. Please refer to "Synchronization" on page 524 for details. Some registers are enable-protected, meaning they can only be written when the I2C is disabled. Enable-protection is denoted by the Enable-Protected property in each individual register description. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 530 26.8.1 I2C Slave Register Description 26.8.1.1 Control A Name: CTRLA Offset: 0x00 Reset: 0x00000000 Property: Write-Protected, Enable-Protected, Write-Synchronized Bit 31 30 29 28 LOWTOUT 27 26 25 SCLSM 24 SPEED[1:0] Access R R/W R R R/W R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 SDAHOLD[1:0] SEXTTOEN Access PINOUT R/W R R/W R/W R R R R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ENABLE SWRST MODE[2:0]=100 RUNSTDBY Access Reset R/W R R R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bit 31 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 30 - LOWTOUT: SCL Low Time-Out This bit enables the SCL low time-out. If SCL is held low for 25ms-35ms, the slave will release its clock hold, if enabled, and reset the internal state machine. Any interrupts set at the time of time-out will remain set. 0: Time-out disabled. 1: Time-out enabled. z Bits 29:28 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 27- SCLSM: SCL Clock Stretch Mode This bit controls when SCL will be stretch for software interaction. 0: SCL stretch according to Figure 26-7 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 531 1: SCL stretch only after ACK bit according to Figure 26-10. This bit is not synchronized. z Bit 26- Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 25:24 - SPEED[1:0]: Transfer Speed These bits define bus speed. Table 26-5. Transfer Speed Value Description 0x0 Standard-mode (Sm) up to 100 kHz and Fast-mode (Fm) up to 400 kHz 0x1 Fast-mode Plus (Fm+) up to 1 MHz 0x2 High-speed mode (Hs-mode) up to 3.4 MHz 0x3 Reserved These bits are not synchronized. z Bit 23 - SEXTTOEN: Slave SCL Low Extend Time-Out This bit enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine. Any interrupts set at the time of time-out will remain set. If the address was recognized, PREC will be set when a STOP is received. 0: Time-out disabled 1: Time-out enabled This bit is not synchronized. z Bit 22 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 21:20 - SDAHOLD[1:0]: SDA Hold Time These bits define the SDA hold time with respect to the negative edge of SCL. Table 26-6. SDA Hold Time Value Name Description 0x0 DIS Disabled 0x1 75 50-100ns hold time 0x2 450 300-600ns hold time 0x3 600 400-800ns hold time These bits are not synchronized. z Bits 19:17 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 532 z Bit 16 - PINOUT: Pin Usage This bit sets the pin usage to either two- or four-wire operation: 0: 4-wire operation disabled 1: 4-wire operation enabled This bit is not synchronized. z Bits 15:8 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 7 - RUNSTDBY: Run in Standby This bit defines the functionality in standby sleep mode. 0: Disabled - All reception is dropped. 1: Wake on address match, if enabled. This bit is not synchronized. z Bits 6:5 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 4:2 - MODE[2:0]: Operating Mode These bits must be written to 0x04 to select the I2C slave serial communication interface of the SERCOM. These bits are not synchronized. z Bit 1 - ENABLE: Enable 0: The peripheral is disabled. 1: The peripheral is enabled. Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately and the Enable Synchronization Busy bit in the Synchronization busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. This bit is not enable-protected. z Bit 0 - SWRST: Software Reset 0: There is no reset operation ongoing. 1: The reset operation is ongoing. Writing a zero to this bit has no effect. Writing a one to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled. Writing a one to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register will return the reset value of the register. Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete. This bit is not enable-protected. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 533 26.8.1.2 Control B Name: CTRLB Offset: 0x04 Reset: 0x00000000 Property: Write-Protected, Enable-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 ACKACT CMD[1:0] Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 AACKEN GCMD SMEN AMODE[1:0] Access R/W R/W R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 31:19 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 18 - ACKACT: Acknowledge Action 0: Send ACK 1: Send NACK The Acknowledge Action (ACKACT) bit defines the slave's acknowledge behavior after an address or data byte is received from the master. The acknowledge action is executed when a command is written to the CMD bits. If smart mode is enabled (CTRLB.SMEN is one), the acknowledge action is performed when the DATA register is read. This bit is not enable-protected. z Bits 17:16 - CMD[1:0]: Command Writing the Command bits (CMD) triggers the slave operation as defined in Table 26-7. The CMD bits are strobe bits, and always read as zero. The operation is dependent on the slave interrupt flags, INTFLAG.DRDY and INTFLAG.AMATCH, in addition to STATUS.DIR (See Table 26-7). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 534 All interrupt flags (INTFLAG.DRDY, INTFLAG.AMATCH and INTFLAG.PREC) are automatically cleared when a command is given. This bit is not enable-protected. Table 26-7. Command Description CMD[1:0] DIR Action 0x0 X (No action) 0x1 X (Reserved) Used to complete a transaction in response to a data interrupt (DRDY) 0x2 0 (Master write) Execute acknowledge action succeeded by waiting for any start (S/Sr) condition 1 (Master read) Wait for any start (S/Sr) condition Used in response to an address interrupt (AMATCH) 0x3 0 (Master write) Execute acknowledge action succeeded by reception of next byte 1 (Master read) Execute acknowledge action succeeded by slave data interrupt Used in response to a data interrupt (DRDY) z 0 (Master write) Execute acknowledge action succeeded by reception of next byte 1 (Master read) Execute a byte read operation followed by ACK/NACK reception Bits 15:14 - AMODE[1:0]: Address Mode These bits set the addressing mode according to Table 26-8. Table 26-8. Address Mode Description Value Name Description 0x0 MASK The slave responds to the address written in ADDR.ADDR masked by the value in ADDR.ADDRMASK(1). 0x1 2_ADDRS The slave responds to the two unique addresses in ADDR.ADDR and ADDR.ADDRMASK. 0x2 RANGE The slave responds to the range of addresses between and including ADDR.ADDR and ADDR.ADDRMASK. ADDR.ADDR is the upper limit. 0x3 - Reserved. Note: 1. See "SERCOM - Serial Communication Interface" on page 426 for additional information. These bits are not write-synchronized. z Bits 13:11 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 10- AACKEN: Automatic Acknowledge Enable This bit enables the address to be automatically acknowledged if there is an address match. 0: Automatic acknowledge is disabled. 1: Automatic acknowledge is enabled. This bit is not write-synchronized. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 535 z Bit 9 - GCMD: PMBus Group Command This bit enables PMBus group command support. When enabled, a STOP interrupt will be generated if the slave has been addressed since the last STOP condition on the bus. 0: Group command is disabled. 1: Group command is enabled. This bit is not write-synchronized. z Bit 8 - SMEN: Smart Mode Enable This bit enables smart mode. When smart mode is enabled, acknowledge action is sent when DATA.DATA is read. 0: Smart mode is disabled. 1: Smart mode is enabled. This bit is not write-synchronized. z Bits 7:0 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 536 26.8.1.3 Interrupt Enable Clear This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Name: INTENCLR Offset: 0x14 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 ERROR Access Reset z 2 1 0 DRDY AMATCH PREC R/W R R R R R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7- ERROR: Error Interrupt Enable 0: Error interrupt is disabled. 1: Error interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt. z Bits 6:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 2 - DRDY: Data Ready Interrupt Enable 0: The Data Ready interrupt is disabled. 1: The Data Ready interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Data Ready bit, which disables the Data Ready interrupt. z Bit 1 - AMATCH: Address Match Interrupt Enable 0: The Address Match interrupt is disabled. 1: The Address Match interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Address Match Interrupt Enable bit, which disables the Address Match interrupt. z Bit 0 - PREC: Stop Received Interrupt Enable 0: The Stop Received interrupt is disabled. 1: The Stop Received interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Stop Received bit, which disables the Stop Received interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 537 26.8.1.4 Interrupt Enable Set This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Name: INTENSET Offset: 0x16 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 ERROR Access Reset z 2 1 0 DRDY AMATCH PREC R/W R R R R R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 - ERROR: Error Interrupt Enable 0: Error interrupt is disabled. 1: Error interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt. z Bits 6:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 2 - DRDY: Data Ready Interrupt Enable 0: The Data Ready interrupt is disabled. 1: The Data Ready interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Data Ready bit, which enables the Data Ready interrupt. z Bit 1 - AMATCH: Address Match Interrupt Enable 0: The Address Match interrupt is disabled. 1: The Address Match interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Address Match Interrupt Enable bit, which enables the Address Match interrupt. z Bit 0 - PREC: Stop Received Interrupt Enable 0: The Stop Received interrupt is disabled. 1: The Stop Received interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Stop Received bit, which enables the Stop Received interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 538 26.8.1.5 Interrupt Flag Status and Clear Name: INTFLAG Offset: 0x18 Reset: 0x00 Property: - Bit 7 6 5 4 3 ERROR Access Reset z 2 1 0 DRDY AMATCH PREC R/W R R R R R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7- ERROR: Error This flag is cleared by writing a one to it. This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STATUS register. Errors that will set this flag are SEXTTOUT, LOWTOUT, COLL, and BUSERR.Writing a zero to this bit has no effect. Writing a one to this bit will clear the flag. z Bits 6:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 2 - DRDY: Data Ready This flag is set when a I2C slave byte transmission is successfully completed. The flag is cleared by hardware when either: z Writing to the DATA register. z Reading the DATA register with smart mode enabled. z Writing a valid command to the CMD register. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Data Ready interrupt flag. Optionally, the flag can be cleared manually by writing a one to INTFLAG.DRDY. z Bit 1 - AMATCH: Address Match This flag is set when the I2C slave address match logic detects that a valid address has been received. The flag is cleared by hardware when CTRL.CMD is written. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Address Match interrupt flag. Optionally the flag can be cleared manually by writing a one to INTFLAG.AMATCH. When cleared, an ACK/NACK will be sent according to CTRLB.ACKACT. z Bit 0 - PREC: Stop Received This flag is set when a stop condition is detected for a transaction being processed. A stop condition detected between a bus master and another slave will not set this flag. This flag is cleared by hardware after a command is issued on the next address match. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Stop Received interrupt flag. Optionally, the flag can be cleared manually by writing a one to INTFLAG.PREC. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 539 26.8.1.6 Status Name: STATUS Offset: 0x1A Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 9 HS SEXTTOUT 8 Access R R R R R R/W R/W R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CLKHOLD LOWTOUT SR DIR RXNACK COLL BUSERR Access R R/W R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 15:11 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 10 - HS: High-speed This bit is set if the slave detects a START followed by a Master Code transmission. Writing a zero to this bit has no effect. Writing a one to this bit will clear the status. However, this flag is automatically cleared when a STOP is received. z Bit 9 - SEXTTOUT: Slave SCL Low Extend Time-Out This bit is set if a slave SCL low extend time-out occurs. This bit is cleared automatically if responding to a new start condition with ACK or NACK (write 3 to CTRLB.CMD) or when INTFLAG.AMATCH is cleared. 0: No SCL low extend time-out has occurred. 1: SCL low extend time-out has occurred. Writing a zero to this bit has no effect. Writing a one to this bit will clear the status. z Bit 8 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 7 - CLKHOLD: Clock Hold The slave Clock Hold bit (STATUS.CLKHOLD) is set when the slave is holding the SCL line low, stretching the I2C clock. Software should consider this bit a read-only status flag that is set when INTFLAG.DRDY or INTFLAG.AMATCH is set. This bit is automatically cleared when the corresponding interrupt is also cleared. z Bit 6 - LOWTOUT: SCL Low Time-out This bit is set if an SCL low time-out occurs. This bit is cleared automatically if responding to a new start condition with ACK or NACK (write 3 to CTRLB.CMD) or when INTFLAG.AMATCH is cleared. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 540 0: No SCL low time-out has occurred. 1: SCL low time-out has occurred. Writing a zero to this bit has no effect. Writing a one to this bit will clear the status. z Bit 5 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 4 - SR: Repeated Start When INTFLAG.AMATCH is raised due to an address match, SR indicates a repeated start or start condition. 0: Start condition on last address match 1: Repeated start condition on last address match This flag is only valid while the INTFLAG.AMATCH flag is one. z Bit 3 - DIR: Read / Write Direction The Read/Write Direction (STATUS.DIR) bit stores the direction of the last address packet received from a master. 0: Master write operation is in progress. 1: Master read operation is in progress. z Bit 2 - RXNACK: Received Not Acknowledge This bit indicates whether the last data packet sent was acknowledged or not. 0: Master responded with ACK. 1: Master responded with NACK. z Bit 1 - COLL: Transmit Collision If set, the I2C slave was not able to transmit a high data or NACK bit, the I2C slave will immediately release the SDA and SCL lines and wait for the next packet addressed to it. This flag is intended for the SMBus address resolution protocol (ARP). A detected collision in non-ARP situations indicates that there has been a protocol violation, and should be treated as a bus error. Note that this status will not trigger any interrupt, and should be checked by software to verify that the data were sent correctly. This bit is cleared automatically if responding to an address match with an ACK or a NACK (writing 0x3 to CTRLB.CMD), or INTFLAG.AMATCH is cleared. 0: No collision detected on last data byte sent. 1: Collision detected on last data byte sent. Writing a zero to this bit has no effect. Writing a one to this bit will clear the status. z Bit 0 - BUSERR: Bus Error The Bus Error bit (STATUS.BUSERR) indicates that an illegal bus condition has occurred on the bus, regardless of bus ownership. An illegal bus condition is detected if a protocol violating start, repeated start or stop is detected on the I2C bus lines. A start condition directly followed by a stop condition is one example of a protocol violation. If a time-out occurs during a frame, this is also considered a protocol violation, and will set STATUS.BUSERR. This bit is cleared automatically if responding to an address match with an ACK or a NACK (writing 0x3 to CTRLB.CMD) or INTFLAG.AMATCH is cleared. 0: No bus error detected. 1: Bus error detected. Writing a one to this bit will clear the status. Writing a zero to this bit has no effect. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 541 26.8.1.7 Synchronization Busy Name: SYNCBUSY Offset: 0x1C Reset: 0x00000000 Property: Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ENABLE SWRST Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 31:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 1 - ENABLE: SERCOM Enable Synchronization Busy Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the SYNCBUSY.ENABLE bit will be set until synchronization is complete. Writes to any register (except for CTRLA.SWRST) while enable synchronization is on-going will be discarded and an APB error will be generated. 0: Enable synchronization is not busy. 1: Enable synchronization is busy. z Bit 0 - SWRST: Software Reset Synchronization Busy Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the SYNCBUSY.SWRST bit will be set until synchronization is complete. Writes to any register while synchronization is on-going will be discarded and an APB error will be generated. 0: SWRST synchronization is not busy. 1: SWRST synchronization is busy. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 542 26.8.1.8 Address Name: ADDR Offset: 0x24 Reset: 0x00000000 Property: Write-Protected, Enable-Protected Bit 31 30 29 28 27 26 25 24 ADDRMASK[9:7] Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 ADDRMASK[6:0] Access R/W R/W R/W R/W R/W R/W R/W R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 ADDR[9:7] TENBITEN Access R/W R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADDR[6:0] Access Reset GENCEN R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 31:27 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 26:17 - ADDRMASK[9:0]: Address Mask The ADDRMASK bits acts as a second address match register, an address mask register or the lower limit of an address range, depending on the CTRLB.AMODE setting. z Bit 16- Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 15- TENBITEN: Ten Bit Addressing Enable Writing a one to TENBITEN enables 10-bit address recognition. 0: 10-bit address recognition disabled. 1: 10-bit address recognition enabled. z Bits 14:11 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 543 z Bits 10:1 - ADDR[9:0]: Address The slave address (ADDR) bits contain the I2C slave address used by the slave address match logic to determine if a master has addressed the slave. When using 7-bit addressing, the slave address is represented by ADDR.ADDR[6:0]. When using 10-bit addressing (ADDR.TENBITEN=1), the slave address is represented by ADDR.ADDR[9:0] When the address match logic detects a match, INTFLAG.AMATCH is set and STATUS.DIR is updated to indicate whether it is a read or a write transaction. z Bit 0 - GENCEN: General Call Address Enable Writing a one to GENCEN enables general call address recognition. A general call address is an address of all zeroes with the direction bit written to zero (master write). 0: General call address recognition disabled. 1: General call address recognition enabled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 544 26.8.1.9 Data Name: DATA Offset: 0x28 Reset: 0x0000 Property: Write-Synchronized, Read-Synchronized Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 15:8 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 7:0 - DATA[7:0]: Data The slave data register I/O location (DATA.DATA) provides access to the master transmit and receive data buffers. Reading valid data or writing data to be transmitted can be successfully done only when SCL is held low by the slave (STATUS.CLKHOLD is set). An exception occurs when reading the last data byte after the stop condition has been received. Accessing DATA.DATA auto-triggers I2C bus operations. The operation performed depends on the state of CTRLB.ACKACT, CTRLB.SMEN and the type of access (read/write). Writing or reading DATA.DATA when not in smart mode does not require synchronization. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 545 26.8.2 I2C Master Register Description 26.8.2.1 Control A Name: CTRLA Offset: 0x00 Reset: 0x00000000 Property: Write-Protected, Enable-Protected, Write-Synchronized Bit 31 30 29 LOWTOUT 28 INACTOUT[1:0] 27 26 25 SCLSM 24 SPEED[1:0] Access R R/W R/W R/W R/W R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 SEXTTOEN MEXTTOEN R/W R/W R/W R/W R R R R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ENABLE SWRST Access PINOUT SDAHOLD[1:0] MODE[2:0]=101 RUNSTDBY Access Reset R/W R R R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bit 31 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 30 - LOWTOUT: SCL Low Time-Out This bit enables the SCL low time-out. If SCL is held low for 25ms-35ms, the master will release its clock hold, if enabled, and complete the current transaction. A stop condition will automatically be transmitted. INTFLAG.SB or INTFLAG.MB will be set as normal, but the clock hold will be released. The STATUS.LOWTOUT and STATUS.BUSERR status bits will be set. 0: Time-out disabled. 1: Time-out enabled. This bit is not synchronized. z Bits 29:28 - INACTOUT[1:0]: Inactive Time-Out If the inactive bus time-out is enabled and the bus is inactive for longer than the time-out setting, the bus state logic will be set to idle. An inactive bus arise when either an I2C master or slave is holding the SCL low. The available time-outs are given in Table 26-9. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 546 Enabling this option is necessary for SMBus compatibility, but can also be used in a non-SMBus set-up. Table 26-9. Inactive Timout Value Name Description 0x0 DIS Disabled 0x1 55US 5-6 SCL cycle time-out (50-60s) 0x2 105US 10-11 SCL cycle time-out (100-110s) 0x3 205US 20-21 SCL cycle time-out (200-210s) Calculated time-out periods are based on a 100kHz baud rate. These bits are not synchronized. z Bit 27- SCLSM: SCL Clock Stretch Mode This bit controls when SCL will be stretch for software interaction. 0: SCL stretch according to Figure 26-7. 1: SCL stretch only after ACK bit. This bit is not synchronized. z Bit 26- Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 25:24 - SPEED[1:0]: Transfer Speed These bits define bus speed. Table 26-10. Transfer Speed Value Description 0x0 Standard-mode (Sm) up to 100 kHz and Fast-mode (Fm) up to 400 kHz 0x1 Fast-mode Plus (Fm+) up to 1 MHz 0x2 High-speed mode (Hs-mode) up to 3.4 MHz 0x3 Reserved These bits are not synchronized. z Bit 23 - SEXTTOEN: Slave SCL Low Extend Time-Out This bit enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine. Any interrupts set at the time of time-out will remain set. If the address was recognized, PREC will be set when a STOP is received. 0: Time-out disabled 1: Time-out enabled This bit is not synchronized. z Bit 22 - MEXTTOEN: Master SCL Low Extend Time-Out This bit enables the master SCL low extend time-out. If SCL is cumulatively held low for greater than 10ms from START-to-ACK, ACK-to-ACK, or ACK-to-STOP the master will release its clock hold if enabled, and complete the current transaction. A STOP will automatically be transmitted. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 547 SB or MB will be set as normal, but CLKHOLD will be release. The MEXTTOUT and BUSERR status bits will be set. 0: Time-out disabled 1: Time-out enabled This bit is not synchronized. z Bits 21:20 - SDAHOLD[1:0]: SDA Hold Time These bits define the SDA hold time with respect to the negative edge of SCL. Table 26-11. SDA Hold Time Value Name Description 0x0 DIS Disabled 0x1 75NS 50-100ns hold time 0x2 450NS 300-600ns hold time 0x3 600NS 400-800ns hold time These bits are not synchronized. z Bits 19:17 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 16 - PINOUT: Pin Usage This bit set the pin usage to either two- or four-wire operation: 0: 4-wire operation disabled. 1: 4-wire operation enabled. This bit is not synchronized. z Bits 15:8 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 7 - RUNSTDBY: Run in Standby This bit defines the functionality in standby sleep mode. 0: GCLK_SERCOMx_CORE is disabled and the I2C master will not operate in standby sleep mode. 1: GCLK_SERCOMx_CORE is enabled in all sleep modes allowing the master to operate in standby sleep mode. This bit is not synchronized. z Bits 6:5 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 4:2 - MODE[2:0]: Operating Mode These bits must be written to 0x5 to select the I2C master serial communication interface of the SERCOM. These bits are not synchronized. z Bit 1 - ENABLE: Enable 0: The peripheral is disabled. 1: The peripheral is enabled. Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately and the Synchronization Enable Busy bit in the Sync- Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 548 busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. This bit is not enable-protected. z Bit 0 - SWRST: Software Reset 0: There is no reset operation ongoing. 1: The reset operation is ongoing. Writing a zero to this bit has no effect. Writing a one to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled. Writing a one to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register will return the reset value of the register. Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete. This bit is not enable-protected. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 549 26.8.2.2 Control B Name: CTRLB Offset: 0x04 Reset: 0x00000000 Property: Write-Protected, Enable-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 ACKACT CMD[1:0] Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 QCEN SMEN Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 31:19 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 18 - ACKACT: Acknowledge Action The Acknowledge Action (ACKACT) bit defines the I2C master's acknowledge behavior after a data byte is received from the I2C slave. The acknowledge action is executed when a command is written to CTRLB.CMD, or if smart mode is enabled (CTRLB.SMEN is written to one), when DATA.DATA is read. 0: Send ACK. 1: Send NACK. This bit is not enable-protected. This bit is not write-synchronized. z Bits 17:16 - CMD[1:0]: Command Writing the Command bits (CMD) triggers the master operation as defined in Table 26-12. The CMD bits are strobe bits, and always read as zero. The acknowledge action is only valid in master read mode. In master write mode, a command will only result in a repeated start or stop condition. The CTRLB.ACKACT bit and the CMD bits Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 550 can be written at the same time, and then the acknowledge action will be updated before the command is triggered. Commands can only be issued when the Slave on Bus interrupt flag (INTFLAG.SB) or Master on Bus interrupt flag (INTFLAG.MB) is one. If CMD 0x1 is issued, a repeated start will be issued followed by the transmission of the current address in ADDR.ADDR. If another address is desired, ADDR.ADDR must be written instead of the CMD bits. This will trigger a repeated start followed by transmission of the new address. Issuing a command will set STATUS.SYNCBUSY. Table 26-12. Command Description CMD[1:0] Direction Action 0x0 X (No action) 0x1 X Execute acknowledge action succeeded by repeated Start 0 (Write) No operation 1 (Read) Execute acknowledge action succeeded by a byte read operation X Execute acknowledge action succeeded by issuing a stop condition 0x2 0x3 These bits are not enable-protected. z Bits 15:10 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 9 - QCEN: Quick Command Enable Setting the Quick Command Enable bit (QCEN) enables quick command. 0: Quick Command is disabled. 1: Quick Command is enabled. This bit is not write-synchronized. z Bit 8 - SMEN: Smart Mode Enable This bit enables smart mode. When smart mode is enabled, acknowledge action is sent when DATA.DATA is read. 0: Smart mode is disabled. 1: Smart mode is enabled. This bit is not write-synchronized. z Bits 7:0 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 551 26.8.2.3 Baud Rate Name: BAUD Offset: 0x0C Reset: 0x0000 Property: Write-Protected, Enable-Protected Bit 31 30 29 28 27 26 25 24 HSBAUDLOW[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 HSBAUD[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 BAUDLOW[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BAUD[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 31:24 - HSBAUDLOW[7:0]: High Speed Master Baud Rate Low HSBAUDLOW not equal to 0 HSBAUDLOW indicates the SCL low time according to the following formula. HSBAUDLOW = f GCLK T LOW -1 HSBAUDLOW equal to 0 The HSBAUD register is used to time TLOW, THIGH, TSU;STO, THD;STA and TSU;STA.. TBUF is timed by the BAUD register. z Bits 23:16 - HSBAUD[7:0]: High Speed Master Baud Rate The HSBAUD register indicates the SCL high time according to the following formula. When HSBAUDLOW is zero, TLOW, THIGH, TSU;STO, THD;STA and TSU;STA are derived using this formula. TBUF is timed by the BAUD register. BAUD = z f GCLK T HIGH -1 Bits 15:8 - BAUDLOW[7:0]: Master Baud Rate Low If the Master Baud Rate Low bit group (BAUDLOW) has a non-zero value, the SCL low time will be described by the value written. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 552 For more information on how to calculate the frequency, see "SERCOM I2C - SERCOM Inter-Integrated Circuit" on page 505. z Bits 7:0 - BAUD[7:0]: Master Baud Rate The Master Baud Rate bit group (BAUD) is used to derive the SCL high time if BAUD.BAUDLOW is non-zero. If BAUD.BAUDLOW is zero, BAUD will be used to generate both high and low periods of the SCL. For more information on how to calculate the frequency, see "SERCOM I2C - SERCOM Inter-Integrated Circuit" on page 505. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 553 26.8.2.4 Interrupt Enable Clear This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Name: INTENCLR Offset: 0x14 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 ERROR Access Reset z 1 0 SB MB R/W R R R R R R/W R/W 0 0 0 0 0 0 0 0 Bit 7- ERROR: Error Interrupt Enable 0: Error interrupt is disabled. 1: Error interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt. z Bits 6:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 1 - SB: Slave on Bus Interrupt Enable 0: The Slave on Bus interrupt is disabled. 1: The Slave on Bus interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Slave on Bus Interrupt Enable bit, which disables the Slave on Bus interrupt. z Bit 0 - MB: Master on Bus Interrupt Enable 0: The Master on Bus interrupt is disabled. 1: The Master on Bus interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Master on Bus Interrupt Enable bit, which disables the Master on Bus interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 554 26.8.2.5 Interrupt Enable Set This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Name: INTENSET Offset: 0x16 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 ERROR Access Reset z 1 0 SB MB R/W R R R R R R/W R/W 0 0 0 0 0 0 0 0 Bit 7 - ERROR: Error Interrupt Enable 0: Error interrupt is disabled. 1: Error interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt. z Bits 6:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 1 - SB: Slave on Bus Interrupt Enable 0: The Slave on Bus interrupt is disabled. 1: The Slave on Bus interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Slave on Bus Interrupt Enable bit, which enables the Slave on Bus interrupt. z Bit 0 - MB: Master on Bus Interrupt Enable 0: The Master on Bus interrupt is disabled. 1: The Master on Bus interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Master on Bus Interrupt Enable bit, which enables the Master on Bus interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 555 26.8.2.6 Interrupt Flag Status and Clear Name: INTFLAG Offset: 0x18 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 ERROR Access Reset z 1 0 SB MB R/W R R R R R R/W R/W 0 0 0 0 0 0 0 0 Bit 7- ERROR: Error This flag is cleared by writing a one to it. This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STATUS register. Errors that will set this flag are LENERR, SEXTTOUT, MEXTTOUT, LOWTOUT, ARBLOST, and BUSERR. Writing a zero to this bit has no effect. Writing a one to this bit will clear the flag. z Bits 6:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 1 - SB: Slave on Bus The Slave on Bus flag (SB) is set when a byte is successfully received in master read mode, i.e., no arbitration lost or bus error occurred during the operation. When this flag is set, the master forces the SCL line low, stretching the I2C clock period. The SCL line will be released and SB will be cleared on one of the following actions: z Writing to ADDR.ADDR z Writing to DATA.DATA z Reading DATA.DATA when smart mode is enabled (CTRLB.SMEN) z Writing a valid command to CTRLB.CMD Writing a one to this bit location will clear the SB flag. The transaction will not continue or be terminated until one of the above actions is performed. Writing a zero to this bit has no effect. z Bit 0 - MB: Master on Bus The Master on Bus flag (MB) is set when a byte is transmitted in master write mode. The flag is set regardless of the occurrence of a bus error or an arbitration lost condition. MB is also set when arbitration is lost during sending of NACK in master read mode, and when issuing a start condition if the bus state is unknown. When this flag is set and arbitration is not lost, the master forces the SCL line low, stretching the I2C clock period. The SCL line will be released and MB will be cleared on one of the following actions: z Writing to ADDR.ADDR z Writing to DATA.DATA z Reading DATA.DATA when smart mode is enabled (CTRLB.SMEN) z Writing a valid command to CTRLB.CMD If arbitration is lost, writing a one to this bit location will clear the MB flag. If arbitration is not lost, writing a one to this bit location will clear the MB flag. The transaction will not continue or be terminated until one of the above actions is performed. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 556 Writing a zero to this bit has no effect. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 557 26.8.2.7 Status Name: STATUS Offset: 0x1A Reset: 0x0000 Property: Write-Synchronized Bit 15 14 13 12 11 10 9 8 LENERR SEXTTOUT MEXTTOUT Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CLKHOLD LOWTOUT RXNACK ARBLOST BUSERR Access R R/W R R/W R R R/W R/W Reset 0 0 0 0 0 0 0 0 BUSSTATE[1:0] z Bits 15:11 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 10 - LENERR: Transaction Length Error This bit is set when automatic length is used for a DMA transaction and the slave sends a NACK before ADDR.LEN bytes have been written by the master. Writing a one to this bit location will clear STATUS.LENERR. This flag is automatically cleared when writing to the ADDR register. Writing a zero to this bit has no effect. This bit is not write-synchronized. z Bit 9 - SEXTTOUT: Slave SCL Low Extend Time-Out This bit is set if a slave SCL low extend time-out occurs. Writing a one to this bit location will clear STATUS.SEXTTOUT. Normal use of the I2C interface does not require the STATUS.SEXTTOUT flag to be cleared by this method. This flag is automatically cleared when writing to the ADDR register. Writing a zero to this bit has no effect. This bit is not write-synchronized. z Bit 8 - MEXTTOUT: Master SCL Low Extend Time-Out This bit is set if a master SCL low time-out occurs. Writing a one to this bit location will clear STATUS.MEXTTOUT. Normal use of the I2C interface does not require the STATUS.MEXTTOUT flag to be cleared by this method. This flag is automatically cleared when writing to the ADDR register. Writing a zero to this bit has no effect. This bit is not write-synchronized. z Bit 7 - CLKHOLD: Clock Hold The Master Clock Hold flag (STATUS.CLKHOLD) is set when the master is holding the SCL line low, stretching the I2C clock. Software should consider this bit a read-only status flag that is set when INTFLAG.SB or INT- Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 558 FLAG.MB is set. When the corresponding interrupt flag is cleared and the next operation is given, this bit is automatically cleared. Writing a zero to this bit has no effect. Writing a one to this bit has no effect. This bit is not write-synchronized. z Bit 6 - LOWTOUT: SCL Low Time-Out This bit is set if an SCL low time-out occurs. Writing a one to this bit location will clear STATUS.LOWTOUT. Normal use of the I2C interface does not require the LOWTOUT flag to be cleared by this method. This flag is automatically cleared when writing to the ADDR register. Writing a zero to this bit has no effect. This bit is not write-synchronized. z Bits 5:4 - BUSSTATE[1:0]: Bus State These bits indicate the current I2C bus state as defined in Table 26-13. After enabling the SERCOM as an I2C master, the bus state will be unknown. Table 26-13. Bus State Value Name Description 0x0 Unknown The bus state is unknown to the I2C master and will wait for a stop condition to be detected or wait to be forced into an idle state by software 0x1 Idle The bus state is waiting for a transaction to be initialized 0x2 Owner The I2C master is the current owner of the bus 0x3 Busy Some other I2C master owns the bus When the master is disabled, the bus-state is unknown. When in the unknown state, writing 0x1 to BUSSTATE forces the bus state into the idle state. The bus state cannot be forced into any other state. Writing STATUS.BUSSTATE to idle will set STATUS.SYNCBUSY. z Bit 3 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 2 - RXNACK: Received Not Acknowledge This bit indicates whether the last address or data packet sent was acknowledged or not. 0: Slave responded with ACK. 1: Slave responded with NACK. Writing a zero to this bit has no effect. Writing a one to this bit has no effect. This bit is not write-synchronized. z Bit 1 - ARBLOST: Arbitration Lost The Arbitration Lost flag (STATUS.ARBLOST) is set if arbitration is lost while transmitting a high data bit or a NACK bit, or while issuing a start or repeated start condition on the bus. The Master on Bus interrupt flag (INTFLAG.MB) will be set when STATUS.ARBLOST is set. Writing the ADDR.ADDR register will automatically clear STATUS.ARBLOST. Writing a zero to this bit has no effect. Writing a one to this bit will clear it. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 559 This bit is not write-synchronized. z Bit 0 - BUSERR: Bus Error The Bus Error bit (STATUS.BUSERR) indicates that an illegal bus condition has occurred on the bus, regardless of bus ownership. An illegal bus condition is detected if a protocol violating start, repeated start or stop is detected on the I2C bus lines. A start condition directly followed by a stop condition is one example of a protocol violation. If a time-out occurs during a frame, this is also considered a protocol violation, and will set BUSERR. If the I2C master is the bus owner at the time a bus error occurs, STATUS.ARBLOST and INTFLAG.MB will be set in addition to BUSERR. Writing the ADDR.ADDR register will automatically clear the BUSERR flag. Writing a zero to this bit has no effect. Writing a one to this bit will clear it. This bit is not write-synchronized. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 560 26.8.2.8 Syncbusy Name: SYNCBUSY Offset: 0x1C Reset: 0x00000000 Property: Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SYSOP ENABLE SWRST Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 31:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 2- SYSOP: System Operation Synchronization Busy Writing CTRLB, STATUS.BUSSTATE, ADDR, or DATA when the SERCOM is enabled requires synchronization. When written, the SYNCBUSY.SYSOP bit will be set until synchronization is complete. 0: System operation synchronization is not busy. 1: System operation synchronization is busy. z Bit 1 - ENABLE: SERCOM Enable Synchronization Busy Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the SYNCBUSY.ENABLE bit will be set until synchronization is complete. Writes to any register (except for CTRLA.SWRST) while enable synchronization is on-going will be discarded and an APB error will be generated. 0: Enable synchronization is not busy. 1: Enable synchronization is busy. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 561 z Bit 0 - SWRST: Software Reset Synchronization Busy Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the SYNCBUSY.SWRST bit will be set until synchronization is complete. Writes to any register while synchronization is on-going will be discarded and an APB error will be generated. 0: SWRST synchronization is not busy. 1: SWRST synchronization is busy. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 562 26.8.2.9 Address Name: ADDR Offset: 0x24 Reset: 0x0000 Property: Write-Synchronized Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 LEN[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 TENBITEN HS LENEN R/W R/W R/W R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Reset Bit Access ADDR[10:8] ADDR[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 31:24 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 23:16 - LEN[7:0]: Transaction Length For DMA operation, this field represents the data length of the transaction from 0 to 255 bytes. The transaction length enable (ADDR.LENEN) must be written to 1 for automatic transaction length to be used. After ADDR.LEN bytes have been transmitted or received, a NACK (for master reads) and STOP are automatically generated. z Bit 15 - TENBITEN: Ten Bit Addressing Enable This bit enables 10-bit addressing. This bit can be written simultaneously with ADDR to indicate a 10-bit or 7-bit address transmission. 0: 10-bit addressing disabled. 1: 10-bit addressing enabled. z Bit 14 - HS: High Speed This bit enables High-speed mode for the current transfer from repeated START to STOP. This bit can be written simultaneously with ADDR for a high speed transfer. 0: High-speed transfer disabled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 563 1: High-speed transfer enabled. z Bit 13 - LENEN: Transfer Length Enable This bit enables automatic transfer length. 0: Automatic transfer length disabled. 1: Automatic transfer length enabled. z Bits 12:11 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 10:0 - ADDR[10:0]: Address When ADDR is written, the consecutive operation will depend on the bus state: Unknown: INTFLAG.MB and STATUS.BUSERR are set, and the operation is terminated. Busy: The I2C master will await further operation until the bus becomes idle. Idle: The I2C master will issue a start condition followed by the address written in ADDR. If the address is acknowledged, SCL is forced and held low, and STATUS.CLKHOLD and INTFLAG.MB are set. Owner: A repeated start sequence will be performed. If the previous transaction was a read, the acknowledge action is sent before the repeated start bus condition is issued on the bus. Writing ADDR to issue a repeated start is performed while INTFLAG.MB or INTFLAG.SB is set. Regardless of winning or loosing arbitration, the entire address will be sent. If arbitration is lost, only ones are transmitted from the point of loosing arbitration and the rest of the address length. STATUS.BUSERR, STATUS.ARBLOST, INTFLAG.MB and INTFLAG.SB will be cleared when ADDR is written. The ADDR register can be read at any time without interfering with ongoing bus activity, as a read access does not trigger the master logic to perform any bus protocol related operations. The I2C master control logic uses bit 0 of ADDR as the bus protocol's read/write flag (R/W); 0 for write and 1 for read. z Bits 31:24 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 23:16 - LEN[7:0]: Transaction Length For DMA operation, this field represents the data length of the transaction from 0 to 255 bytes. The transaction length enable (ADDR.LENEN) must be written to 1 for automatic transaction length to be used. After ADDR.LEN bytes have been transmitted or received, a NACK (for master reads) and STOP are automatically generated. z Bit 15 - TENBITEN: Ten Bit Addressing Enable This bit enables 10-bit addressing. This bit can be written simultaneously with ADDR to indicate a 10-bit or 7-bit address transmission. 0: 10-bit addressing disabled. 1: 10-bit addressing enabled. z Bit 14 - HS: High Speed This bit enables High-speed mode for the current transfer from repeated START to STOP. This bit can be written simultaneously with ADDR for a high speed transfer. 0: .High-speed transfer disabled. 1: High-speed transfer enabled. z Bit 13 - LENEN: Transfer Length Enable This bit enables automatic transfer length. 0: Automatic transfer length disabled. 1: Automatic transfer length enabled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 564 z Bits 12:11 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 10:0 - ADDR[10:0]: Address When ADDR is written, the consecutive operation will depend on the bus state: Unknown: INTFLAG.MB and STATUS.BUSERR are set, and the operation is terminated. Busy: The I2C master will await further operation until the bus becomes idle. Idle: The I2C master will issue a start condition followed by the address written in ADDR. If the address is acknowledged, SCL is forced and held low, and STATUS.CLKHOLD and INTFLAG.MB are set. Owner: A repeated start sequence will be performed. If the previous transaction was a read, the acknowledge action is sent before the repeated start bus condition is issued on the bus. Writing ADDR to issue a repeated start is performed while INTFLAG.MB or INTFLAG.SB is set. Regardless of winning or loosing arbitration, the entire address will be sent. If arbitration is lost, only ones are transmitted from the point of loosing arbitration and the rest of the address length. STATUS.BUSERR, STATUS.ARBLOST, INTFLAG.MB and INTFLAG.SB will be cleared when ADDR is written. The ADDR register can be read at any time without interfering with ongoing bus activity, as a read access does not trigger the master logic to perform any bus protocol related operations. The I2C master control logic uses bit 0 of ADDR as the bus protocol's read/write flag (R/W); 0 for write and 1 for read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 565 26.8.2.10 Data Name: DATA Offset: 0x18 Reset: 0x0000 Property: Write-Synchronized, Read-Synchronized Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 15:8 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 7:0 - DATA[7:0]: Data The master data register I/O location (DATA) provides access to the master transmit and receive data buffers. Reading valid data or writing data to be transmitted can be successfully done only when SCL is held low by the master (STATUS.CLKHOLD is set). An exception occurs when reading the last data byte after the stop condition has been sent. Accessing DATA.DATA auto-triggers I2C bus operations. The operation performed depends on the state of CTRLB.ACKACT, CTRLB.SMEN and the type of access (read/write). Writing or reading DATA.DATA when not in smart mode does not require synchronization. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 566 26.8.2.11 Debug Control Name: DBGCTRL Offset: 0x30 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 DBGSTOP Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:1 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 0 - DBGSTOP: Debug Stop Mode This bit controls functionality when the CPU is halted by an external debugger. 0: The baud-rate generator continues normal operation when the CPU is halted by an external debugger. 1: The baud-rate generator is halted when the CPU is halted by an external debugger. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 567 27. TC - Timer/Counter 27.1 Overview The TC consists of a counter, a prescaler, compare/capture channels and control logic. The counter can be set to count events, or it can be configured to count clock pulses. The counter, together with the compare/capture channels, can be configured to timestamp input events, allowing capture of frequency and pulse width. It can also perform waveform generation, such as frequency generation and pulse-width modulation (PWM). 27.2 Features z Selectable configuration z 8-, 16- or 32-bit TC, with compare/capture channels z Waveform generation z z Frequency generation Single-slope pulse-width modulation z Input capture Event capture Frequency capture z Pulse-width capture z z z One input event z Interrupts/output events on: z z Counter overflow/underflow Compare match or capture z Internal prescaler z Can be used with DMA and to trigger DMA transactions Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 568 Block Diagram Figure 27-1. Timer/Counter Block Diagram BASE COUNTER PER PRESCALER count COUNTER OVF/UNF (INT Req.) clear load COUNT CONTROL LOGIC direction ERR (INT Req.) =0 Zero Update Top = event 27.3 Compare / Capture CONTROL LOGIC WOx Out WAVEFORM GENERATION CC0 match = MCx (INT Req.) Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 569 27.4 Signal Description Signal Name Type Description WO[1:0] Digital output Waveform output Refer to "I/O Multiplexing and Considerations" on page 12 for details on the pin mapping for this peripheral. One signal can be mapped on several pins. 27.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 27.5.1 I/O Lines Using the TC's I/O lines requires the I/O pins to be configured. Refer to "PORT" on page 373 for details. 27.5.2 Power Management The TC can continue to operate in any sleep mode where the selected source clock is running. The TC interrupts can be used to wake up the device from sleep modes. The events can trigger other operations in the system without exiting sleep modes. Refer to "PM - Power Manager" on page 112 for details on the different sleep modes. 27.5.3 Clocks The TC bus clock (CLK_TCx_APB, where x represents the specific TC instance number) can be enabled and disabled in the Power Manager, and the default state of CLK_TCx_APB can be found in the Peripheral Clock Masking section in "PM - Power Manager" on page 112. The different TC instances are paired, even and odd, starting from TC0, and use the same generic clock, GCLK_TCx. This means that the TC instances in a TC pair cannot be set up to use different GCLK_TCx clocks. This generic clock is asynchronous to the user interface clock (CLK_TCx_APB). Due to this asynchronicity, accessing certain registers will require synchronization between the clock domains. Refer to "Synchronization" on page 580 for further details. 27.5.4 DMA The DMA request lines (or line if only one request) are connected to the DMA Controller (DMAC). Using the TC DMA requests requires the DMA Controller to be configured first. Refer to "DMAC - Direct Memory Access Controller" on page 267 for details. 27.5.5 Interrupts The interrupt request line is connected to the Interrupt Controller. Using the TC interrupts requires the Interrupt Controller to be configured first. Refer to "Nested Vector Interrupt Controller" on page 29 for details. 27.5.6 Events To use the TC event functionality, the corresponding events need to be configured in the event system. Refer to "EVSYS - Event System" on page 400 for details. 27.5.7 Debug Operation When the CPU is halted in debug mode the TC will halt normal operation. The TC can be forced to continue operation during debugging. Refer to the Debug Control (DBGCTRL) register for details. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 570 27.5.8 Register Access Protection All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the following registers: z Interrupt Flag register (INTFLAG) z Status register (STATUS) z Read Request register (READREQ) z Count register (COUNT), "Counter Value" on page 602 z Period register (PER), " Period Value" on page 605 z Compare/Capture Value registers (CCx), " Compare/Capture" on page 606 Write-protection is denoted by the Write-Protection property in the register description. When the CPU is halted in debug mode, all write-protection is automatically disabled. Write-protection does not apply for accesses through an external debugger. Refer to "PAC - Peripheral Access Controller" on page 36 for details. 27.5.9 Analog Connections Not applicable. 27.6 Functional Description 27.6.1 Principle of Operation The counter in the TC can be set to count on events from the Event System, or on the GCLK_TCx frequency. The pulses from GCLK_TCx will go through the prescaler, where it is possible to divide the frequency down. The value in the counter is passed to the compare/capture channels, where it can either be compared with user defined values or captured on a predefined event. The TC can be configured as an 8-, 16- or 32-bit counter. Which mode is chosen will determine the maximum range of the counter. The counter range combined with the operating frequency will determine the maximum time resolution achievable with the TC peripheral. The TC can be count up or down. By default, the counter will operate in a continuous mode and count up, where the counter will wrap to the zero when reaching the top value When one of the compare/capture channels is used in compare mode, the TC can be used for waveform generation. Upon a match between the counter and the value in one or more of the Compare/Capture Value registers (CCx), one or more output pins on the device can be set to toggle. The CCx registers and the counter can thereby be used in frequency generation and PWM generation. Capture mode can be used to automatically capture the period and pulse width of signals. 27.6.2 Basic Operation 27.6.2.1 Initialization The following register is enable-protected, meaning that it can only be written when the TC is disabled (CTRLA.ENABLE is zero): z Control A register (CTRLA), except the Run Standby (RUNSTDBY), Enable (ENABLE) and Software Reset (SWRST) bits The following bits are enable-protected: z Event Action bits in the Event Control register (EVCTRL.EVACT) Enable-protected bits in the CTRLA register can be written at the same time as CTRLA.ENABLE is written to one, but not at the same time as CTRLA.ENABLE is written to zero. Before the TC is enabled, it must be configured, as outlined by the following steps: Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 571 z The TC bus clock (CLK_TCx_APB) must be enabled z The mode (8, 16 or 32 bits) of the TC must be selected in the TC Mode bit group in the Control A register (CTRLA.MODE). The default mode is 16 bits z One of the wavegen modes must be selected in the Waveform Generation Operation bit group in the Control A register (CTRLA.WAVEGEN) z If the GCLK_TCx frequency used should be prescaled, this can be selected in the Prescaler bit group in the Control A register (CTRLA.PRESCALER) z If the prescaler is used, one of the presync modes must be chosen in the Prescaler and Counter Synchronization bit group in the Control A register (CTRLA.PRESYNC) z One-shot mode can be selected by writing a one to the One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT) z If the counter should count down from the top value, write a one to the Counter Direction bit in the Control B Set register (CTRLBSET.DIR) z If capture operations are to be used, the individual channels must be enabled for capture in the Capture Channel x Enable bit group in the Control C register (CTRLC.CPTEN) z The waveform output for individual channels can be inverted using the Waveform Output Invert Enable bit group in the Control C register (CTRLC.INVEN) 27.6.2.2 Enabling, Disabling and Resetting The TC is enabled by writing a one to the Enable bit in the Control A register (CTRLA.ENABLE). The TC is disabled by writing a zero to CTRLA.ENABLE. The TC is reset by writing a one to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in the TC, except DBGCTRL, will be reset to their initial state, and the TC will be disabled. Refer to the CTRLA register for details. The TC should be disabled before the TC is reset to avoid undefined behavior. 27.6.2.3 Prescaler Selection As seen in Figure 27-2, the GCLK_TC clock is fed into the internal prescaler. Prescaler output intervals from 1 to 1/1024 are available. For a complete list of available prescaler outputs, see the register description for the Prescaler bit group in the Control A register (CTRLA.PRESCALER). The prescaler consists of a counter that counts to the selected prescaler value, whereupon the output of the prescaler toggles. When the prescaler is set to a value greater than one, it is necessary to choose whether the prescaler should reset its value to zero or continue counting from its current value on the occurrence of an overflow or underflow. It is also necessary to choose whether the TC counter should wrap around on the next GCLK_TC clock pulse or the next prescaled clock pulse (CLK_TC_CNT of Figure 27-2). To do this, use the Prescaler and Counter Synchronization bit group in the Control A register (CTRLA.PRESYNC). If the counter is set to count events from the event system, these will not pass through the prescaler, as seen in Figure 27-2. Figure 27-2. Prescaler PRESCALER GCLK_TC PRESCALER GCLK_TC / {1,2,4,8,64,256,1024 } EVACT CNT EVENT CLK_TC_CNT Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 572 27.6.2.4 TC Mode The counter mode is selected with the TC Mode bit group in the Control A register (CTRLA.MODE). By default, the counter is enabled in the 16-bit counter mode. Three counter modes are available: z COUNT8: The 8-bit TC has its own Period register (PER). This register is used to store the period value that can be used as the top value for waveform generation. z COUNT16: This is the default counter mode. There is no dedicated period register in this mode. z COUNT32: This mode is achieved by pairing two 16-bit TC peripherals. This pairing is explained in "Clocks" on page 570. The even-numbered TC instance will act as master to the odd-numbered TC peripheral, which will act as a slave. The slave status of the slave is indicated by reading the Slave bit in the Status register (STATUS.SLAVE). The registers of the slave will not reflect the registers of the 32-bit counter. Writing to any of the slave registers will not affect the 32-bit counter. Normal access to the slave COUNT and CCx registers is not allowed. 27.6.2.5 Counter Operations The counter can be set to count up or down. When the counter is counting up and the top value is reached, the counter will wrap around to zero on the next clock cycle. When counting down, the counter will wrap around to the top value when zero is reached. In one-shot mode, the counter will stop counting after a wraparound occurs. To set the counter to count down, write a one to the Direction bit in the Control B Set register (CTRLBSET.DIR). To count up, write a one to the Direction bit in the Control B Clear register (CTRLBCLR.DIR). Each time the counter reaches the top value or zero, it will set the Overflow Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.OVF). It is also possible to generate an event on overflow or underflow when the Overflow/Underflow Event Output Enable bit in the Event Control register (EVCTRL.OVFEO) is one. The counter value can be read from the Counter Value register (COUNT) or a new value can be written to the COUNT register. Figure 27-3 gives an example of writing a new counter value. The COUNT value will always be zero when starting the TC, unless some other value has been written to it or if the TC has been previously reloaded at TOP value, because stopped while TC was counting down. Figure 27-3. Counter Operation Period(T) Direction Change COUNT written "update " COUNT TOP BOT DIR Stop Command On the stop command, which can be evoked in the Command bit group in the Control B Set register (CTRLBSET.CMD), the counter will retain its current value. All waveforms are cleared. The counter stops counting, and the Stop bit in the Status register is set (STATUS.STOP). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 573 Retrigger Command and Event Action Retriggering can be evoked either as a software command, using the Retrigger command in the Control B Set register (CTRLBSET.CMD), or as a retrigger event action, using the Event Action bit group in the Event Control register (EVCTRL.EVACT). When a retrigger is evoked while the counter is running, the counter will wrap to the top value or zero, depending on the counter direction.. When a retrigger is evoked with the counter stopped, the counter will continue counting from the value in the COUNT register. Note: When retrigger event action is configured and enabled as an event action, enabling the counter will not start the counter. The counter will start at the next incoming event and restart on any following event. Count Event Action When the count event action is configured, every new incoming event will make the counter increment or decrement, depending on the state of the direction bit (CTRLBSET.DIR). Start Event Action When the TC is configured with a start event action in the EVCTRL.EVACT bit group, enabling the TC does not make the counter start; the start is postponed until the next input event or software retrigger action. When the counter is running, an input event has not effect on the counter. 27.6.2.6 Compare Operations When using the TC with the Compare/Capture Value registers (CCx) configured for compare operation, the counter value is continuously compared to the values in the CCx registers. This can be used for timer or waveform operation. Waveform Output Operations The compare channels can be used for waveform generation on the corresponding I/O pins. To make the waveform visible on the connected pin, the following requirements must be fulfilled: z Choose a waveform generation operation z Optionally, invert the waveform output by writing the corresponding Waveform Output Invert Enable bit in the Control C register (CTRLC.INVx) z Enable the corresponding multiplexor in the PORT The counter value is continuously compared with each CCx available. When a compare match occurs, the Match or Capture Channel x interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.MCx) is set on the next zero-toone transition of CLK_TC_CNT (see Figure 27-4). An interrupt and/or event can be generated on such a condition when INTENSET.MCx and/or EVCTRL.MCEOx is one. One of four configurations in the Waveform Generation Operation bit group in the Control A register (CTRLA.WAVEGEN) must be chosen to perform waveform generation. This will influence how the waveform is generated and impose restrictions on the top value. The four configurations are: z Normal frequency (NFRQ) z Match frequency (MFRQ) z Normal PWM (NPWM) z Match PWM (MPWM) When using NPWM or NFRQ, the top value is determined by the counter mode. In 8-bit mode, the Period register (PER) is used as the top value and the top value can be changed by writing to the PER register. In 16- and 32-bit mode, the top value is fixed to the maximum value of the counter. Frequency Operation When NFRQ is used, the waveform output (WO[x]) toggles every time CCx and the counter are equal, and the interrupt flag corresponding to that channel will be set. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 574 Figure 27-4. Normal Frequency Operation CNT written "wraparound " TOP COUNT CCx Zero WO[x] When MFRQ is used, the value in CC0 will be used as the top value and WO[0] will toggle on every overflow/underflow. Figure 27-5. Match Frequency Operation Period (T) Direction Change COUNT written " wraparound " COUNT TOP Zero WO[0] PWM Operation In PWM operation, the CCx registers control the duty cycle of the waveform generator output. Figure 27-6 shows how in count-up the WO[x] output is set at a start or compare match between the COUNT value and the top value and cleared on the compare match between the COUNT value and CCx register value. In count-down the WO[x] output is cleared at start or compare match between the COUNT value and the top value and set on the compare match between the COUNT value and CCx register value. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 575 Figure 27-6. Normal PWM Operation Period(T) CCn= BOT CCn= TOP "wraparound " "match " TOP COUNT CC n Zero WO[x] In match operation, Compare/Capture register CC0 is used as the top value, in this case a negative pulse will appear on WO[0] on every overflow/underflow. The following equation is used to calculate the exact period for a single-slope PWM (RPWM_SS) waveform: log ( TOP + 1 ) R PWM_SS = ----------------------------------log ( 2 ) f CLK_TC f PWM_SS = -----------------------------N ( TOP + 1 ) where N represent the prescaler divider used (1, 2, 4, 8, 16, 64, 256, 1024). Changing the Top Value Changing the top value while the counter is running is possible. If a new top value is written when the counter value is close to zero and counting down, the counter can be reloaded with the previous top value, due to synchronization delays. If this happens, the counter will count one extra cycle before the new top value is used. Figure 27-7. Changing the Top Value when Counting Down MAX " reload" " write" COUNT ZERO New TOP value That is higher than Current COUNT New TOP value That is Lower than Current COUNT Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 576 When counting up a change from a top value that is lower relative to the old top value can make the counter miss this change if the counter value is larger than the new top value when the change occurred. This will make the counter count to the max value. An example of this can be seen in Figure 27-8. Figure 27-8. Changing the Top Value when Counting Up Counter Wraparound MAX " wraparound " " write " COUNT ZERO New TOP value That is higher than Current COUNT New TOP value That is Lower than Current COUNT 27.6.2.7 Capture Operations To enable and use capture operations, the event line into the TC must be enabled using the TC Event Input bit in the Event Control register (EVCTRL.TCEI). The capture channels to be used must also be enabled in the Capture Channel x Enable bit group in the Control C register (CTRLC.CPTENx) before capture can be performed. Event Capture Action The compare/capture channels can be used as input capture channels to capture any event from the Event System and give them a timestamp. Because all capture channels use the same event line, only one capture channel should be enabled at a time when performing event capture. Figure 27-9 shows four capture events for one capture channel. Figure 27-9. Input Capture Timing events TOP COUNT ZERO Capture 0 Capture 1 Capture 2 Capture 3 When the Capture Interrupt flag is set and a new capture event is detected, there is nowhere to store the new timestamp. As a result, the Error Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.ERR) is set. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 577 Period and Pulse-Width Capture Action The TC can perform two input captures and restart the counter on one of the edges. This enables the TC to measure the pulse width and period. This can be used to characterize the frequency and duty cycle of an input signal: 1 f = --T tp dutyCycle = ---T When using PPW event action, the period (T) will be captured into CC0 and the pulse width (tp) in CC1. In PWP event action, the pulse width (tp) will be captured in CC0 and the period (T) in CC1. Selecting PWP (pulse-width, period) or PPW (period, pulse-width) in the Event Action bit group in the Event Control register (EVCTRL.EVACT) enables the TC to performs two capture actions, one on the rising edge and one on the falling edge. The TC Inverted Event Input in the Event Control register (EVCTRL.TCINV) is used to select whether the wraparound should occur on the rising edge or the falling edge. If EVCTRL.TCINV is written to one, the wraparound will happen on the falling edge. The event source to be captured must be an asynchronous event. To fully characterize the frequency and duty cycle of the input signal, activate capture on CC0 and CC1 by writing 0x3 to the Capture Channel x Enable bit group in the Control C register (CTRLC.CPTEN). When only one of these measurements is required, the second channel can be used for other purposes. The TC can detect capture overflow of the input capture channels. When the Capture Interrupt flag is set and a new capture event is detected, there is nowhere to store the new timestamp. Asa result, INTFLAG.ERR is set. 27.6.3 Additional Features 27.6.3.1 One-Shot Operation When one-shot operation is enabled, the counter automatically stops on the next counter overflow or underflow condition. When the counter is stopped, STATUS.STOP is automatically set by hardware and the waveform outputs are set to zero. One-shot operation can be enabled by writing a one into the One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT) and disabled by writing a one to the One-Shot bit in the Control B Clear register (CTRLBCLR.ONESHOT). When enabled, it will count until an overflow or underflow occurs. The one-shot operation can be restarted with a retrigger command, a retrigger event or a start event. When the counter restarts its operation, the Stop bit in the Status register (STATUS.STOP) is automatically cleared by hardware. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 578 27.6.4 DMA, Interrupts and Events Table 27-1. Module Request for TC Condition Interrupt request Event output Overflow / Underflow x x Channel Compare Match or Capture x Capture Overflow Error x Synchronization Ready x Event input x x1 x Start Counter x Retrigger Counter x Increment / Decrement counter x Simple Capture x Period Capture x Pulse Width Capture x Note: 1. DMA request DMA request is cleared Cleared on next clock cycle For compare channel - Cleared on next clock cycle. For capture channel - cleared when CCx register is read Two DMA requests lines are available, one for each compare/capture channel. 27.6.4.1 DMA Operation The TC can generate the following DMA requests: z Overflow (OVF): the request is set when an update condition (overflow, underflow) is detected. The request is cleared on next clock cycle. z Channel Match or Capture (MCx): for a compare channel, the request is set on each compare match detection and cleared on next clock cycle. For a capture channel, the request is set when valid data is present in CCx register, and cleared when CCx register is read. When using the TC with the DMA OVF request, the new value will be transfered to the register after the update condition. This means that the value is updated after the DMA and synchronization delay, and if the COUNT value has reached the new value before PER or CCx is updated, a match will not happen. When using the TC with the DMA MCx request and updating CCx with a value that is lower than the current COUNT when down-counting, or higher than the current COUNT when up-counting, this value could cause a new compare match before the counter overflows. This will trigger the next DMA transfer, update CCx again, and the previous value is disregarded from the output signal WO[x]. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 579 27.6.4.2 Interrupts The TC has the following interrupt sources: z Overflow/Underflow: OVF. This is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. z Compare or Capture Channel: MCx. This is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. z Capture Overflow Error: ERR. This is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. z Synchronization Ready: SYNCRDY. This is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the TC is reset. See the INTFLAG register for details on how to clear interrupt flags. The TC has one common interrupt request line for all the interrupt sources. The user must read the INTFLAG register to determine which interrupt condition is present. Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to "Nested Vector Interrupt Controller" on page 29 for details. 27.6.4.3 Events The TC can generate the following output events: z Overflow/Underflow (OVF) z Match or Capture (MC) Writing a one to an Event Output bit in the Event Control register (EVCTRL.MCEO) enables the corresponding output event. Writing a zero to this bit disables the corresponding output event. To enable one of the following event actions, write to the Event Action bit group (EVCTRL.EVACT). z Start the counter z Retrigger counter z Increment or decrement counter (depends on counter direction) z Capture event z Capture period z Capture pulse width Writing a one to the TC Event Input bit in the Event Control register (EVCTRL.TCEI) enables input events to the TC. Writing a zero to this bit disables input events to the TC. Refer to "EVSYS - Event System" on page 400 for details on configuring the Event System. 27.6.5 Sleep Mode Operation The TC can be configured to operate in any sleep mode. To be able to run in standby, the RUNSTDBY bit in the Control A register (CTRLA.RUNSTDBY) must be written to one. The TC can wake up the device using interrupts from any sleep mode or perform actions through the Event System. 27.6.6 Synchronization Due to the asynchronicity between CLK_TCx_APB and GCLK_TCx some registers must be synchronized when accessed. A register can require: z Synchronization when written z Synchronization when read z Synchronization when written and read Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 580 z No synchronization When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. The Synchronization Ready interrupt can be used to signal when synchronization is complete. This can be accessed via the Synchronization Ready Interrupt Flag in the Interrupt Flag Status and Clear register (INTFLAG.SYNCRDY). If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is stalled. The following bits need synchronization when written: z Software Reset bit in the Control A register (CTRLA.SWRST) z Enable bit in the Control A register (CTRLA.ENABLE) Write-synchronization is denoted by the Write-Synchronized property in the register description. The following registers need synchronization when written: z Control B Clear register (CTRLBCLR) z Control B Set register (CTRLBSET) z Control C register (CTRLC) z Count Value register (COUNT) z Period Value register (PERIOD) z Compare/Capture Value registers (CCx) Write-synchronization is denoted by the Write-Synchronized property in the register description. The following registers need synchronization when read: z Control B Clear register (CTRLBCLR) z Control B Set register (CTRLBSET) z Control C register (CTRLC) z Count Value register (COUNT) z Period Value register (PERIOD) z Compare/Capture Value registers (CCx) Read-synchronization is denoted by the Read-Synchronized property in the register description. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 581 27.7 Register Summary Table 27-2. Register Summary - 8-Bit Mode Registers Offset Name 0x00 Bit Pos. 7:0 WAVEGEN[1:0] MODE[1:0] ENABLE SWRST CTRLA 0x01 PRESCSYNC[1:0] 15:8 0x02 RUNSTDBY 7:0 PRESCALER[2:0] ADDR[4:0] READREQ 0x03 15:8 RREQ RCONT 0x04 CTRLBCLR 7:0 CMD[1:0] ONESHOT DIR 0x05 CTRLBSET 7:0 CMD[1:0] ONESHOT DIR 0x06 CTRLC 7:0 0x07 Reserved 0x08 DBGCTRL 0x09 Reserved 0x0A CPTEN1 CPTEN0 INVEN1 7:0 INVEN0 DBGRUN 7:0 TCEI TCINV EVACT[2:0] 15:8 MCEO1 MCEO0 EVCTRL 0x0B OVFEO 0x0C INTENCLR 7:0 MC1 MC0 SYNCRDY ERR OVF 0x0D INTENSET 7:0 MC1 MC0 SYNCRDY ERR OVF 0x0E INTFLAG 7:0 MC1 MC0 SYNCRDY ERR OVF 0x0F STATUS 7:0 SLAVE STOP 0x10 COUNT 7:0 COUNT[7:0] 0x11 Reserved 0x12 Reserved 0x13 Reserved 0x14 PER 7:0 PER[7:0] 0x15 Reserved 0x16 Reserved 0x17 Reserved 0x18 CC0 7:0 CC[7:0] 0x19 CC1 7:0 CC[7:0] 0x1A Reserved 0x1B Reserved 0x1C Reserved 0x1D Reserved 0x1E Reserved 0x1F Reserved SYNCBUSY Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 582 Table 27-3. Register Summary - 16-Bit Mode Registers Offset Name 0x00 Bit Pos. 7:0 WAVEGEN[1:0] MODE[1:0] ENABLE SWRST CTRLA 0x01 15:8 0x02 PRESCSYNC[1:0] RUNSTDBY PRESCALER[2:0] ADDR[4:0] 7:0 READREQ 0x03 15:8 RREQ RCONT 0x04 CTRLBCLR 7:0 CMD[1:0] ONESHOT DIR 0x05 CTRLBSET 7:0 CMD[1:0] ONESHOT DIR 0x06 CTRLC 7:0 0x07 Reserved 0x08 DBGCTRL 0x09 Reserved 0x0A CPTEN1 CPTEN0 INVEN1 7:0 INVEN0 DBGRUN 7:0 TCEI TCINV EVACT[2:0] 15:8 MCEO1 MCEO0 EVCTRL 0x0B OVFEO 0x0C INTENCLR 7:0 MC1 MC0 SYNCRDY ERR OVF 0x0D INTENSET 7:0 MC1 MC0 SYNCRDY ERR OVF 0x0E INTFLAG 7:0 MC1 MC0 SYNCRDY ERR OVF 0x0F STATUS 7:0 SLAVE STOP 0x10 SYNCBUSY 7:0 COUNT[7:0] 15:8 COUNT[15:8] 7:0 CC[7:0] 15:8 CC[15:8] 7:0 CC[7:0] 15:8 CC[15:8] COUNT 0x11 0x12 Reserved 0x13 Reserved 0x14 Reserved 0x15 Reserved 0x16 Reserved 0x17 Reserved 0x18 CC0 0x19 0x1A CC1 0x1B 0x1C Reserved 0x1D Reserved 0x1E Reserved 0x1F Reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 583 Table 27-4. Register Summary - 32-Bit Mode Registers Offset Name 0x00 Bit Pos. 7:0 WAVEGEN[1:0] MODE[1:0] ENABLE SWRST CTRLA 0x01 PRESCSYNC[1:0] 15:8 0x02 RUNSTDBY 7:0 PRESCALER[2:0] ADDR[4:0] READREQ 0x03 15:8 RREQ RCONT 0x04 CTRLBCLR 7:0 CMD[1:0] ONESHOT DIR 0x05 CTRLBSET 7:0 CMD[1:0] ONESHOT DIR 0x06 CTRLC 7:0 0x07 Reserved 0x08 DBGCTRL 0x09 Reserved 0x0A CPTEN1 CPTEN0 INVEN1 7:0 INVEN0 DBGRUN 7:0 TCEI TCINV EVACT[2:0] 15:8 MCEO1 MCEO0 EVCTRL 0x0B OVFEO 0x0C INTENCLR 7:0 MC1 MC0 SYNCRDY ERR OVF 0x0D INTENSET 7:0 MC1 MC0 SYNCRDY ERR OVF 0x0E INTFLAG 7:0 MC1 MC0 SYNCRDY ERR OVF 0x0F STATUS 7:0 SLAVE STOP 0x10 SYNCBUSY 7:0 COUNT[7:0] 15:8 COUNT[15:8] 0x12 23:16 COUNT[23:16] 0x13 31:24 COUNT[31:24] 7:0 CC[7:0] 15:8 CC[15:8] 0x1A 23:16 CC[23:16] 0x1B 31:24 CC[31:24] 0x1C 7:0 CC[7:0] 15:8 CC[15:8] 0x1E 23:16 CC[23:16] 0x1F 31:24 CC[31:24] 0x11 COUNT 0x14 Reserved 0x15 Reserved 0x16 Reserved 0x17 Reserved 0x18 0x19 CC0 0x1D CC1 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 584 27.8 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protected property in each individual register description. Refer to the "Register Access Protection" on page 571 and the "PAC - Peripheral Access Controller" on page 36 for details. Some registers require synchronization when read and/or written. Synchronization is denoted by the Write-Synchronized or Read-Synchronized property in each individual register description. Refer to "Synchronization" on page 580 for details. Some registers are enable-protected, meaning they can only be written when the TC is disabled. Enable-protection is denoted by the Enable-Protected property in each individual register description. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 585 27.8.1 Control A Name: CTRLA Offset: 0x00 Reset: 0x0000 Property: Write-Protected, Enable-Protected, Write-Synchronized Bit 15 14 13 12 PRESCSYNC[1:0] 11 10 RUNSTDBY 9 8 PRESCALER[2:0] Access R R R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ENABLE SWRST WAVEGEN[1:0] MODE[1:0] Access R R/W R/W R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 15:14 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 13:12 - PRESCSYNC[1:0]: Prescaler and Counter Synchronization These bits select whether on start or retrigger event the counter should wrap around on the next GCLK_TCx clock or the next prescaled GCLK_TCx clock. It's also possible to reset the prescaler. The options are as shown in Table 27-5. These bits are not synchronized. Table 27-5. Prescaler and Counter Synchronization Value Name Description 0x0 GCLK Reload or reset the counter on next generic clock 0x1 PRESC Reload or reset the counter on next prescaler clock 0x2 RESYNC Reload or reset the counter on next generic clock. Reset the prescaler counter 0x3 - Reserved z Bit 11 - RUNSTDBY: Run in Standby This bit is used to keep the TC running in standby mode: 0: The TC is halted in standby. 1: The TC continues to run in standby. This bit is not synchronized. z Bits 10:8 - PRESCALER[2:0]: Prescaler These bits select the counter prescaler factor, as shown in Table 27-6. These bits are not synchronized. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 586 Table 27-6. Prescaler Value Name Description 0x0 DIV1 Prescaler: GCLK_TC 0x1 DIV2 Prescaler: GCLK_TC/2 0x2 DIV4 Prescaler: GCLK_TC/4 0x3 DIV8 Prescaler: GCLK_TC/8 0x4 DIV16 Prescaler: GCLK_TC/16 0x5 DIV64 Prescaler: GCLK_TC/64 0x6 DIV256 Prescaler: GCLK_TC/256 0x7 DIV1024 Prescaler: GCLK_TC/1024 z Bit 7 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 6:5 - WAVEGEN[1:0]: Waveform Generation Operation These bits select the waveform generation operation. They affect the top value, as shown in "Waveform Output Operations" on page 574. It also controls whether frequency or PWM waveform generation should be used. How these modes differ can also be seen from "Waveform Output Operations" on page 574. These bits are not synchronized. Table 27-7. Waveform Generation Operation Value Name Operation Top Value Waveform Output on Match Waveform Output on Wraparound 0x0 NFRQ Normal frequency PER(1)/Max Toggle No action 0x1 MFRQ Match frequency CC0 Toggle No action Clear when counting up Set when counting up Set when counting down Clear when counting down Clear when counting up Set when counting up Set when counting down Clear when counting down 0x2 NPWM 0x3 Note: MPWM 1. Normal PWM Match PWM PER(1)/Max CC0 This depends on the TC mode. In 8-bit mode, the top value is the Period Value register (PER). In 16- and 32-bit mode it is the maximum value. z Bit 4 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 3:2 - MODE[1:0]: TC Mode These bits select the TC mode, as shown in Table 27-8. These bits are not synchronized. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 587 Table 27-8. TC Mode Value Name Description 0x0 COUNT16 Counter in 16-bit mode 0x1 COUNT8 Counter in 8-bit mode 0x2 COUNT32 Counter in 32-bit mode 0x3 - Reserved z Bit 1 - ENABLE: Enable 0: The peripheral is disabled. 1: The peripheral is enabled. Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete. z Bit 0 - SWRST: Software Reset 0: There is no reset operation ongoing. 1: The reset operation is ongoing. Writing a zero to this bit has no effect. Writing a one to this bit resets all registers in the TC, except DBGCTRL, to their initial state, and the TC will be disabled. Writing a one to CTRLA.SWRST will always take precedence; all other writes in the same write-operation will be discarded. Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 588 27.8.2 Read Request For a detailed description of this register and its use, refer to the"Synchronization" on page 580. Name: READREQ Offset: 0x02 Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 9 8 RREQ RCONT Access W R/W R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADDR[4:0] Access R R R R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bit 15 - RREQ: Read Request Writing a zero to this bit has no effect. This bit will always read as zero. Writing a one to this bit requests synchronization of the register pointed to by the Address bit group (READREQ.ADDR) and sets the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY). z Bit 14 - RCONT: Read Continuously 0: Continuous synchronization is disabled. 1: Continuous synchronization is enabled. When continuous synchronization is enabled, the register pointed to by the Address bit group (READREQ.ADDR) will be synchronized automatically every time the register is updated. z Bits 13:5 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 4:0 - ADDR[4:0]: Address These bits select the offset of the register that needs read synchronization. In the TC, only COUNT and CCx are available for read synchronization. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 589 27.8.3 Control B Clear This register allows the user to change this register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Set (CTRLBSET) register. Name: CTRLBCLR Offset: 0x04 Reset: 0x00 Property: Write-Protected, Write-Synchronized, Read-Synchronized Bit 7 6 5 4 3 2 CMD[1:0] Access ONESHOT 0 DIR R/W R/W R R R R/W R R/W 0 0 0 0 0 0 0 0 Reset z 1 Bits 7:6 - CMD[1:0]: Command These bits are used for software control of retriggering and stopping the TC. When a command has been executed, the CMD bit group will read back as zero. The commands are executed on the next prescaled GCLK_TC clock cycle. Writing a zero to one of these bits has no effect. Writing a one to one of these bits will clear the pending command. Table 27-9. Command Value Name Description 0x0 NONE No action 0x1 RETRIGGER Force a start, restart or retrigger 0x2 STOP Force a stop 0x3 - Reserved z Bits 5:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 2 - ONESHOT: One-Shot This bit controls one-shot operation of the TC. When in one-shot mode, the TC will stop counting on the next overflow/underflow condition or a stop command. 0: The TC will wrap around and continue counting on an overflow/underflow condition. 1: The TC will wrap around and stop on the next underflow/overflow condition. Writing a zero to this bit has no effect. Writing a one to this bit will disable one-shot operation. z Bit 1 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 0 - DIR: Counter Direction This bit is used to change the direction of the counter. 0: The timer/counter is counting up (incrementing). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 590 1: The timer/counter is counting down (decrementing). Writing a zero to this bit has no effect. Writing a one to this bit will make the counter count up. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 591 27.8.4 Control B Set This register allows the user to change this register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Set (CTRLBCLR) register. Name: CTRLBSET Offset: 0x05 Reset: 0x00 Property: Write-Protected, Write-Synchronized, Read-Synchronized Bit 7 6 5 4 3 CMD[1:0] Access 1 ONESHOT 0 DIR R/W R/W R R R R/W R R/W 0 0 0 0 0 0 0 0 Reset z 2 Bits 7:6 - CMD[1:0]: Command These bits is used for software control of retriggering and stopping the TC. When a command has been executed, the CMD bit group will be read back as zero. The commands are executed on the next prescaled GCLK_TC clock cycle. Writing a zero to one of these bits has no effect. Writing a one to one of these bits will set a command. Table 27-10. Command Value Name Description 0x0 NONE No action 0x1 RETRIGGER Force a start, restart or retrigger 0x2 STOP Force a stop 0x3 - Reserved z Bits 5:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 2 - ONESHOT: One-Shot This bit controls one-shot operation of the TC. When active, the TC will stop counting on the next overflow/underflow condition or a stop command. 0: The TC will wrap around and continue counting on an overflow/underflow condition. 1: The timer/counter will wrap around and stop on the next underflow/overflow condition. Writing a zero to this bit has no effect. Writing a one to this bit will enable one-shot operation. z Bit 1 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 0 - DIR: Counter Direction This bit is used to change the direction of the counter. 0: The timer/counter is counting up (incrementing). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 592 1: The timer/counter is counting down (decrementing). Writing a zero to this bit has no effect Writing a one to this bit will make the counter count down. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 593 27.8.5 Control C Name: CTRLC Offset: 0x06 Reset: 0x00 Property: Write-Protected, Write-Synchronized, Read-Synchronized Bit 7 6 5 4 CPTEN1 CPTEN0 3 2 1 0 INVEN1 INVEN0 Access R R R/W R/W R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:6 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 5:4 - CPTENx: Capture Channel x Enable These bits are used to select whether channel x is a capture or a compare channel. Writing a one to CPTENx enables capture on channel x. Writing a zero to CPTENx disables capture on channel x. z Bits 3:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 1:0 - INVENx: Waveform Output x Invert Enable These bits are used to select inversion on the output of channel x. Writing a one to INVENx inverts the output from WO[x]. Writing a zero to INVENx disables inversion of the output from WO[x]. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 594 27.8.6 Debug Control Name: DBGCTRL Offset: 0x08 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 DBGRUN Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:1 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 0 - DBGRUN: Debug Run Mode This bit is not affected by a software reset, and should not be changed by software while the TC is enabled. 0: The TC is halted when the device is halted in debug mode. 1: The TC continues normal operation when the device is halted in debug mode. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 595 27.8.7 Event Control Name: EVCTRL Offset: 0x0A Reset: 0x0000 Property: Write-Protected, Enable-Protected Bit 15 14 13 12 MCEO1 MCEO0 11 10 9 8 OVFEO Access R R R/W R/W R R R R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 TCEI TCINV EVACT[2:0] Access R R R/W R/W R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 15:14 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 13:12 - MCEOx: Match or Capture Channel x Event Output Enable These bits control whether event match or capture on channel x is enabled or not and generated for every match or capture. 0: Match/Capture event on channel x is disabled and will not be generated. 1: Match/Capture event on channel x is enabled and will be generated for every compare/capture. These bits are not enable-protected. z Bits 11:9 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 8 - OVFEO: Overflow/Underflow Event Output Enable This bit is used to enable the Overflow/Underflow event. When enabled an event will be generated when the counter overflows/underflows. 0: Overflow/Underflow event is disabled and will not be generated. 1: Overflow/Underflow event is enabled and will be generated for every counter overflow/underflow. This bit is not enable-protected. z Bits 7:6 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 5 - TCEI: TC Event Input This bit is used to enable input events to the TC. 0: Incoming events are disabled. 1: Incoming events are enabled. This bit is not enable-protected. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 596 z Bit 4 - TCINV: TC Inverted Event Input This bit inverts the input event source when used in PWP or PPW measurement. 0: Input event source is not inverted. 1: Input event source is inverted. This bit is not enable-protected. z Bit 3 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 2:0 - EVACT[2:0]: Event Action These bits define the event action the TC will perform on an event,as shown in Table 27-11. Table 27-11. Event Action Value Name Description 0x0 OFF Event action disabled 0x1 RETRIGGER Start, restart or retrigger TC on event 0x2 COUNT Count on event 0x3 START Start TC on event 0x4 - Reserved 0x5 PPW Period captured in CC0, pulse width in CC1 0x6 PWP Period captured in CC1, pulse width in CC0 0x7 - Reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 597 27.8.8 Interrupt Enable Clear This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Name: INTENCLR Offset: 0x0C Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 MC1 MC0 SYNCRDY 2 1 0 ERR OVF Access R R/W R/W R/W R/W R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:6 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 5:4 - MCx: Match or Capture Channel x Interrupt Enable 0: The Match or Capture Channel x interrupt is disabled. 1: The Match or Capture Channel x interrupt is enabled. Writing a zero to MCx has no effect. Writing a one to MCx will clear the corresponding Match or Capture Channel x Interrupt Disable/Enable bit, which disables the Match or Capture Channel x interrupt. z Bit 3 - SYNCRDY: Synchronization Ready Interrupt Enable 0: The Synchronization Ready interrupt is disabled. 1: The Synchronization Ready interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Synchronization Ready Interrupt Disable/Enable bit, which disables the Synchronization Ready interrupt. z Bit 2 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 1 - ERR: Error Interrupt Enable 0: The Error interrupt is disabled. 1: The Error interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Error Interrupt Disable/Enable bit, which disables the Error interrupt. z Bit 0 - OVF: Overflow Interrupt Enable 0: The Overflow interrupt is disabled. 1: The Overflow interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Overflow Interrupt Disable/Enable bit, which disables the Overflow interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 598 27.8.9 Interrupt Enable Set This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Name: INTENSET Offset: 0x0D Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 MC1 MC0 SYNCRDY 2 1 0 ERR OVF Access R R R/W R/W R/W R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:6 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 5:4 - MCx: Match or Capture Channel x Interrupt Enable 0: The Match or Capture Channel x interrupt is disabled. 1: The Match or Capture Channel x interrupt is enabled. Writing a zero to MCx has no effect. Writing a one to MCx will set the corresponding Match or Capture Channel x Interrupt Enable bit, which enables the Match or Capture Channel x interrupt. z Bit 3 - SYNCRDY: Synchronization Ready Interrupt Enable 0: The Synchronization Ready interrupt is disabled. 1: The Synchronization Ready interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Synchronization Ready Interrupt Disable/Enable bit, which enables the Synchronization Ready interrupt. z Bit 2 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 1 - ERR: Error Interrupt Enable 0: The Error interrupt is disabled. 1: The Error interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Error Interrupt bit, which enables the Error interrupt. z Bit 0 - OVF: Overflow Interrupt Enable 0: The Overflow interrupt is disabled. 1: The Overflow interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 599 27.8.10 Interrupt Flag Status and Clear Name: INTFLAG Offset: 0x0E Reset: 0x00 Property: - Bit 7 6 5 4 3 2 MC1 MC0 SYNCRDY 1 0 ERR OVF Access R R R/W R/W R/W R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:6 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 5:4 - MCx: Match or Capture Channel x This flag is set on the next CLK_TC_CNT cycle after a match with the compare condition or once CCx register contain a valid capture value, and will generate an interrupt request if the corresponding Match or Capture Channel x Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.MCx) is one. Writing a zero to one of these bits has no effect. Writing a one to one of these bits will clear the corresponding Match or Capture Channel x interrupt flag In capture mode, this flag is automatically cleared when CCx register is read. z Bit 3 - SYNCRDY: Synchronization Ready This flag is set on a 1-to-0 transition of the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY), except when the transition is caused by an enable or software reset, and will generate an interrupt request if the Synchronization Ready Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.SYNCRDY) is one. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Synchronization Ready interrupt flag z Bit 2 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 1 - ERR: Error This flag is set if a new capture occurs on a channel when the corresponding Match or Capture Channel x interrupt flag is one, in which case there is nowhere to store the new capture. Writing a zero to this bit has no effect. Writing a one to this bit clears the Error interrupt flag. z Bit 0 - OVF: Overflow This flag is set on the next CLK_TC_CNT cycle after an overflow condition occurs, and will generate an interrupt if INTENCLR/SET.OVF is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Overflow interrupt flag. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 600 27.8.11 Status Name: STATUS Offset: 0x0F Reset: 0x08 Property: - Bit 7 6 5 SYNCBUSY 4 3 SLAVE STOP 2 1 0 Access R R R R R R R R Reset 0 0 0 0 1 0 0 0 z Bit 7 - SYNCBUSY: Synchronization Busy This bit is cleared when the synchronization of registers between the clock domains is complete. This bit is set when the synchronization of registers between clock domains is started. z Bits 6:5 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 4 - SLAVE: Slave This bit is set when the even-numbered master TC is set to run in 32-bit mode. The odd-numbered TC will be the slave. z Bit 3 - STOP: Stop This bit is set when the TC is disabled, on a Stop command or on an overflow or underflow condition when the One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT) is one. 0: Counter is running. 1: Counter is stopped. z Bits 2:0 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 601 27.8.12 Counter Value 27.8.12.1 8-Bit Mode Name: COUNT Offset: 0x10 Reset: 0x00 Property: Write-Synchronized, Read-Synchronized Bit 7 6 5 4 3 2 1 0 COUNT[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - COUNT[7:0]: Counter Value These bits contain the current counter value. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 602 27.8.12.2 16-Bit Mode Name: COUNT Offset: 0x10 Reset: 0x0000 Property: Write-Synchronized, Read-Synchronized Bit 15 14 13 12 11 10 9 8 COUNT[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COUNT[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 15:0 - COUNT[15:0]: Counter Value These bits contain the current counter value. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 603 27.8.12.3 32-Bit Mode Name: COUNT Offset: 0x10 Reset: 0x00000000 Property: Write-Synchronized, Read-Synchronized Bit 31 30 29 28 27 26 25 24 COUNT[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 COUNT[15:8] Access Reset Bit R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 COUNT[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COUNT[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 31:0 - COUNT[31:0]: Counter Value These bits contain the current counter value. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 604 27.8.13 Period Value The Period Value register is available only in 8-bit TC mode. It is not available in 16-bit and 32-bit TC modes. 27.8.13.1 8-Bit Mode Name: PER Offset: 0x14 Reset: 0xFF Property: Write-Synchronized, Read-Synchronized Bit 7 6 5 4 3 2 1 0 PER[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Bits 7:0 - PER[7:0]: Period Value These bits contain the counter period value in 8-bitTC mode. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 605 27.8.14 Compare/Capture 27.8.14.1 8-Bit Mode Name: CCx Offset: 0x18+i*0x1 [i=0..3] Reset: 0x00 Property: Write-Synchronized, Read-Synchronized Bit 7 6 5 4 3 2 1 0 CC[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - CC[7:0]: Compare/Capture Value These bits contain the compare/capture value in 8-bit TC mode. In frequency or PWM waveform match operation (CTRLA.WAVEGEN), the CC0 register is used as a period register. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 606 27.8.14.2 16-Bit Mode Name: CCx Offset: 0x18+i*0x2 [i=0..3] Reset: 0x0000 Property: Write-Synchronized, Read-Synchronized Bit 15 14 13 12 11 10 9 8 CC[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CC[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 15:0 - CC[15:0]: Compare/Capture Value These bits contain the compare/capture value in 16-bit TC mode. In frequency or PWM waveform match operation (CTRLA.WAVEGEN), the CC0 register is used as a period register. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 607 27.8.14.3 32-Bit Mode Name: CCx Offset: 0x18+i*0x4 [i=0..3] Reset: 0x00000000 Property: Write-Synchronized, Read-Synchronized Bit 31 30 29 28 27 26 25 24 CC[31:24] Access Reset Bit R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 CC[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 CC[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CC[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 31:0 - CC[31:0]: Compare/Capture Value These bits contain the compare/capture value in 32-bit TC mode. In frequency or PWM waveform match operation (CTRLA.WAVEGEN), the CC0 register is used as a period register. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 608 28. TCC - Timer/Counter for Control Applications 28.1 Overview The Timer/Counter for Control applications (TCC) consists of a counter, a prescaler, compare/capture channels and control logic. The counter can be set to count events or clock pulses. The counter together with the compare/capture channels can be configured to time stamp input events, allowing capture of frequency and pulse-width. It can also perform waveform generation such as frequency generation and pulse-width modulation. Waveform extensions are intended for motor control, ballast, LED, H-bridge, power converters, and other types of power control applications. It enables low- and high-side output with optional dead-time insertion. It can also generate a synchronized bit pattern across the waveform output pins. The fault options enable fault protection for safe and deterministic handling, disabling and/or shut down of external drivers. The Timer/Counter Block diagram (Figure 28-2 on page 610) shows all the features in TCC but table below shows the configuration of each of the TCCs. Figure 28-1. TCC Configuration Summary TCC# Channels (CC_NUM) (WO_NUM) Counter size Fault Dithering Output matrix Dead Time Insertion (DTI) 0 4 6 24-bit X X X X 1 2 4 24-bit X X 2 2 2 16-bit X 28.2 Waveform Output SWAP Pattern generation X X X Features z Up to four compare/capture channels (CC) with: Double buffered period setting Double buffered compare or capture channel z Circular buffer on period and compare channel registers z z z Waveform generation: Frequency generation Single-slope pulse-width modulation (PWM) z Dual-slope pulse-width modulation with half-cycle reload capability z z z Input capture: Event capture Frequency capture z Pulse-width capture z z z Waveform extensions: Configurable distribution of compare channels outputs across port pins Low- and high-side output with programmable dead-time insertion z Waveform swap option with double buffer support z Pattern generation with double buffer support z Dithering support z z z Fault protection for safe drivers disabling: Two recoverable fault sources Two non-recoverable fault sources z Debugger can be source of non-recoverable fault z z z Input event: z Two input events for counter Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 609 z One input event for each channel z Output event: z z Three output events (Count, Retrigger and Overflow) available for counter One Compare Match/Input Capture event output for each channel z Interrupts: Overflow and Retrigger interrupt Compare Match/Input Capture interrupt z Interrupt on fault detection z z z Can be used with DMA and can trigger DMA transactions 28.3 Block Diagram Figure 28-2. Timer/Counter Block Diagram Base Counter PERB PER Prescaler "count" "clear" "load" "direction" Counter COUNT = OVF (INT/Event/DMA Req.) ERR (INT Req.) Control Logic TOP BOTTOM =0 "TCCx_EV0" "TCCx_EV1" "ev" UPDATE BV "TCCx_MCx" Event System WO[7] 28.4 Waveform Generation Pattern Generation SWAP Dead-Time Insertion Control Logic CCx = Output Matrix CCBx Recoverable Faults BV "capture" Non-recoverable Faults WO[6] Compare/Capture (Unit x = {0,1,...,3}) WO[5] WO[4] WO[3] WO[2] WO[1] WO[0] "match" MCx (INT/Event/DMA Req.) Signal Description Pin Name Type Description TCCx/WO[0] Digital output Compare channel 0 waveform output TCCx/WO[1] Digital output Compare channel 1 waveform output ... ... ... TCCx/WO[WO_NUM-1] Digital output Compare channel n waveform output Refer to Table 5-1 in the "I/O Multiplexing and Considerations" on page 12 for details on the pin mapping for this peripheral. One signal can be mapped on several pins. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 610 28.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 28.5.1 I/O Lines Using the TCC's I/O lines requires the I/O pins to be configured. Refer to "PORT" on page 373 for details. 28.5.2 Power Management The TCC will continue to operate in any sleep mode where the selected source clock is running. The TCC's interrupts can be used to wake up the device from sleep modes. Events connected to the event system can trigger other operations in the system without exiting sleep modes. Refer to "PM - Power Manager" on page 112 for details on the different sleep modes. 28.5.3 Clocks The TCC bus clock (CLK_TCCx_APB, where x represents the specific TCC instance number) can be enabled and disabled in the power manager, and the default state of CLK_TCCx_APB can be found in the Peripheral Clock Masking section in "PM - Power Manager" on page 112. A generic clock (GCLK_TCCx) is required to clock the TCC. This clock must be configured and enabled in the generic clock controller before using the TCC. Refer to "GCLK - Generic Clock Controller" on page 90 for details. This generic clock is asynchronous to the bus clock (CLK_TCCx_APB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. Refer to "Synchronization" on page 641 for further details. 28.5.4 DMA The DMA request lines are connected to the DMA Controller (DMAC). Using the TCC DMA requests, requires the DMA Controller to be configured first. Refer to "DMAC - Direct Memory Access Controller" on page 267 for details. 28.5.5 Interrupts The interrupt request line is connected to the Interrupt Controller. Using the TCC interrupts requires the interrupt controller to be configured first. Refer to "Nested Vector Interrupt Controller" on page 29 for details. 28.5.6 Events The events are connected to the Event System. Refer to "EVSYS - Event System" on page 400 for details on how to configure the Event System. 28.5.7 Debug Operation When the CPU is halted in debug mode the TCC will halt normal operation. The TCC can be forced to continue operation during debugging. Refer to DBGCTRL for details. 28.5.8 Register Access Protection All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the following registers: z Interrupt Flag register (INTFLAG) z Status register (STATUS) z Period and Period Buffer registers (PER, PERB) z Compare/Capture and Compare/Capture Buffer registers (CCx, CCBx) z Control Waveform and Control Waveform Buffer registers (WAVE, WAVEB) z Pattern Generation Value and Pattern Generation Value Buffer registers (PATT, PATTB) Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 611 Write-protection is denoted by the Write-Protected property in the register description. Write-protection does not apply to accesses through an external debugger. Refer to "PAC - Peripheral Access Controller" on page 36 for details. 28.5.9 Analog Connections Not applicable. 28.6 Functional Description 28.6.1 Principle of Operation Each TCC instance has up to four compare/capture channels (CCx). The following definitions are used throughout the documentation: Figure 28-3. Timer/Counter Definitions Name Description TOP The counter reaches TOP when it becomes equal to the highest value in the count sequence. The TOP value can be equal to the period (PER) or the compare channel A (CCA) register setting. This is selected by the waveform generator mode. BOTTOM The counter reaches BOTTOM when it becomes zero MAX The counter reaches maximum when it becomes all ones UPDATE The timer/counter signals an update when it reaches BOTTOM or TOP, depending on the direction settings. In general, the term "timer" is used when the timer/counter clock control is handled by an internal source, and the term "counter" is used when the clock control is handled externally (e.g. counting external events). When used for compare operations, the CC channels are referred to as "compare channels." When used for capture operations, the CC channels are referred to as "capture channels." The counter register (COUNT), period registers with buffer (PER and PERB), and compare and capture registers with buffers (CCx and CCxB) are 16 or 24-bit registers, depending on each TCC instance. Each buffer register has a buffer valid (BV) flag that indicates when the buffer contains a new value. During normal operation, the counter value is continuously compared to the Period (TOP) and to ZERO value to determine whether the counter has reached TOP or ZERO. The counter value is also compared to the CCx registers. These comparisons can be used to generate interrupt requests, request DMA transactions or generate events for the event system. The waveform generator modes use these comparisons to set the waveform period or pulse width. A prescaled generic clock (GCLK_TCCx) and events from the event system can be used to control the counter. The event system is also used as a source to the input capture. The recoverable fault module extension enables event controlled waveforms by acting directly on the generated waveforms from TCC compare channels output. These events can restart, halt the timer/counter period or shorten the output pulse active time, or disable waveform output as long as the fault condition is present. This can typically be used for current sensing regulation or zero crossing and demagnetization retriggering. The MCE0 and MCE1 event sources are shared with the recoverable fault module. Only asynchronous events are used internally when fault unit extension is enabled. For further details on how to configure asynchronous events routing, refer to section "EVSYS - Event System" on page 400. By using digital filtering and/or input blanking, qualification options (as detailed in "Recoverable Faults" on page 629), recoverable fault sources can be filtered and/or windowed to avoid false triggering, for example from I/O pin glitches. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 612 In addition as shown in Figure 28-2 on page 610, six optional independent and successive units primarily intended for use with different types of motor control, ballast, LED, H-bridge, power converter, and other types of power switching applications, are implemented in some of TCC instances. The output matrix (OTMX) can distribute and route out the TCC waveform outputs across the port pins in different configurations, each optimized for different application types. The dead time insertion (DTI) unit splits the four lower OTMX outputs into two non-overlapping signals, the non-inverted low side (LS) and inverted high side (HS) of the waveform output with optional dead-time insertion between LS and HS switching. The swap (SWAP) unit can be used to swap the LS and HS pin outputs, and can be used for fast decay motor control. The pattern generation unit can be used to generate synchronized waveforms with constant logic level on TCC update conditions. This is for example useful for easy stepper motor and full bridge control. The non-recoverable fault module enables event controlled fault protection by acting directly on the generated waveforms from timer/counter compare channels output. When a non-recoverable fault condition is detected, the output waveforms are forced to a safe and pre-configured value that is safe for the application. This is typically used for instant and predictable shut down and disabling high current or voltage drives. The count event sources (TCE0 and TCE1) are shared with the non-recoverable fault extension. The events can be optionally filtered. If the filter options are not used, the non-recoverable faults provide an immediate asynchronous action on waveform output, even for cases where the clock is not present. For further details on how to configure asynchronous events routing, refer to section "EVSYS - Event System" on page 400. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 613 28.6.2 Basic Operation 28.6.2.1 Initialization The following registers are enable-protected, meaning that it can only be written when the TCC is disabled (CTRLA.ENABLE is zero): z Control A (CTRLA) register, except Run Standby (RUNSTDBY), Enable (ENABLE) and Software Reset (SWRST) bits z Recoverable Fault n Control register (FCTRLA and FCTRLB) z Waveform Extension Control register (WEXCTRL) z Drive Control register (DRVCTRL) z Event Control register Enable-protected bits in the CTRLA register can be written at the same time as CTRLA.ENABLE is written to one, but not at the same time as CTRLA.ENABLE is written to zero. Enable-protection is denoted by the Enable-Protected property in the register description. Before the TCC is enabled, it must be configured as outlined by the following steps: z Enable the TCC bus clock (CLK_TCCx_APB) first z If Capture mode is required, enable the channel in capture mode by writing a one to Capture Enable bit in Control A register (CTRLA.CAPTEN) Optionally, the following configurations can be set before or after enabling TCC: z Select PRESCALER setting in the Control A register (CTRLA.PRESCALER) z Select Prescaler Synchronization setting in Control A register (CTRLA.PRESCSYNC) z If down-counting operation must be enabled, write a one to the Counter Direction bit in the Control B Set register (CTRLBSET.DIR) z Select the Waveform Generation operation in WAVE register (WAVE.WAVEGEN) z Select the Waveform Output Polarity in the WAVE register (WAVE.POL) z The waveform output can be inverted for the individual channels using the Waveform Output Invert Enable bit group in the Driver register (DRVCTRL.INVEN) 28.6.2.2 Enabling, Disabling and Resetting The TCC is enabled by writing a one to the Enable bit in the Control A register (CTRLA.ENABLE). The TCC is disabled by writing a zero to CTRLA.ENABLE. The TCC is reset by writing a one to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in the TCC, except DBGCTRL, will be reset to their initial state, and the TCC will be disabled. Refer to CTRLA register for details. The TCC should be disabled before the TCC is reset to avoid undefined behavior. 28.6.2.3 Prescaler Selection The GCLK_TCCx is fed into the internal prescaler. Prescaler output intervals from 1 to 1/1024 are available. For a complete list of available prescaler outputs, see the register description for the Prescaler bit group in the Control A register (CTRLA.PRESCALER). The prescaler consists of a counter that counts to the selected prescaler value, whereupon the output of the prescaler toggles. When the prescaler is set to a value greater than one, it is necessary to choose whether the prescaler should reset its value to zero or continue counting from its current value on the occurrence of an external re-trigger. It is also necessary to choose whether the TCC counter should wrap around on the next GCLK_TCC clock pulse or the next prescaled clock pulse (CLK_TCC_CNT in Figure 28-4). To do this, use the Prescaler and Counter synchronization bit group in the Control A register (CTRLA.PRESYNC). If the counter is set to count events from the event system, these will not pass through the prescaler. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 614 Figure 28-4. Prescaler PRESCALER GCLK_TCC PRESCALER GCLK_TCC / {1,2,4,8,64,256,1024 } EVACT 0/1 COUNT TCCx EV0/1 CLK_TCC_COUNT 28.6.2.4 Counter Operation Depending on the mode of operation, the counter is cleared, reloaded, incremented, or decremented at each TCC clock cycle (CLK_TCC_CNT). A counter clear or reload mark the end of current counter cycle and the start of a new one. The counter will count in the direction set by the direction (CTRLBSET.DIR or CTRLBCLR.DIR) bit for each clock until it reaches TOP or ZERO. A clear operation occurs when the TOP is reached while up-counting, the counter will be set to ZERO (cleared) on the next clock cycle. A reload operation occurs when the ZERO is reached while down-counting, the counter is reloaded with the period register (PER) value. The counter value is continuously compared with the period (PER) and ZERO value to determine if the counter has reached TOP or ZERO. Based on this comparison, the Overflow Interrupt Flag in the Interrupt Flag Status and Clear register (INTFLAG.OVF)is set whenever the counter value matches with TOP / ZERO. This can be used to trigger an interrupt, a DMA request, or an event. If the One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT) is set, the compare match (with TOP/ZERO) will stop the counting operation. Up-counting is enabled by writing a one to the Direction bit in the Control B Clear register (CTRLBCLR.DIR). Downcounting is enabled by writing a one to the Direction bit in the Control B Set register (CTRLBSET.DIR). Figure 28-5. Counter Operation Period (T) Direction Change COUNT written MAX "reload" update "clear" update COUNT TOP ZERO DIR As shown in Figure 28-5, it is possible to change the counter value (by writing directly in the Count register) even when the counter is running. The write access has higher priority than count, clear, or reload. The direction of the counter can also be changed during normal operation. Due to asynchronous clock domains, the internal counter settings are written when the synchronization is complete. Normal operation must be used when using the counter as timer base for the capture channels. Stop Command and Event Action A stop command can be issued from software by using TCC Command bits in Control B Set register (CTRLBSET.CMD = STOP) or when the stop event action is configured in the Input Event1 Action bits in Event Control register (EVCTRL.EVACT1 = STOP). When a stop is detected while the counter is running, the counter will maintain its current value. If waveform generation (WG) is used, all waveforms are set to a state defined in Non-Recoverable State x Output Enable bit and Non- Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 615 Recoverable State x Output Value bit in the Driver Control register.(DRVCTRL.NRE and DRVCTRL.NRV) and the Stop bit in the Status register is set (STATUS.STOP). Retrigger Command and Event Action A retrigger command can be issued from software by using TCC Command bits in Control B Set register (CTRLBSET.CMD = RETRIGGER) or when the retrigger event action is configured in the Input Event0/1 Action bits in Event Control register (EVCTRL.EVACT1 = RETRIGGER). When the command is detected during counting operation, the counter will be reloaded or cleared, depending on the counting direction (CTRLSET.DIR or CTRLBCLR.DIR). The Retrigger bit will be set in the Interrupt Flag Status and Clear register (INTFLAG.TRG). It is also possible to generate an event by writing a one to the Retrigger Event Output Enable bit in the Event Control register (EVCTRL.TRGEO). If the retrigger command is detected when the counter is stopped, the counter will resume counting operation from the value in COUNT. Note: When re-trigger event action is enabled, enabling the counter will not start the counter. The counter will start on the next incoming event and restart on corresponding following event. Start Event Action The start action can be selected in the Event Control register (EVCTRL.EVACT0) and can be used to start the counting operation when stopped. As consequence, the event has no effect if the counter is already counting. When the module is enabled, the counter operation starts when the event is received or when a retrigger software command is applied.When retrigger or start event action is enabled, enabling counter will not start the counter. The counter will start on the next incoming event and restart on corresponding following event. If the event action is disabled, enabling counter will start the counter. Count Event Action The count action can be selected in the Event Control register (EVCTRL.EVACT0) and can be used to count external events (from pins for example). When an event is received, the counter is incremented or decremented, depending on direction settings (CTRLBSET.DIR or CTRLBCLR.DIR). Direction Event Action The direction event action can be selected in the Event Control register (EVCTRL.EVACT1). When this event is used, the asynchronous event path specified in the event system must be configured or selected. The direction event action can be used to control the direction of the counter operation, depending on external events level. When received, the event level overrides the Direction settings (CTRLBSET.DIR or CTRLBCLR.DIR) and the direction bit value is updated accordingly. Increment Event Action The increment event action can be selected in the Event Control register (EVCTRL.EVACT0) and can be used to change the counter state when an event is received. When the TCE0 event is received, the counter increments, whatever direction settings (CTRLBSET.DIR or CTRLBCLR.DIR) is. Decrement Event Action The decrement event action can be selected in the Event Control register (EVCTRL.EVACT1) and can be used to change the counter state when an event is received. When the TCE1 event is received, the counter decrements, whatever direction settings (CTRLBSET.DIR or CTRLBCLR.DIR) is. Non-Recoverable Fault Event Action Non-recoverable fault actions can be selected in the Event Control register (EVCTRL.EVACT0 or EVCTRL.EVACT1). When received, the counter will be stopped and compare channels outputs are overridden according to DRVCTRL register settings (Non-Recoverable State x Output Enable bits and Non-Recoverable State x Output Value bits). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 616 TCE0 and TCE1 must be configured as asynchronous events. 28.6.2.5 Compare Operations By default, Compare/Capture channel is configured for Compare operations. To perform capture operations, it must be re-configured. When using the TCC with the Compare/Capture Value registers (CCx) configured for compare operations, the counter value is continuously compared to the values in the CCx registers. This can be used for timer or for waveform operation. The compare buffer (CCBx) register provides double buffer capability. The double buffering synchronizes the update of the CCx register with the buffer value at the UPDATE condition. For further details, refer to "Double Buffering" on page 621. The synchronization prevents the occurrence of odd-length, non-symmetrical pulses and ensures glitch-free output. If Compare/Capture channel is not configured for capture operation Control A register), then compare operation will be enabled. Waveform Output Generation Operations The compare channels can be used for waveform generation on output port pins. To make the waveform visible on the connected pin, the following requirements must be fulfilled: 1. Choose a waveform generation mode in the Waveform Control register (WAVE.WAVEGEN) 2. Optionally invert the waveform output WO[x] by writing the corresponding Waveform Output Invert Enable bit in the Driver Control register (DRVCTRL.INVENx) 3. Configure the PORT module to enable the peripheral function on the pin The counter value is continuously compared with each CCx value. When a compare match occurs, the Match or Capture Channel x bit in the Interrupt Flag Status and Clear register (INTFLAG.MCx) is set on the next zero-to-one transition of CLK_TCC_COUNT. If Match/Capture occurs, interrupt can be generated when INTENSET.MCX is set. If Compare/Match occurs, an event can be triggered when EVCTRL.MCEOx is set to one. Both interrupt and event can be generated simultaneously. The same condition generates a DMA request. Six waveform configurations are available through the Waveform Generation (WG) bit group in the Waveform Control register (WAVE.WAVEGEN): z Normal Frequency (NFRQ) z Match Frequency (MFRQ) z Single-slope PWM (NPWM) z Dual-slope, interrupt/event at Top (DSTOP) z Dual-slope, interrupt/event at ZERO (DSBOTTOM) z Dual-slope, interrupt/event at Top and ZERO (DSBOTH) z Dual-slope, critical interrupt/event at ZERO (DSCRITICAL) When using MFRQ, the top value is defined by the CC0 register value, for all other waveforms operation the top value is defined by Period (PER) register value. For dual slope waveform operations update time occurs when counter reaches the zero value. For all other waveforms generation modes, the update time occurs on counter wraparound, on overflow, underflow or retrigger. Normal Frequency Generation For normal frequency generation, the period time is controlled by the period register (PER). The waveform generation output (WO[x]) is toggled on each compare match between COUNT and CCx, and the corresponding Match or Capture Channel x will be set. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 617 Figure 28-6. Normal Frequency Operation Period (T) Direction Change COUNT Written MAX COUNT "reload" update "clear" update "match" TOP CCx ZERO WO[x] Match Frequency Generation For match frequency generation, the period time is controlled by CC0 instead of PER. WO[0] toggles on each update condition. Figure 28-7. Match Frequency Operation Period (T) Direction Change COUNT Written MAX "reload" update "clear" update COUNT CC0 ZERO WO[0] Single-Slope PWM Generation For single-slope PWM generation, the period time is controlled by PER, while CCx control the duty cycle of the generated waveform output. When up-counting, WO[x] is set at start or compare match between the COUNT and TOP values, and cleared on compare match between COUNT and CCx register values. When down-counting, WO[x] is cleared at start or compare match between the COUNT and TOP values, and set on compare match between COUNT and CCx register values. Figure 28-8. Single-Slope PWM Operation Period (T) CCx=ZERO CCx=TOP "clear" update "match" MAX TOP COUNT CCx ZERO WO[x] Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 618 The following equation calculates the exact resolution for a single-slope PWM (RPWM_SS) waveform: log(TOP+1) R PWM_SS = ----------------------------log(2) The PWM frequency depends on the Period register value (PER) and the peripheral clock frequency (fGCLK_TCC), and can be calculated by the following equation: f GCLK_TCC f PWM_SS = -------------------------N(TOP+1) Where N represent the prescaler divider used (1, 2, 4, 8, 16, 64, 256, 1024). Dual-Slope PWM Generation For dual-slope PWM generation, the period (TOP) is controlled by PER, while CCx control the duty cycle of the generated waveform output. Figure 28-9 shows how the counter repeatedly counts from ZERO (BOTTOM) to PER and then from PER to ZERO. The waveform generator output is set on compare match when up-counting, and cleared on compare match when down-counting. An interrupt/event is generated on TOP and/or ZERO depend of Dual slope operation selected Table 28-1. In DSBOTH operation, a second update time occur on TOP. Figure 28-9. Dual-Slope Pulse Width Modulation Period (T) CCx=ZERO CCx=TOP "update" "match" MAX CCx COUNT TOP ZERO WO[x] Using dual-slope PWM results in a lower maximum operation frequency compared to single-slope PWM generation. The period (TOP) defines the PWM resolution. The minimum resolution is 1 bits (TOP=0x00000001). The following equation calculates the exact resolution for dual-slope PWM (RPWM_DS): log(PER+1) R PWM_DS = ----------------------------log(2) The PWM frequency depends on the period setting (TOP) and the peripheral clock frequency (fGCLK_TCC), and can be calculated by the following equation: f GCLK_TCC f PWM_DS = -------------------------2N PER Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 619 N represents the prescaler divider used. The waveform generated will have a maximum frequency of half of the TCC clock frequency (fGCLK_TCC) when TOP is set to one (0x00000001) and no prescaling is used. The pulse width (PPWM_DS) depends on the compare channel (CCx) register value and the peripheral clock frequency (fGCLK_TCC), and can be calculated by the following equation: 2N ( PER - CCx ) P PWM_DS = --------------------------------------------f GCLK_TCC Where N represents the prescaler divider used. Note: In DSTOP, DSBOTTOM and DSBOTH operation, when TOP is lower than MAX/2 the CCx MSB bit defines the ramp (rising if CCx[MSB] is 0, or falling if CCx[MSB] is 1) on which the CCx Match interrupt or event is generated. Dual-Slope Critical PWM Generation Critical mode operation allows generation of non-aligned centered pulses. In this mode, the period time is controlled by PER, while CCx control the generated waveform output edge during up-counting and CC(x+CC_NUM/2) control the generated waveform output edge during down-counting. Figure 28-10.Dual-Slope Critical Pulse Width Modulation (N=CC_NUM) Period (T) "reload" update "match" MAX CCx COUNT CC(x+N/2) CCx CC(x+N/2) CCx CC(x+N/2) TOP ZERO WO[x] The table below shows the update counter and overflow event/interrupt generation conditions in different operation modes. Table 28-1. Counter Update and Overflow Event/Interrupt Conditions Description Description Name Operation Top Update Output Waveform On Match Output Waveform On Update OVFIF/Event Up Down NFRQ Normal Frequency PER TOP/ZERO Toggle Stable TOP ZERO MFRQ Match Frequency CC0 TOP/ZERO Toggle Stable TOP ZERO Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 620 Table 28-1. Counter Update and Overflow Event/Interrupt Conditions (Continued) Description Description Output Waveform On Match Output Waveform On Update OVFIF/Event Up Down Name Operation Top Update NPWM Single-slope PWM PER TOP/ZERO TOP ZERO DSCRITICAL Dual-slope PWM PER ZERO - ZERO DSBOTTOM Dual-slope PWM PER ZERO - ZERO DSBOTH Dual-slope PWM PER TOP & ZERO TOP ZERO DSTOP Dual-slope PWM PER ZERO TOP - See Table 28-2 Output Polarity The polarity (WAVE.POLx) is available in all waveform output generation. In single-slope and dual-slope PWM generation, it is possible to invert individually the pulse edge alignment on start or end of PWM cycle for each compare channels. Table 28-2 shows the waveform output set/clear conditions, depending on timer/counter settings, direction and polarity setting. Table 28-2. Waveform Generation Set/Clear Conditions Waveform Generation operation DIR 0 Single-Slope PWM 1 Dual-Slope PWM POLx Waveform Generation Output Update Set Clear 0 Timer/counter matches TOP Timer/counter matches CCx 1 Timer/counter matches CC Timer/counter matches TOP 0 Timer/counter matches CC Timer/counter matches ZERO 1 Timer/counter matches ZERO Timer/counter matches CC 0 Timer/counter matches CC when counting up Timer/counter matches CC when counting down 1 Timer/counter matches CC when counting down Timer/counter matches CC when counting up x In Normal and Match Frequency, the WAVE.POLx value represents the initial state of the waveform output. 28.6.2.6 Double Buffering The Pattern (PATT), Waveform (WAVE), Period (PER) and the Compare Channels (CCx) registers are all double buffered. Each buffer register has a Buffer Valid (PATTBV, WAVEBV, PERBV or CCBVx) bit in the STATUS register, which indicates that the buffer register contains a value that can be copied into the corresponding register. When double buffering is enabled by writing a one to the Lock Update bit in the Control B Clear register (CTRLBCLR.LUPD) and the PER and CCx are used for a compare operation, the Buffer Valid bit is set when data has been written to a buffer register and cleared on an update condition. This is shown for a compare register in Figure 28-11. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 621 Figure 28-11.Compare Channel Double Buffering "APB write enable" BV UPDATE "data write" EN CCBx EN CCx COUNT "match" = As both the register (PATT/WAVE/PER/CCx) and corresponding buffer register (PATTB/WAVEB/PERB/CCBx) are available in the I/O register map, the double buffering feature is not mandatory. The double buffering is disabled by writing a one to CTRLSET.LUPD. This allows initialization and bypassing of the buffer register and the double buffering feature. Note: In normal frequency (NFRQ), match frequency (MFRQ) or PWM down-counting counter mode (CTRLBSET.DIR is one), PER is written at the same time as PERB is written if CTRLB.LUPD is zero or as soon as CTRLB.LUPD becomes zero. Changing the Period The counter period is changed by writing a new value to the Period register or the Period Buffer register. If double buffering is not used, any update of PER is effective after the synchronization delay. Figure 28-12.Unbuffered Single-Slope Up-Counting Operation Counter Wraparound MAX "clear" update "write" COUNT ZERO New value written to PER that is higher than current COUNT New value written to PER that is lower than current COUNT Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 622 Figure 28-13.Unbuffered Single-Slope Down-Counting Operation MAX "reload" update "write" COUNT ZERO New value written to PER that is higher than current COUNT New value written to PER that is lower than current COUNT A counter wraparound can occur in any mode of operation when up-counting without buffering, as shown in Figure 28-12. This due to the fact that COUNT and TOP are continuously compared, and if a new value that is lower than the current COUNT is written to TOP, COUNT will wrap before a compare match happen. Figure 28-14.Unbuffered Dual-Slope Operation Counter Wraparound MAX "update" "write" COUNT ZERO New value written to PER that is higher than current COUNT New value written to PER that is lower than current COUNT When double buffering is used, the buffer can be written at any time and the counter will still maintain correct operation. The period register is always updated on the update condition, as shown for dual-slope operation in Figure 28-15. This prevents wraparound and the generation of odd waveforms. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 623 Figure 28-15.Changing the Period Using Buffering MAX "reload" update "write" COUNT ZERO New value written to PERB that is higher than current COUNT New value written to PERB that is lower than current COUNT PER is updated with PERB value. 28.6.2.7 Capture Operations To enable and use capture operations, the Match or Capture Channel x Event Input Enable (MCEIx) bit must be enabled in the Event Control register (EVCTRL.MCEIx). The capture channels to be used must also be enabled in the Capture Channel x Enable bit in the Control A register (CTRLA.CPTENx) before capture can be performed. Event Capture Action The capture channels can be used to capture the COUNT value upon reception of any event. Since there is one event line per capture channel, multiple capture operations can be enabled at the same time. Figure 28-16 shows four capture events for one capture channel. Figure 28-16.Input Capture Timing events MAX COUNT ZERO Capture 0 Capture 1 Capture 2 Capture 3 For input capture, the buffer register and the corresponding CCx act like a FIFO. When CCx is empty or read, any content in CCBx is transfered to CCx. The buffer valid flag is passed to set the CCx interrupt flag (IF) and generate the optional interrupt, event or DMA request. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 624 Figure 28-17.Capture Double Buffering "capture" COUNT BV EN CCBx IF EN CCx "INT/DMA request" data read When the Capture x (MCx) bit and the buffer valid flag are set and a new capture event is detected, there is nowhere to store the new timestamp. In that case the Error bit in the Interrupt Flag Status and Clear register (INTFLAG.ERR) is set. Period and Pulse-Width Capture Action The TCC can perform two input captures and restart the counter on one of the edges. This enables the TCC to measure the pulse-width and period. This can be used to characterize an input signal in frequency and duty cycle: 1 f = --T tp dutyCycle = ----T When using PPW (Period, Pulse-width) event action, period (TOP) will be captured into CC0 and pulse-width (tp) into CC1. In PWP (Pulse-width, Period) event action, pulse-width (tp) will be captured into CC0 and period (TOP) into CC1. Figure 28-18.PWP Capture Period (T) external signal /event Pulsewitdh (tp) capture times MAX "capture" COUNT ZERO CC0 CC1 CC0 CC1 Selecting PWP or PPW in the Event Action bit group in the Event Control register (EVCTRL.EVACT1) enables the TCC to perform two capture actions, one on the rising edge and one on the falling edge. The Timer/Counter Inverted Event 1 Input Enable bit in Event Control register (EVCTRL.TCEINV1) is used to select which event input edge the counter restarts operation. The event source to be captured must be an asynchronous event. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 625 For a period and width of the pulse of input signal in frequency and duty cycle, enable capture on CC0 and CC1 channels by writing a one to the Capture Channel x Enable bit in the Control A register (CTRLA.CPTENx). When only one of these measurements is required, the second channel can be used for other purposes. The TCC can detect capture overflow of the input capture channels. Capture overflow occurs when the Capture Interrupt Flag is set and a new capture event is detected, there is nowhere to store the new timestamp. In that case INTFLAG.ERR is set. Note: In dual-slope PWM operation, when TOP is lower than MAX/2 the CCx MSB captures the CTRLB.DIR state to identify the ramp (rising if CCx[MSB] is zero, or falling if CCx[MSB] is one) on which the Counter capture has been done. 28.6.3 Additional Features 28.6.3.1 One-Shot Operation When one-shot is enabled, the counter automatically stops on the next counter overflow or underflow condition. When the counter is stopped, STATUS.STOP is set and the waveform outputs are set to the value defined by the NonRecoverable State x Output Enable (NREx) and Non-Recoverable State x Output Value (NRVx) bits in the Drive Control register (DRVCTRL.NREx and DRVCTRL.NRVx). One-shot operation can be enabled by writing a one to the One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT) and disabled by writing a one to the One-Shot bit in the Control B Clear register (CTRLBCLR.ONESHOT). When enabled, the TCC will count until an overflow or underflow occurs and stop counting. The one-shot operation can be restarted by using retrigger software command, a retrigger event or a start event. When the counter restarts its operation, the Stop bit in the Status register (STATUS.STOP) is cleared. 28.6.3.2 Circular Buffer The Period register (PER) and the compare channels register (CC0 to CC3) support circular buffer operation. When circular buffer operation is enabled, at each update condition, the (PER) or CCx values are copied into the corresponding buffer registers. Circular buffer are dedicated to RAMP2, RAMP2A, and DSBOTH operations. Figure 28-19.Circular Buffer on Channel 0 "write enable" BV UPDATE "data write" EN CCB0 EN CC0 UPDATE CIRCC0EN COUNT = "match" 28.6.3.3 Dithering Operation The TCC supports dithering on Pulse-width or Period on a 16, 32 or 64 PWM cycles frame. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 626 Dithering consists in adding some extra clocks cycles in a frame of several PWM cycles, improving the accuracy of the average output pulses width or period. The extra clock cycles are added on some of the compare match signals, one at a time, through a "blue noise" process that minimizes the flickering on the resulting dither patterns. Dithering makes possible to improve the accuracy of the average output pulse width or period. Dithering is enabled by writing the corresponding configuration in the Enhanced Resolution bits in CTRLA register (CTRLA.RESOLUTION): z DITH4 enable dithering every 16 PWM frames z DITH5 enable dithering every 32 PWM frames z DITH6 enable dithering every 64 PWM frames The DITHERCY bits of COUNT, PER and CCx define the number of extra cycles to add into the frame (DITHERCY bits from the respective COUNT, PER or CCx registers). The remaining bits of COUNT, PER, CCx define the compare value itself. The pseudo code, giving the extra cycles insertion regarding the cycle is: int extra_cycle(resolution, dithercy, cycle){ int MASK; int value switch (resolution){ DITH4: MASK = 0x0f; DITH5: MASK = 0x1f; DITH6: MASK = 0x3f; } value = cycle * dithercy; if (((MASK & value) + dithercy) > MASK) return 1; return 0; } 1.7.3.3.1: Dithering on Period Writing DITHERCY in PER will lead to an average PWM period configured by the following formula: If DITH4 mode is enabled, the last 4 significant bits from PER/CCx or COUNT register corresponds to the DITHERCY value, Rest of the bits corresponds to PER/CCx or COUNT value. The PWM resolution can be calculated using the following formulas. DITH4 mode: DITHERCY PwmPeriod = ------------------------------- + PER 16 DITH5 mode: DITHERCY PwmPeriod = ------------------------------- + PER 32 DITH6 mode: DITHERCY PwmPeriod = ------------------------------- + PER 64 1.7.3.3.2: Dithering on Pulse Width Writing DITHERCY in CCx will lead to an average PWM pulse width configured by the following formula: DITH4 mode: DITHERCY PwmPulseWidth = ------------------------------- + CCx 16 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 627 DITH5 mode: DITHERCY PwmPulseWidth = ------------------------------- + CCx 32 DITH6 mode: DITHERCY PwmPulseWidth = ------------------------------- + CCx 64 28.6.3.4 Ramp Operations Three ramp operations are supported and all require the timer/counter running in single-slope PWM generation. RAMP1 Operation This is the default PWM operation, described in "Single-Slope PWM Generation" on page 618. RAMP2 Operation These operations are dedicated for PFC, Half-Brige and Push-Pull SMPS topologies, where two consecutive timer/counter cycles are interleaved, as shown in Figure 28-20. In cycle A, odd channels output are disabled, and in cycle B, even channels output are disabled. The ramp index changes after each update, but can be software modified using the the Ramp index command bits in Control B Set register (CTRLBSET.IDXCMD). Standard RAMP2 (RAMP2) Operation Ramp A and B periods are controlled through PER register value. Period register value can have different values on each ramp by enabling the circular buffer option (CIPEREN). This mode allows use of a two channels TCC to generate two output signals, or one output signal with another CC channel enabled in capture mode. Figure 28-20.RAMP2 Standard Operation Ramp A B A TOP(B) TOP(A) CC0 Retrigger on FaultA "clear" update "match" TOP(B) CIPEREN = 1 CC1 CC1 COUNT B CC0 ZERO WO[0] WO[1] POL0 = 1 Keep on FaultB POL1 = 1 FaultA input FaultB input Alternate RAMP2 (RAMP2A) Operation Alternate RAMP2 operation is similar to RAMP2 with the difference that CC0 controls both WO[0]/WO[1] waveforms when the corresponding circular buffer option is enabled. The waveform polarity is the same on both outputs, and the channel 1 can be used in capture mode. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 628 Figure 28-21.RAMP2 Alternate Operation Ramp A B A TOP(B) TOP(A) B Retrigger on FaultA CC0(B) COUNT CC0(A) "clear" update "match" TOP(B) CIPEREN = 1 CC0(B) CICCEN0 = 1 CC0(A) ZERO WO[0] WO[1] Keep on FaultB POL0 = 1 FaultA input FaultB input 28.6.3.5 Recoverable Faults Recoverable faults can restart or halt the timer/counter. Two faults, called Fault A and Fault B, can trigger recoverable fault actions on compare channels CC0 and CC1 from the timer/counter. The compare channels outputs can be clamped to inactive state as long as the fault condition is present, or from the first valid fault condition detection and until the end of the timer/counter cycle. Fault Inputs The first two channel input events (MC0 and TCCxMC1) can be used as Fault A and Fault B inputs respectively. Event system channel connected to these fault inputs must be configured as asynchronous. In two ramp (RAMP2, RAMP2A) operation. Fault Filtering Three filtering types are available. The recoverable faults can use all three filters independently or various filter combinations. z Input filtering: By default, the event detection is asynchronous. When the event occurs, the fault system will immediately and asynchronously performs the selected fault action on the compare channel output, including system power modes where the clock is not available. To avoid false fault detection on external events (e.g. a glitch on I/O port) a digital filter can be enabled and set in FILTERVAL bits in the corresponding recoverable Fault Control n register (FCTRLn.FILTERVAL). In this case, the event will be delayed by the FILTERVAL value clock cycles. If the event width is less than the FILTERVAL, then the event will be discarded. z Fault blanking: Provides a way to disable fault input just after a selected waveform output edge to prevent false fault triggering because of signal bouncing on fault signal, as shown in Figure 28-22. Blanking can be enabled by writing the edge triggering configuration to the Faultn Blanking Mode bits in the Recoverable FaultnConfiguration register (FCTRLn.BLANK), and the number of clock cycles to blank is written to the Faultn Blanking Time bits in the Recoverable Faultn Configuration register (FCTRLn.BLANKVAL). The maximum blanking time is: 256 / (96 x106) = 2.66us for 96MHz peripheral clock frequency (GCLK_TCCx) 256 / (1x106) = 256us for 1MHz peripheral clock frequency (GCLK_TCCx) Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 629 Figure 28-22.Fault Blanking in RAMP1 Operation with Inverted Polarity "clear" update "match" TOP 9 "Fault input enabled" - "Fault input disabled" CC0 x "Fault discarded" COUNT ZERO CMP0 FCTRLA.BLANKVAL = 0 FCTRLA.BLANKVAL > 0 FaultA Blanking FCTRLA.BLANKVAL > 0 - 9 - 9 x 9 xxx FaultA Input WO[0] z Fault Qualification can be enabled using Faultn Qualification bit in Recoverable Faultn Configuration register (FCTRLn.QUAL). When the recoverable fault qualification is enabled (FCTRLn.QUAL), the fault input is disabled all the time the corresponding channel output has an inactive level, as shown in Figure 2823. Figure 28-23.Fault Qualification in RAMP1 Operation MAX "clear" update TOP "match" COUNT CC0 9 "Fault input enabled" CC1 - "Fault input disabled" x "Fault discarded" ZERO Fault A Input Qual - - 9 - 9 - 9 - 9 x x x 9 x x x x x x Fault Input A Fault B Input Qual - - 9 x x x 9 x x x x x 9 - - 9 x x x x x x x 9 - x x x x Fault Input B Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 630 Figure 28-24.Fault Qualification in RAMP2 Operation with Inverted Polarity A Cycle B A B "clear" update MAX "match" TOP 9 "Fault input enabled" CC0 COUNT - "Fault input disabled" x CC1 "Fault discarded" ZERO Fault A Input Qual - - 9 x x - 9 x x x x x 9 x x x x x Fault Input A - Fault B Input Qual x x x x - 9 x x x x - 9 x x x x x x x Fault Input B Fault Actions Different fault actions can be configured individually for Fault A and Fault B. Most fault actions are not mutually exclusive; hence two or more actions can be enabled at the same time to achieve a result that is a combination of fault actions. z Keep action can be enabled using Faultn Keeper bit in Recoverable Faultn Configuration register (FCTRLn.KEEP). When the keep action (FCTRLn.KEEP) is enabled, the corresponding channel output will be clamped to zero when the fault condition is present. The clamp will be released on the start of the first cycle after the fault condition is no longer present, as shown in Figure 28-25. Figure 28-25.Waveform Generation with Fault Qualification and Keep Action MAX "clear" update TOP "match" 9 "Fault input enabled" CC0 COUNT - "Fault input disabled" x "Fault discarded" ZERO Fault A Input Qual - 9 - 9 - - 9 x - 9 x x 9 x Fault Input A WO[0] z KEEP KEEP Restart action can be enabled using Faultn Restart bit in Recoverable Faultn Configuration register (FCTRLn.RESTART). When the restart action (FCTRLn.RESTART) is enabled, the timer/counter will be restarted when the corresponding fault condition is present. The ongoing cycle is stopped and the timer/counter starts a new cycle, as shown in Figure 28-26. When the new cycle starts, the compare outputs will be clamped to inactive level as long as the fault condition is present. Note that in RAMP2 operation, when a new timer/counter cycle starts, the cycle index will change automatically, as shown in Figure 28-27. Fault A and Fault B are qualified only during the cycle A and cycle B respectively, i.e. the faultA and faultB is disabled during cycle B or cycle A respectively. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 631 Figure 28-26.Waveform Generation in RAMP1 Mode with Restart Action MAX "clear" update "match" TOP CC0 COUNT CC1 ZERO Restart Restart Fault Input A WO[0] WO[1] Figure 28-27.Waveform Generation in RAMP2 Mode with Restart Action Cycle A B Period (T) CCx=ZERO A B CCx=TOP "clear" update "match" MAX TOP COUNT CC0/CC1 ZERO No fault A action in cycle B Restart Fault Input A WO[0] WO[1] z Capture action: Several capture actions can be selected using Faultn Capture Action bits in Faultn Control register (FCTRLn.CAPTURE). When one of the capture operations (FCTRLn.CAPTURE) is selected, the counter value is captured when the fault occurs. Several capture operations are available: z CAPT is equivalent to a standard capture operation, for further details refer to "Capture Operations" on page 624 z CAPTMIN allows to get the minimum time stamped value, with notification through event or interrupt on each new local minimum captured value detection. z CAPTMAX allows to get the maximum time stamped value, with notification through event or IT on each new local maximum captured value, as shown in Figure 28-28. z LOCMIN notifies through event or IT a local minimum captured value is detected. z LOCMAX notifies through event or IT a local maximum captured value is detected. z DERIV0 notifies through event or IT when a local extremum captured value is detected, as shown in Figure 28-29. In CAPT mode, on each filtered faultn, dedicated CCx channel capture counter value and an interrupt is generated. In other mode interrupt is only generated on a extremum captured value. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 632 In CAPT operation, capture is performed on each capture event. MCx interrupt flag is set on each new capture. In CAPTMIN and CAPTMAX operation, capture is performed only when a new lower (for CAPTMIN) and new higher (for CAPTMAX) value is detected. MCx interrupt flag is set on each new capture. In LOCMIN and LOCMAX operation, capture is performed on each capture event. MCx interrupt flag is set only when the captured value is lower (for LOCMIN) and higher (for LOCMAX) values respectively than the previous captured value. DERIV0 is equivalent to a OR function of (LOCMIN, LOCMAX). In CAPTMIN and CAPTMAX operation CCx keeps the extremum values respectively, as show in Figure 28-28, while in LOCMIN, LOCMAX or DERIV0 operations, CCx follow the counter value at fault time, as show in Figure 28-29. Figure 28-28.Capture Action "CAPTMAX" TOP COUNT CC0 "clear" update "match" ZERO FaultA Input CC0 Event/ Interrupt Figure 28-29.Capture Action "DERIV0" TOP COUNT CC0 "update" "match" ZERO FaultA Input CC0 Event/ Interrupt z Hardware halt action can be configured using Faultn Halt mode bits in Recoverable Faultn configuration register (FCTRLn.HALT = HW). When hardware halt action is enabled (FCTRLn.HALT = HW), the timer/counter is halted and the cycle is extended as long as the corresponding fault is present. Figure 28-30 shows an example where restart and hardware halt actions are enabled for Fault A. The compare channel 0 output is clamped to inactive level as long as the timer/counter is halted. The timer/counter resumes the counting operation as soon as the fault condition is no longer present. If the restart action is enabled, the timer/counter is halted as long as the fault condition is present and restarted when the fault condition is no longer present, as shown in Figure 28-31. Note that in RAMP2 and RAMP2A operations, when a new timer/counter cycle starts, the cycle index will automatically change. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 633 Figure 28-30.Waveform Generation with Halt and Restart Actions MAX "clear" update "match" TOP COUNT CC0 HALT ZERO Restart Restart Fault Input A WO[0] Figure 28-31.Waveform Generation with Fault Qualification, Halt and Restart Actions MAX "update" "match" TOP COUNT CC0 HALT ZERO Resume Fault A Input Qual - 9 - 9 - - 9 x 9 x - x Fault Input A WO[0] z KEEP The software halt action can be configured using Faultn Halt mode bits in Recoverable Faultn configuration register (FCTRLn.HALT = SWHALT). Software halt action is similar to hardware halt action with one exception. To restart the timer/counter, the corresponding fault condition should no longer be present and the corresponding FAULTn bit in STATUS register must be cleared. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 634 Figure 28-32.Waveform Generation with Software Halt, Fault Qualification, Keep and Restart Actions MAX "update" "match" TOP COUNT CC0 HALT ZERO Restart Fault A Input Qual - 9 - 9 Restart 9 - 9 x 9 - x Fault Input A Software Clear WO[0] KEEP NO KEEP 28.6.3.6 Non Recoverable Faults The non-recoverable fault action will force all the compare outputs to a pre-defined level programmed into the Driver Control register (DRVCTRL.NRE and DRVCTRL.NRV). The non recoverable fault input (EV0 and EV1) actions are enabled in Event Control register (EVCTRL.EVACT0 and EVCTRL.EVACT1). To avoid false fault detection on external events (e.g. a glitch on an I/O port) a digital filter can be enabled using Non-Recoverable Fault Input x Filter Value bits in the Driver Control register (DRVCTRL.FILTERVALn). In this case, the event detection is synchronous, and event action is delayed by the selected digital filter value clock cycles. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 635 28.6.3.7 Waveform Extension Figure 28-33 shows a schematic diagram of action of the four optional units following the recoverable fault stage, on a port pin pair. The DTI and SWAP units can be seen as a four port pair slices: z Slice 0 DTI0 / SWAP0 acting on port pins (WO[0], WO[WO_NUM/2 +0]) z Slice 1 DTI1 / SWAP1 acting on port pins (WO[1], WO[WO_NUM/2 +1]) And more generally: z Slice n DTIx / SWAPx acting on port pins (WO[x], WO[WO_NUM/2 +x]) Figure 28-33.Waveform Extension Stage Details WEX OTMX DTI PORTS SWAP OTMX[x+WO_NUM/2] PATTERN PGV[x+WO_NUM/2] P[x+WO_NUM/2] LS OTMX DTIx PGO[x+WO_NUM/2] DTIxEN INV[x+WO_NUM/2] SWAPx PGO[x] HS INV[x] P[x] OTMX[x] PGV[x] The output matrix (OTMX) unit distributes compare channels, according to the selectable configurations, as shown in Table 28-3. Table 28-3. Output Matrix Channel Pin Routing Configuration Value OTMX[x] 0x0 CC3 CC2 CC1 CC0 CC3 CC2 CC1 CC0 0x1 CC1 CC0 CC1 CC0 CC1 CC0 CC1 CC0 0x2 CC0 CC0 CC0 CC0 CC0 CC0 CC0 CC0 0x3 CC1 CC1 CC1 CC1 CC1 CC1 CC1 CC0 z Configuration 0x0 is default configuration. The channel location is the default one and channels are distributed on outputs modulo the number of channels. Channel 0 is routed to the Output matrix output OTMX[0], Channel 1 to OTMX[1]. If there are more outputs than channels, then channel 0 is duplicated to the Output matrix output OTMX[CC_NUM], channel 1 to OTMX[CC_NUM+1] and so on. z Configuration 0x1 distributes the channels on output modulo half the number of channels, this gives the lower channels twice the number of output locations than the default configuration. This provides for example, control of the four transistors of a full bridge using only two compare channels. Using pattern generation, some of these four outputs can be overwritten by a constant level, enabling flexible drive of a full bridge in all quadrant configurations. z Configuration 0x2 distributes the compare channel 0 (CC0) to all port pins. With pattern generation, this configuration can control a stepper motor. z Configuration 0x3 distributes the compare channel CC0 to first output and the channel CC1 to all other outputs. Together with pattern generation and the fault extension this configuration can control up to seven LED strings, with a boost stage. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 636 An example of 4 compare channels on 4 outputs:. Value OTMX[3] OTMX[2] OTMX[1] OTMX[0] 0x0 CC3 CC2 CC1 CC0 0x1 CC1 CC0 CC1 CC0 0x2 CC0 CC0 CC0 CC0 0x3 CC1 CC1 CC1 CC0 The dead-time insertion (DTI) unit generates OFF time with the non-inverted low side (LS) and inverted high side (HS) of the WG output forced at low level. This OFF time is called dead time, and dead-time insertion ensures that the LS and HS will never switch simultaneously. The DTI stage consists of four equal dead-time insertion generators; one for each of the first four compare channels. Figure 28-34 shows the block diagram of one DTI generator. The four channels have a common register which controls the dead time and is independent of high side and low side setting. Figure 28-34.Dead-Time Generator Block Diagram DTHS DTLS Dead Time Generator LOAD EN Counter =0 OTMX output D "DTLS" Q (To PORT) Edge Detect "DTHS" (To PORT) As shown in Figure 28-34, the 8-bit dead-time counter is decremented by one for each peripheral clock cycle, until it reaches zero. A nonzero counter value will force both the low side and high side outputs into their OFF state. When the output matrix (OTMX) output changes, the dead-time counter is reloaded according to the edge of the input. When the output changes from low to high (positive edge) it initiates counter reload of the DTLS register, and when the output changes from high to low (negative edge) reload the DTHS register. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 637 Figure 28-35.Dead-Time Generator Timing Diagram "dti_cnt" T tP tDTILS t DTIHS "OTMX output" "DTLS" "DTHS" The pattern generator unit produces a synchronized bit pattern across the port pins it is connected to. The pattern generation features are primarily intended for handling the commutation sequence in brushless DC motor (BLDC), stepper motor and full bridge control. A block diagram of the pattern generator is shown in Figure 28-36. Figure 28-36.Pattern Generator Block Diagram COUNT UPDATE BV PGEB[7:0] EN PGE[7:0] BV PGVB[7:0] EN SWAP output PGV[7:0] WOx[7:0] As with other double buffered timer/counter registers, the register update is synchronized to the UPDATE condition set by the timer/counter waveform generation operation. If the synchronization is not required by the application, the software can simply access directly the PATT.PGE, PATT.PGV bits registers. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 638 28.6.4 DMA, Interrupts and Events Table 28-4. Module request for TCC Interrupt request Condition Overflow / Underflow Event output X Event input (1) X Channel Compare Match or Capture X Retrigger X X Count X X Capture Overflow Error X Synchronization Ready X Debug Fault State X Recoverable Faults X Non-Recoverable Faults X X X DMA request is cleared Cleared when PER/PERB, CCx/CCBx, PATT/PATTB or WAVE/WAVEB register is written. For compare channel: Cleared when CCBx register is written. X(2) X For capture channel: Cleared when CCx register is read. TCCx Event 0 input X(3) TCCx Event 1 input X(4) Notes: 1. DMA request DMA request set on overflow, underflow or retrigger conditions. 2. Can perform capture or generate recoverable fault on an event input. 3. Can retrigger counter / control counter direction / stop the counter / decrement the counter / perform period and pulse width capture / generate non-recoverable fault on an event input. 4. Can retrigger counter / increment or decrement counter depending on direction / start the counter / increment or decrement counter based on direction / increment counter regardless of direction / generate nonrecoverable fault on an event input. 28.6.4.1 DMA Operation The TCC generates the following DMA requests: z Overflow (OVF): the request is set when an update condition (overflow, underflow or re-trigger) is detected. z Compare Match or Capture (MCx): for a compare channel, the request is set on each compare match detection. For a capture channel, the request is set when valid data is present in CCx register, and cleared when CCx register is read. 28.6.4.2 Interrupts The TCC has the following interrupt sources: z Overflow/Underflow: OVF. This is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. z Retrigger: TRG. This is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 639 z Count: CNT. This is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. For further details, refer to EVCTRL.CNTSEL description. z Capture Overflow Error: ERR. This is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. z Debug Fault State: DFS. This is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. z Recoverable Faults: FAULTn. This is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. z Non-recoverable Faults: FAULTx. This is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. z Compare Match or Capture Channel: MCx. This is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the TCC is reset. See the INTFLAG for details on how to clear interrupt flags. The TCC has one common interrupt request line for all the interrupt sources. Refer to "Processor And Architecture" on page 28 for details. The user must read the INTFLAG register to determine which interrupt condition is present. Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to "Processor And Architecture" on page 28 for details. 28.6.4.3 Events The TCC can generate the following output events: z Overflow/Underflow: OVF z Trigger: TRG z Counter: CNT. For further details, refer to EVCTRL.CNTSEL description. z Compare Match or Capture on compare/capture channels: MCx Writing a one to an Event Output bit in the Event Control Register (EVCTRL.xxEO) enables the corresponding output event. Writing a zero to this bit disables the corresponding output event. Refer to "EVSYS - Event System" on page 400 for details on configuring the event system. The TCC can take the following actions on a channel input event (MCx): z Capture event z Generate a recoverable fault The TCC can take the following actions on counter event 1 (TCCx EV1): z Counter retrigger z Counter direction control z Stop the counter z Decrement the counter on event z Period and pulse width capture z Non-recoverable fault The TCC can take the following actions on counter event 0 (TCCx EV0): z Counter retrigger z Count on event (increment or decrement, depending on counter direction) z Counter start. Start counting on the event rising edge. Further events will not restart the counter; it keeps on counting using prescaled GCLK_TCCx, until it reaches TOP or Zero depending on the direction. z Counter increment on event. This will increment the counter irrespective of the counter direction. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 640 z Count during active state of an asynchronous event (increment or decrement, depending on counter direction). In this case, the counter will be incremented or decremented on each cycle of the prescaled clock, as long as the event is active. z Non-recoverable fault The counter Event Actions are available in Event Control register (EVCTRL.EVACT0 and EVCTRL.EVACT1). For further details, refer to EVCTRL register description. Writing a one to an Event Input bit in the Event Control register (EVCTRL.MCEIx or EVCTRL.TCEIx) enables the corresponding action on input event. Writing a zero to this bit disables the corresponding action on input event. Note that if several events are connected to the TCC, the enabled action will apply for each the incoming event. Refer to "EVSYS - Event System" on page 400 for details on how to configure the event system. 28.6.5 Sleep Mode Operation The TCC can be configured to operate in any sleep mode. To be able to run in standby the RUNSTDBY bit (CTRLA.RUNSTDBY) must be written to one. The TCC can wake up the device using interrupts from any sleep mode or performs internal actions through the event system. 28.6.6 Synchronization Due to the asynchronicity between CLK_TCCx_APB and GCLK_TCCx some registers must be synchronized when accessed. A register can require: z Synchronization when written z Synchronization when read z Synchronization when written and read z No synchronization When a register requiring synchronization is accessed, the corresponding synchronization bit is set in Synchronization Busy register (SYNCBUSY) and cleared when the synchronization is complete. An access to a register with synchronization busy bit set, will trigger an hardware interrupt. The following bits need synchronization when written: z Software Reset and Enable bits in Control A register (CTRLA.SWRST and CTRLA.ENABLE) Write-synchronization is denoted by the Write-Synchronized property in the register description. The following registers require synchronization when written: z Control B Clear and Control B Set registers (CTRLBCLR and CTRLBSET) z Status register (STATUS) z Pattern and Pattern Buffer registers (PATT and PATTB) z Waveform and Waveform Buffer registers (WAVE and WAVEB) z Count Value register (COUNT) z Period Value and Period Buffer Value registers (PER and PERB) z Compare/Capture Value and Compare/Capture Buffer Value registers (CCx and CCBx) Write-synchronization is denoted by the Write-Synchronized property in the register description. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 641 28.7 Register Summary Table 28-5. Register Summary Offset Name 0x00 0x01 0x02 Bit Pos. 7:0 CTRLA 0x03 RESOLUTION[1:0] 15:8 ALOCK ENABLE PRESCSYNC[1:0] RUNSTDBY SWRST PRESCALER[2:0] 23:16 31:24 CPTEN3 CPTEN2 CPTEN1 CPTEN0 0x04 CTRLBCLR 7:0 CMD[2:0] IDXCMD[1:0] ONESHOT LUPD DIR 0x05 CTRLBSET 7:0 CMD[2:0] IDXCMD[1:0] ONESHOT LUPD DIR 0x06 Reserved 0x07 Reserved STATUS CTRLB ENABLE SWRST CC3 CC2 CC1 CC0 CCB1 CCB0 PERB WAVEB PATTB QUAL KEEP 0x08 7:0 0x09 15:8 0x0A SYNCBUSY 0x0B 23:16 7:0 0x0D 15:8 FCTRLA 31:24 0x10 7:0 0x11 CCB3 PATT CCB2 FCTRLB 0x13 RESTART BLANK[1:0] COUNT CAPTURE[2:0] 23:16 0x0F 0x12 WAVE 31:24 0x0C 0x0E PER FILTERVAL[3:0] RESTART BLANK[1:0] 15:8 QUAL KEEP CAPTURE[2:0] 7:0 15:8 WEXCTRL SRC[1:0] CHSEL[1:0] HALT[1:0] BLANKVAL[7:0] 31:24 0x14 HALT[1:0] BLANKVAL[7:0] 23:16 0x15 SRC[1:0] CHSEL[1:0] FILTERVAL[3:0] OTMX[1:0] DTIEN3 0x16 23:16 DTLS[7:0] 0x17 31:24 DTHS[7:0] DTIEN2 DTIEN1 DTIEN0 0x18 7:0 NRE7 NRE6 NRE5 NRE4 NRE3 NRE2 NRE1 NRE0 0x19 15:8 NRV7 NRV6 NRV5 NRV4 NRV3 NRV2 NRV1 NRV0 23:16 INVEN7 INVEN6 INVEN5 INVEN4 INVEN3 INVEN2 INVEN1 INVEN0 0x1A DRVCTRL 0x1B 31:24 0x1C Reserved 0x1D Reserved 0x1E DBGCTRL 0x1F Reserved 0x20 15:8 EVCTRL 0x23 TCEI1 TCEI0 EVACT1[2:0] TCINV1 EVACT0[2:0] TCINV0 CNTEO TRGEO OVFEO MCEI2 MCEI1 MCEI0 31:24 MCEO3 MCEO2 MCEO1 MCEO0 ERR CNT TRG OVF MC2 MC1 MC0 7:0 15:8 0x27 CNTSEL[1:0] DBGRUN MCEI3 0x24 INTENCLR FDDBD 23:16 0x25 0x26 FILTERVAL0[3:0] 7:0 7:0 0x21 0x22 FILTERVAL1[3:0] 23:16 FAULT1 FAULT0 FAULTB FAULTA DFS MC3 31:24 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 642 Offset Name 0x28 0x29 0x2A Bit Pos. 7:0 INTENSET 0x2B 15:8 FAULT1 FAULT0 FAULTB CNT TRG OVF MC3 MC2 MC1 MC0 ERR CNT TRG OVF MC2 MC1 MC0 FAULTA DFS 23:16 31:24 0x2C 7:0 0x2D 15:8 0x2E ERR INTFLAG 0x2F FAULT1 FAULT0 FAULTB FAULTA DFS 23:16 MC3 31:24 0x30 7:0 PERBV WAVEBV PATTBV SLAVE DFS IDX STOP 0x31 15:8 FAULT1 FAULT0 FAULTB FAULTA FAULT1IN FAULT0IN FAULTBIN FAULTAIN 23:16 CCBV3 CCBV2 CCBV1 CCBV0 31:24 CMP3 CMP2 CMP1 CMP0 0x32 STATUS 0x33 0x34 7:0 COUNT[7:0] 0x35 15:8 COUNT[15:8] 23:16 COUNT[23:16] 0x36 COUNT 0x37 0x38 0x39 31:24 PATT 0x3A Reserved 0x3B Reserved 0x3C 0x3D 0x3E WAVE 0x3F 7:0 PGE7 PGE6 PGE5 PGE4 PGE3 PGE2 PGE1 PGE0 15:8 PGV7 PGV6 PGV5 PGV4 PGV3 PGV2 PGV1 PGV0 7:0 CIPEREN 15:8 RAMP[1:0] WAVEGEN[2:0] CICCEN3 POL3 POL2 POL1 POL0 SWAP3 SWAP2 SWAP1 SWAP0 7:0 PER[7:0] 15:8 PER[15:8] 23:16 PER[23:16] 0x43 31:24 0x44 7:0 CC[7:0] 0x45 15:8 CC[15:8] 23:16 CC[23:16] 0x46 CC0 0x47 31:24 0x48 7:0 CC[7:0] 0x49 15:8 CC[15:8] 23:16 CC[23:16] 0x4A CC1 0x4B 31:24 0x4C 7:0 CC[7:0] 0x4D 15:8 CC[15:8] 23:16 CC[23:16] 0x4E CC2 0x4F 31:24 0x50 7:0 CC[7:0] 0x51 15:8 CC[15:8] 23:16 CC[23:16] 0x52 0x53 CICCEN0 31:24 0x41 PER CICCEN1 23:16 0x40 0x42 CICCEN2 CC3 31:24 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 643 Offset Name 0x54 ... 0x63 Reserved 0x64 Bit Pos. 7:0 PGEB7 PGEB6 PGEB5 PGEB4 PGEB3 PGEB2 PGEB1 PGEB0 15:8 PGVB7 PGVB6 PGVB5 PGVB4 PGVB3 PGVB2 PGVB1 PGVB0 0x68 7:0 CIPERENB 0x69 15:8 CICCENB3 CICCENB2 CICCENB1 CICCENB0 23:16 POLB3 POLB2 POLB1 POLB0 SWAPB3 SWAPB2 SWAPB1 SWAPB0 0x65 PATTB 0x66 Reserved 0x67 Reserved 0x6A WAVEB 0x6B 31:24 0x6C 7:0 0x6D 0x6E PERB PERB[15:8] PERB[23:16] 31:24 7:0 CCB0 15:8 CCB[15:8] CCB[23:16] 0x73 31:24 7:0 0x76 CCB1 15:8 CCB[15:8] CCB[23:16] 0x77 31:24 7:0 0x79 CCB2 15:8 CCB[15:8] CCB[23:16] 0x7B 31:24 7:0 0x7E 0x7F CCB3 CCB[7:0] 23:16 0x7C 0x7D CCB[7:0] 23:16 0x78 0x7A CCB[7:0] 23:16 0x74 0x75 PERB[7:0] 15:8 0x70 0x72 WAVEGENB[2:0] 23:16 0x6F 0x71 RAMPB[1:0] CCB[7:0] 15:8 CCB[15:8] 23:16 CCB[23:16] 31:24 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 644 28.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protected property in each individual register description. Refer to the "Register Access Protection" on page 611 and the PAC chapter for details. Some registers require synchronization when read and/or written. Synchronization is denoted by the Write-Synchronized or Read-Synchronized property in each individual register description. Refer to the "Synchronization" on page 641 for details. Some registers are enable-protected, meaning they can only be written when the TCC is disabled. Enable-protection is denoted by the Enable-Protected property in each individual register description. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 645 28.8.1 Control A Name: CTRLA Offset: 0x00 Reset: 0x00000000 Property: Enable-Protected, Write-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 CPTEN3 CPTEN2 CPTEN1 CPTEN0 Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 ALOCK PRESCSYNC[1:0] RUNSTDBY PRESCALER[2:0] Access R R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ENABLE SWRST RESOLUTION[1:0] Access R R/W R/W R R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 31:28 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 27:24 - CPTENx [x=3..0]: Capture Channel x Enable These bits are used to select the capture or compare operation on channel x. The number of available channels depend on the TCC instance. Writing a one to CAPTENx enables capture on channel x. Writing a zero to CAPTENx disables capture on channel x. These bits are not synchronized. z Bits 23:15 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 14 - ALOCK: Auto Lock When this bit is set, Lock Update (LUPD) is set to one on each overflow/underflow or re-trigger event. 0: The LUPD bit is not affected on overflow/underflow, and re-trigger event. 1: The LUPD bit is set on each overflow/underflow or re-trigger event. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 646 This bit is not synchronized. z Bits 13:12 - PRESCSYNC[1:0]: Prescaler and Counter Synchronization Selection These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCCx clock or on the next prescaled GCLK_TCCx clock. It also makes possible to reset the prescaler on retrigger event, as shown in the following table. These bits are not synchronized. Table 28-6. Prescaler and Counter Synchronization Selection PRESCSYNC[1:0] Name 0x0 GCLK 0x1 PRESC 0x2 RESYNC 0x3 z Description Reload or reset counter on next GCLK Reload or reset counter on next prescaler clock Reload or reset counter on next GCLK and reset prescaler counter Reserved Bit 11 - RUNSTDBY: Run in Standby This bit is used to keep the TCC running in standby mode: 0: The TCC is halted in standby. 1: The TCC continues to run in standby. This bit is not synchronized. z Bits 10:8 - PRESCALER[2:0]: Prescaler These bits select the Counter prescaler factor as shown in the following table. These bits are not synchronized. Table 28-7. Prescaler PRESCALER[2:0] Name Description 0x0 DIV1 No division 0x1 DIV2 Divide by 2 0x2 DIV4 Divide by 4 0x3 DIV8 Divide by 8 0x4 DIV16 Divide by 16 0x5 DIV64 Divide by 64 0x6 DIV256 Divide by 256 0x7 DIV1024 Divide by 1024 z Bit 7 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 6:5 - RESOLUTION[1:0]: Enhanced Resolution These bits increase the TCC resolution by enabling the dithering options, according to the following table. These bits are not synchronized. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 647 Table 28-8. Enhanced Resolution RESOLUTION[1:0] Name Description 0x0 NONE Dithering is disabled 0x1 DITH4 Dithering is done every 16 PWM frames 0x2 DITH5 Dithering is done every 32 PWM frames 0x3 DITH6 Dithering is done every 64 PWM frames z Bits 4:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 1 - ENABLE: Enable 0: The peripheral is disabled. 1: The peripheral is enabled. Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the ENABLE bit in the SYNCBUSY register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. z Bit 0 - SWRST: Software Reset 0: There is no reset operation ongoing. 1: The reset operation is ongoing. Writing a zero to this bit has no effect. Writing a one to this bit resets all registers in the TCC, except DBGCTRL, to their initial state, and the TCC will be disabled. Writing a one to CTRLA.SWRST will always take precedence; all other writes in the same write-operation will be discarded. Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 648 28.8.2 Control B Clear This register allows the user to change the below mentioned functionalities without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Set (CTRLBSET) register. Name: CTRLBCLR Offset: 0x04 Reset: 0x00 Property: Read-Synchronized, Write-Protected, Write-Synchronized Bit 7 6 5 4 CMD[2:0] Access Reset z 3 IDXCMD[1:0] 2 1 0 ONESHOT LUPD DIR R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:5 - CMD[2:0]: TCC Command These bits can be used for software control of re-triggering and stop commands of the TCC. When a command has been executed, the CMD bit field will read back zero. The commands are executed on the next prescaled GCLK_TCC clock cycle. Writing a zero to this bit group has no effect. Writing a valid value to these bits will clear the corresponding pending command. Table 28-9. TCC Command CMD[2:0] Name 0x0 NONE 0x1 RETRIGGER 0x2 STOP 0x3 UPDATE 0x4 READSYNC 0x5-0x7 z Description No action Clear start, restart or retrigger Force stop Force update of double buffered registers Force COUNT read synchronization Reserved Bits 4:3 - IDXCMD[1:0]: Ramp Index Command These bits can be used to force cycle A and cycle B changes in RAMP2 and RAMP2A operation, according to the following table. On timer/counter update condition, the command is executed, the IDX flag in STATUS register is updated and the IDXCMD command is cleared. Writing a zero to this field has no effect. Writing a valid value to this field will clear the pending command. Table 28-10. Ramp Index Command IDXCMD[1:0] Name 0x0 DISABLE Description Command disabled: Index toggles between cycles A and B Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 649 z IDXCMD[1:0] Name Description 0x1 SET 0x2 CLEAR Clear index: cycle A will be forced in the next cycle 0x3 HOLD Hold index: the next cycle will be the same as the current cycle Set index: cycle B will be forced in the next cycle Bit 2 - ONESHOT: One-Shot This bit controls one-shot operation of the TCC. When one-shot operation is enabled, the TCC will stop counting on the next overflow/underflow condition or on a stop command. 0: The TCC will update the counter value on overflow/underflow condition and continues operation. 1: The TCC will stop counting on the next underflow/overflow condition. Writing a zero to this bit has no effect Writing a one to this bit will disable the one-shot operation. z Bit 1 - LUPD: Lock Update This bit controls the update operation of the TCC buffered registers. When this bit is set, no update of the buffered registers is performed, even though an UPDATE condition has occurred. Locking the update ensures that all buffers registers are valid before an update is performed. This bit has no effect when input capture operation is enabled. 1: The CCBx, PERB, PGVB, PGEB, and SWAPBx buffer registers value are not copied into the corresponding CCx, PER, PGV, PGE and SWAPx registers. 0: The CCBx, PERB, PGVB, PGEB, and SWAPBx buffer registers value are copied into the corresponding CCx, PER, PGV, PGE and SWAPx registers on counter update condition. z Bit 0 - DIR: Counter Direction This bit is used to change the direction of the counter. 0: The timer/counter is counting up (incrementing). 1: The timer/counter is counting down (decrementing). Writing a zero to this bit has no effect Writing a one to this bit will make the counter count up. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 650 28.8.3 Control B Set This register allows the user to change the below mentioned functionalities without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Clear (CTRLBCLR) register. Name: CTRLBSET Offset: 0x05 Reset: 0x00 Property: Write-Protected, Write-Synchronized Bit 7 6 5 4 CMD[2:0] Access Reset z 3 IDXCMD[1:0] 2 1 0 ONESHOT LUPD DIR R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:5 - CMD[2:0]: TCC Command These bits can be used for software control of re-triggering and stop commands of the TCC. When a command has been executed, the CMD field will be read back as zero. The commands are executed on the next prescaled GCLK_TCC clock cycle. Writing a zero to this bit group has no effect Writing a valid value into this bit group will set the associated command, as shown in the table below. Table 28-11. TCC Command CMD[2:0] Name 0x0 NONE 0x1 RETRIGGER 0x2 STOP 0x3 UPDATE 0x4 READSYNC 0x5-0x7 z Description No action Clear start, restart or retrigger Force stop Force update of double buffered registers Force COUNT read synchronization Reserved Bits 4:3 - IDXCMD[1:0]: Ramp Index Command These bits can be used to force cycle A and cycle B changes in RAMP2 and RAMP2A operation, according to the table below. On timer/counter update condition, the command is executed, the IDX flag in STATUS register is updated and the IDXCMD command is cleared. Writing a zero to this field has no effect. Writing a valid value into this field will set a command. Table 28-12. Ramp Index Command IDXCMD[1:0] Name 0x0 DISABLE Description Command disabled: Index toggles between cycles A and B Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 651 z IDXCMD[1:0] Name Description 0x1 SET 0x2 CLEAR Clear index: cycle A will be forced in the next cycle 0x3 HOLD Hold index: the next cycle will be the same as the current cycle Set index: cycle B will be forced in the next cycle Bit 2 - ONESHOT: One-Shot This bit controls one-shot operation of the TCC. When in one-shot operation, the TCC will stop counting on the next overflow/underflow condition or a stop command. 0: The TCC will count continuously. 1: The TCC will stop counting on the next underflow/overflow condition. Writing a zero to this bit has no effect. Writing a one to this bit will enable the one-shot operation. z Bit 1 - LUPD: Lock Update This bit controls the update operation of the TCC buffered registers. When this bit is set, no update of the buffered registers is performed, even though an UPDATE condition has occurred. Locking the update can be used to ensure that all buffer registers are loaded with the desired values, before an update is performed. After all the buffer registers are loaded correctly, the buffered registers can be unlocked. This bit has no effect when input capture operation is enabled. 1: The CCBx, PERB, PGVB, PGEB, and SWAPBx buffer registers value are not copied into CCx, PER, PGV, PGE and SWAPx registers. 0: The CCBx, PERB, PGVB, PGEB, and SWAPBx buffer registers value are copied into CCx, PER, PGV, PGE and SWAPx registers on timer Overflow/underflow or retrigger condition. z Bit 0 - DIR: Counter Direction This bit is used to change the direction of the counter. 0: The timer/counter is counting up (incrementing). 1: The timer/counter is counting down (decrementing). Writing a zero to this bit has no effect Writing a one to this bit will make the counter count down. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 652 28.8.4 Synchronization Busy Name: SYNCBUSY Offset: 0x08 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 CCB3 CCB2 CCB1 CCB0 PERB WAVEB PATTB Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 CC3 CC2 CC1 CC0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PER WAVE PATT COUNT STATUS CTRLB ENABLE SWRST Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 31:23 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 22:19 - CCBx [x=3..0]: Compare Channel Buffer x Busy This bit is cleared when the synchronization of Compare/Capture Channel x Buffer register between the clock domains is complete. This bit is set when the synchronization of Compare/Capture Channel x Buffer register between clock domains is started. CCBx bit is available only for existing Compare/Capture Channels. For details on CC channels number, refer to each TCC feature list. This bit is set when the synchronization of CCBx register between clock domains is started. z Bit 18 - PERB: Period Buffer Busy This bit is cleared when the synchronization of PERB register between the clock domains is complete. This bit is set when the synchronization of PERB register between clock domains is started. z Bit 17 - WAVEB: Wave Buffer Busy This bit is cleared when the synchronization of WAVEB register between the clock domains is complete. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 653 This bit is set when the synchronization of WAVEB register between clock domains is started. z Bit 16 - PATTB: Pattern Buffer Busy This bit is cleared when the synchronization of PATTB register between the clock domains is complete. This bit is set when the synchronization of PATTB register between clock domains is started. z Bits 15:12 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 11:8 - CCx [x=3..0]: Compare Channel x Busy This bit is cleared when the synchronization of Compare/Capture Channel x register between the clock domains is complete. This bit is set when the synchronization of Compare/Capture Channel x register between clock domains is started. CCx bit is available only for existing Compare/Capture Channels. For details on CC channels number, refer to each TCC feature list. This bit is set when the synchronization of CCx register between clock domains is started. z Bit 7 - PER: Period busy This bit is cleared when the synchronization of PER register between the clock domains is complete. This bit is set when the synchronization of PER register between clock domains is started. z Bit 6 - WAVE: Wave Busy This bit is cleared when the synchronization of WAVE register between the clock domains is complete. This bit is set when the synchronization of WAVE register between clock domains is started. z Bit 5 - PATT: Pattern Busy This bit is cleared when the synchronization of PATT register between the clock domains is complete. This bit is set when the synchronization of PATT register between clock domains is started. z Bit 4 - COUNT: Count Busy This bit is cleared when the synchronization of COUNT register between the clock domains is complete. This bit is set when the synchronization of COUNT register between clock domains is started. z Bit 3 - STATUS: Status Busy This bit is cleared when the synchronization of STATUS register between the clock domains is complete. This bit is set when the synchronization of STATUS register between clock domains is started. z Bit 2 - CTRLB: Ctrlb Busy This bit is cleared when the synchronization of CTRLB register between the clock domains is complete. This bit is set when the synchronization of CTRLB register between clock domains is started. z Bit 1 - ENABLE: Enable Busy This bit is cleared when the synchronization of ENABLE register bit between the clock domains is complete. This bit is set when the synchronization of ENABLE register bit between clock domains is started. z Bit 0 - SWRST: Swrst Busy This bit is cleared when the synchronization of SWRST register bit between the clock domains is complete. This bit is set when the synchronization of SWRST register bit between clock domains is started. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 654 28.8.5 Recoverable Fault A Configuration Name: FCTRLA Offset: 0x0C Reset: 0x00000000 Property: Enable-Protected, Write-Protected Bit 31 30 29 28 27 26 25 24 FILTERVAL[3:0] Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 BLANKVAL[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 CAPTURE[2:0] CHSEL[1:0] HALT[1:0] Access R R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 QUAL KEEP RESTART Access Reset BLANK[1:0] SRC[1:0] R/W R/W R/W R/W R/W R R/W R/W 0 0 0 0 0 0 0 0 z Bits 31:28 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 27:24 - FILTERVAL[3:0]: Fault A Filter Value These bits define the filter value applied on MCEx (x=0,1) event input line. The value must be set to zero when MCEx event is used as synchronous event. z Bits 23:16 - BLANKVAL[7:0]: Fault A Blanking Time These bits are used to ignore potential glitches after selectable waveform edge is detected. The edge selection is available in BLANK bits (FCTRLA.BLANK). When enabled, the fault input source is internally disabled during BLANKVAL* prescaled GCLK_TCC periods after the detection of the waveform edge. z Bit 15 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 14:12 - CAPTURE[2:0]: Fault A Capture Action These bits select the capture and Fault A interrupt/event conditions, as defined in the table below. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 655 Table 28-13. Fault A Capture Action CAPTURE[2:0] Name 0x0 DISABLE 0x1 CAPT Capture on fault 0x2 CAPTMIN Minimum capture 0x3 CAPTMAX Maximum capture 0x4 LOCMIN Minimum local detection 0x5 LOCMAX Maximum local detection 0x6 DERIV0 0x7 z Description No capture Minimum and maximum local detection Reserved Bits 11:10 - CHSEL[1:0]: Fault A Capture Channel These bits select the channel for capture operation triggered by recoverable Fault A, as defined in the table below. Table 28-14. Fault A Capture Channel z CHSEL[1:0] Name Description 0x0 CC0 Capture value stored in channel 0 0x1 CC1 Capture value stored in channel 1 0x2 CC2 Capture value stored in channel 2 0x3 CC3 Capture value stored in channel 3 Bits 9:8 - HALT[1:0]: Fault A Halt Mode These bits select the halt action for recoverable Fault A as defined in the table below. Table 28-15. Fault A Halt Mode z HALT[1:0] Name Description 0x0 DISABLE Halt action disabled 0x1 HW Hardware halt action 0x2 SW Software halt action 0x3 NR Non-recoverable fault Bit 7 - RESTART: Fault A Restart Setting this bit enables restart action for Fault A. 0: Fault A restart action is disabled. 1: Fault A restart action is enabled. z Bits 6:5 - BLANK[1:0]: Fault A Blanking Mode These bits, select the blanking start point for recoverable Fault A as defined in the table below. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 656 Table 28-16. Fault A Blanking Mode z BLANK[1:0] Name Description 0x0 NONE No Blanking applied 0x1 RISE Blanking applied from rising edge of the output waveform 0x2 FALL Blanking applied from falling edge of the output waveform 0x3 BOTH Blanking applied from each toggle of the output waveform Bit 4 - QUAL: Fault A Qualification Setting this bit, enables the recoverable Fault A input qualification. 0: The recoverable Fault A input is not disabled on CMPx value condition. 1: The recoverable Fault A input is disabled when output signal is at inactive level (CMPx == 0). z Bit 3 - KEEP: Fault A Keeper Setting this bit enables the Fault A keep action. 0: The Fault A state is released as soon as the recoverable Fault A is released. 1: The Fault A state is released at the end of TCC cycle. z Bit 2 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 1:0 - SRC[1:0]: Fault A Source These bits select the TCC event input for recoverable Fault A, as defined in the table below. Event system channel connected to MCEx event input, must be configured to route the event asynchronously, when used as a recoverable Fault A input. Table 28-17. Fault A Source SRC[1:0] Name Description 0x0 DISABLE Fault input disabled 0x1 ENABLE MCEx (x=0,1) event input 0x2 INVERT Inverted MCEx (x=0,1) event input 0x3 ALTFAULT Alternate fault (A or B) state at the end of the previous period Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 657 28.8.6 Recoverable Fault B Configuration Name: FCTRLB Offset: 0x10 Reset: 0x00000000 Property: Enable-Protected, Write-Protected Bit 31 30 29 28 27 26 25 24 FILTERVAL[3:0] Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 BLANKVAL[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 CAPTURE[2:0] CHSEL[1:0] HALT[1:0] Access R R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 QUAL KEEP RESTART Access Reset BLANK[1:0] SRC[1:0] R/W R/W R/W R/W R/W R R/W R/W 0 0 0 0 0 0 0 0 z Bits 31:28 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 27:24 - FILTERVAL[3:0]: Fault B Filter Value These bits define the filter value applied on MCEx (x=0,1) event input line. The value must be set to zero when MCEx event is used as synchronous event. z Bits 23:16 - BLANKVAL[7:0]: Fault B Blanking Time These bits are used to ignore potential glitches after selectable waveform edge is detected. The edge selection is available in BLANK bits (FCTRLB.BLANK). When enabled, the fault input source is internally disabled during BLANKVAL* prescaled GCLK_TCC periods after the detection of the edge. z Bit 15 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 14:12 - CAPTURE[2:0]: Fault B Capture Action These bits select the capture and Fault B interrupt/event conditions, as defined in table below. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 658 Table 28-18. Fault B Capture Action CAPTURE[2:0] Name 0x0 DISABLE 0x1 CAPT Capture on fault 0x2 CAPTMIN Minimum capture 0x3 CAPTMAX Maximum capture 0x4 LOCMIN Minimum local detection 0x5 LOCMAX Maximum local detection 0x6 DERIV0 0x7 z Description No capture Minimum and maximum local detection Reserved Bits 11:10 - CHSEL[1:0]: Fault B Capture Channel These bits select the channel for capture operation triggered by recoverable Fault B, as defined in the table below. Table 28-19. Fault B Capture Channel z CHSEL[1:0] Name Description 0x0 CC0 Capture value stored in channel 0 0x1 CC1 Capture value stored in channel 1 0x2 CC2 Capture value stored in channel 2 0x3 CC3 Capture value stored in channel 3 Bits 9:8 - HALT[1:0]: Fault B Halt Mode These bits select the halt action for recoverable Fault B as defined in the table below. Table 28-20. Fault B Halt Mode z HALT[1:0] Name Description 0x0 DISABLE Halt action disabled 0x1 HW Hardware halt action 0x2 SW Software halt action 0x3 NR Non-recoverable fault Bit 7 - RESTART: Fault B Restart Setting this bit enables restart action for Fault B. 0: Fault B restart action is disabled. 1: Fault B restart action is enabled. z Bits 6:5 - BLANK[1:0]: Fault B Blanking Mode These bits, select the blanking start point for recoverable Fault B as defined in the table below. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 659 Table 28-21. Fault B Blanking Mode z BLANK[1:0] Name Description 0x0 NONE No Blanking applied 0x1 RISE Blanking applied from rising edge of the output waveform 0x2 FALL Blanking applied from falling edge of the output waveform 0x3 BOTH Blanking applied from each toggle of the output waveform Bit 4 - QUAL: Fault B Qualification Setting this bit, enables the recoverable Fault B input qualification. 0: The recoverable Fault B input is not disabled on CMPx value condition. 1: The recoverable Fault B input is disabled when output signal is at inactive level (CMPx == 0). z Bit 3 - KEEP: Fault B Keeper Setting this bit enables the Fault B keep action. 0: The Fault B state is released as soon as the recoverable Fault B is released. 1: The Fault B state is released at the end of TCC cycle. z Bit 2 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 1:0 - SRC[1:0]: Fault B Source These bits select the TCC event input for recoverable Fault B, as defined in the table below. Event system channel connected to MCEx event input, must be configured to route the event asynchronously, when used as a recoverable Fault B input. Table 28-22. Fault B Source SRC[1:0] Name Description 0x0 DISABLE Fault input disabled 0x1 ENABLE MCEx (x=0,1) event input 0x2 INVERT Inverted MCEx (x=0,1) event input 0x3 ALTFAULT Alternate fault (A or B) state at the end of the previous period Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 660 28.8.7 Waveform Extension Configuration Name: WEXCTRL Offset: 0x14 Reset: 0x00000000 Property: Enable-Protected, Write-Protected Bit 31 30 29 28 27 26 25 24 DTHS[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DTLS[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DTIEN3 DTIEN2 DTIEN1 DTIEN0 Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OTMX[1:0] Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 31:24 - DTHS[7:0]: Dead-time High Side Outputs Value This register holds the number of GCLK_TCC clock cycles for the dead-time high side. z Bits 23:16 - DTLS[7:0]: Dead-time Low Side Outputs Value This register holds the number of GCLK_TCC clock cycles for the dead-time low side. z Bits 15:12 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 11:8 - DTIENx [x=3..0]: Dead-time Insertion Generator x Enable Setting any of these bits enables the dead-time insertion generator for the corresponding output matrix. This will override the output matrix [x] and [x+WO_NUM/2], with the low side and high side waveform respectively. 0: No dead-time insertion override. 1: Dead time insertion override on signal outputs[x] and [x+WO_NUM/2], from matrix outputs[x] signal. z Bits 7:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 661 z Bits 1:0 - OTMX[1:0]: Output Matrix These bits define the matrix routing of the TCC waveform generation outputs to the port pins, according to Table 28-3. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 662 28.8.8 Driver Control Name: DRVCTRL Offset: 0x18 Reset: 0x00000000 Property: Enable-Protected, Write-Protected Bit 31 30 29 28 27 FILTERVAL1[3:0] Access 26 25 24 FILTERVAL0[3:0] R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 INVEN7 INVEN6 INVEN5 INVEN4 INVEN3 INVEN2 INVEN1 INVEN0 R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 NRV7 NRV6 NRV5 NRV4 NRV3 NRV2 NRV1 NRV0 R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 NRE7 NRE6 NRE5 NRE4 NRE3 NRE2 NRE1 NRE0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Access Access Access Reset z Bits 31:28 - FILTERVAL1[3:0]: Non-Recoverable Fault Input 1 Filter Value These bits define the filter value applied on TCEx event input line. This value must be 0 when TCEx event input line is configured as asynchronous event. z Bits 27:24 - FILTERVAL0[3:0]: Non-Recoverable Fault Input 0 Filter Value These bits define the filter value applied on TCEx event input line. This value must be 0 when TCEx event input line is configured as asynchronous event. z Bits 23:16 - INVENx [x=7..0]: Output Waveform x Inversion These bits are used to select inversion on the output of channel x. Writing a one to INVENx inverts output from WO[x]. Writing a zero to INVENx disables inversion of output from WO[x]. These bits define the value of the enabled override outputs, under non-recoverable fault condition. z Bits 15:8 - NRVx [x=7..0]: Non-Recoverable State x Output Value These bits define the value of the enabled override outputs, under non-recoverable fault condition. z Bits 7:0 - NREx [x=7..0]: Non-Recoverable State x Output Enable These bits enable the override of individual outputs by NRVx value, under non-recoverable fault condition. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 663 0: Non-recoverable fault tri-state the output. 1: Non-recoverable faults set the output to NRVx level. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 664 28.8.9 Debug Control Name: DBGCTRL Offset: 0x1E Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 FDDBD 0 DBGRUN Access R R R R R R/W R R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 2 - FDDBD: Fault Detection on Debug Break Detection This bit is not affected by software reset and should not be changed by software while the TCC is enabled. By default this bit is zero, the on-chip debug (OCD) fault protection is enabled. OCD break request from the OCD system will trigger non-recoverable fault. When this bit is set, OCD fault protection is disabled and OCD break request will not trigger a fault. 0: No faults are generated when TCC is halted in debug mode. 1: A non recoverable fault is generated and DFS flag is set when TCC is halted in debug mode. z Bit 1 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 0 - DBGRUN: Debug Running Mode This bit is not affected by software reset and should not be changed by software while the TCC is enabled. 0: The TCC is halted when the device is halted in debug mode. 1: The TCC continues normal operation when the device is halted in debug mode. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 665 28.8.10 Event Control Name: EVCTRL Offset: 0x20 Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 MCEO3 MCEO2 MCEO1 MCEO0 Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 MCEI3 MCEI2 MCEI1 MCEI0 Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 TCEI1 TCEI0 TCINV1 TCINV0 CNTEO TRGEO OVFEO R/W R/W R/W R/W R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Access CNTSEL[1:0] Access Reset EVACT1[2:0] EVACT0[2:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 31:28 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 27:24 - MCEOx [x=3..0]: Match or Capture Channel x Event Output Enable These bits control if the Match/capture event on channel x is enabled and will be generated for every match or capture. 0: Match/capture x event is disabled and will not be generated. 1: Match/capture x event is enabled and will be generated for every compare/capture on channel x. z Bits 23:20 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 19:16 - MCEIx [x=3..0]: Match or Capture Channel x Event Input Enable These bits indicate if the Match/capture x incoming event is enabled These bits are used to enable match or capture input events to the CCx channel of TCC. 0: Incoming events are disabled. 1: Incoming events are enabled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 666 z Bits 15:14 - TCEIx [x=1..0]: Timer/counter Event x Input Enable This bit is used to enable input event x to the TCC. 0: Incoming event x is disabled. 1: Incoming event x is enabled. z Bits 13:12 - TCINVx [x=1..0]: Inverted Event x Input Enable This bit inverts the event x input. 0: Input event source x is not inverted. 1: Input event source x is inverted. z Bit 11 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 10 - CNTEO: Timer/counter Output Event Enable This bit is used to enable the counter cycle event. When enabled, an event will be generated on begin or end of counter cycle depending of CNTSEL[1:0] settings. 0: Counter cycle output event is disabled and will not be generated. 1: Counter cycle output event is enabled and will be generated depend of CNTSEL[1:0] value. z Bit 9 - TRGEO: Retrigger Output Event Enable This bit is used to enable the counter retrigger event. When enabled, an event will be generated when the counter retriggers operation. 0: Counter retrigger event is disabled and will not be generated. 1: Counter retrigger event is enabled and will be generated for every counter retrigger. z Bit 8 - OVFEO: Overflow/Underflow Output Event Enable This bit is used to enable the overflow/underflow event. When enabled, an event will be generated when the counter reaches the TOP or the ZERO value. 0: Overflow/underflow counter event is disabled and will not be generated. 1: Overflow/underflow counter event is enabled and will be generated for every counter overflow/underflow. z Bits 7:6 - CNTSEL[1:0]: Timer/counter Output Event Mode These bits define on which part of the counter cycle the counter event output is generated. Table 28-23. Timer/counter Output Event Mode z CNTSEL[1:0] Name Description 0x0 START An interrupt/event is generated when a new counter cycle starts 0x1 END An interrupt/event is generated when a counter cycle ends 0x2 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 0x3 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends Bits 5:3 - EVACT1[2:0]: Timer/counter Input Event1 Action These bits define the action the TCC will perform on TCCx EV1 event input, as shown in the table below. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 667 Table 28-24. Timer/counter Input Event1 Action z EVACT1[2:0] Name Description 0x0 OFF 0x1 RETRIGGER 0x2 DIR 0x3 STOP Stop counter on event 0x4 DEC Decrement counter on event 0x5 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 0x6 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 0x7 FAULT Event action disabled Re-trigger counter on event Direction control Non-recoverable fault Bits 2:0 - EVACT0[2:0]: Timer/counter Input Event0 Action These bits define the action the TCC will perform on TCCx EV0 event input 0, as shown in the table below. Table 28-25. Timer/counter Input Event0 Action EVACT0[2:0] Name 0x0 OFF 0x1 RETRIGGER 0x2 COUNTEV 0x3 START 0x4 INC 0x5 COUNT 0x6 0x7 Description Event action disabled Start, restart or re-trigger counter on event Count on event Start counter on event Increment counter on event Count on active state of asynchronous event Reserved FAULT Non-recoverable fault Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 668 28.8.11 Interrupt Enable Clear This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register. Name: INTENCLR Offset: 0x24 Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 MC3 MC2 MC1 MC0 Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 FAULT1 FAULT0 FAULTB FAULTA DFS R/W R/W R/W R/W R/W R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ERR CNT TRG OVF Access Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 31:20 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 19:16 - MCx [x=3..0]: Match or Capture Channel x Interrupt Enable 0: The Match or Capture Channel x interrupt is disabled. 1: The Match or Capture Channel x interrupt is enabled. Writing a zero to MCx has no effect. Writing a one to MCx will clear the corresponding Match or Capture Channel x Interrupt Disable/Enable bit, which disables the Match or Capture Channel x interrupt. z Bit 15 - FAULT1: Non-Recoverable Fault 1 Interrupt Enable 0: The Non-Recoverable Fault 1 interrupt is disabled. 1: The Non-Recoverable Fault 1 interrupt is enabled. Writing a zero to this bit has no effect. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 669 Writing a one to this bit will clear the Non-Recoverable Fault 1 Interrupt Disable/Enable bit, which disables the Non-Recoverable Fault 1 interrupt. z Bit 14 - FAULT0: Non-Recoverable Fault 0 Interrupt Enable 0: The Non-Recoverable Fault 0 interrupt is disabled. 1: The Non-Recoverable Fault 0 interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Non-Recoverable Fault 0 Interrupt Disable/Enable bit, which disables the Non-Recoverable Fault 0 interrupt. z Bit 13 - FAULTB: Recoverable Fault B Interrupt Enable 0: The Recoverable Fault B interrupt is disabled. 1: The Recoverable Fault B interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Recoverable Fault B Interrupt Disable/Enable bit, which disables the Recoverable Fault B interrupt. z Bit 12 - FAULTA: Recoverable Fault A Interrupt Enable 0: The Recoverable Fault A interrupt is disabled. 1: The Recoverable Fault A interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Recoverable Fault A Interrupt Disable/Enable bit, which disables the Recoverable Fault A interrupt. z Bit 11 - DFS: Non-Recoverable Debug Fault Interrupt Enable 0: The Debug Fault State interrupt is disabled. 1: The Debug Fault State interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Debug Fault State Interrupt Disable/Enable bit, which disables the Debug Fault State interrupt. z Bits 10:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 3 - ERR: Error Interrupt Enable 0: The Error interrupt is disabled. 1: The Error interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Error Interrupt Disable/Enable bit, which disables the Error interrupt. z Bit 2 - CNT: Counter Interrupt Enable 0: The Counter interrupt is disabled. 1: The Counter interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Counter Interrupt Disable/Enable bit, which disables the Counter interrupt. z Bit 1 - TRG: Retrigger Interrupt Enable 0: The Retrigger interrupt is disabled. 1: The Retrigger interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Retrigger Interrupt Disable/Enable bit, which disables the Retrigger interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 670 z Bit 0 - OVF: Overflow Interrupt Enable 0: The Overflow interrupt is disabled. 1: The Overflow interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Overflow Interrupt Disable/Enable bit, which disables the Overflow interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 671 28.8.12 Interrupt Enable Set This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Name: INTENSET Offset: 0x28 Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 MC3 MC2 MC1 MC0 Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 FAULT1 FAULT0 FAULTB FAULTA DFS R/W R/W R/W R/W R/W R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ERR CNT TRG OVF Access Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 31:20 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 19:16 - MCx [x=3..0]: Match or Capture Channel x Interrupt Enable 0: The Match or Capture Channel x interrupt is disabled. 1: The Match or Capture Channel x interrupt is enabled. Writing a zero to MCx has no effect. Writing a one to MCx will set the corresponding Match or Capture Channel x Interrupt Disable/Enable bit, which enables the Match or Capture Channel x interrupt. z Bit 15 - FAULT1: Non-Recoverable Fault 1 Interrupt Enable 0: The Non-Recoverable Fault 1 interrupt is disabled. 1: The Non-Recoverable Fault 1 interrupt is enabled. Writing a zero to this bit has no effect. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 672 Writing a one to this bit will set the Non-Recoverable Fault 1 Interrupt Disable/Enable bit, which enables the NonRecoverable Fault 1 interrupt. z Bit 14 - FAULT0: Non-Recoverable Fault 0 Interrupt Enable 0: The Non-Recoverable Fault 0 interrupt is disabled. 1: The Non-Recoverable Fault 0 interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Non-Recoverable Fault 0 Interrupt Disable/Enable bit, which enables the NonRecoverable Fault 0 interrupt. z Bit 13 - FAULTB: Recoverable Fault B Interrupt Enable 0: The Recoverable Fault B interrupt is disabled. 1: The Recoverable Fault B interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Recoverable Fault B Interrupt Disable/Enable bit, which enables the Recoverable Fault B interrupt. z Bit 12 - FAULTA: Recoverable Fault A Interrupt Enable 0: The Recoverable Fault A interrupt is disabled. 1: The Recoverable Fault A interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Recoverable Fault A Interrupt Disable/Enable bit, which enables the Recoverable Fault A interrupt. z Bit 11 - DFS: Non-Recoverable Debug Fault Interrupt Enable 0: The Debug Fault State interrupt is disabled. 1: The Debug Fault State interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Debug Fault State Interrupt Disable/Enable bit, which enables the Debug Fault State interrupt. z Bits 10:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 3 - ERR: Error Interrupt Enable 0: The Error interrupt is disabled. 1: The Error interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Error Interrupt Disable/Enable bit, which enables the Error interrupt. z Bit 2 - CNT: Counter Interrupt Enable 0: The Counter interrupt is disabled. 1: The Counter interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Retrigger Interrupt Disable/Enable bit, which enables the Counter interrupt. z Bit 1 - TRG: Retrigger Interrupt Enable 0: The Retrigger interrupt is disabled. 1: The Retrigger interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Retrigger Interrupt Disable/Enable bit, which enables the Retrigger interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 673 z Bit 0 - OVF: Overflow Interrupt Enable 0: The Overflow interrupt is disabled. 1: The Overflow interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Overflow Interrupt Disable/Enable bit, which enables the Overflow interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 674 28.8.13 Interrupt Flag Status and Clear Name: INTFLAG Offset: 0x2C Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 MC3 MC2 MC1 MC0 Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 FAULT1 FAULT0 FAULTB FAULTA DFS R/W R/W R/W R/W R/W R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ERR CNT TRG OVF Access Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 31:20 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 19:16 - MCx [x=3..0]: Match or Capture x This flag is set on the next CLK_TCC_COUNT cycle after a match with the compare condition or once CCx register contain a valid capture value. Writing a zero to one of these bits has no effect. Writing a one to one of these bits will clear the corresponding Match or Capture Channel x interrupt flag In Capture operation, this flag is automatically cleared when CCx register is read. z Bit 15 - FAULT1: Non-Recoverable Fault 1 This flag is set on the next CLK_TCC_COUNT cycle after a Non-Recoverable Fault 1 occurs. Writing a zero to this bit has no effect. Writing a one to this bit clears the Non-Recoverable Fault 1 interrupt flag. z Bit 14 - FAULT0: Non-Recoverable Fault 0 This flag is set on the next CLK_TCC_COUNT cycle after a Non-Recoverable Fault 0 occurs. Writing a zero to this bit has no effect. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 675 Writing a one to this bit clears the Non-Recoverable Fault 0 interrupt flag. z Bit 13 - FAULTB: Recoverable Fault B This flag is set on the next CLK_TCC_COUNT cycle after a Recoverable Fault B occurs. Writing a zero to this bit has no effect. Writing a one to this bit clears the Recoverable Fault B interrupt flag. z Bit 12 - FAULTA: Recoverable Fault A This flag is set on the next CLK_TCC_COUNT cycle after a Recoverable Fault A occurs. Writing a zero to this bit has no effect. Writing a one to this bit clears the Recoverable Fault A interrupt flag. z Bit 11 - DFS: Non-Recoverable Debug Fault This flag is set on the next CLK_TCC_COUNT cycle after an Debug Fault State occurs. Writing a zero to this bit has no effect. Writing a one to this bit clears the Debug Fault State interrupt flag. z Bits 10:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 3 - ERR: Error This flag is set if a new capture occurs on a channel when the corresponding Match or Capture Channel x interrupt flag is one. In which case there is nowhere to store the new capture. Writing a zero to this bit has no effect. Writing a one to this bit clears the Error interrupt flag. z Bit 2 - CNT: Counter This flag is set on the next CLK_TCC_COUNT cycle after a counter event occurs. Writing a zero to this bit has no effect. Writing a one to this bit clears the CNT interrupt flag. z Bit 1 - TRG: Retrigger This flag is set on the next CLK_TCC_COUNT cycle after a counter retrigger occurs. Writing a zero to this bit has no effect. Writing a one to this bit clears the Retrigger interrupt flag. z Bit 0 - OVF: Overflow This flag is set on the next CLK_TCC_COUNT cycle after an overflow condition occurs. Writing a zero to this bit has no effect. Writing a one to this bit clears the Overflow interrupt flag. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 676 28.8.14 Status Name: STATUS Offset: 0x30 Reset: 0x00000001 Property: - Bit 31 30 29 28 27 26 25 24 CMP3 CMP2 CMP1 CMP0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 CCBV3 CCBV2 CCBV1 CCBV0 Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 FAULT1 FAULT0 FAULTB FAULTA FAULT1IN FAULT0IN FAULTBIN FAULTAIN R/W R/W R/W R/W R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PERBV WAVEBV PATTBV SLAVE DFS IDX STOP R/W R/W R/W R R/W R R R 0 0 0 0 0 0 0 1 Access Access Reset z Bits 31:28 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 27:24 - CMPx [x=3..0]: Compare Channel x Value This bit reflects the channel x output compare value. 0: Channel compare output value is 0. 1: Channel compare output value is 1. z Bits 23:20 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 19:16 - CCBVx [x=3..0]: Compare Channel x Buffer Valid For a compare channel, the bit is set when a new value is written to the corresponding CCBx register. The bit is cleared by writing a one to the corresponding location or automatically cleared on an UPDATE condition. For a capture channel, the bit is set when a valid capture value is stored in the CCBx register. The bit is automatically cleared when the CCx register is read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 677 z Bit 15 - FAULT1: Non-Recoverable Fault 1 State This bit is set by hardware as soon as non-recoverable Fault 1 condition occurs. This bit is cleared by writing a one to this bit and when the corresponding FAULT1IN status bit is low. Once this bit is clear, the timer/counter will restart from the last COUNT value. To restart the timer/counter from BOTTOM, the timer/counter restart command must be executed before clearing the corresponding FAULT1 bit. For further details on timer/counter commands, refer to available commands description (CTRLBSET.CMD). z Bit 14 - FAULT0: Non-Recoverable Fault 0 State This bit is set by hardware as soon as non-recoverable Fault 0 condition occurs. This bit is cleared by writing a one to this bit and when the corresponding FAULT0IN status bit is low. Once this bit is clear, the timer/counter will restart from the last COUNT value. To restart the timer/counter from BOTTOM, the timer/counter restart command must be executed before clearing the corresponding FAULT0 bit. For further details on timer/counter commands, refer to available commands description (CTRLBSET.CMD). z Bit 13 - FAULTB: Recoverable Fault B State This bit is set by hardware as soon as recoverable Fault B condition occurs. This bit is cleared by hardware when Fault B action is resumed, or by writing a one to this bit when the corresponding FAULTBIN bit is low. If software halt command is enabled (FCTRLB.HALT=SW), clearing this bit release the timer/counter. z Bit 12 - FAULTA: Recoverable Fault A State This bit is set by hardware as soon as recoverable Fault A condition occurs. This bit is cleared by hardware when Fault A action is resumed, or by writing a one to this bit when the corresponding FAULTAIN bit is low. If software halt command is enabled (FCTRLA.HALT=SW), clearing this bit release the timer/counter. z Bit 11 - FAULT1IN: Non-Recoverable Fault1 Input This bit is set while an active Non-Recoverable Fault 1 input is present. z Bit 10 - FAULT0IN: Non-Recoverable Fault0 Input This bit is set while an active Non-Recoverable Fault 0 input is present. z Bit 9 - FAULTBIN: Recoverable Fault B Input This bit is set while an active Recoverable Fault B input is present. z Bit 8 - FAULTAIN: Recoverable Fault A Input This bit is set while an active Recoverable Fault A input is present. z Bit 7 - PERBV: Period Buffer Valid This bit is set when a new value is written to the PERB register. This bit is automatically cleared by hardware on UPDATE condition or by writing a one to this bit. z Bit 6 - WAVEBV: Wave Buffer Valid This bit is set when a new value is written to the WAVEB register. This bit is automatically cleared by hardware on UPDATE condition or by writing a one to this bit. z Bit 5 - PATTBV: Pattern Buffer Valid This bit is set when a new value is written to the PATTB register. This bit is automatically cleared by hardware on UPDATE condition or by writing a one to this bit. z Bit 4 - SLAVE: Slave Tis bit is set when TCC is set in Slave mode. This bit follows the CTRLA.MSYNC bit state. z Bit 3 - DFS: Non-Recoverable Debug Fault State This bit is set by hardware in debug mode when DBGCTRL.FDDBD bit is set. The bit is cleared by writing a one to this bit and when the TCC is not in debug mode. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 678 When the bit is set, the counter is halted and the waveforms state depend on DRVCTRL.NRE and DRVCTRL.NRV registers. z Bit 2 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 1 - IDX: Ramp In RAMP2 and RAMP2A operation, the bit is cleared during the cycle A and set during the cycle B. In RAMP1 operation, the bit is always read zero. For details on ramp operations, refer to "Ramp Operations" on page 628. z Bit 0 - STOP: Stop This bit is set when the TCC is disabled, on a STOP command or on an UPDATE condition when One-Shot operation mode is enabled (CTRLBSET.ONESHOT = 1). This bit is clear on the next incoming counter increment or decrement. 0: Counter is running. 1: Counter is stopped. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 679 28.8.15 Count Mode: DITH4 Name: COUNT Offset: 0x34 Reset: 0x00000000 Property: Read-Synchronized, Write-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 COUNT[19:12] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 COUNT[11:4] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COUNT[3:0] Access Reset R/W R/W R/W R/W R R R R 0 0 0 0 0 0 0 0 z Bits 31:24 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 23:4 - COUNT[19:0]: Counter Value These bits hold the value of the counter register. The number of bits in this field corresponds to the size of the counter. z Bits 3:0 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 680 Mode: DITH5 Name: COUNT Offset: 0x34 Reset: 0x00000000 Property: Read-Synchronized, Write-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 COUNT[18:11] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 COUNT[10:3] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COUNT[2:0] Access Reset R/W R/W R/W R R R R R 0 0 0 0 0 0 0 0 z Bits 31:24 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 23:5 - COUNT[18:0]: Counter Value These bits hold the value of the counter register. The number of bits in this field corresponds to the size of the counter. z Bits 4:0 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 681 Mode: DITH6 Name: COUNT Offset: 0x34 Reset: 0x00000000 Property: Read-Synchronized, Write-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 COUNT[17:10] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 COUNT[9:2] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 R/W R/W R R R R R R 0 0 0 0 0 0 0 0 COUNT[1:0] Access Reset z Bits 31:24 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 23:6 - COUNT[17:0]: Counter Value These bits hold the value of the counter register. The number of bits in this field corresponds to the size of the counter. z Bits 5:0 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 682 28.8.16 Pattern Name: PATT Offset: 0x38 Reset: 0x0000 Property: Write-Synchronized Bit 15 14 13 12 11 10 9 8 PGV7 PGV6 PGV5 PGV4 PGV3 PGV2 PGV1 PGV0 R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PGE7 PGE6 PGE5 PGE4 PGE3 PGE2 PGE1 PGE0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Access Access Reset z Bits 15:8 - PGVx [x=7..0]: Pattern Generator x Output Value This register holds the values of pattern for each waveform output. z Bits 7:0 - PGEx [x=7..0]: Pattern Generator x Output Enable This register holds the enables of pattern generation for each waveform output. A bit position at one, overrides the corresponding SWAP output with the corresponding PGVx value. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 683 28.8.17 Waveform Control Name: WAVE Offset: 0x3C Reset: 0x00000000 Property: Write-Synchronized Bit 31 30 29 28 27 26 25 24 SWAP3 SWAP2 SWAP1 SWAP0 Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 POL3 POL2 POL1 POL0 Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 CICCEN3 CICCEN2 CICCEN1 CICCEN0 Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CIPEREN Access Reset RAMP[1:0] WAVEGEN[2:0] R/W R R/W R/W R R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 31:28 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 27:24 - SWAPx [x=3..0]: Swap DTI Output Pair x Setting these bits enables output swap of DTI outputs [x] and [x+WO_NUM/2]. Note the DTIxEN settings will not affect the swap operation. z Bits 23:20 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 19:16 - POLx [x=3..0]: Channel x Polarity Setting these bits enable the output polarity in single-slope and dual-slope PWM operations. In single-slope PWM waveform generation: 0: Compare output is initialized to ~DIR and set to DIR when TCC counter matches CCx value 1: Compare output is initialized to DIR and set to ~DIR when TCC counter matches CCx value. In dual-slope PWM waveform generation: 0: Compare output is set to ~DIR when TCC counter matches CCx value Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 684 1: Compare output is set to DIR when TCC counter matches CCx value. z Bits 15:12 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 11:8 - CICCENx [x=3..0]: Circular Channel x Enable Setting these bits enable the compare circular buffer option on channel. When the bit is set, CCx register value is copied-back into the CCx register on UPDATE condition. z Bit 7 - CIPEREN: Circular period Enable Setting these bits enable the period circular buffer option. When the bit field is set, the PER register value is copied-back into the PERB register on UPDATE condition. z Bit 6 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 5:4 - RAMP[1:0]: Ramp Mode These bits select Ramp operation (RAMP), as shown in the table below. These bits are not synchronized. Table 28-26. Ramp Mode RAMP[1:0] Name 0x0 RAMP1 0x1 RAMP2A 0x2 RAMP2 0x3 Description RAMP1 operation Alternative RAMP2 operation RAMP2 operation Reserved z Bit 3 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 2:0 - WAVEGEN[2:0]: Waveform Generation These bits select the waveform generation operation, as shown in the table below. The settings impact the top value and select the frequency/PWM mode. These bits are not synchronized. Table 28-27. Waveform Generation WAVEGEN[2:0] Name 0x0 NFRQ Normal frequency 0x1 MFRQ Match frequency 0x2 NPWM Normal PWM 0x3 0x4 Description Reserved DSCRITICAL Dual-slope critical Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 685 WAVEGEN[2:0] Name Description 0x5 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 0x6 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 0x7 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 686 28.8.18 Period Mode: DITH4 Name: PER Offset: 0x40 Reset: 0x00FFFFFF Property: Write-Synchronized Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 PER[19:12] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 15 14 13 12 11 10 9 8 PER[11:4] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 0 PER[3:0] Access Reset DITHERCY[3:0] R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 z Bits 31:24 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 23:4 - PER[19:0]: Period Value These bits hold the value of the period buffer register. The value is copied to PER register on UPDATE condition. The number of bits in this field corresponds to the size of the counter. z Bits 3:0 - DITHERCY[3:0]: Dithering Cycle Number These bits hold the number of extra cycles that are added on the PWM period each number of frames as specified in Table 28-8 on page 648. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 687 Mode: DITH5 Name: PER Offset: 0x40 Reset: 0x00FFFFFF Property: Write-Synchronized Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 PER[18:11] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 15 14 13 12 11 10 9 8 PER[10:3] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 0 PER[2:0] Access Reset DITHERCY[4:0] R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 z Bits 31:24 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 23:5 - PER[18:0]: Period Value These bits hold the value of the period buffer register. The value is copied to PER register on UPDATE condition. The number of bits in this field corresponds to the size of the counter. z Bits 4:0 - DITHERCY[4:0]: Dithering Cycle Number These bits hold the number of extra cycles that are added on the PWM period each number of frames as specified in Table 28-8 on page 648. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 688 Mode: DITH6 Name: PER Offset: 0x40 Reset: 0x00FFFFFF Property: Write-Synchronized Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 PER[17:10] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 15 14 13 12 11 10 9 8 PER[9:2] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 0 PER[1:0] Access Reset DITHERCY[5:0] R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 z Bits 31:24 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 23:6 - PER[17:0]: Period Value These bits hold the value of the period buffer register. The value is copied to PER register on UPDATE condition. The number of bits in this field corresponds to the size of the counter. z Bits 5:0 - DITHERCY[5:0]: Dithering Cycle Number These bits hold the number of extra cycles that are added on the PWM period each number of frames as specified in Table 28-8 on page 648. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 689 28.8.19 Compare and Capture Mode: DITH4 Name: CCn Offset: 0x44+n*0x4 [n=0..3] Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 CC[19:12] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 CC[11:4] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CC[3:0] Access Reset DITHERCY[3:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 31:24 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 23:4 - CC[19:0]: Channel Compare/Capture Value These bits hold the value of the Channel x compare/capture register. The number of bits in this field corresponds to the size of the counter. z Bits 3:0 - DITHERCY[3:0]: Dithering Cycle Number These bits hold the number of extra cycles that are added on the PWM pulse width each number of frames as specified in Table 28-8 on page 648. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 690 Mode: DITH5 Name: CCn Offset: 0x44+n*0x4 [n=0..3] Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 CC[18:11] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 CC[10:3] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CC[2:0] Access Reset DITHERCY[4:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 31:24 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 23:5 - CC[18:0]: Channel Compare/Capture Value These bits hold the value of the Channel x compare/capture register. The number of bits in this field corresponds to the size of the counter. z Bits 4:0 - DITHERCY[4:0]: Dithering Cycle Number These bits hold the number of extra cycles that are added on the PWM pulse width each number of frames as specified in Table 28-8 on page 648. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 691 Mode: DITH6 Name: CCn Offset: 0x44+n*0x4 [n=0..3] Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 CC[17:10] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 CC[9:2] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CC[1:0] Access Reset DITHERCY[5:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 31:24 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 23:6 - CC[17:0]: Channel Compare/Capture Value These bits hold the value of the Channel x compare/capture register. The number of bits in this field corresponds to the size of the counter. z Bits 5:0 - DITHERCY[5:0]: Dithering Cycle Number These bits hold the number of extra cycles that are added on the PWM pulse width each number of frames as specified in Table 28-8 on page 648. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 692 28.8.20 Pattern Buffer Name: PATTB Offset: 0x64 Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 9 8 PGVB7 PGVB6 PGVB5 PGVB4 PGVB3 PGVB2 PGVB1 PGVB0 R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PGEB7 PGEB6 PGEB5 PGEB4 PGEB3 PGEB2 PGEB1 PGEB0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Access Access Reset z Bits 15:8 - PGVBx [x=7..0]: Pattern Generator x Output Enable These bits represent the PGV buffers. When the double buffering is enable, PGVB bits value is copied to the PGV bits on an UPDATE condition. z Bits 7:0 - PGEBx [x=7..0]: Pattern Generator x Output Enable Buffer These bits represent the PGE buffers. When the double buffering is enable, PGEB bits value is copied to the PGE bits on an UPDATE condition. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 693 28.8.21 Waveform Control Buffer Name: WAVEB Offset: 0x68 Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 SWAPB3 SWAPB2 SWAPB1 SWAPB0 Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 POLB3 POLB2 POLB1 POLB0 Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 CICCENB3 CICCENB2 CICCENB1 CICCENB0 Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CIPERENB Access Reset RAMPB[1:0] WAVEGENB[2:0] R/W R R/W R/W R R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 31:28 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 27:24 - SWAPBx [x=3..0]: Swap DTI Output Pair x Buffer These bits represent the SWAP buffers. When the double buffering is enable, SWAPB bits value is copied to the SWAP bits on an UPDATE condition. z Bits 23:20 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 19:16 - POLBx [x=3..0]: Channel x Polarity Buffer These bits represent the POL buffers. When the double buffering is enable, POLB bits value is copied to the POL bits on an UPDATE condition. z Bits 15:12 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 694 z Bits 11:8 - CICCENBx [x=3..0]: Circular Channel x Enable Buffer These bits represent the CICCEN buffers. When the double buffering is enable, CICCENB bits value is copied to the CICCEN bits on an UPDATE condition. z Bit 7 - CIPERENB: Circular Period Enable Buffer This bit represents the CIPEREN buffer. When the double buffering is enable, CIPERENB bit value is copied to the CIPEREN bit on an UPDATE condition. z Bit 6 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 5:4 - RAMPB[1:0]: Ramp Mode Buffer These bits represent the RAMP buffers. When the double buffering is enable, RAMPB bits value is copied to the RAMP bits on an UPDATE condition. Table 28-28. Ramp Mode Buffer RAMPB[1:0] Name 0x0 RAMP1 0x1 RAMP2A 0x2 RAMP2 0x3 Description RAMP1 operation Alternative RAMP2 operation RAMP2 operation Reserved z Bit 3 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 2:0 - WAVEGENB[2:0]: Waveform Generation Buffer These bits represent the WAVEGEN buffers. When the double buffering is enable, WAVEGENB bits value is copied to the WAVEGEN bits on an UPDATE condition. Table 28-29. Waveform Generation Buffer WAVEGENB[2:0] Name 0x0 NFRQ Normal frequency 0x1 MFRQ Match frequency 0x2 NPWM Normal PWM 0x3 Description Reserved 0x4 DSCRITICAL Dual-slope critical 0x5 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 0x6 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 0x7 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 695 28.8.22 Period Buffer Mode: DITH4 Name: PERB Offset: 0x6C Reset: 0x00FFFFFF Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 PERB[19:12] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 15 14 13 12 11 10 9 8 PERB[11:4] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 0 PERB[3:0] Access Reset DITHERCYB[3:0] R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 z Bits 31:24 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 23:4 - PERB[19:0]: Period Buffer Value These bits hold the value of the period register. The number of bits in this field corresponds to the size of the counter. z Bits 3:0 - DITHERCYB[3:0]: Dithering Buffer Cycle Number These bits represent the PER.DITHERCY bits buffer. When the double buffering is enable, DITHERCYB bits value is copied to the PER.DITHERCY bits on an UPDATE condition. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 696 Mode: DITH5 Name: PERB Offset: 0x6C Reset: 0x00FFFFFF Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 PERB[18:11] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 15 14 13 12 11 10 9 8 PERB[10:3] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 0 PERB[2:0] Access Reset DITHERCYB[4:0] R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 z Bits 31:24 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 23:5 - PERB[18:0]: Period Buffer Value These bits hold the value of the period register. The number of bits in this field corresponds to the size of the counter. z Bits 4:0 - DITHERCYB[4:0]: Dithering Buffer Cycle Number These bits represent the PER.DITHERCY bits buffer. When the double buffering is enable, DITHERCYB bits value is copied to the PER.DITHERCY bits on an UPDATE condition. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 697 Mode: DITH6 Name: PERB Offset: 0x6C Reset: 0x00FFFFFF Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 PERB[17:10] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 15 14 13 12 11 10 9 8 PERB[9:2] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 0 PERB[1:0] Access Reset DITHERCYB[5:0] R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 z Bits 31:24 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 23:6 - PERB[17:0]: Period Buffer Value These bits hold the value of the period register. The number of bits in this field corresponds to the size of the counter. z Bits 5:0 - DITHERCYB[5:0]: Dithering Buffer Cycle Number These bits represent the PER.DITHERCY bits buffer. When the double buffering is enable, DITHERCYB bits value is copied to the PER.DITHERCY bits on an UPDATE condition. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 698 28.8.23 Compare and Capture Buffer Mode: DITH4 Name: CCBn Offset: 0x70+n*0x4 [n=0..3] Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 CCB[19:12] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 CCB[11:4] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CCB[3:0] Access Reset DITHERCYB[3:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 31:24 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 23:4 - CCB[19:0]: Channel Compare/Capture Buffer Value These bits hold the value of the channel x compare/capture buffer register. The register serves as the buffer for the associated compare or capture registers (CCx). Accessing this register using the CPU or DMA will affect the corresponding CCBVx status bit. The number of bits in this field corresponds to the size of the counter. z Bits 3:0 - DITHERCYB[3:0]: Dithering Buffer Cycle Number These bits represent the CCx.DITHERCY bits buffer. When the double buffering is enable, DITHERCYB bits value is copied to the CCx.DITHERCY bits on an UPDATE condition. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 699 Mode: DITH5 Name: CCBn Offset: 0x70+n*0x4 [n=0..3] Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 CCB[18:11] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 CCB[10:3] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CCB[2:0] Access Reset DITHERCYB[4:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 31:24 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 23:5 - CCB[18:0]: Channel Compare/Capture Buffer Value These bits hold the value of the channel x compare/capture buffer register. The register serves as the buffer for the associated compare or capture registers (CCx). Accessing this register using the CPU or DMA will affect the corresponding CCBVx status bit. The number of bits in this field corresponds to the size of the counter. z Bits 4:0 - DITHERCYB[4:0]: Dithering Buffer Cycle Number These bits represent the CCx.DITHERCY bits buffer. When the double buffering is enable, DITHERCYB bits value is copied to the CCx.DITHERCY bits on an UPDATE condition. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 700 Mode: DITH6 Name: CCBn Offset: 0x70+n*0x4 [n=0..3] Reset: 0x00000000 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 CCB[17:10] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 CCB[9:2] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CCB[1:0] Access Reset DITHERCYB[5:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 31:24 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 23:6 - CCB[17:0]: Channel Compare/Capture Buffer Value These bits hold the value of the channel x compare/capture buffer register. The register serves as the buffer for the associated compare or capture registers (CCx). Accessing this register using the CPU or DMA will affect the corresponding CCBVx status bit. The number of bits in this field corresponds to the size of the counter. z Bits 5:0 - DITHERCYB[5:0]: Dithering Buffer Cycle Number These bits represent the CCx.DITHERCY bits buffer. When the double buffering is enable, DITHERCYB bits value is copied to the CCx.DITHERCY bits on an UPDATE condition. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 701 29. USB - Universal Serial Bus 29.1 Overview The Universal Serial Bus interface (USB) module complies with the Universal Serial Bus (USB) 2.1 specification supporting both device and embedded host modes. The USB device mode supports 8 endpoint addresses. All endpoint addresses have one input and one output endpoint, for a total of 16 endpoints. Each endpoint is fully configurable in any of the four transfer types: control, interrupt, bulk or isochronous. The USB host mode supports up to 8 pipes. The maximum data payload size is selectable up to 1023 bytes. Internal SRAM is used to keep the configuration and data buffer for each endpoint. The memory locations used for the endpoint configurations and data buffers is fully configurable. The amount of memory allocated is dynamic according to the number of endpoints in use, and the configuration of these. The USB module has a built-in Direct Memory Access (DMA) and will read/write data from/to the system RAM when a USB transaction takes place. No CPU or DMA Controller resources are required. To maximize throughput, an endpoint can be configured for ping-pong operation. When this is done the input and output endpoint with the same address are used in the same direction. The CPU or DMA Controller can then read/write one data buffer while the USB module writes/reads from the other buffer. This gives double buffered communication. Multi-packet transfer enables a data payload exceeding the maximum packet size of an endpoint to be transferred as multiple packets without any software intervention. This reduces the number of interrupts and software intervention needed for USB transfers. For low power operation the USB module can put the microcontroller in any sleep mode when the USB bus is idle and a suspend condition is given. Upon bus resume the USB module can wake the microcontroller from any sleep mode. 29.2 Features z Compatible with the USB 2.1 specification z USB Embedded Host and Device mode z Supports full (12Mbit/s) and low (1.5Mbit/s) speed communication z Supports Link Power Management (LPM-L1) protocol z On-chip transceivers with built-in pull-ups and pull-downs z On-Chip USB serial resistors z 1kHz SOF clock available on external pin z Device mode z Supports 8 IN endpoints and 8 OUT endpoints No endpoint size limitations z Built-in DMA with multi-packet and dual bank for all endpoints z Supports feedback endpoint z Supports crystal less clock z z Host mode Supports 8 physical pipes No pipe size limitations z Supports multiplexed virtual pipe on one physical pipe to allow an unlimited USB tree z z z z z Built-in DMA with multi-packet support and dual bank for all pipes Supports feedback endpoint Supports the USB 2.0 Phase-locked SOFs feature Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 702 29.3 USB Block Diagram Figure 29-1. LS/FS Implementation: USB Block Diagram USB AHB Master AHB User APB interface DP USB interrupts NVIC SOF 1kHz GCLK_USB GCLK System clock domain 29.4 DM USB 2.0 Core USB clock domain Signal Description Pin Name Pin Description Type DM Data -: Differential Data Line - Port Input/Output DP Data +: Differential Data Line + Port Input/Output SOF 1kHZ SOF Output Output Refer to "I/O Multiplexing and Considerations" on page 12 for details on the pin mapping for this peripheral. One signal can be mapped to one of several pins. 29.5 Product Dependencies In order to use this peripheral module, other parts of the system must be configured correctly, as described below. 29.5.1 I/O Lines The USB pins may be multiplexed with the I/O lines Controller. The user must first configure the I/O Controller to assign the USB pins to their peripheral functions. A 1kHz SOF clock is available on external pin. The user must first configure the I/O Controller to assign the 1kHz SOF clock to the peripheral function. The SOF clock is available for device and host. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 703 29.5.2 Power Management The USB will continue to operate in any sleep mode where the selected source clock is running. The USB's interrupts can be used to wake up the device from sleep modes. Events connected to the event system can trigger other operations in the system without exiting sleep modes. Refer to the "PM - Power Manager" on page 112 for details on the different sleep modes. 29.5.3 Clocks The USB bus clock (CLK_USB_AHB) can be enabled and disabled in the Power Manager, and the default state of CLK_USB_AHB can be found in the Peripheral Clock Masking section in "PM - Power Manager" on page 112. A generic clock (GCLK_USB) is required to clock the USB. This clock must be configured and enabled in the Generic Clock Controller before using the USB. Refer to "GCLK - Generic Clock Controller" on page 90 for further details. This generic clock is asynchronous to the bus clock (CLK_USB_AHB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. Refer to "Synchronization" on page 96 for further details. The USB module requires a GCLK_USB of 48 MHz 0.25% clock for low speed and full speed operation. To follow the USB data rate at 12Mbit/s in full-speed mode, the CLK_USB_AHB clock should be at minimum 8MHz. Clock recovery is achieved by a digital phase-locked loop in the USB module, which complies with the USB jitter specifications. If crystal-less operation is used in USB device mode, please refer to "USB Clock Recovery Mode" on page 152. 29.5.4 DMA The USB has a built-in Direct Memory Access (DMA) and will read/write data from/to the system RAM when a USB transaction takes place. No CPU or DMA Controller resources are required. 29.5.5 Interrupts The interrupt request lines are connected to the interrupt controller. Using the USB interrupts requires the interrupt controller to be configured first. Refer to "Nested Vector Interrupt Controller" on page 29 for details. 29.5.6 Events Not Applicable 29.5.7 Debug Operation When the CPU is halted in debug mode the USB continues normal operation. If the USB is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 29.5.8 Register Access Protection All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the following registers: z Device Interrupt Flag (INTFLAG) register z Endpoint Interrupt Flag (EPINTFLAG) register z Host Interrupt Flag (INTFLAG) register z Pipe Interrupt Flag (PINTFLAG) register Write-protection is denoted by the Write-Protected property in the register description. Write-protection does not apply to accesses through an external debugger. Refer to "PAC - Peripheral Access Controller" on page 36 for details. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 704 29.5.9 Analog Connections Not applicable. 29.5.10 Calibration The output drivers for the DP/DM USB line interface can be tuned with calibration values from the production test. The calibration values must be loaded from the NVM Software Calibration Area into the USB Pad Calibration register (PADCAL) by software, before enabling the USB, to achieve the specified accuracy. Refer to "NVM Software Calibration Area Mapping" on page 26 for further details. For details on Pad Calibration, refer to Pad Calibration register PADCAL. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 705 29.6 Functional Description 29.6.1 USB General Operation 29.6.1.1 Initialization After a hardware reset, the USB is disabled. The user should first enable the USB (CTRLA.ENABLE) in either device mode or host mode (CTRLA.MODE). Figure 29-2. General States HW RESET | CTRLA.SWRST Any state Idle CTRLA.ENABLE = 1 CTRLA.MODE =0 CTRLA.ENABLE = 0 CTRLA.ENABLE = 1 CTRLA.MODE =1 Device CTRLA.ENABLE = 0 Host After a hardware reset, the USB is in the idle state. In this state: z The module is disabled. The USB Enable bit in the Control A register (CTRLA.ENABLE) is reset. z The module clock is stopped in order to minimize power consumption. z The USB pad is in suspend mode. z The internal states and registers of the device and host are reset. Before using the USB, the Pad Calibration register (PADCAL) must be loaded with production calibration values from the NVM Software Calibration Area. Refer to "NVM Software Calibration Area Mapping" on page 26 for further details. The USB is enabled by writing a one to CTRLA.ENABLE. The USB is disabled by writing a zero to CTRLA.ENABLE. The USB is reset by writing a one to the Software Reset bit in CTRLA (CTRLA.SWRST). All registers in the USB will be reset to their initial state, and the USB will be disabled. Refer to the CTRLA register for details. The user can configure pads and speed before enabling the USB by writing to the Operating Mode bit in the Control A register (CTRLA.MODE) and the Speed Configuration field in the Control B register (CTRLB.SPDCONF). These values are taken into account once the USB has been enabled by writing a one to CTRLA.ENABLE. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 706 After writing a one to CTRLA.ENABLE, the USB enters device or host mode (according to CTRLA.MODE). Please refer Figure 29-2. The USB can be disabled at any time by writing a zero to CTRLA.ENABLE. Refer to "USB Device Operations" on page 707 for the basic operation of the device mode. Refer to "Host Operations" on page 716 for the basic operation of the host mode. 29.6.2 USB Device Operations This section gives an overview of the USB module device operation during normal transactions. For more details on general USB and USB protocol, please refer to the Universal Serial Bus specification revision 2.1. 29.6.2.1 Initialization To attach the USB device to start the USB communications from the USB host, a zero should be written to the Detach bit in the Device Control B register (CTRLB.DETACH). To detach the device from the USB host, a one must be written to the CTRLB.DETACH. After the device is attached, the host will request the USB device descriptor using the default device address zero. On successful transmission, it will send a USB reset. After that, it sends an address to be configured for the device. All further transactions will be directed to this device address. This address should be configured in the Device Address field in the Device Address register (DADD.DADD) and the Address Enable bit in DADD (DADD.ADDEN) should be written to one to accept the communications directed to this address. DADD.ADDEN is automatically cleared on receiving a USB reset. 29.6.2.2 Endpoint Configuration Endpoint data can be placed anywhere in the device RAM. The USB controller accesses these endpoints directly through the AHB master (built-in DMA) with the help of the endpoint descriptors. The base address of the endpoint descriptors needs to be written in the Descriptor Address register (DESCADD) by the user. Please refer the Endpoint Descriptor structure in "Endpoint Descriptor structure" on page 761. Before using an endpoint, the user should configure the direction and type of the endpoint in Type of Endpoint field in the Device Endpoint Configuration register (EPCFG.EPTYPE0/1). The endpoint descriptor registers should be initialized to known values before using the endpoint, so that the USB controller does not read the random values from the RAM. The Endpoint Size field in the Packet Size register (PCKSIZE.SIZE) should be configured as per the size reported to the host for that endpoint. The Address of Data Buffer register (ADDR) should be set to the data buffer used for endpoint transfers. The Ram Access Interrupt bit in Device Interrupt Flag register (INTFLAG.RAMACER) is set when a RAM access underflow error occurs during IN data stage. When an endpoint is disabled, the following registers are cleared for that endpoint: z Device Endpoint Interrupt Enable Clear/Set (EPINTENCLR/SET) register z Device Endpoint Interrupt Flag (EPINTFLAG) register z Transmit Stall 0 bit in the Endpoint Status register (EPSTATUS.STALLRQ0) z Transmit Stall 1 bit in the Endpoint Status register (EPSTATUS.STALLRQ1) 29.6.2.3 Multi-Packet Transfers Multi-packet transfer enables a data payload exceeding the endpoint maximum transfer size to be transferred as multiple packets without software intervention. This reduces the number of interrupts and software intervention required to manage higher level USB transfers. Multi-packet transfer is identical to the IN and OUT transactions described below unless otherwise noted in this section. The application software provides the size and address of the RAM buffer to be proceeded by the USB module for a specific endpoint, and the USB module will split the buffer in the required USB data transfers without any software intervention. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 707 Figure 29-3. Multi-Packet Feature - Reduction of CPU Overhead Data Payload Without Multi-packet support Transfer Complete Interrupt & Data Processing Maximum Endpoint size With Multi-packet support 29.6.2.4 USB Reset The USB bus reset is initiated by a connected host and managed by hardware. During USB reset the following registers are cleared: z Device Endpoint Configuration (EPCFG) register - except for Endpoint 0 z Device Frame Number (FNUM) register z Device Address (DADD) register z Device Endpoint Interrupt Enable Clear/Set (EPINTENCLR/SET) register z Device Endpoint Interrupt Flag (EPINTFLAG) register z Transmit Stall 0 bit in the Endpoint Status register (EPSTATUS.STALLRQ0) z Transmit Stall 1 bit in the Endpoint Status register (EPSTATUS.STALLRQ1) z Endpoint Interrupt Summary (EPINTSMRY) register z Upstream resume bit in the Control B register (CTRLB.UPRSM) At the end of the reset process, the End of Reset bit is set in the Interrupt Flag register (INTFLAG.EORST). 29.6.2.5 Start-of-Frame When a Start-of-Frame (SOF) token is detected, the frame number from the token is stored in the Frame Number field in the Device Frame Number register (FNUM.FNUM) and the Start-of-Frame interrupt bit in the Device Interrupt Flag register (INTFLAG.SOF) is set. If there is a CRC or bit-stuff error, the Frame Number Error status flag (FNUM.FNCERR) in the FNUM register is set. 29.6.2.6 Management of SETUP Transactions When a SETUP token is detected and the device address of the token packet does not match DADD.DADD the packet is discarded and the USB module returns to idle and waits for the next token packet. When the address matches, the USB module checks if the endpoint is enabled in EPCFG. If the addressed endpoint is disabled, the packet is discarded and the USB module returns to idle and waits for the next token packet. When the endpoint is enabled, the USB module then checks on the EPCFG of the addressed endpoint. If the EPCFG.EPTYPE0 is not set to control, the USB module returns to idle and waits for the next token packet. When the EPCFG.EPTYPE0 matches, the USB module then fetches the Data Buffer Address (ADDR) from the addressed endpoint's descriptor and waits for a DATA0 packet. If a PID error or any other PID than DATA0 is detected, the USB module returns to idle and waits for the next token packet. When the data PID matches and if Received Setup Complete interrupt bit in the Device Endpoint Interrupt Flag register (EPINTFLAG.RXSTP) is equal to zero, ignoring the Bank 0 Ready bit in the Device Endpoint Status register (EPSTATUS.BK0RDY), the incoming data is written to the data buffer pointed to by the Data Buffer Address (ADDR). If the number of received data bytes exceeds the endpoint's maximum data payload size as specified by the Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 708 PCKSIZE.SIZE, the remainders of the received data bytes are discarded. The packet will still be checked for bit-stuff and CRC errors. Software must never report a endpoint size to the host that is greater than the value configured in PCKSIZE.SIZE. If a bit-stuff or CRC error is detected in the packet, the USB module returns to idle and waits for the next token packet. If data is successfully received, an ACK handshake is returned to the host, and the number of received data bytes, excluding the CRC, is written to the Byte Count (PCKSIZE.BYTE_COUNT). If the number of received data bytes is the maximum data payload specified by PCKSIZE.SIZE, no CRC data is written to the data buffer. If the number of received data bytes is the maximum data payload specified by PCKSIZE.SIZE minus one, only the first CRC data is written to the data buffer. If the number of received data is equal or less than the data payload specified by PCKSIZE.SIZE minus two, both CRC data bytes are written to the data buffer. Finally the EPSTATUS is updated. Data Toggle OUT bit (EPSTATUS.DTGLOUT), the Data Toggle IN bit (EPSTATUS.DTGLIN), the current bank bit (EPSTATUS.CURRBK) and the Bank Ready 0 bit (EPSTATUS.BK0RDY) are set. Bank Ready 1 bit (EPSTATUS.BK1RDY) and the Stall Bank 0/1 bit (EPSTATUS.STALLQR0/1) are cleared on receiving the SETUP request. The RXSTP bit is set and triggers an interrupt if the Received Setup Interrupt Enable bit is set in Endpoint Interrupt Enable Set/Clear register (EPINTENSET/CLR.RXSTP). 29.6.2.7 Management of OUT Transactions Figure 29-4. OUT Transfer: Data Packet Host to USB Device Memory Map HOST I/O Register USB I/O Registers BULK OUT EPT 2 D A T A 0 D A T A 1 D A T A 0 BULK OUT EPT 3 D A T A 0 D A T A 1 D A T A 0 D A T A 1 BULK OUT EPT 1 D A T A 0 D A T A 0 D A T A 1 Internal RAM USB Module USB Endpoints Descriptor Table D A T A 0 DESCADD ENDPOINT 1 DATA ENDPOINT 3 DATA DP DM USB Buffers time ENDPOINT 2 DATA When a OUT token is detected and the device address of the token packet does not match DADD.DADD, the packet is discarded and the USB module returns to idle and waits for the next token packet. If the address matches, the USB module checks if the endpoint number received is enabled in the EPCFG of the addressed endpoint. If the addressed endpoint is disabled, the packet is discarded and the USB module returns to idle and waits for the next token packet. When the endpoint is enabled, the USB module then checks the Endpoint Configuration register (EPCFG) of the addressed output endpoint. If the type of the endpoint (EPCFG.EPTYPE0) is not set to OUT, the USB module returns to idle and waits for the next token packet. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 709 The USB module then fetches the Data Buffer Address (ADDR) from the addressed endpoint's descriptor, and waits for a DATA0 or DATA1 packet. If a PID error or any other PID than DATA0 or DATA1 is detected, the USB module returns to idle and waits for the next token packet. If EPSTATUS.STALLRQ0 in EPSTATUS is set, the incoming data is discarded. If the endpoint is not isochronous, a STALL handshake is returned to the host and the Transmit Stall Bank 0 interrupt bit in EPINTFLAG (EPINTFLAG.STALL0) is set. For isochronous endpoints, data from both a DATA0 and DATA1 packet will be accepted. For other endpoint types the PID is checked against EPSTATUS.DTGLOUT. If a PID mismatch occurs, the incoming data is discarded, and an ACK handshake is returned to the host. If EPSTATUS.BK0RDY is set, the incoming data is discarded, the bit Transmit Fail 0 interrupt bit in EPINTFLAG (EPINTFLAG.TRFAIL0) and the status bit STATUS_BK.ERRORFLOW are set. If the endpoint is not isochronous, a NAK handshake is returned to the host. The incoming data is written to the data buffer pointed to by the Data Buffer Address (ADDR). If the number of received data bytes exceeds the maximum data payload specified as PCKSIZE.SIZE, the remainders of the received data bytes are discarded. The packet will still be checked for bit-stuff and CRC errors. If a bit-stuff or CRC error is detected in the packet, the USB module returns to idle and waits for the next token packet. If the endpoint is isochronous and a bit-stuff or CRC error in the incoming data, the number of received data bytes, excluding CRC, is written to PCKSIZE.BYTE_COUNT. Finally the EPINTFLAG.TRFAIL0 and CRC Error bit in the Device Bank Status register (STATUS_BK.CRCERR) is set for the addressed endpoint. If data was successfully received, an ACK handshake is returned to the host if the endpoint is not isochronous, and the number of received data bytes, excluding CRC, is written to PCKSIZE.BYTE_COUNT. If the number of received data bytes is the maximum data payload specified by PCKSIZE.SIZE no CRC data bytes are written to the data buffer. If the number of received data bytes is the maximum data payload specified by PCKSIZE.SIZE minus one, only the first CRC data byte is written to the data buffer If the number of received data is equal or less than the data payload specified by PCKSIZE.SIZE minus two, both CRC data bytes are written to the data buffer. Finally in EPSTATUS for the addressed output endpoint, EPSTATUS.BK0RDY is set and EPSTATUS.DTGLOUT is toggled if the endpoint is not isochronous. The flag Transmit Complete 0 interrupt bit in EPINTFLAG (EPINTFLAG.TRCPT0) is set for the addressed endpoint. 29.6.2.8 Multi-Packet Transfers for OUT Endpoint The number of data bytes received is stored in endpoint PCKSIZE.BYTE_COUNT as for normal operation. Since PCKSIZE.BYTE_COUNT is updated after each transaction, it must be set to zero when setting up a new transfer. The total number of bytes to be received must be written to PCKSIZE.MULTI_PACKET_SIZE. This value must be a multiple of PCKSIZE.SIZE, otherwise excess data may be written to SRAM locations used by other parts of the application. EPSTATUS.DTGLOUT management for non-isochronous packets and EPINTFLAG.BK1RDY/BK0RDY management are as for normal operation. If a maximum payload size packet is received, PCKSIZE.BYTE_COUNT will be incremented by PCKSIZE.SIZE after the transaction has completed, and EPSTATUS.DTGLOUT will be toggled if the endpoint is not isochronous. If the updated PCKSIZE.BYTE_COUNT is equal to PCKSIZE.MULTI_PACKET_SIZE (i.e. the last transaction), EPSTATUS.BK1RDY/BK0RDY, and EPINTFLAG.TRCPT0/TRCPT1 will be set. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 710 29.6.2.9 Management of IN Transactions Figure 29-5. IN Transfer: Data Packet USB Device to Host After Request from Host Memory Map I/O Register HOST USB I/O Registers CPU Internal RAM EPT 2 D A T A 0 D A T A 1 EPT 3 D A T A 0 D A T A 0 D A T A 1 D A T A 0 D A T A 1 USB Module EPT 1 D A T A 0 D A T A 0 D A T A 1 DP DM ENDPOINT 2 DATA DESCADD USB Endpoints Descriptor Table D A T A 0 ENDPOINT 3 DATA USB Buffers EPT 2 I N T O K E N I N I N EPT 3 T EPT 1 T O K E N O K E N ENDPOINT 1 DATA time When a IN token is detected and if the device address of the token packet does not match DADD.DADD, the packet is discarded and the USB module returns to idle and waits for the next token packet. When the address matches, the USB module checks if the endpoint received is enabled in the EPCFG of the addressed endpoint and if not the packet is discarded and the USB module returns to idle and waits for the next token packet. When the endpoint is enabled, the USB module then checks on the EPCFG of the addressed input endpoint. If the EPCFG.EPTYPE1 is not set to IN, the USB module returns to idle and waits for the next token packet. If EPSTATUS.STALLRQ1 in EPSTATUS is set, and the endpoint is not isochronous, a STALL handshake is returned to the host and EPINTFLAG.STALL1 is set. If EPSTATUS.BK1RDY is cleared, the flag EPINTFLAG.TRFAIL1 is set. If the endpoint is not isochronous, a NAK handshake is returned to the host. The USB module then fetches the Data Buffer Address (ADDR) from the addressed endpoint's descriptor. The data pointed to by the Data Buffer Address (ADDR) is sent to the host in a DATA0 packet if the endpoint is isochronous. For non-isochronous endpoints a DATA0 or DATA1 packet is sent depending on the state of EPSTATUS.DTGLIN. When the number of data bytes specified in endpoint PCKSIZE.BYTE_COUNT is sent, the CRC is appended and sent to the host. For isochronous endpoints, EPSTATUS.BK1RDY is cleared and EPINTFLAG.TRCPT1 is set. For all non-isochronous endpoints the USB module waits for an ACK handshake from the host. If an ACK handshake is not received within 16 bit times, the USB module returns to idle and waits for the next token packet. If an ACK handshake is successfully received EPSTATUS.BK1RDY is cleared, EPINTFLAG.TRCPT1 is set and EPSTATUS.DTGLIN is toggled. Figure 29-6. 29.6.2.10 Multi-Packet Transfers for IN Endpoint The total number of data bytes to be sent is written to PCKSIZE.BYTE_COUNT as for normal operation. The Multipacket size register (PCKSIZE.MULTI_PACKET_SIZE) is used to store the number of bytes that are sent, and must be written to zero when setting up a new transfer. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 711 When an IN token is received, PCKSIZE.BYTE_COUNT and PCKSIZE.MULTI_PACKET_SIZE are fetched. If PCKSIZE.BYTE_COUNT minus PCKSIZE.MULTI_PACKET_SIZE is less than the endpoint PCKSIZE.SIZE, endpoint BYTE_COUNT minus endpoint PCKSIZE.MULTI_PACKET_SIZE bytes are transmitted, otherwise PCKSIZE.SIZE number of bytes are transmitted. If endpoint PCKSIZE.BYTE_COUNT is a multiple of PCKSIZE.SIZE, the last packet sent will be zero-length if the AUTOZLP bit is set. If a maximum payload size packet was sent (i.e. not the last transaction), MULTI_PACKET_SIZE will be incremented by the PCKSIZE.SIZE. If the endpoint is not isochronous the EPSTATUS.DTLGIN bit will be toggled when the transaction has completed. If a short packet was sent (i.e. the last transaction), MULTI_PACKET_SIZE is incremented by the data payload. EPSTATUS.BK0/1RDY will be cleared and EPINTFLAG.TRCPT0/1 will be set. 29.6.2.11 Ping-Pong Operation When an endpoint is configured for ping-pong operation, it uses both the input and output data buffers (banks) for a given endpoint in a single direction. The direction is selected by enabling one of the IN or OUT direction in EPCFG.EPTYPE0/1 and configuring the opposite direction in EPCFG.EPTYPE1/0 as Dual Bank. When ping-pong operation is enabled for an endpoint, the endpoint in the opposite direction must be configured as dual bank. The data buffer, data address pointer and byte counter from the enabled endpoint are used as Bank 0, while the matching registers from the disabled endpoint are used as Bank 1. Figure 29-7. Ping-Pong Overview Without Ping Pong Endpoint single bank t Endpoint dual bank Bank0 With Ping Pong Bank1 t USB data packet Available time for data processing by CPU to avoid NACK The Bank Select flag in EPSTATUS.CURBK indicates which bank data will be used in the next transaction, and is updated after each transaction. According to EPSTATUS.CURBK, EPINTFLAG.TRCPT0 or EPINTFLAG.TRFAIL0 or EPINTFLAG.TRCPT1 or EPINTFLAG.TRFAIL1 in EPINTFLAG and Data Buffer 0/1 ready (EPSTATUS.BK0RDY and EPSTATUS.BK1RDY) are set. The EPSTATUS.DTGLOUT and EPSTATUS.DTGLIN are updated for the enabled endpoint direction only. 29.6.2.12 Feedback Operation Feedback endpoints are endpoints with same address but in different direction. This is usually used in explicit feedback mechanism in USB Audio, where a feedback endpoint is associated to one or more isochronous data endpoints to which it provides feedback service. The feedback endpoint always has the opposite direction from the data endpoint. The feedback endpoint always has the opposite direction from the data endpoint(s). The feedback endpoint has the same endpoint number as the first (lower) data endpoint. A feedback endpoint can be created by configuring an endpoint with different endpoint size (PCKSIZE.SIZE) and different endpoint type (EPCFG.EPTYPE0/1) for the IN and OUT direction. Example Configuration for Feedback Operation: Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 712 Endpoint n / IN: EPCFG.EPTYPE1 = Interrupt IN, PCKSIZE.SIZE = 64. Endpoint n / OUT: EPCFG.EPTYPE0= Isochronous OUT, PCKSIZE.SIZE = 512. 29.6.2.13 Suspend State and Pad Behavior Figure 29-8 illustrates the behavior of the USB pad in device mode. Figure 29-8. Pad Behavior CTRLA.ENABLE = 1 | CTRLB.DETACH = 0 | INTFLAG.SUSPEND = 0 Idle CTRLA.ENABLE = 0 | CTRLB.DETACH = 1 | INTFLAG.SUSPEND = 1 Active In Idle state, the pad is in low power consumption mode. In Active state, the pad is active. Figure 29-9 illustrates the pad events leading to a PAD state change. Figure 29-9. Pad Events SUSPEND Suspend detected Cleared on Wakeup Wakeup detected WAKEUP Cleared by software to acknowledge the interrupt PAD state Active Idle Active The Suspend Interrupt bit in the Device Interrupt Flag register (INTFLAG.SUSPEND) is set when a USB Suspend state has been detected on the USB bus. The USB pad is then automatically put in the Idle state. The detection of a non-idle state sets the Wake Up Interrupt bit in INTFLAG(INTFLAG.WAKEUP) and wakes the USB pad. The pad goes to the Idle state if the USB module is disabled or if CTRLB.DETACH is written to one. It returns to the Active state when CTRLA.ENABLE is written to one and CTRLB.DETACH is written to zero. 29.6.2.14 Remote Wakeup The remote wakeup request (also known as upstream resume) is the only request the device may send on its own initiative. This should be preceded by a DEVICE_REMOTE_WAKEUP request from the host. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 713 First, the USB must have detected a "Suspend" state on the bus, i.e. the remote wakeup request can only be sent after INTFLAG.SUSPEND has been set. The user may then write a one to the Remote Wakeup bit in CTRLB(CTRLB.UPRSM) to send an Upstream Resume to the host initiating the wakeup. This will automatically be done by the controller after 5 ms of inactivity on the USB bus. When the controller sends the Upstream Resume INTFLAG.WAKEUP is set and INTFLAG.SUSPEND is cleared. The CTRLB.UPRSM is cleared at the end of the transmitting Upstream Resume. In case of a rebroadcast resume initiated by the host, the End of Resume bit in INTFLAG(INTFLAG.EORSM) flag is set when the rebroadcast resume is completed. In the case where the CTRLB.UPRSM bit is set while a host initiated downstream resume is already started, the CTRLB.UPRSM is cleared and the upstream resume request is ignored. 29.6.2.15 Link Power Management L1 (LPM-L1) Suspend State Entry and Exit as Device The LPM Handshake bit in CTRLB.LPMHDSK should be configured to accept the LPM transaction. When a LPM transaction is received on any enabled endpoint n and a handshake has been sent in response by the controller according to CTRLB.LPMHDSK, the Device Link Power Manager (EXTREG) register is updated in the bank 0 of the addressed endpoint's descriptor. It contains information such as the Best Effort Service Latency (BESL), the Remote Wake bit (bRemoteWake), and the Link State parameter (bLinkState). If the LPM transaction was positively acknowledged (ACK handshake), USB sets the Link Power Management Interrupt bit in INTFLAG(INTFLAG.LPMSUSP) bit which indicates that the USB transceiver is suspended, reducing power consumption. This suspend occurs 9 microseconds after the LPM transaction according to the specification. To further reduce consumption, it is recommended to stop the USB clock while the device is suspended. The MCU can also enter in one of the available sleep modes if the wakeup time latency of the selected sleep mode complies with the host latency constraint (see the BESL parameter in EXTREG). Recovering from this LPM-L1 suspend state is exactly the same as the Suspend state (see Section "Suspend State and Pad Behavior" on page 713) except that the remote wakeup duration initiated by USB is shorter to comply with the Link Power Management specification. If the LPM transaction is responded with a NYET, the Link Power Management Not Yet Interrupt Flag INTFLAG(INTFLAG.LPMNYET) is set. This generates an interrupt if the Link Power Management Not Yet Interrupt Enable bit in INTENCLR/SET (INTENCLR/SET.LPMNYET) is set. If the LPM transaction is responded with a STALL or no handshake, no flag is set, and the transaction is ignored. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 714 29.6.2.16 USB Device Interrupt EPINTFLAG7.STALL EPINTENSET7.STALL0/STALL1 EPINTFLAG7.TRFAIL1 EPINTENSET7.TRFAIL1 EPINTFLAG7.TRFAIL0 EPINTENSET7.TRFAIL0 ENDPOINT7 EPINTFLAG7.RXSTP EPINTSMRY EPINT7 EPINTENSET7.RXSTP EPINT6 EPINTFLAG7.TRCPT1 EPINTENSET7.TRCPT1 EPINTFLAG7.TRCPT0 EPINTENSET7.TRCPT0 USB EndPoint Interrupt EPINTFLAG0.STALL EPINTENSET0.STALL0/STALL1 EPINTFLAG0.TRFAIL1 EPINTENSET0.TRFAIL1 EPINTFLAG0.TRFAIL0 EPINTENSET0.TRFAIL0 EPINTFLAG0.RXSTP ENDPOINT0 EPINT1 EPINT0 EPINTENSET0.RXSTP EPINTFLAG0.TRCPT1 EPINTENSET0.TRCPT1 EPINTFLAG0.TRCPT0 USB Interrupt EPINTENSET0.TRCPT0 INTFLAG.LPMSUSP INTENSET.LPMSUSP INTFLAG.LPMNYET INTENSET.DDISC INTFLAG.RAMACER INTENSET.RAMACER INTFLAG.UPRSM INTFLAG INTENSET.UPRSM INTFLAG.EORSM USB Device Interrupt INTENSET.EORSM INTFLAG.WAKEUP * INTENSET.WAKEUP INTFLAG.EORST INTENSET.EORST INTFLAG.SOF INTENSET.SOF INTFLAGA.MSOF INTENSET.MSOF INTFLAG.SUSPEND INTENSET.SUSPEND * Asynchronous interrupt The WAKEUP is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 715 29.6.3 Host Operations This section gives an overview of the USB module Host operation during normal transactions. For more details on general USB and USB protocol, refer to Universal Serial Bus Specification revision 2.1. 29.6.3.1 Device Detection and Disconnection Prior to device detection the software must set the VBUS is OK bit in CTRLB (CTRLB.VBUSOK) register when the VBUS is available. This notifies the USB host that USB operations can be started. When the bit CTRLB.VBUSOK is zero and even if the USB HOST is configured and enabled, host operation is halted. Setting the bit CTRLB.VBUSOK will allow host operation when the USB is configured. The Device detection is managed by the software using the Line State field in the Host Status (STATUS.LINESTATE) register. The device connection is detected by the host controller when DP or DM is pulled high, depending of the speed of the device. The device disconnection is detected by the host controller when both DP and DM are pulled down using the STATUS.LINESTATE registers. The Device Connection Interrupt bit in INTFLAG (INTFLAG.DCONN) is set if a device connection is detected. The Device Disconnection Interrupt bit in INTFLAG (INTFLAG.DDISC) is set if a device disconnection is detected. 29.6.3.2 Host Terminology In host mode, the term pipe is used instead of endpoint. A host pipe corresponds to a device endpoint, refer to "Universal Serial Bus Specification revision 2.1." for more information. 29.6.3.3 USB Reset The USB sends a USB reset signal when the user writes a one to the USB Reset bit in CTRLB (CTRLB.BUSRESET). When the USB reset has been sent, the USB Reset Sent Interrupt bit in the INTFLAG (INTFLAG.RST) is set and all pipes will be disabled. If the bus was previously in a suspended state (Start of Frame Generation Enable bit in CTRLB (CTRLB.SOFE) is zero) the USB will switch it to the Resume state, causing the bus to asynchronously set the Host Wakeup Interrupt flag (INTFLAG.WAKEUP). The CTRLB.SOFE bit will be set in order to generate SOFs immediately after the USB reset. During USB reset the following registers are cleared: z All Host Pipe Configuration register (PCFG) z Host Frame Number register (FNUM) z Interval for the Bulk-Out/Ping transaction register (BINTERVAL) z Host Start-of-Frame Control register (HSOFC) z Pipe Interrupt Enable Clear/Set register (PINTENCLR/SET) z Pipe Interrupt Flag register (PINTFLAG) z Pipe Freeze bit in Pipe Status register (PSTATUS.FREEZE) After the reset the user should check the Speed Status field in the Status register (STATUS.SPEED) to find out the current speed according to the capability of the peripheral. 29.6.3.4 Pipe Configuration Pipe data can be placed anywhere in the RAM. The USB controller accesses these pipes directly through the AHB master (built-in DMA) with the help of the pipe descriptors. The base address of the pipe descriptors needs to be written in the Descriptor Address register (DESCADD) by the user. Please refer the Pipe Descriptor structure in "Pipe Descriptor Structure" on page 793. Before using a pipe, the user should configure the direction and type of the pipe in Type of Pipe field in the Host Pipe Configuration register (PCFG.PTYPE). The pipe descriptor registers should be initialized to known values before using the pipe, so that the USB controller does not read the random values from the RAM. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 716 The Pipe Size field in the Packet Size register (PCKSIZE.SIZE) should be configured as per the size reported by the device for the endpoint associated with this pipe. The Address of Data Buffer register (ADDR) should be set to the data buffer used for pipe transfers. The Pipe Bank bit in PCFG (PCFG.BK) should be set to one if dual banking is desired. Dual bank is not supported for Control pipes. The Ram Access Interrupt bit in Host Interrupt Flag register (INTFLAG.RAMACER) is set when a RAM access underflow error occurs during an OUT stage. When a pipe is disabled, the following registers are cleared for that pipe: z Interval for the Bulk-Out/Ping transaction register (BINTERVAL) z Pipe Interrupt Enable Clear/Set register (PINTENCLR/SET) z Pipe Interrupt Flag register (PINTFLAG) z Pipe Freeze bit in Pipe Status register (PSTATUS.FREEZE) 29.6.3.5 Pipe Activation A disabled pipe is inactive, and will be reset along with its context registers (pipe registers for the pipe n). Pipes are enabled by writing Type of the Pipe in PCFG (PCFG.PTYPE) to a value different than 0x0 (disabled). When a pipe is enabled, the Pipe Freeze bit in Pipe Status register (PSTATUS.FREEZE) is set. This allow the user to complete the configuration of the pipe, without starting a USB transfer. When starting an enumeration, the user retrieves the device descriptor by sending an GET_DESCRIPTOR USB request. This descriptor contains the maximal packet size of the device default control endpoint (bMaxPacketSize0) which the user should use to reconfigure the size of the default control pipe. 29.6.3.6 Pipe Address Setup Once the device has answered the first host requests with the default device address 0, the host assigns a new address to the device. The host controller has to send a USB reset to the device and a SET_ADDRESS(addr) SETUP request with the new address to be used by the device. Once this SETUP transaction is complete, the user writes the new address to the Pipe Device Address field in the Host Control Pipe register (CTRL_PIPE.PDADDR) in Pipe descriptor. All following requests by this pipe will be performed using this new address. 29.6.3.7 Suspend and Wakeup Writing CTRLB.SOFE to zero when in host mode will cause the USB to cease sending Start-of-Frames on the USB bus and enter the Suspend state. The USB device will enter the Suspend state 3ms later. Before entering suspend by writing CTRLB.SOFE to zero, the user must freeze the active pipes by setting their PSTATUS.FREEZE bit. Any current on-going pipe will complete its transaction, and then all pipes will be inactive. The user should wait at least 1 complete frame before entering the suspend mode to avoid any data loss. The device can awaken the host by sending an Upstream Resume (Remote Wakeup feature). When the host detects a non-idle state on the USB bus, it sets the INTFLAG.WAKEUP. If the non-idle bus state corresponds to an Upstream Resume (K state), the Upstream Resume Received Interrupt bit in INTFLAG (INTFLAG.UPRSM) is set and the user must generate a Downstream Resume within 1 ms and for at least 20 ms. It is required to first write a one to the Send USB Resume bit in CTRLB (CTRLB.RESUME) to respond to the upstream resume with a downstream resume. Alternatively, the host can resume from a suspend state by sending a Downstream Resume on the USB bus (CTRLB.RESUME set to 1). In both cases, when the downstream resume is completed, the CTRLB.SOFE bit is automatically set and the host enters again the active state. 29.6.3.8 Phase-locked SOFs To support the Synchronous Endpoints capability, the period of the emitted Start-of-Frame is maintained while the USB connection is not in the active state. This does not apply for the disconnected/connected/reset states. It applies for active/idle/suspend/resume states. The period of Start-of-Frame will be 1ms when the USB connection is in active state and an integer number of milli-seconds across idle/suspend/resume states. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 717 To ensure the Synchronous Endpoints capability, the GCLK_USB clock must be kept running. If the GCLK_USB is interrupted, the period of the emitted Start-of-Frame will be erratic. 29.6.3.9 Management of Control Pipes A control transaction is composed of three stages: z SETUP z Data (IN or OUT) z Status (IN or OUT) The user has to change the pipe token according to each stage using the Pipe Token field in PCFG (PCFG.PTOKEN). For control pipes only, the token is assigned a specific initial data toggle sequence: z SETUP: Data0 z IN: Data1 z OUT: Data1 29.6.3.10 Management of IN Pipes IN packets are sent by the USB device controller upon IN request reception from the host. All the received data from the device to the host will be stored in the bank provided the bank is empty. The pipe and its descriptor in RAM must be configured. The host indicates it is able to receive data from the device by clearing the Bank 0/1 Ready bit in PSTATUS (PSTATUS.BK0/1RDY), which means that the memory for the bank is available for new USB transfer. The USB will perform IN requests as long as the pipe is not frozen by the user. The generation of IN requests starts when the pipe is unfrozen (PSTATUS.PFREEZE is set to zero). When the current bank is full, the Transmit Complete 0/1 bit in PINTFLAG (PINTFLAG.TRCPT0/1) will be set and trigger an interrupt if enabled and the PSTATUS.BK0/1RDY bit will be set. PINTFLAG.TRCPT0/1 must be cleared by software to acknowledge the interrupt. This is done by writing a one to the PINTFLAG.TRCPT0/1 of the addressed pipe. The user reads the PCKSIZE.BYTE_COUNT to know how many bytes should be read. To free the bank the user must read the IN data from the address ADDR in the pipe descriptor and clear the PKSTATUS.BK0/1RDY bit. When the IN pipe is composed of multiple banks, a successful IN transaction will switch to the next bank. Another IN request will be performed by the host as long as the PSTATUS.BK0/1RDY bit for that bank is set. The PINTFLAG.TRCPT0/1 and PSTATUS.BK0/1RDY will be updated accordingly. The user can follow the current bank looking at Current Bank bit in PSTATUS (PSTATUS.CURBK) and by looking at Data Toggle for IN pipe bit in PSTATUS (PSTATUS.DTGLIN). When the pipe is configured as single bank (Pipe Bank bit in PCFG (PCFG.BK) is 0), only PINTFLAG.TRCPT0 and PSTATUS.BK0 are used. When the pipe is configured as dual bank (PCFG.BK is 1), both PINTFLAG.TRCPT0/1 and PSTATUS.BK0/1 are used. 29.6.3.11 Management of OUT Pipes OUT packets are sent by the host. All the data stored in the bank will be sent to the device provided the bank is filled. The pipe and its descriptor in RAM must be configured. The host can send data to the device by writing to the data bank 0 in single bank or the data bank 0/1 in dual bank. The generation of OUT packet starts when the pipe is unfrozen (PSTATUS.PFREEZE is zero). The user writes the OUT data to the data buffer pointer by ADDR in the pipe descriptor and allows the USB to send the data by writing a one to the PSTATUS.BK0/1RDY. This will also cause a switch to the next bank if the OUT pipe is part of a dual bank configuration. PINTFLAGn.TRCPT0/1 must be cleared before setting PSTATUS.BK0/1RDY to avoid missing an PINTFLAGn.TRCPT0/1 event. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 718 29.6.3.12 Alternate Pipe The user has the possibility to run sequentially several logical pipes on the same physical pipe. It allows addressing of any device endpoint of any attached device on the bus. Before switching pipe, the user should save the pipe context (Pipe registers and descriptor for pipe n). After switching pipe, the user should restore the pipe context (Pipe registers and descriptor for pipe n) and in particular PCFG, and PSTATUS. 29.6.3.13 Data Flow Error This error exists only for isochronous and interrupt pipes for both IN and OUT directions. It sets the Transmit Fail bit in PINTFLAG (PINTFLAG.TRFAIL), which triggers an interrupt if the Transmit Fail bit in PINTENCLR/SET(PINTENCLR/SET.TRFAIL) is set. The user must check the Pipe Interrupt Summary register (PINTSMRY) to find out the pipe which triggered the interrupt.Then the user must check the origin of the interrupt's bank by looking at the Pipe Bank Status register (STATUS_BK) for each bank. If the Error Flow bit in the STATUS_BK (STATUS_BK.ERRORFLOW) is set then the user is able to determine the origin of the data flow error. As the user knows that the endpoint is an IN or OUT the error flow can be deduced as OUT underflow or as an IN overflow. An underflow can occur during an OUT stage if the host attempts to send data from an empty bank. If a new transaction is successful, the relevant bank descriptor STATUS_BK.ERRORFLOW will be cleared. An overflow can occur during an IN stage if the device tries to send a packet while the bank is full. Typically this occurs when a CPU is not fast enough. The packet data is not written to the bank and is lost. If a new transaction is successful, the relevant bank descriptor STATUS_BK.ERRORFLOW will be cleared. 29.6.3.14 CRC Error This error exists only for isochronous IN pipes. It sets the PINTFLAG.TRFAIL, which triggers an interrupt if PINTENCLR/SET.TRFAIL is set. The user must check the PINTSMRY to find out the pipe which triggered the interrupt. Then the user must check the origin of the interrupt's bank by looking at the bank descriptor STATUS_BK for each bank and if the CRC Error bit in STATUS_BK (STATUS_BK.CRCERR) is set then the user is able to determine the origin of the CRC error. A CRC error can occur during the IN stage if the USB detects a corrupted packet. The IN packet will remain stored in the bank and PINTFLAG.TRCPT0/1 will be set. 29.6.3.15 PERR Error This error exists for all pipes. It sets the PINTFLAG.PERR Interrupt, which triggers an interrupt if PINTFLAG.PERR is set. The user must check the PINTSMRY register to find out the pipe which can cause an interrupt. A PERR error occurs if one of the error field in the STATUS_PIPE register in the Host pipe descriptor is set and the Error Count field in STATUS_PIPE (STATUS_PIPE.ERCNT) exceeds the maximum allowed number of Pipe error(s) as defined in Pipe Error Max Number field in CTRL_PIPE (CTRL_PIPE.PERMAX). Refer to section STATUS_PIPE. If one of the error field in the STATUS_PIPE register from the Host Pipe Descriptor is set and the STATUS_PIPE.ERCNT is less than the CTRL_PIPE.PERMAX, the STATUS_PIPE.ERCNT is incremented. 29.6.3.16 Link Power Management L1 (LPM-L1) Suspend State Entry and Exit as Host. An EXTENDED LPM transaction can be transmitted by any enabled pipe. The PCFGn.PTYPE should be set to EXTENDED. Other fields as PCFG.PTOKEN, PCFG.BK PCKSIZE.SIZE are irrelevant in this configuration. The user should also set the EXTREG.VARIABLE in the descriptor as described in EXTREG. When the pipe is configured and enabled, an EXTENDED TOKEN followed by a LPM TOKEN are transmitted. The device responds with a valid HANDSHAKE, corrupted HANDSHAKE or no HANDSHAKE (TIME-OUT). If the valid HANDSHAKE is an ACK, the host will immediately proceed to L1 SLEEP and the PINTFLAG.TRCT0 is set. The minimum duration of the L1 SLEEP state will be the TL1RetryAndResidency as defined in the reference document "ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum". When entering the L1 SLEEP state, the CTRLB.SOFE is cleared, avoiding Start-of-Frame generation. If the valid HANDSHAKE is a NYET PINTFLAG.TRFAIL is set. If the valid HANDSHAKE is a STALL the PINTFLAG.STALL is set. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 719 If there is no HANDSHAKE or corrupted HANDSHAKE, the EXTENDED/LPM pair of TOKENS will be transmitted again until reaching the maximum number of retries as defined by the CTRL_PIPE.PERMAX in the pipe descriptor. If the last retry returns no valid HANDSHAKE, the PINTFLAGn.PERR is set, and the STATUS_BK is updated in the pipe descriptor. All LPM transactions, should they end up with a ACK, a NYET, a STALL or a PERR, will set the PSTATUS.PFREEZE bit, freezing the pipe before a succeeding operation. The user should unfreeze the pipe to start a new LPM transaction. To exit the L1 STATE, the user initiate a DOWNSTREAM RESUME by setting the bit CTRLB.RESUME or a L1 RESUME by setting the Send L1 Resume bit in CTRLB (CTRLB.L1RESUME). In the case of a L1 RESUME, the K STATE duration is given by the BESL bit field in the EXTREG.VARIABLE field. See EXTREG. When the host is in the L1 SLEEP state after a successful LPM transmitted, the device can initiate an UPSTREAM RESUME. This will set the Upstream Resume Interrupt bit in INTFLAG (INTFLAG.UPRSM). The host should proceed then to a L1 RESUME as described above. After resuming from the L1 SLEEP state, the bit CTRLB.SOFE is set, allowing Start-of-Frame generation. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 720 29.6.3.17 Host Interrupt PINTFLAG7.STALL PINTENSET.STALL PINTFLAG7.PERR PINTENSET.PERR PINTFLAG7.TRFAIL PINTENSET.TRFAIL PIPE7 PINTFLAG7.TXSTP PINTSMRY PINT7 PINTENSET.TXSTP PINT6 PINTFLAG7.TRCPT1 PINTENSET.TRCPT1 PINTFLAG7.TRCPT0 PINTENSET.TRCPT0 USB PIPE Interrupt PINTFLAG0.STALL PINTENSET.STALL PINTFLAG0.PERR PINTENSET.PERR PINTFLAG0.TRFAIL PINTENSET.TRFAIL PINTFLAG0.TXSTP PIPE0 PINT1 PINT0 PINTENSET.TXSTP PINTFLAG0.TRCPT1 PINTENSET.TRCPT1 PINTFLAG0.TRCPT0 USB Interrupt PINTENSET.TRCPT0 INTFLAG.DDISC * INTENSET.DDISC INTFLAG.DCONN * INTENSET.DCONN INTFLAG.RAMACER INTFLAG INTENSET.RAMACER INTFLAG.UPRSM USB Host Interrupt INTENSET.UPRSM INTFLAG.DNRSM INTENSET.DNRSM INTFLAG.WAKEUP * INTENSET.WAKEUP INTFLAG.RST INTENSET.RST INTFLAG.HSOF INTENSET.HSOF * Asynchronous interrupt The WAKEUP is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 721 29.7 Register Summary The register mapping depends on the Operating Mode field in the Control A register (CTRLA.MODE). The register summary is detailed below. 29.7.1 Common Device Host Summary Table 29-1. Common Register Summary Offset Name Bit Pos. 0x00 CTRLA 7:0 0x01 Reserved 0x02 SYNCBUSY 7:0 0x03 QOSCTRL 7:0 0x0D FSMSTATUS 7:0 0x24 MODE RUNSTBY DQOS[1:0] SWRST ENABLE SWRST CQOS[1:0] FSMSTATE[6:0] 7:0 DESCADD[7:0] 15:8 DESCADD[15:8] 0x26 23:16 DESCADD[23:16] 0x27 31:24 DESCADD[31:24] 0x25 ENABLE DESCADD 0x28 7:0 TRANSN[1:0] TRANSP[4:0] PADCAL 0x29 15:8 TRIM[2:0] TRANSN[4:2] 29.7.2 Device Summary Table 29-2. General Device Registers Summary Offset Name 0x04 Reserved 0x05 Reserved 0x06 Reserved 0x07 Reserved 0x08 Bit Pos. 7:0 NREPLY SPDCONF[1:0] UPRSM LPMHDSK[1:0] GNAK DETACH CTRLB 0x09 15:8 0x0A DADD 0x0B Reserved 0x0C STATUS 0x0E Reserved 0x0F Reserved 0x10 ADDEN 7:0 DADD[6:0] LINESTATE[1:0] 7:0 SPEED[1:0] FNUM[4:0] FNUM 0x11 0x12 15:8 FNCERR 7:0 RAMACER FNUM[10:5] Reserved 0x14 UPRSM EORSM WAKEUP EORST SOF SUSPEND INTENCLR 0x15 15:8 0x16 Reserved 0x17 Reserved LPMSUSP LPMNYET Offset Name 0x18 Bit Pos. 7:0 RAMACER UPRSM EORSM WAKEUP EORST SOF SUSPEND INTENSET 0x19 15:8 0x1A Reserved 0x1B Reserved 0x1C 7:0 LPMSUSP RAMACER UPRSM EORSM WAKEUP EORST SOF LPMNYET SUSPEND INTFLAG 0x1D 15:8 0x1E Reserved 0x1F Reserved 0x20 LPMSUSP 7:0 EPINT[7:0] 15:8 EPINT[15:8] LPMNYET EPINTSMRY 0x21 0x22 Reserved 0x23 Reserved Table 29-3. Device endpoint Register n Offset Name Bit Pos. 0x1m0 EPCFGx 7:0 EPTYPE1[1:0] EPTYPE0[1:0] 0x1m1 Reserved 0x1m2 Reserved 0x1m3 Reserved 0x1m4 EPSTATUSCLR 7:0 BK1RDY BK0RDY STALLRQ1 STALLRQ0 CURBK DTGLIN DTGLOUT 0x1m5 EPSTATUSSET 7:0 BK1RDY BK0RDY STALLRQ1 STALLRQ0 CURBK DTGLIN DTGLOUT 0x1m6 EPSTATUS 7:0 BK1RDY BK0RDY STALLRQ1 STALLRQ0 CURBK DTGLIN DTGLOUT 0x1m7 EPINTFLAG 7:0 STALL1 STALL0 RXSTP TRFAIL1 TRFAIL0 TRCPT1 TRCPT0 0x1m8 EPINTENCLR 7:0 STALL1 STALL0 RXSTP TRFAIL1 TRFAIL0 TRCPT1 TRCPT0 0x1m9 EPINTENSET 7:0 STALL1 STALL0 RXSTP TRFAIL1 TRFAIL0 TRCPT1 TRCPT0 0x1mA Reserved 0x1mB Reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 723 Table 29-4. Device endpoint n Descriptor Bank 0 Offset 0x n0 + index Name 0x00 Bit Pos. 7:0 ADD[7:0] 15:8 ADD[15:8] 0x02 23:16 ADD[23:16] 0x03 31:24 ADD[31:24] 0x04 7:0 BYTE_COUNT[7:0] 0x01 ADDR 0x05 15:8 MULTI_PACKET_SIZE[1:0] BYTE_COUNT[13:8] PCKSIZE 0x06 23:16 0x07 31:24 0x08 EXTREG 0x09 7:0 15:8 0x0A STATUS_BK 7:0 0x0B Reserved 7:0 0x0C Reserved 7:0 0x0D Reserved 7:0 0x0E Reserved 7:0 0x0F Reserved 7:0 MULTI_PACKET_SIZE[9:2] AUTO_ZLP SIZE[2:0] MULTI_PACKET_SIZE[13:10] VARIABLE[3:0] SUBPID[3:0] VARIABLE[10:4] ERRORFLOW CRCERR Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 724 Table 29-5. Device endpoint n Descriptor Bank 1 Offset 0x n0 + 0x10 + index Name 0x00 Bit Pos. 7:0 ADD[7:0] 15:8 ADD[15:8] 0x02 23:16 ADD[23:16] 0x03 31:24 ADD[31:24] 0x04 7:0 BYTE_COUNT[7:0] 0x01 ADDR 0x05 15:8 MULTI_PACKET_SIZE[1:0] BYTE_COUNT[13:8] PCKSIZE 0x06 23:16 0x07 31:24 0x08 Reserved 7:0 0x09 Reserved 15:8 0x0A STATUS_BK 7:0 0x0B Reserved 7:0 0x0C Reserved 7:0 0x0D Reserved 7:0 0x0E Reserved 7:0 0x0F Reserved 7:0 MULTI_PACKET_SIZE[9:2] AUTO_ZLP SIZE[2:0] MULTI_PACKET_SIZE[13:10] ERRORFLOW Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 CRCERR 725 29.7.3 Host Summary Table 29-6. General Host Registers Summary Offset Name 0x04 Reserved 0x05 Reserved 0x06 Reserved 0x07 Reserved 0x08 Bit Pos. 7:0 TSTK TSTJ SPDCONF[1:0] RESUME CTRLB 0x09 15:8 0x0A HSOFC 0x0B Reserved 0x0C STATUS 0x0E Reserved 0x0F Reserved 0x10 7:0 7:0 L1RESUME VBUSOK FLENCE BUSRESET SOFE FLENC[3:0] LINESTATE[1:0] 7:0 SPEED[1:0] FNUM[4:0] FNUM 0x11 0x12 15:8 FLENHIGH 0x14 FNUM[10:5] 7:0 7:0 FLENHIGH[7:0] RAMACER UPRSM DNRSM WAKEUP RST HSOF INTENCLR 0x15 15:8 0x16 Reserved 0x17 Reserved 0x18 7:0 RAMACER UPRSM DNRSM WAKEUP RST DDISC DCONN DDISC DCONN DDISC DCONN HSOF INTENSET 0x19 15:8 0x1A Reserved 0x1B Reserved 0x1C 7:0 RAMACER UPRSM DNRSM WAKEUP RST HSOF INTFLAG 0x1D 15:8 0x1E Reserved 0x1F Reserved 0x20 7:0 PINT[7:0] 15:8 PINT[15:8] PINTSMRY 0x21 0x22 Reserved 0x23 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 726 Table 29-7. Host pipe Register n Offset Name Bit Pos. 0x1m0 PCFGn 7:0 PTYPE[2:0] BK PTOKEN[1:0] 0x1m1 Reserved 0x1m2 Reserved 0x1m3 BINTERVAL 7:0 0x1m4 PSTATUSCLR 7:0 BK1RDY BK0RDY PFREEZE CURBK DTGL 0x1m5 PSTATUSSET 7:0 BK1RDY BK0RDY PFREEZE CURBK DTGL 0x1m6 PSTATUS 7:0 BK1RDY BK0RDY PFREEZE CURBK DTGL 0x1m7 PINTFLAG 7:0 STALL TXSTP PERR TRFAIL TRCPT1 TRCPT0 0x1m8 PINTENCLR 7:0 STALL TXSTP PERR TRFAIL TRCPT1 TRCPT0 0x1m9 PINTENSET 7:0 STALL TXSTP PERR TRFAIL TRCPT1 TRCPT0 0x1mA Reserved 0x1mB Reserved BINTERVAL[7:0] Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 727 Table 29-8. Host pipe n Descriptor Bank 0 Offset 0x n0 + index Name 0x00 Bit Pos. 7:0 ADD[7:0] 15:8 ADD[15:8] 0x02 23:16 ADD[23:16] 0x03 31:24 ADD[31:24] 0x04 7:0 BYTE_COUNT[7:0] 0x01 ADDR 0x05 15:8 MULTI_PACKET_SIZE[1:0] BYTE_COUNT[13:8] PCKSIZE 0x06 23:16 0x07 31:24 0x08 7:0 MULTI_PACKET_SIZE[9:2] AUTO_ZLP SIZE[2:0] MULTI_PACKET_SIZE[13:10] VARIABLE[3:0] SUBPID[3:0] EXTREG 0x09 0x0A 15:8 STATUS_BK 0x0B VARIABLE[10:4] 7:0 ERRORFLOW CRCERR 15:8 0x0C 7:0 PDADDR[6:0] CTRL_PIPE 0x0D 0x0E 0x0F 15:8 STATUS_PIP E 7:0 PEPMAX[3:0] ERCNT[2:0] PEPNUM[3:0] CRC16ER TOUTER PIDER DAPIDER DTGLER 15:8 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 728 Table 29-9. Host pipe n Descriptor Bank 1 Offset 0x n0 +0x10 +index Name 0x00 Bit Pos. 7:0 ADD[7:0] 15:8 ADD[15:8] 0x02 23:16 ADD[23:16] 0x03 31:24 ADD[31:24] 0x04 7:0 BYTE_COUNT[7:0] 0x01 ADDR 0x05 15:8 MULTI_PACKET_SIZE[1:0 BYTE_COUNT[13:8] PCKSIZE 0x06 23:16 0x07 31:24 0x08 7:0 0x09 15:8 0x0A STATUS_BK AUTO_ZLP SIZE[2:0] MULTI_PACKET_SIZE[13:10] 7:0 0x0B 15:8 0x0C 7:0 0x0D 15:8 0x0E MULTI_PACKET_SIZE[9:2] 7:0 ERCNT[2:0] CRC16ER TOUTER PIDER ERRORFLOW CRCERR DAPIDER DTGLER STATUS_PIPE 0x0F 15:8 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 729 29.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by Write-Protected property in each individual register description. Please refer to the "Register Access Protection" on page 704 section and the "PAC - Peripheral Access Controller" on page 36 for details. Some registers require synchronization when read and/or written. Synchronization is denoted by the Write-Synchronized or the Read-Synchronized property in each individual register description. Refer to "Synchronization" on page 96 for details. Some registers are enable-protected, meaning they can only be written when the USB is disabled. Enable-protection is denoted by the Enable-Protected property in each individual register description. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 730 29.8.1 Common Device Host Registers 29.8.1.1 Control A Name: CTRLA Offset: 0x00 Reset: 0x0000 Property: Write-Protected, Write-Synchronised Bit 7 6 5 4 3 MODE 2 1 0 RUNSTBY ENABLE SWRST Access R/W R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bit 7- MODE: Operating Mode This bit defines the operating mode of the USB. 0: USB Device mode 1: USB Host mode z Bits 6:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 2 - RUNSDTBY: Run in Standby Mode 0: USB clock is stopped in standby mode. 1: USB clock is running in standby mode This bit is Enable-Protected. z Bit 1 - ENABLE: Enable 0: The peripheral is disabled or being disabled. 1: The peripheral is enabled or being enabled. Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the Synchronization status enable bit in the synchronization register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. This bit is Write-Synchronized z Bit 0 - SWRST: Software Reset 0: There is no reset operation ongoing. 1: The reset operation is ongoing. Writing a zero to this bit has no effect. Writing a one to this bit resets all registers in the USB, to their initial state, and the USB will be disabled. Writing a one to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete. This bit is Write-Synchronized. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 731 29.8.1.2 Synchronization Busy Name: SYNCBUSY Offset: 0x02 Reset: 0x0000 Property: - Bit 7 6 5 4 3 2 1 0 ENABLE SWRST Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 7:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 1 - ENABLE: Synchronization Enable status bit This bit is cleared when the synchronization of ENABLE register between the clock domains is complete. This bit is set when the synchronization of ENABLE register between clock domains is started. z Bit 0 - SWRST: Synchronization Software Reset status bit This bit is cleared when the synchronization of SWRST register between the clock domains is complete. This bit is set when the synchronization of SWRST register between clock domains is started. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 732 29.8.1.3 QOS Control Name: QOSCTRL Offset: 0x03 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 DQOS[1:0] 0 CQOS[1:0] Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 1 0 1 z Bits 7:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 3:2 -DQOS[1:0]: Data Quality of Service These bits define the memory priority access during the endpoint or pipe read/write data operation.Refer to "SRAM Quality of Service" on page 34. z Bits 1:0 - CQOS[1:0]: Configuration Quality of Service These bits define the memory priority access during the endpoint or pipe read/write configuration operation.Refer to "SRAM Quality of Service" on page 34. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 733 29.8.1.4 Finite State Machine Status Name: FSMSTATUS Offset: 0x0D Reset: 0xXXXX Property: Read only Bit 7 6 5 4 3 2 1 0 FSMSTATE[6:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 1 z Bits 7 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 6:0 - FSMSTATE[6:0]: Fine State Machine Status These bits indicate the state of the finite state machine of the USB controller. FSMSTATE[6:0] Description 0x01 OFF (L3). Corresponds to the powered-off, disconnected, and disabled state 0x02 ON (L0). Corresponds to the Idle and Active states 0x04 SUSPEND (L2) 0x08 SLEEP (L1) 0x10 DNRESUME. Down Stream Resume. 0x20 UPRESUME. Up Stream Resume. 0x40 RESET. USB lines Reset. Others Reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 734 29.8.1.5 Descriptor Address Name: DESCADD Offset: 0x24 Reset: 0x00000000 Property: Write-Protected Bit 31 30 29 28 27 26 25 24 DESCADD[31:24] +3 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DESCADD[23:16] +2 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DESCADD[15:8] +1 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DESCADD[7:0] +0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 31:0 - DESCADD[31:0]: Descriptor Address Value These bits define the base address of the main USB descriptor in RAM. The two least significant bits must be written to zero. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 735 29.8.1.6 Pad Calibration Name: PADCAL Offset: 0x28 Reset: 0x0000 Property: Write-Protected Bit 15 14 13 12 11 10 TRIM[2:0] 9 8 TRANSN[4:2] Access R R/W R/W R/W R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 TRANSN[1:0] TRANSP[4:0] Access R/W R/W R R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 The Pad Calibration values must be loaded from the NVM Software Calibration Area into the USB Pad Calibration register by software, before enabling the USB, to achieve the specified accuracy. Refer to "NVM Software Calibration Area Mapping" on page 26 for further details. z Bit 15 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 14:12 - TRIM: Trim bits for DP/DM These bits calibrate the matching of rise/fall of DP/DM. z Bit 11 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 10:6 - TRANSN: Trimmable Output Driver Impedance N These bits calibrate the NMOS output impedance of DP/DM drivers. z Bit 5 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 4:0 - TRANSP: Trimmable Output Driver Impedance P These bits calibrate the PMOS output impedance of DP/DM drivers. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 736 29.8.2 Device Registers - Common 29.8.2.1 Control B Name: CTRLB Offset: 0x08 Reset: 0x0001 Property: Write-Protected Bits 15 14 13 12 11 10 LPMHD[1:0] 9 8 GNAK Access R R R R R/W R/W R/W R/ Reset 0 0 0 0 0 0 0 0 Bits 7 6 5 4 3 2 1 0 UPRSM DETACH Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 NREPLY SPDCONF[1:0] z Bits 15:12 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 11:10 - LPMHDSK[1:0]: Link Power Management Handshake These bits select the Link Power Management Handshake configuration as shown in Table 29-10. Table 29-10. LPMHDSK Selection LPMHDSK[1:0] Description 0x0 No handshake. LPM is not supported 0x1 ACK 0x2 NYET 0x3 Reserved z Bit 9 - GNAK: Global NAK This bit configures the operating mode of the NAK. 0: The handshake packet reports the status of the USB transaction 1: A NAK handshake is answered for each USB transaction regardless of the current endpoint memory bank status This bit is not synchronized. z Bits 8:5 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 4 - NREPLY: No reply excepted SETUP Token 0: Disable the "NO_REPLY" feature: Any transaction to endpoint 0 will be handled according to the USB2.0 standard. 1: Enable the "NO_REPLY" feature: Any transaction to endpoint 0 will be ignored except SETUP. This bit is cleared by hardware when receiving a SETUP packet. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 737 This bit has no effect for any other endpoint but endpoint 0. z Bits 3:2 - : Speed Configuration These bits select the speed configuration as shown in Table 29-11. Table 29-11. SPDCONF Selection SPDCONF [1:0] Description 0x0 FS: Full speed 0x1 LS: Low Speed 0x2 Reserved 0x3 Reserved z Bit 1 - UPRSM: Upstream Resume 0: Writing a zero to this bit has no effect. 1: Writing a one to this bit will generate an upstream resume to the host for a remote wakeup. This bit is cleared when the USB receives a USB reset or once the upstream resume has been sent. z Bit 0 - DETACH: Detach 0: The device is attached to the USB bus so that communications may occur. 1: It is the default value at reset. The internal device pull-ups are disabled, removing the device from the USB bus. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 738 29.8.2.2 Device Address Name: DADD Offset: 0x0A Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 ADDEN 3 2 1 0 DADD[6:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bit 7 - ADDEN: Device Address Enable 0: Writing a zero will deactivate the DADD field (USB device address) and return the device to default address 0. 1: Writing a one will activate the DADD field (USB device address). This bit is cleared when a USB reset is received. z Bits 6:0 - DADD: Device Address These bits define the device address. The DADD register is reset when a USB reset is received. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 739 29.8.2.3 Status Name: STATUS Offset: 0x0C Reset: 0x0000 Property: - Bit 7 6 5 4 3 LINESTATE[1:0] 2 1 0 SPEED[1:0] Access R R R R R R R R Reset 0 1 0 0 0 1 0 0 z Bits 7:6 - LINESTATE[1:0]: USB Line State Status These bits define the current line state DP/DM as showed in Table 29-12. Table 29-12. USB Line State Status LINESTATE[1:0] USB Line Status 0x0 SE0/RESET 0x1 FS-J or LS-K State 0x2 FS-K or LS-J State z Bits 5:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 3:2 - SPEED [1:0]: Speed Status These bits define the current speed used of the device . Table 29-13. Speed Status SPEED[1:0] SPEED STATUS 0x0 Low-speed mode 0x1 Full-speed mode 0x2 Reserved 0x3 Reserved z Bits 1:0 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 740 29.8.2.4 Device Frame Number Name: FNUM Offset: 0x10 Reset: 0x0000 Property: Read only Bit 15 14 13 12 11 FNCERR 10 9 8 FNUM[10:5] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 FNUM[4:0] MFNUM[2:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bit 15 - FNCERR: Frame Number CRC Error This bit is cleared upon receiving a USB reset. This bit is set when a corrupted frame number (or micro-frame number) is received. This bit and the SOF (or MSOF) interrupt bit are updated at the same time. z Bit 14 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 13:3 - FNUM: Frame Number These bits are cleared upon receiving a USB reset. These bits are updated with the frame number information as provided from the last SOF packet even if a corrupted SOF is received. z Bits 2:0 - MFNUM: Micro Frame Number These bits are cleared upon receiving a USB reset or at the beginning of each Start-of-Frame (SOF interrupt). These bits are updated with the micro-frame number information as provided from the last MSOF packet even if a corrupted MSOF is received. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 741 29.8.2.5 Device Interrupt Enable Clear This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register. Name: INTENCLR Offset: 0x14 Reset: 0x0000 Property: Write-Protected Bit 15 14 13 12 11 10 9 8 LPMSUSP LPMNYET Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RAMACER UPRSM EORSM WAKEUP EORST SOF Access R/W R/W R/W R/W R/W R/W R SUSPEND R/W Reset 0 0 0 0 0 0 0 0 z Bits 15:10 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 9 - LPMSUSP: Link Power Management Suspend Interrupt Enable 0: The Link Power Management Suspend interrupt is disabled. 1: The Link Power Management Suspend interrupt is enabled and an interrupt request will be generated when the Link Power Management Suspend interrupt Flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Link Power Management Suspend Interrupt Enable bit and disable the corresponding interrupt request. z Bit 8 - LPMNYET: Link Power Management Not Yet Interrupt Enable 0: The Link Power Management Not Yet interrupt is disabled. 1: The Link Power Management Not Yet interrupt is enabled and an interrupt request will be generated when the Link Power Management Not Yet interrupt Flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Link Power Management Not Yet interrupt Enable bit and disable the corresponding interrupt request. z Bit 7 - RAMACER: RAM Access Interrupt Enable 0: The RAM Access interrupt is disabled. 1: The RAM Access interrupt is enabled and an interrupt request will be generated when the RAM Access interrupt Flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the RAM Access interrupt Enable bit and disable the corresponding interrupt request. z Bit 6 - UPRSM: Upstream Resume Interrupt Enable 0: The Upstream Resume interrupt is disabled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 742 1: The Upstream Resume interrupt is enabled and an interrupt request will be generated when the Upstream Resume interrupt Flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Upstream Resume interrupt Enable bit and disable the corresponding interrupt request. z Bit 5 - EORSM: End Of Resume Interrupt Enable 0: The End Of Resume interrupt is disabled. 1: The End Of Resume interrupt is enabled and an interrupt request will be generated when the End Of Resume interrupt Flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the End Of Resume interrupt Enable bit and disable the corresponding interrupt request. z Bit 4 - WAKEUP: Wake-Up Interrupt Enable 0: The Wake Up interrupt is disabled. 1: The Wake Up interrupt is enabled and an interrupt request will be generated when the Wake Up interrupt Flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Wake Up interrupt Enable bit and disable the corresponding interrupt request. z Bit 3 - EORST: End of Reset Interrupt Enable 0: The End of Reset interrupt is disabled. 1: The End of Reset interrupt is enabled and an interrupt request will be generated when the End of Reset interrupt Flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the End of Reset interrupt Enable bit and disable the corresponding interrupt request. z Bit 2 - SOF: Start-of-Frame Interrupt Enable 0: The Start-of-Frame interrupt is disabled. 1: The Start-of-Frame interrupt is enabled and an interrupt request will be generated when the Start-of-Frame interrupt Flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Start-of-Frame interrupt Enable bit and disable the corresponding interrupt request. z Bit 1 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 0- SUSPEND: Suspend Interrupt Enable 0: The Suspend interrupt is disabled. 1: The Suspend interrupt is enabled and an interrupt request will be generated when the Suspend interrupt Flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Suspend Interrupt Enable bit and disable the corresponding interrupt request. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 743 29.8.2.6 Device Interrupt Enable Set This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Name: INTENSET Offset: 0x18 Reset: 0x0000 Property: Write-Protected Bit 15 14 13 12 11 10 9 8 Access R R R R R R LPMSUSP LPMNYET R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RAMACER UPRSM EORSM WAKEUP EORST SOF Access R/W R/W R/W R/W R/W R/W R SUSPEND R/W Reset 0 0 0 0 0 0 0 0 z Bits 15:10 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 9 - LPMSUSP: Link Power Management Suspend Interrupt Enable 0: The Link Power Management Suspend interrupt is disabled. 1: The Link Power Management Suspend interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Link Power Management Suspend Enable bit and enable the corresponding interrupt request. z Bit 8 - LPMNYET: Link Power Management Not Yet Interrupt Enable 0: The Link Power Management Not Yet interrupt is disabled. 1: The Link Power Management Not Yet interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Link Power Management Not Yet interrupt bit and enable the corresponding interrupt request. z Bit 7 - RAMACER: RAM Access Interrupt Enable 0: The RAM Access interrupt is disabled. 1: The RAM Access interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the RAM Access Enable bit and enable the corresponding interrupt request. z Bit 6 - UPRSM: Upstream Resume Interrupt Enable 0: The Upstream Resume interrupt is disabled. 1: The Upstream Resume interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Upstream Resume Enable bit and enable the corresponding interrupt request. z Bit 5 - EORSM: End Of Resume Interrupt Enable 0: The End Of Resume interrupt is disabled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 744 1: The End Of Resume interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the End Of Resume interrupt Enable bit and enable the corresponding interrupt request. z Bit 4 - WAKEUP: Wake-Up Interrupt Enable 0: The Wake Up interrupt is disabled. 1: The Wake Up interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Wake Up interrupt Enable bit and enable the corresponding interrupt request. z Bit 3 - EORST: End of Reset Interrupt Enable 0: The End of Reset interrupt is disabled. 1: The End of Reset interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the End of Reset interrupt Enable bit and enable the corresponding interrupt request. z Bit 2 - SOF: Start-of-Frame Interrupt Enable 0: The Start-of-Frame interrupt is disabled. 1: The Start-of-Frame interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Start-of-Frame interrupt Enable bit and enable the corresponding interrupt request. z Bit 1 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 0 - SUSPEND: Suspend Interrupt Enable 0: The Suspend interrupt is disabled. 1: The Suspend interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Suspend interrupt Enable bit and enable the corresponding interrupt request. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 745 29.8.2.7 Device Interrupt Flag Name: INTFLAG Offset: 0x01C Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 Access R R R R R R Reset 0 0 0 0 0 Bit 9 8 LPMSUSP LPMNYET R/W R/W 0 0 0 1 7 6 5 4 3 2 RAMACER UPRSM EORSM WAKEUP EORST SOF 0 Access R/W R/W R/W R/W R/W R/W R R/W Reset 0 0 0 0 0 0 0 0 SUSPEND z Bits 15:10 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 9 - LPMSUSP: Link Power Management Suspend Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when the USB module acknowledge a Link Power Management Transaction (ACK handshake) and has entered the Suspended state and will generate an interrupt if INTENCLR/SET.LPMSUSP is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the LPMSUSP Interrupt Flag. z Bit 8 - LPMNYET: Link Power Management Not Yet Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when the USB module acknowledges a Link Power Management Transaction (handshake is NYET) and will generate an interrupt if INTENCLR/SET.LPMNYET is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the LPMNYET Interrupt Flag. z Bit 7- RAMACER: RAM Access Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when a RAM access underflow error occurs during IN data stage. This bit will generate an interrupt if INTENCLR/SET.RAMACER is one. Writing a zero to this bit has no effect. z Bit 6 - UPRSM: Upstream Resume Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when the USB sends a resume signal called "Upstream Resume" and will generate an interrupt if INTENCLR/SET.UPRSM is one. Writing a zero to this bit has no effect. z Bit 5 - EORSM: End Of Resume Interrupt Flag This flag is cleared by writing a one to the flag. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 746 This flag is set when the USB detects a valid "End of Resume" signal initiated by the host and will generate an interrupt if INTENCLR/SET.EORSM is one. Writing a zero to this bit has no effect. z Bit 4 - WAKEUP: Wake Up Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when the USB is reactivated by a filtered non-idle signal from the lines and will generate an interrupt if INTENCLR/SET.WAKEUP is one. Writing a zero to this bit has no effect. z Bit 3 - EORST: End of Reset Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when a USB "End of Reset" has been detected and will generate an interrupt if INTENCLR/SET.EORST is one. Writing a zero to this bit has no effect. z Bit 2 - SOF: Start-of-Frame Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when a USB "Start-of-Frame" has been detected (every 1 ms) and will generate an interrupt if INTENCLR/SET.SOF is one. The FNUM is updated. Writing a zero to this bit has no effect. z Bit 1 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 0 - SUSPEND: Suspend Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when a USB "Suspend" idle state has been detected for 3 frame periods (J state for 3 ms) and will generate an interrupt if INTENCLR/SET.SUSPEND is one. Writing a zero to this bit has no effect. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 747 29.8.2.8 Endpoint Interrupt Summary Name: EPINTSMRY Offset: 0x20 Reset: 0x00000000 Property: - Bit 15 14 13 12 11 10 9 8 EPINT[15:8] +1 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 EPINT[7:0] +0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 15:0 - EPINT[15:0]: EndPoint Interrupt Summary Register The flag EPINT[n] is set when an interrupt is triggered by the EndPoint n. See "Device EndPoint Interrupt Flag" on page 755 register in the device EndPoint section. This bit will be cleared when no interrupts are pending for EndPoint n. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 748 29.8.3 Device Registers - Endpoint 29.8.3.1 Device Endpoint Configuration register n Name: EPCFGx Offset: 0x100 + (n x 0x20) Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 ETYPE1[2:0] 1 0 ETYPE0[2:0] Access R R/W R/W R/W R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bit 7 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 6:4 - EPTYPE1[2:0]: Type of the Endpoint for IN direction These bits contains the endpoint type for IN direction. Table 29-14. Type of Endpoint EPTYPE1[2:0] Description 0x0 Bank1 is disabled 0x1 Bank1 is enabled and configured as Control IN 0x2 Bank1 is enabled and configured as Isochronous IN 0x3 Bank1 is enabled and configured as Bulk IN 0x4 Bank1 is enabled and configured as Interrupt IN 0x5 Bank1 is enabled and configured as Dual-Bank OUT (EndPoint type is the same as the one defined in EPTYPE0) 0x6-0x7 Reserved Upon receiving a USB reset EPCFGn.EPTYPE1 is cleared except for endpoint 0 which is unchanged. z Bit 3 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 749 z Bits 2:0 - EPTYPE0[2:0]: Type of the Endpoint for OUT direction These bits contains the endpoint type for OUT direction. Table 29-15. Type of Endpoint EPTYPE0[2:0] Description 0x0 Bank0 is disabled 0x1 Bank0 is enabled and configured as Control SETUP / Control OUT 0x2 Bank0 is enabled and configured as Isochronous OUT 0x3 Bank0 is enabled and configured as Bulk OUT 0x4 Bank0 is enabled and configured as Interrupt OUT 0x5 Bank0 is enabled and configured as Dual Bank IN (EndPoint type is the same as the one defined in EPTYPE1) 0x6-0x7 Reserved Upon receiving a USB reset EPCFGn.EPTYPE0 is cleared except for endpoint 0 which is unchanged. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 750 29.8.3.2 EndPoint Status Clear Register n Name: EPSTATUSCLR Offset: 0x104 + (x * 0x20) Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 BK1RDY BK0RDY STALLRQ1 STALLRQ0 Access R/W R/W R/W R/W Reset 0 0 0 0 z 3 2 1 0 CURBK DTGLIN DTGLOUT R/W R/W R/W R/W 0 0 0 0 Bit 7 - BK1RDY: Bank 1 Ready Writing a zero to this bit has no effect. Writing a one to this bit will clear EPSTATUS.BK1RDY bit. z Bit 6 - BK0RDY: Bank 0 Ready Writing a zero to this bit has no effect. Writing a one to this bit will clear EPSTATUS.BK0RDY bit. z Bit 5 - STALLRQ1:STALL bank 1 Request Writing a zero to this bit has no effect. Writing a one to this bit will clear EPSTATUS.STALLRQ1 bit. z Bit 4 - STALLRQ0:STALL bank 0 Request Writing a zero to this bit has no effect. Writing a one to this bit will clear EPSTATUS.STALLRQ0 bit. z Bit 3 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 2 - CURBK: Current Bank Writing a zero to this bit has no effect. Writing a one to this bit will clear EPSTATUS.CURBK bit. z Bit 1 - DTGLIN: Data Toggle IN Writing a zero to this bit has no effect. Writing a one to this bit will clear EPSTATUS.DTGLIN bit. z Bit 0 - DTGLOUT: Data Toggle OUT Writing a zero to this bit has no effect. Writing a one to this bit will clear the EPSTATUS.DTGLOUT bit. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 751 29.8.3.3 EndPoint Status Set n Name: EPSTATUSSET Offset: 0x105 + (n x 0x20) Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 BK1RDY BK0RDY STALLRQ1 STALLRQ0 Access R/W R/W R/W R/W Reset 0 0 0 0 z 3 2 1 0 CURBK DTGLIN DTGLOUT R R/W R/W R/W 0 0 0 0 Bit 7 - BK1RDY: Bank 1 Ready Writing a zero to this bit has no effect. Writing a one to this bit will set EPSTATUS.BK1RDY bit. z Bit 6 - BK0RDY: Bank 0 Ready Writing a zero to this bit has no effect. Writing a one to this bit will set EPSTATUS.BK0RDY bit. z Bit 5 - STALLRQ1: STALL Request bank 1 Writing a zero to this bit has no effect. Writing a one to this bit will set EPSTATUS.STALLRQ1 bit. z Bit 4 - STALLRQ0: STALL Request bank 0 Writing a zero to this bit has no effect. Writing a one to this bit will set EPSTATUS.STALLRQ0 bit. z Bit 3 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 2 - CURBK: Current Bank Writing a zero to this bit has no effect. Writing a one to this bit will set EPSTATUS.CURBK bit. z Bit 1 - DTGLIN: Data Toggle IN Writing a zero to this bit has no effect. Writing a one to this bit will set EPSTATUS.DTGLIN bit. z Bit 0 - DTGLOUT: Data Toggle OUT Writing a zero to this bit has no effect. Writing a one to this bit will set the EPSTATUS.DTGLOUT bit. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 752 29.8.3.4 EndPoint Status n Name: EPSTATUS Offset: 0x106 + (n x 0x20) Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 BK1RDY BK0RDY STALLRQ1 STALLRQ0 Access R R R R Reset 0 0 0 0 z 3 2 1 0 CURBK DTGLIN DTGLOUT R R R R 0 0 0 0 Bit 7 - BK1RDY: Bank 1 is ready 0: The bank number 1 is not ready : For IN direction Endpoints, the bank is not yet filled in. For Control/OUT direction Endpoints, the bank is empty. 1: The bank number 1 is ready: For IN direction Endpoints, the bank is filled in. For Control/OUT direction Endpoints, the bank is full. Writing a one to the bit EPSTATUSCLR.BK1RDY will clear this bit. Writing a one to the bit EPSTATUSSET.BK1RDY will set this bit. z Bit 6 - BK0RDY: Bank 0 is ready 0: The bank number 0 is not ready : For IN direction Endpoints, the bank is not yet filled in. For Control/OUT direction Endpoints, the bank is empty. 1: The bank number 0 is ready: For IN direction Endpoints, the bank is filled in. For Control/OUT direction Endpoints, the bank is full. Writing a one to the bit EPSTATUSCLR.BK0RDY will clear this bit. Writing a one to the bit EPSTATUSSET.BK0RDY will set this bit. z Bit 5 - STALLRQ1: STALL bank 1 request 0: Disable STALLRQ1 feature. 1: Enable STALLRQ1 feature: a STALL handshake will be sent to the host in regards to bank1. Writing a zero to the bit EPSTATUSCLR.STALLRQ1 will clear this bit. Writing a one to the bit EPSTATUSSET.STALLRQ1 will set this bit. This bit is cleared by hardware when receiving a SETUP packet. z Bit 4 - STALLRQ0: STALL bank 0 request 0: Disable STALLRQ0 feature. 1: Enable STALLRQ0 feature: a STALL handshake will be sent to the host in regards to bank0. Writing a zero to the bit EPSTATUSCLR.STALLRQ0 will clear this bit. Writing a one to the bit EPSTATUSSET.STALLRQ0 will set this bit. This bit is cleared by hardware when receiving a SETUP packet. z Bit 3 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 2 - CURBK: Current Bank 0: The bank0 is the bank that will be used in the next single/multi USB packet. 1: The bank1 is the bank that will be used in the next single/multi USB packet. Writing a zero to the bit EPSTATUSCLR.CURBK will clear this bit. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 753 Writing a one to the bit EPSTATUSSET.CURBK will set this bit. z Bit 1 - DTGLIN: Data Toggle IN Sequence 0: The PID of the next expected IN transaction will be zero: data 0. 1: The PID of the next expected IN transaction will be one: data 1. Writing a zero to the bit EPSTATUSCLR.DTGLINCLR will clear this bit. Writing a one to the bit EPSTATUSSET.DTGLINSET will set this bit. z Bit 0 - DTGLOUT: Data Toggle OUT Sequence 0: The PID of the next expected OUT transaction will be zero: data 0. 1: The PID of the next expected OUR transaction will be one: data 1. Writing a zero to the bit EPSTATUSCLR.DTGLOUTCLR will clear this bit. Writing a one to the bit EPSTATUSSET.DTGLOUTSET will set this bit. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 754 29.8.3.5 Device EndPoint Interrupt Flag Name: EPINTFLAG Offset: 0x107 + (n x 0x20) Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 STALL1 STALL0 RXSTP TRFAIL1 TRFAIL0 TRCPT1 TRCPT0 Access R R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 6 - STALL1: Transmit Stall 1 Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when a Transmit Stall occurs and will generate an interrupt if EPINTENCLR/SET.STALL1 is one. EPINTFLAG.STALL1 is set for a single bank IN endpoint or double bank IN/OUT endpoint when current bank is "1". Writing a zero to this bit has no effect. Writing a one to this bit clears the STALL1 Interrupt Flag. z Bit 5 - STALL0: Transmit Stall 0 Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when a Transmit Stall occurs and will generate an interrupt if EPINTENCLR/SET.STALL0 is one. EPINTFLAG.STALL0 is set for a single bank OUT endpoint or double bank IN/OUT endpoint when current bank is "0". Writing a zero to this bit has no effect. Writing a one to this bit clears the STALL0 Interrupt Flag. z Bit 4 - RXSTP: Received Setup Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when a Received Setup occurs and will generate an interrupt if EPINTENCLR/SET.RXSTP is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the RXSTP Interrupt Flag. z Bit 3 - TRFAIL1: Transfer Fail 1 Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when a transfer fail occurs and will generate an interrupt if EPINTENCLR/SET.TRFAIL1 is one. EPINTFLAG.TRFAIL1 is set for a single bank IN endpoint or double bank IN/OUT endpoint when current bank is "1". Writing a zero to this bit has no effect. Writing a one to this bit clears the TRFAIL1 Interrupt Flag. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 755 z Bit 2 - TRFAIL0: Transfer Fail 0 Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when a transfer fail occurs and will generate an interrupt if EPINTENCLR/SET.TRFAIL0 is one. EPINTFLAG.TRFAIL0 is set for a single bank OUT endpoint or double bank IN/OUT endpoint when current bank is "0". Writing a zero to this bit has no effect. Writing a one to this bit clears the TRFAIL0 Interrupt Flag. z Bit 1 - TRCPT1: Transfer Complete 1 interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when a Transfer Complete occurs and will generate an interrupt if EPINTENCLR/SET.TRCPT1 is one. EPINTFLAG.TRCPT1 is set for a single bank IN endpoint or double bank IN/OUT endpoint when current bank is "1". Writing a zero to this bit has no effect. Writing a one to this bit clears the TRCPT1 Interrupt Flag. z Bit 0 - TRCPT0: Transfer Complete 0 interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when a Transfer complete occurs and will generate an interrupt if EPINTENCLR/SET.TRCPT0 is one. EPINTFLAG.TRCPT0 is set for a single bank OUT endpoint or double bank IN/OUT endpoint when current bank is "0". Writing a zero to this bit has no effect. Writing a one to this bit clears the TRCPT0 Interrupt Flag. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 756 29.8.3.6 Device EndPoint Interrupt Enable Name: EPINTENCLR Offset: 0x108 + (n x 0x20) Reset: 0x00 Property: Write-Protected This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Endpoint Interrupt Enable Set (EPINTENSET) register. This register is cleared by USB reset or when EPEN[n] is zero. Bit 7 6 5 4 3 2 1 0 STALL1 STALL0 RXSTP TRFAIL1 TRFAIL0 TRCPT1 TRCPT0 Access R R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 6 - STALL1: Transmit STALL 1 Interrupt Enable 0: The Transmit Stall 1 interrupt is disabled. 1: The Transmit Stall 1 interrupt is enabled and an interrupt request will be generated when the Transmit Stall 1 Interrupt Flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Transmit Stall 1 Interrupt Enable bit and disable the corresponding interrupt request. z Bit 5 - STALL0: Transmit STALL 0 Interrupt Enable 0: The Transmit Stall 0 interrupt is disabled. 1: The Transmit Stall 0 interrupt is enabled and an interrupt request will be generated when the Transmit Stall 0 Interrupt Flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Transmit Stall 0 Interrupt Enable bit and disable the corresponding interrupt request. z Bit 4 - RXSTP: Received Setup Interrupt Enable 0: The Received Setup interrupt is disabled. 1: The Received Setup interrupt is enabled and an interrupt request will be generated when the Received Setup Interrupt Flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Received Setup Interrupt Enable bit and disable the corresponding interrupt request. z Bit 3 - TRFAIL1: Transfer Fail 1 Interrupt Enable 0: The Transfer Fail 1 interrupt is disabled. 1: The Transfer Fail 1 interrupt is enabled and an interrupt request will be generated when the Transfer Fail 1 Interrupt Flag is set. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 757 The user should look into the descriptor table status located in ram to be informed about the error condition : ERRORFLOW, CRC. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Transfer Fail 1 Interrupt Enable bit and disable the corresponding interrupt request. z Bit 2 - TRFAIL0: Transfer Fail 0 Interrupt Enable 0: The Transfer Fail bank 0 interrupt is disabled. 1: The Transfer Fail bank 0 interrupt is enabled and an interrupt request will be generated when the Transfer Fail 0 Interrupt Flag is set. The user should look into the descriptor table status located in ram to be informed about the error condition : ERRORFLOW, CRC. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Transfer Fail 0 Interrupt Enable bit and disable the corresponding interrupt request. z Bit 1 - TRCPT1: Transfer Complete 1 Interrupt Enable 0: The Transfer Complete 1 interrupt is disabled. 1: The Transfer Complete 1 interrupt is enabled and an interrupt request will be generated when the Transfer Complete 1 Interrupt Flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Transfer Complete 1 Interrupt Enable bit and disable the corresponding interrupt request. z Bit 0 - TRCPT0: Transfer Complete 0 interrupt Enable 0: The Transfer Complete bank 0 interrupt is disabled. 1: The Transfer Complete bank 0 interrupt is enabled and an interrupt request will be generated when the Transfer Complete 0 Interrupt Flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Transfer Complete 0 interrupt Enable bit and disable the corresponding interrupt request. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 758 29.8.3.7 Device Interrupt EndPoint Set Name: EPINTENSET Offset: 0x109 + (n x 0x20) Reset: 0x0000 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 STALL1 STALL0 RXSTP TRFAIL1 TRFAIL0 TRCPT1 TRCPT0 Access R R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Endpoint Interrupt Enable Set (EPINTENCLR) register. This register is cleared by USB reset or when EPEN[n] is zero. z Bits 7 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 6 - STALL1: Transmit Stall 1 Interrupt Enable 0: The Transmit Stall 1 interrupt is disabled. 1: The Transmit Stall 1 interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will enable the Transmit bank 1 Stall interrupt. z Bit 5 - STALL0: Transmit Stall 0 Interrupt Enable 0: The Transmit Stall 0 interrupt is disabled. 1: The Transmit Stall 0 interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will enable the Transmit bank 0 Stall interrupt. z Bit 4 - RXSTP: Received Setup Interrupt Enable 0: The Received Setup interrupt is disabled. 1: The Received Setup interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will enable the Received Setup interrupt. z Bit 3 - TRFAIL1: Transfer Fail bank 1 Interrupt Enable 0: The Transfer Fail interrupt is disabled. 1: The Transfer Fail interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will enable the Transfer Fail interrupt. z Bit 3 - TRFAIL0: Transfer Fail bank 0 Interrupt Enable 0: The Transfer Fail interrupt is disabled. 1: The Transfer Fail interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will enable the Transfer Fail interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 759 z Bit 1 - TRCPT1: Transfer Complete bank 1 interrupt Enable 0: The Transfer Complete bank 1 interrupt is disabled. 1: The Transfer Complete bank 1 interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will enable the Transfer Complete 0 interrupt. z Bit 0 - TRCPT0: Transfer Complete bank 0 interrupt Enable 0: The Transfer Complete bank 0 interrupt is disabled. 1: The Transfer Complete bank 0 interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will enable the Transfer Complete 1 interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 760 29.8.4 Device Registers - Endpoint RAM 29.8.4.1 Endpoint Descriptor structure Data Buffers EPn BK1 EPn BK0 Endpoint descriptors Reserved STATUS_BK Bank1 Reserved ADDR (2 x 0xn0) + 0x10 Reserved STATUS_BK Bank0 EXTREG PCKSIZE ADDR 2 x 0xn0 Reserved +0x01B +0x01A +0x018 +0x014 +0x010 +0x00B +0x00A +0x008 +0x004 +0x000 STATUS_BK Descriptor E0 Bank1 Reserved PCKSIZE ADDR Bank0 Reserved STATUS_BK EXTREG PCKSIZE ADDR Growing Memory Addresses Descriptor En PCKSIZE DESCADD Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 761 29.8.4.2 Address of Data Buffer Name: ADDR Offset: 0x00 & 0x10 Reset: 0xxxxxxxx Property: NA Bit 31 30 29 28 27 26 25 24 ADDR[31:24] +3 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset X X X X X X X X Bit 23 22 21 20 19 18 17 16 ADDR[23:16] +2 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset X X X X X X X X Bit 15 14 13 12 11 10 9 8 ADDR[15:8] +1 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset X X X X X X X X Bit 7 6 5 4 3 2 1 0 ADDR[7:0] +0 Access R/W R/W R/W R/W R/W R/W R R Reset X X X X X X X X z Bits 31:0 - ADDR[31:0]: Data Pointer Address Value These bits define the data pointer address as an absolute word address in RAM.The two least significant bits must be zero to ensure the start address is 32-bit aligned. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 762 29.8.4.3 Packet Size Name: PCKSIZE Offset: 0x04 & 0x14 Reset: 0xxxxxxxxx Property: NA Bit 31 30 29 28 27 +3 AUTO_ZLP Access R/W R/W R/W R/W R/W R/W R/W R/W Reset X X X X X X X X Bit 23 22 21 20 19 18 17 16 SIZE[2:0] 26 25 24 MULTI_PACKET_SIZE[13:10] MULTI_PACKET_SIZE[9:2] +2 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset X X X X X X X X Bit 15 14 13 12 11 10 9 8 MULTI_PACKET_SIZE[1:0] +1 BYTE-COUNT[13:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset X X X X X X X X Bit 7 6 5 4 3 2 1 0 BYTE_COUNT[7:0] +0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset X X X X X X X X z Bit 31 - AUTO_ZLP: Automatic Zero Length Packet This bit defines the automatic Zero Length Packet mode of the endpoint. 0: Automatic Zero Length Packet is disabled. 1: Automatic Zero Length Packet is enabled. When enabled, the USB module will manage the ZLP handshake by hardware. This bit is for IN endpoints only. When disabled the handshake should be managed by firmware. z Bits 30:28 - SIZE: Endpoint size These bits contains the maximum packet size of the endpoint. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 763 Table 29-16. Endpoint Size SIZE[2:0] Description 0x0 8 Byte 0x1 16 Byte 0x2 32 Byte 0x3 64 Byte 0x4 128 Byte (1) 0x5 256 Byte (1) 0x6 512 Byte (1) 0x7 1023 Byte (1) 1. for Isochronous endpoints only. z Bits 27:14 - MULTI_PACKET_SIZE: Multiple Packet Size These bits define the 14-bit value that is used for multi-packet transfers. For IN endpoints, MULTI_PACKET_SIZE holds the total number of bytes sent. MULTI_PACKET_SIZE should be written to zero when setting up a new transfer. For OUT endpoints, MULTI_PACKET_SIZE holds the total data size for the complete transfer. This value must be a multiple of the maximum packet size. z Bits 13:0 - BYTE_COUNT: Byte Count These bits define the 14-bit value that is used for the byte count. For IN endpoints, BYTE_COUNT holds the number of bytes to be sent in the next IN transaction. For OUT endpoint or SETUP endpoints, BYTE_COUNT holds the number of bytes received upon the last OUT or SETUP transaction. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 764 29.8.4.4 Extended Register Name: EXTREG Offset: 0x08 Reset: 0xxxxxxxx Property: NA Bit 15 14 13 12 +1 11 10 9 8 VARIABLE[10:4] Access R R/W R/W R/W R/W R/W R/W R/W Reset X X X X X X X X Bit 7 6 5 4 3 2 1 0 VARIABLE[3:0] +0 SUBPID[3:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset X X X X X X X X z Bits 15 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 14:4 - VARIABLE: VARIABLE These bits define the VARIABLE field of a received extended token.These bits are updated when the USB has answered by an handshake token ACK to a LPM transaction. See Section 2.1.1 Protocol Extension Token in the reference document "ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum". To support the USB2.0 Link Power Management addition the VARIABLE field should be read as described below. Table 29-17. VARIABLE bit fields for LPM application VARIABLES Description VARIABLE[3:0] bLinkState (1) VARIABLE[7:4] BESL (2) VARIABLE[8] bRemoteWake (1) VARIABLE[10:9] Reserved (1) for a definition of LPM Token bRemoteWake and bLinkState fields, refer to "Table 2-3 in the reference document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum". (2) for a definition of LPM Token BESL field, refer to "Table 2-3 in the reference document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum" and "Table X-X1 in Errata for ECN USB 2.0 Link Power Management. z Bits 3:0 - SUBPID: SUBPID These bits define the SUBPID field of a received extended token.These bits are updated when the USB has answered by an handshake token ACK to a LPM transaction. See Section 2.1.1 Protocol Extension Token in the reference document "ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum". Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 765 29.8.4.5 Device Status Bank Name: STATUS_BK Offset: 0x0A & 0x1A Reset: 0xxxxxxxx Property: NA Bit 7 6 5 4 3 2 +0 1 0 ERROFLOW CRCERR Access R/W R/W R/W R/W R/W R/W R/W R/W Reset X X X X X X X X z Bits 7:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 1 - ERROFLOW: Error Flow Status This bit defines the Error Flow Status. 0: No Error Flow detected. 1: A Error Flow has been detected. This bit is set when a Error Flow has been detected during transfer from/towards this bank. For OUT transfer, a NAK handshake has been sent. For Isochronous OUT transfer, an overrun condition has occurred. For IN transfer, this bit is not valid. EPSTATUS.TRFAIL0 and EPSTATUS.TRFAIL1 should reflect the flow errors. z Bit 0 - CRCERR: CRC Error This bit defines the CRC Error Status. 0: No CRC Error. 1: CRC Error detected. This bit is set when a CRC error has been detected in an isochronous OUT endpoint bank. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 766 29.8.5 Host Registers - Common 29.8.5.1 Control B Name: CTRLB Offset: 0x08 Reset: 0x0000 Property: Write-Protected Bit 15 14 13 12 11 10 9 8 L1RESUME VBUSOK BUSRESET SOFE Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SPDCONF[1:0] RESUME Access R R R R R/W R/W R/W R Reset 0 0 0 0 0 0 0 0 z Bits 15:12 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 11 - L1RESUME: Send USB L1 Resume Writing 0 to this bit has no effect. 1: Generates a USB L1 Resume on the USB bus. This bit should only be set when the Start-of-Frame generation is enabled (SOFE bit set). The duration of the USB L1 Resume is defined by the EXTREG.VARIABLE[7:4] bits field also known as BESL (See LPM ECN).See also "Extended Register" on page 797. This bit is cleared when the USB L1 Resume has been sent or when a USB reset is requested. z Bit 10 - VBUSOK: VBUS is OK 0: The USB module is notified that the VBUS on the USB line is not powered. 1: The USB module is notified that the VBUS on the USB line is powered. This notifies the USB HOST that USB operations can be started. When this bit is zero and even if the USB HOST is configured and enabled, HOST operation is halted. Setting this bit will allow HOST operation when the USB is configured and enabled. z Bit 9 - BUSRESET: Send USB Reset 0: Reset generation is disabled. It is written to zero when the USB reset is completed or when a device disconnection is detected. Writing zero has no effect. 1: Generates a USB Reset on the USB bus. z Bit 8 - SOFE: Start-of-Frame Generation Enable 0: The SOF generation is disabled and the USB bus is in suspend state. 1: Generates SOF on the USB bus in full speed and keep it alive in low speed mode. This bit is automatically set at the end of a USB reset (INTFLAG.RST) or at the end of a downstream resume (INTFLAG.DNRSM) or at the end of L1 resume. z Bits 7:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 767 z Bits 3:2 - SPDCONF: Speed Configuration for Host These bits select the host speed configuration as shown below Table 29-18. SPDCONF Selection SPDCONF[1:0] Description 0x0 Low and Full Speed capable 0x1 Reserved 0x2 Reserved 0x3 Reserved z Bit 1 - RESUME: Send USB Resume Writing 0 to this bit has no effect. 1: Generates a USB Resume on the USB bus. This bit is cleared when the USB Resume has been sent or when a USB reset is requested. z Bit 0 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 768 29.8.5.2 Host Start-of-Frame Control Register Name: HSOFC Offset: 0x0A Reset: 0x0000 Property: Write-Protected Bit 7 6 5 4 3 2 FLENCE 1 0 FLENC[3:0] Access R/W R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 During a very short period just before transmitting a Start-of-Frame, this register is locked.Thus, after writing, it is recommended to check the register value, and write this register again if necessary. This register is cleared upon a USB reset. z Bit 7 - FLENCE: Frame Length Control Enable When this bit is `1' the time between Start-of Frames can be tuned by up to 0.06% using FLENC[3:0]. Note: In Low Speed mode, FLENCE must be `0'. Table 29-19. Internal Frame Length Down-Counter Value 0 1 z Description Start-of-Frame is generated every 1ms Start-of-Frame generation depends on the signed value of FLENC[3:0]. USB Start-of-Frame period equals 1ms + (FLENC[3:0]/12000)ms Bits 3:0 - FLENC: Frame Length Control These bits define the signed value of the 4-bit FLENC that is added to the Internal Frame Length when FLENCE is `1'.The internal Frame length is the top value of the frame counter when FLENCE is zero. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 769 29.8.5.3 Status Register Name: STATUS Offset: 0x0C Reset: 0x0000 Property: Read only Bit 7 6 5 4 3 LINESTATE[1:0] 2 1 0 SPEED[1:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 7:6 - LINESTATE: USB Line State Status These bits define the current line state DP/DM. Table 29-20. Line State LINESTATE[1:0] USB Line Status 0x0 SE0/RESET 0x1 FS-J or LS-K State 0x2 FS-K or LS-J State z Bits 5:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 3:2 - SPEED[1:0]: Speed Status These bits define the current speed used by the host. Table 29-21. Speed Status SPEED[1:0] Speed Status 0x0 Full-speed mode 0x1 Reserved 0x2 Low-speed mode 0x3 Reserved z Bits 1:0 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 770 29.8.5.4 Host Frame Number Register Name: FNUM Offset: 0x10 Reset: 0x0000 Property: Write-Protected Property: Bit 15 14 13 12 11 10 9 8 Access R R R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 FNUM[10:5] FNUM[4:0] Access R/W R/W R/W R/W R/W R R R Reset 0 0 0 0 0 0 0 0 z Bits 15:14 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 13:3 - FNUM: Frame Number These bits contains the current SOF number. These bits can be written by software to initialize a new frame number value. In this case, at the next SOF, the FNUM field takes its new value. As the FNUM register lies across two consecutive byte addresses, writing byte-wise (8-bits) to the FNUM register may produce incorrect frame number generation. It is recommended to write FNUM register word-wise (32-bits) or half-word-wise (16-bits). z Bits 2:0 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 771 29.8.5.5 Host Frame Length Register Name: FLENHIGH Offset: 0x12 Reset: 0x0000 Property: Read-Only Bit 7 6 5 4 3 2 1 0 FLENHIGH[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 7:0 - FLENHIGH: Frame Length These bits contains the 8 high-order bits of the internal frame counter. Table 29-22. Counter description versus speed Table 29-23. Counter Description vs. Speed Host Register STATUS.SPEED Full Speed Description With a USB clock running at 12MHz, counter length is 12000 to ensure a SOF generation every 1 ms Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 772 29.8.5.6 Host Interrupt Enable Register Clear This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register. Name: INTENCLR Offset: 0x14 Reset: 0x0000 Property: Write-Protected Bit 15 14 13 12 11 10 9 8 DDISC DCONN Access R/ R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RAMACER UPRSM DNRSM WAKEUP RST HSOF Access R/W R/W R/W R/W R/W R/W R R Reset 0 0 0 0 0 0 0 0 z Bits 15:10 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 9 - DDISC: Device Disconnection Interrupt Enable 0: The Device Disconnection interrupt is disabled. 1: The Device Disconnection interrupt is enabled and an interrupt request will be generated when the Device Disconnection interrupt Flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Device Disconnection interrupt Enable bit and disable the corresponding interrupt request. z Bit 8 - DCONN: Device Connection Interrupt Enable 0: The Device Connection interrupt is disabled. 1: The Device Connection interrupt is enabled and an interrupt request will be generated when the Device Connection interrupt Flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Device Connection interrupt Enable bit and disable the corresponding interrupt request. z Bit 7 - RAMACER: RAM Access Interrupt Enable 0: The RAM Access interrupt is disabled. 1: The RAM Access interrupt is enabled and an interrupt request will be generated when the RAM Access interrupt Flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the RAM Access interrupt Enable bit and disable the corresponding interrupt request. z Bit 6 - UPRSM: Upstream Resume from Device Interrupt Enable 0: The Upstream Resume interrupt is disabled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 773 1: The Upstream Resume interrupt is enabled and an interrupt request will be generated when the Upstream Resume interrupt Flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Upstream Resume interrupt Enable bit and disable the corresponding interrupt request. z Bit 5 - DNRSM: Down Resume Interrupt Enable 0: The Down Resume interrupt is disabled. 1: The Down Resume interrupt is enabled and an interrupt request will be generated when the Down Resume interrupt Flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Down Resume interrupt Enable bit and disable the corresponding interrupt request. z Bit 4 - WAKEUP: Wake Up Interrupt Enable 0: The Wake Up interrupt is disabled. 1: The Wake Up interrupt is enabled and an interrupt request will be generated when the Wake Up interrupt Flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Wake Up interrupt Enable bit and disable the corresponding interrupt request. z Bit 3 - RST: BUS Reset Interrupt Enable 0: The Bus Reset interrupt is disabled. 1: The Bus Reset interrupt is enabled and an interrupt request will be generated when the Bus Reset interrupt Flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Bus Reset interrupt Enable bit and disable the corresponding interrupt request. z Bit 2 - HSOF: Host Start-of-Frame Interrupt Enable 0: The Host Start-of-Frame interrupt is disabled. 1: The Host Start-of-Frame interrupt is enabled and an interrupt request will be generated when the Host Start-ofFrame interrupt Flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Host Start-of-Frame interrupt Enable bit and disable the corresponding interrupt request. z Bits 1:0 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 774 29.8.5.7 Host Interrupt Enable Register Set This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Name: INTENSET Offset: 0x18 Reset: 0x0000 Property: Write-Protected Bit 15 14 13 12 11 10 9 8 DDISC DCONN Access R/W R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RAMACER UPRSM DNRSM WAKEUP RST HSOF Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 15:10 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 9 - DDISC: Device Disconnection Interrupt Enable 0: The Device Disconnection interrupt is disabled. 1: The Device Disconnection interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Device Disconnection interrupt bit and enable the DDSIC interrupt. z Bit 8 - DCONN: Device Connection Interrupt Enable 0: The Device Connection interrupt is disabled. 1: The Device Connection interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Device Connection interrupt bit and enable the DCONN interrupt. z Bit 7 - RAMACER: RAM Access Interrupt Enable 0: The RAM Access interrupt is disabled. 1: The RAM Access interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the RAM Access interrupt bit and enable the RAMACER interrupt. z Bit 6 - UPRSM: Upstream Resume from the device Interrupt Enable 0: The Upstream Resume interrupt is disabled. 1: The Upstream Resume interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Upstream Resume interrupt bit and enable the UPRSM interrupt. z Bit 5 - DNRSM: Down Resume Interrupt Enable 0: The Down Resume interrupt is disabled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 775 1: The Down Resume interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Down Resume interrupt Enable bit and enable the DNRSM interrupt. z Bit 4 - WAKEUP: Wake Up Interrupt Enable 0: The WakeUp interrupt is disabled. 1: The WakeUp interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Wake Up interrupt Enable bit and enable the WAKEUP interrupt request. z Bit 3 - RST: Bus Reset Interrupt Enable 0: The Bus Reset interrupt is disabled. 1: The Bus Reset interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Bus Reset interrupt Enable bit and enable the Bus RST interrupt. z Bit 2 - HSOF: Host Start-of-Frame Interrupt Enable 0: The Host Start-of-Frame interrupt is disabled. 1: The Host Start-of-Frame interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Host Start-of-Frame interrupt Enable bit and enable the HSOF interrupt. z Bits 1:0 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 776 29.8.5.8 Host Interrupt Flag Register Name: INTFLAG Offset: 0x1C Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 9 8 DDISC DCONN Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RAMACER UPRSM DNRSM WAKEUP RST HSOF Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 15:10 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 9 - DDISC: Device Disconnection Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when the device has been removed from the USB Bus and will generate an interrupt if INTENCLR/SET.DDISC is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the DDISC Interrupt Flag. z Bit 8 - DCONN: Device Connection Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when a new device has been connected to the USB BUS and will generate an interrupt if INTENCLR/SET.DCONN is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the DCONN Interrupt Flag. z Bit 7 - RAMACER: RAM Access Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when a RAM access error occurs during an OUT stage and will generate an interrupt if INTENCLR/SET.RAMACER is one. Writing a zero to this bit has no effect. z Bit 6 - UPRSM: Upstream Resume from the Device Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when the USB has received an Upstream Resume signal from the Device and will generate an interrupt if INTENCLR/SET.UPRSM is one. Writing a zero to this bit has no effect. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 777 z Bit 5 - DNRSM: Down Resume Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when the USB has sent a Down Resume and will generate an interrupt if INTENCLR/SET.DRSM is one. Writing a zero to this bit has no effect. z Bit 4 - WAKEUP: Wake Up Interrupt Flag This flag is cleared by writing a one. This flag is set when: z The host controller is in suspend mode (SOFE is zero) and an upstream resume from the device is detected. z The host controller is in suspend mode (SOFE is zero) and an device disconnection is detected. z The host controller is in operational state (VBUSOK is one) and an device connection is detected. In all cases it will generate an interrupt if INTENCLR/SET.WAKEUP is one. Writing a zero to this bit has no effect. z Bit 3 - RST: Bus Reset Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when a Bus "Reset" has been sent to the Device and will generate an interrupt if INTENCLR/SET.RST is one. Writing a zero to this bit has no effect. z Bit 2 - HSOF: Host Start-of-Frame Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when a USB "Host Start-of-Frame" in Full Speed or a keep-alive in Low Speed has been sent (every 1 ms) and will generate an interrupt if INTENCLR/SET.HSOF is one. The value of the FNUM register is updated. Writing a zero to this bit has no effect. z Bits 1:0 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 778 29.8.5.9 Pipe Interrupt Summary Register Name: PINTSMRY Offset: 0x20 Reset: 0x00000000 Property: Read-only Bit 15 14 13 12 11 10 9 8 PINT[15:8] +1 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PINT[7:0] +0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 15:0 - PINT: Pipe Interrupt Summary Register The flag PINT[n] is set when an interrupt is triggered by the pipe n. See "Host Pipe Interrupt Flag Register" on page 787 register in the Host Pipe Register section. This bit will be cleared when there are no interrupts pending for Pipe n. Writing to this bit has no effect. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 779 29.8.6 Host Registers - Pipe 29.8.6.1 Host Pipe n Configuration Register Name: PCFGn Offset: 0x100 + (n x 0x20) Reset: 0x0000 Property: Write-Protected Bit 7 6 5 4 3 PTYPE[2:0] 2 1 BK 0 PTOKEN[1:0] Access R R R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:6 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 5:3 - PTYPE: Type of the Pipe These bits contains the pipe type. Table 29-24. Type of the Pipe PTYPE[2:0] Description 0x0 Pipe is disabled 0x1 Pipe is enabled and configured as CONTROL 0x2 Pipe is enabled and configured as ISO 0x3 Pipe is enabled and configured as BULK 0x4 Pipe is enabled and configured as INTERRUPT 0x5 Pipe is enabled and configured as EXTENDED 0x06-0x7 Reserved Theses bits are cleared upon sending a USB reset. z Bit 2 - BK: Pipe Bank 0: A single bank is used for the pipe. 1: A dual bank is used for the pipe. This bit selects the number of banks for the pipe. For control endpoints writing a zero to this bit is required as only Bank0 is used for Setup/In/Out transactions. This bit is cleared when a USB reset is sent. Table 29-25. Bank BK (1) Description 0x0 Single-bank endpoint 0x1 Dual-bank endpoint Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 780 Bank field is ignored when PTYPE is configured as EXTENDED 1. Bits 1:0 - PTOKEN: Pipe Token These bits contains the pipe token. z Table 29-26. Pipe Token PTOKEN[1:0] (1) Description 0x0 SETUP (2) 0x1 IN 0x2 OUT 0x3 Reserved 1. PTOKEN field is ignored when PTYPE is configured as EXTENDED 2. Available only when PTYPE is configured as CONTROL Theses bits are cleared upon sending a USB reset. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 781 29.8.6.2 Interval for the Bulk-Out/Ping transaction Register Name: BINTERVAL Offset: 0x103 + (n x 0x20) Reset: 0x0000 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 BINTERVAL[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:0 - BINTERVAL: BINTERVAL These bits contains the Ping/Bulk-out period. These bits are cleared when a USB reset is sent or when PEN[n] is zero. BINTERVAL Description =0 Multiple consecutive OUT token is sent in the same frame until it is acked by the peripheral >0 One OUT token is sent every BINTERVAL frame until it is acked by the peripheral Depending from the type of pipe the desired period is defined as: Table 29-27. Pipe Type PTYPE Description Interrupt 1 ms to 255 ms Isochronous 2^(Binterval) * 1 ms Bulk or control 1 ms to 255 ms EXT LPM bInterval ignored. Always 1 ms when a NYET is received. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 782 29.8.6.3 Pipe Status Clear Register n Name: PSTATUSCLR Offset: 0x104 + (n x 0x20) Reset: 0x0000 Property: Write-Protected Bit 7 6 BK1RDY BK0RDY Access RW1 RW1 R RW1 R RW1 R RW1 Reset 0 0 0 0 0 0 0 0 z 5 4 3 PFREEZE 2 1 CURBK 0 DTGL Bit 7 - BK1RDY: Bank 1 Ready Clear Writing a zero to this bit has no effect. Writing a one to this bit will clear PSTATUS.BK1RDY bit. z Bit 6 - BK0RDY: Bank 0 Ready Clear Writing a zero to this bit has no effect. Writing a one to this bit will clear PSTATUS.BK0RDY bit. z Bit 5 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 4 - PFREEZE: Pipe Freeze Clear Writing a zero to this bit has no effect. Writing a one to this bit will clear PSTATUS.PFREEZE bit. z Bit 3 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 2 - CURBK: Current Bank Clear Writing a zero to this bit has no effect. Writing a one to this bit will clear PSTATUS.CURBK bit. z Bit 1 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 0 - DTGL: Data Toggle Clear Writing a zero to this bit has no effect. Writing a one to this bit will clear PSTATUS.DTGL bit. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 783 29.8.6.4 Pipe Status Set Register n Name: PSTATUSSET Offset: 0x105 + (n x 0x20) Reset: 0x0000 Property: Write-Protected Bit 7 6 BK1RDY BK0RDY Access RW1 RW1 R RW1 R RW1 R RW1 Reset 0 0 0 0 0 0 0 0 z 5 4 3 PFREEZE 2 1 CURBK 0 DTGL Bit 7- BK1RDY: Bank 1 Ready Set Writing a zero to this bit has no effect. Writing a one to this bit will set the bit PSTATUS.BK1RDY. z Bit 6 - BK0RDY: Bank 0 Ready Set Writing a zero to this bit has no effect. Writing a one to this bit will set the bit PSTATUS.BK0RDY. z Bit 5 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 4 - PFREEZE: Pipe Freeze Set Writing a zero to this bit has no effect. Writing a one to this bit will set PSTATUS.PFREEZE bit. z Bit 3 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 2 - CURBK: Current Bank Set Writing a zero to this bit has no effect. Writing a one to this bit will set PSTATUS.CURBK bit. z Bit 3 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 0 - DTGL: Data Toggle Set Writing a zero to this bit has no effect. Writing a one to this bit will set PSTATUS.DTGL bit. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 784 29.8.6.5 Pipe Status Register n Name: PSTATUS Offset: 0x106 + (n x 0x20) Reset: 0x0000 Property: Write-Protected Bit 7 6 BK1RDY BK0RDY Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z 5 4 3 PFREEZE 2 1 CURBK 0 DTGL Bit 7- BK1RDY: Bank 1 is ready 0: The bank number 1 is not ready: For IN the bank is empty. For Control/OUT the bank is not yet fill in. 1: The bank number 1 is ready: For IN the bank is filled full. For Control/OUT the bank is filled in. Writing a one to the bit EPSTATUSCLR.BK1RDY will clear this bit. Writing a one to the bit EPSTATUSSET.BK1RDY will set this bit. This bank is not used for Control pipe. z Bit 6 - BK0RDY: Bank 0 is ready 0: The bank number 0 is not ready: For IN the bank is not empty. For Control/OUT the bank is not yet fill in. 1: The bank number 0 is ready: For IN the bank is filled full. For Control/OUT the bank is filled in. Writing a one to the bit EPSTATUSCLR.BK0RDY will clear this bit. Writing a one to the bit EPSTATUSSET.BK0RDY will set this bit. This bank is the only one used for Control pipe. z Bit 5 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 4 - PFREEZE: Pipe Freeze 0: The Pipe operates in normal operation. 1: The Pipe is frozen and no additional requests will be sent to the device on this pipe address. Writing a one to the bit EPSTATUSCLR.PFREEZE will clear this bit. Writing a one to the bit EPSTATUSSET.PFREEZE will set this bit. z This bit is also set by the hardware: z When a STALL handshake has been received. z After a PIPE has been enabled (rising of bit PEN.N). z When an LPM transaction has completed whatever handshake is returned or the transaction was timed-out. z When a pipe transfer was completed with a pipe error. See "Host Pipe Interrupt Flag Register" on page 787. When PFREEZE bit is set while a transaction is in progress on the USB bus, this transaction will be properly completed. PFREEZE bit will be read as "1" only when the ongoing transaction will have been completed. z Bit 3 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 2 - CURBK: Current Bank 0: The bank0 is the bank that will be used in the next single/multi USB packet. 1: The bank1 is the bank that will be used in the next single/multi USB packet. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 785 z Bit 5 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bit 0 - DTGL: Data Toggle Sequence 0: The PID of the next expected transaction will be zero: data 0. 1: The PID of the next expected transaction will be one: data 1. Writing a one to the bit EPSTATUSCLR.DTGL will clear this bit. Writing a one to the bit EPSTATUSSET.DTGL will set this bit. This bit is toggled automatically by hardware after a data transaction. This bit will reflect the data toggle in regards of the token type (IN/OUT/SETUP). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 786 29.8.6.6 Host Pipe Interrupt Flag Register Name: PINTFLAG Offset: 0x107 + (n x 0x20) Reset: 0x0000 Property: - Bit 7 6 5 4 3 2 1 0 STALL TXSTP PERR TRFAIL TRCPT1 TRCPT0 Access R R RW1 RW1 RW1 RW1 RW1 RW1 Reset 0 0 0 0 0 0 0 0 z Bits 7:6 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 5 - STALL: STALL Received Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when a stall occurs and will generate an interrupt if PINTENCLR/SET.STALL is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the STALL Interrupt Flag. z Bit 4 - TXSTP: Transmitted Setup Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when a Transfer Complete occurs and will generate an interrupt if PINTENCLR/SET.TXSTP is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the TXSTP Interrupt Flag. z Bit 3 - PERR: Pipe Error Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when a pipe error occurs and will generate an interrupt if PINTENCLR/SET.PERR is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the PERR Interrupt Flag. z Bit 2 - TRFAIL: Transfer Fail Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when a Transfer Fail occurs and will generate an interrupt if PINTENCLR/SET.TRFAIL is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the TRFAIL Interrupt Flag. z Bit 1 - TRCPT1: Transfer Complete 1 interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when a Transfer Complete occurs and will generate an interrupt if PINTENCLR/SET.TRCPT1 is one. PINTFLAG.TRCPT1 is set for a double bank IN/OUT pipe when current bank is 1. Writing a zero to this bit has no effect. Writing a one to this bit clears the TRCPT1 Interrupt Flag. z Bit 0 - TRCPT0: Transfer Complete 0 interrupt Flag This flag is cleared by writing a one to the flag. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 787 This flag is set when a Transfer complete occurs and will generate an interrupt if PINTENCLR/SET.TRCPT0 is one. PINTFLAG.TRCPT0 is set for a single bank IN/OUT pipe or a double bank IN/OUT pipe when current bank is 0. Writing a zero to this bit has no effect. Writing a one to this bit clears the TRCPT0 Interrupt Flag. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 788 29.8.6.7 Host Pipe Interrupt Enable Register Name: PINTENCLR Offset: 0x108 + (n x 0x20) Reset: 0x0000 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 STALL TXSTP PERR TRFAIL TRCPT1 TRCPT0 Access R R RW1 RW1 RW1 RW1 RW1 RW1 Reset 0 0 0 0 0 0 0 0 This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Pipe Interrupt Enable Set (PINTENSET) register. This register is cleared by USB reset or when PEN[n] is zero. z Bits 7:6 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 5 - STALL: Received Stall Interrupt Enable 0: The received Stall interrupt is disabled. 1: The received Stall interrupt is enabled and an interrupt request will be generated when the received Stall interrupt Flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Received Stall interrupt Enable bit and disable the corresponding interrupt request. z Bit 4 - TXSTP: Transmitted Setup Interrupt Enable 0: The Transmitted Setup interrupt is disabled. 1: The Transmitted Setup interrupt is enabled and an interrupt request will be generated when the Transmitted Setup interrupt Flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Transmitted Setup interrupt Enable bit and disable the corresponding interrupt request. z Bit 3 - PERR: Pipe Error Interrupt Enable 0: The Pipe Error interrupt is disabled. 1: The Pipe Error interrupt is enabled and an interrupt request will be generated when the Pipe Error interrupt Flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Pipe Error interrupt Enable bit and disable the corresponding interrupt request. z Bit 2 - TRFAIL: Transfer Fail Interrupt Enable 0: The Transfer Fail interrupt is disabled. 1: The Transfer Fail interrupt is enabled and an interrupt request will be generated when the Transfer Fail interrupt Flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Transfer Fail interrupt Enable bit and disable the corresponding interrupt request. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 789 z Bit 1 - TRCPT1: Transfer Complete Bank 1 interrupt Enable 0: The Transfer Complete Bank 1 interrupt is disabled. 1: The Transfer Complete Bank 1 interrupt is enabled and an interrupt request will be generated when the Transfer Complete interrupt Flag 1 is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Transfer Complete interrupt Enable bit 1 and disable the corresponding interrupt request. z Bit 0 - TRCPT0: Transfer Complete Bank 0 interrupt Enable 0: The Transfer Complete Bank 0 interrupt is disabled. 1: The Transfer Complete Bank 0 interrupt is enabled and an interrupt request will be generated when the Transfer Complete interrupt 0 Flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Transfer Complete interrupt Enable bit 0 and disable the corresponding interrupt request. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 790 29.8.6.8 Host Interrupt Pipe Set Register Name: PINTENSET Offset: 0x109 + (n x 0x20) Reset: 0x0000 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 STALL TXSTP PERR TRFAIL TRCPT1 TRCPT0 Access R R RW1 RW1 RW1 RW1 RW1 RW1 Reset 0 0 0 0 0 0 0 0 This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Pipe Interrupt Enable Set (PINTENCLR) register. This register is cleared by USB reset or when PEN[n] is zero. z Bits 7:6 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 5 - STALL: Stall Interrupt Enable 0: The Stall interrupt is disabled. 1: The Stall interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will enable the Stall interrupt. z Bit 4 - TXSTP: Transmitted Setup Interrupt Enable 0: The Transmitted Setup interrupt is disabled. 1: The Transmitted Setup interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will enable the Transmitted Setup interrupt. z Bit 3 - PERR: Pipe Error Interrupt Enable 0: The Pipe Error interrupt is disabled. 1: The Pipe Error interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will enable the Pipe Error interrupt. z Bit 2 - TRFAIL: Transfer Fail Interrupt Enable 0: The Transfer Fail interrupt is disabled. 1: The Transfer Fail interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will enable the Transfer Fail interrupt. z Bit 1 - TRCPT1: Transfer Complete 1 interrupt Enable 0: The Transfer Complete 1 interrupt is disabled. 1: The Transfer Complete 1 interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will enable the Transfer Complete interrupt Enable bit 1. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 791 z Bit 0 - TRCPT0: Transfer Complete 0 interrupt Enable 0: The Transfer Complete 0 interrupt is disabled. 1: The Transfer Complete 0 interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will enable the Transfer Complete interrupt Enable bit 0. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 792 29.8.7 Host Registers - Pipe RAM 29.8.7.1 Pipe Descriptor Structure Data Buffers Pn BK1 Pn BK0 Pipe descriptors Reserved STATUS_PIPE Descriptor Pn Bank1 CTRL_BK Reserved Reserved PCKSIZE ADDR (2 x 0xn0) + 0x10 Reserved STATUS_PIPE Bank0 CTRL_PIPE STATUS_BK EXTREG PCKSIZE ADDR Descriptor P0 Bank1 CTRL_BK Reserved Reserved PCKSIZE ADDR Reserved STATUS_PIPE Bank0 CTRL_PIPE STATUS_BK EXTREG PCKSIZE ADDR +0x01F +0x01E +0x01C +0x01A +0x018 +0x014 +0x010 +0x00F +0x00E +0x00C +0x00A +0x008 +0x004 +0x000 Growing Memory Addresses Reserved STATUS_PIPE 2 x 0xn0 DESCADD Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 793 29.8.7.2 Address of the Data Buffer Name: ADDR Offset: 0x00 & 0x10 Reset: 0xxxxxxxx Property: NA Bit 31 30 29 28 27 26 25 24 ADDR[31:24] +3 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset X X X X X X X X Bit 23 22 21 20 19 18 17 16 ADDR[23:16] +2 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset X X X X X X X X Bit 15 14 13 12 11 10 9 8 ADDR[15:8] +1 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset X X X X X X X X Bit 7 6 5 4 3 2 1 0 ADDR[7:0] +0 Access R/W R/W R/W R/W R/W R/W R R Reset X X X X X X X X z Bits 31:0 - ADDR[31:0]: Data Pointer Address Value These bits define the data pointer address as an absolute double word address in RAM. The two least significant bits must be zero to ensure the descriptor is 32-bit aligned. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 794 29.8.7.3 Packet Size Name: PCKSIZE Offset: 0x04 & 0x14 Reset: 0xxxxxxxx Property: NA Bit 31 30 29 28 27 +3 AUTO_ZLP Access R/W R/W R/W R/W R/W R/W R/W R/W Reset X X X X X X X X Bit 23 22 21 20 19 18 17 16 SIZE[2:0] 26 25 24 MULTI_PACKET_SIZE[13:10] MULTI_PACKET_SIZE[9:2] +2 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset X X X X X X X X Bit 15 14 13 12 11 10 9 8 MULTI_PACKET_SIZE[1:0] +1 BYTE-COUNT[13:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset X X X X X X X X Bit 7 6 5 4 3 2 1 0 BYTE_COUNT[7:0] +0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset X X X X X X X X z Bit 31- AUTO_ZLP: Automatic Zero Length Packet This bit defines the automatic Zero Length Packet mode of the pipe. 0: Automatic Zero Length Packet is disabled. 1: Automatic Zero Length Packet is enabled. When enabled, the USB module will manage the ZLP handshake by hardware. This bit is for OUT pipes only. When disabled the handshake should be managed by firmware. z Bits 30:28 - SIZE: Pipe size These bits contains the size of the pipe. Theses bits are cleared upon sending a USB reset. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 795 Table 29-28. Pipe Size SIZE[2:0] Description 0x0 8 Byte 0x1 16 Byte 0x2 32 Byte 0x3 64 Byte 0x4 128 Byte (1) 0x5 256 Byte (1) 0x6 512 Byte (1) 1024 Byte in HS mode (1) 0x7 1023 Byte in FS mode (1) (1) for Isochronous pipe only. z Bits 27:14 - MULTI_PACKET_SIZE: Multi Packet IN or OUT size These bits define the 14-bit value that is used for multi-packet transfers. For IN pipes, MULTI_PACKET_SIZE holds the total number of bytes sent. MULTI_PACKET_SIZE should be written to zero when setting up a new transfer. For OUT pipes, MULTI_PACKET_SIZE holds the total data size for the complete transfer. This value must be a multiple of the maximum packet size. z Bits 13:0 - BYTE_COUNT: Byte Count These bits define the 14-bit value that contains number of bytes sent in the last OUT or SETUP transaction for an OUT pipe, or of the number of bytes to be received in the next IN transaction for an input pipe. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 796 29.8.7.4 Extended Register Name: EXTREG Offset: 0x08 Reset: 0xxxxxxxx Property: NA Bit 15 14 13 12 +1 11 10 9 8 VARIABLE[10:4] Access R R/W R/W R/W R/W R/W R/W R/W Reset X X X X X X X X Bit 7 6 5 4 3 2 1 0 VARIABLE[3:0] +0 SUBPID[3:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset X X X X X X X X z Bits 15 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 14:4 - VARIABLE: Extended variable These bits define the VARIABLE field sent with extended token. See "Section 2.1.1 Protocol Extension Token in the reference document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum." To support the USB2.0 Link Power Management addition the VARIABLE field should be set as described below. Table 29-29. VARIABLE bit fields for LPM application VARIABLE Description VARIABLE[3:0] bLinkState (1) VARIABLE[7:4] BESL (See LPM ECN) (2) VARIABLE[8] bRemoteWake (1) VARIABLE[10:9] Reserved 1. for a definition of LPM Token bRemoteWake and bLinkState fields, refer to "Table 2-3 in the reference document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum" 2. for a definition of LPM Token BESL field, refer to "Table 2-3 in the reference document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum" and "Table X-X1 in Errata for ECN USB 2.0 Link Power Management. z Bits 3:0 - SUBPID: SUBPID These bits define the SUBPID field sent with extended token. See "Section 2.1.1 Protocol Extension Token in the reference document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum". To support the USB2.0 Link Power Management addition the SUBPID field should be set as described in "Table 2.2 SubPID Types in the reference document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum". Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 797 29.8.7.5 Host Status Bank Name: STATUS_BK Offset: 0x0A & 0x1A Reset: 0xxxxxxxx Property: NA Bit 7 6 5 4 3 2 +0 1 0 ERROFLOW CRCERR Access R/W R/W R/W R/W R/W R/W R/W R/W Reset X X X X X X X X z Bits 7:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 2 - ERROFLOW: Error Flow Status This bit defines the Error Flow Status. 0: No Error Flow detected. 1: A Error Flow has been detected. This bit is set when a Error Flow has been detected during transfer from/towards this bank. For IN transfer, a NAK handshake has been received. For OUT transfer, a NAK handshake has been received. For Isochronous IN transfer, an overrun condition has occurred. For Isochronous OUT transfer, an underflow condition has occurred. z Bit 0 - CRCERR: CRC Error This bit defines the CRC Error Status. 0: No CRC Error. 1: CRC Error detected. This bit is set when a CRC error has been detected in an isochronous IN endpoint bank. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 798 29.8.7.6 Host Control Pipe Name: CTRL_PIPE Offset: 0x0C Reset: 0xxxxxxxx Property: Write-Protected, Write-Synchronized, Read-Synchronized Bit 15 14 13 12 11 10 PERMAX[3:0] +1 9 8 PEPNUM[3:0] Access R R/W R/W R/W R/W R/W R/W R/W Reset X X X X X X X X Bit 7 6 5 4 3 2 1 0 +0 PDADDR[6:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset X X X X X X X X z Bits 15:12 - PERMAX: Pipe Error Max Number These bits define the maximum number of error for this Pipe before freezing the pipe automatically. z Bits 11:8 - PEPNUM: Pipe EndPoint Number These bits define the number of endpoint for this Pipe. z Bits 7 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 6:0 - PDADDR: Pipe Device Address These bits define the Device Address for this pipe. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 799 29.8.7.7 Host Status Pipe Name: STATUS_PIPE Offset: 0x0E & 0x1E Reset: 0xxxxxxxx Property: Write-Protected, Write-Synchronized, Read-Synchronized Bit 15 14 13 12 11 10 9 8 Access R R/W R/W R/W R/W R/W R/W R/W Reset X X X X X X X X Bit 7 6 5 4 3 2 1 0 CRC16ER TOUTER PIDER DAPIDER DTGLER +1 ERCNT[2:0] +0 Access R R R R R R/W R/W R/W Reset X X X X X X X X z Bits 15:8 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 7:5 - ERCNT: Pipe Error Counter These bits define the number of errors detected on the pipe. z Bit 4 - CRC16ER: CRC16 ERROR This bit defines the CRC16 Error Status. 0: No CRC 16 Error detected. 1: A CRC 16 error has been detected. This bit is set when a CRC 16 error has been detected during a IN transactions. z Bit 3 - TOUTER: TIME OUT ERROR This bit defines the Time Out Error Status. 0: No Time Out Error detected. 1: A Time Out error has been detected. This bit is set when a Time Out error has been detected during a USB transaction. z Bit 2 - PIDER: PID ERROR This bit defines the PID Error Status. 0: No PID Error detected. 1: A PID error has been detected. This bit is set when a PID error has been detected during a USB transaction. z Bit 1 - DAPIDER: Data PID ERROR This bit defines the PID Error Status. 0: No Data PID Error detected. 1: A Data PID error has been detected. This bit is set when a Data PID error has been detected during a USB transaction. z Bit 0 - DTGLER: Data Toggle Error This bit defines the Data Toggle Error Status. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 800 0: No Data Toggle Error. 1: Data Toggle Error detected. This bit is set when a Data Toggle Error has been detected. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 801 30. ADC - Analog-to-Digital Converter 30.1 Overview The Analog-to-Digital Converter (ADC) converts analog signals to digital values. The ADC has 12-bit resolution, and is capable of converting up to 350ksps. The input selection is flexible, and both differential and single-ended measurements can be performed. An optional gain stage is available to increase the dynamic range. In addition, several internal signal inputs are available. The ADC can provide both signed and unsigned results. ADC measurements can be started by either application software or an incoming event from another peripheral in the device. ADC measurements can be started with predictable timing, and without software intervention. Both internal and external reference voltages can be used. An integrated temperature sensor is available for use with the ADC. The bandgap voltage as well as the scaled I/O and core voltages can also be measured by the ADC. The ADC has a compare function for accurate monitoring of user-defined thresholds, with minimum software intervention required. The ADC may be configured for 8-, 10- or 12-bit results, reducing the conversion time. ADC conversion results are provided left- or right-adjusted, which eases calculation when the result is represented as a signed value. It is possible to use DMA to move ADC results directly to memory or peripherals when conversions are done. 30.2 Features z 8-, 10- or 12-bit resolution z Up to 350,000 samples per second (350ksps) z Differential and single-ended inputs z Up to 8 analog inputs z 12 positive and 6 negative, including internal and external z Four internal inputs Bandgap Temperature sensor z Scaled core supply z Scaled I/O supply z z z 1/2x to 16x gain z Single, continuous and pin-scan conversion options z Windowing monitor with selectable channel z Conversion range: z z Vref [1v to VDDANA - 0.6V] ADCx * GAIN [0V to -Vref ] z Built-in internal reference and external reference options z Four bits for reference selection z Event-triggered conversion for accurate timing (one event input) z Optional DMA transfer of conversion result z Hardware gain and offset compensation z Averaging and oversampling with decimation to support, up to 16-bit result z Selectable sampling time 30.3 Block Diagram Figure 30-1. ADC Block Diagram Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 802 CTRLA WINCTRL AVGCTRL WINLT SAMPCTRL WINUT EVCTRL OFFSETCORR SWTRIG GAINCORR INPUTCTRL ADC0 ... ADCn INT.SIG ADC POST PROCESSING RESULT ADC0 ... ADCn INT.SIG INT1V CTRLB INTVCC VREFB PRESCALER REFCTRL 30.4 Signal Description Signal Name Type Description VREFB Analog input External reference voltage B ADC[19..0](1) Analog input Analog input channels Note: 1. Refer to "Configuration Summary" on page 4 for details on exact number of analog input channels. Refer to "I/O Multiplexing and Considerations" on page 12 for details on the pin mapping for this peripheral. One signal can be mapped on several pins. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 803 30.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 30.5.1 I/O Lines Using the ADC's I/O lines requires the I/O pins to be configured using the port configuration (PORT). Refer to "PORT" on page 373 for details. 30.5.2 Power Management The ADC will continue to operate in any sleep mode where the selected source clock is running. The ADC's interrupts can be used to wake up the device from sleep modes. The events can trigger other operations in the system without exiting the sleep modes. Refer to "PM - Power Manager" on page 112 for details on the different sleep modes. 30.5.3 Clocks The ADC bus clock (CLK_ADC_APB) can be enabled and disabled in the Power Manager, and the default state of CLK_ADC_APB can be found in the Table 14-1. A generic clock (GCLK_ADC) is required to clock the ADC. This clock must be configured and enabled in the Generic Clock Controller (GCLK) before using the ADC. Refer "GCLK - Generic Clock Controller" on page 90 for details. This generic clock is asynchronous to the bus clock (CLK_ADC_APB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. Refer to "Synchronization" on page 813 for further details. 30.5.4 DMA The DMA request lines are connected to the DMA controller (DMAC). Using the ADC DMA requests, requires the DMA controller to be configured first. Refer ro "DMAC - Direct Memory Access Controller" on page 267 for details. 30.5.5 Interrupts The interrupt request line is connected to the interrupt controller. Using ADC interrupts requires the interrupt controller to be configured first. Refer to "Nested Vector Interrupt Controller" on page 29 for details. 30.5.6 Events Events are connected to the Event System. Refer to "EVSYS - Event System" on page 400 for details. 30.5.7 Debug Operation When the CPU is halted in debug mode, the ADC will halt normal operation. The ADC can be forced to continue operation during debugging. Refer to the Debug Control register (DBGCTRL) for details. 30.5.8 Register Access Protection All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the following register: z Interrupt Flag Status and Clear register (INTFLAG) Write-protection is denoted by the Write-Protection property in the register description. When the CPU is halted in debug mode or the CPU reset is extended, all write-protection is automatically disabled. Write-protection does not apply for accesses through an external debugger. Refer to "PAC - Peripheral Access Controller" on page 36 for details. 30.5.9 Analog Connections I/O-pins AIN0 to AIN19 as well as the VREFB reference voltage pin are analog inputs to the ADC. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 804 30.5.10 Calibration The values BIAS_CAL and LINEARITY_CAL from the production test must be loaded from the NVM Software Calibration Area into the ADC Calibration register (CALIB) by software to achieve specified accuracy. Refer to "NVM Software Calibration Area Mapping" on page 26 for more details. 30.6 Functional Description 30.6.1 Principle of Operation By default, the ADC provides results with 12-bit resolution. 8-bit or 10-bit results can be selected in order to reduce the conversion time. The ADC has an oversampling with decimation option that can extend the resolution to 16 bits. The input values can be either internal (e.g., internal temperature sensor) or external (connected I/O pins). The user can also configure whether the conversion should be single-ended or differential. 30.6.2 Basic Operation 30.6.2.1 Initialization Before enabling the ADC, the asynchronous clock source must be selected and enabled, and the ADC reference must be configured. The first conversion after the reference is changed must not be used. All other configuration registers must be stable during the conversion. The source for GCLK_ADC is selected and enabled in the System Controller (SYSCTRL). Refer to "SYSCTRL - System Controller" on page 143 for more details. When GCLK_ADC is enabled, the ADC can be enabled by writing a one to the Enable bit in the Control Register A (CTRLA.ENABLE). 30.6.2.2 Enabling, Disabling and Reset The ADC is enabled by writing a one to the Enable bit in the Control A register (CTRLA.ENABLE). The ADC is disabled by writing a zero to CTRLA.ENABLE. The ADC is reset by writing a one to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in the ADC, except DBGCTRL, will be reset to their initial state, and the ADC will be disabled. Refer to the CTRLA register for details. The ADC must be disabled before it is reset. 30.6.2.3 Basic Operation In the most basic configuration, the ADC sample values from the configured internal or external sources (INPUTCTRL register). The rate of the conversion is dependent on the combination of the GCLK_ADC frequency and the clock prescaler. To convert analog values to digital values, the ADC needs first to be initialized, as described in "Initialization" on page 805. Data conversion can be started either manually, by writing a one to the Start bit in the Software Trigger register (SWTRIG.START), or automatically, by configuring an automatic trigger to initiate the conversions. A free-running mode could be used to continuously convert an input channel. There is no need for a trigger to start the conversion. It will start automatically at the end of previous conversion. The automatic trigger can be configured to trigger on many different conditions. The result of the conversion is stored in the Result register (RESULT) as it becomes available, overwriting the result from the previous conversion. To avoid data loss if more than one channel is enabled, the conversion result must be read as it becomes available (INTFLAG.RESRDY). Failing to do so will result in an overrun error condition, indicated by the OVERRUN bit in the Interrupt Flag Status and Clear register (INTFLAG.OVERRUN). To use an interrupt handler, the corresponding bit in the Interrupt Enable Set register (INTENSET) must be written to one. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 805 30.6.3 Prescaler The ADC is clocked by GCLK_ADC. There is also a prescaler in the ADC to enable conversion at lower clock rates. Refer to CTRLB for details on prescaler settings. Figure 30-2. ADC Prescaler DIV512 DIV256 DIV128 DIV64 DIV32 DIV16 DIV8 9-BIT PRESCALER DIV4 GCLK_ADC CTRLB.PRESCALER[2:0] CLK_ADC The propagation delay of an ADC measurement depends on the selected mode and is given by: z Single-shot mode: Resolution 1 + ---------------------------- + DelayGain 2 PropagationDelay = -------------------------------------------------------------------------f CLK - ADC z Free-running mode: Resolution ---------------------------+ DelayGain 2 PropagationDelay = ---------------------------------------------------------------f CLK - ADC Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 806 Table 30-1. Delay Gain Delay Gain (in CLK_ADC Period) Free-running mode Name Single shot mode INTPUTCTRL.GAIN[3:0] Differential Mode Single-Ended Mode Differential mode Single-Ended mode 1X 0x0 0 0 0 1 2X 0x1 0 1 0.5 1.5 4X 0x2 1 1 1 2 8X 0x3 1 2 1.5 2.5 16X 0x4 2 2 2 3 Reserved 0x5 ... 0xE Reserved Reserved Reserved Reserved DIV2 0xF 0 1 0.5 1.5 30.6.4 ADC Resolution The ADC supports 8-bit, 10-bit and 12-bit resolutions. Resolution can be changed by writing the Resolution bit group in the Control B register (CTRLB.RESSEL). After a reset, the resolution is set to 12 bits by default. 30.6.5 Differential and Single-Ended Conversions The ADC has two conversion options: differential and single-ended. When measuring signals where the positive input is always at a higher voltage than the negative input, the single-ended conversion should be used in order to have full 12bit resolution in the conversion, which has only positive values. The negative input must be connected to ground. This ground could be the internal GND, IOGND or an external ground connected to a pin. Refer to INPUTCTRL for selection details. If the positive input may go below the negative input, creating some negative results, the differential mode should be used in order to get correct results. The configuration of the conversion is done in the Differential Mode bit in the Control B register (CTRLB.DIFFMODE). These two types of conversion could be run in single mode or in free-running mode. When set up in free-running mode, an ADC input will continuously sample and do new conversions. The INTFLAG.RESRDY bit will be set at the end of each conversion. 30.6.5.1 Conversion Timing Figure 30-3 shows the ADC timing for a single conversion without gain. The writing of the ADC Start Conversion bit (SWTRIG.START) or Start Conversion Event In bit (EVCTRL.STARTEI) must occur at least one CLK_ADC_APB cycle before the CLK_ADC cycle on which the conversion starts. The input channel is sampled in the first half CLK_ADC period. The sampling time can be increased by using the Sampling Time Length bit group in the Sampling Time Control register (SAMPCTRL.SAMPLEN). Refer to Figure 30-4 for example on increased sampling time. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 807 Figure 30-3. ADC Timing for One Conversion in Differential Mode without Gain 1 2 3 4 5 6 7 8 CLK_ ADC START SAMPLE INT Converting Bit MS B 10 9 8 7 6 5 4 3 2 1 LS B Figure 30-4. ADC Timing for One Conversion in Differential Mode without Gain, but with Increased Sampling Time 1 2 3 4 5 6 7 8 9 10 11 CLK_ ADC START SAMPLE INT Converting Bit MS B 10 9 8 7 6 5 4 3 2 1 LS B Figure 30-5. ADC Timing for Free Running in Differential Mode without Gain 2 1 3 4 5 6 7 9 8 10 11 12 13 6 4 2 0 14 15 16 8 6 CLK_ ADC START SAMPLE INT Converting Bit 11 10 9 8 7 6 5 4 3 2 1 0 11 10 9 8 7 5 3 1 11 10 9 7 5 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 808 Figure 30-6. ADC Timing for One Conversion in Single-Ended Mode without Gain 1 2 3 4 5 6 7 8 9 10 11 CLK_ADC START SAMPLE AMPLIFY INT Converting Bit MS B 10 9 8 7 6 5 4 3 2 1 LS B Figure 30-7. ADC Timing for Free Running in Single-Ended Mode without Gain 2 1 3 4 5 6 7 9 8 10 11 12 13 14 9 7 5 3 1 15 16 CLK_ADC START SAMPLE AMPLIFY INT Converting Bit 11 10 9 8 7 6 5 4 3 2 1 0 11 10 8 6 4 2 0 11 10 30.6.6 Accumulation The result from multiple consecutive conversions can be accumulated. The number of samples to be accumulated is specified by writing to the Number of Samples to be Collected field in the Average Control register (AVGCTRL.SAMPLENUM) as described in Table 30-2. When accumulating more than 16 samples, the result will be too large for the 16-bit RESULT register. To avoid overflow, the result is shifted right automatically to fit within the 16 available bits. The number of automatic right shifts are specified in Table 30-2. Note that to be able to perform the accumulation of two or more samples, the Conversion Result Resolution field in the Control B register (CTRLB.RESSEL) must be written to one. Table 30-2. Accumulation Number of Accumulated Samples AVGCTRL. SAMPLENUM Intermediate Result Precision Number of Automatic Right Shifts Final Result Precision Automatic Division Factor 1 0x0 12 bits 0 12 bits 0 2 0x1 13 bits 0 13 bits 0 4 0x2 14 bits 0 14 bits 0 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 809 Number of Accumulated Samples AVGCTRL. SAMPLENUM Intermediate Result Precision Number of Automatic Right Shifts Final Result Precision Automatic Division Factor 8 0x3 15 bits 0 15 bits 0 16 0x4 16 bits 0 16 bits 0 32 0x5 17 bits 1 16 bits 2 64 0x6 18 bits 2 16 bits 4 128 0x7 19 bits 3 16 bits 8 256 0x8 20 bits 4 16 bits 16 512 0x9 21 bits 5 16 bits 32 1024 0xA 22 bits 6 16 bits 64 Reserved 0xB -0xF 12 bits 12 bits 0 30.6.7 Averaging Averaging is a feature that increases the sample accuracy, though at the cost of reduced sample rate. This feature is suitable when operating in noisy conditions. Averaging is done by accumulating m samples, as described in "Accumulation" on page 809, and divide the result by m. The averaged result is available in the RESULT register. The number of samples to be accumulated is specified by writing to AVGCTRL.SAMPLENUM as described in Table 30-3. The division is obtained by a combination of the automatic right shift described above, and an additional right shift that must be specified by writing to the Adjusting Result/Division Coefficient field in AVGCTRL (AVGCTRL.ADJRES) as described in Table 30-3. Note that to be able to perform the averaging of two or more samples, the Conversion Result Resolution field in the Control B register (CTRLB.RESSEL) must be written to one. 1 Averaging AVGCTRL.SAMPLENUM samples will reduce the effective sample rate by ------------------------------------------------------------------- . AVGCTRL.SAMPLENUM When the required average is reached, the INTFLAG.RESRDY bit is set. Table 30-3. Averaging Number of Accumulated Samples AVGCTRL. SAMPLENUM Intermediate Result Precision Number of Automatic Right Shifts Division Factor AVGCTRL. ADJRES 1 0x0 12 bits 0 1 0x0 2 0x1 13 0 2 0x1 4 0x2 14 0 4 8 0x3 15 0 16 0x4 16 32 0x5 64 Total Number of Right Shifts Final Result Precision Automatic Division Factor 12 bits 0 1 12 bits 0 0x2 2 12 bits 0 8 0x3 3 12 bits 0 0 16 0x4 4 12 bits 0 17 1 16 0x4 5 12 bits 2 0x6 18 2 16 0x4 6 12 bits 4 128 0x7 19 3 16 0x4 7 12 bits 8 256 0x8 20 4 16 0x4 8 12 bits 16 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 810 Number of Accumulated Samples AVGCTRL. ADJRES Total Number of Right Shifts Final Result Precision Automatic Division Factor 16 0x4 9 12 bits 32 16 0x4 10 12 bits 64 12 bits 0 AVGCTRL. SAMPLENUM Intermediate Result Precision Number of Automatic Right Shifts Division Factor 512 0x9 21 5 1024 0xA 22 6 Reserved 0xB -0xF 0x0 30.6.8 Oversampling and Decimation By using oversampling and decimation, the ADC resolution can be increased from 12 bits to up to 16 bits. To increase the resolution by n bits, 4n samples must be accumulated. The result must then be shifted right by n bits. This right shift is a combination of the automatic right shift and the value written to AVGCTRL.ADJRES. To obtain the correct resolution, the ADJRES must be configured as described in the table below. This method will result in n bit extra LSB resolution. Table 30-4. Configuration Required for Oversampling and Decimation Result Resolution Number of Samples to Average 1 AVGCTRL.SAMPLENUM[3:0] Number of Automatic Right Shifts AVGCTRL.ADJRES[2:0] 13 bits 4 =4 0x2 0 0x1 14 bits 42 = 16 0x4 0 0x2 15 bits 43 = 64 0x6 2 0x1 16 bits 44 = 256 0x8 4 0x0 30.6.9 Window Monitor The window monitor allows the conversion result to be compared to some predefined threshold values. Supported modes are selected by writing the Window Monitor Mode bit group in the Window Monitor Control register (WINCTRL.WINMODE[2:0]). Thresholds are given by writing the Window Monitor Lower Threshold register (WINLT) and Window Monitor Upper Threshold register (WINUT). If differential input is selected, the WINLT and WINUT are evaluated as signed values. Otherwise they are evaluated as unsigned values. Another important point is that the significant WINLT and WINUT bits are given by the precision selected in the Conversion Result Resolution bit group in the Control B register (CTRLB.RESSEL). This means that if 8-bit mode is selected, only the eight lower bits will be considered. In addition, in differential mode, the eighth bit will be considered as the sign bit even if the ninth bit is zero. The INTFLAG.WINMON interrupt flag will be set if the conversion result matches the window monitor condition. 30.6.10 Offset and Gain Correction Inherent gain and offset errors affect the absolute accuracy of the ADC. The offset error is defined as the deviation of the actual ADC's transfer function from an ideal straight line at zero input voltage. The offset error cancellation is handled by the Offset Correction register (OFFSETCORR). The offset correction value is subtracted from the converted data before writing the Result register (RESULT). The gain error is defined as the deviation of the last output step's midpoint from the ideal straight line, after compensating for offset error. The gain error cancellation is handled by the Gain Correction register (GAINCORR). To correct these two errors, the Digital Correction Logic Enabled bit in the Control B register (CTRLB.CORREN) must be written to one. Offset and gain error compensation results are both calculated according to: Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 811 Result = ( Conversion value - OFFSETCORR ) GAINCORR In single conversion, a latency of 13 GCLK_ADC is added to the availability of the final result. Since the correction time is always less than the propagation delay, this latency appears in free-running mode only during the first conversion. After that, a new conversion will be initialized when a conversion completes. All other conversion results are available at the defined sampling rate. Figure 30-8. ADC Timing Correction Enabled START CONV0 CONV1 CORR0 CONV2 CONV3 CORR1 CORR2 CORR3 30.6.11 DMA, Interrupts and Events Table 30-5. Module Request for ADC Condition Interrupt request Event output Result Ready x x Overrun x Window Monitor x Synchronization Ready x Event input DMA request x DMA request is cleared When result register is read x Start Conversion x ADC Flush x 30.6.11.1 DMA Operation The ADC generates the following DMA request: z Result Conversion Ready (RESRDY): the request is set when a conversion result is available and cleared when the RESULT register is read. When the averaging operation is enabled, the DMA request is set when the averaging is completed and result is available. 30.6.11.2 Interrupts The ADC has the following interrupt sources: Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 812 z Result Conversion Ready: RESRDY. This is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. z Overrun: OVERRUN z Window Monitor: WINMON. This is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. z Synchronization Ready: SYNCRDY. This is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear register (INTENCLR) register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the peripheral is reset. An interrupt flag is cleared by writing a one to the corresponding bit in the INTFLAG register. Each peripheral can have one interrupt request line per interrupt source or one common interrupt request line for all the interrupt sources. This is device dependent. Refer to "Nested Vector Interrupt Controller" on page 29 for details. If the peripheral has one common interrupt request line for all the interrupt sources, the user must read the INTFLAG register to determine which interrupt condition is present. 30.6.11.3 Events The peripheral can generate the following output events: z Result Ready (RESRDY) z Window Monitor (WINMON) Output events must be enabled to be generated. Writing a one to an Event Output bit in the Event Control register (EVCTRL.xxEO) enables the corresponding output event. Writing a zero to this bit disables the corresponding output event. The events must be correctly routed in the Event System. Refer to "EVSYS - Event System" on page 400 for details. The peripheral can take the following actions on an input event: z ADC start conversion (START) z ADC conversion flush (FLUSH) Input events must be enabled for the corresponding action to be taken on any input event. Writing a one to an Event Input bit in the Event Control register (EVCTRL.xxEI) enables the corresponding action on the input event. Writing a zero to this bit disables the corresponding action on the input event. Note that if several events are connected to the peripheral, the enabled action will be taken on any of the incoming events. The events must be correctly routed in the Event System. Refer to "EVSYS - Event System" on page 400 for details. 30.6.12 Sleep Mode Operation The Run in Standby bit in the Control A register (CTRLA.RUNSTDBY) controls the behavior of the ADC during standby sleep mode. When the bit is zero, the ADC is disabled during sleep, but maintains its current configuration. When the bit is one, the ADC continues to operate during sleep. Note that when RUNSTDBY is zero, the analog blocks are powered off for the lowest power consumption. This necessitates a start-up time delay when the system returns from sleep. When RUNSTDBY is one, any enabled ADC interrupt source can wake up the CPU. While the CPU is sleeping, ADC conversion can only be triggered by events. 30.6.13 Synchronization Due to the asynchronicity between CLK_ADC_APB and GCLK_ADC, some registers must be synchronized when accessed. A register can require: z Synchronization when written Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 813 z Synchronization when read z Synchronization when written and read z No synchronization When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. The Synchronization Ready interrupt can be used to signal when synchronization is complete. If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is stalled. The following bits need synchronization when written: z Software Reset bit in the Control A register (CTRLA.SWRST) z Enable bit in the Control A register (CTRLA.ENABLE) The following registers need synchronization when written: z Control B (CTRLB) z Software Trigger (SWTRIG) z Window Monitor Control (WINCTRL) z Input Control (INPUTCTRL) z Window Upper/Lower Threshold (WINUT/WINLT) Write-synchronization is denoted by the Write-Synchronized property in the register description. The following registers need synchronization when read: z Software Trigger (SWTRIG) z Input Control (INPUTCTRL) z Result (RESULT) Read-synchronization is denoted by the Read-Synchronized property in the register description. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 814 30.7 Register Summary Table 30-6. Register Summary Offset Name Bit Pos. 0x00 CTRLA 7:0 0x01 REFCTRL 7:0 0x02 AVGCTRL 7:0 0x03 SAMPCTRL 7:0 0x04 0x05 CTRLB 0x06 Reserved 0x07 Reserved 0x08 WINCTRL 0x09 ... 0x0B Reserved 0x0C SWTRIG 0x0D ... 0x0F Reserved RUNSTDBY REFCOMP SAMPLENUM[3:0] SAMPLEN[5:0] 7:0 RESSEL[1:0] CORREN FREERUN PRESCALER[2:0] 7:0 WINMODE[2:0] 7:0 START 7:0 MUXPOS[4:0] 15:8 MUXNEG[4:0] 0x13 23:16 INPUTOFFSET[3:0] 31:24 0x15 Reserved 0x16 INTENCLR 7:0 SYNCRDY 0x17 INTENSET 7:0 SYNCRDY 0x18 INTFLAG 7:0 SYNCRDY 0x19 STATUS 0x1B 0x1C 0x1D RESULT WINLT 0x1E Reserved 0x1F Reserved 0x20 0x21 WINUT 0x22 Reserved 0x23 Reserved 0x24 0x25 0x26 0x27 GAINCORR OFFSETCOR R 7:0 WINMONEO RESRDYEO RESULT[7:0] 15:8 RESULT[15:8] 7:0 WINLT[7:0] 15:8 WINLT[15:8] 7:0 WINUT[7:0] 15:8 WINUT[15:8] 7:0 GAINCORR[7:0] STARTEI WINMON OVERRUN RESRDY WINMON OVERRUN RESRDY WINMON OVERRUN RESRDY GAINCORR[11:8] 15:8 7:0 SYNCEI SYNCBUSY 7:0 15:8 FLUSH GAIN[3:0] EVCTRL 7:0 DIFFMODE INPUTSCAN[3:0] 0x14 0x1A LEFTADJ 15:8 0x11 INPUTCTRL SWRST REFSEL[3:0] ADJRES[2:0] 0x10 0x12 ENABLE OFFSETCORR[7:0] OFFSETCORR[11:8] Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 815 Offset 0x28 0x29 0x2A Name CALIB DBGCTRL Bit Pos. 7:0 15:8 7:0 LINEARITY_CAL[7:0] BIAS_CAL[2:0] DBGRUN Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 816 30.8 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protected property in each individual register description. Refer to "Register Access Protection" on page 804 for details. Some registers require synchronization when read and/or written. Synchronization is denoted by the Write-Synchronized or the Read-Synchronized property in each individual register description. Refer to "Synchronization" on page 813 for details. Some registers are enable-protected, meaning they can be written only when the ADC is disabled. Enable-protection is denoted by the Enable-Protected property in each individual register description. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 817 30.8.1 Control A Name: CTRLA Offset: 0x00 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 RUNSTDBY ENABLE SWRST Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 2 - RUNSTDBY: Run in Standby This bit indicates whether the ADC will continue running in standby sleep mode or not: 0: The ADC is halted during standby sleep mode. 1: The ADC continues normal operation during standby sleep mode. z Bit 1 - ENABLE: Enable 0: The ADC is disabled. 1: The ADC is enabled. Due to synchronization, there is a delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately and the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete. z Bit 0 - SWRST: Software Reset 0: There is no reset operation ongoing. 1: The reset operation is ongoing. Writing a zero to this bit has no effect. Writing a one to this bit resets all registers in the ADC, except DBGCTRL, to their initial state, and the ADC will be disabled. Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 818 30.8.2 Reference Control Name: REFCTRL Offset: 0x01 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 REFCOMP Access Reset z 1 0 REFSEL[3:0] R/W R R R R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 - REFCOMP: Reference Buffer Offset Compensation Enable The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. 0: Reference buffer offset compensation is disabled. 1: Reference buffer offset compensation is enabled. z Bits 6:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 3:0 - REFSEL[3:0]: Reference Selection These bits select the reference for the ADC according to Table 30-7. Table 30-7. Reference Selection REFSEL[3:0] Name Description 0x0 INT1V 0x1 INTVCC0 1/1.48 VDDANA 0x2 INTVCC1 1/2 VDDANA (only for VDDANA > 2.0V) 0x3 - 0x4 VREFB 0x5-0xF - 1.0V voltage reference Reserved External reference Reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 819 30.8.3 Average Control Name: AVGCTRL Offset: 0x02 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 ADJRES[2:0] 2 1 0 SAMPLENUM[3:0] Access R R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bit 7 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 6:4 - ADJRES[2:0]: Adjusting Result / Division Coefficient These bits define the division coefficient in 2n steps. z Bits 3:0 - SAMPLENUM[3:0]: Number of Samples to be Collected These bits define how many samples should be added together.The result will be available in the Result register (RESULT). Note: if the result width increases, CTRLB.RESSEL must be changed. Table 30-8. Number of Samples to be Collected SAMPLENUM[3:0] Name 0x0 1 1 sample 0x1 2 2 samples 0x2 4 4 samples 0x3 8 8 samples 0x4 16 16 samples 0x5 32 32 samples 0x6 64 64 samples 0x7 128 128 samples 0x8 256 256 samples 0x9 512 512 samples 0xA 1024 1024 samples 0xB-0xF Description Reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 820 30.8.4 Sampling Time Control Name: SAMPCTRL Offset: 0x03 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 SAMPLEN[5:0] Access R R R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:6 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 5:0 - SAMPLEN[5:0]: Sampling Time Length These bits control the ADC sampling time in number of half CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. Sampling time is set according to the equation: CLK ADC Sampling time = ( SAMPLEN + 1 ) ---------------------- 2 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 821 30.8.5 Control B Name: CTRLB Offset: 0x04 Reset: 0x0000 Property: Write-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 PRESCALER[2:0] Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CORREN FREERUN LEFTADJ DIFFMODE RESSEL[1:0] Access R R R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 15:11 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 10:8 - PRESCALER[2:0]: Prescaler Configuration These bits define the ADC clock relative to the peripheral clock according to Table 30-9. Table 30-9. Prescaler Configuration PRESCALER[2:0] Name Description 0x0 DIV4 Peripheral clock divided by 4 0x1 DIV8 Peripheral clock divided by 8 0x2 DIV16 Peripheral clock divided by 16 0x3 DIV32 Peripheral clock divided by 32 0x4 DIV64 Peripheral clock divided by 64 0x5 DIV128 Peripheral clock divided by 128 0x6 DIV256 Peripheral clock divided by 256 0x7 DIV512 Peripheral clock divided by 512 z Bits 7:6 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 5:4 - RESSEL[1:0]: Conversion Result Resolution These bits define whether the ADC completes the conversion at 12-, 10- or 8-bit result resolution. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 822 Table 30-10. Conversion Result Resolution z RESSEL[1:0] Name Description 0x0 12BIT 12-bit result 0x1 16BIT For averaging mode output 0x2 10BIT 10-bit result 0x3 8BIT 8-bit result Bit 3 - CORREN: Digital Correction Logic Enabled 0: Disable the digital result correction. 1: Enable the digital result correction. The ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. Conversion time will be increased by X cycles according to the value in the Offset Correction Value bit group in the Offset Correction register. z Bit 2 - FREERUN: Free Running Mode 0: The ADC run is single conversion mode. 1: The ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. z Bit 1 - LEFTADJ: Left-Adjusted Result 0: The ADC conversion result is right-adjusted in the RESULT register. 1: The ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. Writing this bit to zero (default) will right-adjust the value in the RESULT register. z Bit 0 - DIFFMODE: Differential Mode 0: The ADC is running in singled-ended mode. 1: The ADC is running in differential mode. In this mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 823 30.8.6 Window Monitor Control Name: WINCTRL Offset: 0x08 Reset: 0x00 Property: Write-Protected, Write-Synchronized Bit 7 6 5 4 3 2 1 0 WINMODE[2:0] Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 2:0 - WINMODE[2:0]: Window Monitor Mode These bits enable and define the window monitor mode. Table 30-11 shows the mode selections. Table 30-11. Window Monitor Mode WINMODE[2:0] Name 0x0 DISABLE No window mode (default) 0x1 MODE1 Mode 1: RESULT > WINLT 0x2 MODE2 Mode 2: RESULT < WINUT 0x3 MODE3 Mode 3: WINLT < RESULT < WINUT 0x4 MODE4 Mode 4: !(WINLT < RESULT < WINUT) 0x5-0x7 Description Reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 824 30.8.7 Software Trigger Name: SWTRIG Offset: 0x0C Reset: 0x00 Property: Write-Protected, Write-Synchronized Bit 7 6 5 4 3 2 1 0 START FLUSH Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 1 - START: ADC Start Conversion 0: The ADC will not start a conversion. 1: The ADC will start a conversion. The bit is cleared by hardware when the conversion has started. Setting this bit when it is already set has no effect. Writing this bit to zero will have no effect. z Bit 0 - FLUSH: ADC Conversion Flush 0: No flush action. 1: The ADC pipeline will be flushed. A flush will restart the ADC clock on the next peripheral clock edge, and all conversions in progress will be aborted and lost. This bit is cleared until the ADC has been flushed. After the flush, the ADC will resume where it left off; i.e., if a conversion was pending, the ADC will start a new conversion. Writing this bit to zero will have no effect. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 825 30.8.8 Input Control Name: INPUTCTRL Offset: 0x10 Reset: 0x00000000 Property: Write-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 GAIN[3:0] Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 INPUTOFFSET[3:0] Access INPUTSCAN[3:0] R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 MUXNEG[4:0] Access R R R R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MUXPOS[4:0] Access R R R R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 31:28 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 27:24 - GAIN[3:0]: Gain Factor Selection These bits set the gain factor of the ADC gain stage according to the values shown in Table 30-12. Table 30-12. Gain Factor Selection GAIN[3:0] Name Description 0x0 1X 1x 0x1 2X 2x 0x2 4X 4x 0x3 8X 8x Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 826 GAIN[3:0] Name 0x4 16X 0x5-0xE 0xF z Description 16x Reserved DIV2 1/2x Bits 23:20 - INPUTOFFSET[3:0]: Positive Mux Setting Offset The pin scan is enabled when INPUTSCAN != 0. Writing these bits to a value other than zero causes the first conversion triggered to be converted using a positive input equal to MUXPOS + INPUTOFFSET. Setting this register to zero causes the first conversion to use a positive input equal to MUXPOS. After a conversion, the INPUTOFFSET register will be incremented by one, causing the next conversion to be done with the positive input equal to MUXPOS + INPUTOFFSET. The sum of MUXPOS and INPUTOFFSET gives the input that is actually converted. z Bits 19:16 - INPUTSCAN[3:0]: Number of Input Channels Included in Scan This register gives the number of input sources included in the pin scan. The number of input sources included is INPUTSCAN + 1. The input channels included are in the range from MUXPOS + INPUTOFFSET to MUXPOS + INPUTOFFSET + INPUTSCAN. The range of the scan mode must not exceed the number of input channels available on the device. z Bits 15:13 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 12:8 - MUXNEG[4:0]: Negative Mux Input Selection These bits define the Mux selection for the negative ADC input. Table 30-13 shows the possible input selections. Table 30-13. Negative Mux Input Selection Value Name Description 0x00 PIN0 Reserved 0x01 PIN1 Reserved 0x02 PIN2 Reserved 0x03 PIN3 Reserved 0x04 PIN4 ADC AIN4 pin(1) 0x05 PIN5 ADC AIN5 pin(1) 0x06 PIN6 ADC AIN6 pin 0x07 PIN7 ADC AIN7 pin 0x08-0x17 - Reserved 0x18 GND Internal ground 0x19 IOGND I/O ground 0x1A-0x1F - Reserved Note: 1. Only available in SAM R21G. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 827 z Bits 7:5 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 4:0 - MUXPOS[4:0]: Positive Mux Input Selection These bits define the Mux selection for the positive ADC input. Table 30-14 shows the possible input selections. If the internal bandgap voltage or temperature sensor input channel is selected, then the Sampling Time Length bit group in the SamplingControl register must be written. Table 30-14. Positive Mux Input Selection MUXPOS[4:0] Group configuration Description 0x00 Reserved 0x01 Reserved 0x02 Reserved 0x03 Reserved 0x04 PIN4 ADC AIN4 pin(1) 0x05 PIN5 ADC AIN5 pin(1) 0x06 PIN6 ADC AIN6 pin 0x07 PIN7 ADC AIN7 pin 0x08 Reserved 0x09 Reserved 0x0A PIN10 ADC AIN10 pin(1) 0x0B PIN11 ADC AIN11 pin(1) 0x0C Reserved 0x0D Reserved 0x0E Reserved 0x0F Reserved 0x10 PIN16 ADC AIN16 pin 0x11 PIN17 ADC AIN17 pin 0x12-0x17 Reserved 0x18 TEMP Temperature reference 0x19 BANDGAP Bandgap voltage 0x1A SCALEDCOREVCC 1/4 scaled core supply 0x1B SCALEDIOVCC 1/4 scaled I/O supply 0x1C-0x1F Note: 1. Reserved Only available in SAM R21G. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 828 30.8.9 Event Control Name: EVCTRL Offset: 0x14 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 WINMONEO RESRDYEO 3 2 1 0 SYNCEI STARTEI Access R R R/W R/W R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:6 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 5 - WINMONEO: Window Monitor Event Out This bit indicates whether the Window Monitor event output is enabled or not and an output event will be generated when the window monitor detects something. 0: Window Monitor event output is disabled and an event will not be generated. 1: Window Monitor event output is enabled and an event will be generated. z Bit 4 - RESRDYEO: Result Ready Event Out This bit indicates whether the Result Ready event output is enabled or not and an output event will be generated when the conversion result is available. 0: Result Ready event output is disabled and an event will not be generated. 1: Result Ready event output is enabled and an event will be generated. z Bits 3:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 1 - SYNCEI: Synchronization Event In 0: A flush and new conversion will not be triggered on any incoming event. 1: A flush and new conversion will be triggered on any incoming event. z Bit 0 - STARTEI: Start Conversion Event In 0: A new conversion will not be triggered on any incoming event. 1: A new conversion will be triggered on any incoming event. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 829 30.8.10 Interrupt Enable Clear This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Name: INTENCLR Offset: 0x16 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 SYNCRDY WINMON OVERRUN RESRDY Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 3 - SYNCRDY: Synchronization Ready Interrupt Enable 0: The Synchronization Ready interrupt is disabled. 1: The Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the Synchronization Ready interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Synchronization Ready Interrupt Enable bit and the corresponding interrupt request. z Bit 2 - WINMON: Window Monitor Interrupt Enable 0: The window monitor interrupt is disabled. 1: The window monitor interrupt is enabled, and an interrupt request will be generated when the Window Monitor interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Window Monitor Interrupt Enable bit and the corresponding interrupt request. z Bit 1 - OVERRUN: Overrun Interrupt Enable 0: The Overrun interrupt is disabled. 1: The Overrun interrupt is enabled, and an interrupt request will be generated when the Overrun interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Overrun Interrupt Enable bit and the corresponding interrupt request. z Bit 0 - RESRDY: Result Ready Interrupt Enable 0: The Result Ready interrupt is disabled. 1: The Result Ready interrupt is enabled, and an interrupt request will be generated when the Result Ready interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Result Ready Interrupt Enable bit and the corresponding interrupt request. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 830 30.8.11 Interrupt Enable Set This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Name: INTENSET Offset: 0x17 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 SYNCRDY WINMON OVERRUN RESRDY Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 3 - SYNCRDY: Synchronization Ready Interrupt Enable 0: The Synchronization Ready interrupt is disabled. 1: The Synchronization Ready interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Synchronization Ready Interrupt Enable bit, which enables the Synchronization Ready interrupt. z Bit 2 - WINMON: Window Monitor Interrupt Enable 0: The Window Monitor interrupt is disabled. 1: The Window Monitor interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Window Monitor Interrupt bit and enable the Window Monitor interrupt. z Bit 1 - OVERRUN: Overrun Interrupt Enable 0: The Overrun interrupt is disabled. 1: The Overrun interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Overrun Interrupt bit and enable the Overrun interrupt. z Bit 0 - RESRDY: Result Ready Interrupt Enable 0: The Result Ready interrupt is disabled. 1: The Result Ready interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Result Ready Interrupt bit and enable the Result Ready interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 831 30.8.12 Interrupt Flag Status and Clear Name: INTFLAG Offset: 0x18 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 SYNCRDY WINMON OVERRUN RESRDY Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:4 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 3 - SYNCRDY: Synchronization Ready This flag is cleared by writing a one to the flag. This flag is set on a one-to-zero transition of the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY), except when caused by an enable or software reset, and will generate an interrupt request if INTENCLR/SET.SYNCRDY is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Synchronization Ready interrupt flag. z Bit 2 - WINMON: Window Monitor This flag is cleared by writing a one to the flag or by reading the RESULT register. This flag is set on the next GCLK_ADC cycle after a match with the window monitor condition, and an interrupt request will be generated if INTENCLR/SET.WINMON is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Window Monitor interrupt flag. z Bit 1 - OVERRUN: Overrun This flag is cleared by writing a one to the flag. This flag is set if RESULT is written before the previous value has been read by CPU, and an interrupt request will be generated if INTENCLR/SET.OVERRUN is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Overrun interrupt flag. z Bit 0 - RESRDY: Result Ready This flag is cleared by writing a one to the flag or by reading the RESULT register. This flag is set when the conversion result is available, and an interrupt will be generated if INTENCLR/SET.RESRDY is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Result Ready interrupt flag. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 832 30.8.13 Status Name: STATUS Offset: 0x19 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 SYNCBUSY Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bit 7 - SYNCBUSY: Synchronization Busy This bit is cleared when the synchronization of registers between the clock domains is complete. This bit is set when the synchronization of registers between clock domains is started. z Bits 6:0 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 833 30.8.14 Result Name: RESULT Offset: 0x1A Reset: 0x0000 Property: Read-Synchronized Bit 15 14 13 12 11 10 9 8 RESULT[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RESULT[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 15:0 - RESULT[15:0]: Result Conversion Value These bits will hold up to a 16-bit ADC result, depending on the configuration. In single-ended without averaging mode, the ADC conversion will produce a 12-bit result, which can be left- or right-shifted, depending on the setting of CTRLB.LEFTADJ. If the result is left-adjusted (CTRLB.LEFTADJ), the high byte of the result will be in bit position [15:8], while the remaining 4 bits of the result will be placed in bit locations [7:4]. This can be used only if an 8-bit result is required; i.e., one can read only the high byte of the entire 16-bit register. If the result is not left-adjusted (CTRLB.LEFTADJ) and no oversampling is used, the result will be available in bit locations [11:0], and the result is then 12 bits long. If oversampling is used, the result will be located in bit locations [15:0], depending on the settings of the Average Control register (AVGCTRL). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 834 30.8.15 Window Monitor Lower Threshold Name: WINLT Offset: 0x1C Reset: 0x0000 Property: Write-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 WINLT[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 WINLT[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 15:0 - WINLT[15:0]: Window Lower Threshold If the window monitor is enabled, these bits define the lower threshold value. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 835 30.8.16 Window Monitor Upper Threshold Name: WINUT Offset: 0x20 Reset: 0x0000 Property: Write-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 WINUT[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 WINUT[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 15:0 - WINUT[15:0]: Window Upper Threshold If the window monitor is enabled, these bits define the upper threshold value. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 836 30.8.17 Gain Correction Name: GAINCORR Offset: 0x24 Reset: 0x0000 Property: Write-Protected Bit 15 14 13 12 11 10 9 8 GAINCORR[11:8] Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 GAINCORR[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 15:12 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 11:0 - GAINCORR[11:0]: Gain Correction Value If the CTRLB.CORREN bit is one, these bits define how the ADC conversion result is compensated for gain error before being written to the result register. The gaincorrection is a fractional value, a 1-bit integer plusan 11-bit fraction, and therefore 1/2 <= GAINCORR < 2. GAINCORR values range from 0.10000000000 to 1.11111111111. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 837 30.8.18 Offset Correction Name: OFFSETCORR Offset: 0x26 Reset: 0x0000 Property: Write-Protected Bit 15 14 13 12 11 10 9 8 OFFSETCORR[11:8] Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OFFSETCORR[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 15:12 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 11:0 - OFFSETCORR[11:0]: Offset Correction Value If the CTRLB.CORREN bit is one, these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. This OFFSETCORR value is in two's complement format. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 838 30.8.19 Calibration Name: CALIB Offset: 0x28 Reset: 0x0000 Property: Write-Protected Bit 15 14 13 12 11 10 9 8 BIAS_CAL[2:0] Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 LINEARITY_CAL[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 15:11 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 10:8 - BIAS_CAL[2:0]: Bias Calibration Value This value from production test must be loaded from the NVM software calibration area into the CALIB register by software to achieve the specified accuracy. The value must be copied only, and must not be changed. z Bits 7:0 - LINEARITY_CAL[7:0]: Linearity Calibration Value This value from production test must be loaded from the NVM software calibration area into the CALIB register by software to achieve the specified accuracy. The value must be copied only, and must not be changed. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 839 30.8.20 Debug Control Name: DBGCTRL Offset: 0x2A Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 DBGRUN Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:1 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 0 - DBGRUN: Debug Run 0: The ADC is halted during debug mode. 1: The ADC continues normal operation during debug mode. This bit can be changed only while the ADC is disabled. This bit should be written only while a conversion is not ongoing. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 840 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 841 31. 31.1 AC - Analog Comparators Overview The Analog Comparator (AC) supports two individual comparators. Each comparator (COMP) compares the voltage levels on two inputs, and provides a digital output based on this comparison. Each comparator may be configured to generate interrupt requests and/or peripheral events upon several different combinations of input change. Hysteresis and propagation delay are two important properties of the comparators; dynamic behavior. Both parameters may be adjusted to achieve the optimal operation for each application. The input selection includes four shared analog port pins and several internal signals. Each comparator output state can also be output on a pin for use by external devices. The comparators are always grouped in pairs on each port. The AC module may implement one pair. These are called Comparator 0 (COMP0) and Comparator 1 (COMP1). They have identical behaviors, but separate control registers. The pair can be set in window mode to compare a signal to a voltage range instead of a single voltage level. 31.2 Features z Two individual comparators z Selectable propagation delay versus current consumption z Selectable hysteresis z On/Off z Analog comparator outputs available on pins z Asynchronous or synchronous z Flexible input selection Four pins selectable for positive or negative inputs Ground (for zero crossing) z Bandgap reference voltage z 64-level programmable VDDANA scaler per comparator z z z Interrupt generation on: Rising or falling edge Toggle z End of comparison z z z Window function interrupt generation on: Signal above window Signal inside window z Signal below window z Signal outside window z z z Event generation on: z z Comparator output Window function inside/outside window z Optional digital filter on comparator output z Low-power option z Single-shot support Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 842 31.3 Block Diagram Figure 31-1. Analog Comparator Block Diagram AIN0 + CMP0 COMP0 AIN1 - HYSTERESIS VDDANA SCALER INTERRUPTS ENABLE INTERRUPT MODE COMPCTRLn WINCTRL ENABLE BANDGAP EVENTS GCLK_AC HYSTERESIS + AIN2 INTERRUPT SENSITIVITY CONTROL & WINDOW FUNCTION CMP1 COMP1 AIN3 31.4 - Signal Description Signal Name Type Description AIN[3..0] Analog input Comparator inputs CMP[1..0] Digital output Comparator outputs Refer to "I/O Multiplexing and Considerations" on page 12 for details on the pin mapping for this peripheral. One signal can be mapped on several pins. 31.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 31.5.1 I/O Lines Using the AC's I/O lines requires the I/O pins to be configured. Refer to the PORT chapter for details. Refer to "PORT" on page 373 for details. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 843 31.5.2 Power Management The AC will continue to operate in any sleep mode where the selected source clock is running. The AC's interrupts can be used to wake up the device from sleep modes. The events can trigger other operations in the system without exiting sleep modes. Refer to "PM - Power Manager" on page 112 for details on the different sleep modes. 31.5.3 Clocks The AC bus clock (CLK_AC_APB) can be enabled and disabled in the Power Manager, and the default state of the CLK_AC_APB can be found in the Peripheral Clock Masking section of "PM - Power Manager" on page 112. Two generic clocks (GCLK_AC_DIG and GCLK_AC_ANA) are used by the AC. The digital clock (GCLK_AC_DIG) is required to provide the sampling rate for the comparators, while the analog clock (GCLK_AC_ANA) is required for lowvoltage operation (VDDANA < 2.5V) to ensure that the resistance of the analog input multiplexors remains low. These clocks must be configured and enabled in the Generic Clock Controller before using the peripheral. Refer to "GCLK - Generic Clock Controller" on page 90 for details. These generic clocks are asynchronous to the CLK_AC_APB clock. Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. Refer to "Synchronization" on page 853 for further details. 31.5.4 DMA Not applicable. 31.5.5 Interrupts The interrupt request line is connected to the Interrupt Controller. Using the AC interrupts requires the Interrupt Controller to be configured first. Refer to "Nested Vector Interrupt Controller" on page 29 for details. 31.5.6 Events The events are connected to the Event System. Using the events requires the Event System to be configured first. Refer to "EVSYS - Event System" on page 400 for details. 31.5.7 Debug Operation When the CPU is halted in debug mode, the peripheral continues normal operation. If the peripheral is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 31.5.8 Register Access Protection All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the following registers: z Control B register (CTRLB) z Interrupt Flag register (INTFLAG) Write-protection is denoted by the Write-Protected property in the register description. Write-protection does not apply for accesses through an external debugger. Refer to "PAC - Peripheral Access Controller" on page 36 for details. 31.5.9 Analog Connections Each comparator has up to four I/O pins that can be used as analog inputs. Each pair of comparators shares the same four pins. These pins must be configured for analog operation before using them as comparator inputs. Any internal reference source, such as a bandgap reference voltage, must be configured and enabled prior to its use as a comparator input. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 844 31.5.10 Other Dependencies Not applicable. 31.6 Functional Description 31.6.1 Principle of Operation Each comparator has one positive input and one negative input. Each positive input may be chosen from a selection of analog input pins. Each negative input may be chosen from a selection of analog input pins or internal inputs, such as a bandgap reference voltage. The digital output from the comparator is one when the difference between the positive and the negative input voltage is positive, and zero otherwise. The individual comparators can be used independently (normal mode) or grouped in pairs to generate a window comparison (window mode). 31.6.2 Basic Operation 31.6.2.1 Initialization Before enabling the AC, the input and output events must be configured in the Event Control register (EVCTRL). These settings cannot be changed while the AC is enabled. Each individual comparator must also be configured by its respective Comparator Control register (COMPCTRL0) before that comparator is enabled. These settings cannot be changed while the comparator is enabled. z Select the desired measurement mode with COMPCTRLx.SINGLE. See "Starting a Comparison" on page 845 for more details z Select the desired hysteresis with COMPCTRLx.HYST. See "Input Hysteresis" on page 849 for more details z Select the comparator speed versus power with COMPCTRLx.SPEED. See "Propagation Delay vs. Power Consumption" on page 849 for more details z Select the interrupt source with COMPCTRLx.INTSEL z Select the positive and negative input sources with the COMPCTRLx.MUXPOS and COMPCTRLx.MUXNEG bits. See section "Selecting Comparator Inputs" on page 847 for more details z Select the filtering option with COMPCTRLx.FLEN 31.6.2.2 Enabling, Disabling and Resetting The AC is enabled by writing a one to the Enable bit in the Control A register (CTRLA.ENABLE). The individual comparators must be also enabled by writing a one to the Enable bit in the Comparator x Control registers (COMPCTRLx.ENABLE). The AC is disabled by writing a zero to CTRLA.ENABLE. This will also disable the individual comparators, but will not clear their COMPCTRLx.ENABLE bits. The AC is reset by writing a one to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in the AC, except DEBUG, will be reset to their initial state, and the AC will be disabled. Refer to the CTRLA register for details. 31.6.2.3 Starting a Comparison Each comparator channel can be in one of two different measurement modes, determined by the Single bit in the Comparator x Control register (COMPCTRLx.SINGLE): z Continuous measurement z Single-shot After being enabled, a start-up delay is required before the result of the comparison is ready. This start-up time is measured automatically to account for environmental changes, such as temperature or voltage supply level, and is specified in "Electrical Characteristics" on page 1055. During the start-up time, the COMP output is not available. If the supply voltage is below 2.5V, the start-up time is also dependent on the voltage doubler. If the supply voltage is guaranteed to be above 2.5V, the voltage doubler can be disabled by writing the Low-Power Mux bit in the Control A register (CTRLA.LPMUX) to one. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 845 The comparator can be configured to generate interrupts when the output toggles, when the output changes from zero to one (rising edge), when the output changes from one to zero (falling edge) or at the end of the comparison. An end-ofcomparison interrupt can be used with the single-shot mode to chain further events in the system, regardless of the state of the comparator outputs. The interrupt mode is set by the Interrupt Selection bit group in the Comparator Control register (COMPCTRLx.INTSEL). Events are generated using the comparator output state, regardless of whether the interrupt is enabled or not. Continuous Measurement Continuous measurement is selected by writing COMPCTRLx.SINGLE to zero. In continuous mode, the comparator is continuously enabled and performing comparisons. This ensures that the result of the latest comparison is always available in the Current State bit in the Status A register (STATUSA.STATEx). After the start-up time has passed, a comparison is done and STATUSA is updated. The Comparator x Ready bit in the Status B register (STATUSB.READYx) is set, and the appropriate peripheral events and interrupts are also generated. New comparisons are performed continuously until the COMPCTRLx.ENABLE bit is written to zero. The start-up time applies only to the first comparison. In continuous operation, edge detection of the comparator output for interrupts is done by comparing the current and previous sample. The sampling rate is the GCLK_AC_DIG frequency. An example of continuous measurement is shown in Figure 31-2. Figure 31-2. Continuous Measurement Example GCLK_AC Write `1' COMPCTRLx.ENABLE STATUSB.READYx 2-3 cycles tSTARTUP Sampled Comparator Output For low-power operation, comparisons can be performed during sleep modes without a clock. The comparator is enabled continuously, and changes in the state of the comparator are detected asynchronously. When a toggle occurs, the Power Manager will start GCLK_AC_DIG to register the appropriate peripheral events and interrupts. The GCLK_AC_DIG clock is then disabled again automatically, unless configured to wake up the system from sleep. Single-Shot Single-shot operation is selected by writing COMPCTRLx.SINGLE to one. During single-shot operation, the comparator is normally idle. The user starts a single comparison by writing a one to the respective Start Comparison bit in the writeonly Control B register (CTRLB.STARTx). The comparator is enabled, and after the start-up time has passed, a single comparison is done and STATUSA is updated. Appropriate peripheral events and interrupts are also generated. No new comparisons will be performed. Writing a one to CTRLB.STARTx also clears the Comparator x Ready bit in the Status B register (STATUSB.READYx). STATUSB.READYx is set automatically by hardware when the single comparison has completed. To remove the need for polling, an additional means of starting the comparison is also available. A read of the Status C register (STATUSC) will start a comparison on all comparators currently configured for single-shot operation. The read will stall the bus until all enabled comparators are ready. If a comparator is already busy with a comparison, the read will stall until the current comparison is compete, and a new comparison will not be started. A single-shot measurement can also be triggered by the Event System. Writing a one to the Comparator x Event Input bit in the Event Control Register (EVCTRL.COMPEIx) enables triggering on incoming peripheral events. Each comparator can be triggered independently by separate events. Event-triggered operation is similar to user-triggered operation; the difference is that a peripheral event from another hardware module causes the hardware to automatically start the comparison and clear STATUSB.READYx. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 846 To detect an edge of the comparator output in single-shot operation for the purpose of interrupts, the result of the current measurement is compared with the result of the previous measurement (one sampling period earlier). An example of single-shot operation is shown in Figure 31-3. Figure 31-3. Single-Shot Example GCLK_AC Write `1' CTRLB.STARTx Write `1' 2-3 cycles STATUSB.READYx 2-3 cycles tSTARTUP tSTARTUP Sampled Comparator Output For low-power operation, event-triggered measurements can be performed during sleep modes. When the event occurs, the Power Manager will start GCLK_AC_DIG. The comparator is enabled, and after the startup time has passed, a comparison is done and appropriate peripheral events and interrupts are also generated. The comparator and GCLK_AC_DIG are then disabled again automatically, unless configured to wake up the system from sleep. 31.6.3 Selecting Comparator Inputs Each comparator has one positive and one negative input. The positive input is fed from an external input pin (AINx). The negative input can be fed either from an external input pin (AINx) or from one of the several internal reference voltage sources common to all comparators. The user selects the input source as follows: z The positive input is selected by the Positive Input MUX Select bit group in the Comparator Control register (COMPCTRLx.MUXPOS) z The negative input is selected by the Negative Input MUX Select bit group in the Comparator Control register (COMPCTRLx.MUXNEG) In the case of using an external I/O pin, the selected pin must be configured for analog usage in the PORT Controller by disabling the digital input and output. The switching of the analog input multiplexors is controlled to minimize crosstalk between the channels. The input selection must be changed only while the individual comparator is disabled. 31.6.4 Window Operation Each comparator pair can be configured to work together in window mode. In this mode, a voltage range is defined, and the comparators give information about whether an input signal is within this range or not. Window mode is enabled by the Window Enable x bit in the Window Control register (WINCTRL.WENx). Both comparators in a pair must have the same measurement mode setting in their respective Comparator Control Registers (COMPCTRLx.SINGLE). To physically configure the pair of comparators for window mode, the same I/O pin should be chosen for each comparator's positive input to create the shared input signal. The negative inputs define the range for the window. In Figure 31-4, COMP0 defines the upper limit and COMP1 defines the lower limit of the window, as shown but the window will also work in the opposite configuration with COMP0 lower and COMP1 higher. The current state of the window function is available in the Window x State bit group of the Status register (STATUS.WSTATEx). Window mode can be configured to generate interrupts when the input voltage changes to below the window, when the input voltage changes to above the window, when the input voltage changes into the window or when the input voltage changes outside the window. The interrupt selections are set by the Window Interrupt Selection bit group in the Window Control register (WINCTRL.WINTSELx[1:0]). Events are generated using the inside/outside state of the window, regardless of whether the interrupt is enabled or not. Note that the individual comparator outputs, interrupts and events continue to function normally during window mode. When the comparators are configured for window mode and single-shot mode, measurements are performed simultaneously on both comparators. Writing a one to either Start Comparison bit in the Control B register (CTRLB.STARTx) starts a measurement. Likewise either peripheral event can start a measurement. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 847 Figure 31-4. Comparators in Window Mode + STATE0 COMP0 UPPER LIMIT OF WINDOW - WSTATE[1:0] INTERRUPT SENSITIVITY CONTROL & WINDOW FUNCTION INPUT SIGNAL INTERRUPTS EVENTS + STATE1 COMP1 LOWER LIMIT OF WINDOW - 31.6.5 Voltage Doubler The AC contains a voltage doubler that can reduce the resistance of the analog multiplexors when the supply voltage is below 2.5V. The voltage doubler is normally switched on/off automatically based on the supply level. When enabling the comparators, additional start-up time is required for the voltage doubler to settle. If the supply voltage is guaranteed to be above 2.5V, the voltage doubler can be disabled by writing the Low-Power Mux bit in the Control A register (CTRLA.LPMUX) to one. Disabling the voltage doubler saves power and reduces the start-up time. 31.6.6 VDDANA Scaler The VDDANA scaler generates a reference voltage that is a fraction of the device's supply voltage, with 64 levels. One independent voltage channel is dedicated for each comparator. The scaler is enabled when a comparator's Negative Input Mux bit group in its Comparator Control register (COMPCTRLx.MUXNEG) is set to five and the comparator is enabled. The voltage of each channel is selected by the Value bit group in the Scaler x registers (SCALERx.VALUE[5:0]). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 848 Figure 31-5. VDDANA Scaler COMPCTRLx.MUXNEG == 5 SCALERx. VALUE 6 to COMPx 31.6.7 Input Hysteresis Application software can selectively enable/disable hysteresis for the comparison. Applying hysteresis will help prevent constant toggling of the output, which can be caused by noise when the input signals are close to each other. Hysteresis is enabled for each comparator individually by the Hysteresis Mode bit in the Comparator x Control register (COMPCTRLx.HYST). Hysteresis is available only in continuous mode (COMPCTRLx.SINGLE=0). 31.6.8 Propagation Delay vs. Power Consumption It is possible to trade off comparison speed for power efficiency to get the shortest possible propagation delay or the lowest power consumption. The speed setting is configured for each comparator individually by the Speed bit group in the Comparator x Control register (COMPCTRLx.SPEED). The Speed bits select the amount of bias current provided to the comparator, and as such will also affect the start-up time. 31.6.9 Filtering The output of the comparators can be digitally filtered to reduce noise using a simple digital filter. The filtering is determined by the Filter Length bits in the Comparator Control x register (COMPCTRLx.FLEN), and is independent for each comparator. Filtering is selectable from none, 3-bit majority (N=3) or 5-bit majority (N=5) functions. Any change in the comparator output is considered valid only if N/2+1 out of the last N samples agree. The filter sampling rate is the CLK_AC frequency scaled by the prescaler setting in the Control A register (CTRLA.PRESCALER). Note that filtering creates an additional delay of N-1 sampling cycles from when a comparison is started until the comparator output is validated. For continuous mode, the first valid output will occur when the required number of filter samples is taken. Subsequent outputs will be generated every cycle based on the current sample plus the previous N-1 samples, as shown in Figure 31-6. For single-shot mode, the comparison completes after the Nth filter sample, as shown in Figure 31-7. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 849 Figure 31-6. Continuous Mode Filtering Sampling Clock Sampled Comparator Output 3-bit Majority Filter Output 5-bit Majority Filter Output Figure 31-7. Single-Shot Filtering Sampling Clock Start t SUT 3-bit Sampled Comparator Output 3-bit Majority Filter Output 5-bit Sampled Comparator Output 5-bit Majority Filter Output During sleep modes, filtering is supported only for single-shot measurements. Filtering must be disabled if continuous measurements will be done during sleep modes, or the resulting interrupt/event may be generated incorrectly. 31.6.10 Comparator Output The output of each comparator can be routed to an I/O pin by setting the Output bit group in the Comparator Control x register (COMPCTRLx.OUT). This allows the comparator to be used by external circuitry. Either the raw, nonsynchronized output of the comparator or the CLK_AC-synchronized version, including filtering, can be used as the I/O signal source. The output appears on the corresponding CMP[x] pin. 31.6.11 Offset Compensation The Swap bit in the Comparator Control registers (COMPCTRLx.SWAP) controls switching of the input signals to a comparator's positive and negative terminals. When the comparator terminals are swapped, the output signal from the comparator is also inverted, as shown in Figure 31-8. This allows the user to measure or compensate for the comparator input offset voltage. As part of the input selection, COMPCTRLx.SWAP can be changed only while the comparator is disabled. Figure 31-8. Input Swapping for Offset Compensation + MUXPOS COMPx - CMPx HYSTERESIS ENABLE SWAP MUXNEG COMPCTRLx SWAP Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 850 31.7 Additional Features 31.7.1 DMA Operation Not applicable. 31.7.2 Interrupts The peripheral has the following interrupt sources: z Comparator (COMPx): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. z Window (WINx): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. Comparator interrupts are generated based on the conditions selected by the Interrupt Selection bit group in the Comparator Control registers (COMPCTRLx.INTSEL). Window interrupts are generated based on the conditions selected by the Window Interrupt Selection bit group in the Window Control register (WINCTRL.WINTSEL[1:0]). Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the peripheral is reset. An interrupt flag is cleared by writing a one to the corresponding bit in the INTFLAG register. Each peripheral can have one interrupt request line per interrupt source or one common interrupt request line for all the interrupt sources. If the peripheral has one common interrupt request line for all the interrupt sources, the user must read the INTFLAG register to determine which interrupt condition is present. For details on clearing interrupt flags, refer to the INTFLAG register description. Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to "Nested Vector Interrupt Controller" on page 29 for details. 31.7.3 Events The peripheral can generate the following output events: z Comparator: COMPEO0, COMPEO1(EVCTRL) z Window: WINEO0(EVCTRL) Output events must be enabled to be generated. Writing a one to an Event Output bit in the Event Control register (EVCTRL.COMPEOx) enables the corresponding output event. Writing a zero to this bit disables the corresponding output event. The events must be correctly routed in the Event System. Refer to "EVSYS - Event System" on page 400 for details. The peripheral can take the following actions on an input event: z Single-shot measurement z Single-shot measurement in window mode Input events must be enabled for the corresponding action to be taken on any input event. Writing a one to an Event Input bit in the Event Control register (EVCTRL.COMPEIx) enables the corresponding action on input event. Writing a zero to a bit disables the corresponding action on input event. Note that if several events are connected to the peripheral, the enabled action will be taken on any of the incoming events. The events must be correctly routed in the Event System. Refer to "EVSYS - Event System" on page 400 for details. When EVCTRL.COMPEIx is one, the event will start a comparison on COMPx after the start-up time delay. In normal mode, each comparator responds to its corresponding input event independently. For a pair of comparators in window mode, either comparator event will trigger a comparison on both comparators simultaneously. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 851 31.7.4 Sleep Mode Operation The Run in Standby bit in the Control A register (CTRLA.RUNSTDBY) controls the behavior of the AC during standby sleep mode. When the bit is zero, the comparator pair is disabled during sleep, but maintains its current configuration. When the bit is one, the comparator pair continues to operate during sleep. Note that when RUNSTDBY is zero, the analog blocks are powered off for the lowest power consumption. This necessitates a start-up time delay when the system returns from sleep. When RUNSTDBY is one, any enabled AC interrupt source can wake up the CPU. While the CPU is sleeping, singleshot comparisons are only triggerable by events. The AC can also be used during sleep modes where the clock used by the AC is disabled, provided that the AC is still powered (not in shutdown). In this case, the behavior is slightly different and depends on the measurement mode, as listed in Table 31-1. Table 31-1. Sleep Mode Operation COMPCTRLx.MODE RUNSTDBY=0 RUNSTDBY=1 0 (Continuous) COMPx disabled GCLK_AC_DIG stopped, COMPx enabled 1 (Single-shot) COMPx disabled GCLK_AC_DIG stopped, COMPx enabled only when triggered by an input event 31.7.4.1 Continuous Measurement during Sleep When a comparator is enabled in continuous measurement mode and GCLK_AC_DIG is disabled during sleep, the comparator will remain continuously enabled and will function asynchronously. The current state of the comparator is asynchronously monitored for changes. If an edge matching the interrupt condition is found, GCLK_AC_DIG is started to register the interrupt condition and generate events. If the interrupt is enabled in the Interrupt Enable registers (INTENCLR/SET), the AC can wake up the device; otherwise GCLK_AC_DIG is disabled until the next edge detection. Filtering is not possible with this configuration. Figure 31-9. Continuous Mode SleepWalking GCLK_AC Comparator State Comparator Output or Event 31.7.4.2 Single-Shot Measurement during Sleep For low-power operation, event-triggered measurements can be performed during sleep modes. When the event occurs, the Power Manager will start GCLK_AC_DIG. The comparator is enabled, and after the start-up time has passed, a comparison is done, with filtering if desired, and the appropriate peripheral events and interrupts are also generated, as shown in Figure 31-10 The comparator and GCLK_AC_DIG are then disabled again automatically, unless configured to wake the system from sleep. Filtering is allowed with this configuration. Figure 31-10.Single-Shot SleepWalking GCLK_AC tSTARTUP t STARTUP Input Event Comparator Output or Event Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 852 31.7.5 Synchronization Due to the asynchronicity between CLK_MODULE_APB and GCLK_MODULE, some registers must be synchronized when accessed. A register can require: z Synchronization when written z Synchronization when read z Synchronization when written and read z No synchronization When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is stalled. The following bits need synchronization when written: z Software Reset bit in Control A register (CTRLA.SWRST) z Enable bit in Control A register (CTRLA.ENABLE) z Enable bit in Comparator Control register (COMPCTRLn.ENABLE) The following register need synchronization when written: z Window Control register (WINCTRL) Refer to the Synchronization chapter for further details. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 853 31.8 Register Summary Table 31-2. Register Summary Offset Name Bit Pos. 0x00 CTRLA 7:0 0x01 CTRLB 7:0 0x02 0x03 EVCTRL LPMUX RUNSTDBY 7:0 WINEO0 15:8 ENABLE SWRST START1 START0 COMPEO1 COMPEO0 COMPEI1 COMPEI0 0x04 INTENCLR 7:0 WIN0 COMP1 COMP0 0x05 INTENSET 7:0 WIN0 COMP1 COMP0 0x06 INTFLAG 7:0 WIN0 COMP1 COMP0 0x07 Reserved 0x08 STATUSA 7:0 0x09 STATUSB 7:0 0x0A STATUSC 7:0 0x0B Reserved 0x0C WINCTRL 0x0D ... 0x0F Reserved 0x10 0x11 0x12 COMPCTRL0 15:8 7:0 COMPCTRL1 0x17 INTSEL[1:0] SWAP SPEED[1:0] MUXPOS[1:0] 23:16 0x14 15:8 23:16 STATE1 STATE0 READY1 READY0 STATE1 STATE0 WINTSEL0[1:0] 7:0 31:24 0x16 WSTATE0[1:0] 7:0 0x13 0x15 WSTATE0[1:0] SYNCBUSY WEN0 SINGLE ENABLE MUXNEG[2:0] HYST OUT[1:0] FLEN[2:0] INTSEL[1:0] SWAP SPEED[1:0] MUXPOS[1:0] SINGLE ENABLE MUXNEG[2:0] HYST OUT[1:0] 31:24 FLEN[2:0] 0x18 ... 0x1F Reserved 0x20 SCALER0 7:0 VALUE[5:0] 0x21 SCALER1 7:0 VALUE[5:0] Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 854 31.9 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protected property in each individual register description. Refer to "Register Access Protection" on page 844 for details. Some registers require synchronization when read and/or written. Synchronization is denoted by the Write-Synchronized or the Read-Synchronized property in each individual register description. Refer to "Synchronization" on page 853 for details. Some registers are enable-protected, meaning they can be written only when the AC is disabled. Enable-protection is denoted by the Enable-Protected property in each individual register description. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 855 31.9.1 Control A Name: CTRLA Offset: 0x00 Reset: 0x00 Property: Write-Protected, Write-Synchronized Bit 7 6 5 4 3 LPMUX Access Reset z 2 1 0 RUNSTDBY ENABLE SWRST R/W R R R R R/W R/W W 0 0 0 0 0 0 0 0 Bit 7 - LPMUX: Low-Power Mux 0: The analog input muxes have low resistance, but consume more power at lower voltages (e.g., are driven by the voltage doubler). 1: The analog input muxes have high resistance, but consume less power at lower voltages (e.g., the voltage doubler is disabled). This bit is not synchronized z Bits 6:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 2 - RUNSTDBY: Run in Standby This bit controls the behavior of the comparators during standby sleep mode. 0: The comparator pair is disabled during sleep. 1: The comparator pair continues to operate during sleep. This bit is not synchronized z Bit 1 - ENABLE: Enable 0: The AC is disabled. 1: The AC is enabled. Each comparator must also be enabled individually by the Enable bit in the Comparator Control register (COMPCTRLn.ENABLE). Due to synchronization, there is delay from updating the register until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately after being written. STATUS.SYNCBUSY is set. STATUS.SYNCBUSY is cleared when the peripheral is enabled/disabled. z Bit 0 - SWRST: Software Reset 0: There is no reset operation ongoing. 1: The reset operation is ongoing. Writing a zero to this bit has no effect. Writing a one to this bit resets all registers in the AC to their initial state, and the AC will be disabled. Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 856 31.9.2 Control B Name: CTRLB Offset: 0x01 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 START1 START0 Access R R R R R R W W Reset 0 0 0 0 0 0 0 0 z Bits 7:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 1:0 - STARTx [x=1..0]: Comparator x Start Comparison Writing a zero to this field has no effect. Writing a one to STARTx starts a single-shot comparison on COMPx if both the Single-Shot and Enable bits in the Comparator x Control Register are one (COMPCTRLx.SINGLE and COMPCTRLx.ENABLE). If comparator x is not implemented, or if it is not enabled in single-shot mode, writing a one has no effect. This bit always reads as zero. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 857 31.9.3 Event Control Name: EVCTRL Offset: 0x02 Reset: 0x0000 Property: Write-Protected Bit 15 14 13 12 11 10 9 8 COMPEI1 COMPEI0 Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COMPEO1 COMPEO0 WINEO0 Access R R R R/W R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 15:10 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 9:8 - COMPEIx [x=1..0]: Comparator x Event Input Note that several actions can be enabled for incoming events. If several events are connected to the peripheral, the enabled action will be taken for any of the incoming events. There is no way to tell which of the incoming events caused the action. These bits indicate whether a comparison will start or not on any incoming event. 0: Comparison will not start on any incoming event. 1: Comparison will start on any incoming event. z Bits 7:5 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 4 - WINEO: Window x Event Output Enable These bits indicate whether the window x function can generate a peripheral event or not. 0: Window x Event is disabled. 1: Window x Event is enabled. z Bits 3:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 1:0 - COMPEOx [x=1..0]: Comparator x Event Output Enable These bits indicate whether the comparator x output can generate a peripheral event or not. 0: COMPx event generation is disabled. 1: COMPx event generation is enabled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 858 31.9.4 Interrupt Enable Clear This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Name: INTENCLR Offset: 0x04 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 WIN0 1 0 COMP1 COMP0 Access R R R R/W R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:5 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 4 - WIN: Window x Interrupt Enable Reading this bit returns the state of the Window x interrupt enable. 0: The Window x interrupt is disabled. 1: The Window x interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit disables the Window x interrupt. z Bits 3:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 1:0 - COMPx [x=1..0]: Comparator x Interrupt Enable Reading this bit returns the state of the Comparator x interrupt enable. 0: The Comparator x interrupt is disabled. 1: The Comparator x interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit disables the Comparator x interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 859 31.9.5 Interrupt Enable Set This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Name: INTENSET Offset: 0x05 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 WIN0 1 0 COMP1 COMP0 Access R R R R/W R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:5 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 4 - WIN: Window x Interrupt Enable Reading this bit returns the state of the Window x interrupt enable. 0: The Window x interrupt is disabled. 1: The Window x interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit enables the Window x interrupt. z Bits 3:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 1:0 - COMPx [x=1..0]: Comparator x Interrupt Enable Reading this bit returns the state of the Comparator x interrupt enable. 0: The Comparator x interrupt is disabled. 1: The Comparator x interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Ready interrupt bit and enable the Ready interrupt. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 860 31.9.6 Interrupt Flag Status and Clear Name: INTFLAG Offset: 0x06 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 WIN0 1 0 COMP1 COMP0 Access R R R R/W R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:5 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 4 - WIN: Window x This flag is set according to the Window x Interrupt Selection bit group in the WINCTRL register (WINCTRL.WINTSELx) and will generate an interrupt if INTENCLR/SET.WINx is also one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Window x interrupt flag. z Bits 3:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 1:0 - COMPx [x=1..0]: Comparator x Reading this bit returns the status of the Comparator x interrupt flag. If comparator x is not implemented, COMPx always reads as zero. This flag is set according to the Interrupt Selection bit group in the Comparator x Control register (COMPCTRLx.INTSEL) and will generate an interrupt if INTENCLR/SET.COMPx is also one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Comparator x interrupt flag. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 861 31.9.7 Status A Name: STATUSA Offset: 0x08 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 WSTATE0[1:0] 1 0 STATE1 STATE0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 7:6 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 5:4 - WSTATE0[1:0]: Window 0 Current State These bits show the current state of the signal if the window 0 mode is enabled, according to Table 31-3. If the window 0 function is not implemented, WSTATE0 always reads as zero. Table 31-3. Window 0 Current State WSTATE0[1:0] Name 0x0 ABOVE Signal is above window 0x1 INSIDE Signal is inside window 0x2 BELOW Signal is below window 0x3 Description Reserved z Bits 3:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 1:0 - STATEx [x=1..0]: Comparator x Current State This bit shows the current state of the output signal from COMPx. STATEx is valid only when STATUSB.READYx is one. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 862 31.9.8 Status B Name: STATUSB Offset: 0x09 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 SYNCBUSY 1 0 READY1 READY0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bit 7 - SYNCBUSY: Synchronization Busy This bit is cleared when the synchronization of registers between the clock domains is complete. This bit is set when the synchronization of registers between clock domains is started. z Bits 6:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 1:0 - READYx [x=1..0]: Comparator x Ready This bit is cleared when the comparator x output is not ready. This bit is set when the comparator x output is ready. If comparator x is not implemented, READYx always reads as zero. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 863 31.9.9 Status C STATUSC is a copy of STATUSA (see STATUSA register), with the additional feature of automatically starting singleshot comparisons. A read of STATUSC will start a comparison on all comparators currently configured for single-shot operation. The read will stall the bus until all enabled comparators are ready. If a comparator is already busy with a comparison, the read will stall until the current comparison is compete, and a new comparison will not be started. Name: STATUSC Offset: 0x0A Reset: 0x00 Property: - Bit 7 6 5 4 3 2 WSTATE0[1:0] 1 0 STATE1 STATE0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 7:6 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 5:4 - WSTATE0[1:0]: Window 0 Current State These bits show the current state of the signal if the window 0 mode is enabled. If the window 0 function is not implemented, WSTATE0 always reads as zero. Table 31-4. Window 0 Current State WSTATE0[1:0] Name 0x0 ABOVE Signal is above window 0x1 INSIDE Signal is inside window 0x2 BELOW Signal is below window 0x3 Description Reserved z Bits 3:2 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 1:0 - STATEx [x=1..0]: Comparator x Current State This bit shows the current state of the output signal from COMPx. If comparator x is not implemented, STATEx always reads as zero. STATEx is only valid when STATUSB.READYx is one. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 864 31.9.10 Window Control Name: WINCTRL Offset: 0x0C Reset: 0x00 Property: Write-Protected, Write-Synchronized Bit 7 6 5 4 3 2 1 WINTSEL0[1:0] 0 WEN0 Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:3 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 2:1 - WINTSEL0[1:0]: Window 0 Interrupt Selection These bits configure the interrupt mode for the comparator window 0 mode. Table 31-5. Window 0 Interrupt Selection z WINTSEL0[1:0] Name Description 0x0 ABOVE Interrupt on signal above window 0x1 INSIDE Interrupt on signal inside window 0x2 BELOW Interrupt on signal below window 0x3 OUTSIDE Interrupt on signal outside window Bit 0 - WEN0: Window 0 Mode Enable 0: Window mode is disabled for comparators 0 and 1. 1: Window mode is enabled for comparators 0 and 1. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 865 31.9.11 Comparator Control n The configuration of comparator n is protected while comparator n is enabled (COMPCTRLn.ENABLE=1). Changes to the other bits in COMPCTRLn can only occur when COMPCTRLn.ENABLE is zero. Name: COMPCTRLn Offset: 0x10+n*0x4 [n=0..1] Reset: 0x00000000 Property: Write-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 FLEN[2:0] Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 HYST OUT[1:0] Access R R R R R/W R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 SWAP Access MUXPOS[1:0] MUXNEG[2:0] R/W R R/W R/W R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SINGLE ENABLE INTSEL[1:0] SPEED[1:0] Access R R/W R/W R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 31:27 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 26:24 - FLEN[2:0]: Filter Length These bits configure the filtering for comparator n. COMPCTRLn.FLEN can only be written while COMPCTRLn.ENABLE is zero. These bits are not synchronized. Table 31-6. Filter Length FLEN[2:0] Name 0x0 OFF Description No filtering Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 866 FLEN[2:0] Name 0x1 MAJ3 3-bit majority function (2 of 3) 0x2 MAJ5 5-bit majority function (3 of 5) 0x3-0x7 Description Reserved z Bits 23:20 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 19 - HYST: Hysteresis Enable This bit indicates the hysteresis mode of comparator n. Hysteresis is available only for continuous mode (COMPCTRLn.SINGLE=0). COMPCTRLn.HYST can be written only while COMPCTRLn.ENABLE is zero. 0: Hysteresis is disabled. 1: Hysteresis is enabled. This bit is not synchronized z Bit 18 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 17:16 - OUT[1:0]: Output These bits configure the output selection for comparator n. COMPCTRLn.OUT can be written only while COMPCTRLn.ENABLE is zero. These bits are not synchronized. Table 31-7. Output OUT[1:0] Name 0x0 OFF 0x1 ASYNC 0x2 SYNC 0x3 z Description The output of COMPn is not routed to the COMPn I/O port The asynchronous output of COMPn is routed to the COMPn I/O port The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port Reserved Bit 15 - SWAP: Swap Inputs and Invert This bit swaps the positive and negative inputs to COMPn and inverts the output. This function can be used for offset cancellation. COMPCTRLn.SWAP can be written only while COMPCTRLn.ENABLE is zero. 0: The output of MUXPOS connects to the positive input, and the output of MUXNEG connects to the negative input. 1: The output of MUXNEG connects to the positive input, and the output of MUXPOS connects to the negative input. This bit is not synchronized z Bit 14 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 867 z Bits 13:12 - MUXPOS[1:0]: Positive Input Mux Selection These bits select which input will be connected to the positive input of comparator n. COMPCTRLn.MUXPOS can be written only while COMPCTRLn.ENABLE is zero. These bits are not synchronized. Table 31-8. Positive Input Mux Selection MUXPOS[1:0] Name Description 0x0 PIN0 I/O pin 0 0x1 PIN1 I/O pin 1 0x2 PIN2 I/O pin 2 0x3 PIN3 I/O pin 3 z Bit 11 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 10:8 - MUXNEG[2:0]: Negative Input Mux Selection These bits select which input will be connected to the negative input of comparator n. COMPCTRLn.MUXNEG can only be written while COMPCTRLn.ENABLE is zero. These bits are not synchronized. Table 31-9. Negative Input Mux Selection Value Name Description 0x0 PIN0 I/O pin 0 0x1 PIN1 I/O pin 1 0x2 PIN2 I/O pin 2 0x3 PIN3 I/O pin 3 0x4 GND Ground 0x5 VSCALE VDDANA scaler 0x6 BANDGAP Internal bandgap voltage 0x7 Reserved z Bit 7 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 6:5 - INTSEL[1:0]: Interrupt Selection These bits select the condition for comparator n to generate an interrupt or event. COMPCTRLn.INTSEL can be written only while COMPCTRLn.ENABLE is zero. These bits are not synchronized. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 868 Table 31-10. Interrupt Selection INTSEL[1:0] Name Description 0x0 TOGGLE Interrupt on comparator output toggle 0x1 RISING Interrupt on comparator output rising 0x2 FALLING Interrupt on comparator output falling 0x3 EOC Interrupt on end of comparison (single-shot mode only) z Bit 4 - Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 3:2 - SPEED[1:0]: Speed Selection This bit indicates the speed/propagation delay mode of comparator n. COMPCTRLn.SPEED can be written only while COMPCTRLn.ENABLE is zero. These bits are not synchronized. Table 31-11. Speed Selection SPEED[1:0] Name 0x0 LOW Low speed 0x1 HIGH High speed 0x2-0x3 z Description Reserved Bit 1 - SINGLE: Single-Shot Mode This bit determines the operation of comparator n. COMPCTRLn.SINGLE can be written only while COMPCTRLn.ENABLE is zero. 0: Comparator n operates in continuous measurement mode. 1: Comparator n operates in single-shot mode. This bit is not synchronized z Bit 0 - ENABLE: Enable Writing a zero to this bit disables comparator n. Writing a one to this bit enables comparator n. After writing to this bit, the value read back will not change until the action initiated by the writing is complete. Due to synchronization, there is a latency of at least two GCLK_AC_DIG clock cycles from updating the register until the comparator is enabled/disabled. The bit will continue to read the previous state while the change is in progress. Writing a one to COMPCTRLn.ENABLE will prevent further changes to the other bits in COMPCTRLn. These bits remain protected until COMPCTRLn.ENABLE is written to zero and the write is synchronized. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 869 31.9.12 Scaler n Name: SCALERn Offset: 0x20+n*0x1 [n=0..1] Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 VALUE[5:0] Access R R R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:6 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 5:0 - VALUE[5:0]: Scaler Value These bits define the scaling factor for channel n of the VDD voltage scaler. The output voltage, VSCALE, is: V DD ( VALUE + 1 ) V SCALE = -------------------------------------------------64 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 870 32. PTC - Peripheral Touch Controller 32.1 Overview The purpose of PTC is to acquire signals to detect touch on capacitive sensors. The external capacitive touch sensor is typically formed on a PCB, and the sensor electrodes are connected to the analog front end of the PTC through the I/O pins in the device. The PTC supports both self- and mutual-capacitance sensors. In mutual-capacitance mode, sensing is done using capacitive touch matrices in various X-Y configurations, including indium tin oxide (ITO) sensor grids. The PTC requires one pin per X-line and one pin per Y-line. In self-capacitance mode, the PTC requires only one pin (Y-line) for each touch sensor. 32.2 Features z Low-power, high-sensitivity, environmentally robust capacitive touch buttons, sliders, wheels and proximity sensing z Supports mutual capacitance and self-capacitance sensing 2/6 buttons in self-capacitance mode, for 32-/48- pins respectively 12/48 buttons in mutual-capacitance mode, for 32-/48- pins respectively z Mix-and-match mutual-and self-capacitance sensors z z z One pin per electrode - no external components z Load compensating charge sensing z Parasitic capacitance compensation and adjustable gain for superior sensitivity z Zero drift over the temperature and VDD range z Auto calibration and re-calibration of sensors z Single-shot and free-running charge measurement z Hardware noise filtering and noise signal de-synchronization for high conducted immunity z Selectable channel change delay z Allows choosing the settling time on a new channel, as required z Acquisition-start triggered by command or interrupt event z Low CPU utilization through interrupt on acquisition-complete z 5% CPU utilization scanning 10 channels at 50ms scan rate z Supported by the Atmel(R) QTouch(R) Composer development tool, which comprises QTouch Library project builder and QTouch analyzer Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 871 32.3 Block Diagram Figure 32-1. PTC Block Diagram Mutual-capacitance Input Control Compensation Circuit Y0 Y1 Y15 RS Acquisition Module 100K IRQ - Gain control - ADC - Filtering Result 10 X0 X Line Driver X1 X15 Figure 32-2. PTC Block Diagram Self-capacitance Input Control Compensation Circuit Y0 Y1 RS CY0 Y15 100K Acquisition Module IRQ - Gain control - ADC - Filtering Result 10 CY15 X Line Driver Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 872 32.4 Signal Description Name Type Description X[n:0] Digital X-line (Output) Y[m:0] Analog Y-line (Input/Output) Note: 1. The number of X and Y lines are device dependent. Refer to "Configuration Summary" on page 4 for details. Refer to "I/O Multiplexing and Considerations" on page 12 for details on the pin mapping for this peripheral. One signal can be mapped on several pins. 32.5 Product Dependencies In order to use this Peripheral, configure the other components of the system as described in the following sections. 32.5.1 I/O Lines The I/O lines used for analog X-lines and Y-lines must be connected to external capacitive touch sensor electrodes. External components are not required for normal operation. However, to improve the EMC performance, a series resistor of 1 K can be used on X-lines and Y-lines. Mutual-capacitance Sensor Arrangement A mutual-capacitance sensor is formed between two I/O lines - an X electrode for transmitting and Y electrode for receiving. The mutual capacitance between the X and Y electrode is measured by the Peripheral Touch Controller. Figure 32-3. Mutual Capacitance Sensor Arrangement Sensor Capacitance Cx,y MCU X0 X1 Xn Cx0,y0 Cx0,y1 Cx0,ym Cx1,y0 Cx1,y1 Cx1,ym Cxn,y0 Cxn,y1 Cxn,ym PTC PTC Module Module Y0 Y1 Ym Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 873 Self-capacitance Sensor Arrangement The self-capacitance sensor is connected to a single pin on the Peripheral Touch Controller through the Y electrode for receiving the signal. The sense electrode capacitance is measured by the Peripheral Touch Controller. Figure 32-4. Self-capacitance Sensor Arrangement MCU Sensor Capacitance Cy Y0 Cy0 Y1 PTC Module Ym Cy1 Cym For more information about designing the touch sensor, refer to Buttons, Sliders and Wheels Touch Sensor Design Guide on http://www.atmel.com. 32.5.2 Clocks The PTC is clocked by the GCLK_PTC clock. The PTC operates from an asynchronous clock source and the operation is independent of the main system clock and its derivative clocks, such as the peripheral bus clock (CLK_APB). A number of clock sources can be selected as the source for the asynchronous GCLK_PTC. The clock source is selected by configuring the Generic Clock Selection ID in the Generic Clock Control register. For more information about selecting the clock sources, refer to "GCLK - Generic Clock Controller" on page 90. The selected clock must be enabled in the Power Manager, before it can be used by the PTC. By default these clocks are disabled. The frequency range of GCLK_PTC is 400kHz to 4MHz. For more details, refer to "PM - Power Manager" on page 112. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 874 32.6 Functional Description In order to access the PTC, the user must use the QTouch Composer tool to configure and link the QTouch Library firmware with the application code. QTouch Library can be used to implement buttons, sliders, wheels and proximity sensor in a variety of combinations on a single interface. For more information about QTouch library, refer to the Atmel QTouch Library Peripheral Touch Controller User Guide. Figure 32-5. QTouch Library Usage Custom Code Compiler Link Application Atmel Qtouch Library Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 875 33. RFCTRL - AT86RF233 Front-End Control Signal Interface 33.1 Overview The RFCTRL module provides a register and multiplexer for selecting the front-end control signal outputs of the integrated transceiver as alternate pin functions for the SAMR21. 33.2 Features z Supports up to 6 front-end control output signals z Supports all front-end control input signals (DIG1, DIG2, DIG3 and DIG4) from the AT86RF233 33.3 Block Diagram Figure 33-1. RFCTRL Block Diagram DIG1 DIG2 FECTRL[0] DIG3 DIG4 . . . FECTRL[6] 33.4 Product Dependencies In order to use the module, the I/O port pins used for front-end control signals must be configured as alternate pin function outputs. The RFCTRL module is enabled by writing the RFCTRL APB Clock Enable bit (APBCMASK.RFCTRL) in the Power Manager to `1'. Refer to "Peripheral Clock Masking" on page 116 for details. 33.5 Functional Description The RFCTRL module is intended to flexible route the PA/LNA and antenna diversity front-end control signals as well as RX/TX frame time stamping to alternate pin functions of the Cortex-M0+ CPU without any further software action required after initialization of the alternate pin function output. The module provides six 2-bit registers which control the muxing of the DIG1, DIG2, DIG3 and DIG4 front-end control signal outputs of the integrated transceiver to alternate pin functions of the SAMR21 device. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 876 33.6 Offset Register Summary Name 0x00 Bit Position 7:0 F3CFG[1:0] F2CFG[1:0] F1CFG[1:0] F0CFG[1:0] F5CFG[1:0] F4CFG[1:0] FECTRL 0x01 15:8 0x02 Reserved 7:0 0x03 Reserved 7:0 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 877 33.7 Register Description 33.7.1 Front-end Control Register Name: FECTRL Offset: 0x00 Reset: 0x0000 Property: - Bit 15 14 13 12 11 12 9 F5CFG[1:0] 0x01 8 F4CFG[1:0] Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 F3CFG[1:0] 0x00 Access Reset F2CFG[1:0] F1CFG[1:0] F0CFG[1:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bit 15:12 - Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 11:10 - F5CFG[1:0]: Front-end Control Signal 5 Configuration These bits define the front-end output control signal 5, as shown in Table 33-1. z Bit 9:8 - F4CFG[1:0]: Front-end Control Signal 4 Configuration These bits define the front-end output control signal 4, as shown in Table 33-1. z Bit 7:6 - F3CFG[1:0]: Front-end Control Signal 3 Configuration These bits define the front-end output control signal 3, as shown in Table 33-1. z Bit 5:4 - F2CFG[1:0]: Front-end Control Signal 2 Configuration These bits define the front-end output control signal 2, as shown in Table 33-1. z Bit 3:2 - F1CFG[1:0]: Front-end Control Signal 1 Configuration These bits define the front-end output control signal 1, as shown in Table 33-1. z Bit 1:0 - F0CFG[1:0]: Front-end Control Signal 0 Configuration These bits define the front-end output control signal 0, as shown in Table 33-1. Table 33-1. Front-End Control Configuration FnCFG[1:0] Operating Mode 0x0 Route transceiver DIG1 signal output to FECTRL[n] alternate pin function 0x1 Route transceiver DIG2 signal output to FECTRL[n] alternate pin function 0x2 Route transceiver DIG3 signal output to FECTRL[n] alternate pin function 0x3 Route transceiver DIG4 signal output to FECTRL[n] alternate pin function Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 878 34. Application Schematic 34.1 Basic Application Schematic A basic application schematic of the SAM R21 with a single-ended RF connector is shown in Figure 34-1. The 50 single-ended RF input is transformed to the 100 differential RF port impedance using balun B1. The capacitors C1 and C2 provide AC coupling of the RF input to the RF port, optional capacitor C4 improves matching if required. Figure 34-1. Basic Application Schematic VDD CX1 CB2 10F CX2 XTAL XTAL2 XTAL1 GNDANA VDDANA AVDD GNDANA CB1 VDD SWDIO SWCLK C1 B1 GNDANA VDD VDDIN CB5 VDDCORE RFP Cortex Debug Connector 10 F CB6 C4 RFN SAM R21 GND GNDANA C2 VDD VDDIO DVDD RESET CB3 CB4 The power supply decoupling capacitors (CB2, CB4, CB5) are connected to the external analog supply VDDANA, the external digital supplies VDDIO and VDDIN. Capacitors CB1, CB3 and CB6 are bypass capacitors for the integrated analog and digital voltage regulators to ensure stable operation. All bypass capacitors should be placed as close as possible to the pins and should have a low-resistance and low-inductance connection to ground to achieve the best performance. The crystal (XTAL), the two load capacitors (CX1, CX2), and the internal circuitry connected to pins XTAL1 and XTAL2 form the crystal oscillator. To achieve the best accuracy and stability of the reference frequency, large parasitic capacitances should be avoided. Crystal lines should be routed as short as possible and not in proximity of digital I/O signals. This is especially required for the High Data Rate Modes; refer to "High Data Rate Modes" on page 1013. The ground plane of the application board should be separated into four independent fragments: the analog, the digital, the antenna, and the XTAL ground plane. The exposed paddle shall act as the reference point of the individual grounds. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 879 Table 34-1. Exemplary Bill of Materials (BoM) for Basic Application Schematic Symbol Description Value Manufacturer Part Number Commnt B1 SMD balun 2.45GHz Wuerth 748421245 2.45GHz Balun CB1 LDO VREG CB3 bypass capacitor 100nF Generic CB2 Power supply decoupling CB4 1F CX1, CX2 Crystal load capacitor 12pF C1, C2 RF coupling capacitor 22pF C4 (optional) XTAL AVX Murata AVX X7R (0402) 0603YD105KAT2A GRM188R61C105KA12 D 06035A120JA Murata GRM1555C1H120JA01 D Murata GRM1555C1H220JA01J Epcos B37920 AVX 06035A220JAT2A (0603) COG (0402) C0G 16V 10% 16V 5% 50V 5% (0402 or 0603) 50V Value depends on final PCB implementation RF matching Crystal X5R 10% CX-4025 16MHz SX-4025 16MHz ACAL Taitjen XWBBPL-F-1 Siward A207-011 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 880 34.2 Extended Feature Set Application Schematic The Atmel AT86RF233 supports additional features like: z Security Module (AES), "Security Module (AES)" on page 1005 z Random Number Generator, "Random Number Generator" on page 1013 z High Data Rate Modes, "High Data Rate Modes" on page 1013 z Antenna Diversity, "Antenna Diversity" on page 1020 z Uses internal DIG1(/2) signals available as alternate pin functions FECTRL[0..5] on pins PA08..15 z RX/TX Indicator, "RX/TX Indicator" on page 1025 z Rx and Tx Frame Time Stamping (TX_ARET), "RX and TX Frame Time Stamping (TX_ARET)" on page 1027 z z z Uses internal DIG3/4 signals available as alternate pin functions FECTRL[0..5] on pins PA08..15 Uses internal DIG2 signal available as alternate pin function FECTRL[0..5] on pins PA08..15 Frame Buffer Empty Indicator, "Frame Buffer Empty Indicator" on page 1030 z Uses internal IRQ signal connected to PB00 z Dynamic Frame Buffer Protection, "Dynamic Frame Buffer Protection" on page 1032 z Alternate Start-Of-Frame Delimiter, "Alternate Start-Of-Frame Delimiter" on page 1033 z Reduced Power Consumption Mode (RPC), "Reduced Power Consumption Mode (RPC)" on page 1034 z Time-Of-Flight Module (TOM) Measurements, "Time-Of-Flight Module (TOM)" on page 1039 z Phase Difference Measurement, "Phase Difference Measurement" on page 1050 An extended feature set application schematic illustrating the use of the AT86RF233 Extended Feature Set, see "AT86RF233 Extended Feature Set" on page 1005, is shown in Figure 34-2. Although this example shows all additional hardware features combined, it is possible to use all features separately or in various combinations. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 881 Figure 34-2. Extended Feature Application Schematic 10F VDD CB2 CX2 CX1 XTAL XTAL2 XTAL1 GNDANA VDDANA AVDD GNDANA CB1 VDD FECTRLi(DIG3) SWDIO FECTRLj(DIG4) SWCLK ANT0 VDDIN GNDANA Balun PA RFSwitch RFSwitch N2 LNA SW1 B1 N1 SW2 VDDCORE CB6 RFP SAM R21 VDD CB5 Cortex Debug Connector 10 F GND RFN GNDANA RESET FECTRLk(DIG1) VDD VDDIO DVDD ANT1 CB3 CB4 In this example, a balun (B1) transforms the differential RF signal at the SAM R21 radio transceiver RF pins (RFP/RFN) to a single ended RF signal, similar to the Basic Application Schematic; refer to Figure 34-1. During receive mode the radio transceiver searches for the most reliable RF signal path using the Antenna Diversity algorithm. One antenna is selected (SW2) by the Antenna Diversity RF switch control signal (DIG1), refer to "Antenna Diversity" on page 1020. The RX signal is amplified by an optional low-noise amplifier (N2) and fed to the radio transceiver using the RX/TX switch (SW1). During transmit mode the SAM R21 TX signal is amplified using an external PA (N1) and fed to the antennas via an RF switch (SW2). These switches are controlled by the RX/TX Indicator, represented by the differential pin pair DIG3/DIG4, refer to "RX/TX Indicator" on page 1025. The Security Module (AES), Random Number Generator, High Data Rate Modes, Frame Buffer Empty Indicator, Dynamic Frame Buffer Protection, Alternate Start-Of-Frame Delimiter or Reduced Power Consumption Mode (RPC) do not require specific circuitry to operate, for details refer to "Security Module (AES)" on page 1005, "Random Number Generator" on page 1013, "High Data Rate Modes" on page 1013, "Frame Buffer Empty Indicator" on page 1030, "Dynamic Frame Buffer Protection" on page 1032, "Alternate Start-Of-Frame Delimiter" on page 1033 and "Reduced Power Consumption Mode (RPC)" on page 1034. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 882 35. AT86RF233 Microcontroller Interface 35.1 Overview This section describes the AT86RF233 to microcontroller interface. The interface comprises a slave SPI and additional control signals, refer to Figure 35-1. The SPI timing and protocol are described below. Figure 35-1. Microcontroller to AT86RF233 Interface SAM R21 SAM D21 SERCOM 4 PAD1 PAD2 PAD0 PAD3 GCLK (3) GENERATOR 1 AT86RF233 PB31(F) PB30(F) (1) (1) PC19(F) (1) PC18(F) (1) PC16(F) PB00(A) (1) MOSI MISO SCLK CLKM IRQ PA20 SLP_TR PB15 /RST PB16 PB17 SPI-SLAVE (1) EXTINT0 PORTx /SEL (2) (2) DIG1 DIG2 CONTROL LOGIC ANTENNA DIVERSITY CONTROL RFCTRL PA10 PA11 (2) (2) DIG3 DIG4 External PA and POWER CONTROL Notes: 1. Alternate pin function and direction has to be configured by software. 2. Pin function is configured by hardware automatically after reset. 3. Die revision A uses GCLK GENERATOR 5. The SPI is used for register, Frame Buffer, SRAM and AES access. The additional control signals are connected to the GCLK, EIC, GPIO and RFCTRL interface of the microcontroller. Table 35-1 introduces the radio transceiver I/O signals and their functionality. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 883 Table 35-1. Signal Description of Microcontroller Interface Signal Description /SEL SPI select signal, active low MOSI SPI data (master output slave input) signal MISO SPI data (master input slave output) signal SCLK SPI clock signal CLKM Optional, Clock output, refer to "Master Clock Signal Output (CLKM)" on page 991, usable as: - microcontroller clock source and/or MAC timer reference - high precision timing reference IRQ SLP_TR Interrupt request signal, further used as: - Frame Buffer Empty indicator, refer to "Frame Buffer Empty Indicator" on page 1030 Multi purpose control signal (functionality is state dependent, see "Sleep/Wake-up and Transmit Signal (SLP_TR)" on page 894): - Sleep/Wakeup - enable/disable SLEEP state - Sleep/Wakeup - enable/disable DEEP_SLEEP state - TX start - BUSY_TX_(ARET) state /RST AT86RF233 reset signal, active low DIG2 Optional, - IRQ_2 (RX_START) for RX Frame Time Stamping, see "RX and TX Frame Time Stamping (TX_ARET)" on page 1027 - Signals frame transmit within TX_ARET mode for TX Time Stamping 35.2 SPI Timing Description The CLKM signal can be used as clock input source for the Generic Clock Generator 1. If the microcontroller derives the SPI master clock (SCLK) directly from CLKM, the SPI operates in synchronous mode, otherwise in asynchronous mode. In asynchronous mode, the maximum SCLK frequency fasync is limited to 7.5MHz. The CLKM signal is not required to derive SCLK and may be disabled to reduced power consumption and spurious emissions. Figure 35-2 and Figure 35-3 illustrate the SPI timing and introduces its parameters. The corresponding timing parameter definitions t1-t9 are defined in "Digital Interface Timing Characteristics" on page 1101. Figure 35-2. SPI Timing, Global Map and Definition of Timing Parameters, t5, t6, t8, t9 t8 t9 /SEL SCLK MOSI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 t5 MISO Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 t6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 884 Figure 35-3. SPI Timing, Detailed Drawing of Timing Parameters, t1 to t4 /SEL SCLK t3 MOSI t4 Bit 7 Bit 6 t1 Bit 5 t2 MISO Bit 7 Bit 6 Bit 5 The SPI is based on a byte-oriented protocol and is always a bidirectional communication between the master and slave. The SPI master starts the transfer by asserting /SEL = L. Then the master generates eight SPI clock cycles to transfer one byte to the radio transceiver (via MOSI). At the same time, the slave transmits one byte to the master (via MISO). When the master wants to receive one byte of data from the slave, it must also transmit one byte to the slave. All bytes are transferred with the MSB first. An SPI transaction is finished by releasing /SEL = H. An SPI register access consists of two bytes, a Frame Buffer or SRAM access of at least two or more bytes as described in "SPI Protocol" on page 885. /SEL = L enables the MISO output driver of the AT86RF233. The MSB of MISO is valid after t1 and is updated on each SCLK falling edge. If the driver is disabled, there is no internal pull-up transistor connected to it. Driving the appropriate signal level must be ensured by the microcontroller. Note: 1. When both /SEL and /RST are active, the MISO output driver is also enabled. Referring to Figure 35-2 and Figure 35-3, AT86RF233 MOSI is sampled at the rising edge of the SCLK signal and the output is set at the falling edge of SCLK. The signal must be stable before and after the rising edge of SCLK as specified by t3 and t4, refer to "Digital Interface Timing Characteristics" on page 1101. This SPI operational mode is commonly known as "SPI mode 0". 35.3 SPI Protocol Each SPI sequence starts with transferring a command byte from the SPI master via MOSI (see Table 35-2) with the MSB first. This command byte defines the SPI access mode and additional mode-dependent information. Table 35-2. SPI Command Byte Definition Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 1 0 Register address [5:0] 1 1 Register address [5:0] 0 0 1 Reserved 0 1 1 Reserved 0 0 0 Reserved 0 1 0 Reserved Bit 1 Bit 0 Access Mode Register access Frame Buffer access SRAM access Access Type Read access Write access Read access Write access Read access Write access Each SPI transfer returns bytes back to the SPI master on the MISO output signal. The content of the first byte (see value "PHY_STATUS" in Figure 35-4 to Figure 35-14) is set to zero after reset. To transfer status information of the radio transceiver to the microcontroller, the content of the first byte can be configured with register bits SPI_CMD_MODE (register 0x04, TRX_CTRL_1). For details, refer to "Register Description" on page 890. Note: 1. Return values on MISO stated as XX shall be ignored by the microcontroller. The different access modes are described within the following sections. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 885 35.3.1 Register Access Mode Register Access Mode is used to read and write AT86RF233 registers (register address from 0x00 up to 0x3F). A register access mode is a two-byte read/write operation initiated by /SEL = L. The first transferred byte on MOSI is the command byte including an identifier bit (bit[7] = 1), a read/write select bit (bit[6]), and a 6-bit register address. On read access, the content of the selected register address is returned in the second byte on MISO (see Figure 35-4). Figure 35-4. Packet Structure - Register Read Access byte 1 (command byte) MOSI 1 0 MISO Note: 1. ADDRESS[5:0] PHY_STATUS (1) byte 2 (data byte) XX READ DATA[7:0] Each SPI access can be configured to return radio controller status information (PHY_STATUS) on MISO, for details refer to "Radio Transceiver Status Information" on page 890. On write access, the second byte transferred on MOSI contains the write data to the selected address (see Figure 35-5). Figure 35-5. Packet Structure - Register Write Access byte 1 (command byte) MOSI MISO 1 1 ADDRESS[5:0] PHY_STATUS byte 2 (data byte) WRITE DATA[7:0] XX Each register access must be terminated by setting /SEL = H. Figure 35-6 illustrates a typical SPI sequence for a register access sequence for write and read respectively. Figure 35-6. Example SPI Sequence - Register Access Mode Register Write Access Register Read Access /SEL SCLK MOSI WRITE COMMAND MISO PHY_STATUS WRITE DATA XX READ COMMAND PHY_STATUS XX READ DATA 35.3.2 Frame Buffer Access Mode Frame Buffer Access Mode is used to read and write Atmel AT86RF233 frame buffer. The frame buffer address is always reset to zero and incremented to access PSDU, LQI, ED and RX_STATUS data. The Frame Buffer can hold up to 128-byte of one PHY service data unit (PSDU) IEEE 802.15.4 data frame. A detailed description of the Frame Buffer can be found in "Frame Buffer" on page 981. An introduction to the IEEE 802.15.4 frame format can be found in "Introduction - IEEE 802.15.4-2006 Frame Format" on page 947. Each access starts with /SEL = L followed by a command byte on MOSI. Each frame read or write access command byte is followed by the PHR data byte, indicating the frame length, followed by the PSDU data, see Figure 35-7 and Figure 358. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 886 In Frame Buffer Access Mode during buffer reads, the PHY header (PHR) and the PSDU data are transferred via MISO following PHY_STATUS byte. Once the PSDU data is uploaded, three more bytes are transferred containing the link quality indication (LQI) value, the energy detection (ED) value, and the status information (RX_STATUS) of the received frame, for LQI details refer to "Link Quality Indication (LQI)" on page 972. The Figure 35-7 illustrates the packet structure of a Frame Buffer read access. Note: 1. The frame buffer read access can be terminated immediately at any time by setting /SEL = H, for example after reading the PHR byte only. Figure 35-7. Packet Structure - Frame Read Access byte 1 (command byte ) byte 2 (data byte ) byte 3 (data byte ) byte n-1 (data byte ) byte n (data byte ) MOSI 0 0 1 reserved[4:0] XX XX XX XX MISO PHY_STATUS PHR[7:0] PSDU[7:0] ED[7:0] RX_STATUS[7:0] The structure of RX_STATUS is described in below. Structure of RX_STATUS Bit 7 6 RX_CRC_VALID Note: 1. 5 4 3 2 1 0 TRAC_STATUS Refer to the RX_CRC_VALID bit in the PHY_RSSI register and to TRAC_STATUS bits in the TRX_STATE for more information. On frame buffer write access the second byte transferred on MOSI contains the frame length (PHR field) followed by the payload data (PSDU) as shown by Figure 35-8. Figure 35-8. Packet Structure - Frame Write Access byte 1 (command byte ) byte 2 (data byte ) byte 3 (data byte ) byte n-1 (data byte ) byte n (data byte ) MOSI 0 1 1 reserved[4:0] PHR[7:0] PSDU[7:0] PSDU[7:0] PSDU[7:0] MISO PHY_STATUS XX XX XX XX The number of bytes n for one frame buffer access is calculated as follows: Read Access: n = 5 + frame_length [PHY_STATUS, PHR byte, PSDU data, LQI, ED, and RX_STATUS] Write Access: n = 2 + frame_length [command byte, PHR byte, and PSDU data] The maximum value of frame_length is 127 bytes. That means that n 132 for Frame Buffer read and n 129 for Frame Buffer write accesses. Each read or write of a data byte automatically increments the address counter of the Frame Buffer until the access is terminated by setting /SEL = H. A Frame Buffer read access can be terminated at any time without any consequences by setting /SEL = H, for example after reading the frame length byte only. A successive Frame Buffer read operation starts again with the PHR field. The content of the AT86RF233 Frame Buffer is overwritten by a new received frame or a Frame Buffer write access. Figure 35-9 and Figure 35-10 illustrate an example SPI sequence of a Frame Buffer access to read a frame with 2-byte PSDU and write a frame with 4-byte PSDU. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 887 Figure 35-9. Example SPI Sequence - Frame Buffer Read of a Frame with 2-byte PSDU /SEL SCLK MOSI COMMAND XX MISO PHY_ STATUS PHR XX PSDU 1 XX PSDU 2 XX XX LQI ED XX RX_STATUS Figure 35-10.Example SPI Sequence - Frame Buffer Write of a Frame with 4-byte PSDU /SEL SCLK MOSI COMMAND MISO PHY_STATUS PHR XX PSDU 1 XX PSDU 2 XX PSDU 3 XX PSDU 4 XX Access violations during a Frame Buffer read or write access are indicated by interrupt IRQ_6 (TRX_UR). For further details, refer to "Frame Buffer" on page 981. Notes: 1. 2. 3. The Frame Buffer is shared between RX and TX operations, the frame data is overwritten by freshly received data frames. If an existing TX payload data frame is to be retransmitted, it must be ensured that no TX data is overwritten by newly received RX data. To avoid overwriting during receive Dynamic Frame Buffer Protection can be enabled, refer to "Dynamic Frame Buffer Protection" on page 1032. For exceptions, receiving acknowledgement frames in Extended Operating Mode (TX_ARET) refer to "TX_ARET_ON - Transmit with Automatic Frame Retransmission and CSMA-CA Retry" on page 928. 35.3.3 SRAM Access Mode The SRAM access mode is used to read and write AT86RF233 frame buffer beginning with a specified byte address. It enables to access dedicated buffer data directly from a desired address without a need of incrementing the frame buffer from the top. The SRAM access mode allows accessing dedicated bytes within the Frame Buffer or AES address space, refer to "Security Module (AES)" on page 1005. This may reduce the SPI traffic. During frame receive, after occurrence of IRQ_2 (RX_START), an SRAM access can be used to upload the PHR field while preserving Dynamic Frame Buffer Protection, see "Dynamic Frame Buffer Protection" on page 1032. Each SRAM access starts with /SEL = L. The first transferred byte on MOSI shall be the command byte and must indicate an SRAM access mode according to the definition in Table 35-2. The following byte indicates the start address of the write or read access. SRAM address space: z Frame Buffer:0x00 to 0x7F z AES:0x82 to 0x94 On SRAM read access, one or more bytes of read data are transferred on MISO starting with the third byte of the access sequence; refer to Figure 35-11. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 888 Figure 35-11.Packet Structure - SRAM Read Access byte 1 (command byte ) byte 2 (address ) byte 3 (data byte ) byte n-1 (data byte ) byte n (data byte ) MOSI 0 0 0 reserved[4:0] ADDRESS[7:0] XX XX XX MISO PHY_STATUS XX DATA[7:0] DATA[7:0] DATA[7:0] On SRAM write access, one or more bytes of write data are transferred on MOSI starting with the third byte of the access sequence; refer to Figure 35-12. Do not attempt to read or write bytes beyond the SRAM buffer size. Figure 35-12.Packet Structure - SRAM Write Access byte 1 (command byte ) byte 2 (address ) byte 3 (data byte ) byte n-1 (data byte ) byte n (data byte ) MOSI 0 1 0 reserved[4:0] ADDRESS[7:0] DATA[7:0] DATA[7:0] DATA[7:0] MISO PHY_STATUS XX XX XX XX As long as /SEL = L, every subsequent byte read or byte write increments the address counter of the Frame Buffer until the SRAM access is terminated by /SEL = H. Figure 35-13 and Figure 35-14 illustrate an example SPI sequence of an Atmel AT86RF233 SRAM access to read and write a data package of five byte length, respectively. Figure 35-13.Example SPI Sequence - SRAM Read Access of a 5-byte Data Package /SEL SCLK MOSI COMMAND MISO PHY_STATUS ADDRESS XX XX DATA 1 XX DATA 2 XX XX DATA 3 DATA 4 XX DATA 5 Figure 35-14.Example SPI Sequence - SRAM Write Access of a 5-byte Data Package /SEL SCLK MOSI COMMAND MISO PHY_STATUS Notes: ADDRESS XX DATA 1 XX DATA 2 XX DATA 3 XX DATA 4 XX DATA 5 XX 1. The SRAM access mode is not intended to be used as an alternative to the Frame Buffer access modes (see "Frame Buffer Access Mode" on page 886). 2. Frame Buffer access violations are not indicated by a TRX_UR interrupt when using the SRAM access mode, for further details refer to "Interrupt Handling" on page 983. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 889 35.4 Radio Transceiver Status Information Each AT86RF233 SPI access can return radio transceiver status information which is a first byte transmitted out of MISO output as the serial data is being shifted into MOSI input. Radio transceiver status information (PHY_STATUS) can be configured using register bits SPI_CMD_MODE (register 0x04, TRX_CTRL_1) to return TRX_STATUS, PHY_RSSI or IRQ_STATUS register as shown in below. 35.4.1 Register Description Underlined values in the AT86RF233 register description indicate reset settings. 35.4.1.1 TRX_CTRL_1 Name: TRX_CTRL_1 Offset: 0x04 Reset: 0x22 Property: - The TRX_CTRL_1 register is a multi-purpose register to control various operating modes and settings of the radio transceiver. Bit 0x04 Access Reset z 7 6 5 4 3 PA_EXT_EM IRQ_2_EXT_ EN TX_AUTO_ CRC_ON RX_BL_ CTRL R/W R/W R/W R/W R/W 0 0 1 0 0 2 1 0 IRQ_MASK_ MODE IRQ_ POLARITY R/W R/W R/W 0 1 0 SPI_CMD_MODE Bit 3:2 - SPI_CMD_MODE Each SPI transfer returns bytes back to the SPI master. The content of the first byte (PHY_STATUS) can be configured using register bits SPI_CMD_MODE. Table 35-3. SPI_CMD_MODE Value Description 0x0 Default (empty, all bits zero) 0x1 Monitor TRX_STATUS register 0x2 Monitor PHY_RSSI register 0x3 Monitor IRQ_STATUS register Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 890 35.5 Radio Transceiver Identification AT86RF233 can be identified by four registers. One 8-bit register contains a unique part number (PART_NUM) and one register contains the corresponding 8-bit version number (VERSION_NUM). Two additional 8-bit registers contain the JEDEC manufacture ID. 35.5.1 Register Description 35.5.1.1 PART_NUM Name: PART_NUM Offset: 0x1C Reset: 0x0B Property: - The register PART_NUM can be used for the radio transceiver identification and includes the part number of the device. Bit 7 6 5 4 3 2 1 0 PART_NUM 0x1C Access R R R R R R R R Reset 0 0 0 0 1 0 1 1 z Bit 7:0 - PART_NUM Table 35-4. PART_NUM Value Description 0x0B AT86RF233 part number Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 891 35.5.1.2 VERSION_NUM Name: VERSION_NUM Offset: 0x1D Reset: 0x02 Property: - The register VERSION_NUM can be used for the radio transceiver identification and includes the version number of the device. Bit 7 6 5 4 3 2 1 0 VERSION_NUM 0x1D Access R R R R R R R R Reset 0 0 0 0 0 0 1 0 5 4 3 2 1 0 z Bit 7:0 - VERSION_NUM Table 35-5. VERSION_NUM Value Description 0x02 Revision B 35.5.1.3 MAN_ID_0 Name: MAN_ID_0 Offset: 0x1E Reset: 0x1F Property: - Part one of the JEDEC manufacturer ID. Bit 7 6 MAN_ID_0 0x1E Access R R R R R R R R Reset 0 0 0 1 1 1 1 1 z Bit 7:0 - MAN_ID_0 Table 35-6. MAN_ID_0 Value Description 0x1F Atmel JEDEC manufacturer ID, bits[7:0] of the 32-bit JEDEC manufacturer ID are stored in register bits MAN_ID_0. Bits [15:8] are stored in register 0x1F (MAN_ID_1). The higher 16 bits of the ID are not stored in registers. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 892 35.5.1.4 MAN_ID_1 Name: MAN_ID_1 Offset: 0x1F Reset: 0x00 Property: - Part two of the JEDEC manufacturer ID. Bit 7 6 5 4 3 2 1 0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 MAN_ID_1 0x1F z Bit 7:0 - MAN_ID_1 Table 35-7. MAN_ID_1 Value Description 0x00 Atmel JEDEC manufacturer ID, bits[15:8] of the 32-bit JEDEC manufacturer ID are stored in register bits MAN_ID_1. Bits [7:0] are stored in register 0x1E (MAN_ID_0). The higher 16 bits of the ID are not stored in registers. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 893 35.6 Sleep/Wake-up and Transmit Signal (SLP_TR) The internal SLP_TR input signal to the AT86RF233 is connected to PA20 and has multiple functions. Its function relates to the current state of the AT86RF233 and is summarized in Table 35-8. The radio transceiver states are explained in detail in "AT86RF233 Operating Modes" on page 902. Table 35-8. SLP_TR Multi-Functional Signal Transceiver Status Function Transition Description PLL_ON TX start LOH Starts frame transmission TX_ARET_ON TX start LOH Starts TX_ARET transaction BUSY_RX_AACK TX start LOH Starts ACK transmission during RX_AACK slotted operation, see "RX_AACK Slotted Operation - Slotted Acknowledgement" on page 926 TRX_OFF Sleep LOH Takes the radio transceiver into SLEEP state, CLKM disabled PREP_DEEP_SLEEP Deep Sleep LOH Takes the radio transceiver into DEEP_SLEEP state, CLKM disabled SLEEP Wakeup HOL Takes the radio transceiver back into TRX_OFF state, level sensitive DEEP_SLEEP Wakeup HOL Takes the radio transceiver back into TRX_OFF state, level sensitive In states PLL_ON and TX_ARET_ON, the internal SLP_TR signal connected to PA20 is used as trigger input to initiate a TX transaction. Here SLP_TR is sensitive on rising edge only. After initiating a state change by a rising edge at of the SLP_TR signal in radio transceiver states TRX_OFF or PREP_DEEP_SLEEP, the radio transceiver remains in the new state as long as the signal is logical high and returns to the preceding state with the falling edge. 35.6.1 SLEEP state The SLEEP state is used when radio transceiver functionality is not required, and thus the AT86RF233 can be powered down to reduce the overall power consumption. A power-down scenario is shown in Figure 35-15. When the radio transceiver is in TRX_OFF state the microcontroller forces the AT86RF233 to SLEEP by setting SLP_TR = H. If the CLKM signal provides a clock to the microcontroller this clock is switched off after 35 CLKM cycles. This enables a microcontroller in a synchronous system to complete its power-down routine and prevent deadlock situations. The AT86RF233 awakes when the microcontroller releases the SLP_TR signal. This concept provides the lowest possible power consumption. The CLKM clock frequency settings for 250kHz and 62.5kHz are not intended to directly clock the microcontroller. When using these clock rates, CLKM is turned off immediately when entering SLEEP state. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 894 Figure 35-15.Sleep and Wake-Up Initiated by Asynchronous Microcontroller Timer SLP _TR t TR 1a C LKM tTR 3 (35 C LKM clock cycles) C LKM off async timer elapses (microcontroller) Note: 1. Timing figures tTR3 and tTR1a refer to Table 36-1 on page 910. 35.6.2 DEEP_SLEEP state The DEEP_SLEEP state is used when radio transceiver functionality is not required, and thus the Atmel AT86RF233 can be powered down to reduce the overall power consumption. When the radio transceiver is in PREP_DEEP_SLEEP state the microcontroller forces the AT86RF233 to DEEP_SLEEP by setting SLP_TR = H. If CLKM provides a clock to the microcontroller this clock is switched off after 35 CLKM cycles. This enables a microcontroller in a synchronous system to complete its power-down routine and prevent deadlock situations. The AT86RF233 awakes when the microcontroller releases SLP_TR and goes into TRX_OFF state. This concept provides the lowest possible power consumption. The CLKM clock frequency settings for 250kHz and 62.5kHz are not intended to directly clock the microcontroller. When using these clock rates, CLKM is turned off immediately when entering DEEP_SLEEP state. Notes: 1. 2. After leaving the DEEP_SLEEP state the CLKM clock frequency is set back to 1MHz. If the radio transceiver is in DEEP_SLEEP state the register contents are cleared. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 895 35.7 Interrupt Logic 35.7.1 Overview AT86RF233 differentiates between nine interrupt events (eight physical interrupt registers, one shared by two functions). Each interrupt is enabled by setting the corresponding bit in the interrupt mask register 0x0E (IRQ_MASK). Internally, each pending interrupt is flagged in the interrupt status register. All interrupt events are OR-combined to a single interrupt signal (IRQ). If an interrupt is issued, the signal IRQ = H, the microcontroller shall read the interrupt status register 0x0F (IRQ_STATUS) to determine the source of the interrupt. A read access to this register clears the interrupt status register and thus the IRQ signal to the MCU, too. Interrupts are not cleared automatically when the event trigger for respective interrupt flag bit in the register 0x0F (IRQ_STATUS) is no longer active. Only a read access to register 0x0F (IRQ_STATUS) clears the flag bits. Exceptions are IRQ_0 (PLL_LOCK) and IRQ_1 (PLL_UNLOCK) where each is cleared in addition by the appearance of the other. The supported interrupts for the Basic Operating Mode are summarized in Table 35-9. Table 35-9. Interrupt Description in Basic Operating Mode IRQ_NAME Description Section IRQ_7 (BAT_LOW) Indicates a supply voltage below the programmed threshold. "Interrupt Handling" on page 988 IRQ_6 (TRX_UR) Indicates a Frame Buffer access violation. "Interrupt Handling" on page 983 IRQ_5 (AMI) Indicates address matching. "Frame Filter" on page 952 IRQ_4 (CCA_ED_DONE) Multi-functional interrupt: 1. AWAKE_END: Indicates finished transition to TRX_OFF state from P_ON, SLEEP, DEEP_SLEEP, or RESET state. "TRX_OFF - Clock State" on page 904 2. CCA_ED_DONE: "Interrupt Handling" on page 966 Indicates the end of a CCA or ED measurement. "Interrupt Handling" on page 969 IRQ_3 (TRX_END) RX: Indicates the completion of a frame reception. "Interrupt Handling" on page 906 TX: Indicates the completion of a frame transmission. "Interrupt Handling" on page 906 Note: IRQ_2 (RX_START) Indicates the start of a PSDU reception; the AT86RF233 state changed to BUSY_RX; the PHR can be read from Frame Buffer. "Interrupt Handling" on page 906 IRQ_1 (PLL_UNLOCK) Indicates PLL unlock. If the radio transceiver is in BUSY_TX / BUSY_TX_ARET state, the PA is turned off immediately. "Interrupt Handling" on page 995 IRQ_0 (PLL_LOCK) Indicates PLL lock. "Interrupt Handling" on page 995 1. The IRQ_4 (AWAKE_END) interrupt can usually not be seen when the transceiver enters TRX_OFF state after P_ON, DEEP_SLEEP, or RESET, because register 0x0E (IRQ_MASK) is reset to mask all interrupts. It is recommended to enable IRQ_4 (AWAKE_END) to be notified once the TRX_OFF state is entered. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 896 The interrupt handling in Extended Operating Mode is described in "Interrupt Handling" on page 931. 35.7.2 Interrupt Mask Modes and IRQ Signal Polarity If register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, an interrupt event can be read from IRQ_STATUS register even if the interrupt itself is masked. However, in that case no timing information for this interrupt is provided. The Table 35-10, Figure 35-16, and Figure 35-17 describes the function. Table 35-10. IRQ Mask Configuration IRQ_MASK Value IRQ_MASK Mode Description 0 0 IRQ is suppressed entirely and none of interrupt sources are shown in register IRQ_STATUS. 0 1 IRQ is suppressed entirely but all interrupt causes are shown in register IRQ_STATUS. 0 0 All enabled interrupts are signaled on the internal IRQ signal to the microcontroller and are also shown in register IRQ_STATUS. 0 1 All enabled interrupts are signaled on the internal IRQ signal to the microcontroller and all interrupt causes are shown in register IRQ_STATUS. Interrupt Sources Figure 35-16.IRQ_MASK_MODE = 0 . . . IR Q _M A S K (register 0x0 E ) IR Q _S T A T U S (register 0x0 F ) OR IR Q Interrupt Sources Figure 35-17.IRQ_MASK_MODE = 1 . . . IR Q _S TA TU S (register 0x0F) IR Q _M A S K OR IR Q (register 0x0E ) The AT86RF233 IRQ signal polarity can be configured with register bit IRQ_POLARITY (register 0x04, TRX_CTRL_1). The default behavior is active high, which means that the signal IRQ = H issues an interrupt request. If the "Frame Buffer Empty Indicator" is enabled during Frame Buffer read access, the IRQ signal has an alternative functionality, refer to "Frame Buffer Empty Indicator" on page 1030 for details. A solution to monitor the IRQ_STATUS register (without clearing it) is described in "Register Description" on page 890. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 897 35.7.3 Register Description 35.7.3.1 IRQ_MASK Name: IRQ_MASK Offset: 0x0E Reset: 0x00 Property: - The IRQ_MASK register controls the interrupt signaling via the internal IRQ signal to the microcontroller. Bit 7 6 5 4 3 2 1 0 IRQ_MASK 0x0E Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7:0 - IRQ_MASK Mask register for interrupts. IRQ_MASK[7] correspondents to IRQ_7 (BAT_LOW). IRQ_MASK[0] correspondents to IRQ_0 (PLL_LOCK). Table 35-11. IRQ_MASK Value Description 0x00 The IRQ_MASK register is used to enable or disable individual interrupts. An interrupt is enabled if the corresponding bit is set to one. All interrupts are disabled after power-on sequence (P_ON or DEEP_SLEEP state) or reset (RESET state). Valid values are [0xFF, 0xFE, ..., 0x00]. Note: 1. If an interrupt is enabled it is recommended to read the interrupt status register 0x0F (IRQ_STATUS) first to clear the history. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 898 35.7.3.2 IRQ_STATUS Name: IRQ_STATUS Offset: 0x0F Reset: 0x00 Property: - The IRQ_STATUS register contains the status of the pending interrupt requests. Bit 7 6 5 4 3 2 1 0 IRQ_7_BAT_ LOW IRQ_6_TRX_ UR IRQ_5_AMI IRQ_4_ CCA_ED_ DONE IRQ_3_TRX_ END IRQ_2_RX_ START IRQ_1_PLL_ UNLOCK IRQ_0_PLL_ LOCK Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 0x0F For more information to meanings of interrupts, see Table 35-9. By reading the register after an interrupt is signaled by the IRQ signal to the microcontroller the source of the issued interrupt can be identified. A read access to this register resets all interrupt bits, and so clears the IRQ_STATUS register. Notes: 1. 2. If register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, an interrupt event can be read from IRQ_STATUS register even if the interrupt itself is masked; refer to Figure 35-17. However in that case no timing information for this interrupt is provided. If register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, it is recommended to read the interrupt status register 0x0F (IRQ_STATUS) first to clear the history. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 899 35.7.3.3 TRX_CTRL_1 Name: TRX_CTRL_1 Offset: 0x04 Reset: 0x22 Property: - The TRX_CTRL_1 register is a multi-purpose register to control various operating modes and settings of the radio transceiver. Bit 0x04 7 6 5 4 PA_EXT_EM IRQ_2_EXT_ EN TX_AUTO_ CRC_ON RX_BL_ CTRL R/W R/W R/W R/W R/W 0 0 1 0 0 Access Reset z 3 2 1 0 IRQ_MASK_ MODE IRQ_ POLARITY R/W R/W R/W 0 1 0 SPI_CMD_MODE Bit 6 - IRQ_2_EXT_EN The register bit IRQ_2_EXT_EN controls signaling for time stamping via DIG2 signal. Table 35-12. IRQ_2_EXT_EN Value Description 0x0 Time stamping over the internal DIG2 signal to the microcontroller is disabled 0x1(1) Time stamping over the internal DIG2 signal to the microcontroller is enabled Note: 1. The DIG2 signal is also active if the corresponding interrupt event IRQ_2 (RX_START) mask bit in register 0x0E (IRQ_MASK) is set to zero. The signal remains at high level until the end of the frame receive or transmit procedure. The timing of a received frame can be determined by the DIG2 signal. If register bit IRQ_2_EXT_EN is set to one, the reception of a PHR field is directly issued on DIG2, similar to interrupt IRQ_2 (RX_START). For further details refer to "RX and TX Frame Time Stamping (TX_ARET)" on page 1027. z Bit 1 - IRQ_MASK_MODE The radio transceiver supports polling of interrupt events. Interrupt polling is enabled by setting register bit IRQ_MASK_MODE. Table 35-13. IRQ_MASK_MODE Value Description 0x0 Interrupt polling is disabled. Masked off IRQ bits will not appear in IRQ_STATUS register. 0x1 Interrupt polling is enabled. Masked off IRQ bits will appear in IRQ_STATUS register. With the interrupt polling enabled (IRQ_MASK_MODE = 1) the interrupt events are flagged in the register 0x0F (IRQ_STATUS) when their respective mask bits are disabled in the register 0x0E (IRQ_MASK). z Bit 0 - IRQ_POLARITY The register bit IRQ_POLARITY controls the polarity for IRQ signal to the microcontroller. The default polarity of the IRQ signal is active high. The polarity can be configured to active low via register bit IRQ_POLARITY. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 900 Table 35-14. IRQ_POLARITY Value Description 0x0 IRQ signal is high active 0x1 IRQ signal is low active Note: 1. A modification of register bit IRQ_POLARITY has no influence to RX_BL_CTRL behavior. This setting does not affect the polarity of the "Frame Buffer Empty Indicator", refer to "Frame Buffer Empty Indicator" on page 1030. The Frame Buffer Empty Indicator is always active high. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 901 36. AT86RF233 Operating Modes 36.1 Basic Operating Mode This section summarizes all states to provide the basic functionality of AT86RF233, such as receiving and transmitting frames, the power-on sequence, sleep, and deep sleep. The Basic Operating Mode is designed for IEEE 802.15.4 and general ISM band applications; the corresponding radio transceiver states are shown in Figure 36-1. Figure 36-1. Basic Operating Mode State Diagram For timing, refer to Table 36-1 on page 910 P_ON SLEEP (Power-on after VDD) (Sleep State) PREP_ DEEP_SLEEP P SL EE FF P_ EE R P_T SL =L (from all states) /RST = L PR EP SLP F TR X_ O OF 18 17 _D H _TR X_ XOSCRF=OFF Pull=ON 16 3 = _TR =L 2 TR 19 XOSCRF=ON Pull=OFF SLP 15 (Sleep State) (Prepare Sleep State) XOSCRF=OFF Pull=OFF XOSCRF=ON Pull=ON DEEP_SLEEP SLP_TR=H FORCE_TRX_OFF TRX_OFF 12 N _O FF RX N X_ O TR RX_ON 4 FF 8 O L_ PL Frame End O X_ BUSY_RX (Receive State) SHR Detected 5 TR 6 RESET (all states except P_ON) XOSCRF=ON Pull=OFF 7 /RST = H 13 (Clock State) (all states except SLEEP or DEEP_SLEEP) 11 RX_ON PLL_ON (Rx Listen State) Frame End BUSY_TX (Transmit State) (PLL State) 10 PLL_ON 9 SLP_TR = H or TX_START FORCE_PLL_ON 14 (all states except DEEP_SLEEP, Legend: SLEEP, or P_ON) Blue: SPI Write to Register TRX_STATE (0x02) Red: Control signals from the microcontroller Green: Event Basic Operating Mode States X State transition number 36.1.1 State Control The radio transceiver's states are controlled by shifting serial digital data using the SPI to write individual commands to the command register bits TRX_CMD (register 0x02, TRX_STATE). Change of the transceiver state can also be triggered by driving directly two signals SLP_TR and /RST. A successful state change can be verified by reading the radio transceiver status from register bits TRX_STATUS (register 0x01, TRX_STATUS). If TRX_STATUS = 0x1F (STATE_TRANSITION_IN_PROGRESS) the AT86RF233 is in a state transition. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 902 The SLP_TR signal that has to be driven by the microcontroller has multiple functions (refer to "Sleep/Wake-up and Transmit Signal (SLP_TR)" on page 894). Depending on the radio transceiver state, a rising edge of the SLP_TR signal causes the following state transitions: z TRX_OFF -> SLEEP z PLL_ON -> BUSY_TX z PREP_ DEEP_SLEEP -> DEEP_SLEEP (Level sensitive) (Level sensitive) Whereas the falling edge of SLP_TR causes the following state transitions: z SLEEP -> TRX_OFF (Level sensitive) z DEEP_SLEEP -> TRX_OFF (Level sensitive) A low level on /RST causes a reset of all registers (register bits CLKM_CTRL are shadowed, for details, refer to "Master Clock Signal Output (CLKM)" on page 991) and forces the radio transceiver into TRX_OFF state. However, if the device was in P_ON state it remains in the P_ON state. For all states except SLEEP and DEEP_SLEEP, the state change commands FORCE_TRX_OFF or TRX_OFF lead to a transition into TRX_OFF state. If the radio transceiver is in active receive or transmit states (BUSY_*), the command FORCE_TRX_OFF interrupts these active processes, and forces an immediate transition to TRX_OFF. In contrast a TRX_OFF command is stored until an active state (receiving or transmitting) has been finished. After that the transition to TRX_OFF is performed. For a fast transition from any non sleep states to PLL_ON state the command FORCE_PLL_ON is provided. Active processes are interrupted. In contrast to FORCE_TRX_OFF, this command does not disable PLL and analog voltage regulator (AVREG). It is not available in states P_ON, SLEEP, DEEP_SLEEP, or RESET. The completion of each requested state change shall always be confirmed by reading the register bits TRX_STATUS (register 0x01, TRX_STATUS). Note: If FORCE_TRX_OFF and FORCE_PLL_ON commands are used, it is recommended to set SLP_TR = L before. 36.1.2 Basic Operating Mode Description 36.1.2.1 P_ON - Power-On after VDD When the external supply voltage (VDD) is firstly applied to the AT86RF233, the radio transceiver goes into P_ON state performing an on-chip reset. The crystal oscillator is activated and the master clock is provided at the CLKM clock signal to the microcontroller after the crystal oscillator has stabilized. CLKM can be used as a clock source for the microcontroller generic clock controller after it has been configured as described in "Master Clock Signal Output (CLKM)" on page 991. The SPI interface and digital voltage regulator (DVREG) are enabled. The on-chip power-on-reset sets all registers to their default values. A dedicated reset signal from the microcontroller at /RST is not necessary, but recommended for hardware / software synchronization reasons. All digital inputs are pulled-up or pulled-down during P_ON state, refer to "Pull-up and Pull-down Configuration" on page 19. This is necessary as the microcontroller GPIO signals are floating after power-on or reset. The input pull-up and pulldown transistors are disabled when the radio transceiver leaves P_ON state towards TRX_OFF state. A reset during P_ON state does not change the pull-up and pull-down configuration. Leaving P_ON state, output signals DIG1/DIG2 are pulled-down to digital ground, whereas signals DIG3/DIG4 are pulled-down to analog ground, unless their configuration is changed. Prior to leaving P_ON, the microcontroller must set the Atmel AT86RF233 input signals to the default operating values: SLP_TR = L, /RST = H and /SEL = H. All interrupts are disabled by default. Thus, interrupts for state transition control are to be enabled first, for example enable IRQ_4 (AWAKE_END) to indicate a state transition to TRX_OFF state or interrupt IRQ_0 (PLL_LOCK) to signal a Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 903 locked PLL in PLL_ON state. In P_ON state a first access to the radio transceiver registers is possible after a master clock is provided at the internal CLKM clock signal to the microcontroller, refer to tTR1 in Table 36-1 on page 910. Once the supply voltage has stabilized and the crystal oscillator has settled (refer to parameter tXTAL in Table 36-2 on page 912), the interrupt mask for the AWAKE_END should be set. A valid SPI write access to register bits TRX_CMD (register 0x02, TRX_STATE) with the command TRX_OFF or FORCE_TRX_OFF initiate a state change from P_ON towards TRX_OFF state, which is then indicated by an interrupt IRQ_4 (AWAKE_END) if enabled. 36.1.2.2 SLEEP - Sleep State In SLEEP state, the radio transceiver is disabled. No circuitry is operating beyond the circuitry monitoring SLP_TR and /RST. This state can only be entered from state TRX_OFF, by setting the SLP_TR = H. If CLKM is enabled with a clock rates higher than 250kHz, the SLEEP state is entered 35 CLKM cycles after the rising edge of SLP_TR. At that time CLKM is turned off. If the CLKM output is already turned off (register bits CLKM_CTRL = 0), the SLEEP state is entered immediately. At clock rates 250kHz and 62.5kHz, the main clock at CLKM is turned off immediately. Setting SLP_TR = L returns the radio transceiver back to the TRX_OFF state. During SLEEP state the radio transceiver register contents and the AES register contents remain valid while the contents of the Frame Buffer are lost. /RST = L in SLEEP state returns the radio transceiver to TRX_OFF state and thereby sets all registers to their default values. Exceptions are register bits CLKM_CTRL (register 0x03, TRX_CTRL_0). These register bits require a specific treatment, for details see "Master Clock Signal Output (CLKM)" on page 991. 36.1.2.3 PREP_DEEP_SLEEP - Deep Sleep Preparation State The state PREP_DEEP_SLEEP is the preparation state for DEEP_SLEEP state. The state can be reached by writing the command PREP_DEEP_SLEEP to register bits TRX_CMD (register 0x02, TRX_STATE). If CLKM is enabled with a clock rates higher than 250kHz, the DEEP_SLEEP state is entered 35 CLKM cycles after the rising edge of SLP_TR. At that time CLKM is turned off. If the CLKM output is already turned off (register bits CLKM_CTRL = 0), the DEEP_SLEEP state is entered immediately. At clock rates 250kHz and 62.5kHz, the main clock at CLKM is turned off immediately. 36.1.2.4 DEEP_SLEEP - Deep Sleep State In DEEP_SLEEP state, the entire radio transceiver is disabled. No circuitry is operating beyond the circuitry monitoring SLP_TR. The radio transceiver current consumption is reduced to leakage current only. This state can only be entered from state PREP_DEEP_SLEEP, by setting the SLP_TR = H. Setting SLP_TR = L returns the radio transceiver back to the TRX_OFF state. After DEEP_SLEEP state the radio transceiver register contents and the AES register contents obtain the reset values while the contents of the Frame Buffer are lost. The CLKM starts with the default 1MHz master clock at CLKM clock signal to the microcontroller after the crystal oscillator has stabilized. All AT86RF233 digital inputs are pulled-up or pulled-down during DEEP_SLEEP state, refer to "Pull-up and Pull-down Configuration" on page 19, except SLP_TR. 36.1.2.5 TRX_OFF - Clock State In TRX_OFF the crystal oscillator is running and the master clock is available if enabled. The SPI interface and digital voltage regulator are enabled, thus the radio transceiver registers, the Frame Buffer and security engine (AES) are accessible (see "Frame Buffer" on page 981 and "Security Module (AES)" on page 1005). In contrast to P_ON state the pull-up and pull-down configuration is disabled. Notes: 1. SLP_TR and /RST are available for state control. 2. The analog front-end is disabled during TRX_OFF state. Entering the TRX_OFF state from P_ON, SLEEP, DEEP_SLEEP or RESET state is indicated by interrupt IRQ_4 (AWAKE_END) if enabled. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 904 36.1.2.6 PLL_ON - PLL State Entering the PLL_ON state from TRX_OFF state enables the analog voltage regulator (AVREG) first. After the voltage regulator has been settled (see Table 36-2 on page 912), the PLL frequency synthesizer is enabled. When the PLL has been settled at the receive frequency to a channel defined by register bits CHANNEL (register 0x08, PHY_CC_CCA) or register bits CC_NUMBER (register 0x13, CC_CTRL_0) and CC_BAND (register 0x14, CC_CTRL_1), refer to "RF Channel Selection" on page 994, a successful PLL lock is indicated by issuing an interrupt IRQ_0 (PLL_LOCK). If an RX_ON command is issued in PLL_ON state, the receiver is enabled immediately. If the PLL has not been settled before the state change nevertheless takes place. Even if the register bits TRX_STATUS (register 0x01, TRX_STATUS) indicates RX_ON, actual frame reception can only start once the PLL has locked. The PLL_ON state corresponds to the TX_ON state in IEEE 802.15.4. 36.1.2.7 RX_ON and BUSY_RX - RX Listen and Receive State In RX_ON state the receiver is in the RX data polling mode and the PLL frequency synthesizer is locked to its preprogrammed frequency. The AT86RF233 receive mode is internally separated into RX_ON state and BUSY_RX state. There is no difference between these states with respect to the analog radio transceiver circuitry, which are always turned on. In both states, the receiver and the PLL frequency synthesizer are enabled. During RX_ON state, the receiver listens for incoming frames. After detecting a valid synchronization header (SHR), the Atmel AT86RF233 automatically enters the BUSY_RX state. The reception of a valid PHY header (PHR) generates an IRQ_2 (RX_START) if enabled. During PSDU reception, the frame data are stored continuously in the Frame Buffer until the last byte was received. The completion of the frame reception is indicated by an interrupt IRQ_3 (TRX_END) and the radio transceiver reenters the state RX_ON. At the same time the register bit RX_CRC_VALID (register 0x06, PHY_RSSI) is updated with the result of the FCS check (see "Frame Check Sequence (FCS)" on page 961). Received frames are passed to the frame filtering unit, refer to "Frame Filter" on page 952. If the content of the MAC addressing fields (refer to [2] IEEE 802.15.4-2006 Section 7.2.1) generates a match, IRQ_5 (AMI) interrupt is issued, refer to "Interrupt Logic" on page 896. The expected address values are to be stored in registers 0x20 - 0x2B (Short address, PAN-ID and IEEE address). Frame filtering is available in Basic Operating Mode and Extended Operating Mode, refer to "Frame Filter" on page 952. Leaving state RX_ON is possible by writing a state change command to register bits TRX_CMD in register 0x02 (TRX_STATE). 36.1.2.8 BUSY_TX - Transmit State In the BUSY_TX state AT86RF233 is in the data transmission state. A transmission can only be initiated from the PLL_ON state. The transmission can be started either by driving event such as: z A rising edge on SLP_TR, or z A serial TX_START command via the SPI to register bits TRX_CMD (register 0x02, TRX_STATE). Either of these takes the radio transceiver into the BUSY_TX state. Refer to "Frame Transmit Procedure" on page 1003 for more details. During the transition to the BUSY_TX state, the PLL frequency shifts to the transmit frequency, refer to "PLL Settling Time and Frequency Agility" on page 994. The actual transmission of the first data chip of the SHR starts after 16s to allow PLL settling and PA ramp-up, see Figure 36-7. After transmission of the SHR, the Frame Buffer content is transmitted. In case the PHR indicates a frame length of zero, the transmission is aborted immediately after the PHR field. After the frame transmission has been completed, the AT86RF233 automatically turns off the power amplifier, generates an IRQ_3 (TRX_END) interrupt and returns into PLL_ON state. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 905 36.1.2.9 RESET State The RESET state is used to set back the state machine and to reset all registers of Atmel AT86RF233 to their default values; exceptions are register bits CLKM_CTRL (register 0x03, TRX_CTRL_0). These register bits require a specific treatment, for details see "Master Clock Signal Output (CLKM)" on page 991. Once in RESET state a device enters TRX_OFF state by setting or pulling the internal reset signal /RST to the AT86RF233 high. If the device is still in the P_ON state it remains in the P_ON state though. A reset is triggered by pulling /RST low (/RST = L) and the state returns after setting /RST = H. The reset pulse should have a minimum length as specified in "Reset Procedure" on page 909 (parameter t10). During reset, the microcontroller has to set the radio transceiver control signals SLP_TR and /SEL to their default values. An overview about the register reset values is provided in Table 41-2 on page 1054. 36.1.3 Interrupt Handling All interrupts provided by the AT86RF233 (see Table 35-9 on page 896) are supported in Basic Operating Mode. For example, interrupts are provided to observe the status of radio transceiver RX and TX operations. When being in receive mode, IRQ_2 (RX_START) indicates the detection of a valid PHR first, IRQ_5 (AMI) an address match, and IRQ_3 (TRX_END) the completion of the frame reception. During transmission, IRQ_3 (TRX_END) indicates the completion of the frame transmission. Figure 36-2 shows an example for a transmit/receive transaction between two devices and the related interrupt events in Basic Operating Mode. Device 1 transmits a frame containing a MAC header (in this example of length seven), MAC payload, and a valid FCS. The end of the frame transmission is indicated by IRQ_3 (TRX_END). The frame is received by Device 2. Interrupt IRQ_2 (RX_START) indicates the detection of a valid PHR field and IRQ_3 (TRX_END) the completion of the frame reception. If the frame passes the Frame Filter (refer to "Frame Filter" on page 952), an address match interrupt IRQ_5 (AMI) is issued after the reception of the MAC header (MHR). The received frame is stored in the Frame Buffer. In Basic Operating Mode the third interrupt IRQ_3 (TRX_END) is issued at the end of the received frame. In Extended Operating Mode, refer to "Extended Operating Mode" on page 915; the interrupt is only issued if the received frame passes the address filter and the FCS is valid. Further exceptions are explained in "Extended Operating Mode" on page 915. Processing delay tIRQ is a typical value, refer to "Digital Interface Timing Characteristics" on page 1101. Figure 36-2. Timing of RX_START, AMI and TRX_END Interrupt in Basic Operation Modes 160 PLL_ON 192 192+(9+m)*32 BUSY_TX Time [s] PLL_ON SLP_TR IRQ Number of Octets Frame Content TRX_STATE IRQ Interrupt latency tTR10 4 1 1 7 m 2 Preamble SFD PHR MHR MSDU FCS RX_ON BUSY_RX IRQ_2 (RX_START) tIRQ IRQ_5 (AMI) tIRQ Frame on Air Typ. Processing Delay IRQ_3 (TRX_END) RX_ON TRX_END tIRQ Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 RX (Device 2) TRX_STATE 128 TX (Device1) -16 0 906 36.1.4 Basic Operating Mode Timing This section depicts AT86RF233 state transitions and their timing properties. Timing figures are explained in Table 36-1, Table 36-2 and "Digital Interface Timing Characteristics" on page 1101. 36.1.4.1 Power-on Procedure The power-on procedure to P_ON state is shown in Figure 36-3. Figure 36-3. Power-on Procedure to P_ON XOSCRF, DVREG When the external supply voltage (VDD) is initially supplied to the AT86RF233, the radio transceiver enables the crystal oscillator (XOSCRF) and the internal 1.8V voltage regulator for the digital domain (DVREG). After tTR1 = 330s (typ.), the master clock signal is available at the internal CLKM clock signal to the microcontroller. As soon as CLKM is available the SPI is enabled and can be used to control the transceiver. As long as no state change towards state TRX_OFF is performed, the radio transceiver remains in P_ON state. 36.1.4.2 Wake-up Procedure from SLEEP The wake-up procedure from SLEEP state is shown in Figure 36-4. Figure 36-4. Wake-Up Procedure from SLEEP State 0 State Block CLKM on SLP_TR = L Event Time [s] 200 IRQ_4 (AWAKE_END) TRX_OFF SLEEP XOSCRF, DVREG Time FTN XOSCRF, DVREG tTR2 The radio transceiver's SLEEP state is left by releasing SLP_TR to logic low. This restarts the XOSCRF and DVREG. After tTR2 = 210s (typ.) the radio transceiver enters TRX_OFF state. The internal clock signal is available and provided by CLKM, if enabled. This procedure is similar to the Power-on Procedure. However the radio transceiver automatically proceeds to the TRX_OFF state. During this, transition the filter-tuning network (FTN) calibration is performed. Entering TRX_OFF state is signaled by IRQ_4 (AWAKE_END), if this interrupt was enabled by the appropriate mask register bit. 36.1.4.3 Wake-up Procedure from DEEP_SLEEP The wake-up procedure from DEEP_SLEEP state is shown in Figure 36-5. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 907 Figure 36-5. Wake-Up Procedure from DEEP_SLEEP State 0 SLP_TR = L Event State IRQ_4 (AWAKE_END) CLKM on DEEP_ SLEEP Block Time [s] 350 TRX_OFF XOSCRF, DVREG Time FTN XOSCRF, DVREG tTR18 The AT86RF233 radio transceiver's DEEP_SLEEP state is left by releasing SLP_TR to logic low. This restarts the XOSCRF and DVREG. After tTR18 = 360s (typ.) the radio transceiver enters TRX_OFF state. The internal clock signal is available and provided at a default rate of 1MHz to CLKM. This procedure is similar to the Power-on Procedure. However the radio transceiver automatically proceeds to the TRX_OFF state. During this, transition the filter-tuning network (FTN) calibration is performed. 36.1.4.4 PLL_ON and RX_ON States The transition from TRX_OFF to PLL_ON or RX_ON mode is shown in Figure 36-6. Figure 36-6. Transition from TRX_OFF to PLL_ON or RX_ON State 0 80 IRQ_0 (PLL_LOCK) Event State 1. 2. PLL_ON TRX_OFF Block AVREG Command PLL_ON Time Notes: Time [s] PLL RX_ON RX RX_ON tTR4 tTR8 If TRX_CMD = RX_ON in TRX_OFF state RX_ON state is entered immediately, even if the PLL has not settled. Timing figures tTR4 and tTR8 refers to Table 36-1 on page 910. In TRX_OFF state, entering the commands PLL_ON or RX_ON initiates a ramp-up sequence of the internal 1.8V voltage regulator for the analog domain (AVREG). RX_ON state can be entered any time from PLL_ON state, regardless whether the PLL has already locked, which is indicated by IRQ_0 (PLL_LOCK). Likewise, PLL_ON state can be entered any time from RX_ON state. 36.1.4.5 BUSY_TX to RX_ON States The transition from PLL_ON to BUSY_TX state and subsequently to RX_ON state is shown in Figure 36-7. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 908 Figure 36-7. PLL_ON to BUSY_TX to RX_ON Timing 0 16 x x + 32 Time [ s ] SLP_TR State PLL _ ON Block BUSY _ TX PLL Command PA or command TX Time RX _ ON PA , TX _ START PLL RX RX _ ON t TR 10 t TR11 Starting from PLL_ON state, it is further assumed that the PLL has already been locked. A transmission is initiated either by a rising edge of SLP_TR or by command TX_START. The PLL settles to the transmit frequency and the PA is enabled. After the duration of tTR10 = 16s, the AT86RF233 changes into BUSY_TX state, transmitting the internally generated SHR and the PSDU data of the Frame Buffer. After completing the frame transmission, indicated by IRQ_3 (TRX_END), the PLL settles back to the receive frequency within tTR11 = 32s and returns to state PLL_ON. If during BUSY_TX the radio transmitter is requested to change to a receive state, it automatically proceeds to state RX_ON upon completion of the transmission. 36.1.4.6 Reset Procedure The radio transceiver reset procedure is shown in Figure 36-8. Figure 36-8. Reset Procedure x 0 x + 10 Event State Block Time [s] x + 30 [IRQ_4 (AWAKE_END)] TRX_OFF various XOSCRF, DVREG FTN XOSCRF, DVREG /RST Time Note: >t10 >t11 tTR13 Timing figure tTR13 refers to Table 36-1, t10, t11 refers to "Digital Interface Timing Characteristics" on page 1101. /RST = L sets all registers to their default values. Exceptions are register bits CLKM_CTRL (register 0x03, TRX_CTRL_0), refer to "Master Clock Signal Output (CLKM)" on page 991. After releasing the reset /RST = H, the wakeup sequence including an FTN calibration cycle is performed, refer to "Automatic Filter Tuning (FTN)" on page 1001. After that the TRX_OFF state is entered. Figure 36-8 illustrates the reset procedure once P_ON state was left and the radio transceiver was not in SLEEP or DEEP_SLEEP state. The reset procedure is identical for all originating radio transceiver states except of state P_ON, SLEEP, or DEEP_SLEEP. Instead, the procedures described in "P_ON - Power-On after VDD" on page 903 must be followed to enter the TRX_OFF state. If the radio transceiver was in state SLEEP or DEEP_SLEEP, the XOSCRF and DVREG are enabled before entering TRX_OFF state. If register bits TRX_STATUS indicates STATE_TRANSITION_IN_PROGRESS during system initialization until the AT86RF233 reaches TRX_OFF state, do not try to initiate a further state change while the radio transceiver is in this Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 909 state. Notes: 1. 2. 3. The reset impulse should have a minimum length t10 = 625ns as specified in "Digital Interface Timing Characteristics" on page 1101. An access to the device should not occur earlier than t11 625ns after releasing the /RST signal; refer to "Digital Interface Timing Characteristics" on page 1101. A reset overrides an SPI command request that might have been queued. 36.1.4.7 State Transition Timing Summary The Atmel AT86RF233 transition numbers correspond to Figure 36-1 and do not include SPI access time unless otherwise stated. See measurement setup in Figure 34-1. Table 36-1. State Transition Timing Symbol tTR1 tTR1a tTR1b tTR2 tTR3 Parameter Condition Min. Typ. Max. Unit P_ONCLKM is available Depends on crystal oscillator setup (CL= 10pF) and external capacitor at DVDD (100nF nom.). 330 1000 s SLEEPCLKM is available Depends on crystal oscillator setup (CL= 10pF) and external capacitor at DVDD (100nF nom.). 180 1000 s DEEP_SLEEPCLKM is available Depends on crystal oscillator setup (CL= 10pF) and external capacitor at DVDD (100nF nom.). 330 1000 s SLEEPTRX_OFF Depends on crystal oscillator setup (CL= 10pF) and external capacitor at DVDD (100nF nom.). 210 1000 s For fCLKM > 250kHz. 35 CLKM cycles Otherwise. 0 CLKM cycles Depends on external capacitor at AVDD (100nF nom.). 80 s 1 s 80 s TRX_OFFSLEEP tTR4 TRX_OFFPLL_ON tTR5 PLL_ONTRX_OFF tTR6 TRX_OFFRX_ON tTR7 RX_ONTRX_OFF 1 s tTR8 PLL_ONRX_ON 1 s tTR9 RX_ONPLL_ON Transition time is also valid for TX_ARET_ON, RX_AACK_ON. 1 s PLL_ONBUSY_TX When asserting SLP_TR or TRX_CMD = TX_START first symbol transmission is delayed by one symbol period (PLL settling and PA ramp-up). 16 s tTR10 Depends on external capacitor at AVDD (100nF nom.). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 910 Table 36-1. State Transition Timing (Continued) Symbol Parameter Condition tTR11 BUSY_TXPLL_ON PLL settling time. 32 s tTR12 Various statesTRX_OFF Using TRX_CMD = FORCE_TRX_OFF; not valid for SLEEP or DEEP_SLEEP. 1 s tTR13 RESETTRX_OFF Not valid for P_ON, SLEEP, or DEEP_SLEEP. 26 s tTR14 Various statesPLL_ON Using TRX_CMD = FORCE_PLL_ON; not valid for P_ON, SLEEP, DEEP_SLEEP, or RESET. 1 s tTR15 P_ONTRX_OFF Using TRX_CMD = TRX_OFF directly after CLKM is available. 360 tTR16 PREP_DEEP_SLEEPTRX_OFF 1 s tTR17 TRX_OFFPREP_DEEP_SLEEP 1 s tTR18 tTR19 DEEP_SLEEPTRX_OFF Min. Typ. Max. 1000 Unit s Depends on crystal oscillator setup (CL= 10pF) and external capacitor at DVDD (100nF nom.). 360 For fCLKM > 250kHz. 35 CLKM cycles Otherwise. 0 CLKM cycles 1000 PREP_DEEP_SLEEPDEEP_SLEEP s The state transition timing is calculated based on the timing of the individual blocks shown in Figure 36-3 to Figure 36-8. The worst case values include maximum operating temperature, minimum supply voltage, and device parameter variations. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 911 Table 36-2. Block Initialization and Settling Time Symbol Parameter Condition Min. Typ. Max. Unit tXTAL Reference oscillator settling time Start XTALclock available at CLKM. Depends on crystal Q factor and load capacitor. 330 1000 s tFTN FTN calibration time 25 s tDVREG DVREG settling time Depends on external bypass capacitor at DVDD (CB3 = 100nF nom., 10F worst case). 50 1000 s tAVREG AVREG settling time Depends on external bypass capacitor at AVDD (CB1 = 100nF nom., 10F worst case). 50 1000 s tPLL_INIT Initial PLL settling time PLL settling time TRX_OFFPLL_ON, including 40s AVREG settling time. 80 250 s tPLL_SW PLL settling time on channel switch Duration of channel switch within frequency band. 11 100 s tPLL_CF PLL CF calibration PLL center frequency calibration. 8 24 s tPLL_DCU PLL DCU calibration PLL DCU calibration. 6 6 s tRX_TX RXTX Maximum settling time RXTX. 16 s tTX_RX TXRX Maximum settling time TXRX. 32 s tSHR_SYNC SHR, sync SHR synchronization period. 160 s tRSSI RSSI, update RSSI update period in receive states. 2 tED ED measurement ED measurement period is eight symbols. 135 180 s tCCA CCA measurement CCA measurement period is eight symbols. 135 180 s tRND Random value, update Random value update period. 1 tAES AES core cycle time 8 32 96 23.4 s s 24 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 s 912 36.1.5 Register Description 36.1.5.1 TRX_STATUS Name: TRX_STATUS Offset: 0x01 Reset: 0x00, 0x08 Property: - The read-only register TRX_STATUS signals the present state of the radio transceiver as well as the status of a CCA operation. Bit 7 6 CCA_DONE CCA_STATUS Access R R R R R Reset 0 0 0 0 0 0x01 z 5 4 3 2 1 0 R R R 0 0 0 TRX_STATUS Bit 4:0 - TRX_STATUS The register bits TRX_STATUS signal the current radio transceiver status. Table 36-3. TRX_STATUS Value Description 0x00 P_ON 0x01 BUSY_RX 0x02 BUSY_TX 0x06 RX_ON 0x08 TRX_OFF (CLK Mode) 0x09 PLL_ON (TX_ON) 0x0F(1) SLEEP 0x10 PREP_DEEP_SLEEP 0x11(2) BUSY_RX_AACK 0x12(2) BUSY_TX_ARET 0x16(2) RX_AACK_ON 0x19(2) TX_ARET_ON 0x1F(3) STATE_TRANSITION_IN_PROGRESS All other values are reserved Notes: 1. In SLEEP or DEEP_SLEEP state register not accessible. 2. Extended Operating Mode only. 3. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS state. A read access to register bits TRX_STATUS reflects the current radio transceiver state. A state change is initiated by writing a state transition command to register bits TRX_CMD (register 0x02, TRX_STATE). Alternatively, some state transitions can be initiated by the rising edge of SLP_TR in the appropriate state. These register bits are used for Basic and Extended Operating Mode, see "Extended Operating Mode" on page 915. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 913 If the requested state transition has not been completed, the TRX_STATUS returns STATE_TRANSITION_IN_PROGRESS value. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS state. State transition timings are defined in Table 36-1 on page 910. 36.1.5.2 TRX_STATE Name: TRX_STATE Offset: 0x02 Reset: 0x00 Property: - The radio transceiver states are advanced via register TRX_STATE by writing a command word into register bits TRX_CMD. The read-only register bits TRAC_STATUS indicate the status or result of an Extended Operating Mode transaction. Bit 7 6 5 4 3 TRAC_STATUS 0x02 2 1 0 TRX_CMD Access R R R R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bit 4:0 - TRX_CMD A write access to register bits TRX_CMD initiate a radio transceiver state transition to the new state. Table 36-4. TRX_CMD Value Description 0x00(1) NOP 0x02(2) TX_START 0x03 FORCE_TRX_OFF 0x04(3) FORCE_PLL_ON 0x06 RX_ON 0x08 TRX_OFF (CLK Mode) 0x09 PLL_ON (TX_ON) 0x10 PREP_DEEP_SLEEP 0x16(4) RX_AACK_ON 0x19(4) TX_ARET_ON All other values are reserved Notes: 1. 2. 3. 4. TRX_CMD = "0" after power on reset (POR). The frame transmission starts one symbol after TX_START command. FORCE_PLL_ON is not valid for states P_ON, SLEEP, DEEP_SLEEP, and RESET, as well as STATE_TRANSITION_IN_PROGRESS towards these states. Extended Operating Mode only. A write access to register bits TRX_CMD initiates a radio transceiver state transition towards the new state. These register bits are used for Basic and Extended Operating Mode, see "Extended Operating Mode" on page 915 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 914 36.2 Extended Operating Mode Extended Operating Mode makes up for a large set of automated functionality add-on's which can be referred to as a hardware MAC accelerator. These add-on's go beyond the basic radio transceiver functionality provided by the Basic Operating Mode. Extended Operating Mode functions handle time critical MAC tasks, requested by the IEEE 802.15.4 standard, in hardware, such as automatic acknowledgement, automatic CSMA-CA, and retransmission. This results in a more efficient IEEE 802.15.4 software MAC implementation, including reduced code size, and may allow use of a smaller microcontroller or operation at low clock rates. The Extended Operating Mode is designed to support IEEE 802.15.4-2006 and IEEE 802.15.4-2011 compliant frames; the mode is backward compatible to IEEE 802.15.4-2003 and supports non IEEE 802.15.4 compliant frames. This mode comprises the following procedures: Automatic acknowledgement (RX_AACK) divides into the tasks: z Frame reception and automatic FCS check z Configurable addressing fields check z Interrupt indicating address match z Interrupt indicating frame reception, if it passes address filtering and FCS check z Automatic ACK frame transmission (if the received frame passed the address filter and FCS check and if an ACK is required by the frame type and ACK request) z Support of slotted acknowledgment using SLP_TR signal (used for beacon-enabled operation) Automatic CSMA-CA and Retransmission (TX_ARET) divides into the tasks: z CSMA-CA, including automatic CCA retry and random backoff z Frame transmission and automatic FCS field generation z Reception of ACK frame (if an ACK was requested) z Automatic retry of transmissions if ACK was expected but not received or accepted z Interrupt signaling with transaction status Automatic FCS check and generation, refer to "Frame Check Sequence (FCS)" on page 961, is used by the RX_AACK and TX_ARET modes. In RX_AACK mode, an automatic FCS check is always performed for incoming frames. In TX_ARET mode, an ACK which is received within the time required by IEEE 802.15.4 is automatically accepted if the FCS is valid and the ACK sequence number must match the sequence number of the previously transmitted frame. Dependent on the value of the frame pending subfield in the received acknowledgement frame received, the transaction status is set, see register bits TRAC_STATUS (register 0x02, TRX_STATE), "Register Description" on page 933. An AT86RF233 state diagram, including the Extended Operating Mode states, is shown in Figure 36-9. Orange marked states represent the Basic Operating Mode; blue marked states represent the Extended Operating Mode. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 915 Figure 36-9. Extended Operating Mode State Diagram P_ON SLEEP (Power-on after VDD) (Sleep State) P EE SL /RST = H N RX N X_ O FF _O 5 4 TR FF (Rx Listen State) 11 RX_ON PLL_ON 10 SLP_TR = H or TX_START L_ 14 FORCE_PLL_ON (all states except SLEEP or DEEP_SLEEP or P_ON) TR _A RE T_ ON X_ OF F From / To TRX_OFF TX PLL_ON TX_ARET_ON PL CK RX _A A ON T_ RE _A _O N TX RX_AACK_ON N _O RX_ON BUSY_TX (Transmit State) 9 RX_AACK_ON RX_AACK_ON Transaction Finished Frame End (PLL State) ON PLL_ON RX F OF X_ ON TR K_ AC _A RX SHR Detected BUSY_RX_AACK RESET (all states except P_ON) O 8 From / To TRX_OFF /RST = L O L_ PL 7 RX_ON Frame End (from all states) L XOSCRF =ON Pull=OFF SHR Detected BUSY_RX R= P_T SL 13 (Clock State) X_ TR 6 FF TRX_OFF 12 FORCE_TRX_OFF (all states except SLEEP or DEEP_SLEEP) 18 P_ F (Sleep State) XOSCRF =OFF Pull=ON 17 PR EP _D OF TR X_ O _TR SLP X_ DEEP_SLEEP 19 16 3 EE H =L 2 TR XOSCRF =ON Pull=OFF = _TR SLP 15 SLP_TR=H (Prepare Sleep State) XOSCRF =OFF Pull=OFF XOSCRF =ON Pull=ON (Receive State) PREP_ DEEP_SLEEP SLP_TR=H or TX_START TX_ARET_ON TX_ARET_ON BUSY_TX_ARET Frame End Legend: Blue: SPI Write to Register TRX_STATE (0x02) Red: Control signals from the microcontroller Green: Event Basic Operating Mode States Extended Operating Mode States 36.2.1 State Control The Extended Operating Mode include RX_AACK and TX_ARET modes and are controlled by writing respective command to register bits TRX_CMD (register 0x02, TRX_STATE). Receive with Automatic Acknowledgement state RX_AACK_ON and Transmit with Automatic Frame Retransmission and CSMA-CA Retry state TX_ARET_ON can be Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 916 entered either from TRX_OFF or PLL_ON state as illustrated in Figure 36-9. The completion of each change state command shall always be confirmed by reading the register bits TRX_STATUS (register 0x01, TRX_STATUS). RX_AACK - Receive with Automatic Acknowledgement A state transition to RX_AACK_ON is initiated by writing the RX_AACK_ON command to the register bits TRX_CMD. On success, reading register bits TRX_STATUS (register 0x01, TRX_STATUS) returns RX_AACK_ON or BUSY_RX_AACK. The latter one is returned when a frame is being received. The RX_AACK Extended Operating Mode is left by writing a new command to the register bits TRX_CMD. If the AT86RF233 is within a frame receive or acknowledgment procedure (BUSY_RX_AACK), the state change is executed after finishing. Alternatively, the commands FORCE_TRX_OFF or FORCE_PLL_ON can be used to cancel the RX_AACK transaction and switch to TRX_OFF or PLL_ON state respectively. TX_ARET - Transmit with Automatic Frame Retransmission and CSMA-CA Retry A state transition to TX_ARET_ON is initiated by writing command TX_ARET_ON to register bits TRX_CMD (register 0x02, TRX_STATE). The radio transceiver is in the TX_ARET_ON state when register bits TRX_STATUS (register 0x01, TRX_STATUS) return TX_ARET_ON. The TX_ARET transaction (frame transmission) is actually started by a rising edge on SLP_TR or by writing the command TX_START to register bits TRX_CMD. The TX_ARET Extended Operating Mode is left by writing a new command to the register bits TRX_CMD. If the AT86RF233 is in the middle of a CSMA-CA transaction, a frame transmission or an acknowledgment procedure (BUSY_TX_ARET), the state change is executed after completing of the operation. Alternatively, the command FORCE_TRX_OFF or FORCE_PLL_ON can be used to instantly terminate the TX_ARET transaction and change into radio transceiver state TRX_OFF or PLL_ON, respectively. Note: A state change request from TRX_OFF to RX_AACK_ON or TX_ARET_ON internally passes through PLL_ON state to initiate the radio transceiver front end. Inserting PLL_ON state and associated delays while performing this transition are indicated in Table 36-1 on page 910. State transitions can be tracked when interrupt IRQ_0 (PLL_LOCK) is used as an indicator. 36.2.2 Configuration As the usage of the Extended Operating Mode is based on Basic Operating Mode functionality, only features beyond the basic radio transceiver functionality are described in the following sections. For details of the Basic Operating Mode, refer to "Basic Operating Mode" on page 902. When using the RX_AACK or TX_ARET modes, the following registers needs to be configured. RX_AACK configuration steps: z Set the short address, PAN-ID and IEEE address: Registers 0x20 - 0x2B z z Configure RX_AACK properties: Registers 0x2C, 0x2E z Handling of Frame Version Subfield z Handling of Pending Data Indicator z Characterization as PAN coordinator z Handling of Slotted Acknowledgement Additional Frame Filtering Properties: Registers 0x17, 0x2E z Use of Promiscuous Mode z Use of automatic ACK generation z Handling of reserved frame types The configuration of the Frame Filter is described in "Configuration" on page 952. The addresses for the address match algorithm are to be stored in the appropriate address registers. Additional control of the RX_AACK mode is done with register 0x17 (XAH_CTRL_1) and register 0x2E (CSMA_SEED_1). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 917 As long as a short address is not set, only broadcast frames and frames matching the full 64-bit IEEE address can be received. Configuration examples for different device operating modes and handling of various frame types can be found in "Description of RX_AACK Configuration Bits" on page 920. TX_ARET configuration steps: z Set register bit TX_AUTO_CRC_ON = 1: Register 0x04, TRX_CTRL_1 z z Configure CSMA-CA z MAX_FRAME_RETRIES: Register 0x2C, XAH_CTRL_0 z MAX_CSMA_RETRIES: Register 0x2C, XAH_CTRL_0 z CSMA_SEED: Registers 0x2D, 0x2E z MAX_BE, MIN_BE: Register 0x2F, CSMA_BE Configure CCA (see "Clear Channel Assessment (CCA)" on page 968) MAX_FRAME_RETRIES (register 0x2C, XAH_CTRL_0) defines the maximum number of frame retransmissions. The register bits MAX_CSMA_RETRIES (register 0x2C, XAH_CTRL_0) configure the number of CSMA-CA retries after a busy channel is detected. The register bits CSMA_SEED (registers 0x2D, 0x2E) define a random seed for the backoff-time random-number generator in the AT86RF233. The register bits MAX_BE and MIN_BE (register 0x2F, CSMA_BE) set the maximum and minimum CSMA backoff exponent (see [2]), respectively. 36.2.3 RX_AACK_ON - Receive with Automatic ACK The RX_AACK Extended Operating Mode handles reception and automatic acknowledgement of IEEE 802.15.4 compliant frames. The general functionality of the RX_AACK procedure is shown in Figure 36-10. The gray shaded area is the standard flow of an RX_AACK transaction for IEEE 802.15.4 compliant frames, refer to "Configuration of IEEE Compliant Scenarios" on page 922. All other procedures are exceptions for specific operating modes or frame formats, refer to "Configuration of non IEEE 802.15.4 Compliant Scenarios" on page 924. In RX_AACK_ON state, the Atmel AT86RF233 listens for incoming frames. After detecting a valid PHR, the radio transceiver changes into BUSY_RX_AACK state and parses the frame content of the MAC header (MHR), refer to "MAC Protocol Data Unit (MPDU)" on page 948. If the content of the MAC addressing fields of the received frame (refer to [2] IEEE 802.15.4 Section 7.2.1) matches one of the configured addresses, dependent on the addressing mode, an address match interrupt IRQ_5 (AMI) is issued, refer to "Frame Filter" on page 952. The reference address values are to be stored in registers 0x20 - 0x2B (Short address, PAN-ID and IEEE address). Frame filtering as described in "Frame Filter" on page 952 is also applied in Basic Operating Mode. However, in Basic Operating Mode, the result of frame filtering or FCS check do not affect the generation of an interrupt IRQ_3 (TRX_END). Generally, at nodes configured as a normal device or a PAN coordinator, a frame is indicated by interrupt IRQ_3 (TRX_END) if the frame passes the Frame Filter and the FCS is valid. The interrupt is issued after the completion of the frame reception. The microcontroller can then read the frame data. An exception applies if promiscuous mode is enabled, see "Configuration of IEEE Compliant Scenarios" on page 922. In this case, an interrupt IRQ_3 (TRX_END) is issued for all frames. During reception AT86RF233 parses bit[5] (ACK Request) of the frame control field of the received data or MAC command frame to check if an acknowledgement (ACK) reply is expected. If the bit is set and if the frame passes the third level of filtering, see IEEE 802.15.4-2006, Section 7.5.6.2, the radio transceiver automatically generates and transmits an ACK frame. The sequence number is copied from the received frame. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 918 The content of the frame pending subfield of the ACK response is set by register bit AACK_SET_PD (register 0x2E, CSMA_SEED_1) when the ACK frame is sent in response to a data request MAC command frame, otherwise this subfield is set to zero. By default, the acknowledgment frame is transmitted aTurnaroundTime (12 symbol periods; see [2] IEEE 802.15.4-2006, Section 6.4.1) after the reception of the last symbol of a data or MAC command frame. Optionally, for non-compliant networks, this delay can be reduced to two symbols by register bit AACK_ACK_TIME (register 0x17, XAH_CTRL_1). If the register bit AACK_DIS_ACK (register 0x17, CSMA_SEED_1) is set, no acknowledgement frame is sent even if an acknowledgment frame is requested. This is useful for operating the MAC hardware accelerator in promiscuous mode, see "Configuration of IEEE Compliant Scenarios" on page 922. For slotted operation, the start of the transmission of acknowledgement frames is controlled by SLP_TR, refer to "RX_AACK Slotted Operation - Slotted Acknowledgement" on page 926. The status of the RX_AACK operation is indicated by register bits TRAC_STATUS (register 0x02, TRAC_STATUS), see "Register Description" on page 933. During the operations described above, the AT86RF233 remains in BUSY_RX_AACK state. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 919 Figure 36-10.Flow Diagram of RX_AACK TRX_STATE = RX_AACK_ON N SHR detected Y TRX_STATE = BUSY_RX_AACK Generate IRQ_2 (RX_START) Scanning MHR (see Note 1) Y Reserved Frames N Frame Filtering Note 1: Frame Filtering, Promiscuous Mode and Reserved Frames: - A radio transceiver in Promiscuous Mode, or configured to receive Reserved Frames handles received frames passing the third level of filtering - For details refer to the description of Promiscuous Mode and Reserved Frame Types Promiscuous Mode Frame reception Generate IRQ_5 (AMI) N AACK_PROM_MODE == 1 Frame reception Y N FCS valid N (see Note 2) Note 2: FCS check is omitted for Promiscous Mode FCF[2:0] >3 Y Y Generate IRQ_3 (TRX_END) N N AACK_UPLD_RES_FT == 1 ACK requested (see Note 3) Note 3: Additional conditions: - ACK requested & - AACK_DIS_ACK==0 & - frame_version<=AACK_FVN_MODE Y Y N FCS valid N Slotted Operation == 0 Y Y Generate IRQ_3 (TRX_END) Generate IRQ_3 (TRX_END) N AACK_ACK_TIME == 0 Y Wait 2 symbol periods SLP_TR rising edge Wait 12 symbol periods Wait 2 symbol periods N Y Transmit ACK TRX_STATE = RX_AACK_ON 36.2.3.1 Description of RX_AACK Configuration Bits Overview RX_AACK configuration as described below shall be done prior to switching the AT86RF233 into state RX_AACK_ON, refer to "State Control" on page 916. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 920 Table 36-5 summarizes all register bits which affect the behavior of an RX_AACK transaction. For frame filtering it is further required to setup address registers to match the expected address. A graphical representation of various operating modes is illustrated in Figure 36-10. Table 36-5. Overview of RX_AACK Configuration Bits Register Address Register Bits Register Name Description 0x20,0x21 SHORT_ADDR_0/1 Setup Frame Filter, see "Configuration" on page 952. 0x22,0x23 PAN_ID_0/1 0x24 IEEE_ADDR_0 ... ... 0x2B IEEE_ADDR_7 0x0C 7 RX_SAFE_MODE Dynamic frame buffer protection, see "Dynamic Frame Buffer Protection" on page 1032. 0x17 1 AACK_PROM_MODE Support promiscuous mode. 0x17 2 AACK_ACK_TIME Change auto acknowledge start time. 0x17 4 AACK_UPLD_RES_FT Enable reserved frame type reception, needed to receive nonstandard compliant frames, see "Configuration of non IEEE 802.15.4 Compliant Scenarios" on page 924. 0x17 5 AACK_FLTR_RES_FT Filter reserved frame types like data frame type, needed for filtering of non-standard compliant frames, see "Configuration of non IEEE 802.15.4 Compliant Scenarios" on page 924. 0x2C 0 SLOTTED_OPERATIO N If set, acknowledgment transmission has to be triggered by SLP_TR, see "RX_AACK Slotted Operation - Slotted Acknowledgement" on page 926. 0x2E 3 AACK_I_AM_COORD If set, the device is a PAN coordinator, that is responds to a null address, see "Configuration of IEEE Compliant Scenarios" on page 922. 0x2E 4 AACK_DIS_ACK Disable generation of acknowledgment. 0x2E 5 AACK_SET_PD Set frame pending subfield in Frame Control Field (FCF), refer to "Frame Control Field (FCF)" on page 948. 0x2E 7:6 AACK_FVN_MODE Controls the ACK behavior, depending on FCF frame version number. The usage of the RX_AACK configuration bits for various operating modes of a node is explained in the following sections. Configuration bits not mentioned in the following two sections should be set to their reset values according to Table 41-2 on page 1054. All registers mentioned in Table 36-5 are described in "Register Summary" on page 932. The general behavior of the "AT86RF233 Extended Feature Set" on page 1005, settings: z SFD_VALUE (alternative SFD value) z ANT_DIV (Antenna Diversity) z RX_PDT_LEVEL (blocking frame reception of lower power signals) z RPC (Reduced Power Consumption) are completely independent from RX_AACK mode and can be arbitrarily combined. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 921 36.2.3.2 Configuration of IEEE Compliant Scenarios Device not operating as a PAN Coordinator Table 36-6 shows a typical Atmel AT86RF233 RX_AACK configuration of an IEEE 802.15.4 device operating as a normal device, rather than a PAN coordinator or router. Table 36-6. Configuration of IEEE 802.15.4 Devices Register Address Register Bits Register Name 0x20,0x21 SHORT_ADDR_0/1 0x22,0x23 PAN_ID_0/1 0x24 IEEE_ADDR_0 ... ... 0x2B IEEE_ADDR_7 0x0C 7 RX_SAFE_MODE Description Setup Frame Filter, see "Configuration" on page 952. 0: Disable frame protection. 1: Enable frame protection. 0: Slotted acknowledgment transmissions are not to be used. 0x2C 0 SLOTTED_OPERATION 1: Slotted acknowledgment transmissions are to be used, see "RX_AACK Slotted Operation - Slotted Acknowledgement" on page 926. Controls the ACK behavior, depending on FCF frame version number. b00: Acknowledges only frames with version number 0, that is according to IEEE 802.15.4-2003 frames. 0x2E 7:6 AACK_FVN_MODE b01: Acknowledges only frames with version number 0 or 1, that is frames according to IEEE 802.15.4-2006. b10: Acknowledges only frames with version number 0 or 1 or 2. b11: Acknowledges all frames, independent of the FCF frame version number. 1. The default value of the short address is 0xFFFF. Thus, if no short address has been configured, only frames with either the broadcast address or the IEEE address are accepted by the frame filter. 2. In the IEEE 802.15.4-2003 standard the frame version subfield does not yet exist but is marked as reserved. According to this standard, reserved fields have to be set to zero. At the same time, the IEEE 802.15.4-2003 standard requires ignoring reserved bits upon reception. Thus, there is a contradiction in the standard which can be interpreted in two ways: 1. If a network should only allow access to nodes compliant to IEEE 802.15.4-2003, then AACK_FVN_MODE should be set to zero. 2. If a device should acknowledge all frames independent of its frame version, AACK_FVN_MODE should be set to three. However, this may result in conflicts with co-existing IEEE 802.15.4-2006 standard compliant networks. The same holds for PAN coordinators, see below. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 922 PAN-Coordinator Table 36-7 shows the AT86RF233 RX_AACK configuration for a PAN coordinator. Table 36-7. Configuration of a PAN Coordinator Register Address Register Bits Register Name Description 0x20,0x21 SHORT_ADDR_0/1 Setup Frame Filter, see "Configuration" on page 952. 0x22,0x23 PAN_ID_0/1 0x24 IEEE_ADDR_0 ... ... 0x2B IEEE_ADDR_7 0x0C 7 RX_SAFE_MODE 0: Disable frame protection. 1: Enable frame protection. 0: Slotted acknowledgment transmissions are not to be used. 0x2C 0 SLOTTED_OPERATION 1: Slotted acknowledgment transmissions are to be used, see "RX_AACK Slotted Operation - Slotted Acknowledgement" on page 926. 0x2E 3 AACK_I_AM_COORD 1: Device is PAN coordinator. 0x2E 5 AACK_SET_PD 0: Frame pending subfield is not set in FCF. 1: Frame pending subfield is set in FCF. Controls the ACK behavior, depends on FCF frame version number. b00: Acknowledges only frames with version number 0, that is according to IEEE 802.15.4-2003 frames. 0x2E 7:6 AACK_FVN_MODE b01: Acknowledges only frames with version number 0 or 1, that is frames according to IEEE 802.15.4-2006. b10: Acknowledges only frames with version number 0 or 1 or 2. b11: Acknowledges all frames, independent of the FCF frame version number. Promiscuous Mode or Sniffer The promiscuous mode is described in IEEE 802.15.4-2006, Section 7.5.6.5. This mode is further illustrated in Figure 3610. According to IEEE 802.15.4-2006 when in promiscuous mode, the MAC sub layer shall pass received frames with correct FCS to the next higher layer and shall not process them further. This implies that received frames should never be automatically acknowledged. In order to support sniffer application and promiscuous mode, only second level filter rules as defined by IEEE 802.15.4-2006, Section 7.5.6.2, are applied to the received frame. Table 36-8 shows a typical configuration of a device operating in promiscuous mode. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 923 Table 36-8. Configuration of Promiscuous Mode Register Address Register Bits Register Name 0x20,0x21 SHORT_ADDR_0/1 0x22,0x23 PAN_ID_0/1 0x24 IEEE_ADDR_0 ... ... 0x2B IEEE_ADDR_7 Description Each address shall be set: 0x00. 0x17 1 AACK_PROM_MODE 1: Enable promiscuous mode. 0x2E 4 AACK_DIS_ACK 1: Disable generation of acknowledgment. Controls the ACK behavior, depends on FCF frame version number. b00: Acknowledges only frames with version number 0, that is according to IEEE 802.15.4-2003 frames. 0x2E 7:6 AACK_FVN_MODE b01: Acknowledges only frames with version number 0 or 1, that is frames according to IEEE 802.15.4-2006. b10: Acknowledges only frames with version number 0 or 1 or 2. b11: Acknowledges all frames, independent of the FCF frame version number. If the AT86RF233 radio transceiver is in promiscuous mode, second level of filtering according to IEEE 802.15.4-2006, Section 7.5.6.2, is applied to a received frame. However, an IRQ_3 (TRX_END) is issued even if the FCS is invalid. Thus, it is necessary to read register bit RX_CRC_VALID (register 0x06, PHY_RSSI) after IRQ_3 (TRX_END) in order to verify the reception of a frame with a valid FCS. Alternatively, bit[7] of byte RX_STATUS can be evaluated, refer to "Frame Buffer Access Mode" on page 886. If a device, operating in promiscuous mode, receives a frame with a valid FCS which further passed the third level of filtering according to IEEE 802.15.4-2006, Section 7.5.6.2, an acknowledgement (ACK) frame would be transmitted. But, according to the definition of the promiscuous mode, a received frame shall not be acknowledged, even if requested. Thus, register bit AACK_DIS_ACK (register 0x2E, CSMA_SEED_1) must be set to one to disable ACK generation. In all receive modes IRQ_5 (AMI) interrupt is issued, when the received frame matches the node's address according to the filter rules described in "Frame Filter" on page 952. Alternatively, in state RX_ON (Basic Operating Mode, refer to "Basic Operating Mode" on page 902), when a valid PHR is detected, an IRQ_2 (RX_START) is generated and the frame is received. The end of the frame reception is signalized with an IRQ_3 (TRX_END). At the same time the register bit RX_CRC_VALID (register 0x06, PHY_RSSI) is updated with the result of the FCS check (see "Frame Check Sequence (FCS)" on page 961). According to the promiscuous mode definition the register bit RX_CRC_VALID needs to be checked in order to dismiss corrupted frames. However, the RX_AACK transaction additionally enables extended functionality like automatic acknowledgement and non-destructive frame filtering. 36.2.3.3 Configuration of non IEEE 802.15.4 Compliant Scenarios Sniffer Table 36-9 shows an AT86RF233 RX_AACK configuration to setup a sniffer device. Other RX_AACK configuration bits, refer to Table 36-5, should be set to their reset values. All frames received are indicated by an IRQ_2 (RX_START) and IRQ_3 (TRX_END). After frame reception register bit RX_CRC_VALID (register 0x06, PHY_RSSI) is updated with the result of the FCS check (see "Frame Check Sequence (FCS)" on page 961). The RX_CRC_VALID bit needs to be checked in order to dismiss corrupted frames. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 924 Table 36-9. Configuration of a Sniffer Device Register Address Register Bits Register Name Description 0x17 1 AACK_PROM_MODE 1: Enable promiscuous mode. 0x2E 4 AACK_DIS_ACK 1: Disable generation of acknowledgment. This operating mode is similar to the promiscuous mode. Reception of Reserved Frames In RX_AACK mode, frames with reserved frame types (refer to Table 37-3 on page 949) can also be handled. This might be required when implementing proprietary, non-standard compliant, protocols. The reception of reserved frame types is an extension of the AT86RF233 Frame Filter, see "Frame Filter" on page 952. Received frames are either handled like data frames, or may be allowed to completely bypass the Frame Filter. The flow chart in Figure 36-10 shows the corresponding state machine. In addition to Table 36-6 or Table 36-7, the following Table 36-10 shows RX_AACK configuration registers required to setup a node to receive reserved frame types. Table 36-10. RX_AACKK Configuration to Receive Reserved Frame Types Register Address Register Bits Register Name Description 0x17 4 AACK_UPLD_RES_FT 1: Enable reserved frame type reception. 0x17 5 AACK_FLTR_RES_FT Filter reserved frame types like data frame type, see note below. 0: Disable reserved frame types filtering. 1: Enable reserved frame types filtering. There are three different options for handling reserved frame types. 1. AACK_UPLD_RES_FT = 1, AACK_FLTR_RES_FT = 0: Any non-corrupted frame with a reserved frame type is indicated by an IRQ_3 (TRX_END) interrupt. No further address filtering is applied on those frames. An IRQ_5 (AMI) interrupt is never generated and the acknowledgment subfield is ignored. 2. AACK_UPLD_RES_FT = 1, AACK_FLTR_RES_FT = 1: If AACK_FLTR_RES_FT = 1 any frame with a reserved frame type is filtered by the address filter similar to a data frame as described in the standard. This implies the generation of the IRQ_5 (AMI) interrupts upon address match. An IRQ_3 (TRX_END) interrupt is only generated if the address matched and the frame was not corrupted. An acknowledgment is only send, when the ACK request subfield was set in the received frame and an IRQ_3 (TRX_END) interrupt occurred. 3. AACK_UPLD_RES_FT = 0: Any received frame with a reserved frame type is discarded. Short Acknowledgment Frame (ACK) Start Timing Register bit AACK_ACK_TIME (register 0x17, XAH_CTRL_1), see Table 36-11 defines the delay between the end of the frame reception and the start of the transmission of an acknowledgment frame. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 925 Table 36-11. Overview of RX_AACK Configuration Bits Register Address Register Bits 0x17 2 Register Name Description AACK_ACK_TIME 0: IEEE 802.15.4 standard compliant acknowledgement timing of 12 symbol periods. In slotted acknowledgement operation mode, the acknowledgment frame transmission can be triggered two symbol periods after reception of the frame earliest. 1: Non-standard IEEE 802.15.4 reduced acknowledgment timing is set to 32s (two symbol periods). This feature can be used in all scenarios, independent of other configurations. Shorter acknowledgment timing is especially useful when using High Data Rate Modes to increase battery lifetime and to improve the overall data throughput; refer to "High Data Rate Modes" on page 1013. 36.2.3.4 RX_AACK Slotted Operation - Slotted Acknowledgement In networks using slotted operation the start of the acknowledgment frame, and thus the exact timing, must be provided by the microcontroller. Exact timing requirements for the transmission of acknowledgments in beacon-enabled networks are explained in IEEE 802.15.4-2006, Section 7.5.6.4.2. In conjunction with the microcontroller the Atmel AT86RF233 supports slotted acknowledgement operation. This mode is invoked by setting register bit SLOTTED_OPERATION (register 0x2C, XAH_CTRL_0) to one. If an acknowledgment (ACK) frame is to be transmitted in RX_AACK mode, the radio transceiver expects a rising edge on SLP_TR to actually start the transmission. During this waiting period, the transceiver reports SUCCESS_WAIT_FOR_ACK through register bits TRAC_STATUS (register 0x02, TRX_STATE), see Figure 36-10. The minimum delay between the occurrence of interrupt IRQ_3 (TRX_END) and pin start of the ACK frame in slotted operation is two symbol periods. Figure 36-11 illustrates the timing of an RX_AACK transaction in slotted operation. The acknowledgement frame is ready to transmit three symbol times after the reception of the last symbol of a data or MAC command frame indicated by IRQ_3 (TRX_END). The transmission of the acknowledgement frame is initiated by the microcontroller with the rising edge of SLP_TR and starts tTR10 = 16s later. The interrupt latency tIRQ is specified in "Digital Interface Timing Characteristics" on page 1101. Figure 36-11.Timing Example of an RX_AACK Transaction for Slotted Operation Frame Type TRX_STATE RX/TX IRQ Typ. Processing Delay 512 SFD 704 Data Frame (Length = 10, ACK=1) 1026 time [s] Frame on Air 64 ACK Frame RX_AACK_ON BUSY_RX_AACK RX_AACK_ON RX TX TX RX RX/TX 0 TRX_END tIRQ ACK transmission initated by microcontroller 32 s (2 symbols) SLP_TR waiting period signalled by register bits TRAC_STATUS SLP_TR tTR10 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 926 36.2.3.5 RX_AACK Mode Timing A timing example of an RX_AACK transaction is shown in Figure 36-12. In this example a data frame of length 10 with an ACK request is received. The AT86RF233 changes to state BUSY_RX_AACK after SFD detection. The completion of the frame reception is indicated by an IRQ_3 (TRX_END) interrupt. The interrupts IRQ_2 (RX_START) and IRQ_5 (AMI) are disabled in this example. The ACK frame is automatically transmitted after aTurnaroundTime (12 symbols), assuming default acknowledgment frame start timing. The interrupt latency tIRQ is specified in "Digital Interface Timing Characteristics" on page 1101. Figure 36-12.Timing Example of an RX_AACK Transaction TRX_STATE SFD 704 Data Frame (Length = 10, ACK=1) 1088 time [s] Frame on Air Frame Type RX/TX 512 64 ACK Frame RX_AACK_ON BUSY_RX_AACK RX RX_AACK_ON TX IRQ RX TRX_END Typ. Processing Delay RX/TX 0 tIRQ 192 s (12 symbols) Note: If register bit AACK_ACK_TIME (register 0x17, XAH_CTRL_1) is set, an acknowledgment frame is sent already two symbol times after the reception of the last symbol of a data or MAC command frame. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 927 36.2.4 TX_ARET_ON - Transmit with Automatic Frame Retransmission and CSMA-CA Retry Figure 36-13.Flow Diagram of TX_ARET TRX_STATE = TX_ARET_ON frame_rctr = 0 N Start TX Y TRX_STATE = BUSY_TX_ARET TRAC_STATUS = INVALID (see Note 1) N Note 1: If MAX_CSMA_RETRIES = 7 no retry is performed MAX_CSMA_RETRIES <7 Y csma_rctr = 0 Random Back-Off csma_rctr = csma_rctr + 1 CCA N CCA Result Failure csma_rctr > MAX_CSMA_RETRIES Y Success Transmit Frame frame_rctr = frame_rctr + 1 ACK requested N Y N Receive ACK until timeout Y ACK valid Y N N frame_rctr > MAX_FRAME_RETRIES Y TRAC_STATUS = NO_ACK Data Pending N Y TRAC_STATUS = SUCCESS_DATA_PENDING TRAC_STATUS = SUCCESS TRAC_STATUS = CHANNEL_ACCESS_FAILURE Issue IRQ_3 (TRX_END) interrupt TRX_STATE = TX_ARET_ON Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 928 36.2.4.1 Overview The implementation of TX_ARET algorithm is shown in Figure 36-13. The TX_ARET Extended Operating Mode supports the frame transmission process as defined by IEEE 802.15.4-2006. It is invoked as described in "State Control" on page 916 by writing TX_ARET_ON to register subfield TRX_CMD (register 0x02, TRX_STATE). If a transmission is initiated in TX_ARET mode, the AT86RF233 executes the CSMA-CA algorithm as defined by [2]IEEE 802.15.4-2006, Section 7.5.1.4. If the CCA reports IDLE, the frame is transmitted from the Frame Buffer. If an acknowledgement frame is requested, the radio transceiver checks for an ACK reply automatically. The CSMA-CA based transmission process is repeated until a valid acknowledgement is received or the number of frame retransmissions MAX_FRAME_RETRIES (register 0x2C, XAH_CTRL_0) is exceeded. The completion of the TX_ARET transaction is indicated by the IRQ_3 (TRX_END) interrupt, see "Interrupt Handling" on page 931. 36.2.4.2 Description Prior to invoking AT86RF233 TX_ARET mode, the basic configuration steps as described in "Configuration" on page 917 shall be executed. It is further recommended to write the PSDU transmit data to the Frame Buffer in advance. The transmit start event may either come from a rising edge on SLP_TR, refer to "Sleep/Wake-up and Transmit Signal (SLP_TR)" on page 894, or by writing a TX_START command to register bits TRX_CMD (register 0x02, TRX_STATE). If the CSMA-CA detects a busy channel, it is retried as specified by the register bits MAX_CSMA_RETRIES (register 0x2C, XAH_CTRL_0). In case that CSMA-CA does not detect a clear channel after MAX_CSMA_RETRIES, it aborts the TX_ARET transaction, issues interrupt IRQ_3 (TRX_END), and sets the value of the register bits TRAC_STATUS to CHANNEL_ACCESS_FAILURE. During transmission of a frame the radio transceiver parses bit[5] (ACK Request) of the MAC header (MHR) frame control field of the PSDU data (PSDU octet #1) to be transmitted to check if an ACK reply is expected. If no ACK is expected, the radio transceiver issues IRQ_3 (TRX_END) directly after the frame transmission has been completed. The register bits TRAC_STATUS (register 0x02, TRX_STATE) are set to SUCCESS. If an ACK is expected, after transmission the radio transceiver automatically switches to receive mode waiting for a valid ACK reply (that is matching sequence number and correct FCS). After receiving a valid ACK frame, the "Frame Pending" subfield of this frame is parsed and the status register bits TRAC_STATUS are updated to SUCCESS or SUCCESS_DATA_PENDING accordingly, refer to Table 36-12. At the same time, the entire TX_ARET transaction is terminated and interrupt IRQ_3 (TRX_END) is issued. If no valid ACK is received or after timeout of 54 symbol periods (864s), the radio transceiver retries the entire transaction (CSMA-CA based frame transmission) until the maximum number of frame retransmissions is exceeded, see register bits MAX_FRAME_RETRIES (register 0x2C, XAH_CTRL_0). In that case, the TRAC_STATUS is set to NO_ACK, the TX_ARET transaction is terminated, and interrupt IRQ_3 (TRX_END) is issued. The current CSMA-CA and frame retransmission counter values of an ongoing TX_ARET transaction can be retrieved by the register bits ARET_FRAME_RETRIES and ARET_CSMA_RETRIES (register 0x19, XAH_CTRL_2). Note: 1. The acknowledgment receive procedure does not overwrite the Frame Buffer content. Transmit data in the Frame Buffer is not modified during the entire TX_ARET transaction. Received frames, other than the expected ACK frame, are discarded automatically. Additionally to the RX Frame Time stamping via DIG2, a TX Frame Time stamping within TX_ARET mode can be activated, if the register bits IRQ_2_EXT_EN (register 0x04, TRX_CTRL_1) and ARET_TX_TS_EN (register 0x17, XAH_CTRL_1) are set to one, see "RX and TX Frame Time Stamping (TX_ARET)" on page 1027. After that, the microcontroller may read the value of the register bits TRAC_STATUS (register 0x02, TRX_STATE) to verify whether the transaction was successful or not. The register bits are set according to the following cases, additional exit codes are described in "Register Summary" on page 932. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 929 Table 36-12 summarizes the Extended Operating Mode result codes in register subfield TRAC_STATUS (register 0x02, TRX_STATE) with respect to the TX_ARET transaction. Values are meaningful after an interrupt until the next frame transmit. Table 36-12. Interpretation of TRAC_STATUS Register Bits Value Name Description 0 SUCCESS The transaction was responded to by a valid ACK, or, if no ACK is requested, after a successful frame transmission. 1 SUCCESS_DATA_PENDING Equivalent to SUCCESS and indicating that the "Frame Pending" bit (see "Frame Control Field (FCF)" on page 948) of the received acknowledgment frame was set. 3 CHANNEL_ACCESS_FAILURE Channel is still busy after attempting MAX_CSMA_RETRIES of CSMA-CA. 5 NO_ACK No acknowledgement frames were received during all retry attempts. 7 INVALID Transaction not yet finished. A value of MAX_CSMA_RETRIES = 7 initiates an immediate TX_ARET transaction without performing CSMA-CA. This can be used for example to transmit indirect data to a device. Further the value MAX_FRAME_RETRIES is ignored and the TX_ARET transaction is performed only once. A timing example of a TX_ARET transaction is shown in Figure 36-14. Figure 36-14.Timing Example of a TX_ARET Transaction FrameType TRX_STATE 672 128 x Data Frame (Length = 10, ACK=1) TX_ARET_ON RX/TX ACK Frame BUSY_TX_ARET TX_ARET_ON RX TX RX/TX CSMA-CA time [s] x+352 Frame on Air 0 SLP_TR IRQ TRX_END Typ. Processing Delay Notes: 1. 2. tCSMA-CA tTR10 tTR11 tIRQ tCSMA-CA defines the random CSMA-CA backoff time. Timing figure tTR10 and tTR11 refer to Table 36-1 on page 910. Here an example data frame of length 10 with an ACK request is transmitted. After that, the AT86RF233 switches to receive mode and expects an acknowledgement response. During the whole transaction including frame transmit, wait for ACK and ACK receive the radio transceiver status register bits TRX_STATUS (register 0x01, TRX_STATUS) signals BUSY_TX_ARET. A successful reception of the acknowledgment frame is indicated by triggering of IRQ_3 (TRX_END). The status register bits TRX_STATUS (register 0x01, TRX_STATUS) changes back to TX_ARET_ON state. When the frame pending subfield of the received ACK frame is set to one (more data is to follow) register bits TRAC_STATUS (register 0x02, TRX_STATE) are set either to SUCCESS_DATA_PENDING status instead of SUCCESS status. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 930 36.2.5 Interrupt Handling The AT86RF233 interrupt handling in the Extended Operating Mode is similar to the Basic Operating Mode, refer to "Interrupt Handling" on page 906. Interrupts can be enabled by setting the appropriate bit in register 0x0E (IRQ_MASK). For RX_AACK and TX_ARET modes the following interrupts inform about the status of a frame reception and transmission: Table 36-13. Interrupt Handling in Extended Operating Mode Mode Interrupt Description IRQ_2 (RX_START) Indicates a PHR reception IRQ_5 (AMI) Issued at address match RX_AACK Signals completion of RX_AACK transaction if successful IRQ_3 (TRX_END) A received frame must pass the address filter The FCS is valid TX_ARET IRQ_3 (TRX_END) Signals completion of TX_ARET transaction RX_AACK / TX_ARET IRQ_0 (PLL_LOCK) Entering RX_AACK_ON or TX_ARET_ON state from TRX_OFF state, the PLL_LOCK interrupt signals that the transaction can be started 36.2.5.1 RX_AACK For support of the RX_AACK functionality, it is recommended to enable IRQ_3 (TRX_END). This interrupt is issued only if frames pass the frame filtering, refer to "Frame Filter" on page 952, and have a valid FCS to reflect data validity. This functionality differs in Basic Operating Mode, refer to "Interrupt Handling" on page 906. The usage of other interrupts is optional. On reception of a valid PHR an IRQ_2 (RX_START) is issued. IRQ_5 (AMI) indicates address match, refer to filter rules in "Frame Filter" on page 952, and the completion of a frame reception with a valid FCS is indicated by interrupt IRQ_3 (TRX_END). Thus, it can happen that an IRQ_2 (RX_START) and/or IRQ_5 (AMI) are issued, but the IRQ_3 (TRX_END) interrupt is never triggered when a frame does not pass the FCS computation check. 36.2.5.2 TX_ARET The IRQ_3 (TRX_END) interrupt is always generated after completing an TX_ARET transaction. Subsequently the transaction status can be read from register bits TRAC_STATUS (register 0x02, TRX_STATE). Several interrupts are automatically suppressed by the radio transceiver during TX_ARET transaction. In contrast to "Clear Channel Assessment (CCA)" on page 968, the CCA algorithm (part of CSMA-CA) does not generate interrupt IRQ_4 (CCA_ED_DONE). Furthermore, the interrupts IRQ_2 (RX_START) and/or IRQ_5 (AMI) are not generated during the TX_ARET acknowledgment receive process. All other interrupts as described in "Interrupt Logic" on page 896, are also available in Extended Operating Mode. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 931 36.2.6 Register Summary The following AT86RF233 registers are to be configured to control the Extended Operating Mode: Table 36-14. Register Summary Reg. Addr. Register Name Description 0x01 TRX_STATUS Radio transceiver status, CCA result 0x02 TRX_STATE Radio transceiver state control, TX_ARET status 0x04 TRX_CTRL_1 TX_AUTO_CRC_ON 0x08 PHY_CC_CCA CCA mode control, see "Register Description" on page 970 0x09 CCA_THRES CCA ED threshold settings, see "Register Description" on page 970 0x17 XAH_CTRL_1 TX_ARET and RX_AACK control 0x19 XAH_CTRL_2 TX_ARET control Frame Filter configuration Short address, PAN ID, and IEEE address 0x20 - 0x2B See "Register Description" on page 954 and "Register Description - Address Registers" on page 957 0x2C XAH_CTRL_0 TX_ARET control, retries value control 0x2D CSMA_SEED_0 CSMA-CA seed value 0x2E CSMA_SEED_1 CSMA-CA seed value, RX_AACK control 0x2F CSMA_BE CSMA-CA backoff exponent control Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 932 36.2.7 Register Description 36.2.7.1 TRX_STATUS Name: TRX_STATUS Offset: 0x01 Reset: 0x00, 0x08 Property: - The read-only register TRX_STATUS signals the present state of the radio transceiver as well as the status of a CCA operation. Bit 7 6 CCA_DONE CCA_STATUS Access R R R R R Reset 0 0 0 0 0 0x01 5 4 3 2 1 0 R R R 0 0 0 TRX_STATUS Bit 4:0 - TRX_STATUS The register bits TRX_STATUS signal the current radio transceiver status. z Table 36-15. TRX_STATUS Value Description 0x00 P_ON 0x01 BUSY_RX 0x02 BUSY_TX 0x06 RX_ON 0x08 TRX_OFF (CLK Mode) 0x09 PLL_ON (TX_ON) 0x0F(1) SLEEP 0x10 PREP_DEEP_SLEEP (2) BUSY_RX_AACK 0x12(2) BUSY_TX_ARET 0x16(2) RX_AACK_ON 0x19(2) TX_ARET_ON 0x11 0x1F (3) STATE_TRANSITION_IN_PROGRESS All other values are reserved Notes: 1. In SLEEP or DEEP_SLEEP state register not accessible. 2. Extended Operating Mode only. 3. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS state. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 933 A read access to TRX_STATUS register signals the current radio transceiver state status. A state change is initiated by writing a state transition command to register bits TRX_CMD (register 0x02, TRX_STATE). Alternatively, some state transitions can be initiated by the rising edge of SLP_TR in the appropriate state. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 934 36.2.7.2 TRX_STATE Name: TRX_STATE Offset: 0x02 Reset: 0x00 Property: - The radio transceiver states are advanced via register TRX_STATE by writing a command word into register bits TRX_CMD. The read-only register bits TRAC_STATUS indicate the status or result of an Extended Operating Mode transaction. Bit 7 6 5 4 3 TRAC_STATUS 0x02 2 1 0 TRX_CMD Access R R R R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bit 7:5 - TRAC_STATUS Table 36-16. TRAC_STATUS Value Description RX_AACK TX_ARET 0x0(1) SUCCESS X X 0x1 SUCCESS_DATA_PENDING 0x2 SUCCESS_WAIT_FOR_ACK 0x3 CHANNEL_ACCESS_FAILURE X 0x5 NO_ACK X 0x7(1) INVALID X X X X All other values are reserved Note: 1. Even though the reset value for register bits TRAC_STATUS is zero, the RX_AACK and TX_ARET procedures set the register bits to TRAC_STATUS = 7 (INVALID) when they are started. The status of the RX_AACK and TX_ARET procedure is indicated by register bits TRAC_STATUS. Values are meaningful after an interrupt until the next frame transmit. Details of the algorithm and a description of the status information are given in "RX_AACK_ON - Receive with Automatic ACK" on page 918 and "TX_ARET_ON - Transmit with Automatic Frame Retransmission and CSMA-CA Retry" on page 928. RX_AACK SUCCESS_WAIT_FOR_ACK: Indicates an ACK frame is about to be sent in RX_AACK slotted acknowledgement. Slotted acknowledgement operation must be enabled with register bit SLOTTED_OPERATION (register 0x2C, XAH_XTRL_0). The microcontroller must pulse SLP_TR at the next backoff slot boundary in order to initiate a transmission of the ACK frame. For details refer to [2] IEEE 802.15.4-2006, Section 7.5.6.4.2. TX_ARET SUCCESS_DATA_PENDING: Indicates a successful reception of an ACK frame with frame pending bit set to one. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 935 z Bit 4:0 - TRX_CMD A write access to register bits TRX_CMD initiate a radio transceiver state transition to the new state Table 36-17. TRX_CMD Value Description 0x00(1) NOP 0x02(2) TX_START 0x03 FORCE_TRX_OFF 0x04 (3) FORCE_PLL_ON 0x06 RX_ON 0x08 TRX_OFF (CLK Mode) 0x09 PLL_ON (TX_ON) 0x10 PREP_DEEP_SLEEP 0x16(4) RX_AACK_ON 0x19(4) TX_ARET_ON All other values are reserved Notes: 1. TRX_CMD = "0" after power on reset (POR). 2. The frame transmission starts one symbol after TX_START command. 3. FORCE_PLL_ON is not valid for states P_ON, SLEEP, DEEP_SLEEP, and RESET, as well as STATE_TRANSITION_IN_PROGRESS towards these states. 4. Extended Operating Mode only. A successful state transition shall be confirmed by reading register bits TRX_STATUS (register 0x01, TRX_STATUS). The register bits TRX_CMD are used for Basic and Extended Operating Modes, refer to "Basic Operating Mode" on page 902. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 936 36.2.7.3 TRX_CTRL_1 Name: TRX_CTRL_1 Offset: 0x04 Reset: 0x22 Property: - The TRX_CTRL_1 register is a multi-purpose register to control various operating modes and settings of the radio transceiver. Bit 0x04 7 6 5 4 PA_EXT_EN IRQ_2_EXT_ EN TX_AUTO_ CRC_ON RX_BL_ CTRL R/W R/W R/W R/W R/W 0 0 1 0 0 Access Reset z 3 2 1 0 IRQ_MASK_ MODE IRQ_ POLARITY R/W R/W R/W 0 1 0 SPI_CMD_MODE Bit 5 - TX_AUTO_CRC_ON The register bit TX_AUTO_CRC_ON controls the automatic FCS generation for transmit operations. . Table 36-18. TX_AUTO_CRC_ON Value Description 0x0 Automatic FCS generation is disabled 0x1 Automatic FCS generation is enabled Note: 1. The TX_AUTO_CRC_ON function can be used within Basic and Extended Operating Modes. For further details refer to "Frame Check Sequence (FCS)" on page 961. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 937 36.2.7.4 XAH_CTRL_1 Name: XAH_CTRL_1 Offset: 0x17 Reset: 0x00 Property: - The XAH_CTRL_1 register is a multi-purpose controls register for Extended Operating Mode. Bit 7 6 ARET_TX_T S_EN 0x17 Access 4 AACK_ FLTR_ RES_FT AACK_ UPLD_RES_ FT 3 2 1 0 AACK_ ACK_TIME AACK_ PROM_ MODE AACK_ SPC_EN R/W R/W R/W R/W R R/W R/W R/W 0 0 0 0 0 0 0 0 Reset z 5 Bit 7 - ARET_TX_TS_EN If register bit ARET_TX_TS_EN = 1, then any frame transmission within TX_ARET mode is signaled via DIG2. Table 36-19. ARET_TX_TS_EN Value Description 0x0 TX_ARET time stamping via DIG2 is disabled 0x1(1) TX_ARET time stamping via DIG2 is enabled Note: z 1. It is necessary to set register bit IRQ_2_EXT_EN (register 0x04, TRX_CTRL_1). Bit 5 - AACK_FLTR_RES_FT Filter reserved frame types like data frame type. The register bit AACK_FLTR_RES_FT shall only be set if register bit AACK_UPLD_RES_FT = 1. Table 36-20. AACK_FLTR_RES_FT Value Description 0x0(1) Filtering reserved frame types is disabled 0x1(2) Filtering reserved frame types is enabled Notes: 1. 2. If AACK_FLTR_RES_FT = 0 the received reserved frame is only checked for a valid FCS. If AACK_FLTR_RES_FT = 1 reserved frame types are filtered similar to data frames as specified in IEEE 802.15.4-2006. Reserved frame types are explained in IEEE 802.15.4 Section 7.2.1.1.1. z Bit 4 - AACK_UPLD_RES_FT Upload reserved frame types within RX_AACK mode. . Table 36-21. AACK_UPLD_RES_FT Value Description 0x0 Upload of reserved frame types is disabled 0x1(1) Upload of reserved frame types is enabled Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 938 Note: 1. If AACK_UPLD_RES_FT = 1 received frames indicated as a reserved frame are further processed. For those frames, an IRQ_3 (TRX_END) interrupt is generated if the FCS is valid. In conjunction with the configuration bit AACK_FLTR_RES_FT, these frames are handled like IEEE 802.15.4 compliant data frames during RX_AACK transaction. An IRQ_5 (AMI) interrupt is issued, if the addresses in the received frame match the node's addresses. That means, if a reserved frame passes the third level filter rules, an acknowledgement frame is generated and transmitted if it was requested by the received frame. If this is not wanted register bit AACK_DIS_ACK (register 0x2E, CSMA_SEED_1) has to be set. z Bit 2 - AACK_ACK_TIME The register bit AACK_ACK_TIME controls the acknowledgment frame response time within RX_AACK mode. Table 36-22. AACK_ACK_TIME Value Description 0x0 Acknowledgment time is 12 symbol periods (a Turnaround Time) 0x1 Acknowledgment time is two symbol periods According to [2] IEEE 802.15.4-2006, Section 7.5.6.4.2 the transmission of an acknowledgment frame shall commence 12 symbol periods (aTurnaroundTime) after the reception of the last symbol of a data or MAC command frame. This is achieved with the reset value of the register bit AACK_ACK_TIME. Alternatively, if AACK_ACK_TIME = 1 an acknowledgment frame is sent already two symbol periods after the reception of the last symbol of a data or MAC command frame. This may be applied to proprietary networks or networks using the High Data Rate Modes to increase battery lifetime and to improve the overall data throughput, refer to "High Data Rate Modes" on page 1013. z Bit 1 - AACK_PROM_MODE The register bit AACK_PROM_MODE enables the promiscuous mode, within the RX_AACK mode. . Table 36-23. AACK_PROM_MODE Value Description 0x0 Promiscuous mode is disabled 0x1 Promiscuous mode is enabled Refer to [2] IEEE 802.15.4-2006 Section 7.5.6.5. If this register bit is set, every incoming frame with a valid PHR finishes with IRQ_3 (TRX_END) interrupt even if the third level filter rules do not match or the FCS is not valid. However, register bit RX_CRC_VALID (register 0x06, PHY_RSSI) is set accordingly. In contrast to [2] IEEE 802.15.4-2006, if a frame passes the third level filter rules, an acknowledgement frame is generated and transmitted unless disabled by register bit AACK_DIS_ACK (register 0x2E, CSMA_SEED_1), or use Basic Operating Mode instead. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 939 36.2.7.5 XAH_CTRL_2 Name: XAH_CTRL_2 Offset: 0x19 Reset: 0x00 Property: - The read-only register XAH_CTRL_2 retrieves the current counter values for Extended Operating Mode. Bit 7 6 5 4 3 ARET_FRAME_RETRIES 0x19 2 1 0 ARET_CSMA_RETRIES Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bit 7:4 - ARET_FRAME_RETRIES Retrieves current frame retry counter value. Table 36-24. ARET_FRAME_RETRIES Value Description 0x0 Minimum possible frame retry counter value 0xF Maximum possible frame retry counter value Note: z 1. A new CCA_BACKOFF cycle or new frame transmit cycle changed these value. Bit 3:1 - ARET_CSMA_RETRIES Retrieves current CSMA-CA retry counter value. . Table 36-25. ARET_CSMA_RETRIES Value Description 0x0 Minimum possible CSMA-CA retry counter value 0x5 Maximum possible CSMA-CA retry counter value Note: 1. A new CCA_BACKOFF cycle or new frame transmit cycle changed these value. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 940 36.2.7.6 XAH_CTRL_0 Name: XAH_CTRL_0 Offset: 0x2C Reset: 0x38 Property: - The XAH_CTRL_0 register is a control register for Extended Operating Mode. Bit 7 6 5 4 3 MAX_FRAME_RETRIES 0x2C Access Reset 2 1 MAX_CSMA_RETRIES 0 SLOTTED_OPERATION R/W R/W R/W R/W R/W R/W R/W R/W 0 0 1 1 1 0 0 0 Bit 7:4 - MAX_FRAME_RETRIES Number of retransmission attempts in TX_ARET mode before the transaction gets cancelled. z . Table 36-26. MAX_FRAME_RETRIES Value Description The setting of MAX_FRAME_RETRIES in TX_ARET mode specifies the number of attempts to retransmit a frame, when it was not acknowledged by the recipient, before the transaction gets cancelled. Valid values are [0x7, 0x6, ..., 0x0]. 0x3 z Bit 3:1 - MAX_CSMA_RETRIES Number of retries in TX_ARET mode to repeat the CSMA-CA procedure before the transaction gets cancelled. . Table 36-27. MAX_CSMA_RETRIES Value Description 0x0(1) No retries 0x1(1) One retry 0x2(1) Two retries 0x3(1) Three retries 0x4(1) Four retries 0x5(1) Five retries 0x6 Reserved 0x7(2) Immediate frame transmission without performing CSMA-CA Notes: 1. 2. z MAX_CSMA_RETRIES specifies the number of retries in TX_ARET mode to repeat the CSMA-CA procedure before the transaction gets cancelled. According to IEEE 802.15.4 the valid range of MAX_CSMA_RETRIES is [5, 4, ..., 0]. A value of MAX_CSMA_RETRIES = 7 initiates an immediate frame transmission without performing CSMACA. No retry is performed. This may especially be required for slotted acknowledgement operation. Bit 0 - SLOTTED_OPERATION For RX_AACK mode, the register bit SLOTTED_OPERATION determines, if the transceiver will require a time base for slotted operation. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 941 . Table 36-28. SLOTTED_OPERATION Value Description 0x0 The radio transceiver operates in unslotted mode. An acknowledgment frame is automatically sent if requested. 0x1 The transmission of an acknowledgement frame has to be controlled by the microcontroller. Using RX_AACK mode in networks operating in beacon or slotted mode, refer to [2] IEEE 802.15.4-2006, Section 5.5.1, register bit SLOTTED_OPERATION indicates that acknowledgement frames are to be sent on backoff slot boundaries (slotted acknowledgement), refer to "RX_AACK Slotted Operation - Slotted Acknowledgement" on page 926. If this register bit is set the acknowledgement frame transmission has to be initiated by the microcontroller using the rising edge of SLP_TR. This waiting state is signaled in register bits TRAC_STATUS (register 0x02, TRX_STATE) with value SUCCESS_WAIT_FOR_ACK. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 942 36.2.7.7 CSMA_SEED_0 Name: CSMA_SEED_0 Offset: 0x2D Reset: 0xEA Property: - The register CSMA_SEED_0 contains the lower 8-bit of CSMA_SEED. Bit 7 6 5 4 R/W R/W R/W R/W 1 1 1 0 3 2 1 0 R/W R/W R/W R/W 1 0 1 0 CSMA_SEED_0 0x2D Access Reset z Bit 7:0 - CSMA_SEED_0 Lower 8-bit of CSMA_SEED, bits [7:0]. Used as seed for random number generation in the CSMA-CA algorithm. . Table 36-29. CSMA_SEED_0 Value Description This register contains the lower 8-bit of the CSMA_SEED, bits [7:0]. The higher 3-bit are part of register bits CSMA_SEED_1 (register 0x2E, CSMA_SEED_1). CSMA_SEED is the seed for the random number generation that determines the length of the backoff period in the CSMA-CA algorithm. 0xEA Notes: 1. 2. It is recommended to initialize register bits CSMA_SEED_0 and CSMA_SEED_1 with random values. This can be done using register bits RND_VALUE (register 0x06, PHY_RSSI), refer to "Random Number Generator" on page 1013. The content of register bits CSMA_SEED_0 and CSMA_SEED_1 initializes the TX_ARET random backoff generator after wakeup from DEEP_SLEEP state. It is recommended to re-initialize both registers after every DEEP_SLEEP state with a random value. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 943 36.2.7.8 CSMA_SEED_1 Name: CSMA_SEED_1 Offset: 0x2E Reset: 0x42 Property: - The CSMA_SEED_1 register is a control register for RX_AACK and contains a part of the CSMA_SEED for the CSMACA algorithm. Bit 7 6 5 4 3 AACK_SET_ PD AACK_DIS_ ACK AACK_I_AM_ COORD 2 1 0 CSMA_SEED_1 0x2E AACK_FVN_MODE Access R/W R/W R/W R/W R/W R/W R/W R/W 0 1 0 0 0 0 1 0 Reset z Bit 7:6 - AACK_FVN_MODE The register bits AACK_FVN_MODE control the ACK behavior dependent on FCF frame version number within RX_AACK mode. Table 36-30. AACK_FVN_MODE Value Description 0x0 Accept frames with version number 0 0x1 Accept frames with version number 0 or 1 0x2 Accept frames with version number 0 or 1 or 2 0x3 Accept frames independent of frame version number Note: 1. AACK_FVN_MODE value one indicates frames according to [2] IEEE 802.15.4-2006, a value of three indicates frames according to [1] IEEE 802.15.4-2003 standard. The frame control field of the MAC header (MHR) contains a frame version subfield. The setting of register bits AACK_FVN_MODE specifies the frame filtering behavior of the Atmel AT86RF233. According to the content of these register bits the radio transceiver passes frames with a specific frame version number, number group, or independent of the frame version number. Thus the register bits AACK_FVN_MODE defines the maximum acceptable frame version. Received frames with a higher frame version number than configured do not pass the frame filter and are not acknowledged. The frame version field of the acknowledgment frame is set to zero according to [2] IEEE 802.15.4-2006, Section 7.2.2.3.1 Acknowledgment frame MHR fields. z Bit 5 - AACK_SET_PD The content of AACK_SET_PD bit is copied into the frame pending subfield of the acknowledgment frame if the ACK is the response to a data request MAC command frame. . Table 36-31. AACK_SET_PD Value Description 0x0 Pending data bit set to zero 0x1 Pending data bit set to one Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 944 In addition, if register bits AACK_FVN_MODE (register 0x2E, CSMA_SEED_1) are configured to accept frames with a frame version other than zero or one, the content of register bit AACK_SET_PD is also copied into the frame pending subfield of the acknowledgment frame for any MAC command frame with a frame version of two or three that have the security enabled subfield set to one. This is done with the assumption that a future version of the [2] IEEE 802.15.4-2006 standard might change the length or structure of the auxiliary security header. z Bit 4 - AACK_DIS_ACK If this bit is set no acknowledgment frames are transmitted in RX_AACK Extended Operating Mode, even if requested. . Table 36-32. AACK_DIS_ACK Value Description 0x0 Acknowledgment frames are transmitted 0x1 Acknowledgment frames are not transmitted z Bit 3 - AACK_I_AM_COORD This register bit has to be set if the node is a PAN coordinator. It is used for frame filtering in RX_AACK. . Table 36-33. AACK_I_AM_COORD Value Description 0x0 PAN coordinator addressing is disabled 0x1 PAN coordinator addressing is enabled If AACK_I_AM_COORD = 1 and if only source addressing fields are included in a data or MAC command frame, the frame shall be accepted only if the device is the PAN coordinator and the source PAN identifier matches macPANId, for details refer to [2] IEEE 802.15.4-2006, Section 7.5.6.2 (third-level filter rule six). z Bit 2:0 - CSMA_SEED_1 Higher 3-bit of CSMA_SEED, bits [10:8]. Seed for random number generation in the CSMA-CA algorithm. . Table 36-34. CSMA_SEED_1 Value Description 0x2 These register bits are the higher 3-bit of the CSMA_SEED, bits [10:8]. The lower part is in register 0x2D (CSMA_SEED_0), see register CSMA_SEED_0 for details. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 945 36.2.7.9 CSMA_BE Name: CSMA_BE Offset: 0x2F Reset: 0x53 Property: - The register CSMA_BE contains the backoff exponents for the CSMA-CA algorithm. Bit 7 6 R/W R/W 0 1 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W 0 1 0 0 1 1 MAX_BE[3:0] 0x2F Access Reset Note: z 1. MIN_BE[3:0] If MIN_BE = 0 and MAX_BE = 0 the CCA backoff period is always set to zero. Bits 7:4 - MAX_BE Maximum backoff exponent in the CSMA-CA algorithm. Table 36-35. MAX_BE Value Description 0x5 Register bits MAX_BE defines the maximum backoff exponent used in the CSMA-CA algorithm to generate a pseudo random number for CCA backoff. Valid values are [0x8, 0x7, ..., 0x0]. For details refer to [2] IEEE 802.15.4-2006, Section 7.5.1.4. z Bits 3:0 - MIN_BE Minimum backoff exponent in the CSMA-CA algorithm. . Table 36-36. MIN_BE Value Description 0x3 Register bits MIN_BE defines the minimum backoff exponent used in the CSMA-CA algorithm to generate a pseudo random number for CCA backoff. Valid values are [MAX_BE, (MAX_BE - 1), ..., 0x0]. For details refer to [2] IEEE 802.15.4-2006, Section 7.5.1.4. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 946 37. AT86RF233 Functional Description 37.1 Introduction - IEEE 802.15.4-2006 Frame Format Figure 37-1 provides an overview of the physical layer (PHY) frame structure as defined by the IEEE 802.15.4-2006 standard.Figure 37-2 shows the medium access control layer (MAC) frame structure. Figure 37-1. IEEE 802.15.4 Frame Format - PHY Layer Frame Structure (PPDU) PHY Protocol Data Unit (PPDU) Preamble Sequence SFD Frame Length PHY Payload 5 octets 1 octet Maximum 127 octets Synchronization Header (SHR) (PHR) PHY Service Data Unit (PSDU) MAC Protocol Data Unit (MPDU) 37.1.1 PHY Protocol Data Unit (PPDU) 37.1.1.1 Synchronization Header (SHR) The SHR consists of a four-octet preamble field (all zero), followed by a single byte start-of-frame delimiter (SFD) which has the predefined value 0xA7. During transmission, the SHR is automatically generated by the AT86RF233, thus the Frame Buffer shall contain PHR and PSDU only, see "Frame Buffer Access Mode" on page 886. The transmission of the SHR requires 160s (10 symbols). As the SPI data rate is normally higher than the over-air data rate, this allows the microcontroller to initiate a transmission without having transferred the full frame data already. Instead it is possible to subsequently write the frame content. The fact that the SPI data rate is normally higher than over-the-air data rate, allows the microcontroller to first initiate a frame transmission and then as the SHR is transmitted write the frame data. This is to minimize frame buffer data fill overhead transmission delay. During a frame reception, the SHR is used for synchronization purposes. The matching SFD determines the beginning of the PHR and the following PSDU payload data. 37.1.1.2 PHY Header (PHR) The PHY header is a single octet following the SHR. The least significant seven bits denote the frame length of the following PSDU, while the most significant bit of that octet is reserved, and shall be set to zero for IEEE 802.15.4 compliant frames. On reception, the PHR is returned as the first octet during Frame Buffer read access. While the IEEE 802.15.4-2006 standard declares bit seven of the PHR octet as being reserved, the AT86RF233 preserves this bit upon transmission and reception so it can be used to carry additional information within proprietary networks. Nevertheless, this bit is not considered to be a part of the frame length, so only frames between one and 127 octets are possible. For IEEE 802.15.4 compliant operation bit [7] has to be masked by software. In transmit mode, the PHR needs to be supplied as the first octet during Frame Buffer write access, see "Frame Buffer Access Mode" on page 886. In receive mode, the PHR (that is frame length greater than zero) is returned as the first octet during Frame Buffer read access (see "Frame Buffer Access Mode" on page 886) and is signaled by an interrupt IRQ_2 (RX_START). 37.1.1.3 PHY Payload (PHY Service Data Unit, PSDU) The PSDU has a variable length between zero and aMaxPHYPacketSize (127, maximum PSDU size in octets). The length of the PSDU is signaled by the frame length field (PHR), refer to Table 37-1. The PSDU contains the MAC protocol data unit (MPDU), where the last two octets are used for the Frame Check Sequence (FCS), see "Frame Check Sequence (FCS)" on page 961. Received frames with a frame length field set to zero (invalid PHR) are not signaled to the microcontroller. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 947 Table 37-1 summarizes the type of payload versus the frame length value. Table 37-1. Frame Length - PHR Frame Length Value Payload 0-4 Reserved 5 MPDU (Acknowledgement) 6-8 Reserved 9 - aMaxPHYPacketSize MPDU 37.1.1.4 Timing Summary Table 37-2 shows timing information for the above mentioned frame structure depending on the selected data rate. Table 37-2. PPDU Timing PSDU Bit Rate [kb/s] PHY Mode O-QPSK (1) O-QPSK(2) Notes: 1. 2. Header Bit Rate [kb/s] Duration SHR [s] PHR [s] Max. PSDU [ms] 250 250 160 32 4.064 500 250 160 32 2.032 1000 250 160 32 1.016 2000 250 160 32 0.508 Compliant to IEEE 802.15.4-2006 [2] "High Data Rate Modes" on page 1013. 37.1.2 MAC Protocol Data Unit (MPDU) Figure 37-2 shows the frame structure of the MAC layer. Figure 37-2. IEEE 802.15.4-2006 Frame Format - MAC Layer Frame Structure (MPDU) MAC Protocol Data Unit (MPDU) Sequence Number FCF Addressing Fields MAC Payload MAC Header (MHR) Destination PAN ID 0 1 Frame Type 2 Destination Source address PAN ID 0/4/6/8/10/12/14/16/18/20 octets 3 4 5 Sec. Enabled Frame Pending ACK Request FCS MAC Service Data Unit (MSDU) 6 7 Source address 8 PAN ID Reserved Comp. Frame Control Field 2 octets 9 (MFR) Auxiliary Security Header CRC-16 0/5/6/10/14 octets 2 octets 10 11 Destination addressing mode 12 13 Frame Version 14 15 Source addressing mode 37.1.2.1 MAC Header (MHR) Fields The MAC header consists of the Frame Control Field (FCF), a sequence number, and the addressing fields (which are of variable length, and can even be empty in certain situations). 37.1.2.2 Frame Control Field (FCF) The FCF consists of 16 bits, and occupies the first two octets of the MPDU or PSDU, respectively. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 948 Figure 37-3. IEEE 802.15.4-2006 Frame Control Field (FCF) 0 1 Frame Type 2 3 4 5 6 Sec. Enabled Frame Pending ACK Request PAN ID Comp. 7 8 9 10 11 Destination addressing mode Reserved 12 13 Frame Version 14 15 Source addressing mode Frame Control Field 2 octets Bits [2:0]: describes the "Frame Type". Table 37-3 summarizes frame types defined by IEEE 802.15.4-2006 [2], Section 7.2.1.1.1. Table 37-3. Frame Control Field - Frame Type Subfield Frame Control Field Bit Assignment Description Frame Type Value b2, b1, b0 Value 000 0 Beacon 001 1 Data 010 2 Acknowledge 011 3 MAC command 100 - 111 4-7 Reserved This subfield is used for frame filtering by the third level filter rules. By default, only frame types 0 - 3 pass the third level filter rules, refer to "Frame Filter" on page 952. Automatic frame filtering by the Atmel AT86RF233 is enabled when using the RX_AACK mode, refer to "RX_AACK_ON - Receive with Automatic ACK" on page 918. However, a reserved frame (frame type value > 3) can be received if register bit AACK_UPLD_RES_FT (register 0x17, XAH_CTRL_1) is set, for details refer to "Configuration of non IEEE 802.15.4 Compliant Scenarios" on page 924. Frame filtering is also provided in Basic Operating Mode, refer to "Basic Operating Mode" on page 902. Bit 3: indicates whether security processing applies to this frame. This field is evaluated by the Frame Filter. Bit 4: is the "Frame Pending" subfield. This field can be set in an acknowledgment frame (ACK) in response to a data request MAC command frame. This bit indicates that the node, which transmitted the ACK, might have more data to send to the node receiving the ACK. Note: 1. For acknowledgment frames automatically generated by the AT86RF233, this bit is set according to the content of register bit AACK_SET_PD in register 0x2E (CSMA_SEED_1) if the received frame was a data request MAC command frame. Bit 5: forms the "Acknowledgment Request" subfield. If this bit is set within a data or MAC command frame that is not broadcast, the recipient shall acknowledge the reception of the frame within the time specified by IEEE 802.15.4 (that is within 192s for non beacon-enabled networks). The radio transceiver parses this bit during RX_AACK mode and transmits an acknowledgment frame if necessary. In TX_ARET mode this bit indicates if an acknowledgement frame is expected after transmitting a frame. If this is the case, the receiver waits for the acknowledgment frame, otherwise the TX_ARET transaction is finished. Bit 6: the "PAN ID Compression" subfield, indicates that in a frame where both the destination and source addresses are present, the PAN ID is omitted from the source addressing field. This bit is evaluated by the Frame Filter of the AT86RF233. This subfield was previously named "Intra-PAN". Bits [11:10]: the "Destination Addressing Mode" subfield describes the format of the destination address of the frame. The values of the address modes are summarized in Table 37-4, according to IEEE 802.15.4. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 949 Table 37-4. Frame Control Field - Destination and Source Addressing Mode Frame Control Field Bit Assignments Description Addressing Mode b11 b10 b15 b14 Value 00 0 PAN identifier and address fields are not present 01 1 Reserved 10 2 Address field contains a 16-bit short address 11 3 Address field contains a 64-bit extended address If the destination address mode is either two or three (that is if the destination address is present), it always consists of a 16-bit PAN-ID first, followed by either the 16-bit or 64-bit address as described by the mode. Bits [13:12]: the "Frame Version" subfield specifies the version number corresponding to the frame, see Table 37-5. These bits are reserved in IEEE 802.15.4-2003. This subfield shall be set to zero to indicate a frame compatible with IEEE 802.15.4-2003 and one to indicate an IEEE 802.15.4-2006 frame. All other subfield values shall be reserved for future use. RX_AACK register bits AACK_FVN_MODE (register 0x2E, CSMA_SEED_1) controls the behavior of frame acknowledgements. This register determines if, depending on the Frame Version Number, a frame is acknowledged or not. This is necessary for backward compatibility to IEEE 802.15.4-2003 and for future use. Even if frame version numbers two and three are reserved, it can be handled by the radio transceiver, for details refer to "Register Description" on page 933. See [2] IEEE 802.15.4-2006, Section 7.2.3, for details on frame compatibility. Table 37-5. Frame Control Field - Frame Version Subfield Frame Control Field Bit Assignment Description Frame Version b13 b12 Value 00 0 Frames are compatible with IEEE 802.15.4-2003 01 1 Frames are compatible with IEEE 802.15.4-2006 10 2 Reserved 11 3 Reserved Bits [15:14]: the "Source Addressing Mode" subfield, with similar meaning as "Destination Addressing Mode", see Table 37-4. The addressing field description bits of the FCF (Bits 0-2, 3, 6, 10-15) affect the AT86RF233 Frame Filter, see "Frame Filter" on page 952. 37.1.2.3 Frame Compatibility between IEEE 802.15.4-2003 and IEEE 802.15.4-2006 All unsecured frames according to IEEE 802.15.4-2006 are compatible with unsecured frames compliant with IEEE 802.15.4-2003 with two exceptions: a coordinator realignment command frame with the "Channel Page" field present (see [2] IEEE 802.15.4-2006, Section 7.3.8) and any frame with a MAC Payload field larger than aMaxMACSafePayloadSize octets. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 950 Compatibility for secured frames is shown in Table 37-6, which identifies the security operating modes for IEEE 802.15.4-2003 and IEEE 802.15.4-2006. Table 37-6. Frame Control Field- Security and Frame Version Frame Control Field Bit Assignment Description Security Enabled b3 Frame Version b13 b12 0 00 No security. Frames are compatible between IEEE 802.15.4-2003 and IEEE 802.15.4-2006. 0 01 No security. Frames are not compatible between IEEE 802.15.4-2003 and IEEE 802.15.4-2006. 1 00 Secured frame formatted according to IEEE 802.15.4-2003. This frame type is not supported in IEEE 802.15.4-2006. 1 01 Secured frame formatted according to IEEE 802.15.4-2006. 37.1.2.4 Sequence Number The one-octet sequence number following the FCF identifies a particular frame, so that duplicated frame transmissions can be detected. While operating in RX_AACK mode, the content of this field is copied from the frame to be acknowledged into the acknowledgment frame. 37.1.2.5 Addressing Fields The addressing fields of the MPDU are used by the AT86RF233 for address matching indication. The destination address (if present) is always first, followed by the source address (if present). Each address field consists of the PAN-ID and a device address. If both addresses are present, and the "PAN ID compression" subfield in the FCF is set to one, the source PAN-ID is omitted. Note that in addition to these general rules, IEEE 802.15.4 further restricts the valid address combinations for the individual possible MAC frame types. For example, the situation where both addresses are omitted (source addressing mode = 0 and destination addressing mode = 0) is only allowed for acknowledgment frames. The address filter in the AT86RF233 has been designed to apply to IEEE 802.15.4 compliant frames. It can be configured to handle other frame formats and exceptions. 37.1.2.6 Auxiliary Security Header Field The Auxiliary Security Header specifies information required for security processing and has a variable length. This field determines how the frame is actually protected (security level) and which keying material from the MAC security PIB is used (see [2] IEEE 802.15.4-2006, Section 7.6.1). This field shall be present only if the Security Enabled subfield b3, see "Frame Compatibility between IEEE 802.15.4-2003 and IEEE 802.15.4-2006" on page 950, is set to one. For details of its structure, see IEEE 802.15.4-2006, Section 7.6.2 Auxiliary security header. 37.1.2.7 MAC Service Data Unit (MSDU) This is the actual MAC payload. It is usually structured according to the individual frame type. A description can be found in IEEE 802.15.4-2006, Section 5.5.3.2. 37.1.2.8 MAC Footer (MFR) Fields The MAC footer consists of a two octet Frame Checksum (FCS), for details refer to "Frame Check Sequence (FCS)" on page 961. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 951 37.2 Frame Filter Frame Filtering is a procedure that evaluates whether or not a received frame matches predefined criteria, like source or destination address or frame types. A filtering procedure as described in IEEE 802.15.4-2006 Section 7.5.6.2 (Third level of filtering) is applied to the frame to accept a received frame and to generate the address match interrupt IRQ_5 (AMI). The AT86RF233 Frame Filter passes only frames that satisfy all of the following requirements/rules (quote from [2] IEEE 802.15.4-2006, Section 7.5.6.2): 1. The Frame Type subfield shall not contain a reserved frame type. 2. The Frame Version subfield shall not contain a reserved value. 3. If a destination PAN identifier is included in the frame, it shall match macPANId or shall be the broadcast PAN identifier (0xFFFF). 4. If a short destination address is included in the frame, it shall match either macShortAddress or the broadcast address (0xFFFF). Otherwise, if an extended destination address is included in the frame, it shall match aExtendedAddress. 5. If the frame type indicates that the frame is a beacon frame, the source PAN identifier shall match macPANId unless macPANId is equal to 0xFFFF, in which case the beacon frame shall be accepted regardless of the source PAN identifier. 6. If only source addressing fields are included in a data or MAC command frame, the frame shall be accepted only if the device is the PAN coordinator and the source PAN identifier matches macPANId. Moreover the AT86RF233 has two additional requirements: 7. The frame type shall indicate that the frame is not an acknowledgment (ACK) frame. 8. At least one address field must be present. Address match, indicated by interrupt IRQ_5 (AMI), is further controlled by the content of subfields of the frame control field of a received frame according to the following rule: If Destination Addressing Mode is 0/1 and Source Addressing Mode is zero (see "Frame Control Field (FCF)" on page 948), no interrupt IRQ_5 (AMI) is generated. This effectively causes all acknowledgement frames not to be announced, which would otherwise always pass the filter, regardless of whether they are intended for this device or not. For backward compatibility to IEEE 802.15.4-2003 third level filter rule two (Frame Version) can be disabled by register bits AACK_FVN_MODE (register 0x2E, CSMA_SEED_1). Frame filtering is available in Extended and Basic Operating Mode. A frame that passes the Frame Filter generates the interrupt IRQ_5 (AMI) if not masked. Notes: 1. 2. Filter rule one is affected by register bits AACK_FLTR_RES_FT and AACK_UPLD_RES_FT, "Register Description" on page 933. Filter rule two is affected by register bits AACK_FVN_MODE, Section "Register Description" on page 933. 37.2.1 Configuration The Frame Filter is configured by setting the appropriate address variables and several additional properties as described in Table 37-7. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 952 Table 37-7. Frame Filter Configuration Register Address Register Bits Register Name 0x20,0x21 SHORT_ADDR_0/1 0x22,0x23 PAN_ID_0/1 0x24 IEEE_ADDR_0 ... ... 0x2B IEEE_ADDR_7 0x17 0x17 1 4 AACK_PROM_MODE AACK_UPLD_RES_FT Description Set macShortAddress, macPANId , and aExtendedAddress as described in [2]. 0: Disable promiscuous mode. 1: Enable promiscuous mode. Enable reserved frame type reception, needed to receive nonstandard compliant frames, see "Handling of Reserved Frame Types" on page 953. 0: Disable reserved frame type reception. 1: Enable reserved frame type reception. 0x17 5 AACK_FLTR_RES_FT Filter reserved frame types like data frame type, needed for filtering of non-standard compliant frames. 0: Disable reserved frame types filtering. 1: Enable reserved frame types filtering. 0x2E 3 AACK_I_AM_COORD 0: Device is not PAN coordinator. 1: Device is PAN coordinator. Controls the ACK behavior, depends on FCF frame version number. b00: Acknowledges only frames with version number 0, that is according to IEEE 802.15.4-2003 frames. 0x2E 7:6 AACK_FVN_MODE b01: Acknowledges only frames with version number 0 or 1, that is frames according to IEEE 802.15.4-2006. b10: Acknowledges only frames with version number 0 or 1 or 2. b11: Acknowledges all frames, independent of the FCF frame version number. 37.2.2 Handling of Reserved Frame Types Reserved frame types (as described in "Configuration of non IEEE 802.15.4 Compliant Scenarios" on page 924) are treated according to bits AACK_UPLD_RES_FT and AACK_FLTR_RES_FT of register 0x17 (XAH_CTRL_1) with three options: 1. AACK_UPLD_RES_FT = 1, AACK_FLTR_RES_FT = 0: Any non-corrupted frame with a reserved frame type is indicated by an IRQ_3 (TRX_END) interrupt. No further address filtering is applied on those frames. An IRQ_5 (AMI) interrupt is never generated and the acknowledgment subfield is ignored. 2. AACK_UPLD_RES_FT = 1, AACK_FLTR_RES_FT = 1: If AACK_FLTR_RES_FT = 1 any frame with a reserved frame type is filtered by the address filter similar to a data frame as described in the standard. This implies the generation of the IRQ_5 (AMI) interrupts upon address match. An IRQ_3 (TRX_END) interrupt is only generated if the address matched and the frame was not corrupted. An acknowledgment is only send, when the ACK request subfield was set in the received frame and an IRQ_3 (TRX_END) interrupt occurred. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 953 3. AACK_UPLD_RES_FT = 0: Any received frame with a reserved frame type is discarded. 37.2.3 Register Description 37.2.3.1 XAH_CTRL_1 Name: XAH_CTRL_1 Offset: 0x17 Reset: 0x00 Property: - The XAH_CTRL_1 register is a multi-purpose controls register for Extended Operating Mode. Bit 7 6 ARET_TX_ TS_EN 0x17 Access 4 AACK_FLTR_ RES_ FT AACK_UPLD _RES_ FT 3 2 1 0 AACK_ACK _TIME AACK_PROM_ MODE AACK_ SPC_EN R/W R/W R/W R/W R R/W R/W R/W 0 0 0 0 0 0 0 0 Reset z 5 Bit 5 - AACK_FLTR_RES_FT Filter reserved frame types like data frame type. The register bit AACK_FLTR_RES_FT shall only be set if register bit AACK_UPLD_RES_FT = 1. Table 37-8. AACK_FLTR_RES_FT Value Description 0x0(1) Filtering reserved frame types is disabled 0x1(2) Filtering reserved frame types is enabled Notes: 1. 2. If AACK_FLTR_RES_FT = 0 the received reserved frame is only checked for a valid FCS. If AACK_FLTR_RES_FT = 1 reserved frame types are filtered similar to data frames as specified in IEEE 802.15.4-2006. Reserved frame types are explained in IEEE 802.15.4 Section 7.2.1.1.1. z Bit 4 - AACK_UPLD_RES_FT Upload reserved frame types within RX_AACK mode. Table 37-9. AACK_UPLD_RES_FT Value Description 0x0 Upload of reserved frame types is disabled 0x1(1) Upload of reserved frame types is enabled Note: 1. If AACK_UPLD_RES_FT = 1 received frames indicated as a reserved frame are further processed. For those frames, an IRQ_3 (TRX_END) interrupt is generated if the FCS is valid. In conjunction with the configuration bit AACK_FLTR_RES_FT, these frames are handled like IEEE 802.15.4 compliant data frames during RX_AACK transaction. An IRQ_5 (AMI) interrupt is issued, if the addresses in the received frame match the node's addresses. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 954 That means, if a reserved frame passes the third level filter rules, an acknowledgement frame is generated and transmitted if it was requested by the received frame. If this is not wanted register bit AACK_DIS_ACK (register 0x2E, CSMA_SEED_1) has to be set. z Bit 1 - AACK_PROM_MODE The register bit AACK_PROM_MODE enables the promiscuous mode, within the RX_AACK mode. Table 37-10. AACK_PROM_MODE Value Description 0x0 Promiscuous mode is disabled 0x1 Promiscuous mode is enabled Refer to [2] IEEE 802.15.4-2006 Section 7.5.6.5. If this register bit is set, every incoming frame with a valid PHR finishes with IRQ_3 (TRX_END) interrupt even if the third level filter rules do not match or the FCS is not valid. However, register bit RX_CRC_VALID (register 0x06, PHY_RSSI) is set accordingly. In contrast to IEEE 802.15.4-2006, if a frame passes the third level filter rules, an acknowledgement frame is generated and transmitted unless disabled by register bit AACK_DIS_ACK (register 0x2E, CSMA_SEED_1), or use Basic Operating Mode instead. 37.2.3.2 CSMA_SEED_1 Name: CSMA_SEED_1 Offset: 0x2E Reset: 0x42 Property: - The CSMA_SEED_1 register is a control register for RX_AACK and contains a part of the CSMA_SEED for the CSMACA algorithm. Bit 7 6 5 4 3 AACK_SET_ PD AACK_DIS_ ACK AACK_I_AM_ COORD 2 1 0 CSMA_SEED_1 0x2E AACK_FVN_MODE Access R/W R/W R/W R/W R/W R/W R/W R/W 0 1 0 0 0 0 1 0 Reset z Bit 7:6 - AACK_FVN_MODE The register bits AACK_FVN_MODE control the ACK behavior dependent on FCF frame version number within RX_AACK mode. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 955 Table 37-11. AACK_FVN_MODE Value Description 0x0 Accept frames with version number 0 0x1 Accept frames with version number 0 or 1 0x2 Accept frames with version number 0 or 1 or 2 0x3 Accept frames independent of frame version number Note: 1. AACK_FVN_MODE value one indicates frames according to IEEE 802.15.4-2006, a value of three indicates frames according to IEEE 802.15.4-2003 standard. The frame control field of the MAC header (MHR) contains a frame version subfield. The setting of register bits AACK_FVN_MODE specifies the frame filtering behavior of the AT86RF233. According to the content of these register bits the radio transceiver passes frames with a specific frame version number, number group, or independent of the frame version number. Thus the register bits AACK_FVN_MODE defines the maximum acceptable frame version. Received frames with a higher frame version number than configured do not pass the frame filter and are not acknowledged. The frame version field of the acknowledgment frame is set to zero according to IEEE 802.15.4-2006, Section 7.2.2.3.1 Acknowledgment frame MHR fields. z Bit 3 - AACK_I_AM_COORD This register bit has to be set if the node is a PAN coordinator. It is used for frame filtering in RX_AACK. Table 37-12. AACK_I_AM_COORD Value Description 0x0 PAN coordinator addressing is disabled 0x1 PAN coordinator addressing is enabled If AACK_I_AM_COORD = 1 and if only source addressing fields are included in a data or MAC command frame, the frame shall be accepted only if the device is the PAN coordinator and the source PAN identifier matches macPANId, for details refer to IEEE 802.15.4-2006, Section 7.5.6.2 (third-level filter rule six). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 956 37.2.4 Register Description - Address Registers 37.2.4.1 SHORT_ADDR_0 Name: SHORT_ADDR_0 Offset: 0x20 Reset: 0xFF Property: This register contains the lower 8-bit of the MAC short address for Frame Filter address recognition, bits[7:0]. Bit 7 6 5 4 3 2 1 0 SHORT_ADDR_0 0x20 Access R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Reset 37.2.4.2 SHORT_ADDR_1 Name: SHORT_ADDR_1 Offset: 0x21 Reset: 0xFF Property: - This register contains the higher 8-bit of the MAC short address for Frame Filter address recognition, bits[15:8]. Bit 7 6 5 4 R/W R/W R/W R/W 1 1 1 1 3 2 1 0 R/W R/W R/W R/W 1 1 1 1 SHORT_ADDR_1 0x21 Access Reset 37.2.4.3 PAN_ID_0 Name: PAN_ID_0 Offset: 0x22 Reset: 0xFF Property: - This register contains the lower 8-bit of the MAC PAN ID for Frame Filter address recognition, bits[7:0]. Bit 7 6 5 4 Reset 2 1 0 PAN_ID_0 0x22 Access 3 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 957 37.2.4.4 PAN_ID_1 Name: PAN_ID_1 Offset: 0x23 Reset: 0xFF Property: - This register contains the higher 8-bit of the MAC PAN ID for Frame Filter address recognition, bits[15:8]. Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 PAN_ID_1 0x23 Access Reset 37.2.4.5 IEEE_ADDR_0 Name: IEEE_ADDR_0 Offset: 0x24 Reset: 0x00 Property: - This register contains the lower 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[7:0]. Bit 7 6 5 4 3 2 1 0 IEEE_ADDR_0 0x24 Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 37.2.4.6 IEEE_ADDR_1 Name: IEEE_ADDR_1 Offset: 0x25 Reset: 0x00 Property: - This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[15:8]. Bit 7 6 5 4 Access Reset 3 2 1 0 IEEE_ADDR_1 0x25 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 958 37.2.4.7 IEEE_ADDR_2 Name: IEEE_ADDR_2 Offset: 0x26 Reset: 0x00 Property: - This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[23:16]. Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 IEEE_ADDR_2 0x26 Access Reset 37.2.4.8 IEEE_ADDR_3 Name: IEEE_ADDR_3 Offset: 0x27 Reset: 0x00 Property: - This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[31:24]. Bit 7 6 5 4 3 2 1 0 IEEE_ADDR_3 0x27 Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 37.2.4.9 IEEE_ADDR_4 Name: IEEE_ADDR_4 Offset: 0x28 Reset: 0x00 Property: - This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[39:32]. Bit 7 6 5 4 Access Reset 3 2 1 0 IEEE_ADDR_4 0x28 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 959 37.2.4.10 IEEE_ADDR_5 Name: IEEE_ADDR_5 Offset: 0x29 Reset: 0x00 Property: - This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[47:40]. Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 IEEE_ADDR_5 0x29 Access Reset 37.2.4.11 IEEE_ADDR_6 Name: IEEE_ADDR_6 Offset: 0x2A Reset: 0x00 Property: - This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[55:48]. Bit 7 6 5 4 3 2 1 0 IEEE_ADDR_6 0x2A Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 37.2.4.12 IEEE_ADDR_7 Name: IEEE_ADDR_7 Offset: 0x2B Reset: 0x00 Property: - This register contains the higher 8-bit of the MAC IEEE Frame Filter address for address recognition, bits[63:56]. Bit 7 6 5 4 Access Reset 3 2 1 0 IEEE_ADDR_7 0x2B R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 960 37.3 Frame Check Sequence (FCS) The Frame Check Sequence (FCS) is characterized by: z Indication of bit errors, based on a cyclic redundancy check (CRC) of length 16 bit z A use of International Telecommunication Union (ITU) CRC polynomial z Automatic evaluation during reception z Automatic generation during transmission 37.3.1 Overview The FCS is intended for use at the MAC layer to detect corrupted frames at a first level of filtering. It is computed by applying an ITU CRC polynomial to all transferred bytes following the length field (MHR and MSDU fields). The frame check sequence has a length of 16 bit and is located in the last two bytes of a frame (MAC footer, see Figure 37-2). The AT86RF233 applies an FCS check on each received frame. The FCS check result is stored in register bit RX_CRC_VALID (register 0x06, PHY_RSSI). On transmission the radio transceiver generates and appends the FCS bytes during the frame transmission. This behavior can be disabled by setting register bit TX_AUTO_CRC_ON = 0 (register 0x04, TRX_CTRL_1). 37.3.2 CRC Calculation The CRC polynomial used in IEEE 802.15.4 networks is defined by G16 ( x ) = x 16 + x 12 + x 5 + 1 . The FCS shall be calculated for transmission using the following algorithm: Let M ( x ) = b0 x k -1 + b1 x k -2 + K + bk -2 x + bk -1 be the polynomial representing the sequence of bits for which the checksum is to be computed. Multiply M(x) by x16, giving the polynomial N ( x) = M ( x) x16 . Divide N(x) modulo two by the generator polynomial, G16(x), to obtain the remainder polynomial, R ( x) = r0 x 15 + r1 x 14 + ... + r14 x + r15 . The FCS field is given by the coefficients of the remainder polynomial, R(x). Example: Considering a five octet ACK frame. The MHR field consists of 0100 0000 0000 0000 0101 0110. The leftmost bit (b0) is transmitted first in time. The FCS is in this case 0010 0111 1001 1110. The leftmost bit (r0) is transmitted first in time. 37.3.3 Automatic FCS Generation The automatic FCS generation is activated with register bit TX_AUTO_CRC_ON = 1. This allows the AT86RF233 to compute the FCS autonomously. For a frame with a frame length specified as N (3 N 127), the FCS is calculated on the first N-2 octets in the Frame Buffer, and the resulting FCS field is transmitted in place of the last two octets from the Frame Buffer. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 961 If the radio transceiver's automatic FCS generation is enabled, the Frame Buffer write access can be stopped right after MAC payload. There is no need to write FCS dummy bytes. In RX_AACK mode, when a received frame needs to be acknowledged, the FCS of the ACK frame is always automatically generated by the AT86RF233, independent of the TX_AUTO_CRC_ON setting. Example: A frame transmission of length five with TX_AUTO_CRC_ON set, is started with a Frame Buffer write access of five bytes (the last two bytes can be omitted). The first three bytes are used for FCS generation; the last two bytes are replaced by the internally calculated FCS. 37.3.4 Automatic FCS Check An automatic FCS check is applied on each received frame with a frame length N 2. Register bit RX_CRC_VALID (register 0x06, PHY_RSSI) is set if the FCS of a received frame is valid. The register bit is updated when issuing interrupt IRQ_3 (TRX_END) and remains valid until the next TRX_END interrupt caused by a new frame reception. In addition, bit[7] of byte RX_STATUS is set accordingly, refer to "Frame Buffer Access Mode" on page 886. In Extended Operating Mode, the RX_AACK procedure does not accept a frame if the corresponding FCS is not valid, that is no IRQ_3 (TRX_END) interrupt is issued. When operating in TX_ARET mode, the FCS of a received ACK is automatically checked. If it is not correct, the ACK is not accepted; refer to "TX_ARET_ON - Transmit with Automatic Frame Retransmission and CSMA-CA Retry" on page 928 for automated retries. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 962 37.3.5 Register Description 37.3.5.1 TRX_CTRL_1 Name: TRX_CTRL_1 Offset: 0x04 Reset: 0x22 Property: - The TRX_CTRL_1 register is a multi-purpose register to control various operating modes and settings of the radio transceiver. Bit 0x04 7 6 5 PA_EXT_EN IRQ_2_EXT_ EN TX_AUTO_C RC_ON RX_BL_CTRL R/W R/W R/W R/W R/W 0 0 1 0 0 Access Reset z 4 3 2 1 0 IRQ_MASK_ MODE IRQ_ POLARITY R/W R/W R/W 0 1 0 SPI_CMD_MODE Bit 5 - TX_AUTO_CRC_ON The register bit TX_AUTO_CRC_ON controls the automatic FCS generation for transmit operations. Table 37-13. TX_AUTO_CRC_ON Value Description 0x0 Automatic FCS generation is disabled 0x1 Automatic FCS generation is enabled Note: 1. The TX_AUTO_CRC_ON function can be used within Basic and Extended Operating Modes. 37.3.5.2 PHY_RSSI Name: PHY_RSSI Offset: 0x06 Reset: 0x60 Property: - The PHY_RSSI register is a multi-purpose register that indicates FCS validity, to provide random numbers, and a RSSI value. Bit 7 6 RX_CRC_VALID 0x06 5 4 3 RND_VALUE 2 1 0 RSSI Access R R R R R R R R Reset 0 1 1 0 0 0 0 0 z Bit 7 - RX_CRC_VALID The register bit RX_CRC_VALID signals the FCS check status for a received frame. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 963 Table 37-14. RX_CRC_VALID Value Description 0x0 FCS is not valid 0x1 FCS is valid Reading this register bit indicates whether the last received frame has a valid FCS or not. The register bit is updated when issuing interrupt IRQ_3 (TRX_END) and remains valid until the next TRX_END interrupt is issued, caused by a new frame reception. 37.4 Received Signal Strength Indicator (RSSI) The AT86RF233 Received Signal Strength Indicator is characterized by: z Minimum RSSI level is -94dBm (RSSIBASE_VAL) z Dynamic range is 87dB z Minimum RSSI value is 0 z Maximum RSSI value is 28 37.4.1 Overview The RSSI is a 5-bit value indicating the receive power in the selected channel, in steps of 3dB. No attempt is made to distinguish IEEE 802.15.4 signals from others, only the received signal strength is evaluated. The RSSI provides the basis for an ED measurement, see "Energy Detection (ED)" on page 965. 37.4.2 Reading RSSI In Basic Operating Modes, the RSSI value is valid in any receive state and is updated every tRSSI = 2s. The current RSSI value can be accessed by reading register bits RSSI (register 0x06, PHY_RSSI). It is not recommended reading the RSSI value when using the Extended Operating Modes or Smart Receiving, see " SRT - Smart Receiving Technology" on page 1034. Instead, the automatically generated ED value should be used, see "Energy Detection (ED)" on page 965. 37.4.3 Data Interpretation The RSSI value is a 5-bit value in a range of zero to 28, indicating the receiver input power in steps of about 3dB. A RSSI value of zero indicates a receiver RF input power of PRF -94dBm. For a RSSI value in the range of one to 28, the RF input power can be calculated as follows: PRF[dBm] = RSSIBASE_VAL[dBm] + 3[dB] x RSSI Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 964 37.4.4 Register Description 37.4.4.1 PHY_RSSI Name: PHY_RSSI Offset: 0x06 Reset: 0x60 Property: - The PHY_RSSI register is a multi-purpose register that indicates FCS validity, to provide random numbers, and a RSSI value. Bit 7 6 RX_CRC_VALID 0x06 5 4 3 RND_VALUE 2 1 0 RSSI Access R R R R R R R R Reset 0 1 1 0 0 0 0 0 z Bit 4:0 - RSSI Received signal strength as a linear curve on a logarithmic input power scale with a resolution of 3dB. Table 37-15. RSSI Value Description 0x00 Minimum RSSI value 0x1C Maximum RSSI value The result of the automated RSSI measurement is stored in register bits RSSI (register 0x06, PHY_RSSI). The value is updated every tRSSI = 2s in any receive state. The read value is a number between zero and 28 indicating the received signal strength as a linear curve on a logarithmic input power scale with a resolution of 3dB. An RSSI value of zero indicates an RF input power of PRF -94dBm (RSSIBASE_VAL), a value of 28 a power of PRF -10dBm (see parameter RSSIMAX specified in "Receiver Characteristics" on page 1104). 37.5 Energy Detection (ED) The AT86RF233 Energy Detection (ED) module is characterized by: z 84 unique energy levels defined z 1dB resolution z A measurement time of eight symbol periods for IEEE 802.15.4 compliant data rates 37.5.1 Overview The receiver ED measurement (ED scan procedure) can be used as a part of a channel selection algorithm. It is an estimation of the received signal power within the bandwidth of an IEEE 802.15.4 channel. No attempt is made to identify or decode signals on the channel. The ED value is calculated by averaging RSSI values over eight symbols (128s). For High Data Rate Modes the automated ED measurement duration is reduced to 32?s, refer to "High Data Rate Modes" on page 1013. For manually initiated ED measurements in these modes the measurement period is still 128?s as long as the receiver is in RX_ON state. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 965 37.5.2 Measurement Description There are two ways to initiate an ED measurement: z Manually, by writing an arbitrary value to register 0x07 (PHY_ED_LEVEL), or z Automatically, after detection of a valid SHR of an incoming frame. 37.5.2.1 Manually: For manually initiated ED measurements, the radio transceiver needs to be either in the state RX_ON or BUSY_RX. The end of the ED measurement time (eight symbol periods plus a processing time) is indicated by the interrupt IRQ_4 (CCA_ED_DONE) and the measurement result is stored in register 0x07 (PHY_ED_LEVEL), refer to tED in Table 36-2 on page 912. In order to avoid interference with an automatically initiated ED measurement, the SHR detection can be disabled by setting register bit RX_PDT_DIS (register 0x15, RX_SYN), refer to "Receiver (RX)" on page 975. Note: It is not recommended to manually initiate an ED measurement when using the Extended Operation Mode. 37.5.2.2 Automatically: An automated ED measurement is started upon SHR detection. The end of the automated measurement is not signaled by an interrupt. When using Basic Operating Mode, a valid ED value from the currently received frame is accessible 108s after IRQ_2 (RX_START) and remains valid until a new RX_START interrupt is generated by the next incoming frame or until another ED measurement is initiated. When using the Extended Operating Mode, it is recommended to mask IRQ_2 (RX_START), thus the interrupt cannot be used as timing reference. A successful frame reception is signalized by interrupt IRQ_3 (TRX_END). The minimum time span between an IRQ_3 (TRX_END) interrupt and a following SFD detection is tSHR_SYNC = 96s due to the length of the SHR. Including the ED measurement time, the ED value needs to be read within 224s after the TRX_END interrupt; otherwise, it could be overwritten by the result of the next measurement cycle. This is important for time critical applications or if interrupt IRQ_2 (RX_START) is not used to indicate the reception of a frame. Note: The ED result is not updated during the rest of the frame reception, even by requesting an ED measurement manually. 37.5.3 Data Interpretation The PHY_ED_LEVEL is an 8-bit register. The ED_LEVEL value of the AT86RF233 has a valid range from 0x00 to 0x53 with a resolution of 1dB. Values 0x54 to 0xFE do not occur and a value of 0xFF indicates the reset value. Due to environmental conditions (temperature, voltage, semiconductor parameters, etc.) the calculated ED_LEVEL value has a maximum tolerance of 5dB, this is to be considered as constant offset over the measurement range. An ED_LEVEL value of zero indicates a receiver RF input power of PRF -94dBm (see parameter RSSIBASE_VAL, "Receiver Characteristics" on page 1104). For an ED_LEVEL value in the range of one to 83, the RF input power can be calculated as follows: PRF[dBm] = RSSIBASE_VAL[dBm] + 1[dB] x ED_LEVEL 37.5.4 Interrupt Handling Interrupt IRQ_4 (CCA_ED_DONE) is issued at the end of a manually initiated ED measurement. Note: 1. An ED request should only be initiated in receive states. Otherwise the radio transceiver generates an IRQ_4 (CCA_ED_DONE); however no ED measurement was performed. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 966 37.5.5 Register Description 37.5.5.1 PHY_ED_LEVEL Name: PHY_ED_LEVEL Offset: 0x07 Reset: 0xFF Property: - The PHY_ED_LEVEL register contains the result of an ED measurement. Bit 7 6 5 4 3 2 1 0 ED_LEVEL 0x07 Access R R R R R R R R Reset 1 1 1 1 1 1 1 1 z Bit 7:0 - ED_LEVEL The register bits ED_LEVEL signals the ED level for the current channel. Table 37-16. ED_LEVEL Value Description 0x00 Minimum ED level value 0x53 Maximum ED level value 0xFF Reset value The minimum ED value zero indicates receiver power less than or equal RSSIBASE_VAL. The range is 83dB with a resolution of 1dB and an accuracy of 5dB. The value 0xFF signals that no measurement has been started yet (reset value). A manual ED measurement can be initiated by a write access to the register. The measurement duration is eight symbol periods (128s) for a data rate of 250kb/s. For High Data Rate Modes the automated measurement duration is reduced to 32?s, refer to "High Data Rate Modes" on page 1013. For manually initiated ED measurements in these modes the measurement period is still 128?s as long as the receiver is in RX_ON state. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 967 37.6 Clear Channel Assessment (CCA) The main features of the Clear Channel Assessment (CCA) module are: z All four modes are available as defined by IEEE 802.15.4-2006 in Section 6.9.9 z Adjustable threshold for energy detection algorithm 37.6.1 Overview A CCA measurement is used to detect a clear channel. Four CCA modes are specified by IEEE 802.15.4-2006: Table 37-17. CCA Mode Overview CCA Mode 1 Description Energy above threshold. CCA shall report a busy medium upon detecting any energy above the ED threshold. Carrier sense only. 2 CCA shall report a busy medium only upon the detection of a signal with the modulation and spreading characteristics of an IEEE 802.15.4 compliant signal. The signal strength may be above or below the ED threshold. Carrier sense with energy above threshold. CCA shall report a busy medium using a logical combination of 0, 3 Detection of a signal with the modulation and spreading characteristics of this standard and Energy above the ED threshold. Where the logical operator may be configured as either OR (mode 0) or AND (mode 3). 37.6.2 Configuration and Request The CCA modes are configurable via register 0x08 (PHY_CC_CCA). When in Basic Operating Mode, an CCA request can be initiated manually by setting CCA_REQUEST = 1 (register 0x08, PHY_CC_CCA), if the Atmel AT86RF233 is in any RX state. The current channel status (CCA_STATUS) and the CCA completion status (CCA_DONE) are accessible through register 0x01 (TRX_STATUS). The CCA evaluation is done over eight symbol periods and the result is accessible tCCA = 180s (max.) (128s measurement duration and processing delay) after the request, refer to Table 36-2 on page 912. The end of a manually initiated CCA measurement is indicated by an interrupt IRQ_4 (CCA_ED_DONE). The register bits CCA_ED_THRES (register 0x09, CCA_THRES) defines the receive power threshold of the "energy above threshold" algorithm. The threshold is calculated by: PCCA_ED_THRES[dBm] = RSSIBASE_VAL[dBm] + 2[dB] x CCA_ED_THRES. Any received power above this level is interpreted as a busy channel. Note: It is not recommended to manually initiate and CCA measurement when using the Extended Operating Mode. 37.6.3 Data Interpretation The AT86RF233 current channel status (CCA_STATUS) and the CCA completion status (CCA_DONE) are accessible through register 0x01 (TRX_STATUS). Note: The register bits CCA_DONE and CCA_STATUS are cleared in response to a CCA REQUEST. The completion of a measurement cycle is indicated by CCA_DONE = 1. If the radio transceiver detects no signal (idle channel) during the CCA evaluation period, the CCA_STATUS bit is set to one; otherwise, it is set to zero. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 968 When using the "energy above threshold" algorithm, a received power above PCCA_ED_THRES is interpreted as a busy channel. When using the "carrier sense" algorithm (that is CCA_MODE = 0, 2, and 3), the AT86RF233 reports a busy channel upon detection of a PHY mode specific IEEE 802.15.4 signal above RSSIBASE_VAL (see "Receiver Characteristics" on page 1104). The AT86RF233 is also capable of detecting signals below this value, but the detection probability decreases with decreasing signal power. It is almost zero at the radio transceivers sensitivity level (see parameter PSENS on "Receiver Characteristics" on page 1104). 37.6.4 Interrupt Handling Interrupt IRQ_4 (CCA_ED_DONE) is issued at the end of a manually initiated CCA measurement. Note: A CCA request should only be initiated in Basic Operating Mode receive states. Otherwise the radio transceiver generates an IRQ_4 (CCA_ED_DONE) and sets the register bit CCA_DONE = 1, even though no CCA measurement was performed. 37.6.5 Measurement Time The response time for a manually initiated CCA measurement depends on the receiver state. In RX_ON state, the CCA measurement is done over eight symbol periods and the result is accessible upon the event IRQ_4 (CCA_ED_DONE) or upon CCA_DONE = 1 (register 0x01, TRX_STATUS). In BUSY_RX state, the CCA measurement duration depends on the CCA mode and the CCA request relative to the detection of the SHR. The end of the CCA measurement is indicated by IRQ_4 (CCA_ED_DONE). The variation of a CCA measurement period in BUSY_RX state is described in Table 37-18. It is recommended to perform CCA measurements in RX_ON state only. To avoid switching accidentally to BUSY_RX state, the SHR detection can be disabled by setting register bit RX_PDT_DIS (register 0x15, RX_SYN), refer to "Receiver (RX)" on page 975. The receiver remains in RX_ON state to perform a CCA measurement until the register bit RX_PDT_DIS is set back to continue the frame reception. In this case, the CCA measurement duration is eight symbol periods. Table 37-18. CCA Measurement Period and Access in BUSY_RX state CCA Mode Request within ED measurement(1) Request after ED measurement Energy above threshold. 1 CCA result is available after finishing automated ED measurement period. CCA result is immediately available after request. Carrier sense only. 2 CCA result is immediately available after request. Carrier sense with Energy above threshold (AND). 3 CCA result is available after finishing automated ED measurement period. CCA result is immediately available after request. Carrier sense with Energy above threshold (OR). 0 Note: CCA result is available after finishing automated ED measurement period. 1. CCA result is immediately available after request. After detecting the SHR, an automated ED measurement is started with a length of eight symbol periods (two symbol periods for high rate PHY modes, refer to "Energy Detection (ED)" on page 965. This automated ED measurement must be finished to provide a result for the CCA measurement. Only one automated ED measurement per frame is performed. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 969 37.6.6 Register Description 37.6.6.1 TRX_STATUS Name: TRX_STATUS Offset: 0x01 Reset: 0x00, 0x08 Property: - The read-only register TRX_STATUS signals the present state of the radio transceiver as well as the status of a CCA operation. Bit 7 6 5 4 3 2 1 0 CCA_DONE CCA_STATUS Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 0x01 TRX_STATUS Bit 7 - CCA_DONE Table 37-19. CCA_DONE z Value Description 0x0 CCA calculation not finished 0x1 CCA calculation finished The register bit CCA_DONE indicates if a CCA request is completed. This is also indicated by an interrupt IRQ_4 (CCA_ED_DONE). The register bit CCA_DONE is cleared in response to a CCA_REQUEST. Bit 6 - CCA_STATUS Table 37-20. CCA_STATUS z Value Description 0x0 Channel indicated as busy 0x1 Channel indicated as idle After a CCA request is completed, the result of the CCA measurement is available in register bit CCA_STATUS. The register bit CCA_STATUS is cleared in response to a CCA_REQUEST. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 970 37.6.6.2 PHY_CC_CCA Name: PHY_CC_CCA Offset: 0x08 Reset: 0x2B Property: - The PHY_CC_CCA register is a multi-purpose register that controls CCA configuration, CCA measurement, and the IEEE 802.15.4 channel setting. Bit 7 6 CCA_REQUEST 0x08 Access Reset z 5 4 3 CCA_MODE 2 1 0 CHANNEL R/W R/W R/W R/W R/W R/W R/W R/W 0 0 1 0 1 0 1 1 Bit 7 - CCA_REQUEST The register bit CCA_REQUEST initiates a manual started CCA measurement. Table 37-21. CCA_REQUEST Value Description 0x0 Reset value 0x1 Starts a CCA measurement Notes: 1. 2. The read value returns always with zero. If a CCA request is initiated in states others than RX_ON or RX_BUSY the PHY generates an IRQ_4 (CCA_ED_DONE) and sets the register bit CCA_DONE, however no CCA was carried out. A manual CCA measurement is initiated with setting CCA_REQUEST = 1. The end of the CCA measurement is indicated by interrupt IRQ_4 (CCA_ED_DONE). Register bits CCA_DONE and CCA_STATUS (register 0x01, TRX_STATUS) are updated after a CCA_REQUEST. The register bit is automatically cleared after requesting a CCA measurement with CCA_REQUEST = 1. z Bit 6:5 - CCA_MODE The CCA mode can be selected using register bits CCA_MODE. Table 37-22. CCA_MODE Value Description 0x0 Mode 3a, Carrier sense OR energy above threshold 0x1 Mode 1, Energy above threshold 0x2 Mode 2, Carrier sense only 0x3 Mode 3b, Carrier sense AND energy above threshold Note: 1. IEEE 802.15.4-2006 CCA mode 3 defines the logical combination of CCA mode 1 and 2 with the logical operators AND or OR Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 971 37.6.6.3 CCA_THRES Name: CCA_THRES Offset: 0x09 Reset: 0xC7 Property: - The CCA_THRES register sets the ED threshold level for CCA. Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 0 0 0 1 1 1 CCA_ED_THRES 0x09 Access Reset z Bit 3:0 - CCA_ED_THRES An ED value above the threshold signals the channel as busy during a CCA_ED measurement. Table 37-23. CCA_ED_THRES 37.7 Value Description 0x7 For CCA_MODE = 1, a busy channel is indicated if the measured received power is above P_THRES[dBm] = RSSI_BASE_VAL[dBm] + 2[dB] x CCA_ED_THRES. CCA modes 0 and 3 are logically related to this result. Link Quality Indication (LQI) The IEEE 802.15.4 standard defines the LQI as a characterization of the strength and/or quality of a received frame. The use of the LQI result by the network or application layer is not specified in this standard. The LQI value shall be an integer ranging from zero to 255, with at least eight unique values. The minimum and maximum LQI values (0x00 and 0xFF) should be associated with the lowest and highest quality compliant signals, respectively, and LQI values in between should be uniformly distributed between these two limits. 37.7.1 Overview The LQI measurement of the AT86RF233 is implemented as a measure of the link quality which can be described with the packet error rate (PER) for this link. An LQI value can be associated with an expected packet error rate. The PER is the ratio of erroneous received frames to the total number of received frames. A PER of zero indicates no frame error, whereas at a PER of one no frame was received correctly. The radio transceiver uses correlation results of multiple symbols within a frame to determine the LQI value. This is done for each received frame. The minimum frame length for a valid LQI value is two octets PSDU. LQI values are integers ranging from zero to 255. As an example, Figure 37-4 shows the conditional packet error rate (PER) when receiving a certain LQI value. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 972 Figure 37-4. Conditional Packed Error Rate vs. LQI 1 0.9 0.8 0.7 PER 0.6 0.5 0.4 0.3 0.2 0.1 0 0 50 100 150 200 250 LQI That means that a large number of transmission with an identical LQI value results in a packet error rate shown in the Figure 37-4. Lost packets have been discarded since in this case there is no LQI value available. If, instead, the mean LQI over a large number of transmissions is computed, and the mean LQI is quantized to an LQI value of the figure, the corresponding frame error rate is not strictly equal to the true error rate. The values are taken from received frames of PSDU length of 20 octets on transmission channels with reasonable low multipath delay spreads. If the transmission channel characteristic has higher multipath delay spread than assumed in the example, the PER is slightly higher for a certain LQI value. Since the packet error rate is a statistical value, the PER shown in Figure 37-4 is based on a huge number of transactions. A reliable estimation of the packet error rate cannot be based on a single or a small number of LQI values. 37.7.2 Obtaining the LQI Value The LQI value is available, once the corresponding frame has been completely received. This is indicated by the interrupt IRQ_3 (TRX_END). The value can be obtained by means of a frame buffer read access, see "Frame Buffer Access Mode" on page 886. 37.7.3 Data Interpretation The reason for a low LQI value can be twofold: a low signal strength and/or high signal distortions, for example by interference and/or multipath propagation. High LQI values, however, indicate a sufficient signal strength and low signal distortions. Notes: 1. The LQI value is almost always 255 for scenarios with very low signal distortions and a signal strength much greater than the sensitivity level. In this case, the packet error rate tends towards zero and increase of the signal strength, that is by increasing the transmission power, cannot decrease the error rate any further. Received signal strength indication (RSSI) or energy detection (ED) can be used to evaluate the signal strength and the link margin. 2. The received signal power as indicated by received signal strength indication (RSSI) value or energy detection (ED) value of the AT86RF233 do not characterize the signal quality and the ability to decode a signal. ZigBee networks often require identification of the "best" routing between two nodes. LQI and RSSI/ED can be applied, depending on the optimization criteria. If a low frame error rate (corresponding to a high throughput) is the optimization Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 973 criteria, then the LQI value should be taken into consideration. If, however, the target is a low transmission power, then the RSSI/ED value is also helpful. Various combinations of LQI and RSSI/ED are possible for routing decisions. As a rule of thumb, information on RSSI/ED is useful in order to differentiate between links with high LQI values. However, transmission links with low LQI values should be discarded for routing decisions, even if the RSSI/ED values are high, since it is merely an information about the received signal strength, whereas the source can be an interferer. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 974 38. AT86RF233 Module Description 38.1 Receiver (RX) 38.1.1 Overview The AT86RF233 receiver is split into an analog radio front-end and a digital base band processor (RX BBP), see Figure 38-1. Figure 38-1. Receiver Block Diagram Analog Domain LO Digital Domain Frame Buffer RFP LNA PPF BPF Limiter ADC RX BBP SPI SPI I/F RFN AGC RSSI Control, Registers C I/F The differential RF signal is amplified by a low noise amplifier (LNA), filtered (PPF) and down converted to an intermediate frequency by a mixer. Channel selectivity is performed using an integrated band pass filter (BPF). A limiting amplifier (Limiter) provides sufficient gain to overcome the DC offset of the succeeding analog-to-digital converter (ADC) and generates a digital RSSI signal. The ADC output signal is sampled and processed further by the digital base band receiver (RX BBP). The RX BBP performs additional signal filtering and signal synchronization. The frequency offset of each frame is calculated by the synchronization unit and is used during the remaining receive process to correct the offset. The receiver is designed to handle frequency and symbol rate deviations fSRD up to 120ppm, caused by combined receiver and transmitter deviations. For details refer to "General RF Specifications" on page 1102 parameter fSRD. Finally the signal is demodulated and the data are stored in the Frame Buffer. In Basic Operating Mode, refer to "Basic Operating Mode" on page 902, the reception of a frame is indicated by an interrupt IRQ_2 (RX_START). Accordingly its end is signalized by an interrupt IRQ_3 (TRX_END). Based on the quality of the received signal a link quality indicator (LQI) is calculated and appended to the frame, refer to "Link Quality Indication (LQI)" on page 972. Additional signal processing is applied to the frame data to provide further status information like ED value (register 0x07, PHY_ED_LEVEL) and FCS correctness (register 0x06, PHY_RSSI). Beyond these features the Extended Operating Mode of the AT86RF233 supports address filtering and pending data indication. For details refer to "Extended Operating Mode" on page 915. 38.1.2 Frame Receive Procedure The frame receive procedure including the radio transceiver setup for reception and reading PSDU data from the Frame Buffer is described in "Frame Receive Procedure" on page 1003 Frame Receive Procedure. 38.1.3 Configuration In Basic Operating Mode the receiver is enabled by writing command RX_ON to register bits TRX_CMD (register 0x02, TRX_STATE) in states TRX_OFF or PLL_ON. Similarly in Extended Operating Mode, the receiver is enabled for RX_AACK operation from states TRX_OFF, PLL_ON or TX_ARET_ON by writing the command RX_AACK_ON. There is no additional configuration required to receive IEEE 802.15.4 compliant frames when using the Basic Operating Mode. However, the frame reception in the AT86RF233 Extended Operating Mode requires further register configurations, for details refer to "Extended Operating Mode" on page 915. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 975 The AT86RF233 receiver has an outstanding sensitivity performance of -99dBm. At certain environmental conditions or for High Data Rate Modes ("High Data Rate Modes" on page 1013) it may be useful to manually decrease this sensitivity. This is achieved by adjusting the synchronization header detector threshold using register bits RX_PDT_LEVEL (register 0x15, RX_SYN). Received signals with a RSSI value below the threshold do not activate the demodulation process. Furthermore, it may be useful to protect a received frame against overwriting by subsequent received frames. A Dynamic Frame Buffer Protection is enabled with register bit RX_SAFE_MODE (register 0x0C, TRX_CTRL_2) set, see "Dynamic Frame Buffer Protection" on page 1032. The receiver remains in RX_ON or RX_AACK_ON state until the whole frame is uploaded by the microcontroller, indicated by /SEL = H during the SPI Frame Receive Mode. The Frame Buffer content is only protected if the FCS is valid. A Static Frame Buffer Protection is enabled with register bit RX_PDT_DIS (register 0x15, RX_SYN) set. The receiver remains in RX_ON or RX_AACK_ON state and no further SHR is detected until the register bit RX_PDT_DIS is set back. 38.1.4 Register Description 38.1.4.1 RX_SYN Name: RX_SYN Offset: 0x15 Reset: 0x00 Property: - The register RX_SYN controls the blocking of receiver path and the sensitivity threshold of the receiver. Bit 7 6 5 4 3 RX_PDT_DIS 0x15 Access Reset z 2 1 0 RX_PDT_LEVEL R/W R R R R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 - RX_PDT_DIS The register bit RX_PDT_DIS prevents the reception of a frame during RX phase. . Table 38-1. RX_PDT_DIS Value Description 0x0 RX path is enabled 0x1 RX path is disabled RX_PDT_DIS = 1 prevents the reception of a frame even if the radio transceiver is in receive modes. An ongoing frame reception is not affected. This operation mode is independent of the setting of register bits RX_PDT_LEVEL. z Bit 3:0 - RX_PDT_LEVEL The register bits RX_PDT_LEVEL desensitize the receiver in steps of 3dB. Table 38-2. RX_PDT_LEVEL Value Description 0x00 Maximum RX sensitivity 0x0F RX input level[dBm] > RSSI_BASE_VAL[dBm] + 3[dB] x 14 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 976 These register bits desensitize the receiver such that frames with an RSSI level below the RX_PDT_LEVEL threshold level (if RX_PDT_LEVEL > 0) are not received. For a RX_PDT_LEVEL > 0 value the threshold level can be calculated according to the following formula: PRF[dBm] > RSSIBASE_VAL[dBm] + 3[dB] x (RX_PDT_LEVEL - 1). Examples for certain register settings are given in Table 38-3. Table 38-3. Receiver Desensitization Threshold Level - RX_PDT_LEVEL Register Value RX Input Threshold Level Value [dBm] 0x0 RSSI_BASE_VAL (reset value) RSSI value not considered 0x1 > RSSI_BASE_VAL + 3[db] x 0 > -94 0xE > RSSI_BASE_VAL + 3[db] x 13 > -55 0xF > RSSI_BASE_VAL + 3[db] x 14 > -52 ... If register bits RX_PDT_LEVEL = 0 (reset value) all frames with a valid SHR and PHR are received, independently of their signal strength. If register bits RX_PDT_LEVEL > 0, the current consumption of the receiver in all RX listening states is reduced to IRX_ON_L0 = 11.3mA (typ.), refer to "Current Consumption Specifications" on page 1105. Additional power saving techniques in receive modes are specified in "Reduced Power Consumption Mode (RPC)" on page 1034. 38.1.4.2 TST_AGC Name: TST_AGC Offset: 0x3C Reset: 0x00 Property: - Bit 7 6 0x3C 5 4 3 2 AGC_HOLD_ SEL AGC_RST AGC_OFF AGC_HOLD 1 0 GC Access R R R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Note: z 1. The register bits can be read or written, the values will effect the device operation only if the register bit PMU_EN (register 0x03, TRX_CTRL_0) is set, otherwise reset values will be applied. Bit 5 - AGC_HOLD_SEL The register bit AGC_HOLD_SEL controls the AGC operation mode. Table 38-4. AGC_HOLD_SEL Value Description 0x0 Normal operation is selected 0x1 Manual control of AGC operation is selected. Used setting from register bit AGC_HOLD. z Bit 4 - AGC_RST The register bit AGC_RST resets the AGC receiver gain control to maximum gain. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 977 Table 38-5. AGC_RST Value Description 0x0 No AGC gain control reset 0x1 AGC gain control reset z Bit 3 - AGC_OFF The register bit AGC_OFF disables automatic AGC gain regulation. Allows manual receiver gain setting with register bits GC. Table 38-6. AGC_OFF Value Description 0x0 Automatic AGC gain regulation is switched on 0x1 Automatic AGC gain regulation is switched off z Bit 2 - AGC_HOLD The register bit AGC_HOLD controls the AGC running mode. Table 38-7. AGC_HOLD Value Description 0x0 AGC is within free running mode 0x1 AGC running mode is frozen z Bit 1:0 - GC The register bits GC control the receiver gain. A setting of register bits GC effect the device operation only if register bit AGC_OFF is set. Table 38-8. GC Value Description 0x0 Set receiver path to maximum gain 0x1 Set receiver path to medium gain 0x2 Set receiver path to minimum gain All other values are reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 978 38.2 Transmitter (TX) 38.2.1 Overview The AT86RF233 transmitter consists of a digital base band processor (TX BBP) and an analog radio front end, see Figure 38-2. Figure 38-2. Transmitter Block Diagram Ext. RF front-end and Output Power Control DIG3/4 RFP PA Buf C I/F Control, Registers TX Data PLL - TX Modulation TX BBP SPI I/F SPI RFN Frame Buffer Analog Domain Digital Domain The TX BBP reads the frame data from the Frame Buffer and performs the bit-to-symbol and symbol-to-chip mapping as specified by IEEE 802.15.4 in Section 6.5.2. The O-QPSK modulation signal is generated and fed into the analog radio front end. The fractional-N frequency synthesizer (PLL) converts the baseband transmit signal to the RF signal, which is amplified by the power amplifier (PA). The PA output is internally connected to bidirectional differential antenna pins (RFP, RFN), so that no external antenna switch is needed. 38.2.2 Frame Transmit Procedure The frame transmit procedure including writing PSDU data in the Frame Buffer and initiating a transmission is described in "Frame Transmit Procedure" on page 1003. 38.2.3 Configuration The maximum output power of the transmitter is typically +4dBm. The output power can be configured via register bits TX_PWR (register 0x05, PHY_TX_PWR). The output power of the transmitter can be controlled over a range of 21dB. A transmission can be started from PLL_ON or TX_ARET_ON state by a rising edge of SLP_TR or by writing TX_START command to register bits TRX_CMD (register 0x02, TRX_STATE). Figure 38-3. TX Power Ramping for Maximum TX Power 0 TRX_STATE PLL_ON 2 4 6 8 10 12 14 16 18 Length [s] BUSY_TX SLP_TR PA buffer PA Modulation 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 0 0 0 0 0 0 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 979 38.2.4 TX Power Ramping To optimize the output power spectral density (PSD), the PA buffer and PA are enabled sequentially, see in Figure 38-3. In this example the transmission is initiated with the rising edge of SLP_TR. The radio transceiver state changes from PLL_ON to BUSY_TX. The modulation of the frame starts 16s after SLP_TR rising edge. 38.2.5 Register Description 38.2.5.1 PHY_TX_PWR Name: PHY_TX_PWR Offset: 0x05 Reset: 0x00 Property: - The PHY_TX_PWR register controls the output power of the transmitter. Bit 7 6 5 4 3 2 1 0 TX_PWR 0x05 Access R R/W R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bit 3:0 - TX_PWR The register bits TX_PWR determine the TX output power of the radio transceiver. Table 38-9. TX_PWR Value TX Output Power [dBm] 0x0 +4 0x1 +3.7 0x2 +3.4 0x3 +3 0x4 +2.5 0x5 +2 0x6 +1 0x7 0 0x8 -1 0x9 -2 0xA -3 0xB -4 0xC -6 0xD -8 0xE -12 0xF -17 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 980 Notes: 1. A state change that is a command gets written to the TRX_CMD field resets the value of the TX_PWR fields to the originally set value. 2. If the extended operating mode is used with RPC enabled (that is XAH_TX_RPC_EN is set to one), the read value of the TX_PWR field provides the used transmit power for last transmitted frame including acknowledgement frame. The TX_PWR field contains only the value of the RPC-controlled transmission if a frame has already been sent. This allows monitoring the actual RPC handling used for transmitting. 38.2.5.2 PHY_TX_TIME for TOM_EN=0x01 Name: PHY_TX_TIME Offset: 0x3B Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 IRC_TX_TIME 0x3B Notes: 1. 2. z If PMU mode is active, signals 8-bit PMU measurement value. If TOM mode is active, signals 4-bit IRC_TX_TIME value. Bit 3:0 - IRC_TX_TIME The register bits IRC_TX_TIME signals the alignment between rising edge of SLP_TR to 1MHz CLKM clock. Table 38-10. IRC_TX_TIME 38.3 Value Description 0x0 Signals 4-bit IRC_TX_TIME measurement value. The resolution is 1/16MHz. Valid values are [0xF, 0xE, ..., 0x0]. Frame Buffer The AT86RF233 contains a 128 byte dual port SRAM. One port is connected to the SPI interface, the other one to the internal transmitter and receiver modules. For data communication, both ports are independent and simultaneously accessible. The Frame Buffer utilizes the SRAM address space 0x00 to 0x7F for RX and TX operation of the radio transceiver and can keep a single IEEE 802.15.4 RX or a single TX frame of maximum length at a time. Frame Buffer access modes are described in "Frame Buffer Access Mode" on page 886. Frame Buffer access conflicts are indicated by an under run interrupt IRQ_6 (TRX_UR). Note: The IRQ_6 (TRX_UR) interrupt also occurs on the attempt to write frames longer than 127 octets to the Frame Buffer (overflow). In that case the content of the Frame Buffer cannot be guaranteed. Frame Buffer access is only possible if the digital voltage regulator (DVREG) is turned on. This is valid in all device states except in SLEEP or DEEP_SLEEP state. An access in P_ON state is possible if CLKM provides a master clock. 38.3.1 Data Management Data in Frame Buffer (received data or data to be transmitted) remains valid as long as: z No new frame or other data are written into the buffer over SPI z No new frame is received (in any BUSY_RX state) z No state change into SLEEP or DEEP_SLEEP state is made z No RESET took place Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 981 By default there is no protection of the Frame Buffer against overwriting. Therefore, if a frame is received during Frame Buffer read access of a previously received frame, interrupt IRQ_6 (TRX_UR) is issued and the stored data might be overwritten. Even so, the old frame data can be read, if the SPI data rate is higher than the effective over air data rate. For a data rate of 250kb/s a minimum SPI clock rate of 1MHz is recommended. Finally the microcontroller should check the transferred frame data integrity by an FCS check. To protect the Frame Buffer content against being overwritten by newly incoming frames, the radio transceiver state should be changed to PLL_ON state after reception. This can be achieved by writing immediately the command PLL_ON to register bits TRX_CMD (register 0x02, TRX_STATE) after receiving the frame, indicated by IRQ_3 (TRX_END). Alternatively, Dynamic Frame Buffer Protection can be used to protect received frames against overwriting, for details refer to "Dynamic Frame Buffer Protection" on page 1032. Both procedures do not protect the Frame Buffer from overwriting by the microcontroller. In Extended Operating Mode during TX_ARET operation, see "TX_ARET_ON - Transmit with Automatic Frame Retransmission and CSMA-CA Retry" on page 928, the radio transceiver switches to receive, if an acknowledgement of a previously transmitted frame was requested. During this period received frames are evaluated, but not stored in the Frame Buffer. This allows the radio transceiver to wait for an acknowledgement frame and retry the frame transmission without writing them again. A radio transceiver state change, except a transition to SLEEP, DEEP_SLEEP, or RESET state, does not affect the Frame Buffer contents. If the radio transceiver is forced into SLEEP or DEEP_SLEEP, the Frame Buffer is powered off and the stored data gets lost. 38.3.2 User accessible Frame Content The AT86RF233 supports an IEEE 802.15.4 compliant frame format as shown in Figure 38-4. Figure 38-4. AT86RF233 Frame Structure 0 Frame Duration Access Note: Length [octets] 4 5 Preamble Sequence SFD 4 octets 1 6 PHR SHR not accesible PHY generated n+3 Payload n+5 FCS n+6 LQI(1) n+7 ED(1) n+8 RX_STATUS(1) 3 octets n octets (n <= 128) TX: Frame Buffer content RX: Frame Buffer content Stored into Frame Buffer during reception. A frame comprises two sections, the radio transceiver internally generated SHR field and the user accessible part stored in the Frame Buffer. The SHR contains the preamble and the SFD field. The variable frame section contains the PHR and the PSDU including the FCS, see "Frame Check Sequence (FCS)" on page 961. To access the data follow the procedures described in "Frame Buffer Access Mode" on page 886. The frame length information (PHR field) and the PSDU are stored in the Frame Buffer. During frame reception, the link quality indicator (LQI) value, the energy detection (ED) value, and the status information (RX_STATUS) of a received frame are additionally stored, see "Link Quality Indication (LQI)" on page 972, "Energy Detection (ED)" on page 965, and "Frame Buffer Access Mode" on page 886, respectively. The radio transceiver appends these values to the frame data during Frame Buffer read access. If the SRAM read access is used to read an RX frame, the frame length field (PHR) can be accessed at address zero. The SHR (except the SFD value used to generate the SHR) cannot be read by the microcontroller. For frame transmission, the PHR and the PSDU needs to be stored in the Frame Buffer. The maximum Frame Buffer size supported by the radio transceiver is 128 bytes. If the register bit TX_AUTO_CRC_ON is set in register 0x04 (TRX_CTRL_1), the FCS field of the PSDU is replaced by the automatically calculated FCS during frame transmission. There is no need to write the FCS field when using the automatic FCS generation. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 982 To manipulate individual bytes of the Frame Buffer a SRAM write access can be used instead. For non IEEE 802.15.4 compliant frames, the minimum frame length supported by the radio transceiver is one byte (Frame Length Field + one byte of data). 38.3.3 Interrupt Handling Access conflicts may occur when reading and writing data simultaneously at the two independent ports of the Frame Buffer, TX/RX BBP and SPI. These ports have their own address counter that points to the Frame Buffer's current address. Access violations may cause data corruption and are indicated by IRQ_6 (TRX_UR) interrupt when using the Frame Buffer access mode. Note that access violations are not indicated when using the SRAM access mode. While receiving a frame, primarily the data needs to be stored in the AT86RF233 Frame Buffer before reading it. This can be ensured by accessing the Frame Buffer 32s after IRQ_2 (RX_START) at the earliest. When reading the frame data continuously the SPI data rate shall be lower than 250kb/s to ensure no under run interrupt occurs. To avoid access conflicts and to simplify the Frame Buffer read access Frame Buffer Empty indication may be used, for details refer to "Frame Buffer Empty Indicator" on page 1030. During transmission, an access violation occurs on Frame Buffer write access, when the SPI port's address counter value becomes less than or equal to that of TX BBP port. Both these access violations may cause data corruption and are indicated by IRQ_6 (TRX_UR) interrupt when using the Frame Buffer access mode. Access violations are not indicated when using the SRAM access mode. Notes: 1. 38.4 Interrupt IRQ_6 (TRX_UR) is valid 64s after IRQ_2 (RX_START). The occurrence of the interrupt can be disregarded when reading the first byte of the Frame Buffer between 32s and 64s after the RX_START interrupt. 2. If a Frame Buffer read access is not finished until a new frame is received, an IRQ_6 (TRX_UR) interrupt occurs. Nevertheless the old frame data can be read, if the SPI data rate is higher than the effective PHY data rate. A minimum SPI clock rate of 1MHz is recommended in this case. Finally, the microcontroller should check the integrity of the transferred frame data by calculating the FCS. 3. When writing data to the Frame Buffer during frame transmission, the SPI data rate shall be higher than the PHY data rate to ensure no under run interrupt. The first byte of the PSDU data must be available in the Frame Buffer before SFD transmission is complete, which takes 176s (16s PA ramp-up + 160s SHR) from the rising edge of SLP_TR (see Figure 36-2). Voltage Regulators (AVREG, DVREG) The main features of the Voltage Regulator blocks are: z Bandgap stabilized 1.8V supply for analog and digital domain z Low dropout (LDO) voltage regulator z AVREG/DVREG can be disabled when an external regulated voltage is supplied to AVDD/DVDD pin 38.4.1 Overview The internal voltage regulators supply a stabilized voltage to the AT86RF233. The AVREG provides the regulated 1.8V supply voltage for the analog section and the DVREG supplies the 1.8V supply voltage for the digital section. A simplified schematic of the internal voltage regulator is shown in Figure 38-5. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 983 Figure 38-5. Simplified Schematic of AVREG EVDD Bandgap voltage reference 1.25 V AVDD A simplified schematic of the internal digital voltage regulator is shown in Figure 38-6. Figure 38-6. Simplified Schematic of DVREG DEVDD Bandgap voltage reference 1. 25 V BIAS DVDD Low power voltage regulator Voltage regulator Digital voltage regulator The block "Low power voltage regulator" within the "Digital voltage regulator" maintains the DVDD supply voltage at 1.5V (typical) when the AT86RF233 voltage regulator is disabled in sleep mode. All configuration register values are stored. The low power voltage regulator is always enabled. Therefore, its bias current contributes to the leakage current in sleep mode with about 100nA (typical). The voltage regulators (AVREG, DVREG) require bypass capacitors for stable operation. The value of the bypass capacitors determine the settling time of the voltage regulators. The bypass capacitors shall be placed as close as possible to the pins and shall be connected to ground with the shortest possible traces (see Table 34-1 on page 880). 38.4.2 Configuration The voltage regulators can be configured by the register 0x10 (VREG_CTRL). It is recommended to use the internal regulators, but it is also possible to supply the low voltage domains by an external voltage supply. For this configuration, the internal regulators need to be switched off by setting the register bits to the values AVREG_EXT = 1 and DVREG_EXT = 1. A regulated external supply voltage of 1.8V needs to be connected to the DVDD and AVDD pins. When providing the external supply, ensure a sufficiently long stabilization time before interacting with the AT86RF233. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 984 38.4.3 Data Interpretation The status bits AVDD_OK = 1 and DVDD_OK = 1 in register 0x10 (VREG_CTRL) indicate an enabled and stable internal supply voltage. Reading value zero indicates a disabled or internal supply voltage not settled to the final value. Setting AVREG_EXT = 1 and DVREG_EXT = 1 forces the signals AVDD_OK and DVDD_OK to one. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 985 38.4.4 Register Description 38.4.4.1 VREG_CTRL Name: VREG_CTRL Offset: 0x10 Reset: 0x00 Property: - The VREG_CTRL register controls the use of the voltage regulators and indicates the status of these. Bit 0x10 7 6 AVREG_EXT AVDD_OK R/W R R 0 0 0 Access Reset z 5 4 3 2 DVREG_EXT DVDD_OK 1 0 R R/W 0 0 R R R 0 0 0 Bit 7 - AVREG_EXT If set this register bit disables the internal analog voltage regulator to apply an external regulated 1.8V supply for the analog building blocks. Table 38-11. AVREG_EXT Value Description 0x0 Internal voltage regulator enabled, analog section 0x1 Internal voltage regulator disabled, use external regulated 1.8V supply voltage for the analog section z Bit 6 - AVDD_OK This register bit indicates if the internal 1.8V regulated voltage supply AVDD has settled. The bit is set to logic high, if AVREG_EXT = 1. Table 38-12. AVDD_OK Value Description 0x0 Analog voltage regulator is disabled or supply voltage not stable 0x1 Analog supply voltage is stable z Bit 3 - DVREG_EXT If set this register bit disables the internal digital voltage regulator to apply an external regulated 1.8V supply for the digital building blocks. Table 38-13. DVREG_EXT Value Description 0x0 Internal voltage regulator enabled, digital section 0x1 Internal voltage regulator disabled, use external regulated 1.8V supply voltage for the digital section z Bit 2 - DVDD_OK This register bit indicates if the internal 1.8V regulated voltage supply DVDD has settled. The bit is set to logic high, if DVREG_EXT = 1. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 986 Table 38-14. DVDD_OK Value Description 0x0 Digital voltage regulator is disabled or supply voltage not stable 0x1 Digital supply voltage is stable Note: 38.5 1. While the reset value of this bit is zero, any practical access to the register is only possible when DVREG is active. So this bit is normally always read out as one. Battery Monitor (BATMON) The main features of the battery monitor are: z Configurable voltage reference threshold from 1.70V to 3.675V z Interrupt on low - supply voltage condition z Continuous BATMON status monitor as a register flag 38.5.1 Overview The AT86RF233 battery monitor (BATMON) detects and flags a low external supply voltage level provided on EVDD. The external voltage supply EVDD is continuously compared with the internal threshold voltage to detect a low voltage supply level. In this case BATMON_IRQ is triggered and BATMON_OK flag is cleared to indicate undervoltage condition, see Figure 38-7. Figure 38-7. Simplified Schematic of BATMON EVDD BATMON_HR + DAC 4 BATMON_VTH Threshold Voltage For input-to-output mapping see control register 0x11 (BATMON) BATMON_OK - 1" clear D Q BATMON_IRQ 38.5.2 Configuration The BATMON can be configured using the register 0x11 (BATMON). Register bits BATMON_VTH sets the threshold voltage. It is configurable with a resolution of 75mV in the upper voltage range (BATMON_HR = 1) and with a resolution of 50mV in the lower voltage range (BATMON_HR = 0), for details refer to register 0x11 (BATMON). 38.5.3 Data Interpretation The signal register bit BATMON_OK of register 0x11 (BATMON) monitors the current value of the battery voltage: z If BATMON_OK = 0, the battery voltage is lower than the threshold voltage z If BATMON_OK = 1, the battery voltage is higher than the threshold voltage After setting a new threshold, the value BATMON_OK should be read out to verify the current supply voltage value. Note: The battery monitor is inactive during P_ON, SLEEP, and DEEP_SLEEP states, see register bits TRX_STATUS (register 0x01, TRX_STATUS). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 987 38.5.4 Interrupt Handling A supply voltage drop below the configured threshold value is indicated by an interrupt IRQ_7 (BAT_LOW), see "Interrupt Logic" on page 896. Note: The AT86RF233 IRQ_7 (BAT_LOW) interrupt is issued only if BATMON_OK changes from one to zero. IRQ_7 (BAT_LOW) interrupt is not generated under following conditions: z The battery voltage remained below 1.8V threshold value on power-on (BATMON_OK was never one), or z A new threshold is set, which is still above the current supply voltage (BATMON_OK remains zero). When the battery voltage is close to the programmed threshold voltage, noise or temporary voltage drops may generate unwanted interrupts. To avoid this: z Disable the IRQ_7 (BAT_LOW) in register 0x0E (IRQ_MASK) and treat the battery as empty, or z Set a lower threshold value. 38.5.5 Register Description 38.5.5.1 BATMON Name: BATMON Offset: 0x11 Reset: 0x02 Property: - The BATMON register configures the battery monitor to compare the supply voltage at EVDD to the threshold. Additionally, the supply voltage status at EVDD can be read from register bit BATMON_OK according to the actual BATMON settings. Bit 7 6 0x11 5 4 BATMON_OK BATMON_HR 3 2 1 0 BATMON_VTH Access R R/W R R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 1 0 z Bit 5 - BATMON_OK The register bit BATMON_OK indicates the level of the external supply voltage with respect to the programmed threshold BATMON_VTH. Table 38-15. BATMON_OK Value Description 0x0 The battery voltage is below the threshold 0x1 The battery voltage is above the threshold z Bit 4 - BATMON_HR The register bit BATMON_HR sets the range and resolution of the battery monitor. Table 38-16. BATMON_HR Value Description 0x0 Enables the low range, see BATMON_VTH 0x1 Enables the high range, see BATMON_VTH Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 988 z Bit 3:0 - BATMON_VTH The voltage threshold values for the battery monitor are set by register bits BATMON_VTH. Table 38-17. BATMON_VTH 38.6 Value BATMON_VTH Voltage [V] BATMON_HR = 1 Voltage [V] BATMON_HR = 0 0x0 2.550 1.70 0x1 2.625 1.75 0x2 2.700 1.80 0x3 2.775 1.85 0x4 2.850 1.90 0x5 2.925 1.95 0x6 3.000 2.00 0x7 3.075 2.05 0x8 3.150 2.10 0x9 3.225 2.15 0xA 3.300 2.20 0xB 3.375 2.25 0xC 3.450 2.30 0xD 3.525 2.35 0xE 3.600 2.40 0xF 3.675 2.45 Crystal Oscillator (XOSCRF) The main crystal oscillator features are: z 16MHz amplitude controlled crystal oscillator z 180s typical settling time after leaving SLEEP state z 330s typical settling time after leaving DEEP_SLEEP state z Configurable trimming capacitance array z Configurable clock output (CLKM) 38.6.1 Overview The crystal oscillator generates the reference frequency for the AT86RF233. All other internally generated frequencies of the radio transceiver are derived from this unique frequency. Therefore, the overall system performance is mainly determined by the accuracy of crystal reference frequency. The external components of the crystal oscillator should be selected carefully and the related board layout should be done with caution (see "Application Schematic" on page 879). The register 0x12 (XOSC_CTRL) provides access to the control signals of the oscillator. Two operating modes are supported. It is recommended to use the integrated oscillator setup as described in Figure 38-8. Alternatively, a reference frequency can be fed to the internal circuitry by using an external clock reference as shown in Figure 38-9. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 989 38.6.2 Integrated Oscillator Setup Using the internal oscillator, the oscillation frequency depends on the load capacitance between the crystal XTAL1 pin and XTAL2 pin. The total load capacitance CL must be equal to the specified load capacitance of the crystal itself. It consists of the external capacitors CX and parasitic capacitances connected to the XTAL nodes. Figure 38-8 shows all parasitic capacitances, such as PCB stray capacitances and the pin input capacitance, summarized to CPAR. Figure 38-8. Simplified XOSCRF Schematic with External Components & 3$5 &; &; & 3$5 9'' XTAL1 (9'' 0+] XTAL2 3&% SAM R21 & 75,0 & 75,0 XTAL_TRIM [3:0] XTAL_TRIM [3:0] (9'' Additional internal trimming capacitors CTRIM are available. Any value in the range from 0pF to 4.5pF with a 0.3pF resolution is selectable using XTAL_TRIM of register 0x12 (XOSC_CTRL). To calculate the total load capacitance, the following formula can be used: CL[pF] = 0.5 x (CX[pF] + CTRIM[pF] + CPAR[pF]) The AT86RF233 trimming capacitors provide the possibility of reducing frequency deviations caused by production process variations or by external components tolerances. Note that the oscillation frequency can only be reduced by increasing the trimming capacitance. The frequency deviation caused by one step of CTRIM decreases with increasing crystal load capacitor values. An amplitude control circuit is included to ensure stable operation under different operating conditions and for different crystal types. Enabling the crystal oscillator in P_ON state and after leaving SLEEP or DEEP_SLEEP state causes a slightly higher current during the amplitude build-up phase to guarantee a short start-up time. At stable operation, the current is reduced to the amount necessary for a robust operation. This also keeps the drive level of the crystal low. Generally, crystals with a higher load capacitance are less sensitive to parasitic pulling effects caused by external component variations or by variations of board and circuit parasitic. On the other hand, a larger crystal load capacitance results in a longer start-up time and a higher steady state current consumption. 38.6.3 External Reference Frequency Setup When using an external reference frequency, the signal must be connected to the XTAL1 pin as indicated in Figure 38-9 and the register bits XTAL_MODE (register 0x12, XOSC_CTRL) need to be set to the external oscillator mode for power Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 990 saving reasons. The oscillation peak-to-peak amplitude shall be between 400mV and 1V. The XTAL2 pin should not be wired. It is possible, among other waveforms, to use sine and square wave signals. Note: The quality of the external reference (that is phase noise) determines the system performance. Figure 38-9. Setup for Using an External Frequency Reference 16MHz XTAL1 XTAL2 PCB SAM R21 38.6.4 Master Clock Signal Output (CLKM) The generated reference clock signal can be fed to the microcontroller using CLKM. The internal 16MHz raw clock can be divided by an internal prescaler. Thus, clock frequencies of 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 250kHz, or 62.5kHz can be supplied by CLKM. The CLKM frequency is configurable using register 0x03 (TRX_CTRL_0). There are two possibilities to change the CLKM frequency. If CLKM_SHA_SEL = 0, changing the register bits CLKM_CTRL (register 0x03, TRX_CTRL_0) immediately affects a glitch free the CLKM clock rate change. Otherwise (CLKM_SHA_SEL = 1 and CLKM_CTRL > 0 before changing the register bits CLKM_CTRL), the new clock rate is supplied when leaving the SLEEP state the next time. To reduced power consumption and spurious emissions, it is recommended to turn off the Atmel AT86RF233 CLKM clock when not in use. Notes: 1. During reset procedure, see "RESET State" on page 906, register bits CLKM_CTRL are shadowed. Although the clock setting of CLKM remains after reset, a read access to register bits CLKM_CTRL delivers the reset value one. For that reason it is recommended to write the previous configuration (before reset) to register bits CLKM_CTRL (after reset) to align the radio transceiver behavior and register configuration. Otherwise the CLKM clock rate is set back to the reset value (1MHz) after the next SLEEP cycle. For example, if the CLKM clock rate is configured to 16MHz the CLKM clock rate remains at 16MHz after a reset, however the register bits CLKM_CTRL are set back to one. Since CLKM_SHA_SEL reset value is one, the CLKM clock rate changes to 1MHz after the next SLEEP cycle if the CLKM_CTRL setting is not updated. 2. After leaving the DEEP_SLEEP state CLKM starts with the default 1MHz master clock at CLKM after the crystal oscillator has stabilized. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 991 38.6.5 Register Description 38.6.5.1 TRX_CTRL_0 Name: TRX_CTRL_0 Offset: 0x03 Reset: 0x09 Property: - The TRX_CTRL_0 register controls the CLKM clock rate. Bit 7 6 TOM_EN 0x03 Access 5 4 3 PMU_EN PMU_IF_INVERSE CLKM_SHA_SEL 2 1 0 CLKM_CTRL R/W R R/W R/W R/W R/W R/W R/W 0 0 0 0 1 0 0 1 Reset Bit 3 - CLKM_SHA_SEL The register bit CLKM_SHA_SEL defines whether a new clock rate (defined by CLKM_CTRL) is set immediately or gets effective after the next SLEEP cycle. z Table 38-18. CLKM_SHA_SEL Value Description 0x0 CLKM clock rate change appears immediately 0x1 CLKM clock rate change appears after SLEEP cycle z Bit 2:0 - CLKM_CTRL The register bits CLKM_CTRL set the clock rate of CLKM. Table 38-19. CLKM_CTRL Value Description 0x0 No clock at CLKM, signal set to logic low 0x1 1MHz 0x2 2MHz 0x3 4MHz 0x4 8MHz 0x5 16MHz 0x6 250kHz 0x7 62.5kHz (IEEE 802.15.4 symbol rate) Note: 1. If a clock rate is selected between 1MHz and 16MHz and SLP_TR is set to logic high in state TRX_OFF, the TRX delivers additional 35 clock cycles before entering state SLEEP or DEEP_SLEEP. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 992 38.6.5.2 XOSC_CTRL Name: XOSC_CTRL Offset: 0x12 Reset: 0x0F Property: - The XOSC_CTRL register controls the operation of the crystal oscillator. Bit 7 6 5 4 3 2 XTAL_MODE 0x12 Access 0 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 0 0 0 0 Reset z 1 XTAL_TRIM Bit 7:4 - XTAL_MODE The register bits XTAL_MODE sets the operating mode of the crystal oscillator. Table 38-20. XTAL_MODE Value Description 0x5 Internal crystal oscillator disabled, use external reference frequency 0xF Internal crystal oscillator enabled and XOSCRF voltage regulator enabled All other values are reserved For normal operation the default value is set to XTAL_MODE = 0xF after reset. Using an external clock source it is recommended to set XTAL_MODE = 0x5. z Bit 3:0 - XTAL_TRIM The register bits XTAL_TRIM control internal capacitance arrays connected to the XTAL1 and XTAL2 pins. Table 38-21. XTAL_TRIM 38.7 Value Description 0x0 A capacitance value in the range from 0pF to 4.5pF is selectable with a resolution of 0.3pF. Valid values are [0xF, 0xE, ..., 0x0]. Frequency Synthesizer (PLL) The main PLL features are: z Generate RX/TX frequencies for all IEEE 802.15.4 - 2.4GHz channels z Generate RX/TX frequencies from 2360MHz to 2480MHz z Autonomous calibration loops for stable operation within the operating range z Two PLL-interrupts for status indication z Fast PLL settling to support frequency hopping 38.7.1 Overview The PLL generates the RF frequencies for the AT86RF233. During receive operation the frequency synthesizer works as a local oscillator on the radio transceiver receive frequency, during transmit operation the voltage-controlled oscillator (VCO) is directly modulated to generate the RF transmit signal. The frequency synthesizer is implemented as a fractional-N PLL. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 993 Two calibration loops ensure correct PLL functionality within the specified operating limits. 38.7.2 RF Channel Selection The PLL is designed to support 16 channels in the 2.4GHz ISM band with channel spacing of 5MHz according to IEEE 802.15.4. The center frequency of these channels is defined as follows: Fc[MHz] = 2405[MHz] + 5[MHz] x (k - 11), for k = 11, 12, ..., 26 where k is the channel number. The channel k is selected by register bits CHANNEL (register 0x08, PHY_CC_CA). Additionally, the PLL supports all frequencies from 2360MHz to 2480MHz with 500kHz frequency spacing. The frequency is selected by register bits CC_BAND (registers 0x14, CC_CTRL_1) and register bits CC_NUMBER (registers 0x13, CC_CTRL_0). Table 38-22 shows the settings of the register bits CC_BAND and CC_NUMBER. Table 38-22. Frequency Bands and Numbers CC_BAND CC_NUMBER Description 0x0 Not used Channels according to IEEE 802.15.4; frequency selected by register bits CHANNEL (register 0x08, PHY_CC_CCA) 0x1, ..., 0x7 0x00 - 0xFF Reserved 0x8 0x00 - 0x6B Reserved 0x8 0x6C - 0xFF 2360MHz - 2433.5MHz Fc[MHz] = 2306[MHz] + 0.5[MHz] x CC_NUMBER 0x9 0x00 - 0x5C 2434MHz - 2480MHz. Fc[MHz] = 2434[MHz] + 0.5[MHz] x CC_NUMBER 0x9 0x5D - 0xFF Reserved 0xA, ..., 0xF 0x00 - 0xFF Reserved 38.7.3 PLL Settling Time and Frequency Agility When the PLL is enabled during state transition from TRX_OFF to PLL_ ON or RX_ON, the settling time is typically tTR4 = 80s, including settling of the analog voltage regulator (AVREG) and PLL self calibration, refer to Table 36-2 on page 912. A lock of the PLL is indicated with an interrupt IRQ_0 (PLL_LOCK). Switching between 2.4GHz ISM band channels in PLL_ON or RX_ON states is typically done within tPLL_SW = 11s. This makes the radio transceiver highly suitable for frequency hopping applications. The PLL frequency in PLL_ON and receive states is 2MHz below the PLL frequency in transmit states. When starting the transmit procedure, the PLL frequency is changed to the transmit frequency within a period of tRX_TX = 16s before really starting the transmission. After the transmission, the PLL settles back to the receive frequency within a period of tTX_RX = 32s. This frequency step does not generate an interrupt IRQ_0 (PLL_LOCK) or IRQ_1 (PLL_UNLOCK) within these periods. 38.7.4 Calibration Loops Due to variation of temperature, supply voltage and part-to-part variations of the radio transceiver the VCO characteristics may vary. To ensure a stable operation, two automated control loops are implemented, center frequency (CF) tuning and delay cell (DCU) calibration. Both calibration loops are initiated automatically when the PLL is enabled during state transition from Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 994 TRX_OFF to PLL_ON or RX_ON state. Additionally, both calibration loops are initiated when the PLL changes to a different frequency setting. If the PLL operates for a long time on the same channel, for example more than five minutes, or the operating temperature changes significantly, it is recommended to initiate the calibration loops manually. Both AT86RF233 calibration loops can be initiated manually by SPI command. To start the calibration, the device should be in state PLL_ON. The center frequency calibration can be initiated by setting PLL_CF_START = 1 (register 0x1A, PLL_CF). The calibration loop is completed when the IRQ_0 (PLL_LOCK) occurs, if enabled. The duration of the center frequency calibration loop depends on the difference between the current CF value and the final CF value. During the calibration, the CF value is incremented or decremented. Each step takes tPLL_CF = 8s. The minimum time is 8s; the maximum time is 24s. The recommended procedure to start the center frequency calibration is to read the register 0x1A (PLL_CF), to set the PLL_CF_START register bit to one, and to write the value back to the register. The delay cell calibration can be initiated by setting the bit PLL_DCU_START of register 0x1B (PLL_DCU) to one. The delay time of the programmable delay unit is adjusted to the correct value. The calibration works as successive approximation and is independent of the values in the register 0x1B (PLL_DCU). The duration of the calibration is tPLL_DCU = 6s. During both calibration processes, no correct receive or transmit operation is possible. The recommended state for the calibration is therefore PLL_ON, but calibration is not blocked at receive or transmit states. Both calibrations can be executed concurrently. 38.7.5 Interrupt Handling Two different interrupts indicate the PLL status (refer to register 0x0F). IRQ_0 (PLL_LOCK) indicates that the PLL has locked. IRQ_1 (PLL_UNLOCK) interrupt indicates an unexpected unlock condition. A PLL_LOCK interrupt clears any preceding PLL_UNLOCK interrupt automatically and vice versa. An IRQ_0 (PLL_LOCK) interrupt is supposed to occur in the following situations: z State change from TRX_OFF to PLL_ON / RX_ON / TX_ARET_ON / RX_AACK_ON z Frequency setting change in states PLL_ON / RX_ON / TX_ARET_ON / RX_AACK_ON z A manually started center frequency calibration has been completed All other PLL_LOCK interrupt events indicate that the PLL locked again after a prior unlock happened. An IRQ_1 (PLL_UNLOCK) interrupt occurs in the following situations: z A manually initiated center frequency calibration in states PLL_ON / (RX_ON) z Frequency setting change in states PLL_ON / RX_ON Any other occurrences of IRQ_1 (PLL_UNLOCK) indicate erroneous behavior and require checking of the actual device status. PLL_LOCK and PLL_UNLOCK affect the behavior of the transceiver: In states BUSY_TX and BUSY_TX_ARET the transmission is stopped and the transceiver returns into state PLL_ON. During BUSY_RX and BUSY_RX_AACK, the transceiver returns to state RX_ON and RX_AACK_ON, respectively, once the PLL has locked. Notes: 1. 2. An AT86RF233 interrupt IRQ_0 (PLL_LOCK) clears any preceding IRQ_1 (PLL_UNLOCK) interrupt automatically and vice versa. The state transition from BUSY_TX / BUSY_TX_ARET to PLL_ON / TX_ARET_ON after successful transmission does not generate an IRQ_0 (PLL_LOCK) within the settling period. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 995 38.7.6 Register Description 38.7.6.1 PHY_CC_CCA Name: PHY_CC_CCA Offset: 0x08 Reset: 0x2B Property: - The PHY_CC_CCA register is a multi-purpose register that controls CCA configuration, CCA measurement, and the IEEE 802.15.4 channel setting. Bit 7 6 CCA_REQUEST 0x08 Access Reset z 5 4 3 CCA_MODE 2 1 0 CHANNEL R/W R/W R/W R/W R/W R/W R/W R/W 0 0 1 0 1 0 1 1 Bit 4:0 - CHANNEL The register bits CHANNEL define the RX/TX channel. The channel assignment is according to IEEE 802.15.4. Table 38-23. CHANNEL Value Description 0x0B 2405MHz 0x0C 2410MHz 0x0D 2415MHz 0x0E 2420MHz 0x0F 2425MHz 0x10 2430MHz 0x11 2435MHz 0x12 2440MHz 0x13 2445MHz 0x14 2450MHz 0x15 2455MHz 0x16 2460MHz 0x17 2465MHz 0x18 2470MHz 0x19 2475MHz 0x1A 2480MHz All other values are reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 996 38.7.6.2 CC_CTRL_0 Name: CC_CTRL_0 Offset: 0x13 Reset: 0x00 Property: - The CC_CTRL_0 register controls the frequency selection, if the selection by CHANNEL (register 0x08, PHY_CC_CCA) is not used. Bit 7 6 5 4 3 2 1 0 CC_NUMBER 0x13 Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 1 0 Bit 7:0 - CC_NUMBER Table 38-24. CC_NUMBER Value 0x00 Description Alternative frequency selection with 500kHz frequency spacing CC_BAND = 0x0: Not used CC_BAND = 0x8: Valid values are [0xFF, 0xFE, ..., 0x6C] CC_BAND = 0x9: Valid values are [0x5C, 0x5B, ..., 0x00] All other values are reserved 38.7.6.3 CC_CTRL_1 Name: CC_CTRL_1 Offset: 0x14 Reset: 0x00 Property: - The CC_CTRL_1 register controls the selection of the frequency bands. Bit 7 6 5 4 3 2 Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 CC_BAND 0x14 z Bit 3:0 - CC_BAND The register bits CC_BAND control the selection for IEEE 802.15.4 channel band and additional frequencies bands. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 997 Table 38-25. CC_BAND Value Description 0x0 The IEEE 802.15.4 channel within register bits CHANNEL is selected 0x8 The frequency band 0x8 is selected 0x9 The frequency band 0x9 is selected All other values are reserved If the register bits CC_BAND and CC_NUMBER are used, the frequency mapping is described in Table 38-22. 38.7.6.4 PLL_CF Name: PLL_CF Offset: 0x1A Reset: 0x57 Property: - The PLL_CF register controls the operation of the center frequency calibration loop. Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 1 0 1 0 1 1 1 PLL_CF_START 0x1A Access Reset z PLL_CF Bit 7 - PLL_CF_START Manual start of center frequency calibration cycle. Table 38-26. PLL_CF_START Value Description 0x0 Center frequency calibration cycle is finished 0x1 Initiates center frequency calibration cycle PLL_CF_START = 1 initiates the center frequency calibration. The calibration cycle has finished after tPLL_CF = 8s (typ.). The register bit is cleared immediately after finishing the calibration. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 998 38.7.6.5 PLL_DCU Name: PLL_DCU Offset: 0x1B Reset: 0x20 Property: - The PLL_DCU register controls the operation of the delay cell calibration loop. Bit 7 6 5 4 3 2 1 0 R/W R R/W R/W R/W R/W R/W R/W 0 0 1 0 0 0 0 0 PLL_DCU_START 0x1B Access Reset z Bit 7 - PLL_DCU_START Manual start of delay cell calibration cycle. Table 38-27. PLL_DCU_START Value Description 0x0 Delay cell calibration cycle is finished 0x1 Initiates delay cell calibration cycle PLL_DCU_START = 1 initiates the delay cell calibration. The calibration cycle has finished after tPLL_DCU = 6s. The register bit is cleared immediately after finishing the calibration. 38.7.6.6 TST_SDM Name: TST_SDM Offset: 0x3D Reset: 0x00 Property: - Bit 0x3D 7 6 5 4 MOD_SEL MOD TX_RX TX_RX_SEL R/W R/W R/W 0 0 0 Access Reset Note: z 3 2 1 0 R/W R/W R/W R/W R/W 0 0 0 0 0 The register bits can be read or written, the values will effect the device operation only if the register bit PMU_EN (register 0x03, TRX_CTRL_0) is set, otherwise reset values will be applied. Bit 7 - MOD_SEL The register bit MOD_SEL controls the modulation data source mode. Table 38-28. MOD_SEL Value Description 0x0 Normal operation is selected 0x1 Manual control of modulation data source is selected. Used setting from register bit MOD. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 999 z Bit 6 - MOD The register bit MOD controls the manual modulation signal setting. Table 38-29. MOD Value Description 0x0 Continuous 0 chips 0x1 Continuous 1 chips z Bit 5 - TX_RX The register bit TX_RX controls the TX and RX PLL frequency setting within manual control mode. Table 38-30. TX_RX Value Description 0x0 RX PLL frequency is selected 0x1 TX PLL frequency is selected z Bit 4 - TX_RX_SEL The register bit TX_RX_SEL controls the PLL frequency control mode. Table 38-31. TX_RX_SEL Value Description 0x0 Normal operation is selected 0x1 Manual control of PLL TX/RX frequency mode is selected. Used setting from register bit TX_RX. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1000 38.8 Automatic Filter Tuning (FTN) 38.8.1 Overview The AT86RF233 FTN is incorporated to compensate device tolerances for temperature, supply voltage variations as well as part-to-part variations of the radio transceiver. The filter-tuning result is used to correct the analog baseband filter transfer function and the PLL loop-filter time constant, refer to "General Circuit Description" on page 15. An FTN calibration cycle is initiated automatically when entering the TRX_OFF state from the P_ON, SLEEP, DEEP_SLEEP, or RESET state. Although receiver and transmitter are very robust against these variations, it is recommended to initiate the FTN manually if the radio transceiver does not use the SLEEP or DEEP_SLEEP states. If necessary, a calibration cycle is to be initiated in states TRX_OFF, PLL_ON or RX_ON. This applies in particular for the High Data Rate Modes with a much higher sensitivity against BPF transfer function variations. The recommended calibration interval is five minutes or less, if the AT86RF233 operates always in an active state (PLL_ON, TX_ARET_ON, RX_ON, and RX_AACK_ON). 38.8.2 Register Description 38.8.2.1 FTN_CTRL Name: FTN_CTRL Offset: 0x18 Reset: 0x58 Property: - The FTN_CTRL register controls the operation of the filter tuning network calibration loop. Bit 7 6 5 4 3 FTN_START 0x18 Access Reset z 2 1 0 FTNV R/W R/W R/W R/W R/W R/W R/W R/W 0 1 0 1 1 0 0 0 Bit 7 - FTN_START Manual start of a filter calibration cycle. Table 38-32. FTN_START Value Description 0x0 Filter calibration is finished 0x1 Initiates filter calibration cycle FTN_START = 1 initiates the filter tuning network calibration. When the calibration cycle has finished after tFTN = 25s (typ.). The register bit is cleared immediately after finishing the calibration. z Bit 5:0 - FTNV Filter tuning value used for internal calibration loops. Table 38-33. FTNV Value Description 0x18 Register bits FTNV defines the filter tuning value. Valid values are [0x3F, 0x3E, ..., 0x00]. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1001 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1002 39. AT86RF233 Radio Transceiver Usage 39.1 Frame Receive Procedure This section describes basic procedures to receive and transmit frames using the AT86RF233. For a detailed programming description refer to reference [7]. A frame reception comprises of two actions: The transceiver listens for, receives, and demodulates the frame to the Frame Buffer and signals the reception to the microcontroller. After or during that process, the microcontroller can read the available frame data from the Frame Buffer via the SPI interface. While being in state RX_ON or RX_AACK_ON, the radio transceiver searches for incoming frames on the selected channel. Assuming the appropriate interrupts are enabled, the detection of a frame is indicated by interrupt IRQ_2 (RX_START). When the frame reception is completed, interrupt IRQ_3 (TRX_END) is issued. Different Frame Buffer read access scenarios are recommended for: Non-time critical applications read access starts after IRQ_3(TRX_END) Time-critical applications read access starts after IRQ_2(RX_START) For non-time-critical operations, it is recommended to wait for interrupt IRQ_3 (TRX_END) before starting a Frame Buffer read access. Figure 39-1 illustrates the frame receive procedure using IRQ_3 (TRX_END). Figure 39-1. Transactions between AT86RF233 and Microcontroller during Receive Read IRQ status , IRQ signal deasserted IRQ issued (IRQ_3) Read IRQ status , IRQ signal deasserted Microcontroller AT86RF233 IRQ issued (IRQ_2) Read frame data (Frame Buffer access) Critical protocol timing could require starting the Frame Buffer read access after interrupt IRQ_2 (RX_START). The first byte of the frame data can be read 32s after the IRQ_2 (RX_START) interrupt. The microcontroller must ensure to read slower than the frame is received. Otherwise a Frame Buffer under run occurs, IRQ_6 (TRX_UR) is issued, and the frame data may be not valid. To avoid this, the Frame Buffer read access can be controlled by using a Frame Buffer Empty indicator, refer to "Frame Buffer Empty Indicator" on page 1030. 39.2 Frame Transmit Procedure A frame transmission comprises of two actions, a write to Frame Buffer and the transmission of its contents. Both actions can be run in parallel if required by critical protocol timing. Figure 39-2 illustrates the AT86RF233 frame transmit procedure, when writing and transmitting the frame consecutively. After a Frame Buffer write access, the frame transmission is initiated by asserting the SLP_TR signal or writing command TX_START to register bits TRX_CMD (register 0x02, TRX_STATE). The transceiver must be either in PLL_ON state for basic operating mode or TX_ARET_ON state for extended operating mode. The completion of the transaction is indicated by interrupt IRQ_3 (TRX_END). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1003 Figure 39-2. Transaction between AT86RF233 and Microcontroller during Transmit Write TRX_CMD = TX_START, or assert SLP_TR signal IRQ_3 (TRX_END) issued Microcontroller AT86RF233 Write frame data (Frame Buffer access) Read IRQ_STATUS register, IRQ signal deasserted Alternatively for time critical applications when the frame start transmission time needs to be minimized, a frame transmission task can be started first. Then it can be followed by the Frame Buffer write access event (populating PSDU data). This way the data to be transmitted is needs to be written in the transmit frame buffer as the transceiver initializes and begins SHR transmission; refer to Figure 39-3. By initiating a transmission, either by asserting the SLP_TR signal or writing a TX_START command to register bits TRX_CMD (register 0x02, TRX_STATE), the radio transceiver starts transmitting the SHR, which is internally generated. This first phase requires for PLL settling and 160s for SHR transmission. The PHR must be available in the Frame Buffer before this time elapses. Furthermore the SPI data rate must be higher than the PHY data rate selected by register bits OQPSK_DATA_RATE (register 0x0C, TRX_CTRL_2) to ensure that no Frame Buffer under run occurs. Figure 39-3. Time Optimized Frame Transmit Procedure. Microcontroller AT86RF233 Write TRX_CMD = TX_START, or assert SLP_TR signal Write frame data (Frame Buffer access) IRQ_3 (TRX_END) issued Read IRQ_STATUS register, IRQ signal deasserted Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1004 40. AT86RF233 Extended Feature Set 40.1 Security Module (AES) The security module (AES) features include: z Hardware accelerated encryption and decryption z Compatible with AES-128 standard (128-bit key and data block size) z ECB (encryption/decryption) mode and CBC (encryption) mode support z Stand-alone operation, independent of other blocks 40.1.1 Overview The security module is based on an AES-128 core according to FIPS197 standard, refer to [6]. The security module works independently of other building blocks of the AT86RF233. Encryption and decryption can be performed in parallel with a frame transmission or reception. The control of the security block is implemented as an SRAM access to address space 0x82 to 0x94. A Fast SRAM access mode allows for simultaneous new data writes and reads of processed data within the same SPI transfer. This access procedure is used to reduce the turnaround time for ECB and CBC modes, see "Data Transfer - Fast SRAM Access" on page 1009. In addition, the security module contains another 128-bit register to store the initial key used for security operations. This initial key is not modified by the security module. 40.1.2 Security Module Preparation The use of the security module requires a configuration of the security engine before starting a security operation. The following steps are required: Table 40-1. AES Engine Configuration Steps Step 1 Description Key Setup Section Write encryption or decryption key to SRAM "Security Key Setup" on page 1006 Select AES mode: ECB or CBC "Electronic Code Book (ECB)" on page 1006 2 AES mode 3 Write Data Write plaintext or cipher text to SRAM 4 Start operation Start AES operation 5 Read Data Read cipher text or plaintext from SRAM Select encryption or decryption "Cipher Block Chaining (CBC)" on page 1008 "Data Transfer - Fast SRAM Access" on page 1009 "Data Transfer - Fast SRAM Access" on page 1009 Before starting any security operation, a key must be written to the security engine, refer to "Security Key Setup" on page 1006. The key set up requires the configuration of the AES engine KEY mode using register bits AES_MODE (SRAM address 0x83, AES_CTRL). The following step selects the AES mode, either electronic code book (ECB) or cipher block chaining (CBC). These modes are explained in more detail in "Security Operation Modes" on page 1006. Further, encryption or decryption must be selected with register bit AES_DIR (SRAM address 0x83, AES_CTRL). After this, the 128-bit plain text or cipher text data has to be provided to the AES hardware engine. The data uses the SRAM address range 0x84 - 0x93. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1005 An encryption or decryption is initiated with register bit AES_REQUEST = 1 (SRAM address 0x83, that is AES_CTRL, or the mirrored version SRAM address 0x94, that is AES_CTRL_MIRROR). The AES module control registers are only accessible using SRAM read and write accesses on address space 0x82 to 0x94. Configuring the AES mode, providing the data, and starting a decryption or encryption operation can be combined in a single SRAM access. Notes: 1. 2. 3. 4. No additional register access is required to operate the security block. Access to the security block is not possible while the radio transceiver is in SLEEP, DEEP_SLEEP, or RESET state. All configurations of the security module, the SRAM content, and keys are reset during DEEP_SLEEP or RESET state. A read or write access to register 0x83 (AES_CTRL) during AES operation terminates the current processing. 40.1.3 Security Key Setup The setup of the key is prepared by setting register bits AES_MODE = 1 (SRAM address 0x83, AES_CTRL). Afterwards the 128-bit key must be written to SRAM addresses 0x84 through 0x93 (registers AES_KEY). It is recommended to combine the setting of control register 0x83 (AES_CTRL) and the 128-bit key transfer using only one SRAM access starting from address 0x83. The address space for the 128-bit key and 128-bit data is identical from programming point of view. However, both use different pages which are selected by register bit AES_MODE before storing the data. A read access to registers AES_KEY (0x84 - 0x93) returns the last round key of the preceding security operation. After an ECB encryption operation, this is the key that is required for the corresponding ECB decryption operation. However, the initial AES key, written to the security module in advance of an AES run, see step one in Table 40-1 on page 1005, is not modified during the AES operation. This initial key is used for the next AES run even it cannot be read from AES_KEY. Note: 1. ECB decryption is not required for IEEE 802.15.4 or ZigBee security processing. The AT86RF233 provides this functionality as an additional feature. 40.1.4 Security Operation Modes 40.1.4.1 Electronic Code Book (ECB) ECB is the basic operating mode of the security module. After setting up the initial AES key, register bits AES_MODE = 0 (SRAM address 0x83, AES_CTRL) sets up ECB mode. Register bit AES_DIR (SRAM address 0x83, AES_CTRL) selects the direction, either encryption or decryption. The data to be processed has to be written to SRAM addresses 0x84 through 0x93 (registers AES_STATE). An example for a programming sequence is shown in Figure 40-1. This example assumes a suitable key has been loaded before. A security operation can be started within one SRAM access by appending the start command AES_REQUEST = 1 (register 0x94, AES_CTRL_MIRROR) to the SPI sequence. Register AES_CTRL_MIRROR is a mirrored version of register 0x83 (AES_CTRL). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1006 Figure 40-1. ECB Programming SPI Sequence - Encryption byte 0 (cmd.) byte 1 (address) byte 2 (AES cmd) 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 SRAM write 0x83 byte 3 data_0[7:0] .... byte 18 byte 19 (AES cmd) data_15[7:0] 1 0 0 0 0 0 0 0 ECB, encryption AES start Summarizing, the following steps are required to perform a security operation using only one Atmel AT86RF233 SPI access: 1. 2. Configure SPI access: 1. SRAM write, refer to "SRAM Access Mode" on page 888 2. Start address 0x83 Configure AES operation: 1. 3. Write 128-bit data block: 1. 4. address 0x83: select ECB mode, direction addresses 0x84 - 0x93: either plain or ciphertext Start AES operation: 1. address 0x94: start AES operation, ECB mode This sequence is recommended because the security operation is configured and started within one SPI transaction. The ECB encryption operation is illustrated in Figure 40-2. Figure 40-3 shows the ECB decryption mode, which is supported in a similar way. Figure 40-2. ECB Mode - Encryption Plaintext Encryption Key Block Cipher Encryption Ciphertext Plaintext Encryption Key Block Cipher Encryption Ciphertext Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1007 Figure 40-3. ECB Mode - Decryption Ciphertext Decryption Key Ciphertext Block Cipher Decryption Decryption Key Plaintext Block Cipher Decryption Plaintext When decrypting, due to the nature of AES algorithm, the initial key to be used is not the same as the one used for encryption, but rather the last round key instead. This last round key is the content of the key address space stored after running one full encryption cycle, and must be saved for decryption. If the decryption key has not been saved, it has to be recomputed by first running a dummy encryption (of an arbitrary plaintext) using the original encryption key, then fetching the resulting round key from the key memory, and writing it back into the key memory as the decryption key. ECB decryption is not used by either IEEE 802.15.4 or ZigBee frame security. Both of these standards do not directly encrypt the payload, but rather a nonce instead, and protect the payload by applying an XOR operation between the resulting (AES-) cipher text and the original payload. As the nonce is the same for encryption and decryption only ECB encryption is required. Decryption is performed by XORing the received cipher text with its own encryption result respectively, which results in the original plaintext payload upon success. 40.1.4.2 Cipher Block Chaining (CBC) In CBC mode, the result of a previous AES operation is XORed with the new incoming vector, forming the new plaintext to encrypt, see Figure 40-4. This mode is used for the computation of a cryptographic checksum (message integrity code, MIC). Figure 40-4. CBC Mode - Encryption Plaintext Encryption Key Initialization Vector (IV) Block Cipher Encryption Plaintext Encryption Key Block Cipher Encryption Ciphertext Ciphertext ECB mode CBC mode After preparing the AES key and defining the AES operation direction using Atmel AT86RF233 SRAM register bit AES_DIR, the data has to be provided to the AES engine and the CBC operation can be started. The first CBC run has to be configured as ECB to process the initial data (plaintext XORed with an initialization vector provided by the microcontroller). All succeeding AES runs are to be configured as CBC by setting register bits AES_MODE = 2 (register 0x83, AES_CTRL). Register bit AES_DIR (register 0x83, AES_CTRL) must be set to Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1008 AES_DIR = 0 to enable AES encryption. The data to be processed has to be transferred to the SRAM starting with address 0x84 to 0x93 (register AES_STATE). Setting register bit AES_REQUEST = 1 (register 0x94, AES_CTRL_MIRROR) as described in "Security Operation Modes" on page 1006 starts the first encryption within one SRAM access. This causes the next 128 bits of plaintext data to be XORed with the previous cipher text data, see Figure 40-4. According to IEEE 802.15.4 the input for the very first CBC operation has to be prepared by a XORing a plaintext with an initialization vector (IV). The value of the initialization vector is zero. However, for non-compliant usage any other initialization vector can be used. This operation has to be prepared by the microcontroller. Note: 1. The IEEE 802.15.4-2006 standard MIC algorithm requires CBC mode encryption only, as it implements a oneway hash function. 40.1.5 Data Transfer - Fast SRAM Access The ECB and CBC modules including the AES core are clocked with 16MHz. One AES operation takes tAES = 23.4s to execute, refer to Table 36-2 on page 912. That means that the processing of the data is usually faster than the transfer of the data via the SPI interface. To reduce the overall processing time the AT86RF233 provides a Fast SRAM access for the address space 0x82 to 0x94. Figure 40-5. Packet Structure - Fast SRAM Access Mode AES run #n AES run #0 AES access #1 AES access #n+1 MOSI cmd add cfg P0 P1 ... P14 P15 start cmd add cfg P0 P1 ... P14 P15 start MISO stat xx ... stat xx ... C13 C14 C15 xx xx 0x83 Address xx xx ... xx xx 0x94 xx xx C0 0x83 ... byte 1 (addr.) byte 2 (cfg) byte 3 byte 4 MOSI SRAM write address 0x83 <AES_CTRL> P0[7:0] P1[7:0] MISO PHY_STATUS XX XX XX C0[7:0] 0x83 0x84 0x85 Note: 1. cmd add cfg xx stat xx xx xx ... xx C0 xx xx start ... C13 C14 C15 0x83 0x94 byte 0 (cmd) Address ... AES access #0 ... byte 18 byte 19 (start) ... P15[7:0] <AES_CTRL>(1) ... C14[7:0] C15[7:0] 0x93 0x94 0x94 Byte 19 is the mirrored version of register AES_CTRL on SRAM address 0x94, see register description AES_CTRL_MIRROR for details. In contrast to a standard SRAM access, refer to "SRAM Access Mode" on page 888, the Fast SRAM access allows writing and reading of data simultaneously during one SPI access for consecutive AES operations (AES run). For each byte P0 transferred to MOSI for example in "AES access #1", see Figure 40-5 (lower part), the previous content of the respective AES register C0 is clocked out at MISO with an offset of one byte. In the example shown in Figure 40-5 the initial plaintext P0 - P15 is written to the SRAM within "AES access #0". The last command on address 0x94 (AES_CTRL_MIRROR) starts the AES operation ("AES run #0"). In the next "AES access #1" new plaintext data P0 - P15 is written to the SRAM for the second AES run, in parallel the ciphertext C0 - C15 from the first AES run is clocked out at MISO. To read the ciphertext from the last "AES run #(n)" one dummy "AES access #(n+1)" is needed. Note: 2. The SRAM write access always overwrites the previous processing result. The Fast SRAM access automatically applies to all write operations to SRAM addresses 0x82 to 0x94. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1009 40.1.6 Start of Security Operation and Status A security operation is started within one AT86RF233 SRAM access by appending the start command AES_REQUEST = 1 (register 0x94, AES_CTRL_MIRROR) to the SPI sequence. Register AES_CTRL_MIRROR is a mirrored version of register 0x83 (AES_CTRL). The status of the security processing is indicated by register 0x82 (AES_STATUS). After tAES = 24s (max.) AES processing time register bit AES_DONE changes to one (register 0x82, AES_STATUS) indicating that the security operation has finished. 40.1.7 SRAM Register Summary The following registers are required to control the security module: Table 40-2. SRAM Security Module Address Space Overview ARAM Addr Register Name Description 0x80 - 0x81 Reserved 0x82 AES_STATUS AES status 0x83 AES_CTRL Security module control, AES mode Depends on AES_MODE setting: 0x84 - 0x93 AES_MODE = 1: AES_KEY - Contains AES_KEY (key) AES_MODE = 0 or 2: AES_STATE 0x94 - Contains AES_STATE (128 bit data block) AES_CTRL_MIRROR 0x95 - 0xFF Mirror of register 0x83 (AES_CTRL) Reserved These registers are only accessible using SRAM write and read accesses, for details refer to "SRAM Access Mode" on page 888. Note: 1. The AES registers are reset when entering the DEEP_SLEEP state. 40.1.8 SRAM Register Description 40.1.8.1 AES_STATUS Name: AES_STATUS Offset: 0x82 Reset: 0x00 Property: - The read-only register AES_STATUS signals the status of the security module and operation. Bit 7 6 5 4 3 2 1 AES_ER 0x82 0 AES_DONE Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bit 7 - AES_ER This SRAM register bit indicates an error of the AES module. An error may occur for instance after an access to SRAM register 0x83 (AES_CTRL) while an AES operation is running or after reading less than 128-bits from SRAM register space 0x84 - 0x93 (AES_STATE). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1010 Table 40-3. AES Error Value Description 0x0 No error of the AES module 0x1 AES module error z Bit 0 - AES_DONE: AES Done The bit AES_DONE signals the status of AES operation. Table 40-4. AES Done Value Description 0x0 AES operation has not been completed 0x1 AES operation has been completed 40.1.8.2 AES_CTRL Name: AES_CTRL Offset: 0x83 Reset: 0x00 Property: - The AES_CTRL register controls the operation of the security module. Bit 7 6 AES_REQUEST 0x83 5 4 AES_MODE 3 2 1 0 AES_DIR Access W R/W R/W R/W R/W R R R Reset 0 0 0 0 0 0 0 0 Notes: 1. 2. z Do not access this register during AES operation to read the AES core status. A read or write access during AES operation stops the actual processing. To read the AES status use register bit AES_DONE in "AES_STATUS" on page 1010. Bit 7 - AES_REQUEST A write access with AES_REQUEST = 1 initiates the AES operation. Table 40-5. AES Request Value Description 0x0 Security module, AES core idle 0x1 A write access starts the AES operation z Bit 6:4 - AES_MODE This register bit sets the AES operation mode. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1011 Table 40-6. AES Mode Value Description 0x0 ECB mode 0x1 KEY mode 0x2 CBC mode 0x3 - 0x7 Reserved z Bit 3 - AES_DIR: AES Direction The register bit AES_DIR sets the AES operation direction, either encryption or decryption. Table 40-7. AES Direction Value Description 0x0 AES encryption (ECB, CBC) 0x1 AES decryption (ECB) 40.1.8.3 AES_CTRL_MIRROR Name: AES_CTRL_MIRROR Offset: 0x94 Reset: 0x00 Property: - AES_CTRL_MIRROR is a mirrored version of "AES_CTRL" on page 1011. Refer to "AES_CTRL" on page 1011 for details. This register could be used to start a security operation within a single SRAM access by appending it to the data stream and setting register bit AES_REQUEST = 1. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1012 40.2 Random Number Generator 40.2.1 Overview The AT86RF233 incorporates a two bit truly random number generator by observation of noise. This random number can be used to: z Generate random seeds for CSMA-CA algorithm, see "Extended Operating Mode" on page 915 z Generate random values for AES key generation, see "Security Module (AES)" on page 1005 Random numbers are stored in register bits RND_VALUE (register 0x06, PHY_RSSI). The random number is updated every tRND = 1s in Basic Operation Mode receive states. The Random Number Generator does not work if the preamble detector is disabled (RX_PDT_DIS = 1, refer to "Register Description" on page 976). 40.2.2 Register Description 40.2.2.1 PHY_RSSI Name: PHY_RSSI Offset: 0x06 Reset: 0x60 Property: - The PHY_RSSI register is a multi-purpose register that indicates FCS validity, to provide random numbers, and a RSSI value. Bit 7 RX_CRC_VALID 0x06 6 5 4 3 2 RND_VALUES 1 0 RSSI Access R R R R R R R R Reset 0 1 1 0 0 0 0 0 z Bit 6:5 - RND_VALUE The 2-bit random value can be retrieved by reading register bits RND_VALUE. Table 40-8. RND Value Value Description 0x3 Deliver two bit noise value within receive state. Valid values are [3, 2, ..., 0]. Note: 40.3 1. The radio transceiver shall be in Basic Operating Mode receive state. High Data Rate Modes Note: Only applicable for T = -40C to 85C. The main features are: z High Data Rate Transmission up to 2000kb/s. z Support of Basic and Extended Operating Mode z Support of other features of the Extended Feature Set 40.3.1 Overview The AT86RF233 also supports alternative data rates, higher than 250kb/s for applications beyond IEEE 802.15.4 compliant networks. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1013 The selection of a data rate does not affect the remaining functionality. Thus it is possible to run all features and operating modes of the radio transceiver in various combinations. The data rate can be selected by writing to register bits OQPSK_DATA_RATE (register 0x0C, TRX_CTRL_2). The High Data Rate Modes occupy the same RF channel bandwidth as the IEEE 802.15.4 - 2.4GHz 250kb/s standard mode. Due to the decreased spreading factor, the sensitivity of the receiver is reduced accordingly. Table 40-9 shows typical values of the sensitivity for different data rates. Table 40-9. High Data Rate Sensitivity for AWGN channel High Data Rate Sensitivity Description 250kb/s -101dBm PER 1%, PSDU length of 20 octets 500kb/s -96dBm PER 1%, PSDU length of 20 octets 1000kb/s -94dBm PER 1%, PSDU length of 20 octets 2000kb/s -88dBm PER 1%, PSDU length of 20 octets By default there is no header based signaling of the data rate within a transmitted frame. Thus nodes using a data rate other than the default IEEE 802.15.4 data rate of 250kb/s are to be configured in advance and consistently. Alternatively, the configurable start of frame delimiter (SFD) could be used as an indicator of the PHY data rate, see "Alternate StartOf-Frame Delimiter" on page 1033. 40.3.2 High Data Rate Packet Structure In order to allow appropriate frame synchronization, AT86RF233 higher data rate modulation is restricted to the payload octets only. The SHR and the PHR field are transmitted with the IEEE 802.15.4 compliant data rate of 250kb/s, refer to "PHY Protocol Data Unit (PPDU)" on page 947. A comparison of the general packet structure for different data rates with an example PSDU length of 80 octets is shown in Figure 40-6. Figure 40-6. High Data Rate Frame Structure 500 kb/s PSDU: 80 octets 1000 kb/s PSDU: 80 octets 2000 kb/s PSDU: 80 octets 1472 2752 time [s] FCS SFD PHR PSDU: 80 octets 832 FCS 250 kb/s SFD PHR 512 SFD PHR 192 SFD PHR 0 Due to the overhead caused by the SHR, PHR as well as the FCS, the effective data rate is lower than the selected data rate. This is also affected by the length of the PSDU. A graphical representation of the effective PSDU data rate is shown in Figure 40-7. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1014 Figure 40-7. Effective Data Rate "B" for O-QPSK High Data Rate Modes 1600 2000 1000 500 250 1400 1200 B [kb/s] 1000 2000 kb/s 800 1000 kb/s 600 500 kb/s 400 250 kb/s 200 0 0 20 40 60 80 100 120 PSDU length in octets The effective throughput is further affected by the MAC overhead, the acknowledgment scheme as well as the microcontroller processing capability. Consequently, High Data Rate transmission and reception is useful for large PSDU lengths due to the higher effective data rate, or to reduce the power consumption of the system. When using High Data Rate Modes the active on-air time is significantly reduced. 40.3.3 High Data Rate Frame Buffer Access The AT86RF233 Frame Buffer access to read or write frames for High Data Rate transmission is similar to the procedure described in "Frame Buffer Access Mode" on page 886. However, during Frame Buffer read access the next byte transferred after the PSDU data is the LQI value. This value is invalid for the High Data Rates. Figure 40-5 illustrates the packet structure of a High Data Rate Frame Buffer read access. Figure 40-8. Package Structure - High Data Rate Frame Buffer Read Access byte 1 (command byte ) byte 2 (data byte ) byte 3 (data byte ) byte n-1 (data byte ) byte n (data byte ) MOSI 0 0 1 reserved[4:0] XX XX XX XX MISO PHY_STATUS PHR[7:0] PSDU[7:0] ED[7:0] RX_STATUS[7:0] The structure of RX_STATUS is described in "Structure of RX_STATUS" on page 887. 40.3.4 High Data Rate Energy Detection According to IEEE 802.15.4 the ED measurement duration is eight symbol periods. For frames operated at higher data rates the automated ED measurement duration is reduced to 32s to take the reduced frame length into account, refer to "Energy Detection (ED)" on page 965. During Frame Buffer read access the ED value is appended to the PSDU data, refer to "High Data Rate Frame Buffer Access" on page 1015. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1015 40.3.5 High Data Rate Mode Options 40.3.5.1 Receiver Sensitivity Control The different data rates between PPDU header (SHR and PHR) and PHY payload (PSDU) cause a different sensitivity between header and payload. This can be adjusted by defining sensitivity threshold levels of the receiver. With a sensitivity threshold level RX_PDT_LEVEL > 0 (register 0x15, RX_SYN), the receiver does not receive frames with an RSSI level below that threshold. Enabling receiver sensitivity control with at least RX_PDT_LEVEL = 1 is recommended for the 2000kb/s rate with a PSDU sensitivity of -88dBm. In the case of receiving with the default setting of RX_PDT_LEVEL, a high data rate frame may be detected even if the PSDU sensitivity is above the received signal strength. In this case the frame is rejected. A description of the settings to control the sensitivity threshold RX_PDT_LEVEL (register 0x15, RX_SYN) can be found in "Register Description" on page 976. 40.3.5.2 Scrambler For data rate 2000kb/s, additional chip scrambling is applied per default, in order to mitigate data dependent spectral properties. Scrambling can be disabled if AT86RF233 register bit OQPSK_SCRAM_EN (register 0x0C, TRX_CTRL_2) is set to zero. 40.3.5.3 Carrier Sense For clear channel assessment, IEEE 802.15.4-2006 specifies several modes which may either apply Energy above threshold or Carrier sense (CS) or a combination of both. In High Data Rate Modes only "Energy above threshold" is supported, since the modulation spreading is not compliant to IEEE 802.15.4-2006. 40.3.5.4 Link Quality Indicator (LQI) For the High Data Rate Modes, the link quality indicator does not contain useful information and should be discarded. 40.3.5.5 Reduced Acknowledgment Timing On higher data rates the IEEE 802.15.4 compliant acknowledgment frame response time of 192s significantly reduces the effective data rate of the network. To minimize this influence in Extended Operating Mode RX_AACK, refer to "RX_AACK_ON - Receive with Automatic ACK" on page 918, the acknowledgment frame response time can be reduced to 32s. Figure 40-9 illustrates an example for a reception and acknowledgement of a frame with a data rate of 2000kb/s and a PSDU length of 80 symbols. The PSDU length of the acknowledgment frame is five octets according to IEEE 802.15.4. Figure 40-9. High Data Rate AACK Timing 704 916 SFD 192 s PHR PSDU: 80 octets 544 SFD SFD PHR SFD AACK_ACK_TIME = 1 PSDU: 80 octets PHR AACK_ACK_TIME = 0 512 PHR 192 0 time [s] ACK ACK 32 s If register bit AACK_ACK_TIME (register 0x17, XAH_CTRL_1) is set the acknowledgment time is reduced from 192s to 32s. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1016 40.3.6 Register Description 40.3.6.1 TRX_CTRL_2 Name: TRX_CTRL_2 Offset: 0x0C Reset: - Property: - The TRX_CTRL_2 register is a multi-purpose control register to control various settings of the radio transceiver. Bit 7 6 RX_SAFE_MODE 0x0C Access Reset z 5 4 3 2 OQPSK_SCRAM_EN 1 0 OQPSK_DATA_RATE R/W R R/W R R R/W R/W R/W 0 0 1 0 0 0 0 0 Bit 5 - OQPSK_SCRAM_EN If register bit OQPSK_SCRAM_EN is enabled, an additional chip scrambling is applied for 2000kb/s data rate. Table 40-10. OQPSK Scrambler Enabled Value Description 0 Scrambler is disabled 1 Scrambler is enabled z Bit 2:0 - OQPSK_DATA_RATE [2:0] A write access to these register bits set the OQPSK PSDU data rate used by the radio transceiver. The reset value O-QPSK_DATA_RATE = 0 is the PSDU data rate according to IEEE 802.15.4. Table 40-11. OQPSK Data Rate Value Description 0x0(1) 250kb/s 0x1 500kb/s 0x2 1000kb/s 0x3 2000kb/s 0x4 - 0x7 All other values are reserved Note: 1. EEE 802.15.4 compliant. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1017 40.3.6.2 RX_SYN Name: RX_SYN Offset: 0x15 Reset: - Property: - The register RX_SYN controls the blocking of receiver path and the sensitivity threshold of the receiver. Bit 7 6 5 4 3 RX_PDT_DIS 0x15 Access Reset z 2 1 0 RX_PDT_LEVEL R/W R R R R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 3:0 - RX_PDT_LEVEL The register bits RX_PDT_LEVEL desensitize the receiver in steps of 3dB. Table 40-12. RX_PDT_LEVEL Value Description 0x00 Maximum RX sensitivity 0x01 - 0x0E Reserved 0x0F RX input level > RSSI_BASE_VAL + 3[dB] x 14 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1018 40.3.6.3 XAH_CTRL_1 Name: XAH_CTRL_1 Offset: 0x17 Reset: - Property: - The XAH_CTRL_1 register is a multi-purpose controls register for Extended Operating Mode. Bit 7 6 ARET_TX_TS_EN 0x17 Access Reset z 5 4 AACK_FLTR _RES_FT AACK_ULD _RES_FT 3 2 1 0 AACK_ ACK_TIME AACK_ PROM_ MODE AACK_ SPC_EN R/W R R/W R/W R R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 2 - AACK_ACK_TIME The register bit AACK_ACK_TIME controls the acknowledgment frame response time within RX_AACK mode. Table 40-13. AACK_ACK_TIME Value Description 0x0 Acknowledgment time is 12 symbol periods (aTurnaroundTime) 0x1 Acknowledgment time is two symbol periods According to IEEE 802.15.4-2006, Section 7.5.6.4.2 the transmission of an acknowledgment frame shall commence 12 symbol periods (aTurnaroundTime) after the reception of the last symbol of a data or MAC command frame. This is achieved with the reset value of the register bit AACK_ACK_TIME. Alternatively, if AACK_ACK_TIME = 1 an acknowledgment frame is sent already two symbol periods after the reception of the last symbol of a data or MAC command frame. This may be applied to proprietary networks or networks using the High Data Rate Modes to increase battery lifetime and to improve the overall data throughput. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1019 40.4 Antenna Diversity The Antenna Diversity implementation is characterized by: z Improves signal path robustness between nodes z AT86RF233 self-contained antenna diversity algorithm z Direct register based antenna selection 40.4.1 Overview Due to multipath propagation effects between network nodes, the receive signal strength may vary and affect the link quality, even for small variance of the antenna location. These fading effects can result in an increased error floor or loss of the connection between devices. To improve the reliability of an RF connection between network nodes Antenna Diversity can be applied to reduce effects of multipath propagation and fading. Antenna Diversity uses two antennas to select the most reliable RF signal path. To ensure highly independent receive signals on both antennas, the antennas should be carefully separated from each other. If a valid IEEE 802.15.4 frame is detected on one antenna, this antenna is selected for reception. Otherwise the search is continued on the other antenna and vice versa. Antenna Diversity can be used in Basic and Extended Operating Modes and can also be combined with other features and operating modes like High Data Rate and RX/TX Indication. 40.4.2 Antenna Diversity Application Example A block diagram for an application using an antenna switch is shown in Figure 40-10. Figure 40-10.Antenna Diversity - Block Diagram ANT0 SW1 SAM R21 B1 GNDANA RFSWITCH RFP BALUN RFN AT86RF233 DIG1 DIG2 DIG3 DIG4 GNDANA ANT1 FECTRLi(DIG1) FECTRLj(DIG2) RFCTRL SAM D21 Generally, when the external RF-Switch (SW1) is to be controlled by antenna diversity algorithm, the antenna diversity enable must be activated by register bit ANT_EXT_SW_EN (register 0x0D, ANT_DIV). Then the internal digital control signals DIG1 and DIG2 are enabled (refer to "Digital I/O Signals" on page 18) to drive the antenna switch control signals to the differential inputs of the RF Switch (SW1) to switch between ANT0 and ANT1. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1020 If the AT86RF233 is not in a receive or transmit state, it is recommended to disable register bit ANT_EXT_SW_EN to reduce the power consumption or avoid leakage current of an external RF switch, especially during SLEEP or DEEP_SLEEP state. If register bit ANT_EXT_SW_EN = 0, output signals DIG1/DIG2 are pulled-down to digital ground. 40.4.2.1 User Defined Antenna Selection A microcontroller defined selection of a certain antenna can be done by disabling the automated Antenna Diversity algorithm (ANT_DIV_EN = 0) and selecting one antenna using register bits ANT_CTRL = 1 / 2. The antenna defined by register bits ANT_CTRL (register 0x0D, ANT_DIV) is used for transmission and reception. 40.4.2.2 Autonomous Antenna Selection The autonomous Antenna Diversity algorithm is enabled with register bits ANT_DIV_EN = 1 and ANT_CTRL = 0 / 3 (register 0x0D, ANT_DIV). It allows the use of Antenna Diversity even if the microcontroller does currently not control the radio transceiver, for instance in Extended Operating Mode. Upon reception of a frame, the AT86RF233 selects one antenna. The selected antenna is then indicated by register bit ANT_SEL (register 0x0D, ANT_DIV). If required, it is recommended to read register bit ANT_SEL after IRQ_2 (RX_START). After the frame reception is completed, the antenna selection continues searching for new frames on both antennas. However, the register bit ANT_SEL maintains its previous value (from the last received frame) until a new IEEE 802.15.4 frame has been detected, and the selection algorithm locked into one antenna again. At this time the register bit ANT_SEL is updated again. If a device is in RX_AACK mode, receiving a frame containing an ACK request, the ACK frame is transmitted using the same antenna as used during receive. If a device performs a transaction in TX_ARET mode, it starts to listen for an ACK on the transmit antenna. If no ACK was received, the next transmission attempt is done on the other transmit antenna. This will be repeated with each retry. 40.4.3 Antenna Diversity Sensitivity Control Due to a different receive algorithm used by the Antenna Diversity algorithm, the correlator threshold of the receiver has to be adjusted. It is recommended to set register bits PDT_THRES (register 0x0A, RX_CTRL) to three. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1021 40.4.4 Register Description 40.4.4.1 RX_CTRL Name: RX_CTRL Offset: 0x0A Reset: 0x37 Property: - The RX_CTRL register controls the sensitivity of the Antenna Diversity mode and indicates the receiver synchronization behavior. Bit 7 6 5 4 3 2 PEL_SHIFT_VALUES 0x0A 1 0 PDT_THRES Access R R R/W R/W R/W R/W R/W R/W Reset 0 0 1 1 0 1 1 1 z Bit 3:0 - PDT_THRES The register bits PDT_THRES control the sensitivity of the receiver correlation unit. Table 40-14. PDT_THRES Value Description 0x0 - 0x2 Reserved 0x3(1) Recommended correlator threshold for Antenna Diversity operation 0x4 - 0x6 Reserved 0x7 To be used if Antenna Diversity algorithm is disabled 0x8 - 0xF Reserved Note: 1. If the Antenna Diversity algorithm is enabled (ANT_DIV_EN = 1), the value shall be set to PDT_THRES = 3, otherwise it shall be set back to the reset value. This is not automatically done by the hardware. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1022 40.4.4.2 ANT_DIV Name: ANT_DIV Offset: 0x0D Reset: 0x00 Property: - The ANT_DIV register controls Antenna Diversity. Bit 7 6 5 4 ANT_SEL 0x0D 3 2 ANT_DIV_EN ANT_EXT _SW_EN 1 0 ANT_CTRL Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bit 7 - ANT_SEL Signals selected antenna, related to the last received frame. Table 40-15. ANT_SEL Value Description 0x0 Antenna 0 0x1 Antenna 1 Note: 1. If the autonomous Antenna Diversity algorithm is enabled, the register bit ANT_SEL maintains its previous value (from the last received frame) until a new SHR has been found. This register bit signals the currently selected antenna path. The selection may be based either on the last antenna diversity cycle (ANT_DIV_EN = 1) or on the content of register bits ANT_CTRL, for details refer to "Antenna Diversity Application Example" on page 1020. z Bit 3 - ANT_DIV_EN The register bit ANT_DIV_EN activates the autonomous Antenna Diversity algorithm. Table 40-16. ANT_DIV_EN Value Description 0x0 Antenna Diversity algorithm is disabled 0x1 Antenna Diversity algorithm is enabled Note: 1. If ANT_DIV_EN = 1 register bit ANT_EXT_SW_EN shall be set to one, too. This is not automatically done by the hardware. If register bit ANT_DIV_EN is set the Antenna Diversity algorithm is enabled. On reception of a frame the algorithm selects an antenna autonomously during SHR search. This selection is kept until: z z A new SHR search starts z Leaving receive states z Register bits ANT_CTRL are manually programmed Bit 2 - ANT_EXT_SW_EN The register bit ANT_EXT_SW_EN controls the external antenna switch. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1023 Table 40-17. ANT_EXT_SW_EN Value Description 0x0 Antenna Diversity RF switch control is disabled 0x1 Antenna Diversity RF switch control is enabled If enabled, DIG1 and DIG2 provides a differential control signal for an Antenna Diversity switch. The selection of a specific antenna is done either by the automated Antenna Diversity algorithm (ANT_DIV_EN = 1), or according to register bits ANT_CTRL if Antenna Diversity algorithm is disabled. If the AT86RF233 is not in receive or transmit state, it is recommended to disable register bit ANT_EXT_SW_EN to reduce the power consumption or avoid leakage current of an external RF switch, especially during SLEEP or DEEP_SLEEP state. If register bit ANT_EXT_SW_EN = 0, DIG1 and DIG2 are pulled-down to digital ground. DIG2 is overloaded with RX and TX Frame Time Stamping, see "RX and TX Frame Time Stamping (TX_ARET)" on page 1027, if IRQ_2_EXT_EN is set. z Bit 1:0 - ANT_CTRL These register bits provide a static control of an Antenna Diversity switch. Table 40-18. ANT_CTRL Value Description 0x0 Mandatory setting for applications not using Antenna Diversity and if autonomous antenna selection is enabled 0x1 Antenna 0 DIG1 = L DIG2 = H 0x2 Antenna 1 DIG1 = H DIG2 = L 0x3 Same behavior as value zero These register bits provide a static control of an Antenna Diversity switch if ANT_DIV_EN = 0 and ANT_EXT_SW_EN = 1. Although it is possible to change register bits ANT_CTRL in state TRX_OFF, this change will be effective at DIG1 and DIG2 in states PLL_ON and RX_ON. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1024 40.5 RX/TX Indicator The main features are: z RX/TX indicator to control an external RF front-end z Microcontroller independent RF front-end control z Providing TX timing information 40.5.1 Overview While IEEE 802.15.4 is targeting low cost and low power applications, solutions supporting higher transmit output power are occasionally desirable. To simplify the control of an optional external RF front-end, a differential control signal pair can indicate that the AT86RF233 is currently in transmit mode. The control of an external RF front-end is done via internal digital control signals DIG3/4 available as alternate pin functions FECTRL[0..5] on pins PA08..15, refer to "Block Diagrams" on page 8. The function of this signal pair is enabled with register bit PA_EXT_EN (register 0x04, TRX_CTRL_1). While the transmitter is turned off, the DIG3 signal is set to low level and DIG4 signal to high level. If the radio transceiver starts to transmit, the two signals change the polarity. This differential signal pair can be used to control PA, LNA, and RF switches. If the AT86RF233 is not in a receive or transmit state, it is recommended to disable register bit PA_EXT_EN (register 0x04, TRX_CTRL_1) to reduce the power consumption or avoid leakage current of external RF switches and other building blocks, especially during SLEEP or DEEP_SLEEP state. If register bit PA_EXT_EN = 0, the output signals DIG3/DIG4 are pulled-down to analog ground. 40.5.2 External RF-Front End Control The timing of an external RF front-end relative to the radio transceiver sequencing is shown in Figure 40-11 and Figure 40-12, focusing on the TX indication. A rising edge of the internal SLP_TR signal initiates a transmission, refer to "Receiver (RX)" on page 975. The radio transceiver control switches the differential signal pair DIG3/DIG4 6s after TX request recognition to TX operating mode indication. After finishing the transmission, as shown in Figure 40-12, signal pair DIG3/DIG4 is switched back to RX operating mode indication 3s after disabling the AT86RF233 internal PA. Figure 40-11.TX Power Up Ramping Control for RF Front-End for Maximum TX Power 0 TRX_STATE PLL_ON 2 4 6 8 10 12 14 16 18 Length [s] BUSY_TX SLP_TR PA buffer PA Modulation 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 0 0 0 0 0 0 DIG3 DIG4 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1025 Figure 40-12.TX Power Down Ramping for Maximum TX Power 0 2 TRX_STATE BUSY_TX 4 6 Length [s] PLL_ON PA buffer PA Modulation 1 1 1 0 1 0 1 0 1 0 1 0 1 0 0 0 DIG3 DIG4 40.5.3 Register Description 40.5.3.1 TRX_CTRL_1 Name: TRX_CTRL_1 Offset: 0x04 Reset: 0x22 Property: - The TRX_CTRL_1 register is a multi-purpose register to control various operating modes and settings of the radio transceiver. Bit 0x04 Access 7 6 5 4 PA_EXT_EN IRQ_2_EXT_E N TX_AUTO_ CRC_ON RX_BL_ CTRL R/W R/W R/W R/W R/W 0 0 1 0 0 Reset z 3 2 1 0 IRQ_MASK_M ODES IRQ_ POLARITY R/W R/W R/W 0 1 0 SPI_CMD_MODE Bit 7 - PA_EXT_EN The register bit PA_EXT_EN enables RF front-end control signals DIG3 and DIG4 to indicate the transmit state of the radio transceiver. Table 40-19. PA_EXT_EN PA_EXT_EN State 0x0 n/a TX_BUSY 0x1(1) Other Note: 1. Signal Value DIG3 L DIG4 L DIG3 H DIG4 L DIG3 L DIG4 H Description External RF front-end control disabled External RF front-end control enabled It is recommended to set PA_EXT_EN = 1 only in receive or transmit states to reduce the power consumption or avoid leakage current of external RF switches or other building blocks, especially during SLEEP or DEEP_SLEEP state. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1026 40.6 RX and TX Frame Time Stamping (TX_ARET) 40.6.1 Overview An exact timing of received and transmitted frames is signaled by the AT86RF233 DIG2, refer to "Block Diagrams" on page 8. A valid PHR reception or start of frame transmission (start of modulation at beginning of first synchronization byte) is indicated by a DIG2 rising edge. The signal remains high during frame reception or transmission. TX Frame Time Stamping is limited to TX_ARET, whereas the RX Frame Time Stamping is available for all receive modes. Exemplary, Figure 40-13 illustrates a frame reception example. If this signal is not used for RX Frame Time Stamping, it can be configured for Antenna Diversity, refer to "Antenna Diversity" on page 1020. Otherwise, this signal is internally connected to ground. Figure 40-13.Timing of RX_START and DIG2 for RX Frame Time Stamping Number of Octets Frame Content TRX_STATE 128 160 192 192 + m * 32 4 1 1 m < 128 Preamble SFD PHR PSDU (250 kb/s) RX_ON BUSY_RX Time [s] Frame on Air 0 RX_ON IRQ IRQ_2 (RX_START) Interrupt latency Note: RX DIG2 (RX Frame Time Stamp) 1. TRX_END tIRQ tIRQ Timing figures tIRQ refer to "Digital Interface Timing Characteristics" on page 1101. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1027 40.6.2 Register Description 40.6.2.1 TRX_CTRL_1 Name: TRX_CTRL_1 Offset: 0x04 Reset: 0x22 Property: - The TRX_CTRL_1 register is a multi-purpose register to control various operating modes and settings of the radio transceiver. Bit 0x04 7 6 5 4 PA_EXT_EN IRQ_2_EXT_E N TX_AUTO_ CRC_ON RX_BL_ CTRL R/W R/W R/W R/W R/W 0 0 1 0 0 Access Reset z 3 2 1 0 IRQ_MASK_M ODES IRQ_ POLARITY R/W R/W R/W 0 1 0 SPI_CMD_MODE Bit 6 - IRQ_2_EXT_EN The register bit IRQ_2_EXT_EN controls external signaling for time stamping via DIG2. Table 40-20. IRQ_2_EXT_EN Value Description 0x0 Time stamping over DIG2 is disabled 0x1(1) Time stamping over DIG2 is enabled Note: 1. DIG2 is also active if the corresponding interrupt event IRQ_2 (RX_START) mask bit in register 0x0E (IRQ_MASK) is set to zero. The signal remains at high level until the end of the frame receive or transmit procedure. 40.6.2.2 XAH_CTRL_1 Name: XAH_CTRL_1 Offset: 0x17 Reset: 0x00 Property: - The XAH_CTRL_1 register is a multi-purpose controls register for Extended Operating Mode. Bit 7 6 ARET_TX_ TS_EN 0x17 Access Reset z 5 4 AACK_FLTR_ RES_FT AACK_UPLD_ RES_FT 3 2 1 0 AACK _ACK_ TIME AACK_PROM_ MODE AACK_SPC_ EN R/W R/W R/W R/W R R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 - ARET_TX_TS_EN If register bit ARET_TX_TS_EN = 1, then any frame transmission within TX_ARET mode is signaled via DIG2. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1028 Table 40-21. ARET_TX_TS_EN Value Description 0x0 TX_ARET time stamping via DIG2 is disabled (1) 0x1 Note: TX_ARET time stamping via DIG2 is enabled 1. It is necessary to set register bit IRQ_2_EXT_EN (register 0x04, TRX_CTRL_1). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1029 40.7 Frame Buffer Empty Indicator 40.7.1 Overview For time critical applications that want to start reading the frame data as early as possible, the Atmel AT86RF233 Frame Buffer status can be indicated to the microcontroller through a dedicated signal. This signal indicates to the microcontroller if an access to the Frame Buffer is not possible since valid PSDU data are missing. The IRQ signal connected to the microcontroller port PB00 can be configured as a Frame Buffer Empty Indicator during a Frame Buffer read access. This mode is enabled by register bit RX_BL_CTRL (register 0x04, TRX_CTRL_1). The IRQ signal turns into Frame Buffer Empty Indicator after the Frame Buffer read access command, see note (1) in Figure 4014, has been transferred on the SPI bus until the Frame Buffer read procedure has finished indicated by /SEL = H, see note (4). Figure 40-14.Timing Diagram of Frame Buffer Empty Indicator /SEL SCLK MOSI MISO Command XX PHY_STATUS IRQ_STATUS Command TRX_STATUS XX PHR[7:0] XX XX PSDU[7:0] PSDU[7:0] XX XX PSDU[7:0] LQI[7:0] XX ED[7:0] XX Command RX_STATUS XX TRX_STATUS IRQ_STATUS Frame Buffer Empty Indicator IRQ IRQ_2 (RX_START) IRQ_3 (TRX_END) t12 Notes Notes: 1. (1) (2) (3) (4) Timing figure t12 refer to "Digital Interface Timing Characteristics" on page 1101. 2. A Frame Buffer read access can proceed as long as IRQ = L. 3. IRQ = H indicates that the Frame Buffer is currently not ready for another SPI cycle. 4. The Frame Buffer read procedure has finished indicated by /SEL = H. The microcontroller has to observe the IRQ signal internally connected to PB00 during the Frame Buffer read procedure. A Frame Buffer read access can proceed as long as IRQ = L(2). When the IRQ output is pulled high (IRQ = H), the Frame Buffer is not ready for another SPI cycle(3) above. The read operation can be resumed as the IRQ output is pulled low again (IRQ = L) to indicate new data in the buffer. On Frame Buffer read access, three more byte are transferred via MISO after PHR and PSDU data, namely LQI, ED, and RX_STATUS; refer to "Frame Buffer Access Mode" on page 886. Because these bytes are appended and physically not stored in the frame buffer, they are ignored for Frame Buffer empty indication. The Frame Buffer Empty Indicator IRQ becomes valid after t12 = 750ns starting from the last SCLK rising edge while reading a Frame Buffer command byte, see figure above. Upon completing the SPI frame data receive task, SPI read access can be disabled by pulling /SEL = H, note (4). At this time the IRQ output can be used to flag pending interrupts to the processor. If during the Frame Buffer read access a receive error occurs (for example an PLL unlock), the Frame Buffer Empty Indicator locks on 'empty' ((IRQ) = H) too. To prevent possible deadlocks, the microcontroller should impose a timeout counter that checks whether the Frame Buffer Empty Indicator remains logic high for more than two octet periods. A new byte must have been arrived at the frame buffer during that period. If not, the Frame Buffer read access should be aborted. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1030 40.7.2 Register Description 40.7.2.1 TRX_CTRL_1 Name: TRX_CTRL_1 Offset: 0x04 Reset: 0x22 Property: - The TRX_CTRL_1 register is a multi-purpose register to control various operating modes and settings of the radio transceiver. Bit 0x04 Access 7 6 5 4 PA_EXT_EN IRQ_2_EXT_ EN TX_AUTO_ CRC_ON RX_BL_CTRL R/W R/W R/W R/W R/W 0 0 1 0 0 Reset z 3 2 1 0 IRQ_MASK_ MODES IRQ_ POLARITY R/W R/W R/W 0 1 0 SPI_CMD_MODE Bit 4 - RX_BL_CTRL The register bit RX_BL_CTRL controls the Frame Buffer Empty Indicator. Table 40-22. RX_BL_CTRL Value Description 0x0 Frame Buffer Empty Indicator disabled 0x1 Frame Buffer Empty Indicator enabled Note: 1. A modification of register bit IRQ_POLARITY has no influence to RX_BL_CTRL behavior. If this register bit is set, the Frame Buffer Empty Indicator is enabled. After sending a Frame Buffer read command (refer to "SPI Protocol" on page 885), signal IRQ indicates that an access to the Frame Buffer is not possible since PSDU data are not available yet. The IRQ signal does not indicate any interrupts during this time. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1031 40.8 Dynamic Frame Buffer Protection 40.8.1 Overview The Atmel AT86RF233 continues the reception of incoming frames as long as it is in any receive state. When a frame was successfully received and stored into the Frame Buffer, the following frame will overwrite the Frame Buffer content again. To relax the timing requirements for a Frame Buffer read access the Dynamic Frame Buffer Protection prevents that a new valid frame passes to the Frame Buffer until a Frame Buffer read access has ended (indicated by /SEL = H, refer to "SPI Protocol" on page 885). A received frame is automatically protected against overwriting: z in Basic Operating Mode, if its FCS is valid z in Extended Operating Mode, if an IRQ_3 (TRX_END) is generated. The Dynamic Frame Buffer Protection is enabled with RX_SAFE_MODE (register 0x0C, TRX_CTRL_2) set and applicable in transceiver states RX_ON and RX_AACK_ON. Note: 1. The Dynamic Frame Buffer Protection only prevents write accesses from the air interface - not from the SPI interface. A Frame Buffer or SRAM write access may still modify the Frame Buffer content. 40.8.2 Register Description 40.8.2.1 TRX_CTRL_2 Name: TRX_CTRL_2 Offset: 0x0C Reset: 0x20 Property: - The TRX_CTRL_2 register is a multi-purpose control register to control various settings of the radio transceiver. Bit 7 6 5 4 3 2 RX_SAFE_ MODE 0x0C Access 0 OQPSK_DATA_RATE R/W R R/W R R R/W R/W R/W 0 0 1 0 0 0 0 0 Reset z 1 Bit 7 - RX_SAFE_MODE Protect Frame Buffer after frame reception with valid FCF check. Table 40-23. RX_SAFE_MODE Value Description 0x0 Disable Dynamic Frame Buffer protection 0x1(1) Enable Dynamic Frame Buffer protection Note: 1. Dynamic Frame Buffer Protection is released on the rising edge of /SEL during a Frame Buffer read access, or on the radio transceiver's state change from RX_ON or RX_AACK_ON to another state. This operation mode is independent of the setting of register bits RX_PDT_LEVEL, (register 0x15, RX_SYN), refer to "Configuration" on page 975. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1032 z Bit 2:0 - OQPSK_DATA_RATE [2:0] A write access to these register bits set the OQPSK PSDU data rate used by the radio transceiver. The reset value O-QPSK_DATA_RATE = 0 is the PSDU data rate according to IEEE 802.15.4. Table 40-24. OQPSK Data Rate Value Description 0x0(1) 250kb/s 0x1 - 0x7 All other values are reserved Note: 40.9 1. IEEE 802.15.4 compliant. Alternate Start-Of-Frame Delimiter 40.9.1 Overview The SFD (start of frame delimiter) is a field indicating the end of the SHR and the start of the packet data. The length of the SFD is one octet (two symbols for O-QPSK). The octet is used for byte synchronization only and is not included in the Atmel AT86RF233 Frame Buffer. The value of the SFD can be changed if it is needed to operate in non-IEEE 802.15.4 compliant networks. A node with a non-standard SFD value cannot synchronize with any of the IEEE 802.15.4 network nodes. Due to the way the SHR is formed, it is not recommended to set the low-order four bits to zero. The LSB of the SFD is transmitted first, that is right after the last bit of the preamble sequence. 40.9.2 Register Description 40.9.2.1 SFD_VALUE Name: SFD_VALUE Offset: 0x0B Reset: 0xA7 Property: - The SFD_VALUE register contains the one octet start-of-frame delimiter (SFD). Bit 7 6 5 4 R/W R/W R/W R/W 1 0 1 0 3 2 1 0 R/W R/W R/W R/W 0 1 1 1 SFD_VALUE 0x0B Access Reset z Bit 7:0 - SFD_VALUE The register bits SFD_VALUE are required for transmit and receive operation. Table 40-25. SFD_VALUE Value Description 0xA7 For transmission this value is copied into start-of-frame delimiter (SFD) field of frame header. For reception this value is checked for incoming frames. The default value is according to IEEE 802.15.4 specification. For IEEE 802.15.4 compliant networks, set SFD_VALUE = 0xA7 as specified in [2]. This is the default value of the register. To establish non IEEE 802.15.4 compliant networks, the SFD value can be changed to any other value. If enabled, IRQ_2 (RX_START) is issued only if the received SFD matches SFD_VALUE and a valid PHR is received. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1033 40.10 Reduced Power Consumption Mode (RPC) The Reduced Power Consumption mode is characterized by: z Significant power reduction for several operating modes z Self-contained, self-calibrating and adaptive power reduction schemes 40.10.1 Overview AT86RF233 RPC offers a variety independent techniques and methods to significantly reduce the power consumption. RPC is applicable to several operating modes and transparent to other extended features. Notes: 1. 2. To achieve the lowest power consumption set register 0x16, TRX_RPC to 0xFF or disabling the Reduced Power Consumption modes set register 0x16, TRX_RPC to 0xC1 or 0x01. 40.10.2 RPC Methods and Elements 40.10.2.1 PES - PLL Energy Saving The PES mode is activated with register bit PLL_RPC_EN (register 0x16, TRX_RPC) set to one. Applicable to states: PLL_ON and TX_ARET_ON A state change towards PLL_ON or TX_ARET_ON causes an initial PLL calibration run, immediately followed by entering the PES mode. A state change towards RX or TX states, a channel switch or PLL calibration causes a PLL wake-up. After finishing such an operation, the PLL automatically enters the PES mode. The typical current consumption IPLL_ON reduces from 5.2mA to 450A. 40.10.2.2 SRT - Smart Receiving Technology The SRT mode is activated with register bit RX_RPC_EN (register 0x16, TRX_RPC) set to one. Applicable to states: RX_ON, RX_AACK_ON and TX_ARET SRT reduces the average power consumption during RX listening periods. In typical environment situations SRT reduces the average current consumption IRX_ON by up to 50%. A configuration of SRT is done with register bits RX_RPC_CTRL (register 0x16, TRX_RPC). Notes: 1. 2. It's recommended to disable SRT during RSSI measurements or random number generation, "Received Signal Strength Indicator (RSSI)" on page 964 and "Random Number Generator" on page 1013. During CCA or/and ED scan the SRT is disabled automatically. 3. If autonomous antenna diversity is enabled, SRT cannot achieve the maximum effect. 4. Depending on operating conditions (traffic, temperature, channel noise, frequency settings) the effective reduction of current consumption may vary. 40.10.2.3 ERD - Extended Receiver Desensitizing AT86RF233 ERD is activated with register bit PDT_RPC_EN (register 0x16, TRX_RPC) set to one. Applicable to states: RX, RX_AACK and TX_ARET In combination with RX_PDT_LEVEL settings, the average RX current is further significantly reduced, for details refer to "Current Consumption Specifications" on page 1105. An RX_PDT_LEVEL = 0x08 setting requires special attention. In contrast to definitions in Table 38-3, the sensitivity is reduced to -83dBm only, but at much lower average RX listen current than comparable register settings. Notes: 1. 2. With RX_PDT_LEVEL = 0x08, RSSI/ED can not resolve RX input levels from -83dBm to -70dBm. During CCA or/and ED scan the ERD is disabled automatically. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1034 40.10.2.4 TPH - Automated TX Power Handling TPH is activated with register bit XAH_TX_RPC_EN (register 0x16, TRX_RPC) set to one. Applicable to states: RX_AACK ACK frame TX output power setting is automatically adapted according to a combination of received RX frame ED and LQI values. If an expected frame has been successfully received with ED > -77dBm and LQI > 224, the TX output power is reduced. The minimum power is -17dBm (ED > -45dBm and LQI > 224), whereas the maximum is set be register bits TX_PWR (register 0x05, PHY_TX_PWR). Reading the TX_PWR field provides the used transmit power for last transmitted frame including acknowledgement frame. This allows monitoring the actual RPC handling used for transmitting. See register bits TX_PWR description for further information. The Table 40-26 shows the typical current consumption for dedicated TX output power values. Table 40-26. TX Output Power vs. Current Consumption (Extraction) Register Bits TX_PWR Notes: 1. 2. TX Output Power [dBm] Current Consumption [mA] +4 13.8 +0 11.8 -17 7.2 The upper limit will be declared by register bits TX_PWR (register 0x05, PHY_TX_PWR), refer to "Register Description" on page 980. If the sequence number, refer to "MAC Protocol Data Unit (MPDU)" on page 948, from previous received frame equal to the current frame sequence number, then no automatic TX power reduction will be activated. Applicable to states: TX_ARET If the first frame transmission fails, using a reduced TX output power as set by register bits TX_PWR (register 0x05, PHY_TX_PWR), the next frame retry starts with maximum TX output power (+4dBm). Note: 1. The lower limit for the first frame transmitting will be declared by register bits TX_PWR (register 0x05, PHY_TX_PWR), refer to "Register Description" on page 980. Achievable TX current consumption IBUSY_TX reductions are shown in "Current Consumption Specifications" on page 1105 or Table 40-26. 40.10.2.5 PAM - PAN Address Match Recognition AT86RF233 PAM is activated with register bit IPAN_RPC_EN (register 0x16, TRX_RPC) set to one. Applicable to states: RX_AACK Address match fail indication of the IEEE 802.15.4 frame filtering causes stopping of the receive procedure in two ways: 1. If PAN address does not match, a new listen period starts immediately, 2. If PAN address matches, the radio transceiver enters power saving mode for the remaining frame and ACK period, if an ACK is requested. Notes: 1. 2. PAM is applicable to short ACK time and reserved frames types as set by register bit AACK_ACK_TIME and register bit AACK_FLTR_RES_FT (register 0x17, XAH_CTRL_1), respectively. If promiscuous mode is enabled with AACK_PROM_MODE (register 0x17, XAH_CTRL_1) set, PAM is disabled automatically. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1035 40.10.2.6 Miscellaneous Power Reduction Functions Applicable to states: RX and RX_AACK In addition to Dynamic Frame Buffer Protection, refer to "Dynamic Frame Buffer Protection" on page 1032: During Dynamic Frame Buffer Protection, the radio transceiver automatically enters the power save mode. Applicable to states: TX_ARET In addition to CSMA-CA retry, refer to "TX_ARET_ON - Transmit with Automatic Frame Retransmission and CSMA-CA Retry" on page 928: After starting the TX_ARET transaction, a random backoff period is performed. Within this backoff period the radio transceiver automatically enters power saving mode. Applicable to states: TX_ARET and RX_AACK In addition to TX/RX turnaround time, refer to "Extended Operating Mode" on page 915: The radio transceiver automatically enters power saving mode in: z TX_ARET: during the time waiting for an ACK frame, or z RX_AACK: during the time waiting for ACK transmission Note: 1. To handle nodes configured with a RX/TX turnaround time less than 12 symbols, register bits are to be set to RX_RPC_CTRL = 0 within TX_ARET. Alternatively, register bit AACK_ACK_TIME (register 0x17, XAH_CTRL_1) can be set to one. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1036 40.10.3 Register Description 40.10.3.1 TRX_RPC Name: TRX_RPC Offset: 0x16 Reset: 0xC1 Property: - The TRX_RPC register controls the Reduce Power Consumption modes. Bit 7 0x16 RX_RPC_CTRL Access Reset Note: z 6 5 4 3 2 1 RX_RPC _EN PDT_RPC_ EN PLL_RPC _EN XAH_TX _RPC_EN IPAN_RPC _EN 0 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 0 0 0 0 0 1 1. The reserved bit needs to be set one for write access. Bit 7:6 - RX_RPC_CTRL The register bits RX_RPC_CTRL are used for internal performance settings within Smart Receiving mode. Table 40-27. RX_RPC_CTRL Value Description 0x0 Activates minimum power saving behavior for Smart Receiving mode 0x01 - 0x02 Reserved 0x3 Activates maximum power saving behavior for Smart Receiving mode z Bit 5 - RX_RPC_EN The register bit RX_RPC_EN activates the Smart Receiving mode for all RX listening modes. Table 40-28. RX_RPC_EN Value Description 0x0 Smart receiving mode is disabled 0x1 Smart receiving mode is enabled z Bit 4 - PDT_RPC_EN The register bit PDT_RPC_EN controls in combination with the RX_PDT_LEVEL value the reduced sensitivity behavior under the RPC mode. Table 40-29. PDT_RPC_EN Value Description 0x0 The reduced sensitivity RPC mode is disabled 0x1 The reduced sensitivity RPC mode is enabled z Bit 3 - PLL_RPC_EN The register bit PLL_RPC_EN controls the extended PLL behavior within PLL_ON and TX_ARET_ON modes. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1037 Table 40-30. PLL_RPC_EN Value Description 0x0 The extended PLL behavior is disabled 0x1 The extended PLL behavior is enabled z Bit 2 - XAH_TX_RPC_EN The register bit XAH_TX_RPC_EN controls in combination with the TX_PWR value the automatic TX power handling within the Extended Operating Mode. Table 40-31. XAH_TX_RPC_EN Value Description 0x0 The automatic TX power handling is disabled 0x1 The automatic TX power handling is enabled z Bit 1 - IPAN_RPC_EN The register bit IPAN_RPC_EN controls the own PAN handling within the RPC mode. Table 40-32. IPAN_RPC_EN Value Description 0x0 The RPC PAN handling is disabled 0x1 The RPC PAN handling is enabled Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1038 40.11 Time-Of-Flight Module (TOM) The time-of-flight measurement functions are characterized by: z 24-bit Timer/Counter (T/C) z Automated T/C start, capturing and reset z Reference frequency error measurement z Preamble synchronization monitoring 40.11.1 Overview The AT86RF233 includes a set of means to trigger time measurements during message transfer. 40.11.2 Interrupt Handling If TOM mode is enabled, it causes the generation of IRQ_2 (RX_START) interrupts for all received frames, even with PHR set to zero and IRQ_2 (RX_START) is enabled. 40.11.3 TOM Measurements 40.11.3.1 24-bit Timer/Counter The AT86RF233 features a 24-bit Timer/Counter (T/C), which is automatically started, captured or reset. The actual action depends on specified events and operating modes. The T/C is operated at 16MHz. If a timer event occurs, the current time stamp is captured to the Frame Buffer. The timer is reset and started automatically. An exception is the RX synchronization mode: if the SFD is not equal to 0xA7. In this case, the current counter value is only captured to the Frame Buffer. T/C Content Access With TOM mode enabled, the 24-bit T/C value (TIM) is mapped to Frame Buffer address space 0x7D, ..., 0x7F. z TIM_0: Frame Buffer Address (0x7D): T/C [7:0] z TIM_1: Frame Buffer Address (0x7E): T/C [15:8] z TIM_2: Frame Buffer Address (0x7F): T/C [23:16] Events The Timer/Counter is controlled as follow: Table 40-33. 24-bit Timer/Counter Event Overview Event Delay [s] Capture Reset Start TX start (rising edge of signal SLP_TR) 16.125 x x x 80 x x x 80 x - - RX Synchronization; at detection of SFD (SFD is equal 0xA7) RX Synchronization; at detection of SFD (SFD is not equal 0xA7) 40.11.3.2 Reference Frequency Error Measurement During frame reception and register bit TOM_EN is set within the AT86RF233, the frequency error between two peer devices is estimated. The frequency error calculation (FEC) value is accessible from Frame Buffer address 0x7C. The 8-bit value represents the drift between two successive received chips (0.5s) with a granularity of 180/256. The value is accessible after IRQ_2 (RX_START) and updated after IRQ_3 (TRX_END). It is interpreted as a two's complement signed value in range of -500kHz, ..., < 500kHz, respectively. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1039 The frequency offset can be calculated as follow: foffs[ppm] = FEC x (500000 / 128) / fRF[MHz] 40.11.3.3 Preamble Fine Synchronization Monitoring During receive the radio transceiver searches for SHR symbols and SFD initially. The register bits PEL_SHIFT_VALUE (register 0x0A, RX_CTRL) signals an early/late behavior relative to the determined discrete, 16MHz based, synchronization time stamp. As an alternative to the PEL_SHIFT_VALUE value the complex magnitude values from the synchronization module can be used for a better time stamp estimation. With TOM mode enabled, the complex magnitude values (CPM) from the symbol cross correlator are mapped to Frame Buffer address space 0x73, ..., 0x7C. z CPM_0: Frame Buffer Address (0x73) z ... z CPM_8: Frame Buffer Address (0x7C) 40.11.3.4 Storage of Measurement Results Using TOM mode, the Frame Buffer address space 0x73, ..., 0x7F is reserved to store captured T/C content and other data. This limits the number of usable PSDU octets for standard operation to 114. Any received frame exceeding this number corrupts data stored in the Frame Buffer address starting from address 0x73. Notes: 1. Basic Operating Mode within TX states: If TOM_EN is still set, but not required for the actual transaction, it is possible to transmit up to 127 octets by writing PSDU data to the Frame Buffer after initiating the transmission with rising edge of SLP_TR or TX_START command. 2. Extended Operating Mode within TX_ARET states: If TOM_EN is still set, but not required for the actual transaction, it is possible to transmit up to 127 octets by writing PSDU data to the Frame Buffer after initiating the transmission with rising edge of SLP_TR or TX_START command and MAX_FRAME_RETRIES (register 0x2C, XAH_CTRL_0) set to zero. 3. Reception of an ACK frame causes mapping of TOM measurement results to Frame Buffer address space 0x73, ..., 0x7F. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1040 40.11.4 Register Description 40.11.4.1 TRX_CTRL_0 Name: TRX_CTRL_0 Offset: 0x03 Reset: 0x09 Property: - The TRX_CTRL_0 register controls the CLKM clock rate. Bit 7 6 TOM_EN 0x03 Access Reset z 5 4 3 PMU_EN PMU_IF _INVERSE CLKM_SHA_ SEL 2 1 0 CLKM_CTRL R/W R R/W R/W R/W R/W R/W R/W 0 0 0 0 1 0 0 1 Bit 7 - TOM_EN The register bit TOM_EN controls the Time-Of-Flight Measurement mode. Table 40-34. TOM_EN Value Description 0x0 TOM mode is disabled 0x1 TOM mode is enabled 40.11.4.2 RX_CTRL Name: RX_CTRL Offset: 0x0A Reset: 0x37 Property: - The RX_CTRL register controls the sensitivity of the Antenna Diversity mode and indicates the receiver synchronization behavior. Bit 7 6 5 4 3 2 PEL_SHIFT_VALUES 0x0A 1 0 PDT_THRES Access R R R/W R/W R/W R/W R/W R/W Reset 0 0 1 1 0 1 1 1 z Bit 7:6 - PEL_SHIFT_VALUE The register bits PEL_SHIFT_VALUE signals the synchronization shift behavior. Table 40-35. PEL_SHIFT_VALUE Value Description 0x0 Synchronization behavior is normal 0x1 Synchronization behavior is early 0x2 Synchronization behavior is late 0x3 Reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1041 40.11.4.3 XAH_CTRL_1 Name: XAH_CTRL_1 Offset: 0x17 Reset: 0x00 Property: - The XAH_CTRL_1 register is a multi-purpose controls register for Extended Operating Mode. Bit 7 6 ARET_TX_T S_EN 0x17 Access Reset z 5 4 AACK_FLTR_ RES_FT AACK_UPLD_ RES_FT 3 2 1 0 AACK _ACK_ TIME AACK_PROM_ MODE AACK_SPC_E N R/W R/W R/W R/W R R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 0 - AACK_SPC_EN The register bit AACK_SPC_EN enables the synchronization point correction (SPC) within RX_AACK mode. If SPC is enabled, then acknowledgement frame start time will be corrected against PEL_SHIFT_VALUE content. Table 40-36. AACK_SPC_EN Value Description 0x0 Synchronization point correction is disabled 0x1 Synchronization point correction is enabled Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1042 40.11.5 Frame Buffer Content Summary 40.11.5.1 TOM_CPM_0 for TOM_EN=0x01 Name: TOM_CPM_0 Offset: 0x73 Reset: 0x00 Property: - The TOM_CPM_0 register contains the result of synchronization correlator. Bit 7 6 5 4 3 2 1 0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 3 2 1 0 CPM_0 0x73 z Bit 7:0 - CPM_0 This register contains the CPM_0 value. Table 40-37. CPM_0 Value Description 0x00 Complex magnitude value; distance from main peak minus 1000ns. Valid values are [0xFF, 0xFE, ..., 0x00]. 40.11.5.2 TOM_CPM_1 for TOM_EN=0x01 Name: TOM_CPM_1 Offset: 0x74 Reset: 0x00 Property: - The TOM_CPM_1 register contains the result of synchronization correlator. Bit 7 6 5 4 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 CPM_1 0x74 z Bit 7:0 - CPM_1 This register contains the CPM_1 value. Table 40-38. CPM_1 Value Description 0x00 Complex magnitude value; distance from main peak minus 750ns. Valid values are [0xFF, 0xFE, ..., 0x00]. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1043 40.11.5.3 TOM_CPM_2 for TOM_EN=0x01 Name: TOM_CPM_2 Offset: 0x75 Reset: 0x00 Property: - The TOM_CPM_2 register contains the result of synchronization correlator. Bit 7 6 5 4 3 2 1 0 CPM_2 0x75 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 3 2 1 0 z Bit 7:0 - CPM_2 This register contains the CPM_2 value. Table 40-39. CPM_2 Value Description 0x00 Complex magnitude value; distance from main peak minus 500ns. Valid values are [0xFF, 0xFE, ..., 0x00]. 40.11.5.4 TOM_CPM_3 for TOM_EN=0x01 Name: TOM_CPM_3 Offset: 0x76 Reset: 0x00 Property: - The TOM_CPM_3 register contains the result of synchronization correlator. Bit 7 6 5 4 CPM_3 0x76 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bit 7:0 - CPM_3 This register contains the CPM_3 value. Table 40-40. CPM_3 Value Description 0x00 Complex magnitude value; distance from main peak minus 250ns. Valid values are [0xFF, 0xFE, ..., 0x00]. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1044 40.11.5.5 TOM_CPM_4 for TOM_EN=0x01 Name: TOM_CPM_4 Offset: 0x77 Reset: 0x00 Property: - The TOM_CPM_4 register contains the result of synchronization correlator. Bit 7 6 5 4 3 2 1 0 CPM_4 0x77 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 3 2 1 0 z Bit 7:0 - CPM_4 This register contains the CPM_4 value. Table 40-41. CPM_4 Value Description 0x00 Complex magnitude value; distance from main peak 0ns. Valid values are [0xFF, 0xFE, ..., 0x00]. 40.11.5.6 TOM_CPM_5) for TOM_EN=0x01 Name: TOM_CPM_5 Offset: 0x78 Reset: 0x00 Property: - The TOM_CPM_5 register contains the result of synchronization correlator. Bit 7 6 5 4 CPM_5 0x78 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bit 7:0 - CPM_5 This register contains the CPM_5 value. Table 40-42. CPM_5 Value Description 0x00 Complex magnitude value; distance from main peak plus 250ns. Valid values are [0xFF, 0xFE, ..., 0x00]. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1045 40.11.5.7 TOM_CPM_6) for TOM_EN=0x01 Name: TOM_CPM_6 Offset: 0x79 Reset: 0x00 Property: - The TOM_CPM_6 register contains the result of synchronization correlator. Bit 7 6 5 4 3 2 1 0 CPM_6 0x79 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 3 2 1 0 z Bit 7:0 - CPM_6 This register contains the CPM_6 value. Table 40-43. CPM_6 Value Description 0x00 Complex magnitude value; distance from main peak plus 500ns. Valid values are [0xFF, 0xFE, ..., 0x00]. 40.11.5.8 TOM_CPM_7 for TOM_EN=0x01 Name: TOM_CPM_7 Offset: 0x7A Reset: 0x00 Property: - The TOM_CPM_7 register contains the result of synchronization correlator. Bit 7 6 5 4 CPM_7 0x7A Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bit 7:0 - CPM_7 This register contains the CPM_7 value. Table 40-44. CPM_7 Value Description 0x00 Complex magnitude value; distance from main peak plus 750ns. Valid values are [0xFF, 0xFE, ..., 0x00]. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1046 40.11.5.9 TOM_CPM_8 for TOM_EN=0x01 Name: TOM_CPM_8 Offset: 0x7B Reset: 0x00 Property: - The TOM_CPM_8 register contains the result of synchronization correlator. Bit 7 6 5 4 3 2 1 0 CPM_8 0x7B Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bit 7:0 - CPM_8 This register contains the CPM_8 value. Table 40-45. CPM_8 Value Description 0x00 Complex magnitude value; distance from main peak plus 1000ns. Valid values are [0xFF, 0xFE, ..., 0x00]. 40.11.5.10 TOM_FEC for TOM_EN=0x01 Name: TOM_FEC Offset: 0x7C Reset: 0x00 Property: - The TOM_FEC register contains the result of a frequency offset measurement. Bit 7 6 5 4 3 2 1 0 FEC 0x7C Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bit 7:0 - FEC This register contains the FEC value. An initial frequency offset estimation is available after PHR field detection. An accumulated frequency offset measurement value over the frame duration is available at frame end. Table 40-46. FEC Value Description 0x00 Two's complement signed value in range of -500kHz, ..., 500kHz. Valid values are [0xFF, 0xFE, ..., 0x00]. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1047 40.11.5.11 TOM_TIM_0 for TOM_EN=0x01 Name: TOM_TIM_0 Offset: 0x7D Reset: 0x00 Property: - This register contains the lower 8-bit of the time-of-flight measurement, bits[7:0]. Bit 7 6 5 4 3 2 1 0 TIM_0 0x7D Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 3 2 1 0 z Bit 7:0 - TIM_0 Lower 8-bit of time-of-flight measurement, bits[7:0]. Table 40-47. TIM_0 Value Description 0x00 Timer/Counter measurement value based on 16MHz. Valid values are [0xFF, 0xFE, ..., 0x00]. 40.11.5.12 TOM_TIM_1 for TOM_EN=0x01 Name: TOM_TIM_1 Offset: 0x7E Reset: 0x00 Property: - This register contains 8-bit of the time-of-flight measurement, bits[15:8]. Bit 7 6 5 4 TIM_1 0x7E Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bit 7:0 - TIM_1 8-bit of time-of-flight measurement, bits[15:8]. Table 40-48. TIM_1 Value Description 0x00 Timer/Counter measurement value based on 16MHz. Valid values are [0xFF, 0xFE, ..., 0x00]. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1048 40.11.5.13 TOM_TIM_2 for TOM_EN=0x01 Name: TOM_TIM_2 Offset: 0x7F Reset: 0x00 Property: - This register contains the higher 8-bit of the time-of-flight measurement, bits[23:16]. Bit 7 6 5 4 3 2 1 0 TIM_2 0x7F Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bit 7:0 - TIM_2 Higher 8-bit of time-of-flight measurement, bits[23:16]. Table 40-49. TIM_2 Value Description 0x00 Timer/Counter measurement value based on 16MHz. Valid values are [0xFF, 0xFE, ..., 0x00]. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1049 40.12 Phase Difference Measurement The Phase Difference Measurement Unit (PMU) is characterized by: z Relative phase measurement of received signal 40.12.1 Overview The AT86RF233 performs a phase measurement of a received signal relative to an internal reference. The derived value represents the phase delay of the received signal referenced to an internal reference signal in the receiver low-IF domain, see "Receiver (RX)" on page 975. The measured value is captured in register bits PMU_VALUE (register 0x3B, PHY_PMU_VALUE) and periodically updated. 40.12.2 Register Description 40.12.2.1 TRX_CTRL_0 Name: TRX_CTRL_0 Offset: 0x03 Reset: 0x09 Property: - The TRX_CTRL_0 register controls the CLKM clock rate. Bit 7 6 TOM_EN 0x03 Access Reset z 5 4 3 2 PMU_EN PMU_IF_ INVERSE CLKM_ SHA_SEL 1 0 CLKM_CTRL R/W R R/W R/W R/W R/W R/W R/W 0 0 0 0 1 0 0 1 Bit 5 - PMU_EN The register bit PMU_EN controls the Phase Difference Measurement Unit mode. Table 40-50. PMU_EN Value Description 0x0 PMU mode is disabled 0x1 PMU mode is enabled z Bit 4 - PMU_IF_INVERSE The register bit PMU_IF_INVERSE controls the PMU Intermediate Frequency path. Table 40-51. PMU_IF_INVERSE Value Description 0x0 Normal IF position 0x1 Inverse IF position Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1050 40.12.2.2 PHY_PMU_VALUE for PMU_EN=0x01: Name: PHY_PMU_VALUE Offset: 0x3B Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 PMU_VALUE 0x03 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bit 7:0 - PMU_VALUE The register bits PMU_VALUE signals the PMU measurement value. Table 40-52. PMU_VALUE Value Description 0x00 Signals 8-bit PMU measurement value. The value is updated every 8s. Valid values are [0xFF, 0xFE, ..., 0x00]. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1051 41. AT86RF233 Register Reference The AT86RF233 provides a register space of 64 8-bit registers used to configure, control and monitor the radio transceiver. Note: All registers not mentioned within the following table are reserved for internal use and must not be overwritten. When writing to a register, any reserved bits shall be overwritten only with their reset value. Table 41-1. AT86RF233 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 0x01 TRX_STATUS CCA_DONE CCA_STATUS RESERVED 0x02 TRX_STATE 0x03 TRX_CTRL_0 TOM_EN RESERVED PMU_EN PMU_IF_ INVERSE 0x04 TRX_CTRL_1 PA_EXTN_EN IRQ_2_EXT_EN TX_AUTO_CRC_ ON RX_BL_ CTRL 0x05 PHY_TX_PWR RESERVED RESERVED 0x06 PHY_RSSI RX_CRC_VALID 0x07 PHY_ED_LEVEL 0x08 PHY_CC_CCA 0x09 CCA_THRES 0x0A RX_CTRL 0x0B SFD_VALUE 0x0C TRX_CTRL_2 RX_SAFE_MODE 0x0D ANT_DIV ANT_SEL 0x0E IRQ_MASK 0x0F IRQ_STATUS IRQ_7_BAT_LOW IRQ_6_TRX_UR 0x10 VREG_CTRL AVREG_EXT AVDD_OK Bit 2 Bit 1 Bit 0 TRX_STATUS 913, 933, 970 TRX_CMD 914, 935 TRAC_STATUS CKLM_SHA_ SEL 992, 1041, 1050 CLKM_CTRL IRQ_MASK_ MODE SPI_CMD_MODE RESERVED IRQ_ POLARITY 963, 965, 1013 RSSI 967 ED_LEVEL CCA_MODE 971, 996 CHANNEL RESERVED PEL_SHIFT_VALUE RESERVED RESERVED CCA_ED_THRES 972 PDT_THRES 1022, 1041 1033 SFD_VALUE RESERVED RESERVED OQPSK_DATA_RATE RESERVED RESERVED ANT_EXT_ SW_EN ANT_DIV_EN ANT_CTRL IRQ_4_CCA_ ED_DONE RESERVED 1032 1023 898 IRQ_MASK IRQ_5_AMI 890, 900, 937, 963, 1026, 1028, 1031 980 TX_PWR RND_VALUE CCA_REQUEST Page IRQ_3_TRX_ END IRQ_2_ RX_START DVREG_EXT DVDD_OK BATMON_ HR IRQ_1_PLL_ UNLOCK IRQ_0_PLL_ LOCK RESERVED 899 986 BATMON_VTH 988 XTAL_TRIM 993 0x11 BATMON 0x12 XOSC_CTRL 0x13 CC_CTRL_0 0x14 CC_CTRL_1 0x15 RX_SYN 0x16 TRX_RPC 0x17 XAH_CTRL_1 ARET_TC_TS_EN RESERVED 0x18 FTN_CTRL FTN_START RESERVED 0x19 XAH_CTRL_2 0x1A PLL_CF PLL_CF_START RESERVED 0x1B PLL_DCU PLL_DCU_START RESERVED 0x1C PART_NUM PART_NUM 891 0x1D VERSION_NUM VERSION_NUM 892 RESERVED RESERVED BATMON_OK XTAL_MODE 997 CC_NUMBER RESERVED RX_PDT_DIS RESERVED RX_RPC_CTRL CC_BAND 997 RX_PDT_LEVEL 976 RX_RPC_EN PDT_RPC_ EN PLL_RPC_EN XAH_TX_ RPC_EN IPAN_RPC_ EN RESERVED 1037 AACK_FLTR_ RES_FT AACK_UPLD_ RES_FT RESERVED AACK_ACK _TIME AACK_PRO M_MODE AACK_SPC_ EN 938, 954, 1028, 1042 1001 FTNV ARET_FRAME_RETIRES ARET_CSMA_RETRIES RESERVED RESERVED PLL_CF RESERVED Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 940 998 999 1052 Table 41-1. AT86RF233 Register Summary (Continued) Address Name 0x1E MAN_ID_0 MAN_ID_0 892 0x1F MAN_ID_1 MAN_ID_1 893 0x20 SHORT_ADDR_0 SHORT_ADDR_0 957 0x21 SHORT_ADDR_1 SHORT_ADDR_1 957 0x22 PAN_ID_0 PAN_ID_0 957 0x23 PAN_ID_1 PAN_ID_1 958 0x24 IEEE_ADDR_0 IEEE_ADDR_0 958 0x25 IEEE_ADDR_1 IEEE_ADDR_1 958 0x26 IEEE_ADDR_2 IEEE_ADDR_2 959 0x27 IEEE_ADDR_3 IEEE_ADDR_3 959 0x28 IEEE_ADDR_4 IEEE_ADDR_4 959 0x29 IEEE_ADDR_5 IEEE_ADDR_5 960 0x2A IEEE_ADDR_6 IEEE_ADDR_6 960 0x2B IEEE_ADDR_7 IEEE_ADDR_7 960 0x2C XAH_CTRL_0 0x2D CSMA_SEED_0 0x2E CSMA_SEED_1 0x2F CSMA_BE 0x36 TST_CTRL_DIGI 0x3C TST_AGC 0x3D TST_SDM Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 MAX_FRAME_RETRIES Bit 2 Bit 1 Bit 0 SLOTTED_ OPERATION MAX_CSMA_RETRIES AACK_FVN_MODE AACK_SET_PD AACK_I_AM_ COORD MAX_BE RESERVED RESERVED RESERVED MOD_SEL RESERVED RESERVED AGC_HOLD_SEL AGC_RST TX_RX TX_RX_SEL MOD 941 943 CSMA_SEED_0 AACK_DIS_ ACK Page AGC_OFF CSMA_SEED_1 944, 955 MIN_BE 946 TST_CTRL_DIGI 1169 AGC_HOLD GC 977 RESERVED 999 IRC_TX_TIME 981 Register Page - TOM_EN=0x01 0x3B PHY_TX_TIME RESERVED Register Page - PMU_EN=0x01 0x3B PHY_PMU_VALUE 1051 PMU_VALUE The reset values of the AT86RF233 registers in state P_ON(1, 2, 3) are shown in Table 41-2 on page 1054. Note: All reset values in Table 41-2 on page 1054 are only valid after a power on reset. After a reset procedure (/RST = L) as described in "Reset Procedure" on page 909, the reset values of selected registers (for example registers 0x01, 0x10, 0x11, 0x30) can differ from that in Table 41-2 on page 1054. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1053 Table 41-2. AT86RF233 Register Summary - Reset Values Address Reset Value Address Reset Value Address Reset Value Address Reset Value 0x00 0x00 0x10 0x00 0x20 0xFF 0x30 0x00 0x01 0x00 0x11 0x02 0x21 0xFF 0x31 0x00 0x02 0x00 0x12 0xF0 0x22 0xFF 0x32 0x00 0x03 0x09 0x13 0x00 0x23 0xFF 0x33 0x00 0x04 0x22 0x14 0x00 0x24 0x00 0x34 0x00 0x05 0x00 0x15 0x00 0x25 0x00 0x35 0x00 0x06 0x60 0x16 0xC1 0x26 0x00 0x36 0x00 0x07 0xFF 0x17 0x00 0x27 0x00 0x37 0x00 0x08 0x2B 0x18 0x58 0x28 0x00 0x38 0x00 0x09 0xC7 0x19 0x00 0x29 0x00 0x39 0x40 0x0A 0X37 0x1A 0x57 0x2A 0x00 0x3A 0x00 0x0B 0xA7 0x1B 0x20 0x2B 0x00 0x3B 0x00 0x0C 0x20 0x1C 0x0B 0x2C 0x38 0x3C 0x00 0x0D 0x00 0x1D 0x02 0x2D 0xEA 0x3D 0x00 0x0E 0x00 0x1E 0x1F 0x2E 0x42 0x3E 0x00 0x0F 0x00 0x1F 0x00 0x2F 0x53 0x3F 0x00 Notes: 1. While the reset value of register 0x10 is 0x00, any practical access to the register is only possible when DVREG is active. So this register is always read out as 0x04. For details, refer to "Voltage Regulators (AVREG, DVREG)" on page 983. 2. While the reset value of register 0x11 is 0x02, any practical access to the register is only possible when BATMON is activated. So this register is always read out as 0x22 in P_ON state. For details, refer to "Battery Monitor (BATMON)" on page 987. 3. While the reset value of register 0x30 is 0x00, any practical access to the register is only possible when the radio transceiver is accessible. So the register is usually read out as: z 0x11 after a reset in P_ON state z 0x07 after a reset in any other state Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1054 42. Electrical Characteristics 42.1 Disclaimer All typical values are measured at T = 25C unless otherwise specified. All minimum and maximum values are valid across operating temperature and voltage unless otherwise specified. 42.2 Absolute Maximum Ratings Stresses beyond those listed in Table 42-1 may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 42-1. Absolute Maximum Ratings Symbol Parameter Condition Min. Max. Units VDD Power supply voltage 0 3.8 V IVDD Current into a VDD pin - 92 mA IGND Current out of a GND pin - 130 mA VPIN Pin voltage with respect to GND and VDD GND-0.3V VDD+0.3V V VANA Voltage on RFP, RFN, AVDD and DVDD -0.3 2.0 V VESD ESD robustness PRF Input RF level TLEAD Lead temperature Tstorage Storage temperature Human Body Model (HBM) [4] 4 kV Charged Device Model (CDM) [5] 550 V T = 10s (soldering profile compliant with IPC/JEDEC J STD 020B) -60 +10 dBm 260 C 150 C Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1055 42.3 General Operating Ratings The device must operate within the ratings listed in Table 42-2 in order for all other electrical characteristics and typical characteristics of the device to be valid. Table 42-2. General Operating Conditions Symbol Parameter Condition Min. Typ. Max. Units 1.8(1) 3.3 3.6 V 1.7 1.8 1.9 V 1.8(1) 3.3 3.6 V -40 25 125 C - - 100 C VDD Power supply voltage Voltage on VDDIN, VDDIO and VDDANA(2) VDD1.8 Power supply voltage (on AVDD and DVDD) External supply voltage(3) VDDANA Analog supply voltage TA Temperature range TJ Junction temperature Notes: 1. With BOD33 disabled. If the BOD33 is enabled, check Table 42-17. 2. Even if an implementation uses the external 1.8V voltage supply VDD1.8 it is required to connect VDD. 3. AT86RF233 register 0x10 (VREG_CTRL) needs to be programmed to disable internal voltage regulators and supply blocks by an external 1.8V supply, refer to "Voltage Regulators (AVREG, DVREG)" on page 983. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1056 42.4 Supply Characteristics The following characteristics are applicable to the operating temperature range: TA = -40C to 85C, unless otherwise specified and are valid for a junction temperature up to TJ = 100C. Refer to "Power Supply and Start-Up Considerations" on page 20. Table 42-3. Supply Characteristics Voltage Symbol Conditions VDDIO VDDIN VDDANA Full Voltage Range Min. Max. Units 1.8 3.6 V Table 42-4. Supply Rise Rates Rise Rate 42.5 Symbol Parameter VDDIO VDDIN VDDANA DC supply peripheral I/Os, internal regulator and analog supply voltage Max. Units 0.1 V/s Maximum Clock Frequencies Table 42-5. Maximum GCLK Generator Output Frequencies Symbol Description Conditions Max. Units 96 MHz 48 MHz Max. Units fGCLKGEN0 / fGCLK_MAIN fGCLKGEN1 fGCLKGEN2 fGCLKGEN3 fGCLKGEN4 fGCLKGEN5 Undivided GCLK Generator Output Frequency fGCLKGEN6 Divided fGCLKGEN7 fGCLKGEN8 Table 42-6. Maximum Peripheral Clock Frequencies Symbol Description fCPU CPU clock frequency 48 MHz fAHB AHB clock frequency 48 MHz fAPBA APBA clock frequency 48 MHz fAPBB APBB clock frequency 48 MHz fAPBC APBC clock frequency 48 MHz Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1057 Table 42-6. Maximum Peripheral Clock Frequencies (Continued) Symbol Max. Units DFLL48M Reference clock frequency 33 KHz FDPLL96M Reference clock frequency 2 MHz FDPLL96M 32k Reference clock frequency 32 KHz fGCLK_WDT WDT input clock frequency 48 MHz fGCLK_RTC RTC input clock frequency 48 MHz fGCLK_EIC EIC input clock frequency 48 MHz fGCLK_USB USB input clock frequency 48 MHz fGCLK_EVSYS_CHANNEL_0 EVSYS channel 0 input clock frequency 48 MHz fGCLK_EVSYS_CHANNEL_1 EVSYS channel 1 input clock frequency 48 MHz fGCLK_EVSYS_CHANNEL_2 EVSYS channel 2 input clock frequency 48 MHz fGCLK_EVSYS_CHANNEL_3 EVSYS channel 3 input clock frequency 48 MHz fGCLK_EVSYS_CHANNEL_4 EVSYS channel 4 input clock frequency 48 MHz fGCLK_EVSYS_CHANNEL_5 EVSYS channel 5 input clock frequency 48 MHz fGCLK_EVSYS_CHANNEL_6 EVSYS channel 6 input clock frequency 48 MHz fGCLK_EVSYS_CHANNEL_7 EVSYS channel 7 input clock frequency 48 MHz fGCLK_EVSYS_CHANNEL_8 EVSYS channel 8 input clock frequency 48 MHz fGCLK_EVSYS_CHANNEL_9 EVSYS channel 9 input clock frequency 48 MHz fGCLK_EVSYS_CHANNEL_10 EVSYS channel 10 input clock frequency 48 MHz fGCLK_EVSYS_CHANNEL_11 EVSYS channel 11 input clock frequency 48 MHz fGCLK_SERCOMx_SLOW Common SERCOM slow input clock frequency 48 MHz fGCLK_SERCOM0_CORE SERCOM0 input clock frequency 48 MHz fGCLK_SERCOM1_CORE SERCOM1 input clock frequency 48 MHz fGCLK_SERCOM2_CORE SERCOM2 input clock frequency 48 MHz fGCLK_SERCOM3_CORE SERCOM3 input clock frequency 48 MHz fGCLK_SERCOM4_CORE SERCOM4 input clock frequency 48 MHz fGCLK_SERCOM5_CORE SERCOM5 input clock frequency 48 MHz fGCLK_TCC0, GCLK_TCC1 TCC0,TCC1 input clock frequency 96 MHz fGCLK_TCC2, GCLK_TC3 TCC2,TC3 input clock frequency 96 MHz fGCLK_TC4, GCLK_TC5 TC4,TC5 input clock frequency 48 MHz ADC input clock frequency 48 MHz fGCLK_DFLL48M_REF fGCLK_DPLL fGCLK_DPLL_32K fGCLK_ADC Description Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1058 Table 42-6. Maximum Peripheral Clock Frequencies (Continued) Symbol Description Max. Units fGCLK_AC_DIG AC digital input clock frequency 48 MHz fGCLK_AC_ANA AC analog input clock frequency 64 KHz PTC input clock frequency 48 MHz fGCLK_PTC Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1059 42.6 Power Consumption The values in are measured values of power consumption under the following conditions, except where noted: z Operating conditions z VVDDIN = 3.3V z Wake up time from sleep mode is measured from the edge of the wakeup signal to the execution of the first instruction fetched in flash. z Oscillators z z z XOSC (crystal oscillator) stopped z XOSC32K (32kHz crystal oscillator) running with external 32kHz crystal z DFLL48M using XOSC32K as reference and running at 48MHz Clocks z DFLL48M used as main clock source, except otherwise specified z CPU, AHB clocks undivided z APBA clock divided by 4 z APBB and APBC bridges off The following AHB module clocks are running: NVMCTRL, APBA bridge z z All other AHB clocks stopped The following peripheral clocks running: PM, SYSCTRL, RTC z All other peripheral clocks stopped z I/Os are inactive with internal pull-up z CPU is running on flash with 1 wait states z NVMCTRL cache enabled z BOD33 disabled z AT86RF233 has to be set in Deep Sleep Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1060 Table 42-7. Current Consumption Mode Conditions TA Min. Typ. Max. 25C 3.11 3.37 3.64 85C 3.24 3.48 3.76 CPU running a While(1) algorithm VDDIN=1.8V, CPU is running on Flash with 3 wait states 25C 3.10 3.36 3.64 85C 3.24 3.48 3.75 CPU running a While(1) algorithm, CPU is running on Flash with 3 wait states with GCLKIN as reference 25C 60*freq + 74 60*freq + 136 62*freq + 196 85C 62*freq + 154 62*freq + 228 62*freq + 302 25C 4.12 4.53 4.92 85C 4.27 4.63 4.98 CPU running a Fibonacci algorithm VDDIN=1.8V, CPU is running on flash with 3 25C 4.12 4.53 4.92 wait states 85C 4.27 4.63 4.98 CPU running a Fibonacci algorithm, CPU is running on Flash with 3 wait states with GCLKIN as reference 25C 86*freq + 76 88*freq + 136 88*freq + 196 85C 88*freq + 156 88*freq + 230 88*freq + 302 25C 5.78 6.32 6.80 85C 5.93 6.47 7.00 CPU running a CoreMark algorithm VDDIN=1.8V, CPU is running on flash with 3 25C 5.17 5.60 5.96 wait states 85C 5.35 5.73 6.10 CPU running a CoreMark algorithm, CPU is running on Flash with 3 wait states with GCLKIN as reference 25C 106*freq + 78 106*freq + 136 108*freq + 196 85C 106*freq + 154 108*freq + 232 108*freq + 310 25C 1.89 2.04 2.20 85C 1.98 2.14 2.33 25C 1.34 1.46 1.58 85C 1.41 1.55 1.71 25C 1.07 1.17 1.28 85C 1.13 1.27 1.40 25C - 4.06 12.8 85C - 55.2 100 25C - 2.70 12.2 85C - 53.3 100 CPU running a While(1) algorithm CPU running a Fibonacci algorithm ACTIVE CPU running a CoreMark algorithm IDLE0 Default operating conditions IDLE1 I IDLE2 I Default operating conditions Default operating conditions XOSC32K running RTC running at 1kHz STANDBY XOSC32K and RTC stopped Units mA A (with freq in MHz) mA A (with freq in MHz) mA A (with freq in MHz) Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 mA A 1061 Table 42-7. Current Consumption (Continued) Mode Conditions XOSC32K running RTC running at 1kHz STANDBY (SAMR21E19A) XOSC32K and RTC stopped TA Min. Typ. Max. 25C - 5.1 17.8 85C - 60.2 105.0 25C - 3.7 17.2 85C - 58.3 105.0 Units A Table 42-8. Wake-up Time Mode Conditions IDLE0 OSC8M used as main clock source, Cache disabled IDLE1 I IDLE2 I STANDBY I OSC8M used as main clock source, Cache disabled OSC8M used as main clock source, Cache disabled OSC8M used as main clock source, Cache disabled TA Min. Typ. Max. 25C - 4.0 - 85C - 4.0 - 25C - 12.1 - 85C - 13.6 - 25C - 13.0 - 85C - 14.5 - 25C - 19.6 - 85C - 19.7 - Units s Figure 42-1. Measurement Schematic VDDIN VDDANA VDDIO Amp 0 VDDCORE Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1062 42.7 Peripheral Power Consumption Since USB peripheral complies with the Universal Serial Bus (USB) v2.0 standard, USB peripheral power consumption is described a specific section 42.7.1 All peripheral except USB Default conditions, except where noted: z Operating conditions z z z VVDDIN = 3.3V Oscillators z XOSC (crystal oscillator) stopped z XOSC32K (32kHz crystal oscillator) running with external 32kHz crystal z OSC8M at 8MHz Clocks z OSC8M used as main clock source z CPU, AHB and APBn clocks undivided z The following AHB module clocks are running: NVMCTRL, HPB2 bridge, HPB1 bridge, HPB0 bridge z The following peripheral clocks running: PM, SYSCTRL z z All other AHB clocks stopped All other peripheral clocks stopped z I/Os are inactive with internal pull-up z CPU in IDLE0 mode z Cache enabled z BOD33 disabled In this default conditions, the power consumption Idefault is measured. Operating mode for each peripheral in turn: z Configure and enable the peripheral GCLK (When relevant, see conditions) z Unmask the peripheral clock z Enable the peripheral (when relevant) z Set CPU in IDLE0 mode z Measurement Iperiph z Wake-up CPU via EIC (async: level detection, filtering disabled) z Disable the peripheral (when relevant) z Mask the peripheral clock z Disable the peripheral GCLK (when relevant, see conditions) Each peripheral power consumption provided in table x.y is the value (Iperiph - Idefault), using the same measurement method as for global power consumption measurement Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1063 Table 42-9. Typical Peripheral Current Consumption Peripheral Conditions Typ. Units RTC fGCLK_RTC = 32kHz, 32bit counter mode 7.4 A WDT fGCLK_WDT=32kHz, normal mode with EW 5.5 A Both fGCLK=8MHz, Enable both COMP 31.3 A 50 A AC TCx(1) fGCLK=8MHz, Enable + COUNTER in 8bit mode TCC2 fGCLK=8MHz, Enable + COUNTER 95.5 A TCC1 fGCLK=8MHz, Enable + COUNTER 167.5 A TCC0 fGCLK=8MHz, Enable + COUNTER 180.3 A SERCOMx. I2CM(2) fGCLK=8MHz, Enable 69.7 A SERCOMx. I2CS fGCLK=8MHz, Enable 29.2 A SERCOMx. SPI fGCLK=8MHz, Enable 64.6 A SERCOMx. USART fGCLK=8MHz, Enable 65.5 A DMAC(3) RAM to RAM transfer 399.5 A Notes: 1. All TCs from 4 to 7 share the same power consumption values. 2. All SERCOMs from 0 to 5 share the same power consumption values. 3. The value includes the power consumption of the R/W access to the RAM. 42.7.2 USB Peripheral Power Consumption Default conditions, except where noted: z Operating conditions z VVDDIN = 3.3V z Oscillators z Clocks z z XOSC32K (32kHz crystal oscillator) running with external 32kHz crystal in USB Host mode z USB Device mode: DFLL48M in USB recovery mode (Crystal less) z USB Host mode: DFLL48M in closed loop with XOSC32K (32kHz crystal oscillator) running with external 32kHz crystal z CPU, AHB and APBn clocks undivided The following AHB module clocks are running: NVMCTRL, HPB2 bridge, HPB1 bridge, HPB0 bridge z All other AHB clocks stopped z I/Os are inactive with internal pull-up z CPU in IDLE0 mode z Cache enabled z BOD33 disabled In this default conditions, the power consumption Idefault is measured. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1064 Measurements do not include consumption of clock source (ex: DFLL48M or FDPLL96M) and CPU. However no CPU activity is required during all states (Suspend, IDLE, Data transfer). Measurements have been done with an USB cable of 1.5m. For USB Device mode, measurements include the maximum consumption (200 A) through pull-up resistor on the D+ line for USB attach. This value depends on USB Host characteristic. Operating modes: z Run the USB Device/Host states in regards of the Universal Serial Bus (USB) v2.0 standard. USB power consumption is provided in the following tables. Table 42-10. Typical USB Device Full Speed mode Current Consumption USB Device state Suspend Suspend IDLE Active OUT Active IN Conditions GCLK_USB is off, using USB wakeup asynchronous interrupt. USB bus in suspend mode. GCLK_USB is on. USB bus in suspend mode. Start Of Frame is running. No packet transferred. Start Of Frame is running. Bulk OUT on 100% bandwidth. Start Of Frame is running. Bulk IN on 100% bandwidth. Typ. Units 201 A 0.83 mA 1.17 mA 2.17 mA 10.3 mA Typ. Units 0.10 A 0.19 mA 201 A 0.83 mA Table 42-11. Typical USB Host Full Speed mode Current Consumption USB Device state Wait connection Wait connection Suspend Suspend Conditions GCLK_USB is off, using USB wakeup asynchronous interrupt. USB bus not connected. GCLK_USB is on. USB bus not connected. GCLK_USB is off, using USB wakeup asynchronous interrupt. USB bus in suspend mode. GCLK_USB is on. USB bus in suspend mode. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1065 Table 42-11. Typical USB Host Full Speed mode Current Consumption (Continued) USB Device state IDLE Active OUT Active IN Conditions Start Of Frame is running. No packet transferred. Start Of Frame is running. Bulk OUT on 100% bandwidth. Start Of Frame is running. Bulk IN on 100% bandwidth. Typ. Units 1.17 mA 2.17 mA 10.3 mA Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1066 42.8 I/O Pin Characteristics 42.8.1 Normal I/O Pins Table 42-12. Normal I/O Pins Characteristics Symbol Parameter RPULL Pull-up - Pull-down resistance VIL Input low-level voltage VIH Input high-level voltage VOL Output low-level voltage VOH Output high-level voltage IOL Output low-level current IOH Output high-level current tRISE Rise time (1) tFALL Fall time ILEAK Note: (1) Input leakage current 1. Conditions Min. Typ. Max. Units 20 40 60 k VDD=1.8V-2.7V - - 0.25*VDD VDD=2.7V-3.6V - - 0.3*VDD VDD=1.8V-2.7V 0.7*VDD - - VDD=2.7V-3.6V 0.55*VDD - - VDD>1.6V, IOL maxI - 0.1*VDD 0.2*VDD VDD>1.6V, IOH maxI 0.8*VDD 0.9*VDD - VDD=1.8V-3V, PORT.PINCFG.DRVSTR=0 - - 1 VDD=3V-3.6V, PORT.PINCFG.DRVSTR=0 - - 2.5 VDD=1.8V-3V, PORT.PINCFG.DRVSTR=1 - - 3 VDD=3V-3.6V, PORT.PINCFG.DRVSTR=1 - - 10 VDD=1.8V-3V, PORT.PINCFG.DRVSTR=0 - - 0.70 VDD=3V-3.6V, PORT.PINCFG.DRVSTR=0 - - 2 VDD=1.8V-3V, PORT.PINCFG.DRVSTR=1 - - 2 VDD=3V-3.6V, PORT.PINCFG.DRVSTR=1 - - 7 PORT.PINCFG.DRVSTR=0 load = 5pF, VDD = 3.3V - - 15 PORT.PINCFG.DRVSTR=1 load = 20pF, VDD = 3.3V - - 15 PORT.PINCFG.DRVSTR=0 load = 5pF, VDD = 3.3V - - 15 PORT.PINCFG.DRVSTR=1 load = 20pF, VDD = 3.3V - - 15 Pull-up resistors disabled -1 +/-0.015 1 I V mA nS nS A These values are based on simulation. These values are not covered by test limits in production or characterization. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1067 42.8.2 I2C Pins Refer to "I/O Multiplexing and Considerations" on page 12 to get the list of I2C pins. Table 42-13. I2C Pins Characteristics in I2C configuration Symbol Parameter RPULL Pull-up - Pull-down resistance VIL Input low-level voltage VIH Input high-level voltage VHYS Hysteresis of Schmitt trigger inputs VOL CI IOL Output low-level voltage Capacitance for each I/O Pin Output low-level current fSCL SCL clock frequency RP Value of pull-up resistor Condition Min. Typ. Max. Units 20 40 60 k VDD=1.8V-2.7VI - - 0.25*VDD VDD=2.7V-3.6V - - 0.3*VDD VDD=1.8V-2.7V 0.7*VDD - - VDD=2.7V-3.6VI 0.55*VDD - - 0.08*VDD - - VDD> 2.0VI, IOL=3mA - - 0.4 VDD2.0V IOL=2mA - - 0.2*VDD I V pF I VOL =0.4V Standard, Fast and HS Modes 3 VOL =0.4V Fast Mode + 20 - - VOL =0.6V 6 - - I - - 3.4 mA MHz fSCL 100kHz fSCL > 100kHz I2C pins timing characteristics can be found in "SERCOM in I2C Mode Timing" on page 1098. 42.8.3 XOSC Pin XOSC pins behave as normal pins when used as normal I/Os. Refer to table "Normal I/O Pins Characteristics". 42.8.4 XOSC32 Pin XOSC32 pins behave as normal pins when used as normal I/Os. Refer to table "Normal I/O Pins Characteristics". 42.8.5 External Reset Pin Reset pin has the same electrical characteristics as normal I/O pins. Refer to table "Normal I/O Pins Characteristics". Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1068 42.9 Analog Characteristics 42.9.1 Voltage Regulator Characteristics Table 42-14. Voltage Regulator Electrical Characteristics Symbol VDDCORE Note: Parameter Conditions Voltage regulator normal mode DC calibrated output voltage Min. Typ. Max. Units 1.1 1.23 1.30 V Supplying any external components using VDDCORE pin is not allowed to assure the integrity of the core supply voltage. Table 42-15. Decoupling requirements Symbol Parameter CIN Input regulator capacitor, between VDDIN and GND COUT Output regulator capacitor, between VDDCORE and GND Conditions I Min. Typ. Max. Units - 1 - F 0.8 1 - F 42.9.2 Power-On Reset (POR) Characteristics Table 42-16. POR Characteristics Symbol Parameter VPOT+ Voltage threshold on VDD rising VPOT- Voltage threshold on VDD falling Conditions I Min. Typ. Max. Units 1.27 1.45 1.58 V 0.72 0.99 1.32 V VDD falls at 1V/ms or slower Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1069 VDD Figure 42-2. POR Operating Principle VPOT+ VPOT- Reset Time 42.9.3 Brown-Out Detectors Characteristics 42.9.3.1 BOD33 Figure 42-3. BOD33 Hysteresis OFF VCC VBOD RESET Figure 42-4. BOD33 Hysteresis ON VCC VBOD- VBOD+ RESET Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1070 Table 42-17. BOD33 LEVEL Value Symbol BOD33.LEVEL Conditions Min. Typ. Max. - 1.715 1.745 - 1.750 1.779 - 2.84 2.92 48 - 3.2 3.3 6 1.62 1.64 1.67 1.64 1.675 1.71 2.72 2.77 2.81 3.0 3.07 3.2 6 7 VBOD+ Hysteresis ON 39 VBODor 7 VBOD 39 Hysteresis ON or Hysteresis OFF 48 Note: Units V See chapter Memories table "NVM User Row Mapping" on page 25 for the BOD33 default value settings. Table 42-18. BOD33 Characteristics Symbol Parameter Conditions I Step size, between adjacent values in BOD33.LEVEL I VHYST VBOD+ - VBOD- Hysteresis ON tDET Detection time Time with VDDANA < VTH necessary to generate a reset signal tSTARTUP Startup time I IIdleBOD33 ISbyBOD33 Note: Current consumption in Active/Idle Mode Current Consumption in Standby mode 1. Continuous mode Sampling mode Sampling mode Temp. -40 to 85C Min. Typ. Max. Units - 34 - mV 35 - 170 mV - 0.9(1) - s - 2.2(1) - s 25 48 25C -40 to 85C - - 50 25C - 0.034 0.21 -40 to 85C - - 1.62 25C - 0.132 0.38 -40 to 85C - - 1 A A These values are based on simulation. These values are not covered by test limits in production or characterization. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1071 42.9.4 Analog-to-Digital (ADC) Characteristics Table 42-19. Operating Conditions Symbol Parameter RES Resolution ADC Clock frequency fCLK_ADC Conditions Min. Typ. Max. Units I 8 - 12 bits I 30 - 2100 kHz 1000 ksps Conversion speed Sample rate(1) 10 Single shot 5 - 300 ksps Free running 5 - 350 ksps 0.5 - - cycles 6 - - cycles Sampling time(1) Conversion time(1) 1x Gain VREF Voltage reference range 1.0 - VDDANA-0.6 V VREFINT1V Internal 1V reference (2) - 1.0 - V Internal ratiometric reference 0(2) - VDDANA/1.48 - V VREFINTVCC0 VREFINTVCC0 Voltage Error VREFINTVCC1 VREFINTVCC1 Voltage Error Internal ratiometric reference 0(2) error 2.0V < VDDANA<3.63V -1.0 - +1.0 % Internal ratiometric reference 1(2) VDDANA>2.0V - VDDANA/2 - V Internal ratiometric reference 1(2) error 2.0V < VDDANA<3.63V -1.0 - +1.0 % -VREF/GAIN - +VREF/GAIN V 0.0 - +VREF/GAIN V Conversion range(1) Differential mode Single-ended mode CSAMPLE Sampling capacitance(2) - 3.5 - pF RSAMPLE Input channel source resistance(2) - - 3.5 k IDD DC supply current(1) - 1.25 1.79 mA Notes: 1. fCLK_ADC = 2.1MHzI(3) These values are based on characterization. These values are not covered by test limits in production. 2. These values are based on simulation. These values are not covered by test limits in production or characterization. 3. In this condition and for a sample rate of 350ksps, 1 Conversion at gain 1x takes 6 clock cycles of the ADC clock. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1072 Table 42-20. Differential Mode Symbol ENOB Parameter Conditions Min. Typ. Max. Units - 10.5 11.1 bits Effective Number Of Bits With gain compensation TUE Total Unadjusted Error I 1x Gainn 1.5 4.3 15.0 LSB INLI Integral Non Linearity 1x Gainn 1.0 1.3 4.5 LSB DNL Differential Non Linearity 1x Gainn +/-0.3 +/-0.5 +/-0.95 LSB Ext. Ref 1x -10.0 2.5 +10.0 mV VREF=VDDANA/1.48 -15.0 -1.5 +10.0 mV Bandgap -20.0 -5.0 +20.0 mV Ext. Ref. 0.5x +/-0.1 +/-0.2 +/-0.45 % Ext. Ref. 2x to 16x +/-0.05 +/-0.1 +/-0.11 % Ext. Ref. 1x -5.0 -1.5 +5.0 mV VREF=VDDANA/1.48 -5.0 0.5 +5.0 mV Bandgap -5.0 3.0 +5.0 mV 62.7 70.0 75.0 dB I Gain Error I I Gain Accuracy(5) Offset Error SFDR Spurious Free Dynamic Range SINAD Signal-to-Noise and Distortion FCLK_ADC = 2.1MHz 54.1 65.0 68.5 dB Signal-to-Noise Ratio FIN = 40kHz 54.5 65.5 68.6 dB Total Harmonic Distortion AIN = 95%FSR -77.0 -64.0 -63.0 dB Noise RMS T=25C 0.6 1.0 1.6 mV SNR THD 1x Gain Notes: 1. Maximum numbers are based on characterization and not tested in production, and valid for 5% to 95% of the input voltage range. 2. Dynamic parameter numbers are based on characterization and not tested in production. 3. Respect the input common mode voltage through the following equations (where VCM_IN is the Input channel common mode voltage): a. b. If |VIN| > VREF/4 z VCM_IN < 0.95*VDDANA + VREF/4 - 0.75V z VCM_IN > VREF/4 -0.05*VDDANA -0.1V If |VIN| < VREF/4 z VCM_IN < 1.2*VDDANA - 0.75V z VCM_IN > 0.2*VDDANA - 0.1V 4. The ADC channels on pins PA08, PA09 are powered from the VDDIO power supply. The ADC performance of these pins will not be the same as all the other ADC channels on pins powered from the VDDANA power supply. 5. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x 100) / (2*Vref/GAIN) Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1073 Table 42-21. Single-Ended Mode Symbol ENOB Parameter Conditions Min. Typ. Max. Units Effective Number of Bits With gain compensation - 9.5 9.8 Bits TUE Total Unadjusted Error 1x gain - 10.5 14.0 LSB INL Integral Non-Linearity 1x gain 1.0 1.6 3.5 LSB DNL Differential Non-Linearity 1x gain +/-0.5 +/-0.6 +/-0.95 LSB Gain Error Ext. Ref. 1x -5.0 0.7 +5.0 mV Ext. Ref. 0.5x +/-0.2 +/-0.34 +/-0.4 % Ext. Ref. 2x to 16X +/-0.01 +/-0.1 +/-0.2 % -5.0 1.5 +5.0 mV 63.1 65.0 67.0 dB Gain Accuracy(4) Offset Error Ext. Ref. 1x SFDR Spurious Free Dynamic Range SINAD Signal-to-Noise and Distortion FCLK_ADC = 2.1MHz 47.5 59.5 61.0 dB Signal-to-Noise Ratio FIN = 40kHz 48.0 60.0 64.0 dB Total Harmonic Distortion AIN = 95%FSR -65.4 -63.0 -62.1 dB Noise RMS T = 25C - 1.0 - mV SNR THD 1x Gain Notes: 1. Maximum numbers are based on characterization and not tested in production, and for 5% to 95% of the input voltage range. 2. Respect the input common mode voltage through the following equations (where VCM_IN is the Input channel common mode voltage) for all VIN: z VCM_IN < 0.7*VDDANA + VREF/4 - 0.75V z VCM_IN > VREF/4 - 0.3*VDDANA - 0.1V 3. The ADC channels on pins PA08, PA09 are powered from the VDDIO power supply. The ADC performance of these pins will not be the same as all the other ADC channels on pins powered from the VDDANA power supply. 4. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x 100) / (Vref/GAIN) 42.9.4.1 Performance with the Averaging Digital Feature Averaging is a feature which increases the sample accuracy. ADC automatically computes an average value of multiple consecutive conversions. The numbers of samples to be averaged is specified by the Number-of-Samples-to-becollected bit group in the Average Control register (AVGCTRL.SAMPLENUM[3:0]) and the averaged output is available in the Result register (RESULT). Table 42-22. Averaging Feature Average Number Conditions 1 8 32 128 In differential mode, 1x gain, VDDANA=3.0V, VREF=1.0V, 350kSps at 25C SINAD (dB) SFDR (dB) ENOB (bits) 66.0 65.0 72.8 9.75 67.6 65.8 75.1 10.62 69.7 67.1 75.3 10.85 70.4 67.5 75.5 10.91 SNR (dB) Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1074 42.9.4.2 Performance with the hardware offset and gain correction Inherent gain and offset errors affect the absolute accuracy of the ADC. The offset error cancellation is handled by the Offset Correction register (OFFSETCORR) and the gain error cancellation, by the Gain Correction register (GAINCORR). The offset and gain correction value is subtracted from the converted data before writing the Result register (RESULT). Table 42-23. Offset and Gain correction feature Gain Factor Offset Error (mV) Conditions 0.5x 1x In differential mode, 1x gain, VDDANA=3.0V, VREF=1.0V, 350kSps at 25C 2x 8x 16x Gain Error (mV) Total Unadjusted Error (LSB) 0.25 1.0 2.4 0.20 0.10 1.5 0.15 -0.15 2.7 -0.05 0.05 3.2 0.10 -0.05 6.1 42.9.4.3 Inputs and Sample and Hold Acquisition Times The analog voltage source must be able to charge the sample and hold (S/H) capacitor in the ADC in order to achieve maximum accuracy. Seen externally the ADC input consists of a resistor ( R SAMPLE ) and a capacitor ( C SAMPLE ). In addition, the source resistance ( R SOURCE ) must be taken into account when calculating the required sample and hold time. Figure 42-5 shows the ADC input channel equivalent circuit. Figure 42-5. ADC Input VDDANA/2 Analog Input AINx RSOURCE CSAMPLE RSAMPLE VIN To achieve n bits of accuracy, the C SAMPLE capacitor must be charged at least to a voltage of V CSAMPLE V IN x ( 1 - 2 -( n + 1 ) ) Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1075 The minimum sampling time t SAMPLEHOLD for a given R SOURCE can be found using this formula: t SAMPLEHOLD ( R SAMPLE + R SOURCE ) x ( C SAMPLE ) x ( n + 1 ) x ln ( 2 ) for a 12 bits accuracy: t SAMPLEHOLD ( R SAMPLE + R SOURCE ) x ( C SAMPLE ) x 9.02 where 1 t SAMPLEHOLD = --------------------2 x f ADC Table 42-24. Clock and Timing(1) Symbol Parameter Conversion rate Startup time I Note: 1. Conditions Min. Typ. Max. Units Cload=100pF Normal mode - - 350 Rload > 5k For DATA=+/-1 - - 1000 VDDNA > 2.6V - - 2.85 s VDDNA < 2.6V - - 10 s ksps These values are based on simulation. These values are not covered by test limits in production or characterization. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1076 Table 42-25. Accuracy Characteristics(1) Symbol RES Parameter Input resolution Conditions Integral non-linearity VREF = VDDANA VREF= INT1V VREF= Ext 1.0V DNL Differential non-linearity VREF= VDDANA VREF= INT1V Note: Typ. Max. Units - - 10 Bits VDD = 1.6V 0.75 1.1 2.5 VDD = 3.6V 0.6 1.2 1.5 VDD = 1.6V 1.4 2.2 2.5 VDD = 3.6V 0.9 1.4 1.5 VDD = 1.6V 0.75 1.3 1.5 VDD = 3.6V 0.8 1.2 1.5 VDD = 1.6V +/-0.9 +/-1.2 +/-1.5 VDD = 3.6V +/-0.9 +/-1.1 +/-1.2 VDD = 1.6V +/-1.1 +/-1.5 +/-1.7 VDD = 3.6V +/-1.0 +/-1.1 +/-1.2 VDD = 1.6V +/-1.1 +/-1.4 +/-1.5 VDD = 3.6V +/-1.0 +/-1.5 +/-1.6 I VREF= Ext 1.0V INL Min. LSB LSB I Gain error Ext. VREF +/-1.5 +/-5 +/-10 mV I Offset error Ext. VREF +/-2 +/-3 +/-6 mV 1. All values measured using a conversion rate of 350ksps. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1077 42.9.5 Analog Comparator Characteristics Table 42-26. Electrical and Timing Symbol Parameter Conditions I Positive input voltage range I I Negative input voltage range I I Offset Notes: 1. Max. 0 - VDDANA Units V - VDDANA Hysteresis = 0, Fast mode -15 0.0 +15 mV Hysteresis = 0, Low power mode -25 0.0 +25 mV Hysteresis = 1, Fast mode 20 50 80 mV Hysteresis = 1, Low power mode 15 40 75 mV Changes for VACM=VDDANA/2 100mV overdrive, Fast mode - 60 116 ns Changes for VACM=VDDANA/2 100mV overdrive, Low power mode - 225 370 ns Enable to ready delay Fast mode - 1 2 s Enable to ready delay Low power mode - 12 19 s INL(3) -1.4 0.75 +1.4 LSB DNL(3) -0.9 0.25 +0.9 LSB Offset Error (1)(2) -0.200 0.260 +0.920 LSB Gain Error (1)(2) -0.89 0.215 0.89 LSB Min. Typ. Max. Units After calibration at T= 25C, over [-40, +85]C 1.08 1.1 1.12 V Over voltage at 25C 1.09 1.1 1.11 V Propagation delay VSCALE Typ. 0 Hysteresis tSTARTUP Min. Startup time According to the standard equation V(X)=VLSB*(X+1); VLSB=VDDANA/64 2. Data computed with the Best Fit method 3. Data computed using histogram 42.9.6 Internal 1.1V Bandgap Reference Characteristics Table 42-27. Bandgap and Internal 1.1V reference characteristics Symbol Parameter INT1V Internal 1.1V Bandgap reference Conditions Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1078 42.9.7 Temperature Sensor Characteristics 42.9.7.1 Temperature Sensor Characteristics Table 42-28. Temperature Sensor Characteristics(1) Symbol Parameter Temperature sensor output voltage I Conditions T= 25C, VDDANA = 3.3V Min. Typ. Max. Units - 0.667 - V 2.3 2.4 2.5 mV/C I Temperature sensor slope I Variation over VDDANA voltage VDDANA=1.8V to 3.6V -1.7 1 3.7 mV/V I Temperature Sensor accuracy Using the method described in the "Software-based Refinement of the Actual Temperature" on page 1079 -10 - 10 C Note: 1. These values are based on characterization. These values are not covered by test limits in production. 42.9.7.2 Software-based Refinement of the Actual Temperature The temperature sensor behavior is linear but it depends on several parameters such as the internal voltage reference which itself depends on the temperature. To take this into account, each device contains a Temperature Log row with data measured and written during the production tests. These calibration values should be read by software to infer the most accurate temperature readings possible. This Software Temperature Log row can be read at address 0x00806030 This section specifies the Temperature Log row content and explains how to refine the temperature sensor output using the values in the Temperature Log row. Temperature Log Row All values in this row were measured in the following conditions: z VDDIN = VDDIO = VDDANA = 3.3V z ADC Clock speed = 1MHz z ADC mode: Free running mode, ADC averaging mode with 4 averaged samples z ADC voltage reference = 1.0V internal reference (INT1V) z ADC input = temperature sensor Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1079 Table 42-29. Temperature Log Row Content Bit Position Name Description 7:0 ROOM_TEMP_VAL_INT Integer part of room temperature in C 11:8 ROOM_TEMP_VAL_DEC Decimal part of room temperature 19:12 HOT_TEMP_VAL_INT Integer part of hot temperature in C 23:20 HOT_TEMP_VAL_DEC Decimal part of hot temperature 31:24 ROOM_INT1V_VAL 39:32 HOT_INT1V_VAL 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) 51:40 ROOM_ADC_VAL 12bit ADC conversion at room temperature 63:52 HOT_ADC_VAL 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) 12bit ADC conversion at hot temperature The temperature sensor values are logged during test production flow for Room and Hot insertions: z ROOM_TEMP_VAL_INT and ROOM_TEMP_VAL_DEC contains the measured temperature at room insertion (e.g. for ROOM_TEMP_VAL_INT=25 and ROOM_TEMP_VAL_DEC=2, the measured temperature at room insertion is 25.2C). z HOT_TEMP_VAL_INT and HOT_TEMP_VAL_DEC contains the measured temperature at hot insertion (e.g. for HOT_TEMP_VAL_INT=83 and HOT_TEMP_VAL_DEC=3, the measured temperature at room insertion is 83.3C). The temperature log row also contains the corresponding 12bit ADC conversions of both Room and Hot temperatures: z ROOM_ADC_VAL contains the 12bit ADC value corresponding to (ROOM_TEMP_VAL_INT, ROOM_TEMP_VAL_DEC) z HOT_ADC_VAL contains the 12bit ADC value corresponding to (HOT_TEMP_VAL_INT, HOT_TEMP_VAL_DEC) The temperature log row also contains the corresponding 1V internal reference of both Room and Hot temperatures: z ROOM_INT1V_VAL is the 2's complement of the internal 1V reference value corresponding to (ROOM_TEMP_VAL_INT, ROOM_TEMP_VAL_DEC) z HOT_INT1V_VAL is the 2's complement of the internal 1V reference value corresponding to (HOT_TEMP_VAL_INT, HOT_TEMP_VAL_DEC) z ROOM_INT1V_VAL and HOT_INT1V_VAL values are centered around 1V with a 0.001V step. In other words, the range of values [0,127] corresponds to [1V, 0.873V] and the range of values [-1, -127] corresponds to [1.001V, 1.127V]. INT1V == 1 - (VAL/1000) is valid for both ranges. Using Linear Interpolation For concise equations, we'll use the following notations: z (ROOM_TEMP_VAL_INT, ROOM_TEMP_VAL_DEC) is denoted tempR z (HOT_TEMP_VAL_INT, HOT_TEMP_VAL_DEC) is denoted tempH z ROOM_ADC_VAL is denoted ADCR, its conversion to Volt is denoted VADCR z HOT_ADC_VAL is denoted ADCH, its conversion to Volt is denoted VADCH Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1080 z ROOM_INT1V_VAL is denoted INT1VR z HOT_INT1V_VAL is denoted INT1VH Using the (tempR, ADCR) and (tempH, ADCH) points, using a linear interpolation we have the following equation: V ADCH - V ADCR ADC - V ADCR V ------------------------------------ = --------------------------------------- temp - temp R temp H - temp R Given a temperature sensor ADC conversion value ADCm, we can infer a coarse value of the temperature tempC as: temp C INT1V 1 - - ADC R --------------------R- ( temp H - temp R ) ADC m -------------------12 12 (2 - 1) ( 2 - 1 ) = temp R + -----------------------------------------------------------------------------------------------------------------------------------------------------------INT1V H INT1V - - ADC R --------------------R- ADC H -------------------12 12 ( 2 - 1 ) ( 2 - 1 ) [Equation 1] Notes: 1. 2. In the previous expression, we've added the conversion of the ADC register value to be expressed in V. This is a coarse value because we assume INT1V=1V for this ADC conversion. Using the (tempR, INT1VR) and (tempH, INT1VH) points, using a linear interpolation we have the following equation: INT1V - INT1V R H - INT1V R ------------------------------------------ INT1V --------------------------------------------- temp - temp R = temp H - temp R Then using the coarse temperature value, we can infer a closer to reality INT1V value during the ADC conversion as: ( INT1V H - INT1V R ) ( temp C - temp R ) INT1V m = INT1V R + --------------------------------------------------------------------------------------------------- ( temp H - temp R ) Back to [Equation 1], we replace INT1V=1V by INT1V = INT1Vm, we can then deduce a finer temperature value as: INT1V m INT1V - - ADC R --------------------R- ( temp H temp R ) ADC m -------------------12 12 ( 2 - 1 ) ( 2 - 1 ) temp f = temp R + ---------------------------------------------------------------------------------------------------------------------------------------------------------INT1V H INT1V - - ADC R --------------------R- ADCH -------------------12 12 ( 2 - 1 ) ( 2 - 1 ) [Equation 1bis] Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1081 42.10 NVM Characteristics Table 42-30. Maximum Operating Frequency VDD range NVM Wait States 1.8V to 2.7V 2.7V to 3.6V Maximum Operating Frequency 0 14 1 28 2 42 3 48 0 24 1 48 Units MHz Note that on this flash technology, a max number of 8 consecutive write is allowed per row. Once this number is reached, a row erase is mandatory. Table 42-31. Flash Endurance and Data Retention Symbol Parameter Conditions Min. Typ. Max. Units RetNVM25k Retention after up to 25k Average ambient 55C 10 50 - Years RetNVM2.5k Retention after up to 2.5k Average ambient 55C 20 100 - Years RetNVM100 Retention after up to 100 Average ambient 55C 25 >100 - Years CycNVM Cycling Endurance(1) -40C < Ta < 85C 25k 150k - Cycles Min. Typ. Max. Units Note: 1. An endurance cycle is a write and an erase operation. Table 42-32. EEPROM Emulation(1) Endurance and Data Retention Symbol Parameter Conditions RetEEPROM100k Retention after up to 100k Average ambient 55C 10 50 - Years RetEEPROM10k Retention after up to 10k Average ambient 55C 20 100 - Years CycEEPROM Cycling Endurance(2) -40C < Ta < 85C 100k 600k - Cycles Notes: 1. 2. The EEPROM emulation is a software emulation described in the App note AT03265. An endurance cycle is a write and an erase operation. Table 42-33. NVM Characteristics Symbol Parameter Conditions Min. Typ. Max. Units tFPP Page programming time - - - 2.5 ms tFRE Row erase time I - - - 6 ms tFCE DSU chip erase time (CHIP_ERASE) - - - 240 ms Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1082 42.11 Oscillators Characteristics 42.11.1 Crystal Oscillator (XOSC) Characteristics 42.11.1.1 Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN. Table 42-34. Digital Clock Characteristics Symbol fCPXIN Parameter Conditions XIN clock frequency I Min. Typ. Max. Units - - 32 MHz 42.11.1.2 Crystal Oscillator Characteristics The following table describes the characteristics for the oscillator when a crystal is connected between XIN and XOUT as shown in Figure 42-6. The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in the table. The exact value of CL can be found in the crystal datasheet. The capacitance of the external capacitors (CLEXT) can then be computed as follows: C LEXT = 2 ( CL - C STRAY - C SHUNT ) where CSTRAY is the capacitance of the pins and PCB, CSHUNT is the shunt capacitance of the crystal. Table 42-35. Crystal Oscillator Characteristics Symbol fOUT ESR Parameter Crystal oscillator frequency Crystal Equivalent Series Resistance Safety Factor = 3 The AGC doesn't have any noticeable impact on these measurements. CXIN Parasitic capacitor load CXOUT Parasitic capacitor load Conditions Min. Typ. Max. Units 0.4 - 32 MHz f = 0.455MHz, CL = 100pF XOSC.GAIN = 0 - - 5.6K f = 2MHz, CL = 20pF XOSC.GAIN = 0 - - 416 f = 4MHz, CL = 20pF XOSC.GAIN = 1 - - 243 f = 8MHz, CL = 20pF XOSC.GAIN = 2 - - 138 f = 16MHz, CL = 20pF XOSC.GAIN = 3 - - 66 f = 32MHz, CL = 18pF XOSC.GAIN = 4 - - 56 I - 5.9 - pF - 3.2 - pF I Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1083 Table 42-35. Crystal Oscillator Characteristics (Continued) Symbol IXOSC tSTARTUP Parameter Conditions Current Consumption Startup time Min. Typ. Max. f = 2MHz, CL = 20pF, AGC off 27 65 85 f = 2MHz, CL = 20pF, AGC on 14 52 73 f = 4MHz, CL = 20pF, AGC off 61 117 150 f = 4MHz, CL = 20pF, AGC on 23 74 100 f = 8MHz, CL = 20pF, AGC off 131 226 296 f = 8MHz, CL = 20pF, AGC on 56 128 172 f = 16MHz, CL = 20pF, AGC off 305 502 687 f = 16MHz, CL = 20pF, AGC on 116 307 552 f = 32MHz, CL = 18pF, AGC off 1031 1622 2200 f = 32MHz, CL = 18pF, AGC on 278 615 1200 f = 2MHz, CL = 20pF, XOSC.GAIN = 0, ESR = 600 - 14K 48K f = 4MHz, CL = 20pF, XOSC.GAIN = 1, ESR = 100 - 6800 19.5K f = 8MHz, CL = 20pF, XOSC.GAIN = 2, ESR = 35 - 5550 13K f = 16MHz, CL = 20pF, XOSC.GAIN = 3, ESR = 25 - 6750 14.5K f = 32MHz, CL = 18pF, XOSC.GAIN = 4, ESR = 40 - 5.3K 9.6K Units A cycles Figure 42-6. Oscillator Connection Xin C LEXT Crystal LM C SHUNT RM C STRAY CM Xout C LEXT Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1084 42.11.2 External 32kHz Crystal Oscillator (XOSC32K) Characteristics 42.11.2.1 Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN32 pin. Table 42-36. Digital Clock Characteristics Symbol Parameter Conditions Min. Typ. Max. Units fCPXIN32 XIN32 clock frequency I - 32.768 - kHz I XIN32 clock duty cycle I - 50 - % 42.11.2.2 Crystal Oscillator Characteristics Figure 42-6 and the equation in "Crystal Oscillator Characteristics" on page 1083 also applies to the 32kHz oscillator connection. The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in the table. The exact value of CL can be found in the crystal datasheet. Table 42-37. 32kHz Crystal Oscillator Characteristics Symbol Parameter Conditions Min. Typ. Max. Units fOUT Crystal oscillator frequency I - 32768 - Hz tSTARTUP Startup time ESRXTAL = 39.9k, CL = 12.5pF - 28K 30K cycles CL Crystal load capacitance I - - 12.5 CSHUNT Crystal shunt capacitance I - 0.1 - CXIN32 Parasitic capacitor load - 3.1 - CXOUT32 Parasitic capacitor load - 3.3 - IXOSC32K Current consumption - 1.22 2.19 A ESR Crystal equivalent series resistance f=32.768kHz Safety Factor = 3 - - 141 k TQFP64/48/32 packages CL=12.5pF Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 pF 1085 Table 42-38. 32kHz Crystal Oscillator Characteristics Symbol Parameter Conditions Min. Typ. Max. Units fOUT Crystal oscillator frequency I - 32768 - Hz tSTARTUP Startup time ESRXTAL = 39.9k, CL = 12.5pF - 28K 30K cycles CL Crystal load capacitance I - - 12.5 CSHUNT Crystal shunt capacitance I - 0.1 - CXIN32 Parasitic capacitor load - 3.2 - CXOUT32 Parasitic capacitor load - 3.7 - IXOSC32K Current consumption - 1.22 2.19 A ESR Crystal equivalent series resistance f=32.768kHz Safety Factor = 3 - - 100 k Min. Typ. Max. Units 47 48 49 MHz - 403 453 A 7 8 9 s TQFP64/48/32 packages CL=12.5pF pF 42.11.3 Digital Frequency Locked Loop (DFLL48M) Characteristics Table 42-39. DFLL48M Characteristics - Open Loop Mode(1) Symbol Parameter Conditions DFLLVAL.COARSE = DFLL48M COARSE CAL I fOUT Output frequency DFLLVAL.FINE = 512 DFLLVAL.COARSE = DFLL48M COARSE CAL I IDFLL Power consumption on VDDIN DFLLVAL.FINE = 512 tSTARTUP Startup time DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 fOUT within 90% of final value Note: 1. DFLL48M in Open loop after calibration at room temperature. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1086 Table 42-40. DFLL48M Characteristics - Closed Loop Mode(1) Symbol Parameter Conditions Min. Typ. Max. Units 47 48 49 MHz 0.732 32.768 33 kHz fOUT Average Output frequency fREF = 32.768kHz fREF Reference frequency I Jitter Cycle to Cycle jitter fREF = 32.768kHz - - 0.42 ns IDFLL Power consumption on VDDIN fREF = 32 768kHz - 425 482 A 100 200 500 s fREF = 32.768kHz DFLLVAL.COARSE = DFLL48M COARSE CAL tLOCK DFLLVAL.FINE = 512 Lock time DFLLCTRL.BPLCKC = 1 DFLLCTRL.QLDIS = 0 DFLLCTRL.CCDIS = 1 DFLLMUL.FSTEP = 10 Note: 1. To insure that the device stays within the maximum allowed clock frequency, any reference clock for DFLL in close loop must be within a 2% error accuracy. 42.11.4 32.768kHz Internal oscillator (OSC32K) Characteristics Table 42-41. 32kHz RC Oscillator Characteristics Symbol fOUT Parameter Output frequency Conditions Min. Typ. Max. Calibrated against a 32.768kHz reference at 25C, over [-40, +85]C, over [1.8, 3.6]V 28.508 32.768 34.734 Calibrated against a 32.768kHz reference at 25C, at VDD=3.3V 32.276 32.768 33.260 Calibrated against a 32.768kHz reference at 25C, over [1.8, 3.6]V 31.457 32.768 34.079 Units kHz IOSC32K Current consumption I - 0.67 1.31 A tSTARTUP Startup time I - 1 2 cycle Duty Duty Cycle I - 50 - % Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1087 42.11.5 Ultra Low Power Internal 32kHz RC Oscillator (OSCULP32K) Characteristics Table 42-42. Ultra Low Power Internal 32kHz RC Oscillator Characteristics Symbol fOUT Parameter Output frequency Conditions Min. Typ. Max. Calibrated against a 32.768kHz reference at 25C, over [-40, +85]C, over [1.8, 3.6]V 25.559 32.768 38.011 Calibrated against a 32.768kHz reference at 25C, at VDD=3.3V 31.293 32.768 34.570 Calibrated against a 32.768kHz reference at 25C, over [1.8, 3.6]V 31.293 32.768 34.570 - - 125 nA IOSCULP32K (1)(2) Units kHz tSTARTUP Startup time I - 10 - cycles Duty Duty Cycle I - 50 - % Notes: 1. 2. These values are based on simulation. These values are not covered by test limits in production or characterization. This oscillator is always on. 42.11.6 8MHz RC Oscillator (OSC8M) Characteristics Table 42-43. Internal 8MHz RC Oscillator Characteristics Symbol Parameter Conditions Min. Typ. Max. Units Calibrated against a 8MHz reference at 25C, over [-40, +85]C, over [1.8, 3.6]V 7.8 8 8.16 Calibrated against a 8MHz reference at 25C, at VDD=3.3V 7.94 8 8.06 Calibrated against a 8MHz reference at 25C, over [1.8, 3.6]V 7.92 8 8.08 64 96 A I fOUT Output frequency MHz IOSC8M Current consumption IDLE2 on OSC32K versus IDLE2 on calibrated OSC8M enabled at 8MHz (FRANGE=1, PRESC=0) tSTARTUP Startup time I - 2.1 3 s Duty Duty cycle I - 50 - % I DLE Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1088 42.11.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics Table 42-44. FDPLL96M Characteristics(1) Symbol Parameter Conditions Min. Typ. Max. Units fIN Input frequency 32 - 2000 KHz fOUT Output frequency 48 - 96 MHz IFDPLL96M Current consumption fIN= 32 kHz, fOUT= 48 MHz 500 700 fIN= 32 kHz, fOUT= 96 MHz 900 1200 1.5 2.0 fIN= 32 kHz, fOUT= 96 MHz 3.0 10.0 fIN= 2 MHz, fOUT= 48 MHz 1.3 2.0 fIN= 2 MHz, fOUT= 96 MHz 3.0 7.0 After startup, time to get lock signal. 1.3 2 ms 25 50 s 40 50 60 % Min. Typ. Max. Units fIN= 32 kHz, fOUT= 48 MHz Jp Period jitter tLOCK Lock Time - % fIN= 32 kHz, fOUT= 96 MHz fIN= 2 MHz, fOUT= 96 MHz Duty A Duty cycle Table 42-45. FDPLL96M Characteristics(1) Symbol Parameter Conditions fIN Input frequency 32 - 2000 KHz fOUT Output frequency 48 - 96 MHz IFDPLL96M Current consumption fIN= 32 kHz, fOUT= 48 MHz 500 700 fIN= 32 kHz, fOUT= 96 MHz 900 1200 1.5 2.1 fIN= 32 kHz, fOUT= 96 MHz 4 10.0 fIN= 2 MHz, fOUT= 48 MHz 1.6 2.2 fIN= 2 MHz, fOUT= 96 MHz 4.6 10.2 After startup, time to get lock signal. 1.2 2 ms 25 50 s 50 60 % fIN= 32 kHz, fOUT= 48 MHz Jp Period jitter tLOCK Lock Time - Note: Duty cycle 1. % fIN= 32 kHz, fOUT= 96 MHz fIN= 2 MHz, fOUT= 96 MHz Duty A 40 All values have been characterized with FILTSEL[1/0] as default value. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1089 42.12 PTC Typical Characteristics Figure 42-7. Power Consumption [A] 1 sensor, noise countermeasures disabled, f=48MHz, Vcc=3.3V 140 120 100 80 Scan rate 10ms 60 Scan rate 50ms 40 Scan rate 100ms Scan rate 200ms 20 0 1 2 4 8 16 32 64 Sample averaging Figure 42-8. Power Consumption [A] 1 sensor, noise countermeasures Enabled, f=48MHz, Vcc=3.3V 200 180 160 140 120 Scan rate 10ms 100 80 Scan rate 50ms 60 Scan rate 100ms 40 Scan rate 200ms 20 0 1 2 4 8 16 32 64 Sample averaging Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1090 Figure 42-9. Power Consumption [A] 10 sensors, noise countermeasures disabled, f=48MHz, Vcc=3.3V 1200 1000 800 Scan rate 10ms 600 Scan rate 50ms Scan rate 100ms 400 Scan rate 200ms 200 Linear (Scan rate 50ms) 0 1 2 4 8 16 32 64 Sample averaging Figure 42-10.Power Consumption [A] 10 sensors, noise countermeasures Enabled, f=48MHz, Vcc=3.3V 900 800 700 600 500 Scan rate 10ms 400 Scan rate 50ms 300 Scan rate 100ms 200 Scan rate 200ms 100 0 1 2 4 8 16 32 64 Sample averaging Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1091 Figure 42-11.Power Consumption [A] 100 sensors, noise countermeasures disabled, f=48MHz, Vcc=3.3V 5000 4500 4000 3500 3000 Scan rate 10ms 2500 2000 Scan rate 50ms 1500 Scan rate 100ms 1000 Scan rate 200ms 500 0 1 2 4 8 16 32 64 Sample averaging Figure 42-12.Power Consumption [A] 100 sensors, noise countermeasures Enabled, f=48MHz, Vcc=3.3V 1800 1600 1400 1200 1000 Scan rate 10ms 800 Scan rate 50ms 600 Scan rate 100ms 400 Scan rate 200ms 200 0 1 2 4 8 16 32 64 Sample averaging Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1092 Figure 42-13.CPU Utilization 80 % 70 % 60 % 50 % Channel count 1 40 % Channel count 10 30 % Channel count 100 20 % 10 % 0% 10 50 100 200 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1093 42.13 USB Characteristics The USB on-chip buffers comply with the Universal Serial Bus (USB) v2.0 standard. All AC parameters related to these buffers can be found within the USB 2.0 electrical specifications. The USB interface is USB-IF certified: - TID 40001583 - Peripheral Silicon > Low/Full Speed > Silicon Building Blocks - TID 120000272 - Embedded Hosts > Full Speed Electrical configuration required to be USB compliance: - The CPU frequency must be higher 8MHz when USB is active (No constraint for USB suspend mode) - The operating voltages must be 3.3V (Min. 3.0V, Max. 3.6V). - The GCLK_USB frequency accuracy source must be less than: - In USB device mode, 48MHz +/-0.25% - In USB host mode, 48MHz +/-0.05% Table 42-46. GCLK_USB Clock Setup Recommendations Clock setup DFLL48M USB Device USB Host Open loop No No Closed loop, any internal OSC source No No Closed loop, any external XOSC source Yes No Yes(2) N/A Any internal OSC source (32K, 8M, ... ) No No Any external XOSC source (< 1MHz) Yes No Closed loop, USB SOF source (USB recovery mode)(1) FDPLL96M Any external XOSC source (> 1MHz) Notes: 1. Yes (3) Yes When using DFLL48M in USB recovery mode, the Fine Step value must be Ah to guarantee a USB clock at +/-0.25% before 11ms after a resume. 2. Very high signal quality and crystal less. It is the best setup for USB Device mode. 3. FDPLL lock time is short when the clock frequency source is high (> 1MHz). Thus, FDPLL and external OSC can be stopped during USB suspend mode to reduce consumption and guarantee a USB wakeup time (See TDRSMDN in USB specification). Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1094 42.14 Timing Characteristics 42.14.1 External Reset Table 42-47. External Reset Characteristics Symbol tEXT Parameter Condition Minimum reset pulse width I Min. Typ. Max. Units 10 - - ns 42.14.2 SERCOM in SPI Mode Timing Figure 42-14.SPI Timing Requirements in Master Mode SS tSCKR tMOS tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS MISO (Data Input) tMIH tSCK MSB LSB tMOH tMOH MOSI (Data Output) MSB LSB Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1095 Figure 42-15.SPI Timing Requirements in Slave Mode SS tSSS tSCKR tSCKF tSSH SCK (CPOL = 0) tSSCKW SCK (CPOL = 1) tSSCKW tSIS MOSI (Data Input) tSIH MSB tSOSSS MISO (Data Output) tSSCK LSB tSOS MSB tSOSSH LSB Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1096 Table 42-48. SPI Timing Characteristics and Requirements(1) Symbol Parameter Conditions tSCK SCK period Master tSCKW SCK high/low width Master - 0.5*tSCK - tSCKR SCK rise time(2) Master - - - tSCKF SCK fall time(2) Master - - - tMIS MISO setup to SCK Master - 21 - tMIH MISO hold after SCK Master - 13 - tMOS MOSI setup SCK Master - tSCK/2 - 3 - tMOH MOSI hold after SCK Master - 3 - tSSCK Slave SCK Period Slave 1*tCLK_APB - - tSSCKW SCK high/low width Slave 0.5*tSSCK - - tSSCKR SCK rise time(2) Slave - - - SCK fall time Slave - - - tSIS MOSI setup to SCK Slave tSSCK/2 - 9 - - tSIH MOSI hold after SCK Slave tSSCK/2 - 3 - - PRELOADEN=1 2*tCLK_APB + tSOS - - PRELOADEN=0 tSOS+7 - - (2) tSSCKF tSSS SS setup to SCK Slave Min. Typ. Max. 84 tSSH SS hold after SCK Slave tSIH - 4 - - tSOS MISO setup SCK Slave - tSSCK/2 - 18 - tSOH MISO hold after SCK Slave - 18 - tSOSS MISO setup after SS low Slave - 18 - tSOSH MISO hold after SS high Slave - 10 - Notes: 1. 2. Units ns These values are based on simulation. These values are not covered by test limits in production. See "I/O Pin Characteristics" on page 1067 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1097 42.14.3 SERCOM in I2C Mode Timing Table 42-49 describes the requirements for devices connected to the I2C Interface Bus. Timing symbols refer to Figure 42-16. Figure 42-16.I2C Interface Bus Timing tOF tHIGH tLOW tR tLOW SCL tSU;STA SDA tHD;STA tHD;DAT tSU;DAT tSU;STO tBUF Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1098 Table 42-49. I2C Interface Timing(1) Symbol Parameter Conditions Standard / Fast Mode Rise time for both SDA and SCL Output fall time from VIHmin to VILmax tOF Typ. Max. - 215 300 I Cb(2) = 400pF I Cb(2) = 550pF 60 100 High Speed Mode I Cb(2) = 100pF 20 40 Standard / Fast Mode 10pF < Cb(2) < 400pF 20.0 50.0 10pF < Cb(2) < 550pF 15.0 50.0 10pF < Cb(2) < 100pF 10.0 40.0 Fast tR Min. Mode + Fast Mode + High Speed Mode Hold time (repeated) START condition fSCL > 100kHz, Master tLOW-9 - - tLOW Low period of SCL Clock fSCL > 100kHz 113 - - tBUF Bus free time between a STOP and a START condition fSCL > 100kHz tLOW - - tSU;STA Setup time for a repeated START condition fSCL > 100kHz, Master tLOW+7 - - tHD;DAT Data hold time fSCL > 100kHz, Master 9 - 12 tSU;DAT Data setup time fSCL > 100kHz, Master 104 - - tSU;STO Setup time for STOP condition fSCL > 100kHz, Master tLOW+9 - - tSU;DAT;rx Data setup time (receive mode) fSCL > 100kHz, Slave 51 - 56 tHD;DAT;tx Data hold time (send mode) fSCL > 100kHz, Slave 71 90 138 tHD;STA Notes: 1. 2. Units ns These values are based on simulation. These values are not covered by test limits in production. Cb = Capacitive load on each bus line. Otherwise noted, value of Cb set to 20pF. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1099 42.14.4 SWD Timing Figure 42-17.SWD Interface Signals Read Cycle From debugger to SWDIO pin Stop Park Tri State Thigh Tos Data Data Parity Start Tlow From debugger to SWDCLK pin SWDIO pin to debugger Tri State Acknowledge Tri State Write Cycle From debugger to SWDIO pin Stop Park Tri State Tis Start Tih From debugger to SWDCLK pin SWDIO pin to debugger Tri State Acknowledge Data Data Parity Tri State Table 42-50. SWD Timings(1) Symbol Parameter Conditions Min. Max. Thigh SWDCLK High period 10 500000 Tlow SWDCLK Low period 10 500000 Tos SWDIO output skew to falling edge SWDCLK -5 5 Tis Input Setup time required between SWDIO Tih Input Hold time required between SWDIO and rising edge SWDCLK Note: 1. VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40pF Units ns 4 - 1 - These values are based on simulation. These values are not covered by test limits in production or characterization. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1100 42.15 AT86RF233 Electrical Characteristics 42.15.1 Digital Interface Timing Characteristics Test Conditions: TOP = +25C, VDD = 3.0V, CLoad = 50pF (unless otherwise stated). Symbol Parameter Condition fsync SCLK frequency fasync SCLK frequency t1 /SEL falling edge to MISO active t2 SCLK falling edge to MISO out t3 Min. Max. Unit Synchronous operation 8 MHz Asynchronous operation 7.5 MHz 180 ns 25 ns MOSI setup time 10 ns t4 MOSI hold time 10 ns t5 LSB last byte to MSB next byte SPI read/write, standard SRAM and frame access modes 250(1) ns t5a LSB last byte to MSB next byte Fast SRAM read/write access mode 500(1) ns t6 /SEL rising edge to MISO tri state t7 SLP_TR pulse width TX start trigger 62.5 SPI idle time: SEL rising to falling edge SPI read/write, standard SRAM and frame access modes Idle time between consecutive SPI accesses 250(1) ns t8a SPI idle time: SEL rising to falling edge Fast SRAM read/write access mode Idle time between consecutive SPI accesses 500((1) ns t9 Last SCLK rising edge to /SEL rising edge t10 Reset pulse width 10 clock cycles at 16MHz 625 ns t11 SPI access latency after reset 10 clock cycles at 16MHz 625 ns t12 Frame buffer empty indicator latency rising edge of last SCLK clock of the Frame Buffer read command byte to rising edge of IRQ tIRQ IRQ_2, IRQ_3, IRQ_4 latency Relative to the event to be indicated t8 Data hold time Typ. 10 ns Note(2) ns 250 ns 750 ns 9 s Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1101 Symbol Parameter fCLKM CLKM output clock frequency Notes: 1. 2. Condition Min. Typ. Max. Unit Configurable in register 0x03 CLKM_CTRL = 0 0 MHz CLKM_CTRL = 1 1 MHz CLKM_CTRL = 2 2 MHz CLKM_CTRL = 3 4 MHz CLKM_CTRL = 4 8 MHz CLKM_CTRL = 5 16 MHz CLKM_CTRL = 6 250 kHz CLKM_CTRL = 7 62.5 kHz For Fast SRAM read/write accesses on address space 0x82 - 0x94 the time t5(Min.) and t8(Min.) increases to 500ns. Maximum pulse width less than (TX frame length + 16s). 42.15.2 General RF Specifications Test Conditions (unless otherwise stated): vDD = 3.0V, tRF = 2445MHz, TOP = +25C, Measurement setup see Figure 34-1. Symbol Parameter fRF Frequency range fCH Channel spacing fHDR Condition Min. Typ. Max. Unit As specified in [1], [2] 2405 2445 2480 MHz 500kHz spacing 2360 2480 MHz As specified in [1], [2] 5 MHz 500kHz spacing 500 kHz Header bit rate (SHR, PHR) As specified in [1], [2] 250 kb/s fPSDU PSDU bit rate As specified in [1], [2] 250 kb/s fCHIP Chip rate As specified in [1], [2] 2000 kchip/ s fCLK Crystal oscillator frequency Reference oscillator 16 MHz fSRD PSDU bit rate Symbol rate deviation Reference frequency accuracy for correct functionality 250kb/s f20dB Note: -60(1) 20dB bandwidth 1. +60 2.8 ppm MHz A reference frequency accuracy of 40ppm is required by [1] [2]. 42.15.3 Transmitter Characteristics Test Conditions (unless otherwise stated): VDD = 3.0V, fRF = 2445MHz, TOP = +25C, Measurement setup see Figure 34-1. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1102 Symbol Parameter Condition PTX_MAX TX Output power Maximum configurable TX output power value Register bit TX_PWR = 0 +4 dBm PRANGE Output power range 16 steps, configurable in register 0x05 (PHY_TX_PWR) 21 dB PACC Output power tolerance 2 dB EVM Error vector magnitude 15 %rms PHARM Harmonics(2) Spurious Emissions(1) PSPUR_TX Notes: 1. Min. Typ. 2nd harmonic Max. -28 Unit dBm 3rd harmonic -45 dBm 30 - 1000MHz -36 dBm 1 - 12.75GHz -30 dBm 1.8 - 1.9GHz -47 dBm 5.15 - 5.3GHz -47 dBm Complies with EN 300 328/440, FCC-CFR-47 part 15, ARIB STD-66, RSS-210. 2. Measured single ended @ RFP/ RFN into 50; termination of the other pin with 50; constant wave signal. Compliance with EN 300 328/400, FCC-CFR-47 part 15, ARIB STD-66, RSS-210 might require an appropriate balun and/or harmonics filter. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1103 42.15.4 Receiver Characteristics Test Conditions (unless otherwise stated): VDD = 3.0V, fRF = 2445MHz, TOP = +25C, fPSDU = 250kb/s, Measurement setup see Figure 34-1. Symbol Parameter Condition PSENS Receiver sensitivity 250kb/s(1) NF Noise figure PRX_MAX Maximum RX input level PACRN Min. Typ. Max. -99 Unit dBm 6 dB 250kb/s(1) 8 dBm Adjacent channel rejection: -5MHz PRF= -82dBm(1) 32 dB PACRP Adjacent channel rejection: +5MHz PRF= -82dBm(1) 35 dB PAACRN Adjacent channel rejection: -10MHz PRF= -82dBm(1) 48 dB PAACRP Adjacent channel rejection: +10MHz PRF= -82dBm(1) 48 dB PAACR2N 2nd alternate channel rejection: -15MHz PRF= -82dBm(1) 54 dB PAACR2P 2nd alternate channel rejection: +15MHz PRF= -82dBm(1) 54 dB LO leakage(3) -57 dBm PSPUR_RX Spurious emissions 30 - 1000MHz -57 dBm 1 - 12.75GHz -47 dBm +300 kHz -300(2) fCAR_OFFS TX/RX carrier frequency offset Sensitivity loss 3dB IIP3 3rd- order intercept point At maximum gain Offset freq. interf. 1 = 5MHz Offset freq. interf. 2 = 10MHz -10 dBm IIP2 2nd- order intercept point At maximum gain Offset freq. interf. 1 = 60MHz Offset freq. interf. 2 = 62MHz 31 dBm RSSITOL RSSI tolerance Tolerance within gain step RSSIRANGE RSSI dynamic range 87 dB RSSIRES RSSI resolution 3 dB RSSIBASE_VAL RSSI sensitivity Defined as RSSI_BASE_VAL 5 -94 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 dB dBm 1104 Symbol Parameter Condition RSSIMIN Minimum RSSI value PRF RSSI_BASE_VAL 0 RSSIMAX Maximum RSSI value PRF RSSI_BASE_VAL + 84dB 28 Notes: 1. Min. Typ. Max. Unit AWGN channel, PER 1%, PSDU length 20 octets. 2. Offset equals 120ppm. 3. Measured single ended @ RFP/ RFN into 50; termination of the other pin with 50; constant wave signal. Compliance with EN 300 328/400, FCC-CFR-47 part 15, ARIB STD-66, RSS-210 might require an appropriate balun. 42.15.5 Current Consumption Specifications Test Conditions (unless otherwise stated): VDD = 3.0V, fRF = 2445MHz, TOP = +25C, Measurement setup see Figure 34-1. Symbol Parameter IBUSY_TX Supply current transmit state IRX_ON Supply current RX_ON state Condition Min. Typ. Max. Unit PTX= +4dBm 13.8 mA PTX= +0dBm 11.8 mA PTX= -17dBm 7.2 mA high sensitivity RX_PDT_LEVEL = [0x0] 11.8 mA 11.3 mA 5.2 mA 450 A with active RPC mode(2) may further reduce current consumptions receiver desensitize RX_PDT_LEVEL = [0x1,.., 0xE, 0xF](1) with active RPC mode(2) may further reduce current consumptions; using RX_PDT_LEVEL = [0x8, ..., 0xE, 0xF](1)reduces current consumption further by about 1mA IRX_ON_L0 Supply current RX_ON state with active receiver desensitize IPLL_ON Supply current PLL_ON state ITRX_OFF Supply current TRX_OFF state 300 A ISLEEP Supply current SLEEP state 0.2 A IDEEP_SLEEP Supply current DEEP_SLEEP state 0.02 A Notes: 1. with active RPC mode(2) Refer to "Receiver (RX)" on page 975. 2. Refer to "Reduced Power Consumption Mode (RPC)" on page 1034. 3. All power consumption measurements are performed with CLKM disabled. 4. The SAMD21 supply current has to be added to the AT86RF233 supply currents specified in the table above. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1105 42.15.6 XOSCRF Crystal Parameter Requirements Test Conditions: TOP = +25C, VDD = 3.0V (unless otherwise stated). Symbol Parameter f0 Crystal frequency CL Load capacitance C0 Crystal shunt capacitance ESR Equivalent series resistance Condition Min. Typ. Max, 16 8 Unit MHz 14 pF 7 pF 100 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1106 43. Packaging Information 43.1 Thermal Considerations 43.1.1 Thermal Resistance Data Table 43-1 summarizes the thermal resistance data depending on the package. Table 43-1. Thermal Resistance Data Package Type JA JC 32-pin QFN 37.2 C/W 3.1 C/W 48-pin QFN 33 C/W 11.4 C/W 43.1.2 Junction Temperature The average chip-junction temperature, TJ, in C can be obtained from the following: where: z JA = package thermal resistance, Junction-to-ambient (C/W), provided in Table 43-1. z JC = package thermal resistance, Junction-to-case thermal resistance (C/W), provided in Table 43-1. z HEATSINK = cooling device thermal resistance (C/W), provided in the device datasheet. z PD = device power consumption (W). z TA = ambient temperature (C). From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature TJ in C. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1107 43.2 Package Drawings 43.2.1 48-pin QFN Table 43-2. Device and Package Maximum Weight 100 mg Table 43-3. Package Characteristics Moisture Sensitivity Level MSL3 Table 43-4. Package Reference JEDEC Drawing Reference MO-220 JESD97 Classification E3 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1108 43.2.2 32-pin QFN (PG) GPC:ZKV Table 43-5. Device and Package Maximum Weight 90 mg Table 43-6. Package Characteristics Moisture Sensitivity Level MSL3 Table 43-7. Package Reference JEDEC Drawing Reference MO-220 JESD97 Classification E3 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1109 43.2.3 32-pin QFN (32M5) GPC: ZSA > w@J: @ >> ,@?J N = @ p J ? J & % ? l N = Y P = k ,@?J w@J: K = N p = ,J@$y %$J z = =>>$ ?@J$,@>$, +Q \ &^!& d ; @$ f g ={yJ ?@J$,@>$, =>$">j > |J?J= > +Jg=J ">j ={yJ >% }J@y} $? %J? %J$y}; ?@J$,@>$@$y $? >%Jj$=@$y =>$">j > ,J f %% ?@J$,@>$, jJ @$ @%%@JJj, g@Q %%>:%J Qjj ,}%% $> Jg=JJ? %J? $QJj, ,j :@} }J ~ $? =>$@$QJ =>Q$Jj=%>={:@,J > %J? ~ :}J$ w@J:J? "j> }J > k %J? :@?} @, J,QjJ? J:JJ$ $? "j> }J %J? @ z =>%$j@f %@J, > }J Jg>,J? ? , :J%% , }J %J?, @$ ~ @$?Jg Q, J @$?@=J? f %,Jj j{ p ,f>% $>J jJ" ? ,= ? k jJ" J ,= J k jJ" & ,= l p % Table 43-8. Device and Package Maximum Weight 78.5 mg Table 43-9. Package Characteristics Moisture Sensitivity Level MSL3 Table 43-10. Package Reference JEDEC Drawing Reference MO-220 JESD97 Classification E3 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1110 44. Soldering Profile The following table gives the recommended soldering profile from J-STD-20. Profile Feature Green Package Average Ramp-up Rate (217C to peak) 3C/s max Preheat Temperature 175C +/-25C 150-200C Time Maintained Above 217C Time within 5C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25C to Peak Temperature 60-150s 30s 260C 6C/s max 8 minutes max A maximum of three reflow passes is allowed per component. SVNREVISION Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1111 45. Schematic Checklist 45.1 Introduction This chapter describes a common checklist which should be used when starting and reviewing the schematics for a SAM R21 design. This chapter illustrates a recommended power supply connection, how to connect external analog references, programmer, debugger, oscillator and crystal. 45.1.1 Operation in Noisy Environment If the microcontroller is operating in an environment with much electromagnetic noise it must be protected from this noise to ensure reliable operation. In addition to following best practice EMC design guidelines, the recommendations listed in the schematic checklist sections must be followed. In particular placing decoupling capacitors very close to the power pins, a RC-filter on the RESET pin, and a pull-up resistor on the SWCLK pin is critical for reliable operations. It is also relevant to eliminate or attenuate noise in order to avoid that it reaches supply pins, I/O pins and crystals. 45.2 Power Supply The SAM R21 supports a single power supply from 1.8 to 3.6V. 45.2.1 Power Supply Connections Figure 45-1. Power Supply Schematic Close to device (for every pin) 1.8V - 3.6V VDDANA 100nF 10F GNDANA AVDD VDDIO 100nF VDDIN 100nF 10F VDDCORE 1F GND 100nF DVDD Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1112 Table 45-1. Power Supply Connections, VDDCORE From Internal Regulator Signal Name Recommended Pin Connection Description 1.8V to 3.6V Decoupling/filtering capacitors 100nF(1)(2) and 10F(1) VDDIO Decoupling/filtering inductor 10H Digital supply voltage (1)(3) 1.8V to 3.6V Decoupling/filtering capacitors 100nF(1)(2) and 10F(1) VDDANA Ferrite bead(4) prevents the VDD noise interfering the VDDANA GND Ground GNDANA Ground for the analog power domain Notes: 1. 2. 3. 4. 45.3 Analog supply voltage These values are only given as typical examples. Decoupling capacitor should be placed close to the device for each supply pin pair in the signal group, low ESR caps should be used for better decoupling. An inductor should be added between the external power and the VDD for power filtering. Ferrite bead has better filtering performance than the common inductor at high frequencies. It can be added between VDD and VDDANA for preventing digital noise from entering the analog power domain. The bead should provide enough impedance (e.g. 50 at 20MHz and 220 at 100MHz) for separating the digital power from the analog power domain. Make sure to select a ferrite bead designed for filtering applications with a low DC resistance to avoid a large voltage drop across the ferrite bead. External Analog Reference Connections The following schematic checklist is only necessary if the application is using external analog references. If the internal references are used instead, the following circuits in Figure 45-2 and Figure 45-2 are not necessary. Figure 45-2. External Analog Reference Schematic With One Reference Close to device (for every pin) VREFB EXTERNAL REFERENCE 4.7F 100nF GND Table 45-2. External Analog Reference Connections Signal Name Recommended Pin Connection Description VREFB 1.0V to VDDANA - 0.6V for ADC Decoupling/filtering capacitors 100nF(1)(2) and 4.7F(1) External reference from VREFB pin on the analog port GND Ground Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1113 Notes: 1. 2. These values are given as a typical example. Decoupling capacitor should be placed close to the device for each supply pin pair in the signal group. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1114 45.4 External Reset Circuit The external reset circuit is connected to the RESET pin when the external reset function is used. If the external reset function has been disabled, the circuit is not necessary. The reset switch can also be removed, if the manual reset is not necessary. The RESET pin itself has an internal pull-up resistor, hence it is optional to also add an external pull-up resistor. Figure 45-3. External Reset Circuit Example Schematic VDD 10k 330 RESET 100nF GND A pull-up resistor makes sure that the reset does not go low unintended causing a device reset. An additional resistor has been added in series with the switch to safely discharge the filtering capacitor, i.e. preventing a current surge when shorting the filtering capacitor which again causes a noise spike that can have a negative effect on the system. Table 45-3. Reset Circuit Connections Signal Name Recommended Pin Connection Description Reset low level threshold voltage VDDIO = 1.8V - 2.0V: Below 0.33 * VDDIO VDDIO = 2.7V - 3.6V: Below 0.36 * VDDIO RESET Decoupling/filter capacitor 100nF(1) Reset pin Pull-up resistor 10k(1)(2) Resistor in series with the switch 330(1) Notes: 1. 2. 45.5 These values are given as a typical example. The SAM R21 features an internal pull-up resistor on the RESET pin, hence an external pull-up is optional. Unused or Unconnected Pins For unused pins the default state of the pins for the will give the lowest current leakage. There is thus no need to do any configuration of the unused pins in order to lower the power consumption. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1115 45.6 Clocks and Crystal Oscillators The SAM R21 can be run from internal or external clock sources, or a mix of internal and external sources. An example of usage will be to use the internal 8MHz oscillator as source for the system clock, and an external 32.768kHz watch crystal as clock source for the Real-Time counter (RTC). 45.6.1 External Clock Source Figure 45-4. External Clock Source Example Schematic External Clock XIN XOUT/GPIO NC/GPIO Table 45-4. External Clock Source Connections Signal Name Recommended Pin Connection Description XIN XIN is used as input for an external clock signal Input for inverting oscillator pin XOUT/GPIO Can be left unconnected or used as normal GPIO 45.6.2 Crystal Oscillator Figure 45-5. Crystal Oscillator Example Schematic XIN 15pF XOUT 15pF The crystal should be located as close to the device as possible. Long signal lines may cause too high load to operate the crystal, and cause crosstalk to other parts of the system. Table 45-5. Crystal Oscillator Checklist Signal Name Recommended Pin Connection XIN Load capacitor 15pF(1)(2) XOUT Load capacitor 15pF(1)(2) Notes: 1. 2. Description External crystal between 0.4 to 30MHz These values are given only as typical example. Decoupling capacitor should be placed close to the device for each supply pin pair in the signal group. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1116 45.6.3 External Real Time Oscillator The low frequency crystal oscillator is optimized for use with a 32.768kHz watch crystal. When selecting crystals, load capacitance and crystal's Equivalent Series Resistance (ESR) must be taken into consideration. Both values are specified by the crystal vendor. The SAM R21 oscillator (not available in SAMR21E) is optimized for very low power consumption, hence close attention should be made when selecting crystals, see Table 45-6 for maximum ESR recommendations on 9pF and 12.5pF crystals. The Low-frequency Crystal Oscillator provides an internal load capacitance of typical values available in Table 42-37, "32kHz Crystal Oscillator Characteristics," on page 1085. This internal load capacitance and PCB capacitance can allow to use a Crystal inferior to 12.5pF load capacitance without external capacitors as shown in Figure 45-6. Table 45-6. Maximum ESR Recommendation for 32.768kHz Crystal Crystal CL (pF) Max ESR [k] 12.5 313 Note: Maximum ESR is typical value based on characterization. These values are not covered by test limits in production. Figure 45-6. External Real Time Oscillator without Load Capacitor XIN32 32.768kHz XOUT32 However, to improve Crystal accuracy and Safety Factor, it can be recommended by crystal datasheet to add external capacitors as shown in Figure 45-7. To find suitable load capacitance for a 32.768kHz crystal, consult the crystal datasheet. Figure 45-7. External Real Time Oscillator with Load Capacitor 22pF 32.768kHz XIN32 XOUT32 22pF Table 45-7. External Real Time Oscillator Checklist Signal Name Recommended Pin Connection Description XIN32 Load capacitor 22pF(1)(2) Timer oscillator input XOUT32 Load capacitor 22pF(1)(2) Timer oscillator output Notes: 1. 2. These values are given only as typical examples. Decoupling capacitor should be placed close to the device for each supply pin pair in the signal group. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1117 45.6.4 Calculating the Correct Crystal Decoupling Capacitor In order to calculate correct load capacitor for a given crystal one can use the model shown in Figure 45-8 which includes internal capacitors CLn, external parasitic capacitance CELn and external load capacitance CPn. Figure 45-8. Crystal Circuit With Internal, External and Parasitic Capacitance XIN CEL1 Internal CL2 XOUT CP1 CP2 External CL1 CEL2 Using this model the total capacitive load for the crystal can be calculated as shown in the equation below: ( C L1 + C P1 + C EL1 ) ( C L2 + C P2 + C EL2 ) C tot = -------------------------------------------------------------------------------------------------------C L1 + C P1 + C EL1 + C L2 + C P2 + C EL2 where Ctot is the total load capacitance seen by the crystal, this value should be equal to the load capacitance value found in the crystal manufacturer datasheet. The parasitic capacitance CELn can in most applications be disregarded as these are usually very small. If accounted for the value is dependent on the PCB material and PCB layout. For some crystal the internal capacitive load provided by the device itself can be enough. To calculate the total load capacitance in this case. CELn and CPn are both zero, CL1 = CL2 = CL, and the equation reduces to the following: CL C tot = ------2 For device equivalent internal pin capacitance, refer to "External 32kHz Crystal Oscillator (XOSC32K) Characteristics" on page 1085. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1118 45.7 Programming and Debug Ports For programming and/or debugging the SAM R21 the device should be connected using the Serial Wire Debug (SWD) interface. Currently, the SWD interface is supported by several Atmel and third party programmers and debuggers, such as the SAM-ICE, JTAGICE3 or SAM R21 Xplained Pro (SAM R21 evaluation kit) Embedded Debugger. Refer to the SAM-ICE, JTAGICE3 or SAM R21 Xplained Pro user guides for details on debugging and programming connections and options. For connecting to any other programming or debugging tool, refer to that specific programmer's or debugger's user guide. The SAM R21 Xplained Pro evaluation board for the SAM R21 supports programming and debugging through the onboard embedded debugger so no external programmer or debugger is needed. Note that a pull-up resistor on the SWCLK pin is critical for reliable operations. Refer to "Operation in Noisy Environment" on page 1112. Figure 45-9. SWCLK Circuit Connections VDD 1k SWCLK Table 45-8. SWCLK Circuit Connections Pin Name Description Recommended Pin Connection SWCLK Serial wire clock pin Pull-up resistor 1k 45.7.1 Cortex Debug Connector (10-pin) For debuggers and/or programmers that support the Cortex Debug Connector (10-pin) interface the signals should be connected as shown in Figure 45-10 with details described in Table 45-9. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1119 Figure 45-10.Cortex Debug Connector (10-pin) VDD Cortex Debug Connector (10-pin) VTref SWDIO 1 GND GND NC NC SWDCLK RESET NC NC RESET SWCLK SWDIO GND Table 45-9. Cortex Debug Connector (10-pin) Header Signal Name Description Recommended Pin Connection SWDCLK Serial wire clock pin Pull-up resistor 1k SWDIO Serial wire bidirectional data pin RESET Refer to "External Reset Circuit" on page 1115 RESET Target device reset pin, active low VTref Target voltage sense, should be connected to the device VDD GND Ground Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1120 45.7.2 10-pin JTAGICE3 Compatible Serial Wire Debug Interface The JTAGICE3 debugger and programmer does not support the Cortex Debug Connector (10-pin) directly, hence a special pinout is needed to directly connect the SAM R21 to the JTAGICE3, alternatively one can use the JTAGICE3 squid cable and manually match the signals between the JTAGICE3 and SAM R21. Figure 45-11 describes how to connect a 10-pin header that support connecting the JTAGICE3 directly to the SAM R21 without the need for a squid cable. To connect the JTAGICE3 programmer and debugger to the SAM R21, one can either use the JTAGICE3 squid cable, or use a 10-pin connector as shown in Figure 45-11 with details given in Table 45-10 to connect to the target using the JTAGICE3 50 mil cable directly. Figure 45-11.10-pin JTAGICE3 Compatible Serial Wire Debug Interface 10-pin JTAGICE3 Compatible VDD Serial Wire Debug Header SWDCLK 1 NC SWDIO GND VTG RESET RESET NC NC NC NC SWCLK SWDIO GND Table 45-10. 10-pin JTAGICE3 Compatible Serial Wire Debug Interface Header Signal Name Description SWDCLK Serial wire clock pin SWDIO Serial wire bidirectional data pin RESET Target device reset pin, active low VTG Target voltage sense, should be connected to the device VDD GND Ground Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1121 45.7.3 20-pin IDC JTAG Connector For debuggers and/or programmers that support the 20-pin IDC JTAG Connector, e.g. the SAM-ICE, the signals should be connected as shown in Figure 45-12 with details described in Table 45-11. Figure 45-12.20-pin IDC JTAG Connector VDD 20-pin IDC JTAG Connector VCC 1 NC NC GND NC GND SWDIO GND SWDCLK GND NC GND NC GND* nRESET GND* NC GND* NC GND* RESET SWCLK SWDIO GND Table 45-11. 20-pin IDC JTAG Connector Header Signal Name Description SWDCLK Serial wire clock pin SWDIO Serial wire bidirectional data pin nRESET Target device reset pin, active low VCC Target voltage sense, should be connected to the device VDD GND Ground GND* These pins are reserved for firmware extension purposes. They can be left open or connected to GND in normal debug environment. They are not essential for SWD in general. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1122 45.8 USB Interface The USB interface consists of a differential data pair (D+/D-) and a power supply (VBUS, GND). Refer to the "Electrical Characteristics" on page 1055 for operating voltages which will allow USB operation. Table 45-12. USB Interface Checklist Signal Name Recommended Pin Connection z D+ D- Description The impedance of the pair should be matched on the PCB to minimize reflections. z USB differential tracks should be routed with the same characteristics (length, width, number of vias, etc.) z Signals should be routed as parallel as possible, with a minimum number of angles and vias USB full speed / low speed positive data upstream pin USB full speed / low speed negative data upstream pin Figure 45-13.Low Cost USB Interface Example Schematic USB Connector VBUS D+ DGND VBUS USB Differential Data Line Pair USB_D+ USB_D- Shield GND (Board) It is recommended to increase ESD protection on the USB D+, D-, and VBUS lines using dedicated transient suppressors. These protections should be located as close as possible to the USB connector to reduce the potential discharge path and reduce discharge propagation within the entire system. The USB FS cable includes a dedicated shield wire that should be connected to the board with caution. Special attention should be paid to the connection between the board ground plane and the shield from the USB connector and the cable. Tying the shield directly to ground would create a direct path from the ground plane to the shield, turning the USB cable into an antenna. To limit the USB cable antenna effect, it is recommended to connect the shield and ground through an RC filter. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1123 Figure 45-14.Protected USB Interface Example Schematic VBUS USB Transient protection USB Connector USB Differential Data Line Pair VBUS D+ DGND RC Filter (GND/Shield Connection) USB_D- 4.5nF 1MO Shield USB_D+ GND (Board) Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1124 46. About This Document 46.1 Conventions 46.1.1 Numerical Notation Table 46-1. Numerical notation 165 Decimal number 0101b Binary number (example 0b0101 = 5 decimal) 0101 Binary numbers are given without suffix if unambiguous 0x3B24 Hexadecimal number X Represents an unknown or don't care value Z Represents a high-impedance (floating) state for either a signal or a bus 46.1.2 Memory Size and Type Table 46-2. Memory Size and Bit Rate Symbol Description kB/kbyte kilobyte (210 = 1024) MB/Mbyte megabyte (220 = 1024*1024) GB/Gbyte gigabyte (230 = 1024*1024*1024) b bit (binary 0 or 1) B byte (8 bits) 1kbit/s 1,000 bit/s rate (not 1,024 bit/s) 1Mbit/s 1,000,000 bit/s rate 1Gbit/s 1,000,000,000 bit/s rate 46.1.3 Frequency and Time Table 46-3. Frequency and Time Symbol Description kHz 1kHz = 103Hz = 1,000Hz MHz 106 = 1,000,000Hz GHz 109 = 1,000,000,000Hz s second ms millisecond s microsecond ns nanosecond Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1125 46.1.4 Registers and Bits Table 46-4. Register and bit mnemonics 46.2 R/W Read/Write accessible register bit. The user can read from and write to this bit. R Read-only accessible register bit. The user can only read this bit. Writes will be ignored. W Write-only accessible register bit. The user can only write this bit. Reading this bit will return an undefined value. BIT Bit names are shown in uppercase. (Example PINA1) BITS[n:m] A set of bits from bit n down to m. (Example: PINA3..0 = {PINA3, PINA2, PINA1, PINA0} Reserved Reserved bits are unused and reserved for future use. For compatibility with future devices, always write reserved bits to zero when the register is written. Reserved bits will always return zero when read. PERIPHERALi If several instances of a peripheral exist, the peripheral name is followed by a number to indicate the number of the instance in the range 0-n. PERIPHERALi denotes one specific instance. Reset Value of a register after a power reset. This is also the value of registers in a peripheral after performing a software reset of the peripheral, except for the Debug Control registers. SET/CLR Registers with SET/CLR suffix allows the user to clear and set bits in a register without doing a readmodify-write operation. These registers always come in pairs. Writing a one to a bit in the CLR register will clear the corresponding bit in both registers, while writing a one to a bit in the SET register will set the corresponding bit in both registers. Both registers will return the same value when read. If both registers are written simultaneously, the write to the CLR register will take precedence. Acronyms and Abbreviations Table 46-5 contains acronyms and abbreviations used in this document. Table 46-5. Acronyms and Abbreviations Abbreviation Description AACK Automatic Acknowledgement ACK Acknowledgement AC Analog Comparator AD Antenna Diversity ADC Analog-to-Digital Converter ADDR Address AES Advanced Encryption Standard AGC Automatic Gain Control AHB AMBA Advanced High-performance Bus APB AMBA Advanced Peripheral Bus AREF Analog reference voltage ARET Automatic Retransmission AVDD Analog supply voltage AVREG Analog Voltage Regulator Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1126 Table 46-5. Acronyms and Abbreviations (Continued) Abbreviation Description AWGN Additive White Gaussian Noise BATMON Battery Monitor BBP Base-Band Processor BLB Boot Lock Bit BOD Brown-out detector BPF Band-Pass Filter CBC Cipher Block Chaining CAL Calibration CC Compare/capture CCA Clear Channel Assessment CF Center Frequency CLK Clock CRC Cyclic Redundancy Check CS Carrier Sense CSMA-CA Carrier Sense Multiple Access - Collision Avoidance CW Continuous Wave CTRL Control DAC Digital to Analog converter DFLL Digital Frequency Locked Loop DSU Device service unit DVREG Digital Voltage Regulator ECB Electronic Code Book ED Energy Detect EEPROM Electrically Erasable Programmable Read-Only Memory EIC External interrupt controller ESD Electrostatic Discharge EVM Error Vector Magnitude EVSYS Event System FC Channel Center Frequency FCF Frame Control Field FCS Frame Check Sequence FIFO First In, First Out FTN Filter Tuning Network Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1127 Table 46-5. Acronyms and Abbreviations (Continued) Abbreviation Description GCLK Generic clock GND Ground GPIO General Purpose Input/Output I2C Inter-integrated circuit IEEE Institute of Electrical and Electronic Engineers IF Interrupt Flag INT Interrupt IOBUS I/O Bus IRQ Interrupt Request ISM Industrial Scientific Medical LDO Low Dropout LNA Low-Noise Amplifier LO Local Oscillator LPF Low-Pass Filter LQI Link Quality Indication LSB Least Significant Bit MAC Medium Access Control MFR MAC Footer MHR MAC Header MIC Message Integrity Code MISO Master Input, Slave Output MOSI Master Output, Slave Input MSB Most Significant Bit MSDU MAC Service Data Unit MPDU MAC Protocol Data Unit MSK Minimum Shift Key NMI Non-Maskable Interrupt NOP No Operation NVIC Nested vector interrupt controller NVMCTRL Non-Volatile Memory controller O-QPSK Offset Quadrature Phase Shift Keying OSC Oscillator PA Power Amplifier Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1128 Table 46-5. Acronyms and Abbreviations (Continued) Abbreviation Description PAC Peripheral access controller PAN Personal Area Network PC Program counter PCB Printed Circuit Board PER Period PHR PHY Header PHY Physical Layer PLL Phase-Locked Loop PM Power manager POR Power-on reset PPDU PHY Protocol Data Unit PPF Poly-Phase Filter PRBS Pseudo Random Binary Sequence PSD Power Spectrum Density PSDU PHY Service Data Unit PTC Peripheral touch controller PWM Pulse Width Modulation RAM Random-access memory REF Reference RF Radio Frequency RMW Read-modify-write RSSI Received Signal Strength Indicator RTC Real-time counter RX Receiver SERCOM Serial communication interface SFD Start-Of-Frame Delimiter SHR Synchronization Header SMBus System Management Bus SP Stack Pointer SPI Serial peripheral interface SRAM Static random-access memory SRD Short Range Device SSBF Single Side Band Filter Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1129 Table 46-5. Acronyms and Abbreviations (Continued) Abbreviation Description SYSCTRL System controller SWD Single-wire debug TC Timer/Counter TRX Transceiver TX Transmitter ULP Ultra Low Power USART Universal synchronous and asynchronous serial receiver and transmitter VDD Digital supply voltage VCO Voltage Controlled Oscillator VREF Voltage reference WDT Watchdog timer WPAN Wireless Personal Area Network XOSC Crystal oscillator XTAL Crystal Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1130 47. Errata 47.1 Revision A 47.1.1 Device 1 - CLKM is internally connected to GCLK/IO[5] on PC16. As this clock source cannot be used as GCLK_MAIN it is not possible to clock the CPU from the AT86RF233 CLKM clock output. Errata reference: 13152 Fix/Workaround: None 2 - In single shot mode and at 125C, the ADC conversions have linearity errors. Errata reference: 13277 Fix/Workaround: - Workaround 1: At 125C, do not use the ADC in single shot mode; use the ADC in free running mode only. - Workaround 2: At 125C, use the ADC in single shot mode only with VDDANA > 3V. 3 - TCC0/WO[6] on PA16 and TCC0/WO[7] on PA17 are not available. Errata reference: 11622 Fix/Workaround: None 4 - On pin PA24 and PA25 the pull-up and pull-down configuration is not disabled automatically when alternative pin function is enabled. Errata reference: 12368 Fix/Workaround: For pin PA24 and PA25, the GPIO pull-up and pull-down must be disabled before enabling alternative functions on them. 5 - If APB clock is stopped and GCLK clock is running, APB read access to read-synchronized registers will freeze the system. The CPU and the DAP AHB-AP are stalled, as a consequence debug operation is impossible. Errata reference: 10416 Fix/Workaround: Do not make read access to read-synchronized registers when APB clock is stopped and GCLK is running. To recover from this situation, power cycle the device or reset the device using the RESETN pin. 6 - In I2C Slave mode, writing the CTRLB register when in the AMATCH or DRDY interrupt service routines can cause the state machine to reset. Errata reference: 13574 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1131 Fix/Workaround: Write CTRLB.ACKACT to 0 using the following sequence: // If higher priority interrupts exist, then disable so that the // following two writes are atomic. SERCOM - STATUS.reg = 0; SERCOM - CTRLB.reg = 0; // Re-enable interrupts if applicable. Write CTRLB.ACKACT to 1 using the following sequence: // If higher priority interrupts exist, then disable so that the // following two writes are atomic. SERCOM - STATUS.reg = 0; SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT; // Re-enable interrupts if applicable. Otherwise, only write to CTRLB in the AMATCH or DRDY interrupts if it is to close out a transaction. When not closing a transaction, clear the AMATCH interrupt by writing a 1 to its bit position instead of using CTRLB.CMD. The DRDY interrupt is automatically cleared by reading/writing to the DATA register in smart mode. If not in smart mode, DRDY should be cleared by writing a 1 to its bit position. Code replacements examples: Current: SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; Change to: // If higher priority interrupts exist, then disable so that the // following two writes are atomic. SERCOM - STATUS.reg = 0; SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT; // Re-enable interrupts if applicable. Current: SERCOM - CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; Change to: // If higher priority interrupts exist, then disable so that the // following two writes are atomic. SERCOM - STATUS.reg = 0; SERCOM - CTRLB.reg = 0; // Re-enable interrupts if applicable. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1132 Current: /* ACK or NACK address */ SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3); Change to: // CMD=0x3 clears all interrupts, so to keep the result similar, // PREC is cleared if it was set. if (SERCOM - INTFLAG.bit.PREC) SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; 7 - PA24 and PA25 cannot be used as input when configured as GPIO with continuous sampling (cannot be read by PORT). Errata reference: 12005 Fix/Workaround: - Use PA24 and PA25 for peripherals or only as output pins. - Or configure PA31 to PA24 for on-demand sampling (CTRL[31:24] all zeroes) and access the IN register through the APB (not the IOBUS), to allow waiting for on-demand sampling. 8 - The SYSTICK calibration value is incorrect. Errata reference: 14154 Fix/Workaround: The correct SYSTICK calibration value is 0x40000000. This value should not be used to initialize the Systick RELOAD value register, which should be initialized instead with a value depending on the main clock frequency and on the tick period required by the application. For a detailed description of the SYSTICK module, refer to the official ARM Cortex-M0+ documentation. 9 - In Standby, Idle1 and Idle2 sleep modes the device might not wake up from sleep. An External Reset, Power on Reset or Watch Dog Reset will start the device again. Errata reference: 13140 Fix/Workaround: the SLEEPPRM bits in the NVMCTRL.CTRLB register must be written to 3 (NVMCTRL - CTRLB.bit.SLEEPPRM = 3) to ensure correct operation of the device. The average power consumption of the device will increase with 20uA compared to numbers in the electrical characteristics chapter. 10 - While the internal startup is not completed, PA07 pin is driven low by the chip. Then as all the other pins it is configured as an High Impedance pin. Errata reference: 12118 Fix/Workaround: None Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1133 11 - Digital pin outputs from Timer/Counters, AC (Analog Comparator), GCLK (Generic Clock Controller), and SERCOM (I2C and SPI) do not change value during standby sleep mode. Errata reference: 12537 Fix/Workaround: Set the voltage regulator in Normal mode before entering STANDBY sleep mode in order to keep digital pin output enabled. This is done by setting the RUNSTDBY bit in the VREG register. 12 - The voltage regulator in low power mode is not functional at temperatures above 85C. Errata reference: 12291 Fix/Workaround: Enable normal mode on the voltage regulator in standby sleep mode. Example code: // Set the voltage regulator in normal mode configuration in standby sleep mode SYSCTRL->VREG.bit.RUNSTDBY = 1; 13 - If the external XOSC32K is broken, neither the external pin RST nor the GCLK software reset can reset the GCLK generators using XOSC32K as source clock. Errata reference: 12164 Fix/Workaround: Do a power cycle to reset the GCLK generators after an external XOSC32K failure. 47.1.2 DSU 1 - If a debugger has issued a DSU Cold-Plugging procedure and then released the CPU from the resulting ""CPU Reset Extension"", the CPU will be held in ""CPU Reset Extension"" after any upcoming reset event. Errata reference: 12015 Fix/workaround: The CPU must be released from the ""CPU Reset Extension"" either by writing a one in the DSU STATUSA.CRSTEXT register or by applying an external reset with SWCLK high or by power cycling the device. 2 - The MBIST ""Pause-on-Error"" feature is not functional on this device. Errata reference: 14324 Fix/Workaround: Do not use the ""Pause-on-Error"" feature. 47.1.3 PM 1 - In debug mode, if a watchdog reset occurs, the debug session is lost. Errata reference: 12196 Fix/Workaround: A new debug session must be restart after a watchdog reset. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1134 47.1.4 XOSC32K 1 - The automatic amplitude control of the XOSC32K does not work. Errata reference: 10933 Fix/Workaround: Use the XOSC32K with Automatic Amplitude control disabled (XOSC32K.AAMPEN = 0) 47.1.5 DFLL48M 1 - The DFLL clock must be requested before being configured otherwise a write access to a DFLL register can freeze the device. Errata reference: 9905 Fix/Workaround: Write a zero to the DFLL ONDEMAND bit in the DFLLCTRL register before configuring the DFLL module. 2 - If the DFLL48M reaches the maximum or minimum COARSE or FINE calibration values during the locking sequence, an out of bounds interrupt will be generated. These interrupts will be generated even if the final calibration values at DFLL48M lock are not at maximum or minimum, and might therefore be false out of bounds interrupts. Errata reference: 10669 Fix/Workaround: Check that the lockbits: DFLLLCKC and DFLLLCKF in the SYSCTRL Interrupt Flag Status and Clear register (INTFLAG) are both set before enabling the DFLLOOB interrupt. 3 - The DFLL status bits in the PCLKSR register during the USB clock recovery mode can be wrong after a USB suspend state. Errata reference: 11938 Fix/Workaround: Do not monitor the DFLL status bits in the PCLKSR register during the USB clock recovery mode. 47.1.6 FDPLL 1 - The lock flag (DPLLSTATUS.LOCK) may clear randomly. When the lock flag randomly clears, DPLLLCKR and DPLLLCKF interrupts will also trigger, and the DPLL output is masked. Errata reference: 11791 Fix/Workaround: Set DPLLCTRLB.LBYPASS to 1 to disable masking of the DPLL output by the lock status. 2 - FDPLL lock time-out values are different from the parameters in the datasheet. Errata reference: 12145 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1135 Fix/Workaround: The time-out values are: - DPLLCTRLB.LTIME[2:0] = 4 : 10ms - DPLLCTRLB.LTIME[2:0] = 5 : 10ms - DPLLCTRLB.LTIME[2:0] = 6 : 11ms - DPLLCTRLB.LTIME[2:0] = 7 : 11ms 47.1.7 DMAC 1 - If data is written to CRCDATAIN in two consecutive instructions, the CRC computation may be incorrect. Errata reference: 13507 Fix/Workaround: Add a NOP instruction between each write to CRCDATAIN register. 47.1.8 NVMCTRL 1 - Default value of MANW in NVM.CTRLB is 0. Errata reference: 13134 This can lead to spurious writes to the NVM if a data write is done through a pointer with a wrong address corresponding to NVM area. Fix/Workaround: Set MANW in the NVM.CTRLB to 1 at startup 2 - When the part is secured and EEPROM emulation area configured to none, the CRC32 is not executed on the entire flash area but up to the onchip flash size minus half a row. Errata reference: 11988 Fix/Workaround: When using CRC32 on a protected device with EEPROM emulation area configured to none, compute the reference CRC32 value to the full chip flash size minus half row. 3 - When external reset is active it causes a high leakage current on VDDIO. Errata reference: 13446 Fix/Workaround: Minimize the time external reset is active. 47.1.9 SERCOM 1 - The I2C Slave SCL Low Extend Time-out (CTRLA.SEXTTOEN) and Master SCL Low Extend Time-out (CTRLA.MEXTTOEN) cannot be used if SCL Low Time-out (CTRLA.LOWTOUT) is disabled. When SCTRLA.LOWTOUT=0, the GCLK_SERCOM_SLOW is not requested. Errata reference: 12003 Fix/Workaround: Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1136 To use the Master or Slave SCL low extend time-outs, enable the SCL Low Timeout (CTRLA.LOWTOUT=1). 2 - In USART autobaud mode, missing stop bits are not recognized as inconsistent sync (ISF) or framing (FERR) errors. Errata reference: 13852 Fix/Workaround: None 3 - If the SERCOM is enabled in SPI mode with SSL detection enabled (CTRLB.SSDE) and CTRLB.RXEN=1, an erroneous slave select low interrupt (INTFLAG.SSL) can be generated. Errata reference: 13369 Fix/Workaround: Enable the SERCOM first with CTRLB.RXEN=0. In a subsequent write, set CTRLB.RXEN=1. 4 - In TWI master mode, an ongoing transaction should be stalled immediately when DBGCTRL.DBGSTOP is set and the CPU enters debug mode. Instead, it is stopped when the current byte transaction is completed and the corresponding interrupt is triggered if enabled. Errata reference: 12499 Fix/Workaround: In TWI master mode, keep DBGCTRL.DBGSTOP=0 when in debug mode. 47.1.10 USB 1 - The FLENC register negative sign management is not correct. Errata reference: 11472 Fix/Workaround: The following rule must be used for negative values: - FLENC 8h is equal to 0 decimal. - FLENC 9h to Fh are equal to -1 to -7 decimal instead of -7 to -1. 47.1.11 TC 1 - Spurious TC overflow and Match/Capture events may occur. Errata reference: 13268 Fix/Workaround: Do not use the TC overflow and Match/Capture events. Use the corresponding Interrupts instead. 47.1.12 TCC 1 - The TCC interrupts FAULT1, FAULT0, FAULTB, FAULTA, DFS, ERR,and CNT cannot wake up the chip from standby mode. Errata reference: 11951 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1137 Fix/Workaround: Do not use the TCC interrupts FAULT1, FAULT0, FAULTB, FAULTA, DFS, ERR, or CNT to wake up the chip from standby mode. 2 - If the OVF flag in the INTFLAG register is already set when enabling the DMA, this will trigger an immediate DMA transfer and overwrite the current buffered value in the TCC register. Errata reference: 12127 Fix/Workaround: None 3 - In RAMP 2 mode with Fault keep, qualified and restart: Errata reference: 13262 If a fault occurred at the end of the period during the qualified state, the switch to the next ramp can have two restarts. Fix/Workaround: Avoid faults few cycles before the end or the beginning of a ramp. 4 - With blanking enabled, a recoverable fault that occurs during the first increment of a rising TCC is not blanked. Errata reference: 12519 Fix/Workaround: None 5 - In Dual slope mode a Retrigger Event does not clear the TCC counter. Errata reference: 12354 Fix/Workaround: None 6 - In two ramp mode, two events will be generated per cycle, one on each ramp's end. EVCTRL.CNTSEL.END cannot be used to identify the end of a double ramp cycle. Errata reference: 12224 Fix/Workaround: None 7 - If an input event triggered STOP action is performed at the same time as the counter overflows, the first pulse width of the subsequent counter start can be altered with one prescaled clock cycle. Errata reference: 12107 Fix/Workaround: None 8 - When the RUNSTDBY bit is written after the TCC is enabled, the respective TCC APB bus is stalled and the RUNDSTBY bit in the TCC CTRLA register is not enabled-protected. Errata reference: 12477 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1138 Fix/Workaround: None. 9 - TCC fault filtering on inverted fault is not working. Errata reference: 12512 Fix/Workaround: Use only non-inverted faults. 10 - When waking up from the STANDBY power save mode, the SYNCBUSY.CTRLB and SYNCBUSY.STATUS bits may be locked to 1. Errata reference: 12227 Fix/Workaround: After waking up from STANDBY power save mode, perform a software reset of the TCC if you are using the SYNCBUSY.CTRLB and SYNCBUSY.STATUS bits 11 - When the Peripheral Access Controller (PAC) protection is enabled, writing to WAVE or WAVEB registers will not cause a hardware exception. Errata reference: 11468 Fix/Workaround: None 12 - If the MCx flag in the INTFLAG register is set when enabling the DMA, this will trigger an immediate DMA transfer and overwrite the current buffered value in the TCC register. Errata reference: 12155 Fix/Workaround: None 47.1.13 PTC 1 - WCOMP interrupt flag is not stable. The WCOMP interrupt flag will not always be set as described in the datasheet. Errata reference: 12860 Fix/Workaround: Do not use the WCOMP interrupt. Use the WCOMP event. 47.2 Revision B 47.2.1 Device 1 - In single shot mode and at 125C, the ADC conversions have linearity errors. Errata reference: 13277 Fix/Workaround: - Workaround 1: At 125C, do not use the ADC in single shot mode; use the ADC in free running mode only. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1139 - Workaround 2: At 125C, use the ADC in single shot mode only with VDDANA > 3V. 2 - On pin PA24 and PA25 the pull-up and pull-down configuration is not disabled automatically when alternative pin function is enabled. Errata reference: 12368 Fix/Workaround: For pin PA24 and PA25, the GPIO pull-up and pull-down must be disabled before enabling alternative functions on them. 3 - The PDM2 mode (i.e. when using two PDM microphones) does not work. Errata reference: 13410 Fix/Workaround: None. Only one PDM microphone can be connected. Thus, the I2S controller should be configured in normal Receive mode with one slot. 4 - The I2S is non-functional in the slave mode (i.e. when (FSSEL=1, SCKSEL=1). Errata reference: 13407 Fix/Workaround: None. FSSEL and SCKSEL must be 0. 5 - If APB clock is stopped and GCLK clock is running, APB read access to read-synchronized registers will freeze the system. The CPU and the DAP AHB-AP are stalled, as a consequence debug operation is impossible. Errata reference: 10416 Fix/Workaround: Do not make read access to read-synchronized registers when APB clock is stopped and GCLK is running. To recover from this situation, power cycle the device or reset the device using the RESETN pin. 6 - In I2C Slave mode, writing the CTRLB register when in the AMATCH or DRDY interrupt service routines can cause the state machine to reset. Errata reference: 13574 Fix/Workaround: Write CTRLB.ACKACT to 0 using the following sequence: // If higher priority interrupts exist, then disable so that the // following two writes are atomic. SERCOM - STATUS.reg = 0; SERCOM - CTRLB.reg = 0; // Re-enable interrupts if applicable. Write CTRLB.ACKACT to 1 using the following sequence: // If higher priority interrupts exist, then disable so that the Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1140 // following two writes are atomic. SERCOM - STATUS.reg = 0; SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT; // Re-enable interrupts if applicable. Otherwise, only write to CTRLB in the AMATCH or DRDY interrupts if it is to close out a transaction. When not closing a transaction, clear the AMATCH interrupt by writing a 1 to its bit position instead of using CTRLB.CMD. The DRDY interrupt is automatically cleared by reading/writing to the DATA register in smart mode. If not in smart mode, DRDY should be cleared by writing a 1 to its bit position. Code replacements examples: Current: SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; Change to: // If higher priority interrupts exist, then disable so that the // following two writes are atomic. SERCOM - STATUS.reg = 0; SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT; // Re-enable interrupts if applicable. Current: SERCOM - CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; Change to: // If higher priority interrupts exist, then disable so that the // following two writes are atomic. SERCOM - STATUS.reg = 0; SERCOM - CTRLB.reg = 0; // Re-enable interrupts if applicable. Current: /* ACK or NACK address */ SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3); Change to: // CMD=0x3 clears all interrupts, so to keep the result similar, // PREC is cleared if it was set. if (SERCOM - INTFLAG.bit.PREC) SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1141 7 - PA24 and PA25 cannot be used as input when configured as GPIO with continuous sampling (cannot be read by PORT). Errata reference: 12005 Fix/Workaround: - Use PA24 and PA25 for peripherals or only as output pins. - Or configure PA31 to PA24 for on-demand sampling (CTRL[31:24] all zeroes) and access the IN register through the APB (not the IOBUS), to allow waiting for on-demand sampling. 8 - Rx serializer in the RIGHT Data Slot Formatting Adjust mode (SERCTRL.SLOTADJ clear) does not work when the slot size is not 32 bits. Errata reference: 13411 Fix/Workaround: In SERCTRL.SERMODE RX, SERCTRL.SLOTADJ RIGHT must be used with CLKCTRL.SLOTSIZE 32. 9 - The SYSTICK calibration value is incorrect. Errata reference: 14154 Fix/Workaround: The correct SYSTICK calibration value is 0x40000000. This value should not be used to initialize the Systick RELOAD value register, which should be initialized instead with a value depending on the main clock frequency and on the tick period required by the application. For a detailed description of the SYSTICK module, refer to the official ARM Cortex-M0+ documentation. 10 - Depending CPU clock/ I2S clock ratio, the SYNCBUSY.CKEN0 flag occasionally stuck at 1 when starting a new audio stream with CTRLA.SWRST=1, then CTRLA.ENABLE=1, then CTRLA.CKEN0=1 Errata reference: 13408 Fix/Workaround: Disable the IP by writing 0 to CTRLA.ENABLE before resetting it (CTRLA.SWRST=1). 11 - In Standby, Idle1 and Idle2 sleep modes the device might not wake up from sleep. An External Reset, Power on Reset or Watch Dog Reset will start the device again. Errata reference: 13140 Fix/Workaround: the SLEEPPRM bits in the NVMCTRL.CTRLB register must be written to 3 (NVMCTRL - CTRLB.bit.SLEEPPRM = 3) to ensure correct operation of the device. The average power consumption of the device will increase with 20uA compared to numbers in the electrical characteristics chapter. 12 - While the internal startup is not completed, PA07 pin is driven low by the chip. Then as all the other pins it is configured as an High Impedance pin. Errata reference: 12118 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1142 Fix/Workaround: None 13 - Digital pin outputs from Timer/Counters, AC (Analog Comparator), GCLK (Generic Clock Controller), and SERCOM (I2C and SPI) do not change value during standby sleep mode. Errata reference: 12537 Fix/Workaround: Set the voltage regulator in Normal mode before entering STANDBY sleep mode in order to keep digital pin output enabled. This is done by setting the RUNSTDBY bit in the VREG register. 14 - The voltage regulator in low power mode is not functional at temperatures above 85C. Errata reference: 12291 Fix/Workaround: Enable normal mode on the voltage regulator in standby sleep mode. Example code: // Set the voltage regulator in normal mode configuration in standby sleep mode SYSCTRL->VREG.bit.RUNSTDBY = 1; 15 - If the external XOSC32K is broken, neither the external pin RST nor the GCLK software reset can reset the GCLK generators using XOSC32K as source clock. Errata reference: 12164 Fix/Workaround: Do a power cycle to reset the GCLK generators after an external XOSC32K failure. 47.2.2 DSU 1 - If a debugger has issued a DSU Cold-Plugging procedure and then released the CPU from the resulting ""CPU Reset Extension"", the CPU will be held in ""CPU Reset Extension"" after any upcoming reset event. Errata reference: 12015 Fix/workaround: The CPU must be released from the ""CPU Reset Extension"" either by writing a one in the DSU STATUSA.CRSTEXT register or by applying an external reset with SWCLK high or by power cycling the device. 2 - The MBIST ""Pause-on-Error"" feature is not functional on this device. Errata reference: 14324 Fix/Workaround: Do not use the ""Pause-on-Error"" feature. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1143 47.2.3 PM 1 - In debug mode, if a watchdog reset occurs, the debug session is lost. Errata reference: 12196 Fix/Workaround: A new debug session must be restart after a watchdog reset. 47.2.4 XOSC32K 1 - The automatic amplitude control of the XOSC32K does not work. Errata reference: 10933 Fix/Workaround: Use the XOSC32K with Automatic Amplitude control disabled (XOSC32K.AAMPEN = 0) 47.2.5 DFLL48M 1 - The DFLL clock must be requested before being configured otherwise a write access to a DFLL register can freeze the device. Errata reference: 9905 Fix/Workaround: Write a zero to the DFLL ONDEMAND bit in the DFLLCTRL register before configuring the DFLL module. 2 - If the DFLL48M reaches the maximum or minimum COARSE or FINE calibration values during the locking sequence, an out of bounds interrupt will be generated. These interrupts will be generated even if the final calibration values at DFLL48M lock are not at maximum or minimum, and might therefore be false out of bounds interrupts. Errata reference: 10669 Fix/Workaround: Check that the lockbits: DFLLLCKC and DFLLLCKF in the SYSCTRL Interrupt Flag Status and Clear register (INTFLAG) are both set before enabling the DFLLOOB interrupt. 3 - The DFLL status bits in the PCLKSR register during the USB clock recovery mode can be wrong after a USB suspend state. Errata reference: 11938 Fix/Workaround: Do not monitor the DFLL status bits in the PCLKSR register during the USB clock recovery mode. 47.2.6 DMAC 1 - If data is written to CRCDATAIN in two consecutive instructions, the CRC computation may be incorrect. Errata reference: 13507 Fix/Workaround: Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1144 Add a NOP instruction between each write to CRCDATAIN register. 47.2.7 NVMCTRL 1 - Default value of MANW in NVM.CTRLB is 0. Errata reference: 13134 This can lead to spurious writes to the NVM if a data write is done through a pointer with a wrong address corresponding to NVM area. Fix/Workaround: Set MANW in the NVM.CTRLB to 1 at startup 2 - When the part is secured and EEPROM emulation area configured to none, the CRC32 is not executed on the entire flash area but up to the onchip flash size minus half a row. Errata reference: 11988 Fix/Workaround: When using CRC32 on a protected device with EEPROM emulation area configured to none, compute the reference CRC32 value to the full chip flash size minus half row. 3 - When external reset is active it causes a high leakage current on VDDIO. Errata reference: 13446 Fix/Workaround: Minimize the time external reset is active. 47.2.8 SERCOM 1 - The I2C Slave SCL Low Extend Time-out (CTRLA.SEXTTOEN) and Master SCL Low Extend Time-out (CTRLA.MEXTTOEN) cannot be used if SCL Low Time-out (CTRLA.LOWTOUT) is disabled. When SCTRLA.LOWTOUT=0, the GCLK_SERCOM_SLOW is not requested. Errata reference: 12003 Fix/Workaround: To use the Master or Slave SCL low extend time-outs, enable the SCL Low Timeout (CTRLA.LOWTOUT=1). 2 - In USART autobaud mode, missing stop bits are not recognized as inconsistent sync (ISF) or framing (FERR) errors. Errata reference: 13852 Fix/Workaround: None 3 - If the SERCOM is enabled in SPI mode with SSL detection enabled (CTRLB.SSDE) and CTRLB.RXEN=1, an erroneous slave select low interrupt (INTFLAG.SSL) can be generated. Errata reference: 13369 Fix/Workaround: Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1145 Enable the SERCOM first with CTRLB.RXEN=0. In a subsequent write, set CTRLB.RXEN=1. 4 - In TWI master mode, an ongoing transaction should be stalled immediately when DBGCTRL.DBGSTOP is set and the CPU enters debug mode. Instead, it is stopped when the current byte transaction is completed and the corresponding interrupt is triggered if enabled. Errata reference: 12499 Fix/Workaround: In TWI master mode, keep DBGCTRL.DBGSTOP=0 when in debug mode. 47.2.9 TC 1 - Spurious TC overflow and Match/Capture events may occur. Errata reference: 13268 Fix/Workaround: Do not use the TC overflow and Match/Capture events. Use the corresponding Interrupts instead. 47.2.10 TCC 1 - In RAMP 2 mode with Fault keep, qualified and restart: Errata reference: 13262 If a fault occurred at the end of the period during the qualified state, the switch to the next ramp can have two restarts. Fix/Workaround: Avoid faults few cycles before the end or the beginning of a ramp. 2 - With blanking enabled, a recoverable fault that occurs during the first increment of a rising TCC is not blanked. Errata reference: 12519 Fix/Workaround: None 3 - In Dual slope mode a Retrigger Event does not clear the TCC counter. Errata reference: 12354 Fix/Workaround: None 4 - In two ramp mode, two events will be generated per cycle, one on each ramp's end. EVCTRL.CNTSEL.END cannot be used to identify the end of a double ramp cycle. Errata reference: 12224 Fix/Workaround: None Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1146 5 - If an input event triggered STOP action is performed at the same time as the counter overflows, the first pulse width of the subsequent counter start can be altered with one prescaled clock cycle. Errata reference: 12107 Fix/Workaround: None 6 - When the RUNSTDBY bit is written after the TCC is enabled, the respective TCC APB bus is stalled and the RUNDSTBY bit in the TCC CTRLA register is not enabled-protected. Errata reference: 12477 Fix/Workaround: None. 7 - TCC fault filtering on inverted fault is not working. Errata reference: 12512 Fix/Workaround: Use only non-inverted faults. 8 - When waking up from the STANDBY power save mode, the SYNCBUSY.CTRLB and SYNCBUSY.STATUS bits may be locked to 1. Errata reference: 12227 Fix/Workaround: After waking up from STANDBY power save mode, perform a software reset of the TCC if you are using the SYNCBUSY.CTRLB and SYNCBUSY.STATUS bits 9 - When the Peripheral Access Controller (PAC) protection is enabled, writing to WAVE or WAVEB registers will not cause a hardware exception. Errata reference: 11468 Fix/Workaround: None 10 - If the MCx flag in the INTFLAG register is set when enabling the DMA, this will trigger an immediate DMA transfer and overwrite the current buffered value in the TCC register. Errata reference: 12155 Fix/Workaround: None 47.2.11 PTC 1 - WCOMP interrupt flag is not stable. The WCOMP interrupt flag will not always be set as described in the datasheet. Errata reference: 12860 Fix/Workaround: Do not use the WCOMP interrupt. Use the WCOMP event. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1147 47.3 Revision C 47.3.1 Device 1 - In single shot mode and at 125C, the ADC conversions have linearity errors. Errata reference: 13277 Fix/Workaround: - Workaround 1: At 125C, do not use the ADC in single shot mode; use the ADC in free running mode only. - Workaround 2: At 125C, use the ADC in single shot mode only with VDDANA > 3V. 2 - In the table ""NVM User Row Mapping"", the WDT Window bitfield default value on silicon is not as specified in the datasheet. The datasheet defines the default value as 0x5, while it is 0xB on silicon. Errata reference: 13951 Fix/Workaround: None. 3 - On pin PA24 and PA25 the pull-up and pull-down configuration is not disabled automatically when alternative pin function is enabled. Errata reference: 12368 Fix/Workaround: For pin PA24 and PA25, the GPIO pull-up and pull-down must be disabled before enabling alternative functions on them. 4 - If APB clock is stopped and GCLK clock is running, APB read access to read-synchronized registers will freeze the system. The CPU and the DAP AHB-AP are stalled, as a consequence debug operation is impossible. Errata reference: 10416 Fix/Workaround: Do not make read access to read-synchronized registers when APB clock is stopped and GCLK is running. To recover from this situation, power cycle the device or reset the device using the RESETN pin. 5 - In I2C Slave mode, writing the CTRLB register when in the AMATCH or DRDY interrupt service routines can cause the state machine to reset. Errata reference: 13574 Fix/Workaround: Write CTRLB.ACKACT to 0 using the following sequence: // If higher priority interrupts exist, then disable so that the // following two writes are atomic. SERCOM - STATUS.reg = 0; SERCOM - CTRLB.reg = 0; Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1148 // Re-enable interrupts if applicable. Write CTRLB.ACKACT to 1 using the following sequence: // If higher priority interrupts exist, then disable so that the // following two writes are atomic. SERCOM - STATUS.reg = 0; SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT; // Re-enable interrupts if applicable. Otherwise, only write to CTRLB in the AMATCH or DRDY interrupts if it is to close out a transaction. When not closing a transaction, clear the AMATCH interrupt by writing a 1 to its bit position instead of using CTRLB.CMD. The DRDY interrupt is automatically cleared by reading/writing to the DATA register in smart mode. If not in smart mode, DRDY should be cleared by writing a 1 to its bit position. Code replacements examples: Current: SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; Change to: // If higher priority interrupts exist, then disable so that the // following two writes are atomic. SERCOM - STATUS.reg = 0; SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT; // Re-enable interrupts if applicable. Current: SERCOM - CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; Change to: // If higher priority interrupts exist, then disable so that the // following two writes are atomic. SERCOM - STATUS.reg = 0; SERCOM - CTRLB.reg = 0; // Re-enable interrupts if applicable. Current: /* ACK or NACK address */ SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3); Change to: // CMD=0x3 clears all interrupts, so to keep the result similar, Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1149 // PREC is cleared if it was set. if (SERCOM - INTFLAG.bit.PREC) SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; 6 - PA24 and PA25 cannot be used as input when configured as GPIO with continuous sampling (cannot be read by PORT). Errata reference: 12005 Fix/Workaround: - Use PA24 and PA25 for peripherals or only as output pins. - Or configure PA31 to PA24 for on-demand sampling (CTRL[31:24] all zeroes) and access the IN register through the APB (not the IOBUS), to allow waiting for on-demand sampling. 7 - Rx serializer in the RIGHT Data Slot Formatting Adjust mode (SERCTRL.SLOTADJ clear) does not work when the slot size is not 32 bits. Errata reference: 13411 Fix/Workaround: In SERCTRL.SERMODE RX, SERCTRL.SLOTADJ RIGHT must be used with CLKCTRL.SLOTSIZE 32. 8 - The SYSTICK calibration value is incorrect. Errata reference: 14154 Fix/Workaround: The correct SYSTICK calibration value is 0x40000000. This value should not be used to initialize the Systick RELOAD value register, which should be initialized instead with a value depending on the main clock frequency and on the tick period required by the application. For a detailed description of the SYSTICK module, refer to the official ARM Cortex-M0+ documentation. 9 - In Standby, Idle1 and Idle2 sleep modes the device might not wake up from sleep. An External Reset, Power on Reset or Watch Dog Reset will start the device again. Errata reference: 13140 Fix/Workaround: the SLEEPPRM bits in the NVMCTRL.CTRLB register must be written to 3 (NVMCTRL - CTRLB.bit.SLEEPPRM = 3) to ensure correct operation of the device. The average power consumption of the device will increase with 20uA compared to numbers in the electrical characteristics chapter. 10 - While the internal startup is not completed, PA07 pin is driven low by the chip. Then as all the other pins it is configured as an High Impedance pin. Errata reference: 12118 Fix/Workaround: None Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1150 11 - The voltage regulator in low power mode is not functional at temperatures above 85C. Errata reference: 12291 Fix/Workaround: Enable normal mode on the voltage regulator in standby sleep mode. Example code: // Set the voltage regulator in normal mode configuration in standby sleep mode SYSCTRL->VREG.bit.RUNSTDBY = 1; 12 - If the external XOSC32K is broken, neither the external pin RST nor the GCLK software reset can reset the GCLK generators using XOSC32K as source clock. Errata reference: 12164 Fix/Workaround: Do a power cycle to reset the GCLK generators after an external XOSC32K failure. 47.3.2 DSU 1 - If a debugger has issued a DSU Cold-Plugging procedure and then released the CPU from the resulting ""CPU Reset Extension"", the CPU will be held in ""CPU Reset Extension"" after any upcoming reset event. Errata reference: 12015 Fix/workaround: The CPU must be released from the ""CPU Reset Extension"" either by writing a one in the DSU STATUSA.CRSTEXT register or by applying an external reset with SWCLK high or by power cycling the device. 2 - The MBIST ""Pause-on-Error"" feature is not functional on this device. Errata reference: 14324 Fix/Workaround: Do not use the ""Pause-on-Error"" feature. 47.3.3 PM 1 - In debug mode, if a watchdog reset occurs, the debug session is lost. Errata reference: 12196 Fix/Workaround: A new debug session must be restart after a watchdog reset. 47.3.4 XOSC32K 1 - The automatic amplitude control of the XOSC32K does not work. Errata reference: 10933 Fix/Workaround: Use the XOSC32K with Automatic Amplitude control disabled (XOSC32K.AAMPEN = 0) Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1151 47.3.5 DFLL48M 1 - The DFLL clock must be requested before being configured otherwise a write access to a DFLL register can freeze the device. Errata reference: 9905 Fix/Workaround: Write a zero to the DFLL ONDEMAND bit in the DFLLCTRL register before configuring the DFLL module. 2 - If the DFLL48M reaches the maximum or minimum COARSE or FINE calibration values during the locking sequence, an out of bounds interrupt will be generated. These interrupts will be generated even if the final calibration values at DFLL48M lock are not at maximum or minimum, and might therefore be false out of bounds interrupts. Errata reference: 10669 Fix/Workaround: Check that the lockbits: DFLLLCKC and DFLLLCKF in the SYSCTRL Interrupt Flag Status and Clear register (INTFLAG) are both set before enabling the DFLLOOB interrupt. 3 - The DFLL status bits in the PCLKSR register during the USB clock recovery mode can be wrong after a USB suspend state. Errata reference: 11938 Fix/Workaround: Do not monitor the DFLL status bits in the PCLKSR register during the USB clock recovery mode. 47.3.6 DMAC 1 - If data is written to CRCDATAIN in two consecutive instructions, the CRC computation may be incorrect. Errata reference: 13507 Fix/Workaround: Add a NOP instruction between each write to CRCDATAIN register. 47.3.7 NVMCTRL 1 - Default value of MANW in NVM.CTRLB is 0. Errata reference: 13134 This can lead to spurious writes to the NVM if a data write is done through a pointer with a wrong address corresponding to NVM area. Fix/Workaround: Set MANW in the NVM.CTRLB to 1 at startup 2 - When the part is secured and EEPROM emulation area configured to none, the CRC32 is not executed on the entire flash area but up to the onchip flash size minus half a row. Errata reference: 11988 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1152 Fix/Workaround: When using CRC32 on a protected device with EEPROM emulation area configured to none, compute the reference CRC32 value to the full chip flash size minus half row. 3 - When external reset is active it causes a high leakage current on VDDIO. Errata reference: 13446 Fix/Workaround: Minimize the time external reset is active. 47.3.8 SERCOM 1 - The I2C Slave SCL Low Extend Time-out (CTRLA.SEXTTOEN) and Master SCL Low Extend Time-out (CTRLA.MEXTTOEN) cannot be used if SCL Low Time-out (CTRLA.LOWTOUT) is disabled. When SCTRLA.LOWTOUT=0, the GCLK_SERCOM_SLOW is not requested. Errata reference: 12003 Fix/Workaround: To use the Master or Slave SCL low extend time-outs, enable the SCL Low Timeout (CTRLA.LOWTOUT=1). 2 - In USART autobaud mode, missing stop bits are not recognized as inconsistent sync (ISF) or framing (FERR) errors. Errata reference: 13852 Fix/Workaround: None 3 - If the SERCOM is enabled in SPI mode with SSL detection enabled (CTRLB.SSDE) and CTRLB.RXEN=1, an erroneous slave select low interrupt (INTFLAG.SSL) can be generated. Errata reference: 13369 Fix/Workaround: Enable the SERCOM first with CTRLB.RXEN=0. In a subsequent write, set CTRLB.RXEN=1. 4 - In TWI master mode, an ongoing transaction should be stalled immediately when DBGCTRL.DBGSTOP is set and the CPU enters debug mode. Instead, it is stopped when the current byte transaction is completed and the corresponding interrupt is triggered if enabled. Errata reference: 12499 Fix/Workaround: In TWI master mode, keep DBGCTRL.DBGSTOP=0 when in debug mode. 47.3.9 TC 1 - Spurious TC overflow and Match/Capture events may occur. Errata reference: 13268 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1153 Fix/Workaround: Do not use the TC overflow and Match/Capture events. Use the corresponding Interrupts instead. 47.3.10 TCC 1 - In RAMP 2 mode with Fault keep, qualified and restart: Errata reference: 13262 If a fault occurred at the end of the period during the qualified state, the switch to the next ramp can have two restarts. Fix/Workaround: Avoid faults few cycles before the end or the beginning of a ramp. 2 - With blanking enabled, a recoverable fault that occurs during the first increment of a rising TCC is not blanked. Errata reference: 12519 Fix/Workaround: None 3 - In Dual slope mode a Retrigger Event does not clear the TCC counter. Errata reference: 12354 Fix/Workaround: None 4 - In two ramp mode, two events will be generated per cycle, one on each ramp's end. EVCTRL.CNTSEL.END cannot be used to identify the end of a double ramp cycle. Errata reference: 12224 Fix/Workaround: None 5 - If an input event triggered STOP action is performed at the same time as the counter overflows, the first pulse width of the subsequent counter start can be altered with one prescaled clock cycle. Errata reference: 12107 Fix/Workaround: None 6 - When the RUNSTDBY bit is written after the TCC is enabled, the respective TCC APB bus is stalled and the RUNDSTBY bit in the TCC CTRLA register is not enabled-protected. Errata reference: 12477 Fix/Workaround: None. 7 - TCC fault filtering on inverted fault is not working. Errata reference: 12512 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1154 Fix/Workaround: Use only non-inverted faults. 8 - When waking up from the STANDBY power save mode, the SYNCBUSY.CTRLB and SYNCBUSY.STATUS bits may be locked to 1. Errata reference: 12227 Fix/Workaround: After waking up from STANDBY power save mode, perform a software reset of the TCC if you are using the SYNCBUSY.CTRLB and SYNCBUSY.STATUS bits 9 - When the Peripheral Access Controller (PAC) protection is enabled, writing to WAVE or WAVEB registers will not cause a hardware exception. Errata reference: 11468 Fix/Workaround: None 10 - If the MCx flag in the INTFLAG register is set when enabling the DMA, this will trigger an immediate DMA transfer and overwrite the current buffered value in the TCC register. Errata reference: 12155 Fix/Workaround: None 47.3.11 PTC 1 - WCOMP interrupt flag is not stable. The WCOMP interrupt flag will not always be set as described in the datasheet. Errata reference: 12860 Fix/Workaround: Do not use the WCOMP interrupt. Use the WCOMP event. 47.4 Revision D 47.4.1 Device 1 - In single shot mode and at 125C, the ADC conversions have linearity errors. Errata reference: 13277 Fix/Workaround: - Workaround 1: At 125C, do not use the ADC in single shot mode; use the ADC in free running mode only. - Workaround 2: At 125C, use the ADC in single shot mode only with VDDANA > 3V. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1155 2 - In the table ""NVM User Row Mapping"", the WDT Window bitfield default value on silicon is not as specified in the datasheet. The datasheet defines the default value as 0x5, while it is 0xB on silicon. Errata reference: 13951 Fix/Workaround: None. 3 - On pin PA24 and PA25 the pull-up and pull-down configuration is not disabled automatically when alternative pin function is enabled. Errata reference: 12368 Fix/Workaround: For pin PA24 and PA25, the GPIO pull-up and pull-down must be disabled before enabling alternative functions on them. 4 - If APB clock is stopped and GCLK clock is running, APB read access to read-synchronized registers will freeze the system. The CPU and the DAP AHB-AP are stalled, as a consequence debug operation is impossible. Errata reference: 10416 Fix/Workaround: Do not make read access to read-synchronized registers when APB clock is stopped and GCLK is running. To recover from this situation, power cycle the device or reset the device using the RESETN pin. 5 - In I2C Slave mode, writing the CTRLB register when in the AMATCH or DRDY interrupt service routines can cause the state machine to reset. Errata reference: 13574 Fix/Workaround: Write CTRLB.ACKACT to 0 using the following sequence: // If higher priority interrupts exist, then disable so that the // following two writes are atomic. SERCOM - STATUS.reg = 0; SERCOM - CTRLB.reg = 0; // Re-enable interrupts if applicable. Write CTRLB.ACKACT to 1 using the following sequence: // If higher priority interrupts exist, then disable so that the // following two writes are atomic. SERCOM - STATUS.reg = 0; SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT; // Re-enable interrupts if applicable. Otherwise, only write to CTRLB in the AMATCH or DRDY interrupts if it is to close out a transaction. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1156 When not closing a transaction, clear the AMATCH interrupt by writing a 1 to its bit position instead of using CTRLB.CMD. The DRDY interrupt is automatically cleared by reading/writing to the DATA register in smart mode. If not in smart mode, DRDY should be cleared by writing a 1 to its bit position. Code replacements examples: Current: SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; Change to: // If higher priority interrupts exist, then disable so that the // following two writes are atomic. SERCOM - STATUS.reg = 0; SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT; // Re-enable interrupts if applicable. Current: SERCOM - CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; Change to: // If higher priority interrupts exist, then disable so that the // following two writes are atomic. SERCOM - STATUS.reg = 0; SERCOM - CTRLB.reg = 0; // Re-enable interrupts if applicable. Current: /* ACK or NACK address */ SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3); Change to: // CMD=0x3 clears all interrupts, so to keep the result similar, // PREC is cleared if it was set. if (SERCOM - INTFLAG.bit.PREC) SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; 6 - PA24 and PA25 cannot be used as input when configured as GPIO with continuous sampling (cannot be read by PORT). Errata reference: 12005 Fix/Workaround: - Use PA24 and PA25 for peripherals or only as output pins. - Or configure PA31 to PA24 for on-demand sampling (CTRL[31:24] all zeroes) and access the IN register through the APB (not the IOBUS), to allow waiting for on-demand sampling. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1157 7 - Rx serializer in the RIGHT Data Slot Formatting Adjust mode (SERCTRL.SLOTADJ clear) does not work when the slot size is not 32 bits. Errata reference: 13411 Fix/Workaround: In SERCTRL.SERMODE RX, SERCTRL.SLOTADJ RIGHT must be used with CLKCTRL.SLOTSIZE 32. 8 - The SYSTICK calibration value is incorrect. Errata reference: 14154 Fix/Workaround: The correct SYSTICK calibration value is 0x40000000. This value should not be used to initialize the Systick RELOAD value register, which should be initialized instead with a value depending on the main clock frequency and on the tick period required by the application. For a detailed description of the SYSTICK module, refer to the official ARM Cortex-M0+ documentation. 9 - While the internal startup is not completed, PA07 pin is driven low by the chip. Then as all the other pins it is configured as an High Impedance pin. Errata reference: 12118 Fix/Workaround: None 10 - If the external XOSC32K is broken, neither the external pin RST nor the GCLK software reset can reset the GCLK generators using XOSC32K as source clock. Errata reference: 12164 Fix/Workaround: Do a power cycle to reset the GCLK generators after an external XOSC32K failure. 11 - The voltage regulator in low power mode is not functional at temperatures above 85C. Errata reference: 12291 Fix/Workaround: Enable normal mode on the voltage regulator in standby sleep mode. Example code: // Set the voltage regulator in normal mode configuration in standby sleep mode SYSCTRL->VREG.bit.RUNSTDBY = 1; 47.4.2 DSU 1 - If a debugger has issued a DSU Cold-Plugging procedure and then released the CPU from the resulting ""CPU Reset Extension"", the CPU will be held in ""CPU Reset Extension"" after any upcoming reset event. Errata reference: 12015 Fix/workaround: The CPU must be released from the ""CPU Reset Extension"" either by writing a one in the DSU STATUSA.CRSTEXT register or by applying an external reset with SWCLK high or by power cycling the device. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1158 2 - The MBIST ""Pause-on-Error"" feature is not functional on this device. Errata reference: 14324 Fix/Workaround: Do not use the ""Pause-on-Error"" feature. 47.4.3 PM 1 - In debug mode, if a watchdog reset occurs, the debug session is lost. Errata reference: 12196 Fix/Workaround: A new debug session must be restart after a watchdog reset. 47.4.4 XOSC32K 1 - The automatic amplitude control of the XOSC32K does not work. Errata reference: 10933 Fix/Workaround: Use the XOSC32K with Automatic Amplitude control disabled (XOSC32K.AAMPEN = 0) 47.4.5 DFLL48M 1 - The DFLL clock must be requested before being configured otherwise a write access to a DFLL register can freeze the device. Errata reference: 9905 Fix/Workaround: Write a zero to the DFLL ONDEMAND bit in the DFLLCTRL register before configuring the DFLL module. 2 - If the DFLL48M reaches the maximum or minimum COARSE or FINE calibration values during the locking sequence, an out of bounds interrupt will be generated. These interrupts will be generated even if the final calibration values at DFLL48M lock are not at maximum or minimum, and might therefore be false out of bounds interrupts. Errata reference: 10669 Fix/Workaround: Check that the lockbits: DFLLLCKC and DFLLLCKF in the SYSCTRL Interrupt Flag Status and Clear register (INTFLAG) are both set before enabling the DFLLOOB interrupt. 3 - The DFLL status bits in the PCLKSR register during the USB clock recovery mode can be wrong after a USB suspend state. Errata reference: 11938 Fix/Workaround: Do not monitor the DFLL status bits in the PCLKSR register during the USB clock recovery mode. 47.4.6 DMAC 1 - If data is written to CRCDATAIN in two consecutive instructions, the CRC computation may be incorrect. Errata reference: 13507 Fix/Workaround: Add a NOP instruction between each write to CRCDATAIN register. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1159 47.4.7 NVMCTRL 1 - Default value of MANW in NVM.CTRLB is 0. Errata reference: 13134 This can lead to spurious writes to the NVM if a data write is done through a pointer with a wrong address corresponding to NVM area. Fix/Workaround: Set MANW in the NVM.CTRLB to 1 at startup 2 - When the part is secured and EEPROM emulation area configured to none, the CRC32 is not executed on the entire flash area but up to the on-chip flash size minus half a row. Errata reference: 11988 Fix/Workaround: When using CRC32 on a protected device with EEPROM emulation area configured to none, compute the reference CRC32 value to the full chip flash size minus half row. 3 - When external reset is active it causes a high leakage current on VDDIO. Errata reference: 13446 Fix/Workaround: Minimize the time external reset is active. 47.4.8 SERCOM 1 - The I2C Slave SCL Low Extend Time-out (CTRLA.SEXTTOEN) and Master SCL Low Extend Time-out (CTRLA.MEXTTOEN) cannot be used if SCL Low Time-out (CTRLA.LOWTOUT) is disabled. When SCTRLA.LOWTOUT=0, the GCLK_SERCOM_SLOW is not requested. Errata reference: 12003 Fix/Workaround: To use the Master or Slave SCL low extend time-outs, enable the SCL Low Time-out (CTRLA.LOWTOUT=1). 2 - In USART autobaud mode, missing stop bits are not recognized as inconsistent sync (ISF) or framing (FERR) errors. Errata reference: 13852 Fix/Workaround: None 3 - If the SERCOM is enabled in SPI mode with SSL detection enabled (CTRLB.SSDE) and CTRLB.RXEN=1, an erroneous slave select low interrupt (INTFLAG.SSL) can be generated. Errata reference: 13369 Fix/Workaround: Enable the SERCOM first with CTRLB.RXEN=0. In a subsequent write, set CTRLB.RXEN=1. 4 - In TWI master mode, an ongoing transaction should be stalled immediately when DBGCTRL.DBGSTOP is set and the CPU enters debug mode. Instead, it is stopped when the Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1160 current byte transaction is completed and the corresponding interrupt is triggered if enabled. Errata reference: 12499 Fix/Workaround: In TWI master mode, keep DBGCTRL.DBGSTOP=0 when in debug mode. 47.4.9 TC 1 - Spurious TC overflow and Match/Capture events may occur. Errata reference: 13268 Fix/Workaround: Do not use the TC overflow and Match/Capture events. Use the corresponding Interrupts instead. 47.4.10 TCC 1 - In RAMP 2 mode with Fault keep, qualified and restart: Errata reference: 13262 If a fault occurred at the end of the period during the qualified state, the switch to the next ramp can have two restarts. Fix/Workaround: Avoid faults few cycles before the end or the beginning of a ramp. 2 - With blanking enabled, a recoverable fault that occurs during the first increment of a rising TCC is not blanked. Errata reference: 12519 Fix/Workaround: None 3 - In Dual slope mode a Retrigger Event does not clear the TCC counter. Errata reference: 12354 Fix/Workaround: None 4 - In two ramp mode, two events will be generated per cycle, one on each ramp's end. EVCTRL.CNTSEL.END cannot be used to identify the end of a double ramp cycle. Errata reference: 12224 Fix/Workaround: None 5 - If an input event triggered STOP action is performed at the same time as the counter overflows, the first pulse width of the subsequent counter start can be altered with one prescaled clock cycle. Errata reference: 12107 Fix/Workaround: None Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1161 6 - When the RUNSTDBY bit is written after the TCC is enabled, the respective TCC APB bus is stalled and the RUNDSTBY bit in the TCC CTRLA register is not enabled-protected. Errata reference: 12477 Fix/Workaround: None. 7 - TCC fault filtering on inverted fault is not working. Errata reference: 12512 Fix/Workaround: Use only non-inverted faults. 8 - When waking up from the STANDBY power save mode, the SYNCBUSY.CTRLB and SYNCBUSY.STATUS bits may be locked to 1. Errata reference: 12227 Fix/Workaround: After waking up from STANDBY power save mode, perform a software reset of the TCC if you are using the SYNCBUSY.CTRLB and SYNCBUSY.STATUS bits 9 - When the Peripheral Access Controller (PAC) protection is enabled, writing to WAVE or WAVEB registers will not cause a hardware exception. Errata reference: 11468 Fix/Workaround: None 10 - If the MCx flag in the INTFLAG register is set when enabling the DMA, this will trigger an immediate DMA transfer and overwrite the current buffered value in the TCC register. Errata reference: 12155 Fix/Workaround: None 47.4.11 PTC 1 - WCOMP interrupt flag is not stable. The WCOMP interrupt flag will not always be set as described in the datasheet. Errata reference: 12860 Fix/Workaround: Do not use the WCOMP interrupt. Use the WCOMP event. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1162 48. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 48.1 Rev. G - 05/2016 General: Removed references to device variant B. Removed references to EEPROM Read While Write (RWW). "I/O Multiplexing and Considerations" on page 12: SWDIO added to the COM column in Table 5-1. "EVSYS - Event System" on page 400: CTRL.SWRST bit description updated. "TCC - Timer/Counter for Control Applications" on page 609: Table 28-1 on page 609: Number of waveform output (WO_NUM) for TCC0 updated from 8 to 6. Register Summary: INTENCLR, INTENSET and INTFLAG registers updated. "USB - Universal Serial Bus" on page 702: HSOFC.FLENCE bit description updated. "Schematic Checklist" on page 1112: "External Real Time Oscillator" on page 1117: Table listing equivalent internal pin capacitance removed and replaced with a reference to the electrical characteristics chapter. 48.2 Rev. F - 11/2015 Introduced 256KB+512KB Flash Offering: "Ordering Information" on page 6: Added ATSAMR21E19A-MF and -MFT. "Product Mapping" on page 23: Added SAM R21E19A to "Physical Memory Map" on page 24. "Block Diagrams" on page 8: Updated "SAM R21 Interconnection" on page 9. "DSU - Device Service Unit" on page 45: Added SAM R21E18A to Table 11-8. "Electrical Characteristics" on page 1055: Added STANDBY current consumption numbers for SAM R21E19A in "Power Consumption" on page 1060. "Packaging Information" on page 1107: Added "32-pin QFN (32M5)" on page 1110. "Electrical Characteristics at 125C" on page 1171: Added VDD minimum voltage for SAM R21E19 in "General Operating Ratings" on page 1171 and added section "Supply Characteristics" on page 1172. "AT86RF233 Extended Feature Set" on page 1005 Added "High Data Rate Modes" on page 1013 (Only applicable for T= -40C to 85C). "I/O Multiplexing and Considerations" on page 12: Added USB/SOF1kHz to PA23 in the COM column in Table 5-1. "SYSCTRL - System Controller" on page 143: Updated description in "Drift Compensation" on page 151. "NVMCTRL - Non-Volatile Memory Controller" on page 350 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1163 Updated Product Dependencies, Clocks section: Removed reference to the AUTOWS bit. "ADC - Analog-to-Digital Converter" on page 802: Table 30-14: ADC AIN9 pin removed. References to AREFB replaced with VREFB. INPUTCTRL Register: Updated Table 30-14. REFCTRL.REFSEL: Value 0x3 corrected to "Reserved" in Table 30-7. "RFCTRL - AT86RF233 Front-End Control Signal Interface" on page 876 Updated Product Dependencies section. "Electrical Characteristics" on page 1055 "Digital Frequency Locked Loop (DFLL48M) Characteristics" on page 1086: Removed note from Table 42-40. "Schematic Checklist" on page 1112: "Power Supply Connections" on page 1112: VDDCORE decoupling capacitor value updated from 100nF to 1F. References to AREFB replaced with VREFB. "Electrical Characteristics at 125C" on page 1171 "Digital Frequency Locked Loop (DFLL48M) Characteristics" on page 1187: Removed note from DFLL48M Characteristics - Closed Loop Mode table. "Power Consumption" on page 1174: Power consumption units updated. 48.3 Rev. E - 02/2015 "Description" on page 1 CoreMark score updated from 2.14 to 2.46 CoreMark/MHz. "Processor And Architecture" on page 28: "Configuration" on page 33: Removed green connection dots between DMAC Data and AHB-APB Bridge A and Bridge B. "AT86RF233 Microcontroller Interface" on page 883: Figure 35-1: EXTINT1 replaced by EXTINT0. "Schematic Checklist" on page 1112 Updated description in "Unused or Unconnected Pins" on page 1115. "References" on page 1170: Removed reference [7] AT86RF233 Software Programming Model. 48.4 Rev. D - 02/2015 "Description" on page 1 and "Features" on page 2: Updated 250kB/s to 250kb/s. "PORT" on page 373: Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1164 "I/O Pin Configuration" on page 378: Removed reference to "open-drain". Access for DRVSTR bit in Pin Configuration n register (PINCFGn.DRVCTR) updated from W to R/W. Errata: Updated errata for revision A, B, C, D: Added Errata Reference 13507. 48.5 Rev. C - 01/2015 "DSU - Device Service Unit" on page 45: Register Description: DID.DEVSEL, Table 11-8 Device Selection updated. "SYSCTRL - System Controller" on page 143: Removed references to XOSC32K and OSC32K 1kHz clock output option: - XOSC32K: "32kHz External Crystal Oscillator (XOSC32K) Operation" on page 148 - OSC32K: "32kHz Internal Oscillator (OSC32K) Operation" on page 149 1kHz Output Enable (EN1K) bit set as reserved bit: - Bit 4 in XOSC32K - Bit 3 in OSC32K "Electrical Characteristics" on page 1055: "Brown-Out Detectors Characteristics" on page 1070: Added Figure 42-3 and Figure 42-4 and updated conditions in Table 42-17 and Table 42-18. Errata: Updated errata for revision A: Added Errata Reference 10933, 12015, 12291, 12354, 12368, 12499, 13268, 13277, 13574. Updated errata for revision B: Added Errata Reference 10933, 12015, 12291, 12368, 12499, 13268, 13277, 13574. Updated errata for revision C: Added Errata Reference 12291, 13574, 13951. Added errata for revision D. "Electrical Characteristics at 125C" on page 1171: Electrical characteristics for 125C added. 48.6 Rev. B - 09/2014 "Block Diagrams" on page 8 NVM Controller bus connection changed from Master to Slave. "Clock System" on page 82 "Register Synchronization" on page 83 updated by splitting the section into "Common Synchronizer Register Synchronization" on page 83 and "Distributed Synchronizer Register Synchronization" on page 86. "Electrical Characteristics" on page 1055 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1165 "Analog-to-Digital (ADC) Characteristics" on page 1072: Added note defining gain accuracy parameter in: - ADC Differential Mode, Table 42-20 - ADC Single-Ended Mode, Table 42-21 Errata Updated errata for revision A and B: Added Errata Reference 13140, 12860. Added errata for revision C. 48.7 Rev. A - 07/2014 Initial revision Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1166 Appendix A. Continuous Transmission Test Mode A.1 Overview The AT86RF233 offers a Continuous Transmission Test Mode to support final application / production tests as well as certification tests. Using this test mode, the radio transceiver transmits continuously a previously transferred frame (PRBS mode) or a continuous wave signal (CW mode). In CW mode, two different signal frequencies per channel can be transmitted: z f1[MHz] = Fc[MHz] = 2405[MHz] + 5[MHz] x (k - 11), for k = 11, 12, ..., 26[MHz] + 0.5MHz z f2[MHz] = Fc[MHz] = 2405[MHz] + 5[MHz] x (k - 11), for k = 11, 12, ..., 26[MHz] - 0.5MHz Where Fc is the channel center frequency, refer to "RF Channel Selection" on page 994. Note: 1. In CW mode, it is not possible to transmit a RF signal directly on the channel center frequency. PSDU data in the Frame Buffer must contain at least a valid PHR (see "Introduction - IEEE 802.15.4-2006 Frame Format" on page 947). It is recommended to use a frame of maximum length (127 bytes) and arbitrary PSDU data for the PRBS mode. The SHR and the PHR are not transmitted. The transmission starts with the PSDU data and is repeated continuously. A.2 Configuration Before enabling Continuous Transmission Test Mode all register configurations should be done as follow: z TX channel setting (optional) z TX output power setting (optional) z Mode selection (PRBS / CW) A register access to register 0x36 and 0x1C enables the Continuous Transmission Test Mode. The transmission is started by enabling the PLL (TRX_CMD = PLL_ON) and writing the TX_START command to register 0x02. Even for CW signal transmission, it is required to write valid PSDU data to the Frame Buffer. For PRBS mode it is recommended to write a frame of maximum length. The detailed programming sequence is shown in Table 48-1. The column R/W informs about writing (W) or reading (R) a register or the Frame Buffer. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1167 Table 48-1. Continuous Transmission Programming Sequence. Step Action Register R/W Value Description 1 RESET 2 Register Access 0x0E W 0x01 Set IRQ mask register, enable IRQ_0 (PLL_LOCK) 3 Register Access 0x04 W 0x00 Disable TX_AUTO_CRC_ON 4 Register Access 0x02 W 0x03 Set radio transceiver state TRX_OFF 5 Register Access 0x03 W 0x01 Set clock at internal pad CLKM) 6 Register Access 0x08 W 0x33 Set IEEE 802.15.4 CHANNEL, for example channel 19 7 Register Access 0x05 W 0x00 Set TX output power, for example to PTX_MAX 8 Register Access 0x01 R 0x08 Verify TRX_OFF state 9 Register Access 0x36 W 0x0F Enable Continuous Transmission Test Mode - step # 1 10(1) Register Access 0x0C W 0x03 Enable raw data mode 11(1) Register Access 0x0A W 0x37 Enable raw data mode 12(2) Frame Buffer Write Access 13 Register Access 0x1C W 0x54 Enable Continuous Transmission Test Mode - step # 2 14 Register Access 0x1C W 0x46 Enable Continuous Transmission Test Mode - step # 3 15 Register Access 0x02 W 0x09 Enable PLL_ON state 16 Interrupt event 0x0F R 0x01 Wait for IRQ_0 (PLL_LOCK) 17 Register Access 0x02 W 0x02 18 Measurement 19 Register Access 20 RESET Reset AT86RF233 Write packet header containing the following number of bytes for with PSDU data (even for CW mode), refer to Table 48-2 W Initiate Transmission, enter BUSY_TX state Perform measurement 0x1C W 0x00 Disable Continuous Transmission Test Mode Reset AT86RF233 Notes: 1. Only required for CW mode, do not configure for PRBS mode. 2. Frame Buffer content varies for different modulation schemes. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1168 The content of the Frame Buffer has to be defined for Continuous Transmission PRBS mode or CW mode. To measure the power spectral density (PSD) mask of the transmitter it is recommended to use a random sequence of maximum length for the PSDU data. To measure CW signals it is necessary to write either 0x00 or 0xFF to the Frame Buffer, for details refer to Table 48-2. Table 48-2. Frame Buffer Content for various Continuous Transmission Modulation Schemes. Step 12 Action Frame Content Frame Buffer Access Note: 1. Comment Random Sequence Modulated RF signal Number of bytes and 0x00 (each byte of PSDU) Fc - 0.5MHz, CW signal Number of bytes and 0xFF (each byte of PSDU) Fc + 0.5MHz, CW signal It is recommended to use a frame of maximum length (127 bytes). A.3 Register Description A.3.1 TST_CTRL_DIGI The TST_CTRL_DIG register enables the continuous transmission test mode. Name: TST_CTRL_DIGI Offset: 0x36 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 TST_CTRL_DIG 0x36 Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 3:0 - TST_CTRL_DIG The register bits TST_CTRL_DIG with value 0xF enables continuous transmission. Table 48-3. TST_CTRL_DIG Value Description 0x0 No mode is active 0xF Continuous Transmission enabled All other values are reserved Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1169 Appendix B. References 1. IEEE Standard 802.15.4TM 2003: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (WPANs). 2. IEEE Standard 802.15.4TM 2006: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (WPANs). 3. IEEE Standard 802.15.4TM 2011: Low-Rate Wireless Personal Area Networks (WPANs). 4. ANSI/ESD STM5.1 - 2007, Electrostatic Discharge Sensitivity Testing - Human Body Model (HBM); JESD22A114E - 2006; CEI/IEC 60749-26 - 2006; AEC-Q100-002-Ref-D. 5. ESD-STM5.3.1-1999: ESD Association Standard Test Method for electrostatic discharge sensitivity testing Charged Device Model (CDM). 6. NIST FIPS PUB 197: Advanced Encryption Standard (AES), Federal Information Processing Standards Publication 197, US Department of Commerce/NIST, November 26, 2001. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1170 Appendix C. Electrical Characteristics at 125C C.1 Disclaimer All typical values are measured at T = 25C unless otherwise specified. All minimum and maximum values are valid across operating temperature and voltage unless otherwise specified. C.2 Absolute Maximum Ratings Stresses beyond those listed in Table C-1 may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table C-1. Symbol Absolute Maximum Ratings Parameter Condition Min. Max. Units VDD Power supply voltage 0 3.8 V IDD Current into a VDD pin - 28 mA IGND Current out of a GND pin - 39 mA VPIN Pin voltage with respect to GND and VDD GND-0.3V VDD+0.3V V VANA Voltage on RFP, RFN, AVDD and DVDD -0.3 2.0 V VESD ESD robustness PRF Input RF level Human Body Model (HBM) [4] 4 kV Charged Device Model (CDM) [5] 550 V +10 dBm 260 C 150 C T = 10s TLEAD Lead temperature Tstorgae Storage temperature Note: (soldering profile compliant with IPC/JEDEC J STD 020B) -60 1. Maximum source current is 14mA and maximum sink current is 19.5mA per cluster. A cluster is a group of GPIOs as shown in . Also note that each VDD/GND pair is connected to 2 clusters so current consumption through the pair will be a sum of the clusters source/sink currents. Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage. C.3 General Operating Ratings The device must operate within the ratings listed in Table C-2 in order for all other electrical characteristics and typical characteristics of the device to be valid. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1171 Table C-2. General Operating Conditions Symbol Parameter Condition Min. 1.8(1) VDD Power supply voltage Voltage on VDDIN, VDDIO and VDDANA(2) VDD1.8 Power supply voltage (on AVDD and DVDD) External supply voltage(3) VDDANA Analog supply voltage TA Temperature range TJ Junction temperature Notes: 1. Max. Units 3.3 3.6 V 1.7 1.8 1.9 V 1.8(1) 3.3 3.6 V -40 25 125 C - - 145 C 2.35(4) With BOD33 disabled. If the BOD33 is enabled, check Table 42-17. 2. Even if an implementation uses the external 1.8V voltage supply VDD1.8 it is required to connect VDD. 3. AT86RF233 register 0x10 (VREG_CTRL) needs to be programmed to disable internal voltage regulators and supply blocks by an external 1.8V supply, refer to "Voltage Regulators (AVREG, DVREG)" on page 983. Applicable for the SAM R21E19 due to the VDD minimum supply voltage of the Serial Flash. 4. C.4 Typ. Supply Characteristics The following characteristics are applicable to the operating temperature range: TA = -40C to 125C, unless otherwise specified and are valid for a junction temperature up to TJ = 100 C. Refer to "Power Supply and Start-Up Considerations" on page 20. Table 48-4. Supply Characteristics Voltage Symbol Conditions VDDIO VDDIN VDDANA Full Voltage Range Note: 1. Min. Max. Units 1.8 / 2.35(1) 3.6 V 2.35V is only applicable for the SAM R21E19 due to the VDD minimum supply voltage of the Serial Flash. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1172 C.5 Maximum Clock Frequencies Table C-3. Maximum GCLK Generator Output Frequencies Symbol Description Conditions Max. Units Undivided 96 MHz Divided 32 MHz Max. Units fGCLKGEN0 / fGCLK_MAIN fGCLKGEN1 fGCLKGEN2 fGCLKGEN3 fGCLKGEN4 fGCLKGEN5 GCLK Generator Output Frequency fGCLKGEN6 fGCLKGEN7 fGCLKGEN8 Table C-4. Maximum Peripheral Clock Frequencies Symbol Description fCPU CPU clock frequency 32 MHz fAHB AHB clock frequency 32 MHz fAPBA APBA clock frequency 32 MHz fAPBB APBB clock frequency 32 MHz fAPBC APBC clock frequency 32 MHz DFLL48M Reference clock frequency 33 KHz FDPLL96M Reference clock frequency 2 MHz FDPLL96M 32k Reference clock frequency 32 KHz fGCLK_WDT WDT input clock frequency 48 MHz fGCLK_RTC RTC input clock frequency 48 MHz fGCLK_EIC EIC input clock frequency 48 MHz fGCLK_USB USB input clock frequency 48 MHz fGCLK_EVSYS_CHANNEL_0 EVSYS channel 0 input clock frequency 48 MHz fGCLK_EVSYS_CHANNEL_1 EVSYS channel 1 input clock frequency 48 MHz fGCLK_EVSYS_CHANNEL_2 EVSYS channel 2 input clock frequency 48 MHz fGCLK_EVSYS_CHANNEL_3 EVSYS channel 3 input clock frequency 48 MHz fGCLK_EVSYS_CHANNEL_4 EVSYS channel 4 input clock frequency 48 MHz fGCLK_EVSYS_CHANNEL_5 EVSYS channel 5 input clock frequency 48 MHz fGCLK_EVSYS_CHANNEL_6 EVSYS channel 6 input clock frequency 48 MHz fGCLK_EVSYS_CHANNEL_7 EVSYS channel 7 input clock frequency 48 MHz fGCLK_EVSYS_CHANNEL_8 EVSYS channel 8 input clock frequency 48 MHz fGCLK_DFLL48M_REF fGCLK_DPLL fGCLK_DPLL_32K Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1173 Table C-4. Maximum Peripheral Clock Frequencies (Continued) Symbol Max. Units fGCLK_EVSYS_CHANNEL_9 EVSYS channel 9 input clock frequency 48 MHz fGCLK_EVSYS_CHANNEL_10 EVSYS channel 10 input clock frequency 48 MHz fGCLK_EVSYS_CHANNEL_11 EVSYS channel 11 input clock frequency 48 MHz fGCLK_SERCOMx_SLOW Common SERCOM slow input clock frequency 48 MHz fGCLK_SERCOM0_CORE SERCOM0 input clock frequency 48 MHz fGCLK_SERCOM1_CORE SERCOM1 input clock frequency 48 MHz fGCLK_SERCOM2_CORE SERCOM2 input clock frequency 48 MHz fGCLK_SERCOM3_CORE SERCOM3 input clock frequency 48 MHz fGCLK_SERCOM4_CORE SERCOM4 input clock frequency 48 MHz fGCLK_SERCOM5_CORE SERCOM5 input clock frequency 48 MHz fGCLK_TCC0, GCLK_TCC1 TCC0,TCC1 input clock frequency 80 MHz fGCLK_TCC2, GCLK_TC3 TCC2,TC3 input clock frequency 80 MHz fGCLK_TC4, GCLK_TC5 TC4,TC5 input clock frequency 48 MHz ADC input clock frequency 48 MHz fGCLK_AC_DIG AC digital input clock frequency 48 MHz fGCLK_AC_ANA AC analog input clock frequency 64 KHz PTC input clock frequency 48 MHz fGCLK_ADC fGCLK_PTC C.6 Description Power Consumption The values in Table C-5 are measured values of power consumption under the following conditions, except where noted: z Operating conditions z VVDDIN = 3.3V z Wake up time from sleep mode is measured from the edge of the wakeup signal to the execution of the first instruction fetched in flash. z Oscillators z z XOSC32K (32kHz crystal oscillator) stopped z XOSC (crystal oscillator) running with external 32MHz clock on XIN z DFLL48M stopped Clocks z XOSC used as main clock source, except otherwise specified z CPU, AHB clocks undivided z APBA clock divided by 4 z APBB and APBC bridges off z The following AHB module clocks are running: NVMCTRL, APBA bridge z The following peripheral clocks running: PM, SYSCTRL, RTC z z All other AHB clocks stopped All other peripheral clocks stopped Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1174 z I/Os are inactive with internal pull-up z CPU is running on flash with 1 wait states z Cache enabled z BOD33 disabled z AT86RF233 has to be set in Deep Sleep z Stacked serial Flash not included Table C-5. Mode Current Consumption Min. Typ. Max. CPU running a While(1) algorithm - 3.75 4.12 CPU running a While(1) algorithm VDDIN=1.8V, CPU is running on Flash with 3 wait states - 3.77 4.13 CPU running a While(1) algorithm, CPU is running on Flash with 3 wait states with GCLKIN as reference - 62*freq +422 62*freq +484 CPU running a Fibonacci algorithm - 4.85 5.29 CPU running a Fibonacci algorithm VDDIN=1.8V, CPU is running on flash with 3 - 4.87 5.29 - 88*freq +424 88*freq +486 - 6.70 7.30 - 5.98 6.41 - 108*freq +426 108*freq +492 IDLE0 - 2.40 2.69 IDLE1 - 1.79 2.05 IDLE2 - 1.50 1.76 XOSC32K running RTC running at 1kHz(1) - 350.0 852 XOSC32K and RTC stopped() - 348.0 850 ACTIVE Conditions TA Units mA A (with freq in MHz) mA wait states CPU running a Fibonacci algorithm, CPU is running on Flash with 3 wait states with GCLKIN as reference CPU running a CoreMark algorithm CPU running a CoreMark algorithm VDDIN=1.8V, CPU is running on flash with 3 125 C A (with freq in MHz) mA wait states CPU running a CoreMark algorithm, CPU is running on Flash with 3 wait states with GCLKIN as reference STANDBY Note: 1. A (with freq in MHz) mA A Measurements were done with SYSCTRL->VREG.bit.RUNSTDBY = 1 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1175 Table C-6. Wake-up Time Mode Conditions IDLE0 Min. Typ. Max. OSC8M used as main clock source, Cache disabled 3.9 4 4.1 OSC8M used as main clock source, Cache disabled 13.5 14.9 16.4 IDLE1 I IDLE2 I STANDBY I Figure C-1. TA OSC8M used as main clock source, Cache disabled 125 C OSC8M used as main clock source, Cache disabled Units s 14.4 15.8 17.2 19.2 20.6 22.1 Measurement Schematic VDDIN VDDANA VDDIO Amp 0 VDDCORE Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1176 C.7 Analog Characteristics C.7.1 Power-On Reset (POR) Characteristics VPOT+ VPOT- Figure C-2. Parameter Conditions Voltage threshold on VDD rising Voltage threshold on VDD falling I VDD falls at 1V/ms or slower Min. Typ. Max. Units 1.27 1.45 1.58 V 0.53 0.99 1.32 V POR Operating Principle VDD Symbol POR Characteristics VPOT+ VPOT- Time Reset Table C-7. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1177 C.7.2 Brown-Out Detectors Characteristics BOD33 Table C-8. BOD33 Characteristics Symbol Parameter Conditions Temp. Min. Typ. Max. Units - 34 - mV I Step size, between adjacent values in BOD33.LEVEL VHYST VBOD+ - VBOD- Hysteresis ON 35 - 170 mV Detection time Time with VDDANA < VTH necessary to generate a reset signal - 0.9(1) - s 25 C - 25 48 -40- to 125 C - - 50 25 C - 0.034 0.21 -40- to 125 C - - 2.92 0.132 0.38 tDET IIdleBOD33 Current consumption om Active/Idle mode ISbyBOD33 Current consumption in Standby mode tSTARTUP Startup time Note: C.7.3 1. Continuous mode Sampling mode 25 C Sampling mode -40- to 125 C 1.62 -40- to 125 C - 1.2(1) - A A s These values are based on simulation. These values are not covered by test limits in production or characterization. Analog-to-Digital (ADC) Characteristics Table C-9. Operating Conditions Symbol Parameter RES Resolution ADC Clock frequency fCLK_ADC Conditions (1) Sample rate Min. Typ. Max. Units I 8 - 12 bits I 30 - 2100 kHz Single shot (with VDDANA > 3.0V)(4) 5 - 300 ksps Free running 5 - 350 ksps 0.5 - - cycles - 6 - cycles 1.0 - VDDANA-0.6 V - 1.0 - V - VDDANA/1.48 - V -1.0 - +1.0 % (1) Sampling time Conversion time(1) VREF Voltage reference range VREFINT1V Internal 1V reference (2) 1x Gain (2) VREFINTVCC0 Internal ratiometric reference 0 VREFINTVCC0 Internal ratiometric reference 0(2) error Voltage Error 2.0V < VDDANA<3.63V Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1178 Table C-9. Operating Conditions (Continued) Symbol Parameter Conditions Min. Typ. Max. Units VREFINTVCC1 Internal ratiometric reference 1(2) VDDANA>2.0V - VDDANA/2 - V VREFINTVCC1 Internal ratiometric reference 1(2) error 2.0V < VDDANA<3.63V -1.0 - +1.0 % -VREF/GAIN - +VREF/GAIN V 0.0 - +VREF/GAIN V Voltage Error Conversion range(1) Differential mode Single-ended mode CSAMPLE Sampling capacitance(2) - 3.5 - pF RSAMPLE Input channel source resistance(2) - - 3.5 k - 1.25 1.85 mA DC supply current(1) IDD Notes: 1. 2. 3. 4. Table C-10. Symbol ENOB fCLK_ADC = 2.1MHzI(3) These values are based on characterization. These values are not covered by test limits in production. These values are based on simulation. These values are not covered by test limits in production or characterization. In this condition and for a sample rate of 350ksps, a conversion takes 6 clock cycles of the ADC clock (conditions: 1X gain, 12-bit resolution, differential mode, free-running). All single-shot measurements are performed with VDDANA > 3.0V (cf. ADC errata) Differential Mode Parameter Conditions Min. Typ. Max. Units - 10.5 10.9 bits Effective Number Of Bits With gain compensation TUE Total Unadjusted Error I 1x Gainn 1.5 4.3 17.0 LSB INLI Integral Non Linearity 1x Gainn 1.0 1.3 6.5 LSB DNL Differential Non Linearity 1x Gainn +/-0.3 +/-0.5 +/-0.95 LSB Ext. Ref 1x -15.0 2.5 +20.0 mV -20 -1.5 +20.0 mV Bandgap -15.0 -5.0 +15.0 mV Ext. Ref. 0.5x +/-0.1 +/-0.2 +/-0.45 % Ext. Ref. 2x to 16x +/-0.1 +/-0.2 +/-2.0 % Ext. Ref. 1x -10.0 -1.5 +10.0 mV VREF=VDDANA/1.48 -10.0 0.5 +15.0 mV Bandgap -10.0 3.0 +15.0 mV 64.2 70.0 78.9 dB I I I Gain Error Gain Accuracy(5) Offset Error VREF=VDDANA/1.48 SFDR Spurious Free Dynamic Range SINAD Signal-to-Noise and Distortion FCLK_ADC = 2.1MHz 61.4 65.0 66 dB Signal-to-Noise Ratio FIN = 40kHz 64.3 65.5 66.0 dB Total Harmonic Distortion AIN = 95%FSR -74.8 -64.0 -65.0 dB Noise RMS T=25 C 0.6 1.0 1.6 mV SNR THD 1x Gain Notes: 1. Maximum numbers are based on characterization and not tested in production, and valid for 5% to 95% of the input voltage range. 2. Dynamic parameter numbers are based on characterization and not tested in production. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1179 3. Respect the input common mode voltage through the following equations (where VCM_IN is the Input channel common mode voltage): c. d. If |VIN| > VREF/4 z VCM_IN < 0.95*VDDANA + VREF/4 - 0.75V z VCM_IN > VREF/4 -0.05*VDDANA -0.1V If |VIN| < VREF/4 z VCM_IN < 1.2*VDDANA - 0.75V z VCM_IN > 0.2*VDDANA - 0.1V 4. The ADC channels on pins PA08, PA09 are powered from the VDDIO power supply. The ADC performance of these pins will not be the same as all the other ADC channels on pins powered from the VDDANA power supply. 5. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x 100) / (2*Vref/GAIN) Table C-11. Symbol ENOB Single-Ended Mode Parameter Conditions Min. Typ. Max. Units Effective Number of Bits With gain compensation - 9.5 9.8 Bits TUE Total Unadjusted Error 1x gain - 10.5 40.0 LSB INL Integral Non-Linearity 1x gain 1.0 1.6 7.5 LSB DNL Differential Non-Linearity 1x gain +/-0.5 +/-0.6 +/-0.95 LSB Gain Error Ext. Ref. 1x -10.0 0.7 +10.0 mV Ext. Ref. 0.5x +/-0.1 +/-0.34 +/-0.4 % Ext. Ref. 2x to 16X +/-0.01 +/-0.1 +/-0.15 % -5.0 1.5 +10.0 mV 63.1 65.0 66.5 dB Gain Accuracy(4) Offset Error Ext. Ref. 1x SFDR Spurious Free Dynamic Range SINAD Signal-to-Noise and Distortion FCLK_ADC = 2.1MHz 50.7 59.5 61.0 dB Signal-to-Noise Ratio FIN = 40kHz 49.9 60.0 64.0 dB Total Harmonic Distortion AIN = 95%FSR -65.4 -63.0 -62.1 dB Noise RMS T = 25 C - 1.0 - mV SNR THD 1x Gain Notes: 1. Maximum numbers are based on characterization and not tested in production, and for 5% to 95% of the input voltage range. 2. Respect the input common mode voltage through the following equations (where VCM_IN is the Input channel common mode voltage) for all VIN: z VCM_IN < 0.7*VDDANA + VREF/4 - 0.75V z VCM_IN > VREF/4 - 0.3*VDDANA - 0.1V 3. The ADC channels on pins PA08, PA09 are powered from the VDDIO power supply. The ADC performance of these pins will not be the same as all the other ADC channels on pins powered from the VDDANA power supply. 4. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x 100) / (Vref/GAIN) Inputs and Sample and Hold Acquisition Times The analog voltage source must be able to charge the sample and hold (S/H) capacitor in the ADC in order to achieve maximum accuracy. Seen externally the ADC input consists of a resistor ( R SAMPLE ) and a capacitor ( C SAMPLE ). In addition, the source resistance ( R SOURCE ) must be taken into account when calculating the required sample and hold time. Figure C-3 shows the ADC input channel equivalent circuit. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1180 Figure C-3. ADC Input VDDANA/2 Analog Input AINx RSOURCE CSAMPLE RSAMPLE VIN To achieve n bits of accuracy, the C SAMPLE capacitor must be charged at least to a voltage of V CSAMPLE V IN x ( 1 - 2 -( n + 1 ) The minimum sampling time ) t SAMPLEHOLD for a given R SOURCE can be found using this formula: t SAMPLEHOLD ( R SAMPLE + R SOURCE ) x ( C SAMPLE ) x ( n + 1 ) x ln ( 2 ) for a 12 bits accuracy: t SAMPLEHOLD ( R SAMPLE + R SOURCE ) x ( C SAMPLE ) x 9.02 where 1 t SAMPLEHOLD = --------------------2 x f ADC Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1181 C.7.4 Analog Comparator Characteristics Table C-12. Symbol Electrical and Timing Parameter Conditions I Positive input voltage range I I Negative input voltage range I I Offset - VDDANA V Hysteresis = 0, Fast mode -15 0.0 +15 mV Hysteresis = 0, Low power mode -25 0.0 +25 mV Hysteresis = 1, Fast mode 20 50 83 mV Hysteresis = 1, Low power mode 15 40 75 mV Changes for VACM=VDDANA/2 100mV overdrive, Fast mode - 60 116 ns Changes for VACM=VDDANA/2 100mV overdrive, Low power mode - 225 370 ns Enable to ready delay Fast mode - 1 2 s Enable to ready delay Low power mode - 12 19 s - 0.75 1.58 LSB - 0.25 0.95 LSB Offset Error (1)(2) -0.200 0.260 +1.035 LSB Gain Error (1)(2) 0.55 1.2 2.0 LSB Min. Typ. Max. Units - 0.667 - V 2.2 2.4 2.7 mV/ C -9 1 14 mV/V -13.0 - 13.0 C INL(3) C.7.5 0 Units VDDANA Startup time DNL Notes: 1. Max. - Propagation delay VSCALE Typ. 0 Hysteresis tSTARTUP Min. (3) According to the standard equation V(X)=VLSB*(X+1); VLSB=VDDANA/64 2. Data computed with the Best Fit method 3. Data computed using histogram Temperature Sensor Characteristics Table C-13. Symbol Temperature Sensor Characteristics(1) Parameter Temperature sensor output voltage I Conditions T= 25 C, VDDANA = 3.3V I Temperature sensor slope I Variation over VDDANA voltage VDDANA=1.8V to 3.6V I Temperature sensor accuracy Using the method described in section 36.9.8.2 Note: 1. These values are based on characterization. These values are not covered by test limits in production. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1182 C.8 NVM Characteristics Table C-14. Maximum Operation Frequency VDD range NVM Wait States 1.8V to 2.7V 2.7V to 3.6V Maximum Operating Frequency 0 14 1 28 2 40 0 24 1 40 Units MHz Note that on this flash technology, a max number of 4 consecutive write is allowed per row. Once this number is reached, a row erase is mandatory. Table C-15. Flash Endurance and Data Retention Symbol Parameter Conditions Min. Typ. Max. Units RetNVM25k Retention after up to 25k Average ambient 55C 10 50 - Years RetNVM2.5k Retention after up to 2.5k Average ambient 55C 20 100 - Years RetNVM100 Retention after up to 100 Average ambient 55C 25 >100 - Years CycNVM Cycling Endurance(1) -40C < Ta < 125C 25k 150k - Cycles Min. Typ. Max. Units Note: 1. An endurance cycle is a write and an erase operation. EEPROM Emulation(1) Endurance and Data Retention Table C-16. Symbol Parameter Conditions RetEEPROM100k Retention after up to 100k Average ambient 55 C 10 50 - Years RetEEPROM10k Retention after up to 10k Average ambient 55 C 20 100 - Years CycEEPROM Cycling Endurance(2) -40 C < Ta < 125 C 100k 600k - Cycles Notes: 1. 2. Table C-17. Symbol The EEPROM emulation is a software emulation described in the App note AT03265. An endurance cycle is a write and an erase operation. NVM Characteristics Parameter Conditions Min. Typ. Max. Units tFPP Page programming time - - - 2.5 ms tFRE Row erase time I - - - 6 ms tFCE DSU chip erase time (CHIP_ERASE) - - - 240 ms Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1183 C.9 Oscillators Characteristics C.9.1 Crystal Oscillator (XOSC) Characteristics Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN. Table C-18. Symbol fCPXIN Digital Clock Characteristics Parameter Conditions XIN clock frequency I Min. Typ. Max. Units - - 32 MHz Crystal Oscillator Characteristics The following table describes the characteristics for the oscillator when a crystal is connected between XIN and XOUT as shown in Figure C-4. The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in the table. The exact value of CL can be found in the crystal datasheet. The capacitance of the external capacitors (CLEXT) can then be computed as follows: C LEXT = 2 ( CL - C STRAY - C SHUNT ) where CSTRAY is the capacitance of the pins and PCB, CSHUNT is the shunt capacitance of the crystal. Table C-19. Symbol fOUT ESR Crystal Oscillator Characteristics Parameter Crystal oscillator frequency Crystal Equivalent Series Resistance Safety Factor = 3 The AGC doesn t have any noticeable impact on these measurements. CXIN Parasitic capacitor load CXOUT Parasitic capacitor load Conditions Min. Typ. Max. Units 0.4 - 32 MHz f = 0.455MHz, CL = 100pF XOSC.GAIN = 0 - - 5.6K f = 2MHz, CL = 20pF XOSC.GAIN = 0 - - 416 f = 4MHz, CL = 20pF XOSC.GAIN = 1 - - 243 f = 8MHz, CL = 20pF XOSC.GAIN = 2 - - 138 f = 16MHz, CL = 20pF XOSC.GAIN = 3 - - 66 f = 32MHz, CL = 18pF XOSC.GAIN = 4 - - 56 I - 5.9 - pF - 3.2 - pF I Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1184 Table C-19. Symbol IXOSC tSTARTUP Figure C-4. Crystal Oscillator Characteristics (Continued) Parameter Conditions Current Consumption Startup time Min. Typ. Max. f = 2MHz, CL = 20pF, AGC off 27 65 90 f = 2MHz, CL = 20pF, AGC on 14 52 79 f = 4MHz, CL = 20pF, AGC off 61 117 161 f = 4MHz, CL = 20pF, AGC on 23 74 110 f = 8MHz, CL = 20pF, AGC off 131 226 319 f = 8MHz, CL = 20pF, AGC on 56 128 193 f = 16MHz, CL = 20pF, AGC off 305 502 742 f = 16MHz, CL = 20pF, AGC on 116 307 627 f = 32MHz, CL = 18pF, AGC off 1031 1622 2344 f = 32MHz, CL = 18pF, AGC on 278 615 1422 f = 2MHz, CL = 20pF, XOSC.GAIN = 0, ESR = 600 - 14K 48K f = 4MHz, CL = 20pF, XOSC.GAIN = 1, ESR = 100 - 6800 19.5K f = 8MHz, CL = 20pF, XOSC.GAIN = 2, ESR = 35 - 5550 13K f = 16MHz, CL = 20pF, XOSC.GAIN = 3, ESR = 25 - 6750 14.5K f = 32MHz, CL = 18pF, XOSC.GAIN = 4, ESR = 40 - 5.3K 9.6K Units A cycles Oscillator Connection Xin C LEXT Crystal LM C SHUNT RM C STRAY CM Xout C LEXT Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1185 C.9.2 External 32kHz Crystal Oscillator (XOSC32K) Characteristics Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN32 pin. Table C-20. Symbol Digital Clock Characteristics Parameter Conditions Min. Typ. Max. Units fCPXIN32 XIN32 clock frequency I - 32.768 - kHz I XIN32 clock duty cycle I - 50 - % Crystal Oscillator Characteristics Figure C-4 and the equation in "Crystal Oscillator (XOSC) Characteristics" on page 1184 also applies to the 32kHz oscillator connection. The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in the table. The exact value of CL can be found in the crystal datasheet. Table C-21. Symbol 32kHz Crystal Oscillator Characteristics Parameter Conditions Min. Typ. Max. Units fOUT Crystal oscillator frequency I - 32768 - Hz tSTARTUP Startup time ESRXTAL = 39.9k, CL = 12.5pF - 28K 31K cycles CL Crystal load capacitance I - - 12.5 CSHUNT Crystal shunt capacitance I - 0.1 - CXIN32 Parasitic capacitor load - 3.1 - CXOUT32 Parasitic capacitor load - 3.3 - IXOSC32K Current consumption - 1.22 2.44 A ESR Crystal equivalent series resistance f=32.768kHz Safety Factor = 3 - - 141 k TQFP64/48/32 packages CL=12.5pF Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 pF 1186 C.9.3 Digital Frequency Locked Loop (DFLL48M) Characteristics Table C-22. Symbol DFLL48M Characteristics - Open Loop Mode(1) (Device Variant A) Parameter Conditions DFLLVAL.COARSE = DFLL48M COARSE CAL Min. Typ. Max. Units 47 48 49 MHz - 403 457 A 7 8 9 s Min. Typ. Max. Units I fOUT Output frequency DFLLVAL.FINE = 512 DFLLVAL.COARSE = DFLL48M COARSE CAL I IDFLL Power consumption on VDDIN DFLLVAL.FINE = 512 tSTARTUP DFLLVAL.COARSE = DFLL48M COARSE CAL Startup time DFLLVAL.FINE = 512 fOUT within 90% of final value Note: 1. Table C-23. Symbol DFLL48M in Open loop after calibration at room temperature. DFLL48M Characteristics - Closed Loop Mode (Device Variant A) Parameter Conditions fOUT Average Output frequency fREF = 32.768kHz 47.76 48 48.24 MHz fREF Reference frequency I 0.732 32.768 33 kHz Jitter Period Jitter fREF = 32.768kHz - - 1.04 ns IDFLL Power consumption on VDDIN fREF = 32.768kHz - 425 482 A 100 200 500 s Conditions Min. Typ. Max. Units Calibrated against a 32.768kHz reference at 25 C, over [-40, +125]C, over [1.8, 3.6]V 28.508 32.768 35.389 Calibrated against a 32.768kHz reference at 25 C, at VDD=3.3V 32.276 32.768 33.260 Calibrated against a 32.768kHz reference at 25 C, over [1.8, 3.6]V 31.457 32.768 34.079 fREF = 32.768kHz DFLLVAL.COARSE = DFLL48M COARSE CAL tLOCK Lock time DFLLVAL.FINE = 512 DFLLCTRL.BPLCKC = 1 DFLLCTRL.QLDIS = 0 DFLLCTRL.CCDIS = 1 DFLLMUL.FSTEP = 10 C.9.4 32.768kHz Internal oscillator (OSC32K) Characteristics Table C-24. Symbol fOUT 32kHz RC Oscillator Characteristics (Device Variant A) Parameter Output frequency Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 kHz 1187 Symbol C.9.5 Parameter Conditions Min. Typ. Max. Units IOSC32K Current consumption I - 0.79 1.80 A tSTARTUP Startup time I - 1 2 cycle Duty Duty Cycle I - 50 - % Min. Typ. Max. Units Calibrated against a 32.768kHz reference at 25 C, over [-40, +125]C, over [1.8, 3.6]V 25.559 32.768 40.305 Calibrated against a 32.768kHz reference at 25 C, at VDD=3.3V 31.293 32.768 34.570 Calibrated against a 32.768kHz reference at 25 C, over [1.8, 3.6]V 31.293 32.768 34.570 - - 180 nA Ultra Low Power Internal 32kHz RC Oscillator (OSCULP32K) Characteristics Table C-25. Symbol fOUT Ultra Low Power Internal 32kHz RC Oscillator Characteristics Parameter Conditions Output frequency IOSCULP32K (1)(2) tSTARTUP Startup time I - 10 - cycles Duty Duty Cycle I - 50 - % Notes: 1. 2. C.9.6 kHz These values are based on simulation. These values are not covered by test limits in production or characterization. This oscillator is always on. 8MHz RC Oscillator (OSC8M) Characteristics Figure C-5. Symbol Internal 8MHz RC Oscillator Characteristics (Device Variant A) Parameter Conditions Min. Typ. Max. Calibrated against a 8MHz reference at 25 C, over [-40, +125]C, over [1.8, 3.6]V 7.54 8 8.19 Calibrated against a 8MHz reference at 25 C, at VDD=3.3V 7.94 8 8.06 Calibrated against a 8MHz reference at 25 C, over [1.8, 3.6]V 7.92 8 8.08 Units I fOUT Output frequency MHz IOSC8M Current consumption IDLE2 on OSC32K versus IDLE2 on calibrated OSC8M enabled at 8MHz (FRANGE=1, PRESC=0) - 64 100 A tSTARTUP Startup time I - 2.1 3 s Duty Duty cycle I - 50 - % I DLE Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1188 C.9.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics Table C-26. Symbol FDPLL96M Characteristics(1) (Device Variant A) Parameter Conditions Min. Typ. Max. Units fIN Input frequency 32 - 2000 KHz fOUT Output frequency 48 - 96 MHz IFDPLL96M Current consumption fIN= 32 kHz, fOUT= 48 MHz 500 700 fIN= 32 kHz, fOUT= 96 MHz 900 1200 1.5 2.0 fIN= 32 kHz, fOUT= 96 MHz 3.0 10.0 fIN= 2 MHz, fOUT= 48 MHz 1.3 2.0 fIN= 2 MHz, fOUT= 96 MHz 3.0 7.0 After startup, time to get lock signal. 1.3 2 ms 25 50 s 50 60 % fIN= 32 kHz, fOUT= 48 MHz Jp Period jitter tLOCK Lock Time - Note: C.9.8 Duty cycle 1. % fIN= 32 kHz, fOUT= 96 MHz fIN= 2 MHz, fOUT= 96 MHz Duty A 40 All values have been characterized with FILTSEL[1/0] as default value. USB Characteristics The USB shares the same characteristics as in the -40 C to 85 C. Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1189 C.10 Timing Characteristics C.10.1 SERCOM in SPI Mode Timing Data are not available in this current datasheet revision C.10.2 SERCOM in I2C Mode Timing Data are not available in this current datasheet revision Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1190 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1191 Table of Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1. Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 2.2 SAM R21E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SAM R21G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3. Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 3.2 MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SAM R21 Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4. Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 4.2 SAM R21G - QFN48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SAM R21E - QFN32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5. I/O Multiplexing and Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 5.2 5.3 5.4 5.5 Multiplexed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Multiplexed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Other Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog and RF Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 13 14 17 18 6. Power Supply and Start-Up Considerations . . . . . . . . . . . . . . . . . . . 20 6.1 6.2 6.3 6.4 Power Domain Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset and Brown-Out Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . 20 20 21 22 7. Product Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8. Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.1 8.2 8.3 Embedded Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Physical Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 NVM Calibration and Auxiliary Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9. Processor And Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.1 9.2 9.3 9.4 9.5 9.6 Cortex M0+ Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nested Vector Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Micro Trace Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Speed Bus System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AHB-APB Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PAC - Peripheral Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 29 31 32 35 36 10. Peripherals Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . 43 11. DSU - Device Service Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11.1 11.2 11.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1192 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 11.12 11.13 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debug Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chip-Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intellectual Property Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 46 47 48 48 49 50 51 56 59 12. Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12.1 12.2 12.3 12.4 12.5 12.6 12.7 Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous and Asynchronous Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enabling a Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-demand, Clock Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption vs Speed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocks after Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 83 83 87 88 88 88 13. GCLK - Generic Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 90 90 91 91 92 97 98 14. PM - Power Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 112 113 113 113 115 122 123 15. SYSCTRL - System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 143 144 145 145 146 160 162 16. WDT - Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 16.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1193 16.2 16.3 16.4 16.5 16.6 16.7 16.8 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 206 207 207 208 213 214 17. RTC - Real-Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 17.1 17.2 17.3 17.4 17.5 17.6 17.7 17.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 224 224 225 225 227 232 235 18. DMAC - Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . 267 18.1 18.2 18.3 18.4 18.5 18.6 18.7 18.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 267 268 268 268 270 288 291 19. EIC - External Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . 331 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 331 331 332 332 333 337 338 20. NVMCTRL - Non-Volatile Memory Controller . . . . . . . . . . . . . . . . 350 20.1 20.2 20.3 20.4 20.5 20.6 20.7 20.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 350 350 350 351 351 357 358 21. PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 21.1 21.2 21.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1194 21.4 21.5 21.6 21.7 21.8 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 374 376 381 383 22. EVSYS - Event System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 22.1 22.2 22.3 22.4 22.5 22.6 22.7 22.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 400 401 401 401 402 407 408 23. SERCOM - Serial Communication Interface . . . . . . . . . . . . . . . . . 426 23.1 23.2 23.3 23.4 23.5 23.6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 426 426 426 427 428 24. SERCOM USART - SERCOM Universal Synchronous and Asynchronous Receiver and Transmitter 434 24.1 24.2 24.3 24.4 24.5 24.6 24.7 24.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 434 435 435 435 437 448 450 25. SERCOM SPI - SERCOM Serial Peripheral Interface . . . . . . . . . . 472 25.1 25.2 25.3 25.4 25.5 25.6 25.7 25.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 472 472 472 473 474 483 485 26. SERCOM I2C - SERCOM Inter-Integrated Circuit . . . . . . . . . . . . . 505 26.1 26.2 26.3 26.4 26.5 26.6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 505 505 506 506 507 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1195 26.7 26.8 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 27. TC - Timer/Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 27.1 27.2 27.3 27.4 27.5 27.6 27.7 27.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 568 569 570 570 571 582 585 28. TCC - Timer/Counter for Control Applications . . . . . . . . . . . . . . . . 609 28.1 28.2 28.3 28.4 28.5 28.6 28.7 28.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 609 610 610 611 612 642 645 29. USB - Universal Serial Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702 29.1 29.2 29.3 29.4 29.5 29.6 29.7 29.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702 702 703 703 703 706 722 730 30. ADC - Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . 802 30.1 30.2 30.3 30.4 30.5 30.6 30.7 30.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802 802 802 803 804 805 815 817 31. AC - Analog Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842 31.1 31.2 31.3 31.4 31.5 31.6 31.7 31.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842 842 843 843 843 845 851 854 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1196 31.9 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855 32. PTC - Peripheral Touch Controller . . . . . . . . . . . . . . . . . . . . . . . . . 871 32.1 32.2 32.3 32.4 32.5 32.6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871 871 872 873 873 875 33. RFCTRL - AT86RF233 Front-End Control Signal Interface . . . . . . 876 33.1 33.2 33.3 33.4 33.5 33.6 33.7 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876 876 876 876 876 877 878 34. Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879 34.1 34.2 Basic Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879 Extended Feature Set Application Schematic . . . . . . . . . . . . . . . . . . . . . . . 881 35. AT86RF233 Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . 883 35.1 35.2 35.3 35.4 35.5 35.6 35.7 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Timing Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Radio Transceiver Status Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Radio Transceiver Identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sleep/Wake-up and Transmit Signal (SLP_TR). . . . . . . . . . . . . . . . . . . . . . Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883 884 885 890 891 894 896 36. AT86RF233 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902 36.1 36.2 Basic Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902 Extended Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915 37. AT86RF233 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . 947 37.1 37.2 37.3 37.4 37.5 37.6 37.7 Introduction - IEEE 802.15.4-2006 Frame Format . . . . . . . . . . . . . . . . . . . Frame Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frame Check Sequence (FCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Received Signal Strength Indicator (RSSI) . . . . . . . . . . . . . . . . . . . . . . . . . Energy Detection (ED) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clear Channel Assessment (CCA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Link Quality Indication (LQI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947 952 961 964 965 968 972 38. AT86RF233 Module Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 975 38.1 38.2 38.3 38.4 38.5 38.6 Receiver (RX). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter (TX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frame Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Regulators (AVREG, DVREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery Monitor (BATMON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Oscillator (XOSCRF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975 979 981 983 987 989 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1197 38.7 38.8 Frequency Synthesizer (PLL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993 Automatic Filter Tuning (FTN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001 39. AT86RF233 Radio Transceiver Usage . . . . . . . . . . . . . . . . . . . . . 1003 39.1 39.2 Frame Receive Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003 Frame Transmit Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003 40. AT86RF233 Extended Feature Set . . . . . . . . . . . . . . . . . . . . . . . . 1005 40.1 40.2 40.3 40.4 40.5 40.6 40.7 40.8 40.9 40.10 40.11 40.12 Security Module (AES). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Random Number Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High Data Rate Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Antenna Diversity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RX/TX Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RX and TX Frame Time Stamping (TX_ARET) . . . . . . . . . . . . . . . . . . . . . Frame Buffer Empty Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic Frame Buffer Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alternate Start-Of-Frame Delimiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reduced Power Consumption Mode (RPC) . . . . . . . . . . . . . . . . . . . . . . . Time-Of-Flight Module (TOM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase Difference Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005 1013 1013 1020 1025 1027 1030 1032 1033 1034 1039 1050 41. AT86RF233 Register Reference . . . . . . . . . . . . . . . . . . . . . . . . . . 1052 42. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055 42.1 42.2 42.3 42.4 42.5 42.6 42.7 42.8 42.9 42.10 42.11 42.12 42.13 42.14 42.15 Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Operating Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Clock Frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NVM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillators Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PTC Typical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AT86RF233 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055 1055 1056 1057 1057 1060 1063 1067 1069 1082 1083 1090 1094 1095 1101 43. Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1107 43.1 43.2 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1107 Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1108 44. Soldering Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111 45. Schematic Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1112 45.1 45.2 45.3 45.4 45.5 45.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Analog Reference Connections . . . . . . . . . . . . . . . . . . . . . . . . . . External Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unused or Unconnected Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocks and Crystal Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1112 1112 1113 1115 1115 1116 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1198 45.7 45.8 Programming and Debug Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1119 USB Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1123 46. About This Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125 46.1 46.2 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125 Acronyms and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1126 47. Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1131 47.1 47.2 47.3 47.4 Revision A Revision B Revision C Revision D ................................................. ................................................. ................................................. ................................................. 1131 1139 1148 1155 48. Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1163 48.1 48.2 48.3 48.4 48.5 48.6 48.7 Rev. G - 05/2016 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rev. F - 11/2015 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rev. E - 02/2015 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rev. D - 02/2015 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rev. C - 01/2015 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rev. B - 09/2014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rev. A - 07/2014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1163 1163 1164 1164 1165 1165 1166 Appendix A. Continuous Transmission Test Mode . . . . . . . . . . . . . . . 1167 A.1 A.2 A.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1167 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1167 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169 Appendix B. References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1170 Appendix C. Electrical Characteristics at 125C . . . . . . . . . . . . . . . . . 1171 C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 C.10 Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171 General Operating Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171 Supply Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1172 Maximum Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1174 Analog Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177 NVM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1183 Oscillators Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1184 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1190 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192 Atmel | SMART SAM R21 [DATASHEET] Atmel-42223G-SAM-R21_Datasheet-05/2016 1199 ARM Connected Logo Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com (c) 2016 Atmel Corporation. / Rev.: Atmel-42223G-SAM-R21_Datasheet_05/2016. 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