Atmel-42223G–SAM-R21_Datasheet–05/2016
SMART
Description
The Atmel® | SMART™ SAM R21 is a series of low-power microcontrollers using the 32-bit ARM®
Cortex®-M0+ processor and an integrated ultra-low power 2.4GHz ISM band transceiver. SAM
R21 devices are available in 32- and 48-pin packages with up to 256KB Flash, 32KB of SRAM
and are operating at a maximum frequency of 48MHz and reach 2.46 Coremark/MHz. They are
designed for simple and intuitive migration with identical peripheral modules, hex compatible
code, identical linear address map and pin compatible migration paths between all devices in the
product series. All devices include intelligent and flexible peripherals, Atmel Event System for
inter-peripheral signaling, and support for capacitive touch button, slider and wheel user
interfaces.
The Atmel SAM R21 devices provide the following features: In-system programmable Flash,
optional 512KB serial Flash,12-channel direct memory access (DMA) controller, 12-channel
Event System, programmable interrupt controller, up to 28 programmable I/O pins, ultra-low
power 2.4GHz ISM band transceiver with a data rate of 250kb/s, 32-bit real-time clock and
calendar, three 16-bit Timer/Counters (TC) and three 16-bit Timer/Counters for Control (TCC),
where each TC can be configured to perform frequency and waveform generation, accurate
program execution timing or input capture with time and frequency measurement of digital
signals. The TCs can operate in 8- or 16-bit mode, selected TCs can be cascaded to form a 32-bit
TC, and the three Timer/Counters for Control have extended functions optimized for motor,
lighting and other control applications. The series provide one full-speed USB 2.0 embedded host
and device interface; up to five Serial Communication Modules (SERCOM) that each can be
configured to act as an USART, UART, SPI, I2C up 3.4MHz and LIN slave; up to eight channel
350ksps 12-bit ADC with programmable gain and optional oversampling and decimation
supporting up to 16-bit resolution, two analog comparators with window mode, Peripheral Touch
Controller supporting up to 48 buttons, sliders, wheels and proximity sensing; programmable
Watchdog Timer, brown-out detector and power-on reset and two-pin Serial Wire Debug (SWD)
program and debug interface.
All devices have accurate and low-power external and internal oscillators. All oscillators can be
used as a source for the system clock. Different clock domains can be independently configured
to run at different frequencies, enabling power saving by running each peripheral at its optimal
clock frequency, and thus maintaining a high CPU frequency while reducing power consumption.
The SAM R21 devices have two software-selectable sleep modes, idle and standby. In idle mode
the CPU is stopped while all other functions can be kept running. In standby all clocks and
functions are stopped expect those selected to continue running. The device supports
SleepWalking, which is the module's ability to wake itself up and wake up its own clock, and
hence perform predefined tasks without waking up the CPU. The CPU can then be only woken on
a need basis, e.g. a threshold is crossed or a result is ready. The Event System supports
synchronous and asynchronous events, allowing peripherals to receive, react to and send events
even in standby mode.
The Flash program memory can be reprogrammed in-system through the SWD interface. The
same interface can be used for non-intrusive on-chip debug of application code. A boot loader
running in the device can use any communication interface to download and upgrade the
application program in the Flash memory.
The SAM R21 devices are supported with a full suite of program and system development tools,
including C compilers, macro assemblers, program debugger/simulators, programmers and
evaluation kits.
Atmel SAM R21E / SAM R21G
SMART ARM-Based Wireless Microcontroller
DATASHEET
2
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Features
zProcessor
zARM Cortex-M0+ CPU running at up to 48MHz
zSingle-cycle hardware multiplier
zMicro Trace Buffer (MTB)
zMemories
z768(1)/256/128/64KB in-system self-programmable Flash
z32/16/8KB SRAM
zSystem
zPower-on reset (POR) and brown-out detection (BOD)
zInternal and external clock options with 48MHz Digital Frequency Locked Loop (DFLL48M) and 48MHz to 96MHz Fractional
Digital Phase Locked Loop (FDPLL96M)
zExternal Interrupt Controller (EIC)
zUp to 15 external interrupts
zOne non-maskable interrupt
zTwo-pin Serial Wire Debug (SWD) programming, test and debugging interface
zLow Power
zIdle and standby sleep modes
zSleepWalking peripherals
zPeripherals
z12-channel Direct Memory Access Controller (DMAC)
z12-channel Event System
zIntegrated Ultra Low Power Transceiver for 2.4GHz ISM Band
zSupported PSDU Data rates: 250kb/s, 500kb/s, 1000kb/s and 2000kb/s(2)
z-99dBm RX Sensitivity; TX Output Power up to +4dBm
zHardware Assisted MAC (Auto-Acknowledge, Auto-Retry)
zSFD-Detection; Spreading; De-Spreading; Framing; CRC-16 Computation
zAntenna Diversity and TX/RX Control
z128 Byte TX/RX Frame Buffer
zIntegrated 16MHz Crystal Oscillator (external crystal needed)
zPLL synthesizer with 5 MHz and 500 kHz channel spacing for 2.4GHz ISM band
zHardware Security (AES, True Random Generator)
zThree 16-bit Timer/Counters (TC), configurable as either:
zOne 16-bit TC with compare/capture channels
zOne 8-bit TC with compare/capture channels
zOne 32-bit TC with compare/capture channels, by using two TCs
zThree 16-bit Timer/Counters for Control (TCC), with extended functions:
zUp to four compare channels with optional complementary output
zGeneration of synchronized pulse width modulation (PWM) pattern across port pins
zDeterministic fault protection, fast decay and configurable dead-time between complementary output
zDithering that increase resolution with up to 5 bit and reduce quantization error
z32-bit Real Time Counter (RTC) with clock/calendar function
zWatchdog Timer (WDT)
zCRC-32 generator
zOne full-speed (12Mbps) Universal Serial Bus (USB) 2.0 interface
zEmbedded host and device function
zEight endpoints
zUp to five Serial Communication Interfaces (SERCOM), each configurable to operate as either:
zUSART with full-duplex and single-wire half-duplex configuration
zI2C up to 3.4MHz
zSPI
zLIN slave
zOne 12-bit, 350ksps Analog-to-Digital Converter (ADC) with up to eight external channels
zDifferential and single-ended input
z1/2x to 16x programmable gain stage
zAutomatic offset and gain error compensation
zOversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution
zTwo Analog Comparators (AC) with window compare function
zPeripheral Touch Controller (PTC)
z48-channel capacitive touch and proximity sensing
zI/O and Package
z16/28 programmable I/O pins
z32-pin and 48-pin QFN
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Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
zOperating Voltage
z1.8V – 3.6V
zTemperature Range
z-40°C to 85°C Industrial
z-40°C to 125°C Industrial
Notes: 1. Only applicable for SAM R21E19: 256KB embedded + 512KB serial Flash.
2. High data rates (500kb/s, 1000kb/s and 2000kb/s) only applicable for T=-40°C to 85°C.
4
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
1. Configuration Summary
SAM R21G SAM R21E
Pins 48 32
General Purpose I/O-pins (GPIOs) 28 16
Flash 256/128/64KB 256/128/64KB
SRAM 32/16/8KB 32/16/8KB
Timer Counter (TC) instances 3 3
Waveform output channels per TC instance 2 2
Timer Counter for Control (TCC) instances 3 3
Waveform output channels per TCC 4/4/2 4/4/2
DMA channels 12 12
USB interface 1 1
Serial Communication Interface (SERCOM) instances 5+1(1) 4+1(1)
Inter-IC Sound (I2S) interface No No
Analog-to-Digital Converter (ADC) channels 8 4
Analog Comparators (AC) 2 2
Digital-to-Analog Converter (DAC)
channels No No
Real-Time Counter (RTC) Yes Yes
RTC alarms 1 1
RTC compare values 1 32-bit value or
2 16-bit values
1 32-bit value or
2 16-bit values
External Interrupt lines 15 14
Peripheral Touch Controller (PTC) X and Y lines 8x6 6x2
Maximum CPU frequency 48MHz
Packages QFN QFN
32.768kHz crystal oscillator (XOSC32K) Yes No
Oscillators
16MHz crystal oscillator for 2.4GHz TRX (XOSCRF)
0.4-32MHz crystal oscillator (XOSC)
32.768kHz internal oscillator (OSC32K)
32kHz ultra-low-power internal oscillator (OSCULP32K)
8MHz high-accuracy internal oscillator (OSC8M)
48MHz Digital Frequency Locked Loop (DFLL48M)
96MHz Fractional Digital Phased Locked Loop (FDPLL96M)
Event System channels 12 12
SW Debug Interface Yes Yes
Watchdog Timer (WDT) Yes Yes
5
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Note: 1. SERCOM4 is internally connected to the AT86RF233.
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Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
2. Ordering Information
2.1 SAM R21E
Note: 1. Serial Flash MX25V4006EWSK. For more information, see http://www.macronix.com.
ATSAMR 21 E 16 A - M U T
Product Family
SAMR = SoC Microcontroller with RF
Product Series
21 = Cortex M0+ CPU, USB
Flash Memory
19 = 256KB + 512KB
18 = 256KB
17 = 128KB
16 = 64KB
Device Variant
A = Default Variant
Pin Count
E = 32 Pins
G = 48 Pins
Package Carrier
No character = Tray (Default)
T = Tape and Reel
Package Grade
Package Type
M = QFN
U = -40 - 85°C Matte Sn Plating
F = -40 - 125°C Matte Sn Plating
Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type
ATSAMR21E16A-MF
64K 8K QFN32
Tray
ATSAMR21E16A-MFT Tape & R ee l
ATSAMR21E16A-MU Tray
ATSAMR21E16A-MUT Tape & R ee l
ATSAMR21E17A-MF
128K 16K QFN32
Tray
ATSAMR21E17A-MFT Tape & R ee l
ATSAMR21E17A-MU Tray
ATSAMR21E17A-MUT Tape & R ee l
ATSAMR21E18A-MF
256K 32K QFN32
Tray
ATSAMR21E18A-MFT Tape & R ee l
ATSAMR21E18A-MU Tray
ATSAMR21E18A-MUT Tape & R ee l
ATSAMR21E19A-MF
256K + 512K(1) 32K QFN32
Tray
ATSAMR21E19A-MFT Tape & R ee l
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Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
2.2 SAM R21G
Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type
ATSAMR21G16A-MF
64K 8K QFN48
Tray
ATSAMR21G16A-MFT Tape & R e el
ATSAMR21G16A-MU Tray
ATSAMR21G16A-MUT Tape & Re el
ATSAMR21G17A-MF
128K 16K QFN48
Tray
ATSAMR21G17A-MFT Tape & R e el
ATSAMR21G17A-MU Tray
ATSAMR21G17A-MUT Tape & Re el
ATSAMR21G18A-MF
256K 32K QFN48
Tray
ATSAMR21G18A-MFT Tape & R e el
ATSAMR21G18A-MU Tray
ATSAMR21G18A-MUT Tape & Re el
8
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
3. Block Diagrams
3.1 MCU Block Diagram
Notes: 1. Some products have different number of SERCOM instances, Timer/Counter instances, PTC signals and ADC sig-
nals. Refer to “Ordering Information” on page 6 for details.
2. The three TCC instances have different configurations, including the number of Waveform Output (WO) lines. Refer
to “Peripherals Configuration Summary” on page 43 for details.
3. Refer to the PORT Function Multiplexing Table 5-1 for details about the available GCLK_IO and ADC signals.
4. Only available for SAM R21G.
6 x SERCOM
8 x Timer Counter
REAL TIME
COUNTER
AHB-APB
BRIDGE C
M
M
HIGH SPEED
BUS MATRIX
PORT
PORT
WATCHDOG
TIMER
SERIAL
WIRE
SWDIO
S
CORTEX-M0+
PROCESSOR
Fmax 48 MHz
SWCLK
DEVICE
SERVICE
UNIT
AHB-APB
BRIDGE A
8-CHANNEL
12-bit ADC 350KSPS
AIN[n]
AIN[3..0]
S
SRAM
CONTROLLER
32/16/8KB
RAM
M
RESET
CONTROLLER
SLEEP
CONTROLLER
CLOCK
CONTROLLER
POWER MANAGER
RESETN
3 x TIMER / COUNTER
EVENT SYSTEM
S
5x SERCOM
2 ANALOG
COMPARATORS
SYSTEM CONTROLLER
OSCULP32K
OSC32K
OSC8M
DFLL48M
BOD33
VREF
X[7..0]
Y[5..0]
PERIPHERAL
TOUCH
CONTROLLER
PERIPHERAL
ACCESS CONTROLLER
AHB-APB
BRIDGE B
EXTERNAL INTERRUPT
CONTROLLER
PERIPHERAL
ACCESS CONTROLLER
PERIPHERAL
ACCESS CONTROLLER
EXTINT[15..1]
NMI
GCLK_IO[n]
S
XOUT
XIN
XOUT32
XIN32
XOSC32K
XOSC
PAD0
WO1
PAD1
PAD2
PAD3
WO0
VREFB
256/128/64KB
NVM
NVM
CONTROLLER
Cache
S
DMA
USB FS
DEVICE
MINI-HOST
DP
DM
3x TIMER / COUNTER
FOR CONTROL
WOn
IOBUS
FDPLL96M
DMA
DMA
DMA
DMA
MEMORY
TRACE BUFFER
S
SOF 1KHZ
WO0
WO1
(2)
(3)
(3) GENERIC CLOCK
CONTROLLER
(4)
9
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
3.2 SAM R21 Interconnection
SAMR21
AT86RF233
SAMD21
SPI
(Slave)
SERCOM 4(3)
XOSC
RF
/SEL
MISO
MOSI
SCLK
AVREG
2.4GHz TRX (analog)
DIG3
AVSS
AVSS
XTAL1
XTAL2
EXTERNAL
INTERRUPT
CONTROLLER
IRQ
Control Logic
GENERIC
CLOCK
CLKM
AVSS
ADC
DVREG
DVSS
DVDD
DEVDD
RFP
RFN
PC16
PB00
PC18
PC19
PB30
PB31
TRX (digital)
PORT
SLP_TR
RSTN
DIG2
DIG1
DIG4
2.4 GHz RF
front-end circuit
FECTRL0..1
AC
XOSC
32K
VREG
DVDD
GNDANA
RFN
RFP
AVSS GNDANA
XTAL1
XTAL2
GNDANA
VDDIO
AVDD
AVDD
EVDD
VDDANA
GNDANA
PAD3
PAD0
PAD2
PAD1
VDDIN
VDDCORE
GND
EXTINT0
GCLK_IO1
(4)
PTC
PA09
PA08
PA13
(2)
PA12
(2)
PA14
PA15
FECTRL2..5
(1)
Notes: 1. Paddle connected to digital ground DVSS, GND.
2. Only available for SAM R21G.
3. Dedicated SERCOM4 alternate pin function mapping for internally connected AT86RF233.
4. Die revision A uses GCLK_IO5.
5. Only available for SAM R21E19.
RFCTRL
DIG1..4
SERCOM 5
PAD3
PAD0
PAD2
PAD1
PA20
PB15
MX25V4006(5)
(1)
PB23
PA22
PB22
PA23
SI
CS#
SCLK
SO
PORT
GND PA12
WP#
PA00
HOLD#VCC
10
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
4. Pinout
4.1 SAM R21G - QFN48
Note: The large center pad underneath the QFN package is made of metal and internally connected to GND.
It should be soldered and connected to the digital ground on the board to ensure good mechanical stability.
It is not recommended to use the exposed paddle as a replacement of the regular GND pin.
GND
VDDIO 13
GND 14
PA08 15
PA09 16
GNDANA 17
RFP 18
RFN 19
GNDANA 20
PA12 21
PA13 22
PA14 23
PA15 24
PA1625
PA1726
PA1827
PA1928
GND29
DVDD30
PA2231
PA2332
PA2433
PA2534
GND35
VDDIO36
PB0348
PB0247
PA3146
PA3045
VDDIN44
VDDCORE43
42
PA2841
RESET40
PA2739
PB2338
PB2237
PA00 1
PA01 2
XTAL2 3
XTAL1 4
GNDANA 5
VDDANA 6
AVDD 7
GNDANA 8
PA04 9
PA05 10
PA06 11
PA07 12
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
RF PIN
DIGITAL PIN/
OSCILLATOR
11
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
4.2 SAM R21E - QFN32
Note: The large center pad underneath the QFN package is made of metal and internally connected to GND.
It should be soldered and connected to the digital ground on the board to ensure good mechanical stability.
It is not recommended to use the exposed paddle as a replacement of the regular GND pin.
PA08
PA09
GNDANA
RFP
RFN
GNDANA
PA14
PA15
PA1617
PA1718
PA1819
PA1920
DVDD21
PA2422
PA2523
VDDIO24
PA3132
PA3031
VDDIN30
VDDCORE29
GND28
PA2827
RESET26
PA2725
XTAL2 1
XTAL1 2
GNDANA 3
VDDANA 4
AVDD 5
GNDANA 6
PA06 7
PA07 8
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT
RESET PIN
9
10
11
12
13
14
15
16
RF PIN
DIGITAL PIN/
SUPPLY OSCILLATOR
12
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
5. I/O Multiplexing and Considerations
5.1 Multiplexed Signals
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned to one of the
peripheral functions A, B, C, D, E, F, G or H. To enable a peripheral function on a pin, the Peripheral Multiplexer Enable
bit in the Pin Configuration register corresponding to that pin (PINCFGn.PMUXEN, n = 0..31) in the PORT must be
written to one. The selection of peripheral function A to H is done by writing to the Peripheral Multiplexing Odd and Even
bits in the Peripheral Multiplexing register (PMUXn.PMUXE/O) in the PORT.
Table 5-1 describes the peripheral signals multiplexed to the PORT I/O pins.
Table 5-1. PORT Function Multiplexing
Pin
I/O Pin Supply Type
A B(1)(2) C D E F G H
SAMR21
E
SAMR21
GEIC REF ADC AC PTC
SERCOM
(1)(2)
SERCOM-
ALT
TC
TCC
FECTRL
TCC
SERCOM COM
AC/
GCLK
1PA00 VDDANA SERCOM1/
PAD[0] TCC2/WO[0]
2PA01 VDDANA EXTINT[1] SERCOM1/
PAD[1] TCC2/WO[1]
9PA04 VDDANA EXTINT[4]
ADC/
VREFB
AIN[4] AIN[0] Y[2] SERCOM0/
PAD[0] TCC0/WO[0]
10 PA05 VDDANA EXTINT[5] AIN[5] AIN[1] Y[3] SERCOM0/
PAD[1] TCC0/WO[1]
711 PA06 VDDANA EXTINT[6] AIN[6] AIN[2] Y[4] SERCOM0/
PAD[2] TCC1/WO[0]
812 PA07 VDDANA EXTINT[7] AIN[7] AIN[3] Y[5] SERCOM0/
PAD[3] TCC1/WO[1]
915 PA08 VDDIO I2CNMI AIN[16] X[0] SERCOM0/
PAD[0]
SERCOM2/
PAD[0] TCC0/WO[0] FECTRL[0]
10 16 PA09 VDDIO I2CEXTINT[9] AIN[17] X[1] SERCOM0/
PAD[1]
SERCOM2/
PAD[1] TCC0/WO[1] FECTRL[1]
21 PA12 VDDIO I2CEXTINT[12] SERCOM2/
PAD[0] TCC2/WO[0] FECTRL[2] AC/
CMP[0]
22 PA13 VDDIO I2CEXTINT[13] SERCOM2/
PAD[1] TCC2/WO[1] FECTRL[3] AC/
CMP[1]
15 23 PA14 VDDIO EXTINT[14] SERCOM2/
PAD[2] TC3/WO[0] FECTRL[4] GCLK_IO[0]
16 24 PA15 VDDIO EXTINT[15] SERCOM2/
PAD[3] TC3/WO[1] FECTRL[5] GCLK_IO[1]
17 25 PA16 VDDIO I2CX[4] SERCOM1/
PAD[0]
SERCOM3/
PAD[0] TCC2/WO[0] TCC0/
WO[0] GCLK_IO[2]
18 26 PA17 VDDIO I2CEXTINT[1] X[5] SERCOM1/
PAD[1]
SERCOM3/
PAD[1] TCC2/WO[1] TCC0/
WO[1] GCLK_IO[3]
19 27 PA18 VDDIO EXTINT[2] X[6] SERCOM1/
PAD[2]
SERCOM3/
PAD[2] TC3/WO[0] TCC0/
WO[2]
AC/
CMP[0]
20 28 PA19 VDDIO EXTINT[3] X[7] SERCOM1/
PAD[3]
SERCOM3/
PAD[3] TC3/WO[1] TCC0/
WO[3]
AC/
CMP[1]
31 PA22 VDDIO I2CEXTINT[6] X[10] SERCOM3/
PAD[0]
SERCOM5/
PAD[0] TC4/WO[0] TCC0/
WO[4] GCLK_IO[6]
32 PA23 VDDIO I2CEXTINT[7] X[11] SERCOM3/
PAD[1]
SERCOM5/
PAD[1] TC4/WO[1] TCC0/
WO[5]
USB/
SOF1kHz GCLK_IO[7]
22 33 PA24 VDDIO EXTINT[12] SERCOM3/
PAD[2]
SERCOM5/
PAD[2] TC5/WO[0] TCC1/
WO[2] USB_DM
23 34 PA25 VDDIO EXTINT[13] SERCOM3/
PAD[3]
SERCOM5/
PAD[3] TC5/WO[1] TCC1/
WO[3] USB_DP
13
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Notes: 1. All analog pin functions are on peripheral function B. Peripheral function B must be selected to disable the digital control of the pin.
2. Only some pins can be used in SERCOM I2C mode. See the Type column for using a SERCOM pin in I2C mode. Refer to “Electrical Characteristics” on page
1055 for details on the I2C pin characteristics.
3. This function is only activated in the presence of a debugger.
5.2 Internal Multiplexed Signals
PA20, PB00, PB15, PB30, PB31, PC16, PC18 and PC19 are by default controlled by the PORT as a general purpose I/O
and alternatively it can be assigned to one of the peripheral functions A, B, C, D, E, F, G or H. To enable a peripheral
function on a pin, the Peripheral Multiplexer Enable bit in the Pin Configuration register corresponding to that pin
(PINCFGn.PMUXEN, n = 0-31) in the PORT must be written to one. The selection of peripheral function A to H is done
by writing to the Peripheral Multiplexing Odd and Even bits in the Peripheral Multiplexing register (PMUXn.PMUXE/O) in
the PORT.
PA10, PA11, PB16 and PB17 cannot be configured as output ports. These ports are always connected to the RFCTRL
inputs.
37 PB22 VDDIO EXTINT[6] SERCOM5/
PAD[2] GCLK_IO[0]
38 PB23 VDDIO EXTINT[7] SERCOM5/
PAD[3] GCLK_IO[1]
25 39 PA27 VDDIO EXTINT[15] SERCOM3/
PAD[0] GCLK_IO[0]
27 41 PA28 VDDIO EXTINT[8] SERCOM3/
PAD[1] GCLK_IO[0]
31 45 PA30 VDDIO EXTINT[10] SERCOM1/
PAD[2] TCC1/WO[0] SWCLK GCLK_IO[0]
32 46 PA31 VDDIO EXTINT[11] SERCOM1/
PAD[3] TCC1/WO[1] SWDIO(3)
47 PB02 VDDANA EXTINT[2] AIN[10] Y[8] SERCOM5/
PAD[0]
48 PB03 VDDANA EXTINT[3] AIN[11] Y[9] SERCOM5/
PAD[1]
Table 5-1. PORT Function Multiplexing (Continued)
Pin
I/O Pin Supply Type
A B(1)(2) C D E F G H
SAMR21
E
SAMR21
GEIC REF ADC AC PTC
SERCOM
(1)(2)
SERCOM-
ALT
TC
TCC
FECTRL
TCC
SERCOM COM
AC/
GCLK
Internal
Signal I/O Pin Supply Type
A B C D E F G H
EIC REF ADC AC PTC SERCOM
SERCOM-
ALT TC
FECTRL
TCC
SERCOM COM
AC/
GCLK
DIG3 PA10 VDDIO Input EXTINT[10]
DIG4 PA11 VDDIO Input EXTINT[11]
SLP_TR PA20 VDDIO I/O
IRQ PB00 VDDANA I/O EXTINT[0]
RSTN PB15 VDDIO I/O
DIG1 PB16 VDDIO Input EXTINT[0]
DIG2 PB17 VDDIO Input EXTINT[1]
MOSI PB30 VDDIO I/O SERCOM4/
PAD[2]
SEL PB31 VDDIO I/O SERCOM4/
PAD[1]
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Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Note: 1. Die revision A uses GCLK/IO[5].
5.3 Other Functions
5.3.1 Oscillator Pinout
The oscillators are not mapped to the normal PORT functions and their multiplexing are controlled by registers in the
System Controller (SYSCTRL). Refer to “SYSCTRL – System Controller” on page 143 for more information.
The integrated AT86RF233 16 MHz crystal oscillator is directly connected to pins and has no multiplexing functionality.
5.3.2 Serial Wire Debug Interface Pinout
Only the SWCLK pin is mapped to the normal PORT functions. A debugger cold-plugging or hot-plugging detection will
automatically switch the SWDIO port to the SWDIO function. Refer to “DSU – Device Service Unit” on page 45 for more
information.
CLKM PC16 VDDIO I/O GCLK/
IO[1](1)
SCLK PC18 VDDIO I/O SERCOM4/
PAD[3]
MISO PC19 VDDIO I/O SERCOM4/
PAD[0]
Internal
Signal I/O Pin Supply Type
A B C D E F G H
EIC REF ADC AC PTC SERCOM
SERCOM-
ALT TC
FECTRL
TCC
SERCOM COM
AC/
GCLK
Oscillator Supply Signal I/O Pin
XOSC VDDIO
XIN PA14
XOUT PA15
XOSC32K VDDANA
XIN32 PA00
XOUT32 PA01
Oscillator Supply Signal I/O Pin
XOSCRF EVDD/VDDANA
XTAL1 XTAL1
XTAL2 XTAL2
Signal Supply I/O Pin
SWCLK VDDIO PA30
SWDIO VDDIO PA31
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Atmel | SMART SAM R21 [DATASHEET]
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5.3.3 General Circuit Description
The Atmel AT86RF233 single-chip radio transceiver provides a complete radio transceiver interface between an antenna
and the SAM D21 microcontroller. It comprises the analog radio, digital modulation and demodulation including time and
frequency synchronization, as well as data buffering. A single 128-byte TRX buffer stores receive or transmit data.
Communication between transmitter and receiver is based on direct sequence spread spectrum with different modulation
schemes and spreading codes.
The AT86RF233 block diagram is shown in Figure 5-1.
Figure 5-1. AT86RF233 Block Diagram
The number of external components is minimized such that only the antenna, the crystal and decoupling capacitors are
required. The bidirectional differential antenna pins (RFP, RFN) are used for transmission and reception, thus no external
antenna switch is needed. Control of an external power amplifier is supported by two digital control signals (differential
operation).
The received RF signal at SAM R21 pin 13/19 (RFN) and pin 12/18 (RFP) is differentially fed through the low-noise
amplifier (LNA) to the RF filter (PPF) to generate a complex signal, driving the integrated channel filter (BPF). The limiting
amplifier provides sufficient gain to drive the succeeding analog-to-digital converter (ADC) and generates a digital RSSI
signal. The ADC output signal is sampled by the digital base band receiver (RX BBP).
The transmit modulation scheme is offset-QPSK (O-QPSK) with half-sine pulse shaping and 32-length block coding
(spreading) according to [1], [2] and [3]. The modulation signal is generated in the digital transmitter (TX BBP) and
applied to the fractional-N frequency synthesis (PLL), to ensure the coherent phase modulation required for
demodulation of O-QPSK signals. The frequency-modulated signal is fed to the power amplifier (PA).
Two on-chip low-dropout voltage regulators (A|DVREG) provide regulated analog and digital 1.8V supply outputs.
An internal 128-byte RAM for RX and TX (Frame Buffer) buffers the data to be transmitted or the received data.
The configuration of the internal AT86RF233, reading and writing of Frame Buffer is controlled by the SPI interface and
additional control lines.
The AT86RF233 further contains comprehensive hardware-MAC support (Extended Operating Mode) and a security
engine (AES) to improve the overall system power efficiency and timing. The stand-alone 128-bit AES engine can be
AVREG
LNA
PLL PA
PPF BPF ADC
AGC
ext. PA and Power
Control
Configuration Registers
SPI
(Slave)
RSSI
IRQ
CLKM
/RST
SLP_TR
/SEL
MISO
MOSI
SCLK
DIG3/4
RFP
RFN
TX Data
Control Logic
DIG2
Antenna Diversity
FTN, BATMON
XOSCRF
Analog Domain Digital Domain
AES
DIG1/2
AD
DVREG
RX BBP
Frame
Buffer
TX BBP
Limiter
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accessed in parallel to all PHY operational transactions and states using the SPI interface, except during SLEEP and
DEEP_SLEEP states.
For long-range applications or to improve the reliability of a RF connection the RF performance can further be improved
by using an external RF front-end or Antenna Diversity. Both operation modes are supported by the AT86RF233 with
dedicated control signals DIG1, …, DIG4 which can be activated as alternate pin output functions FECTRL[0..5] by the
integrated microcontroller.
Additional features of the Extended Feature Set, see “AT86RF233 Extended Feature Set” on page 1005, are provided to
simplify the interaction between radio transceiver and microcontroller.
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5.4 Analog and RF Pins
5.4.1 Supply and Ground Pins
5.4.1.1 EVDD, DEVDD
EVDD and DEVDD are analog and digital supply voltage pins of the AT86RF233 radio transceiver.
5.4.1.2 AVDD, DVDD
AVDD and DVDD are outputs of the internal voltage regulators and require bypass capacitors for stable operation. The
voltage regulators are controlled independently by the radio transceivers state machine and are activated depending on
the current radio transceiver state. The voltage regulators can be configured for external supply; for details, refer to
“Voltage Regulators (AVREG, DVREG)” on page 983.
5.4.1.3 AVSS, DVSS
AVSS and DVSS are analog and digital ground pins respectively. The analog and digital power domains should be
separated on the PCB.
5.4.2 RF Pins
5.4.2.1 RFN, RFP
A differential RF port (RFP/RFN) provides common-mode rejection to suppress the switching noise of the internal digital
signal processing blocks. At board-level, the differential RF layout ensures high receiver sensitivity by reducing spurious
emissions originated from other digital ICs such as a microcontroller.
The RF port is designed for a 100Ω differential load. A DC path between the RF pins is allowed; a DC path to ground or
supply voltage is not allowed.
A simplified schematic of the RF front end is shown in Figure 5-2.
Figure 5-2. Simplified RF Front-end Schematic.
The RF port DC values depend on the operating state; refer to “AT86RF233 Operating Modes” on page 902. In
TRX_OFF state, when the analog front-end is disabled (see “TRX_OFF – Clock State” on page 904), the RF pins are
pulled to ground, preventing a floating voltage larger than 1.8V which is not allowed for the internal circuitry.
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Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
In transmit mode, a control loop provides a common-mode voltage of 0.9V. Transistor M0 is off, allowing the PA to set
the common-mode voltage. The common-mode capacitance at each pin to ground shall be < 30pF to ensure the stability
of this common-mode feedback loop.
In receive mode, the RF port provides a low-impedance path to ground when transistor M0, (see Figure 5-2) pulls the
inductor center tap to ground. A DC voltage drop of 20mV across the on-chip inductor can be measured at the RF pins.
5.4.3 Crystal Oscillator Pins
5.4.3.1 XTAL1, XTAL2
The pin 2/4 (XTAL1) of SAM R21 is the input of the reference oscillator amplifier (XOSCRF), the pin 1/3 (XTAL2) is the
output. A detailed description of the crystal oscillator setup and the related XTAL1/XTAL2 pin configuration can be found
in “Crystal Oscillator (XOSCRF)” on page 989.
When using an external clock reference signal, XTAL1 shall be used as input pin. For further details, refer to “External
Reference Frequency Setup” on page 990.
5.4.4 Analog Pin Summary
5.5 Digital I/O Signals
The AT86RF233 provides a digital microcontroller interface. The interface comprises a slave SPI (/SEL, SCLK, MOSI,
and MISO) and additional control signals (CLKM, IRQ, SLP_TR, /RST, and DIG2). The microcontroller interface is
described in detail in “AT86RF233 Microcontroller Interface” on page 883.
Additional digital output signals DIG1, …, DIG4 are provided to control external blocks, that is for Antenna Diversity RF
switch control or as an RX/TX Indicator, see “Antenna Diversity” on page 1020 and “RX/TX Indicator” on page 1025
respectively.
5.5.1 Driver Strength Settings
The driver strength of all digital output signals (MISO, IRQ, DIG1,..., DIG4 and CLKM) to the microcontroller are fixed.
Table 5-2. Analog Pin Behavior - DC values
Pin Values and Conditions Description
RFP/RFN
VDC = 0.9V (BUSY_TX)
VDC = 20mV (receive states)
VDC = 0mV (otherwise)
DC level at pins RFP/RFN for various transceiver states.
AC coupling is required if a circuitry with a DC path to ground
or supply is used. Serial capacitance and capacitance of each
pin to ground must be < 30pF.
XTAL1/XTAL2 VDC = 0.9V at both pins
CPAR = 3pF
DC level at pins XTAL1/XTAL2 for various transceiver states.
Parasitic capacitance (CPAR) of the pins must be considered as
additional load capacitance to the crystal.
DVDD
VDC = 1.8V (all states, except SLEEP
and DEEP_SLEEP)
VDC = 0mV (DEEP_SLEEP)
VDC = 1.5V (SLEEP)
DC level at pin DVDD for various transceiver states.
Supply pins (voltage regulator output) for the digital 1.8V
voltage domain. The outputs shall be bypassed by 100nF.
AVDD
VDC = 1.8V (all states, except P_ON,
SLEEP, DEEP_SLEEP, RESET, and
TRX_OFF)
VDC = 0mV (otherwise)
DC level at pin AVDD for various transceiver states.
Supply pin (voltage regulator output) for the analog 1.8V
voltage domain. The outputs shall be bypassed by 100nF.
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5.5.2 Pull-up and Pull-down Configuration
Pulling transistors are internally connected to all digital inputs from the microcontroller in radio transceiver states P_ON
(including reset during P_ON) and DEEP_SLEEP, refer to “P_ON – Power-On after VDD” on page 903 and
“DEEP_SLEEP – Deep Sleep State” on page 904.
Table 5-3 summarizes the pull-up and pull-down configuration.
Note: 1. Except SLP_TR pin for DEEP_SLEEP state.
In all other radio transceiver states, including RESET, no pull-up or pull-down transistors are connected to any of the
digital inputs mentioned in Table 5-3.
In all other states, external circuitry should guaranty defined levels at all input pins. Floating input signals may cause
unexpected functionality and increased power consumption, for example in SLEEP state.
If the additional digital output signals DIG1, …, DIG4 are not activated, they are pulled-down to digital ground
(DIG1/DIG2) or analog ground (DIG3/DIG4).
Table 5-3. Pull-Up / Pull-Down Configuration of Digital Input Signals from the Microcontroller
Signal H = pull-up, L = pull-down
/RST H
/SEL H
SCLK L
MOSI L
SLP_TR(1))L
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Atmel | SMART SAM R21 [DATASHEET]
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6. Power Supply and Start-Up Considerations
6.1 Power Domain Overview
6.2 Power Supply Considerations
6.2.1 Power Supplies
The Atmel® SAM R21 has several different power supply pins:
zVDDIO: Powers I/O lines, OSC8M and XOSC. Voltage is 1.8V to 3.6V.
zVDDIN: Powers I/O lines, the internal regulator and the stacked 512KB serial Flash. Voltage is 1.8V to 3.6V.
zVDDANA: Powers I/O lines and the ADC, AC, PTC, OSCULP32K, OSC32K, XOSC32K. Voltage is 1.8V to 3.6V.
zVDDCORE: Internal regulated voltage output. Powers the core, memories, peripherals, DFLL48M and
FDPLL96M. Voltage is 1.2V.
The same voltage must be applied to both VDDIN, VDDIO and VDDANA. This common voltage is referred to as VDD in
the datasheet.
The ground pins, GND, are common to VDDCORE, VDDIO and VDDIN. The ground pin for VDDANA is GNDANA.
For decoupling recommendations for the different power supplies, refer to the schematic checklist.
Refer to “Schematic Checklist” on page 1112 for details.
VOLTAGE
REGULATOR
VDDIN
VDDCORE
GND
ADC
AC
PTC
XOSC32K
OSC32K
VDDANA
GNDANA
PA[7:4]
PB[3:2]
PA[1:0]
Digital Logic
(CPU, peripherals)
DFLL48M
VDDIO
OSC8M
XOSC
OSCULP32K
PA[31:16]
PB[31:10]
PA[15:14]
BOD33
POR
PA[13:8]
BOD12
FDPLL96M
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6.2.2 Voltage Regulator
The SAM R21 voltage regulator has two different modes:
zNormal mode: To be used when the CPU and peripherals are running
zLow Power (LP) mode: To be used when the regulator draws small static current. It can be used in standby mode
6.2.3 Typical Powering Schematics
The SAM R21 uses a single supply from 1.8V to 3.6V.
The following figure shows the recommended power supply connection.
Figure 6-1. Power Supply Connection
6.2.4 Power-Up Sequence
6.2.4.1 Minimum Rise Rate
The integrated power-on reset (POR) circuitry monitoring the VDDANA power supply requires a minimum rise rate. Refer
to the “Electrical Characteristics” on page 1055 for details.
6.2.4.2 Maximum Rise Rate
The rise rate of the power supply must not exceed the values described in Electrical Characteristics. Refer to the
“Electrical Characteristics” on page 1055 for details.
6.3 Power-Up
This section summarizes the power-up sequence of the SAM R21. The behavior after power-up is controlled by the
Power Manager. Refer to “PM – Power Manager” on page 112 for details.
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6.3.1 Starting of Clocks
After power-up, the device is set to its initial state and kept in reset, until the power has stabilized throughout the device.
Once the power has stabilized, the device will use a 1MHz clock. This clock is derived from the 8MHz Internal Oscillator
(OSC8M), which is divided by eight and used as a clock source for generic clock generator 0. Generic clock generator 0
is the main clock for the Power Manager (PM).
Some synchronous system clocks are active, allowing software execution.
Refer to the “Clock Mask Register” section in “PM – Power Manager” on page 112 for the list of default peripheral clocks
running. Synchronous system clocks that are running are by default not divided and receive a 1MHz clock through
generic clock generator 0. Other generic clocks are disabled except GCLK_WDT, which is used by the Watchdog Timer
(WDT).
6.3.2 I/O Pins
After power-up, the I/O pins are tri-stated.
6.3.3 Fetching of Initial Instructions
After reset has been released, the CPU starts fetching PC and SP values from the reset address, which is 0x00000000.
This address points to the first executable address in the internal flash. The code read from the internal flash is free to
configure the clock system and clock sources. Refer to “PM – Power Manager” on page 112, “GCLK – Generic Clock
Controller” on page 90 and “SYSCTRL – System Controller” on page 143 for details. Refer to the ARM Architecture
Reference Manual for more information on CPU startup (http://www.arm.com).
6.4 Power-On Reset and Brown-Out Detector
The SAM R21 embeds three features to monitor, warn and/or reset the device:
zPOR: Power-on reset on VDDANA
zBOD33: Brown-out detector on VDDANA
zBOD12: Voltage Regulator Internal Brown-out detector on VDDCORE. The Voltage Regulator Internal BOD is
calibrated in production and its calibration configuration is stored in the NVM User Row. This configuration should
not be changed if the user row is written to assure the correct behavior of the BOD12.
6.4.1 Power-On Reset on VDDANA
POR monitors VDDANA. It is always activated and monitors voltage at startup and also during all the sleep modes. If
VDDANA goes below the threshold voltage, the entire chip is reset.
6.4.2 Brown-Out Detector on VDDANA
BOD33 monitors VDDANA. Refer to “SYSCTRL – System Controller” on page 143 for details.
6.4.3 Brown-Out Detector on VDDCORE
Once the device has started up, BOD12 monitors the internal VDDCORE.
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Atmel | SMART SAM R21 [DATASHEET]
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7. Product Mapping
Figure 7-1. Atmel | SMART SAM R21 Product Mapping
This figure represents the full configuration of the Atmel | SMART SAM R21 with maximum Flash and SRAM capabilities and a full
set of peripherals. Refer to the “Configuration Summary” on page 4 for details.
Code
SRAM
Undefined
Peripherals
Reserved
Undefined
Reserved
Global Memory Space
0x00000000
0x20000000
0x22008000
0x40000000
0x43000000
0x60000000
0x60000200
0xFFFFFFFF
Internal SRAM
SRAM
AHB-APB
Bridge A
AHB-APB
Bridge B
AHB-APB
Bridge C
AHB-APB
Internal Flash
Reserved
Code
0x00000000
0x00400000
0x1FFFFFFF
0x20000000
0x20008000
0x40000000
0x41000000
0x42000000
0x42FFFFFF
Reserved
PAC0
PM
SYSCTRL
GCLK
WDT
RTC
EIC
AHB-APB Bridge A
0x40000000
0x40000400
0x40000800
0x40000C00
0x40001000
0x40001400
0x40001800
0x40FFFFFF
0x40001C00
AHB-APB Bridge B
Reserved
PAC1
DSU
NVMCTRL
PORT
0x41000000
0x41002000
0x41004000
0x41004400
0x41FFFFFF
0x41004700
SERCOM5
PAC2
EVSYS
SERCOM0
SERCOM1
SERCOM2
SERCOM3
SERCOM4(1)
AHB-APB Bridge C
Reserved
TCC0
TCC1
TCC2
TC3
TC4
TC5
Reserved
ADC
AC
0x42000000
0x42000400
0x42000800
0x42000C00
0x42001000
0x42001400
0x42001800
0x42002000
0x42001C00
0x42003000
0x42003400
0x42003800
0x42003C00
0x42004000
0x42004400
0x42004800
Reserved
0x40FFFFFF
Reserved
0x42004C00
0x42002400
0x42002800
0x42002C00
PTC
0x42005400
0x42005000
Reserved
RFCTRL
0x42005800
DMAC
USB
MTB
0x41004800
0x41005000
0x41006000
Note 1. SERCOM4 is internally connected to the AT86RF233.
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Atmel | SMART SAM R21 [DATASHEET]
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8. Memories
8.1 Embedded Memories
zInternal high-speed flash
zInternal high-speed RAM, single-cycle access at full speed
zStacked 512KB serial Flash (SAMR21E19A)
8.2 Physical Memory Map
The High-Speed bus is implemented as a bus matrix. All High-Speed bus addresses are fixed, and they are never
remapped in any way, even during boot. The 32-bit physical address space is mapped as follow:
Table 8-1. SAM R21 physical memory map(1)
Note: 1. x = G or E. Refer to “Ordering Information” on page 6 for details.
Table 8-2. Flash memory parameters(1)
Note: 1. x = G or E. Refer to “Ordering Information” on page 6 for details.
2. The number of pages (NVMP) and page size (PSZ) can be read from the NVM Pages and Page Size bits in
the NVM Parameter register in the NVMCTRL (PARAM.NVMP and PARAM.PSZ, respectively). Refer to
PARAM for details.
3. The Flash memory parameters refers to the embedded memories: SAMR21x19 shares same embedded
memories as SAMR21x18.
Memory Start address
Size
SAMR21x19 SAMR21x18 SAMR21x17 SAMR21x16
Embedded Flash 0x00000000 256Kbytes 256Kbytes 128Kbytes 64Kbytes
Embedded SRAM 0x20000000 32Kbytes 32Kbytes 16Kbytes 8Kbytes
Peripheral Bridge A 0x40000000 64Kbytes 64Kbytes 64Kbytes 64Kbytes
Peripheral Bridge B 0x41000000 64Kbytes 64Kbytes 64Kbytes 64Kbytes
Peripheral Bridge C 0x42000000 64Kbytes 64Kbytes 64Kbytes 64Kbytes
Device Flash size Number of pages Page size
SAMR21x19(3) 256Kbytes 4096 64 bytes
SAMR21x18 256Kbytes 4096 64 bytes
SAMR21x17 128Kbytes 2046 64 bytes
SAMR21x16 64Kbytes 1024 64 bytes
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8.3 NVM Calibration and Auxiliary Space
The device calibration data are stored in different sections of the NVM calibration and auxiliary space presented in Figure
8-1.
Figure 8-1. Calibration and Auxiliary Space
The values from the automatic calibration row are loaded into their respective registers at startup.
8.3.1 NVM User Row Mapping
The NVM User Row contains calibration data that are automatically read at device power on.
The NVM User Row can be read at address 0x804000.
To write the NVM User Row refer to “NVMCTRL – Non-Volatile Memory Controller” on page 350.
Note that when writing to the user row the values do not get loaded by the other modules on the device until a device
reset occurs.
0x00800000
AUX0 offset address
Automatic calibration
row Calibration and auxiliary
space address offset
AUX0 – NVM User
Row
AUX1
0x00804000
0x00806000 AUX1 offset address
0x00806000
Area 3 offset ad
Area 1: Reserved (64 bits)
Area 2: Device configuration
area (64 bits)
Area 1 address
Area 2 offset ad
Area 3: Reserved
(128bits)
Area 4: Software
calibration area (256bits)
0x00806008
0x00806010
0x00806020 Area 4 offset add
AUX1
0x00806040
000000
NVM base address
+ NVM size
NVM main address
space
NVM Base Address
Calibration and
auxiliary space
800000
NVM base address +
0x00800000
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Table 8-3. NVM User Row Mapping
8.3.2 NVM Software Calibration Area Mapping
The NVM Software Calibration Area contains calibration data that are measured and written during production test.
These calibration values should be read by the application software and written back to the corresponding register.
The NVM Software Calibration Area can be read at address 0x806020.
The NVM Software Calibration Area can not be written.
Bit Position Name Usage
2:0 BOOTPROT Used to select one of eight different bootloader sizes. Refer to “NVMCTRL –
Non-Volatile Memory Controller” on page 350. Default value = 7.
3Reserved
6:4 EEPROM Used to select one of eight different EEPROM sizes. Refer to “NVMCTRL –
Non-Volatile Memory Controller” on page 350. Default value = 7.
7Reserved
13:8 BOD33 Level BOD33 Threshold Level at power on. Refer to BOD33 register.
Default value = 7.
14 BOD33 Enable BOD33 Enable at power on . Refer to BOD33 register. Default value = 1.
16:15 BOD33 Action BOD33 Action at power on. Refer to BOD33 register. Default value = 1.
24:17 Reserved Voltage Regulator Internal BOD (BOD12) configuration. These bits are written
in production and must not be changed. Default value = 0x70.
25 WDT Enable WDT Enable at power on. Refer to WDT CTRL register.
Default value = 0.
26 WDT Always-On WDT Always-On at power on. Refer to WDT CTRL register.
Default value = 0.
30:27 WDT Period WDT Period at power on. Refer to WDT CONFIG register.
Default value = 0x0B.
34:31 WDT Window WDT Window mode time-out at power on. Refer to WDT CONFIG register.
Default value = 0x05.
38:35 WDT EWOFFSET WDT Early Warning Interrupt Time Offset at power on. Refer to WDT
EWCTRL register. Default value = 0x0B.
39 WDT WEN WDT Timer Window Mode Enable at power on. Refer to WDT CTRL register.
Default value = 0.
40 BOD33 Hysteresis BOD33 Hysteresis configuration at power on. Refer to BOD33 register.
Default value = 0.
41 Reserved Voltage Regulator Internal BOD(BOD12) configuration. This bit is written in
production and must not be changed. Default value = 0.
47:42 Reserved
63:48 LOCK
NVM Region Lock Bits. Refer to “NVMCTRL – Non-Volatile Memory
Controller” on page 350.
Default value = 0xFFFF.
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Table 8-4. NVM Software Calibration Area Mapping
8.3.3 Serial Number
Each device has a unique 128-bit serial number which is a concatenation of four 32-bit words contained at the following
addresses:
Word 0: 0x0080A00C
Word 1: 0x0080A040
Word 2: 0x0080A044
Word 3: 0x0080A048
The uniqueness of the serial number is guaranteed only when using all 128 bits.
Bit Position Name Description
2:0 Reserved
14:3 Reserved
26:15 Reserved
34:27 ADC LINEARITY ADC Linearity Calibration. Should be written to CALIB register.
37:35 ADC BIASCAL ADC Bias Calibration. Should be written to CALIB register.
44:38 OSC32K CAL OSC32KCalibration. Should be written to OSC32K register.
49:45 USB TRANSN USB TRANSN calibration value. Should be written to PADCAL register.
54:50 USB TRANSP USB TRANSP calibration value. Should be written to PADCAL register.
57:55 USB TRIM USB TRIM calibration value. Should be written to the PADCAL register.
63:58 DFLL48M COARSE CAL DFLL48M Coarse calibration value. Should be written to DFLLVAL register.
73:64 DFLL48M FINE CAL DFLL48M Fine calibration value. Should be written to DFLLVAL register.
127:74 Reserved
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9. Processor And Architecture
9.1 Cortex M0+ Processor
The Atmel | SMART SAM R21 implements the ARM® Cortex™-M0+ processor, based on the ARMv6 Architecture and
Thumb®-2 ISA. The Cortex M0+ is 100% instruction set compatible with its predecessor, the Cortex-M0 core, and
upward compatible to Cortex-M3 and M4 cores. The ARM Cortex-M0+ implemented is revision r0p1. For more
information refer to www.arm.com.
9.1.1 Cortex M0+ Configuration
Note: 1. All software run in privileged mode only.
The ARM Cortex-M0+ core has two bus interfaces:
zSingle 32-bit AMBA-3 AHB-Lite system interface that provides connections to peripherals and all system
memory, which includes flash and RAM.
zSingle 32-bit I/O port bus interfacing to the PORT with 1-cycle loads and stores.
9.1.2 Cortex-M0+ Peripherals
zSystem Control Space (SCS)
zThe processor provides debug through registers in the SCS. Refer to the Cortex-M0+ Technical Reference
Manual for details (www.arm.com).
zSystem Timer (SysTick)
zThe System Timer is a 24-bit timer that extends the functionality of both the processor and the NVIC. Refer
to the Cortex-M0+ Technical Reference Manual for details (www.arm.com).
Table 9-1. Cortex M0+ Configuration
Features Configurable option
Atmel | SMART SAM R21
configuration
Interrupts External interrupts 0-32 28
Data endianness Little-endian or big-endian Little-endian
SysTick timer Present or absent Present
Number of watchpoint comparators 0, 1, 2 2
Number of breakpoint comparators 0, 1, 2, 3, 4 4
Halting debug support Present or absent Present
Multiplier Fast or small Fast (single cycle)
Single-cycle I/O port Present or absent Present
Wake-up interrupt controller Supported or not supported Not supported
Vector Table Offset Register Present or absent Present
Unprivileged/Privileged support Present or absent Absent(1)
Memory Protection Unit Not present or 8-region Not present
Reset all registers Present or absent Absent
Instruction fetch width 16-bit only or mostly 32-bit 32-bit
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zNested Vectored Interrupt Controller (NVIC)
zExternal interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts. Software can set the
priority of each interrupt. The NVIC and the Cortex-M0+ processor core are closely coupled, providing low
latency interrupt processing and efficient processing of late arriving interrupts. Refer to “Nested Vector
Interrupt Controller” on page 29 and the Cortex-M0+ Technical Reference Manual for details
(www.arm.com).
zSystem Control Block (SCB)
zThe System Control Block provides system implementation information, and system control. This includes
configuration, control, and reporting of the system exceptions. Refer to the Cortex-M0+ Devices Generic
User Guide for details (www.arm.com).
zMicro Trace Buffer (MTB)
zThe CoreSight MTB-M0+ (MTB) provides a simple execution trace capability to the Cortex-M0+ processor.
Refer to section “Micro Trace Buffer” on page 31 and the CoreSight MTB-M0+ Technical Reference Manual
for details (www.arm.com).
9.1.3 Cortex-M0+ Address Map
Table 9-2. Cortex-M0+ Address Map
9.1.4 I/O Interface
9.1.4.1 Overview
Because accesses to the AMBA® AHB-Lite™ and the single cycle I/O interface can be made concurrently, the Cortex-
M0+ processor can fetch the next instructions while accessing the I/Os. This enables single cycle I/O accesses to be
sustained for as long as needed. Refer to “CPU Local Bus” on page 375 for more information.
9.1.4.2 Description
Direct access to PORT registers.
9.2 Nested Vector Interrupt Controller
9.2.1 Overview
The Nested Vectored Interrupt Controller (NVIC) in the SAM R21 supports 32 interrupt lines with four different priority
levels. For more details, refer to the Cortex-M0+ Technical Reference Manual (www.arm.com).
9.2.2 Interrupt Line Mapping
Each of the 28 interrupt lines is connected to one peripheral instance, as shown in the table below. Each peripheral can
have one or more interrupt flags, located in the peripheral’s Interrupt Flag Status and Clear (INTFLAG) register. The
interrupt flag is set when the interrupt condition occurs. Each interrupt in the peripheral can be individually enabled by
writing a one to the corresponding bit in the peripheral’s Interrupt Enable Set (INTENSET) register, and disabled by
Address Peripheral
0xE000E000 System Control Space (SCS)
0xE000E010 System Timer (SysTick)
0xE000E100 Nested Vectored Interrupt Controller (NVIC)
0xE000ED00 System Control Block (SCB)
0x41006000 (see also “Product Mapping” on page 23)Micro Trace Buffer (MTB)
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writing a one to the corresponding bit in the peripheral’s Interrupt Enable Clear (INTENCLR) register. An interrupt request
is generated from the peripheral when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt
requests for one peripheral are ORed together on system level, generating one interrupt request for each peripheral. An
interrupt request will set the corresponding interrupt pending bit in the NVIC interrupt pending registers
(SETPEND/CLRPEND bits in ISPR/ICPR). For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt
enable register (SETENA/CLRENA bits in ISER/ICER). The NVIC interrupt priority registers IPR0-IPR7 provide a priority
field for each interrupt.
Table 9-3. Interrupt Line Mapping
Peripheral Source NVIC Line
EIC NMI – External Interrupt Controller NMI
PM – Power Manager 0
SYSCTRL – System Control 1
WDT – Watchdog Timer 2
RTC – Real Time Counter 3
EIC – External Interrupt Controller 4
NVMCTRL – Non-Volatile Memory Controller 5
DMAC - Direct Memory Access Controller 6
USB - Universal Serial Bus 7
EVSYS – Event System 8
SERCOM0 – Serial Communication Interface 0 9
SERCOM1 – Serial Communication Interface 1 10
SERCOM2 – Serial Communication Interface 2 11
SERCOM3 – Serial Communication Interface 3 12
SERCOM4 – Serial Communication Interface 4 13
SERCOM5 – Serial Communication Interface 5 14
TCC0 – Timer Counter for Control 0 15
TCC1 – Timer Counter for Control 1 16
TCC2 – Timer Counter for Control 2 17
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9.3 Micro Trace Buffer
9.3.1 Features
zProgram flow tracing for the Cortex-M0+ processor
zMTB SRAM can be used for both trace and general purpose storage by the processor
zThe position and size of the trace buffer in SRAM is configurable by software
zCoreSight compliant
9.3.2 Overview
When enabled, the MTB records changes in program flow, reported by the Cortex-M0+ processor over the execution
trace interface shared between the Cortex-M0+ processor and the CoreSight MTB-M0+. This information is stored as
trace packets in the SRAM by the MTB. An off-chip debugger can extract the trace information using the Debug Access
Port to read the trace information from the SRAM. The debugger can then reconstruct the program flow from this
information.
The MTB simultaneously stores trace information into the SRAM, and gives the processor access to the SRAM. The
MTB ensures that trace write accesses have priority over processor accesses.
The execution trace packet consists of a pair of 32-bit words that the MTB generates when it detects the processor PC
value changes non-sequentially. A non-sequential PC change can occur during branch instructions or during exception
entry. See the CoreSight MTB-M0+ Technical Reference Manual for more details on the MTB execution trace packet
format.
Tracing is enabled when the MASTER.EN bit in the Master Trace Control Register is 1. There are various ways to set the
bit to 1 to start tracing, or to 0 to stop tracing. See the CoreSight Cortex-M0+ Technical Reference Manual for more
details on the Trace start and stop and for a detailed description of the MTB’s MASTER register. The MTB can be
programmed to stop tracing automatically when the memory fills to a specified watermark level or to start or stop tracing
by writing directly to the MASTER.EN bit. If the watermark mechanism is not being used and the trace buffer overflows,
then the buffer wraps around overwriting previous trace packets.
The base address of the MTB registers is 0x41006000; this address is also written in the CoreSight ROM Table. The
offset of each register from the base address is fixed and as defined by the CoreSight MTB-M0+ Technical Reference
Manual. The MTB has 4 programmable registers to control the behavior of the trace features:
TC3 – Timer Counter 3 18
TC4 – Timer Counter 4 19
TC5 – Timer Counter 5 20
Reserved 21
Reserved 22
ADC – Analog-to-Digital Converter 23
AC – Analog Comparator 24
Reserved 25
PTC – Peripheral Touch Controller 26
Reserved 27
Table 9-3. Interrupt Line Mapping (Continued)
Peripheral Source NVIC Line
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zPOSITION: Contains the trace write pointer and the wrap bit,
zMASTER: Contains the main trace enable bit and other trace control fields,
zFLOW: Contains the WATERMARK address and the AUTOSTOP and AUTOHALT control bits,
zBASE: Indicates where the SRAM is located in the processor memory map. This register is provided to enable
auto discovery of the MTB SRAM location, by a debug agent.
See the CoreSight MTB-M0+ Technical Reference Manual for a detailed description of these registers.
9.4 High-Speed Bus System
9.4.1 Features
High-Speed Bus Matrix has the following features:
zSymmetric crossbar bus switch implementation
zAllows concurrent accesses from different masters to different slaves
z32-bit data bus
zOperation at a one-to-one clock frequency with the bus masters
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9.4.2 Configuration
CM0+ 0
DSU 1
High-Speed Bus SLAVES
Internal Flash
0
AHB-APB Bridge A
1
AHB-APB Bridge B
2
AHB-APB Bridge C
3
MTB
Multi-Slave
MASTERS
USB
DMAC WB
DMAC Fetch
CM0+
4
DMAC Data
DSU
6
SRAM
DSU 1
MTB
USB
DMAC WB
DMAC Fetch
Priviledged SRAM-access
MASTERS
DSU 2
DMAC Data
4
5
0123 65
SLAVE ID
SRAM PORT ID
MASTER ID
Table 9-4. Bus Matrix Masters
Bus Matrix Masters Master ID
CM0+ - Cortex M0+ Processor 0
DSU - Device Service Unit 1
DMAC - Direct Memory Access Controller / Data Access 2
Table 9-5. Bus Matrix Slaves
Bus Matrix Slaves Slave ID
Internal Flash Memory 0
AHB-APB Bridge A 1
AHB-APB Bridge B 2
AHB-APB Bridge C 3
SRAM Port 4 - CM0+ Access 4
SRAM Port 5 - DMAC Data Access 5
SRAM Port 6 - DSU Access 6
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9.4.3 SRAM Quality of Service
To ensure that masters with latency requirements get sufficient priority when accessing RAM, the different masters can
be configured to have a given priority for different type of access.
The Quality of Service (QoS) level is independently selected for each master accessing the RAM. For any access to the
RAM the RAM also receives the QoS level. The QoS levels and their corresponding bit values for the QoS level
configuration is shown in Table 9-7.
Table 9-7. Quality of Service
If a master is configured with QoS level 0x00 or 0x01 there will be minimum one cycle latency for the RAM access.
The priority order for concurrent accesses are decided by two factors. First the QoS level for the master and then a static
priority given by table nn-mm (table: SRAM port connection) where the lowest port ID has the highest static priority.
The MTB has fixed QoS level 3 and the DSU has fixed QoS level 1.
The CPU QoS level can be written/read at address 0x41007110, bits [1:0]. Its reset value is 0x0.
Refer to different master QOSCTRL registers for configuring QoS for the other masters (USB, DMAC).
Table 9-6. SRAM Port Connection
SRAM Port Connection Port ID Connection Type
MTB - Micro Trace Buffer 0Direct
USB - Universal Serial Bus 1Direct
DMAC - Direct Memory Access Controller - Write-Back Access 2Direct
DMAC - Direct Memory Access Controller - Fetch Access 3Direct
CM0+ - Cortex M0+ Processor 4Bus Matrix
DMAC - Direct Memory Access Controller - Data Access 5Bus Matrix
DSU - Device Service Unit 6Bus Matrix
Value Name Description
00 DISABLE Background (no sensitive operation)
01 LOW Sensitive Bandwidth
10 MEDIUM Sensitive Latency
11 HIGH Critical Latency
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9.5 AHB-APB Bridge
The AHB-APB bridge is an AHB slave, providing an interface between the high-speed AHB domain and the low-power
APB domain. It is used to provide access to the programmable control registers of peripherals (see “Product Mapping” on
page 23).
AHB-APB bridge is based on AMBA APB Protocol Specification V2.0 (ref. as APB4) including:
zWait state support
zError reporting
zTransaction protection
zSparse data transfer (byte, half-word and word)
Additional enhancements:
zAddress and data cycles merged into a single cycle
zSparse data transfer also apply to read access
to operate the AHB-APB bridge, the clock (CLK_HPBx_AHB) must be enabled. See “PM – Power Manager” on page 112
for details.
Figure 9-1. APB Write Access.
T0 T1 T2 T3
Addr 1
Data 1
PADDR
PWRITE
PCLK
PSEL
PENABLE
PWDATA
PREADY
T0 T1 T2 T3
Addr 1
Data 1
PADDR
PWRITE
PCLK
PSEL
PENABLE
PWDATA
PREADY
T4 T5
Wait statesNo wait states
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Figure 9-2. APB Read Access.
9.6 PAC – Peripheral Access Controller
9.6.1 Overview
There is one PAC associated with each AHB-APB bridge. The PAC can provide write protection for registers of each
peripheral connected on the same bridge.
The PAC peripheral bus clock (CLK_PACx_APB) can be enabled and disabled in the Power Manager. CLK_PAC0_APB
and CLK_PAC1_APB are enabled are reset. CLK_PAC2_APB is disabled at reset. Refer to “PM – Power Manager” on
page 112 for details. The PAC will continue to operate in any sleep mode where the selected clock source is running.
Write-protection does not apply for debugger access. When the debugger makes an access to a peripheral, write-
protection is ignored so that the debugger can update the register.
Write-protect registers allow the user to disable a selected peripheral’s write-protection without doing a read-modify-write
operation. These registers are mapped into two I/O memory locations, one for clearing and one for setting the register
bits. Writing a one to a bit in the Write Protect Clear register (WPCLR) will clear the corresponding bit in both registers
(WPCLR and WPSET) and disable the write-protection for the corresponding peripheral, while writing a one to a bit in the
Write Protect Set (WPSET) register will set the corresponding bit in both registers (WPCLR and WPSET) and enable the
write-protection for the corresponding peripheral. Both registers (WPCLR and WPSET) will return the same value when
read.
If a peripheral is write-protected, and if a write access is performed, data will not be written, and the peripheral will return
an access error (CPU exception).
The PAC also offers a safety feature for correct program execution, with a CPU exception generated on double write-
protection or double unprotection of a peripheral. If a peripheral n is write-protected and a write to one in WPSET[n] is
detected, the PAC returns an error. This can be used to ensure that the application follows the intended program flow by
always following a write-protect with an unprotect, and vice versa. However, in applications where a write-protected
peripheral is used in several contexts, e.g., interrupts, care should be taken so that either the interrupt can not happen
while the main application or other interrupt levels manipulate the write-protection status, or when the interrupt handler
needs to unprotect the peripheral, based on the current protection status, by reading WPSET.
T0 T1 T2 T3
Addr 1
Data 1
PADDR
PWRITE
PCLK
PSEL
PENABLE
PRDATA
PREADY
T0 T1 T2 T3
Addr 1
Data 1
PADDR
PWRITE
PCLK
PSEL
PENABLE
PRDATA
PREADY
T4 T5
Wait statesNo wait states
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9.6.2 Register Description
Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and
the 8-bit halves of a 16-bit register can be accessed directly.
Refer to “Product Mapping” on page 23 for PAC locations.
9.6.2.1 PAC0 Register Description
Write Protect Clear
Name: WPCLR
Offset: 0x00
Reset: 0x00000000
Property: -
zBits 31:7 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 6:1 – EIC, RTC, WDT, GCLK, SYSCTRL, PM: Write Protect Disable
0: Write-protection is disabled.
1: Write-protection is enabled.
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bits for the corresponding peripherals.
zBit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
Bit3130292827262524
AccessRRRRRRRR
Reset00000000
Bit2322212019181716
AccessRRRRRRRR
Reset00000000
Bit151413121110 9 8
AccessRRRRRRRR
Reset00000000
Bit76543210
EIC RTC WDT GCLK SYSCTRL PM
Access R R/W R/W R/W R/W R/W R/W R
Reset00000000
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Write Protect Set
Name: WPSET
Offset: 0x04
Reset: 0x00000000
Property: -
zBits 31:7 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 6:1 – EIC, RTC, WDT, GCLK, SYSCTRL, PM: Write Protect Enable
0: Write-protection is disabled.
1: Write-protection is enabled.
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write Protect bit for the corresponding peripherals.
zBit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
AccessRRRRRRRR
Reset00000000
Bit 15 14 13 12 11 10 9 8
AccessRRRRRRRR
Reset00000000
Bit76543210
EIC RTC WDT GCLK SYSCTRL PM
Access R R/W R/W R/W R/W R/W R/W R
Reset00000000
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9.6.2.2 PAC1 Register Description
Write Protect Clear
Name: WPCLR
Offset: 0x00
Reset: 0x00000002
Property: -
zBits 31:7 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 6:1 – MTB, USB, DMAC, PORT, NVMCTRL, DSU: Write Protect
0: Write-protection is disabled.
1: Write-protection is enabled.
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
zBit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
Bit3130292827262524
AccessRRRRRRRR
Reset00000000
Bit2322212019181716
AccessRRRRRRRR
Reset00000000
Bit151413121110 9 8
AccessRRRRRRRR
Reset00000000
Bit76543210
MTB USB DMAC PORT NVMCTRL DSU
Access R R/W R/W R/W R/W R/W R/W R
Reset00000010
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Write Protect Set
Name: WPSET
Offset: 0x04
Reset: 0x00000002
Property: -
zBits 31:7 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 6:1 – MTB, USB, DMAC, PORT, NVMCTRL, DSU: Write Protect
0: Write-protection is disabled.
1: Write-protection is enabled.
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write Protect bit for the corresponding peripherals.
zBit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
AccessRRRRRRRR
Reset00000000
Bit 15 14 13 12 11 10 9 8
AccessRRRRRRRR
Reset00000000
Bit76543210
MTB USB DMAC PORT NVMCTRL DSU
Access R R/W R/W R/W R/W R/W R/W R
Reset00000010
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9.6.2.3 PAC2 Register Description
Write Protect Clear
Name: WPCLR
Offset: 0x00
Reset: 0x00800000
Property: -
zBits 31:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
reset value when this register is written. These bits will always return reset value when read.
zBits 21,19,17:16,13:1 – RFCTRL, PTC, AC, ADC, TC5, TC4, TC3, TCC2, TCC1, TCC0, SERCOM5, SERCOM4,
SERCOM3, SERCOM2, SERCOM1, SERCOM0, EVSYS: Write Protect
0: Write-protection is disabled.
1: Write-protection is enabled.
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
zBit 18,15,14,0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
Bit3130292827262524
AccessRRRRRRRR
Reset00000000
Bit2322212019181716
RFCTRL PTC AC ADC
Access R R R/W R R/W R R/W R/W
Reset10000000
Bit151413121110 9 8
TC5 TC4 TC3 TCC2 TCC1 TCC0
Access R R R/W R/W R/W R/W R/W R/W
Reset00000000
Bit76543210
SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS
Access R/W R/W R/W R/W R/W R/W R/W R
Reset00000000
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Write Protect Set
Name: WPSET
Offset: 0x04
Reset: 0x00800000
Property: -
zBits 31:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
reset value when this register is written. These bits will always return reset value when read.
zBits 21,19,17:16,13:1 – RFCTRL, PTC, AC, ADC, TC5, TC4, TC3, TCC2, TCC1, TCC0, SERCOM5, SERCOM4,
SERCOM3, SERCOM2, SERCOM1, SERCOM0, EVSYS: Write Protect
0: Write-protection is disabled.
1: Write-protection is enabled.
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write Protect bit for the corresponding peripherals.
zBit 18,15,14,0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
Bit3130292827262524
AccessRRRRRRRR
Reset00000000
Bit2322212019181716
RFCTRL PTC AC ADC
Access R R R/W R R/W R R/W R/W
Reset10000000
Bit151413121110 9 8
TC5 TC4 TC3 TCC2 TCC1 TCC0
Access R R R/W R/W R/W R/W R/W R/W
Reset00000000
Bit76543210
SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS
Access R/W R/W R/W R/W R/W R/W R/W R
Reset00000000
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10. Peripherals Configuration Summary
Table 10-1. Peripherals Configuration Summary
Peripheral
Name
Base
Address
IRQ
Line
AHB Clock APB Clock Generic Clock PAC Events DMA
Index
Enabled
at Reset Index
Enabled
at Reset Index Index
Prot at
Reset User Generator Index SleepWalking
AHB-APB
Bridge A 0x40000000 0 Y
PAC0 0x40000000 0 Y
PM 0x40000400 0 1 Y 1 N Y
SYSCTRL 0x40000800 1 2 Y
0: DFLL48M
reference
1: FDPLL96M clk
source
2: FDPLL96M
32kHz
2 N Y
GCLK 0x40000C00 3 Y 3 N Y
WDT 0x40001000 2 4 Y 3 4 N
RTC 0x40001400 3 5 Y 4 5 N
1: CMP0/ALARM0
2: CMP1
3: OVF
4-11: PER0-7
Y
EIC 0x40001800 NMI,
46 Y 5 6 N 12-27: EXTINT0-15 Y
AHB-APB
Bridge B 0x41000000 1 Y
PAC1 0x41000000 0 Y
DSU 0x41002000 3 Y 1 Y 1 Y
NVMCTRL 0x41004000 5 4 Y 2 Y 2 N
PORT 0x41004400 3 Y 3 N
DMAC 0x41004800 6 5 Y 4 Y 4 N 0-3: CH0-3 30-33: CH0-3
USB 0x41005000 7 6 Y 5 Y 6 5 N Y
MTB 0x41006000 6 N
AHB-APB
Bridge C 0x42000000 2 Y
PAC2 0x42000000 0 N
EVSYS 0x42000400 8 1 N 7-18: one per
CHANNEL 1 N Y
SERCOM0 0x42000800 9 2 N 20: CORE
19: SLOW 2 N 1: RX
2: TX Y
SERCOM1 0x42000C00 10 3 N 21: CORE
19: SLOW 3 N 3: RX
4: TX Y
SERCOM2 0x42001000 11 4 N 22: CORE
19: SLOW 4 N 5: RX
6: TX Y
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SERCOM3 0x42001400 12 5 N 23: CORE
19: SLOW 5 N 7: RX
8: TX Y
SERCOM4 0x42001800 13 6 N 24: CORE
19: SLOW 6 N 9: RX
10: TX Y
SERCOM5 0x42001C00 14 7 N 25: CORE
19: SLOW 7 N 11: RX
12: TX Y
TCC0 0x42002000 15 8 N 26 8 N 4-5: EV0-1
6-9: MC0-3
34: OVF
35: TRG
36: CNT
37-40: MC0-3
13: OVF
14-17: MC0-3 Y
TCC1 0x42002400 16 9 N 26 9 N 10-11: EV0-1
12-13: MC0-1
41: OVF
42: TRG
43: CNT
44-45: MC0-1
18: OVF
19-20: MC0-1 Y
TCC2 0x42002800 17 10 N27 10 N14-15: EV0-1
16-17: MC0-1
46: OVF
47: TRG
48: CNT
49-50: MC0-1
21: OVF
22-23: MC0-1 Y
TC3 0x42002C00 18 11 N27 11 N18: EV 51: OVF
52-53: MC0-1
24: OVF
25-26: MC0-1 Y
TC4 0x42003000 19 12 N28 12 N19: EV 54: OVF
55-56: MCX0-1
27: OVF
28-29: MC0-1 Y
TC5 0x42003400 20 13 N28 13 N20: EV 57: OVF
58-59: MC0-1
30: OVF
31-32: MC0-1 Y
ADC 0x42004000 23 16 Y30 16 N23: START
24: SYNC
66: RESRDY
67: WINMON 39: RESRDY Y
AC 0x42004400 24 17 N31: DIG
32: ANA 17 N25-26: SOC0-1 68-69: COMP0-1
70: WIN0 Y
PTC 0x42004C00 26 19 N34 19 N28: STCONV 72: EOC
73: WCOMP
RFCTRL 0x42005400 21 N21 N
Table 10-1. Peripherals Configuration Summary
Peripheral
Name
Base
Address
IRQ
Line
AHB Clock APB Clock Generic Clock PAC Events DMA
Index
Enabled
at Reset Index
Enabled
at Reset Index Index
Prot at
Reset User Generator Index SleepWalking
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11. DSU – Device Service Unit
11.1 Overview
The Device Service Unit (DSU) provides a means to detect debugger probes. This enables the ARM Debug Access Port
(DAP) to have control over multiplexed debug pads and CPU reset. The DSU also provides system-level services to
debug adapters in an ARM debug system. It implements a CoreSight Debug ROM that provides device identification as
well as identification of other debug components in the system. Hence, it complies with the ARM Peripheral Identification
specification. The DSU also provides system services to applications that need memory testing, as required for
IEC60730 Class B compliance, for example. The DSU can be accessed simultaneously by a debugger and the CPU, as
it is connected on the High-Speed Bus Matrix. For security reasons, some of the DSU features will be limited or
unavailable when the device is protected by the NVMCTRL security bit (refer to “Security Bit” on page 356).
11.2 Features
zCPU reset extension
zDebugger probe detection (Cold- and Hot-Plugging)
zChip-Erase command and status
z32-bit cyclic redundancy check (CRC32) of any memory accessible through the bus matrix
zARM® CoreSight™ compliant device identification
zTwo debug communications channels
zDebug access port security filter
zOnboard memory built-in self-test (MBIST)
11.3 Block Diagram
Figure 11-1. DSU Bock Diagram
D
SU
S
W
C
LK
CO
RE
S
I
G
HT R
OM
DAP
S
E
CU
RITY FILTER
C
RC-32
MBI
ST
C
HIP ERAS
E
R
E
S
ET
c
pu_reset_extens
i
o
n
CP
U
D
AP
S
WDI
O
NVM
C
TRL
DB
G
M
HIGH-SPEED
HIGH-
SPEE
BUS MATRIX
MATR
US M
M
S
d
e
b
ugger_presen
t
D
E
B
U
G
G
E
R
P
R
O
B
E
INTERFA
C
E
A
HB-A
P
PORT
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11.4 Signal Description
Refer to “I/O Multiplexing and Considerations” on page 12 for details on the pin mapping for this peripheral.
11.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
11.5.1 I/O Lines
The SWCLK pin is by default assigned to the DSU module to allow debugger probe detection and the condition to stretch
the CPU reset phase. For more information, refer to “Debugger Probe Detection” on page 47. The Hot-Plugging feature
depends on the PORT configuration. If the SWCLK pin function is changed in the PORT or if the PORT_MUX is disabled,
the Hot-Plugging feature is disabled until a power-reset or an external reset.
11.5.2 Power Management
The DSU will continue to operate in any sleep mode where the selected source clock is running.
Refer to “PM – Power Manager” on page 112 for details on the different sleep modes.
11.5.3 Clocks
The DSU bus clocks (CLK_DSU_APB and CLK_DSU_AHB) can be enabled and disabled in the Power Manager. For
more information on the CLK_DSU_APB and CLK_DSU_AHB clock masks, refer to “PM – Power Manager” on page
112.
11.5.4 DMA
Not applicable.
11.5.5 Interrupts
Not applicable.
11.5.6 Events
Not applicable.
11.5.7 Register Access Protection
All registers with write access are optionally write-protected by the Peripheral Access Controller (PAC), except the
following registers:
zDebug Communication Channel 0 register (DCC0)
zDebug Communication Channel 1 register (DCC1)
Write-protection is denoted by the Write-Protection property in the register description.
Write-protection does not apply for accesses through an external debugger. Refer to “PAC – Peripheral Access
Controller” on page 36 for details.
Signal Name Type Description
RESET Digital Input External reset
SWCLK Digital Input SW clock
SWDIO Digital I/O SW bidirectional data pin
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11.5.8 Analog Connections
Not applicable.
11.6 Debug Operation
11.6.1 Principle of Operation
The DSU provides basic services to allow on-chip debug using the ARM Debug Access Port and the ARM processor
debug resources:
zCPU reset extension
zDebugger probe detection
For more details on the ARM debug components, refer to the ARM Debug Interface v5Architecture Specification.
11.6.2 CPU Reset Extension
“CPU reset extension” refers to the extension of the reset phase of the CPU core after the external reset is released. This
ensures that the CPU is not executing code at startup while a debugger connects to the system. It is detected on a
RESET release event when SWCLK is low. At startup, SWCLK is internally pulled up to avoid false detection of a
debugger if SWCLK is left unconnected. When the CPU is held in the reset extension phase, the CPU Reset Extension
bit (CRSTEXT) of the Status A register (STATUSA.CRSTEXT) is set. To release the CPU, write a one to
STATUSA.CRSTEXT. STATUSA.CRSTEXT will then be set to zero. Writing a zero to STATUSA.CRSTEXT has no
effect. For security reasons, it is not possible to release the CPU reset extension when the device is protected by the
NVMCTRL security bit (refer to “Security Bit” on page 356). Trying to do so sets the Protection Error bit (PERR) of the
Status A register (STATUSA.PERR).
Figure 11-2. Typical CPU Reset Extension Set and Clear Timing Diagram
11.6.3 Debugger Probe Detection
11.6.3.1 Cold-Plugging
Cold-Plugging is the detection of a debugger when the system is in reset. Cold-Plugging is detected when the CPU reset
extension is requested, as described above.
11.6.3.2 Hot-Plugging
Hot-Plugging is the detection of a debugger probe when the system is not in reset. Hot-Plugging is not possible under
reset because the detector is reset when POR or RESET are asserted. Hot-Plugging is active when a SWCLK falling
edge is detected. The SWCLK pad is multiplexed with other functions and the user must ensure that its default function is
assigned to the debug system. If the SWCLK function is changed, the Hot-Plugging feature is disabled until a power-
DSU CRSTEXT
Clear
SWCLK
CPU reset
extension
CPU_STATE reset running
RE
S
E
T
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reset or external reset occurs. Availability of the Hot-Plugging feature can be read from the Hot-Plugging Enable bit of the
Status B register (STATUSB.HPE).
Figure 11-3. Hot-Plugging Detection Timing Diagram
The presence of a debugger probe is detected when either Hot-Plugging or Cold-Plugging is detected. Once detected,
the Debugger Present bit of the Status B register (STATUSB.DBGPRES) is set. For security reasons, Hot-Plugging is not
available when the device is protected by the NVMCTRL security bit (refer to “Security Bit” on page 356).
This detection requires that pads are correctly powered. Thus, at cold startup, this detection cannot be done until POR is
released. If the device is protected, Cold-Plugging is the only way to detect a debugger probe, and so the external reset
timing must be longer than the POR timing. If external reset is deasserted before POR release, the user must retry the
procedure above until it gets connected to the device.
11.7 Chip-Erase
Chip-Erase consists of removing all sensitive information stored in the chip and clearing the NVMCTRL security bit (refer
to “Security Bit” on page 356). Hence, all volatile memories and the flash array (including the EEPROM emulation area)
will be erased. The flash auxiliary rows, including the user row, will not be erased. When the device is protected, the
debugger must reset the device in order to be detected. This ensures that internal registers are reset after the protected
state is removed. The Chip-Erase operation is triggered by writing a one to the Chip-Erase bit in the Control register
(CTRL.CE). This command will be discarded if the DSU is protected by the Peripheral Access Controller (PAC). Once
issued, the module clears volatile memories prior to erasing the flash array. To ensure that the Chip-Erase operation is
completed, check the Done bit of the Status A register (STATUSA.DONE). The Chip-Erase operation depends on clocks
and power management features that can be altered by the CPU. For that reason, it is recommended to issue a Chip-
Erase after a Cold-Plugging procedure to ensure that the device is in a known and safe state.
The recommended sequence is as follows:
1. Issue the Cold-Plugging procedure (refer to “Cold-Plugging” on page 47). The device then:
1. Detects the debugger probe
2. Holds the CPU in reset
2. Issue the Chip-Erase command by writing a one to CTRL.CE. The device then:
1. Clears the system volatile memories
2. Erases the whole flash array (including the EEPROM emulation area, not including auxiliary rows)
3. Erases the lock row, removing the NVMCTRL security bit protection
3. Check for completion by polling STATUSA.DONE (read as one when completed).
4. Reset the device to let the NVMCTRL update fuses.
11.8 Programming
Programming of the flash or RAM memories is available when the device is not protected by the NVMCTRL security bit
(refer to “Security Bit” on page 356).
SWCLK
Hot-Plugging
CPU_STATE
reset running
R
ESET
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1. At power up, RESET is driven low by a debugger. The on-chip regulator holds the system in a POR state until the
input supply is above the POR threshold (refer to “Power-On Reset (POR) Characteristics” on page 1069). The
system continues to be held in this static state until the internally regulated supplies have reached a safe operating
state.
2. The PM starts, clocks are switched to the slow clock (Core Clock, System Clock, Flash Clock and any Bus Clocks
that do not have clock gate control). Internal resets are maintained due to the external reset.
3. The debugger maintains a low level on SWCLK. Releasing RESET results in a debugger Cold-Plugging
procedure.
4. The debugger generates a clock signal on the SWCLK pin, the Debug Access Port (DAP) receives a clock.
5. The CPU remains in reset due to the Cold-Plugging procedure; meanwhile, the rest of the system is released.
6. A Chip-Erase is issued to ensure that the flash is fully erased prior to programming.
7. Programming is available through the AHB-AP.
8. After operation is completed, the chip can be restarted either by asserting RESET, toggling power or writing a one
to the Status A register CPU Reset Phase Extension bit (STATUSA.CRSTEXT). Make sure that the SWCLK pin is
high when releasing RESET to prevent extending the CPU reset.
11.9 Intellectual Property Protection
Intellectual property protection consists of restricting access to internal memories from external tools when the device is
protected, and is accomplished by setting the NVMCTRL security bit (refer to “Security Bit” on page 356). This protected
state can be removed by issuing a Chip-Erase (refer to “Chip-Erase” on page 48). When the device is protected,
read/write accesses using the AHB-AP are limited to the DSU address range and DSU commands are restricted.
The DSU implements a security filter that monitors the AHB transactions generated by the ARM AHB-AP inside the DAP.
If the device is protected, then AHB-AP read/write accesses outside the DSU external address range are discarded,
causing an error response that sets the ARM AHB-AP sticky error bits (refer to the ARM Debug Interface v5 Architecture
Specification on http://www.arm.com).
The DSU is intended to be accessed either:
zInternally from the CPU, without any limitation, even when the device is protected
zExternally from a debug adapter, with some restrictions when the device is protected
For security reasons, DSU features have limitations when used from a debug adapter. To differentiate external accesses
from internal ones, the first 0x100 bytes of the DSU register map have been replicated at offset 0x100:
zThe first 0x100 bytes form the internal address range
zThe next 0x100 bytes form the external address range
When the device is protected, the DAP can only issue MEM-AP accesses in the DSU address range limited to the 0x100-
0x2000 offset range.
The DSU operating registers are located in the 0x00-0xFF area and remapped in 0x100-0x1FF to differentiate accesses
coming from a debugger and the CPU. If the device is protected and an access is issued in the region 0x100-0x1FF, it is
subject to security restrictions. For more information, refer to Table 11-1.
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Some features not activated by APB transactions are not available when the device is protected:
11.10 Device Identification
Device identification relies on the ARM CoreSight component identification scheme, which allows the chip to be identified
as an ATMEL device implementing a DSU. The DSU contains identification registers to differentiate the device.
11.10.1 CoreSight Identification
A system-level ARM CoreSight ROM table is present in the device to identify the vendor and the chip identification
method. Its address is provided in the MEM-AP BASE register inside the ARM Debug Access Port. The CoreSight ROM
implements a 64-bit conceptual ID composed as follows from the PID0 to PID7 CoreSight ROM Table registers:
Figure 11-5. Conceptual 64-Bit Peripheral ID
Figure 11-4. APB Memory Mapping
0x0000
DSU operating
registers
Internal address range
(cannot be accessed from debug tools when the device is
protected by the NVMCTRL security bit)
0x00FC
0x0100 Replicated
DSU operating
registers
External address range
(can be accessed from debug tools with some restrictions)
0x01FD
Empty
0x1000
DSU CoreSight
ROM
0x1FFC
Table 11-1. Feature Availability Under Protection
Features Availability When the Device is Protected
CPU reset extension Yes
Debugger Cold-Plugging Yes
Debugger Hot-Plugging No
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For more information, refer to the ARM Debug Interface Version 5 Architecture Specification.
11.10.2 DSU Chip Identification Method:
The DSU DID register identifies the device by implementing the following information:
zProcessor identification
zProduct family identification
zProduct series identification
zDevice select
11.11 Functional Description
11.11.1 Principle of Operation
The DSU provides memory services such as CRC32 or MBIST that require almost the same interface. Hence, the
Address, Length and Data registers are shared. They must be configured first; then a command can be issued by writing
the Control register. When a command is ongoing, other commands are discarded until the current operation is
completed. Hence, the user must wait for the STATUSA.DONE bit to be set prior to issuing another one.
11.11.2 Basic Operation
11.11.2.1 Initialization
The module is enabled by enabling its clocks. For more details, refer to “Clocks” on page 46. The DSU registers can be
write-protected. Refer to “PAC – Peripheral Access Controller” on page 36.
11.11.2.2 Operation from a debug adapter
Debug adapters should access the DSU registers in the external address range 0x100 – 0x2000. If the device is
protected by the NVMCTRL security bit (refer to “Security Bit” on page 356), accessing the first 0x100 bytes causes the
system to return an error (refer to “Intellectual Property Protection” on page 49).
11.11.2.3 Operation from the CPU
There are no restrictions when accessing DSU registers from the CPU. However, the user should access DSU registers
in the internal address range (0x0 – 0x100) to avoid external security restrictions (refer to “Intellectual Property
Protection” on page 49).
Table 11-2. Conceptual 64-Bit Peripheral ID Bit Descriptions
Field Size Description Location
JEP-106 CC code 4Atmel continuation code: 0x0 PID4
JEP-106 ID code 7Atmel device ID: 0x1F PID1+PID2
4KB count 4Indicates that the CoreSight component is a ROM: 0x0 PID4
RevAnd 4Not used; read as 0 PID3
CUSMOD 4Not used; read as 0 PID3
PARTNUM 12 Contains 0xCD0 to indicate that DSU is present PID0+PID1
REVISION 4
DSU revision (starts at 0x0 and increments by 1 at both major and minor
revisions). Identifies DSU identification method variants. If 0x0, this
indicates that device identification can be completed by reading the
Device Identification register (DID)
PID3
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11.11.3 32-bit Cyclic Redundancy Check (CRC32)
The DSU unit provides support for calculating a cyclic redundancy check (CRC32) value for a memory area (including
flash and AHB RAM).
When the CRC32 command is issued from:
zThe internal range, the CRC32 can be operated at any memory location
zThe external range, the CRC32 operation is restricted; DATA, ADDR and LENGTH values are forced (see below)
The algorithm employed is the industry standard CRC32 algorithm using the generator polynomial 0xEDB88320
(reversed representation).
11.11.3.1 Starting CRC32 Calculation
CRC32 calculation for a memory range is started after writing the start address into the Address register (ADDR) and the
size of the memory range into the Length register (LENGTH). Both must be word-aligned.
The initial value used for the CRC32 calculation must be written to the Data register. This value will usually be
0xFFFFFFFF, but can be, for example, the result of a previous CRC32 calculation if generating a common CRC32 of
separate memory blocks.
Once completed, the calculated CRC32 value can be read out of the Data register. The read value must be
complemented to match standard CRC32 implementations or kept non-inverted if used as starting point for subsequent
CRC32 calculations.
If the device is in protected state by the NVMCTRL security bit (refer to “Security Bit” on page 356), it is only possible to
calculate the CRC32 of the whole flash array when operated from the external address space. In most cases, this area
will be the entire onboard non-volatile memory. The Address, Length and Data registers will be forced to predefined
values once the CRC32 operation is started, and values written by the user are ignored. This allows the user to verify the
contents of a protected device.
The actual test is started by writing a one in the 32-bit Cyclic Redundancy Check bit of the Control register (CTRL.CRC).
A running CRC32 operation can be canceled by resetting the module (writing a one to CTRL.SWRST).
11.11.3.2 Interpreting the Results
The user should monitor the Status A register. When the operation is completed, STATUSA.DONE is set. Then the Bus
Error bit of the Status A register (STATUSA.BERR) must be read to ensure that no bus error occurred.
11.11.4 Debug Communication Channels
The Debug Communication Channels (DCCO and DCC1) consist of a pair of registers with associated handshake logic,
accessible by both CPU and debugger even if the device is protected by the NVMCTRL security bit (refer to “Security Bit”
on page 356). The registers can be used to exchange data between the CPU and the debugger, during run time as well
as in debug mode. This enables the user to build a custom debug protocol using only these registers. The DCC0 and
DCC1 registers are accessible when the protected state is active. When the device is protected, however, it is not
possible to connect a debugger while the CPU is running (STATUSA.CRSTEXT is not writable and the CPU is held
under reset). Dirty bits in the status registers indicate whether a new value has been written in DCC0 or DCC1. These
bits,DCC0D and DCC1D, are located in the STATUSB registers. They are automatically set on write and cleared on
Table 11-3. AMOD Bit Descriptions when Operating CRC32
AMOD[1:0] Short Name External Range Restrictions
0ARRAY CRC32 is restricted to the full flash array area (EEPROM emulation area not included)
DATA forced to 0xFFFFFFFF before calculation (no seed)
1EEPROM CRC32 of the whole EEPROM emulation area
DATA forced to 0xFFFFFFFF before calculation (no seed)
2-3 Reserved
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read. The DCC0 and DCC1 registers are shared with the onboard memory testing logic (MBIST). Accordingly, DCC0 and
DCC1 must not be used while performing MBIST operations.
11.11.5 Testing of Onboard Memories (MBIST)
The DSU implements a feature for automatic testing of memory also known as MBIST. This is primarily intended for
production test of onboard memories. MBIST cannot be operated from the external address range when the device is
protected by the NVMCTRL security bit (refer to “Security Bit” on page 356). If a MBIST command is issued when the
device is protected, a protection error is reported in the Protection Error bit in the Status A register (STATUSA.PERR).
1. Algorithm
The algorithm used for testing is a type of March algorithm called "March LR". This algorithm is able to detect a
wide range of memory defects, while still keeping a linear run time. The algorithm is:
1. Write entire memory to 0, in any order.
2. Bit for bit read 0, write 1, in descending order.
3. Bit for bit read 1, write 0, read 0, write 1, in ascending order.
4. Bit for bit read 1, write 0, in ascending order.
5. Bit for bit read 0, write 1, read 1, write 0, in ascending order.
6. Read 0 from entire memory, in ascending order.
The specific implementation used has a run time of O(14n) where n is the number of bits in the RAM. The detected
faults are:
zAddress decoder faults
zStuck-at faults
zTransition faults
zCoupling faults
zLinked Coupling faults
zStuck-open faults
2. Starting MBIST
To test a memory, you need to write the start address of the memory to the ADDR.ADDR bit group, and the size of
the memory into the Length register. See “Physical Memory Map” on page 24 to know which memories are avail-
able, and which address they are at.
For best test coverage, an entire physical memory block should be tested at once. It is possible to test only a sub-
set of a memory, but the test coverage will then be somewhat lower.
The actual test is started by writing a one to CTRL.MBIST. A running MBIST operation can be canceled by writing
a one to CTRL.SWRST.
3. Interpreting the Results
The tester should monitor the STATUSA register. When the operation is completed, STATUSA.DONE is set.
There are three different modes:
zADDR.AMOD=0: exit-on-error (default)
In this mode, the algorithm terminates either when a fault is detected or on successful completion. In both cases,
STATUSA.DONE is set. If an error was detected, STATUSA.FAIL will be set. User then can read the DATA and
ADDR registers to locate the fault. Refer to “Locating Errors” on page 53.
zADDR.AMOD=1: pause-on-error
In this mode, the MBIST algorithm is paused when an error is detected. In such a situation, only STATUSA.FAIL is
asserted. The state machine waits for user to clear STATUSA.FAIL by writing a one in STATUSA.FAIL to resume.
Prior to resuming, user can read the DATA and ADDR registers to locate the fault. Refer to “Locating Errors” on
page 53.
4. Locating Errors
If the test stops with STATUSA.FAIL set, one or more bits failed the test. The test stops at the first detected error.
The position of the failing bit can be found by reading the following registers:
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zADDR: Address of the word containing the failing bit.
zDATA: contains data to identify which bit failed, and during which phase of the test it failed. The DATA
register will in this case contains the following bit groups:
Table 11-4. DATA bits Description When MBIST Operation Returns An Error
zbit_index: contains the bit number of the failing bit
zphase: indicates which phase of the test failed and the cause of the error. See Table 11-5 on page 54.
11.11.6 System Services Availability When Accessed Externally
External access: Access performed in the DSU address offset 0x200-0x1FFF range.
Internal access: Access performed in the DSU address offset 0x0-0x100 range.
Bit3130292827262524
Bit2322212019181716
Bit151413121110 9 8
phase
Bit76543210
bit_index
Table 11-5. MBIST Operation Phases
Phase Test Actions
0Write all bits to zero. This phase cannot fail.
1Read 0, write 1, increment address
2Read 1, write 0
3Read 0, write 1, decrement address
4Read 1, write 0, decrement address
5Read 0, write 1
6Read 1, write 0, decrement address
7Read all zeros. bit_index is not used
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Table 11-6. Available Features When Operated From The External Address Range and Device is Protected
Features
Availability From The External Address Range and Device is Protected
Chip-Erase command and status Yes
CRC32 Yes, only full array or full EEPROM
CoreSight Compliant Device identification Yes
Debug communication channels Yes
Testing of onboard memories (MBIST) Yes
STATUSA.CRSTEXT clearing No (STATUSA.PERR is set when attempting to do so)
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11.12 Register Summary
Table 11-7. Register Summary
Offset Name
Bit
Pos.
0x0000 CTRL 7:0 CE MBIST CRC SWRST
0x0001 STATUSA 7:0 PERR FAIL BERR CRSTEXT DONE
0x0002 STATUSB 7:0 HPE DCCD1 DCCD0 DBGPRES PROT
0x0003 Reserved
0x0004
ADDR
7:0 ADDR[5:0]
0x0005 15:8 ADDR[13:6]
0x0006 23:16 ADDR[21:14]
0x0007 31:24 ADDR[29:22]
0x0008
LENGTH
7:0 LENGTH[5:0]
0x0009 15:8 LENGTH[13:6]
0x000A 23:16 LENGTH[21:14]
0x000B 31:24 LENGTH[29:22]
0x000C
DATA
7:0 DATA[7:0]
0x000D 15:8 DATA[15:8]
0x000E 23:16 DATA[23:16]
0x000F 31:24 DATA[31:24]
0x0010
DCC0
7:0 DATA[7:0]
0x0011 15:8 DATA[15:8]
0x0012 23:16 DATA[23:16]
0x0013 31:24 DATA[31:24]
0x0014
DCC1
7:0 DATA[7:0]
0x0015 15:8 DATA[15:8]
0x0016 23:16 DATA[23:16]
0x0017 31:24 DATA[31:24]
0x0018
DID
7:0 DEVSEL[7:0]
0x0019 15:8 DIE[3:0] REVISION[3:0]
0x001A 23:16 FAMILY SERIES[5:0]
0x001B 31:24 PROCESSOR[3:0] FAMILY[4:1]
0x001C
...
0x00FF
Reserved
0x0100
...
0x01FF
External address range:
Replicates the 0x00:0xFF address range,
Gives access to the same resources but with security restrictions when the device is protected.
This address range is the only one accessible externally (using the ARM DAP) when the device is protected.
0x0200
...
0x0FFF
Reserved
0x1000
ENTRY0
7:0 FMT EPRES
0x1001 15:8 ADDOFF[3:0]
0x1002 23:16 ADDOFF[11:4]
0x1003 31:24 ADDOFF[19:12]
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0x1004
ENTRY1
7:0 FMT EPRES
0x1005 15:8 ADDOFF[3:0]
0x1006 23:16 ADDOFF[11:4]
0x1007 31:24 ADDOFF[19:12]
0x1008
END
7:0 END[7:0]
0x1009 15:8 END[15:8]
0x100A 23:16 END[23:16]
0x100B 31:24 END[31:24]
0x100C
...
0x1FCB
Reserved
0x1FCC
MEMTYPE
7:0 SMEMP
0x1FCD 15:8
0x1FCE 23:16
0x1FCF 31:24
0x1FD0
PID4
7:0 FKBC[3:0] JEPCC[3:0]
0x1FD1 15:8
0x1FD2 23:16
0x1FD3 31:24
0x1FD4
...
0x1FDF
Reserved
0x1FE0
PID0
7:0 PARTNBL[7:0]
0x1FE1 15:8
0x1FE2 23:16
0x1FE3 31:24
0x1FE4
PID1
7:0 JEPIDCL[3:0] PARTNBH[3:0]
0x1FE5 15:8
0x1FE6 23:16
0x1FE7 31:24
0x1FE8
PID2
7:0 REVISION[3:0] JEPU JEPIDCH[2:0]
0x1FE9 15:8
0x1FEA 23:16
0x1FEB 31:24
0x1FEC
PID3
7:0 REVAND[3:0] CUSMOD[3:0]
0x1FED 15:8
0x1FEE 23:16
0x1FEF 31:24
0x1FF0
CID0
7:0 PREAMBLEB0[7:0]
0x1FF1 15:8
0x1FF2 23:16
0x1FF3 31:24
Offset Name
Bit
Pos.
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Atmel-42223G–SAM-R21_Datasheet–05/2016
0x1FF4
CID1
7:0 CCLASS[3:0] PREAMBLE[3:0]
0x1FF5 15:8
0x1FF6 23:16
0x1FF7 31:24
0x1FF8
CID2
7:0 PREAMBLEB2[7:0]
0x1FF9 15:8
0x1FFA 23:16
0x1FFB 31:24
0x1FFC
CID3
7:0 PREAMBLEB3[7:0]
0x1FFD 15:8
0x1FFE 23:16
0x1FFF 31:24
Offset Name
Bit
Pos.
59
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
11.13 Register Description
Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters
and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write protection is denoted by
the Write-Protected property in each individual register description. Refer to “Register Access Protection” on page 46 for
details.
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Atmel | SMART SAM R21 [DATASHEET]
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11.13.1 Control
Name: CTRL
Offset: 0x0000
Reset: 0x00
Property: Write-Protected
zBits 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 4 – CE: Chip Erase
Writing a zero to this bit has no effect.
Writing a one to this bit starts the Chip-Erase operation.
zBit 3 – MBIST: Memory Built-In Self-Test
Writing a zero to this bit has no effect.
Writing a one to this bit starts the memory BIST algorithm.
zBit 2 – CRC: 32-bit Cyclic Redundancy Check
Writing a zero to this bit has no effect.
Writing a one to this bit starts the cyclic redundancy check algorithm.
zBit 1 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 0 – SWRST: Software Reset
Writing a zero to this bit has no effect.
Writing a one to this bit resets the module.
Bit 76543210
CE MBIST CRC SWRST
Access R R R W W W R W
Reset00000000
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Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
11.13.2 Status A
Name: STATUSA
Offset: 0x0001
Reset: 0x00
Property: Write-Protected
zBits 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 4 – PERR: Protection Error
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Protection Error bit.
This bit is set when a command that is not allowed in protected state is issued.
zBit 3 – FAIL: Failure
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Failure bit.
This bit is set when a DSU operation failure is detected.
zBit 2 – BERR: Bus Error
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Bus Error bit.
This bit is set when a bus error is detected.
zBit 1 – CRSTEXT: CPU Reset Phase Extension
Writing a zero to this bit has no effect.
Writing a one to this bit clears the CPU Reset Phase Extension bit.
This bit is set when a debug adapter Cold-Plugging is detected, which extends the CPU reset phase.
zBit 0 – DONE: Done
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Done bit.
This bit is set when a DSU operation is completed.
Bit 76543210
PERR FAIL BERR CRSTEXT DONE
Access R R R R/W R/W R/W R/W R/W
Reset00000000
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Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
11.13.3 Status B
Name: STATUSB
Offset: 0x0002
Reset: 0x1X
Property: Write-Protected
zBits 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 4 – HPE: Hot-Plugging Enable
Writing a zero to this bit has no effect.
Writing a one to this bit has no effect.
This bit is set when Hot-Plugging is enabled.
This bit is cleared when Hot-Plugging is disabled. This is the case when the SWCLK function is changed. Only a
power-reset or a external reset can set it again.
zBits 3:2 – DCCDx [x=1..0]: Debug Communication Channel x Dirty
Writing a zero to this bit has no effect.
Writing a one to this bit has no effect.
This bit is set when DCCx is written.
This bit is cleared when DCCx is read.
zBit 1 – DBGPRES: Debugger Present
Writing a zero to this bit has no effect.
Writing a one to this bit has no effect.
This bit is set when a debugger probe is detected.
This bit is never cleared.
zBit 0 – PROT: Protected
Writing a zero to this bit has no effect.
Writing a one to this bit has no effect.
This bit is set at powerup when the device is protected.
This bit is never cleared.
Bit 76543210
HPE DCCD1 DCCD0 DBGPRES PROT
AccessRRRRRRRR
Reset000100XX
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Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
11.13.4 Address
Name: ADDR
Offset: 0x0004
Reset: 0x00000000
Property: Write-Protected
zBits 31:2 – ADDR[29:0]: Address
Initial word start address needed for memory operations.
zBits 1:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit 3130292827262524
ADDR[29:22]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
ADDR[21:14]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
ADDR[13:6]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
ADDR[5:0]
AccessR/WR/WR/WR/WR/WR/W R R
Reset00000000
64
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
11.13.5 Length
Name: LENGTH
Offset: 0x0008
Reset: 0x00000000
Property: Write-Protected
zBits 31:2 – LENGTH[29:0]: Length
Length in words needed for memory operations.
zBits 1:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit 3130292827262524
LENGTH[29:22]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
LENGTH[21:14]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
LENGTH[13:6]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
LENGTH[5:0]
AccessR/WR/WR/WR/WR/WR/W R R
Reset00000000
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Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
11.13.6 Data
Name: DATA
Offset: 0x000C
Reset: 0x00000000
Property: Write-Protected
zBits 31:0 – DATA[31:0]: Data
Memory operation initial value or result value.
Bit 3130292827262524
DATA[31:24]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
DATA[23:16]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
DATA[15:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
DATA[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
11.13.7 Debug Communication Channel n
Name: DCCn
Offset: 0x0010+n*0x4 [n=0..1]
Reset: 0x00000000
Property: -
zBits 31:0 – DATA[31:0]: Data
Data register.
Bit 3130292827262524
DATA[31:24]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
DATA[23:16]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
DATA[15:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
DATA[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
11.13.8 Device Identification
The information in this register is related to the ordering code. Refer to the “Ordering Information” on page 6 for details.
Name: DID
Offset: 0x0018
Reset: -
Property: Write-Protected
zBits 31:28 – PROCESSOR[3:0]: Processor
The value of this field defines the processor used on the device. For this device, the value of this field is 0x1, cor-
responding to the ARM Cortex-M0+ processor.
zBits 27:23 – FAMILY[4:0]: Product Family
The value of this field corresponds to the Product Family part of the ordering code. For this device, the value of this
field is 0x0, corresponding to the SAM D family of base line microcontrollers.
zBit 22 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 21:16 – SERIES[5:0]: Product Series
The value of this field corresponds to the Product Series part of the ordering code. For this device, the value of this
field is 0x01, corresponding to a product with the Cortex-M0+ processor with DMA and USB features.
zBits 15:12 – DIE[3:0]: Die Identification
Identifies the die in the family.
Bit 3130292827262524
PROCESSOR[3:0] FAMILY[4:1]
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
FAMILY SERIES[5:0]
AccessRRRRRRRR
Reset00000000
Bit 151413121110 9 8
DIE[3:0] REVISION[3:0]
AccessRRRRRRRR
Reset00000000
Bit 76543210
DEVSEL[7:0]
AccessRRRRRRRR
Reset00000000
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Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
zBits 11:8 – REVISION[3:0]: Revision
Identifies the die revision number.
zBits 7:0 – DEVSEL[7:0]: Device Select
DEVSEL is used to identify a device within a product family and product series. The value corresponds to the
Flash memory density, pin count and device variant parts of the ordering code. Refer to “Ordering Information” on
page 6 for details.
Note: 1. Serial Flash MX25V4006EWSK.
Table 11-8. Device Selection
DEVSEL Device Flash RAM Pincount
0x00 - 0x17 Reserved
0x18 SAMR21E19A 256KB+512KB(1) 32KB 32
0x19 SAMR21G18A 256KB 32KB 48
0x1A SAMR21G17A 128KB 32KB 48
0x1B SAMR21G16A 64KB 16KB 48
0x1C SAMR21E18A 256KB 32KB 32
0x1D SAMR21E17A 128K 32KB 32
0x1E SAMR21E16A 64KB 16KB 32
0x1F-0xFF Reserved
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Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
11.13.9 Coresight ROM Table Entry n
Name: ENTRYn
Offset: 0x1000+n*0x4 [n=0..1]
Reset: 0xXXXXX00X
Property: Write-Protected
zBits 31:12 – ADDOFF[19:0]: Address Offset
The base address of the component, relative to the base address of this ROM table.
zBits 11:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 1 – FMT: Format
Always read as one, indicates a 32-bit ROM table.
zBit 0 – EPRES: Entry Present
This bit indicates whether an entry is present at this location in the ROM table.
This bit is set at powerup if the device is not protected indicating that the entry is not present.
This bit is cleared at powerup if the device is not protected indicating that the entry is present.
Bit 3130292827262524
ADDOFF[19:12]
AccessRRRRRRRR
ResetXXXXXXXX
Bit 2322212019181716
ADDOFF[11:4]
AccessRRRRRRRR
ResetXXXXXXXX
Bit 151413121110 9 8
ADDOFF[3:0]
AccessRRRRRRRR
ResetXXXX0000
Bit 76543210
FMT EPRES
AccessRRRRRRRR
Reset0000001X
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11.13.10Coresight ROM Table End
Name: END
Offset: 0x1008
Reset: 0x00000000
Property: -
zBits 31:0 – END[31:0]: End Marker
Indicates the end of the CoreSight ROM table entries.
Bit 3130292827262524
END[31:24]
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
END[23:16]
AccessRRRRRRRR
Reset00000000
Bit 151413121110 9 8
END[15:8]
AccessRRRRRRRR
Reset00000000
Bit 76543210
END[7:0]
AccessRRRRRRRR
Reset00000000
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Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
11.13.11Coresight ROM Table Memory Type
Name: MEMTYPE
Offset: 0x1FCC
Reset: 0x0000000X
Property: -
zBits 31:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 0 – SMEMP: System Memory Present
This bit indicates whether system memory is present on the bus that connects to the ROM table.
This bit is set at powerup if the device is not protected indicating that the system memory is accessible from a
debug adapter.
This bit is cleared at powerup if the device is protected indicating that the system memory is not accessible from a
debug adapter.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
AccessRRRRRRRR
Reset00000000
Bit 151413121110 9 8
AccessRRRRRRRR
Reset00000000
Bit 76543210
SMEMP
AccessRRRRRRRR
Reset0000000X
72
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
11.13.12Peripheral Identification 4
Name: PID4
Offset: 0x1FD0
Reset: 0x00000000
Property: -
zBits 31:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 7:4 – FKBC[3:0]: 4KB Count
These bits will always return zero when read, indicating that this debug component occupies one 4KB block.
zBits 3:0 – JEPCC[3:0]: JEP-106 Continuation Code
These bits will always return zero when read, indicating a Atmel device.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
AccessRRRRRRRR
Reset00000000
Bit 151413121110 9 8
AccessRRRRRRRR
Reset00000000
Bit 76543210
FKBC[3:0] JEPCC[3:0]
AccessRRRRRRRR
Reset00000000
73
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
11.13.13Peripheral Identification 0
Name: PID0
Offset: 0x1FE0
Reset: 0x000000D0
Property: -
zBits 31:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 7:0 – PARTNBL[7:0]: Part Number Low
These bits will always return 0xD0 when read, indicating that this device implements a DSU module instance.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
AccessRRRRRRRR
Reset00000000
Bit 151413121110 9 8
AccessRRRRRRRR
Reset00000000
Bit 76543210
PARTNBL[7:0]
AccessRRRRRRRR
Reset11010000
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Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
11.13.14Peripheral Identification 1
Name: PID1
Offset: 0x1FE4
Reset: 0x000000FC
Property: -
zBits 31:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 7:4 – JEPIDCL[3:0]: Low part of the JEP-106 Identity Code
These bits will always return 0xF when read, indicating a Atmel device (Atmel JEP-106 identity code is 0x1F).
zBits 3:0 – PARTNBH[3:0]: Part Number High
These bits will always return 0xC when read, indicating that this device implements a DSU module instance.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
AccessRRRRRRRR
Reset00000000
Bit 151413121110 9 8
AccessRRRRRRRR
Reset00000000
Bit 76543210
JEPIDCL[3:0] PARTNBH[3:0]
AccessRRRRRRRR
Reset11111100
75
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
11.13.15Peripheral Identification 2
Name: PID2
Offset: 0x1FE8
Reset: 0x00000009
Property: -
zBits 31:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 7:4 – REVISION[3:0]: Revision Number
Revision of the peripheral. Starts at 0x0 and increments by one at both major and minor revisions.
zBit 3 – JEPU: JEP-106 Identity Code is used
This bit will always return one when read, indicating that JEP-106 code is used.
zBits 2:0 – JEPIDCH[2:0]: JEP-106 Identity Code High
These bits will always return 0x1 when read, indicating an Atmel device (Atmel JEP-106 identity code is 0x1F).
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
AccessRRRRRRRR
Reset00000000
Bit 151413121110 9 8
AccessRRRRRRRR
Reset00000000
Bit 76543210
REVISION[3:0] JEPU JEPIDCH[2:0]
AccessRRRRRRRR
Reset00001001
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Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
11.13.16Peripheral Identification 3
Name: PID3
Offset: 0x1FEC
Reset: 0x00000000
Property: -
zBits 31:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 7:4 – REVAND[3:0]: Revision Number
These bits will always return 0x0 when read.
zBits 3:0 – CUSMOD[3:0]: ARM CUSMOD
These bits will always return 0x0 when read.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
AccessRRRRRRRR
Reset00000000
Bit 151413121110 9 8
AccessRRRRRRRR
Reset00000000
Bit 76543210
REVAND[3:0] CUSMOD[3:0]
AccessRRRRRRRR
Reset00000000
77
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
11.13.17Component Identification 0
Name: CID0
Offset: 0x1FF0
Reset: 0x0000000D
Property: -
zBits 31:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 7:0 – PREAMBLEB0[7:0]: Preamble Byte 0
These bits will always return 0xD when read.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
AccessRRRRRRRR
Reset00000000
Bit 151413121110 9 8
AccessRRRRRRRR
Reset00000000
Bit 76543210
PREAMBLEB0[7:0]
AccessRRRRRRRR
Reset00001101
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Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
11.13.18Component Identification 1
Name: CID1
Offset: 0x1FF4
Reset: 0x00000010
Property: -
zBits 31:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 7:4 – CCLASS[3:0]: Component Class
These bits will always return 0x1 when read indicating that this ARM CoreSight component is ROM table (refer to
the ARM Debug Interface v5 Architecture Specification at http://www.arm.com).
zBits 3:0 – PREAMBLE[3:0]: Preamble
These bits will always return 0x0 when read.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
AccessRRRRRRRR
Reset00000000
Bit 151413121110 9 8
AccessRRRRRRRR
Reset00000000
Bit 76543210
CCLASS[3:0] PREAMBLE[3:0]
AccessRRRRRRRR
Reset00010000
79
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
11.13.19Component Identification 2
Name: CID2
Offset: 0x1FF8
Reset: 0x00000005
Property: -
zBits 31:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 7:0 – PREAMBLEB2[7:0]: Preamble Byte 2
These bits will always return 0x05 when read.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
AccessRRRRRRRR
Reset00000000
Bit 151413121110 9 8
AccessRRRRRRRR
Reset00000000
Bit 76543210
PREAMBLEB2[7:0]
AccessRRRRRRRR
Reset00000101
80
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
11.13.20Component Identification 3
Name: CID3
Offset: 0x1FFC
Reset: 0x000000B1
Property: -
zBits 31:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 7:0 – PREAMBLEB3[7:0]: Preamble Byte 3
These bits will always return 0xB1 when read.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
AccessRRRRRRRR
Reset00000000
Bit 151413121110 9 8
AccessRRRRRRRR
Reset00000000
Bit 76543210
PREAMBLEB3[7:0]
AccessRRRRRRRR
Reset10110001
81
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
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Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
12. Clock System
This chapter only aims to summarize the clock distribution and terminology in the SAM R21 device. It will not explain
every detail of its configuration. For in-depth documentation, see the referenced module chapters.
12.1 Clock Distribution
Figure 12-1. Clock distribution
The clock system on the SAM R21 consists of:
zClock sources, controlled by SYSCTRL
zA Clock source is the base clock signal used in the system. Example clock sources are the internal 8MHz
oscillator (OSC8M), External crystal oscillator (XOSC) and the Digital frequency locked loop (DFLL48M).
zGeneric Clock Controller (GCLK) which controls the clock distribution system, made up of:
zGeneric Clock generators: A programmable prescaler, that can use any of the system clock sources as its
source clock. The Generic Clock Generator 0, also called GCLK_MAIN, is the clock feeding the Power
Manager used to generate synchronous clocks.
zGeneric Clocks: Typically the clock input of a peripheral on the system. The generic clocks, through the
Generic Clock Multiplexer, can use any of the Generic Clock generators as its clock source. Multiple
instances of a peripheral will typically have a separate generic clock for each instance. The DFLL48M clock
input (when multiplying another clock source) is generic clock 0.
zPower Manager (PM)
zThe PM controls synchronous clocks on the system. This includes the CPU, bus clocks (APB, AHB) as well
as the synchronous (to the CPU) user interfaces of the peripherals. It contains clock masks that can turn
on/off the user interface of a peripheral as well as prescalers for the CPU and bus clocks.
Figure 12-2 shows an example where SERCOM0 is clocked by the DFLL48M in open loop mode. The DFLL48M is
enabled, the Generic Clock Generator 1 uses the DFLL48M as its clock source, and the generic clock 20, also called
GCLK_SERCOM0_CORE, that is connected to SERCOM0 uses generator 1 as its source. The SERCOM0 interface,
clocked by CLK_SERCOM0_APB, has been unmasked in the APBC Mask register in the PM.
GCLK Generator
0
S
Y
SC
TRL
GC
LK
GC
LK
G
enerator 1
GC
LK
G
enerator
x
GCLK Multi
p
lexer
0
(DFLL48M Reference)
GC
LK Multiplexer 1
GCLK Multiplexer y Peripheral
z
Peripheral
0
S
y
nchronous Clock
C
ontroller
PM
A
HB/APB S
y
stem Clock
s
GCLK_MAIN
_
N
OSC8
M
OSC3
2K
OSCULP32K
XOSC32K
DFLL48M
X
OS
C
G
eneric
C
locks
F
DPLL
96M
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Figure 12-2. Example of SERCOM clock
12.2 Synchronous and Asynchronous Clocks
As the CPU and the peripherals can be clocked from different clock sources, possibly with widely different clock speeds,
some peripheral accesses by the CPU needs to be synchronized between the different clock domains. In these cases the
peripheral includes a SYNCBUSY status flag that can be used to check if a sync operation is in progress. As the nature
of the synchronization might vary between different peripherals, detailed description for each peripheral can be found in
the sub-chapter “synchronization” for each peripheral where this is necessary.
In the datasheet references to synchronous clocks are referring to the CPU and bus clocks, while asynchronous clocks
are clock generated by generic clocks.
12.3 Register Synchronization
There are two different register synchronization schemes implemented on this device: some modules use a common
synchronizer register synchronization scheme, while other modules use a distributed synchronizer register
synchronization scheme.
The modules using a common synchronizer register synchronization scheme are: GCLK, WDT, RTC, EIC, TC, ADC, AC,
DAC.
The modules using a distributed synchronizer register synchronization scheme are: SERCOM USART, SERCOM SPI,
SERCOM I2C, TCC, USB.
12.3.1 Common Synchronizer Register Synchronization
12.3.1.1 Overview
All peripherals are composed of one digital bus interface, which is connected to the APB or AHB bus and clocked using a
corresponding synchronous clock, and one core clock, which is clocked using a generic clock. Access between these
clock domains must be synchronized. As this mechanism is implemented in hardware the synchronization process takes
place even if the different clocks domains are clocked from the same source and on the same frequency. All registers in
the bus interface are accessible without synchronization. All core registers in the generic clock domain must be
synchronized when written. Some core registers must be synchronized when read. Registers that need synchronization
has this denoted in each individual register description. Two properties are used: write-synchronization and read-
synchronization.
A common synchronizer is used for all registers in one peripheral, as shown in Figure 12-3. Therefore, only one register
per peripheral can be synchronized at a time.
SYSCTRL
DFLL48M
G
eneric
C
lock
G
enerator
1
G
eneric
C
lock
Multiplexer
20
SERCOM 0
Synchronous Clock
Controller
PM
CLK_SERCOM0_APB
GCLK_SERCOM0_CORE
GCLK
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Figure 12-3. Synchronization
12.3.1.2 Write-Synchronization
The write-synchronization is triggered by a write to any generic clock core register. The Synchronization Busy bit in the
Status register (STATUS.SYNCBUSY) will be set when the write-synchronization starts and cleared when the write-
synchronization is complete. Refer to “Synchronization Delay” on page 86 for details on the synchronization delay.
When the write-synchronization is ongoing (STATUS.SYNCBUSY is one), any of the following actions will cause the
peripheral bus to stall until the synchronization is complete:
zWriting a generic clock core register
zReading a read-synchronized core register
zReading the register that is being written (and thus triggered the synchronization)
Core registers without read-synchronization will remain static once they have been written and synchronized, and can be
read while the synchronization is ongoing without causing the peripheral bus to stall. APB registers can also be read
while the synchronization is ongoing without causing the peripheral bus to stall.
Non Synced reg
INTFLAG
STATUS
READREQ
Write-Synced reg
Write-Synced reg
R/W-Synced reg
Synchronizer Sync
SYNCBUSY
Synchronous Domain
(CLK_APB)
Asynchronous Domain
(generic clock)
Peripheral bus
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12.3.1.3 Read-Synchronization
Reading a read-synchronized core register will cause the peripheral bus to stall immediately until the read-
synchronization is complete. STATUS.SYNCBUSY will not be set. Refer to “Synchronization Delay” on page 86 for
details on the synchronization delay. Note that reading a read-synchronized core register while STATUS.SYNCBUSY is
one will cause the peripheral bus to stall twice; first because of the ongoing synchronization, and then again because
reading a read-synchronized core register will cause the peripheral bus to stall immediately.
12.3.1.4 Completion of synchronization
The user can either poll STATUS.SYNCBUSY or use the Synchronisation Ready interrupt (if available) to check when
the synchronization is complete. It is also possible to perform the next read/write operation and wait, as this next
operation will be started once the previous write/read operation is synchronized and/or complete.
12.3.1.5 Read Request
The read request functionality is only available to peripherals that have the Read Request register (READREQ)
implemented. Refer to the register description of individual peripheral chapters for details.
To avoid forcing the peripheral bus to stall when reading read-synchronized core registers, the read request mechanism
can be used.
Basic Read Request
Writing a one to the Read Request bit in the Read Request register (READREQ.RREQ) will request read-
synchronization of the register specified in the Address bits in READREQ (READREQ.ADDR) and set
STATUS.SYNCBUSY. When read-synchronization is complete, STATUS.SYNCBUSY is cleared. The read-
synchronized value is then available for reading without delay until READREQ.RREQ is written to one again.
The address to use is the offset to the peripheral's base address of the register that should be synchronized.
Continuous Read Request
Writing a one to the Read Continuously bit in READREQ (READREQ.RCONT) will force continuous read-
synchronization of the register specified in READREQ.ADDR. The latest value is always available for reading without
stalling the bus, as the synchronization mechanism is continuously synchronizing the given value.
SYNCBUSY is set for the first synchronization, but not for the subsequent synchronizations. If another synchronization is
attempted, i.e. by executing a write-operation of a write-synchronized register, the read request will be stopped, and will
have to be manually restarted.
Note that continuous read-synchronization is paused in sleep modes where the generic clock is not running. This means
that a new read request is required if the value is needed immediately after exiting sleep.
12.3.1.6 Enable Write-Synchronization
Writing to the Enable bit in the Control register (CTRL.ENABLE) will also trigger write-synchronization and set
STATUS.SYNCBUSY. CTRL.ENABLE will read its new value immediately after being written. The Synchronisation
Ready interrupt (if available) cannot be used for Enable write-synchronization.
When the enable write-synchronization is ongoing (STATUS.SYNCBUSY is one), attempt to do any of the following will
cause the peripheral bus to stall until the enable synchronization is complete:
zWriting a core register
zWriting an APB register
zReading a read-synchronized core register
APB registers can be read while the enable write-synchronization is ongoing without causing the peripheral bus to stall.
12.3.1.7 Software Reset Write-Synchronization
Writing a one to the Software Reset bit in CTRL (CTRL.SWRST) will also trigger write-synchronization and set
STATUS.SYNCBUSY. When writing a one to the CTRL.SWRST bit it will immediately read as one. CTRL.SWRST and
STATUS.SYNCBUSY will be cleared by hardware when the peripheral has been reset. Writing a zero to the
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CTRL.SWRST bit has no effect. The Synchronisation Ready interrupt (if available) cannot be used for Software Reset
write-synchronization.
When the software reset is in progress (STATUS.SYNCBUSY and CTRL.SWRST are one), attempt to do any of the
following will cause the peripheral bus to stall until the Software Reset synchronization and the reset is complete:
zWriting a core register
zWriting an APB register
zReading a read-synchronized register
APB registers can be read while the software reset is being write-synchronized without causing the peripheral bus to
stall.
12.3.1.8 Synchronization Delay
The synchronization will delay the write or read access duration by a delay D, given by the equation:
Where is the period of the generic clock and is the period of the peripheral bus clock. A normal peripheral
bus register access duration is .
12.3.2 Distributed Synchronizer Register Synchronization
12.3.2.1 Overview
All peripherals are composed of one digital bus interface, which is connected to the APB or AHB bus and clocked using a
corresponding synchronous clock, and one core clock, which is clocked using a generic clock. Access between these
clock domains must be synchronized. As this mechanism is implemented in hardware the synchronization process takes
place even if the different clocks domains are clocked from the same source and on the same frequency. All registers in
the bus interface are accessible without synchronization. All core registers in the generic clock domain must be
synchronized when written. Some core registers must be synchronized when read. Registers that need synchronization
has this denoted in each individual register description.
12.3.2.2 General Write synchronization
Inside the same module, each core register, denoted by the Write-Synchronized property, use its own synchronization
mechanism so that writing to different core registers can be done without waiting for the end of synchronization of
previous core register access.
To write again to the same core register in the same module, user must wait for the end of synchronization or the write
will be discarded.
For each core register, that can be written, a synchronization status bit is associated
Example:
REGA, REGB are 8-bit core registers. REGC is 16-bit core register.
Since synchronization is per register, user can write REGA (8-bit access) then immediately write REGB (8-bit access)
without error.
User can write REGC (16-bit access) without affecting REGA or REGB. But if user writes REGC in two consecutives 8-bit
accesses, second write will be discarded and generate an error.
5PGCLK
⋅2PAPB
⋅+D6PGCLK
⋅3PAPB
⋅+<<
PGCLK
PAPB
2PAPB
⋅
Offset Register
0x00 REGA
0x01 REGB
0x02
REGC
0x03
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When user makes a 32-bit access to offset 0x00, all registers are written but REGA, REGB, REGC can be updated at a
different time because of independent write synchronization
12.3.2.3 General read synchronization
Before any read of a core register, the user must check that the related bit in SYNCBUSY register is cleared.
Read access to core register is always immediate but the return value is reliable only if a synchonization of this core
register is not going.
12.3.2.4 Completion of synchronization
The user can either poll SYNCBUSY register or use the Synchronisation Ready interrupt (if available) to check when the
synchronization is complete.
12.3.2.5 Enable Write-Synchronization
Writing to the Enable bit in the Control register (CTRL.ENABLE) will also trigger write-synchronization and set
SYNCBUSY.ENABLE. CTRL.ENABLE will read its new value immediately after being written. The Synchronisation
Ready interrupt (if available) cannot be used for Enable write-synchronization.
12.3.2.6 Software Reset Write-Synchronization
Writing a one to the Software Reset bit in CTRL (CTRL.SWRST) will also trigger write-synchronization and set
SYNCBUSY.SWRST. When writing a one to the CTRL.SWRST bit it will immediately read as one. CTRL.SWRST and
SYNCBUSY.SWRST will be cleared by hardware when the peripheral has been reset. Writing a zero to the
CTRL.SWRST bit has no effect. The Synchronisation Ready interrupt (if available) cannot be used for Software Reset
write-synchronization.
12.3.2.7 Synchronization Delay
The synchronization will delay the write or read access duration by a delay D, given by the equation:
Where is the period of the generic clock and is the period of the peripheral bus clock. A normal peripheral
bus register access duration is .
12.4 Enabling a Peripheral
To enable a peripheral clocked by a generic clock, the following parts of the system needs to be configured:
zA running clock source.
zA clock from the Generic Clock Generator must be configured to use one of the running clock sources, and the
generator must be enabled.
zThe generic clock, through the Generic Clock Multiplexer, that connects to the peripheral needs to be configured
with a running clock from the Generic Clock Generator, and the generic clock must be enabled.
zThe user interface of the peripheral needs to be unmasked in the PM. If this is not done the peripheral registers will
read as all 0’s and any writes to the peripheral will be discarded.
5PGCLK
⋅2PAPB
⋅+D6PGCLK
⋅3PAPB
⋅+<<
PGCLK
PAPB
2PAPB
⋅
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12.5 On-demand, Clock Requests
Figure 12-4. Clock request routing
All the clock sources in the system can be run in an on-demand mode, where the clock source is in a stopped state when
no peripherals are requesting the clock source. Clock requests propagate from the peripheral, via the GCLK, to the clock
source. If one or more peripheral is using a clock source, the clock source will be started/kept running. As soon as the
clock source is no longer needed and no peripheral have an active request the clock source will be stopped until
requested again. For the clock request to reach the clock source, the peripheral, the generic clock and the clock from the
Generic Clock Generator in-between must be enabled. The time taken from a clock request being asserted to the clock
source being ready is dependent on the clock source startup time, clock source frequency as well as the divider used in
the Generic Clock Generator. The total startup time from a clock request to the clock is available for the peripheral is:
Delay_start_max = Clock source startup time + 2 * clock source periods + 2 * divided clock source periods
Delay_start_min = Clock source startup time + 1 * clock source period + 1 * divided clock source period
The delay for shutting down the clock source when there is no longer an active request is:
Delay_stop_min = 1 * divided clock source period + 1 * clock source period
Delay_stop_max = 2 * divided clock source periods + 2 * clock source periods
The On-Demand principle can be disabled individually for each clock source by clearing the ONDEMAND bit located in
each clock source controller. The clock is always running whatever is the clock request. This has the effect to remove the
clock source startup time at the cost of the power consumption.
In standby mode, the clock request mechanism is still working if the modules are configured to run in standby mode
(RUNSTDBY bit).
12.6 Power Consumption vs Speed
Due to the nature of the asynchronous clocking of the peripherals there are some considerations that needs to be taken
if either targeting a low-power or a fast-acting system. If clocking a peripheral with a very low clock, the active power
consumption of the peripheral will be lower. At the same time the synchronization to the synchronous (CPU) clock
domain is dependent on the peripheral clock speed, and will be longer with a slower peripheral clock; giving lower
response time and more time waiting for the synchronization to complete.
12.7 Clocks after Reset
On any reset the synchronous clocks start to their initial state:
zOSC8M is enabled and divided by 8
zGCLK_MAIN uses OSC8M as source
zCPU and BUS clocks are undivided
On a power reset the GCLK starts to their initial state:
zAll generic clock generators disabled except:
zthe generator 0 (GCLK_MAIN) using OSC8M as source, with no division
zthe generator 2 using OSCULP32K as source, with no division
DFLL48M
G
eneric
C
lock
G
enerator
Clock request
G
eneric
C
lock
M
ulti
p
lexer
Clock request
P
er
iph
era
l
Clock request
ENABLE
RUNSTDBY
ONDEMAND
CLKEN
RUNSTDBY
ENABLE
RUNSTDBY
GENEN
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zAll generic clocks disabled except:
zthe WDT generic clock using the generator 2 as source
On a user reset the GCLK starts to their initial state, except for:
zgeneric clocks that are write-locked (WRTLOCK is written to one prior to reset or the WDT generic clock if the
WDT Always-On at power on bit set in the NVM User Row)
zThe generic clock dedicated to the RTC if the RTC generic clock is enabled
On any reset the clock sources are reset to their initial state except the 32KHz clock sources which are reset only by a
power reset.
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13. GCLK – Generic Clock Controller
13.1 Overview
Several peripherals may require specific clock frequencies to operate correctly. The Generic Clock Controller consists of
number of generic clock generators and generic clock multiplexers that can provide a wide range of clock frequencies.
The generic clock generators can be set to use different external and internal clock sources. The selected clock can be
divided down in the generic clock generator. The outputs from the generic clock generators are used as clock sources for
the generic clock multiplexers, which select one of the sources to generate a generic clock (GCLK_PERIPHERAL), as
shown in Figure 13-2. The number of generic clocks, m, depends on how many peripherals the device has.
13.2 Features
zProvides generic clocks
zWide frequency range
zClock source for the generator can be changed on the fly
13.3 Block Diagram
The Generic Clock Controller can be seen in the clocking diagram, which is shown in Figure 13-1 .
Figure 13-1. Device Clocking Diagram
The Generic Clock Controller block diagram is shown in Figure 13-2.
GC
LK_I
O
G
eneric
C
lock
G
enerato
r
OSC
32K
OSC
ULP32K
XOSC
32
K
S
Y
SC
TRL
C
lock
D
ivider
&
Mas
k
er
C
loc
k
G
at
e
G
eneric Clock Multi
p
lexe
r
P
ERIPHERAL
S
G
ENERI
C
C
L
OC
K
CO
NTR
O
LLE
R
PM
GC
LK_MAI
N
D
FLL48M
X
OSC
OSC8M
FDPLL96M
GC
LK_PERIPHERA
L
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Figure 13-2. Generic Clock Controller Block Diagram(1)
Note: 1. If the GENCTRL.SRC=GCLKIN the GCLK_IO is set as an input.
13.4 Signal Description
Refer to “I/O Multiplexing and Considerations” on page 12 for details on the pin mapping for this peripheral. One signal
can be mapped on several pins.
13.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
13.5.1 I/O Lines
Using the Generic Clock Controller’s I/O lines requires the I/O pins to be configured. Refer to “PORT” on page 373 for
details.
13.5.2 Power Management
The Generic Clock Controller can operate in all sleep modes, if required. Refer to Table 14-4 for details on the different
sleep modes.
13.5.3 Clocks
The Generic Clock Controller bus clock (CLK_GCLK_APB) can be enabled and disabled in the Power Manager, and the
default state of CLK_GCLK_APB can be found in the Peripheral Clock Masking section in APBAMASK.
Generic Clock Generator 0
GC
LK_I
O
[0]
(
I/O input)
C
lock
D
ivider
&
Maske
r
C
lock
S
ources GCLKGEN
[
0
]
GC
LK_I
O
[1]
(
I/O input
)
GC
LK
G
EN[1]
G
CLK
_
IO
[
n
]
(
I
/O
input
)
GC
LK
G
EN[n]
Clock
G
at
e
G
eneric
C
lock Multiplexer
0
GCLK_PERIPHERAL[0]
Clock
G
at
e
G
eneric
C
lock Multiplexer 1
C
lock
G
at
e
G
eneric Clock Multi
p
lexer
m
GC
LK
G
EN[n:0]
GC
LK_MAIN
GC
LK_I
O
[1
]
(
I
/O
output
)
GC
LK_I
O
[0
]
(I/O output
)
GCLK
_
IO
[
n
]
(
I
/O
output
)
G
eneric
C
lock
G
enerator
1
C
lock
Divider &
Maske
r
G
eneric
C
lock
G
enerator
n
C
lock
D
ivider
&
M
as
k
er
GCLK_PERIPHERAL[1]
GCLK_PERIPHERAL[m]
Table 13-1. Signal Description
Signal Name Type Description
GCLK_IO[7:0] Digital I/O Source clock when input
Generic clock when output
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13.5.4 DMA
Not applicable.
13.5.5 Interrupts
Not applicable.
13.5.6 Events
Not applicable.
13.5.7 Debug Operation
Not applicable.
13.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC).
Write-protection is denoted by the Write-Protection property in the register description.
When the CPU is halted in debug mode or the CPU reset is extended, all write-protection is automatically disabled.
Write-protection does not apply for accesses through an external debugger. Refer to “PAC – Peripheral Access
Controller” on page 36 for details.
13.5.9 Analog Connections
Not applicable.
13.6 Functional Description
13.6.1 Principle of Operation
The GCLK module is comprised of eight generic clock generators sourcing m generic clock multiplexers.
A clock source selected as input to one of the generic clock generators can be used directly, or it can be prescaled in the
generic clock generator before the generator output is used as input to one or more of the generic clock multiplexers.
A generic clock multiplexer provides a generic clock to a peripheral (GCLK_PERIPHERAL). A generic clock can act as
the clock to one or several of peripherals.
13.6.2 Basic Operation
13.6.2.1 Initialization
Before a generic clock is enabled, the clock source of its generic clock generator should be enabled. The generic clock
must be configured as outlined by the following steps:
1. The generic clock generator division factor must be set by performing a single 32-bit write to the Generic Clock
Generator Division register (GENDIV):
zThe generic clock generator that will be selected as the source of the generic clock must be written to the ID
bit group (GENDIV.ID).
zThe division factor must be written to the DIV bit group (GENDIV.DIV)
Refer to GENDIV register for details.
2. The generic clock generator must be enabled by performing a single 32-bit write to the Generic Clock Generator
Control register (GENCTRL):
zThe generic clock generator that will be selected as the source of the generic clock must be written to the ID
bit group (GENCTRL.ID)
zThe generic clock generator must be enabled by writing a one to the GENEN bit (GENCTRL.GENEN)
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Refer to GENCTRL register for details.
3. The generic clock must be configured by performing a single 16-bit write to the Generic Clock Control register
(CLKCTRL):
zThe generic clock that will be configured must be written to the ID bit group (CLKCTRL.ID)
zThe generic clock generator used as the source of the generic clock must be written to the GEN bit group
(CLKCTRL.GEN)
Refer to CLKCTRL register for details.
13.6.2.2 Enabling, Disabling and Resetting
The GCLK module has no enable/disable bit to enable or disable the whole module.
The GCLK is reset by writing a one to the Software Reset bit in the Control register (CTRL.SWRST). All registers in the
GCLK will be reset to their initial state except for generic clocks and associated generators that have their Write Lock bit
written to one. Refer to “Configuration Lock” on page 95 for details.
13.6.2.3 Generic Clock Generator
Each generic clock generator (GCLKGEN) can be set to run from one of eight different clock sources except
GCLKGEN[1] which can be set to run from one of seven sources. GCLKGEN[1] can act as source to the other generic
clock generators but can not act as source to itself.
Each generic clock generator GCLKGEN[x] can be connected to one specific GCLK_IO[x] pin. The GCLK_IO[x] can be
set to act as source to GCLKGEN[x] or GCLK_IO[x] can be set up to output the clock generated by GCLKGEN[x].
The selected source (GCLKGENSRC see Figure 13-3) can optionally be divided. Each generic clock generator can be
independently enabled and disabled.
Each GCLKGEN clock can then be used as a clock source for the generic clock multiplexers. Each generic clock is
allocated to one or several peripherals.
GCLKGEN[0], is used as GCLK_MAIN for the synchronous clock controller inside the Power Manager.
Refer to “PM – Power Manager” on page 112 for details on the synchronous clock generation.
Figure 13-3. Generic Clock Generator
13.6.2.4 Enabling a Generic Clock Generator
A generic clock generator is enabled by writing a one to the Generic Clock Generator Enable bit in the Generic Clock
Generator Control register (GENCTRL.GENEN).
13.6.2.5 Disabling a Generic Clock Generator
A generic clock generator is disabled by writing a zero to GENCTRL.GENEN. When GENCTRL.GENEN is read as zero,
the GCLKGEN clock is disabled and clock gated.
GC
LK_I
O
[x]
D
IVIDE
R
C
loc
k
G
at
e
GC
LK
G
EN[x
]
C
lock
S
ource
s
0
1
GENCTRL.DIVSE
L
G
EN
C
TRL.
G
ENEN
G
ENDIV.DI
V
G
ENCTRL.SR
C
GC
LK
G
EN
S
R
C
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13.6.2.6 Selecting a Clock Source for the Generic Clock Generator
Each generic clock generator can individually select a clock source by writing to the Source Select bit group in
GENCTRL (GENCTRL.SRC). Changing from one clock source, A, to another clock source, B, can be done on the fly. If
clock source B is not ready, the generic clock generator will continue running with clock source A. As soon as clock
source B is ready, however, the generic clock generator will switch to it. During the switching, the generic clock generator
holds clock requests to clock sources A and B and then releases the clock source A request when the switch is done.
The available clock sources are device dependent (usually the crystal oscillators, RC oscillators, PLL and DFLL clocks).
GCLKGEN[1] can be used as a common source for all the generic clock generators except generic clock generator 1.
13.6.2.7 Changing Clock Frequency
The selected generic clock generator source, GENCLKSRC can optionally be divided by writing a division factor
in the Division Factor bit group in the Generic Clock Generator Division register (GENDIV.DIV). Depending on the value
of the Divide Selection bit in GENCTRL (GENCTRL.DIVSEL), it can be interpreted in two ways by the integer divider.
Note that the number of DIV bits for each generic clock generator is device dependent.
Refer to Table 13-11 for details.
13.6.2.8 Duty Cycle
When dividing a clock with an odd division factor, the duty-cycle will not be 50/50. Writing a one to the Improve Duty
Cycle bit in GENCTRL (GENCTRL.IDC) will result in a 50/50 duty cycle.
13.6.2.9 Generic Clock Output on I/O Pins
Each Generic Clock Generator's output can be directed to a GCLK_IO pin. If the Output Enable bit in GENCTRL
(GENCTRL.OE) is one and the generic clock generator is enabled (GENCTRL.GENEN is one), the generic clock
generator requests its clock source and the GCLKGEN clock is output to a GCLK_IO pin. If GENCTRL.OE is zero,
GCLK_IO is set according to the Output Off Value bit. If the Output Off Value bit in GENCTRL (GENCTRL.OOV) is zero,
the output clock will be low when generic clock generator is turned off. If GENCTRL.OOV is one, the output clock will be
high when generic clock generator is turned off.
In standby mode, if the clock is output (GENCTRL.OE is one), the clock on the GCLK_IO pin is frozen to the OOV value
if the Run In Standby bit in GENCTRL (GENCTRL.RUNSTDBY) is zero. If GENCTRL.RUNSTDBY is one, the GCLKGEN
clock is kept running and output to GCLK_IO.
13.6.3 Generic Clock
Figure 13-4. Generic Clock Multiplexer
13.6.3.1 Enabling a Generic Clock
Before a generic clock is enabled, one of the generic clock generators must be selected as the source for the generic
clock by writing to CLKCTRL.GEN. The clock source selection is individually set for each generic clock.
C
loc
k
G
at
e
GCLK_PERIPHERAL
C
LKCTRL.GEN
C
LK
C
TRL.
C
LKEN
GCLKGEN
[
0
]
GC
LK
G
EN[1]
GC
LK
G
EN[2]
GCLKGEN
[
n
]
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When a generic clock generator has been selected, the generic clock is enabled by writing a one to the Clock Enable bit
in CLKCTRL (CLKCTRL.CLKEN). The CLKCTRL.CLKEN bit must be synchronized to the generic clock domain.
CLKCTRL.CLKEN will continue to read as its previous state until the synchronization is complete.
13.6.3.2 Disabling a Generic Clock
A generic clock is disabled by writing a zero to CLKCTRL.CLKEN. The SYNCBUSY bit will be cleared when this write-
synchronization is complete. CLKCTRL.CLKEN will continue to read as its previous state until the synchronization is
complete. When the generic clock is disabled, the generic clock is clock gated.
13.6.3.3 Selecting a Clock Source for the Generic Clock
When changing a generic clock source by writing to CLKCTRL.GEN, the generic clock must be disabled before being re-
enabled with the new clock source setting. This prevents glitches during the transition:
1. Write a zero to CLKCTRL.CLKEN
2. Wait until CLKCTRL.CLKEN reads as zero
3. Change the source of the generic clock by writing CLKCTRL.GEN
4. Re-enable the generic clock by writing a one to CLKCTRL.CLKEN
13.6.3.4 Configuration Lock
The generic clock configuration is locked for further write accesses by writing the Write Lock bit (WRTLOCK) in the
CLKCTRL register. All writes to the CLKCTRL register will be ignored. It can only be unlocked by a power reset.
The generic clock generator sources of a locked generic clock are also locked. The corresponding GENCTRL and
GENDIV are locked, and can be unlocked only by a power reset.
There is one exception concerning the GCLKGEN[0]. As it is used as GCLK_MAIN, it can not be locked. It is reset by any
reset to startup with a known configuration.
The SWRST can not unlock the registers.
13.6.4 Additional Features
13.6.4.1 Indirect Access
The Generic Clock Generator Control and Division registers (GENCTRL and GENDIV) and the Generic Clock Control
register (CLKCTRL) are indirectly addressed as shown in Figure 13-5.
Figure 13-5. GCLK Indirect Access
Writing these registers is done by setting the corresponding ID bit group.
To read a register, the user must write the ID of the channel, i, in the corresponding register. The value of the register for
the corresponding ID is available in the user interface by a read access.
GENCTR
L
G
ENDIV
C
LK
C
TR
L
G
EN
C
TRL.ID=
i
G
ENDIV.ID=i
CLKCTRL.ID=
j
U
ser Interface
GENCTR
L
G
ENDIV
G
eneric
C
lock
G
enerator [i
]
C
LK
C
TR
L
G
eneric Clock[
j
]
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For example, the sequence to read the GENCTRL register of generic clock generator i is:
1. Do an 8-bit write of the i value to GENCTRL.ID
2. Read GENCTRL
13.6.4.2 Generic Clock Enable after Reset
The Generic Clock Controller must be able to provide a generic clock to some specific peripherals after a reset. That
means that the configuration of the generic clock generators and generic clocks after reset is device-dependent.
Refer to Table 13-9 and Table 13-10 for details on GENCTRL reset.
Refer to Table 13-13 and Table 13-14 for details on GENDIV reset.
Refer to Table 13-5 and Table 13-6 for details on CLKCTRL reset.
13.6.5 Sleep Mode Operation
13.6.5.1 SleepWalking
The GCLK module supports the SleepWalking feature. During a sleep mode where the generic clocks are stopped, a
peripheral that needs its generic clock to execute a process must request it from the Generic Clock Controller.
The Generic Clock Controller will receive this request and then determine which generic clock generator is involved and
which clock source needs to be awakened. It then wakes up the clock source, enables the generic clock generator and
generic clock stages successively and delivers the generic clock to the peripheral.
13.6.5.2 Run in Standby Mode
In standby mode, the GCLK can continuously output the generic clock generator output to GCLK_IO.
Refer to “Generic Clock Output on I/O Pins” on page 94 for details.
13.6.6 Synchronization
Due to the asynchronicity between CLK_GCLK_APB and GCLKGENSRC some registers must be synchronized when
accessed. A register can require:
zSynchronization when written
zSynchronization when read
zSynchronization when written and read
zNo synchronization
When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is
stalled.
The following registers need synchronization when written:
zGeneric Clock Generator Control register (GENCTRL)
zGeneric Clock Generator Division register (GENDIV)
zControl register (CTRL)
Write-synchronization is denoted by the Write-Synchronization property in the register description.
Refer to “Register Synchronization” on page 83 for further details.
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13.7 Register Summary
Table 13-2. Register Summary
Offset Name
Bit
Pos.
0x0 CTRL 7:0 SWRST
0x1 STATUS 7:0 SYNCBUSY
0x2
CLKCTRL
7:0 ID[5:0]
0x3 15:8 WRTLOCK CLKEN GEN[3:0]
0x4
GENCTRL
7:0 ID[3:0]
0x5 15:8 SRC[4:0]
0x6 23:16 RUNSTDBY DIVSEL OE OOV IDC GENEN
0x7 31:24
0x8
GENDIV
7:0 ID[3:0]
0x9 15:8 DIV[7:0]
0xA 23:16 DIV[15:8]
0xB 31:24
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13.8 Register Description
Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters
and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by
the Write-protected property in each individual register description. Refer to “Register Access Protection” on page 92 for
details.
Some registers require synchronization when read and/or written. Synchronization is denoted by the Write-Synchronized
or the Read-Synchronized property in each individual register description. Refer to “Synchronization” on page 96 for
details.
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13.8.1 Control
Name: CTRL
Offset: 0x0
Reset: 0x00
Property: Write-Protected, Write-Synchronized
zBits 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 0 – SWRST: Software Reset
0: There is no reset operation ongoing.
1: There is a reset operation ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the GCLK to their initial state after a power reset, except for generic
clocks and associated generators that have their WRTLOCK bit in CLKCTRL read as one.
Refer to Table 13-9 for details on GENCTRL reset.
Refer to Table 13-13 for details on GENDIV reset.
Refer to Table 13-5 for details on CLKCTRL reset.
Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete. CTRL.SWRST and
STATUS.SYNCBUSY will both be cleared when the reset is complete.
Bit 76543210
SWRST
AccessRRRRRRRR/W
Reset00000000
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13.8.2 Status
Name: STATUS
Offset: 0x1
Reset: 0x00
Property: -
zBit 7 – SYNCBUSY: Synchronization Busy Status
This bit is cleared when the synchronization of registers between the clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
zBits 6:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit 76543210
SYNCBUSY
AccessRRRRRRRR
Reset00000000
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13.8.3 Generic Clock Control
This register allows the user to configure one of the generic clocks, as specified in the CLKCTRL.ID bit group. To write to
the CLKCTRL register, do a 16-bit write with all configurations and the ID.
To read the CLKCTRL register, first do an 8-bit write to the CLKCTRL.ID bit group with the ID of the generic clock whose
configuration is to be read, and then read the CLKCTRL register.
Name: CLKCTRL
Offset: 0x2
Reset: 0x0000
Property: Write-Protected
zBit 15 – WRTLOCK: Write Lock
When this bit is written, it will lock from further writes the generic clock pointed to by CLKCTRL.ID, the generic
clock generator pointed to in CLKCTRL.GEN and the division factor used in the generic clock generator. It can
only be unlocked by a power reset.
One exception to this is generic clock generator 0, which cannot be locked.
0: The generic clock and the associated generic clock generator and division factor are not locked.
1: The generic clock and the associated generic clock generator and division factor are locked.
zBit 14 – CLKEN: Clock Enable
This bit is used to enable and disable a generic clock.
0: The generic clock is disabled.
1: The generic clock is enabled.
zBits 13:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 11:8 – GEN[3:0]: Generic Clock Generator
Bit 151413121110 9 8
WRTLOCK CLKEN GEN[3:0]
AccessR/WR/W R R R/WR/WR/WR/W
Reset00000000
Bit 76543210
ID[5:0]
Access R R R/W R/W R/W R/W R/W R/W
Reset00000000
Table 13-3. Generic Clock Generator
GEN[3:0] Name Description
0x0 GCLKGEN0 Generic clock generator 0
0x1 GCLKGEN1 Generic clock generator 1
0x2 GCLKGEN2 Generic clock generator 2
0x3 GCLKGEN3 Generic clock generator 3
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zBits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 5:0 – ID[5:0]: Generic Clock Selection ID
These bits select the generic clock that will be configured. The value of the ID bit group versus module instance is
shown in Table 13-4.
0x4 GCLKGEN4 Generic clock generator 4
0x5 GCLKGEN5 Generic clock generator 5
0x6 GCLKGEN6 Generic clock generator 6
0x7 GCLKGEN7 Generic clock generator 7
0x8 GCLKGEN8 Generic clock generator 8
0x9-0xF Reserved
Table 13-4. Generic Clock Selection ID
Value Name Description
0x00 GCLK_DFLL48M_REF DFLL48M Reference
0x01 GCLK_DPLL FDPLL96M input clock source for reference
0x02 GCLK_DPLL_32K FDPLL96M 32kHz clock for FDPLL96M internal lock timer
0x03 GCLK_WDT WDT
0x04 GCLK_RTC RTC
0x05 GCLK_EIC EIC
0x06 GCLK_USB USB
0x07 GCLK_EVSYS_CHANNEL_0 EVSYS_CHANNEL_0
0x08 GCLK_EVSYS_CHANNEL_1 EVSYS_CHANNEL_1
0x09 GCLK_EVSYS_CHANNEL_2 EVSYS_CHANNEL_2
0x0A GCLK_EVSYS_CHANNEL_3 EVSYS_CHANNEL_3
0x0B GCLK_EVSYS_CHANNEL_4 EVSYS_CHANNEL_4
0x0C GCLK_EVSYS_CHANNEL_5 EVSYS_CHANNEL_5
0x0D GCLK_EVSYS_CHANNEL_6 EVSYS_CHANNEL_6
0x0E GCLK_EVSYS_CHANNEL_7 EVSYS_CHANNEL_7
0x0F GCLK_EVSYS_CHANNEL_8 EVSYS_CHANNEL_8
0x10 GCLK_EVSYS_CHANNEL_9 EVSYS_CHANNEL_9
0x11 GCLK_EVSYS_CHANNEL_10 EVSYS_CHANNEL_10
0x12 GCLK_EVSYS_CHANNEL_11 EVSYS_CHANNEL_11
Table 13-3. Generic Clock Generator (Continued)
GEN[3:0] Name Description
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A power reset will reset the CLKCTRL register for all IDs, including the RTC. If the WRTLOCK bit of the corre-
sponding ID is zero and the ID is not the RTC, a user reset will reset the CLKCTRL register for this ID.
After a power reset, the reset value of the CLKCTRL register versus module instance is as shown in Table 13-5.
0x13 GCLK_SERCOMx_SLOW SERCOMx_SLOW
0x14 GCLK_SERCOM0_CORE SERCOM0_CORE
0x15 GCLK_SERCOM1_CORE SERCOM1_CORE
0x16 GCLK_SERCOM2_CORE SERCOM2_CORE
0x17 GCLK_SERCOM3_CORE SERCOM3_CORE
0x18 GCLK_SERCOM4_CORE SERCOM4_CORE
0x19 GCLK_SERCOM5_CORE SERCOM5_CORE
0x1A GCLK_TCC0, GCLK_TCC1 TCC0,TCC1
0x1B GCLK_TCC2, GCLK_TC3 TCC2,TC3
0x1C GCLK_TC4, GCLK_TC5 TC4,TC5
0x1D Reserved
0x1E GCLK_ADC ADC
0x1F GCLK_AC_DIG AC_DIG
0x20 GCLK_AC_ANA AC_ANA
0x21 Reserved
0x22 GCLK_PTC PTCReserved
0x23 Reserved
0x24 Reserved
0x25-0x3F Reserved
Table 13-5. CLKCTRL Reset Value after a Power Reset
Module Instance Reset Value after Power Reset
CLKCTRL.GEN CLKCTRL.CLKEN CLKCTRL.WRTLOCK
RTC 0x00 0x00 0x00
WDT 0x02
0x01 if WDT Enable bit in NVM
User Row written to one
0x00 if WDT Enable bit in NVM
User Row written to zero
0x01 if WDT Always-On bit in
NVM User Row written to one
0x00 if WDT Always-On bit in
NVM User Row written to zero
Others 0x00 0x00 0x00
Table 13-4. Generic Clock Selection ID (Continued)
Value Name Description
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After a user reset, the reset value of the CLKCTRL register versus module instance is as shown in Table 13-6.
Table 13-6. CLKCTRL Reset Value after a User Reset
Module Instance Reset Value after a User Reset
CLKCTRL.GEN CLCTRL.CLKEN CLKCTRL.WRTLOCK
RTC
0x00 if WRTLOCK=0 and
CLKEN=0
No change if WRTLOCK=1
or CLKEN=1
0x00 if WRTLOCK=0 and CLKEN=0
No change if WRTLOCK=1 or CLKEN=1 No change
WDT 0x02 if WRTLOCK=0
No change if WRTLOCK=1
If WRTLOCK=0
0x01 if WDT Enable bit in NVM User
Row written to one
0x00 if WDT Enable bit in NVM User
Row written to zero
If WRTLOCK=1 no change
No change
Others 0x00 if WRTLOCK=0
No change if WRTLOCK=1
0x00 if WRTLOCK=0
No change if WRTLOCK=1 No change
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13.8.4 Generic Clock Generator Control
This register allows the user to configure one of the generic clock generators, as specified in the GENCTRL.ID bit group.
To write to the GENCTRL register, do a 32-bit write with all configurations and the ID.
To read the GENCTRL register, first do an 8-bit write to the GENCTRL.ID bit group with the ID of the generic clock
generator whose configuration is to be read, and then read the GENCTRL register.
Name: GENCTRL
Offset: 0x4
Reset: 0x00000000
Property: Write-Protected, Write-Synchronized
zBits 31:22 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 21 – RUNSTDBY: Run in Standby
This bit is used to keep the generic clock generator running when it is configured to be output to its dedicated
GCLK_IO pin. If GENCTRL.OE is zero, this bit has no effect and the generic clock generator will only be running if
a peripheral requires the clock.
0: The generic clock generator is stopped in standby and the GCLK_IO pin state (one or zero) will be dependent
on the setting in GENCTRL.OOV.
1: The generic clock generator is kept running and output to its dedicated GCLK_IO pin during standby mode.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
RUNSTDBY
DIVSEL OE OOV IDC GENEN
Access R R R/W R/W R/W R/W R/W R/W
Reset00000000
Bit 151413121110 9 8
SRC[4:0]
Access R R R R/W R/W R/W R/W R/W
Reset00000000
Bit 76543210
ID[3:0]
AccessRRRRR/WR/WR/WR/W
Reset00000000
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zBit 20 – DIVSEL: Divide Selection
This bit is used to decide how the clock source used by the generic clock generator will be divided. If the clock
source should not be divided, the DIVSEL bit must be zero and the GENDIV.DIV value for the corresponding
generic clock generator must be zero or one.
0: The generic clock generator equals the clock source divided by GENDIV.DIV.
1: The generic clock generator equals the clock source divided by 2^(GENDIV.DIV+1).
zBit 19 – OE: Output Enable
This bit is used to enable output of the generated clock to GCLK_IO when GCLK_IO is not selected as a source in
the GENCLK.SRC bit group.
0: The generic clock generator is not output.
1: The generic clock generator is output to the corresponding GCLK_IO, unless the corresponding GCLK_IO is
selected as a source in the GENCLK.SRC bit group.
zBit 18 – OOV: Output Off Value
This bit is used to control the value of GCLK_IO when GCLK_IO is not selected as a source in the GENCLK.SRC
bit group.
0: The GCLK_IO will be zero when the generic clock generator is turned off or when the OE bit is zero.
1: The GCLK_IO will be one when the generic clock generator is turned off or when the OE bit is zero.
zBit 17 – IDC: Improve Duty Cycle
This bit is used to improve the duty cycle of the generic clock generator when odd division factors are used.
0: The generic clock generator duty cycle is not 50/50 for odd division factors.
1: The generic clock generator duty cycle is 50/50.
zBit 16 – GENEN: Generic Clock Generator Enable
This bit is used to enable and disable the generic clock generator.
0: The generic clock generator is disabled.
1: The generic clock generator is enabled.
zBits 15:13 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 12:8 – SRC[4:0]: Source Select
These bits define the clock source to be used as the source for the generic clock generator, as shown in Table 13-
7.
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zBits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 3:0 – ID[3:0]: Generic Clock Generator Selection
These bits select the generic clock generator that will be configured or read. The value of the ID bit group versus
which generic clock generator is configured is shown in Table 13-8.
A power reset will reset the GENCTRL register for all IDs, including the generic clock generator used by the RTC. If a
generic clock generator ID other than generic clock generator 0 is not a source of a “locked” generic clock or a source of
the RTC generic clock, a user reset will reset the GENCTRL for this ID.
After a power reset, the reset value of the GENCTRL register is as shown in Table 13-9.
Table 13-7. Source Select
Value Name Description
0x00 XOSC XOSC oscillator output
0x01 GCLKIN Generator input pad
0x02 GCLKGEN1 Generic clock generator 1 output
0x03 OSCULP32K OSCULP32K oscillator output
0x04 OSC32K OSC32K oscillator output
0x05 XOSC32K XOSC32K oscillator output
0x06 OSC8M OSC8M oscillator output
0x07 DFLL48M DFLL48M output
0x08 FDPLL96M FDPLL96M output
0x09-0x1F Reserved Reserved for future use
Table 13-8. Generic Clock Generator Selection
Value Name Description
0x0 GCLKGEN0 Generic clock generator 0
0x1 GCLKGEN1 Generic clock generator 1
0x2 GCLKGEN2 Generic clock generator 2
0x3 GCLKGEN3 Generic clock generator 3
0x4 GCLKGEN4 Generic clock generator 4
0x5 GCLKGEN5 Generic clock generator 5
0x6 GCLKGEN6 Generic clock generator 6
0x7 GCLKGEN7 Generic clock generator 7
0x8 GCLKGEN8 Generic clock generator 8
0x9-0xF Reserved
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After a user reset, the reset value of the GENCTRL register is as shown in Table 13-10
.
Table 13-9. GENCTRL Reset Value after a Power Reset
GCLK Generator ID Reset Value after a Power Reset
0x00 0x00010600
0x01 0x00000001
0x02 0x00010302
0x03 0x00000003
0x04 0x00000004
0x05 0x00000005
0x06 0x00000006
0x07 0x00000007
0x08 0x00000008
Table 13-10. GENCTRL Reset Value after a User Reset
GCLK Generator ID Reset Value after a User Reset
0x00 0x00010600
0x01 0x00000001 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x02 0x00010302 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x03 0x00000003 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x04 0x00000004 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x05 0x00000005 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x06 0x00000006 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x07 0x00000007 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x08 0x00000008 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
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13.8.5 Generic Clock Generator Division
This register allows the user to configure one of the generic clock generators, as specified in the GENDIV.ID bit group.
To write to the GENDIV register, do a 32-bit write with all configurations and the ID.
To read the GENDIV register, first do an 8-bit write to the GENDIV.ID bit group with the ID of the generic clock generator
whose configuration is to be read, and then read the GENDIV register.
Name: GENDIV
Offset: 0x8
Reset: 0x00000000
Property: -
zBits 31:24 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 23:8 – DIV[15:0]: Division Factor
These bits apply a division on each selected generic clock generator. The number of DIV bits each generator has
can be seen in Table 13-11. Writes to bits above the specified number will be ignored.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
DIV[15:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
DIV[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
ID[3:0]
AccessRRRRR/WR/WR/WR/W
Reset00000000
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zBits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 3:0 – ID[3:0]: Generic Clock Generator Selection
These bits select the generic clock generator on which the division factor will be applied, as shown in Table 13-12.
A power reset will reset the GENDIV register for all IDs, including the generic clock generator used by the RTC. If a
generic clock generator ID other than generic clock generator 0 is not a source of a ‚“locked” generic clock or a source of
the RTC generic clock, a user reset will reset the GENDIV for this ID.
After a power reset, the reset value of the GENDIV register is as shown in Table 13-13.
Table 13-11. Division Factor
Generator Division Factor Bits
Generic clock generator 0 8 division factor bits - DIV[7:0]
Generic clock generator 1 16 division factor bits - DIV[15:0]
Generic clock generators 2 5 division factor bits - DIV[4:0]
Generic clock generators 3 - 8 8 division factor bits - DIV[7:0]
Table 13-12. Generic Clock Generator Selection
Values Description
0x0 Generic clock generator 0
0x1 Generic clock generator 1
0x2 Generic clock generator 2
0x3 Generic clock generator 3
0x4 Generic clock generator 4
0x5 Generic clock generator 5
0x6 Generic clock generator 6
0x7 Generic clock generator 7
0x8 Generic clock generator 8
0x9-0xF Reserved
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After a user reset, the reset value of the GENDIV register is as shown in Table 13-14.
Table 13-13. GENDIV Reset value after a Power Reset
GCLK Generator ID Reset Value after a Power Reset
0x00 0x00000000
0x01 0x00000001
0x02 0x00000002
0x03 0x00000003
0x04 0x00000004
0x05 0x00000005
0x06 0x00000006
0x07 0x00000007
0x08 0x00000008
Table 13-14. GENDIV Reset Value after a User Reset
GCLK Generator ID Reset Value after a User Reset
0x00 0x00000000
0x01 0x00000001 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x02 0x00000002 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x03 0x00000003 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x04 0x00000004 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x05 0x00000005 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x06 0x00000006 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x07 0x00000007 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x08 0x00000008 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
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14. PM – Power Manager
14.1 Overview
The Power Manager (PM) controls the reset, clock generation and sleep modes of the microcontroller.
Utilizing a main clock chosen from a large number of clock sources from the GCLK, the clock controller provides
synchronous system clocks to the CPU and the modules connected to the AHB and the APBx bus. The synchronous
system clocks are divided into a number of clock domains; one for the CPU and AHB and one for each APBx. Any
synchronous system clock can be changed at run-time during normal operation. The clock domains can run at different
speeds, enabling the user to save power by running peripherals at a relatively low clock frequency, while maintaining
high CPU performance. In addition, the clock can be masked for individual modules, enabling the user to minimize power
consumption.
Before entering the STANDBY sleep mode the user must make sure that a significant amount of clocks and peripherals
are disabled, so that the voltage regulator is not overloaded. This is because during STANDBY sleep mode the internal
voltage regulator will be in low power mode.
Various sleep modes and clock gating are provided in order to fit power consumption requirements. This enables the
microcontroller to stop unused modules to save power. In ACTIVE mode, the CPU is executing application code. When
the device enters a sleep mode, program execution is stopped and some modules and clock domains are automatically
switched off by the PM according to the sleep mode. The application code decides which sleep mode to enter and when.
Interrupts from enabled peripherals and all enabled reset sources can restore the microcontroller from a sleep mode to
ACTIVE mode.
The PM also contains a reset controller, which collects all possible reset sources. It issues a microcontroller reset and
sets the device to its initial state, and allows the reset source to be identified by software.
14.2 Features
zReset control
zReset the microcontroller and set it to an initial state according to the reset source
zMultiple reset sources
zPower reset sources: POR, BOD12, BOD33
zUser reset sources: External reset (RESET), Watchdog Timer reset, software reset
zReset status register for reading the reset source from the application code
zClock control
zControls CPU, AHB and APB system clocks
zMultiple clock sources and division factor from GCLK
zClock prescaler with 1x to 128x division
zSafe run-time clock switching from GCLK
zModule-level clock gating through maskable peripheral clocks
zPower management control
zSleep modes: IDLE, STANDBY
zSleepWalking support on GCLK clocks
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14.3 Block Diagram
Figure 14-1. PM Block Diagram
14.4 Signal Description
Refer to “I/O Multiplexing and Considerations” on page 12 for details on the pin mapping for this peripheral. One signal
can be mapped on several pins.
14.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
14.5.1 I/O Lines
Not applicable.
14.5.2 Power Management
Not applicable.
SYNCHRONOUS
CLOCK CONTROLLER
SLEEP MODE
CONTROLLER
RESET
CONTROLLER
CPU
BOD12
BOD33
POR
WDT
GCLK
RESET SOURCES
PERIPHERALS
RESET
CLK_APB
CLK_AHB
CLK_CPU
USER RESET
POWER RESET
POWER MANAGER
CPU
Signal Name Type Description
RESET Digital input External reset
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14.5.3 Clocks
The PM bus clock (CLK_PM_APB) can be enabled and disabled in the power manager, and the default state of
CLK_PM_APB can be found in Table 14-1. If this clock is disabled in the Power Manager, it can only be re-enabled by a
reset.
A generic clock (GCLK_MAIN) is required to generate the main clock. The clock source for GCLK_MAIN is configured by
default in the Generic Clock Controller, and can be re-configured by the user if needed. Refer to “GCLK – Generic Clock
Controller” on page 90 for details.
14.5.3.1 Main Clock
The main clock (CLK_MAIN) is the common source for the synchronous clocks. This is fed into the common 8-bit
prescaler that is used to generate synchronous clocks to the CPU, AHB and APBx modules.
14.5.3.2 CPU Clock
The CPU clock (CLK_CPU) is routed to the CPU. Halting the CPU clock inhibits the CPU from executing instructions.
14.5.3.3 AHB Clock
The AHB clock (CLK_AHB) is the root clock source used by peripherals requiring an AHB clock. The AHB clock is always
synchronous to the CPU clock and has the same frequency, but may run even when the CPU clock is turned off. A clock
gate is inserted from the common AHB clock to any AHB clock of a peripheral.
14.5.3.4 APBx Clocks
The APBx clock (CLK_APBX) is the root clock source used by modules requiring a clock on the APBx bus. The APBx
clock is always synchronous to the CPU clock, but can be divided by a prescaler, and will run even when the CPU clock
is turned off. A clock gater is inserted from the common APB clock to any APBx clock of a module on APBx bus.
14.5.4 DMA
Not applicable.
14.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the PM interrupt requires the Interrupt Controller
to be configured first. Refer to “Nested Vector Interrupt Controller” on page 29 for details.
14.5.6 Events
Not applicable.
14.5.7 Debug Operation
When the CPU is halted in debug mode, the PM continues normal operation. In sleep mode, the clocks generated from
the PM are kept running to allow the debugger accessing any modules. As a consequence, power measurements are not
possible in debug mode.
14.5.8 Register Access Protection
All registers with write access are optionally write-protected by the Peripheral Access Controller (PAC), except the
following registers:
zInterrupt Flag register (INTFLAG). Refer to INTFLAG for details
zReset Cause register (RCAUSE). Refer to RCAUSE for details
Write-protection is denoted by the Write-Protection property in the register description.
Write-protection does not apply for accesses through an external debugger. Refer to “PAC – Peripheral Access
Controller” on page 36 for details.
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14.5.9 Analog Connections
Not applicable.
14.6 Functional Description
14.6.1 Principle of Operation
14.6.1.1 Synchronous Clocks
The GCLK_MAIN clock from GCLK module provides the source for the main clock, which is the common root for the
synchronous clocks for the CPU and APBx modules. The main clock is divided by an 8-bit prescaler, and each of the
derived clocks can run from any tapping off this prescaler or the undivided main clock, as long as fCPU ≥ fAPBx. The
synchronous clock source can be changed on the fly to respond to varying load in the application. The clocks for each
module in each synchronous clock domain can be individually masked to avoid power consumption in inactive modules.
Depending on the sleep mode, some clock domains can be turned off (see Table 14-4 on page 119).
14.6.1.2 Reset Controller
The Reset Controller collects the various reset sources and generates reset for the device. The device contains a power-
on-reset (POR) detector, which keeps the system reset until power is stable. This eliminates the need for external reset
circuitry to guarantee stable operation when powering up the device.
14.6.1.3 Sleep Mode Controller
In ACTIVE mode, all clock domains are active, allowing software execution and peripheral operation. The PM Sleep
Mode Controller allows the user to choose between different sleep modes depending on application requirements, to
save power (see Table 14-4 on page 119).
14.6.2 Basic Operation
14.6.2.1 Initialization
After a power-on reset, the PM is enabled and the Reset Cause (RCAUSE - refer to RCAUSE for details) register
indicates the POR source. The default clock source of the GCLK_MAIN clock is started and calibrated before the CPU
starts running. The GCLK_MAIN clock is selected as the main clock without any division on the prescaler. The device is
in the ACTIVE mode.
By default, only the necessary clocks are enabled (see Table 14-1).
14.6.2.2 Enabling, Disabling and Resetting
The PM module is always enabled and can not be reset.
14.6.2.3 Selecting the Main Clock Source
Refer to “GCLK – Generic Clock Controller” on page 90 for details on how to configure the main clock source.
14.6.2.4 Selecting the Synchronous Clock Division Ratio
The main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks. By default, the
synchronous clocks run on the undivided main clock. The user can select a prescaler division for the CPU clock by
writing the CPU Prescaler Selection bits in the CPU Select register (CPUSEL.CPUDIV), resulting in a CPU clock
frequency determined by this equation:
fCPU
fmain
2CPUDIV
----------------------
=
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Similarly, the clock for the APBx can be divided by writing their respective registers (APBxSEL.APBxDIV). To ensure
correct operation, frequencies must be selected so that fCPU ≥ fAPBx. Also, frequencies must never exceed the specified
maximum frequency for each clock domain.
Note that the AHB clock is always equal to the CPU clock.
CPUSEL and APBxSEL can be written without halting or disabling peripheral modules. Writing CPUSEL and APBxSEL
allows a new clock setting to be written to all synchronous clocks at the same time. It is possible to keep one or more
clocks unchanged. This way, it is possible to, for example, scale the CPU speed according to the required performance,
while keeping the APBx frequency constant.
Figure 14-2. Synchronous Clock Selection and Prescaler
14.6.2.5 Clock Ready Flag
There is a slight delay from when CPUSEL and APBxSEL are written until the new clock setting becomes effective.
During this interval, the Clock Ready flag in the Interrupt Flag Status and Clear register (INTFLAG.CKRDY) will read as
zero. If CKRDY in the INTENSET register is written to one, the Power Manager interrupt can be triggered when the new
clock setting is effective. CPUSEL must not be re-written while CKRDY is zero, or the system may become unstable or
hang.
14.6.2.6 Peripheral Clock Masking
It is possible to disable or enable the clock for a peripheral in the AHB or APBx clock domain by writing the corresponding
bit in the Clock Mask register (APBxMASK - refer to APBAMASK for details) to zero or one. Refer to Table 14-1 for the
default state of each of the peripheral clocks.
Clock gate
Clock gate
Prescaler
Sleep Controller Sleep mode
CLK_AHB
Clock gate
Clock gate
CLK_APBA
Clock gate
Clock gate
CLK_APBC
Clock gate
Clock gate
CLK_APBB
APBCDIV
APBBDIV
APBADIV
CLK_PERIPHERAL_AHB_0
CLK_PERIPHERAL_AHB_1
CLK_PERIPHERAL_AHB_n
CLK_PERIPHERAL_APBA_0
CLK_PERIPHERAL_APBA_1
CLK_PERIPHERAL_APBA_n
CLK_PERIPHERAL_APBB_0
CLK_PERIPHERAL_APBB_1
CLK_PERIPHERAL_APBB_n
CLK_PERIPHERAL_APBC_0
CLK_PERIPHERAL_APBC_1
CLK_PERIPHERAL_APBC_n
APBCMASK
APBBMASK
APBAMASK
CPUDIV
AHBMASK
CLK_CPU
GCLK
GCLK_MAIN
Clock
gate
Clock
gate
Clock
gate
Clock
gate
Clock
gate
Clock
gate
Clock
gate
Clock
gate
Clock
gate
CLK_MAIN
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When the APB clock for a module is not provided its registers cannot be read or written. The module can be re-enabled
later by writing the corresponding mask bit to one.
A module may be connected to several clock domains (for instance, AHB and APB), in which case it will have several
mask bits.
Note that clocks should only be switched off if it is certain that the module will not be used. Switching off the clock for the
NVM Controller (NVMCTRL) will cause a problem if the CPU needs to read from the flash memory. Switching off the
clock to the Power Manager (PM), which contains the mask registers, or the corresponding APBx bridge, will make it
impossible to write the mask registers again. In this case, they can only be re-enabled by a system reset.
14.6.2.7 Reset Controller
The latest reset cause is available in RCAUSE, and can be read during the application boot sequence in order to
determine proper action.
There are two groups of reset sources:
zPower Reset: Resets caused by an electrical issue.
Table 14-1. Peripheral Clock Default State
Peripheral Clock Default State
CLK_PAC0_APB Enabled
CLK_PM_APB Enabled
CLK_SYSCTRL_APB Enabled
CLK_GCLK_APB Enabled
CLK_WDT_APB Enabled
CLK_RTC_APB Enabled
CLK_EIC_APB Enabled
CLK_PAC1_APB Enabled
CLK_DSU_APB Enabled
CLK_NVMCTRL_APB Enabled
CLK_PORT_APB Enabled
CLK_HMATRIX_APB Enabled
CLK_PAC2_APB Disabled
CLK_SERCOMx_APB Disabled
CLK_TCx_APB Disabled
CLK_ADC_APB Enabled
CLK_AC_APB Disabled
CLK_PTC_APB Disabled
CLK_USB_APB Enabled
CLK_DMAC_APB Enabled
CLK_TCC_APB Disabled
CLK_RFCTRL_APB Disabled
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zUser Reset: Resets caused by the application.
The table below lists the parts of the device that are reset, depending on the reset type.
The external reset is generated when pulling the RESET pin low. This pin has an internal pull-up, and does not need to
be driven externally during normal operation.
The POR, BOD12 and BOD33 reset sources are generated by their corresponding module in the System Controller
Interface (SYSCTRL).
The WDT reset is generated by the Watchdog Timer.
The System Reset Request (SysResetReq) is a software reset generated by the CPU when asserting the
SYSRESETREQ bit located in the Reset Control register of the CPU (See the ARM® Cortex® Technical Reference
Manual on http://www.arm.com).
Figure 14-3. Reset Controller
Table 14-2. Effects of the Different Reset Events
Power Reset User Reset
POR, BOD12, BOD33 External Reset
WDT Reset,
SysResetReq
RTC
All the 32kHz sources
WDT with ALWAYSON feature
Generic Clock with WRTLOCK
feature
Y N N
Debug logic Y Y N
Others Y Y Y
RESET CONTROLLER
BOD12
BOD33
POR
WDT
RESET
RESET SOURCES
RTC
32kHz clock sources
WDT with ALWAYSON
Generic Clock with
WRTLOCK
Debug Logic
Others
CPU
RCAUSE
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14.6.2.8 Sleep Mode Controller
Sleep mode is activated by the Wait For Interrupt instruction (WFI). The Idle bits in the Sleep Mode register
(SLEEP.IDLE) and the SLEEPDEEP bit of the System Control register of the CPU should be used as argument to select
the level of the sleep mode.
There are two main types of sleep mode:
zIDLE mode: The CPU is stopped. Optionally, some synchronous clock domains are stopped, depending on the
IDLE argument. Regulator operates in normal mode.
zSTANDBY mode: All clock sources are stopped, except those where the RUNSTDBY bit is set. Regulator operates
in low-power mode. Before entering standby mode the user must make sure that a significant amount of clocks
and peripherals are disabled, so that the voltage regulator is not overloaded.
Notes: 1. Asynchronous: interrupt generated on generic clock or external clock or external event.
2. Synchronous: interrupt generated on the APB clock.
IDLE Mode
The IDLE modes allow power optimization with the fastest wake-up time.
The CPU is stopped. To further reduce power consumption, the user can disable the clocking of modules and clock
sources by configuring the SLEEP.IDLE bit group. The module will be halted regardless of the bit settings of the mask
registers in the Power Manager (PM.AHBMASK, PM.APBxMASK).
Regulator operates in normal mode.
Table 14-3. Sleep Mode Entry and Exit Table
Mode Level Mode Entry Wake-Up Sources
IDLE
0SCR.SLEEPDEEP = 0
SLEEP.IDLE=Level
WFI
Synchronous(2) (APB, AHB), asynchronous(1)
1Synchronous (APB), asynchronous
2Asynchronous
STANDBY SCR.SLEEPDEEP = 1
WFI Asynchronous
Table 14-4. Sleep Mode Overview
Sleep
Mode
CPU
Clock
AHB
Clock
APB
Clock
Oscillators Main
Clock
Regulator
Mode
RAM
Mode
ONDEMAND = 0 ONDEMAND = 1
RUNSTDBY=0 RUNSTDBY=1 RUNSTDBY=0 RUNSTDBY=1
Idle 0 Stop Run Run Run Run Run if
requested
Run if
requested Run Normal Normal
Idle 1 Stop Stop Run Run Run Run if
requested
Run if
requested Run Normal Normal
Idle 2 Stop Stop Stop Run Run Run if
requested
Run if
requested Run Normal Normal
Standby Stop Stop Stop Stop Run Stop Run if
requested Stop Low
power
Low
power
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zEntering IDLE mode: The IDLE mode is entered by executing the WFI instruction. Additionally, if the
SLEEPONEXIT bit in the ARM Cortex System Control register (SCR) is set, the IDLE mode will also be entered
when the CPU exits the lowest priority ISR. This mechanism can be useful for applications that only require the
processor to run when an interrupt occurs. Before entering the IDLE mode, the user must configure the IDLE mode
configuration bit group and must write a zero to the SCR.SLEEPDEEP bit.
zExiting IDLE mode: The processor wakes the system up when it detects the occurrence of any interrupt that is not
masked in the NVIC Controller with sufficient priority to cause exception entry. The system goes back to the
ACTIVE mode. The CPU and affected modules are restarted.
STANDBY Mode
The STANDBY mode allows achieving very low power consumption.
In this mode, all clocks are stopped except those which are kept running if requested by a running module or have the
ONDEMAND bit set to zero. For example, the RTC can operate in STANDBY mode. In this case, its Generic Clock clock
source will also be enabled.
The regulator and the RAM operate in low-power mode.
A SLEEPONEXIT feature is also available.
zEntering STANDBY mode: This mode is entered by executing the WFI instruction with the SCR.SLEEPDEEP bit of
the CPU is written to 1.
zExiting STANDBY mode: Any peripheral able to generate an asynchronous interrupt can wake up the system. For
example, a module running on a Generic clock can trigger an interrupt. When the enabled asynchronous wake-up
event occurs and the system is woken up, the device will either execute the interrupt service routine or continue
the normal program execution according to the Priority Mask Register (PRIMASK) configuration of the CPU.
14.6.3 SleepWalking
SleepWalking is the capability for a device to temporarily wakeup clocks for peripheral to perform a task without waking-
up the CPU in STANDBY sleep mode. At the end of the sleepwalking task, the device can either be waken-up by an
interrupt (from a peripheral involved in SleepWalking) or enter again into STANDBY sleep mode.
In Atmel | SMART SAM R21 devices, SleepWalking is supported only on GCLK clocks by using the on-demand clock
principle of the clock sources. Refer to “On-demand, Clock Requests” on page 88 for more details.
14.6.4 DMA Operation
Not applicable.
14.6.5 Interrupts
The peripheral has the following interrupt sources:
zClock Ready flag
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
(INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one
to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a one to the
corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the interrupt
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is
cleared, the interrupt is disabled or the peripheral is reset. An interrupt flag is cleared by writing a one to the
corresponding bit in the INTFLAG register. Each peripheral can have one interrupt request line per interrupt source or
one common interrupt request line for all the interrupt sources. Refer to “Nested Vector Interrupt Controller” on page 29
for details. If the peripheral has one common interrupt request line for all the interrupt sources, the user must read the
INTFLAG register to determine which interrupt condition is present.
14.6.6 Events
Not applicable.
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14.6.7 Sleep Mode Operation
In all IDLE sleep modes, the power manager is still running on the selected main clock.
In STANDDBY sleep mode, the power manager is frozen and is able to go back to ACTIVE mode upon any
asynchronous interrupt.
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14.7 Register Summary
Table 14-5. Register Summary
Offset Name
Bit
Pos.
0x00 CTRL 7:0
0x01 SLEEP 7:0 IDLE[1:0]
0x02
...
0x07
Reserved
0x08 CPUSEL 7:0 CPUDIV[2:0]
0x09 APBASEL 7:0 APBADIV[2:0]
0x0A APBBSEL 7:0 APBBDIV[2:0]
0x0B APBCSEL 7:0 APBCDIV[2:0]
0x0C
...
0x13
Reserved
0x14
AHBMASK
7:0 USB DMAC NVMCTRL DSU HPB2 HPB1 HPB0
0x15 15:8
0x16 23:16
0x17 31:24
0x18
APBAMASK
7:0 EIC RTC WDT GCLK SYSCTRL PM PAC0
0x19 15:8
0x1A 23:16
0x1B 31:24
0x1C
APBBMASK
7:0 USB DMAC PORT NVMCTRL DSU PAC1
0x1D 15:8
0x1E 23:16
0x1F 31:24
0x20
APBCMASK
7:0 SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS PAC2
0x21 15:8 TC5 TC4 TC3 TCC2 TCC1 TCC0
0x22 23:16 RFCTRL PTC AC ADC
0x23 31:24
0x24
...
0x33
Reserved
0x34 INTENCLR 7:0 CKRDY
0x35 INTENSET 7:0 CKRDY
0x36 INTFLAG 7:0 CKRDY
0x37 Reserved
0x38 RCAUSE 7:0 SYST WDT EXT BOD33 BOD12 POR
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14.8 Register Description
Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters
and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Exception for APBASEL, APBBSEL and APBCSEL: These registers must only be accessed with 8-bit access.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by
the Write-Protected property in each individual register description. Refer to “Register Access Protection” on page 114
for details.
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14.8.1 Control
Name: CTRL
Offset: 0x00
Reset: 0x00
Property: Write-Protected
zBits 7:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit 76543210
AccessRRRRRRRR
Reset00000000
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14.8.2 Sleep Mode
Name: SLEEP
Offset: 0x01
Reset: 0x00
Property: Write-Protected
zBits 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 1:0 – IDLE[1:0]: Idle Mode Configuration
These bits select the Idle mode configuration after a WFI instruction.
Table 14-6. Idle Mode Configuration
Bit 76543210
IDLE[1:0]
AccessRRRRRRR/WR/W
Reset00000000
IDLE[1:0] Name Description
0x0 CPU The CPU clock domain is stopped
0x1 AHB The CPU and AHB clock domains are stopped
0x2 APB The CPU, AHB and APB clock domains are stopped
0x3 Reserved
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14.8.3 CPU Clock Select
Name: CPUSEL
Offset: 0x08
Reset: 0x00
Property: Write-Protected
zBits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 2:0 – CPUDIV[2:0]: CPU Prescaler Selection
These bits define the division ratio of the main clock prescaler (2n).
Table 14-7. CPU Prescaler Selection
Bit 76543210
CPUDIV[2:0]
AccessRRRRRR/WR/WR/W
Reset00000000
CPUDIV[2:0] Name Description
0x0 DIV1 Divide by 1
0x1 DIV2 Divide by 2
0x2 DIV4 Divide by 4
0x3 DIV8 Divide by 8
0x4 DIV16 Divide by 16
0x5 DIV32 Divide by 32
0x6 DIV64 Divide by 64
0x7 DIV128 Divide by 128
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14.8.4 APBA Clock Select
Name: APBASEL
Offset: 0x09
Reset: 0x00
Property: Write-Protected
zBits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 2:0 – APBADIV[2:0]: APBA Prescaler Selection
These bits define the division ratio of the APBA clock prescaler (2n).
Table 14-8. APBA Prescaler Selection
Bit 76543210
APBADIV[2:0]
AccessRRRRRR/WR/WR/W
Reset00000000
APBADIV[2:0] Name Description
0x0 DIV1 Divide by 1
0x1 DIV2 Divide by 2
0x2 DIV4 Divide by 4
0x3 DIV8 Divide by 8
0x4 DIV16 Divide by 16
0x5 DIV32 Divide by 32
0x6 DIV64 Divide by 64
0x7 DIV128 Divide by 128
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14.8.5 APBB Clock Select
Name: APBBSEL
Offset: 0x0A
Reset: 0x00
Property: Write-Protected
zBits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 2:0 – APBBDIV[2:0]: APBB Prescaler Selection
These bits define the division ratio of the APBB clock prescaler (2n).
Table 14-9. APBB Prescaler Selection
Bit 76543210
APBBDIV[2:0]
AccessRRRRRR/WR/WR/W
Reset00000000
APBBDIV[2:0] Name Description
0x0 DIV1 Divide by 1
0x1 DIV2 Divide by 2
0x2 DIV4 Divide by 4
0x3 DIV8 Divide by 8
0x4 DIV16 Divide by 16
0x5 DIV32 Divide by 32
0x6 DIV64 Divide by 64
0x7 DIV128 Divide by 128
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14.8.6 APBC Clock Select
Name: APBCSEL
Offset: 0x0B
Reset: 0x00
Property: Write-Protected
zBits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 2:0 – APBCDIV[2:0]: APBC Prescaler Selection
These bits define the division ratio of the APBC clock prescaler (2n).
Table 14-10. APBC Prescaler Selection
Bit 76543210
APBCDIV[2:0]
AccessRRRRRR/WR/WR/W
Reset00000000
APBCDIV[2:0] Name Description
0x0 DIV1 Divide by 1
0x1 DIV2 Divide by 2
0x2 DIV4 Divide by 4
0x3 DIV8 Divide by 8
0x4 DIV16 Divide by 16
0x5 DIV32 Divide by 32
0x6 DIV64 Divide by 64
0x7 DIV128 Divide by 128
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14.8.7 AHB Mask
Name: AHBMASK
Offset: 0x14
Reset: 0x0000007F
Property: Write-Protected
zBits 31:7 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 6 – USB: USB AHB Clock Mask
0: The AHB clock for the USB is stopped.
1: The AHB clock for the USB is enabled.
zBit 5 – DMAC: DMAC AHB Clock Mask
0: The AHB clock for the DMAC is stopped.
1: The AHB clock for the DMAC is enabled.
zBit 4 – NVMCTRL: NVMCTRL AHB Clock Mask
0: The AHB clock for the NVMCTRL is stopped.
1: The AHB clock for the NVMCTRL is enabled.
zBit 3 – DSU: DSU AHB Clock Mask
0: The AHB clock for the DSU is stopped.
1: The AHB clock for the DSU is enabled.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
AccessRRRRRRRR
Reset00000000
Bit 151413121110 9 8
AccessRRRRRRRR
Reset00000000
Bit 76543210
USB DMAC NVMCTRL DSU HPB2 HPB1 HPB0
Access R R/W R/W R/W R/W R/W R/W R/W
Reset01111111
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zBit 2 – HPB2: HPB2 AHB Clock Mask
0: The AHB clock for the HPB2 is stopped.
1: The AHB clock for the HPB2 is enabled.
zBit 1 – HPB1: HPB1 AHB Clock Mask
0: The AHB clock for the HPB1 is stopped.
1: The AHB clock for the HPB1 is enabled.
zBit 0 – HPB0: HPB0 AHB Clock Mask
0: The AHB clock for the HPB0 is stopped.
1: The AHB clock for the HPB0 is enabled.
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14.8.8 APBA Mask
Name: APBAMASK
Offset: 0x18
Reset: 0x0000007F
Property: Write-Protected
zBits 31:7 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 6 – EIC: EIC APB Clock Enable
0: The APBA clock for the EIC is stopped.
1: The APBA clock for the EIC is enabled.
zBit 5 – RTC: RTC APB Clock Enable
0: The APBA clock for the RTC is stopped.
1: The APBA clock for the RTC is enabled.
zBit 4 – WDT: WDT APB Clock Enable
0: The APBA clock for the WDT is stopped.
1: The APBA clock for the WDT is enabled.
zBit 3 – GCLK: GCLK APB Clock Enable
0: The APBA clock for the GCLK is stopped.
1: The APBA clock for the GCLK is enabled.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
AccessRRRRRRRR
Reset00000000
Bit 151413121110 9 8
AccessRRRRRRRR
Reset00000000
Bit 76543210
EIC RTC WDT GCLK SYSCTRL PM PAC0
Access R R/W R/W R/W R/W R/W R/W R/W
Reset01111111
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zBit 2 – SYSCTRL: SYSCTRL APB Clock Enable
0: The APBA clock for the SYSCTRL is stopped.
1: The APBA clock for the SYSCTRL is enabled.
zBit 1 – PM: PM APB Clock Enable
0: The APBA clock for the PM is stopped.
1: The APBA clock for the PM is enabled.
zBit 0 – PAC0: PAC0 APB Clock Enable
0: The APBA clock for the PAC0 is stopped.
1: The APBA clock for the PAC0 is enabled.
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14.8.9 APBB Mask
Name: APBBMASK
Offset: 0x1C
Reset: 0x0000007F
Property: Write-Protected
zBits 31:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 5 – USB: USB APB Clock Enable
0: The APBB clock for the USB is stopped.
1: The APBB clock for the USB is enabled.
zBit 4 – DMAC: DMAC APB Clock Enable
0: The APBB clock for the DMAC is stopped.
1: The APBB clock for the DMAC is enabled.
zBit 3 – PORT: PORT APB Clock Enable
0: The APBB clock for the PORT is stopped.
1: The APBB clock for the PORT is enabled.
zBit 2 – NVMCTRL: NVMCTRL APB Clock Enable
0: The APBB clock for the NVMCTRL is stopped.
1: The APBB clock for the NVMCTRL is enabled.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
AccessRRRRRRRR
Reset00000000
Bit 151413121110 9 8
AccessRRRRRRRR
Reset00000000
Bit 76543210
USB DMAC PORT NVMCTRL DSU PAC1
Access R R R/W R/W R/W R/W R/W R/W
Reset00111111
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zBit 1 – DSU: DSU APB Clock Enable
0: The APBB clock for the DSU is stopped.
1: The APBB clock for the DSU is enabled.
zBit 0 – PAC1: PAC1 APB Clock Enable
0: The APBB clock for the PAC1 is stopped.
1: The APBB clock for the PAC1 is enabled.
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14.8.10 APBC Mask
Name: APBCMASK
Offset: 0x20
Reset: 0x00010000
Property: Write-Protected
zBits 31:22 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 21 – RFCTRL: RFCTRL APB Clock Enable
0: The APBC clock for the RFCTRL is stopped.
1: The APBC clock for the RFCTRL is enabled.
zBit 20 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 19 – PTC: PTC APB Clock Enable
0: The APBC clock for the PTC is stopped.
1: The APBC clock for the PTC is enabled.
zBit 18 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
RFCTRL PTC AC ADC
Access R R R/W R R/W R R/W R/W
Reset00000001
Bit 151413121110 9 8
TC5 TC4 TC3 TCC2 TCC1 TCC0
Access R R R/W R/W R/W R/W R/W R/W
Reset00000000
Bit 76543210
SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS PAC2
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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zBit 17 – AC: AC APB Clock Enable
0: The APBC clock for the AC is stopped.
1: The APBC clock for the AC is enabled.
zBit 16 – ADC: ADC APB Clock Enable
0: The APBC clock for the ADC is stopped.
1: The APBC clock for the ADC is enabled.
zBits 15:14 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 13 – TC5: TC5 APB Clock Enable
0: The APBC clock for the TC5 is stopped.
1: The APBC clock for the TC5 is enabled.
zBit 12 – TC4: TC4 APB Clock Enable
0: The APBC clock for the TC4 is stopped.
1: The APBC clock for the TC4 is enabled.
zBit 11 – TC3: TC3 APB Clock Enable
0: The APBC clock for the TC3 is stopped.
1: The APBC clock for the TC3 is enabled.
zBit 10 – TCC2: TCC2 APB Clock Enable
0: The APBC clock for the TCC2 is stopped.
1: The APBC clock for the TCC2 is enabled.
zBit 9 – TCC1: TCC1 APB Clock Enable
0: The APBC clock for the TCC1 is stopped.
1: The APBC clock for the TCC1 is enabled.
zBit 8 – TCC0: TCC0 APB Clock Enable
0: The APBC clock for the TCC0 is stopped.
1: The APBC clock for the TCC0 is enabled.
zBit 7 – SERCOM5: SERCOM5 APB Clock Enable
0: The APBC clock for the SERCOM5 is stopped.
1: The APBC clock for the SERCOM5 is enabled.
zBit 6 – SERCOM4: SERCOM4 APB Clock Enable
0: The APBC clock for the SERCOM4 is stopped.
1: The APBC clock for the SERCOM4 is enabled.
zBit 5 – SERCOM3: SERCOM3 APB Clock Enable
0: The APBC clock for the SERCOM3 is stopped.
1: The APBC clock for the SERCOM3 is enabled.
zBit 4 – SERCOM2: SERCOM2 APB Clock Enable
0: The APBC clock for the SERCOM2 is stopped.
1: The APBC clock for the SERCOM2 is enabled.
zBit 3 – SERCOM1: SERCOM1 APB Clock Enable
0: The APBC clock for the SERCOM1 is stopped.
1: The APBC clock for the SERCOM1 is enabled.
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zBit 2 – SERCOM0: SERCOM0 APB Clock Enable
0: The APBC clock for the SERCOM0 is stopped.
1: The APBC clock for the SERCOM0 is enabled.
zBit 1 – EVSYS: EVSYS APB Clock Enable
0: The APBC clock for the EVSYS is stopped.
1: The APBC clock for the EVSYS is enabled.
zBit 0 – PAC2: PAC2 APB Clock Enable
0: The APBC clock for the PAC2 is stopped.
1: The APBC clock for the PAC2 is enabled.
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14.8.11 Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set (INTENSET) register.
Name: INTENCLR
Offset: 0x34
Reset: 0x00
Property: Write-Protected
zBits 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 0 – CKRDY: Clock Ready Interrupt Enable
0: The Clock Ready interrupt is disabled.
1: The Clock Ready interrupt is enabled and will generate an interrupt request when the Clock Ready Interrupt flag
is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Clock Ready Interrupt Enable bit and the corresponding interrupt request.
Bit 76543210
CKRDY
AccessRRRRRRRR/W
Reset00000000
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14.8.12 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Name: INTENSET
Offset: 0x35
Reset: 0x00
Property: Write-Protected
zBits 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 0 – CKRDY: Clock Ready Interrupt Enable
0: The Clock Ready interrupt is disabled.
1: The Clock Ready interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Clock Ready Interrupt Enable bit and enable the Clock Ready interrupt.
Bit 76543210
CKRDY
AccessRRRRRRRR/W
Reset00000000
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14.8.13 Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x36
Reset: 0x00
Property: -
zBits 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 0 – CKRDY: Clock Ready
This flag is cleared by writing a one to the flag.
This flag is set when the synchronous CPU and APBx clocks have frequencies as indicated in the CPUSEL and
APBxSEL registers, and will generate an interrupt if INTENCLR/SET.CKRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Clock Ready Interrupt flag.
Bit 76543210
CKRDY
AccessRRRRRRRR/W
Reset00000000
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14.8.14 Reset Cause
Name: RCAUSE
Offset: 0x38
Reset: 0x01
Property: -
zBit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 6 – SYST: System Reset Request
This bit is set if a system reset request has been performed. Refer to the Cortex processor documentation for more
details.
zBit 5 – WDT: Watchdog Reset
This flag is set if a Watchdog Timer reset occurs.
zBit 4 – EXT: External Reset
This flag is set if an external reset occurs.
zBit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 2 – BOD33: Brown Out 33 Detector Reset
This flag is set if a BOD33 reset occurs.
zBit 1 – BOD12: Brown Out 12 Detector Reset
This flag is set if a BOD12 reset occurs.
zBit 0 – POR: Power On Reset
This flag is set if a POR occurs.
Bit 76543210
SYST WDT EXT BOD33 BOD12 POR
AccessRRRRRRRR
Reset00000001
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15. SYSCTRL – System Controller
15.1 Overview
The System Controller (SYSCTRL) provides a user interface to the clock sources, brown out detectors, on-chip voltage
regulator and voltage reference of the device.
Through the interface registers, it is possible to enable, disable, calibrate and monitor the SYSCTRL sub-peripherals.
All sub-peripheral statuses are collected in the Power and Clocks Status register (PCLKSR - refer to PCLKSR). They can
additionally trigger interrupts upon status changes via the INTENSET (INTENSET), INTENCLR (INTENCLR) and
INTFLAG (INTFLAG) registers.
Additionally, BOD33 interrupts can be used to wake up the device from standby mode upon a programmed brown-out
detection.
15.2 Features
z0.4-32MHz Crystal Oscillator (XOSC)
zTunable gain control
zProgrammable start-up time
zCrystal or external input clock on XIN I/O
z32.768kHz Crystal Oscillator (XOSC32K)
zAutomatic or manual gain control
zProgrammable start-up time
zCrystal or external input clock on XIN32 I/O
z32.768kHz High Accuracy Internal Oscillator (OSC32K)
zFrequency fine tuning
zProgrammable start-up time
z32.768kHz Ultra Low Power Internal Oscillator (OSCULP32K)
zUltra low power, always-on oscillator
zFrequency fine tuning
zCalibration value loaded from Flash Factory Calibration at reset
z8MHz Internal Oscillator (OSC8M)
zFast startup
zOutput frequency fine tuning
z4/2/1MHz divided output frequencies available
zCalibration value loaded from Flash Factory Calibration at reset
zDigital Frequency Locked Loop (DFLL48M)
zInternal oscillator with no external components
z48MHz output frequency
zOperates standalone as a high-frequency programmable oscillator in open loop mode
zOperates as an accurate frequency multiplier against a known frequency in closed loop mode
zFractional Digital Phase Locked Loop (FDPLL96M)
z48MHz to 96MHz output clock frequency
z32KHz to 2MHz input reference clock frequency range
zThree possible sources for the reference clock
zAdjustable proportional integral controller
zFractional part used to achieve 1/16th of reference clock step
z3.3V Brown-Out Detector (BOD33)
zProgrammable threshold
zThreshold value loaded from Flash User Calibration at startup
zTriggers resets or interrupts
zOperating modes:
zContinuous mode
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zSampled mode for low power applications (programmable refresh frequency)
zHysteresis
zInternal Voltage Regulator system (VREG)
zOperating modes:
zNormal mode
zLow-power mode
zWith an internal non-configurable Brown-out detector (BOD12)
zVoltage Reference System (VREF)
zBandgap voltage generator with programmable calibration value
zTemperature sensor
zBandgap calibration value loaded from Flash Factory Calibration at startup
15.3 Block Diagram
Figure 15-1. SYSCTRL Block Diagram
XOSC
XOSC
32K
OSC3
2K
OSCU
LP
3
2
K
O
SC8
M
D
FLL48M
VO
LTA
GE
R
EFEREN
CE
S
Y
S
TEM
OSC
ILLAT
O
R
S
CO
NTR
O
L
P
O
WE
R
MO
NIT
O
R
CO
NTR
OL
V
O
LTA
G
E
REFEREN
C
E
CO
NTR
O
L
S
TATU
S
(
PCLKSR re
g
ister
)
I
NTERRUPT
S
G
ENERAT
OR
B
O
D3
3
I
nterru
p
t
s
S
Y
SC
TR
L
F
DPLL
96M
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15.4 Signal Description
The I/O lines are automatically selected when XOSC or XOSC32K are enabled. Refer to “Oscillator Pinout” on page 14.
15.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
15.5.1 I/O Lines
I/O lines are configured by SYSCTRL when either XOSC or XOSC32K are enabled, and need no user configuration.
15.5.2 Power Management
The SYSCTRL can continue to operate in any sleep mode where the selected source clock is running. The SYSCTRL
interrupts can be used to wake up the device from sleep modes. The events can trigger other operations in the system
without exiting sleep modes. Refer to “PM – Power Manager” on page 112 for details on the different sleep modes.
15.5.3 Clocks
The SYSCTRL gathers controls for all device oscillators and provides clock sources to the Generic Clock Controller
(GCLK). The available clock sources are: XOSC, XOSC32K, OSC32K, OSCULP32K, OSC8M, DFLL48M and
FDPLL96M.
The SYSCTRL bus clock (CLK_SYSCTRL_APB) can be enabled and disabled in the Power Manager, and the default
state of CLK_SYSCTRL_APB can be found in the Peripheral Clock Masking section in the “PM – Power Manager” on
page 112.
The clock used by BOD33in sampled mode is asynchronous to the user interface clock (CLK_SYSCTRL_APB).
Likewise, the DFLL48M control logic uses the DFLL oscillator output, which is also asynchronous to the user interface
clock (CLK_SYSCTRL_APB). Due to this asynchronicity, writes to certain registers will require synchronization between
the clock domains. Refer to “Synchronization” on page 159 for further details.
15.5.4 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the SYSCTRL interrupts requires the Interrupt
Controller to be configured first. Refer to “Nested Vector Interrupt Controller” on page 29 for details.
15.5.5 Debug Operation
When the CPU is halted in debug mode, the SYSCTRL continues normal operation. If the SYSCTRL is configured in a
way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss
may result during debugging.
If a debugger connection is detected by the system, BOD33 reset will be blocked.
Signal Name Types Description
XIN Analog Input Multipurpose Crystal Oscillator or external
clock generator input
XOUT Analog Output External Multipurpose Crystal Oscillator
output
XIN32 Analog Input 32kHz Crystal Oscillator or external clock
generator input
XOUT32 Analog Output 32kHz Crystal Oscillator output
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15.5.6 Register Access Protection
All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the
following registers:
zInterrupt Flag Status and Clear register (INTFLAG - refer to INTFLAG)
Write-protection is denoted by the Write-Protection property in the register description.
When the CPU is halted in debug mode, all write-protection is automatically disabled.
Write-protection does not apply for accesses through an external debugger. Refer to “PAC – Peripheral Access
Controller” on page 36 for details.
15.5.7 Analog Connections
When used, the 32.768kHz crystal must be connected between the XIN32 and XOUT32 pins, and the 0.4-32MHz crystal
must be connected between the XIN and XOUT pins, along with any required load capacitors. For details on
recommended oscillator characteristics and capacitor load, refer to the “Electrical Characteristics” on page 1055 for
details.
15.6 Functional Description
15.6.1 Principle of Operation
XOSC, XOSC32K, OSC32K, OSCULP32K, OSC8M, DFLL48M, FDPLL96M, BOD33, and VREF are configured via
SYSCTRL control registers. Through this interface, the sub-peripherals are enabled, disabled or have their calibration
values updated.
The Power and Clocks Status register gathers different status signals coming from the sub-peripherals controlled by the
SYSCTRL. The status signals can be used to generate system interrupts, and in some cases wake up the system from
standby mode, provided the corresponding interrupt is enabled.
The oscillator must be enabled to run. The oscillator is enabled by writing a one to the ENABLE bit in the respective
oscillator control register, and disabled by writing a zero to the oscillator control register. In idle mode, the default
operation of the oscillator is to run only when requested by a peripheral. In standby mode, the default operation of the
oscillator is to stop. This behavior can be changed by the user, see below for details.
The behavior of the oscillators in the different sleep modes is shown in Table 15-1 on page 146
To force an oscillator to always run in idle mode, and not only when requested by a peripheral, the oscillator
ONDEMAND bit must be written to zero. The default value of this bit is one, and thus the default operation in idle mode is
to run only when requested by a peripheral.
Table 15-1. Behavior of the Oscillators
Oscillator Idle 0, 1, 2 Standby
XOSC Run on request Stop
XOSC32K Run on request Stop
OSC32K Run on request Stop
OSCULP32K Run Run
OSC8M Run on request Stop
DFLL48M Run on request Stop
FDPLL96M Run on request Stop
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To force the oscillator to run in standby mode, the RUNSTDBY bit must be written to one. The oscillator will then run in
standby mode when requested by a peripheral (ONDEMAND is one). To force an oscillator to always run in standby
mode, and not only when requested by a peripheral, the ONDEMAND bit must be written to zero and RUNSTDBY must
be written to one.
Table 15-2 on page 147 shows the behavior in the different sleep modes, depending on the settings of ONDEMAND and
RUNSTDBY.
Note that this does not apply to the OSCULP32K oscillator, which is always running and cannot be disabled.
15.6.2 External Multipurpose Crystal Oscillator (XOSC) Operation
The XOSC can operate in two different modes:
zExternal clock, with an external clock signal connected to the XIN pin
zCrystal oscillator, with an external 0.4-32MHz crystal
The XOSC can be used as a clock source for generic clock generators, as described in the “GCLK – Generic Clock
Controller” on page 90.
At reset, the XOSC is disabled, and the XIN/XOUT pins can be used as General Purpose I/O (GPIO) pins or by other
peripherals in the system. When XOSC is enabled, the operating mode determines the GPIO usage. When in crystal
oscillator mode, the XIN and XOUT pins are controlled by the SYSCTRL, and GPIO functions are overridden on both
pins. When in external clock mode, only the XIN pin will be overridden and controlled by the SYSCTRL, while the XOUT
pin can still be used as a GPIO pin.
The XOSC is enabled by writing a one to the Enable bit in the External Multipurpose Crystal Oscillator Control register
(XOSC.ENABLE). To enable the XOSC as a crystal oscillator, a one must be written to the XTAL Enable bit
(XOSC.XTALEN). If XOSC.XTALEN is zero, external clock input will be enabled.
When in crystal oscillator mode (XOSC.XTALEN is one), the External Multipurpose Crystal Oscillator Gain (XOSC.GAIN)
must be set to match the external crystal oscillator frequency. If the External Multipurpose Crystal Oscillator Automatic
Amplitude Gain Control (XOSC.AMPGC) is one, the oscillator amplitude will be automatically adjusted, and in most
cases result in a lower power consumption.
The XOSC will behave differently in different sleep modes based on the settings of XOSC.RUNSTDBY,
XOSC.ONDEMAND and XOSC.ENABLE:
Table 15-2. Behavior in the different sleep modes
Sleep mode ONDEMAND RUNSTDBY Behavior
Idle 0, 1, 2 0 X Run
Idle 0, 1, 2 1 X Run when requested by a peripheral
Standby 0 0 Stop
Standby 0 1 Run
Standby 1 0 Stop
Standby 1 1 Run when requested by a peripheral
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After a hard reset, or when waking up from a sleep mode where the XOSC was disabled, the XOSC will need a certain
amount of time to stabilize on the correct frequency. This start-up time can be configured by changing the Oscillator
Start-Up Time bit group (XOSC.STARTUP) in the External Multipurpose Crystal Oscillator Control register. During the
start-up time, the oscillator output is masked to ensure that no unstable clock propagates to the digital logic. The External
Multipurpose Crystal Oscillator Ready bit in the Power and Clock Status register (PCLKSR.XOSCRDY) is set when the
user-selected startup time is over. An interrupt is generated on a zero-to-one transition on PCLKSR.XOSCRDY if the
External Multipurpose Crystal Oscillator Ready bit in the Interrupt Enable Set register (INTENSET.XOSCRDY) is set.
Note: Do not enter standby mode when an oscillator is in startup:
Wait for the OSCxRDY bit in SYSCTRL.PCLKSR register to be set before going into standby mode.
15.6.3 32kHz External Crystal Oscillator (XOSC32K) Operation
The XOSC32K can operate in two different modes:
zExternal clock, with an external clock signal connected to XIN32
zCrystal oscillator, with an external 32.768kHz crystal connected between XIN32 and XOUT32
The XOSC32K can be used as a source for generic clock generators, as described in the “GCLK – Generic Clock
Controller” on page 90.
At power-on reset (POR) the XOSC32K is disabled, and the XIN32/XOUT32 pins can be used as General Purpose I/O
(GPIO) pins or by other peripherals in the system. When XOSC32K is enabled, the operating mode determines the GPIO
usage. When in crystal oscillator mode, XIN32 and XOUT32 are controlled by the SYSCTRL, and GPIO functions are
overridden on both pins. When in external clock mode, only the XIN32 pin will be overridden and controlled by the
SYSCTRL, while the XOUT32 pin can still be used as a GPIO pin.
The external clock or crystal oscillator is enabled by writing a one to the Enable bit (XOSC32K.ENABLE) in the 32kHz
External Crystal Oscillator Control register. To enable the XOSC32K as a crystal oscillator, a one must be written to the
XTAL Enable bit (XOSC32K.XTALEN). If XOSC32K.XTALEN is zero, external clock input will be enabled.
The oscillator is disabled by writing a zero to the Enable bit (XOSC32K.ENABLE) in the 32kHz External Crystal Oscillator
Control register while keeping the other bits unchanged. Writing to the XOSC32K.ENABLE bit while writing to other bits
may result in unpredictable behavior. The oscillator remains enabled in all sleep modes if it has been enabled
beforehand. The start-up time of the 32kHz External Crystal Oscillator is selected by writing to the Oscillator Start-Up
Time bit group (XOSC32K.STARTUP) in the in the 32kHz External Crystal Oscillator Control register. The SYSCTRL
masks the oscillator output during the start-up time to ensure that no unstable clock propagates to the digital logic. The
32kHz External Crystal Oscillator Ready bit (PCLKSR.XOSC32KRDY) in the Power and Clock Status register is set
when the user-selected startup time is over. An interrupt is generated on a zero-to-one transition of
PCLKSR.XOSC32KRDY if the 32kHz External Crystal Oscillator Ready bit (INTENSET.XOSC32KRDY) in the Interrupt
Enable Set Register is set.
As a crystal oscillator usually requires a very long start-up time (up to one second), the 32kHz External Crystal Oscillator
will keep running across resets, except for power-on reset (POR).
XOSC.RUNSTDBY XOSC.ONDEMAND XOSC.ENABLE Sleep Behavior
- - 0 Disabled
0 0 1 Always run in IDLE sleep modes.
Disabled in STANDBY sleep mode.
0 1 1
Only run in IDLE sleep modes if
requested by a peripheral. Disabled in
STANDBY sleep mode.
1 0 1 Always run in IDLE and STANDBY sleep
modes.
1 1 1 Only run in IDLE or STANDBY sleep
modes if requested by a peripheral.
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XOSC32K can provide two clock outputs when connected to a crystal. The XOSC32K has a 32.768kHz output enabled
by writing a one to the 32kHz External Crystal Oscillator 32kHz Output Enable bit (XOSC32K.EN32K) in the 32kHz
External Crystal Oscillator Control register. XOSC32K.EN32K is only usable when XIN32 is connected to a crystal, and
not when an external digital clock is applied on XIN32.
Note: Do not enter standby mode when an oscillator is in startup:
Wait for the OSCxRDY bit in SYSCTRL.PCLKSR register to be set before going into standby mode.
15.6.4 32kHz Internal Oscillator (OSC32K) Operation
The OSC32K provides a tunable, low-speed and low-power clock source.
The OSC32K can be used as a source for the generic clock generators, as described in the “GCLK – Generic Clock
Controller” on page 90.
The OSC32K is disabled by default. The OSC32K is enabled by writing a one to the 32kHz Internal Oscillator Enable bit
(OSC32K.ENABLE) in the 32kHz Internal Oscillator Control register. It is disabled by writing a zero to OSC32K.ENABLE.
The OSC32K has a 32.768kHz output enabled by writing a one to the 32kHz Internal Oscillator 32kHz Output Enable bit
(OSC32K.EN32K).
The frequency of the OSC32K oscillator is controlled by the value in the 32kHz Internal Oscillator Calibration bits
(OSC32K.CALIB) in the 32kHz Internal Oscillator Control register. The OSC32K.CALIB value must be written by the
user. Flash Factory Calibration values are stored in the NVM Software Calibration Area (refer to “NVM Software
Calibration Area Mapping” on page 26). When writing to the Calibration bits, the user must wait for the
PCLKSR.OSC32KRDY bit to go high before the value is committed to the oscillator.
15.6.5 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Operation
The OSCULP32K provides a tunable, low-speed and ultra-low-power clock source. The OSCULP32K is factory-
calibrated under typical voltage and temperature conditions. The OSCULP32K should be preferred to the OSC32K
whenever the power requirements are prevalent over frequency stability and accuracy.
The OSCULP32K can be used as a source for the generic clock generators, as described in the “GCLK – Generic Clock
Controller” on page 90.
The OSCULP32K is enabled by default after a power-on reset (POR) and will always run except during POR. The
OSCULP32K has a 32.768kHz output and a 1.024kHz output that are always running.
The frequency of the OSCULP32K oscillator is controlled by the value in the 32kHz Ultra Low Power Internal Oscillator
Calibration bits (OSCULP32K.CALIB) in the 32kHz Ultra Low Power Internal Oscillator Control register.
OSCULP32K.CALIB is automatically loaded from Flash Factory Calibration during startup, and is used to compensate for
process variation, as described in the “Electrical Characteristics” on page 1055. The calibration value can be overridden
by the user by writing to OSCULP32K.CALIB.
15.6.6 8MHz Internal Oscillator (OSC8M) Operation
OSC8M is an internal oscillator operating in open-loop mode and generating an 8MHz frequency. The OSC8M is factory-
calibrated under typical voltage and temperature conditions.
OSC8M is the default clock source that is used after a power-on reset (POR). The OSC8M can be used as a source for
the generic clock generators, as described in the “GCLK – Generic Clock Controller” on page 90.
In order to enable OSC8M, the Oscillator Enable bit in the OSC8M Control register (OSC8M.ENABLE) must be written to
one. OSC8M will not be enabled until OSC8M.ENABLE is set. In order to disable OSC8M, OSC8M.ENABLE must be
written to zero. OSC8M will not be disabled until OSC8M is cleared.
The frequency of the OSC8M oscillator is controlled by the value in the calibration bits (OSC8M.CALIB) in the OSC8M
Control register. CALIB is automatically loaded from Flash Factory Calibration during startup, and is used to compensate
for process variation, as described in the “Electrical Characteristics” on page 1055.
The user can control the oscillation frequency by writing to the Frequency Range (FRANGE) and Calibration (CALIB) bit
groups in the 8MHz RC Oscillator Control register (OSC8M). It is not recommended to update the FRANGE and CALIB
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bits when the OSC8M is enabled. As this is in open-loop mode, the frequency will be voltage, temperature and process
dependent. Refer to the “Electrical Characteristics” on page 1055 for details.
OSC8M is automatically switched off in certain sleep modes to reduce power consumption, as described in the “PM –
Power Manager” on page 112.
15.6.7 Digital Frequency Locked Loop (DFLL48M) Operation
The DFLL48M can operate in both open-loop mode and closed-loop mode. In closed-loop mode, a low-frequency clock
with high accuracy can be used as the reference clock to get high accuracy on the output clock (CLK_DFLL48M).
The DFLL48M can be used as a source for the generic clock generators, as described in the “GCLK – Generic Clock
Controller” on page 90.
15.6.7.1 Basic Operation
Open-Loop Operation
After any reset, the open-loop mode is selected. When operating in open-loop mode, the output frequency of the
DFLL48M will be determined by the values written to the DFLL Coarse Value bit group and the DFLL Fine Value bit
group (DFLLVAL.COARSE and DFLLVAL.FINE) in the DFLL Value register. Using "DFLL48M COARSE CAL" value
from “NVM User Row Mapping” on page 25 in DFLL.COARSE helps to output a frequency close to 48 MHz.
It is possible to change the values of DFLLVAL.COARSE and DFLLVAL.FINE and thereby the output frequency of the
DFLL48M output clock, CLK_DFLL48M, while the DFLL48M is enabled and in use. CLK_DFLL48M is ready to be used
when PCLKSR.DFLLRDY is set after enabling the DFLL48M.
Closed-Loop Operation
In closed-loop operation, the output frequency is continuously regulated against a reference clock. Once the
multiplication factor is set, the oscillator fine tuning is automatically adjusted. The DFLL48M must be correctly configured
before closed-loop operation can be enabled. After enabling the DFLL48M, it must be configured in the following way:
1. Enable and select a reference clock (CLK_DFLL48M_REF). CLK_DFLL48M_REF is Generic Clock Channel 0
(GCLK_DFLL48M_REF). Refer to “GCLK – Generic Clock Controller” on page 90 for details.
2. Select the maximum step size allowed in finding the Coarse and Fine values by writing the appropriate values to
the DFLL Coarse Maximum Step and DFLL Fine Maximum Step bit groups (DFLLMUL.CSTEP and DFLL-
MUL.FSTEP) in the DFLL Multiplier register. A small step size will ensure low overshoot on the output frequency,
but will typically result in longer lock times. A high value might give a large overshoot, but will typically provide
faster locking. DFLLMUL.CSTEP and DFLLMUL.FSTEP should not be higher than 50% of the maximum value of
DFLLVAL.COARSE and DFLLVAL.FINE, respectively.
3. Select the multiplication factor in the DFLL Multiply Factor bit group (DFLLMUL.MUL) in the DFLL Multiplier regis-
ter. Care must be taken when choosing DFLLMUL.MUL so that the output frequency does not exceed the
maximum frequency of the DFLL. If the target frequency is below the minimum frequency of the DFLL48M, the out-
put frequency will be equal to the DFLL minimum frequency.
4. Start the closed loop mode by writing a one to the DFLL Mode Selection bit (DFLLCTRL.MODE) in the DFLL Con-
trol register.
The frequency of CLK_DFLL48M (Fclkdfll48m) is given by:
where Fclkdfll48mref is the frequency of the reference clock (CLK_DFLL48M_REF). DFLLVAL.COARSE and
DFLLVAL.FINE are read-only in closed-loop mode, and are controlled by the frequency tuner to meet user specified
frequency. In closed-loop mode, the value in DFLLVAL.COARSE is used by the frequency tuner as a starting point for
Coarse. Writing DFLLVAL.COARSE to a value close to the final value before entering closed-loop mode will reduce the
time needed to get a lock on Coarse.
Using "DFLL48M COARSE CAL" from “NVM User Row Mapping” on page 25 for DFLL.COARSE will start DFLL with a
frequency close to 48 MHz.
Fclkdfll48m DFLLMUL.MUL Fclkdfll48mref
×=
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Following Software sequence should be followed while using the same.
1. load "DFLL48M COARSE CAL" from “NVM User Row Mapping” on page 25 in DFLL.COARSE register
2. Set DFLLCTRL.BPLCKC bit
3. Start DFLL close loop
This procedure will reduce DFLL Lock time to DFLL Fine lock time.
Frequency Locking
The locking of the frequency in closed-loop mode is divided into two stages. In the first, coarse stage, the control logic
quickly finds the correct value for DFLLVAL.COARSE and sets the output frequency to a value close to the correct
frequency. On coarse lock, the DFLL Locked on Coarse Value bit (PCLKSR.DFLLLOCKC) in the Power and Clocks
Status register will be set.
In the second, fine stage, the control logic tunes the value in DFLLVAL.FINE so that the output frequency is very close to
the desired frequency. On fine lock, the DFLL Locked on Fine Value bit (PCLKSR.DFLLLOCKF) in the Power and Clocks
Status register will be set.
Interrupts are generated by both PCLKSR.DFLLLOCKC and PCLKSR.DFLLLOCKF if INTENSET.DFLLOCKC or
INTENSET.DFLLOCKF are written to one.
CLK_DFLL48M is ready to be used when the DFLL Ready bit (PCLKSR.DFLLRDY) in the Power and Clocks Status
register is set, but the accuracy of the output frequency depends on which locks are set. For lock times, refer to the
“Electrical Characteristics” on page 1055.
Frequency Error Measurement
The ratio between CLK_DFLL48M_REF and CLK48M_DFLL is measured automatically when the DFLL48M is in closed-
loop mode. The difference between this ratio and the value in DFLLMUL.MUL is stored in the DFLL Multiplication Ratio
Difference bit group(DFLLVAL.DIFF) in the DFLL Value register. The relative error on CLK_DFLL48M compared to the
target frequency is calculated as follows:
Drift Compensation
If the Stable DFLL Frequency bit (DFLLCTRL.STABLE) in the DFLL Control register is zero, the frequency tuner will
automatically compensate for drift in the CLK_DFLL48M without losing either of the locks. This means that
DFLLVAL.FINE can change after every measurement of CLK_DFLL48M.
The DFLLVAL.FINE value overflows or underflows can occur in close loop mode when the clock source reference drifts
or is unstable. This will set the DFLL Out Of Bounds bit (PCLKSR.DFLLOOB) in the Power and Clocks Status register.
To avoid this error, the reference clock in close loop mode must be stable, an external oscillator is recommended and
internal oscillator forbidden. The better choice is to use an XOSC32K.
Reference Clock Stop Detection
If CLK_DFLL48M_REF stops or is running at a very low frequency (slower than CLK_DFLL48M/(2 * MULMAX)), the DFLL
Reference Clock Stopped bit (PCLKSR.DFLLRCS) in the Power and Clocks Status register will be set. Detecting a
stopped reference clock can take a long time, on the order of 217 CLK_DFLL48M cycles. When the reference clock is
stopped, the DFLL48M will operate as if in open-loop mode. Closed-loop mode operation will automatically resume if the
CLK_DFLL48M_REF is restarted. An interrupt is generated on a zero-to-one transition on PCLKSR.DFLLRCS if the
DFLL Reference Clock Stopped bit (INTENSET.DFLLRCS) in the Interrupt Enable Set register is set.
15.6.7.2 Additional Features
Dealing with Delay in the DFLL in Closed-Loop Mode
The time from selecting a new CLK_DFLL48M frequency until this frequency is output by the DFLL48M can be up to
several microseconds. If the value in DFLLMUL.MUL is small, this can lead to instability in the DFLL48M locking
mechanism, which can prevent the DFLL48M from achieving locks. To avoid this, a chill cycle, during which the
ERROR DIFF
MUL
--------------
=
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CLK_DFLL48M frequency is not measured, can be enabled. The chill cycle is enabled by default, but can be disabled by
writing a one to the DFLL Chill Cycle Disable bit (DFLLCTRL.CCDIS) in the DFLL Control register. Enabling chill cycles
might double the lock time.
Another solution to this problem consists of using less strict lock requirements. This is called Quick Lock (QL), which is
also enabled by default, but it can be disabled by writing a one to the Quick Lock Disable bit (DFLLCTRL.QLDIS) in the
DFLL Control register. The Quick Lock might lead to a larger spread in the output frequency than chill cycles, but the
average output frequency is the same.
USB Clock Recovery Mode
USB Clock Recovery mode can be used to create the 48MHz USB clock from the USB Start Of Frame (SOF). The mode
is enabled by writing a one to the USB Clock Recovery Mode bit in DFLL Control register (DFLLCTRL.USBCRM).
The SOF signal from USB device will be used as reference clock (CLK_DFLL_REF), ignoring the selected generic clock
reference. When the USB device is connected, a SOF will be sent every 1ms, thus DFLLMUL.MUL bits should be written
to 0xBB80 to obtain a 48MHz clock. In USB clock recovery mode, the DFLLCTRL.BPLCKC bit state is ignored and the
value stored in the DFLLVAL.COARSE will be used as COARSE final value. The lock procedure will also go
instantaneously to the fine lock search. The COARSE calibration value can be loaded from NVM OTP row by software.
DFLLCTRL.QLDIS bit must be cleared and DFLLCTRL.CCDIS should be set to speed up the lock phase. The
DFLLCTRL.STABLE bit state is ignored to let an auto jitter reduction mechanism working instead.
Wake from Sleep Modes
DFLL48M can optionally reset its lock bits when it is disabled. This is configured by the Lose Lock After Wake bit
(DFLLCTRL.LLAW) in the DFLL Control register. If DFLLCTRL.LLAW is zero, the DFLL48M will be re-enabled and start
running with the same configuration as before being disabled, even if the reference clock is not available. The locks will
not be lost. When the reference clock has restarted, the Fine tracking will quickly compensate for any frequency drift
during sleep if DFLLCTRL.STABLE is zero. If DFLLCTRL.LLAW is one when the DFLL is turned off, the DFLL48M will
lose all its locks, and needs to regain these through the full lock sequence.
Accuracy
There are three main factors that determine the accuracy of Fclkdfll48m. These can be tuned to obtain maximum accuracy
when fine lock is achieved.
zFine resolution: The frequency step between two Fine values. This is relatively smaller for high output frequencies.
zResolution of the measurement: If the resolution of the measured Fclkdfll48m is low, i.e., the ratio between the
CLK_DFLL48M frequency and the CLK_DFLL48M_REF frequency is small, then the DFLL48M might lock at a
frequency that is lower than the targeted frequency. It is recommended to use a reference clock frequency of
32kHz or lower to avoid this issue for low target frequencies.
zThe accuracy of the reference clock.
15.6.8 FDPLL96M – Fractional Digital Phase-Locked Loop Controller
15.6.8.1 Overview
The FDPLL96M controller allows flexible interface to the core digital function of the Digital Phase Locked Loop (DPLL).
The FDPLL96M integrates a digital filter with a proportional integral controller, a Time-to-Digital Converter (TDC), a test
mode controller, a Digitally Controlled Oscillator (DCO) and a PLL controller. It also provides a fractional multiplier of
frequency N between the input and output frequency.
The CLK_FDPLL96M_REF is the DPLL input clock reference. The selectable sources for the reference clock are
XOSC32K, XOSC and GCLK_DPLL. The path between XOSC and input multiplexer integrates a clock divider.
The selected clock must be configured and enabled before using the FDPLL96M. If the GCLK is selected as reference
clock, it must be configured and enabled in the Generic Clock Controller before using the FDPLL96M. Refer to “GCLK –
Generic Clock Controller” on page 90 for details.If the GCLK_DPLL is selected as the source for the
CLK_FDPLL96M_REF, care must be taken to make sure the source for this GCLK is within the valid frequency range for
the FDPLL96M.
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The XOSC source can be divided inside the FDPLL96M. The user must make sure that the programmable clock divider
and XOSC frequency provides a valid CLK_FDPLL96M_REF clock frequency that meets the FDPLL96M input frequency
range.
The output clock of the FDPLL96M is CLK_FDPLL96M. The state of the CLK_FDPLL96M clock only depends on the
FDPLL96M internal control of the final clock gater CG.
The FDPLL96M requires a 32kHz clock from the GCLK when the FDPLL96M internal lock timer is used. This clock must
be configured and enabled in the Generic Clock Controller before using the FDPLL96M. Refer to “GCLK – Generic Clock
Controller” on page 90 for details.
15.6.8.2 Block Diagram
Figure 15-2. FDPLL96M Block Diagram
15.6.8.3 Principle of Operation
The task of the FDPLL96M is to maintain coherence between the input reference clock signal (CLK_FDPLL96M_REF)
and the respective output frequency CK via phase comparison. The FDPLL96M supports three independent sources of
clocks XOSC32K, XOSC and GCLK_DPLL. When the FDPLL96M is enabled, the relationship between the reference
clock (CLK_FDPLL96M_REF) frequency and the output clock (CLK_FDPLL96M) frequency is defined below.
Where LDR is the loop divider ratio integer part, LDRFRAC is the loop divider ratio fractional part, fckrx is the frequency of
the selected reference clock and fck is the frequency of the FDPLL96M output clock. As previously stated a clock divider
exist between XOSC and CLK_FDPLL96M_REF. The frequency between the two clocks is defined below.
Table 15-3. Generic Clock Input for FDPLL96M
Generic Clock FDPLL96M
FDPLL96M 32kHz clock GCLK_DPLL_32K for internal lock timer
FDPLL96M GCLK_DPLL for CLK_FDPLL96M_REF
TDC Digital
Filter DCO
÷N
XOSC32K
XOSC
CK
%JWJEFS
GCLK_DPLL
$(
CLK_FDPLL96M
User
Interface
CLK_FDPLL96M_REF
GCLK_DPLL_32K
fclk_fdpll96mfclk_fdpll96m_ref LDR 1LDRFRAC
16
----------------------------
++
⎝⎠
⎛⎞
×=
fclk_fdpll96m_ref fxosc
1
2DIV 1+()×
----------------------------------
⎝⎠
⎛⎞
×=
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When the FDPLL96M is disabled, the output clock is reset. If the loop divider ratio fractional part
(DPLLRATIO.LDRFRAC) field is reset, the FDPLL96M works in integer mode, otherwise the fractional mode is activated.
It shall be noted that fractional part has a negative impact on the jitter of the FDPLL96M.
Example (integer mode only): assuming fckr = 32kHz and fck = 48MHz, the multiplication ratio is 1500. It means that LDR
shall be set to 1499.
Example (fractional mode): assuming fckr = 32 kHz and fck = 48.006MHz, the multiplication ratio is 1500.1875 (1500 +
3/16). Thus LDR is set to 1499 and LDRFRAC to 3.
15.6.8.4 Initialization, Enabling, Disabling and Resetting
The FDPLL96M is enabled by writing a one to the Enable bit in the DPLL Control A register (DPLLCTRLA.ENABLE). The
FDPLL96M is disabled by writing a zero to DPLLCTRLA.ENABLE. The frequency of the FDPLL96M output clock CK is
stable when the module is enabled and when the DPLL Lock Status bit in the DPLL Status register
(DPLLSTATUS.LOCK) bit is set. When DPLLCTRLB.LTIME is different from 0, a user defined lock time is used to
validate the lock operation. In this case the lock time is constant. If DPLLCTRLB.LTIME is reset, the lock signal is linked
with the status bit of the DPLL, the lock time vary depending on the filter selection and final target frequency.
When DPLLCTRLB.WUF is set, the wake up fast mode is activated. In that mode the clock gating cell is enabled at the
end of the startup time. At that time, the final frequency is not stable as it is still in the acquisition period, but it allows to
save several milliseconds. After first acquisition, DPLLCTRLB.LBYPASS indicates if the Lock signal is discarded from
the control of the clock gater generating the output clock CLK_FDPLL96M.
Table 15-4. CLK_FDPLL96M behavior from startup to first edge detection.
WUF LTIME CLK_FDPLL96M Behavior
0 0 Normal Mode: First Edge when lock is asserted
0Not Equal To Zero Lock Timer Timeout mode: First Edge when the timer downcounts to 0.
1 X Wake Up Fast Mode: First Edge when CK is active (startup time)
Table 15-5. CLK_FDPLL96M behavior after First Edge detection.
LBYPASS CLK_FDPLL96M Behavior
0Normal Mode: the CLK_FDPLL96M is turned off when lock signal is low.
1Lock Bypass Mode: the CLK_FDPLL96M is always running, lock is irrelevant.
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Figure 15-3. CK and CLK_FDPLL96M Off Mode to Running Mode
Figure 15-4. CK and CLK_FDPLL96M Off Mode to Running Mode when Wake-Up Fast is Activated
Figure 15-5. CK and CLK_FDPLL96M Running Mode to Off Mode
15.6.8.5 Reference Clock Switching
When a software operation requires reference clock switching, the normal operation is to disable the FDPLL96M, modify
the DPLLCTRLB.REFCLK to select the desired reference source and activate the FDPLL96M again.
CKRx
ENABLE
CK
LOCK
$,45"#-&UTUBSUVQ@UJNF UMPDL@UJNF
CLK_FDPLL96M
CKRx
ENABLE
CK
LOCK
$,45"#-&UTUBSUVQ@UJNF UMPDL@UJNF
CLK_FDPLL96M
CKRx
ENABLE
CK
LOCK
CLK_FDPLL96M
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15.6.8.6 Loop Divider Ratio updates
The FDPLL96M supports on-the-fly update of the DPLLRATIO register, so it is allowed to modify the loop divider ratio
and the loop divider ratio fractional part when the FDPLL96M is enabled. At that time, the DPLLSTATUS.LOCK bit is
cleared and set again by hardware when the output frequency reached a stable state. The DPLL Lock Fail bit in the
Interrupt Flag Status and Clear register (INTFLAG.DPLLLCK) is set when a falling edge has been detected. The flag is
cleared when the software write a one to the interrupt flag bit location.
Figure 15-6. RATIOCTRL Register Update Operation
15.6.8.7 Digital Filter Selection
The PLL digital filter (PI controller) is automatically adjusted in order to provide a good compromise between stability and
jitter. Nevertheless a software operation can override the filter setting using the DPLLCTRLB.FILTER field. The
DPLLCTRLB.LPEN field can be use to bypass the TDC module.
15.6.9 3.3V Brown-Out Detector Operation
The 3.3V BOD monitors the 3.3V VDDANA supply (BOD33). It supports continuous or sampling modes.
The threshold value action (reset the device or generate an interrupt), the Hysteresis configuration, as well as the
enable/disable settings are loaded from Flash User Calibration at startup, and can be overridden by writing to the
corresponding BOD33 register bit groups.
15.6.9.1 3.3V Brown-Out Detector (BOD33)
The 3.3V Brown-Out Detector (BOD33) monitors the VDDANA supply and compares the voltage with the brown-out
threshold level set in the BOD33 Level bit group (BOD33.LEVEL) in the BOD33 register. The BOD33 can generate either
an interrupt or a reset when VDDANA crosses below the brown-out threshold level. The BOD33 detection status can be
read from the BOD33 Detection bit (PCLKSR.BOD33DET) in the Power and Clocks Status register.
At startup or at power-on reset (POR), the BOD33 register values are loaded from the Flash User Row. Refer to “NVM
User Row Mapping” on page 25 for more details.
15.6.9.2 Continuous Mode
When the BOD33 Mode bit (BOD33.MODE) in the BOD33 register is written to zero and the BOD33 is enabled, the
BOD33 operates in continuous mode. In this mode, the BOD33 is continuously monitoring the VDDANA supply voltage.
Continuous mode is the default mode for BOD33.
CKRx
LDR
LDRFRAC
CK
CLK_FDPLL96M
mult0 mult1
LOCK
LOCKL
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15.6.9.3 Sampling Mode
The sampling mode is a low-power mode where the BOD33 is being repeatedly enabled on a sampling clock’s ticks. The
BOD33 will monitor the supply voltage for a short period of time and then go to a low-power disabled state until the next
sampling clock tick.
Sampling mode is enabled by writing one to BOD33.MODE. The frequency of the clock ticks (Fclksampling) is controlled by
the BOD33 Prescaler Select bit group (BOD33.PSEL) in the BOD33 register.
The prescaler signal (Fclkprescaler) is a 1kHz clock, output from the32kHz Ultra Low Power Oscillator, OSCULP32K.
As the sampling mode clock is different from the APB clock domain, synchronization among the clocks is necessary.
Figure 15-7 shows a block diagram of the sampling mode. The BOD33Synchronization Ready bits (PCLKSR.B33SRDY)
in the Power and Clocks Status register show the synchronization ready status of the synchronizer. Writing attempts to
the BOD33 register are ignored while PCLKSR.B33SRDY is zero.
Figure 15-7. Sampling Mode Block diagram
The BOD33 Clock Enable bit (BOD33.CEN) in the BOD33 register should always be disabled before changing the
prescaler value. To change the prescaler value for the BOD33 during sampling mode, the following steps need to be
taken:
1. Wait until the PCLKSR.B33SRDY bit is set.
2. Write the selected value to the BOD33.PSEL bit group.
15.6.9.4 Hysteresis
The hysteresis functionality can be used in both continuous and sampling mode. Writing a one to the BOD33 Hysteresis
bit (BOD33.HYST) in the BOD33 register will add hysteresis to the BOD33 threshold level.
15.6.10 Voltage Reference System Operation
The Voltage Reference System (VREF) consists of a Bandgap Reference Voltage Generator and a temperature sensor.
The Bandgap Reference Voltage Generator is factory-calibrated under typical voltage and temperature conditions.
At reset, the VREF.CAL register value is loaded from Flash Factory Calibration.
The temperature sensor can be used to get an absolute temperature in the temperature range of CMIN to CMAX
degrees Celsius. The sensor will output a linear voltage proportional to the temperature. The output voltage and
Fclksampling
Fclkprescaler
2PSEL 1+()
------------------------------
=
US
ER INTERFA
CE
R
E
G
I
S
TER
S
(
APB clock domain
)
P
RE
SC
ALE
R
(
clk_prescale
r
domain
)
S
YN
C
HR
O
NIZER
P
S
EL
C
EN
MO
DE
ENABL
E
C
LK_APB
C
LK_PRE
SC
ALER
C
LK
_
SAMPLIN
G
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temperature range are located in the “Electrical Characteristics” on page 1055. To calculate the temperature from a
measured voltage, the following formula can be used:
15.6.10.1 User Control of the Voltage Reference System
To enable the temperature sensor, write a one the Temperature Sensor Enable bit (VREF.TSEN) in the VREF register.
The temperature sensor can be redirected to the ADC for conversion. The Bandgap Reference Voltage Generator output
can also be routed to the ADC if the Bandgap Output Enable bit (VREF.BGOUTEN) in the VREF register is set.
The Bandgap Reference Voltage Generator output level is determined by the CALIB bit group (VREF.CALIB) value in the
VREF register.The default calibration value can be overridden by the user by writing to the CALIB bit group.
15.6.11 Internal Voltage Regulator System (VREG)
The embedded Voltage Regulator (VREG) is an internal voltage regulator that supplies the core and digital logic.
The regulator has two operating modes:
za normal operating mode: used when the CPU and peripherals are running
za low-power operating mode: used when the regulator draws small static current. By default, this mode is used in
standby sleep mode. It is possible to have the voltage regulator operate in normal mode when the chip is in
standby sleep mode: this is done by setting the VREG.RUNSTDBY bit.
The low-power operating mode has two possible configurations in standby sleep mode:
za low drive configuration, this is the default setting (the VREG.FORCELDO bit is cleared),
za high drive configuration: this setting is required for higher loads in standby sleep mode (case where several
modules are up despite the standby mode). To activate this configuration, the FORCELDO bit
(VREG.FORCELDO) in the VREG register must be set.
The internal voltage regulator system contains an internal brown-out detector(BOD12) on VDDCORE. BOD12 is
calibrated in production and its calibration configuration is stored in the NVM User Row. This configuration must not be
changed to assure the correct behavior of the BOD12. The BOD12 can generate either an interrupt or a reset when
VDDCORE crosses below the preset brown-out level. The BOD12 is always disabled in standby sleep mode.
15.6.12 DMA Operation
Not applicable.
15.6.13 Interrupts
The SYSCTRL has the following interrupt sources:
zXOSCRDY - Multipurpose Crystal Oscillator Ready: A “0-to-1” transition on the PCLKSR.XOSCRDY bit is detected
zXOSC32KRDY - 32kHz Crystal Oscillator Ready: A “0-to-1” transition on the PCLKSR.XOSC32KRDY bit is detected
zOSC32KRDY - 32kHz Internal Oscillator Ready: A “0-to-1” transition on the PCLKSR.OSC32KRDY bit is detected
zOSC8MRDY - 8MHz Internal Oscillator Ready: A “0-to-1” transition on the PCLKSR.OSC8MRDY bit is detected
zDFLLRDY - DFLL48M Ready: A “0-to-1” transition on the PCLKSR.DFLLRDY bit is detected
zDFLLOOB - DFLL48M Out Of Boundaries: A “0-to-1” transition on the PCLKSR.DFLLOOB bit is detected
zDFLLLOCKF - DFLL48M Fine Lock: A “0-to-1” transition on the PCLKSR.DFLLLOCKF bit is detected
zDFLLLOCKC - DFLL48M Coarse Lock: A “0-to-1” transition on the PCLKSR.DFLLLOCKC bit is detected
zDFLLRCS - DFLL48M Reference Clock has Stopped: A “0-to-1” transition on the PCLKSR.DFLLRCS bit is detected
zBOD33RDY - BOD33 Ready: A “0-to-1” transition on the PCLKSR.BOD33RDY bit is detected
zBOD33DET - BOD33 Detection: A “0-to-1” transition on the PCLKSR.BOD33DET bit is detected. This is an
asynchronous interrupt and can be used to wake-up the device from any sleep mode.
zB33SRDY - BOD33 Synchronization Ready: A “0-to-1” transition on the PCLKSR.B33SRDY bit is detected
zPLL Lock (LOCK): Indicates that the DPLL Lock bit is asserted.
CMIN Vmes VoutMAX
–()
Δtemperature
Δvoltage
------------------------------------
+
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zPLL Lock Lost (LOCKL): Indicates that a falling edge has been detected on the Lock bit during normal operation mode.
zPLL Lock Timer Timeout (LTTO): This interrupt flag indicates that the software defined time DPLLCTRLB.LTIME has
elapsed since the start of the FDPLL96M.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
(INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one
to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a one to the
corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the interrupt
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is
cleared, the interrupt is disabled, or the SYSCTRL is reset. See Interrupt Flag Status and Clear (INTFLAG) register for
details on how to clear interrupt flags.
All interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt request
to the NVIC. Refer to “Nested Vector Interrupt Controller” on page 29 for details. The user must read the INTFLAG
register to determine which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to “Nested Vector Interrupt
Controller” on page 29 for details.
15.6.14 Synchronization
Due to the multiple clock domains, values in the DFLL48M control registers need to be synchronized to other clock
domains. The status of this synchronization can be read from the Power and Clocks Status register (PCLKSR). Before
writing to any of the DFLL48M control registers, the user must check that the DFLL Ready bit (PCLKSR.DFLLRDY) in
PCLKSR is set to one. When this bit is set, the DFLL48M can be configured and CLK_DFLL48M is ready to be used. Any
write to any of the DFLL48M control registers while DFLLRDY is zero will be ignored. An interrupt is generated on a zero-
to-one transition of DFLLRDY if the DFLLRDY bit (INTENSET.DFLLDY) in the Interrupt Enable Set register is set.
In order to read from any of the DFLL48M configuration registers, the user must request a read synchronization by
writing a one to DFLLSYNC.READREQ. The registers can be read only when PCLKSR.DFLLRDY is set. If
DFLLSYNC.READREQ is not written before a read, a synchronization will be started, and the bus will be halted until the
synchronization is complete. Reading the DFLL48M registers when the DFLL48M is disabled will not halt the bus.
The prescaler counter used to trigger one-shot brown-out detections also operates asynchronously from the peripheral
bus. As a consequence, the prescaler registers require synchronization when written or read. The synchronization
results in a delay from when the initialization of the write or read operation begins until the operation is complete.
The write-synchronization is triggered by a write to the BOD33 control register. The Synchronization Ready bit
(PCLKSR.B33SRDY) in the PCLKSR register will be cleared when the write-synchronization starts and set when the
write-synchronization is complete. When the write-synchronization is ongoing (PCLKSR.B33SRDYis zero), an attempt to
do any of the following will cause the peripheral bus to stall until the synchronization is complete:
zWriting to the BOD33control register
zReading the BOD33 control register that was written
The user can either poll PCLKSR.B33SRDY or use the INTENSET.B33SRDY interrupts to check when the
synchronization is complete. It is also possible to perform the next read/write operation and wait, as this next operation
will be completed after the ongoing read/write operation is synchronized.
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15.7 Register Summary
Table 15-6. Register Summary
Offset Name
Bit
Pos.
0x00
INTENCLR
7:0 DFLLLCKC DFLLLCKF DFLLOOB DFLLRDY OSC8MRDY OSC32KRDY
XOSC32KRDY XOSCRDY
0x01 15:8 DPLLLCKR B33SRDY BOD33DET BOD33RDY DFLLRCS
0x02 23:16 DPLLLTO DPLLLCKF
0x03 31:24
0x04
INTENSET
7:0 DFLLLCKC DFLLLCKF DFLLOOB DFLLRDY OSC8MRDY OSC32KRDY
XOSC32KRDY XOSCRDY
0x05 15:8 DPLLLCKR B33SRDY BOD33DET BOD33RDY DFLLRCS
0x06 23:16 DPLLLTO DPLLLCKF
0x07 31:24
0x08
INTFLAG
7:0 DFLLLCKC DFLLLCKF DFLLOOB DFLLRDY OSC8MRDY OSC32KRDY
XOSC32KRDY XOSCRDY
0x09 15:8 DPLLLCKR B33SRDY BOD33DET BOD33RDY DFLLRCS
0x0A 23:16 DPLLLTO DPLLLCKF
0x0B 31:24
0x0C
PCLKSR
7:0 DFLLLCKC DFLLLCKF DFLLOOB DFLLRDY OSC8MRDY OSC32KRDY
XOSC32KRDY XOSCRDY
0x0D 15:8 DPLLLCKR B33SRDY BOD33DET BOD33RDY DFLLRCS
0x0E 23:16 DPLLLTO DPLLLCKF
0x0F 31:24
0x10
XOSC
7:0 ONDEMAND RUNSTDBY XTALEN ENABLE
0x11 15:8 STARTUP[3:0] AMPGC GAIN[2:0]
0x12 Reserved
0x13 Reserved
0x14
XOSC32K
7:0 ONDEMAND RUNSTDBY AAMPEN EN32K XTALEN ENABLE
0x15 15:8 WRTLOCK STARTUP[2:0]
0x16 Reserved
0x17 Reserved
0x18
OSC32K
7:0 ONDEMAND RUNSTDBY EN32K ENABLE
0x19 15:8 WRTLOCK STARTUP[2:0]
0x1A 23:16 CALIB[6:0]
0x1B 31:24
0x1C OSCULP32K 7:0 WRTLOCK CALIB[4:0]
0x1D
...
0x1F
Reserved
0x20
OSC8M
7:0 ONDEMAND RUNSTDBY ENABLE
0x21 15:8 PRESC[1:0]
0x22 23:16 CALIB[7:0]
0x23 31:24 FRANGE[1:0] CALIB[11:8]
0x24
DFLLCTRL
7:0 ONDEMAND RUNSTDBY USBCRM LLAW STABLE MODE ENABLE
0x25 15:8 WAITLOCK BPLCKC QLDIS CCDIS
0x26 Reserved
0x27 Reserved
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0x28
DFLLVAL
7:0 FINE[7:0]
0x29 15:8 COARSE[5:0] FINE[9:8]
0x2A 23:16 DIFF[7:0]
0x2B 31:24 DIFF[15:8]
0x2C
DFLLMUL
7:0 MUL[7:0]
0x2D 15:8 MUL[15:8]
0x2E 23:16 FSTEP[7:0]
0x2F 31:24 CSTEP[5:0] FSTEP[9:8]
0x30 DFLLSYNC 7:0 READREQ
0x31
...
0x33
Reserved
0x34
BOD33
7:0 RUNSTDBY ACTION[1:0] HYST ENABLE
0x35 15:8 PSEL[3:0] CEN MODE
0x36 23:16 LEVEL[5:0]
0x37 31:24
0x38
...
0x3B
Reserved
0x3C
VREG
7:0 RUNSTDBY
0x3D 15:8 FORCELDO
0x3E Reserved
0x3F Reserved
0x40
VREF
7:0 BGOUTEN TSEN
0x41 15:8
0x42 23:16 CALIB[7:0]
0x43 31:24 CALIB[10:8]
0x44 DPLLCTRLA 7:0 ONDEMAND RUNSTDBY ENABLE
0x45
...
0x47
Reserved
0x48
DPLLRATIO
7:0 LDR[7:0]
0x49 15:8 LDR[11:8]
0x4A 23:16 LDRFRAC[3:0]
0x4B 31:24
0x4C
DPLLCTRLB
7:0 REFCLK[1:0] WUF LPEN FILTER[1:0]
0x4D 15:8 LBYPASS LTIME[2:0]
0x4E 23:16 DIV[7:0]
0x4F 31:24 DIV[10:8]
0x50 DPLLSTATUS 7:0 DIV ENABLE CLKRDY LOCK
Offset Name
Bit
Pos.
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15.8 Register Description
Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters
and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by
the Write-Protected property in each individual register description. Refer to “Register Access Protection” on page 146
and the “PAC – Peripheral Access Controller” on page 36 for details.
Some registers require synchronization when read and/or written. Synchronization is denoted by the Synchronized
property in each individual register description. Refer to “Synchronization” on page 159 for details.
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15.8.1 Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x00
Reset: 0x00000000
Property: Write-Protected
zBits 31:18 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 17 – DPLLLTO: DPLL Lock Timeout Interrupt Enable
0: The DPLL Lock Timeout interrupt is disabled.
1: The DPLL Lock Timeout interrupt is enabled, and an interrupt request will be generated when the DPLL Lock
Timeout Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DPLL Lock Timeout Interrupt Enable bit, which disables the DPLL Lock Time-
out interrupt.
zBit 16 – DPLLLCKF: DPLL Lock Fall Interrupt Enable
0: The DPLL Lock Fall interrupt is disabled.
1: The DPLL Lock Fall interrupt is enabled, and an interrupt request will be generated when the DPLL Lock Fall
Interrupt flag is set.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
DPLLLTO
DPLLLCKF
AccessRRRRRRR/WR/W
Reset00000000
Bit 151413121110 9 8
DPLLLCKR
B33SRDY
BOD33DET BOD33RDY
DFLLRCS
Access R/W R R R R/W R/W R/W R/W
Reset00000000
Bit 76543210
DFLLLCKC DFLLLCKF
DFLLOOB DFLLRDY
OSC8MRDY
OSC32KRDY
XOSC32KRDY
XOSCRDY
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DPLL Lock Fall Interrupt Enable bit, which disables the DPLL Lock Fall
interrupt.
zBit 15 – DPLLLCKR: DPLL Lock Rise Interrupt Enable
0: The DPLL Lock Rise interrupt is disabled.
1: The DPLL Lock Rise interrupt is enabled, and an interrupt request will be generated when the DPLL Lock Rise
Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DPLL Lock Rise Interrupt Enable bit, which disables the DPLL Lock Rise
interrupt.
zBits 14:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 11 – B33SRDY: BOD33 Synchronization Ready Interrupt Enable
0: The BOD33 Synchronization Ready interrupt is disabled.
1: The BOD33 Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the
BOD33 Synchronization Ready Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the BOD33 Synchronization Ready Interrupt Enable bit, which disables the
BOD33 Synchronization Ready interrupt.
zBit 10 – BOD33DET: BOD33 Detection Interrupt Enable
0: The BOD33 Detection interrupt is disabled.
1: The BOD33 Detection interrupt is enabled, and an interrupt request will be generated when the BOD33 Detec-
tion Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the BOD33 Detection Interrupt Enable bit, which disables the BOD33 Detection
interrupt.
zBit 9 – BOD33RDY: BOD33 Ready Interrupt Enable
0: The BOD33 Ready interrupt is disabled.
1: The BOD33 Ready interrupt is enabled, and an interrupt request will be generated when the BOD33 Ready
Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the BOD33 Ready Interrupt Enable bit, which disables the BOD33 Ready
interrupt.
zBit 8 – DFLLRCS: DFLL Reference Clock Stopped Interrupt Enable
0: The DFLL Reference Clock Stopped interrupt is disabled.
1: The DFLL Reference Clock Stopped interrupt is enabled, and an interrupt request will be generated when the
DFLL Reference Clock Stopped Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DFLL Reference Clock Stopped Interrupt Enable bit, which disables the DFLL
Reference Clock Stopped interrupt.
zBit 7 – DFLLLCKC: DFLL Lock Coarse Interrupt Enable
0: The DFLL Lock Coarse interrupt is disabled.
1: The DFLL Lock Coarse interrupt is enabled, and an interrupt request will be generated when the DFLL Lock
Coarse Interrupt flag is set.
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Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DFLL Lock Coarse Interrupt Enable bit, which disables the DFLL Lock Coarse
interrupt.
zBit 6 – DFLLLCKF: DFLL Lock Fine Interrupt Enable
0: The DFLL Lock Fine interrupt is disabled.
1: The DFLL Lock Fine interrupt is enabled, and an interrupt request will be generated when the DFLL Lock Fine
Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DFLL Lock Fine Interrupt Enable bit, which disables the DFLL Lock Fine
interrupt.
zBit 5 – DFLLOOB: DFLL Out Of Bounds Interrupt Enable
0: The DFLL Out Of Bounds interrupt is disabled.
1: The DFLL Out Of Bounds interrupt is enabled, and an interrupt request will be generated when the DFLL Out Of
Bounds Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DFLL Out Of Bounds Interrupt Enable bit, which disables the DFLL Out Of
Bounds interrupt.
zBit 4 – DFLLRDY: DFLL Ready Interrupt Enable
0: The DFLL Ready interrupt is disabled.
1: The DFLL Ready interrupt is enabled, and an interrupt request will be generated when the DFLL Ready Interrupt
flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DFLL Ready Interrupt Enable bit, which disables the DFLL Ready interrupt.
zBit 3 – OSC8MRDY: OSC8M Ready Interrupt Enable
0: The OSC8M Ready interrupt is disabled.
1: The OSC8M Ready interrupt is enabled, and an interrupt request will be generated when the OSC8M Ready
Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the OSC8M Ready Interrupt Enable bit, which disables the OSC8M Ready
interrupt.
zBit 2 – OSC32KRDY: OSC32K Ready Interrupt Enable
0: The OSC32K Ready interrupt is disabled.
1: The OSC32K Ready interrupt is enabled, and an interrupt request will be generated when the OSC32K Ready
Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the OSC32K Ready Interrupt Enable bit, which disables the OSC32K Ready
interrupt.
zBit 1 – XOSC32KRDY: XOSC32K Ready Interrupt Enable
0: The XOSC32K Ready interrupt is disabled.
1: The XOSC32K Ready interrupt is enabled, and an interrupt request will be generated when the XOSC32K
Ready Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the XOSC32K Ready Interrupt Enable bit, which disables the XOSC32K Ready
interrupt.
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zBit 0 – XOSCRDY: XOSC Ready Interrupt Enable
0: The XOSC Ready interrupt is disabled.
1: The XOSC Ready interrupt is enabled, and an interrupt request will be generated when the XOSC Ready Inter-
rupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the XOSC Ready Interrupt Enable bit, which disables the XOSC Ready interrupt.
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15.8.2 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name: INTENSET
Offset: 0x04
Reset: 0x00000000
Property: Write-Protected
zBits 31:18 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 17 – DPLLLTO: DPLL Lock Timeout Interrupt Enable
0: The DPLL Lock Timeout interrupt is disabled.
1: The DPLL Lock Timeout interrupt is enabled, and an interrupt request will be generated when the DPLL Lock
Timeout Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the DPLL Lock Timeout Interrupt Enable bit, which enables the DPLL Lock Timeout
interrupt.
zBit 16 – DPLLLCKF: DPLL Lock Fall Interrupt Enable
0: The DPLL Lock Fall interrupt is disabled.
1: The DPLL Lock Fall interrupt is enabled, and an interrupt request will be generated when the DPLL Lock Fall
Interrupt flag is set.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
DPLLLTO
DPLLLCKF
AccessRRRRRRR/WR/W
Reset00000000
Bit 151413121110 9 8
DPLLLCKR
B33SRDY
BOD33DET BOD33RDY
DFLLRCS
Access R/W R R R R/W R/W R/W R/W
Reset00000000
Bit 76543210
DFLLLCKC DFLLLCKF
DFLLOOB DFLLRDY
OSC8MRDY
OSC32KRDY
XOSC32KRDY
XOSCRDY
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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Writing a zero to this bit has no effect.
Writing a one to this bit will set the DPLL Lock Fall Interrupt Enable bit, which enables the DPLL Lock Fall interrupt.
zBit 15 – DPLLLCKR: DPLL Lock Rise Interrupt Enable
0: The DPLL Lock Rise interrupt is disabled.
1: The DPLL Lock Rise interrupt is enabled, and an interrupt request will be generated when the DPLL Lock Rise
Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the DPLL Lock Rise Interrupt Enable bit, which enables the DPLL Lock Rise
interrupt.
zBits 14:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 11 – B33SRDY: BOD33 Synchronization Ready Interrupt Enable
0: The BOD33 Synchronization Ready interrupt is disabled.
1: The BOD33 Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the
BOD33 Synchronization Ready Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the BOD33 Synchronization Ready Interrupt Enable bit, which enables the BOD33
Synchronization Ready interrupt.
zBit 10 – BOD33DET: BOD33 Detection Interrupt Enable
0: The BOD33 Detection interrupt is disabled.
1: The BOD33 Detection interrupt is enabled, and an interrupt request will be generated when the BOD33 Detec-
tion Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the BOD33 Detection Interrupt Enable bit, which enables the BOD33 Detection
interrupt.
zBit 9 – BOD33RDY: BOD33 Ready Interrupt Enable
0: The BOD33 Ready interrupt is disabled.
1: The BOD33 Ready interrupt is enabled, and an interrupt request will be generated when the BOD33 Ready
Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the BOD33 Ready Interrupt Enable bit, which enables the BOD33 Ready interrupt.
zBit 8 – DFLLRCS: DFLL Reference Clock Stopped Interrupt Enable
0: The DFLL Reference Clock Stopped interrupt is disabled.
1: The DFLL Reference Clock Stopped interrupt is enabled, and an interrupt request will be generated when the
DFLL Reference Clock Stopped Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the DFLL Reference Clock Stopped Interrupt Enable bit, which enables the DFLL
Reference Clock Stopped interrupt.
zBit 7 – DFLLLCKC: DFLL Lock Coarse Interrupt Enable
0: The DFLL Lock Coarse interrupt is disabled.
1: The DFLL Lock Coarse interrupt is enabled, and an interrupt request will be generated when the DFLL Lock
Coarse Interrupt flag is set.
Writing a zero to this bit has no effect.
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Writing a one to this bit will set the DFLL Lock Coarse Interrupt Enable bit, which enables the DFLL Lock Coarse
interrupt.
zBit 6 – DFLLLCKF: DFLL Lock Fine Interrupt Enable
0: The DFLL Lock Fine interrupt is disabled.
1: The DFLL Lock Fine interrupt is enabled, and an interrupt request will be generated when the DFLL Lock Fine
Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the DFLL Lock Fine Interrupt Disable/Enable bit, disable the DFLL Lock Fine inter-
rupt and set the corresponding interrupt request.
zBit 5 – DFLLOOB: DFLL Out Of Bounds Interrupt Enable
0: The DFLL Out Of Bounds interrupt is disabled.
1: The DFLL Out Of Bounds interrupt is enabled, and an interrupt request will be generated when the DFLL Out Of
Bounds Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the DFLL Out Of Bounds Interrupt Enable bit, which enables the DFLL Out Of
Bounds interrupt.
zBit 4 – DFLLRDY: DFLL Ready Interrupt Enable
0: The DFLL Ready interrupt is disabled.
1: The DFLL Ready interrupt is enabled, and an interrupt request will be generated when the DFLL Ready Interrupt
flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the DFLL Ready Interrupt Enable bit, which enables the DFLL Ready interrupt and
set the corresponding interrupt request.
zBit 3 – OSC8MRDY: OSC8M Ready Interrupt Enable
0: The OSC8M Ready interrupt is disabled.
1: The OSC8M Ready interrupt is enabled, and an interrupt request will be generated when the OSC8M Ready
Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the OSC8M Ready Interrupt Enable bit, which enables the OSC8M Ready interrupt.
zBit 2 – OSC32KRDY: OSC32K Ready Interrupt Enable
0: The OSC32K Ready interrupt is disabled.
1: The OSC32K Ready interrupt is enabled, and an interrupt request will be generated when the OSC32K Ready
Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the OSC32K Ready Interrupt Enable bit, which enables the OSC32K Ready
interrupt.
zBit 1 – XOSC32KRDY: XOSC32K Ready Interrupt Enable
0: The XOSC32K Ready interrupt is disabled.
1: The XOSC32K Ready interrupt is enabled, and an interrupt request will be generated when the XOSC32K
Ready Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the XOSC32K Ready Interrupt Enable bit, which enables the XOSC32K Ready
interrupt.
zBit 0 – XOSCRDY: XOSC Ready Interrupt Enable
0: The XOSC Ready interrupt is disabled.
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1: The XOSC Ready interrupt is enabled, and an interrupt request will be generated when the XOSC Ready Inter-
rupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the XOSC Ready Interrupt Enable bit, which enables the XOSC Ready interrupt.
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15.8.3 Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x08
Reset: 0x00000000
Property: -
Note: Depending on the fuse settings, various bits of the INTFLAG register can be set to one at startup. Therefore the
user should clear those bits before using the corresponding interrupts.
zBits 31:18 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 17 – DPLLLTO: DPLL Lock Timeout
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DPLL Lock Timeout bit in the Status register (PCLKSR.DPLLLTO)
and will generate an interrupt request if INTENSET.DPLLLTO is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DPLL Lock Timeout interrupt flag.
zBit 16 – DPLLLCKF: DPLL Lock Fall
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DPLL Lock Fall bit in the Status register (PCLKSR.DPLLLCKF)
and will generate an interrupt request if INTENSET.DPLLLCKF is one.
Writing a zero to this bit has no effect.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
DPLLLTO
DPLLLCKF
AccessRRRRRRR/WR/W
Reset00000000
Bit 151413121110 9 8
DPLLLCKR
B33SRDY
BOD33DET BOD33RDY
DFLLRCS
Access R/W R R R R/W R/W R/W R/W
Reset00000000
Bit 76543210
DFLLLCKC DFLLLCKF
DFLLOOB DFLLRDY
OSC8MRDY
OSC32KRDY
XOSC32KRDY
XOSCRDY
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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Writing a one to this bit clears the DPLL Lock Fall interrupt flag.
zBit 15 – DPLLLCKR: DPLL Lock Rise
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DPLL Lock Rise bit in the Status register (PCLKSR.DPLLLCKR)
and will generate an interrupt request if INTENSET.DPLLLCKR is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DPLL Lock Rise interrupt flag.
zBits 14:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 11 – B33SRDY: BOD33 Synchronization Ready
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the BOD33 Synchronization Ready bit in the Status register
(PCLKSR.B33SRDY) and will generate an interrupt request if INTENSET.B33SRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the BOD33 Synchronization Ready interrupt flag
zBit 10 – BOD33DET: BOD33 Detection
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the BOD33 Detection bit in the Status register (PCLKSR.BOD33DET)
and will generate an interrupt request if INTENSET.BOD33DET is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the BOD33 Detection interrupt flag.
zBit 9 – BOD33RDY: BOD33 Ready
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the BOD33 Ready bit in the Status register (PCLKSR.BOD33RDY)
and will generate an interrupt request if INTENSET.BOD33RDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the BOD33 Ready interrupt flag.
zBit 8 – DFLLRCS: DFLL Reference Clock Stopped
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DFLL Reference Clock Stopped bit in the Status register
(PCLKSR.DFLLRCS) and will generate an interrupt request if INTENSET.DFLLRCS is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DFLL Reference Clock Stopped interrupt flag.
zBit 7 – DFLLLCKC: DFLL Lock Coarse
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DFLL Lock Coarse bit in the Status register (PCLKSR.DFLLL-
CKC) and will generate an interrupt request if INTENSET.DFLLLCKC is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DFLL Lock Coarse interrupt flag.
zBit 6 – DFLLLCKF: DFLL Lock Fine
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DFLL Lock Fine bit in the Status register (PCLKSR.DFLLLCKF)
and will generate an interrupt request if INTENSET.DFLLLCKF is one.
Writing a zero to this bit has no effect.
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Writing a one to this bit clears the DFLL Lock Fine interrupt flag.
zBit 5 – DFLLOOB: DFLL Out Of Bounds
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DFLL Out Of Bounds bit in the Status register (PCLKSR.DFL-
LOOB) and will generate an interrupt request if INTENSET.DFLLOOB is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DFLL Out Of Bounds interrupt flag.
zBit 4 – DFLLRDY: DFLL Ready
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DFLL Ready bit in the Status register (PCLKSR.DFLLRDY) and
will generate an interrupt request if INTENSET.DFLLRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DFLL Ready interrupt flag.
zBit 3 – OSC8MRDY: OSC8M Ready
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the OSC8M Ready bit in the Status register (PCLKSR.OSC8MRDY)
and will generate an interrupt request if INTENSET.OSC8MRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the OSC8M Ready interrupt flag.
zBit 2 – OSC32KRDY: OSC32K Ready
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the OSC32K Ready bit in the Status register (PCLKSR.OSC32KRDY)
and will generate an interrupt request if INTENSET.OSC32KRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the OSC32K Ready interrupt flag.
zBit 1 – XOSC32KRDY: XOSC32K Ready
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the XOSC32K Ready bit in the Status register
(PCLKSR.XOSC32KRDY) and will generate an interrupt request if INTENSET.XOSC32KRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the XOSC32K Ready interrupt flag.
zBit 0 – XOSCRDY: XOSC Ready
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the XOSC Ready bit in the Status register (PCLKSR.XOSCRDY) and
will generate an interrupt request if INTENSET.XOSCRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the XOSC Ready interrupt flag.
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15.8.4 Power and Clocks Status
Name: PCLKSR
Offset: 0x0C
Reset: 0x00000000
Property: -
zBits 31:18 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 17 – DPLLLTO: DPLL Lock Timeout
0: DPLL Lock time-out not detected.
1: DPLL Lock time-out detected.
zBit 16 – DPLLLCKF: DPLL Lock Fall
0: DPLL Lock fall edge not detected.
1: DPLL Lock fall edge detected.
zBit 15 – DPLLLCKR: DPLL Lock Rise
0: DPLL Lock rise edge not detected.
1: DPLL Lock fall edge detected.
zBits 14:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
DPLLLTO
DPLLLCKF
AccessRRRRRRRR
Reset00000000
Bit 151413121110 9 8
DPLLLCKR
B33SRDY
BOD33DET BOD33RDY
DFLLRCS
AccessRRRRRRRR
Reset00000000
Bit 76543210
DFLLLCKC DFLLLCKF
DFLLOOB DFLLRDY
OSC8MRDY
OSC32KRDY
XOSC32KRDY
XOSCRDY
AccessRRRRRRRR
Reset00000000
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zBit 11 – B33SRDY: BOD33 Synchronization Ready
0: BOD33 synchronization is complete.
1: BOD33 synchronization is ongoing.
zBit 10 – BOD33DET: BOD33 Detection
0: No BOD33 detection.
1: BOD33 has detected that the I/O power supply is going below the BOD33 reference value.
zBit 9 – BOD33RDY: BOD33 Ready
0: BOD33 is not ready.
1: BOD33 is ready.
zBit 8 – DFLLRCS: DFLL Reference Clock Stopped
0: DFLL reference clock is running.
1: DFLL reference clock has stopped.
zBit 7 – DFLLLCKC: DFLL Lock Coarse
0: No DFLL coarse lock detected.
1: DFLL coarse lock detected.
zBit 6 – DFLLLCKF: DFLL Lock Fine
0: No DFLL fine lock detected.
1: DFLL fine lock detected.
zBit 5 – DFLLOOB: DFLL Out Of Bounds
0: No DFLL Out Of Bounds detected.
1: DFLL Out Of Bounds detected.
zBit 4 – DFLLRDY: DFLL Ready
0: The Synchronization is ongoing.
1: The Synchronization is complete.
This bit is cleared when the synchronization of registers between clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
zBit 3 – OSC8MRDY: OSC8M Ready
0: OSC8M is not ready.
1: OSC8M is stable and ready to be used as a clock source.
zBit 2 – OSC32KRDY: OSC32K Ready
0: OSC32K is not ready.
1: OSC32K is stable and ready to be used as a clock source.
zBit 1 – XOSC32KRDY: XOSC32K Ready
0: XOSC32K is not ready.
1: XOSC32K is stable and ready to be used as a clock source.
zBit 0 – XOSCRDY: XOSC Ready
0: XOSC is not ready.
1: XOSC is stable and ready to be used as a clock source.
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15.8.5 External Multipurpose Crystal Oscillator (XOSC) Control
Name: XOSC
Offset: 0x10
Reset: 0x0080
Property: Write-Protected
zBits 15:12 – STARTUP[3:0]: Start-Up Time
These bits select start-up time for the oscillator according to the table below.
The OSCULP32K oscillator is used to clock the start-up counter.
Bit 151413121110 9 8
STARTUP[3:0] AMPGC GAIN[2:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
ONDEMAND RUNSTDBY
XTALEN ENABLE
Access R/W R/W R R R R/W R/W R
Reset10000000
Table 15-7. Start-UpTime for External Multipurpose Crystal Oscillator
STARTUP[3:0]
Number of
OSCULP32K Clock
Cycles
Number of XOSC
Clock Cycles Approximate Equivalent Time(1)(2)(3)
0x0 1 3 31µs
0x1 2 3 61µs
0x2 4 3 122µs
0x3 8 3 244µs
0x4 16 3488µs
0x5 32 3977µs
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Notes: 1. Number of cycles for the start-up counter
2. Number of cycles for the synchronization delay, before PCLKSR.XOSCRDY is set.
3. Actual start-up time is n OSCULP32K cycles + 3 XOSC cycles, but given the time neglects the 3 XOSC
cycles.
zBit 11 – AMPGC: Automatic Amplitude Gain Control
0: The automatic amplitude gain control is disabled.
1: The automatic amplitude gain control is enabled. Amplitude gain will be automatically adjusted during Crystal
Oscillator operation.
zBits 10:8 – GAIN[2:0]: Oscillator Gain
These bits select the gain for the oscillator. The listed maximum frequencies are recommendations, and might vary
based on capacitive load and crystal characteristics. Setting this bit group has no effect when the Automatic Ampli-
tude Gain Control is active.
Table 15-8. Oscillator Gain
zBit 7 – ONDEMAND: On Demand Control
The On Demand operation mode allows an oscillator to be enabled or disabled, depending on peripheral clock
requests.
0x6 64 31953µs
0x7 128 33906µs
0x8 256 37813µs
0x9 512 315625µs
0xA 1024 331250µs
0xB 2048 362500µs
0xC 4096 3125000µs
0xD 8192 3250000µs
0xE 16384 3500000µs
0xF 32768 31000000µs
GAIN[2:0] Recommended Max Frequency
0x0 2MHz
0x1 4MHz
0x2 8MHz
0x3 16MHz
0x4 30MHz
0x5-0x7 Reserved
Table 15-7. Start-UpTime for External Multipurpose Crystal Oscillator (Continued)
STARTUP[3:0]
Number of
OSCULP32K Clock
Cycles
Number of XOSC
Clock Cycles Approximate Equivalent Time(1)(2)(3)
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In On Demand operation mode, i.e., if the XOSC.ONDEMAND bit has been previously written to one, the oscillator
will be running only when requested by a peripheral. If there is no peripheral requesting the oscillator s clock
source, the oscillator will be in a disabled state.
If On Demand is disabled, the oscillator will always be running when enabled.
In standby sleep mode, the On Demand operation is still active if the XOSC.RUNSTDBY bit is one. If
XOSC.RUNSTDBY is zero, the oscillator is disabled.
0: The oscillator is always on, if enabled.
1: The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. The oscilla-
tor is disabled if no peripheral is requesting the clock source.
zBit 6 – RUNSTDBY: Run in Standby
This bit controls how the XOSC behaves during standby sleep mode:
0: The oscillator is disabled in standby sleep mode.
1: The oscillator is not stopped in standby sleep mode. If XOSC.ONDEMAND is one, the clock source will be run-
ning when a peripheral is requesting the clock. If XOSC.ONDEMAND is zero, the clock source will always be
running in standby sleep mode.
zBits 5:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 2 – XTALEN: Crystal Oscillator Enable
This bit controls the connections between the I/O pads and the external clock or crystal oscillator:
0: External clock connected on XIN. XOUT can be used as general-purpose I/O.
1: Crystal connected to XIN/XOUT.
zBit 1 – ENABLE: Oscillator Enable
0: The oscillator is disabled.
1: The oscillator is enabled.
zBit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
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15.8.6 32kHz External Crystal Oscillator (XOSC32K) Control
Name: XOSC32K
Offset: 0x14
Reset: 0x0080
Property: Write-Protected
zBits 15:13 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 12 – WRTLOCK: Write Lock
This bit locks the XOSC32K register for future writes to fix the XOSC32K configuration.
0: The XOSC32K configuration is not locked.
1: The XOSC32K configuration is locked.
zBit 11 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 10:8 – STARTUP[2:0]: Oscillator Start-Up Time
These bits select the start-up time for the oscillator according to Table 15-9.
The OSCULP32K oscillator is used to clock the start-up counter.
Bit 151413121110 9 8
WRTLOCK STARTUP[2:0]
Access R R R R/W R R/W R/W R/W
Reset00000000
Bit 76543210
ONDEMAND RUNSTDBY
AAMPEN EN32K XTALEN ENABLE
Access R/W R/W R/W R R/W R/W R/W R
Reset10000000
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Notes: 1. Number of cycles for the start-up counter.
2. Number of cycles for the synchronization delay, before PCLKSR.XOSC32KRDY is set.
3. Start-up time is n OSCULP32K cycles + 3 XOSC32K cycles.
zBit 7 – ONDEMAND: On Demand Control
The On Demand operation mode allows an oscillator to be enabled or disabled depending on peripheral clock
requests.
In On Demand operation mode, i.e., if the ONDEMAND bit has been previously written to one, the oscillator will
only be running when requested by a peripheral. If there is no peripheral requesting the oscillator s clock source,
the oscillator will be in a disabled state.
If On Demand is disabled the oscillator will always be running when enabled.
In standby sleep mode, the On Demand operation is still active if the XOSC32K.RUNSTDBY bit is one. If
XOSC32K.RUNSTDBY is zero, the oscillator is disabled.
0: The oscillator is always on, if enabled.
1: The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. The oscilla-
tor is disabled if no peripheral is requesting the clock source.
zBit 6 – RUNSTDBY: Run in Standby
This bit controls how the XOSC32K behaves during standby sleep mode:
0: The oscillator is disabled in standby sleep mode.
1: The oscillator is not stopped in standby sleep mode. If XOSC32K.ONDEMAND is one, the clock source will be
running when a peripheral is requesting the clock. If XOSC32K.ONDEMAND is zero, the clock source will always
be running in standby sleep mode.
zBit 5 – AAMPEN: Automatic Amplitude Control Enable
0: The automatic amplitude control for the crystal oscillator is disabled.
1: The automatic amplitude control for the crystal oscillator is enabled.
zBit 4 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
Table 15-9. Start-Up Time for 32kHz External Crystal Oscillator
STARTUP[2:0]
Number of
OSCULP32K Clock
Cycles
Number of
XOSC32K Clock
Cycles
Approximate Equivalent Time
(OSCULP = 32kHz)(1)(2)(3)
0x0 1 3 122µs
0x1 32 31068µs
0x2 2048 362592µs
0x3 4096 3125092µs
0x4 16384 3500092µs
0x5 32768 31000092µs
0x6 65536 32000092µs
0x7 131072 34000092µs
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zBit 3 – EN32K: 32kHz Output Enable
0: The 32kHz output is disabled.
1: The 32kHz output is enabled.
zBit 2 – XTALEN: Crystal Oscillator Enable
This bit controls the connections between the I/O pads and the external clock or crystal oscillator:
0: External clock connected on XIN32. XOUT32 can be used as general-purpose I/O.
1: Crystal connected to XIN32/XOUT32.
zBit 1 – ENABLE: Oscillator Enable
0: The oscillator is disabled.
1: The oscillator is enabled.
zBit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
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15.8.7 32kHz Internal Oscillator (OSC32K) Control
Name: OSC32K
Offset: 0x18
Reset: 0x003F0080
Property: Write-Protected
zBits 31:23 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 22:16 – CALIB[6:0]: Oscillator Calibration
These bits control the oscillator calibration.
This value must be written by the user.
Factory calibration values can be loaded from the non-volatile memory. Refer to “NVM Software Calibration Area
Mapping” on page 26.
zBits 15:13 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 12 – WRTLOCK: Write Lock
This bit locks the OSC32K register for future writes to fix the OSC32K configuration.
0: The OSC32K configuration is not locked.
1: The OSC32K configuration is locked.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
CALIB[6:0]
Access R R/W R/W R/W R/W R/W R/W R/W
Reset00111111
Bit 151413121110 9 8
WRTLOCK STARTUP[2:0]
Access R R R R/W R R/W R/W R/W
Reset00000000
Bit 76543210
ONDEMAND RUNSTDBY
EN32K ENABLE
Access R/W R/W R R R R/W R/W R
Reset10000000
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zBit 11 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 10:8 – STARTUP[2:0]: Oscillator Start-Up Time
These bits select start-up time for the oscillator according to Table 15-10.
The OSCULP32K oscillator is used as input clock to the startup counter.
Notes: 1. Number of cycles for the start-up counter.
2. Number of cycles for the synchronization delay, before PCLKSR.OSC32KRDY is set.
3. Start-up time is n OSC32K cycles + 2 OSC32K cycles.
zBit 7 – ONDEMAND: On Demand Control
The On Demand operation mode allows an oscillator to be enabled or disabled depending on peripheral clock
requests.
In On Demand operation mode, i.e., if the ONDEMAND bit has been previously written to one, the oscillator will
only be running when requested by a peripheral. If there is no peripheral requesting the oscillator s clock source,
the oscillator will be in a disabled state.
If On Demand is disabled the oscillator will always be running when enabled.
In standby sleep mode, the On Demand operation is still active if the OSC32K.RUNSTDBY bit is one. If
OSC32K.RUNSTDBY is zero, the oscillator is disabled.
0: The oscillator is always on, if enabled.
1: The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. The oscilla-
tor is disabled if no peripheral is requesting the clock source.
zBit 6 – RUNSTDBY: Run in Standby
This bit controls how the OSC32K behaves during standby sleep mode:
0: The oscillator is disabled in standby sleep mode.
1: The oscillator is not stopped in standby sleep mode. If OSC32K.ONDEMAND is one, the clock source will be
running when a peripheral is requesting the clock. If OSC32K.ONDEMAND is zero, the clock source will always be
running in standby sleep mode.
Table 15-10. Start-Up Time for 32kHz Internal Oscillator
STARTUP[2:0]
Number of OSC32K
clock cycles
Approximate Equivalent Time
(OSCULP= 32 kHz)(1)(2)(3)
0x0 392µs
0x1 4122µs
0x2 6183µs
0x3 10 305µs
0x4 18 549µs
0x5 34 1038µs
0x6 66 2014µs
0x7 130 3967µs
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zBits 5:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 2 – EN32K: 32kHz Output Enable
0: The 32kHz output is disabled.
1: The 32kHz output is enabled.
zBit 1 – ENABLE: Oscillator Enable
0: The oscillator is disabled.
1: The oscillator is enabled.
zBit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
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15.8.8 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control
Name: OSCULP32K
Offset: 0x1C
Reset: 0xXX
Property: Write-Protected
zBit 7 – WRTLOCK: Write Lock
This bit locks the OSCULP32K register for future writes to fix the OSCULP32K configuration.
0: The OSCULP32K configuration is not locked.
1: The OSCULP32K configuration is locked.
zBits 6:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 4:0 – CALIB[4:0]: Oscillator Calibration
These bits control the oscillator calibration.
These bits are loaded from Flash Calibration at startup.
Bit 76543210
WRTLOCK CALIB[4:0]
Access R/W R R R/W R/W R/W R/W R/W
Reset00 0XXXXX
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15.8.9 8MHz Internal Oscillator (OSC8M) Control
Name: OSC8M
Offset: 0x20
Reset: 0xXXXX0382
Property: Write-Protected
zBits 31:30 – FRANGE[1:0]: Oscillator Frequency Range
These bits control the oscillator frequency range according to the table below. These bits are loaded from Flash
Calibration at startup.
Table 15-11. Oscillator Frequency Range
zBits 29:28 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit 3130292827262524
FRANGE[1:0] CALIB[11:8]
AccessR/WR/W R R R/WR/WR/WR/W
Reset X X 0 0 X X X X
Bit 2322212019181716
CALIB[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
ResetXXXXXXXX
Bit 151413121110 9 8
PRESC[1:0]
AccessRRRRRRR/WR/W
Reset00000011
Bit 76543210
ONDEMAND RUNSTDBY
ENABLE
AccessR/WR/WRRRRR/WR
Reset10000010
FRANGE[1:0] Description
0x0 4 to 6MHz
0x1 6 to 8MHz
0x2 8 to 11MHz
0x3 11 to 15MHz
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zBits 27:16 – CALIB[11:0]: Oscillator Calibration
These bits control the oscillator calibration. The calibration field is split in two:
CALIB[11:6] is for temperature calibration
CALIB[5:0] is for overall process calibration
These bits are loaded from Flash Calibration at startup.
zBits 15:10 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 9:8 – PRESC[1:0]: Oscillator Prescaler
These bits select the oscillator prescaler factor setting according to the table below.
Table 15-12. Oscillator Prescaler
zBit 7 – ONDEMAND: On Demand Control
The On Demand operation mode allows an oscillator to be enabled or disabled depending on peripheral clock
requests.
In On Demand operation mode, i.e., if the ONDEMAND bit has been previously written to one, the oscillator will
only be running when requested by a peripheral. If there is no peripheral requesting the oscillator s clock source,
the oscillator will be in a disabled state.
If On Demand is disabled the oscillator will always be running when enabled.
In standby sleep mode, the On Demand operation is still active if the OSC8M.RUNSTDBY bit is one. If
OSC8M.RUNSTDBY is zero, the oscillator is disabled.
0: The oscillator is always on, if enabled.
1: The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. The oscilla-
tor is disabled if no peripheral is requesting the clock source.
zBit 6 – RUNSTDBY: Run in Standby
This bit controls how the OSC8M behaves during standby sleep mode:
0: The oscillator is disabled in standby sleep mode.
1: The oscillator is not stopped in standby sleep mode. If OSC8M.ONDEMAND is one, the clock source will be run-
ning when a peripheral is requesting the clock. If OSC8M.ONDEMAND is zero, the clock source will always be
running in standby sleep mode.
zBits 5:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 1 – ENABLE: Oscillator Enable
0: The oscillator is disabled or being enabled.
1: The oscillator is enabled or being disabled.
The user must ensure that the OSC8M is fully disabled before enabling it, and that the OSC8M is fully enabled
before disabling it by reading OSC8M.ENABLE.
PRESC[1:0] Description
0x0 1
0x1 2
0x2 4
0x3 8
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zBit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
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15.8.10 DFLL48M Control
Name: DFLLCTRL
Offset: 0x24
Reset: 0x0080
Property: Write-Protected, Write-Synchronized
zBits 15:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 11 – WAITLOCK: Wait Lock
This bit controls the DFLL output clock, depending on lock status:
0: Output clock before the DFLL is locked.
1: Output clock when DFLL is locked.
zBit 10 – BPLCKC: Bypass Coarse Lock
This bit controls the coarse lock procedure:
0: Bypass coarse lock is disabled.
1: Bypass coarse lock is enabled.
zBit 9 – QLDIS: Quick Lock Disable
0: Quick Lock is enabled.
1: Quick Lock is disabled.
zBit 8 – CCDIS: Chill Cycle Disable
0: Chill Cycle is enabled.
1: Chill Cycle is disabled.
zBit 7 – ONDEMAND: On Demand Control
The On Demand operation mode allows an oscillator to be enabled or disabled depending on peripheral clock
requests.
In On Demand operation mode, i.e., if the ONDEMAND bit has been previously written to one, the oscillator will
only be running when requested by a peripheral. If there is no peripheral requesting the oscillator s clock source,
the oscillator will be in a disabled state.
If On Demand is disabled the oscillator will always be running when enabled.
In standby sleep mode, the On Demand operation is still active if the DFLLCTRL.RUNSTDBY bit is one. If
DFLLCTRL.RUNSTDBY is zero, the oscillator is disabled.
0: The oscillator is always on, if enabled.
Bit 151413121110 9 8
WAITLOCK
BPLCKC QLDIS CCDIS
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 76543210
ONDEMAND RUNSTDBY
USBCRM LLAW STABLE MODE ENABLE
AccessR/WR/WR/WR/WR/WR/WR/W R
Reset10000000
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1: The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. The oscilla-
tor is disabled if no peripheral is requesting the clock source.
zBit 6 – RUNSTDBY: Run in Standby
This bit controls how the DFLL behaves during standby sleep mode:
0: The oscillator is disabled in standby sleep mode.
1: The oscillator is not stopped in standby sleep mode. If DFLLCTRL.ONDEMAND is one, the clock source will be
running when a peripheral is requesting the clock. If DFLLCTRL.ONDEMAND is zero, the clock source will always
be running in standby sleep mode.
zBit 5 – USBCRM: USB Clock Recovery Mode
0: USB Clock Recovery Mode is disabled.
1: USB Clock Recovery Mode is enabled.
zBit 4 – LLAW: Lose Lock After Wake
0: Locks will not be lost after waking up from sleep modes if the DFLL clock has been stopped.
1: Locks will be lost after waking up from sleep modes if the DFLL clock has been stopped.
zBit 3 – STABLE: Stable DFLL Frequency
0: FINE calibration tracks changes in output frequency.
1: FINE calibration register value will be fixed after a fine lock.
zBit 2 – MODE: Operating Mode Selection
0: The DFLL operates in open-loop operation.
1: The DFLL operates in closed-loop operation.
zBit 1 – ENABLE: DFLL Enable
0: The DFLL oscillator is disabled.
1: The DFLL oscillator is enabled.
Due to synchronization, there is delay from updating the register until the peripheral is enabled/disabled. The value
written to DFLLCTRL.ENABLE will read back immediately after written.
zBit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
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15.8.11 DFLL48M Value
Name: DFLLVAL
Offset: 0x28
Reset: 0x00000000
Property: Read-Synchronized, Write-Protected
zBits 31:16 – DIFF[15:0]: Multiplication Ratio Difference
In closed-loop mode (DFLLCTRL.MODE is written to one), this bit group indicates the difference between the ideal
number of DFLL cycles and the counted number of cycles. This value is not updated in open-loop mode, and
should be considered invalid in that case.
zBits 15:10 – COARSE[5:0]: Coarse Value
Set the value of the Coarse Calibration register. In closed-loop mode, this field is read-only.
zBits 9:0 – FINE[9:0]: Fine Value
Set the value of the Fine Calibration register. In closed-loop mode, this field is read-only.
Bit 3130292827262524
DIFF[15:8]
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
DIFF[7:0]
AccessRRRRRRRR
Reset00000000
Bit 151413121110 9 8
COARSE[5:0] FINE[9:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
FINE[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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15.8.12 DFLL48M Multiplier
Name: DFLLMUL
Offset: 0x2C
Reset: 0x00000000
Property: Write-Protected
zBits 31:26 – CSTEP[5:0]: Coarse Maximum Step
This bit group indicates the maximum step size allowed during coarse adjustment in closed-loop mode. When
adjusting to a new frequency, the expected output frequency overshoot depends on this step size.
zBits 25:16 – FSTEP[9:0]: Fine Maximum Step
This bit group indicates the maximum step size allowed during fine adjustment in closed-loop mode. When adjust-
ing to a new frequency, the expected output frequency overshoot depends on this step size.
zBits 15:0 – MUL[15:0]: DFLL Multiply Factor
This field determines the ratio of the CLK_DFLL output frequency to the CLK_DFLL_REF input frequency. Writing
to the MUL bits will cause locks to be lost and the fine calibration value to be reset to its midpoint.
Bit 3130292827262524
CSTEP[5:0] FSTEP[9:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
FSTEP[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
MUL[15:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
MUL[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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15.8.13 DFLL48M Synchronization
Name: DFLLSYNC
Offset: 0x30
Reset: 0x00
Property: Write-Protected
zBit 7 – READREQ: Read Request
To be able to read the current value of DFLLVAL in closed-loop mode, this bit should be written to one. The
updated value is available in DFLLVAL when PCLKSR.DFLLRDY is set.
zBits 6:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit 76543210
READREQ
AccessWRRRRRRR
Reset00000000
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15.8.14 3.3V Brown-Out Detector (BOD33) Control
Name: BOD33
Offset: 0x34
Reset: 0x00XX00XX
Property: Write-Protected, Write-Synchronized
zBits 31:22 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 21:16 – LEVEL[5:0]: BOD33 Threshold Level
This field sets the triggering voltage threshold for the BOD33. See the “Electrical Characteristics” on page 1055 for
actual voltage levels. Note that any change to the LEVEL field of the BOD33 register should be done when the
BOD33 is disabled in order to avoid spurious resets or interrupts.
These bits are loaded from Flash User Row at startup. Refer to “NVM User Row Mapping” on page 25 for more
details.
zBits 15:12 – PSEL[3:0]: Prescaler Select
Selects the prescaler divide-by output for the BOD33 sampling mode according to the table below. The input clock
comes from the OSCULP32K 1kHz output.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
LEVEL[5:0]
Access R R R/W R/W R/W R/W R/W R/W
Reset00XXXXXX
Bit 151413121110 9 8
PSEL[3:0] CEN MODE
AccessR/WR/WR/WR/W R R R/WR/W
Reset00000000
Bit 76543210
RUNSTDBY ACTION[1:0]
HYST ENABLE
Access R R/W R R/W R/W R/W R/W R
Reset000XXXX0
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Table 15-13. Prescaler Select
zBits 11:10 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 9 – CEN: Clock Enable
0: The BOD33 sampling clock is either disabled and stopped, or enabled but not yet stable.
1: The BOD33 sampling clock is either enabled and stable, or disabled but not yet stopped.
Writing a zero to this bit will stop the BOD33 sampling clock.
Writing a one to this bit will start the BOD33 sampling clock.
zBit 8 – MODE: Operation Mode
0: The BOD33 operates in continuous mode.
1: The BOD33 operates in sampling mode.
zBit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 6 – RUNSTDBY: Run in Standby
0: The BOD33 is disabled in standby sleep mode.
1: The BOD33 is enabled in standby sleep mode.
zBit 5 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
PSEL[3:0] Name Description
0x0 DIV2 Divide clock by 2
0x1 DIV4 Divide clock by 4
0x2 DIV8 Divide clock by 8
0x3 DIV16 Divide clock by 16
0x4 DIV32 Divide clock by 32
0x5 DIV64 Divide clock by 64
0x6 DIV128 Divide clock by 128
0x7 DIV256 Divide clock by 256
0x8 DIV512 Divide clock by 512
0x9 DIV1K Divide clock by 1024
0xA DIV2K Divide clock by 2048
0xB DIV4K Divide clock by 4096
0xC DIV8K Divide clock by 8192
0xD DIV16K Divide clock by 16384
0xE DIV32K Divide clock by 32768
0xF DIV64K Divide clock by 65536
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zBits 4:3 – ACTION[1:0]: BOD33 Action
These bits are used to select the BOD33 action when the supply voltage crosses below the BOD33 threshold.
These bits are loaded from Flash User Row at startup. Refer to “NVM User Row Mapping” on page 25 for more
details.
Table 15-14. BOD33 Action
zBit 2 – HYST: Hysteresis
This bit indicates whether hysteresis is enabled for the BOD33 threshold voltage:
0: No hysteresis.
1: Hysteresis enabled.
This bit is loaded from Flash User Row at startup. Refer to “NVM User Row Mapping” on page 25 for more details.
zBit 1 – ENABLE: Enable
0: BOD33 is disabled.
1: BOD33 is enabled.
This bit is loaded from Flash User Row at startup. Refer to “NVM User Row Mapping” on page 25 for more details.
zBit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
ACTION[1:0] Name Description
0x0 NONE No action
0x1 RESET The BOD33 generates a reset
0x2 INTERRUPT The BOD33 generates an interrupt
0x3 Reserved
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15.8.15 Voltage Regulator System (VREG) Control
Name: VREG
Offset: 0x3C
Reset: 0x0X00
Property: Write-Protected
zBits 15:14 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 13 – FORCELDO: Force LDO Voltage Regulator
0: The voltage regulator is in low power and low drive configuration in standby sleep mode.
1: The voltage regulator is in low power and high drive configuration in standby sleep mode.
zBits 12:7 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 6 – RUNSTDBY: Run in Standby
0: The voltage regulator is in low power configuration in standby sleep mode.
1: The voltage regulator is in normal configuration in standby sleep mode.
zBits 5:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit 151413121110 9 8
FORCELDO
AccessRRR/WRRRRR
Reset00000000
Bit 76543210
RUNSTDBY
AccessRR/WRRRRRR
Reset00000000
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15.8.16 Voltage References System (VREF) Control
Name: VREF
Offset: 0x40
Reset: 0x0XXX0000
Property: Write-Protected
zBits 31:27 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 26:16 – CALIB[10:0]: Bandgap Voltage Generator Calibration
These bits are used to calibrate the output level of the bandgap voltage reference. These bits are loaded from
Flash Calibration Row at startup.
zBits 15:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 2 – BGOUTEN: Bandgap Output Enable
0: The bandgap output is not available as an ADC input channel.
1: The bandgap output is routed to an ADC input channel.
zBit 1 – TSEN: Temperature Sensor Enable
0: Temperature sensor is disabled.
1: Temperature sensor is enabled and routed to an ADC input channel.
Bit 3130292827262524
CALIB[10:8]
AccessRRRRRR/WR/WR/W
Reset00000XXX
Bit 2322212019181716
CALIB[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
ResetXXXXXXXX
Bit 151413121110 9 8
AccessRRRRRRRR
Reset00000000
Bit 76543210
BGOUTEN TSEN
AccessRRRRRR/WR/WR
Reset00000000
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zBit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
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15.8.17 DPLL Control A
Name: DPLLCTRLA
Offset: 0x44
Reset: 0x80
Property: Write-Protected
zBit 7 – ONDEMAND: On Demand Clock Activation
0: The DPLL is always on when enabled.
1: The DPLL is activated only when a peripheral request the DPLL as a source clock. The DPLLCTRLA.ENABLE
bit must be one to validate that operation, otherwise the peripheral request has no effect.
zBit 6 – RUNSTDBY: Run in Standby
0: The DPLL is disabled in standby sleep mode.
1: The DPLL is not stopped in standby sleep mode.
zBits 5:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 1 – ENABLE: DPLL Enable
0: The DPLL is disabled.
1: The DPLL is enabled.
The software operation of enabling or disabling the DPLL takes a few clock cycles, so check the DPLLSTA-
TUS.ENABLE status bit to identify when the DPLL is successfully activated or disabled.
zBit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
Bit 76543210
ONDEMAND RUNSTDBY
ENABLE
AccessR/WR/WRRRRR/WR
Reset10000000
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15.8.18 DPLL Ratio Control
Name: DPLLRATIO
Offset: 0x48
Reset: 0x00000000
Property: Write-Protected
zBits 31:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 19:16 – LDRFRAC[3:0]: Loop Divider Ratio Fractional Part
Write this field with the fractional part of the frequency multiplier.
zBits 15:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 11:0 – LDR[11:0]: Loop Divider Ratio
Write this field with the integer part of the frequency multiplier.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
LDRFRAC[3:0]
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
LDR[11:8]
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 76543210
LDR[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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15.8.19 DPLL Control B
Name: DPLLCTRLB
Offset: 0x4C
Reset: 0x00000000
Property: Write-Protected
zBits 31:27 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 26:16 – DIV[10:0]: Clock Divider
These bits are used to set the XOSC clock source division factor. Refer to “Principle of Operation” on page 153.
zBits 15:13 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 12 – LBYPASS: Lock Bypass
0: Normal Mode: the CLK_FDPLL96M is turned off when lock signal is low.
1: Lock Bypass Mode: the CLK_FDPLL96M is always running, lock is irrelevant.
zBit 11 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
Bit 3130292827262524
DIV[10:8]
AccessRRRRRR/WR/WR/W
Reset00000000
Bit 2322212019181716
DIV[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
LBYPASS LTIME[2:0]
Access R R R R/W R R/W R/W R/W
Reset00000000
Bit 76543210
REFCLK[1:0] WUF LPEN FILTER[1:0]
Access R R R/W R/W R/W R/W R/W R/W
Reset00000000
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zBits 10:8 – LTIME[2:0]: Lock Time
These bits select Lock Timeout.
Table 15-15. Lock Time
zBits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 5:4 – REFCLK[1:0]: Reference Clock Selection
These bits select the CLK_FDPLL96M_REF source.
Table 15-16. Reference Clock Selection
zBit 3 – WUF: Wake Up Fast
0: DPLL CK output is gated until complete startup time and lock time.
1: DPLL CK output is gated until startup time only.
zBit 2 – LPEN: Low-Power Enable
0: The time to digital converter is selected.
1: The time to digital converter is not selected, this will improve power consumption but increase the output jitter.
zBits 1:0 – FILTER[1:0]: Proportional Integral Filter Selection
These bits select the DPLL filter type.
Table 15-17. Proportional Integral Filter Selection
LTIME[2:0] Name Description
0x0 DEFAULT No time-out
0x1-0x3 Reserved
0x4 8MS Time-out if no lock within 8 ms
0x5 9MS Time-out if no lock within 9 ms
0x6 10MS Time-out if no lock within 10 ms
0x7 11MS Time-out if no lock within 11 ms
REFCLK[1:0] Name Description
0x0 XOSC32 XOSC32 clock reference
0x1 XOSC XOSC clock reference
0x2 GCLK_DPLL GCLK_DPLL clock reference
0x3 Reserved
FILTER[1:0] Name Description
0x0 DEFAULT Default filter mode
0x1 LBFILT Low bandwidth filter
0x2 HBFILT High bandwidth filter
0x3 HDFILT High damping filter
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15.8.20 DPLL Status
Name: DPLLSTATUS
Offset: 0x50
Reset: 0x00
Property: -
zBits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 3 – DIV: Divider Enable
0: The reference clock divider is disabled.
1: The reference clock divider is enabled.
zBit 2 – ENABLE: DPLL Enable
0: The DPLL is disabled.
1: The DPLL is enabled.
zBit 1 – CLKRDY: Output Clock Ready
0: The DPLL output clock is off
1: The DPLL output clock in on.
zBit 0 – LOCK: DPLL Lock Status
0: The DPLL Lock signal is cleared.
1: The DPLL Lock signal is asserted.
Bit 76543210
DIV ENABLE CLKRDY LOCK
AccessRRRRRRRR
Reset00000000
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16. WDT – Watchdog Timer
16.1 Overview
The Watchdog Timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover
from error situations such as runaway or deadlocked code. The WDT is configured to a predefined time-out period, and is
constantly running when enabled. If the WDT is not cleared within the time-out period, it will issue a system reset. An
early-warning interrupt is available to indicate an upcoming watchdog time-out condition.
The window mode makes it possible to define a time slot (or window) inside the total time-out period during which the
WDT must be cleared. If the WDT is cleared outside this window, either too early or too late, a system reset will be
issued. Compared to the normal mode, this can also catch situations where a code error causes the WDT to be cleared
frequently.
When enabled, the WDT will run in active mode and all sleep modes. It is asynchronous and runs from a CPU-
independent clock source.The WDT will continue operation and issue a system reset or interrupt even if the main clocks
fail.
16.2 Features
zIssues a system reset if the Watchdog Timer is not cleared before its time-out period
zEarly Warning interrupt generation
zAsynchronous operation from dedicated oscillator
zTwo types of operation:
zNormal mode
zWindow mode
zSelectable time-out periods, from 8 cycles to 16,000 cycles in normal mode or 16 cycles to 32,000 cycles in window
mode
zAlways-on capability
16.3 Block Diagram
Figure 16-1. WDT Block Diagram
GCLK_WDT COUNT
Reset
PER/WINDOW/EWOFFSET
0
CLEAR
0xA5
Early Warning Interrupt
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16.4 Signal Description
Not applicable.
16.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
16.5.1 I/O Lines
Not applicable.
16.5.2 Power Management
The WDT can continue to operate in any sleep mode where the selected source clock is running. The WDT interrupts
can be used to wake up the device from sleep modes. The events can trigger other operations in the system without
exiting sleep modes. Refer to “PM – Power Manager” on page 112 for details on the different sleep modes.
16.5.3 Clocks
The WDT bus clock (CLK_WDT_APB) is enabled by default, and can be enabled and disabled in the Power Manager.
Refer to “PM – Power Manager” on page 112 for details.
A generic clock (GCLK_WDT) is required to clock the WDT. This clock must be configured and enabled in the Generic
Clock Controller before using the WDT. Refer to “GCLK – Generic Clock Controller” on page 90 for details.
This generic clock is asynchronous to the user interface clock (CLK_WDT_APB). Due to this asynchronicity, accessing
certain registers will require synchronization between the clock domains. Refer to “Synchronization” on page 212 for
further details.
GCLK_WDT is intended to be sourced from the clock of the internal ultra-low-power (ULP) oscillator. Due to the ultra-
low-power design, the oscillator is not very accurate, and so the exact time-out period may vary from device to device.
This variation must be kept in mind when designing software that uses the WDT to ensure that the time-out periods used
are valid for all devices. For more information on ULP oscillator accuracy, consult the “Ultra Low Power Internal 32kHz
RC Oscillator (OSCULP32K) Characteristics” on page 1088.
GCLK_WDT can also be clocked from other sources if a more accurate clock is needed, but at the cost of higher power
consumption.
16.5.4 DMA
Not applicable.
16.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the WDT interrupts requires the Interrupt
Controller to be configured first. Refer to “Nested Vector Interrupt Controller” on page 29 for details.
16.5.6 Events
Not applicable.
16.5.7 Debug Operation
When the CPU is halted in debug mode, the WDT will halt normal operation. If the WDT is configured in a way that
requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result
during debugging. The WDT can be forced to halt operation during debugging.
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16.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the
following registers:
zInterrupt Flag Status and Clear register (INTFLAG)
Write-protection is denoted by the Write-Protection property in the register description.
When the CPU is halted in debug mode, all write-protection is automatically disabled.
Write-protection does not apply for accesses through an external debugger. Refer to “PAC – Peripheral Access
Controller” on page 36 for details.
16.5.9 Analog Connections
Not applicable.
16.6 Functional Description
16.6.1 Principle of Operation
The Watchdog Timer (WDT) is a system for monitoring correct program operation, making it possible to recover from
error situations such as runaway code by issuing a reset. When enabled, the WDT is a constantly running timer that is
configured to a predefined time-out period. Before the end of the time-out period, the WDT should be reconfigured.
The WDT has two modes of operation, normal and window. Additionally, the user can enable Early Warning interrupt
generation in each of the modes. The description for each of the basic modes is given below. The settings in the Control
register (CTRL) and the Interrupt Enable register (INTENCLR/SET - refer to INTENCLR) determine the mode of
operation, as illustrated in Table 16-1.
The WDT operating modes are determined by settings of Enable bit in CTRL register (CTRL.ENABLE), Window Mode
Enable bit in CTRL register (CTRL.WEN) and Early Warning Interrupt Enable bit in INTENSET/INTENCLR registers
(INTENSET.EW/ EW.INTENCLR.EW)
16.6.2 Basic Operation
16.6.2.1 Initialization
The following bits are enable-protected:
zWindow Mode Enable in the Control register (CTRL.WEN)
zAlways-On in the Control register (CTRL-ALWAYSON)
The following registers are enable-protected:
zConfiguration register (CONFIG)
zEarly Warning Interrupt Control register (EWCTRL)
Any writes to these bits or registers when the WDT is enabled or is being enabled (CTRL.ENABLE is one) will be
discarded. Writes to these registers while the WDT is being disabled will be completed after the disabling is complete.
Table 16-1. WDT Operating Modes
CTRL.ENABLE CTRL.WEN INTENSET.EW Mode
0 x x Stopped
100Normal
101Normal with Early Warning interrupt
110Window
111Window with Early Warning interrupt
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Enable-protection is denoted by the Enable-Protected property in the register description.
Initialization of the WDT can be done only while the WDT is disabled.
Normal Mode
zDefining the required Time-Out Period bits in the Configuration register (CONFIG.PER).
Normal Mode with Early Warning interrupt
zDefining the required Time-Out Period bits in the Configuration register (CONFIG.PER).
zDefining Early Warning Interrupt Time Offset bits in the Early Warning Interrupt Control register (EWCTRL.
EWOFFSET).
zSetting Early Warning Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.EW).
Window Mode
zDefining Time-Out Period bits in the Configuration register (CONFIG.PER).
zDefining Window Mode Time-Out Period bits in the Configuration register (CONFIG.WINDOW).
zSetting Window Enable bit in the Control register (CTRL.WEN).
Window Mode with Early Warning interrupt
zDefining Time-Out Period bits in the Configuration register (CONFIG.PER).
zDefining Window Mode Time-Out Period bits in the Configuration register (CONFIG.WINDOW).
zSetting Window Enable bit in the Control register (CTRL.WEN).
zDefining Early Warning Interrupt Time Offset bits in the Early Warning Interrupt Control register (EWCTRL.
EWOFFSET).
zSetting Early Warning Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.EW).
16.6.2.2 Configurable Reset Values
On a power-on reset, some registers will be loaded with initial values from the NVM User Row. Refer to “NVM User Row
Mapping” on page 25 for more details.
This encompasses the following bits and bit groups:
zEnable bit in the Control register (CTRL.ENABLE)
zAlways-On bit in the Control register (CTRL.ALWAYSON)
zWatchdog Timer Windows Mode Enable bit in the Control register (CTRL.WEN)
zWatchdog Timer Windows Mode Time-Out Period bits in the Configuration register (CONFIG.WINDOW)
zTime-Out Period in the Configuration register (CONFIG.PER)
zEarly Warning Interrupt Time Offset bits in the Early Warning Interrupt Control register (EWCTRL.EWOFFSET)
For more information about fuse locations, see “NVM User Row Mapping” on page 25.
16.6.2.3 Enabling and Disabling
The WDT is enabled by writing a one to the Enable bit in the Control register (CTRL.ENABLE). The WDT is disabled by
writing a zero to CTRL.ENABLE.
The WDT can be disabled only while the Always-On bit in the Control register (CTRL.ALWAYSON) is zero.
16.6.2.4 Normal Mode
In normal-mode operation, the length of a time-out period is configured in CONFIG.PER. The WDT is enabled by writing
a one to the Enable bit in the Control register (CTRL.ENABLE). Once enabled, if the WDT is not cleared from the
application code before the time-out occurs, the WDT will issue a system reset. There are 12 possible WDT time-out
(TOWDT) periods, selectable from 8ms to 16s, and the WDT can be cleared at any time during the time-out period. A new
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WDT time-out period will be started each time the WDT is cleared by writing 0xA5 to the Clear register (CLEAR). Writing
any value other than 0xA5 to CLEAR will issue an immediate system reset.
By default, WDT issues a system reset upon a time-out, and the early warning interrupt is disabled. If an early warning
interrupt is required, the Early Warning Interrupt Enable bit in the Interrupt Enable register (INTENSET.EW) must be
enabled. Writing a one to the Early Warning Interrupt bit in the Interrupt Enable Set register (INTENSET.EW) enables the
interrupt, and writing a one to the Early Warning Interrupt bit in the Interrupt Enable Clear register (INTENCLR.EW)
disables the interrupt. If the Early Warning Interrupt is enabled, an interrupt is generated prior to a watchdog time-out
condition. In normal mode, the Early Warning Offset bits in the Early Warning Interrupt Control register
(EWCTRL.EWOFFSET) define the time where the early warning interrupt occurs. The normal-mode operation is
illustrated in Figure 16-2.
The Early Warning Offset bits define the number of GCLK_WDT clocks before the interrupt is generated, relative to the
start of the watchdog time-out period. For example, if the WDT is operating in normal mode with CONFIG.PER = 0x2 and
EWCTRL.EWOFFSET = 0x1, the Early Warning interrupt is generated 16 GCLK_WDT clock cycles from the start of the
watchdog time-out period, and the watchdog time-out system reset is generated 32 GCLK_WDT clock cycles from the
start of the watchdog time-out period. The user must take caution when programming the Early Warning Offset bits. If
these bits define an Early Warning interrupt generation time greater than the watchdog time-out period, the watchdog
time-out system reset is generated prior to the Early Warning interrupt. Thus, the Early Warning interrupt will never be
generated.
Figure 16-2. Normal-Mode Operation
16.6.2.5 Window Mode
In window-mode operation, the WDT uses two different time-out periods, a closed window time-out period (TOWDTW) and
the normal, or open, time-out period (TOWDT). The closed window time-out period defines a duration from 8ms to 16s
where the WDT cannot be reset. If the WDT is cleared during this period, the WDT will issue a system reset. The normal
WDT time-out period, which is also from 8ms to 16s, defines the duration of the open period during which the WDT can
be cleared. The open period will always follow the closed period, and so the total duration of the time-out period is the
sum of the closed window and the open window time-out periods. The closed window is defined by the Window Period
bits in the Configuration register (CONFIG.WINDOW), and the open window is defined by the Period bits in the
Configuration register (CONFIG.PER).
By default, the WDT issues a system reset upon a time-out and the Early Warning interrupt is disabled. If an Early
Warning interrupt is required, INTENCLR/SET.EW must be set. Writing a one to INTENSET.EW enables the interrupt,
and writing a one to INTENCLR.EW disables the interrupt. If the Early Warning interrupt is enabled in window mode, the
interrupt is generated at the start of the open window period.
In a typical application where the system is in sleep mode, it can use this interrupt to wake up and clear the Watchdog
Timer, after which the system can perform other tasks or return to sleep mode.
t [ms]
WDT Count
510
15 20 25 30 35
PER[3:0]=1
Timely WDT Clear
TO
WDT
WDT Timeout
System Reset
EWOFFSET[3:0]=0
Early Warning Interrupt
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The window mode operation is illustrated in Figure 16-3.
Figure 16-3. Window-Mode Operation
16.6.3 Additional Features
16.6.3.1 Always-On Mode
The always-on mode is enabled by writing a one to the Always-On bit in the Control register (CTRL.ALWAYSON). When
the always-on mode is enabled, the WDT runs continuously, regardless of the state of CTRL.ENABLE. Once written, the
Always-On bit can only be cleared by a power-on reset. The Configuration (CONFIG) and Early Warning Control
(EWCTRL) registers are read-only registers while the CTRL.ALWAYSON bit is set. Thus, the time period configuration
bits (CONFIG.PER, CONFIG.WINDOW, EWCTRL.EWOFFSET) of the WDT cannot be changed.
Enabling or disabling window-mode operation by writing the Window Enable bit (CTRL.WEN) is allowed while in the
always-on mode, but note that CONFIG.PER cannot be changed.
The Interrupt Clear and Interrupt Set registers are accessible in the always-on mode. The Early Warning interrupt can still
be enabled or disabled while in the always-on mode, but note that EWCTRL.EWOFFSET cannot be changed.
Table 16-2 shows the operation of the WDT when CTRL.ALWAYSON is set.
Table 16-2. WDT Operating Modes With Always-On
16.6.4 Interrupts
The WDT has the following interrupt sources:
zEarly Warning (EW): this is an asynchronous interrupt and can be used to wake-up the device from any sleep
mode.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one
to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the
t [ms]
WDT Count
510
15 20 25 30 35
WINDOW[3:0]=0
PER[3:0]=0
Timely WDT Clear
Closed
TO
WDTW
Open
TO
WDT
Early WDT Clear
WDT Timeout
Early Warning Interrupt
CTRL.WEN INTENSET.EW Mode
0 0 Always-on and normal mode
0 1 Always-on and normal mode with Early Warning interrupt
1 0 Always-on and window mode
1 1 Always-on and window mode with Early Warning interrupt
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corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is
cleared, the interrupt is disabled or the WDT is reset. See INTFLAG for details on how to clear interrupt flags.
The WDT has one common interrupt request line for all the interrupt sources. The user must read INTFLAG to determine
which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to “Nested Vector Interrupt
Controller” on page 29 for details.
16.6.5 Synchronization
Due to the asynchronicity between CLK_WDT_APB and GCLK_WDT some registers must be synchronized when
accessed. A register can require:
zSynchronization when written
zSynchronization when read
zSynchronization when written and read
zNo synchronization
When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. The Synchronization
Ready interrupt can be used to signal when synchronization is complete. This can be accessed via the Synchronization
Ready Interrupt Flag in the Interrupt Flag Status and Clear register (INTFLAG.SYNCRDY).
If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is
stalled.
The following registers need synchronization when written:
zControl register (CTRL)
zClear register (CLEAR)
Write-synchronization is denoted by the Write-Synchronized property in the register description.
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16.7 Register Summary
Table 16-3. Register Summary
Offset Name
Bit
Pos.
0x0 CTRL 7:0 ALWAYSON WEN ENABLE
0x1 CONFIG 7:0 WINDOW[3:0] PER[3:0]
0x2 EWCTRL 7:0 EWOFFSET[3:0]
0x3 Reserved
0x4 INTENCLR 7:0 EW
0x5 INTENSET 7:0 EW
0x6 INTFLAG 7:0 EW
0x7 STATUS 7:0 SYNCBUSY
0x8 CLEAR 7:0 CLEAR[7:0]
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16.8 Register Description
Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters
and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by
the Write-Protected property in each individual register description. Please refer to “Register Access Protection” on page
208 for details.
Some registers require synchronization when read and/or written. Synchronization is denoted by the Write-Synchronized
or the Read-Synchronized property in each individual register description. Please refer to “Synchronization” on page 212
for details.
Some registers are enable-protected, meaning they can be written only when the WDT is disabled. Enable-protection is
denoted by the Enable-Protected property in each individual register description.
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16.8.1 Control
Name: CTRL
Offset: 0x0
Reset: 0xXX
Property: Enable-Protected, Write-Protected, Write-Synchronized
zBit 7 – ALWAYSON: Always-On
This bit allows the WDT to run continuously. After being written to one, this bit cannot be written to zero, and the
WDT will remain enabled until a power-on reset is received. When this bit is one, the Control register (CTRL), the
Configuration register (CONFIG) and the Early Warning Control register (EWCTRL) will be read-only, and any
writes to these registers are not allowed. Writing a zero to this bit has no effect.
0: The WDT is enabled and disabled through the ENABLE bit.
1: The WDT is enabled and can only be disabled by a power-on reset (POR).
This bit is not enable-protected.
This bit is loaded from NVM User Row at startup. Refer to “NVM User Row Mapping” on page 25 for more details.
zBits 6:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 2 – WEN: Watchdog Timer Window Mode Enable
This bit enables window mode.
This bit can only be written when CTRL.ENABLE is zero or CTRL.ALWAYSON is one:
zWhen CTRL.ALWAYSON=0, this bit is enable-protected by CTRL.ENABLE.
zWhen CTRL.ALWAYSON=1 this bit is not enable-protected by CTRL.ENABLE.
The initial value of this bit is loaded from Flash Calibration.
0: Window mode is disabled (normal operation).
1: Window mode is enabled.
This bit is loaded from NVM User Row at startup. Refer to “NVM User Row Mapping” on page 25 for more details.
zBit 1 – ENABLE: Enable
This bit enables or disables the WDT. Can only be written while CTRL.ALWAYSON is zero.
0: The WDT is disabled.
1: The WDT is enabled.
Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/disabled. The
value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete.
This bit is not enable-protected.
This bit is loaded from NVM User Row at startup. Refer to “NVM User Row Mapping” on page 25 for more details.
zBit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
Bit 76543210
ALWAYSON
WEN ENABLE
AccessR/WRRRRR/WR/WR
ResetX0000XX0
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16.8.2 Configuration
Name: CONFIG
Offset: 0x1
Reset: 0xXX
Property: Enable-Protected, Write-Protected, Write-Synchronized
zBits 7:4 – WINDOW[3:0]: Window Mode Time-Out Period
In window mode, these bits determine the watchdog closed window period as a number of oscillator cycles. The
closed window periods are defined in Table 16-4.
These bits are loaded from NVM User Row at startup. Refer to “NVM User Row Mapping” on page 25 for more
details.
Table 16-4. Window Mode Time-Out Period
zBits 3:0 – PER[3:0]: Time-Out Period
These bits determine the watchdog time-out period as a number of GCLK_WDT clock cycles. In window mode
operation, these bits define the open window period. The different typical time-out periods are found in Table 16-5.
These bits are loaded from NVM User Row at startup. Refer to “NVM User Row Mapping” on page 25 for more
details.
Bit 76543210
WINDOW[3:0] PER[3:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
ResetXXXXXXXX
WINDOW[3:0] Description
0x0 8 clock cycles
0x1 16 clock cycles
0x2 32 clock cycles
0x3 64 clock cycles
0x4 128 clock cycles
0x5 256 clock cycles
0x6 512 clock cycles
0x7 1024 clock cycles
0x8 2048 clock cycles
0x9 4096 clock cycles
0xA 8192 clock cycles
0xB 16384 clock cycles
0xC-0xF Reserved
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Table 16-5. Time-Out Period
PER[3:0] Description
0x0 8 clock cycles
0x1 16 clock cycles
0x2 32 clock cycles
0x3 64 clock cycles
0x4 128 clock cycles
0x5 256 clock cycles
0x6 512 clock cycles
0x7 1024 clock cycles
0x8 2048 clock cycles
0x9 4096 clock cycles
0xA 8192 clock cycles
0xB 16384 clock cycles
0xC-0xF Reserved
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16.8.3 Early Warning Interrupt Control
Name: EWCTRL
Offset: 0x2
Reset: 0x0X
Property: Enable-Protected, Write-Protected
zBits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 3:0 – EWOFFSET[3:0]: Early Warning Interrupt Time Offset
These bits determine the number of GCLK_WDT clocks in the offset from the start of the watchdog time-out period
to when the Early Warning interrupt is generated. The Early Warning Offset is defined in Table 16-6. These bits
are loaded from NVM User Row at startup. Refer to “NVM User Row Mapping” on page 25 for more details.
Table 16-6. Early Warning Interrupt Time Offset
Bit 76543210
EWOFFSET[3:0]
AccessRRRRR/WR/WR/WR/W
Reset0000XXXX
EWOFFSET[3:0] Description
0x0 8 clock cycles
0x1 16 clock cycles
0x2 32 clock cycles
0x3 64 clock cycles
0x4 128 clock cycles
0x5 256 clock cycles
0x6 512 clock cycles
0x7 1024 clock cycles
0x8 2048 clock cycles
0x9 4096 clock cycles
0xA 8192 clock cycles
0xB 16384 clock cycles
0xC-0xF Reserved
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16.8.4 Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x4
Reset: 0x00
Property: Write-Protected
zBits 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 0 – EW: Early Warning Interrupt Enable
0: The Early Warning interrupt is disabled.
1: The Early Warning interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit disables the Early Warning interrupt.
Bit 76543210
EW
AccessRRRRRRRR/W
Reset00000000
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16.8.5 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name: INTENSET
Offset: 0x5
Reset: 0x00
Property: Write-Protected
zBits 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 0 – EW: Early Warning Interrupt Enable
0: The Early Warning interrupt is disabled.
1: The Early Warning interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit enables the Early Warning interrupt.
Bit 76543210
EW
AccessRRRRRRRR/W
Reset00000000
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16.8.6 Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x6
Reset: 0x00
Property: -
zBits 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 0 – EW: Early Warning
This flag is set when an Early Warning interrupt occurs, as defined by the EWOFFSET bit group in EWCTRL.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Early Warning interrupt flag.
Bit 76543210
EW
AccessRRRRRRRR/W
Reset00000000
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16.8.7 Status
Name: STATUS
Offset: 0x7
Reset: 0x00
Property: -
zBit 7 – SYNCBUSY: Synchronization Busy
This bit is cleared when the synchronization of registers between clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
zBits 6:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit 76543210
SYNCBUSY
AccessRRRRRRRR
Reset00000000
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16.8.8 Clear
Name: CLEAR
Offset: 0x8
Reset: 0x00
Property: Write-Protected, Write-Synchronized
zBits 7:0 – CLEAR[7:0]: Watchdog Clear
Writing 0xA5 to this register will clear the Watchdog Timer and the watchdog time-out period is restarted. Writing
any other value will issue an immediate system reset.
Table 16-7. Watchdog Clear
Bit 76543210
CLEAR[7:0]
AccessWWWWWWWW
Reset00000000
CLEAR[7:0] Name Description
0x0-0xA4 Reserved
0xA5 KEY Clear Key
0xA6-0xFF Reserved
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17. RTC – Real-Time Counter
17.1 Overview
The Real-Time Counter (RTC) is a 32-bit counter with a 10-bit programmable prescaler that typically runs continuously to
keep track of time. The RTC can wake up the device from sleep modes using the alarm/compare wake up, periodic wake
up or overflow wake up mechanisms.
The RTC is typically clocked by the 1.024kHz output from the 32.768kHz High-Accuracy Internal Crystal
Oscillator(OSC32K) and this is the configuration optimized for the lowest power consumption. The faster 32.768kHz
output can be selected if the RTC needs a resolution higher than 1ms. The RTC can also be clocked from other sources,
selectable through the Generic Clock module (GCLK).
The RTC can generate periodic peripheral events from outputs of the prescaler, as well as alarm/compare interrupts and
peripheral events, which can trigger at any counter value. Additionally, the timer can trigger an overflow interrupt and
peripheral event, and be reset on the occurrence of an alarm/compare match. This allows periodic interrupts and
peripheral events at very long and accurate intervals.
The 10-bit programmable prescaler can scale down the clock source, and so a wide range of resolutions and time-out
periods can be configured. With a 32.768kHz clock source, the minimum counter tick interval is 30.5µs, and time-out
periods can range up to 36 hours. With the counter tick interval configured to 1s, the maximum time-out period is more
than 136 years.
17.2 Features
z32-bit counter with 10-bit prescaler
zMultiple clock sources
z32-bit or 16-bit Counter mode
zOne 32-bit or two 16-bit compare values
zClock/Calendar mode
zTime in seconds, minutes and hours (12/24)
zDate in day of month, month and year
zLeap year correction
zDigital prescaler correction/tuning for increased accuracy
zOverflow, alarm/compare match and prescaler interrupts and events
zOptional clear on alarm/compare match
17.3 Block Diagram
Figure 17-1. RTC Block Diagram (Mode 0 — 32-Bit Counter)
COUNT
COMPn
=Compare n
Overflow
0
MATCHCLR
10-bit
Prescaler
GCLK_RTC CLK_RTC_CNT
32
Periodic
Events
32
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Figure 17-2. RTC Block Diagram (Mode 1 — 16-Bit Counter)
Figure 17-3. RTC Block Diagram (Mode 2 — Clock/Calendar)
17.4 Signal Description
Not applicable.
17.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
17.5.1 I/O Lines
Not applicable.
17.5.2 Power Management
The RTC can continue to operate in any sleep mode. The RTC interrupts can be used to wake up the device from sleep
modes. The events can trigger other operations in the system without exiting sleep modes. Refer to “PM – Power
Manager” on page 112 for details on the different sleep modes.
The RTC will be reset only at power-on (POR) or by writing a one to the Software Reset bit in the Control register
(CTRL.SWRST).
10-bit
Prescaler
GCLK_RTC
COUNT
PER
Overflow
0
COMPn
Compare n
CLK_RTC_CNT
16
Periodic
Events
16
16
=
=
CLOCK
ALARMn
=Alarm n
Overflow
0
MATCHCLR
10-bit
Prescaler
GCLK_RTC CLK_RTC_CNT
32
Periodic
Events
32
MASKn
Y/M/D H:M:S
Y/M/D H:M:S
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17.5.3 Clocks
The RTC bus clock (CLK_RTC_APB) can be enabled and disabled in the Power Manager, and the default state of
CLK_RTC_APB can be found in the Peripheral Clock Masking section in the “PM – Power Manager” on page 112.
A generic clock (GCLK_RTC) is required to clock the RTC. This clock must be configured and enabled in the Generic
Clock Controller before using the RTC. Refer to “GCLK – Generic Clock Controller” on page 90 for details.
This generic clock is asynchronous to the user interface clock (CLK_RTC_APB). Due to this asynchronicity, accessing
certain registers will require synchronization between the clock domains. Refer to “Synchronization” on page 231 for
further details.
The RTC should never be used with the generic clock generator 0.
17.5.4 DMA
Not applicable.
17.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the RTC interrupts requires the Interrupt
Controller to be configured first. Refer to “Nested Vector Interrupt Controller” on page 29 for details.
17.5.6 Events
To use the RTC event functionality, the corresponding events need to be configured in the event system. Refer to
“EVSYS – Event System” on page 400 for details.
17.5.7 Debug Operation
When the CPU is halted in debug mode the RTC will halt normal operation. The RTC can be forced to continue operation
during debugging. Refer to the Debug Control (DBGCTRL) register for details.
17.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the
following registers:
zInterrupt Flag Status and Clear register ( INTFLAG)
zRead Request register (READREQ)
zStatus register (STATUS)
zDebug register (DBGCTRL)
Write-protection is denoted by the Write-Protection property in the register description.
When the CPU is halted in debug mode, all write-protection is automatically disabled.
Write-protection does not apply for accesses through an external debugger. Refer to “PAC – Peripheral Access
Controller” on page 36 for details.
17.5.9 Analog Connections
A 32.768kHz crystal can be connected to the XIN32 and XOUT32 pins, along with any required load capacitors. For
details on recommended crystal characteristics and load capacitors, refer to “Electrical Characteristics” on page 1055 for
details.
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17.6 Functional Description
17.6.1 Principle of Operation
The RTC keeps track of time in the system and enables periodic events, as well as interrupts and events at a specified
time. The RTC consists of a 10-bit prescaler that feeds a 32-bit counter. The actual format of the 32-bit counter depends
on the RTC operating mode.
17.6.2 Basic Operation
17.6.2.1 Initialization
The following bits are enable-protected, meaning that they can only be written when the RTC is disabled (CTRL.ENABLE
is zero):
zOperating Mode bits in the Control register (CTRL.MODE)
zPrescaler bits in the Control register (CTRL.PRESCALER)
zClear on Match bit in the Control register (CTRL.MATCHCLR)
zClock Representation bit in the Control register (CTRL.CLKREP)
The following register is enable-protected:
zEvent Control register (EVCTRL)
Any writes to these bits or registers when the RTC is enabled or being enabled (CTRL.ENABLE is one) will be discarded.
Writes to these bits or registers while the RTC is being disabled will be completed after the disabling is complete.
Enable-protection is denoted by the Enable-Protection property in the register description.
Before the RTC is enabled, it must be configured, as outlined by the following steps:
zRTC operation mode must be selected by writing the Operating Mode bit group in the Control register
(CTRL.MODE)
zClock representation must be selected by writing the Clock Representation bit in the Control register
(CTRL.CLKREP)
zPrescaler value must be selected by writing the Prescaler bit group in the Control register (CTRL.PRESCALER)
The RTC prescaler divides down the source clock for the RTC counter. The frequency of the RTC clock
(CLK_RTC_CNT) is given by the following formula:
The frequency of the generic clock, GCLK_RTC, is given by fGCLK_RTC, and fCLK_RTC_CNT is the frequency of the internal
prescaled RTC clock, CLK_RTC_CNT.
Note that in the Clock/Calendar mode, the prescaler must be configured to provide a 1Hz clock to the counter for correct
operation.
17.6.2.2 Enabling, Disabling and Resetting
The RTC is enabled by writing a one to the Enable bit in the Control register (CTRL.ENABLE). The RTC is disabled by
writing a zero to CTRL.ENABLE.
The RTC should be disabled before resetting it.
The RTC is reset by writing a one to the Software Reset bit in the Control register (CTRL.SWRST). All registers in the
RTC, except DBGCTRL, will be reset to their initial state, and the RTC will be disabled.
Refer to the CTRL register for details.
fCLK_RTC_CNT
fGCLK_RTC
2PRESCALER
-----------------------------
=
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17.6.3 Operating Modes
The RTC counter supports three RTC operating modes: 32-bit Counter, 16-bit Counter and Clock/Calendar. The
operating mode is selected by writing to the Operating Mode bit group in the Control register (CTRL.MODE).
17.6.3.1 32-Bit Counter (Mode 0)
When the RTC Operating Mode bits in the Control register (CTRL.MODE) are zero, the counter operates in 32-bit
Counter mode. The block diagram of this mode is shown in Figure 17-1. When the RTC is enabled, the counter will
increment on every 0-to-1 transition of CLK_RTC_CNT. The counter will increment until it reaches the top value of
0xFFFFFFFF, and then wrap to 0x00000000. This sets the Overflow interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG.OVF).
The RTC counter value can be read from or written to the Counter Value register (COUNT) in 32-bit format.
The counter value is continuously compared with the 32-bit Compare register (COMP0). When a compare match occurs,
the Compare 0interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMP0) is set on the next 0-to-1
transition of CLK_RTC_CNT.
If the Clear on Match bit in the Control register (CTRL.MATCHCLR) is one, the counter is cleared on the next counter
cycle when a compare match with COMP0 occurs. This allows the RTC to generate periodic interrupts or events with
longer periods than are possible with the prescaler events. Note that when CTRL.MATCHCLR is one, INTFLAG.CMP0
and INTFLAG.OVF will both be set simultaneously on a compare match with COMP0.
17.6.3.2 16-Bit Counter (Mode 1)
When CTRL.MODE is one, the counter operates in 16-bit Counter mode as shown in Figure 17-2. When the RTC is
enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. In 16-bit Counter mode, the 16-bit
Period register (PER) holds the maximum value of the counter. The counter will increment until it reaches the PER value,
and then wrap to 0x0000. This sets the Overflow interrupt flag in the Interrupt Flag Status and Clear register
(INTFLAG.OVF).
The RTC counter value can be read from or written to the Counter Value register (COUNT) in 16-bit format.
The counter value is continuously compared with the 16-bit Compare registers (COMPn, n=0–1). When a compare
match occurs, the Compare n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn, n=0–1) is set
on the next 0-to-1 transition of CLK_RTC_CNT.
17.6.3.3 Clock/Calendar (Mode 2)
When CTRL.MODE is two, the counter operates in Clock/Calendar mode, as shown in Figure 17-3. When the RTC is
enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. The selected clock source and RTC
prescaler must be configured to provide a 1Hz clock to the counter for correct operation in this mode.
The time and date can be read from or written to the Clock Value register (CLOCK) in a 32-bit time/date format. Time is
represented as:
zSeconds
zMinutes
zHours
Hours can be represented in either 12- or 24-hour format, selected by the Clock Representation bit in the Control register
(CTRL.CLKREP). This bit can be changed only while the RTC is disabled.
Date is represented as:
zDay as the numeric day of the month (starting at 1)
zMonth as the numeric month of the year (1 = January, 2 = February, etc.)
zYear as a value counting the offset from a reference value that must be defined in software
The date is automatically adjusted for leap years, assuming every year divisible by 4 is a leap year. Therefore, the
reference value must be a leap year, e.g. 2000. The RTC will increment until it reaches the top value of 23:59:59
December 31st of year 63, and then wrap to 00:00:00 January 1st of year 0. This will set the Overflow interrupt flag in the
Interrupt Flag Status and Clear registers (INTFLAG.OVF).
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The clock value is continuously compared with the 32-bit Alarm register (ALARM0). When an alarm match occurs, the
Alarm 0 Interrupt flag in the Interrupt Flag Status and Clear registers (INTFLAG.ALARMn0) is set on the next 0-to-1
transition of CLK_RTC_CNT.
A valid alarm match depends on the setting of the Alarm Mask Selection bits in the Alarm 0 Mask register (MASK0.SEL).
These bits determine which time/date fields of the clock and alarm values are valid for comparison and which are
ignored.
If the Clear on Match bit in the Control register (CTRL.MATCHCLR) is one, the counter is cleared on the next counter
cycle when an alarm match with ALARM0 occurs. This allows the RTC to generate periodic interrupts or events with
longer periods than are possible with the prescaler events (see “Periodic Events” on page 229). Note that when
CTRL.MATCHCLR is one, INTFLAG.ALARM0 and INTFLAG.OVF will both be set simultaneously on an alarm match
with ALARM0.
17.6.4 Additional Features
17.6.4.1 Periodic Events
The RTC prescaler can generate events at periodic intervals, allowing flexible system tick creation. Any of the upper
eight bits of the prescaler (bits 2 to 9) can be the source of an event. When one of the Periodic Event Output bits in the
Event Control register (EVCTRL.PEREOn) is one, an event is generated on the 0-to1 transition of the related bit in the
prescaler, resulting in a periodic event frequency of:
fGCLK_RTC is the frequency of the internal prescaler clock, GCLK_RTC, and n is the position of the EVCTRL.PEREOn bit.
For example, PEREO will generate an event every 8 GCLK_RTC cycles, PEREO1 every 16 cycles, etc. This is shown in
Figure 17-4. Periodic events are independent of the prescaler setting used by the RTC counter, except if
CTRL.PRESCALER is zero. Then, no periodic events will be generated.
Figure 17-4. Example Periodic Events
17.6.4.2 Frequency Correction
The RTC Frequency Correction module employs periodic counter corrections to compensate for a too-slow or too-fast
oscillator. Frequency correction requires that CTRL.PRESCALER is greater than 1.
The digital correction circuit adds or subtracts cycles from the RTC prescaler to adjust the frequency in approximately
1PPM steps. Digital correction is achieved by adding or skipping a single count in the prescaler once every 1024
GCLK_RTC cycles. The Value bit group in the Frequency Correction register (FREQCORR.VALUE) determines the
number of times the adjustment is applied over 976 of these periods. The resulting correction is as follows:
3
_
2+
=n
RTCGCLK
PERIODIC
f
f
PEREO0
PEREO1
PEREO2
PEREO3
PEREO4
GCLK_RTC
Correction in PPM FREQCORR.VALUE
1024 976⋅
----------------------------------------------------- 106PPM⋅=
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This results in a resolution of 1.0006PPM.
The Sign bit in the Frequency Correction register (FREQCORR.SIGN) determines the direction of the correction. A
positive value will speed up the frequency, and a negative value will slow down the frequency.
Digital correction also affects the generation of the periodic events from the prescaler. When the correction is applied at
the end of the correction cycle period, the interval between the previous periodic event and the next occurrence may also
be shortened or lengthened depending on the correction value.
17.6.5 DMA Operation
Not applicable.
17.6.6 Interrupts
The RTC has the following interrupt sources:
zOverflow (INTFLAG.OVF): this is an asynchronous interrupt and can be used to wake-up the device from any
sleep mode.
zCompare n (INTFLAG.CMPn): this is an asynchronous interrupt and can be used to wake-up the device from any
sleep mode.
zAlarm n (INTFLAG.ALARMn): this is an asynchronous interrupt and can be used to wake-up the device from any
sleep mode.
zSynchronization Ready (INTFLAG.SYNCRDY): this is an asynchronous interrupt and can be used to wake-up the
device from any sleep mode.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one
to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is
cleared, the interrupt is disabled or the RTC is reset. See INTFLAG for details on how to clear interrupt flags. The RTC
has one common interrupt request line for all the interrupt sources. The user must read INTFLAG to determine which
interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to “Nested Vector Interrupt
Controller” on page 29 for details.
17.6.7 Events
The RTC can generate the following output events, which are generated in the same way as the corresponding
interrupts:
zOverflow (OVF)
zPeriod n (PERn)
zCompare n (CMPn)
zAlarm n (ALARMn)
Output events must be enabled to be generated. Writing a one to an Event Output bit in the Event Control register
(EVCTRL.xxEO) enables the corresponding output event. Writing a zero to this bit disables the corresponding output
event. Refer to “EVSYS – Event System” on page 400 for details.
17.6.8 Sleep Mode Operation
The RTC will continue to operate in any sleep mode where the source clock is active. The RTC interrupts can be used to
wake up the device from a sleep mode, or the RTC events can trigger other operations in the system without exiting the
sleep mode.
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An interrupt request will be generated after the wake-up if the Interrupt Controller is configured accordingly. Otherwise
the CPU will wake up directly, without triggering an interrupt. In this case, the CPU will continue executing from the
instruction following the entry into sleep.
The periodic events can also wake up the CPU through the interrupt function of the Event System. In this case, the event
must be enabled and connected to an event channel with its interrupt enabled. See “EVSYS – Event System” on page
400 for more information.
17.6.9 Synchronization
Due to the asynchronicity between CLK_RTC_APB and GCLK_RTC some registers must be synchronized when
accessed. A register can require:
zSynchronization when written
zSynchronization when read
zSynchronization when written and read
zNo synchronization
When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. The Synchronization
Ready interrupt can be used to signal when synchronization is complete. This can be accessed via the Synchronization
Ready Interrupt Flag in the Interrupt Flag Status and Clear register (INTFLAG.SYNCRDY).
If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is
stalled.
The following bits need synchronization when written:
zSoftware Reset bit in the Control register (CTRL.SWRST)
zEnable bit in the Control register (CTRL.ENABLE)
The following registers need synchronization when written:
zThe Counter Value register (COUNT)
zThe Clock Value register (CLOCK)
zThe Counter Period register (PER)
zThe Compare n Value registers (COMPn)
zThe Alarm n Value registers (ALARMn)
zThe Frequency Correction register (FREQCORR)
zThe Alarm n Mask register (MASKn)
Write-synchronization is denoted by the Write-Synchronization property in the register description.
The following registers need synchronization when read:
zThe Counter Value register (COUNT)
zThe Clock Value register (CLOCK)
Read-synchronization is denoted by the Read-Synchronization property in the register description.
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17.7 Register Summary
The register mapping depends on the Operating Mode bits in the Control register (CTRL.MODE). The register summary
is presented for each of the three modes.
Table 17-1. MODE0 - Mode Register Summary
Table 17-2. MODE1 - Mode Register Summary
Offset Name
Bit
Pos.
0x00
CTRL
7:0 MATCHCLR MODE[1:0] ENABLE SWRST
0x01 15:8 PRESCALER[3:0]
0x02
READREQ
7:0 ADDR[5:0]
0x03 15:8 RREQ RCONT
0x04
EVCTRL
7:0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0
0x05 15:8 OVFEO CMPEO0
0x06 INTENCLR 7:0 OVF SYNCRDY CMP0
0x07 INTENSET 7:0 OVF SYNCRDY CMP0
0x08 INTFLAG 7:0 OVF SYNCRDY CMP0
0x09 Reserved
0x0A STATUS 7:0 SYNCBUSY
0x0B DBGCTRL 7:0 DBGRUN
0x0C FREQCORR 7:0 SIGN VALUE[6:0]
0x0D
...
0x0F
Reserved
0x10
COUNT
7:0 COUNT[7:0]
0x11 15:8 COUNT[15:8]
0x12 23:16 COUNT[23:16]
0x13 31:24 COUNT[31:24]
0x14
...
0x17
Reserved
0x18
COMP0
7:0 COMP[7:0]
0x19 15:8 COMP[15:8]
0x1A 23:16 COMP[23:16]
0x1B 31:24 COMP[31:24]
Offset Name
Bit
Pos.
0x00
CTRL
7:0 MODE[1:0] ENABLE SWRST
0x01 15:8 PRESCALER[3:0]
0x02
READREQ
7:0 ADDR[5:0]
0x03 15:8 RREQ RCONT
0x04
EVCTRL
7:0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0
0x05 15:8 OVFEO CMPEO1 CMPEO0
0x06 INTENCLR 7:0 OVF SYNCRDY CMP1 CMP0
0x07 INTENSET 7:0 OVF SYNCRDY CMP1 CMP0
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Table 17-3. MODE2 - Mode Register Summary
0x08 INTFLAG 7:0 OVF SYNCRDY CMP1 CMP0
0x09 Reserved
0x0A STATUS 7:0 SYNCBUSY
0x0B DBGCTRL 7:0 DBGRUN
0x0C FREQCORR 7:0 SIGN VALUE[6:0]
0x0D
...
0x0F
Reserved
0x10
COUNT
7:0 COUNT[7:0]
0x11 15:8 COUNT[15:8]
0x12 Reserved
0x13 Reserved
0x14
PER
7:0 PER[7:0]
0x15 15:8 PER[15:8]
0x16 Reserved
0x17 Reserved
0x18
COMP0
7:0 COMP[7:0]
0x19 15:8 COMP[15:8]
0x1A
COMP1
7:0 COMP[7:0]
0x1B 15:8 COMP[15:8]
Offset Name
Bit
Pos.
0x00
CTRL
7:0 MATCHCLR CLKREP MODE[1:0] ENABLE SWRST
0x01 15:8 PRESCALER[3:0]
0x02
READREQ
7:0 ADDR[5:0]
0x03 15:8 RREQ RCONT
0x04
EVCTRL
7:0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0
0x05 15:8 OVFEO ALARMEO0
0x06 INTENCLR 7:0 OVF SYNCRDY ALARM0
0x07 INTENSET 7:0 OVF SYNCRDY ALARM0
0x08 INTFLAG 7:0 OVF SYNCRDY ALARM0
0x09 Reserved
0x0A STATUS 7:0 SYNCBUSY
0x0B DBGCTRL 7:0 DBGRUN
0x0C FREQCORR 7:0 SIGN VALUE[6:0]
0x0D
...
0x0F
Reserved
0x10
CLOCK
7:0 MINUTE[1:0] SECOND[5:0]
0x11 15:8 HOUR[3:0] MINUTE[5:2]
0x12 23:16 MONTH[1:0] DAY[4:0] HOUR[4]
0x13 31:24 YEAR[5:0] MONTH[3:2]
Offset Name
Bit
Pos.
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0x14
...
0x17
Reserved
0x18
ALARM0
7:0 MINUTE[1:0] SECOND[5:0]
0x19 15:8 HOUR[3:0] MINUTE[5:2]
0x1A 23:16 MONTH[1:0] DAY[4:0] HOUR[4]
0x1B 31:24 YEAR[5:0] MONTH[3:2]
0x1C MASK 7:0 SEL[2:0]
Offset Name
Bit
Pos.
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17.8 Register Description
Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters
and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by
the Write-Protected property in each individual register description. Please refer to “Register Access Protection” on page
226 for details.
Some registers require synchronization when read and/or written. Synchronization is denoted by the Write-Synchronized
or the Read-Synchronized property in each individual register description. Please refer to “Synchronization” on page 231
for details.
Some registers are enable-protected, meaning they can only be written when the RTC is disabled. Enable-protection is
denoted by the Enable-Protected property in each individual register description.
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17.8.1 Control - MODE0
Name: CTRL
Offset: 0x00
Reset: 0x0000
Property: Enable-Protected, Write-Protected, Write-Synchronized
zBits 15:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 11:8 – PRESCALER[3:0]: Prescaler
These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock
(CLK_RTC_CNT).
These bits are not synchronized.
Table 17-4. Prescaler
Bit 151413121110 9 8
PRESCALER[3:0]
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 76543210
MATCHCLR MODE[1:0]
ENABLE SWRST
Access R/W R R R R/W R/W R/W W
Reset00000000
PRESCALER[3:0] Name Description
0x0 DIV1 CLK_RTC_CNT = GCLK_RTC/1
0x1 DIV2 CLK_RTC_CNT = GCLK_RTC/2
0x2 DIV4 CLK_RTC_CNT = GCLK_RTC/4
0x3 DIV8 CLK_RTC_CNT = GCLK_RTC/8
0x4 DIV16 CLK_RTC_CNT = GCLK_RTC/16
0x5 DIV32 CLK_RTC_CNT = GCLK_RTC/32
0x6 DIV64 CLK_RTC_CNT = GCLK_RTC/64
0x7 DIV128 CLK_RTC_CNT = GCLK_RTC/128
0x8 DIV256 CLK_RTC_CNT = GCLK_RTC/256
0x9 DIV512 CLK_RTC_CNT = GCLK_RTC/512
0xA DIV1024 CLK_RTC_CNT = GCLK_RTC/1024
0xB-0xF Reserved
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zBit 7 – MATCHCLR: Clear on Match
This bit is valid only in Mode 0 and Mode 2.
0: The counter is not cleared on a Compare/Alarm 0 match.
1: The counter is cleared on a Compare/Alarm 0 match.
This bit is not synchronized.
zBits 6:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 3:2 – MODE[1:0]: Operating Mode
These bits define the operating mode of the RTC.
These bits are not synchronized.
Table 17-5. Operating Mode
zBit 1 – ENABLE: Enable
0: The peripheral is disabled or being disabled.
1: The peripheral is enabled or being enabled.
Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/disabled. The
value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete.
This bit is not enable-protected.
zBit 0 – SWRST: Software Reset
0: There is no reset operation ongoing.
1: The reset operation is ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the RTC, except DBGCTRL, to their initial state, and the RTC will be
disabled.
Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-oper-
ation will be discarded.
Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete. CTRL.SWRST and
STATUS.SYNCBUSY will both be cleared when the reset is complete.
This bit is not enable-protected.
MODE[1:0] Name Description
0x0 COUNT32 Mode 0: 32-bit Counter
0x1 COUNT16 Mode 1: 16-bit Counter
0x2 CLOCK Mode 2: Clock/Calendar
0x3 Reserved
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17.8.2 Control - MODE1
Name: CTRL
Offset: 0x00
Reset: 0x0000
Property: Enable-Protected, Write-Protected, Write-Synchronized
zBits 15:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 11:8 – PRESCALER[3:0]: Prescaler
These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock
(CLK_RTC_CNT).
These bits are not synchronized.
Table 17-6. Prescaler
Bit 151413121110 9 8
PRESCALER[3:0]
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 76543210
MODE[1:0] ENABLE SWRST
AccessRRRRR/WR/WR/WW
Reset00000000
PRESCALER[3:0] Name Description
0x0 DIV1 CLK_RTC_CNT = GCLK_RTC/1
0x1 DIV2 CLK_RTC_CNT = GCLK_RTC/2
0x2 DIV4 CLK_RTC_CNT = GCLK_RTC/4
0x3 DIV8 CLK_RTC_CNT = GCLK_RTC/8
0x4 DIV16 CLK_RTC_CNT = GCLK_RTC/16
0x5 DIV32 CLK_RTC_CNT = GCLK_RTC/32
0x6 DIV64 CLK_RTC_CNT = GCLK_RTC/64
0x7 DIV128 CLK_RTC_CNT = GCLK_RTC/128
0x8 DIV256 CLK_RTC_CNT = GCLK_RTC/256
0x9 DIV512 CLK_RTC_CNT = GCLK_RTC/512
0xA DIV1024 CLK_RTC_CNT = GCLK_RTC/1024
0xB-0xF Reserved
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zBits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 3:2 – MODE[1:0]: Operating Mode
These bits define the operating mode of the RTC.
These bits are not synchronized.
Table 17-7. Operating Mode
zBit 1 – ENABLE: Enable
0: The peripheral is disabled or being disabled.
1: The peripheral is enabled or being enabled.
Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/disabled. The
value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete.
This bit is not enable-protected.
zBit 0 – SWRST: Software Reset
0: There is no reset operation ongoing.
1: The reset operation is ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the RTC, except DBGCTRL, to their initial state, and the RTC will be
disabled.
Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-oper-
ation will be discarded.
Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete. CTRL.SWRST and
STATUS.SYNCBUSY will both be cleared when the reset is complete.
This bit is not enable-protected.
MODE[1:0] Name Description
0x0 COUNT32 Mode 0: 32-bit Counter
0x1 COUNT16 Mode 1: 16-bit Counter
0x2 CLOCK Mode 2: Clock/Calendar
0x3 Reserved
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17.8.3 Control - MODE2
Name: CTRL
Offset: 0x00
Reset: 0x0000
Property: Enable-Protected, Write-Protected, Write-Synchronized
zBits 15:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 11:8 – PRESCALER[3:0]: Prescaler
These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock
(CLK_RTC_CNT).
These bits are not synchronized.
Table 17-8. Prescaler
Bit 151413121110 9 8
PRESCALER[3:0]
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 76543210
MATCHCLR
CLKREP MODE[1:0] ENABLE SWRST
Access R/W R/W R R R/W R/W R/W W
Reset00000000
PRESCALER[3:0] Name Description
0x0 DIV1 CLK_RTC_CNT = GCLK_RTC/1
0x1 DIV2 CLK_RTC_CNT = GCLK_RTC/2
0x2 DIV4 CLK_RTC_CNT = GCLK_RTC/4
0x3 DIV8 CLK_RTC_CNT = GCLK_RTC/8
0x4 DIV16 CLK_RTC_CNT = GCLK_RTC/16
0x5 DIV32 CLK_RTC_CNT = GCLK_RTC/32
0x6 DIV64 CLK_RTC_CNT = GCLK_RTC/64
0x7 DIV128 CLK_RTC_CNT = GCLK_RTC/128
0x8 DIV256 CLK_RTC_CNT = GCLK_RTC/256
0x9 DIV512 CLK_RTC_CNT = GCLK_RTC/512
0xA DIV1024 CLK_RTC_CNT = GCLK_RTC/1024
0xB-0xF Reserved
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zBit 7 – MATCHCLR: Clear on Match
This bit is valid only in Mode 0 and Mode 2. This bit can be written only when the peripheral is disabled.
0: The counter is not cleared on a Compare/Alarm 0 match.
1: The counter is cleared on a Compare/Alarm 0 match.
This bit is not synchronized.
zBit 6 – CLKREP: Clock Representation
This bit is valid only in Mode 2 and determines how the hours are represented in the Clock Value (CLOCK) regis-
ter. This bit can be written only when the peripheral is disabled.
0: 24 Hour
1: 12 Hour (AM/PM)
This bit is not synchronized.
zBits 5:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 3:2 – MODE[1:0]: Operating Mode
These bits define the operating mode of the RTC.
These bits are not synchronized.
Table 17-9. Operating Mode
zBit 1 – ENABLE: Enable
0: The peripheral is disabled or being disabled.
1: The peripheral is enabled or being enabled.
Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/disabled. The
value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete.
This bit is not enable-protected.
zBit 0 – SWRST: Software Reset
0: There is no reset operation ongoing.
1: The reset operation is ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the RTC, except DBGCTRL, to their initial state, and the RTC will be
disabled.
Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-oper-
ation will be discarded.
Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete. CTRL.SWRST and
STATUS.SYNCBUSY will both be cleared when the reset is complete.
This bit is not enable-protected.
MODE[1:0] Name Description
0x0 COUNT32 Mode 0: 32-bit Counter
0x1 COUNT16 Mode 1: 16-bit Counter
0x2 CLOCK Mode 2: Clock/Calendar
0x3 Reserved
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17.8.4 Read Request
Name: READREQ
Offset: 0x02
Reset: 0x0010
Property: -
zBit 15 – RREQ: Read Request
Writing a zero to this bit has no effect.
Writing a one to this bit requests synchronization of the register pointed to by the Address bit group (READ-
REQ.ADDR) and sets the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY).
zBit 14 – RCONT: Read Continuously
Writing a zero to this bit disables continuous synchronization.
Writing a one to this bit enables continuous synchronization of the register pointed to by READREQ.ADDR. The
register value will be synchronized automatically every time the register is updated. READREQ.RCONT prevents
READREQ.RREQ from clearing automatically.
This bit is cleared when the register pointed to by READREQ.ADDR is written.
zBits 13:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 5:0 – ADDR[5:0]: Address
These bits select the offset of the register that needs read synchronization. In the RTC only COUNT and CLOCK,
which share the same address, are available for read synchronization. Therefore, ADDR is a read-only constant of
0x10.
Bit 151413121110 9 8
RREQ RCONT
AccessWR/WRRRRRR
Reset00000000
Bit 76543210
ADDR[5:0]
AccessRRRRRRRR
Reset00010000
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17.8.5 Event Control - MODE0
Name: EVCTRL
Offset: 0x04
Reset: 0x0000
Property: Enable-Protected, Write-Protected
zBit 15 – OVFEO: Overflow Event Output Enable
0: Overflow event is disabled and will not be generated.
1: Overflow event is enabled and will be generated for every overflow.
zBits 14:9 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 8 – CMPEO: Compare 0 Event Output Enable
0: Compare 0 event is disabled and will not be generated.
1: Compare 0 event is enabled and will be generated for every compare match.
zBits 7:0 – PEREOx [x=7..0]: Periodic Interval x Event Output Enable
0: Periodic Interval x event is disabled and will not be generated.
1: Periodic Interval x event is enabled and will be generated.
Bit 151413121110 9 8
OVFEO CMPEO0
AccessR/WRRRRRRR/W
Reset00000000
Bit 76543210
PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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17.8.6 Event Control - MODE1
Name: EVCTRL
Offset: 0x04
Reset: 0x0000
Property: Enable-Protected, Write-Protected
zBit 15 – OVFEO: Overflow Event Output Enable
0: Overflow event is disabled and will not be generated.
1: Overflow event is enabled and will be generated for every overflow.
zBits 14:10 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 9:8 – CMPEOx [x=1..0]: Compare x Event Output Enable
0: Compare x event is disabled and will not be generated.
1: Compare x event is enabled and will be generated for every compare match.
zBits 7:0 – PEREOx [x=7..0]: Periodic Interval x Event Output Enable
0: Periodic Interval x event is disabled and will not be generated.
1: Periodic Interval x event is enabled and will be generated.
Bit 151413121110 9 8
OVFEO CMPEO1 CMPEO0
AccessR/WRRRRRR/WR/W
Reset00000000
Bit 76543210
PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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17.8.7 Event Control - MODE2
Name: EVCTRL
Offset: 0x04
Reset: 0x0000
Property: Enable-Protected, Write-Protected
zBit 15 – OVFEO: Overflow Event Output Enable
0: Overflow event is disabled and will not be generated.
1: Overflow event is enabled and will be generated for every overflow.
zBits 14:9 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 8 – ALARMEO: Alarm 0 Event Output Enable
0: Alarm 0 event is disabled and will not be generated.
1: Alarm 0 event is enabled and will be generated for every alarm.
zBits 7:0 – PEREOx [x=7..0]: Periodic Interval x Event Output Enable
0: Periodic Interval x event is disabled and will not be generated.
1: Periodic Interval x event is enabled and will be generated.
Bit 151413121110 9 8
OVFEO
ALARMEO0
AccessR/WRRRRRRR/W
Reset00000000
Bit 76543210
PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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17.8.8 Interrupt Enable Clear - MODE0
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x06
Reset: 0x00
Property: Write-Protected
zBit 7 – OVF: Overflow Interrupt Enable
0: The Overflow interrupt is disabled.
1: The Overflow interrupt is enabled, and an interrupt request will be generated when the Overflow interrupt flag is
set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overflow Interrupt Enable bit and disable the corresponding interrupt.
zBit 6 – SYNCRDY: Synchronization Ready Interrupt Enable
0: The Synchronization Ready interrupt is disabled.
1: The Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the Synchroni-
zation Ready interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Enable bit and disable the corresponding
interrupt.
zBits 5:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 0 – CMP: Compare 0 Interrupt Enable
0: The Compare 0 interrupt is disabled.
1: The Compare 0 interrupt is enabled, and an interrupt request will be generated when the Compare x interrupt
flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Compare 0 Interrupt Enable bit and disable the corresponding interrupt.
Bit 76543210
OVF SYNCRDY CMP0
AccessR/WR/WRRRRRR/W
Reset00000000
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17.8.9 Interrupt Enable Clear - MODE1
Name: INTENCLR
Offset: 0x06
Reset: 0x00
Property: Write-Protected
zBit 7 – OVF: Overflow Interrupt Enable
0: The Overflow interrupt is disabled.
1: The Overflow interrupt is enabled, and an interrupt request will be generated when the Overflow interrupt flag is
set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overflow Interrupt Enable bit and disable the corresponding interrupt.
zBit 6 – SYNCRDY: Synchronization Ready Interrupt Enable
0: The Synchronization Ready interrupt is disabled.
1: The Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the Synchroni-
zation Ready interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Enable bit and disable the corresponding
interrupt.
zBits 5:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 1:0 – CMPx [x=1..0]: Compare x Interrupt Enable
0: The Compare x interrupt is disabled.
1: The Compare x interrupt is enabled, and an interrupt request will be generated when the Compare x interrupt
flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Compare x Interrupt Enable bit and disable the corresponding interrupt.
Bit 76543210
OVF SYNCRDY CMP1 CMP0
AccessR/WR/WRRRRR/WR/W
Reset00000000
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17.8.10 Interrupt Enable Clear - MODE2
Name: INTENCLR
Offset: 0x06
Reset: 0x00
Property: Write-Protected
zBit 7 – OVF: Overflow Interrupt Enable
0: The Overflow interrupt is disabled.
1: The Overflow interrupt is enabled, and an interrupt request will be generated when the Overflow interrupt flag is
set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overflow Interrupt Enable bit and disable the corresponding interrupt.
zBit 6 – SYNCRDY: Synchronization Ready Interrupt Enable
0: The synchronization ready interrupt is disabled.
1: The synchronization ready interrupt is enabled, and an interrupt request will be generated when the Synchroni-
zation Ready interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Enable bit and disable the corresponding
interrupt.
zBits 5:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 0 – ALARM: Alarm 0 Interrupt Enable
0: The Alarm 0 interrupt is disabled.
1: The Alarm 0 interrupt is enabled, and an interrupt request will be generated when the Alarm 0 interrupt flag is
set.
Writing a zero to this bit has no effect.
Writing a one to this bit disables the Alarm 0 interrupt.
Bit 76543210
OVF SYNCRDY ALARM0
AccessR/WR/WRRRRRR/W
Reset00000000
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17.8.11 Interrupt Enable Set - MODE0
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Name: INTENSET
Offset: 0x07
Reset: 0x00
Property: Write-Protected
zBit 7 – OVF: Overflow Interrupt Enable
0: The overflow interrupt is disabled.
1: The overflow interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overflow Interrupt Enable bit and enable the Overflow interrupt.
zBit 6 – SYNCRDY: Synchronization Ready Interrupt Enable
0: The synchronization ready interrupt is disabled.
1: The synchronization ready interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Synchronization Ready Interrupt Enable bit and enable the Synchronization
Ready interrupt.
zBits 5:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 0 – CMP: Compare 0 Interrupt Enable
0: The compare 0 interrupt is disabled.
1: The compare 0 interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Compare 0 Interrupt Enable bit and enable the Compare 0 interrupt.
Bit 76543210
OVF SYNCRDY CMP0
AccessR/WR/WRRRRRR/W
Reset00000000
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17.8.12 Interrupt Enable Set - MODE1
Name: INTENSET
Offset: 0x07
Reset: 0x00
Property: Write-Protected
zBit 7 – OVF: Overflow Interrupt Enable
0: The overflow interrupt is disabled.
1: The overflow interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overflow interrupt bit and enable the Overflow interrupt.
zBit 6 – SYNCRDY: Synchronization Ready Interrupt Enable
0: The synchronization ready interrupt is disabled.
1: The synchronization ready interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Synchronization Ready Interrupt Enable bit and enable the Synchronization
Ready interrupt.
zBits 5:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 1:0 – CMPx [x=1..0]: Compare x Interrupt Enable
0: The compare x interrupt is disabled.
1: The compare x interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Compare x Interrupt Enable bit and enable the Compare x interrupt.
Bit 76543210
OVF SYNCRDY CMP1 CMP0
AccessR/WR/WRRRRR/WR/W
Reset00000000
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17.8.13 Interrupt Enable Set - MODE2
Name: INTENSET
Offset: 0x07
Reset: 0x00
Property: Write-Protected
zBit 7 – OVF: Overflow Interrupt Enable
0: The overflow interrupt is disabled.
1: The overflow interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overflow Interrupt Enable bit and enable the Overflow interrupt.
zBit 6 – SYNCRDY: Synchronization Ready Interrupt Enable
0: The synchronization ready interrupt is disabled.
1: The synchronization ready interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Synchronization Ready Interrupt bit and enable the Synchronization Ready
interrupt.
zBits 5:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 0 – ALARM: Alarm 0 Interrupt Enable
0: The alarm 0 interrupt is disabled.
1: The alarm 0 interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Alarm 0 Interrupt Enable bit and enable the Alarm 0 interrupt.
Bit 76543210
OVF SYNCRDY ALARM0
AccessR/WR/WRRRRRR/W
Reset00000000
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17.8.14 Interrupt Flag Status and Clear - MODE0
Name: INTFLAG
Offset: 0x08
Reset: 0x00
Property: -
zBit 7 – OVF: Overflow
This flag is cleared by writing a one to the flag.
This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will
be generated if INTENCLR/SET.OVF is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Overflow interrupt flag.
zBit 6 – SYNCRDY: Synchronization Ready
This flag is cleared by writing a one to the flag.
This flag is set on a 1-to-0 transition of the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY),
except when caused by enable or software reset, and an interrupt request will be generated if INTEN-
CLR/SET.SYNCRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Synchronization Ready interrupt flag.
zBits 5:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 0 – CMP: Compare 0
This flag is cleared by writing a one to the flag.
This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition, and an interrupt
request will be generated if INTENCLR/SET.CMP0 is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Compare 0 interrupt flag.
Bit 76543210
OVF SYNCRDY CMP0
AccessR/WR/WRRRRRR/W
Reset00000000
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17.8.15 Interrupt Flag Status and Clear - MODE1
Name: INTFLAG
Offset: 0x08
Reset: 0x00
Property: -
zBit 7 – OVF: Overflow
This flag is cleared by writing a one to the flag.
This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will
be generated if INTENCLR/SET.OVF is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Overflow interrupt flag.
zBit 6 – SYNCRDY: Synchronization Ready
This flag is cleared by writing a one to the flag.
This flag is set on a 1-to-0 transition of the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY),
except when caused by enable or software reset, and an interrupt request will be generated if INTEN-
CLR/SET.SYNCRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Synchronization Ready interrupt flag.
zBits 5:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 1:0 – CMPx [x=1..0]: Compare x
This flag is cleared by writing a one to the flag.
This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition and an interrupt
request will be generated if INTENCLR/SET.CMPx is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Compare x interrupt flag.
Bit 76543210
OVF SYNCRDY CMP1 CMP0
AccessR/WR/WRRRRR/WR/W
Reset00000000
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17.8.16 Interrupt Flag Status and Clear - MODE2
Name: INTFLAG
Offset: 0x08
Reset: 0x00
Property: -
zBit 7 – OVF: Overflow
This flag is cleared by writing a one to the flag.
This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will
be generated if INTENCLR/SET.OVF is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Overflow interrupt flag.
zBit 6 – SYNCRDY: Synchronization Ready
This flag is cleared by writing a one to the flag.
This flag is set on a 1-to-0 transition of the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY),
except when caused by enable or software reset, and an interrupt request will be generated if INTEN-
CLR/SET.SYNCRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Synchronization Ready interrupt flag.
zBits 5:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 0 – ALARM: Alarm 0
This flag is cleared by writing a one to the flag.
This flag is set on the next CLK_RTC_CNT cycle after a match with ALARM0 condition occurs, and an interrupt
request will be generated if INTENCLR/SET.ALARM0 is also one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Alarm 0 interrupt flag.
Bit 76543210
OVF SYNCRDY ALARM0
AccessR/WR/WRRRRRR/W
Reset00000000
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17.8.17 Status
Name: STATUS
Offset: 0x0A
Reset: 0x00
Property: -
zBit 7 – SYNCBUSY: Synchronization Busy
This bit is cleared when the synchronization of registers between the clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
zBits 6:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit 76543210
SYNCBUSY
AccessRRRRRRRR
Reset00000000
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17.8.18 Debug Control
Name: DBGCTRL
Offset: 0x0B
Reset: 0x00
Property: -
zBits 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 0 – DBGRUN: Run During Debug
This bit is not reset by a software reset.
Writing a zero to this bit causes the RTC to halt during debug mode.
Writing a one to this bit allows the RTC to continue normal operation during debug mode.
Bit 76543210
DBGRUN
AccessRRRRRRRR/W
Reset00000000
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17.8.19 Frequency Correction
Name: FREQCORR
Offset: 0x0C
Reset: 0x00
Property: Write-Protected, Write-Synchronized
zBit 7 – SIGN: Correction Sign
0: The correction value is positive, i.e., frequency will be increased.
1: The correction value is negative, i.e., frequency will be decreased.
zBits 6:0 – VALUE[6:0]: Correction Value
These bits define the amount of correction applied to the RTC prescaler.
0: Correction is disabled and the RTC frequency is unchanged.
1–127: The RTC frequency is adjusted according to the value.
Bit 76543210
SIGN VALUE[6:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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17.8.20 Counter Value - MODE0
Name: COUNT
Offset: 0x10
Reset: 0x00000000
Property: Read-Synchronized, Write-Protected, Write-Synchronized
zBits 31:0 – COUNT[31:0]: Counter Value
These bits define the value of the 32-bit RTC counter.
Bit 3130292827262524
COUNT[31:24]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
COUNT[23:16]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
COUNT[15:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
COUNT[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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17.8.21 Counter Value - MODE1
Name: COUNT
Offset: 0x10
Reset: 0x0000
Property: Read-Synchronized, Write-Protected, Write-Synchronized
zBits 15:0 – COUNT[15:0]: Counter Value
These bits define the value of the 16-bit RTC counter.
Bit 151413121110 9 8
COUNT[15:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
COUNT[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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17.8.22 Clock Value - MODE2
Name: CLOCK
Offset: 0x10
Reset: 0x00000000
Property: Read-Synchronized, Write-Protected, Write-Synchronized
zBits 31:26 – YEAR[5:0]: Year
The year offset with respect to the reference year (defined in software).
The year is considered a leap year if YEAR[1:0] is zero.
zBits 25:22 – MONTH[3:0]: Month
1 – January
2 – February
...
12 – December
zBits 21:17 – DAY[4:0]: Day
Day starts at 1 and ends at 28, 29, 30 or 31, depending on the month and year.
zBits 16:12 – HOUR[4:0]: Hour
When CTRL.CLKREP is zero, the Hour bit group is in 24-hour format, with values 0-23. When CTRL.CLKREP is
one, HOUR[3:0] has values 1-12 and HOUR[4] represents AM (0) or PM (1).
Bit 3130292827262524
YEAR[5:0] MONTH[3:2]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
MONTH[1:0] DAY[4:0] HOUR[4]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
HOUR[3:0] MINUTE[5:2]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
MINUTE[1:0] SECOND[5:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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Table 17-10. Hour
zBits 11:6 – MINUTE[5:0]: Minute
0 – 59.
zBits 5:0 – SECOND[5:0]: Second
0– 59.
HOUR[4:0] CLOCK.HOUR[4] CLOCK.HOUR[3:0] Description
0
0x00 - 0x17 Hour (0 - 23)
0x18 - 0x1F Reserved
1
0
0x0 Reserved
0x1 - 0xC AM Hour (1 - 12)
0xD - 0xF Reserved
1
0x0 Reserved
0x1 - 0xC PM Hour (1 - 12)
0xF - 0xF Reserved
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17.8.23 Counter Period - MODE1
Name: PER
Offset: 0x14
Reset: 0x0000
Property: Write-Protected, Write-Synchronized
zBits 15:0 – PER[15:0]: Counter Period
These bits define the value of the 16-bit RTC period.
Bit 151413121110 9 8
PER[15:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
PER[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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17.8.24 Compare n Value - MODE0
Name: COMP
Offset: 0x18
Reset: 0x00000000
Property: Write-Protected, Write-Synchronized
zBits 31:0 – COMP[31:0]: Compare Value
The 32-bit value of COMPn is continuously compared with the 32-bit COUNT value. When a match occurs, the
Compare n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn) is set on the next counter
cycle, and the counter value is cleared if CTRL.MATCHCLR is one.
Bit 3130292827262524
COMP[31:24]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
COMP[23:16]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
COMP[15:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
COMP[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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17.8.25 Compare n Value - MODE1
Name: COMPn
Offset: 0x18+n*0x2 [n=0..1]
Reset: 0x0000
Property: Write-Protected, Write-Synchronized
zBits 15:0 – COMP[15:0]: Compare Value
The 16-bit value of COMPn is continuously compared with the 16-bit COUNT value. When a match occurs, the
Compare n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn) is set on the next counter
cycle.
Bit 151413121110 9 8
COMP[15:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
COMP[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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17.8.26 Alarm 0 Value - MODE2
Name: ALARM0
Offset: 0x18
Reset: 0x00000000
Property: Write-Protected, Write-Synchronized
The 32-bit value of ALARM0 is continuously compared with the 32-bit CLOCK value, based on the masking set by
MASKn.SEL. When a match occurs, the Alarm 0 interrupt flag in the Interrupt Flag Status and Clear register
(INTFLAG.ALARMn) is set on the next counter cycle, and the counter is cleared if CTRL.MATCHCLR is one.
zBits 31:26 – YEAR[5:0]: Year
The alarm year. Years are only matched if MASKn.SEL is 6.
zBits 25:22 – MONTH[3:0]: Month
The alarm month. Months are matched only if MASKn.SEL is greater than 4.
zBits 21:17 – DAY[4:0]: Day
The alarm day. Days are matched only if MASKn.SEL is greater than 3.
zBits 16:12 – HOUR[4:0]: Hour
The alarm hour. Hours are matched only if MASKn.SEL is greater than 2.
zBits 11:6 – MINUTE[5:0]: Minute
The alarm minute. Minutes are matched only if MASKn.SEL is greater than 1.
zBits 5:0 – SECOND[5:0]: Second
The alarm second. Seconds are matched only if MASKn.SEL is greater than 0.
Bit 3130292827262524
YEAR[5:0] MONTH[3:2]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
MONTH[1:0] DAY[4:0] HOUR[4]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
HOUR[3:0] MINUTE[5:2]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
MINUTE[1:0] SECOND[5:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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17.8.27 Alarm n Mask - MODE2
Name: MASK
Offset: 0x1C
Reset: 0x00
Property: Write-Protected, Write-Synchronized
zBits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 2:0 – SEL[2:0]: Alarm Mask Selection
These bits define which bit groups of Alarm n are valid.
Table 17-11. Alarm Mask Selection
Bit 76543210
SEL[2:0]
AccessRRRRRR/WR/WR/W
Reset00000000
SEL[2:0] Name Description
0x0 OFF Alarm Disabled
0x1 SS Match seconds only
0x2 MMSS Match seconds and minutes only
0x3 HHMMSS Match seconds, minutes, and hours only
0x4 DDHHMMSS Match seconds, minutes, hours, and days only
0x5 MMDDHHMMSS Match seconds, minutes, hours, days, and months only
0x6 YYMMDDHHMMSS Match seconds, minutes, hours, days, months, and years
0x7 Reserved
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18. DMAC – Direct Memory Access Controller
18.1 Overview
The Direct Memory Access Controller (DMAC) contains both a Direct Memory Access engine and a Cyclic Redundancy
Check (CRC) engine. The DMAC can transfer data between memories and peripherals, and thus off-load these tasks
from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU time. With access to
all peripherals, the DMAC can handle automatic transfer of data between communication modules.
For the DMA part of the DMAC, it has several DMA channels which all can receive different types of transfer triggers,
which will result in transfer requests from the DMA channels to the arbiter. Refer to Figure 18-1. The arbiter will grant one
DMA channel at a time to act as the active channel. When the active channel has been granted, the fetch engine of the
DMAC will fetch a transfer descriptor from SRAM into the internal memory of the active channel, before the active
channel starts its data transmission. A DMA channel's data transfer can be interrupted by a higher prioritized channel.
The DMAC will write back the updated transfer descriptor from the internal memory of the active channel to SRAM,
before the higher prioritized channel gets to start its transfer. Once a DMA channel is done with its transfer optionally
interrupts and events can be generated.
As one can see from Figure 18-1, the DMAC has four bus interfaces. The data transfer bus, which is used for performing
the actual DMA transfer is an AHB master interface. The AHB/APB Bridge bus is an APB slave interface and is the bus
used when writing and reading the I/O registers of the DMAC. The descriptor fetch bus is an AHB master interface and is
used by the fetch engine, to fetch transfer descriptors from SRAM before a transfer can be started or continued. At last
there is the write-back bus, which is an AHB master interface and it is used to write the transfer descriptor back to SRAM.
As mentioned, the DMAC also has a CRC module available. This can be used by software to detect an accidental error
in the transferred data and to take corrective action, such as requesting the data to be sent again or simply not using the
incorrect data.
18.2 Features
zData transfer between
zPeripheral to peripheral
zPeripheral to memory
zMemory to peripheral
zMemory to memory
zTransfer trigger sources
zSoftware
zEvents from Event System
zDedicated requests from peripherals
zSRAM based transfer descriptors
zSingle transfer using one descriptor
zMulti-buffer or circular buffer modes by linking multiple descriptors
z12 channels
zEnable 12 independent transfers
zAutomatic descriptor fetch for each channel
zSuspend/resume operation support for each channel
zFlexible arbitration scheme
z4 configurable priority levels for each channel
zFixed or round-robin priority scheme within each priority level
zFrom 1 to 256kB data transfer in a single block transfer
zMultiple addressing modes
zStatic
zConfigurable increment scheme
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zOptional interrupt generation
zOn block transfer complete
zOn error detection
zOn channel suspend
z4 event inputs
zOne event input for each of the 4 least significant DMA channels
zCan be selected to trigger normal transfers, periodic transfers or conditional transfers
zCan be selected to suspend or resume channel operation
z4 event outputs
zOne output event for each of the 4 least significant DMA channels
zSelectable generation on AHB, burst, block or transaction transfer complete
zError management supported by write-back function
zDedicated Write-Back memory section for each channel to store ongoing descriptor transfer
zCRC polynomial software selectable to
zCRC-16 (CRC-CCITT)
zCRC-32 (IEEE 802.3)
18.3 Block Diagram
Figure 18-1. DMAC Block Diagram
18.4 Signal Description
Not applicable.
18.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
HIGH SPEED
BUS MATRIX
AHB/APB
Bridge
CPU
SRAM
S
S
M
M
Events
Channel 0
Channel 1
Channel n
Arbiter
DMA Channels
MASTER
Active
Channel
CRC
Engine
Fetch
Engine
Interrupt /
Events
DMAC
Interrupts
Transfer
Triggers n
Data Transfer
Write-back
Descriptor Fetch
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18.5.1 I/O Lines
Not applicable.
18.5.2 Power Management
The DMAC will continue to operate in any sleep mode where the selected source clock is running. The DMAC’s interrupts
can be used to wake up the device from sleep modes. Events connected to the event system can trigger other operations
in the system without exiting sleep modes. Refer to “PM – Power Manager” on page 112 for details on the different sleep
modes. On hardware or software reset, all registers are set to their reset value.
18.5.3 Clocks
The DMAC bus clock (CLK_DMAC_APB) can be enabled and disabled in the power manager, and the default state of
CLK_DMAC_APB can be found in “Peripheral Clock Masking” on page 116.
An AHB clock (CLK_DMAC_AHB) is required to clock the DMAC. This clock must be configured and enabled in the
power manager before using the DMAC, and the default state of CLK_DMAC_AHB can be found in “Peripheral Clock
Masking” on page 116.
This bus clock (CLK_DMAC_APB) is always synchronous to the module clock (CLK_DMAC_AHB), but can be divided by
a prescaler and may run even when the module clock is turned off.
18.5.4 DMA
Not applicable.
18.5.5 Interrupts
The interrupt request line is connected to the interrupt controller. Using the DMAC interrupts requires the interrupt
controller to be configured first. Refer to “Nested Vector Interrupt Controller” on page 29 for details.
18.5.6 Events
The events are connected to the event system. Refer to “EVSYS – Event System” on page 400 for details on how to
configure the Event System.
18.5.7 Debug Operation
When the CPU is halted in debug mode the DMAC will halt normal operation. The DMAC can be forced to continue
operation during debugging. Refer to DBGCTRL for details.
18.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the
following registers:
zInterrupt Pending (INTPEND) register
zChannel ID (CHID) register
zChannel Interrupt Flag Status and Clear (CHINTFLAG) register
Write-protection is denoted by the Write-Protected property in the register description.
Write-protection does not apply to accesses through an external debugger. Refer to “PAC – Peripheral Access
Controller” on page 36 for details.
18.5.9 Analog Connections
Not applicable.
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18.6 Functional Description
18.6.1 Principle of Operation
The DMAC consists of a DMA module and a CRC module.
18.6.1.1 DMA
The DMAC can, without interaction from the CPU, transfer data between peripherals and memories. The data transferred
by the DMAC are called transactions, and these transactions can be split into smaller data transfers. Figure 18-2
shows
the relationship between the different transfer sizes.
Figure 18-2. DMA Transfer Sizes
zBeat transfer: Defined as the size of one data transfer bus access, and the size is selected by writing the Beat Size
bit group in the Block Transfer Control register (BTCTRL.BEATSIZE)
zBurst transfer: Defined as n beat transfers, where n will differ from one device family to another. For this device
family, n is 1. A burst transfer is atomic, and cannot be interrupted.
zBlock transfer: The amount of data one transfer descriptor can transfer, and the amount can range from 1 to 64k
beats. In contrast to the burst transfer, a block transfer can be interrupted.
zTransaction: The DMAC can link several transfer descriptors by having the first descriptor pointing to the second
and so forth, as shown in Figure 18-2. A DMA transaction is defined as all block transfers within a linked list, being
completed.
A transfer descriptor describes how a block transfer should be carried out by the DMAC, and it must remain in SRAM. For
further details on the transfer descriptor refer to “Transfer Descriptors” on page 272.
Figure 18-2 shows several block transfers linked together, which are called linked descriptors. For further information
about linked descriptors, refer to “Linked Descriptors” on page 279.
A DMA transfer is initiated by an incoming transfer trigger on one of the DMA channels. This trigger can be configured to
be either a software trigger, an event trigger or one of the dedicated peripheral triggers. The transfer trigger will result in
a DMA transfer request from the specific channel to the arbiter, and if there are several DMA channels with pending
transfer requests, the arbiter has to choose which channel to grant access to become the active channel. The DMA
channel granted access as the active channel will carry out the transaction as configured in the transfer descriptor. The
DMA channel can be interrupted by a higher prioritized channel after each burst transfer, but will resume its block
transfer when it is granted access as the active channel again.
For each beat transfer an optional output event can be generated, and for each block transfer optional interrupts and an
optional output event can be generated. When a transaction is completed, dependent of the configuration, the DMA
channel will either be suspended or disabled.
18.6.1.2 CRC
The internal CRC supports two commonly used CRC polynomials; CRC-16 (CRC-CCITT) and CRC-32 (IEEE 802.3). It
can be used with selectable DMA channel or independently, with I/O interface.
DMA transaction
Block transfer
Link Enabled
Burst transfer
Link EnabledLink Enabled
Beat transfer
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18.6.2 Basic Operation
18.6.2.1 Initialization
The following DMAC registers are enable-protected, meaning that they can only be written when the DMAC is disabled
(CTRL.DMAENABLE is zero):
zDescriptor Base Memory Address (BASEADDR) register
zWrite-Back Memory Base Address (WRBADDR) register
The following DMAC bit is enable-protected, meaning that it can only be written when both the DMAC and CRC are
disabled (CTRL.DMAENABLE and CTRL.CRCENABLE is zero):
zSoftware Reset bit in Control register (CTRL.SWRST)
The following DMA channel register is enable-protected, meaning that it can only be written when the corresponding
DMA channel is disabled (CHCTRLA.ENABLE is zero):
zChannel Control B (CHCTRLB) register, except the Command (CHCTRLB.CMD) and Channel Arbitration Level
(CHCTRLB.LVL) bits
The following DMA channel bit is enable-protected, meaning that it can only be written when the corresponding DMA
channel is disabled:
zChannel Software Reset bit in Channel Control A register (CHCTRLA.SWRST)
The following CRC registers are enable-protected, meaning that they can only be written when the CRC is disabled
(CTRL.CRCENABLE is zero):
zCRC Control (CRCCTRL) register
zCRC Checksum (CRCCHKSUM) register
Enable-protection is denoted by the Enable-Protected property in the register description.
Before the DMAC is enabled, it must be configured, as outlined by the following steps:
zThe SRAM address of where the descriptor memory section is located must be written to the Description Base
Address (BASEADDR) register
zThe SRAM address of where the write-back section should be located must be written to the Write-Back Memory
Base Address (WRBADDR) register
zPriority level x of the arbiter can be enabled by writing a one to the Priority Level x Enable bit in the Control
register(CTRL.LVLENx)
Before a DMA channel is enabled, the DMA channel and the corresponding first transfer descriptor must be configured,
as outlined by the following steps:
zDMA channel configurations
zThe channel number of the DMA channel to configure must be written to the Channel ID (CHID) register
zTrigger action must be selected by writing the Trigger Action bit group in the Channel Control B register
(CHCTRLB.TRIGACT)
zTrigger source must be selected by writing the Trigger Source bit group in the Channel Control B register
(CHCTRLB.TRIGSRC)
zTransfer Descriptor
zThe size of each access of the data transfer bus must be selected by writing the Beat Size bit group in the
Block Transfer Control register (BTCTRL.BEATSIZE)
zThe transfer descriptor must be made valid by writing a one to the Valid bit in the Block Transfer Control
register (BTCTRL.VALID)
zNumber of beats in the block transfer must be selected by writing the Block Transfer Count (BTCNT)
register
zSource address for the block transfer must be selected by writing the Block Transfer Source Address
(SRCADDR) register
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zDestination address for the block transfer must be selected by writing the Block Transfer Destination
Address (DSTADDR) register
If CRC calculation is needed the CRC module must be configured before it is enabled, as outlined by the following steps:
zCRC input source must selected by writing the CRC Input Source bit group in the CRC Control register
(CRCCTRL.CRCSRC)
zType of CRC calculation must be selected by writing the CRC Polynomial Type bit group in the CRC Control
register (CRCCTRL.CRCPOLY)
zIf I/O is chosen as input source, the beat size must be selected by writing the CRC Beat Size bit group in the CRC
Control register (CRCCTRL.CRCBEATSIZE)
18.6.2.2 Enabling, Disabling and Resetting
The DMAC is enabled by writing a one to the DMA Enable bit in the Control register (CTRL.DMAENABLE). The DMAC is
disabled by writing a zero to CTRL.DMAENABLE.
A DMA channel is enabled by writing a one to Enable bit in the Channel Control A register (CHCTRLA.ENABLE), after
writing the corresponding channel id to the Channel ID bit group in the Channel ID register (CHID.ID). A DMA channel is
disabled by writing a zero to CHCTRLA.ENABLE.
The CRC is enabled by writing a one to the CRC Enable bit in the Control register (CTRL.CRCENABLE). The CRC is
disabled by writing a zero to CTRL.CRCENABLE.
The DMAC is reset by writing a one to the Software Reset bit in the Control register (CTRL.SWRST), when the DMAC
and CRC are disabled. All registers in the DMAC, except DBGCTRL, will be reset to their initial state.
A DMA channel is reset by writing a one to the Software Reset bit in the Channel Control A register (CHCTRLA.SWRST),
after writing the corresponding channel id to the Channel ID bit group in the Channel ID register (CHID.ID). The channel
registers will be reset to their initial state. The corresponding DMA channel must be disabled in order for the reset to take
effect.
18.6.2.3 Transfer Descriptors
Together with the channel configurations the transfer descriptors decides how a block transfer should be executed.
Before a DMA channel is enabled (CHCTRLA.ENABLE is written to one), and receives a transfer trigger, its first transfer
descriptor has to be initialized and valid (BTCTRL.VALID). The first transfer descriptor describes the first block transfer of
a transaction. For further details on the content of a transfer descriptor, refer to “Block Transfer Control” on page 324.
All transfer descriptors must reside in SRAM and the addresses stored in the Descriptor Memory Section Base Address
(BASEADDR) and Write-Back Memory Section Base Address (WRBADDR) registers tells the DMAC where to find the
descriptor memory section and the write-back memory section.
The descriptor memory section is where the DMAC expects to find the first transfer descriptors for all DMA channels. As
BASEADDR points only to the first transfer descriptor of channel 0, refer to Figure 18-3, all first transfer descriptors must
be stored in a contiguous memory section, where the transfer descriptors must be ordered according to their channel
number. Figure 18-3 shows an example of linked descriptors on DMA channel 0. For further details on linked descriptors,
refer to “Linked Descriptors” on page 279.
The write-back memory section is the section where the DMAC stores the transfer descriptors for the ongoing block
transfers. WRBADDR points to the ongoing transfer descriptor of channel 0. All ongoing transfer descriptors will be
stored in a contiguous memory section where the transfer descriptors are ordered according to their channel number.
Figure 18-3 shows an example of linked descriptors on DMA channel 0. For further details on linked descriptors, refer to
“Linked Descriptors” on page 279.
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Figure 18-3. Memory Sections
The size of the descriptor and write-back memory sections is dependant on most significant enabled DMA channel, as
shown below:
For memory optimization, it is recommended to always use the less significant DMA channels if not all channels are
required.
The descriptor and write-back memory sections can either be two separate memory sections, or they can share memory
section (BASEADDR=WRBADDR). The benefit of having them in two separate sections, is that the same transaction for
a channel can be repeated without having to modify the first transfer descriptor. The benefit of having descriptor memory
and write-back memory in the same section is that it requires less SRAM. In addition, the latency from fetching the first
descriptor of a transaction to the first burst transfer is executed, is reduced.
Channel 0 – Descriptor n-1
Channel 0 – Last Descriptor
DESCADDR
DESCADDR
Device Memory Space
BASEADDR Channel 0 – First Descriptor
Channel 1 – First Descriptor
Channel 2 – First Descriptor
Channel n – First Descriptor
Descriptor Section
WRBADDR Channel 0 Ongoing Descriptor
Channel 1 Ongoing Descriptor
Channel 2 Ongoing Descriptor
Channel n Ongoing Descriptor
Write-Back Section
Undefined
Undefined
Undefined
Undefined
Undefined
SRCADDR
DSTADDR
BTCTRL
DESCADDR
BTCNT
SRCADDR
DSTADDR
BTCTRL
DESCADDR
BTCNT
SRCADDR
DSTADDR
BTCTRL
0x00000000
BTCNT
Size 128bits MostSignificantEnabledChannelNumber 1+()⋅=
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18.6.2.4 Arbitration
If a DMA channel is enabled and not suspended when it receives a transfer trigger, it will send a transfer request to the
arbiter. When the arbiter receives the transfer request it will include the DMA channel in the queue of channels having
pending transfers, and the corresponding Pending Channel x bit in the Pending Channels registers
(PENDCH.PENDCHx) will be set. Dependent of the arbitration scheme, the arbiter will choose which DMA channel will
be the next active channel. Refer to Figure 18-4. The active channel is the DMA channel being granted access to perform
its next burst transfer. When the arbiter has granted a DMA channel access to the DMAC, the corresponding
PENDCH.PENDCHx will be cleared. Depending on if the upcoming burst transfer is the first for the transfer request or
not, the corresponding Busy Channel x bit in the Busy Channels register (BUSYCH.BUSYCHx) will either be set or
remain one. When the channel has performed its granted burst transfer(s) it will either be fed into the queue of channels
with pending transfers, set to be waiting for a new transfer trigger, it will be suspended or it will be disabled. This depends
on the channel and block transfer configuration. If the DMA channel is fed into the queue of channels with pending
transfers, the corresponding BUSYCH.BUSYCHx will remain one. If the DMA channel is set to wait for a new transfer
trigger, suspended or disabled, the corresponding BUSYCH.BUSYCHx will be cleared.
If a DMA channel is suspended while it has a pending transfer, it will be removed from the queue of pending channels,
but the corresponding PENDCH.PENDCHx will remain set. When the same DMA channel is resumed, it will be added to
the queue of pending channels again. If a DMA channel gets disabled(CHCTRLA.ENABLE is zero) while it has a pending
transfer, it will be removed from the queue of pending channels, and the corresponding PENDCH.PENDCHx will be
cleared.
Figure 18-4. Arbiter Overview
When a channel level is pending or the channel is transferring data, the corresponding Level Executing bit is set in the
Active Channel and Levels register (ACTIVE.LVLEXx).
Each DMA channel supports a
4
-level priority scheme. The priority level for a channel is configured by writing to the
Channel Arbitration Level bit group in the Channel Control B register(CHCTRLB.LVL). As long as all priority levels are
enabled, a channel with lower priority level number will have priority over a channel with higher priority level number. A
priority level is enabled by writing the Priority Level x Enable bit in the Control register(CTRL.LVLENx) to one, for the
corresponding level.
Within each priority level the DMAC's arbiter can be configured to prioritize statically or dynamically. For the arbiter to
perform static arbitration within a priority level, the Level x Round-Robin Scheduling Enable bit in the Priority Control 0
register (PRICTRL0.RRLVLENx) has to be written to zero. When static arbitration is enabled (PRICTRL0.RRLVLENx is
zero), the arbiter will prioritize a low channel number over a high channel number as shown in Figure 18-5. When using
Channel 0
Arbiter
Channel Priority Level
Channel Pending
Transfer Request
Priority
decoder
ACTIVE.LVLEXx
PRICTRLx.LVLPRI
Channel Burst Done
Burst Done
Channel Suspend
Active
Channel
Channel Number
Channel N
CTRL.LVLENx
Level Enable
Channel Enable
Channel Suspend
Channel Priority Level
Channel Burst Done
Channel Enable
Channel Pending
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the static scheme there is a risk of high channel numbers never being granted access as the active channel. This can be
avoided using a dynamic arbitration scheme.
Figure 18-5. Static Priority
The dynamic arbitration scheme available in the DMAC is round-robin. Round-robin arbitration is enabled by writing
PRICTRL0.RRLVLENx to one, for a given priority level x. With the round-robin scheme, the channel number of the last
channel being granted access will have the lowest priority the next time the arbiter has to grant access to a channel
within the same priority level, as shown in Figure 18-6. The channel number of the last channel being granted access as
the active channel, will be stored in the Level x Channel Priority Number bit group in the Priority Control 0
register(PRICTRL0.LVLPRIx), for the corresponding priority level.
Figure 18-6. Round-Robin Scheduling
18.6.2.5 Data Transmission
Before the DMAC can perform a data transmission, a DMA channel has to be configured and enabled, its corresponding
transfer descriptor has to be initialized and the arbiter has to grant the DMA channel access as the active channel.
Once the arbiter has granted a DMA channel access as the active channel (refer to Figure 18-1) the transfer descriptor
for the DMA channel will be fetched from SRAM using the fetch bus, and stored in the internal memory for the active
channel. Depending on if it is a new or ongoing block transfer, the transfer descriptor will either be fetched from the
descriptor memory section (BASEADDR) or the write-back memory section (WRBADDR). By using the data transfer bus,
the DMAC will read the data from the current source address and write it to the current destination address. For further
details on how the current source and destination addresses are calculated, refer to “Addressing” on page 277.
Channel 0
Channel N
Channel x
Channel x+1
.
.
.
.
.
.
Lowest Channel Highest Priority
Lowest Priority
Highest Channel
Channel 0
Channel N
Channel x
Channel x+1
.
.
.
.
.
.
Lowest Priority
Highest Priority
Channel x last acknowledged request
Channel 0
Channel N
Channel x
Channel x+1
.
.
.
.
.
.
Lowest Priority
Highest Priority
Channel x+2
Channel (x+1) last acknowledged request
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The arbitration procedure is performed after each burst transfer. If the current DMA channel is granted access again, the
block transfer counter (BTCNT) of the internal transfer descriptor will be decremented with the number of beats in a
burst, and the active channel will perform a new burst transfer. If a different DMA channel than the current active channel
is granted access, the BTCNT of the internal transfer descriptor will be decremented with the number of beats in a burst.
The block transfer counter value will be written to the write-back section before the transfer descriptor of the newly
granted DMA channel is fetched into the internal memory of the active channel. The optional output event, Beat, will be
generated if configured and enabled.
When a block transfer has come to its end, BTCNT has reached zero, the Valid bit in the Block Transfer Control register
will be written to zero in the internal transfer descriptor for the active channel before the entire transfer descriptor is
written to the write-back memory. The optional interrupts, Channel Transfer Complete and Channel Suspend, and the
optional output event, Block, will be generated if configured and enabled. If it was the last block transfer in a transaction,
Next Address (DESCADDR) register will hold the value 0x00000000, and the DMA channel will either be suspended or
disabled, depending on the configuration in the Block Action bit group in the Block Transfer Control
register(BTCTRL.BLOCKACT). If the transaction has further block transfers pending, DESCADDR will hold the SRAM
address to the next transfer descriptor to be fetched. The DMAC will fetch the next descriptor into the internal memory of
the active channel and write its content to the write-back section for the channel, before the arbiter gets to choose the
next active channel.
18.6.2.6 Transfer Triggers and Actions
A DMA transfer can be started only when a DMA transfer request is detected. A transfer request can be triggered from
software, from peripheral, or from an event. There are dedicated Trigger Source selections for each DMA Channel
Control B (CHCTRLB.TRIGSRC).
The trigger actions are available in the Trigger Action bit group in the Channel Control B register (CHCTRLB.TRIGACT).
By default, a trigger starts a block transfer operation. If a single descriptor is defined for a channel, the channel is
automatically disabled when a block transfer is complete. If a list of linked descriptors is defined for a channel, the
channel is automatically disabled if the last descriptor in the list is executed or the channel will be waiting for the next
block transfer trigger if the list still has descriptors to execute. When enabled again, the channel will wait for the next
block transfer trigger. It is also possible to select the trigger to start beat or transaction transfers instead of a block
transfer.
If the trigger source generates a transfer request during an ongoing transfer, this will be kept pending
(CHSTATUS.PEND is one), and the transfer can start when the ongoing one is done. Only one pending transfer can be
kept, and so if the trigger source generates more transfer requests when one is already pending, these will be lost. All
channels pending status flags are also available in the Pending Channels register (PENDCH).
When the transfer starts, the corresponding Channel Busy status flag is set in Channel Status register
(CHSTATUS.BUSY). When the trigger action is complete, the Channel Busy status flag is cleared. All channels busy
status flags are also available in the Busy Channels register (BUSYCH) in DMAC.
Figure 18-7 on page 277 shows an example where triggers are used with two linked block descriptors.
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Figure 18-7. Trigger Action and Transfers
18.6.2.7 Addressing
For the DMAC to know from where to where it should transfer the data, each block transfer needs to have a source and
destination address defined. The source address can be set by writing the Transfer Source Address (SRCADDR)
register, and the destination address can be set by writing the Transfer Destination Address (SRCADDR) register.
The addressing of this DMAC module can be static or incremental, for either source or destination of a block transfer, or
both.
Incrementation for the source address of a block transfer is enabled by writing the Source Address Incrementation
Enable bit in the Block Transfer Control register (BTCTRL.SRCINC) to one. The step size of the incrementation is
configurable and can be chosen by writing the Step Selection bit in the Block Transfer Control
BEAT BEAT BEAT
Block Transfer
BEAT BEAT BEAT
Block Transfer
Trigger
BUSYCHn
CHENn
Data Transfer
PENDCHn
Trigger Lost
Beat Trigger Action
BEAT BEAT BEAT
Block Transfer
BEAT BEAT BEAT
Block Transfer
Trigger
BUSYCHn
CHENn
Data Transfer
PENDCHn
Trigger Lost
Block Trigger Action
BEAT BEAT BEAT
Block Transfer
BEAT BEAT BEAT
Block Transfer
Trigger
BUSYCHn
CHENn
Data Transfer
PENDCHn
Trigger Lost
Transaction Trigger Action
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register(BTCTRL.STEPSEL) to one, and the Address Increment Step Size bit group in the Block Transfer Control
register (BTCTRL.STEPSIZE), to the desired step size. If BTCTRL.STEPSEL is zero, the step size for the source
incrementation will be the size of one beat.
When source address incrementation is configured (BTCTRL.SRCINC is one), SRCADDR must be set to the source
address of the last beat transfer in the block transfer. The source address should be calculated as follows:
zSRCADDRSTART is the source address of the first beat transfer in the block transfer
zBTCNT is the initial number of beats remaining in the block transfer
zBEATSIZE is the configured number of bytes in a beat
zSTEPSIZE is the configured number of beats for each incrementation
Figure 18-8 shows an example where DMA channel 0 is configured to increment the source address by one beat
(BTCTRL.SRCINC is one) after each beat transfer, and DMA channel 1 is configured to increment source address by two
beats (BTCTRL.SRCINC is one, BTCTRL.STEPSEL is one, and BTCTRL.STEPSIZE is 0x1). As the destination address
for both channels are peripherals, destination incrementation is disabled(BTCTRL.DSTINC is zero).
Figure 18-8. Source Address Increment
Incrementation for the destination address of a block transfer is enabled by writing the Destination Address
Incrementation Enable bit in the Block Transfer Control register (BTCTRL.DSTINC) to one. The step size of the
incrementation is configurable and can be chosen by writing BTCTRL.STEPSEL to zero, and BTCTRL.STEPSIZE to the
desired step size. If BTCTRL.STEPSEL is one, the step size for the destination incrementation will be the size of one
beat.
When destination address incrementation is configured (BTCTRL.DSTINC is one), SRCADDR must be set to the
destination address of the last beat transfer in the block transfer. The destination address should be calculated as
follows:
zDSTADDRSTART is the destination address of the first beat transfer in the block transfer
zBTCNT is the initial number of beats remaining in the block transfer
zBEATSIZE is the configured number of bytes in a beat
zSTEPSIZE is the configured number of beats for each incrementation
Figure 18-9 shows an example where DMA channel 0 is configured to increment destination address by one beat
(BTCTRL.DSTINC is one) and DMA channel 1 is configured to increment destination address by two beats
(BTCTRL.DSTINC is one, BTCTRL.STEPSEL is zero, and BTCTRL.STEPSIZE is 0x1). As the source address for both
channels are peripherals, source incrementation is disabled(BTCTRL.SRCINC is zero).
, where BTCTRL.STEPSEL is one
, where BTCTRL.STEPSEL is zero
, where BTCTRL.STEPSEL is zero
, where BTCTRL.STEPSEL is one
SRCADDR SRCADDRSTART BTCNT BEATSIZE 1+()2STEPSIZE
⋅⋅+=
SRCADDR SRCADDRSTART BTCNT BEATSIZE 1+()⋅+=
DMA Channel 0
DMA Channel 1
PERIPHERAL 0
PERIPHERAL 1
{a,b}
{c,e}
SRC Data Buffer
a
b
c
d
e
f
DSTADDR DSTADDRSTART BTCNT BEATSIZE 1+()2STEPSIZE
⋅⋅+=
DSTADDR DSTADDRSTART BTCNT BEATSIZE 1+()⋅+=
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Figure 18-9. Destination Address Increment
18.6.2.8 Error Handling
If a bus error is received from AHB slave during a DMA data transfer, the corresponding active channel is disabled and
the corresponding Channel Transfer Error Interrupt flag in the Channel Interrupt Status and Clear register
(CHINTFLAG.TERR) is set. If transfer error interrupt is enabled, optional error interrupt is generated. The transfer
counter will not be decremented and its current value is written-back in the write-back memory section before the channel
is disabled.
When the DMAC fetches an invalid descriptor (BTCTRL.VALID is zero) or when the channel is resumed and the DMA
fetches the next descriptor with null address (DESCADDR is 0x00000000), the corresponding channel operation is
suspended, the Channel Suspend Interrupt Flag in the Channel Interrupt Flag Status and Clear register
(CHINTFLAG.SUSP) is set and the Channel Fetch Error bit in the Channel Status register (CHSTATUS.FERR) is set. If
enabled, optional suspend interrupt is generated.
18.6.3 Additional Features
18.6.3.1 Linked Descriptors
A transaction can either consist of a single block transfer, or it can consist of several block transfers. When a transaction
consist of several block transfers it is called linked descriptors.
Figure 18-3 shows how linked descriptors work. When the first block transfer is completed on DMA channel 0, the DMAC
fetches the next transfer descriptor which is pointed to by the value stored in the Next Descriptor Address (DESCADDR)
register, in the first transfer descriptor. Fetching the next transfer descriptor (DESCADDR) is continued until the last
transfer descriptor. When the block transfer for the last transfer descriptor is executed and DESCADDR=0x00000000,
the transaction is terminated. For further details on how the next descriptor is fetched from SRAM, refer to “Data
Transmission” on page 275.
Adding Descriptor to the End of a List
To add a new descriptor at the end of the descriptor list, create the descriptor in SRAM, with DESCADDR=0x00000000
indicating it is the new last descriptor in the list, and modify the DESCADDR value of the current last descriptor to the
address of the newly created descriptor.
Modifying a Descriptor in a List
In order to add descriptors to a list, the following actions must be performed:
1. Before enabling a channel, the Suspend interrupt must be enabled
2. Reserve memory space addresses to configure a new descriptor
3. Configure the new descriptor
zSet the next descriptor address (DESCADDR)
zSet the destination address (DSTADDR)
zSet the source address (SRCADDR)
zConfigure the block transfer control (BTCTRL) including
zOptionally enable the Suspend block action
zSet the descriptor VALID bit
4. In the existing list and for the descriptor which has to be updated, set the VALID bit to zero
5. Read DESCADDR from the Write-Back memory
DMA Channel 0
DMA Channel 1
PERIPHERAL 0
PERIPHERAL 1
{a,b}
{c,d}
DST Data Buffer
a
b
c
d
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zIf the DMA has not already fetched the descriptor which requires changes:
zUpdate the DESCADDR location of the descriptor from the List
zOptionally clear the Suspend block action
zSet the descriptor VALID bit to one
zOptionally enable the Resume software command
zIf the DMA is executing the same descriptor as the one which requires changes:
zSet the Channel Suspend software command and wait for the Suspend interrupt
zUpdate the Write-Back next descriptor address (DESCRADDR)
zClear the interrupt sources and set the Resume software command
zUpdate the DESCADDR location of the descriptor from the List
zOptionally clear the Suspend block action
zSet the descriptor VALID bit to one
6. Go to step 3 if needed
Adding a Descriptor Between Existing Descriptors
To insert a descriptor C between 2 existing descriptors (A & B), the descriptor currently executed by the DMA must be
identified.
1. If DMA is executing descriptor B, descriptor C cannot be inserted.
2. If DMA has not started to execute descriptor A, follow the steps:
a. Set the descriptor A VALID bit to 0
b. Set the DESCADDR value of descriptor A to point descriptor C instead of descriptor B
c. Set the DESCADDR value of descriptor C to point descriptor B
d. Set the descriptor A VALID bit to 1.
3. If DMA is executing descriptor A,
a. Apply the software suspend command to the channel and
b. Perform steps 2a through 2d
Apply the software resume command to the channel.
18.6.3.2 Channel Suspend
The channel operation can be suspended at anytime by software, by setting the Suspend command in Command bit field
of Channel Control B register (CHCTRLB.CMD). When the ongoing burst transfer is completed, the channel operation is
suspended and the suspend command is automatically cleared.
It is also possible to suspend a channel operation after a block transfer completes. The software must set the Suspend
Block Action in the corresponding Block Transfer Control location (BTCTRL.BLOCKACT). When the block transfer is
completed, the channel operation is suspended. The channel is kept enabled, can receive transfer triggers, but it will be
removed from the arbitration scheme. The channel will automatically suspend the operation if an invalid transfer control
descriptor is fetched from system memory (BTCTRL.VALID=0). The Channel Fetch Error bit in the Channel Status
register (CHSTATUS.FERR) is set when an invalid descriptor is fetched. Only an enabled channel can be suspended. If
the channel is disabled when suspended, the internal suspend command is cleared. When suspended, the Channel
Suspend Interrupt flag in the Channel Interrupt Status and Clear register (CHINTFLAG.SUSP) is set and optional
suspend interrupt is generated.
For more details on transfer descriptors, refer to “Transfer Descriptors” on page 272.
18.6.3.3 Channel Resume and Next Suspend Skip
A channel operation can be resumed by software by setting the Resume command in Command bitfield of Channel
Control B register (CHCTRLB.CMD). If the channel is already suspended, the channel operation resumes from where it
previously stopped when the Resume command is detected. When the Resume command is issued before the channel
is suspended, the next suspend action is skipped and the channel continues the normal operation.
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Figure 18-10.Channel Suspend/Resume Operation
18.6.3.4 Event Input Actions
The event input actions are available only for channels supporting event inputs. For details on channels with event input
support, refer to Table 22-6 and Table 22-4.
The Event Actions bits in the Channel Control B register (CHCTRLB.EVACT) specify the actions the DMA will take on an
input event. Before using event actions, the event controller must be configured first and the corresponding Channel
Event Input Enable bit (CHCTRLB.EVIE) must be set. The DMA supports only resynchronized events. For details on how
to configure the resynchronized event path, refer to the Event System.
Normal transfer: When this event action is selected for a channel, the event input is used to trigger a beat or burst
transfer on peripherals.
The transfer trigger is selected by setting the Trigger Source bits in Channel Control B register to zero
(CHCTRLB.TRIGSRC). The event is acknowledged as soon as the event is received. When received, the Channel
Pending status bit is set (CHSTATUS.PEND). If the event is received while the channel is pending, the event trigger is
lost. Figure 18-11 shows an example where beat transfers are enabled by internal events.
Figure 18-11.Beat Event Trigger Action
Periodic transfers: When this event action is selected for a channel, the event input is used to trigger a transfer on
peripherals with pending transfer requests. This type of event is intended to be used with peripheral triggers for example,
for timed communication protocols or periodic transfers between peripherals, as examples. The peripheral trigger is
selected by the Trigger Source bits in the Channel Control B register (CHCTRLB.TRIGSRC).
The event is acknowledged as soon as the event is received. The peripheral trigger request is stored internally when the
previous trigger action is completed (i.e. channel is not pending) and when an active event is received. If the peripheral
trigger is active, the DMA will wait for an event before the peripheral trigger is internally registered. When both event and
peripheral transfer trigger are active, the Channel Pending status bit is set (CHSTATUS.PEND). A software trigger will
now trigger a transfer.
Figure 18-12 shows an example where the peripheral beat transfers are enabled by periodic events.
Descriptor 0
(suspend disabled)
Memory Descriptor
Transfer
Resume Command
Descriptor 1
(suspend enabled)
Descriptor 2
(suspend enabled)
Suspend skipped
Channel
suspended
Descriptor 3
(last)
Fetch Block
Transfer 0
Block
Transfer 1
Block
Transfer 2
Block
Transfer 3
CHENn
BEAT BEAT BEAT
Block Transfer
BEAT BEAT BEAT
Block Transfer
Event
BUSYCHn
CHENn
Data Transfer
PENDCHn
Trigger Lost
Peripheral Trigger
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Figure 18-12.Periodic Event with Beat Peripheral Triggers
Conditional transfer: When the conditional transfer event action is selected, the event input is used to trigger a
conditional transfer on peripherals with pending transfer requests. As example, this type of event can be used for
peripheral to peripheral transfers, where one peripheral is source of event and the second peripheral is source of DMA
trigger.
The peripheral Trigger Source must be set in Channel Control B register (CHCTRLB.TRIGSRC). Each peripheral trigger
is stored internally when the event is received. When the peripheral trigger is stored internally, the Channel Pending
status bit is set (CHSTATUS.PEND) and the event is acknowledged. A software trigger will now trigger a transfer.
Figure 18-13 shows an example where conditional event is enabled with peripheral beat trigger requests.
Figure 18-13.Conditional Event with Beat Peripheral Triggers
Conditional block transfer: When the conditional block event action is selected, the event input is used to trigger a
conditional block transfer on peripherals. The peripheral Trigger Source must be set in Channel Control B register
(CHCTRLB.TRIGSRC).
Before starting transfers within a block, an event must be received. When received, the event is acknowledged when the
block transfer is completed. A software trigger will trigger a transfer.
Figure 18-14 shows an example where conditional event block transfer is enabled with peripheral beat trigger requests.
Figure 18-14.Conditional Block Transfer with Beat Peripheral Triggers
Trigger LostTrigger Lost
BEAT
Peripheral Trigger
PENDCHn
Event
Block Transfer
Data Transfer
BEAT BEAT
Event
Peripheral Trigger
PENDCHn
Data Transfer Block Transfer
BEAT BEAT
Block Transfer
BEAT BEAT
Block Transfer
Data Transfer
Peripheral Trigger
Event
PENDCHn
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Channel suspend: When the channel suspend event action is selected, the event input is used to suspend an ongoing
channel operation. The event is acknowledged when the current AHB access is completed. For further details on channel
suspend, refer to “Channel Suspend” on page 280.
Channel resume: When the channel resume event action is selected, the event input is used to resume a suspended
channel operation. The event is acknowledged as soon as the event is received and the Channel Suspend Interrupt Flag
(CHINTFLAG.SUSP) is cleared. For further details on channel suspend, refer to “Channel Suspend” on page 280.
Skip next block suspend: This event can be used to skip the next block suspend action. If the channel is suspended
before the event rises, the channel operation is resumed and the event is acknowledged. If the event rises before a
suspend block action is detected, the event is kept until the next block suspend detection. When the block transfer is
completed, the channel continues the operation (not suspended) and the event is acknowledged.
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18.6.3.5 Event Output Selections
The event output selections are available only for channels supporting event outputs. The pulse width of an event output
from a channel is one AHB clock cycle.
The Channel Event Output Enable can be set in Control B register (CHCTRLB.EVOE). The Event Output Selection is
available in each Descriptor Block Control location (BTCTRL.EVOSEL). It is possible to generate events after each beat,
burst or block transfer. To enable an event when the transaction is complete, the block event selection must be set in the
last transfer descriptor only. Figure 18-15 shows an example where the event output generation is enabled in the first
block transfer, and disabled in the second block.
Figure 18-15.Event Output Generation
18.6.3.6 Aborting Transfers
Transfers on any channel can be gracefully aborted by software, by disabling the corresponding DMA channel. It is also
possible to abort all ongoing or pending transfers, by disabling the DMAC.
When DMAC disable request is detected:
zActive channel with ongoing transfers will be disabled when the ongoing beat access is completed and the Write-
Back memory section is updated. This prevents transfer corruption before the channel is disabled.
zAll other enabled channels will be disabled in the next clock cycle.
The corresponding Channel Enable bit in the Channel Control A register (CHCTRLA.ENABLE) is read as zero when the
channel is disabled.
The corresponding DMAC Enable bit in the Control register (CTRL.DMAENABLE) is read as zero when the entire DMAC
module is disabled.
18.6.3.7 CRC Operation
A cyclic redundancy check (CRC) is an error detection technique used to find accidental errors in data. It is commonly
used to determine whether the data during a transmission, or data present in data and programme memories has been
corrupted or not. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be
appended to the data and used as a checksum. When the same data are later received or read, the device or application
repeats the calculation. If the new CRC result does not match the one calculated earlier, the block contains a data error.
The application will then detect this and may take a corrective action, such as requesting the data to be sent again or
simply not using the incorrect data.
Typically, a CRC-n applied to a data block of arbitrary length will detect any single error burst not longer than n bits (any
single alteration that spans no more than n bits of the data), and will detect the fraction 1-2-n of all longer error bursts. The
BEAT BEAT
Block Transfer
Beat Event Output
Data Transfer BEAT BEAT
Block Transfer
Event Output
BEAT BEAT
Block Transfer
Block Event Output
Data Transfer BEAT BEAT
Block Transfer
Event Output
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CRC module in DMAC supports two commonly used CRC polynomials: CRC-16 (CRC-CCITT) and CRC-32 (IEEE
802.3).
zCRC-16:
zPolynomial: x16 + x12 + x5+1
zHex value: 0x1021
zCRC-32:
zPolynomial: x32 +x26+x23 +x22 +x16 +x12 +x11 +x10 +x8 +x7 +x5 +x4 +x2 +x+1
zHex value: 0x04C11DB7
The data source for the CRC module must be selected in software as either the DMA channels or the APB bus interface.
The CRC module then takes data input from the selected source and generates a checksum based on these data. The
checksum is available in the CRC Checksum register (CRCCHKSUM). When CRC-32 polynomial is used, the final
checksum read is bit reversed and complemented, as shown in Figure 18-16 on page 285.
The CRC polynomial to be used is configurable, and the default setting is CRC-16. The CRC module operates on byte
only. When the DMA is used as data source for the CRC module, the DMA channel beat size setting will be used. When
used with APB bus interface, the application must set the CRC Beat Size bit field of CRC Control register
(CRCCTRL.CRCBEATSIZE). 8-, 16- or 32-bit bus transfer access type is supported. The corresponding number of bytes
will be written in the CRCDATAIN register and the CRC module will operate on the input data in a byte by byte manner.
Figure 18-16.CRC Generator Block Diagram
CRC on DMA data: CRC-16 or CRC-32 calculations can be performed on data passing through any DMA channel. Once
a DMA channel is selected as the source, the CRC module will continuously generate the CRC on the data passing
through the DMA channel. The checksum is available for readout once the DMA transaction is completed or aborted. A
CRC can also be generated on SRAM, Flash or I/O memory by passing these data through a DMA channel. If the latter
is done, the destination register for the DMA data can be the data input (CRCDATAIN) register in the CRC module.
CRC using the I/O interface: Before using the CRC module with the I/O interface, the application must set the CRC
Beat Size bits in the CRC Control register (CRCCTRL.CRCBEATSIZE). 8/16/32-bit bus transfer type can be selected.
168 8 32
Checksum
read
crc32
CRCCTRL
CHECKSUM
bit-reverse +
complement
CRC-16 CRC-32
DMAC
Channels
CRCDATAIN
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CRC can be performed on any data by loading them into the CRC module using the CPU and writing the data to the
CRCDATAIN register. Using this method, an arbitrary number of bytes can be written to the register by the CPU, and
CRC is done continuously for each byte. This means if a 32-bit data is written to the CRCDATAIN register the CRC
module takes 4 cycles to calculate the CRC. The CRC complete is signaled by the CRCBUSY bit in the CRCSTATUS
register. New data can be written only when CRCBUSY flag is not set.
18.6.4 DMA Operation
Not applicable.
18.6.5 Interrupts
The DMAC has the following interrupt sources:
zTransfer Complete (TCMPL): Indicates that a block transfer is completed on the corresponding channel. Refer to
“Data Transmission” on page 275 for details.
zTransfer Error (TERR): Indicates that a bus error has occurred during a burst transfer, or that an invalid descriptor
has been fetched. Refer to “Error Handling” on page 279 for details.
zChannel Suspend (SUSP): Indicates that the corresponding channel has been suspended. Refer to
“Channel
Suspend” on page 280
and “Data Transmission” on page 275 for details.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Channel Interrupt Flag Status and
Clear (CHINTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by
writing a one to the corresponding bit in the Channel Interrupt Enable Set (CHINTENSET) register, and disabled by
writing a one to the corresponding bit in the Channel Interrupt Enable Clear (CHINTENCLR) register. An interrupt request
is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains
active until the interrupt flag is cleared, the interrupt is disabled, the DMAC is reset or the corresponding DMA channel is
reset. See CHINTFLAG for details on how to clear interrupt flags. All interrupt requests are ORed together on system
level to generate one combined interrupt request to the NVIC. Refer to “Nested Vector Interrupt Controller” on page 29
for details.
The user must read the Channel Interrupt Status (INTSTATUS) register to identify the channels with pending interrupts
and must read the Channel Interrupt Flag Status and Clear (CHINTFLAG) register to determine which interrupt condition
is present for the corresponding channel. It is also possible to read the Interrupt Pending register (INTPEND), which
provides the lowest channel number with pending interrupt and the respective interrupt flags.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to “Nested Vector Interrupt
Controller” on page 29 for details.
18.6.6 Events
The DMAC can generate the following output events:
zChannel (CH): Generated when a block transfer for a given channel has been completed, or when a beat transfer
within a block transfer for a given channel has been completed. Refer to “Event Output Selections” on page 284 for
details.
Writing a one to the Channel Control B Event Output Enable bit (CHCTRLB.EVOE) enables the corresponding output
event configured in the Event Output Selection bit group in the Block Transfer Control register (BTCTRL.EVOSEL).
Writing a zero to CHCTRLB.EVOE disables the corresponding output event. Refer to “EVSYS – Event System” on page
400 for details on configuring the event system.
The DMAC can take the following actions on an input event:
zTransfer and Periodic Transfer Trigger (TRIG): normal transfer or periodic transfers on peripherals are enabled
zConditional Transfer Trigger (CTRIG): conditional transfers on peripherals are enabled
zConditional Block Transfer Trigger (CBLOCK): conditional block transfers on peripherals are enabled
zChannel Suspend Operation (SUSPEND): suspend a channel operation
zChannel Resume Operation (RESUME): resume a suspended channel operation
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zSkip Next Block Suspend Action (SSKIP): skip the next block suspend transfer condition
Writing a one to the Channel Control B Event Input Enable bit (CHCTRLB.EVIE) enables the corresponding action on
input event. Writing a zero to this bit disables the corresponding action on input event. Note that several actions can be
enabled for incoming events. If several events are connected to the peripheral, any enabled action will be taken for any of
the incoming events. For further details on event input actions, refer to “Event Input Actions” on page 281. Refer to the
Event System chapter for details on configuring the event system.
18.6.7 Sleep Mode Operation
In standby sleep mode, the DMAC will be internally disabled, but maintains its current configuration.
18.6.8 Synchronization
Not applicable.
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18.7 Register Summary
Table 18-1. DMAC Register Summary
Offset Name
Bit
Pos.
0x00
CTRL
7:0 CRCENABLE DMAENABLE SWRST
0x01 15:8 LVLEN3 LVLEN2 LVLEN1 LVLEN0
0x02
CRCCTRL
7:0 CRCPOLY[1:0] CRCBEATSIZE[1:0]
0x03 15:8 CRCSRC[5:0]
0x04
CRCDATAIN
7:0 CRCDATAIN[7:0]
0x05 15:8 CRCDATAIN[15:8]
0x06 23:16 CRCDATAIN[23:16]
0x07 31:24 CRCDATAIN[31:24]
0x08
CRCCHKSUM
7:0 CRCCHKSUM[7:0]
0x09 15:8 CRCCHKSUM[15:8]
0x0A 23:16 CRCCHKSUM[23:16]
0x0B 31:24 CRCCHKSUM[31:24]
0x0C CRCSTATUS 7:0 CRCZERO CRCBUSY
0x0D DBGCTRL 7:0 DBGRUN
0x0E QOSCTRL 7:0 DQOS FQOS WRQOS
0x0F
Reserved
0x10
SWTRIGCTRL
7:0 SWTRIG7 SWTRIG6 SWTRIG5 SWTRIG4 SWTRIG3 SWTRIG2 SWTRIG1 SWTRIG0
0x11 15:8 SWTRIG11 SWTRIG10 SWTRIG9 SWTRIG8
0x12 23:16
0x13 31:24
0x14
PRICTRL0
7:0 RRLVLEN0 LVLPRI0[3:0]
0x15 15:8 RRLVLEN1 LVLPRI1[3:0]
0x16 23:16 RRLVLEN2 LVLPRI2[3:0]
0x17 31:24 RRLVLEN3 LVLPRI3[3:0]
0x18
...
0x1F
Reserved
0x20
INTPEND
7:0 ID[3:0]
0x21 15:8 PEND BUSY FERR SUSP TCMPL TERR
0x22 Reserved
0x23 Reserved
0x24
INTSTATUS
7:0 CHINT7 CHINT6 CHINT5 CHINT4 CHINT3 CHINT2 CHINT1 CHINT0
0x25 15:8 CHINT11 CHINT10 CHINT9 CHINT8
0x26 23:16
0x27 31:24
0x28
BUSYCH
7:0 BUSYCH7 BUSYCH6 BUSYCH5 BUSYCH4 BUSYCH3 BUSYCH2 BUSYCH1 BUSYCH0
0x29 15:8 BUSYCH11 BUSYCH10 BUSYCH9 BUSYCH8
0x2A 23:16
0x2B 31:24
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Table 18-2. DMAC SRAM Register Summary - Descriptor/Write-Back Memory Section
0x2C
PENDCH
7:0 PENDCH7 PENDCH6 PENDCH5 PENDCH4 PENDCH3 PENDCH2 PENDCH1 PENDCH0
0x2D 15:8 PENDCH11 PENDCH10 PENDCH9 PENDCH8
0x2E 23:16
0x2F 31:24
0x30
ACTIVE
7:0 LVLEX3 LVLEX2 LVLEX1 LVLEX0
0x31 15:8 ABUSY ID[4:0]
0x32 23:16 BTCNT[7:0]
0x33 31:24 BTCNT[15:8]
0x34
BASEADDR
7:0 BASEADDR[7:0]
0x35 15:8 BASEADDR[15:8]
0x36 23:16 BASEADDR[23:16]
0x37 31:24 BASEADDR[31:24]
0x38
WRBADDR
7:0 WRBADDR[7:0]
0x39 15:8 WRBADDR[15:8]
0x3A 23:16 WRBADDR[23:16]
0x3B 31:24 WRBADDR[31:24]
0x3C
...
0x3E
Reserved
0x3F CHID 7:0 ID[3:0]
0x40 CHCTRLA 7:0 ENABLE SWRST
0x41
...
0x43
Reserved
0x44
CHCTRLB
7:0 LVL[1:0] EVOE EVIE EVACT[2:0]
0x45 15:8 TRIGSRC[5:0]
0x46 23:16 TRIGACT[1:0]
0x47 31:24 CMD[1:0]
0x48
...
0x4B
Reserved
0x4C CHINTENCLR 7:0 SUSP TCMPL TERR
0x4D CHINTENSET 7:0 SUSP TCMPL TERR
0x4E CHINTFLAG 7:0 SUSP TCMPL TERR
0x4F CHSTATUS 7:0 FERR BUSY PEND
Offset Name
Bit
Pos.
0x00
BTCTRL
7:0 BLOCKACT[1:0] EVOSEL[1:0] VALID
0x01 15:8 STEPSIZE[2:0] STEPSEL DSTINC SRCINC BEATSIZE[1:0]
0x02
BTCNT
7:0 BTCNT[7:0]
0x03 15:8 BTCNT[15:8]
Offset Name
Bit
Pos.
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0x04
SRCADDR
7:0 SRCADDR[7:0]
0x05 15:8 SRCADDR[15:8]
0x06 23:16 SRCADDR[23:16]
0x07 31:24 SRCADDR[31:24]
0x08
DSTADDR
7:0 DSTADDR[7:0]
0x09 15:8 DSTADDR[15:8]
0x0A 23:16 DSTADDR[23:16]
0x0B 31:24 DSTADDR[31:24]
0x0C
DESCADDR
7:0 DESCADDR[7:0]
0x0D 15:8 DESCADDR[15:8]
0x0E 23:16 DESCADDR[23:16]
0x0F 31:24 DESCADDR[31:24]
Offset Name
Bit
Pos.
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18.8 Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters
and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by
the Write-Protected property in each individual register description. Please refer to “Register Access Protection” on page
269 for details.
Some registers are enable-protected, meaning they can only be written when the DMAC is disabled. Enable-protection is
denoted by the Enable-Protected property in each individual register description.
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18.8.1 DMAC Registers
18.8.1.1 Control
Name: CTRL
Offset: 0x00
Reset: 0x0000
Property: Enable-Protected, Write-Protected
zBits 15:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 11:8 – LVLENx [x=3..0]: Priority Level x Enable
0: Transfer requests for Priority level x will not be handled.
1: Transfer requests for Priority level x will be handled.
When this bit is set, all requests with the corresponding level will be fed into the arbiter block. When cleared, all
requests with the corresponding level will be ignored.
For details on arbitration schemes, refer to “Arbitration” on page 274 section.
These bits are not enable-protected.
zBits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 2 – CRCENABLE: CRC Enable
0: The CRC module is disabled.
1: The CRC module is enabled.
Writing a zero to this bit will disable the CRC module if the CRC Status Busy bit in the CRC Status register (CRC-
STATUS.CRCBUSY) is zero. If the CRCSTATUS.CRCBUSY is one, the write will be ignored and the CRC module
will not be disabled.
Writing a one to this bit will enable the CRC module.
This bit is not enable-protected.
zBit 1 – DMAENABLE: DMA Enable
0: The peripheral is disabled.
1: The peripheral is enabled.
Writing a zero to this bit during an ongoing transfer, the bit will not be cleared until the internal data transfer buffer
is empty and the DMA transfer is aborted. The internal data transfer buffer will be empty once the ongoing burst
transfer is completed.
Bit 151413121110 9 8
LVLEN3 LVLEN2 LVLEN1 LVLEN0
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 76543210
CRCENABLE DMAENABLE
SWRST
AccessRRRRRR/WR/WR/W
Reset00000000
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Writing a one to this bit will enable the DMA module.
This bit is not enable-protected.
zBit 0 – SWRST: Software Reset
0: There is no reset operation ongoing.
1: The reset operation is ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit when both the DMAC and the CRC module are disabled (DMAENABLE and CRCENABLE
is zero), resets all registers in the DMAC, except DBGCTRL, to their initial state If either the DMAC or CRC module
is enabled, the reset request will be ignored and the DMAC will return an access error.
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18.8.1.2 CRC Control
Name: CRCCTRL
Offset: 0x02
Reset: 0x0000
Property: Enable-Protected, Write-Protected
zBits 15:14 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 13:8 – CRCSRC[5:0]: CRC Input Source
These bits select the input source for generating the CRC, as shown in Table 18-3. The selected source is locked
until either the CRC generation is completed or the CRC module is disabled. This means the CRCSRC cannot be
modified when the CRC operation is ongoing. The lock is signaled by the CRCBUSY status bit. CRC generation
complete is generated and signaled from the selected source when used with the DMA channel.
Table 18-3. CRC Input Source
zBits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 3:2 – CRCPOLY[1:0]: CRC Polynomial Type
These bits select the CRC polynomial type, as shown in Table 18-4.
Bit 151413121110 9 8
CRCSRC[5:0]
Access R R R/W R/W R/W R/W R/W R/W
Reset00000000
Bit 76543210
CRCPOLY[1:0] CRCBEATSIZE[1:0]
AccessRRRRR/WR/WR/WR/W
Reset00000000
CRCSRC[5:0] Name Description
0x0 NOACT No action
0x1 IO I/O interface
0x2-0x1F Reserved
0x20-0x3F CHN DMA channel n
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Table 18-4. CRC Polynomial Type
zBits 1:0 – CRCBEATSIZE[1:0]: CRC Beat Size
These bits define the size of the data transfer for each bus access when the CRC is used with I/O interface, as
shown in Table 18-5.
Table 18-5. CRC Beat Size
CRCPOLY[1:0] Name Description
0x0 CRC16 CRC-16 (CRC-CCITT)
0x1 CRC32 CRC32 (IEEE 802.3)
0x2-0x3 Reserved
CRCBEATSIZE[1:0] Name Description
0x0 BYTE Byte bus access
0x1 HWORD Half-word bus access
0x2 WORD Word bus access
0x3 Reserved
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18.8.1.3 CRC Data Input
Name: CRCDATAIN
Offset: 0x04
Reset: 0x00000000
Property: Write-Protected
zBits 31:0 – CRCDATAIN[31:0]: CRC Data Input
These bits store the data for which the CRC checksum is computed. After the CRCDATAIN register has been writ-
ten, the number of cycles for the new CRC checksum to be ready is dependent of the configuration of the CRC
Beat Size bit group in the CRC Control register(CRCCTRL.CRCBEATSIZE). Each byte needs one clock cycle to
be calculated.
Bit 3130292827262524
CRCDATAIN[31:24]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
CRCDATAIN[23:16]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
CRCDATAIN[15:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
CRCDATAIN[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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18.8.1.4 CRC Checksum
The CRCCHKSUM represents the 16- or 32-bit checksum value and the generated CRC.
Name: CRCCHKSUM
Offset: 0x08
Reset: 0x00000000
Property: Enable-Protected, Write-Protected
zBits 31:0 – CRCCHKSUM[31:0]: CRC Checksum
These bits store the generated CRC result. The 16 MSB bits are always read zero when CRC-16 is enabled.
These bits should only be read when CRC Module Busy bit in the CRC Status register (CRCSTATUS.BUSY) is
zero.
If CRC-16 is selected and CRCSTATUS.BUSY is zero (CRC generation is completed), this bit group will contain a
valid checksum.
If CRC-32 is selected and CRCSTATUS.BUSY is zero (CRC generation is completed), this bit group will contain a
valid reversed checksum. Bit 31 is swapped with bit 0, bit 30 with bit 1, etc.
Bit 3130292827262524
CRCCHKSUM[31:24]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
CRCCHKSUM[23:16]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
CRCCHKSUM[15:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
CRCCHKSUM[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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18.8.1.5 CRC Status
Name: CRCSTATUS
Offset: 0x0C
Reset: 0x00
Property: Write-Protected
zBits 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 1 – CRCZERO: CRC Zero
This bit is cleared when a new CRC source is selected.
This bit is set when the CRC generation is complete and the CRC Checksum is zero.
zBit 0 – CRCBUSY: CRC Module Busy
When used with an I/O interface (CRCCTRL.CRCSRC is 0x1), this bit is cleared by writing a one to it.
When used with an I/O interface (CRCCTRL.CRCSRC is 0x1), this bit is set when the CRC Data Input (CRC-
DATAIN) register is written.
When used with a DMA channel (CRCCTRL.CRCSRC is 0x20 to 0x3F), this bit is cleared when the corresponding
DMA channel is disabled.
When used with a DMA channel (CRCCTRL.CRCSRC is 0x20 to 0x3F), this bit is set when the corresponding
DMA channel is enabled.
Writing a zero to this bit has no effect.
When used with an I/O interface(CRCCTRL.CRCSRC is 0x1), writing a one to this bit will clear the CRC Module
Busy bit.
When used with a DMA channel, writing a one to this bit has no effect.
Bit 76543210
CRCZERO CRCBUSY
AccessRRRRRRRR/W
Reset00000000
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18.8.1.6 Debug Control
Name: DBGCTRL
Offset: 0x0D
Reset: 0x00
Property: Write-Protected
zBits 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 0 – DBGRUN: Debug Run
This bit is not reset by a software reset.
This bit controls the functionality when the CPU is halted by an external debugger.
0: The DMAC is halted when the CPU is halted by an external debugger.
1: The DMAC continues normal operation when the CPU is halted by an external debugger.
Bit 76543210
DBGRUN
AccessRRRRRRRR/W
Reset00000000
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18.8.1.7 QOS Control
Name: QOSCTRL
Offset: 0x0E
Reset: 0x15
Property: Enable-Protected, Write-Protected
zBits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 5:4 – DQOS[1:0]: DATA Quality of Service
These bits define the SRAM quality of service of the DMAC DATA master. Refer to “SRAM Quality of Service” on
page 34.
zBits 3:2 – FQOS[1:0]: Fetch Quality of Service
These bits define the SRAM quality of service of the DMAC Fetch master. Refer to “SRAM Quality of Service” on
page 34.
zBits 1:0 – WBQOS[1:0]: WB Quality of Service
These bits define the SRAM quality of service of the DMAC WB master. Refer to “SRAM Quality of Service” on
page 34.
Bit 76543210
DQOS[1:0] FQOS[1:0] WBQOS[1:0]
Access R R R/W R/W R/W R/W R/W R/W
Reset00010101
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18.8.1.8 Software Trigger Control
Name: SWTRIGCTRL
Offset: 0x10
Reset: 0x00000000
Property: Write-Protected
zBits 31:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 11:0 – SWTRIGx [x=11..0]: Channel x Software Trigger
This bit is cleared when the Channel Pending bit in the Channel Status register (CHSTATUS.PEND) for the corre-
sponding channel is set, or by writing a one to it.
This bit is set if CHSTATUS.PEND is already one, when writing a one to this bit.
Writing a zero to this bit will clear the bit.
Writing a one to this bit will generate a DMA software trigger on channel x, if CHSTATUS.PEND is zero for channel
x.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
AccessRRRRRRRR
Reset00000000
Bit 151413121110 9 8
SWTRIG11 SWTRIG10
SWTRIG9 SWTRIG8
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 76543210
SWTRIG7 SWTRIG6 SWTRIG5 SWTRIG4 SWTRIG3 SWTRIG2 SWTRIG1 SWTRIG0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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18.8.1.9 Priority Control 0
Name: PRICTRL0
Offset: 0x14
Reset: 0x00000000
Property: Write-Protected
zBit 31 – RRLVLEN3: Level 3 Round-Robin Scheduling Enable
0: Static scheduling scheme for channels with level 3 priority.
1: Round-robin scheduling scheme for channels with level 3 priority.
For details on scheduling schemes, refer to “Arbitration” on page 274.
zBits 30:28 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 27:24 – LVLPRI3[3:0]: Level 3 Channel Priority Number
When round-robin arbitration is enabled (PRICTRL0.RRLVLEN3 is one) for priority level 3, this register holds the
channel number of the last DMA channel being granted access as the active channel with priority level 3.
When static arbitration is enabled (PRICTRL0.RRLVLEN3 is zero) for priority level 3, and the value of this bit
group is non-zero, it will not affect the static priority scheme. If the value of this bit group is x, channel x will have
the highest priority. The priority will decrease as the channel number increases from x to n, where n is the maxi-
mum number of channels. Channel n has higher priority than channel 0, and the priority will continue to decrease
from channel 0 to channel (x-1).
This bit group is not reset when round-robin scheduling gets disabled (PRICTRL0.RRLVLEN3 written to zero).
Bit 3130292827262524
RRLVLEN3 LVLPRI3[3:0]
Access R/W R R R R/W R/W R/W R/W
Reset00000000
Bit 2322212019181716
RRLVLEN2 LVLPRI2[3:0]
Access R/W R R R R/W R/W R/W R/W
Reset00000000
Bit 151413121110 9 8
RRLVLEN1 LVLPRI1[3:0]
Access R/W R R R R/W R/W R/W R/W
Reset00000000
Bit 76543210
RRLVLEN0 LVLPRI0[3:0]
Access R/W R R R R/W R/W R/W R/W
Reset00000000
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zBit 23 – RRLVLEN2: Level 2 Round-Robin Scheduling Enable
0: Static scheduling scheme for channels with level 2 priority.
1: Round-robin scheduling scheme for channels with level 2 priority.
For details on scheduling schemes, refer to “Arbitration” on page 274.
zBits 22:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 19:16 – LVLPRI2[3:0]: Level 2 Channel Priority Number
When round-robin arbitration is enabled (PRICTRL0.RRLVLEN2 is one) for priority level 2, this register holds the
channel number of the last DMA channel being granted access as the active channel with priority level 2.
When static arbitration is enabled (PRICTRL0.RRLVLEN2 is zero) for priority level 2, and the value of this bit
group is non-zero, it will not affect the static priority scheme. If the value of this bit group is x, channel x will have
the highest priority. The priority will decrease as the channel number increases from x to n, where n is the maxi-
mum number of channels. Channel n has higher priority than channel 0, and the priority will continue to decrease
from channel 0 to channel (x-1).
This bit group is not reset when round-robin scheduling gets disabled (PRICTRL0.RRLVLEN2 written to zero).
zBit 15 – RRLVLEN1: Level 1 Round-Robin Scheduling Enable
0: Static scheduling scheme for channels with level 1 priority.
1: Round-robin scheduling scheme for channels with level 1 priority.
For details on scheduling schemes, refer to “Arbitration” on page 274.
zBits 14:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 11:8 – LVLPRI1[3:0]: Level 1 Channel Priority Number
When round-robin arbitration is enabled (PRICTRL0.RRLVLEN1 is one) for priority level 1, this register holds the
channel number of the last DMA channel being granted access as the active channel with priority level 1.
When static arbitration is enabled (PRICTRL0.RRLVLEN1 is zero) for priority level 1, and the value of this bit
group is non-zero, it will not affect the static priority scheme. If the value of this bit group is x, channel x will have
the highest priority. The priority will decrease as the channel number increases from x to n, where n is the maxi-
mum number of channels. Channel n has higher priority than channel 0, and the priority will continue to decrease
from channel 0 to channel (x-1).
This bit group is not reset when round-robin scheduling gets disabled (PRICTRL0.RRLVLEN1 written to zero).
zBit 7 – RRLVLEN0: Level 0 Round-Robin Scheduling Enable
0: Static scheduling scheme for channels with level 0 priority.
1: Round-robin scheduling scheme for channels with level 0 priority.
For details on scheduling schemes, refer to “Arbitration” on page 274.
zBits 6:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 3:0 – LVLPRI0[3:0]: Level 0 Channel Priority Number
When round-robin arbitration is enabled (PRICTRL0.RRLVLEN0 is one) for priority level 0, this register holds the
channel number of the last DMA channel being granted access as the active channel with priority level 0.
When static arbitration is enabled (PRICTRL0.RRLVLEN0 is zero) for priority level 0, and the value of this bit
group is non-zero, it will not affect the static priority scheme. If the value of this bit group is x, channel x will have
the highest priority. The priority will decrease as the channel number increases from x to n, where n is the maxi-
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mum number of channels. Channel n has higher priority than channel 0, and the priority will continue to decrease
from channel 0 to channel (x-1).
This bit group is not reset when round-robin scheduling gets disabled (PRICTRL0.RRLVLEN0 written to zero).
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18.8.1.10 Interrupt Pending
This register allows the user to identify the lowest DMA channel with pending interrupt.
Name: INTPEND
Offset: 0x20
Reset: 0x0000
Property: -
zBit 15 – PEND: Pending
This bit is read one when the channel selected by Channel ID field (ID) is pending.
zBit 14 – BUSY: Busy
This bit is read one when the channel selected by Channel ID field (ID) is busy.
zBit 13 – FERR: Fetch Error
This bit is read one when the channel selected by Channel ID field (ID) fetched an invalid descriptor.
zBits 12:11 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 10 – SUSP: Channel Suspend
This bit is read one when the channel selected by Channel ID field (ID) has pending Suspend interrupt.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Channel ID (ID) Suspend interrupt flag.
zBit 9 – TCMPL: Transfer Complete
This bit is read one when the channel selected by Channel ID field (ID) has pending Transfer Complete interrupt.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Channel ID (ID) Transfer Complete interrupt flag.
zBit 8 – TERR: Transfer Error
This bit is read one when the channel selected by Channel ID field (ID) has pending Transfer Error interrupt.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Channel ID (ID) Transfer Error interrupt flag.
zBits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit 151413121110 9 8
PEND BUSY FERR SUSP TCMPL TERR
AccessRRRRRR/WR/WR/W
Reset00000000
Bit 76543210
ID[3:0]
AccessRRRRR/WR/WR/WR/W
Reset00000000
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zBits 3:0 – ID[3:0]: Channel ID
These bits store the lowest channel number with pending interrupts. The number is valid if Suspend (SUSP),
Transfer Complete (TCMPL) or Transfer Error (TERR) bits are set. The Channel ID field is refreshed when a new
channel (with channel number less than the current one) with pending interrupts is detected, or when the applica-
tion clears the corresponding channel interrupt sources. When no pending channels interrupts are available, these
bits will always return zero value when read.
When the bits are written, indirect access to the corresponding Channel Interrupt Flag register is enabled.
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18.8.1.11 Interrupt Status
Name: INTSTATUS
Offset: 0x24
Reset: 0x00000000
Property: -
zBits 31:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 11:0 – CHINTx [x=11..0]: Channel x Pending Interrupt
This bit is set when Channel x has pending interrupt.
This bit is cleared when the corresponding Channel x interrupts are disabled or the interrupts sources are cleared.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
AccessRRRRRRRR
Reset00000000
Bit 151413121110 9 8
CHINT11 CHINT10 CHINT9 CHINT8
AccessRRRRRRRR
Reset00000000
Bit 76543210
CHINT7 CHINT6 CHINT5 CHINT4 CHINT3 CHINT2 CHINT1 CHINT0
AccessRRRRRRRR
Reset00000000
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18.8.1.12 Busy Channels
Name: BUSYCH
Offset: 0x28
Reset: 0x00000000
Property: -
zBits 31:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 11:0 – BUSYCHx [x=11..0]: Busy Channel x
This bit is cleared when the channel trigger action for DMA channel x is complete, when a bus error for DMA chan-
nel x is detected, or when DMA channel x is disabled.
This bit is set when DMA channel x starts a DMA transfer.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
AccessRRRRRRRR
Reset00000000
Bit 151413121110 9 8
BUSYCH11 BUSYCH10
BUSYCH9 BUSYCH8
AccessRRRRRRRR
Reset00000000
Bit 76543210
BUSYCH7 BUSYCH6 BUSYCH5 BUSYCH4 BUSYCH3 BUSYCH2 BUSYCH1 BUSYCH0
AccessRRRRRRRR
Reset00000000
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18.8.1.13 Pending Channels
Name: PENDCH
Offset: 0x2C
Reset: 0x00000000
Property: -
zBits 31:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 11:0 – PENDCHx [x=11..0]: Pending Channel x
This bit is cleared when trigger execution defined by channel trigger action settings for DMA channel x is started,
when a bus error for DMA channel x is detected or when DMA channel x is disabled. For details on trigger action
settings, refer to Table 18-7.
This bit is set when a transfer is pending on DMA channel x.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
AccessRRRRRRRR
Reset00000000
Bit 151413121110 9 8
PENDCH11 PENDCH10
PENDCH9 PENDCH8
AccessRRRRRRRR
Reset00000000
Bit 76543210
PENDCH7 PENDCH6 PENDCH5 PENDCH4 PENDCH3 PENDCH2 PENDCH1 PENDCH0
AccessRRRRRRRR
Reset00000000
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18.8.1.14 Active Channel and Levels
Name: ACTIVE
Offset: 0x30
Reset: 0x00000000
Property: -
zBits 31:16 – BTCNT[15:0]: Active Channel Block Transfer Count
These bits hold the 16-bit block transfer count of the ongoing transfer. This value is stored in the active channel
and written back in the corresponding Write-Back channel memory location when the arbiter grants a new channel
access. The value is valid only when the active channel active busy flag (ABUSY) is set.
zBit 15 – ABUSY: Active Channel Busy
This bit is cleared when the active transfer count is written back in the Write-Back memory section.
This flag is set when the next descriptor transfer count is read from the Write-Back memory section.
zBits 14:13 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 12:8 – ID[4:0]: Active Channel ID
These bits hold the channel index currently stored in the active channel registers. The value is updated each time
the arbiter grants a new channel transfer access request.
zBits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit 3130292827262524
BTCNT[15:8]
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
BTCNT[7:0]
AccessRRRRRRRR
Reset00000000
Bit 151413121110 9 8
ABUSY ID[4:0]
AccessRRRRRRRR
Reset00000000
Bit 76543210
LVLEX3 LVLEX2 LVLEX1 LVLEX0
AccessRRRRRRRR
Reset00000000
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zBits 3:0 – LVLEXx [x=3..0]: Level x Channel Trigger Request Executing
This bit is set when a level-x channel trigger request is executing or pending.
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18.8.1.15 Descriptor Memory Section Base Address
Name: BASEADDR
Offset: 0x34
Reset: 0x00000000
Property: Enable-Protected, Write-Protected
zBits 31:0 – BASEADDR[31:0]: Descriptor Memory Base Address
These bits store the Descriptor memory section base address. The value must be 128-bit aligned.
Bit 3130292827262524
BASEADDR[31:24]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
BASEADDR[23:16]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
BASEADDR[15:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
BASEADDR[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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18.8.1.16 Write-Back Memory Section Base Address
Name: WRBADDR
Offset: 0x38
Reset: 0x00000000
Property: Enable-Protected, Write-Protected
zBits 31:0 – WRBADDR[31:0]: Write-Back Memory Base Address
These bits store the Write-Back memory base address. The value must be 128-bit aligned.
Bit 3130292827262524
WRBADDR[31:24]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
WRBADDR[23:16]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
WRBADDR[15:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
WRBADDR[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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18.8.1.17 Channel ID
Name: CHID
Offset: 0x3F
Reset: 0x00
Property: -
zBits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 3:0 – ID[3:0]: Channel ID
These bits define the channel number that will be accessed. Before reading or writing a channel register, the chan-
nel ID bit group must be written first.
Bit 76543210
ID[3:0]
AccessRRRRR/WR/WR/WR/W
Reset00000000
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18.8.1.18 Channel Control A
Name: CHCTRLA
Offset: 0x40
Reset: 0x00
Property: Enable-Protected, Write-Protected
zBits 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 1 – ENABLE: Channel Enable
0: DMA channel is disabled.
1: DMA channel is enabled.
Writing a zero to this bit during an ongoing transfer, the bit will not be cleared until the internal data transfer buffer
is empty and the DMA transfer is aborted. The internal data transfer buffer will be empty once the ongoing burst
transfer is completed.
Writing a one to this bit will enable the DMA channel.
This bit is not enable-protected.
zBit 0 – SWRST: Channel Software Reset
0: There is no reset operation ongoing.
1: The reset operation is ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit resets the channel registers to their initial state. The bit can be set when the channel is dis-
abled (ENABLE = 0). Writing a one to this bit will be ignored as long as the channel is enabled (ENABLE = 1). This
bit is automatically cleared when the reset is completed.
Writing a one to this bit when the corresponding DMA channel is disabled (ENABLE is zero), resets all registers for
the corresponding DMA channel to their initial state If the corresponding DMA channel is enabled, the reset
request will be ignored.
Bit 76543210
ENABLE SWRST
AccessRRRRRRR/WR/W
Reset00000000
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18.8.1.19 Channel Control B
Name: CHCTRLB
Offset: 0x44
Reset: 0x00000000
Property: Enable-Protected, Write-Protected
zBits 31:26 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 25:24 – CMD[1:0]: Software Command
These bits define the software commands, as shown in Table 18-6.
These bits are not enable-protected.
Table 18-6. Software Command
Bit 3130292827262524
CMD[1:0]
AccessRRRRRRR/WR/W
Reset00000000
Bit 2322212019181716
TRIGACT[1:0]
AccessR/WR/WRRRRRR
Reset00000000
Bit 151413121110 9 8
TRIGSRC[5:0]
Access R R R/W R/W R/W R/W R/W R/W
Reset00000000
Bit 76543210
LVL[1:0] EVOE EVIE EVACT[2:0]
Access R R/W R/W R/W R/W R/W R/W R/W
Reset00000000
CMD[1:0] Name Description
0x0 NOACT No action
0x1 SUSPEND Channel suspend operation
0x2 RESUME Channel resume operation
0x3 Reserved
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zBits 23:22 – TRIGACT[1:0]: Trigger Action
These bits define the trigger action used for a transfer, as shown in Table 18-7.
Table 18-7. Trigger Action
zBits 21:14 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 13:8 – TRIGSRC[5:0]: Peripheral Trigger Source
These bits define the peripheral trigger which is source of the transfer. For details on trigger selection and trigger
modes, refer to “Transfer Triggers and Actions” on page 276 and Table 18-7.
TRIGACT[1:0] Name Description
0x0 BLOCK One trigger required for each block transfer
0x1 Reserved
0x2 BEAT One trigger required for each beat transfer
0x3 TRANSACTION One trigger required for each transaction
Table 18-8. Peripheral Trigger Source
Value Name Description
0x00 DISABLE Only software/event triggers
0x01 SERCOM0 RX SERCOM0 RX Trigger
0x02 SERCOM0 TX SERCOM0 TX Trigger
0x03 SERCOM1 RX SERCOM1 RX Trigger
0x04 SERCOM1 TX SERCOM1 TX Trigger
0x05 SERCOM2 RX SERCOM2 RX Trigger
0x06 SERCOM2 TX SERCOM2 TX Trigger
0x07 SERCOM3 RX SERCOM3 RX Trigger
0x08 SERCOM3 TX SERCOM3 TX Trigger
0x09 SERCOM4 RX SERCOM4 RX Trigger
0x0A SERCOM4 TX SERCOM4 TX Trigger
0x0B SERCOM5 RX SERCOM5 RX Trigger
0x0C SERCOM5 TX SERCOM5 TX Trigger
0x0D TCC0 OVF TCC0 Overflow Trigger
0x0E TCC0 MC0 TCC0 Match/Compare 0 Trigger
0x0F TCC0 MC1 TCC0 Match/Compare 1 Trigger
0x10 TCC0 MC2 TCC0 Match/Compare 2 Trigger
0x11 TCC0 MC3 TCC0 Match/Compare 3 Trigger
0x12 TCC1 OVF TCC1 Overflow Trigger
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zBit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 6:5 – LVL[1:0]: Channel Arbitration Level
These bits define the arbitration level used for the DMA channel. The available levels are shown in Table 18-9,
where a high level has priority over a low level. For further details on arbitration schemes, refer to “Arbitration” on
page 274.
These bits are not enable-protected.
0x13 TCC1 MC0 TCC1 Match/Compare 0 Trigger
0x14 TCC1 MC1 TCC1 Match/Compare 1 Trigger
0x15 TCC2 OVF TCC2 Overflow Trigger
0x16 TCC2 MC0 TCC2 Match/Compare 0 Trigger
0x17 TCC2 MC1 TCC2 Match/Compare 1 Trigger
0x18 TC3 OVF TC3 Overflow Trigger
0x19 TC3 MC0 TC3 Match/Compare 0 Trigger
0x1A TC3 MC1 TC3 Match/Compare 1 Trigger
0x1B TC4 OVF TC4 Overflow Trigger
0x1C TC4 MC0 TC4 Match/Compare 0 Trigger
0x1D TC4 MC1 TC4 Match/Compare 1 Trigger
0x1E TC5 OVF TC5 Overflow Trigger
0x1F TC5 MC0 TC5 Match/Compare 0 Trigger
0x20 TC5 MC1 TC5 Match/Compare 1 Trigger
0x21 Reserved
0x22 Reserved
0x23 Reserved
0x24 Reserved
0x25 Reserved
0x26 Reserved
0x27 ADC RESRDY ADC Result Ready Trigger
0x28 - 0x2C Reserved
Table 18-8. Peripheral Trigger Source (Continued)
Value Name Description
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Table 18-9. Channel Arbitration Level
zBit 4 – EVOE: Channel Event Output Enable
This bit indicates if the Channel event generation is enabled. The event will be generated for every condition
defined in the descriptor Event Output Selection (BTCTRL.EVOSEL).
0: Channel event generation is disabled.
1: Channel event generation is enabled.
This bit is available only on channels with event output support. Refer to Table 22-6 and Table 22-4 for details.
zBit 3 – EVIE: Channel Event Input Enable
0: Channel event action will not be executed on any incoming event.
1: Channel event action will be executed on any incoming event.
This bit is available only on channels with event input support. Refer to Table 22-6 and Table 22-4 for details.
zBits 2:0 – EVACT[2:0]: Event Input Action
These bits define the event input action, as shown in Table 18-10. The action is executed only if the corresponding
EVIE bit in CHCTRLB register of the channel is set. For details on event actions, refer to “Event Input Actions” on
page 281.
These bits are available only for channels with event input support. Refer to Table 22-6 and Table 22-4 for details.
Table 18-10. Event Input Action
LVL[1:0] Name Description
0x0 LVL0 Channel Priority Level 0
0x1 LVL1 Channel Priority Level 1
0x2 LVL2 Channel Priority Level 2
0x3 LVL3 Channel Priority Level 3
0x4-0x7 Reserved
EVACT[2:0] Name Description
0x0 NOACT No action
0x1 TRIG Transfer and periodic transfer trigger
0x2 CTRIG Conditional transfer trigger
0x3 CBLOCK Conditional block transfer
0x4 SUSPEND Channel suspend operation
0x5 RESUME Channel resume operation
0x6 SSKIP Skip next block suspend action
0x7 Reserved
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18.8.1.20 Channel Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Channel Interrupt Enable Set (CHINTENSET) register.
Name: CHINTENCLR
Offset: 0x4C
Reset: 0x00
Property: Write-Protected
zBits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 2 – SUSP: Channel Suspend Interrupt Enable
0: The Channel Suspend interrupt is disabled.
1: The Channel Suspend interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Channel Suspend Interrupt Enable bit, which disables the Channel Suspend
interrupt.
zBit 1 – TCMPL: Transfer Complete Interrupt Enable
0: The Channel Transfer Complete interrupt is disabled. When block action is set to none, the TCMPL flag will not
be set when a block transfer is completed.
1: The Channel Transfer Complete interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Channel Transfer Complete Interrupt Enable bit, which disables the Channel
Transfer Complete interrupt.
zBit 0 – TERR: Transfer Error Interrupt Enable
0: The Channel Transfer Error interrupt is disabled.
1: The Channel Transfer Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Channel Transfer Error Interrupt Enable bit, which disables the Channel
Transfer Error interrupt.
Bit 76543210
SUSP TCMPL TERR
AccessRRRRRR/WR/WR/W
Reset00000000
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18.8.1.21 Channel Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Channel Interrupt Enable Clear (CHINTENCLR) register.
Name: CHINTENSET
Offset: 0x4D
Reset: 0x00
Property: Write-Protected
zBits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 2 – SUSP: Channel Suspend Interrupt Enable
0: The Channel Suspend interrupt is disabled.
1: The Channel Suspend interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Channel Suspend Interrupt Enable bit, which enables the Channel Suspend
interrupt.
zBit 1 – TCMPL: Transfer Complete Interrupt Enable
0: The Channel Transfer Complete interrupt is disabled.
1: The Channel Transfer Complete interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Channel Transfer Complete Interrupt Enable bit, which enables the Channel
Transfer Complete interrupt.
zBit 0 – TERR: Transfer Error Interrupt Enable
0: The Channel Transfer Error interrupt is disabled.
1: The Channel Transfer Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Channel Transfer Error Interrupt Enable bit, which enables the Channel Trans-
fer Error interrupt.
Bit 76543210
SUSP TCMPL TERR
AccessRRRRRR/WR/WR/W
Reset00000000
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18.8.1.22 Channel Interrupt Flag Status and Clear
Name: CHINTFLAG
Offset: 0x4E
Reset: 0x00
Property: -
zBits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 2 – SUSP: Channel Suspend
This flag is cleared by writing a one to it.
This bit is set when a block transfer with suspend block action is completed, when a software suspend command is
executed, when a suspend event is received or when an invalid descriptor is fetched by the DMA.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Channel Suspend interrupt flag for the corresponding channel.
For details on available software commands, refer to Table 18-6.
For details on available event input actions, refer to Table 18-10.
For details on available block actions, refer to Table 18-14.
zBit 1 – TCMPL: Transfer Complete
This flag is cleared by writing a one to it.
This flag is set when a block transfer is completed and the corresponding interrupt block action is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Complete interrupt flag for the corresponding channel.
zBit 0 – TERR: Transfer Error
This flag is cleared by writing a one to it.
This flag is set when a bus error is detected during a beat transfer or when the DMAC fetches an invalid descriptor.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Error interrupt flag for the corresponding channel.
Bit 76543210
SUSP TCMPL TERR
AccessRRRRRR/WR/WR/W
Reset00000000
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18.8.1.23 Channel Status
Name: CHSTATUS
Offset: 0x4F
Reset: 0x00
Property: -
zBits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 2 – FERR: Fetch Error
This bit is cleared when the software resume command is executed.
This bit is set when an invalid descriptor is fetched.
zBit 1 – BUSY: Channel Busy
This bit is cleared when the channel trigger action is complete, when a bus error is detected or when the channel is
disabled.
This bit is set when the DMA channel starts a DMA transfer.
zBit 0 – PEND: Channel Pending
This bit is cleared when trigger execution defined by channel trigger action settings is started, when a bus error is
detected or when the channel is disabled. For details on trigger action settings, refer to Table 18-7.
This bit is set when a transfer is pending on the DMA channel.
Bit 76543210
FERR BUSY PEND
AccessRRRRRRRR
Reset00000000
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18.8.2 DMAC SRAM Registers
18.8.2.1 Block Transfer Control
The BTCTRL register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Name: BTCTRL
Offset: 0x00
zBits 15:13 – STEPSIZE[2:0]: Address Increment Step Size
These bits select the address increment step size, as shown in Table 18-11. The setting apply to source or desti-
nation address, depending on STEPSEL setting.
Table 18-11. Address Increment Step Size
zBit 12 – STEPSEL: Step Selection
This bit selects if source or destination addresses are using the step size settings, according to Table 18-12.
Table 18-12. Step Selection
zBit 11 – DSTINC: Destination Address Increment Enable
0: The Destination Address Increment is disabled.
1: The Destination Address Increment is enabled.
Writing a zero to this bit will disable the destination address incrementation. The address will be kept fixed during
the data transfer.
Bit 151413121110 9 8
STEPSIZE[2:0] STEPSEL DSTINC SRCINC BEATSIZE[1:0]
Bit 76543210
BLOCKACT[1:0] EVOSEL[1:0] VALID
STEPSIZE[2:0] Name Description
0x0 X1 Next ADDR <- ADDR + BEATSIZE * 1
0x1 X2 Next ADDR <- ADDR + BEATSIZE * 2
0x2 X4 Next ADDR <- ADDR + BEATSIZE * 4
0x3 X8 Next ADDR <- ADDR + BEATSIZE * 8
0x4 X16 Next ADDR <- ADDR + BEATSIZE * 16
0x5 X32 Next ADDR <- ADDR + BEATSIZE * 32
0x6 X64 Next ADDR <- ADDR + BEATSIZE * 64
0x7 X128 Next ADDR <- ADDR + BEATSIZE * 128
STEPSEL Name Description
0x0 DST Step size settings apply to the destination address
0x1 SRC Step size settings apply to the source address
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Writing a one to this bit will enable the destination address incrementation. By default, the destination address is
incremented by 1. If the STEPSEL bit is cleared, flexible step-size settings are available in the STEPSIZE register,
as shown in Table 18-11.
zBit 10 – SRCINC: Source Address Increment Enable
0: The Source Address Increment is disabled.
1: The Source Address Increment is enabled.
Writing a zero to this bit will disable the source address incrementation. The address will be kept fixed during the
data transfer.
Writing a one to this bit will enable the source address incrementation. By default, the source address is incre-
mented by 1. If the STEPSEL bit is set, flexible step-size settings are available in the STEPSIZE register, as
shown in Table 18-11.
zBits 9:8 – BEATSIZE[1:0]: Beat Size
These bits define the size of one beat, as shown in Table 18-13. A beat is the size of one data transfer bus access,
and the setting apply to both read and write accesses.
Table 18-13. Beat Size
zBits 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 4:3 – BLOCKACT[1:0]: Block Action
These bits define what actions the DMAC should take after a block transfer has completed. The available actions
are listed in Table 18-14.
Table 18-14. Block Action
zBits 2:1 – EVOSEL[1:0]: Event Output Selection
These bits define the event output selection, as shown in Table 18-15.
BEATSIZE[1:0] Name Description
0x0 BYTE 8-bit access
0x1 HWORD 16-bit access
0x2 WORD 32-bit access
0x3 Reserved
BLOCKACT[1:0] Name Description
0x0 NOACT No action
0x1 INT Channel in normal operation and block interrupt
0x2 SUSPEND Channel suspend operation is completed
0x3 BOTH Both channel suspend operation and block interrupt
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Table 18-15. Event Output Selection
zBit 0 – VALID: Descriptor Valid
0: The descriptor is not valid.
1: The descriptor is valid.
Writing a zero to this bit in the Descriptor or Write-Back memory will suspend the DMA channel operation when
fetching the corresponding descriptor.
The bit is automatically cleared in the Write-Back memory section when channel is aborted, when an error is
detected during the block transfer, or when the block transfer is completed.
EVOSEL[1:0] Name Description
0x0 DISABLE Event generation disabled
0x1 BLOCK Event strobe when block transfer complete
0x2 Reserved
0x3 BEAT Event strobe when beat transfer complete
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18.8.2.2 Block Transfer Count
The BTCNT register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Name: BTCNT
Offset: 0x02
zBits 15:0 – BTCNT[15:0]: Block Transfer Count
This bit group holds the 16-bit block transfer count.
During a transfer, the internal counter value is decremented by one after each beat transfer. The internal counter is
written to the corresponding write-back memory section for the DMA channel when the DMA channel loses priority,
is suspended or gets disabled. The DMA channel can be disabled by a complete transfer, a transfer error or by
software.
Bit 151413121110 9 8
BTCNT[15:8]
Bit 76543210
BTCNT[7:0]
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18.8.2.3 Transfer Source Address
The SRCADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Name: SRCADDR
Offset: 0x04
zBits 31:0 – SRCADDR[31:0]: Transfer Source Address
This bit group holds the source address corresponding to the last beat transfer address in the block transfer.
Bit 3130292827262524
SRCADDR[31:24]
Bit 2322212019181716
SRCADDR[23:16]
Bit 151413121110 9 8
SRCADDR[15:8]
Bit 76543210
SRCADDR[7:0]
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18.8.2.4 Transfer Destination Address
The DSTADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Name: DSTADDR
Offset: 0x08
zBits 31:0 – DSTADDR[31:0]: Transfer Destination Address
This bit group holds the destination address corresponding to the last beat transfer address in the block transfer.
Bit 3130292827262524
DSTADDR[31:24]
Bit 2322212019181716
DSTADDR[23:16]
Bit 151413121110 9 8
DSTADDR[15:8]
Bit 76543210
DSTADDR[7:0]
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18.8.2.5 Next Descriptor Address
The DESCADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Name: DESCADDR
Offset: 0x0C
zBits 31:0 – DESCADDR[31:0]: Next Descriptor Address
This bit group holds the SRAM address of the next descriptor. The value must be 128-bit aligned. If the value of
this SRAM register is 0x00000000, the transaction will be terminated when the DMAC tries to load the next trans-
fer descriptor.
Bit 3130292827262524
DESCADDR[31:24]
Bit 2322212019181716
DESCADDR[23:16]
Bit 151413121110 9 8
DESCADDR[15:8]
Bit 76543210
DESCADDR[7:0]
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19. EIC – External Interrupt Controller
19.1 Overview
The External Interrupt Controller (EIC) allows external pins to be configured as interrupt lines. Each interrupt line can be
individually masked and can generate an interrupt on rising, falling or both edges, or on high or low levels. Each external
pin has a configurable filter to remove spikes. Each external pin can also be configured to be asynchronous in order to
wake up the device from sleep modes where all clocks have been disabled. External pins can also generate an event.
A separate non-maskable interrupt (NMI) is also supported. It has properties similar to the other external interrupts, but is
connected to the NMI request of the CPU, enabling it to interrupt any other interrupt mode.
19.2 Features
z15 external pins, plus one non-maskable pin
zDedicated interrupt line for each pin
zIndividually maskable interrupt lines
zInterrupt on rising, falling or both edges
zInterrupt on high or low levels
zAsynchronous interrupts for sleep modes without clock
zFiltering of external pins
zEvent generation
zConfigurable wake-up for sleep modes
19.3 Block Diagram
Figure 19-1. EIC Block Diagram
Fil
ter Ed
g
e
/
Level
Detection
I
nterru
pt
Wak
e
E
vent
FILTENx
EXTINTx
intre
q_
extint
[
x
]
inwake
_
extint
[
x
]
e
vt
_
extint
[
x
]
Fil
t
e
rEdge/Level
De
t
ec
t
io
n
I
nterrup
t
W
a
k
e
N
MIFILTEN NMI
S
EN
S
E[2:0]
NMI
intre
q_
nm
i
inwake_nmi
SENSEx
[
2:0
]
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19.4 Signal Description
Refer to “I/O Multiplexing and Considerations” on page 12 for details on the pin mapping for this peripheral. One signal
can be mapped on several pins.
19.5 Product Dependencies
In order to use this EIC, other parts of the system must be configured correctly, as described below.
19.5.1 I/O Lines
Using the EIC’s I/O lines requires the I/O pins to be configured. Refer to “PORT” on page 373 for details.
19.5.2 Power Management
All interrupts are available in all sleep modes, but the EIC can be configured to automatically mask some interrupts in
order to prevent device wake-up.
The EIC will continue to operate in any sleep mode where the selected source clock is running. The EIC’s interrupts can
be used to wake up the device from sleep modes. Events connected to the Event System can trigger other operations in
the system without exiting sleep modes. Refer to “PM – Power Manager” on page 112 for details on the different sleep
modes.
19.5.3 Clocks
The EIC bus clock (CLK_EIC_APB) can be enabled and disabled in the Power Manager, and the default state of
CLK_EIC_APB can be found in the Peripheral Clock Masking section in “PM – Power Manager” on page 112.
A generic clock (GCLK_EIC) is required to clock the peripheral. This clock must be configured and enabled in the
Generic Clock Controller before using the peripheral. Refer to “GCLK – Generic Clock Controller” on page 90 for details.
This generic clock is asynchronous to the user interface clock (CLK_EIC_APB). Due to this asynchronicity, writes to
certain registers will require synchronization between the clock domains. Refer to “Synchronization” on page 336 for
further details.
19.5.4 DMA
Not applicable.
19.5.5 Interrupts
There are two interrupt request lines, one for the external interrupts (EXTINT) and one for non-maskable interrupt (NMI).
The EXTINT interrupt request line is connected to the interrupt controller. Using the EIC interrupt requires the interrupt
controller to be configured first. Refer to “Nested Vector Interrupt Controller” on page 29 for details.
The NMI interrupt request line is also connected to the interrupt controller, but does not require the interrupt to be
configured.
19.5.6 Events
The events are connected to the Event System. Using the events requires the Event System to be configured first. The
External Interrupt Controller generates events as pulses.
Refer to “EVSYS – Event System” on page 400 for details.
Signal Name Type Description
EXTINT[15..1] Digital Input External interrupt pin
NMI Digital Input Non-maskable interrupt pin
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19.5.7 Debug Operation
When the CPU is halted in debug mode, the EIC continues normal operation. If the EIC is configured in a way that
requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result
during debugging.
19.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the
following registers:
zInterrupt Flag Status and Clear register (INTFLAG - refer to INTFLAG)
zNon-Maskable Interrupt Flag Status and Clear register (NMIFLAG - refer to NMIFLAG)
Write-protection is denoted by the Write-Protected property in the register description.
Write-protection does not apply to accesses through an external debugger. Refer to “PAC – Peripheral Access
Controller” on page 36 for details.
19.5.9 Analog Connections
Not applicable.
19.6 Functional Description
19.6.1 Principle of Operation
The EIC detects edge or level condition to generate interrupts to the CPU Interrupt Controller or events to the Event
System. Each external interrupt pin (EXTINT) can be filtered using majority vote filtering, clocked by generic clock
GCLK_EIC.
19.6.2 Basic Operation
19.6.2.1 Initialization
The EIC must be initialized in the following order:
1. Enable CLK_EIC_APB
2. If edge detection or filtering is required, GCLK_EIC must be enabled
3. Write the EIC configuration registers (EVCTRL, WAKEUP, CONFIGy)
4. Enable the EIC
When NMI is used, GCLK_EIC must be enabled after EIC configuration (NMICTRL).
19.6.2.2 Enabling, Disabling and Resetting
The EIC is enabled by writing a one to the Enable bit in the Control register (CTRL.ENABLE). The EIC is disabled by
writing a zero to CTRL.ENABLE.
The EIC is reset by writing a one to the Software Reset bit in the Control register (CTRL.SWRST). All registers in the EIC
will be reset to their initial state, and the EIC will be disabled.
Refer to CTRL register for details.
19.6.3 External Pin Processing
Each external pin can be configured to generate an interrupt/event on edge detection (rising, falling or both edges) or
level detection (high or low). The sense of external pins is configured by writing the Interrupt Sense x bits in the Config y
register (CONFIGy.SENSEx). The corresponding interrupt flag (INTFLAG.EXTINT[x]) in the Interrupt Flag Status and
Clear register (INTFLAG) is set when the interrupt condition is met (CONFIGy.SENSEx must be different from zero).
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When the interrupt has been cleared in edge-sensitive mode, INTFLAG.EXTINT[x] will only be set if a new interrupt
condition is met. In level-sensitive mode, when interrupt has been cleared, INTFLAG.EXTINT[x] will be set immediately if
the EXTINTx pin still matches the interrupt condition.
Each external pin can be filtered by a majority vote filtering, clocked by GCLK_EIC. Filtering is enabled if bit Filter Enable
x in the Configuration y register (CONFIGy.FILTENx) is written to one. The majority vote filter samples the external pin
three times with GCLK_EIC and outputs the value when two or more samples are equal.
When an external interrupt is configured for level detection, or if filtering is disabled, detection is made asynchronously,
and GCLK_EIC is not required.
If filtering or edge detection is enabled, the EIC automatically requests the GCLK_EIC to operate (GCLK_EIC must be
enabled in the GCLK module, see “GCLK – Generic Clock Controller” on page 90 for details). If level detection is
enabled, GCLK_EIC is not required, but interrupt and events can still be generated.
Figure 19-2. Interrupt Detections
The detection delay depends on the detection mode.
Table 19-1. Majority Vote Filter
Samples [0, 1, 2] Filter Output
[0,0,0] 0
[0,0,1] 0
[0,1,0] 0
[0,1,1] 1
[1,0,0] 0
[1,0,1] 1
[1,1,0] 1
[1,1,1] 1
G
CLK
_
EI
C
C
LK_EI
C
_APB
E
XTINT
x
i
ntreq_ext
i
nt
[
x
]
(level detection / no filter)
i
ntre
q_
extint
[
x
]
(level detection / filter
)
i
ntre
q_
extint
[
x
]
(
edge detection
/
no
f
ilter
)
i
ntre
q_
extint
[
x
]
(edge detection / filter
)
N
o interru
p
t
N
o interru
p
t
c
lear INTFLAG.EXTINT
[
x
]
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19.6.4 Additional Features
The non-maskable interrupt pin can also generate an interrupt on edge or level detection, but it is configured with the
dedicated NMI Control register (NMICTRL - refer to NMICTRL). To select the sense for NMI, write to the NMISENSE bit
group in the NMI Control register (NMICTRL.NMISENSE). NMI filtering is enabled by writing a one to the NMI Filter
Enable bit (NMICTRL.NMIFILTEN).
NMI detection is enabled only by the NMICTRL.NMISENSE value, and the EIC is not required to be enabled.
After reset, NMI is configured to no detection mode.
When an NMI is detected, the non-maskable interrupt flag in the NMI Flag Status and Clear register is set
(NMIFLAG.NMI). NMI interrupt generation is always enabled, and NMIFLAG.NMI generates an interrupt request when
set.
19.6.5 DMA Operation
Not applicable.
19.6.6 Interrupts
The EIC has the following interrupt sources:
zExternal interrupt pin (EXTINTx). This is an asynchronous interrupt if the corresponding WAKEUP register bit is
set, and can be used to wake-up the device from any sleep mode. See “Basic Operation” on page 333
zNon-maskable interrupt pin (NMI). This is an asynchronous interrupt and can be used to wake-up the device from
any sleep mode. See “Additional Features” on page 335
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when an interrupt condition occurs (NMIFLAG for NMI). Each interrupt, except NMI, can be
individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set register (INTENSET), and
disabled by writing a one to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request
is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains
active until the interrupt flag is cleared, the interrupt is disabled or the EIC is reset. See the INTFLAG register for details
on how to clear interrupt flags. The EIC has one common interrupt request line for all the interrupt sources (except the
NMI interrupt request line). Refer to “Processor And Architecture” on page 28 for details. The user must read the
INTFLAG (or NMIFLAG) register to determine which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to “Processor And
Architecture” on page 28 for details.
19.6.7 Events
The EIC can generate the following output events:
zExternal event from pin (EXTINTx).
Writing a one to an Event Output Control register (EVCTRLEXTINTEO) enables the corresponding output event. Writing
a zero to this bit disables the corresponding output event. Refer to “EVSYS – Event System” on page 400 for details on
configuring the Event System.
Table 19-2. Interrupt Latency
Detection Mode Latency (Worst Case)
Level without filter 3 CLK_EIC_APB periods
Level with filter 4 GCLK_EIC periods + 3 CLK_EIC_APB periods
Edge without filter 4 GCLK_EIC periods + 3 CLK_EIC_APB periods
Edge with filter 6 GCLK_EIC periods + 3 CLK_EIC_APB periods
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When the condition on pin EXTINTx matches the configuration in the CONFIGy register, the corresponding event is
generated, if enabled.
19.6.8 Sleep Mode Operation
In sleep modes, an EXTINTx pin can wake up the device if the corresponding condition matches the configuration in
CONFIGy register. Writing a one to a Wake-Up Enable bit (WAKEUP.WAKEUPEN[x]) enables the wake-up from pin
EXTINTx. Writing a zero to a Wake-Up Enable bit (WAKEUP.WAKEUPEN[x]) disables the wake-up from pin EXTINTx.
Using WAKEUPEN[x]=1 with INTENSET=0 is not recommended.
Figure 19-3. Wake-Up Operation Example (High-Level Detection, No Filter, WAKEUPEN[x]=1)
19.6.9 Synchronization
Due to the asynchronicity between CLK_EIC_APB and GCLK_EIC, some registers must be synchronized when
accessed. A register can require:
zSynchronization when written
zSynchronization when read
zSynchronization when written and read
zNo synchronization
When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All
operations will complete successfully, but the CPU will be stalled, and interrupts will be pending as long as the bus is
stalled.
The following bits need synchronization when written:
zSoftware Reset bit in the Control register (CTRL.SWRST)
zEnable bit in the Control register (CTRL.ENABLE)
No register needs synchronization when written.
No register needs synchronization when read.
CLK
_
EIC
_
APB
EXTINTx
intwake_extint[x]
intre
q_
extint
[
x
]
c
lear INTFLAG.EXTINT
[
x
]
r
eturn to slee
p
mode
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19.7 Register Summary
Table 19-3. Register Summary
Offset Name
Bit
Pos.
0x00 CTRL 7:0 ENABLE SWRST
0x01 STATUS 7:0 SYNCBUSY
0x02 NMICTRL 7:0 NMIFILTEN NMISENSE[2:0]
0x03 NMIFLAG 7:0 NMI
0x04
EVCTRL
7:0 EXTINTEO7 EXTINTEO6 EXTINTEO5 EXTINTEO4 EXTINTEO3 EXTINTEO2 EXTINTEO1 EXTINTEO0
0x05 15:8
EXTINTEO15 EXTINTEO14 EXTINTEO13 EXTINTEO12 EXTINTEO11 EXTINTEO10 EXTINTEO9 EXTINTEO8
0x06 23:16 EXTINTEO17 EXTINTEO16
0x07 31:24
0x08
INTENCLR
7:0 EXTINT7 EXTINT6 EXTINT5 EXTINT4 EXTINT3 EXTINT2 EXTINT1 EXTINT0
0x09 15:8 EXTINT15 EXTINT14 EXTINT13 EXTINT12 EXTINT11 EXTINT10 EXTINT9 EXTINT8
0x0A 23:16 EXTINT17 EXTINT16
0x0B 31:24
0x0C
INTENSET
7:0 EXTINT7 EXTINT6 EXTINT5 EXTINT4 EXTINT3 EXTINT2 EXTINT1 EXTINT0
0x0D 15:8 EXTINT15 EXTINT14 EXTINT13 EXTINT12 EXTINT11 EXTINT10 EXTINT9 EXTINT8
0x0E 23:16 EXTINT17 EXTINT16
0x0F 31:24
0x10
INTFLAG
7:0 EXTINT7 EXTINT6 EXTINT5 EXTINT4 EXTINT3 EXTINT2 EXTINT1 EXTINT0
0x11 15:8 EXTINT15 EXTINT14 EXTINT13 EXTINT12 EXTINT11 EXTINT10 EXTINT9 EXTINT8
0x12 23:16 EXTINT17 EXTINT16
0x13 31:24
0x14
WAKEUP
7:0 WAKEUPEN7 WAKEUPEN6 WAKEUPEN5 WAKEUPEN4 WAKEUPEN3 WAKEUPEN2 WAKEUPEN1 WAKEUPEN0
0x15 15:8
WAKEUPEN15 WAKEUPEN14 WAKEUPEN13 WAKEUPEN12 WAKEUPEN11 WAKEUPEN10 WAKEUPEN9 WAKEUPEN8
0x16 23:16 WAKEUPEN17 WAKEUPEN16
0x17 31:24
0x18
CONFIG0
7:0 FILTEN1 SENSE1[2:0] FILTEN0 SENSE0[2:0]
0x19 15:8 FILTEN3 SENSE3[2:0] FILTEN2 SENSE2[2:0]
0x1A 23:16 FILTEN5 SENSE5[2:0] FILTEN4 SENSE4[2:0]
0x1B 31:24 FILTEN7 SENSE7[2:0] FILTEN6 SENSE6[2:0]
0x1C
CONFIG1
7:0 FILTEN9 SENSE9[2:0] FILTEN8 SENSE8[2:0]
0x1D 15:8 FILTEN11 SENSE11[2:0] FILTEN10 SENSE10[2:0]
0x1E 23:16 FILTEN13 SENSE13[2:0] FILTEN12 SENSE12[2:0]
0x1F 31:24 FILTEN15 SENSE15[2:0] FILTEN14 SENSE14[2:0]
0x20
CONFIG2
7:0 FILTEN25 SENSE25[2:0] FILTEN24 SENSE24[2:0]
0x21 15:8 FILTEN27 SENSE27[2:0] FILTEN26 SENSE26[2:0]
0x22 23:16 FILTEN29 SENSE29[2:0] FILTEN28 SENSE28[2:0]
0x23 31:24 FILTEN31 SENSE31[2:0] FILTEN30 SENSE30[2:0]
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19.8 Register Description
Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters
and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by
the Write-protected property in each individual register description. Refer to “Register Access Protection” on page 333 for
details.
Some registers require synchronization when read and/or written. Synchronization is denoted by the Synchronized
property in each individual register description. Refer to “Synchronization” on page 336 for details.
Some registers are enable-protected, meaning they can be written only when the EIC is disabled. Enable-protection is
denoted by the Enabled-Protected property in each individual register description.
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19.8.1 Control
Name: CTRL
Offset: 0x00
Reset: 0x00
Property: Write-Protected, Write-Synchronized
zBits 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 1 – ENABLE: Enable
0: The EIC is disabled.
1: The EIC is enabled.
Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/disabled. The
value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete.
zBit 0 – SWRST: Software Reset
0: There is no ongoing reset operation.
1: The reset operation is ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the EIC to their initial state, and the EIC will be disabled.
Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write opera-
tion will be discarded.
Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete. CTRL.SWRST and
STATUS.SYNCBUSY will both be cleared when the reset is complete.
Bit 76543210
ENABLE SWRST
AccessRRRRRRR/WR/W
Reset00000000
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19.8.2 Status
Name: STATUS
Offset: 0x01
Reset: 0x00
Property: -
zBit 7 – SYNCBUSY: Synchronization Busy
This bit is cleared when the synchronization of registers between the clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
zBits 6:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit 76543210
SYNCBUSY
AccessRRRRRRRR
Reset00000000
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19.8.3 Non-Maskable Interrupt Control
Name: NMICTRL
Offset: 0x02
Reset: 0x00
Property: Write-Protected
zBits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 3 – NMIFILTEN: Non-Maskable Interrupt Filter Enable
0: NMI filter is disabled.
1: NMI filter is enabled.
zBits 2:0 – NMISENSE[2:0]: Non-Maskable Interrupt Sense
These bits define on which edge or level the NMI triggers.
Table 19-4. Non-Maskable Interrupt Sense
Bit 76543210
NMIFILTEN NMISENSE[2:0]
AccessRRRRR/WR/WR/WR/W
Reset00000000
NMISENSE[2:0] Name Description
0x0 NONE No detection
0x1 RISE Rising-edge detection
0x2 FALL Falling-edge detection
0x3 BOTH Both-edges detection
0x4 HIGH High-level detection
0x5 LOW Low-level detection
0x6-0x7 Reserved
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19.8.4 Non-Maskable Interrupt Flag Status and Clear
Name: NMIFLAG
Offset: 0x03
Reset: 0x00
Property: -
zBits 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 0 – NMI: Non-Maskable Interrupt
This flag is cleared by writing a one to it.
This flag is set when the NMI pin matches the NMI sense configuration, and will generate an interrupt request.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the non-maskable interrupt flag.
Bit 76543210
NMI
AccessRRRRRRRR/W
Reset00000000
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19.8.5 Event Control
Name: EVCTRL
Offset: 0x04
Reset: 0x00000000
Property: Write-Protected
zBits 31:18 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 17:0 – EXTINTEOx [x=17..0]: External Interrupt x Event Output Enable
These bits indicate whether the event associated with the EXTINTx pin is enabled or not to generated for every
detection.
0: Event from pin EXTINTx is disabled.
1: Event from pin EXTINTx is enabled.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
EXTINTEO17 EXTINTEO16
AccessRRRRRRR/WR/W
Reset00000000
Bit 151413121110 9 8
EXTINTEO15 EXTINTEO14 EXTINTEO13 EXTINTEO12 EXTINTEO11 EXTINTEO10
EXTINTEO9 EXTINTEO8
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
EXTINTEO7 EXTINTEO6 EXTINTEO5 EXTINTEO4 EXTINTEO3 EXTINTEO2 EXTINTEO1 EXTINTEO0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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19.8.6 Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x08
Reset: 0x00000000
Property: Write-Protected
zBits 31:18 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 17:0 – EXTINTx [x=17..0]: External Interrupt x Enable
0: The external interrupt x is disabled.
1: The external interrupt x is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the External Interrupt x Enable bit, which enables the external interrupt.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
EXTINT17 EXTINT16
AccessRRRRRRR/WR/W
Reset00000000
Bit 151413121110 9 8
EXTINT15 EXTINT14 EXTINT13 EXTINT12 EXTINT11 EXTINT10
EXTINT9 EXTINT8
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
EXTINT7 EXTINT6 EXTINT5 EXTINT4 EXTINT3 EXTINT2 EXTINT1 EXTINT0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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19.8.7 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Name: INTENSET
Offset: 0x0C
Reset: 0x00000000
Property: Write-Protected
zBits 31:18 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 17:0 – EXTINTx [x=17..0]: External Interrupt x Enable
0: The external interrupt x is disabled.
1: The external interrupt x is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the External Interrupt x Enable bit, which enables the external interrupt.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
EXTINT17 EXTINT16
AccessRRRRRRR/WR/W
Reset00000000
Bit 151413121110 9 8
EXTINT15 EXTINT14 EXTINT13 EXTINT12 EXTINT11 EXTINT10
EXTINT9 EXTINT8
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
EXTINT7 EXTINT6 EXTINT5 EXTINT4 EXTINT3 EXTINT2 EXTINT1 EXTINT0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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19.8.8 Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x10
Reset: 0x00000000
Property: -
zBits 31:18 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 17:0 – EXTINTx [x=17..0]: External Interrupt x
This flag is cleared by writing a one to it.
This flag is set when EXTINTx pin matches the external interrupt sense configuration and will generate an interrupt
request if INTENCLR/SET.EXTINT[x] is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the External Interrupt x flag.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
EXTINT17 EXTINT16
AccessRRRRRRR/WR/W
Reset00000000
Bit 151413121110 9 8
EXTINT15 EXTINT14 EXTINT13 EXTINT12 EXTINT11 EXTINT10
EXTINT9 EXTINT8
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
EXTINT7 EXTINT6 EXTINT5 EXTINT4 EXTINT3 EXTINT2 EXTINT1 EXTINT0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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19.8.9 Wake-Up Enable
Name: WAKEUP
Offset: 0x14
Reset: 0x00000000
Property: Write-Protected
zBits 31:18 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 17:0 – WAKEUPENx [x=17..0]: External Interrupt x Wake-up Enable
This bit enables or disables wake-up from sleep modes when the EXTINTx pin matches the external interrupt
sense configuration.
0: Wake-up from the EXTINTx pin is disabled.
1: Wake-up from the EXTINTx pin is enabled.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
WAKEUPEN17 WAKEUPEN16
AccessRRRRRRR/WR/W
Reset00000000
Bit 151413121110 9 8
WAKEUPEN15 WAKEUPEN14 WAKEUPEN13 WAKEUPEN12 WAKEUPEN11 WAKEUPEN10
WAKEUPEN9 WAKEUPEN8
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
WAKEUPEN7 WAKEUPEN6 WAKEUPEN5 WAKEUPEN4 WAKEUPEN3 WAKEUPEN2 WAKEUPEN1 WAKEUPEN0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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19.8.10 Configuration n
Name: CONFIGn
Offset: 0x18+n*0x4 [n=0..2]
Reset: 0x00000000
Property: Write-Protected
zBits 31, 27, 23, 19, 15, 11, 7 – FILTENx: Filter 0 Enable
0: Filter is disabled for EXTINT[n*8+x] input.
1: Filter is enabled for EXTINT[n*8+x] input.
zBits 30:28, 26:24, 22:20, 18:16, 14:12, 10:8, 6:4 – SENSEx: Input Sense 0 Configuration
These bits define on which edge or level the interrupt or event for EXTINT[n*8+x] will be generated.
Table 19-5. Input Sense 0 Configuration
Bit 3130292827262524
FILTEN7 SENSE7[2:0] FILTEN6 SENSE6[2:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
FILTEN5 SENSE5[2:0] FILTEN4 SENSE4[2:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
FILTEN3 SENSE3[2:0] FILTEN2 SENSE2[2:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
FILTEN1 SENSE1[2:0] FILTEN0 SENSE0[2:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
SENSE0[2:0] Name Description
0x0 NONE No detection
0x1 RISE Rising-edge detection
0x2 FALL Falling-edge detection
0x3 BOTH Both-edges detection
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0x4 HIGH High-level detection
0x5 LOW Low-level detection
0x6-0x7 Reserved
SENSE0[2:0] Name Description
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20. NVMCTRL – Non-Volatile Memory Controller
20.1 Overview
Non-volatile memory (NVM) is a reprogrammable flash memory that retains program and data storage even with power
off. The NVM Controller (NVMCTRL) connects to the AHB and APB bus interfaces for system access to the NVM block.
The AHB interface is used for reads and writes to the NVM block, while the APB interface is used for commands and
configuration.
20.2 Features
z32-bit AHB interface for reads and writes
zAll NVM sections are memory mapped to the AHB, including calibration and system configuration
z32-bit APB interface for commands and control
zProgrammable wait states for read optimization
z16 regions can be individually protected or unprotected
zAdditional protection for boot loader
zSupports device protection through a security bit
zInterface to Power Manager for power-down of flash blocks in sleep modes
zCan optionally wake up on exit from sleep or on first access
zDirect-mapped cache
20.3 Block Diagram
Figure 20-1. Block Diagram
20.4 Signal Description
Not applicable
Command and
Control
NVM Interface
Cache
NVM Block
NVMCTRL
AHB
APB
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20.5 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described below.
20.5.1 Power Management
The NVMCTRL will continue to operate in any sleep mode where the selected source clock is running. The NVMCTRL’s
interrupts can be used to wake up the device from sleep modes. Refer to “PM – Power Manager” on page 112 for details
on the different sleep modes.
The Power Manager will automatically put the NVM block into a low-power state when entering sleep mode. This is
based on the Control B register (CTRLB - refer to CTRLB) SLEEPPRM bit setting. Read the CTRLB register description
for more details.
20.5.2 Clocks
Two synchronous clocks are used by the NVMCTRL. One is provided by the AHB bus (CLK_NVMCTRL_AHB) and the
other is provided by the APB bus (CLK_NVMCTRL_APB). For higher system frequencies, a programmable number of
wait states can be used to optimize performance. When changing the AHB bus frequency, the user must ensure that the
NVM Controller is configured with the proper number of wait states. Refer to the “Electrical Characteristics” on page 1055
for the exact number of wait states to be used for a particular frequency range.
20.5.3 Interrupts
The NVM Controller interrupt request line is connected to the interrupt controller. Using the NVMCTRL interrupt requires
the interrupt controller to be programmed first.
Refer to “Nested Vector Interrupt Controller” on page 29 for details.
20.5.4 Debug Operation
When an external debugger forces the CPU into debug mode, the peripheral continues normal operation.
Access to the NVM block can be protected by the security bit. In this case, the NVM block will not be accessible. See
“Security Bit” on page 356 for details.
20.5.5 Register Access Protection
All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the
following registers:
zInterrupt Flag Status and Clear register (INTFLAG - refer to INTFLAG)
zStatus register (STATUS - refer to STATUS)
Write-protection is denoted by the Write-Protected property in the register description. Write-protection does not apply for
accesses through an external debugger.
When the CPU is halted in debug mode, all write-protection is automatically disabled. Refer to “PAC – Peripheral Access
Controller” on page 36 for details.
20.5.6 Analog Connections
Not applicable.
20.6 Functional Description
20.6.1 Principle of Operation
The NVM Controller is a slave on the AHB and APB buses. It responds to commands, read requests and write requests,
based on user configuration.
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20.6.2 Basic Operations
20.6.2.1 Initialization
After power up, the NVM Controller goes through a power-up sequence. During this time, access to the NVM Controller
from the AHB bus is halted. Upon power-up completion, the NVM Controller is operational without any need for user
configuration.
20.6.2.2 Enabling, Disabling and Resetting
Not applicable.
20.6.3 Memory Organization
Refer to “Physical Memory Map” on page 24 for memory sizes and addresses for each device.
The NVM is organized into rows, where each row contains four pages, as shown in Figure 20-2. The NVM has a row-
erase granularity, while the write granularity is by page. In other words, a single row erase will erase all four pages in the
row, while four write operations are used to write the complete row.
Figure 20-2. Row Organization
The NVM block contains a calibration and auxiliary space that is memory mapped. Refer to Figure 20-3
for details.
The calibration and auxiliary space contains factory calibration and system configuration information. This space can be
read from the AHB bus in the same way as the main NVM main address space.
In addition, a boot loader section can be allocated at the beginning of the main array, and an EEPROM emulation area
can be allocated at the end of the NVM main address space.
Figure 20-3. NVM Memory Organization
The lower rows in the NVM main address space can be allocated as a boot loader section by using the BOOTPROT
fuses, and the upper rows can be allocated to EEPROM emulation, as shown in Figure 20-4. The boot loader section is
protected by the lock bit(s) corresponding to this address space and by the BOOTPROT[2:0] fuse. The EEPROM rows
Page (n * 4) + 0Row n Page (n * 4) + 1Page (n * 4) + 2Page (n * 4) + 3
Calibration and
Auxillary Space
NVM Main
Address Space
NVM Base Address + 0x00800000
NVM Base Address + NVM Size
NVM Base Address
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can be written regardless of the region lock status. The number of rows protected by BOOTPROT and the number of
rows allocated to EEPROM emulation are given in Table 20-2 and Table 20-3, respectively.
Figure 20-4. EEPROM Emulation and Boot Loader Allocation
20.6.4 Region Lock Bits
The NVM block is grouped into 16 equally sized regions. The region size is dependent on the flash memory size, and is
given in the table below. Each region has a dedicated lock bit preventing writing and erasing pages in the region. After
production, all regions will be unlocked.
Table 20-1. Region Size
To lock or unlock a region, the Lock Region and Unlock Region commands are provided. Writing one of these commands
will temporarily lock/unlock the region containing the address loaded in the ADDR register. ADDR can be written by
software, or the automatically loaded value from a write operation can be used. The new setting will stay in effect until the
next reset, or the setting can be changed again using the lock and unlock commands. The current status of the lock can
be determined by reading the LOCK register.
To change the default lock/unlock setting for a region, the user configuration section of the auxiliary space must be
written using the Write Auxiliary Page command. Writing to the auxiliary space will take effect after the next reset.
Therefore, a boot of the device is needed for changes in the lock/unlock setting to take effect. See “Physical Memory
Map” on page 24 for calibration and auxiliary space address mapping.
20.6.5 Command and Data Interface
The NVM Controller is addressable from the APB bus, while the NVM main address space is addressable from the AHB
bus. Read and automatic page write operations are performed by addressing the NVM main address space directly,
NVM Base Address
EEPROM Emulation
allocation
Program
allocation
NVM Base Address + NVM size
BOOT
allocation
NVM Base Address + BOOTPROT size
NVM Base Address + NVM size - EEPROM size
Memory Size [KB] Region Size [KB]
256 16
128 8
64 4
32 2
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while other operations such as manual page writes and row erase must be performed by issuing commands through the
NVM Controller.
To issue a command, the CTRLA.CMD bits must be written along with the CTRLA.CMDEX value. When a command is
issued, INTFLAG.READY will be cleared until the command has completed. Any commands written while
INTFLAG.READY is low will be ignored. Read the CTRLA register description for more details.
The CTRLB register must be used to control the power reduction mode, read wait states and the write mode.
20.6.5.1 NVM Read
Reading from the NVM main address space is performed via the AHB bus by addressing the NVM main address space
or auxiliary address space directly. Read data is available after the configured number of read wait states (CTRLB.RWS)
set in the NVM Controller, has passed.
The number of cycles data are delayed to the AHB bus is determined by the read wait states. Examples of using zero
and one wait states are shown in Figure 20-5.
Figure 20-5. Read Wait State Examples
20.6.5.2 NVM Write
The NVM Controller requires that an erase must be done before programming. The entire NVM main address space can
be erased by a debugger Chip Erase command. Alternatively, rows can be individually erased by the Erase Row
command.
After programming, the region that the page resides in can be locked to prevent spurious write or erase sequences.
Locking is performed on a per-region basis, and so locking a region locks all pages inside the region.
Data to be written to the NVM block are first written and stored in an internal buffer called the page buffer. The page
buffer contains the same number of bytes as an NVM page. Writes to the page buffer must be 16 or 32 bits. 8-bit writes
to the page buffer is not allowed, and will cause a system exception.
Writing to the NVM block via the AHB bus is performed by a load operation to the page buffer. For each AHB bus write,
the address is stored in the ADDR register. After the page buffer has been loaded with the required number of bytes, the
page can be written to the addressed location by setting CMD to Write Page and setting the key value to CMDEX. The
LOAD bit in the STATUS register indicates whether the page buffer has been loaded or not. Before writing the page to
memory, the accessed row must be erased.
Automatic page writes are enabled by writing the manual write bit to zero (CTRLB.MANW=0). This will trigger a write
operation to the page addressed by ADDR when the last location of the page is written.
Rd 0 Rd 1 Idle
Data 0 Data 1
1 Wait State
Rd 0 Rd 1 Idle
Data 0 Data 1
0 Wait States
AHB Command
AHB Slave Ready
AH B Slave D ata
AHB Command
AHB Slave Ready
AHB Slave Data
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Because the address is automatically stored in ADDR during the I/O bus write operation, the last given address will be
present in the ADDR register. There is no need to load the ADDR register manually, unless a different page in memory is
to be written.
Procedure for Manual Page Writes (MANW=1)
The row to be written must be erased before the write command is given.
zWrite to the page buffer by addressing the NVM main address space directly
zWrite the page buffer to memory: CMD=Write Page and CMDEX
zThe READY bit in the INTFLAG register will be low while programming is in progress, and access through the AHB
will be stalled
Procedure for Automatic Page Writes (MANW=0)
The row to be written must be erased before the last write to the page buffer is performed.
Note that partially written pages must be written with a manual write.
zWrite to the page buffer by addressing the NVM main address space directly.
zWhen the last location in the page buffer is written, the page is automatically written to NVM main address
space.
zINTFLAG.READY will be zero while programming is in progress and access through the AHB will be stalled.
20.6.5.3 Page Buffer Clear
The page buffer is automatically cleared to all ones after a page write is performed. If a partial page has been written and
it is desired to clear the contents of the page buffer, the Page Buffer Clear command can be used.
20.6.5.4 Erase Row
Before a page can be written, the row that contains the page must be erased. The Erase Row command can be used to
erase the desired row. Erasing the row sets all bits to one. If the row resides in a region that is locked, the erase will not
be performed and the Lock Error bit in the Status register (STATUS.LOCKE) will be set.
Procedure for Erase Row
zWrite the address of the row to erase ADDR. Any address within the row can be used.
zIssue an Erase Row command.
20.6.5.5 Lock and Unlock Region
These commands are used to lock and unlock regions as detailed in section “Region Lock Bits” on page 353.
20.6.5.6 Set and Clear Power Reduction Mode
The NVM Controller and block can be taken in and out of power reduction mode through the set and clear power
reduction mode commands. When the NVM Controller and block are in power reduction mode, the Power Reduction
Mode bit in the Status register (STATUS.PRM) is set.
20.6.6 NVM User Configuration
The NVM user configuration resides in the auxiliary space. See “Physical Memory Map” on page 24 for calibration and
auxiliary space address mapping.
The bootloader resides in the main array starting at offset zero. The allocated boot loader section is protected against
write.
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Table 20-2. Boot Loader Size
The EEPROM bits indicates the Flash size reserved for EEPROM emulation according to the Table 20-3. EEPROM
resides in the upper rows of the NVM main address space and are writable, regardless of the region lock status.
Note: 1. the actual size of the EEPROM depends on the emulation software. For more information see Application Note AT03265
20.6.7 Security Bit
The security bit allows the entire chip to be locked from external access for code security. The security bit can be written
by a dedicated command, Set Security Bit (SSB). Once set, the only way to clear the security bit is through a debugger
Chip Erase command. After issuing the SSB command, the PROGE error bit can be checked. Refer to “DSU – Device
Service Unit” on page 45 for details.
20.6.8 Cache
The NVM Controller cache reduces the device power consumption and improves system performance when wait states
are required. It is a direct-mapped cache that implements 8 lines of 64 bits (i.e., 64 bytes). NVM Controller cache can be
enabled by writing a zero in the CACHEDIS bit in the CTRLB register (CTRLB.CACHEDIS). Cache can be configured to
three different modes using the READMODE bit group in the CTRLB register. Refer to CTRLB register description for
more details. The INVALL command can be issued through the CTRLA register to invalidate all cache lines. Commands
affecting NVM content automatically invalidate cache lines.
BOOTPROT [2:0] Rows Protected by BOOTPROT Boot Loader Size in Bytes
7None 0
6 2 512
5 4 1024
4 8 2048
316 4096
232 8192
164 16384
0128 32768
Table 20-3. Flash size for EEPROM emulation
EEPROM[2:0] Rows Allocated to EEPROM EEPROM Size in Bytes for EEPROM emulation(1)
7None 0
6 1 256
5 2 512
4 4 1024
3 8 2048
216 4096
132 8192
064 16384
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20.7 Register Summary
Table 20-4. Register Summary
Offset Name
Bit
Pos.
0x00
CTRLA
7:0 CMD[6:0]
0x01 15:8 CMDEX[7:0]
0x02 Reserved
0x03 Reserved
0x04
CTRLB
7:0 MANW RWS[3:0]
0x05 15:8 SLEEPPRM[1:0]
0x06 23:16 CACHEDIS READMODE[1:0]
0x07 31:24
0x08
PARAM
7:0 NVMP[7:0]
0x09 15:8 NVMP[15:8]
0x0A 23:16 PSZ[2:0]
0x0B 31:24
0x0C INTENCLR 7:0 ERROR READY
0x0D
...
0x0F
Reserved
0x10 INTENSET 7:0 ERROR READY
0x11
...
0x13
Reserved
0x14 INTFLAG 7:0 ERROR READY
0x15
...
0x17
Reserved
0x18
STATUS
7:0 NVME LOCKE PROGE LOAD PRM
0x19 15:8 SB
0x1A Reserved
0x1B Reserved
0x1C
ADDR
7:0 ADDR[7:0]
0x1D 15:8 ADDR[15:8]
0x1E 23:16 ADDR[21:16]
0x1F 31:24
0x20
LOCK
7:0 LOCK[7:0]
0x21 15:8 LOCK[15:8]
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20.8 Register Description
Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters
and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by
the Write-Protected property in each individual register description. Refer to the “Register Access Protection” on page
351 and the “PAC – Peripheral Access Controller” on page 36 for details.
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20.8.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x0000
Property: Write-Protected
zBits 15:8 – CMDEX[7:0]: Command Execution
This bit group should be written with the key value 0xA5 to enable the command written to CMD to be executed. If
the bit group is written with a different key value, the write is not performed and the PROGE status bit is set.
PROGE is also set if the a previously written command is not complete.
The key value must be written at the same time as CMD. If a command is issued through the APB bus on the
same cycle as an AHB bus access, the AHB bus access will be given priority. The command will then be executed
when the NVM block and the AHB bus are idle.
The READY status must be one when the command is issued.
Bit 0 of the CMDEX bit group will read back as one until the command is issued.
Table 20-5. Command Execution
zBit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 6:0 – CMD[6:0]: Command
These bits define the command to be executed when the CMDEX key is written, as shown in Table 20-6.
Bit 151413121110 9 8
CMDEX[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
CMD[6:0]
Access R R/W R/W R/W R/W R/W R/W R/W
Reset00000000
CMDEX[7:0] Name Description
0x0-0xA4 Reserved
0xA5 KEY Execution Key
0xA6-0xFF Reserved
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Table 20-6. Command
CMD[6:0] Name Description
0x00-0x01 -Reserved
0x02 ER Erase Row - Erases the row addressed by the ADDR
register.
0x03 -Reserved
0x04 WP Write Page - Writes the contents of the page buffer to the
page addressed by the ADDR register.
0x05 EAR
Erase Auxiliary Row - Erases the auxiliary row addressed by
the ADDR register. This command can be given only when
the security bit is not set and only to the user configuration
row.
0x06 WAP
Write Auxiliary Page - Writes the contents of the page buffer
to the page addressed by the ADDR register. This command
can be given only when the security bit is not set and only to
the user configuration row.
0x07-0x09 -Reserved
0x0A SF Security Flow Command
0x0B-0x0E -Reserved
0x0F WL Write lockbits
0x10-0x3F -Reserved
0x40 LR Lock Region - Locks the region containing the address
location in the ADDR register.
0x41 UR Unlock Region - Unlocks the region containing the address
location in the ADDR register.
0x42 SPRM Sets the power reduction mode.
0x43 CPRM Clears the power reduction mode.
0x44 PBC Page Buffer Clear - Clears the page buffer.
0x45 SSB Set Security Bit - Sets the security bit by writing 0x00 to the
first byte in the lockbit row.
0x46 INVALL Invalidates all cache lines.
0x47-0x7F -Reserved
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20.8.2 Control B
Name: CTRLB
Offset: 0x04
Reset: 0x00000080
Property: Write-Protected
zBits 31:19 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 18 – CACHEDIS: Cache Disable
This bit is used to disable the cache.
0: The cache is enabled.
1: The cache is disabled.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
CACHEDIS READMODE[1:0]
AccessRRRRRR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
SLEEPPRM[1:0]
AccessRRRRRRR/WR/W
Reset00000000
Bit 76543210
MANW RWS[3:0]
Access R/W R R R/W R/W R/W R/W R
Reset00000000
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zBits 17:16 – READMODE[1:0]: NVMCTRL Read Mode
Table 20-7. NVMCTRL Read Mode
zBits 15:10 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 9:8 – SLEEPPRM[1:0]: Power Reduction Mode during Sleep
Indicates the power reduction mode during sleep.
Table 20-8. Power Reduction Mode during Sleep
zBit 7 – MANW: Manual Write
0: Writing to the last word in the page buffer will initiate a write operation to the page addressed by the last write
operation. This includes writes to memory and auxiliary rows.
1: Write commands must be issued through the CMD register.
zBits 6:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 4:1 – RWS[3:0]: NVM Read Wait States
These bits give the number of wait states for a read operation. Zero indicates zero wait states, one indicates one
wait state, etc., up to 15 wait states.
This register is initialized to 0 wait states. Software can change this value based on the NVM access time and sys-
tem frequency.
READMODE[1:0] Name Description
0x0 NO_MISS_PENALTY The NVM Controller (cache system) does not insert wait
states on a cache miss. Gives the best system performance.
0x1 LOW_POWER
Reduces power consumption of the cache system, but
inserts a wait state each time there is a cache miss. This
mode may not be relevant if CPU performance is required,
as the application will be stalled and may lead to increase
run time.
0x2 DETERMINISTIC
The cache system ensures that a cache hit or miss takes the
same amount of time, determined by the number of
programmed flash wait states. This mode can be used for
real-time applications that require deterministic execution
timings.
0x3 Reserved
SLEEPPRM[1:0] Name Description
0x0 WAKEONACCESS NVM block enters low-power mode when entering
sleep.NVM block exits low-power mode upon first access.
0x1 WAKEUPINSTANT NVM block enters low-power mode when entering
sleep.NVM block exits low-power mode when exiting sleep.
0x2 Reserved
0x3 DISABLED Auto power reduction disabled.
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zBit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
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20.8.3 NVM Parameter
Name: PARAM
Offset: 0x08
Reset: 0x000XXXXX
Property: -
zBits 31:19 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 18:16 – PSZ[2:0]: Page Size
Indicates the page size. Not all device families will provide all the page sizes indicated in the table.
Table 20-9. Page Size
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
PSZ[2:0]
AccessRRRRRRRR
Reset00000XXX
Bit 151413121110 9 8
NVMP[15:8]
AccessRRRRRRRR
ResetXXXXXXXX
Bit 76543210
NVMP[7:0]
AccessRRRRRRRR
ResetXXXXXXXX
PSZ[2:0] Name Description
0x0 88 bytes
0x1 16 16 bytes
0x2 32 32 bytes
0x3 64 64 bytes
0x4 128 128 bytes
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zBits 15:0 – NVMP[15:0]: NVM Pages
Indicates the number of pages in the NVM main address space.
0x5 256 256 bytes
0x6 512 512 bytes
0x7 1024 1024 bytes
PSZ[2:0] Name Description
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20.8.4 Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x0C
Reset: 0x00
Property: Write-Protected
zBits 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 1 – ERROR: Error Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit clears the ERROR interrupt enable.
This bit will read as the current value of the ERROR interrupt enable.
zBit 0 – READY: NVM Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit clears the READY interrupt enable.
This bit will read as the current value of the READY interrupt enable.
Bit 76543210
ERROR READY
AccessRRRRRRR/WR/W
Reset00000000
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20.8.5 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name: INTENSET
Offset: 0x10
Reset: 0x00
Property: Write-Protected
zBits 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 1 – ERROR: Error Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit sets the ERROR interrupt enable.
This bit will read as the current value of the ERROR interrupt enable.
zBit 0 – READY: NVM Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit sets the READY interrupt enable.
This bit will read as the current value of the READY interrupt enable.
Bit 76543210
ERROR READY
AccessRRRRRRR/WR/W
Reset00000000
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20.8.6 Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x14
Reset: 0x00
Property: -
zBits 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 1 – ERROR: Error
This flag is set on the occurrence of an NVME, LOCKE or PROGE error.
0: No errors have been received since the last clear.
1: At least one error has occurred since the last clear.
This bit can be cleared by writing a one to its bit location.
zBit 0 – READY: NVM Ready
0: The NVM controller is busy programming or erasing.
1: The NVM controller is ready to accept a new command.
Bit 76543210
ERROR READY
AccessRRRRRRR/WR
Reset00000000
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20.8.7 Status
Name: STATUS
Offset: 0x18
Reset: 0x0X00
Property: -
zBits 15:9 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 8 – SB: Security Bit Status
0: The Security bit is inactive.
1: The Security bit is active.
zBits 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 4 – NVME: NVM Error
0: No programming or erase errors have been received from the NVM controller since this bit was last cleared.
1: At least one error has been registered from the NVM Controller since this bit was last cleared.
This bit can be cleared by writing a one to its bit location.
zBit 3 – LOCKE: Lock Error Status
0: No programming of any locked lock region has happened since this bit was last cleared.
1: Programming of at least one locked lock region has happened since this bit was last cleared.
This bit can be cleared by writing a one to its bit location.
zBit 2 – PROGE: Programming Error Status
0: No invalid commands or bad keywords were written in the NVM Command register since this bit was last
cleared.
1: An invalid command and/or a bad keyword was/were written in the NVM Command register since this bit was
last cleared.
This bit can be cleared by writing a one to its bit location.
zBit 1 – LOAD: NVM Page Buffer Active Loading
This bit indicates that the NVM page buffer has been loaded with one or more words. Immediately after an NVM
load has been performed, this flag is set, and it remains set until a page write or a page buffer clear (PBCLR) com-
mand is given.
Bit 151413121110 9 8
SB
AccessRRRRRRRR
Reset0000000X
Bit 76543210
NVME LOCKE PROGE LOAD PRM
Access R R R R/W R/W R/W R/W R
Reset00000000
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This bit can be cleared by writing a one to its bit location.
zBit 0 – PRM: Power Reduction Mode
This bit indicates the current NVM power reduction state. The NVM block can be set in power reduction mode in
two ways: through the command interface or automatically when entering sleep with SLEEPPRM set accordingly.
PRM can be cleared in three ways: through AHB access to the NVM block, through the command interface (SPRM
and CPRM) or when exiting sleep with SLEEPPRM set accordingly.
0: NVM is not in power reduction mode.
1: NVM is in power reduction mode.
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20.8.8 Address
Name: ADDR
Offset: 0x1C
Reset: 0x00000000
Property: Write-Protected
zBits 31:22 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 21:0 – ADDR[21:0]: NVM Address
ADDR drives the hardware (16-bit) address to the NVM when a command is executed using CMDEX. 8-bit
addresses must be shifted one bit to the right before writing to this register.
This register is automatically updated when writing to the page buffer, and can also be manually written. This reg-
ister holds the address offset for the section addressed.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
ADDR[21:16]
Access R R R/W R/W R/W R/W R/W R/W
Reset00000000
Bit 151413121110 9 8
ADDR[15:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
ADDR[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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20.8.9 Lock Section
Name: LOCK
Offset: 0x20
Reset: -
Property: -
zBits 15:0 – LOCK[15:0]: Region Lock Bits
In order to set or clear these bits, the CMD register must be used.
0: The corresponding lock region is locked.
1: The corresponding lock region is not locked.
Bit 151413121110 9 8
LOCK[15:8]
AccessRRRRRRRR
Reset00000000
Bit 76543210
LOCK[7:0]
AccessRRRRRRRR
Reset00000000
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21. PORT
21.1 Overview
The Port (PORT) controls the I/O pins of the microcontroller. The I/O pins are organized in a series of groups, collectively
referred to as a port group, and each group can have up to 32 pins that can be configured and controlled individually or
as a group. Each pin may either be used for general-purpose I/O under direct application control or assigned to an
embedded device peripheral. When used for general-purpose I/O, each pin can be configured as input or output, with
highly configurable driver and pull settings.
All I/O pins have true read-modify-write functionality when used for general-purpose I/O; the direction or the output value
of one or more pins may be changed (set, reset or toggled) without unintentionally changing the state of any other pins in
the same port group via a single, atomic 8-, 16- or 32-bit write.
The PORT is connected to the high-speed bus matrix through an AHB/APB bridge. The Pin Direction, Data Output Value
and Data Input Value registers may also be accessed using the low-latency CPU local bus (IOBUS; ARM® single-cycle
I/O port).
21.2 Features
zSelectable input and output configuration individually for each pin
zSoftware-controlled multiplexing of peripheral functions on I/O pins
zFlexible pin configuration through a dedicated Pin Configuration register
zConfigurable output driver and pull settings:
zTotem-pole (push-pull)
zPull configuration
zConfigurable input buffer and pull settings:
zInternal pull-up or pull-down
zInput sampling criteria
zInput buffer can be disabled if not needed for lower power consumption
zRead-modify-write support for pin configuration, output value and pin direction
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21.3 Block Diagram
Figure 21-1. PORT Block Diagram
21.4 Signal Description
Refer to “I/O Multiplexing and Considerations” on page 12 for details on the pin mapping for this peripheral. One signal
can be mapped on several pins.
21.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
21.5.1 I/O Lines
The I/O lines of the PORT are mapped to pins of the physical device package according to a simple naming scheme.
Each port group of up to 32 pins is assigned a letter identifier, starting with A, that monotonically increases through the
alphabet for each subsequent port group. Within each port group, each pin is assigned a numerical identifier according to
its bit position.
The resulting PORT pins are mapped as Pxy, where x=A, B, C,… and y=00, 01, …, 31 to uniquely identify each pin in the
device, e.g., PA24, PC03, etc.
Each pin may have one or more peripheral multiplexer settings, which allow the pin to be routed internally to a dedicated
peripheral function. When enabled, the selected peripheral is given control over the output state of the pin, as well as the
ability to read the current physical pin state. Refer to “I/O Multiplexing and Considerations” on page 12 for details.
Device-specific configurations may result in some pins (and the corresponding Pxy pin) not being implemented.
ANALOG
BLOCKS
PERIPHERALS
Digital Controls of Analog Blocks
Analog Pin
Connections
I/O
PINS
Port Line
Interface
IP Line Interface
Peripheral Mux Select
PORT
Control
and
Status
Pin Line
Interface
Signal Name Type Description
Pxy Digital I/O General-purpose I/O pin y
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21.5.2 Power Management
During reset, all PORT lines are configured as inputs with input buffers, output buffers and pull disabled.
If the PORT peripheral is shut down, the latches contained in the I/O block will retain their current configuration, such as
the output value and pull settings. However, the PORT configuration registers and input synchronizers will lose their
contents, and these will not be restored when PORT is powered up again. The user must, therefore, reconfigure the
PORT peripheral at power up to ensure it is in a well-defined state before use.
The PORT will continue to operate in any sleep mode where the selected module source clock is running.
21.5.3 Clocks
The PORT bus clock (CLK_PORT_APB) can be enabled and disabled in the Power Manager, and the default state of
CLK_PORT_APB can be found in the Peripheral Clock Masking section in the “PM – Power Manager” on page 112.
The PORT is fed by two different clocks: a CPU main clock, which allows the CPU to access the PORT through the low-
latency CPU local bus (IOBUS), and an APB clock, which is a divided clock of the CPU main clock and allows the CPU to
access the PORT registers through the high-speed matrix and the AHB/APB bridge.
IOBUS accesses have priority over APB accesses. The latter must insert wait states in the event of concurrent PORT
accesses.
The PORT input synchronizers use the CPU main clock so that the resynchronization delay is minimized with respect to
the APB clock.
21.5.4 DMA
Not applicable.
21.5.5 Interrupts
Not applicable.
21.5.6 Events
Not applicable.
21.5.7 Debug Operation
When the CPU is halted in debug mode, the PORT continues normal operation. If the PORT is configured in a way that
requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result
during debugging.
21.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC).
Write-protection is denoted by the Write-Protected property in the register description.
When the CPU is halted in debug mode, all write-protection is automatically disabled.
Write-protection does not apply for accesses through an external debugger. Refer to “PAC – Peripheral Access
Controller” on page 36 for details.
21.5.9 Analog Connections
Analog functions are connected directly between the analog blocks and the I/O pins using analog buses. However,
selecting an analog peripheral function for a given pin will disable the corresponding digital features of the pin.
21.5.10 CPU Local Bus
The CPU local bus (IOBUS) is an interface that connects the CPU directly to the PORT. It is a single-cycle bus interface,
and does not support wait states. It supports byte, half word and word sizes.
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The CPU accesses the PORT module through the IOBUS when it performs read or write from address 0x60000000. The
PORT register map is equivalent to the one described in the register description section.
This bus is generally used for low latency. The Data Direction (DIR) and Data Output Value (OUT) registers can be read,
written, set, cleared or toggled using this bus, and the Data Input Value (IN) registers can be read.
Since the IOBUS cannot wait for IN register resynchronization, the Control register (CTRL) must be configured to enable
continuous sampling of all pins that will need to be read via the IOBUS to prevent stale data from being read.
21.6 Functional Description
Figure 21-2. Overview of the PORT
21.6.1 Principle of Operation
The I/O pins of the device are controlled by reads and writes of the PORT peripheral registers. For each port pin, a
corresponding bit in the Data Direction (DIR) and Data Output Value (OUT) registers are used to enable that pin as an
output and to define the output state.
The direction of each pin in a port group is configured via the DIR register. If a bit in DIR is written to one, the
corresponding pin is configured as an output pin. If a bit in DIR is written to zero, the corresponding pin is configured as
an input pin.
When the direction is set as output, the corresponding bit in the OUT register is used to set the level of the pin. If bit y of
OUT is written to one, pin y is driven high. If bit y of OUT is written to zero, pin y is driven low.
Additional pin configuration can be set by writing to the Pin Configuration (PINCFG0) registers.
The Data Input Value bit (IN) is used to read the port pin with resynchronization to the PORT clock. By default, these
input synchronizers are clocked only when an input value read is requested in order to reduce power consumption. Input
value can always be read, whether the pin is configured as input or output, except if digital input is disabled by writing a
zero to the INEN bit in the Pin Configuration registers (PINCFGy).
PULLENy
OUTy
DIRy
INENy
PORTx PADy
VDD
INEN
OE
OUT
PULLEN
PADy
Pull
Resistor
PG
NG
Input to Other Modules Analog Input/Output
IN
INy
APB Bus
Synchronizer
PORT
MULTIPLEXER
...
...
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The PORT also allows peripheral functions to be connected to individual I/O pins by writing a one to the corresponding
PMUXEN bit in the PINCFGy registers and by writing the chosen selection to the Peripheral Multiplexing registers
(PMUX0) for that pin. This will override the connection between the PORT and that I/O pin, and connect the selected
peripheral line interface to the pin instead of the PORT line interface.
Each group of up to 32 pins is controlled by a set of registers, as described in Figure 21-3. This set of registers is
duplicated for each group of pins, with increasing base addresses.
Figure 21-3. Overview of the Peripheral Functions Multiplexing
21.6.2 Basic Operation
21.6.2.1 Initialization
After reset, all standard-function device I/O pins are connected to the PORT with outputs tri-stated and input buffers
disabled, even if no clocks are running. Specific pins, such as the ones used for connection to a debugger, may be
configured differently, as required by their special function.
Each I/O pin y can be configured and accessed by reading or writing PORT registers. Because PORT registers are
grouped into sets of registers for each group of up to 32 pins, the base address of the register set for pin y is at byte
address PORT + (y/32) * 0x80. (y%32) will be used as the index within each register of that register set.
To use pin y as an output, configure it as output by writing the (y%32) bit in the DIR register to one. To avoid disturbing
the configuration of other pins in that group, this can also be done by writing the (y%32) bit in the DIRSET register to one.
The desired output value can be set by writing the (y%32) bit to that value in register OUT.
Similarly, writing one to a bit in Data Output Value Set (OUTSET) register will set the corresponding bit in Data Output
Value (OUT) register to one. Writing one to a bit in Data Output Value Clear (OUTCLR) register will set the corresponding
bit in Data Output Value (OUT) register to zero. Writing one to a bit in Data Output Value Toggle (OUTTGL) register will
toggle the corresponding bit in Data Output Value (OUT) register.
To use pin y as an input, configure it as input by writing the (y%32) bit in the DIR register to zero. To avoid disturbing the
configuration of other pins in that group, this can also be done by writing the (y%32) bit in DIRCLR register to one. The
desired input value can be read from the (y%32) bit in register IN as soon as the INEN bit in the Pin Configuration register
(PINCFGy) is written to one. Refer to “I/O Multiplexing and Considerations” on page 12 for details on pin configuration.
Port x bit y PINCFG
Port x bit y
Periph Line 0
PORT x bit y
PMUXEN
Data+Config
Periph Line 1
Periph Line 15
Port x bit y
PMUX[3:0]
Port y PMUX Select
Port y Line Interface
Pin y
Pin y
Peripheral Line Interface
to be muxed to Pin y
Port y Peripheral
Mux Enable
15
1
0
0
1
Line Interface
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By default, the input synchronizer is clocked only when an input read is requested, which will delay the read operation by
two CLK_PORT cycles. To remove that delay, the input synchronizers for each group of eight pins can be configured to
be always active, but this comes at the expense of higher power consumption. This is controlled by writing a one to the
corresponding SAMPLINGn bit group of the CTRL register, where n = (y%32) / 8.
To use pin y as one of the available peripheral functions for that pin, configure it by writing a one to the corresponding
PMUXEN bit of the PINCFGy register. The PINCFGy register for pin y is at byte offset (PINCFG0 + (y%32)).
The peripheral function can be selected by writing to the PMUXO or PMUXE bit group in the PMUXn register. The
PMUXO/PMUXE bit group is at byte offset (PMUX0 + (y%32) / 2), in bits 3:0 if y is even and in bits 7:4 if y is odd.
The chosen peripheral must also be configured and enabled.
21.6.3 I/O Pin Configuration
The Pin Configuration register (PINCFGy) is used for additional I/O pin configuration. A pin can be set in a totem-pole or
pull configuration.
Because pull configuration is done through the Pin Configuration register, all intermediate PORT states during switching
of pin direction and pin values are avoided.
The I/O pin configurations are described further in this chapter, and summarized in Table 21-1.
21.6.3.1 Pin Configurations Summary
Table 21-1. Pin Configurations Summary
21.6.3.2 Input Configuration
Figure 21-4. I/O Configuration - Standard Input
DIR INEN PULLEN OUT Configuration
0 0 0 X Reset or analog I/O; all digital disabled
0 0 1 0 Pull-down; input disabled
0 0 1 1 Pull-up; input disabled
0 1 0 X Input
0 1 1 0 Input with pull-down
0 1 1 1 Input with pull-up
1 0 X X Output; input disabled
1 1 X X Output; input enabled
PULLEN
DIR
OU
T
IN
INEN
PULLEN
I
NEN
DIR
0
1
0
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Figure 21-5. I/O Configuration - Input with Pull
Note that when pull is enabled, the pull value is defined by the OUTx value.
21.6.3.3 Totem-Pole Output
When configured for totem-pole (push-pull) output, the pin is driven low or high according to the corresponding bit setting
in the OUT register. In this configuration, there is no current limitation for sink or source other than what the pin is capable
of. If the pin is configured for input, the pin will float if no external pull is connected. Note, that enabling the output driver
automatically disables pull.
Figure 21-6. I/O Configuration - Totem-Pole Output with Disabled Input
Figure 21-7. I/O Configuration - Totem-Pole Output with Enabled Input
PULLEN
DIR
OU
T
IN
INEN
PULLEN
I
NEN
DIR
11
0
PULLEN
DIR
OU
T
IN
INEN
PULLEN
I
NEN
DIR
0
0
1
PULLEN
DIR
OU
T
IN
INEN
PULLEN
I
NEN
DIR
0
1
1
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Figure 21-8. I/O Configuration - Output with Pull
21.6.3.4 Digital Functionality Disabled
Figure 21-9. I/O Configuration - Reset or Analog I/O: Digital Output, Input and Pull Disabled
PULLEN
DIR
OU
T
IN
INEN
PULLEN
I
NEN
DIR
1
0
0
PULLEN
DIR
OU
T
IN
INEN
PULLEN
I
NEN
DIR
0
0
0
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21.7 Register Summary
The I/O pins are organized in groups with up to 32 pins. Group 0 consists of the PA pins, group 1 the PB pins, etc. Each
group has its own set of registers. For example, the register address offset for the Data Direction (DIR) register for group
0 (PA00 to PA31) is 0x00, while the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80.
Table 21-2. Register Summary
Offset Name
Bit
Pos.
0x00
DIR
7:0 DIR[7:0]
0x01 15:8 DIR[15:8]
0x02 23:16 DIR[23:16]
0x03 31:24 DIR[31:24]
0x04
DIRCLR
7:0 DIRCLR[7:0]
0x05 15:8 DIRCLR[15:8]
0x06 23:16 DIRCLR[23:16]
0x07 31:24 DIRCLR[31:24]
0x08
DIRSET
7:0 DIRSET[7:0]
0x09 15:8 DIRSET[15:8]
0x0A 23:16 DIRSET[23:16]
0x0B 31:24 DIRSET[31:24]
0x0C
DIRTGL
7:0 DIRTGL[7:0]
0x0D 15:8 DIRTGL[15:8]
0x0E 23:16 DIRTGL[23:16]
0x0F 31:24 DIRTGL[31:24]
0x10
OUT
7:0 OUT[7:0]
0x11 15:8 OUT[15:8]
0x12 23:16 OUT[23:16]
0x13 31:24 OUT[31:24]
0x14
OUTCLR
7:0 OUTCLR[7:0]
0x15 15:8 OUTCLR[15:8]
0x16 23:16 OUTCLR[23:16]
0x17 31:24 OUTCLR[31:24]
0x18
OUTSET
7:0 OUTSET[7:0]
0x19 15:8 OUTSET[15:8]
0x1A 23:16 OUTSET[23:16]
0x1B 31:24 OUTSET[31:24]
0x1C
OUTTGL
7:0 OUTTGL[7:0]
0x1D 15:8 OUTTGL[15:8]
0x1E 23:16 OUTTGL[23:16]
0x1F 31:24 OUTTGL[31:24]
0x20
IN
7:0 IN[7:0]
0x21 15:8 IN[15:8]
0x22 23:16 IN[23:16]
0x23 31:24 IN[31:24]
0x24
CTRL
7:0 SAMPLING[7:0]
0x25 15:8 SAMPLING[15:8]
0x26 23:16 SAMPLING[23:16]
0x27 31:24 SAMPLING[31:24]
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0x28
WRCONFIG
7:0 PINMASK[7:0]
0x29 15:8 PINMASK[15:8]
0x2A 23:16 DRVSTR PULLEN INEN PMUXEN
0x2B 31:24 HWSEL WRPINCFG WRPMUX PMUX[3:0]
0x2C
...
0x2F
Reserved
0x30 PMUX0 7:0 PMUXO[3:0] PMUXE[3:0]
0x31 PMUX1 7:0 PMUXO[3:0] PMUXE[3:0]
...
...
...
0x3F PMUX15 7:0 PMUXO[3:0] PMUXE[3:0]
0x40 PINCFG0 7:0 DRVSTR PULLEN INEN PMUXEN
0x41 PINCFG1 7:0 DRVSTR PULLEN INEN PMUXEN
... ... ...
0x5F PINCFG31 7:0 DRVSTR PULLEN INEN PMUXEN
0x60
...
0x7F
Reserved
0x80
...
0x17D
repeated 2 times from DIR
Offset Name
Bit
Pos.
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21.8 Register Description
Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters
and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by
the Write-Protected property in each individual register description. Refer to “Register Access Protection” on page 375
for details.
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21.8.1 Data Direction
Name: DIR
Offset: 0x00+x*0x80 [x=0..2]
Reset: 0x00000000
Property: Write-Protected
zBits 31:0 – DIR[31:0]: Port Data Direction
These bits set the data direction for the individual I/O pins in the PORT group.
0: The corresponding I/O pin in the group is configured as an input.
1: The corresponding I/O pin in the group is configured as an output.
Bit 3130292827262524
DIR[31:24]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
DIR[23:16]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
DIR[15:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
DIR[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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21.8.2 Data Direction Clear
This register allows the user to set one or more I/O pins as an input, without doing a read-modify-write operation.
Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Toggle (DIRTGL) and Data
Direction Set (DIRSET) registers.
Name: DIRCLR
Offset: 0x04+x*0x80 [x=0..2]
Reset: 0x00000000
Property: Write-Protected
zBits 31:0 – DIRCLR[31:0]: Port Data Direction Clear
0: The I/O pin direction is cleared.
1: The I/O pin direction is set.
Writing a zero to a bit has no effect.
Writing a one to a bit will clear the corresponding bit in the DIR register, which configures the I/O pin as an input.
Bit 3130292827262524
DIRCLR[31:24]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
DIRCLR[23:16]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
DIRCLR[15:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
DIRCLR[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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21.8.3 Data Direction Set
This register allows the user to set one or more I/O pins as an output, without doing a read-modify-write operation.
Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Toggle (DIRTGL) and Data
Direction Clear (DIRCLR) registers.
Name: DIRSET
Offset: 0x08+x*0x80 [x=0..2]
Reset: 0x00000000
Property: Write-Protected
zBits 31:0 – DIRSET[31:0]: Port Data Direction Set
0: The I/O pin direction is cleared.
1: The I/O pin direction is set.
Writing a zero to a bit has no effect.
Writing a one to a bit will set the corresponding bit in the DIR register, which configures the I/O pin as an output.
Bit 3130292827262524
DIRSET[31:24]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
DIRSET[23:16]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
DIRSET[15:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
DIRSET[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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21.8.4 Data Direction Toggle
This register allows the user to toggle the direction of one or more I/O pins, without doing a read-modify-write operation.
Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Set (DIRSET) and Data Direction
Clear (DIRCLR) registers.
Name: DIRTGL
Offset: 0x0C+x*0x80 [x=0..2]
Reset: 0x00000000
Property: Write-Protected
zBits 31:0 – DIRTGL[31:0]: Port Data Direction Toggle
0: The I/O pin direction is cleared.
1: The I/O pin direction is set.
Writing a zero to a bit has no effect.
Writing a one to a bit will toggle the corresponding bit in the DIR register, which reverses the direction of the I/O
pin.
Bit 3130292827262524
DIRTGL[31:24]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
DIRTGL[23:16]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
DIRTGL[15:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
DIRTGL[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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21.8.5 Data Output Value
This register sets the data output drive value for the individual I/O pins in the PORT.
Name: OUT
Offset: 0x10+x*0x80 [x=0..2]
Reset: 0x00000000
Property: Write-Protected
zBits 31:0 – OUT[31:0]: Port Data Output Value
These bits set the logical output drive level of I/O pins configured as outputs via the Data Direction register (DIR).
For pins configured as inputs via the Data Direction register (DIR) with pull enabled via the Pull Enable register
(PULLEN), these bits will set the input pull direction.
0: The I/O pin output is driven low, or the input is connected to an internal pull-down.
1: The I/O pin output is driven high, or the input is connected to an internal pull-up.
Bit 3130292827262524
OUT[31:24]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
OUT[23:16]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
OUT[15:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
OUT[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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21.8.6 Data Output Value Clear
This register allows the user to set one or more output I/O pin drive levels low, without doing a read-modify-write
operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Toggle
(OUTTGL) and Data Output Value Set (OUTSET) registers.
Name: OUTCLR
Offset: 0x14+x*0x80 [x=0..2]
Reset: 0x00000000
Property: Write-Protected
zBits 31:0 – OUTCLR[31:0]: Port Data Output Value Clear
0: The I/O pin output is driven low.
1: The I/O pin output is driven high.
Writing a zero to a bit has no effect.
Writing a one to a bit will clear the corresponding bit in the OUT register, which sets the output drive level low for
I/O pins configured as outputs via the Data Direction register (DIR). For pins configured as inputs via the Data
Direction register (DIR) and with pull enabled via the Pull Enable register (PULLEN), these bits will set the input
pull direction to an internal pull-down.
Bit 3130292827262524
OUTCLR[31:24]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
OUTCLR[23:16]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
OUTCLR[15:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
OUTCLR[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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21.8.7 Data Output Value Set
This register allows the user to set one or more output I/O pin drive levels high, without doing a read-modify-write
operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Toggle
(OUTTGL) and Data Output Value Clear (OUTCLR) registers.
Name: OUTSET
Offset: 0x18+x*0x80 [x=0..2]
Reset: 0x00000000
Property: Write-Protected
zBits 31:0 – OUTSET[31:0]: Port Data Output Value Set
0: The I/O pin output is driven low.
1: The I/O pin output is driven high.
Writing a zero to a bit has no effect.
Writing a one to a bit will set the corresponding bit in the OUT register, which sets the output drive level high for I/O
pins configured as outputs via the Data Direction register (DIR). For pins configured as inputs via the Data Direc-
tion register (DIR) and with pull enabled via the Pull Enable register (PULLEN), these bits will set the input pull
direction to an internal pull-up.
Bit 3130292827262524
OUTSET[31:24]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
OUTSET[23:16]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
OUTSET[15:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
OUTSET[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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21.8.8 Data Output Value Toggle
This register allows the user to toggle the drive level of one or more output I/O pins, without doing a read-modify-write
operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Set
(OUTSET) and Data Output Value Clear (OUTCLR) registers.
Name: OUTTGL
Offset: 0x1C+x*0x80 [x=0..2]
Reset: 0x00000000
Property: Write-Protected
zBits 31:0 – OUTTGL[31:0]: Port Data Output Value Toggle
0: The I/O pin output is driven low.
1: The I/O pin output is driven high.
Writing a zero to a bit has no effect.
Writing a one to a bit will toggle the corresponding bit in the OUT register, which inverts the output drive level for
I/O pins configured as outputs via the Data Direction register (DIR). For pins configured as inputs via the Data
Direction register (DIR) and with pull enabled via the Pull Enable register (PULLEN), these bits will toggle the input
pull direction.
Bit 3130292827262524
OUTTGL[31:24]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
OUTTGL[23:16]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
OUTTGL[15:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
OUTTGL[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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21.8.9 Data Input Value
Name: IN
Offset: 0x20+x*0x80 [x=0..2]
Reset: 0x00000000
Property: -
zBits 31:0 – IN[31:0]: Port Data Input Value
These bits are cleared when the corresponding I/O pin input sampler detects a logical low level on the input pin.
These bits are set when the corresponding I/O pin input sampler detects a logical high level on the input pin.
Bit 3130292827262524
IN[31:24]
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
IN[23:16]
AccessRRRRRRRR
Reset00000000
Bit 151413121110 9 8
IN[15:8]
AccessRRRRRRRR
Reset00000000
Bit 76543210
IN[7:0]
AccessRRRRRRRR
Reset00000000
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21.8.10 Control
Name: CTRL
Offset: 0x24+x*0x80 [x=0..2]
Reset: 0x00000000
Property: Write-Protected
zBits 31:0 – SAMPLING[31:0]: Input Sampling Mode
Configures the input sampling functionality of the I/O pin input samplers for pins configured as inputs via the Data
Direction register (DIR).
0: The I/O pin input synchronizer is disabled.
1: The I/O pin input synchronizer is enabled.
The input samplers are enabled and disabled in sub-groups of eight. Thus, if any pins within a byte request contin-
uous sampling, all pins in that eight pin sub-group will be continuously sampled.
Bit 3130292827262524
SAMPLING[31:24]
AccessWWWWWWWW
Reset00000000
Bit 2322212019181716
SAMPLING[23:16]
AccessWWWWWWWW
Reset00000000
Bit 151413121110 9 8
SAMPLING[15:8]
AccessWWWWWWWW
Reset00000000
Bit 76543210
SAMPLING[7:0]
AccessWWWWWWWW
Reset00000000
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21.8.11 Write Configuration
This write-only register is used to configure several pins simultaneously with the same configuration and/or peripheral
multiplexing.
In order to avoid the side effect of non-atomic access, 8-bit or 16-bit writes to this register will have no effect. Reading this
register always returns zero.
Name: WRCONFIG
Offset: 0x28+x*0x80 [x=0..2]
Reset: 0x00000000
Property: Write-Protected
zBit 31 – HWSEL: Half-Word Select
This bit selects the half-word field of a 32-pin group to be reconfigured in the atomic write operation.
0: The lower 16 pins of the PORT group will be configured.
1: The upper 16 pins of the PORT group will be configured.
This bit will always read as zero.
zBit 30 – WRPINCFG: Write PINCFG
This bit determines whether the atomic write operation will update the Pin Configuration register (PINCFGy) or not
for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits.
0: The PINCFGy registers of the selected pins will not be updated.
1: The PINCFGy registers of the selected pins will be updated.
Writing a zero to this bit has no effect.
Bit 3130292827262524
HWSEL
WRPINCFG
WRPMUX PMUX[3:0]
AccessWWR WWWWW
Reset00000000
Bit 2322212019181716
DRVSTR PULLEN INEN PMUXEN
Access R W R R R W W W
Reset00000000
Bit 151413121110 9 8
PINMASK[15:8]
AccessWWWWWWWW
Reset00000000
Bit 76543210
PINMASK[7:0]
AccessWWWWWWWW
Reset00000000
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Writing a one to this bit updates the configuration of the selected pins with the written WRCONFIG.DRVSTR,
WRCONFIG.SLEWLIM, WRCONFIG.ODRAIN, WRCONFIG.PULLEN, WRCONFIG.INEN, WRCONFIG.PMUXEN
and WRCONFIG.PINMASK values.
This bit will always read as zero.
zBit 29 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 28 – WRPMUX: Write PMUX
This bit determines whether the atomic write operation will update the Peripheral Multiplexing register (PMUXn) or
not for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits.
0: The PMUXn registers of the selected pins will not be updated.
1: The PMUXn registers of the selected pins will be updated.
Writing a zero to this bit has no effect.
Writing a one to this bit updates the pin multiplexer configuration of the selected pins with the written WRCON-
FIG.PMUX value.
This bit will always read as zero.
zBits 27:24 – PMUX[3:0]: Peripheral Multiplexing
These bits determine the new value written to the Peripheral Multiplexing register (PMUXn) for all pins selected by
the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPMUX bit is set.
These bits will always read as zero.
zBit 23 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 22 – DRVSTR: Output Driver Strength Selection
This bit determines the new value written to PINCFGy.DRVSTR for all pins selected by the WRCONFIG.PINMASK
and WRCONFIG.HWSEL bits the WRCONFIG.WRPINCFG bit is set.
This bit will always read as zero.
zBits 21:19 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 18 – PULLEN: Pull Enable
This bit determines the new value written to PINCFGy.PULLEN for all pins selected by the WRCONFIG.PINMASK
and WRCONFIG.HWSEL bits when the WRCONFIG.WRPINCFG bit is set.
This bit will always read as zero.
zBit 17 – INEN: Input Enable
This bit determines the new value written to PINCFGy.DRVSTR for all pins selected by the WRCONFIG.PINMASK
and WRCONFIG.HWSEL bits when the WRCONFIG.WRPINCFG bit is set.
This bit will always read as zero.
zBit 16 – PMUXEN: Peripheral Multiplexer Enable
This bit determines the new value written to PINCFGy.PMUXEN for all pins selected by the WRCONFIG.PIN-
MASK and WRCONFIG.HWSEL bits when the WRCONFIG.WRPINCFG bit is set.
This bit will always read as zero.
zBits 15:0 – PINMASK[15:0]: Pin Mask for Multiple Pin Configuration
These bits select the pins to be configured within the half-word group selected by the WRCONFIG.HWSEL bit.
0: The configuration of the corresponding I/O pin in the half-word group will be left unchanged.
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1: The configuration of the corresponding I/O pin in the half-word pin group will be updated.
These bits will always read as zero.
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21.8.12 Peripheral Multiplexing n
There are up to 16 Peripheral Multiplexing registers in each group, one for every set of two subsequent I/O lines. The n
denotes the number of the set of I/O lines, while the x denotes the number of the group.
Name: PMUXn
Offset: 0x30+n [n=0..15]+x*0x80 [x=0..2]
Reset: 0x00
Property: Write-Protected
zBits 7:4 – PMUXO[3:0]: Peripheral Multiplexing Odd
These bits select the peripheral function for odd-numbered pins (2*n + 1) of a PORT group, if the corresponding
PINCFGy.PMUXEN bit is one.
Not all possible values for this selection may be valid. For more details, refer to “I/O Multiplexing and Consider-
ations” on page 12.
Table 21-3. Peripheral Multiplexing Odd
zBits 3:0 – PMUXE[3:0]: Peripheral Multiplexing Even
These bits select the peripheral function for even-numbered pins (2*n) of a PORT group, if the corresponding
PINCFGy.PMUXEN bit is one.
Not all possible values for this selection may be valid. For more details, refer to “I/O Multiplexing and Consider-
ations” on page 12.
Bit 76543210
PMUXO[3:0] PMUXE[3:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
PMUXO[3:0] Name Description
0x0 APeripheral function A selected
0x1 BPeripheral function B selected
0x2 CPeripheral function C selected
0x3 DPeripheral function D selected
0x4 EPeripheral function E selected
0x5 FPeripheral function F selected
0x6 GPeripheral function G selected
0x7 HPeripheral function H selected
0x8-0xF Reserved
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Table 21-4. Peripheral Multiplexing Even
PMUXE[3:0] Name Description
0x0 APeripheral function A selected
0x1 BPeripheral function B selected
0x2 CPeripheral function C selected
0x3 DPeripheral function D selected
0x4 EPeripheral function E selected
0x5 FPeripheral function F selected
0x6 GPeripheral function G selected
0x7 HPeripheral function H selected
0x8-0xF Reserved
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21.8.13 Pin Configuration n
There are up to 32 Pin Configuration registers in each group, one for each I/O line. The n denotes the number of the I/O
line, while the x denotes the number of the Port group.
Name: PINCFGn
Offset: 0x40+n*0x1 [n=0..31]+x*0x80 [x=0..2]
Reset: 0x00
Property: Write-Protected
zBit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 6 – DRVSTR: Output Driver Strength Selection
This bit controls the output driver strength of an I/O pin configured as an output.
0: Pin drive strength is set to normal drive strength.
1: Pin drive strength is set to stronger drive strength.
zBits 5:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 2 – PULLEN: Pull Enable
This bit enables the internal pull-up or pull-down resistor of an I/O pin configured as an input.
0: Internal pull resistor is disabled, and the input is in a high-impedance configuration.
1: Internal pull resistor is enabled, and the input is driven to a defined logic level in the absence of external input.
zBit 1 – INEN: Input Enable
This bit controls the input buffer of an I/O pin configured as either an input or output.
0: Input buffer for the I/O pin is disabled, and the input value will not be sampled.
1: Input buffer for the I/O pin is enabled, and the input value will be sampled when required.
Writing a zero to this bit disables the input buffer completely, preventing read-back of the physical pin state when
the pin is configured as either an input or output.
zBit 0 – PMUXEN: Peripheral Multiplexer Enable
This bit enables or disables the peripheral multiplexer selection set in the Peripheral Multiplexing register (PMUXn)
to enable or disable alternative peripheral control over an I/O pin direction and output drive value.
0: The peripheral multiplexer selection is disabled, and the PORT registers control the direction and output drive
value.
1: The peripheral multiplexer selection is enabled, and the selected peripheral controls the direction and output
drive value.
Writing a zero to this bit allows the PORT to control the pad direction via the Data Direction register (DIR) and out-
put drive value via the Data Output Value register (OUT). The peripheral multiplexer value in PMUXn is ignored.
Writing a one to this bit enables the peripheral selection in PMUXn to control the pad. In this configuration, the
physical pin state may still be read from the Data Input Value register (IN) if PINCFGy.INEN is set.
Bit 76543210
DRVSTR PULLEN INEN PMUXEN
Access R R/W R R R R/W R/W R/W
Reset00000000
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22. EVSYS – Event System
22.1 Overview
The Event System (EVSYS) allows autonomous, low-latency and configurable communication between peripherals.
Several peripherals can be configured to emit and/or respond to signals known as events. The exact condition to
generate an event, or the action taken upon receiving an event, is specific to each module. Peripherals that respond to
events are called event users. Peripherals that emit events are called event generators. A peripheral can have one or
more event generators and can have one or more event users.
Communication is made without CPU intervention and without consuming system resources such as bus or RAM
bandwidth. This reduces the load on the CPU and other system resources, compared to a traditional interrupt-based
system.
22.2 Features
zSystem for direct peripheral-to-peripheral communication and signaling
z12 configurable event channels, where each channel can:
zBe connected to any event generator
zProvide a pure asynchronous, resynchronized or synchronous path
z71 event generators
z26 event users
zConfigurable edge detector
zPeripherals can be event generators, event users or both
zSleepWalking and interrupt generation while operating in sleep modes
zSoftware event generation
zEach event user can choose which event channel to connect to
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22.3 Block Diagram
Figure 22-1. Event System Block Diagram
22.4 Signal Description
Not applicable.
22.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
22.5.1 I/O Lines
Not applicable.
22.5.2 Power Management
The EVSYS can be used to wake up the CPU from all sleep modes, even if the clock used by the EVSYS channel and
the EVSYS bus clock are disabled. Refer to “PM – Power Manager” on page 112 for details on the different sleep modes.
In all sleep modes where the clock for the EVSYS is stopped, the device can wake up the EVSYS clock.
22.5.3 Clocks
The EVSYS bus clock (CLK_EVSYS_APB) can be enabled and disabled in the Power Manager, and the default state of
CLK_EVSYS_APB can be found in the Peripheral Clock Masking section in “PM – Power Manager” on page 112.
Each EVSYS channel has a dedicated generic clock (GCLK_EVSYS_CHANNELx). These are used for detection and
propagation of events for each channel. These clocks must be configured and enabled in the generic clock controller
before using the EVSYS. Refer to “Enabling a Generic Clock” on page 94 for details.
22.5.4 DMA
Not applicable.
PERIPHERALS
EVSYS
USER
MUX PERIPHERALS
GCLK
GENERATOR
EVENTS
CLOCK REQUESTS
USERS EVENTS
EVENT
CHANNELS
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22.5.5 Interrupts
The interrupt request line is connected to the interrupt controller. Using the EVSYS interrupts requires the interrupt
controller to be configured first. Refer to “Nested Vector Interrupt Controller” on page 29 for details.
22.5.6 Events
Not applicable.
22.5.7 Debug Operation
When the CPU is halted in debug mode, the EVSYS continues normal operation. If the EVSYS is configured in a way
that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may
result during debugging.
22.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the
following register:
zInterrupt Flag Status and Clear register (INTFLAG)
Write-protection is denoted by the Write-Protected property in the register description.
Write-protection does not apply for accesses through an external debugger. Refer to “PAC – Peripheral Access
Controller” on page 36 for details.
22.5.9 Analog Connections
Not applicable.
22.6 Functional Description
22.6.1 Principle of Operation
The EVSYS allows for communication between peripherals via events. Peripherals that respond to events (event users)
are connected to multiplexers which have all event channels as input. Each each event channel can be configured to
route signals from any peripheral emitting events (event generator) to one or more event users.
22.6.2 Basic Operation
22.6.2.1 Initialization
The peripheral that is to act as event generator must be configured to be able to generate events. The peripheral to act
as event user must be configured to handle incoming events.
When this has been done, the event system is ready to be configured. The configuration must follow this order:
1. Configure the event user by performing a single 16-bit write to the User Multiplexer register (USER) with:
1.1. The channel to be connected to a user is written to the Channel bit group (USER.CHANNEL)
1.2. The user to connect the channel is written to the User bit group (USER.USER)
2. Configure the channel by performing a single 32-bit write to the Channel (CHANNEL) register with:
2.1. The channel to be configured is written to the Channel Selection bit group (CHANNEL.CHANNEL)
2.2. The path to be used is written to the Path Selection bit group (CHANNEL.PATH)
2.3. The type of edge detection to use on the channel is written to the Edge Selection bit group
(CHANNEL.EDGSEL)
2.4. The event generator to be used is written to the Event Generator bit group (CHANNEL.EVGEN)
22.6.2.2 Enabling, Disabling and Resetting
The EVSYS is always enabled.
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The EVSYS is reset by writing a one to the Software Reset bit in the Control register (CTRL.SWRST). All registers in the
EVSYS will be reset to their initial state and any ongoing events will be canceled. Refer to the CTRL register for details.
22.6.2.3 Channel Path
There are three different ways to propagate the event provided by an event generator:
zAsynchronous path
zSynchronous path
zResynchronized path
Figure 22-2. Channel
The path is selected by writing to the Path Selection bit group in the Channel register (CHANNEL.PATH).
Asynchronous Path
When using the asynchronous path, the events are propagated from the event generator to the event user with no
intervention from the event system. This means that if the GCLK_EVSYS_CHANNELx for the channel used is inactive,
the event will still be propagated to the user.
Events propagated in the asynchronous path cannot generate any interrupts, and no channel status bits will indicate the
state of the channel. No edge detection is available; this must be handled in the event user.
When the event generator and the event user share the same generic clock, using the asynchronous path will propagate
the event with the least amount of latency.
Synchronous Path
Synchronous path can be used when the event generator and event user share the same generic clock generator and
also if event user supports synchronous path. If event user doesn't support synchronous path, asynchronous path has to
be selected. If they do not share the same generic clock generator, a logic change from the event generator to the event
channel might not be detected in the channel, which means that the event will not be propagated to the event user.
When using the synchronous path, the channel is capable of generating interrupts. The channel status bits in the
Channel Status register (CHSTATUS) are also updated and available for use.
CHANNEL.SWEVT
CHANNEL m
CHANNEL.EVGEN
PERIPHERALS
SLEEPWALKING
DETECTOR
CLOCK_REQUEST_m
CHANNEL.PATH
RESYNC
EDGE
DETECTION
CHANNEL.EDGSEL
CHANNEL_EVT_m
GENERATORS EVENTS
SYNC
ASYNC
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If the Generic Clocks Request bit in the Control register (CTRL.GCLKREQ) is zero, the channel operates in
SleepWalking mode and request the configured generic clock only when an event is to be propagated through the
channel. If CTRL.GCLKREQ is one, the generic clock will always be on for the configured channel.
Resynchronized Path
The resynchronized path should be used when the event generator and the event channel do not share the same generic
clock generator. When the resynchronized path is used, resynchronization of the event from the event generator is done
in the channel.
When the resynchronized path is used, the channel is capable of generating interrupts. The channel status bits in the
Channel Status register (CHSTATUS) are also updated and available for use.
If the Generic Clocks Request bit in the Control register (CTRL.GCLKREQ) is zero, the channel operates in
SleepWalking mode and request the configured generic clock only when an event is to be propagated through the
channel. If CTRL.GCLKREQ is one, the generic clock will always be on for the configured channel.
22.6.2.4 User Multiplexer Setup
Each user multiplexer is dedicated to one event user. A user multiplexer receives all event channel outputs and must be
configured to select one of these channels. The user must always be configured before the channel is configured. A full
list of selectable users can be found in the User Multiplexer register (USER) description. Refer to Table 22-6 for details.
To configure a user multiplexer, the USER register must be written in a single 16-bit write.
It is possible to read out the configuration of a user by first selecting the user by writing to USER.USER using an 8-bit
write and then performing a read of the 16-bit USER register.
Figure 22-3. User MUX
22.6.2.5 Channel Setup
The channel to be used with an event user must be configured with an event generator. The path of the channel should
be configured, and when using a synchronous path or resynchronized path, the edge selection should be configured. All
these configurations are available in the Channel register (CHANNEL).
USER
MUX
PERIPHERAL A PERIPHERAL B
USER.CHANNEL
USER_EVT_x USER_EVT_y USER_EVT_z
CHANNEL_EVT_0
CHANNEL_EVT_1
CHANNEL_EVT_m
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To configure a channel, the Channel register must be written in a single 32-bit write.
It is possible to read out the configuration of a channel by first selecting the channel by writing to CHANNEL.CHANNEL
using a, 8-bit write, and then performing a read of the CHANNEL register.
Event Generators
The event generator is selected by writing to the Event Generator bit group in the Channel register (CHANNEL.EVGEN).
A full list of selectable generators can be found in the CHANNEL register description. Refer to Table 22-4 for details.
The channels are not connected to any of the event generators (CHANNEL.EVGEN = 0x00) by default.
22.6.2.6 Edge Detection
When synchronous or resynchronized paths are used, edge detection must be used. The event system can perform
edge detection in three different ways:
zGenerate an event only on the rising edge
zGenerate an event only on the falling edge
zGenerate an event on rising and falling edges.
Edge detection is selected by writing to the Edge Selection bit group in the Channel register (CHANNEL.EDGSEL).
If the generator event is a pulse, both edges cannot be selected. Use the rising edge or falling edge detection methods,
depending on the generator event default level.
22.6.2.7 Channel Status
The Channel Status register (CHSTATUS) contains the status of the channels when a synchronous or resynchronized
path is in use. There are two different status bits in CHSTATUS for each of the available channels: The Channel x Busy
bit in the Channel Status register (CHSTATUS.CHBUSYx) is set to one if an event on the corresponding channel x has
not been handled by all event users connected to that channel.
The CHSTATUS.USRRDYx bit is set to one if all event users connected to the corresponding channel x are ready to
handle incoming events on that channel.
22.6.2.8 Software Event
A software event can be initiated on a channel by writing a one to the Software Event bit in the Channel register
(CHANNEL.SWEVT) at the same time as writing the Channel bits (CHANNEL.CHANNEL). This will generate a software
event on the selected channel.
The software event can be used for application debugging, and functions like any event generator. To use the software
event, the event path must be configured to either a synchronous path or resynchronized path (CHANNEL.PATH = 0x0
or 0x1), edge detection must be configured to rising-edge detection (CHANNEL.EDGSEL= 0x1) and the Generic Clock
Request bit must be set to one (CTRL.GCLKREQ=0x1).
22.6.3 Interrupts
The EVSYS has the following interrupt sources:
zOverrun Channel x (OVRx): this is an asynchronous interrupt and can be used to wake-up the device from any
sleep mode.
zEvent Detected Channel x (EVDx): this is an asynchronous interrupt and can be used to wake-up the device from
any sleep mode.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one
to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is
cleared, the interrupt is disabled or the EVSYS is reset.
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See the INTFLAG register for details on how to clear interrupt flags. The EVSYS has one common interrupt request line
for all the interrupt sources. The user must read the INTFLAG register to determine which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated.
Refer to “Nested Vector Interrupt Controller” on page 29 for details.
22.6.3.1 The Overrun Channel x Interrupt
The Overrun Channel x interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.OVRx) is set and the
optional interrupt is generated in the following two cases:
zAt least one of the event users on channel x is not ready when a new event occurs. Event user will not be ready if
that user is disabled or not able to handle the incoming event.
zAn event occurs when the previous event on channel x has not yet been handled by all event users. This can
happen when an user is handling event slowly which means that a new event is generated when previous one is
already pending
INTFLAG.OVRx will be set when using a synchronous or resynchronized path, but not when using an asynchronous
path.
22.6.3.2 The Event Detected Channel x Interrupt
The Event Detected Channel x interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.EVDx) is set when
an event coming from the event generator configured on channel x is detected.
INTFLAG.EVDx will be set when using a synchronous and resynchronized path, but not when using an asynchronous
path.
22.6.4 Sleep Mode Operation
The EVSYS can generate interrupts to wake up the device from any sleep mode.
Some event generators can generate an event when the system clock is stopped. The generic clock
(GCLK_EVSYS_CHANNELx) for this channel will be restarted if the channel uses a synchronized path or a
resynchronized path, without waking the system from sleep. The clock remains active only as long as necessary to
handle the event. After the event has been handled, the clock will be turned off and the system will remain in the original
sleep mode. This is known as SleepWalking. When an asynchronous path is used, there is no need for the clock to be
activated for the event to be propagated to the user.
On a software reset, all registers are set to their reset values and any ongoing events are canceled.
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22.7 Register Summary
Table 22-1. Register Summary
Offset Name
Bit
Pos.
0x00 CTRL 7:0 GCLKREQ SWRST
0x01
...
0x03
Reserved
0x04
CHANNEL
7:0 CHANNEL[3:0]
0x05 15:8 SWEVT
0x06 23:16 EVGEN[6:0]
0x07 31:24 EDGSEL[1:0] PATH[1:0]
0x08
USER
7:0 USER[4:0]
0x09 15:8 CHANNEL[4:0]
0x0A Reserved
0x0B Reserved
0x0C
CHSTATUS
7:0 USRRDY7 USRRDY6 USRRDY5 USRRDY4 USRRDY3 USRRDY2 USRRDY1 USRRDY0
0x0D 15:8 CHBUSY7 CHBUSY6 CHBUSY5 CHBUSY4 CHBUSY3 CHBUSY2 CHBUSY1 CHBUSY0
0x0E 23:16 USRRDY11 USRRDY10 USRRDY9 USRRDY8
0x0F 31:24 CHBUSY11 CHBUSY10 CHBUSY9 CHBUSY8
0x10
INTENCLR
7:0 OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0
0x11 15:8 EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0
0x12 23:16 OVR11 OVR10 OVR9 OVR8
0x13 31:24 EVD11 EVD10 EVD9 EVD8
0x14
INTENSET
7:0 OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0
0x15 15:8 EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0
0x16 23:16 OVR11 OVR10 OVR9 OVR8
0x17 31:24 EVD11 EVD10 EVD9 EVD8
0x18
INTFLAG
7:0 OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0
0x19 15:8 EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0
0x1A 23:16 OVR11 OVR10 OVR9 OVR8
0x1B 31:24 EVD11 EVD10 EVD9 EVD8
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22.8 Register Description
Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters
and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by
the Write-Protected property in each individual register description. Refer to “Register Access Protection” on page 402
and “PAC – Peripheral Access Controller” on page 36 for details.
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22.8.1 Control
Name: CTRL
Offset: 0x00
Reset: 0x00
Property: Write-Protected
zBits 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 4 – GCLKREQ: Generic Clock Requests
This bit is used to determine whether the generic clocks used for the different channels should be on all the time or
only when an event needs the generic clock. Events propagated through asynchronous paths will not need a
generic clock.
0: Generic clock is requested and turned on only if an event is detected.
1: Generic clock for a channel is always on.
zBits 3:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 0 – SWRST: Software Reset
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit resets all registers in the EVSYS to their initial state.
Note: Before applying a Software Reset it is recommended to disable the event generators.
Bit 76543210
GCLKREQ SWRST
AccessRRRR/WRRRW
Reset00000000
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22.8.2 Channel
This register allows the user to configure the channel specified in the CHANNEL bit group. To write to this register, do a
single 32-bit write of all the configuration and channel selection data.
To read from this register, first do an 8-bit write to the CHANNEL.CHANNEL bit group specifying the channel
configuration to be read, and then read the Channel register (CHANNEL).
Name: CHANNEL
Offset: 0x04
Reset: 0x00000000
Property: Write-Protected
zBits 31:28 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 27:26 – EDGSEL[1:0]: Edge Detection Selection
These bits set the type of edge detection to be used on the channel.
These bits must be written to zero when using the asynchronous path.
Bit 3130292827262524
EDGSEL[1:0] PATH[1:0]
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
EVGEN[6:0]
Access R R/W R/W R/W R/W R/W R/W R/W
Reset00000000
Bit 151413121110 9 8
SWEVT
AccessRRRRRRRR/W
Reset00000000
Bit 76543210
CHANNEL[3:0]
AccessRRRRR/WR/WR/WR/W
Reset00000000
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Table 22-2. Edge Detection Selection
zBits 25:24 – PATH[1:0]: Path Selection
These bits are used to choose the path to be used by the selected channel.
The path choice can be limited by the channel source, see Table 22-6.
Table 22-3. Path Selection
zBit 23 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 22:16 – EVGEN[6:0]: Event Generator Selection
These bits are used to choose which event generator to connect to the selected channel.
EDGSEL[1:0] Name Description
0x0 NO_EVT_OUTPUT No event output when using the resynchronized or
synchronous path
0x1 RISING_EDGE
Event detection only on the rising edge of the signal from the
event generator when using the resynchronized or
synchronous path
0x2 FALLING_EDGE
Event detection only on the falling edge of the signal from
the event generator when using the resynchronized or
synchronous path
0x3 BOTH_EDGES
Event detection on rising and falling edges of the signal from
the event generator when using the resynchronized or
synchronous path
PATH[1:0] Name Description
0x0 SYNCHRONOUS Synchronous path
0x1 RESYNCHRONIZED Resynchronized path
0x2 ASYNCHRONOUS Asynchronous path
0x3 Reserved
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Table 22-4. Event Generator Selection
Value Event Generator Description
0x00 NONE No event generator selected
0x01 RTC CMP0 Compare 0 (mode 0 and 1) or Alarm 0 (mode 2)
0x02 RTC CMP1 Compare 1
0x03 RTC OVF Overflow
0x04 RTC PER0 Period 0
0x05 RTC PER1 Period 1
0x06 RTC PER2 Period 2
0x07 RTC PER3 Period 3
0x08 RTC PER4 Period 4
0x09 RTC PER5 Period 5
0x0A RTC PER6 Period 6
0x0B RTC PER7 Period 7
0x0C Reserved
0x0D EIC EXTINT1 External Interrupt 1
0x0E EIC EXTINT2 External Interrupt 2
0x0F EIC EXTINT3 External Interrupt 3
0x10 EIC EXTINT4 External Interrupt 4
0x11 EIC EXTINT5 External Interrupt 5
0x12 EIC EXTINT6 External Interrupt 6
0x13 EIC EXTINT7 External Interrupt 7
0x14 EIC EXTINT8 External Interrupt 8
0x15 EIC EXTINT9 External Interrupt 9
0x16 EIC EXTINT10 External Interrupt 10
0x17 EIC EXTINT11 External Interrupt 11
0x18 EIC EXTINT12 External Interrupt 12
0x19 EIC EXTINT13 External Interrupt 13
0x1A EIC EXTINT14 External Interrupt 14
0x1B EIC EXTINT15 External Interrupt 15
0x1C Reserved
0x1D Reserved
0x1E DMAC CH0 Channel 0
0x1F DMAC CH1 Channel 1
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0x20 DMAC CH2 Channel 2
0x21 DMAC CH3 Channel 3
0x22 TCC0 OVF Overflow
0x23 TCC0 TRG Trig
0x24 TCC0 CNT Counter
0x25 TCC0_MCX0 Match/Capture 0
0x26 TCC0_MCX1 Match/Capture 1
0x27 TCC0_MCX2 Match/Capture 2
0x28 TCC0_MCX3 Match/Capture 3
0x29 TCC1 OVF Overflow
0x2A TCC1 TRG Trig
0x2B TCC1 CNT Counter
0x2C TCC1_MCX0 Match/Capture 0
0x2D TCC1_MCX1 Match/Capture 1
0x2E TCC2 OVF Overflow
0x2F TCC2 TRG Trig
0x30 TCC2 CNT Counter
0x31 TCC2_MCX0 Match/Capture 0
0x32 TCC2_MCX1 Match/Capture 1
0x33 TC3 OVF Overflow/Underflow
0x34 TC3 MC0 Match/Capture 0
0x35 TC3 MC1 Match/Capture 1
0x36 TC4 OVF Overflow/Underflow
0x37 TC4 MC0 Match/Capture 0
0x38 TC4 MC1 Match/Capture 1
0x39 TC5 OVF Overflow/Underflow
0x3A TC5 MC0 Match/Capture 0
0x3B TC5 MC1 Match/Capture 1
0x3C Reserved
0x3D Reserved
0x3E Reserved
0x3F Reserved
0x40 Reserved
Table 22-4. Event Generator Selection (Continued)
Value Event Generator Description
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zBits 15:9 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 8 – SWEVT: Software Event
This bit is used to insert a software event on the channel selected by the CHANNEL.CHANNEL bit group.
This bit has the same behavior similar to an event.
This bit must be written together with CHANNEL.CHANNELusing a 16-bit write.
Writing a zero to this bit has no effect.
Writing a one to this bit will trigger a software event for the corresponding channel.
This bit will always return zero when read.
zBits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 3:0 – CHANNEL[3:0]: Channel Selection
These bits are used to select the channel to be set up or read from.
0x41 Reserved
0x42 ADC RESRDY Result Ready
0x43 ADC WINMON Window Monitor
0x44 AC COMP0 Comparator 0
0x45 AC COMP1 Comparator 1
0x46 AC WIN0 Window 0
0x47 Reserved
0x48 PTC EOCReserved End of Conversion
0x49 PTC
WCOMPReserved Window Comparator
0x4A AC1 COMP0 Comparator 0
0x4B AC1 COMP1 Comparator 1
0x4C AC1 WIN0 Window 0
0x4AD-0x7F Reserved
Table 22-4. Event Generator Selection (Continued)
Value Event Generator Description
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22.8.3 User Multiplexer
This register is used to configure a specified event user. To write to this register, do a single 16-bit write of all the
configuration and event user selection data.
To read from this register, first do an 8-bit write to the USER.USER bit group specifying the event user configuration to be
read, and then read USER.
Name: USER
Offset: 0x08
Reset: 0x0000
Property: Write-Protected
zBits 15:13 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 12:8 – CHANNEL[4:0]: Channel Event Selection
These bits are used to select the channel to connect to the event user.
Note that to select channel n, the value (n+1) must be written to the USER.CHANNEL bit group.
Table 22-5. Channel Event Selection
zBits 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 4:0 – USER[4:0]: User Multiplexer Selection
These bits select the event user to be configured with a channel, or the event user to read the channel value from.
Bit 151413121110 9 8
CHANNEL[4:0]
Access R R R R/W R/W R/W R/W R/W
Reset00000000
Bit 76543210
USER[4:0]
Access R R R R/W R/W R/W R/W R/W
Reset00000000
CHANNEL[4:0] Channel Number
0x0 No Channel Output Selected
0x1-0xC Channel n-1 selected
0xD-0xFF Reserved
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Table 22-6. User Multiplexer Selection
USER[7:0] User Multiplexer Description Path Type
0x00 DMAC CH0 Channel 0 Resynchronized path only
0x01 DMAC CH1 Channel 1 Resynchronized path only
0x02 DMAC CH2 Channel 2 Resynchronized path only
0x03 DMAC CH3 Channel 3 Resynchronized path only
0x04 TCC0 EV0 Asynchronous, synchronous and resynchronized paths
0x05 TCC0 EV1 Asynchronous, synchronous and resynchronized paths
0x06 TCC0 MC0 Match/Capture 0 Asynchronous, synchronous and resynchronized paths
0x07 TCC0 MC1 Match/Capture 1 Asynchronous, synchronous and resynchronized paths
0x08 TCC0 MC2 Match/Capture 2 Asynchronous, synchronous and resynchronized paths
0x09 TCC0 MC3 Match/Capture 3 Asynchronous, synchronous and resynchronized paths
0x0A TCC1 EV0 Asynchronous, synchronous and resynchronized paths
0x0B TCC1 EV1 Asynchronous, synchronous and resynchronized paths
0x0C TCC1 MC0 Match/Capture 0 Asynchronous, synchronous and resynchronized paths
0x0D TCC1 MC1 Match/Capture 1 Asynchronous, synchronous and resynchronized paths
0x0E TCC2 EV0 Asynchronous, synchronous and resynchronized paths
0x0F TCC2 EV1 Asynchronous, synchronous and resynchronized paths
0x10 TCC2 MC0 Match/Capture 0 Asynchronous, synchronous and resynchronized paths
0x11 TCC2 MC1 Match/Capture 1 Asynchronous, synchronous and resynchronized paths
0x12 TC3 Asynchronous, synchronous and resynchronized paths
0x13 TC4 Asynchronous, synchronous and resynchronized paths
0x14 TC5 Asynchronous, synchronous and resynchronized paths
0x15 Reserved Reserved
0x16 Reserved Reserved
0x17 ADC START ADC start conversion Asynchronous path only
0x18 ADC SYNC Flush ADC Asynchronous path only
0x19 AC COMP0 Start comparator 0 Asynchronous path only
0x1A AC COMP1 Start comparator 1 Asynchronous path only
0x1B Reserved Reserved
0x1C PTC
STCONVReserved PTC start conversion Asynchronous path onlyReserved
0x1D AC1 COMP0 Start comparator 0 Asynchronous path only
0x1E AC1 COMP1 Start comparator 1 Asynchronous path only
0x1D-0x1F Reserved Reserved
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22.8.4 Channel Status
Name: CHSTATUS
Offset: 0x0C
Reset: 0x000F00FF
Property: -
zBits 31:28 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 27:24 – CHBUSYx [x=11..8]: Channel x Busy
This bit is cleared when channel x is idle
This bit is set if an event on channel x has not been handled by all event users connected to channel x.
zBits 23:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 19:16 – USRRDYx [x=11..8]: Channel x User Ready
This bit is cleared when at least one of the event users connected to the channel is not ready.
This bit is set when all event users connected to channel x are ready to handle incoming events on channel x.
zBits 15:8 – CHBUSYx [x=7..0]: Channel x Busy
This bit is cleared when channel x is idle
This bit is set if an event on channel x has not been handled by all event users connected to channel x.
Bit 3130292827262524
CHBUSY11 CHBUSY10
CHBUSY9 CHBUSY8
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
USRRDY11 USRRDY10
USRRDY9 USRRDY8
AccessRRRRRRRR
Reset00001111
Bit 151413121110 9 8
CHBUSY7 CHBUSY6 CHBUSY5 CHBUSY4 CHBUSY3 CHBUSY2 CHBUSY1 CHBUSY0
AccessRRRRRRRR
Reset00000000
Bit 76543210
USRRDY7 USRRDY6 USRRDY5 USRRDY4 USRRDY3 USRRDY2 USRRDY1 USRRDY0
AccessRRRRRRRR
Reset11111111
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zBits 7:0 – USRRDYx [x=7..0]: Channel x User Ready
This bit is cleared when at least one of the event users connected to the channel is not ready.
This bit is set when all event users connected to channel x are ready to handle incoming events on channel x.
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22.8.5 Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x10
Reset: 0x00000000
Property: Write-Protected
zBits 31:28 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 27:24 – EVDx [x=11..8]: Channel x Event Detection Interrupt Enable
0: The Event Detected Channel x interrupt is disabled.
1: The Event Detected Channel x interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Event Detected Channel x Interrupt Enable bit, which disables the Event
Detected Channel x interrupt.
zBits 23:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 19:16 – OVRx [x=11..8]: Channel x Overrun Interrupt Enable
0: The Overrun Channel x interrupt is disabled.
Bit 3130292827262524
EVD11 EVD10 EVD9 EVD8
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
OVR11 OVR10 OVR9 OVR8
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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1: The Overrun Channel x interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overrun Channel x Interrupt Enable bit, which disables the Overrun Channel
x interrupt.
zBits 15:8 – EVDx [x=7..0]: Channel x Event Detection Interrupt Enable
0: The Event Detected Channel x interrupt is disabled.
1: The Event Detected Channel x interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Event Detected Channel x Interrupt Enable bit, which disables the Event
Detected Channel x interrupt.
zBits 7:0 – OVRx [x=7..0]: Channel x Overrun Interrupt Enable
0: The Overrun Channel x interrupt is disabled.
1: The Overrun Channel x interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overrun Channel x Interrupt Enable bit, which disables the Overrun Channel
x interrupt.
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22.8.6 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name: INTENSET
Offset: 0x14
Reset: 0x00000000
Property: Write-Protected
zBits 31:28 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 27:24 – EVDx [x=11..8]: Channel x Event Detection Interrupt Enable
0: The Event Detected Channel x interrupt is disabled.
1: The Event Detected Channel x interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Event Detected Channel x Interrupt Enable bit, which enables the Event
Detected Channel x interrupt.
zBits 23:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 19:16 – OVRx [x=11..8]: Channel x Overrun Interrupt Enable
0: The Overrun Channel x interrupt is disabled.
Bit 3130292827262524
EVD11 EVD10 EVD9 EVD8
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
OVR11 OVR10 OVR9 OVR8
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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1: The Overrun Channel x interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overrun Channel x Interrupt Enable bit, which enables the Overrun Channel x
interrupt.
zBits 15:8 – EVDx [x=7..0]: Channel x Event Detection Interrupt Enable
0: The Event Detected Channel x interrupt is disabled.
1: The Event Detected Channel x interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Event Detected Channel x Interrupt Enable bit, which enables the Event
Detected Channel x interrupt.
zBits 7:0 – OVRx [x=7..0]: Channel x Overrun Interrupt Enable
0: The Overrun Channel x interrupt is disabled.
1: The Overrun Channel x interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overrun Channel x Interrupt Enable bit, which enables the Overrun Channel x
interrupt.
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22.8.7 Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x18
Reset: 0x00000000
Property: -
zBits 31:28 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 27:24 – EVDx [x=11..8]: Channel x Event Detection
This flag is set on the next CLK_EVSYS_APB cycle when an event is being propagated through the channel, and
an interrupt request will be generated if INTENCLR/SET.EVDx is one.
When the event channel path is asynchronous, the EVDx interrupt flag will not be set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Event Detected Channel n interrupt flag.
zBits 23:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 19:16 – OVRx [x=11..8]: Channel x Overrun
This flag is set on the next CLK_EVSYS cycle after an overrun channel condition occurs, and an interrupt request
will be generated if INTENCLR/SET.OVRx is one.
When the event channel path is asynchronous, the OVRx interrupt flag will not be set.
Bit 3130292827262524
EVD11 EVD10 EVD9 EVD8
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
OVR11 OVR10 OVR9 OVR8
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overrun Channel x interrupt flag.
zBits 15:8 – EVDx [x=7..0]: Channel x Event Detection
This flag is set on the next CLK_EVSYS_APB cycle when an event is being propagated through the channel, and
an interrupt request will be generated if INTENCLR/SET.EVDx is one.
When the event channel path is asynchronous, the EVDx interrupt flag will not be set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Event Detected Channel n interrupt flag.
zBits 7:0 – OVRx [x=7..0]: Channel x Overrun
This flag is set on the next CLK_EVSYS cycle after an overrun channel condition occurs, and an interrupt request
will be generated if INTENCLR/SET.OVRx is one.
When the event channel path is asynchronous, the OVRx interrupt flag will not be set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overrun Channel x interrupt flag.
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23. SERCOM – Serial Communication Interface
23.1 Overview
The serial communication interface (SERCOM) can be configured to support a number of modes; I2C, SPI, and USART.
Once configured and enabled, all SERCOM resources are dedicated to the selected mode.
The SERCOM serial engine consists of a transmitter and receiver, baud-rate generator and address matching
functionality. It can be configured to use the internal generic clock or an external clock, making operation in all sleep
modes possible.
23.2 Features
zCombined interface configurable as one of the following:
zI2C – Two-wire serial interface
zSMBus™ compatible.
zSPI – Serial peripheral interface
zUSART – Universal synchronous and asynchronous serial receiver and transmitter
zSingle transmit buffer and double receive buffer
zBaud-rate generator
zAddress match/mask logic
zOperational in all sleep modes
zCan be used with DMA
23.3 Block Diagram
Figure 23-1. SERCOM Block Diagram
23.4 Signal Description
See the respective SERCOM mode chapters for details:
z“SERCOM USART – SERCOM Universal Synchronous and Asynchronous Receiver and Transmitter” on page
434
z“SERCOM SPI – SERCOM Serial Peripheral Interface” on page 472
z“SERCOM I2C – SERCOM Inter-Integrated Circuit” on page 505
TX/RX DATA
CONTROL/STATUS
Mode n
SERCOM
BAUD/ADDR
Transmitter
Register Interface
Serial Engine
Receiver
Mode 0
Mode 1
Baud Rate
Generator
Address
Match
Mode Specific
PAD[3:0]
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23.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
23.5.1 I/O Lines
Using the SERCOM I/O lines requires the I/O pins to be configured using port configuration (PORT). Refer to “PORT” on
page 373 for details.
From Figure 23-1 one can see that the SERCOM has four internal pads, PAD[3:0]. The signals from I2C, SPI and USART
are routed through these SERCOM pads via a multiplexer. The configuration of the multiplexer is available from the
different SERCOM modes. Refer to the mode specific chapters for details:
z“SERCOM USART – SERCOM Universal Synchronous and Asynchronous Receiver and Transmitter” on page
434
z“SERCOM SPI – SERCOM Serial Peripheral Interface” on page 472
z“SERCOM I2C – SERCOM Inter-Integrated Circuit” on page 505
23.5.2 Power Management
The SERCOM can operate in any sleep mode.SERCOM interrupts can be used to wake up the device from sleep
modes. Refer to “PM – Power Manager” on page 112 for details on the different sleep modes.
23.5.3 Clocks
The SERCOM bus clock (CLK_SERCOMx_APB) is enabled by default, and can be enabled and disabled in the Power
Manager. Refer to “PM – Power Manager” on page 112 for details.
Two generic clocks are used by the SERCOM: GCLK_SERCOMx_CORE and GCLK_SERCOMx_SLOW. The core clock
(GCLK_SERCOMx_CORE) is required to clock the SERCOM while operating as a master, while the slow clock
(GCLK_SERCOMx_SLOW) is only required for certain functions. See specific mode chapters for details.
These clocks must be configured and enabled in the Generic Clock Controller (GCLK) before using the SERCOM. Refer
to “GCLK – Generic Clock Controller” on page 90 for details.
These generic clocks are asynchronous to the user interface clock (CLK_SERCOMx_APB). Due to this asynchronicity,
writes to certain registers will require synchronization between the clock domains. Refer to “Synchronization” on page
433 for further details.
23.5.4 DMA
The DMA request lines are connected to the DMA controller (DMAC). Using the SERCOM DMA requests, requires the
DMA controller to be configured first. Refer to “DMAC – Direct Memory Access Controller” on page 267 for details.
23.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the SERCOM interrupts requires the Interrupt
Controller to be configured first. Refer to “Nested Vector Interrupt Controller” on page 29 for details.
23.5.6 Events
Not applicable.
23.5.7 Debug Operation
When the CPU is halted in debug mode, the SERCOM continues normal operation. If the SERCOM is configured in a
way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss
may result during debugging. The SERCOM can be forced to halt operation during debugging.
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23.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the
following registers:
zInterrupt Flag Status and Clear register (INTFLAG)
zAddress register (ADDR)
zData register (DATA)
Write-protection is denoted by the Write-Protection property in the register description.
When the CPU is halted in debug mode, all write-protection is automatically disabled. Refer to “PAC – Peripheral Access
Controller” on page 36 for details.
23.5.9 Analog Connections
Not applicable.
23.6 Functional Description
23.6.1 Principle of Operation
The basic structure of the SERCOM serial engine is shown in Figure 23-2. Fields shown in capital letters are
synchronous to the system clock and accessible by the CPU, while fields with lowercase letters can be configured to run
on the GCLK_SERCOMx_CORE clock or an external clock.
Figure 23-2. SERCOM Serial Engine
The transmitter consists of a single write buffer and a shift register. The receiver consists of a two-level receive buffer and
a shift register. The baud-rate generator is capable of running on the GCLK_SERCOMx_CORE clock or an external
clock. Address matching logic is included for SPI and I2C operation.
Transmitter
Baud Rate Generator
= =
Selectable
Internal Clk
(GCLK)
Ext Clk
Receiver
Address Match
baud rate generator
tx shift register
rx shift register
rx bufferstatus
BAUD TX DATA ADDR/ADDRMASK
RX DATASTATUS
1/- /2- /16
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23.6.2 Basic Operation
23.6.2.1 Initialization
The SERCOM must be configured to the desired mode by writing to the Operating Mode bits in the Control A register
(CTRLA.MODE). Refer to Figure 23-1 for details.
Table 23-1. SERCOM Modes
For further initialization information, see the respective SERCOM mode chapters.
23.6.2.2 Enabling, Disabling and Resetting
The SERCOM is enabled by writing a one to the Enable bit in the Control A register (CTRLA.ENABLE). The SERCOM is
disabled by writing a zero to CTRLA.ENABLE.
The SERCOM is reset by writing a one to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers
in the SERCOM, except DBGCTRL, will be reset to their initial state, and the SERCOM will be disabled. Refer to the
CTRLA register descriptions for details.
23.6.2.3 Clock Generation – Baud-Rate Generator
The baud-rate generator, as shown in Figure 23-3, is used for internal clock generation for asynchronous and
synchronous communication. The generated output frequency (fBAUD) is determined by the Baud register (BAUD) setting
and the baud reference frequency (fREF). The baud reference clock is the serial engine clock, and it can be internal or
external.
For asynchronous operation, the /16 (divide-by-16) output is used when transmitting and the /1 (divide-by-1) output is
used when receiving. For synchronous operation the /2 (divide-by-2) output is used. This functionality is automatically
configured, depending on the selected operating mode.
CTRLA.MODE Description
0x0 USART with external clock
0x1 USART with internal clock
0x2 SPI in slave operation
0x3 SPI in master operation
0x4 I2C slave operation
0x5 I2C master operation
0x6-0x7 Reserved
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Figure 23-3. Baud Rate Generator
Table 23-2 contains equations for calculating the baud rate (in bits per second) and for calculating the BAUD register
value for each mode of operation.
For asynchronous operation there are two different modes. Using the arithmetic mode, the BAUD register value is 16 bits
(0 to 65,535). Using the fractional mode, the BAUD register is 13 bits, while the fractional adjustment is 3 bits. In this
mode the BAUD setting must be greater than or equal to 1.
For synchronous mode, the BAUD register value is 8 bits (0 to 255).
Table 23-2. Baud Rate Equations
S – Number of samples per bit. Can be 16, 8, or 3.
The Asynchronous Fractional option is used for auto-baud detection.
Base
Period
Selectable
Internal Clk
(GCLK)
Ext Clk
CTRLA.MODE[0]
0
1
0
1
0
1
0
1
f
ref
Clock
Recovery
Tx Clk
Rx Clk
CTRLA.MODE
/2 /8
/1 /2 /16
Baud Rate Generator
Operating Mode Condition Baud Rate (Bits Per Second) BAUD Register Value Calculation
Asynchronous
Arithmetic
Asynchronous
Fractional
Synchronous
S
f
fREF
BAUD ≤
)536,65/1( BAUD
S
f
fREF
BAUD −=
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
−= f
f
REF
BAUD
SBAUD 1536,65
S
f
fREF
BAUD ≤
))8/(( FPBAUDS
f
fREF
BAUD +
=
8
FP
S
BAUD f
f
BAUD
REF −
×
=
2
f
fREF
BAUD ≤
)1(2 +
=BAUD
f
fREF
BAUD
1
2−= f
f
BAUD
REF
BAUD
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The baud rate error is represented by the following formula:
Asynchronous Arithmetic Mode BAUD Value Selection
The formula given for fBAUD calculates the average frequency over 65,536 fREF cycles. Although the BAUD register can be
set to any value between 0 and 65,536, the values that will change the average frequency of fBAUD over a single frame
are more constrained. The BAUD register values that will affect the average frequency over a single frame lead to an
integer increase in the cycles per frame (CPF)
where
zD represent the data bits per frame
zS represent the sum of start and first stop bits, if present
Table 23-3 shows the BAUD register value versus baud frequency at a serial engine frequency of 48MHz. This assumes
a D value of 8 bits and an S value of 2 bits (10 bits, including start and stop bits).
Table 23-3. BAUD Register Value vs. Baud Frequency
⎟
⎠
⎞
⎜
⎝
⎛
−= RateActualBaud
udRateExpectedBa
Error 1
)( SDCPF f
f
BAUD
REF +=
BAUD Register Value Serial Engine CPF fBAUD at 48MHz Serial Engine Frequency (fREF)
0 – 406 160 3MHz
407 – 808 161 2.981MHz
809 – 1205 162 2.963MHz
...
65206 31775 15.11kHz
65207 31871 15.06kHz
65208 31969 15.01kHz
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23.6.3 Additional Features
23.6.3.1 Address Match and Mask
The SERCOM address match and mask feature is capable of matching one address with a mask, two unique addresses
or a range of addresses, based on the mode selected. The match uses seven or eight bits, depending on the mode.
Address With Mask
An address written to the Address bits in the Address register (ADDR.ADDR) with a mask written to the Address Mask
bits in the Address register (ADDR.ADDRMASK) will yield an address match. All bits that are masked are not included in
the match. Note that setting the ADDR.ADDRMASK to all zeros will match a single unique address, while setting
ADDR.ADDRMASK to all ones will result in all addresses being accepted.
Figure 23-4. Address With Mask
Two Unique Addresses
The two addresses written to ADDR and ADDRMASK will cause a match.
Figure 23-5. Two Unique Addresses
Address Range
The range of addresses between and including ADDR.ADDR and ADDR.ADDRMASK will cause a match. ADDR.ADDR
and ADDR.ADDRMASK can be set to any two addresses, with ADDR.ADDR acting as the upper limit and
ADDR.ADDRMASK acting as the lower limit.
Figure 23-6. Address Range
23.6.4 DMA Operation
Not applicable.
rx shift register
ADDRMASK
ADDR
== Match
ADDRMASK
rx shift register
ADDR
==
Match
==
ADDRMASK rx shift register ADDR
==
Match
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23.6.5 Interrupts
Interrupt sources are mode-specific. See the respective SERCOM mode chapters for details.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one
to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is
cleared, the interrupt is disabled or the SERCOM is reset. See the register description for details on how to clear interrupt
flags.
The SERCOM has one common interrupt request line for all the interrupt sources. The user must read the INTFLAG
register to determine which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to “Nested Vector Interrupt
Controller” on page 29 for details.
23.6.6 Events
Not applicable.
23.6.7 Sleep Mode Operation
The peripheral can operate in any sleep mode where the selected serial clock is running. This clock can be external or
generated by the internal baud-rate generator.
The SERCOM interrupts can be used to wake up the device from sleep modes. Refer to the different SERCOM mode
chapters for details.
23.6.8 Synchronization
Due to the asynchronicity between CLK_SERCOMx_APB and GCLK_SERCOMx_CORE, some registers must be
synchronized when accessed. A register can require:
zSynchronization when written
zSynchronization when read
zSynchronization when written and read
zNo synchronization
When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. The Synchronization
Ready interrupt can be used to signal when synchronization is complete.
If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is
stalled.
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24. SERCOM USART – SERCOM Universal Synchronous and Asynchronous
Receiver and Transmitter
24.1 Overview
The universal synchronous and asynchronous receiver and transmitter (USART) is one of the available modes in the
Serial Communication Interface (SERCOM).
Refer to “SERCOM – Serial Communication Interface” on page 426 for details.
The USART uses the SERCOM transmitter and receiver configured as shown in Figure 24-1. Fields shown in capital
letters are synchronous to the CLK_SERCOMx_APB and accessible by the CPU, while fields with lowercase letters can
be configured to run on the internal generic clock or an external clock.
The transmitter consists of a single write buffer, a shift register and control logic for handling different frame formats. The
write buffer allows continuous data transmission without any delay between frames.
The receiver consists of a two-level receive buffer and a shift register. Status information for the received data is
available for error checking. Data and clock recovery units ensure robust synchronization and noise filtering during
asynchronous data reception.
24.2 Features
zFull-duplex operation
zAsynchronous (with clock reconstruction) or synchronous operation
zInternal or external clock source for asynchronous and synchronous operation
zBaud-rate generator
zSupports serial frames with 5, 6, 7, 8 or 9 data bits and 1 or 2 stop bits
zOdd or even parity generation and parity check
zSelectable LSB- or MSB-first data transfer
zBuffer overflow and frame error detection
zNoise filtering, including false start-bit detection and digital low-pass filter
zCollision detection
zCan operate in all sleep modes
zOperation at speeds up to half the system clock for internally generated clocks
zOperation at speeds up to the system clock for externally generated clocks
zRTS and CTS flow control
zIrDA modulation and demodulation up to 115.2 kbps
zLIN slave support
zAuto-baud and break character detection
zStart-of-frame detection
zCan be used with DMA
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24.3 Block Diagram
Figure 24-1. USART Block Diagram
24.4 Signal Description
Please refer to “I/O Multiplexing and Considerations” on page 12 for details on the pin mapping for this peripheral. One
signal can be mapped on several pins.
24.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
24.5.1 I/O Lines
Using the USART’s I/O lines requires the I/O pins to be configured using port configuration (PORT).
Refer to “PORT” on page 373 for details.
When the SERCOM is used in USART mode, the pins should be configured according to Table 24-1. If the receiver or
transmitter is disabled, these pins can be used for other purposes.
Table 24-1. USART Pin Configuration
TxD
RxD
XCK
rx shift register
TX DATA
tx shift register
rx buffer
RX DATA
status
STATUS
BAUD
baud rate generator
Internal Clk
(GCLK)
/1 - /2 - /16
Signal name
Signal Name Type Description
PAD[3:0] Digital I/O General SERCOM pins
Pin Pin Configuration
TxD Output
RxD Input
XCK Output or input
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The combined configuration of PORT and the Transmit Data Pinout and Receive Data Pinout bit groups (refer to the
Control A register description) will define the physical position of the USART signals in Table 24-1.
24.5.2 Power Management
The USART can continue to operate in any sleep mode where the selected source clock is running. The USART
interrupts can be used to wake up the device from sleep modes. The events can trigger other operations in the system
without exiting sleep modes. Refer to “PM – Power Manager” on page 112 for details on the different sleep modes.
24.5.3 Clocks
The SERCOM bus clock (CLK_SERCOMx_APB, where x represents the specific SERCOM instance number) can be
enabled and disabled in the Power Manager, and the default state of CLK_SERCOMx_APB can be found in the
Peripheral Clock Masking section in “PM – Power Manager” on page 112.
A generic clock (GCLK_SERCOMx_CORE) is required to clock the SERCOMx_CORE. This clock must be configured
and enabled in the Generic Clock Controller before using the SERCOMx_CORE. Refer to “GCLK – Generic Clock
Controller” on page 90 for details.
This generic clock is asynchronous to the bus clock (CLK_SERCOMx_APB). Due to this asynchronicity, writes to certain
registers will require synchronization between the clock domains. Refer to “Synchronization” on page 446 for further
details.
24.5.4 DMA
The DMA request lines are connected to the DMA controller (DMAC). Using the SERCOM DMA requests, requires
the DMA controller to be configured first. Refer to “DMAC – Direct Memory Access Controller” on page 267 for
details..
24.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the USART interrupts requires the Interrupt
Controller to be configured first. Refer to “Nested Vector Interrupt Controller” on page 29 for details.
24.5.6 Events
Not applicable.
24.5.7 Debug Operation
When the CPU is halted in debug mode, the USART continues normal operation. If the USART is configured in a way
that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may
result during debugging. The USART can be forced to halt operation during debugging.
Refer to DBGCTRL for details.
24.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the
following registers:
zInterrupt Flag Status and Clear register (INTFLAG)
zStatus register (STATUS)
zData register (DATA)
Write-protection is denoted by the Write-Protection property in the register description.
When the CPU is halted in debug mode, all write-protection is automatically disabled.
Write-protection does not apply for accesses through an external debugger. Refer to “PAC – Peripheral Access
Controller” on page 36 for details.
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24.5.9 Analog Connections
Not applicable.
24.6 Functional Description
24.6.1 Principle of Operation
The USART uses three communication lines for data transfer:
zRxD for receiving
zTxD for transmitting
zXCK for the transmission clock in synchronous operation
USART data transfer is frame based, where a serial frame consists of:
z1 start bit
z5, 6, 7, 8 or 9 data bits
zMSB or LSB first
zNo, even or odd parity bit
z1 or 2 stop bits
A frame starts with the start bit followed by one character of data bits. If enabled, the parity bit is inserted after the data
bits and before the first stop bit. One frame can be directly followed by a new frame, or the communication line can return
to the idle (high) state. Figure 24-2 illustrates the possible frame formats. Bits inside brackets are optional.
Figure 24-2. Frame Formats
St Start bit; always low
(n) Data bits; 0 to 8
P Parity bit; odd or even
Sp Stop bit; always high
IDLE No transfers on the communication line; always high in this state
24.6.2 Basic Operation
24.6.2.1 Initialization
The following registers are enable-protected, meaning they can only be written when the USART is disabled
(CTRL.ENABLE is zero):
zControl A register (CTRLA), except the Enable (ENABLE) and Software Reset (SWRST) bits
zControl B register (CTRLB), except the Receiver Enable (RXEN) and Transmitter Enable (TXEN) bits
zBaud register (BAUD)
Any writes to these registers when the USART is enabled or is being enabled (CTRL.ENABLE is one) will be discarded.
Writes to these registers) while the peripheral is being disabled will be completed after the disabling is complete.
Before the USART is enabled, it must be configured, as outlined in the following steps:
zUSART mode with external or internal clock must be selected first by writing 0x0 or 0x1 to the Operating Mode bit
group in the Control A register (CTRLA.MODE)
1 2 3 4 [5] [6] [7] [8]0St(IDLE) Sp1 [Sp2] (St/IDLE)[P]
Frame
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zCommunication mode (asynchronous or synchronous) must be selected by writing to the Communication Mode bit
in the Control A register (CTRLA.CMODE)
zSERCOM pad to use for the receiver must be selected by writing to the Receive Data Pinout bit group in the
Control A register (CTRLA.RXPO)
zSERCOM pads to use for the transmitter and external clock must be selected by writing to the Transmit Data
Pinout bit in the Control A register (CTRLA.TXPO)
zCharacter size must be selected by writing to the Character Size bit group in the Control B register
(CTRLB.CHSIZE)
zMSB- or LSB-first data transmission must be selected by writing to the Data Order bit in the Control A register
(CTRLA.DORD)
zWhen parity mode is to be used, even or odd parity must be selected by writing to the Parity Mode bit in the Control
B register (CTRLB.PMODE) and enabled by writing 0x1 to the Frame Format bit group in the Control A register
(CTRLA.FORM)
zNumber of stop bits must be selected by writing to the Stop Bit Mode bit in the Control B register
(CTRLB.SBMODE)
zWhen using an internal clock, the Baud register (BAUD) must be written to generate the desired baud rate
zThe transmitter and receiver can be enabled by writing ones to the Receiver Enable and Transmitter Enable bits in
the Control B register (CTRLB.RXEN and CTRLB.TXEN)
24.6.2.2 Enabling, Disabling and Resetting
The USART is enabled by writing a one to the Enable bit in the Control A register (CTRLA.ENABLE). The USART is
disabled by writing a zero to CTRLA.ENABLE.
The USART is reset by writing a one to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in
the USART, except DBGCTRL, will be reset to their initial state, and the USART will be disabled. Refer to the CTRLA
register for details.
24.6.2.3 Clock Generation and Selection
For both synchronous and asynchronous modes, the clock used for shifting and sampling data can be generated
internally by the SERCOM baud-rate generator or supplied externally through the XCK line. Synchronous mode is
selected by writing a one to the Communication Mode bit in the Control A register (CTRLA.CMODE) and asynchronous
mode is selected by writing a zero to CTRLA.CMODE. The internal clock source is selected by writing 0x1 to the
Operation Mode bit group in the Control A register (CTRLA.MODE) and the external clock source is selected by writing
0x0 to CTRLA.MODE.
The SERCOM baud-rate generator is configured as shown in Figure 24-3. When CTRLA.CMODE is zero, the baud-rate
generator is automatically set to asynchronous mode and the 16-bit Baud register value is used. When CTRLA.CMODE
is one, the baud-rate generator is automatically set to synchronous mode and the eight LSBs of the Baud register are
used. Refer to “Clock Generation – Baud-Rate Generator” on page 429 for details on configuring the baud rate.
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Figure 24-3. Clock Generation
Synchronous Clock Operation
When synchronous mode is used, the CTRLA.MODE bit group controls whether the transmission clock (XCK line) is an
input or output. The dependency between the clock edges and data sampling or data change is the same for internal and
external clocks. Data input on the RxD pin is sampled at the opposite XCK clock edge as data is driven on the TxD pin.
The Clock Polarity bit in the Control A register (CTRLA.CPOL) selects which XCK clock edge is used for RxD sampling
and which is used for TxD change. As shown in Figure 24-4, when CTRLA.CPOL is zero, the data will be changed on the
rising XCK edge and sampled on the falling XCK edge. If CTRLA.CPOL is one, the data will be changed on the falling
edge of XCK and sampled on the rising edge of XCK.
Figure 24-4. Synchronous Mode XCK Timing
When the clock is provided through XCK (CTRLA.MODE is 0x0), the shift registers operate directly on the XCK clock.
This means that XCK is not synchronized with the system clock and, therefore, can operate at frequencies up to the
system frequency.
24.6.2.4 Data Register
The USART Transmit Data register (TxDATA) and USART Receive Data register(RxDATA) share the same I/O address,
referred to as the Data register (DATA). Writing the DATA register will update the Transmit Data register. Reading the
DATA register will return the contents of the Receive Data register.
XCK
Baud Rate Generator
Base
Period /2
/2 /16/1
CTRLA.CMODE
0
1
1
0
1
0Tx Clk
Rx Clk
Internal Clk
(GCLK)
0
1
CTRLA.MODE[0]
/8
Sample
RxD / TxD
XCK
CTRLA.CPOL=1
Sample
RxD / TxD
XCK
CTRLA.CPOL=0
Change
Change
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24.6.2.5 Data Transmission
A data transmission is initiated by loading the DATA register with the data to be sent. The data in TxDATA is moved to
the shift register when the shift register is empty and ready to send a new frame. When the shift register is loaded with
data, one complete frame will be transmitted.
The Transmit Complete interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC) is set, and the
optional interrupt is generated, when the entire frame plus stop bit(s) have been shifted out and there is no new data
written to the DATA register.
The DATA register should only be written when the Data Register Empty flag in the Interrupt Flag Status and Clear
register (INTFLAG.DRE) is set, which indicates that the register is empty and ready for new data.
Disabling the Transmitter
Disabling the transmitter will not become effective until any ongoing and pending transmissions are completed, i.e., when
the transmit shift register and TxDATA do not contain data to be transmitted. The transmitter is disabled by writing a zero
to the Transmitter Enable bit in the Control B register (CTRLB.TXEN).
24.6.2.6 Data Reception
The receiver starts data reception when a valid start bit is detected. Each bit that follows the start bit will be sampled at
the baud rate or XCK clock, and shifted into the receive shift register until the first stop bit of a frame is received. When
the first stop bit is received and a complete serial frame is present in the receive shift register, the contents of the shift
register will be moved into the two-level receive buffer. The Receive Complete interrupt flag in the Interrupt Flag Status
and Clear register (INTFLAG.RXC) is set, and the optional interrupt is generated. A second stop bit will be ignored by the
receiver.
The received data can be read by reading the DATA register. DATA should not be read unless the Receive Complete
interrupt flag is set.
Disabling the Receiver
Disabling the receiver by writing a zero to the Receiver Enable bit in the Control B register (CTRLB.RXEN) will flush the
two-level receive buffer, and data from ongoing receptions will be lost.
Error Bits
The USART receiver has three error bits. The Frame Error (FERR), Buffer Overflow (BUFOVF) and Parity Error (PERR)
bits can be read from the Status (STATUS) register. Upon error detection, the corresponding bit will be set until it is
cleared by writing a one to it. These bits are also automatically cleared when the receiver is disabled.
There are two methods for buffer overflow notification. When the immediate buffer overflow notification bit (CTRLA.IBON)
is set, STATUS.BUFOVF is raised immediately upon buffer overflow. Software can then empty the receive FIFO by
reading RxDATA until the receive complete interrupt flag (INTFLAG.RXC) goes low.
When CTRLA.IBON is zero, the buffer overflow condition travels with data through the receive FIFO. After the received
data is read, STATUS.BUFOVF will be set along with INTFLAG.RXC.
Asynchronous Data Reception
The USART includes a clock recovery and data recovery unit for handling asynchronous data reception. The clock
recovery logic is used to synchronize the incoming asynchronous serial frames at the RxD pin to the internally generated
baud-rate clock. The data recovery logic samples and applies a low-pass filter to each incoming bit, thereby improving
the noise immunity of the receiver. The asynchronous reception operational range depends on the accuracy of the
internal baud-rate clock, the rate of the incoming frames and the frame size (in number of bits).
Asynchronous Operational Range
The operational range of the receiver depends on the difference between the received bit rate and the internally
generated baud rate. If the baud rate of an external transmitter is too high or too low compared to the internally generated
baud rate, the receiver will not be able to synchronize the frames to the start bit.
There are two possible sources for a mismatch in baud rate. The reference clock will always have some minor instability.
In addition, the baud-rate generator can not always do an exact division of the reference clock frequency to get the baud
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rate desired. In this case, the BAUD register value should be selected to give the lowest possible error. Refer to
“Asynchronous Arithmetic Mode BAUD Value Selection” on page 431 for details.
Recommended maximum receiver baud-rate errors for various character sizes are shown in the table below.
Table 24-2. Asynchronous Receiver Error for x16 Oversampling
The recommended maximum receiver baud-rate error assumes that the receiver and transmitter equally divide the
maximum total error.
The following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate:
where:
zS is the number of samples per bit (S = 16, 8 or 3)
zSF is the first sample number used for majority voting (SF = 7, 3, or 2) when CTRLA.SAMPA=0.
zSM is the middle sample number used for majority voting (SM = 8, 4, or 2) when CTRLA.SAMPA=0.
zD is the sum of character size and parity size (D = 5 to 10 bits)
zRSLOW is the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate
zRFAST is the ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate
24.6.3 Additional Features
24.6.3.1 Parity
Even or odd parity can be selected for error checking by writing 0x1 to the Frame Format bit group in the Control A
register (CTRLA.FORM). If even parity is selected by writing a zero to the Parity Mode bit in the Control B register
(CTRLB.PMODE), the parity bit of the outgoing frame is set to one if the number of data bits that are one is odd (making
the total number of ones even). If odd parity is selected by writing a one to CTRLB.PMODE, the parity bit of the outgoing
frame is set to one if the number of data bits that are one is even (making the total number of ones odd).
When parity checking is enabled, the parity checker calculates the parity of the data bits in incoming frames and
compares the result with the parity bit of the corresponding frame. If a parity error is detected, the Parity Error bit in the
Status register (STATUS.PERR) is set.
24.6.3.2 Hardware Handshaking
The USART features an out-of-band hardware handshaking flow control mechanism, implemented by connecting the RTS and
CTS pins with the remote device, as shown in Figure 24-5.
D
(Data bits + Parity) RSLOW(%) RFAST(%) Max Total Error (%)
Recommended Max
Rx Error (%)
594.12 107.69 +5.88/-7.69 ±2.5
694.92 106.67 +5.08/-6.67 ±2.0
795.52 105.88 +4.48/-5.88 ±2.0
896.00 105.26 +4.00/-5.26 ±2.0
996.39 104.76 +3.61/-4.76 ±1.5
10 96.70 104.35 +3.30/-4.35 ±1.5
6)1(16
)1(16
++
+
=D
D
RSLOW
8)1(16
)2(16
++
+
=D
D
RFAST
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Figure 24-5. Connection with a Remote Device for Hardware Handshaking
Hardware handshaking is only available with the following configuration:
zUSART with internal clock (CTRLA.MODE = 1).
zAsynchronous mode (CTRLA.CMODE = 0).
zFlow control pinout (CTRLA.TXPO = 2).
The receiver drives its RTS pin high when disabled, or when the receive FIFO is full. This indicates to the remote device
that it must stop transmitting after the ongoing transmission is complete. Enabling and disabling the receiver by writing
RXEN will set/clear the RTS pin after a synchronization delay. When the receive FIFO goes full, RTS is immediately set
and the frame that is currently being received will be stored in the shift register until the receive FIFO is no longer full.
Figure 24-6. Receiver Behavior when Operating with Hardware Handshaking
The current CTS level is available in the STATUS register (STATUS.CTS). Character transmission will only start if CTS is
low. When CTS goes high, the transmitter will stop transmitting after the ongoing transmission is complete.
Figure 24-7. Transmitter Behavior when Operating with Hardware Handshaking
24.6.3.3 IrDA Modulation and Demodulation
IrDA modulation and demodulation is available with the following configuration. When enabled, transmission and
reception is IrDA compliant up to 115.2 kb/s.
zIrDA encoding enabled (CTRLB.ENC=1).
zAsynchronous mode (CTRLA.CMODE = 0).
z16x sample rate (CTRLA.SAMPR[0] = 0).
During transmission, each low bit is transmitted as a high pulse with width as 3/16 of the baud rate period as illustrated in
Figure 24-8.
RXD
CTS
RTS
USART
TXD
RTS
CTS
Remote
Device
TXD RXD
RTS
Rx FIFO Full
RXD
RXEN
CTS
TXD
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Figure 24-8. IrDA Transmit Encoding
The reception decoder has two main functions. The first is to synchronize the incoming data to the IrDA baud rate
counter. Synchronization is performed at the start of each zero pulse. The second function is to decode incoming Rx
data. If a pulse width meets the minimum length set by configuration (RXPL.RXPL), it is accepted. When the baud rate
counter reaches its middle value (1/2 bit length), it is transferred to the receiver.
Figure 24-9 illustrates reception where RXPL.RXPL is set to 19. This indicates that the pulse width should be at least 20
SE clock cycles. When assuming BAUD = 0xE666 or 160 SE cycles per bit, this corresponds to 2/16 baud clock as
minimum pulse width required. In this case the first bit is accepted as a zero, the second bit is a one, and the third bit is
also a one. A low pulse is rejected since it does not meet the minimum requirement of 2/16 baud clock.
Figure 24-9. IrDA Receive Decoding
Note that the polarity of the transmitter and receiver are opposite. During transmission, a zero bit is transmitted as a one
pulse. During reception, an accepted zero pulse is received as a zero bit.
24.6.3.4 Break Character Detection and Auto-baud
Break character detection and auto-baud are available with the following configuration:
zAuto-baud frame format (CTRLA.FORM = 0x04 or 0x05)
zAsynchronous mode (CTRLA.CMODE = 0).
z16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1).
The auto-baud follows the LIN format. All LIN Frames start with a Break Field followed by a Sync Field. The USART uses
a break detection threshold of greater than 11 nominal bit times at the configured baud rate. At any time, if more than 11
consecutive dominant bits are detected on the bus, the USART detects a Break Field. When a Break Field has been
detected, the Receive Break interrupt flag (INTFLAG.RXBRK) is set and the USART expects the Sync Field character to
be 0x55. This field is used to update the actual baud rate in order to stay synchronized. If the received Sync character is
not 0x55, then the Inconsistent Sync Field error flag (STATUS.ISF) is set along with the Error interrupt flag
(INTFLAG.ERROR) and the baud rate is unchanged.
Figure 24-10.LIN Break and Sync Fields
IrDA encoded TXD
TXD
1 baud clock
3/16 baud clock
IrDA encoded RXD
RXD
Baud clock
20 SE clock cycles
0 0.5 11.5 22.5
Break Field Sync Field
8 bit times
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After a break field is detected and the start bit of the Sync Field is detected, a counter is started. The counter is then
incremented for the next 8 bit times of the Sync Field. At the end of these 8 bit times, the counter is stopped. At this
moment, the 13 most significant bits of the counter (value divided by 8) gives the new clock divider (BAUD.BAUD) and
the 3 least significant bits of this value (the remainder) gives the new Fractional Part (BAUD.FP). When the Sync Field
has been received, the clock divider (BAUD.BAUD) and the Fractional Part (BAUD.FP) are updated in the Baud Rate
Generator register (BAUD) after a synchronization delay.
After the Break and Sync Fields, n characters of data can be received.
24.6.3.5 Collision Detection
When the receiver and transmitter are connected either through pin configuration or externally, transmit collision can be
detected by setting the Collision Detection Enable bit (CTRLB.COLDEN). For collision to be detected, the receiver and
transmitter must be enabled (CTRLB.RXEN=1 and CTRLB.TXEN=1).
Collision detection is performed for each bit transmitted by checking the received value vs the transmit value as shown in
Figure 24-11. While the transmitter is idle (no transmission in progress), characters can be received on RxD without
triggering a collision.
Figure 24-11.Collision Checking
Figure 24-12 shows the conditions for a collision detection. In this case, the start bit and the first data bit are received
with the same value as transmitted. The second received data bit is found to be different than the transmitted bit at the
detection point which indicates a collision.
Figure 24-12.Collision Detected
When a collision is detected, the USART automatically follows this sequence:
zThe current transfer is aborted.
zThe transmit buffer is flushed.
zThe transmitter is disabled (CTRLB.TXEN=0).
zThis commences immediately and is complete after synchronization time. The CTRLB Synchronization
Busy bit (SYNCBUSY.CTRLB) will be set until this is complete.
zThis results in the TxD pin being tri-stated.
zThe Collision Detected bit (STATUS.COLL) is set along with the Error interrupt flag (INTFLAG.ERROR).
8-bit character, single stop bit
Collision checked
TXD
RXD
Collision checked and ok
TXD
RXD
Collision detected
Tri-state
TXEN
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zSince the transmit buffer no longer contains data, the Transmit Complete interrupt flag (INTFLAG.TXC) is set.
After a collision, software must manually enable the transmitter before continuing. Software must ensure CTRLB
Synchronization Busy bit (SYNCBUSY.CTRLB) is not asserted before re-enabling the transmitter.
24.6.3.6 Loop-back Mode
By configuring the Receive Data Pinout (CTRLA.RXPO) and Transmit Data Pinout (CTRLA.TXPO) to use the same data
pins for transmit and receive, loop-back is achieved. The loop-back is through the pad, so the signal is also available
externally.
24.6.3.7 Start-of-Frame Detection
The USART start-of-frame detector can wake up the CPU when it detects a start bit. In standby sleep mode, the internal
fast startup oscillator must be selected as the GCLK_SERCOMx_CORE source.
When a 1-to-0 transition is detected on RxD, the 8MHz Internal Oscillator is powered up and the USART clock is
enabled. After startup, the rest of the data frame can be received, provided that the baud rate is slow enough in relation
to the fast startup internal oscillator start-up time. Refer to “Electrical Characteristics” on page 1055 for details. The start-
up time of this oscillator varies with supply voltage and temperature.
The USART start-of-frame detection works both in asynchronous and synchronous modes. It is enabled by writing a one
to the Start of Frame Detection Enable bit in the Control B register (CTRLB.SFDE). If the Receive Start Interrupt Enable
bit in the Interrupt Enable Set register (INTENSET.RXS) is set, the Receive Start interrupt is generated immediately
when a start is detected. When using start-of-frame detection without the Receive Start interrupt, start detection will force
the 8MHz Internal Oscillator and USART clock active while the frame is being received, but the CPU will not wakeup until
the Receive Complete interrupt is generated, if enabled.
24.6.3.8 Sample Adjustment
In asynchronous mode (CTRLA.CMODE=0), three samples in the middle are used to determine the value based on
majority voting. The three samples used for voting can be selected using the Sample Adjustment bit field in Control A
register (CTRLA.SAMPA). When CTRLA.SAMPA is set to zero, samples 7-8-9 are used for 16x over sampling and
samples 3-4-5 are used for 8x over sampling.
24.6.4 DMA, Interrupts and Events
24.6.4.1 DMA Operation
The USART generates the following DMA requests.
Table 24-3. Module Request for SERCOM USART
Condition
Interrupt
request Event output Event input DMA request
DMA request is
cleared
Data Register Empty x x When data is
written
Transmit Complete x
Receive Complete x x When data is
read
Receive Start x
Clear to Send Input
Change x
Receive Break x
Error x
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zData received (RX): The request is set when data is available in the receive FIFO. The request is cleared when
DATA is read.
zData transmit (TX): The request is set when the transmit buffer (TX DATA) is empty. The request is cleared when
DATA is written.
24.6.4.2 Interrupts
The USART has the following interrupt sources:
zError (ERROR): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode.
zReceived Break (RXBRK): this is an asynchronous interrupt and can be used to wake-up the device from any
sleep mode.
zClear to Send Input Change (CTSIC): this is an asynchronous interrupt and can be used to wake-up the device
from any sleep mode.
zReceive Start (RXS): this is an asynchronous interrupt and can be used to wake-up the device from any sleep
mode.
zReceive Complete (RXC): this is an asynchronous interrupt and can be used to wake-up the device from any sleep
mode.
zTransmit Complete (TXC): this is an asynchronous interrupt and can be used to wake-up the device from any
sleep mode.
zData Register Empty (DRE): this is an asynchronous interrupt and can be used to wake-up the device from any
sleep mode.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one
to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is
cleared, the interrupt is disabled or the USART is reset. See the register description for details on how to clear interrupt
flags.
The USART has one common interrupt request line for all the interrupt sources. The user must read INTFLAG to
determine which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to “Nested Vector Interrupt
Controller” on page 29 for details.
24.6.4.3 Events
Not applicable.
24.6.5 Sleep Mode Operation
When using internal clocking, writing the Run In Standby bit in the Control A register (CTRLA.RUNSTDBY) to one will
allow GCLK_SERCOMx_CORE to be enabled in all sleep modes. Any interrupt can wake up the device.
When using external clocking, writing a one to CTRLA.RUNSTDBY will allow the Receive Start or Receive Complete
interrupt.to wake up the device.
If CTRLA.RUNSTDBY is zero, the internal clock will be disabled when any ongoing transfer is finished. A Receive Start
or Transfer Complete interrupt can wake up the device. When using external clocking, this will be disconnected when any
ongoing transfer is finished, and all reception will be dropped.
24.6.6 Synchronization
Due to the asynchronicity between CLK_SERCOMx_APB and GCLK_SERCOMx_CORE, some registers must be
synchronized when accessed. A register can require:
zSynchronization when written
zSynchronization when read
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zSynchronization when written and read
zNo synchronization
When executing an operation that requires synchronization, the corresponding Synchronization Busy bit in the
Synchronization Busy register (SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
If an operation that requires synchronization is executed while the corresponding SYNCBUSY bit is one, a peripheral bus
error is generated.
The following bits need synchronization when written:
zSoftware Reset bit in the Control A register (CTRLA.SWRST). SYNCBUSY.SWRST is set to one while
synchronization is in progress.
zEnable bit in the Control A register (CTRLA.ENABLE). SYNCBUSY.ENABLE is set to one while synchronization is
in progress.
zReceiver Enable bit in the Control B register (CTRLB.RXEN). SYNCBUSY.CTRLB is set to one while
synchronization is in progress.
zTransmitter Enable bit in the Control B register (CTRLB.TXEN). SYNCBUSY.CTRLB is set to one while
synchronization is in progress.
Synchronization is denoted by the Write-Synchronized property in the register description.
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24.7 Register Summary
Table 24-4. Register Summary
Offset Name Bit Pos.
0x00
CTRLA
7:0 RUNSTDBY MODE[2:0] ENABLE SWRST
0x01 15:8 SAMPR[2:0] IBON
0x02 23:16 SAMPA[1:0] RXPO[1:0] TXPO[1:0]
0x03 31:24 DORD CPOL CMODE FORM[3:0]
0x04
CTRLB
7:0 SBMODE CHSIZE[2:0]
0x05 15:8 PMODE ENC SFDE COLDEN
0x06 23:16 RXEN TXEN
0x07 31:24
0x08 Reserved
0x09 Reserved
0x0A Reserved
0x0B Reserved
0x0C
BAUD
7:0 BAUD[7:0]
0x0D 15:8 FP[2:0]/BAUD[15:13] BAUD[12:8]
0x0E RXPL 7:0 RXPL[7:0]
0x0F Reserved
0x10 Reserved
0x11 Reserved
0x12 Reserved
0x13 Reserved
0x14 INTENCLR 7:0 ERROR RXBRK CTSIC RXS RXC TXC DRE
0x15 Reserved
0x16 INTENSET 7:0 ERROR RXBRK CTSIC RXS RXC TXC DRE
0x17 Reserved
0x18 INTFLAG 7:0 ERROR RXBRK CTSIC RXS RXC TXC DRE
0x19 Reserved
0x1A
STATUS
7:0 COLL ISF CTS BUFOVF FERR PERR
0x1B 15:8
0x1C
SYNCBUSY
7:0 CTRLB ENABLE SWRST
0x1D 15:8
0x1E 23:16
0x1F 31:24
0x20 Reserved
0x21 Reserved
0x22 Reserved
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0x23 Reserved
0x24 Reserved
0x25 Reserved
0x26 Reserved
0x27 Reserved
0x28
DATA
7:0 DATA[7:0]
0x29 15:8 DATA[8]
0x2A Reserved
0x2B Reserved
0x2C Reserved
0x2D Reserved
0x2E Reserved
0x2F Reserved
0x30 DBGCTRL 7:0 DBGSTOP
Offset Name Bit Pos.
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24.8 Register Description
Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters
and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by
the Write-Protected property in each individual register description. Refer to “Register Access Protection” on page 436
for details.
Some registers require synchronization when read and/or written. Synchronization is denoted by the Synchronized
property in each individual register description. Refer to “Synchronization” on page 446 for details.
Some registers are enable-protected, meaning they can only be written when the USART is disabled. Enable-protection
is denoted by the Enable-Protected property in each individual register description.
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24.8.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00000000
Property: Enable-Protected, Write-Protected, Write-Synchronized
zBit 31 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 30 – DORD: Data Order
This bit indicates the data order when a character is shifted out from the Data register.
0: MSB is transmitted first.
1: LSB is transmitted first.
This bit is not synchronized.
zBit 29 – CPOL: Clock Polarity
This bit indicates the relationship between data output change and data input sampling in synchronous mode.
This bit is not synchronized.
Bit3130292827262524
DORD CPOL CMODE FORM[3:0]
Access R R/W R/W R/W R/W R/W R/W R/W
Reset00000000
Bit2322212019181716
SAMPA[1:0] RXPO[1:0] TXPO[1:0]
Access R/W R/W R/W R/W R R R/W R/W
Reset00000000
Bit151413121110 9 8
SAMPR[2:0] IBON
Access R/W R/W R/W R R R R R
Reset00000000
Bit76543210
RUNSTDBY MODE[2:0] ENABLE SWRST
Access R/W R R R/W R/W R/W R/W R/W
Reset00000000
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Table 24-5. Clock Polarity
zBit 28 – CMODE: Communication Mode
This bit indicates asynchronous or synchronous communication.
0: Asynchronous communication.
1: Synchronous communication.
This bit is not synchronized.
zBits 27:24 – FORM[3:0]: Frame Format
These bits define the frame format.
These bits are not synchronized.
Table 24-6. Frame Format
zBits 23:22 – SAMPA[1:0]: Sample Adjustment
These bits define the sample adjustment.
These bits are not synchronized.
Table 24-7. Sample Adjustment
zBits 21:20 – RXPO[1:0]: Receive Data Pinout
These bits define the receive data (RxD) pin configuration.
These bits are not synchronized.
CPOL TxD Change RxD Sample
0x0 Rising XCK edge Falling XCK edge
0x1 Falling XCK edge Rising XCK edge
FORM[3:0] Description
0x0 USART frame
0x1 USART frame with parity
0x2-0x3 Reserved
0x4 Auto-baud -- break detection and auto-baud.
0x5 Auto-baud -- break detection and auto-baud with parity
0x6-0xF Reserved
SAMPA[1:0]
16x Over-sampling
(CTRLA.SAMPR=0 or 1)
8x Over-sampling
(CTRLA.SAMPR=2 or 3)
0x0 7-8-9 3-4-5
0x1 9-10-11 4-5-6
0x2 11-12-13 5-6-7
0x3 13-14-15 6-7-8
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zBits 19:18 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 17:16 – TXPO[1:0]: Transmit Data Pinout
These bits define the transmit data (TxD) and XCK pin configurations.
This bit is not synchronized.
Table 24-9. Transmit Data Pinout
zBits 15:13 – SAMPR[2:0]: Sample Rate
These bits define the sample rate.
These bits are not synchronized.
Table 24-10. Sample Rate
zBits 12:9 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 8 – IBON: Immediate Buffer Overflow Notification
This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is asserted when a buffer overflow occurs.
Table 24-8. Receive Data Pinout
RXPO[1:0] Name Description
0x0 PAD[0] SERCOM PAD[0] is used for data reception
0x1 PAD[1] SERCOM PAD[1] is used for data reception
0x2 PAD[2] SERCOM PAD[2] is used for data reception
0x3 PAD[3] SERCOM PAD[3] is used for data reception
TXPO
TxD Pin
Location
XCK Pin Location
(When Applicable) RTS CTS
0x0 SERCOM PAD[0] SERCOM PAD[1] N/A N/A
0x1 SERCOM PAD[2] SERCOM PAD[3] N/A N/A
0x2 SERCOM PAD[0] N/A SERCOM PAD[2] SERCOM PAD[3]
0x3 Reserved
SAMPR[2:0] Description
0x0 16x over-sampling using arithmetic baud rate generation.
0x1 16x over-sampling using fractional baud rate generation.
0x2 8x over-sampling using arithmetic baud rate generation.
0x3 8x over-sampling using fractional baud rate generation.
0x4 3x over-sampling using arithmetic baud rate generation.
0x5-0x7 Reserved
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0: STATUS.BUFOVF is asserted when it occurs in the data stream.
1: STATUS.BUFOVF is asserted immediately upon buffer overflow.
zBit 7 – RUNSTDBY: Run In Standby
This bit defines the functionality in standby sleep mode.
This bit is not synchronized.
Table 24-11. Run In Standby
zBits 6:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 4:2 – MODE: Operating Mode
These bits must be written to 0x0 or 0x1 to select the USART serial communication interface of the SERCOM.
0x0: USART with external clock.
0x1: USART with internal clock.
These bits are not synchronized.
zBit 1 – ENABLE: Enable
0: The peripheral is disabled or being disabled.
1: The peripheral is enabled or being enabled.
Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRLA.ENABLE will read back immediately and the Enable Synchronization Busy bit in the Syn-
chronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE is cleared when the operation
is complete.
This bit is not enable-protected.
zBit 0 – SWRST: Software Reset
0: There is no reset operation ongoing.
1: The reset operation is ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SER-
COM will be disabled.
Writing a one to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-oper-
ation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading
any register will return the reset value of the register.
Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST
and SYNCBUSY.SWRST will both be cleared when the reset is complete.
This bit is not enable-protected.
RUNSTDBY External Clock Internal Clock
0x0
External clock is disconnected when
ongoing transfer is finished. All
reception is dropped.
Generic clock is disabled when ongoing transfer is
finished. The device can wake up on Receive Start or
Transfer Complete interrupt.
0x1 Wake on Receive Start or Receive
Complete interrupt.
Generic clock is enabled in all sleep modes. Any
interrupt can wake up the device.
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24.8.2 Control B
Name: CTRLB
Offset: 0x04
Reset: 0x00000000
Property: Enable-Protected, Write-Protected, Write-Synchronized
zBits 31:18 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 17 – RXEN: Receiver Enable
0: The receiver is disabled or being enabled.
1: The receiver is enabled or will be enabled when the USART is enabled.
Writing a zero to this bit will disable the USART receiver. Disabling the receiver will flush the receive buffer and
clear the FERR, PERR and BUFOVF bits in the STATUS register.
Writing a one to CTRLB.RXEN when the USART is disabled will set CTRLB.RXEN immediately. When the USART
is enabled, CTRLB.RXEN will be cleared, and SYNCBUSY.CTRLB will be set and remain set until the receiver is
enabled. When the receiver is enabled, CTRLB.RXEN will read back as one.
Writing a one to CTRLB.RXEN when the USART is enabled will set SYNCBUSY.CTRLB, which will remain set
until the receiver is enabled, and CTRLB.RXEN will read back as one.
This bit is not enable-protected.
zBit 16 – TXEN: Transmitter Enable
0: The transmitter is disabled or being enabled.
Bit3130292827262524
AccessRRRRRRRR
Reset00000000
Bit2322212019181716
RXEN TXEN
AccessRRRRRRR/WR/W
Reset00000000
Bit151413121110 9 8
PMODE ENC SFDE COLDEN
Access R R R/W R R R/W R/W R/W
Reset00000000
Bit76543210
SBMODE CHSIZE[2:0]
Access R R/W R R R R/W R/W R/W
Reset00000000
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1: The transmitter is enabled or will be enabled when the USART is enabled.
Writing a zero to this bit will disable the USART transmitter. Disabling the transmitter will not become effective until
ongoing and pending transmissions are completed.
Writing a one to CTRLB.TXEN when the USART is disabled will set CTRLB.TXEN immediately. When the USART
is enabled, CTRLB.TXEN will be cleared, and SYNCBUSY.CTRLB will be set and remain set until the transmitter
is enabled. When the transmitter is enabled, CTRLB.TXEN will read back as one.
Writing a one to CTRLB.TXEN when the USART is enabled will set SYNCBUSY.CTRLB, which will remain set
until the receiver is enabled, and CTRLB.TXEN will read back as one.
This bit is not enable-protected.
zBits 15:14 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 13 – PMODE: Parity Mode
This bit selects the type of parity used when parity is enabled (CTRLA.FORM is one). The transmitter will automat-
ically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a
parity value for the incoming data and parity bit, compare it to the parity mode and, if a mismatch is detected, STA-
TUS.PERR will be set.
0: Even parity.
1: Odd parity.
This bit is not synchronized.
zBits 12:11 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 10 – ENC: Encoding Format
This bit selects the data encoding format.
0: Data is not encoded.
1: Data is IrDA encoded.
This bit is not synchronized.
zBit 9 – SFDE: Start of Frame Detection Enable
This bit controls whether the start-of-frame detector will wake up the device when a start bit is detected on the RxD
line, according to the table below.
This bit is not synchronized.
zBit 8 -- COLDEN: Collision Detection Enable
This bit enables collision detection.
0: Collision detection is not enabled.
1: Collision detection is enabled.
SFDE INTENSET.RXS INTENSET.RXC Description
0 X X Start-of-frame detection disabled.
1 0 0 Reserved
1 0 1 Start-of-frame detection enabled. RXC wakes up the device from all sleep modes.
1 1 0 Start-of-frame detection enabled. RXS wakes up the device from all sleep modes.
1 1 1 Start-of-frame detection enabled. Both RXC and RXS wake up the device from all
sleep modes.
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This bit is not synchronized.
zBit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 6 – SBMODE: Stop Bit Mode
This bit selects the number of stop bits transmitted.
0: One stop bit.
1: Two stop bits.
This bit is not synchronized.
zBits 5:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 2:0 – CHSIZE[2:0]: Character Size
These bits select the number of bits in a character.
These bits are not synchronized.
Table 24-12. Character Size
CHSIZE[2:0] Description
0x0 8 bits
0x1 9 bits
0x2-0x4 Reserved
0x5 5 bits
0x6 6 bits
0x7 7 bits
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24.8.3 Baud
Name: BAUD
Offset: 0x0C
Reset: 0x0000
Property: Enable-Protected, Write-Protected
Arithmetic Baud Rate Generation (CTRLA.SAMPR[0]=0)
zBits 15:0 – BAUD[15:0]: Baud Value
These bits control the clock generation, as described in the SERCOM Baud Rate section.
Fractional Baud Rate Generation (CTRLA.SAMPR[0]=1)
zBits 15:13 – FP[2:0]: Fractional Part
These bits control the clock generation, as described in the SERCOM Baud Rate section.
zBits 15:0 – BAUD[12:0]: Baud Value
These bits control the clock generation, as described in the SERCOM Baud Rate section.
Bit151413121110 9 8
FP[2:0]/BAUD[15:13] BAUD[12:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
Bit76543210
BAUD[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
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24.8.4 Receive Pulse Length Register
Name: RXPL
Offset: 0x0E
Reset: 0x00
Property: Write-Protected
zBits 7:0 – RXPL[7:0]: Receive Pulse Length
When the encoding format is set to IrDA (CTRLB.ENC=1), these bits control the minimum pulse length that is
required for a pulse to be accepted by the IrDA receiver with regards to the serial engine clock period.
Bit76543210
RXPL[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
per
SERXPLPULSE ×+≥ )1(
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24.8.5 Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x14
Reset: 0x00
Property: Write-Protected
zBit 7– ERROR: Error Interrupt Enable
0: Error interrupt is disabled.
1: Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
zBit 6 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 5 – RXBRK: Receive Break Interrupt Enable
0: Receive Break interrupt is disabled.
1: Receive Break interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Receive Break Interrupt Enable bit, which disables the Receive Break
interrupt.
zBit 4 – CTSIC: Clear to Send Input Change Interrupt Enable
0: Clear To Send Input Change interrupt is disabled.
1: Clear To Send Input Change interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Clear To Send Input Change Interrupt Enable bit, which disables the Clear To
Send Input Change interrupt.
zBit 3 – RXS: Receive Start Interrupt Enable
0: Receive Start interrupt is disabled.
1: Receive Start interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Receive Start Interrupt Enable bit, which disables the Receive Start interrupt.
zBit 2 – RXC: Receive Complete Interrupt Enable
0: Receive Complete interrupt is disabled.
1: Receive Complete interrupt is enabled.
Writing a zero to this bit has no effect.
Bit76543210
ERROR RXBRK CTSIC RXS RXC TXC DRE
Access R/W R R/W R/W R/W R/W R/W R/W
Reset00000000
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Writing a one to this bit will clear the Receive Complete Interrupt Enable bit, which disables the Receive Complete
interrupt.
zBit 1 – TXC: Transmit Complete Interrupt Enable
0: Transmit Complete interrupt is disabled.
1: Transmit Complete interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transmit Complete Interrupt Enable bit, which disables the Receive Complete
interrupt.
zBit 0 – DRE: Data Register Empty Interrupt Enable
0: Data Register Empty interrupt is disabled.
1: Data Register Empty interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Data Register Empty Interrupt Enable bit, which disables the Data Register
Empty interrupt.
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24.8.6 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear register (INTENCLR) .
Name: INTENSET
Offset: 0x16
Reset: 0x00
Property: Write-Protected
zBit 7 – ERROR: Error Interrupt Enable
0: Error interrupt is disabled.
1: Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.
zBits 6 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 5– RXBRK: Receive Break Interrupt Enable
0: Receive Break interrupt is disabled.
1: Receive Break interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Receive Break Interrupt Enable bit, which enables the Receive Break interrupt.
zBit 4 – CTSIC: Clear to Send Input Change Interrupt Enable
0: Clear To Send Input Change interrupt is disabled.
1: Clear To Send Input Change interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Clear To Send Input Change Interrupt Enable bit, which enables the Clear To
Send Input Change interrupt.
zBit 3 – RXS: Receive Start Interrupt Enable
0: Receive Start interrupt is disabled.
1: Receive Start interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Receive Start Interrupt Enable bit, which enables the Receive Start interrupt.
zBit 2 – RXC: Receive Complete Interrupt Enable
0: Receive Complete interrupt is disabled.
1: Receive Complete interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Receive Complete Interrupt Enable bit, which enables the Receive Complete
interrupt.
Bit76543210
ERROR RXBRK CTSIC RXS RXC TXC DRE
Access R/W R R/W R/W R/W R/W R/W R/W
Reset00000000
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zBit 1– TXC: Transmit Complete Interrupt Enable
0: Transmit Complete interrupt is disabled.
1: Transmit Complete interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Transmit Complete Interrupt Enable bit, which enables the Transmit Complete
interrupt.
zBit 0 – DRE: Data Register Empty Interrupt Enable
0: Data Register Empty interrupt is disabled.
1: Data Register Empty interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Data Register Empty Interrupt Enable bit, which enables the Data Register
Empty interrupt.
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24.8.7 Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x18
Reset: 0x00
Property:
zBit 7– ERROR: Error
This flag is cleared by writing a one to it.
This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the
STATUS register. Errors that will set this flag are COLL, ISF, BUFOVF, FERR, and PERR.Writing a zero to
this bit has no effect.
Writing a one to this bit will clear the flag.
zBits 6 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 5 – RXBRK: Receive Break
This flag is cleared by writing a one to it.
This flag is set when auto-baud is enabled (CTRLA.FORM) and a break character is received.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the flag.
zBit 4 – CTSIC: Clear to Send Input Change
This flag is cleared by writing a one to it.
This flag is set when a change is detected on the CTS pin.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the flag.
zBit 3 – RXS: Receive Start
This flag is cleared by writing a one to it.
This flag is set when a start condition is detected on the RxD line and start-of-frame detection is enabled
(CTRLB.SFDE is one).
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Receive Start interrupt flag.
zBit 2 – RXC: Receive Complete
This flag is cleared by reading the Data register (DATA) or by disabling the receiver.
This flag is set when there are unread data in DATA.
Writing a zero to this bit has no effect.
Writing a one to this bit has no effect.
zBit 1 – TXC: Transmit Complete
This flag is cleared by writing a one to it or by writing new data to DATA.
Bit76543210
ERROR RXBRK CTSIC RXS RXC TXC DRE
Access R/W R R/W R/W R/W R R/W R
Reset00000000
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This flag is set when the entire frame in the transmit shift register has been shifted out and there are no new data
in DATA.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the flag.
zBit 0 – DRE: Data Register Empty
This flag is cleared by writing new data to DATA.
This flag is set when DATA is empty and ready to be written.
Writing a zero to this bit has no effect.
Writing a one to this bit has no effect.
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24.8.8 Status
Name: STATUS
Offset: 0x1A
Reset: 0x0000
Property:
zBits 15:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 5 – COLL: Collision Detected
This bit is cleared by writing a one to the bit or by disabling the receiver.
This bit is set when collision detection is enabled (CTRLB.COLDEN) and a collision is detected.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear it.
zBit 4 – ISF: Inconsistent Sync Field
This bit is cleared by writing a one to the bit or by disabling the receiver.
This bit is set when the frame format is set to auto-baud (CTRLA.FORM) and a sync field not equal to 0x55 is
received.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear it.
zBit 3 – CTS: Clear to Send
This bit indicates the current level of the CTS pin when flow control is enabled (CTRLA.TXPO).
Writing a zero to this bit has no effect.
Writing a one to this bit has no effect.
zBit 2 – BUFOVF: Buffer Overflow
Reading this bit before reading the Data register will indicate the error status of the next character to be read.
This bit is cleared by writing a one to the bit or by disabling the receiver.
This bit is set when a buffer overflow condition is detected. A buffer overflow occurs when the receive buffer is full,
there is a new character waiting in the receive shift register and a new start bit is detected.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear it.
zBit 1 – FERR: Frame Error
Reading this bit before reading the Data register will indicate the error status of the next character to be read.
Bit151413121110 9 8
AccessRRRRRRRR
Reset00000000
Bit76543210
COLL ISF CTS BUFOVF FERR PERR
Access R R R/W R/W R R/W R/W R/W
Reset00000000
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This bit is cleared by writing a one to the bit or by disabling the receiver.
This bit is set if the received character had a frame error, i.e., when the first stop bit is zero.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear it.
zBit 0 – PERR: Parity Error
Reading this bit before reading the Data register will indicate the error status of the next character to be read.
This bit is cleared by writing a one to the bit or by disabling the receiver.
This bit is set if parity checking is enabled (CTRLA.FORM is 0x1 or 0x5) and a parity error is detected.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear it.
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24.8.9 Synchronization Busy
Name: SYNCBUSY
Offset: 0x1C
Reset: 0x00000000
Property:
zBits 31:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 2– CTRLB: CTRLB Synchronization Busy
Writing CTRLB when the SERCOM is enabled requires synchronization. When written, the SYNCBUSY.CTRLB
bit will be set until synchronization is complete. If CTRLB is written while SYNCBUSY.CTRLB is asserted, an APB
error will be generated.
0: CTRLB synchronization is not busy.
1: CTRLB synchronization is busy.
zBit 1 – ENABLE: SERCOM Enable Synchronization Busy
Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the SYNC-
BUSY.ENABLE bit will be set until synchronization is complete.
Writes to any register (except for CTRLA.SWRST) while enable synchronization is on-going will be discarded and
an APB error will be generated.
0: Enable synchronization is not busy.
1: Enable synchronization is busy.
Bit3130292827262524
AccessRRRRRRRR
Reset00000000
Bit2322212019181716
AccessRRRRRRRR
Reset00000000
Bit151413121110 9 8
AccessRRRRRRRR
Reset00000000
Bit76543210
CTRLB ENABLE SWRST
AccessRRRRRRRR
Reset00000000
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zBit 0 – SWRST: Software Reset Synchronization Busy
Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the SYNCBUSY.SWRST bit
will be set until synchronization is complete.
Writes to any register while synchronization is on-going will be discarded and an APB error will be generated.
0: SWRST synchronization is not busy.
1: SWRST synchronization is busy.
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24.8.10 Data
Name: DATA
Offset: 0x28
Reset: 0x0000
Property: -
zBits 15:9 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 8:0 – DATA[8:0]: Data
Reading these bits will return the contents of the Receive Data register. The register should be read only when the
Receive Complete Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.RXC) is set. The sta-
tus bits in STATUS should be read before reading the DATA value in order to get any corresponding error.
Writing these bits will write the Transmit Data register. This register should be written only when the Data Register
Empty Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.DRE) is set.
Bit151413121110 9 8
DATA[8]
AccessRRRRRRRR/W
Reset00000000
Bit76543210
DATA[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
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24.8.11 Debug Control
Name: DBGCTRL
Offset: 0x30
Reset: 0x00
Property: Write-Protected
zBits 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 0 – DBGSTOP: Debug Stop Mode
This bit controls the baud-rate generator functionality when the CPU is halted by an external debugger.
0: The baud-rate generator continues normal operation when the CPU is halted by an external debugger.
1: The baud-rate generator is halted when the CPU is halted by an external debugger.
Bit76543210
DBGSTOP
AccessRRRRRRRR/W
Reset00000000
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25. SERCOM SPI – SERCOM Serial Peripheral Interface
25.1 Overview
The serial peripheral interface (SPI) is one of the available modes in the Serial Communication Interface (SERCOM).
Refer to “SERCOM – Serial Communication Interface” on page 426 for details.
The SPI uses the SERCOM transmitter and receiver configured as shown in “Full-Duplex SPI Master Slave
Interconnection” on page 472. Each side, master and slave, depicts a separate SPI containing a shift register, a transmit
buffer and two receive buffers. In addition, the SPI master uses the SERCOM baud-rate generator, while the SPI slave
can use the SERCOM address match logic. Fields shown in capital letters are synchronous to CLK_SERCOMx_APB
and accessible by the CPU, while fields with lowercase letters are synchronous to the SCK clock.
25.2 Features
zFull-duplex, four-wire interface (MISO, MOSI, SCK, _SS)
zSingle-buffered transmitter, double-buffered receiver
zSupports all four SPI modes of operation
zSingle data direction operation allows alternate function on MISO or MOSI pin
zSelectable LSB- or MSB-first data transfer
zCan be used with DMA
zMaster operation:
zSerial clock speed up to half the system clock
z8-bit clock generator
zHardware controlled _SS
zSlave operation:
zSerial clock speed up to the system clock
zOptional 8-bit address match operation
zOperation in all sleep modes
zWake on _SS transition
25.3 Block Diagram
Figure 25-1. Full-Duplex SPI Master Slave Interconnection
25.4 Signal Description
shift register shift register
Master Slave
MISO
MOSI
SCK
_SS
Tx DATA
rx buffer
Rx DATA
Tx DATA
rx buffer
Rx DATA
==
ADDR/ADDRMASKBAUD
baud rate generator
Address Match
Signal Name Type Description
PAD[3:0] Digital I/O General SERCOM pins
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Refer to “I/O Multiplexing and Considerations” on page 12 for details on the pin mapping for this peripheral. One signal
can be mapped to one of several pins.
25.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
25.5.1 I/O Lines
Using the SERCOM’s I/O lines requires the I/O pins to be configured using port configuration (PORT). Refer to “PORT”
on page 373 for details.
When the SERCOM is configured for SPI operation, the pins should be configured according to Table 25-1. If the
receiver is disabled, the data input pin can be used for other purposes. In master mode the slave select line (_SS) is
hardware controlled when Master Slave Select Enable (CTRLB.MSSEN) is set to one.
Table 25-1. SPI Pin Configuration
The combined configuration of PORT and the Data In/Data Out and Data Out Pinout bit groups in Control A register will
define the physical position of the SPI signals in Table 25-1.
25.5.2 Power Management
The SPI can continue to operate in any sleep mode. The SPI interrupts can be used to wake up the device from sleep
modes. Refer to “PM – Power Manager” on page 112 for details on the different sleep modes.
25.5.3 Clocks
The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Power Manager, and the default
state of CLK_SERCOMx_APB can be found in the Peripheral Clock Masking section in the “PM – Power Manager” on
page 112.
A generic clock (GCLK_SERCOMx_CORE) is required to clock the SPI. This clock must be configured and enabled in
the Generic Clock Controller before using the SPI. Refer to “GCLK – Generic Clock Controller” on page 90 for details.
This generic clock is asynchronous to the bus clock (CLK_SERCOMx_APB). Due to this asynchronicity, writes to certain
registers will require synchronization between the clock domains. Refer to “Synchronization” on page 482 for further
details.
25.5.4 DMA
The DMA request lines are connected to the DMA controller (DMAC). Using the SERCOM DMA requests, requires
the DMA controller to be configured first. Refer to “DMAC – Direct Memory Access Controller” on page 267 for
details.
25.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the SPI, interrupts requires the Interrupt
Controller to be configured first. Refer to “Nested Vector Interrupt Controller” on page 29 for details.
Pin Master SPI Slave SPI
MOSI Output Input
MISO Input Output
SCK Output Input
_SS Output (CTRLB.MSSEN=1) Input
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25.5.6 Events
Not applicable.
25.5.7 Debug Operation
When the CPU is halted in debug mode, the SPI continues normal operation. If the SPI is configured in a way that
requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result
during debugging. The SPI can be forced to halt operation during debugging. Refer to the Debug Control (DBGCTRL)
register for details.
25.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the
following registers:
zInterrupt Flag Clear and Status register (INTFLAG)
zStatus register (STATUS)
zData register (DATA)
Write-protection is denoted by the Write-Protection property in the register description.
When the CPU is halted in debug mode, all write-protection is automatically disabled.
Write-protection does not apply for accesses through an external debugger. Refer to “PAC – Peripheral Access
Controller” on page 36 for details.
25.5.9 Analog Connections
Not applicable.
25.6 Functional Description
25.6.1 Principle of Operation
The SPI is a high-speed synchronous data transfer interface. It allows fast communication between the device and
peripheral devices.
The SPI can operate as master or slave. As master, the SPI initiates and controls all data transactions. The SPI is single
buffered for transmitting and double buffered for receiving. When transmitting data, the Data register can be loaded with
the next character to be transmitted while the current transmission is in progress. For receiving, this means that the data
is transferred to the two-level receive buffer upon reception, and the receiver is ready for a new character.
The SPI transaction format is shown in Figure 25-2, where each transaction can contain one or more characters. The
character size is configurable, and can be either 8 or 9 bits.
Figure 25-2. SPI Transaction Format
The SPI master must initiate a transaction by pulling low the slave select line (_SS) of the desired slave. The master and
slave prepare data to be sent in their respective shift registers, and the master generates the serial clock on the SCK line.
Character
Transaction
MOSI/MISO
_SS
Character 0 Character 1 Character 2
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Data are always shifted from master to slave on the master output, slave input line (MOSI), and from slave to master on
the master input, slave output line (MISO). The master signals the end of the transaction by pulling the _SS line high.
As each character is shifted out from the master, another character is shifted in from the slave.
25.6.2 Basic Operation
25.6.2.1 Initialization
The following registers are enable-protected, meaning that they can only be written when the SPI is disabled
(CTRL.ENABLE is zero):
zControl A register (CTRLA), except Enable (CTRLA.ENABLE) and Software Reset (CTRLA.SWRST)
zControl B register (CTRLB), except Receiver Enable (CTRLB.RXEN)
zBaud register (BAUD)
zAddress register (ADDR)
Any writes to these registers when the SPI is enabled or is being enabled (CTRLA.ENABLE is one) will be discarded.
Writes to these registers while the SPI is being disabled will be completed after the disabling is complete.
Enable-protection is denoted by the Enable-Protection property in the register description.
Before the SPI is enabled, it must be configured, as outlined by the following steps:
zSPI mode in master or slave operation must be selected by writing 0x2 or 0x3 to the Operating Mode bit group in
the Control A register (CTRLA.MODE)
zTransfer mode must be selected by writing the Clock Polarity bit and the Clock Phase bit in the Control A register
(CTRLA.CPOL and CTRLA.CPHA)
zTransaction format must be selected by writing the Frame Format bit group in the Control A register
(CTRLA.FORM)
zSERCOM pad to use for the receiver must be selected by writing the Data In Pinout bit group in the Control A
register (CTRLA.DIPO)
zSERCOM pads to use for the transmitter, slave select and serial clock must be selected by writing the Data Out
Pinout bit group in the Control A register (CTRLA.DOPO)
zCharacter size must be selected by writing the Character Size bit group in the Control B register (CTRLB.CHSIZE)
zData direction must be selected by writing the Data Order bit in the Control A register (CTRLA.DORD)
zIf the SPI is used in master mode, the Baud register (BAUD) must be written to generate the desired baud rate
zIf the SPI is used in master mode and Hardware SS control is required, the Master Slave Select Enable bit in
CTRLB register (CTRLB.MSSEN) should be set to 1.
zThe receiver can be enabled by writing a one to the Receiver Enable bit in the Control B register (CTRLB.RXEN)
25.6.2.2 Enabling, Disabling and Resetting
The SPI is enabled by writing a one to the Enable bit in the Control A register (CTRLA.ENABLE). The SPI is disabled by
writing a zero to CTRLA.ENABLE.
The SPI is reset by writing a one to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in the
SPI, except DBGCTRL, will be reset to their initial state, and the SPI will be disabled. Refer to CTRLA for details.
25.6.2.3 Clock Generation
In SPI master operation (CTRLA.MODE is 0x3), the serial clock (SCK) is generated internally using the SERCOM baud-
rate generator. When used in SPI mode, the baud-rate generator is set to synchronous mode, and the 8-bit Baud register
(BAUD) value is used to generate SCK, clocking the shift register. Refer to “Clock Generation – Baud-Rate Generator”
on page 429 for more details.
In SPI slave operation (CTRLA.MODE is 0x2), the clock is provided by an external master on the SCK pin. This clock is
used to directly clock the SPI shift register.
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25.6.2.4 Data Register
The SPI Transmit Data register (TxDATA) and SPI Receive Data register (RxDATA) share the same I/O address,
referred to as the SPI Data register (DATA). Writing the DATA register will update the Transmit Data register. Reading
the DATA register will return the contents of the Receive Data register.
25.6.2.5 SPI Transfer Modes
There are four combinations of SCK phase and polarity with respect to the serial data. The SPI data transfer modes are
shown in Table 25-2 and Figure 25-3. SCK phase is selected by the Clock Phase bit in the Control A register
(CTRLA.CPHA). SCK polarity is selected by the Clock Polarity bit in the Control A register (CTRLA.CPOL). Data bits are
shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for the data signals to stabilize.
Table 25-2. SPI Transfer Modes
Leading edge is the first clock edge in a clock cycle, while trailing edge is the second clock edge in a clock cycle.
Mode CPOL CPHA Leading Edge Trailing Edge
0 00Rising, sample Falling, setup
1 01Rising, setup Falling, sample
2 10Falling, sample Rising, setup
3 11Falling, setup Rising, sample
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Figure 25-3. SPI Transfer Modes
25.6.2.6 Transferring Data
Master
When configured as a master (CTRLA.MODE is 0x3), if Master Slave Select Enable (CTRLB.MSSEN) is set to zero the
_SS line can be located at any general purpose I/O pin, and must be configured as an output. When the SPI is ready for
a data transaction, software must pull the _SS line low. If Master Slave Enable Select (CTRLB.MSSEN) is set to one,
hardware controls the _SS line.
When writing a character to the Data register (DATA), the character will be transferred to the shift register when the shift
register is empty. Once the contents of TxDATA have been transferred to the shift register, the Data Register Empty flag
in the Interrupt Flag Status and Clear register (INTFLAG.DRE) is set, and a new character can be written to DATA.
As each character is shifted out from the master, another character is shifted in from the slave. If the receiver is enabled
(CTRLA.RXEN is one), the contents of the shift register will be transferred to the two-level receive buffer. The transfer
takes place in the same clock cycle as the last data bit is shifted in, and the Receive Complete Interrupt flag in the
Interrupt Flag Status and Clear register (INTFLAG.RXC) will be set. The received data can be retrieved by reading
DATA.
Bit 1
Bit 6
LSB
MSB
Mode 0
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
Mode 2
SS
MSB
LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
MSB first (DORD = 0)
LSB first (DORD = 1)
Mode 1
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
Mode 3
SS
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When the last character has been transmitted and there is no valid data in DATA, the Transmit Complete Interrupt flag in
the Interrupt Flag Status and Clear register (INTFLAG.TXC) is set. When the transaction is finished, the master must
indicate this to the slave by pulling the _SS line high. If Master Slave Select Enable (CTRLB.MSSEN) is set to zero, the
software must pull the _SS line high.
Slave
When configured as a slave (CTRLA.MODE is 0x2), the SPI interface will remain inactive, with the MISO line tri-stated as
long as the _SS pin is pulled high. Software may update the contents of DATA at any time, as long as the Data Register
Empty flag in the Interrupt Status and Clear register (INTFLAG.DRE) is set.
When _SS is pulled low and SCK is running, the slave will sample and shift out data according to the transaction mode
set. When the contents of TxDATA have been loaded into the shift register, INTFLAG.DRE is set, and new data can be
written to DATA. Similar to the master, the slave will receive one character for each character transmitted. On the same
clock cycle as the last data bit of a character is received, the character will be transferred into the two-level receive buffer.
The received character can be retrieved from DATA when Receive Complete interrupt flag (INTFLAG.RXC) is set.
When the master pulls the _SS line high, the transaction is done and the Transmit Complete Interrupt flag in the Interrupt
Flag Status and Clear register (INTFLAG.TXC) is set.
Once DATA is written, it takes up to three SCK clock cycles before the content of DATA is ready to be loaded into the
shift register. When the content of DATA is ready to be loaded, this will happen on the next character boundary. As a
consequence, the first character transferred in a SPI transaction will not be the content of DATA. This can be avoided by
using the preloading feature.
Refer to “Preloading of the Slave Shift Register” on page 479.
When transmitting several characters in one SPI transaction, the data has to be written to DATA while there are at least
three SCK clock cycles left in the current character transmission. If this criteria is not met, then the previous character
received will be transmitted.
After the DATA register is empty, it takes three CLK_SERCOM_APB cycles for INTFLAG.DRE to be set.
25.6.2.7 Receiver Error Bit
The SPI receiver has one error bit: the Buffer Overflow bit (BUFOVF), which can be read from the Status register
(STATUS). Upon error detection, the bit will be set until it is cleared by writing a one to it. The bit is also automatically
cleared when the receiver is disabled.
There are two methods for buffer overflow notification. When the immediate buffer overflow notification bit (CTRLA.IBON)
is set, STATUS.BUFOVF is set immediately upon buffer overflow. Software can then empty the receive FIFO by reading
RxDATA until the receive complete interrupt flag (INTFLAG.RXC) goes low.
When CTRLA.IBON is zero, the buffer overflow condition travels with data through the receive FIFO. After the received
data is read, STATUS.BUFOVF and INTFLAG.ERROR will be set along with INTFLAG.RXC, and RxDATA will be zero.
25.6.3 Additional Features
25.6.3.1 Address Recognition
When the SPI is configured for slave operation (CTRLA.MODE is 0x2) with address recognition (CTRLA.FORM is 0x2),
the SERCOM address recognition logic is enabled. When address recognition is enabled, the first character in a
transaction is checked for an address match. If there is a match, then the Receive Complete Interrupt flag in the Interrupt
Flag Status and Clear register (INTFLAG.RXC) is set, the MISO output is enabled and the transaction is processed. If
there is no match, the transaction is ignored.
If the device is in sleep mode, an address match can wake up the device in order to process the transaction. If the
address does not match, then the complete transaction is ignored. If a 9-bit frame format is selected, only the lower 8 bits
of the shift register are checked against the Address register (ADDR).
Refer to “Address Match and Mask” on page 432 for further details.
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25.6.3.2 Preloading of the Slave Shift Register
When starting a transaction, the slave will first transmit the contents of the shift register before loading new data from
DATA. The first character sent can be either the reset value of the shift register (if this is the first transmission since the
last reset) or the last character in the previous transmission. Preloading can be used to preload data to the shift register
while _SS is high and eliminate sending a dummy character when starting a transaction.
In order to guarantee enough set-up time before the first SCK edge, enough time must be given between _SS going low
and the first SCK sampling edge, as shown in Figure 25-4.
Preloading is enabled by setting the Slave Data Preload Enable bit in the Control B register (CTRLB.PLOADEN).
Figure 25-4. Timing Using Preloading
Only one data character written to DATA will be preloaded into the shift register while the synchronized _SS signal (see
Figure 25-4) is high. The next character written to DATA before _SS is pulled low will be stored in DATA until transfer
begins. If the shift register is not preloaded, the current contents of the shift register will be shifted out.
25.6.3.3 Master with Several Slaves
Master with multiple slaves in parallel feature is available only when Master Slave Select Enable (CTRLB.MSSEN) is set
to zero and hardware _SS control is disabled. If the bus consists of several SPI slaves, an SPI master can use general
purpose I/O pins to control the _SS line to each of the slaves on the bus, as shown in Figure 25-5. In this configuration,
the single selected SPI slave will drive the tri-state MISO line.
Figure 25-5. Multiple Slaves in Parallel
An alternate configuration is shown in Figure 25-6. In this configuration, all n attached slaves are connected in series. A
common _SS line is provided to all slaves, enabling them simultaneously. The master must shift n characters for a
complete transaction. Depending on the Master Slave Select Enable bit (CTRLB.MSSEN), _SS line is controlled either
by hardware or by user software and normal GPIO
_SS
Synchronization to
system domain
MISO to SCK
setup time
Required _SS to SCK time using
PRELOADEN
_SS synchronized to
system domain
SCK
shift register shift register
MOSI
MISO
SCK
_SS [0]
MOSI
MISO
_SS
SCK
shift register
MOSI
MISO
_SS
SCK
SPI Master
SPI Slave 0
_SS[n-1]
SPI Slave n-1
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Figure 25-6. Multiple Slaves in Series
25.6.3.4 Loop-back Mode
By configuring the Data In Pinout (CTRLA.DIPO) and Data Out Pinout (CTRLA.DOPO) to use the same data pins for
transmit and receive, loop-back is achieved. The loop-back is through the pad, so the signal is also available externally.
25.6.3.5 Hardware Controlled _SS
In master mode, a single _SS chip select can be controlled by hardware by setting the Master Slave Select Enable
(CTRLB.MSSEN) bit to one. In this mode, the _SS pin is driven low for a minimum of one baud cycle before transmission
begins, and stays low for a minimum of one baud cycle after transmission completes. If back-to-back frames are
transmitted, the _SS pin will always be driven high for a minimum of one baud cycle between frames.
In Figure 25-7, the time T is between one and two baud cycles depending on the SPI transfer mode.
Figure 25-7. Hardware Controlled _SS
When MSSEN is set to zero, the _SS pin(s) is/are controlled by user software and normal GPIO.
25.6.3.6 Slave Select Low Detection
In slave mode the SPI is capable of waking the CPU when the slave select (_SS) goes low. When the Slave Select Low
Detect is enabled (CTRLB.SSDE=1), a high to low transition will set the Slave Select Low interrupt flag (INTFLAG.SSL)
and the device will wake if applicable.
shift register shift register
MOSI
MISO
SCK
_SS
MOSI
MISO
_SS
SCK
shift register
MOSI
MISO
_SS
SCK
SPI Master SPI Slave 0
SPI Slave n-1
_SS
SCK
T
T = 1 to 2 baud cycles
TTT
T
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25.6.4 DMA, Interrupts and Events
25.6.4.1 DMA Operation
The SPI generates the following DMA requests:
zData received (RX): The request is set when data is available in the receive FIFO. The request is cleared when
DATA is read.
zData transmit (TX): The request is set when the transmit buffer (TX DATA) is empty. The request is cleared when
DATA is written.
25.6.4.2 Interrupts
The SPI has the following interrupt sources:
zError (ERROR): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode.
zSlave Select Low (SSL): his is an asynchronous interrupt and can be used to wake-up the device from any sleep
mode.
zReceive Complete (RXC): his is an asynchronous interrupt and can be used to wake-up the device from any sleep
mode.
zTransmit Complete (TXC): his is an asynchronous interrupt and can be used to wake-up the device from any sleep
mode.
zData Register Empty (DRE): his is an asynchronous interrupt and can be used to wake-up the device from any
sleep mode.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one
to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is
cleared, the interrupt is disabled or the SPI is reset. See the register description for details on how to clear interrupt flags.
The SPI has one common interrupt request line for all the interrupt sources. The user must read INTFLAG to determine
which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to “Nested Vector Interrupt
Controller” on page 29 for details.
For details on clearing interrupt flags, refer to INTFLAG.
25.6.4.3 Events
Not applicable.
Table 25-3. Module Request for SERCOM SPI
Condition Interrupt request Event output Event input DMA request
DMA request is
cleared
Data Register
Empty x x When data is
written
Transmit
Complete x
Receive
Complete x x When data is read
Slave Select low x
Error x
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25.6.5 Sleep Mode Operation
During master operation, the generic clock will continue to run in idle sleep mode. If the Run In Standby bit in the Control
A register (CTRLA.RUNSTDBY) is one, the GCLK_SERCOM_CORE will also be enabled in standby sleep mode. Any
interrupt can wake up the device.
If CTRLA.RUNSTDBY is zero during master operation, GLK_SERCOMx_CORE will be disabled when the ongoing
transaction is finished. Any interrupt can wake up the device.
During slave operation, writing a one to CTRLA.RUNSTDBY will allow the Receive Complete interrupt to wake up the
device.
If CTRLA.RUNSTDBY is zero during slave operation, all reception will be dropped, including the ongoing transaction.
25.6.6 Synchronization
Due to the asynchronicity between CLK_SERCOMx_APB and GCLK_SERCOMx_CORE, some registers must be
synchronized when accessed. A register can require:
zSynchronization when written
zSynchronization when read
zSynchronization when written and read
zNo synchronization
When executing an operation that requires synchronization, the corresponding Synchronization Busy bit in the
Synchronization Busy register (SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
If an operation that requires synchronization is executed while the corresponding SYNCBUSY bit is one, a peripheral bus
error is generated.
The following bits need synchronization when written:
zSoftware Reset bit in the Control A register (CTRLA.SWRST). SYNCBUSY.SWRST is set to one while
synchronization is in progress.
zEnable bit in the Control A register (CTRLA.ENABLE). SYNCBUSY.ENABLE is set to one while synchronization is
in progress.
zReceiver Enable bit in the Control B register (CTRLB.RXEN). SYNCBUSY.CTRLB is set to one while
synchronization is in progress.
CTRLB.RXEN behaves somewhat differently than described above. Refer to CTRLB for details.
Write-synchronization is denoted by the Write-Synchronized property in the register description.
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25.7 Register Summary
Offset Name Bit Pos.
0x00
CTRLA
7:0 RUNSTDBY MODE[2:0] ENABLE SWRST
0x01 15:8 IBON
0x02 23:16 DIPO[1:0] DOPO[1:0]
0x03 31:24 DORD CPOL CPHA FORM[3:0]
0x04
CTRLB
7:0 PLOADEN CHSIZE[2:0]
0x05 15:8 AMODE[1:0] MSSEN SSDE
0x06 23:16 RXEN
0x07 31:24
0x08 Reserved
0x09 Reserved
0x0A Reserved
0x0B Reserved
0x0C BAUD 7:0 BAUD[7:0]
0x0D Reserved
0x0E Reserved
0x0F Reserved
0x10 Reserved
0x11 Reserved
0x12 Reserved
0x13 Reserved
0x14 INTENCLR 7:0 ERROR SSL RXC TXC DRE
0x15 Reserved
0x16 INTENSET 7:0 ERROR SSL RXC TXC DRE
0x17 Reserved
0x18 INTFLAG 7:0 ERROR SSL RXC TXC DRE
0x19 Reserved
0x1A
STATUS
7:0 BUFOVF
0x1B 15:8
0x1C
SYNCBUSY
7:0 CTRLB ENABLE SWRST
0x1D 15:8
0x1E 23:16
0x1F 31:24
0x20 Reserved
0x21 Reserved
0x22 Reserved
0x23 Reserved
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0x24
ADDR
7:0 ADDR[7:0]
0x25 15:8
0x26 23:16 ADDRMASK[7:0]
0x27 31:24
0x28
DATA
7:0 DATA[7:0]
0x29 15:8 DATA[8]
0x2A Reserved
0x2B Reserved
0x2C Reserved
0x2D Reserved
0x2E Reserved
0x2F Reserved
0x30 DBGCTRL 7:0 DBGSTOP
Offset Name Bit Pos.
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25.8 Register Description
Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters
and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by
the Write-Protected property in each individual register description. Refer to “Register Access Protection” on page 474
for details.
Some registers require synchronization when read and/or written. Write-synchronization is denoted by the Write-
Synchronized property in each individual register description. Refer to “Synchronization” on page 482 for details.
Some registers are enable-protected, meaning they can only be written when the USART is disabled. Enable-protection
is denoted by the Enable-Protected property in each individual register description.
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25.8.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00000000
Property: Write-Protected, Enable-Protected, Write-Synchronized
zBit 31 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 30 – DORD: Data Order
This bit indicates the data order when a character is shifted out from the Data register.
0: MSB is transferred first.
1: LSB is transferred first.
This bit is not synchronized.
zBit 29 – CPOL: Clock Polarity
In combination with the Clock Phase bit (CPHA), this bit determines the SPI transfer mode.
0: SCK is low when idle. The leading edge of a clock cycle is a rising edge, while the trailing edge is a falling edge.
1: SCK is high when idle. The leading edge of a clock cycle is a falling edge, while the trailing edge is a rising edge.
This bit is not synchronized.
zBit 28 – CPHA: Clock Phase
In combination with the Clock Polarity bit (CPOL), this bit determines the SPI transfer mode.
Bit3130292827262524
DORD CPOL CPHA FORM[3:0]
Access R R/W R/W R/W R/W R/W R/W R/W
Reset00000000
Bit2322212019181716
DIPO[1:0] DOPO[1:0]
Access R R R/W R/W R R R/W R/W
Reset00000000
Bit151413121110 9 8
IBON
AccessRRRRRRRR/W
Reset00000000
Bit76543210
RUNSTDBY MODE[2:0] ENABLE SWRST
Access R/W R R R/W R/W R/W R/W R/W
Reset00000000
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0: The data is sampled on a leading SCK edge and changed on a trailing SCK edge.
1: The data is sampled on a trailing SCK edge and changed on a leading SCK edge.
This bit is not synchronized.
Table 25-4. SPI Transfer Modes
zBits 27:24 – FORM[3:0]: Frame Format
Table 25-5 shows the various frame formats supported by the SPI. When a frame format with address is selected,
the first byte received is checked against the ADDR register.
Table 25-5. Frame Format
zBits 23:22 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 21:20 – DIPO[1:0]: Data In Pinout
These bits define the data in (DI) pad configurations.
In master operation, DI is MISO.
In slave operation, DI is MOSI.
These bits are not synchronized.
Table 25-6. Data In Pinout
zBits 19:18 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Mode CPOL CPHA Leading Edge Trailing Edge
0x0 0 0 Rising, sample Falling, change
0x1 0 1 Rising, change Falling, sample
0x2 1 0 Falling, sample Rising, change
0x3 1 1 Falling, change Rising, sample
FORM[3:0] Name Description
0x0 SPI SPI frame
0x1 -Reserved
0x2 SPI_ADDR SPI frame with address
0x3-0xF -Reserved
DIPO[1:0] Name Description
0x0 PAD[0] SERCOM PAD[0] is used as data input
0x1 PAD[1] SERCOM PAD[1] is used as data input
0x2 PAD[2] SERCOM PAD[2] is used as data input
0x3 PAD[3] SERCOM PAD[3] is used as data input
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zBit 17:16 – DOPO: Data Out Pinout
This bit defines the available pad configurations for data out (DO) and the serial clock (SCK). In slave operation,
the slave select line (_SS) is controlled by DOPO, while in master operation the _SS line is controlled by the port
configuration.
In master operation, DO is MOSI.
In slave operation, DO is MISO.
These bits are not synchronized.
Table 25-7. Data Out Pinout
zBits 15:9 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 8 – IBON: Immediate Buffer Overflow Notification
This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is asserted when a buffer overflow occurs.
0: STATUS.BUFOVF is asserted when it occurs in the data stream.
1: STATUS.BUFOVF is asserted immediately upon buffer overflow.
This bit is not synchronized.
zBit 7 – RUNSTDBY: Run In Standby
This bit defines the functionality in standby sleep mode.
These bits are not synchronized.
Table 25-8. Run In Standby Configuration
zBits 6:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 4:2 – MODE: Operating Mode
These bits must be written to 0x2 or 0x3 to select the SPI serial communication interface of the SERCOM.
0x2: SPI slave operation
0x3: SPI master operation
These bits are not synchronized.
zBit 1 – ENABLE: Enable
0: The peripheral is disabled or being disabled.
DOPO DO SCK Slave_SS Master_SS
0x0 PAD[0] PAD[1] PAD[2] System configuration
0x1 PAD[2] PAD[3] PAD[1] System configuration
0x2 PAD[3] PAD[1] PAD[2] System configuration
0x3 PAD[0] PAD[3] PAD[1] System configuration
RUNSTDBY Slave Master
0x0 Disabled. All reception is dropped,
including the ongoing transaction.
Generic clock is disabled when ongoing transaction is
finished. All interrupts can wake up the device.
0x1 Wake on Receive Complete interrupt. Generic clock is enabled while in sleep modes. All
interrupts can wake up the device.
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1: The peripheral is enabled or being enabled.
Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRL.ENABLE will read back immediately and the Synchronization Enable Busy bit in the Syn-
chronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE is cleared when the operation
is complete.
This bit is not enable-protected.
zBit 0 – SWRST: Software Reset
0: There is no reset operation ongoing.
1: The reset operation is ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SER-
COM will be disabled.
Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-oper-
ation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading
any register will return the reset value of the register.
Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST
and SYNCBUSY. SWRST will both be cleared when the reset is complete.
This bit is not enable-protected.
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25.8.2 Control B
Name: CTRLB
Offset: 0x04
Reset: 0x00000000
Property: Write-Protected, Enable-Protected
zBits 31:18 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 17 – RXEN: Receiver Enable
0: The receiver is disabled or being enabled.
1: The receiver is enabled or it will be enabled when SPI is enabled.
Writing a zero to this bit will disable the SPI receiver immediately. The receive buffer will be flushed, data from
ongoing receptions will be lost and STATUS.BUFOVF will be cleared.
Writing a one to CTRLB.RXEN when the SPI is disabled will set CTRLB.RXEN immediately. When the SPI is
enabled, CTRLB.RXEN will be cleared, SYNCBUSY.CTRLB will be set and remain set until the receiver is
enabled. When the receiver is enabled CTRLB.RXEN will read back as one.
Writing a one to CTRLB.RXEN when the SPI is enabled will set SYNCBUSY.CTRLB, which will remain set until
the receiver is enabled, and CTRLB.RXEN will read back as one.
This bit is not enable-protected.
Bit3130292827262524
AccessRRRRRRRR
Reset00000000
Bit2322212019181716
RXEN
AccessRRRRRRR/WR
Reset00000000
Bit151413121110 9 8
AMODE[1:0] MSSEN SSDE
Access R/W R/W R/W R R R R/W R
Reset00000000
Bit76543210
PLOADEN CHSIZE[2:0]
Access R R/W R R R R/W R/W R/W
Reset00000000
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zBit 16 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 15:14 – AMODE: Address Mode
These bits set the slave addressing mode when the frame format (CTRLA.FORM) with address is used. They are
unused in master mode.
Table 25-9. Address Mode
zBit 13 – MSSEN: Master Slave Select Enable
This bit enables hardware slave select (_SS) control.
0: Hardware _SS control is disabled.
1: Hardware _SS control is enabled.
zBits 12:10 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 9 – SSDE: Slave Select Low Detect Enable
This bit enables wake up when the slave select (_SS) pin transitions from high to low.
0: _SS low detector is disabled.
1: _SS low detector is enabled.
zBits 8:7 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 6 – PLOADEN: Slave Data Preload Enable
Setting this bit will enable preloading of the slave shift register when there is no transfer in progress. If the _SS line
is high when DATA is written, it will be transferred immediately to the shift register.
zBits 5:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 2:0 – CHSIZE[2:0]: Character Size
Table 25-10. Character Size
AMODE[1:0] Name Description
0x0 MASK ADDRMASK is used as a mask to the ADDR register
0x1 2_ADDRS The slave responds to the two unique addresses in ADDR and ADDRMASK
0x2 RANGE The slave responds to the range of addresses between and including ADDR
and ADDRMASK. ADDR is the upper limit
0x3 Reserved
CHSIZE[2:0] Name Description
0x0 8BIT 8 bits
0x1 9BIT 9 bits
0x2-0x7 Reserved
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25.8.3 Baud Rate
Name: BAUD
Offset: 0x0C
Reset: 0x00
Property: Write-Protected, Enable-Protected
zBits 7:0 – BAUD: Baud Register
These bits control the clock generation, as described in the SERCOM “Clock Generation – Baud-Rate Generator”
on page 429.
Bit76543210
BAUD[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
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25.8.4 Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x14
Reset: 0x00
Property: Write-Protected
zBit 7– ERROR: Error Interrupt Enable
0: Error interrupt is disabled.
1: Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
zBits 6:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 3– SSL: Slave Select Low Interrupt Enable
0: Slave Select Low interrupt is disabled.
1: Slave Select Low interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Slave Select Low Interrupt Enable bit, which disables the Slave Select Low
interrupt.
zBit 2 – RXC: Receive Complete Interrupt Enable
0: Receive Complete interrupt is disabled.
1: Receive Complete interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Receive Complete Interrupt Enable bit, which disables the Receive Complete
interrupt.
zBit 1 – TXC: Transmit Complete Interrupt Enable
0: Transmit Complete interrupt is disabled.
1: Transmit Complete interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transmit Complete Interrupt Enable bit, which disable the Transmit Complete
interrupt.
zBit 0 – DRE: Data Register Empty Interrupt Enable
0: Data Register Empty interrupt is disabled.
1: Data Register Empty interrupt is enabled.
Writing a zero to this bit has no effect.
Bit76543210
ERROR SSL RXC TXC DRE
Access R/W R R R R/W R/W R/W R/W
Reset00000000
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Writing a one to this bit will clear the Data Register Empty Interrupt Enable bit, which disables the Data Register
Empty interrupt.
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25.8.5 Interrupt Enable Set
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name: INTENSET
Offset: 0x16
Reset: 0x00
Property: Write-Protected
zBit 7 – ERROR: Error Interrupt Enable
0: Error interrupt is disabled.
1: Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.
zBits 6:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 3 – SSL: Slave Select Low Interrupt Enable
0: Slave Select Low interrupt is disabled.
1: Slave Select Low interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Slave Select Low Interrupt Enable bit, which enables the Slave Select Low
interrupt.
zBit 2 – RXC: Receive Complete Interrupt Enable
0: Receive Complete interrupt is disabled.
1: Receive Complete interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Receive Complete Interrupt Enable bit, which enables the Receive Complete
interrupt.
zBit 1 – TXC: Transmit Complete Interrupt Enable
0: Transmit Complete interrupt is disabled.
1: Transmit Complete interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Transmit Complete Interrupt Enable bit, which enables the Transmit Complete
interrupt.
zBit 0 – DRE: Data Register Empty Interrupt Enable
0: Data Register Empty interrupt is disabled.
1: Data Register Empty interrupt is enabled.
Writing a zero to this bit has no effect.
Bit76543210
ERROR SSL RXC TXC DRE
Access R/W R R R R/W R/W R/W R/W
Reset00000000
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Writing a one to this bit will set the Data Register Empty Interrupt Enable bit, which enables the Data Register
Empty interrupt.
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25.8.6 Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x18
Reset: 0x00
Property: -
zBit 7 – ERROR: Error
This flag is cleared by writing a one to it.
This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the
STATUS register. The BUFOVF error will set this interrupt flag.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the flag.
zBits 6:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 3 – SSL: Slave Select Low
This flag is cleared by writing a one to it.
This bit is set when a high to low transition is detected on the _SS pin in slave mode and Slave Select Low
Detect (CTRLB.SSDE) is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the flag.
zBit 2 – RXC: Receive Complete
This flag is cleared by reading the Data (DATA) register or by disabling the receiver.
This flag is set when there are unread data in the receive buffer. If address matching is enabled, the first data
received in a transaction will be an address.
Writing a zero to this bit has no effect.
Writing a one to this bit has no effect.
zBit 1 – TXC: Transmit Complete
This flag is cleared by writing a one to it or by writing new data to DATA.
In master mode, this flag is set when the data have been shifted out and there are no new data in DATA.
In slave mode, this flag is set when the _SS pin is pulled high. If address matching is enabled, this flag is only set
if the transaction was initiated with an address match.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the flag.
zBit 0 – DRE: Data Register Empty
This flag is cleared by writing new data to DATA.
This flag is set when DATA is empty and ready for new data to transmit.
Writing a zero to this bit has no effect.
Bit76543210
ERROR SSL RXC TXC DRE
Access R/W R R R R/W R R/W R
Reset00000000
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Writing a one to this bit has no effect.
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25.8.7 Status
Name: STATUS
Offset: 0x1A
Reset: 0x0000
Property: –
zBits 15:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 2 – BUFOVF: Buffer Overflow
Reading this bit before reading DATA will indicate the error status of the next character to be read.
This bit is cleared by writing a one to the bit or by disabling the receiver.
This bit is set when a buffer overflow condition is detected. An overflow condition occurs if the two-level receive
buffer is full when the last bit of the incoming character is shifted into the shift register. All characters shifted into
the shift registers before the overflow condition is eliminated by reading DATA will be lost.
When set, the corresponding RxDATA will be 0.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear it.
zBits 1:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit151413121110 9 8
AccessRRRRRRRR
Reset00000000
Bit76543210
BUFOVF
AccessRRRRRR/WRR
Reset00000000
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25.8.8 Synchronization Busy
Name: SYNCBUSY
Offset: 0x1C
Reset: 0x00000000
Property:
zBits 31:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 2– CTRLB: CTRLB Synchronization Busy
Writing CTRLB when the SERCOM is enabled requires synchronization. When written, the SYNCBUSY.CTRLB
bit will be set until synchronization is complete. If CTRLB is written while SYNCBUSY.CTRLB is asserted, an APB
error will be generated.
0: CTRLB synchronization is not busy.
1: CTRLB synchronization is busy.
zBit 1 – ENABLE: SERCOM Enable Synchronization Busy
Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the SYNC-
BUSY.ENABLE bit will be set until synchronization is complete.
Writes to any register (except for CTRLA.SWRST) while enable synchronization is on-going will be discarded and
an APB error will be generated.
0: Enable synchronization is not busy.
1: Enable synchronization is busy.
Bit3130292827262524
AccessRRRRRRRR
Reset00000000
Bit2322212019181716
AccessRRRRRRRR
Reset00000000
Bit151413121110 9 8
AccessRRRRRRRR
Reset00000000
Bit76543210
CTRLB ENABLE SWRST
AccessRRRRRRRR
Reset00000000
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zBit 0 – SWRST: Software Reset Synchronization Busy
Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the SYNCBUSY.SWRST bit
will be set until synchronization is complete.
Writes to any register while synchronization is on-going will be discarded and an APB error will be generated.
0: SWRST synchronization is not busy.
1: SWRST synchronization is busy.
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25.8.9 Address
Name: ADDR
Offset: 0x24
Reset: 0x00000000
Property: Write-Protected, Enable-Protected
zBits 31:24 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 23:16 – ADDRMASK[7:0]: Address Mask
These bits hold the address mask when the transaction format (CTRLA.FORM) with address is used.
zBits 15:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 7:0 – ADDR[7:0]: Address
These bits hold the address when the transaction format (CTRLA.FORM) with address is used.
Bit3130292827262524
AccessRRRRRRRR
Reset00000000
Bit2322212019181716
ADDRMASK[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
Bit151413121110 9 8
AccessRRRRRRRR
Reset00000000
Bit76543210
ADDR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
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25.8.10 Data
Name: DATA
Offset: 0x28
Reset: 0x0000
Property: –
zBits 15:9 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 8:0 – DATA[8:0]: Data
Reading these bits will return the contents of the receive data buffer. The register should be read only when the
Receive Complete Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.RXC) is set.
Writing these bits will write the transmit data buffer. This register should be written only when the Data Register
Empty Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.DRE) is set.
Bit151413121110 9 8
DATA[8]
AccessRRRRRRRR/W
Reset00000000
Bit76543210
DATA[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
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25.8.11 Debug Control
Name: DBGCTRL
Offset: 0x30
Reset: 0x00
Property: Write-Protected
zBits 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 0 – DBGSTOP: Debug Stop Mode
This bit controls the functionality when the CPU is halted by an external debugger.
0: The baud-rate generator continues normal operation when the CPU is halted by an external debugger.
1: The baud-rate generator is halted when the CPU is halted by an external debugger.
Bit76543210
DBGSTOP
AccessRRRRRRRR/W
Reset00000000
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26. SERCOM I2C – SERCOM Inter-Integrated Circuit
26.1 Overview
The inter-integrated circuit (I2C) interface is one of the available modes in the serial communication interface (SERCOM).
Refer to “SERCOM – Serial Communication Interface” on page 426 for details.
The I2C interface uses the SERCOM transmitter and receiver configured as shown in Figure 26-1. Fields shown in capital
letters are registers accessible by the CPU, while lowercase fields are internal to the SERCOM. Each side, master and
slave, depicts a separate I2C interface containing a shift register, a transmit buffer and a receive buffer. In addition, the
I2C master uses the SERCOM baud-rate generator, while the I2C slave uses the SERCOM address match logic.
26.2 Features
zMaster or slave operation
zCan be used with DMA
zPhilips I2C compatible
zSMBus™ compatible
zPMBus compatible
z100kHz and 400kHz, 1MHz and 3.4MHz support at low system clock frequencies
zPhysical interface includes:
zSlew-rate limited outputs
zFiltered inputs
zSlave operation:
zOperation in all sleep modes
zWake-up on address match
z7-bit and 10-bit Address match in hardware for:
zUnique address and/or 7-bit general call address
zAddress range
zTwo unique addresses can be used with DMA
26.3 Block Diagram
Figure 26-1. I2C Single-Master Single-Slave Interconnection
shift register shift register
Master Slave
SDA
SCL
Tx DATA
Rx DATA
Tx DATA
Rx DATA ==
ADDR/ADDRMASKBAUD
baud rate generator
0
0
0
0
SCL low hold
S
C
L
l
o
w
o
o
h
o
l
d
SCL low hold
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26.4 Signal Description
Refer to “I/O Multiplexing and Considerations” on page 12 for details on the pin mapping for this peripheral. One signal
can be mapped on several pins. Note that not all the pins are I2C pins. Refer to Table 5-1 for details on the pin type for
each pin.
26.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
26.5.1 I/O Lines
Using the SERCOM’s I/O lines requires the I/O pins to be configured. Refer to “PORT” on page 373 for details.
26.5.2 Power Management
The I2C will continue to operate in any sleep mode where the selected source clock is running. I2C interrupts can be used
to wake up the device from sleep modes. The events can trigger other operations in the system without exiting sleep
modes. Refer to “PM – Power Manager” on page 112 for details on the different sleep modes.
26.5.3 Clocks
The SERCOM bus clock (CLK_SERCOMx_APB, where i represents the specific SERCOM instance number) is enabled
by default, and can be enabled and disabled in the Power Manager. Refer to “PM – Power Manager” on page 112 for
details.
The SERCOM bus clock (CLK_SERCOMx_APB) is enabled by default, and can be enabled and disabled in the Power
Manager. Refer to “PM – Power Manager” on page 112 for details.
Two generic clocks are used by the SERCOM (GCLK_SERCOMx_CORE and GCLK_SERCOM_SLOW). The core clock
(GCLK_SERCOMx_CORE) is required to clock the SERCOM while operating as a master, while the slow clock
(GCLK_SERCOM_SLOW) is required only for certain functions. These clocks must be configured and enabled in the
Generic Clock Controller (GCLK) before using the SERCOM. Refer to “GCLK – Generic Clock Controller” on page 90 for
details.
These generic clocks are asynchronous to the SERCOM bus clock (CLK_SERCOMx_APB). Due to this asynchronicity,
writes to certain registers will require synchronization between the clock domains. Refer to the “Synchronization” on page
524 section for further details.
26.5.4 DMA
The DMA request lines are connected to the DMA controller (DMAC). Using the SERCOM DMA requests, requires the DMA
controller to be configured first. Refer to “DMAC – Direct Memory Access Controller” on page 267 for details.
26.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the I2C interrupts requires the Interrupt Controller
to be configured first. Refer to “Nested Vector Interrupt Controller” on page 29 for details.
Signal Name Type Description
PAD[0] Digital I/O SDA
PAD[1] Digital I/O SCL
PAD[2] Digital I/O SDA_OUT (4-wire)
PAD[3] Digital I/O SDC_OUT (4-wire)
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26.5.6 Events
Not applicable.
26.5.7 Debug Operation
When the CPU is halted in debug mode, the I2C interface continues normal operation. If the I2C interface is configured in
a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss
may result during debugging. The I2C interface can be forced to halt operation during debugging.
Refer to the DBGCTRL register for details.
26.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the
following registers:
zInterrupt Flag Status and Clear register (INTFLAG)
zStatus register (STATUS)
zAddress register (ADDR)
zData register (DATA)
Write-protection is denoted by the Write-Protected property in the register description.
Write-protection does not apply to accesses through en external debugger. Refer to“PAC – Peripheral Access Controller”
on page 36 for details.
26.5.9 Analog Connections
Not applicable.
26.6 Functional Description
26.6.1 Principle of Operation
The I2C interface uses two physical lines for communication:
zSerial Data Line (SDA) for packet transfer
zSerial Clock Line (SCL) for the bus clock
A transaction starts with the start condition, followed by a 7-bit address and a direction bit (read or write) sent from the I2C
master. The addressed I2C slave will then acknowledge (ACK) the address, and data packet transactions can
commence. Every 9-bit data packet consists of 8 data bits followed by a one-bit reply indicating whether the data was
acknowledged or not. In the event that a data packet is not acknowledged (NACK), whether sent from the I2C slave or
master, it will be up to the I2C master to either terminate the connection by issuing the stop condition, or send a repeated
start if more data is to be transceived.
Figure 26-2 illustrates the possible transaction formats and Figure 26-3 explains the legend used.
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Figure 26-2. Basic I2C Transaction Diagram
Figure 26-3. Transaction Diagram Syntax
26.6.2 Basic Operation
26.6.2.1 Initialization
The following registers are enable-protected, meaning they can be written only when the I2C interface is disabled
(CTRLA.ENABLE is zero):
zControl A register (CTRLA), except Enable (CTRLA.ENABLE) and Software Reset (CTRLA.SWRST)
zControl B register (CTRLB), except Acknowledge Action (CTRLB.ACKACT) and Command (CTRLB.CMD)
zBaud Rate register (BAUD)
zAddress register (ADDR) while in slave operation
PS ADDRESS
6 ... 0
R/W ACK ACK
7 ... 0
DATA ACK/NACK
7 ... 0
DATA
SDA
SCL
S A A/AR/WADDRESS DATA PA DATA
Address Packet Data Packet #0
Transaction
Data Packet #1
Direction
"0"
"1"
Master Drives Bus
Slave Drives Bus
Either Master or Slave
Drives Bus
S
Sr
P
START Condition
Repeated START Condition
STOP Condition
A
A
Acknowledge (ACK)
Not Acknowledge (NACK)
R
W
Master Read
Master Write
Data Packet Direction:
"0"
"1"
Acknowledge:
Bus Driver: Special Bus Conditions
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Any writes to these bits or registers when the I2C interface is enabled or is being enabled (CTRLA.ENABLE is one) will
be discarded. Writes to these registers while the I2C interface is being disabled will be completed after the disabling is
complete.
Enable-protection is denoted by the Enable-Protection property in the register description.
Before the I2C interface is enabled, it must be configured as outlined by the following steps:
I2C mode in master or slave operation must be selected by writing 0x4 or 0x5 to the Operating Mode bit group in the
Control A register (CTRLA.MODE)
zSCL low time-out can be enabled by writing to the SCL Low Time-Out bit in the Control A register
(CTRLA.LOWTOUT)
zIn master operation, the inactive bus time-out can be set in the Inactive Time-Out bit group in the Control A
register (CTRLA.INACTOUT)
zHold time for SDA can be set in the SDA Hold Time bit group in the Control A register (CTRLA.SDAHOLD)
zSmart operation can be enabled by writing to the Smart Mode Enable bit in the Control B register
(CTRLB.SMEN)
zIn slave operation, the address match configuration must be set in the Address Mode bit group in the
Control B register (CTRLB.AMODE)
zIn slave operation, the addresses must be set, according to the selected address configuration, in the
Address and Address Mask bit groups in the Address register (ADDR.ADDR and ADDR.ADDRMASK)
zIn master operation, the Baud Rate register (BAUD) must be written to generate the desired baud rate
26.6.2.2 Enabling, Disabling and Resetting
The I2C interface is enabled by writing a one to the Enable bit in the Control A register (CTRLA.ENABLE). The I2C
interface is disabled by writing a zero to CTRLA.ENABLE. The I2C interface is reset by writing a one to the Software
Reset bit in the Control A register (CTRLA.SWRST). All registers in the I2C interface, except DBGCTRL, will be reset to
their initial state, and the I2C interface will be disabled. Refer to CTRLA for details.
26.6.2.3 I2C Bus State Logic
The bus state logic includes several logic blocks that continuously monitor the activity on the I2C bus lines in all sleep
modes. The start and stop detectors and the bit counter are all essential in the process of determining the current bus
state. The bus state is determined according to the state diagram shown in Figure 26-4. Software can get the current bus
state by reading the Master Bus State bits in the Status register (STATUS.BUSSTATE). The value of
STATUS.BUSSTATE in the figure is shown in binary.
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Figure 26-4. Bus State Diagram
The bus state machine is active when the I2C master is enabled. After the I2C master has been enabled, the bus state is
unknown. From the unknown state, the bus state machine can be forced to enter the idle state by writing to
STATUS.BUSSTATE accordingly. However, if no action is taken by software, the bus state will become idle if a stop
condition is detected on the bus. If the inactive bus time-out is enabled, the bus state will change from unknown to idle on
the occurrence of a time-out. Note that after a known bus state is established, the bus state logic will not re-enter the
unknown state from either of the other states.
When the bus is idle it is ready for a new transaction. If a start condition is issued on the bus by another I2C master in a
multimaster setup, the bus becomes busy until a stop condition is detected. The stop condition will cause the bus to re-
enter the IDLE state. If the inactive bus time-out (SMBus) is enabled, the bus state will change from busy to idle on the
occurrence of a time-out. If a start condition is generated internally by writing the Address bit group in the Address
register (ADDR.ADDR) while in idle state, the owner state is entered. If the complete transaction was performed without
interference, i.e., arbitration not lost, the I2C master is allowed to issue a stop condition, which in turn will cause a change
of the bus state back to idle. However, if a packet collision is detected when in the owner state, the arbitration is assumed
lost and the bus state becomes busy until a stop condition is detected.
A repeated start condition will change the bus state only if arbitration is lost while issuing a repeated start.
26.6.2.4 Clock Generation (Standard-mode, Fast-mode and Fast-mode Plus Transfers)
The Master I2C clock (SCL) frequency is determined by a number of factors. The low (TLOW) and high (T_HIGH) times are
determined by the Baud Rate register (BAUD), while the rise (TRISE) and fall (TFALL) times are determined by the bus
topology. Because of the wired-AND logic of the bus, TFALL will be considered as part of TLOW. Likewise, TRISE will be in a
state between TLOW and THIGH until a high state has been detected.
P + Timeout
RESET
Wri te ADDR
(S)
IDLE
(0b01)
SBUSY
(0b11)
P + Ti meout
UNKNOWN
(0b00)
OWNER
(0b10)
Arbitration
Lost
Command P
Wri te ADDR (Sr)
Sr
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Figure 26-5. SCL Timing
The following parameters are timed using the SCL low time period. This comes from the Master Baud Rate Low bit group
in the Baud Rate register (BAUD.BAUDLOW) when non-zero, or the Master Baud Rate bit group in the Baud Rate
register (BAUD.BAUD) when BAUD.BAUDLOW is zero.
zTLOW – Low period of SCL clock
zTSU;STO – Set-up time for stop condition
zTBUF – Bus free time between stop and start conditions
zTHD;STA – Hold time (repeated) start condition
zTSU;STA – Set-up time for repeated start condition
zTHIGH is timed using the SCL high time count from BAUD.BAUD
zTRISE is determined by the bus impedance; for internal pull-ups. Refer to “Electrical Characteristics” on page
1055 for details.
zTFALL is determined by the open-drain current limit and bus impedance; can typically be regarded as zero.
Refer to “Electrical Characteristics” on page 1055 for details.
The SCL frequency is given by:
When BAUD.BAUDLOW is zero, the BAUD.BAUD value is used to time both SCL high and SCL low. In this case the
following formula will give the SCL frequency:
When BAUD.BAUDLOW is non-zero, the following formula is used to determine the SCL frequency:
T
HD;STA
T
LOW
T
HIGH
T
BUF
T
RISE
SCL
SDA
T
SU;STO
T
SU;STA
PS Sr
T
FALL
RISEHIGHLOW
SCL TTT
f++
=1
RISE
GCLK
GCLK
SCL TBAUD f
f
f++
=)5(2
RISE
GCLK
GCLK
SCL TBAUDLOWBAUD f
f
f+++
=10
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When BAUDLOW is non-zero, the following formula can be used to determine the SCL frequency:
The following formulas can be used to determine the SCL TLOW and THIGH times:
For Fast-mode Plus the nominal high to low SCL ratio is 1 to 2 and BAUD should be set accordingly. At a minimum,
BAUD.BAUD and/or BAUD.BAUDLOW must be non-zero.
26.6.2.5 Master Clock Generation (High-speed mode Transfer)
For High-speed mode transfers, there is no SCL synchronization, so the SCL frequency is determined by the GCLK
frequency and the High-speed BAUD setting. When HSBAUDLOW is zero, the HSBAUD value is used to time both SCL
high and SCL low. In this case the following formula can be used to determine the SCL frequency.
When HSBAUDLOW is non-zero, the following formula can be used to determine the SCL frequency.
For High-speed the nominal high to low SCL ratio is 1 to 2 and HSBAUD should be set accordingly. At a minimum, BAUD.BAUD
and/or BAUD.BAUDLOW must be non-zero.
26.6.2.6 I2C Master Operation
The I2C master is byte-oriented and interrupt based. The number of interrupts generated is kept at a minimum by
automatic handling of most events. Auto-triggering of operations and a special smart mode, which can be enabled by
writing a one to the Smart Mode Enable bit in the Control A register (CTRLA.SMEN), are included to reduce software
driver complexity and code size.
The I2C master has two interrupt strategies. When SCL Stretch Mode (CTRLA.SCLSM) is set to zero, SCL is stretched
before or after the acknowledge bit . In this mode the I2C master operates according to the behavior diagram shown in
Figure 26-6. The circles with a capital letter M followed by a number (M1, M2... etc.) indicate which node in the figure the
bus logic can jump to based on software or hardware interaction.
This diagram is used as reference for the description of the I2C master operation throughout the document.
RISE
GCLK
GCLK
SCL TBAUDLOWBAUD f
f
f+++
=10
GCLK
low f
BAUDLOWBAUD
T5. +
=
GCLK
HIGH f
BAUDBAUD
T5. +
=
)1(2 HSBAUD
f
fGCLK
SCL
+
=
HSBAUDLOWHSBAUD
f
fGCLK
SCL ++
=2
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Figure 26-6. I2C Master Behavioral Diagram (SCLSM=0)
In the second strategy (SCLSM=1), interrupts only occur after the ACK bit as shown in Figure 26-7. This strategy can be
used when it is not necessary to check DATA before acknowledging.
Note that setting SCLSM to 1 is required for High-speed mode.
IDLE SBUSYBUSY P
Sr
P
M3
M3
M2
M2
M1
M1
RDATA
ADDRESS
W
A/ADATA
Wait for
IDLE
APPLICATION
S
W
S
W
Sr
P
M3
M2
BUSY
M4
A
S
W
A/A
A/A
A/A
M4
A
IDLE
IDLE
MASTER READ INTERRUPT + SCL HOLD
MASTER WRITE INTERRUPT + SCL HOLD
S
W
S
W
S
W
BUSYR/W
S
WSoftware interaction
The master provides data
on the bus
Addressed slave provides
data on the bus
A
A
R/W
BUSY
M4
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Figure 26-7. I2C Master Behavioral Diagram (SCLSM=1)
Transmitting Address Packets
The I2C master starts a bus transaction by writing ADDR.ADDR with the I2C slave address and the direction bit. If the bus
is busy, the I2C master will wait until the bus becomes idle before continuing the operation. When the bus is idle, the I2C
master will issue a start condition on the bus. The I2C master will then transmit an address packet using the address
written to ADDR.ADDR.
After the address packet has been transmitted by the I2C master, one of four cases will arise, based on arbitration and
transfer direction.
Case 1: Arbitration lost or bus error during address packet transmission
If arbitration was lost during transmission of the address packet, the Master on Bus bit in the Interrupt Flag register
(INTFLAG.MB) and the Arbitration Lost bit in the Status register (STATUS.ARBLOST) are both set. Serial data output to
SDA is disabled, and the SCL is released, which disables clock stretching. In effect the I2C master is no longer allowed to
perform any operation on the bus until the bus is idle again. A bus error will behave similarly to the arbitration lost
condition. In this case, the MB interrupt flag and Master Bus Error bit in the Status register (STATUS.BUSERR) are both
set in addition to STATUS.ARBLOST.
The Master Received Not Acknowledge bit in the Status register (STATUS.RXNACK) will always contain the last
successfully received acknowledge or not acknowledge indication.
In this case, software will typically inform the application code of the condition and then clear the interrupt flag before
exiting the interrupt routine. No other flags have to be cleared at this point, because all flags will be cleared automatically
the next time the ADDR.ADDR register is written.
Case 2: Address packet transmit complete – No ACK received
If no I2C slave device responds to the address packet, then the INTFLAG.MB interrupt flag is set and STATUS.RXNACK
is set. The clock hold is active at this point, preventing further activity on the bus.
The missing ACK response can indicate that the I2C slave is busy with other tasks or sleeping and, therefore, not able to
respond. In this event, the next step can be either issuing a stop condition (recommended) or resending the address
IDLE SBUSYBUSY P
Sr
P
M3
M3
M2
M2
M1
M1
RDATA
ADDRESS
W
A/ADATA
Wait for
IDLE
APPLICATION
S
W
S
W
Sr
P
M3
M2
BUSY
M4
S
W
A/A
M4
A
IDLE
IDLE
MASTER READ INTERRUPT + SCL HOLD
MASTER WRITE INTERRUPT + SCL HOLD
S
W
S
W
S
W
BUSYR/W
S
WSoftware interaction
The master provides data
on the bus
Addressed slave provides
data on the bus
A
A
R/W
BUSY
M4
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packet by using a repeated start condition. However, the reason for the missing acknowledge can be that an invalid I2C
slave address has been used or that the I2C slave is for some reason disconnected or faulty. If using SMBus logic, the
slave must ACK the address, and hence no action means the slave is not available on the bus.
Case 3: Address packet transmit complete – Write packet, Master on Bus set
If the I2C master receives an acknowledge response from the I2C slave, INTFLAG.MB is set and STATUS.RXNACK is
cleared. The clock hold is active at this point, preventing further activity on the bus.
In this case, the software implementation becomes highly protocol dependent. Three possible actions can enable the I2C
operation to continue. The three options are:
zThe data transmit operation is initiated by writing the data byte to be transmitted into DATA.DATA.
zTransmit a new address packet by writing ADDR.ADDR. A repeated start condition will automatically be
inserted before the address packet.
zIssue a stop condition, consequently terminating the transaction.
Case 4: Address packet transmit complete – Read packet, Slave on Bus set
If the I2C master receives an ACK from the I2C slave, the I2C master proceeds to receive the next byte of data from the
I2C slave. When the first data byte is received, the Slave on Bus bit in the Interrupt Flag register (INTFLAG.SB) is set and
STATUS.RXNACK is cleared. The clock hold is active at this point, preventing further activity on the bus.
In this case, the software implementation becomes highly protocol dependent. Three possible actions can enable the I2C
operation to continue. The three options are:
zLet the I2C master continue to read data by first acknowledging the data received. This is automatically done
when reading DATA.DATA if the smart mode is enabled.
zTransmit a new address packet.
zTerminate the transaction by issuing a stop condition.
An ACK or NACK will be automatically transmitted for the last two alternatives if smart mode is enabled. The
Acknowledge Action bit in the Control B register (CTRLB.ACKACT) determines whether ACK or NACK should be sent.
Transmitting Data Packets
When an address packet with direction set to write has been successfully transmitted, INTFLAG.MB will be set and the
I2C master can start transmitting data by writing to DATA.DATA. The I2C master transmits data via the I2C bus while
continuously monitoring for packet collisions. If a collision is detected, the I2C master looses arbitration and
STATUS.ARBLOST is set. If the transmit was successful, the I2C master automatically receives an ACK bit from the I2C
slave and STATUS.RXNACK will be cleared. INTFLAG.MB will be set in both cases, regardless of arbitration outcome.
Testing STATUS.ARBLOST and handling the arbitration lost condition in the beginning of the I2C Master on Bus interrupt
is recommended. This can be done, as there is no difference between handling address and data packet arbitration.
STATUS.RXNACK must be checked for each data packet transmitted before the next data packet transmission can
commence. The I2C master is not allowed to continue transmitting data packets if a NACK is given from the I2C slave.
Receiving Data Packets (SCLSM=0)
When INTFLAG.SB is set, the I2C master will already have received one data packet. The I2C master must respond by
sending either an ACK or NACK. Sending a NACK might not be successfully executed as arbitration can be lost during
the transmission. In this case, a loss of arbitration will cause INTFLAG.SB to not be set on completion. Instead,
INTFLAG.MB will be used to indicate a change in arbitration. Handling of lost arbitration is the same as for data bit
transmission.
Receiving Data Packets (SCLSM=1)
When INTFLAG.SB is set, the I2C master will already have received one data packet and transmitted the ACKACT bit. At
this point the ACKACT must be set to the correct value for the next ACK bit, and the transaction can continue by reading
DATA and issuing a command if not in smart mode.
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High-speed Mode
High-speed transfers are a multi-step process as shown in Figure 26-8. First, a master code (0000 1nnn where nnn is a
unique master code) is transmitted in Full-speed mode, followed by a NACK since no slave should acknowledge.
Arbitration is performed only during the Full-speed Master Code phase. The master code is transmitted by writing the
master code to the address register (ADDR) with the high-speed bit (ADDR.HS) written to zero.
After the Master Code and NACK have been transmitted, the master write interrupt will be asserted. At this point,
the slave address can be written to the ADDR register with the ADDR.HS bit set to one. The master will then generate a
repeated start followed by the slave address in High-speed mode. The bus will remain in High-speed mode until a stop is
generated. If a repeated start is desired, the ADDR.HS bit must again be written to 1 along with the new address to be
transmitted.
Figure 26-8. High Speed Transfer
Transmitting in High-speed mode requires the I2C master to be configured in High-speed mode (SPEED=0b10) and the
SCL clock stretch mode (SCLSM) bit set to one.
10-Bit Addressing
When 10-bit addressing is enabled (TENBITEN=1) and the ADDR register is written, the two address bytes will be
transmitted as shown in Figure 26-9. The addressed slave acknowledges the two address bytes and the transaction
continues. Regardless of whether the transaction is a read or write, the master must start by sending the 10-bit address
with the read/write bit (ADDR.ADDR[0]) equal to zero.
If the master receives a NACK after the first byte, then the write interrupt flag will be raised and the NACK bit will be set.
If the first byte is acknowledged by one or more slaves, then the master will proceed to transmit the second address byte
and the master will first see the write interrupt flag after the second byte is transmitted.
If the transaction is a read, the 10-bit address transmission must be followed by a repeated start and the first 7 bits of the
address with the read/write bit equal to 1.
Figure 26-9. 10-Bit Address Transmission for a Read Transaction
This implies the following procedure for a 10-bit read operation:
zWrite ADDR.ADDR[10:1] with the 10-bit address. ADDR.TENBITEN must be set (can be written simultaneously
with ADDR) and read/write bit (ADDR.ADDR[0]) equal to 0.
zWhen the master write interrupt is asserted, write ADDR[7:0] register to “11110 address[9:8] 1”. ADDR.TENBITEN
must be cleared (can be written simultaneously with ADDR).
zProceed to transmit data.
SAA/A
Sr PA DATA
N Data Packets
Master Code R/W
ADDRESS
Sr ADDRESS
Hs-mode continues
F/S-mode
Hs-mode
F/S-mode
S AW addr[7:0] A
11110 addr[9:8] Sr AR
1
S
W
MASTER WRITE INTERRUPT
11110 addr[9:8]
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26.6.2.7 I2C Slave Operation
The I2C slave is byte-oriented and interrupt-based. The number of interrupts generated is kept at a minimum by
automatic handling of most events. Auto triggering of operations and a special smart mode, which can be enabled by
writing a 1 to the Smart Mode Enable bit in the Control A register (CTRLA.SMEN), are included to reduce software’s
complexity and code size.
The I2C slave has two interrupt strategies. When SCL Stretch Mode (CTRLA.SCLSM) is set to zero, SCL is stretched
before or after the acknowledge bit. In this mode, the I2C slave operates according to the behavior diagram shown in
Figure 26-10. The circles with a capital S followed by a number (S1, S2... etc.) indicate which node in the figure the bus
logic can jump to based on software or hardware interaction.
This diagram is used as reference for the description of the I2C slave operation throughout the document.
Figure 26-10.I2C Slave Behavioral Diagram (SCLSM=0)
In the second strategy (SCLSM=1), interrupts only occur after the ACK bit as shown in Figure 26-11. This strategy can be
used when it is not necessary to check DATA before acknowledging. For master reads, an address and data interrupt will
be issued simultaneously after the address acknowledge, while for master writes, the first data interrupt will be seen after
the first data byte has been received by the slave and the acknowledge bit has been sent to the master.
Note that setting SCLSM to 1 is required for High-speed mode.
S
S3
ADDRESS
S2
A
S1
R
W
DATA A/A
DATA
P
S2
Sr
S3
P
S2
Sr
S3
SLAVE ADDRESS INTERRUPT SLAVE DATA INTERRUPT
A
S
W
S
W
S
W
S
W
AA/A
A
S1
S
W
Interrupt on STOP
Condition Enabled
S1
SLAVE STOP INTERRUPT
S
WSoftware interaction
The master provides data
on the bus
Addressed slave provides
data on the bus
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Figure 26-11.Slave Behavioral Diagram (SCLSM=1)
Receiving Address Packets (SCLSM=0)
When SCLSM is zero, the I2C slave stretches the SCL line according to Figure 26-10. When the I2C slave is properly
configured, it will wait for a start condition to be detected. When a start condition is detected, the successive address
packet will be received and checked by the address match logic. If the received address is not a match, the packet is
rejected and the I2C slave waits for a new start condition. The I2C slave Address Match bit in the Interrupt Flag register
(INTFLAG.AMATCH) is set when a start condition followed by a valid address packet is detected. SCL will be stretched
until the I2C slave clears INTFLAG.AMATCH. Because the I2C slave holds the clock by forcing SCL low, the software is
given unlimited time to respond to the address.
The direction of a transaction is determined by reading the Read / Write Direction bit in the Status register
(STATUS.DIR), and the bit will be updated only when a valid address packet is received.
If the Transmit Collision bit in the Status register (STATUS.COLL) is set, this indicates that the last packet addressed to
the I2C slave had a packet collision. A collision causes the SDA and SCL lines to be released without any notification to
software. The next AMATCH interrupt is, therefore, the first indication of the previous packet’s collision. Collisions are
intended to follow the SMBus Address Resolution Protocol (ARP).
After the address packet has been received from the I2C master, one of two cases will arise based on transfer direction.
Case 1: Address packet accepted – Read flag set
The STATUS.DIR bit is one, indicating an I2C master read operation. The SCL line is forced low, stretching the bus clock.
If an ACK is sent, I2C slave hardware will set the Data Ready bit in the Interrupt Flag register (INTFLAG.DRDY),
indicating data are needed for transmit. If not acknowledge is sent, the I2C slave will wait for a new start condition and
address match.
Typically, software will immediately acknowledge the address packet by sending an ACK/NACK bit. The I2C slave
command CTRLB.CMD = 3 can be used for both read and write operation as the command execution is dependent on
the STATUS.DIR bit.
Writing a one to INTFLAG.AMATCH will also cause an ACK/NACK to be sent corresponding to the CTRLB.ACKACT bit.
Case 2: Address packet accepted – Write flag set
The STATUS.DIR bit is cleared, indicating an I2C master write operation. The SCL line is forced low, stretching the bus
clock. If an ACK is sent, the I2C slave will wait for data to be received. Data, repeated start or stop can be received.
S
S3
ADDRESS
S2
R
W
DATA A/A
DATA
P
S2
Sr
S3
P
S2
Sr
S3
SLAVE ADDRESS INTERRUPT SLAVE DATA INTERRUPT
S
W
S
W
S
W
A/A
S
W
Interrupt on STOP
Condition Enabled
S1
SLAVE STOP INTERRUPT
S
WSoftware interaction
The master provides data
on the bus
Addressed slave provides
data on the bus
A/A
A/A
SLAVE DATA INTERRUPT in Master read mode
)
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If not acknowledge is sent, the I2C slave will wait for a new start condition and address match.
Typically, software will immediately acknowledge the address packet by sending an ACK/NACK bit. The I2C slave
command CTRLB.CMD = 3 can be used for both read and write operation as the command execution is dependent on
STATUS.DIR.
Writing a one to INTFLAG.AMATCH will also cause an ACK/NACK to be sent corresponding to the CTRLB.ACKACT bit.
Receiving Address Packets (SCLSM=1)
When SCLSM is one, the I2C slave only stretches the SCL line after an acknowledge according to Figure 26-11. When
the I2C slave is properly configured, it will wait for a start condition to be detected. When a start condition is detected, the
successive address packet will be received and checked by the address match logic. If the received address is not a
match, the packet is rejected and the I2C slave waits for a new start condition. If the address matches, the acknowledge
action (CTRLB.ACKACT) is automatically sent and the Address Match bit in the Interrupt Flag register
(INTFLAG.AMATCH) is set. SCL will be stretched until the I2C slave clears INTFLAG.AMATCH. Because the I2C slave
holds the clock by forcing SCL low, the software is given unlimited time to respond to the address.
The direction of a transaction is determined by reading the Read / Write Direction bit in the Status register
(STATUS.DIR), and the bit will be updated only when a valid address packet is received.
If the Transmit Collision bit in the Status register (STATUS.COLL) is set, this indicates that the last packet addressed to
the I2C slave had a packet collision. A collision causes the SDA and SCL lines to be released without any notification to
software. The next AMATCH interrupt is, therefore, the first indication of the previous packet’s collision. Collisions are
intended to follow the SMBus Address Resolution Protocol (ARP).
After the address packet has been received from the I2C master, a one can be written to INTFLAG.AMATCH to clear it.
Receiving and Transmitting Data Packets (SCLSM=0)
After the I2C slave has received an address packet, it will respond according to the direction either by waiting for the data
packet to be received or by starting to send a data packet by writing to DATA.DATA. When a data packet is received or
sent, INTFLAG.DRDY will be set. Then, if the I2C slave was receiving data, it will send an acknowledge according to
CTRLB.ACKACT.
Case 1: Data received
INTFLAG.DRDY is set, and SCL is held low pending SW interaction.
Case 2: Data sent
When a byte transmission is successfully completed, the INTFLAG.DRDY interrupt flag is set. If NACK is received, the
I2C slave must expect a stop or a repeated start to be received. The I2C slave must release the data line to allow the I2C
master to generate a stop or repeated start.
Upon stop detection, the Stop Received bit in the Interrupt Flag register (INTFLAG.PREC) will be set and the I2C slave
will return to the idle state.
High Speed Mode
When the I2C slave is configured in High-speed mode (CTRLA.SPEED=0x2) with SCLSM set to one, switching between
Full-speed and High-speed modes is automatic. When the slave recognizes a START followed by a master code
transmission and a NACK, it automatically switches to High-speed mode and sets the High-speed status bit
(STATUS.HS). The slave will then remain in High-speed mode until a STOP is received.
10-Bit Addressing
When 10-bit addressing is enabled (ADDR.TENBITEN=1) the two address bytes following a START will be checked
against the 10-bit slave address recognition. The first byte of the address will always be acknowledged and the second
byte will raise the address interrupt flag as shown in Figure 26-12.
If the transaction is a write, then the 10-bit address will be followed by N data bytes.
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If the operation is a read, the 10-bit address will be followed by a repeated START and reception of “11110 ADDR[9:8] 1”
and the second address interrupt will be received with the DIR bit set. The slave matches on the second address as it
remembers that is was addressed by the previous 10-bit address.
Figure 26-12.10-bit Addressing
PMBus Group Command
When the group command bit is set (CTRLB.GCMD) and 7-bit addressing is used, a STOP interrupt will be generated if
the slave has been addressed since the last STOP condition.
The group command protocol is used to send commands to more than one device. The commands are sent in one
continuous transmission with a single STOP condition at the end. When the STOP condition is detected by the slaves
addressed during the group command, they all begin executing the command they received.
Figure 26-13 shows an example where this slave is addressed by ADDRESS 1. This slave is addressed after a repeated
START condition. There can be multiple slaves addressed before and after, then at the end of the group command, a
single STOP is generated by the master. At this point a STOP interrupt is asserted.
Figure 26-13.PMBus Group Command Example
26.6.3 Additional Features
26.6.3.1 SMBus
The I2C hardware incorporates three hardware SCL low time-outs which allows a time-out to occur for SMBus SCL low
time-out, master extend time-out, and slave extend time-out. These time-outs are driven by the GCLK_SERCOM_SLOW
clock. The GCLK_SERCOM_SLOW clock is used to accurately time the time-out and must be configured to used a
32kHz oscillator. The I2C interface also allows for an SMBus compatible SDA hold time.
zTTIMEOUT
: SCL low time of 25-35 ms. – Measured for a single SCL low period. Enabled by bit
CTRLA.LOWTOUTEN.
S AW addr[7:0] A
11110 addr[9:8] Sr R
S
W
SLAVE ADDRESS
INTERRUPT
S
W
SLAVE ADDRESS
INTERRUPT
11110 addr[9:8]
A
SAn Bytes
W
ADDRESS 0
Command/Data
A
Sr An Bytes
W
ADDRESS 1
(this slave)
Command/Data
S
W
SLAVE ADDRESS
INTERRUPT
S
W
SLAVE DATA
INTERRUPT
A
Sr An Bytes
W
ADDRESS 2
Command/Data
P
S
W
SLAVE STOP
INTERRUPT
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zTLOW:SEXT
:Cumulative clock low extend time of 25 ms – Measured as the cumulative SCL low extend time by a
slave device in a single message from the initial START to the STOP. Enabled by bit CTRLA.SEXTTOEN.
zTLOW:MEXT
: Cumulative clock low extend time of 10 ms. – Measured as the cumulative SCL low extend time by
the master device within a single byte from START-to-ACK, ACK-to-ACK, or ACK-to-STOP. Enabled by bit
(CTRLA.MEXTTOEN.
26.6.3.2 Smart Mode
The I2C interface incorporates a special smart mode that simplifies application code and minimizes the user interaction
needed to keep hold of the I2C protocol. The smart mode accomplishes this by letting the reading of DATA.DATA
automatically issue an ACK or NACK based on the state of CTRLB.ACKACT.
26.6.3.3 4-Wire Mode
Setting the Pin Usage bit in the Control A register (CTRLA.PINOUT) for master or slave to 4-wire mode enables
operation as shown in Figure 26-14. In this mode, the internal I2C tri-state drivers are bypassed, and an external, I2C-
compliant tri-state driver is needed when connecting to an I2C bus.
Figure 26-14.I2C Pad Interface
26.6.3.4 Quick Command
Setting the Quick Command Enable bit in the Control B register (CTRLB.QCEN) enables quick command. When quick
command is enabled, the corresponding interrupt flag is set immediately after the slave acknowledges the address. At
this point, the software can either issue a stop command or a repeated start by writing CTRLB.CMD or ADDR.ADDR.
SCL/SDA
pad
I2C
Driver
SCL_OUT/
SDA_OUT
pad
PINOUT
PINOUT
SCL_IN/
SDA_IN
SCL_OUT/
SDA_OUT
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26.6.4 DMA, Interrupts and Events
26.6.4.1 DMA Operation
Smart mode (CTRLB.SMEN) must be enabled for DMA operation.
Slave DMA
When using the I2C slave with DMA, an address match will cause the address interrupt flag (INTFLAG.ADDRMATCH) to
be raised. After the interrupt has been serviced, data transfer will be performed through DMA.
The I2C slave generates the following requests:
zWrite data received (RX): The request is set when master write data is received. The request is cleared when
DATA is read.
zRead data needed for transmit (TX): The request is set when data is needed for a master read operation. The
request is cleared when DATA is written.
Master DMA
When using the I2C master with DMA, the ADDR register must be written with the desired address (ADDR.ADDR),
transaction length (ADDR.LEN), and transaction length enable (ADDR.LENEN). When ADDR.LENEN is written to 1
Table 26-1. Module Request for SERCOM I2C Slave
Condition Interrupt request Event output Event input DMA request
DMA request is
cleared
Data Ready x
Data received
(Slave receive
mode)
xwhen data is
read
Data needed for
transmit (Slave
transmit mode)
xwhen data is
written
Address Match x
Stop received x
Error x
Table 26-2. Module Request for SERCOM I2C Master
Condition Interrupt request Event output Event input DMA request
DMA request is
cleared
Master on Bus x
Slave on Bus x
Data received
(Master receive
mode)
xwhen data is
read
Data needed for
transmit (Master
transmit mode)
xwhen data is
written
Error x
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along with ADDR.ADDR, ADDR.LEN determines the number of data bytes in the transaction from 0 to 255. DMA is then
used to transfer ADDR.LEN bytes followed by an automatically generated NACK (for master reads) and a STOP.
If a NACK is received by the slave for a master write transaction before ADDR.LEN bytes, a STOP will be automatically
generated and the length error (STATUS.LENERR) will be raised along with the INTFLAG.ERROR interrupt.
The I2C master generates the following requests:
zRead data received (RX): The request is set when master read data is received. The request is cleared when
DATA is read.
zWrite data needed for transmit (TX): The request is set when data is needed for a master write operation. The
request is cleared when DATA is written.
26.6.4.2 Interrupts
The I2C slave has the following interrupt sources:
zError (ERROR): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode.
zData Ready (DRDY): this is an asynchronous interrupt and can be used to wake-up the device from any sleep
mode.
zAddress Match (AMATCH): this is an asynchronous interrupt and can be used to wake-up the device from any
sleep mode.
zStop Received (PREC): this is an asynchronous interrupt and can be used to wake-up the device from any sleep
mode.
The I2C master has the following interrupt sources:
zError (ERROR): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode.
zSlave on Bus (SB): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode.
zMaster on Bus (MB): this is an asynchronous interrupt and can be used to wake-up the device from any sleep
mode.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one
to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is
cleared, the interrupt is disabled or the I2C is reset. See INTFLAG for details on how to clear interrupt flags.
The I2C has one common interrupt request line for all the interrupt sources. The user must read INTFLAG to determine
which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to “Nested Vector Interrupt
Controller” on page 29 for details.
26.6.4.3 Events
Not applicable.
26.6.5 Sleep Mode Operation
During I2C master operation, the generic clock (GCLK_SERCOMx_CORE) will continue to run in idle sleep mode. If the
Run In Standby bit in the Control A register (CTRLA.RUNSTDBY) is one, the GLK_SERCOMx_CORE will also run in
standby sleep mode. Any interrupt can wake up the device.
If CTRLA.RUNSTDBY is zero during I2C master operation, the GLK_SERCOMx_CORE will be disabled when an
ongoing transaction is finished. Any interrupt can wake up the device.
During I2C slave operation, writing a one to CTRLA.RUNSTDBY will allow the Address Match interrupt to wake up the
device.
In I2C slave operation, all receptions will be dropped when CTRLA.RUNSTDBY is zero.
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26.6.6 Synchronization
Due to the asynchronicity between CLK_SERCOMx_APB and GCLK_SERCOMx_CORE, some registers must be
synchronized when accessed. A register can require:
zSynchronization when written
zSynchronization when read
zSynchronization when written and read
zNo synchronization
When executing an operation that requires synchronization, the corresponding Synchronization Busy bit in the
Synchronization Busy register (SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
If an operation that requires synchronization is executed while the corresponding SYNCBUSY bit is one, a peripheral bus
error is generated.
The following bits need synchronization when written:
zSoftware Reset bit in the Control A register (CTRLA.SWRST). SYNCBUSY.SWRST is set to one while
synchronization is in progress.
zEnable bit in the Control A register (CTRLA.ENABLE). SYNCBUSY.ENABLE is set to one while
synchronization is in progress.
zWrite to Bus State bits in the Status register (STATUS.BUSSTATE). SYNCBUSY.SYSOP is set to one while
synchronization is in progress.
zAddress bits in the Address register (ADDR.ADDR) when in master operation. SYNCBUSY.SYSOP is set to
one while synchronization is in progress.
zData (DATA) when in master operation. SYNCBUSY.SYSOP is set to one while synchronization is in
progress.
Write-synchronization is denoted by the Write-Synchronized property in the register description.
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26.7 Register Summary
Table 26-3. Register Summary – Slave Mode
Offset Name
Bit
Pos.
0x00
CTRLA
7:0 RUNSTDBY MODE[2:0]=100 ENABLE SWRST
0x01 15:8
0x02 23:16 SEXTTOEN SDAHOLD[1:0] PINOUT
0x03 31:24 LOWTOUT SCLSM SPEED[1:0]
0x04
CTRLB
7:0
0x05 15:8 AMODE[1:0] AACKEN GCMD SMEN
0x06 23:16 ACKACT CMD[1:0]
0x07 31:24
0x08 Reserved
... Reserved
0x13 Reserved
0x14 INTENCLR 7:0 ERROR DRDY AMATCH PREC
0x15 Reserved
0x16 INTENSET 7:0 ERROR DRDY AMATCH PREC
0x17 Reserved
0x18 INTFLAG 7:0 ERROR DRDY AMATCH PREC
0x19 Reserved
0x1A
STATUS
7:0 CLKHOLD LOWTOUT SR DIR RXNACK COLL BUSERR
0x1B 15:8 SYNCBUSY HS SEXTTOUT
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0x1C
SYNCBUSY
7:0 ENABLE SWRST
0x1D 15:8
0x1E 23:16
0x1F 31:24
0x20 Reserved
0x21 Reserved
0x22 Reserved
0x23 Reserved
0x24
ADDR
7:0 ADDR[6:0] GENCEN
0x25 15:8 TENBITEN ADDR[9:7]
0x26 23:16 ADDRMASK[6:0]
0x27 31:24 ADDRMASK[9:7]
0x28
DATA
7:0 DATA[7:0]
0x29 15:8
Table 26-3. Register Summary – Slave Mode (Continued)
Offset Name
Bit
Pos.
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Table 26-4. Register Summary – Master Mode
Offset Name
Bit
Pos
0x00
CTRLA
7:0 RUNSTDBY MODE[2:0]=101 ENABLE SWRST
0x01 15:8
0x02 23:16 SEXTTOEN MEXTTOEN SDAHOLD[1:0] PINOUT
0x03 31:24 LOWTOUT INACTOUT[1:0] SCLSM SPEED[1:0]
0x04
CTRLB
7:0
0x05 15:8 QCEN SMEN
0x06 23:16 ACKACT CMD[1:0]
0x07 31:24
0x08 Reserved
0x09 Reserved
0x0A Reserved
0x0B Reserved
0x0C
BAUD
7:0 BAUD[7:0]
0x0D 15:8 BAUDLOW[7:0]
0x0E 23:16 HSBAUD[7:0]
0x0F 31:24 HSBAUDLOW[7:0]
0x10 Reserved
0x11 Reserved
0x12 Reserved
0x13 Reserved
0x14 INTENCLR 7:0 ERROR SB MB
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0x15 Reserved
0x16 INTENSET 7:0 ERROR SB MB
0x17 Reserved
0x18 INTFLAG 7:0 ERROR SB MB
0x19 Reserved
0x1A
STATUS
7:0 CLKHOLD LOWTOUT BUSSTATE[1:0] RXNACK ARBLOST BUSERR
0x1B 15:8 LENERR SEXTTOUT MEXTTOUT
0x1C
SYNCBUS
Y
7:0 SYSOP ENABLE SWRST
0x1D 15:8
0x1E 23:16
0x1F 31:24
0x20 Reserved
0x21 Reserved
0x22 Reserved
0x23 Reserved
Table 26-4. Register Summary – Master Mode (Continued)
Offset Name
Bit
Pos
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0x24
ADDR
7:0 ADDR[7:0]
0x25 15:8 TENBITEN HS LENEN ADDR[10:8]
0x26 23:16 LEN[7:0]
0x27 31:24
0x28
DATA
7:0 DATA[7:0]
0x29 15:8
0x2A Reserved
... Reserved
0x2F Reserved
0x30 DBGCTRL 7:0 DBGSTOP
Table 26-4. Register Summary – Master Mode (Continued)
Offset Name
Bit
Pos
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26.8 Register Description
Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters
and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by
the Write-Protected property in each individual register description. Please refer to“Register Access Protection” on page
507 for details.
Some registers require synchronization when read and/or written. Synchronization is denoted by the Write-Synchronized
or the Read-Synchronized property in each individual register description. Please refer to “Synchronization” on page 524
for details.
Some registers are enable-protected, meaning they can only be written when the I2C is disabled. Enable-protection is
denoted by the Enable-Protected property in each individual register description.
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26.8.1 I2C Slave Register Description
26.8.1.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00000000
Property: Write-Protected, Enable-Protected, Write-Synchronized
zBit 31 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 30 – LOWTOUT: SCL Low Time-Out
This bit enables the SCL low time-out. If SCL is held low for 25ms-35ms, the slave will release its clock hold, if
enabled, and reset the internal state machine. Any interrupts set at the time of time-out will remain set.
0: Time-out disabled.
1: Time-out enabled.
zBits 29:28 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 27– SCLSM: SCL Clock Stretch Mode
This bit controls when SCL will be stretch for software interaction.
0: SCL stretch according to Figure 26-7
Bit3130292827262524
LOWTOUT SCLSM SPEED[1:0]
Access R R/W R R R/W R R/W R/W
Reset00000000
Bit2322212019181716
SEXTTOEN SDAHOLD[1:0] PINOUT
Access R/W R R/W R/W R R R R/W
Reset00000000
Bit 15 14 13 12 11 10 9 8
AccessRRRRRRRR
Reset00000000
Bit76543210
RUNSTDBY MODE[2:0]=100 ENABLE SWRST
Access R/W R R R/W R/W R/W R/W R/W
Reset00000000
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1: SCL stretch only after ACK bit according to Figure 26-10.
This bit is not synchronized.
zBit 26– Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 25:24 – SPEED[1:0]: Transfer Speed
These bits define bus speed.
Table 26-5. Transfer Speed
These bits are not synchronized.
zBit 23 – SEXTTOEN: Slave SCL Low Extend Time-Out
This bit enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms
from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state
machine. Any interrupts set at the time of time-out will remain set. If the address was recognized, PREC will
be set when a STOP is received.
0: Time-out disabled
1: Time-out enabled
This bit is not synchronized.
zBit 22 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 21:20 – SDAHOLD[1:0]: SDA Hold Time
These bits define the SDA hold time with respect to the negative edge of SCL.
Table 26-6. SDA Hold Time
These bits are not synchronized.
zBits 19:17 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Value Description
0x0 Standard-mode (Sm) up to 100 kHz and Fast-mode (Fm) up to 400 kHz
0x1 Fast-mode Plus (Fm+) up to 1 MHz
0x2 High-speed mode (Hs-mode) up to 3.4 MHz
0x3 Reserved
Value Name Description
0x0 DIS Disabled
0x1 75 50-100ns hold time
0x2 450 300-600ns hold time
0x3 600 400-800ns hold time
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zBit 16 – PINOUT: Pin Usage
This bit sets the pin usage to either two- or four-wire operation:
0: 4-wire operation disabled
1: 4-wire operation enabled
This bit is not synchronized.
zBits 15:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 7 – RUNSTDBY: Run in Standby
This bit defines the functionality in standby sleep mode.
0: Disabled – All reception is dropped.
1: Wake on address match, if enabled.
This bit is not synchronized.
zBits 6:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 4:2 – MODE[2:0]: Operating Mode
These bits must be written to 0x04 to select the I2C slave serial communication interface of the SERCOM.
These bits are not synchronized.
zBit 1 – ENABLE: Enable
0: The peripheral is disabled.
1: The peripheral is enabled.
Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRL.ENABLE will read back immediately and the Enable Synchronization Busy bit in the Syn-
chronization busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the
operation is complete.
This bit is not enable-protected.
zBit 0 – SWRST: Software Reset
0: There is no reset operation ongoing.
1: The reset operation is ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SER-
COM will be disabled.
Writing a one to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-oper-
ation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading
any register will return the reset value of the register.
Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST
and SYNCBUSY.SWRST will both be cleared when the reset is complete.
This bit is not enable-protected.
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26.8.1.2 Control B
Name: CTRLB
Offset: 0x04
Reset: 0x00000000
Property: Write-Protected, Enable-Protected, Write-Synchronized
zBits 31:19 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 18 – ACKACT: Acknowledge Action
0: Send ACK
1: Send NACK
The Acknowledge Action (ACKACT) bit defines the slave's acknowledge behavior after an address or data byte is
received from the master. The acknowledge action is executed when a command is written to the CMD bits. If
smart mode is enabled (CTRLB.SMEN is one), the acknowledge action is performed when the DATA register is
read.
This bit is not enable-protected.
zBits 17:16 – CMD[1:0]: Command
Writing the Command bits (CMD) triggers the slave operation as defined in Table 26-7. The CMD bits are strobe
bits, and always read as zero. The operation is dependent on the slave interrupt flags, INTFLAG.DRDY and INT-
FLAG.AMATCH, in addition to STATUS.DIR (See Table 26-7).
Bit3130292827262524
AccessRRRRRRRR
Reset00000000
Bit2322212019181716
ACKACT CMD[1:0]
AccessRRRRRR/WR/WR/W
Reset00000000
Bit151413121110 9 8
AMODE[1:0] AACKEN GCMD SMEN
Access R/W R/W R R R R/W R/W R/W
Reset00000000
Bit76543210
AccessRRRRRRRR
Reset00000000
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All interrupt flags (INTFLAG.DRDY, INTFLAG.AMATCH and INTFLAG.PREC) are automatically cleared when a
command is given.
This bit is not enable-protected.
Table 26-7. Command Description
zBits 15:14 – AMODE[1:0]: Address Mode
These bits set the addressing mode according to Table 26-8.
Table 26-8. Address Mode Description
Note: 1. See “SERCOM – Serial Communication Interface” on page 426 for additional information.
These bits are not write-synchronized.
zBits 13:11 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 10– AACKEN: Automatic Acknowledge Enable
This bit enables the address to be automatically acknowledged if there is an address match.
0: Automatic acknowledge is disabled.
1: Automatic acknowledge is enabled.
This bit is not write-synchronized.
CMD[1:0] DIR Action
0x0 X(No action)
0x1 X(Reserved)
0x2
Used to complete a transaction in response to a data interrupt (DRDY)
0 (Master write) Execute acknowledge action succeeded by waiting for any start (S/Sr) condition
1 (Master read) Wait for any start (S/Sr) condition
0x3
Used in response to an address interrupt (AMATCH)
0 (Master write) Execute acknowledge action succeeded by reception of next byte
1 (Master read) Execute acknowledge action succeeded by slave data interrupt
Used in response to a data interrupt (DRDY)
0 (Master write) Execute acknowledge action succeeded by reception of next byte
1 (Master read) Execute a byte read operation followed by ACK/NACK reception
Value Name Description
0x0 MASK The slave responds to the address written in ADDR.ADDR masked by the value in
ADDR.ADDRMASK(1).
0x1 2_ADDRS The slave responds to the two unique addresses in ADDR.ADDR and ADDR.ADDRMASK.
0x2 RANGE The slave responds to the range of addresses between and including ADDR.ADDR and
ADDR.ADDRMASK. ADDR.ADDR is the upper limit.
0x3 -Reserved.
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zBit 9 – GCMD: PMBus Group Command
This bit enables PMBus group command support. When enabled, a STOP interrupt will be generated if the
slave has been addressed since the last STOP condition on the bus.
0: Group command is disabled.
1: Group command is enabled.
This bit is not write-synchronized.
zBit 8 – SMEN: Smart Mode Enable
This bit enables smart mode. When smart mode is enabled, acknowledge action is sent when DATA.DATA is
read.
0: Smart mode is disabled.
1: Smart mode is enabled.
This bit is not write-synchronized.
zBits 7:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
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26.8.1.3 Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x14
Reset: 0x00
Property: Write-Protected
zBit 7– ERROR: Error Interrupt Enable
0: Error interrupt is disabled.
1: Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
zBits 6:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 2 – DRDY: Data Ready Interrupt Enable
0: The Data Ready interrupt is disabled.
1: The Data Ready interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Data Ready bit, which disables the Data Ready interrupt.
zBit 1 – AMATCH: Address Match Interrupt Enable
0: The Address Match interrupt is disabled.
1: The Address Match interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Address Match Interrupt Enable bit, which disables the Address Match
interrupt.
zBit 0 – PREC: Stop Received Interrupt Enable
0: The Stop Received interrupt is disabled.
1: The Stop Received interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Stop Received bit, which disables the Stop Received interrupt.
Bit76543210
ERROR DRDY AMATCH PREC
Access R/W R R R R R/W R/W R/W
Reset00000000
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26.8.1.4 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name: INTENSET
Offset: 0x16
Reset: 0x00
Property: Write-Protected
zBit 7 – ERROR: Error Interrupt Enable
0: Error interrupt is disabled.
1: Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.
zBits 6:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 2 – DRDY: Data Ready Interrupt Enable
0: The Data Ready interrupt is disabled.
1: The Data Ready interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Data Ready bit, which enables the Data Ready interrupt.
zBit 1 – AMATCH: Address Match Interrupt Enable
0: The Address Match interrupt is disabled.
1: The Address Match interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Address Match Interrupt Enable bit, which enables the Address Match interrupt.
zBit 0 – PREC: Stop Received Interrupt Enable
0: The Stop Received interrupt is disabled.
1: The Stop Received interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Stop Received bit, which enables the Stop Received interrupt.
Bit76543210
ERROR DRDY AMATCH PREC
Access R/W R R R R R/W R/W R/W
Reset00000000
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26.8.1.5 Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x18
Reset: 0x00
Property: -
zBit 7– ERROR: Error
This flag is cleared by writing a one to it.
This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the
STATUS register. Errors that will set this flag are SEXTTOUT, LOWTOUT, COLL, and BUSERR.Writing a
zero to this bit has no effect.
Writing a one to this bit will clear the flag.
zBits 6:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 2 – DRDY: Data Ready
This flag is set when a I2C slave byte transmission is successfully completed.
The flag is cleared by hardware when either:
zWriting to the DATA register.
zReading the DATA register with smart mode enabled.
zWriting a valid command to the CMD register.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Data Ready interrupt flag. Optionally, the flag can be cleared manually by writ-
ing a one to INTFLAG.DRDY.
zBit 1 – AMATCH: Address Match
This flag is set when the I2C slave address match logic detects that a valid address has been received.
The flag is cleared by hardware when CTRL.CMD is written.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Address Match interrupt flag. Optionally the flag can be cleared manually by
writing a one to INTFLAG.AMATCH. When cleared, an ACK/NACK will be sent according to CTRLB.ACKACT.
zBit 0 – PREC: Stop Received
This flag is set when a stop condition is detected for a transaction being processed. A stop condition detected
between a bus master and another slave will not set this flag.
This flag is cleared by hardware after a command is issued on the next address match.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Stop Received interrupt flag. Optionally, the flag can be cleared manually by
writing a one to INTFLAG.PREC.
Bit 76543210
ERROR DRDY AMATCH PREC
Access R/WRRRRR/WR/WR/W
Reset 00000000
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26.8.1.6 Status
Name: STATUS
Offset: 0x1A
Reset: 0x0000
Property: -
zBits 15:11 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 10 – HS: High-speed
This bit is set if the slave detects a START followed by a Master Code transmission.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the status. However, this flag is automatically cleared when a STOP is received.
zBit 9 – SEXTTOUT: Slave SCL Low Extend Time-Out
This bit is set if a slave SCL low extend time-out occurs.
This bit is cleared automatically if responding to a new start condition with ACK or NACK (write 3 to CTRLB.CMD)
or when INTFLAG.AMATCH is cleared.
0: No SCL low extend time-out has occurred.
1: SCL low extend time-out has occurred.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the status.
zBit 8 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 7 – CLKHOLD: Clock Hold
The slave Clock Hold bit (STATUS.CLKHOLD) is set when the slave is holding the SCL line low, stretching the I2C
clock. Software should consider this bit a read-only status flag that is set when INTFLAG.DRDY or INT-
FLAG.AMATCH is set.
This bit is automatically cleared when the corresponding interrupt is also cleared.
zBit 6 – LOWTOUT: SCL Low Time-out
This bit is set if an SCL low time-out occurs.
This bit is cleared automatically if responding to a new start condition with ACK or NACK (write 3 to CTRLB.CMD)
or when INTFLAG.AMATCH is cleared.
Bit 151413121110 9 8
HS SEXTTOUT
AccessRRRRRR/WR/WR
Reset00000000
Bit 76543210
CLKHOLD LOWTOUT SR DIR RXNACK COLL BUSERR
Access R R/W R R R R R/W R/W
Reset00000000
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0: No SCL low time-out has occurred.
1: SCL low time-out has occurred.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the status.
zBit 5 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 4 – SR: Repeated Start
When INTFLAG.AMATCH is raised due to an address match, SR indicates a repeated start or start condition.
0: Start condition on last address match
1: Repeated start condition on last address match
This flag is only valid while the INTFLAG.AMATCH flag is one.
zBit 3 – DIR: Read / Write Direction
The Read/Write Direction (STATUS.DIR) bit stores the direction of the last address packet received from a master.
0: Master write operation is in progress.
1: Master read operation is in progress.
zBit 2 – RXNACK: Received Not Acknowledge
This bit indicates whether the last data packet sent was acknowledged or not.
0: Master responded with ACK.
1: Master responded with NACK.
zBit 1 – COLL: Transmit Collision
If set, the I2C slave was not able to transmit a high data or NACK bit, the I2C slave will immediately release the
SDA and SCL lines and wait for the next packet addressed to it.
This flag is intended for the SMBus address resolution protocol (ARP). A detected collision in non-ARP situations
indicates that there has been a protocol violation, and should be treated as a bus error.
Note that this status will not trigger any interrupt, and should be checked by software to verify that the data were
sent correctly. This bit is cleared automatically if responding to an address match with an ACK or a NACK (writing
0x3 to CTRLB.CMD), or INTFLAG.AMATCH is cleared.
0: No collision detected on last data byte sent.
1: Collision detected on last data byte sent.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the status.
zBit 0 – BUSERR: Bus Error
The Bus Error bit (STATUS.BUSERR) indicates that an illegal bus condition has occurred on the bus, regardless
of bus ownership. An illegal bus condition is detected if a protocol violating start, repeated start or stop is detected
on the I2C bus lines. A start condition directly followed by a stop condition is one example of a protocol violation. If
a time-out occurs during a frame, this is also considered a protocol violation, and will set STATUS.BUSERR.
This bit is cleared automatically if responding to an address match with an ACK or a NACK (writing 0x3 to
CTRLB.CMD) or INTFLAG.AMATCH is cleared.
0: No bus error detected.
1: Bus error detected.
Writing a one to this bit will clear the status.
Writing a zero to this bit has no effect.
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26.8.1.7 Synchronization Busy
Name: SYNCBUSY
Offset: 0x1C
Reset: 0x00000000
Property:
zBits 31:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 1 – ENABLE: SERCOM Enable Synchronization Busy
Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the SYNC-
BUSY.ENABLE bit will be set until synchronization is complete.
Writes to any register (except for CTRLA.SWRST) while enable synchronization is on-going will be discarded and
an APB error will be generated.
0: Enable synchronization is not busy.
1: Enable synchronization is busy.
zBit 0 – SWRST: Software Reset Synchronization Busy
Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the SYNCBUSY.SWRST bit
will be set until synchronization is complete.
Writes to any register while synchronization is on-going will be discarded and an APB error will be generated.
0: SWRST synchronization is not busy.
1: SWRST synchronization is busy.
Bit3130292827262524
AccessRRRRRRRR
Reset00000000
Bit2322212019181716
AccessRRRRRRRR
Reset00000000
Bit151413121110 9 8
AccessRRRRRRRR
Reset00000000
Bit76543210
ENABLE SWRST
AccessRRRRRRRR
Reset00000000
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26.8.1.8 Address
Name: ADDR
Offset: 0x24
Reset: 0x00000000
Property: Write-Protected, Enable-Protected
zBits 31:27 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 26:17 – ADDRMASK[9:0]: Address Mask
The ADDRMASK bits acts as a second address match register, an address mask register or the lower limit of an
address range, depending on the CTRLB.AMODE setting.
zBit 16– Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 15– TENBITEN: Ten Bit Addressing Enable
Writing a one to TENBITEN enables 10-bit address recognition.
0: 10-bit address recognition disabled.
1: 10-bit address recognition enabled.
zBits 14:11 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit3130292827262524
ADDRMASK[9:7]
Access R R R R R R/W R/W R/W
Reset00000000
Bit2322212019181716
ADDRMASK[6:0]
Access R/W R/W R/W R/W R/W R/W R/W R
Reset00000000
Bit151413121110 9 8
TENBITEN ADDR[9:7]
Access R/W R R R R R/W R/W R/W
Reset00000000
Bit76543210
ADDR[6:0] GENCEN
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
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zBits 10:1 – ADDR[9:0]: Address
The slave address (ADDR) bits contain the I2C slave address used by the slave address match logic to determine
if a master has addressed the slave.
When using 7-bit addressing, the slave address is represented by ADDR.ADDR[6:0].
When using 10-bit addressing (ADDR.TENBITEN=1), the slave address is represented by ADDR.ADDR[9:0]
When the address match logic detects a match, INTFLAG.AMATCH is set and STATUS.DIR is updated to indicate
whether it is a read or a write transaction.
zBit 0 – GENCEN: General Call Address Enable
Writing a one to GENCEN enables general call address recognition. A general call address is an address of all
zeroes with the direction bit written to zero (master write).
0: General call address recognition disabled.
1: General call address recognition enabled.
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26.8.1.9 Data
Name: DATA
Offset: 0x28
Reset: 0x0000
Property: Write-Synchronized, Read-Synchronized
zBits 15:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 7:0 – DATA[7:0]: Data
The slave data register I/O location (DATA.DATA) provides access to the master transmit and receive data buf-
fers. Reading valid data or writing data to be transmitted can be successfully done only when SCL is held low by
the slave (STATUS.CLKHOLD is set). An exception occurs when reading the last data byte after the stop condition
has been received.
Accessing DATA.DATA auto-triggers I2C bus operations. The operation performed depends on the state of
CTRLB.ACKACT, CTRLB.SMEN and the type of access (read/write).
Writing or reading DATA.DATA when not in smart mode does not require synchronization.
Bit151413121110 9 8
AccessRRRRRRRR
Reset00000000
Bit76543210
DATA[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
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26.8.2 I2C Master Register Description
26.8.2.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00000000
Property: Write-Protected, Enable-Protected, Write-Synchronized
zBit 31 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 30 – LOWTOUT: SCL Low Time-Out
This bit enables the SCL low time-out. If SCL is held low for 25ms-35ms, the master will release its clock hold, if
enabled, and complete the current transaction. A stop condition will automatically be transmitted.
INTFLAG.SB or INTFLAG.MB will be set as normal, but the clock hold will be released. The STATUS.LOWTOUT
and STATUS.BUSERR status bits will be set.
0: Time-out disabled.
1: Time-out enabled.
This bit is not synchronized.
zBits 29:28 – INACTOUT[1:0]: Inactive Time-Out
If the inactive bus time-out is enabled and the bus is inactive for longer than the time-out setting, the bus state logic
will be set to idle. An inactive bus arise when either an I2C master or slave is holding the SCL low. The available
time-outs are given in Table 26-9.
Bit 3130292827262524
LOWTOUT INACTOUT[1:0] SCLSM SPEED[1:0]
Access R R/W R/W R/W R/W R R/W R/W
Reset00000000
Bit 2322212019181716
SEXTTOEN MEXTTOEN SDAHOLD[1:0] PINOUT
Access R/W R/W R/W R/W R R R R/W
Reset00000000
Bit 151413121110 9 8
AccessRRRRRRRR
Reset00000000
Bit 76543210
RUNSTDBY MODE[2:0]=101 ENABLE SWRST
Access R/W R R R/W R/W R/W R/W R/W
Reset00000000
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Enabling this option is necessary for SMBus compatibility, but can also be used in a non-SMBus set-up.
Table 26-9. Inactive Timout
Calculated time-out periods are based on a 100kHz baud rate.
These bits are not synchronized.
zBit 27– SCLSM: SCL Clock Stretch Mode
This bit controls when SCL will be stretch for software interaction.
0: SCL stretch according to Figure 26-7.
1: SCL stretch only after ACK bit.
This bit is not synchronized.
zBit 26– Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 25:24 – SPEED[1:0]: Transfer Speed
These bits define bus speed.
Table 26-10. Transfer Speed
These bits are not synchronized.
zBit 23 – SEXTTOEN: Slave SCL Low Extend Time-Out
This bit enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms
from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state
machine. Any interrupts set at the time of time-out will remain set. If the address was recognized, PREC will
be set when a STOP is received.
0: Time-out disabled
1: Time-out enabled
This bit is not synchronized.
zBit 22 – MEXTTOEN: Master SCL Low Extend Time-Out
This bit enables the master SCL low extend time-out. If SCL is cumulatively held low for greater than 10ms from
START-to-ACK, ACK-to-ACK, or ACK-to-STOP the master will release its clock hold if enabled, and complete the
current transaction. A STOP will automatically be transmitted.
Value Name Description
0x0 DIS Disabled
0x1 55US 5-6 SCL cycle time-out (50-60µs)
0x2 105US 10-11 SCL cycle time-out (100-110µs)
0x3 205US 20-21 SCL cycle time-out (200-210µs)
Value Description
0x0 Standard-mode (Sm) up to 100 kHz and Fast-mode (Fm) up to 400 kHz
0x1 Fast-mode Plus (Fm+) up to 1 MHz
0x2 High-speed mode (Hs-mode) up to 3.4 MHz
0x3 Reserved
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SB or MB will be set as normal, but CLKHOLD will be release. The MEXTTOUT and BUSERR status bits will
be set.
0: Time-out disabled
1: Time-out enabled
This bit is not synchronized.
zBits 21:20 – SDAHOLD[1:0]: SDA Hold Time
These bits define the SDA hold time with respect to the negative edge of SCL.
Table 26-11. SDA Hold Time
These bits are not synchronized.
zBits 19:17 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 16 – PINOUT: Pin Usage
This bit set the pin usage to either two- or four-wire operation:
0: 4-wire operation disabled.
1: 4-wire operation enabled.
This bit is not synchronized.
zBits 15:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 7 – RUNSTDBY: Run in Standby
This bit defines the functionality in standby sleep mode.
0: GCLK_SERCOMx_CORE is disabled and the I2C master will not operate in standby sleep mode.
1: GCLK_SERCOMx_CORE is enabled in all sleep modes allowing the master to operate in standby sleep mode.
This bit is not synchronized.
zBits 6:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 4:2 – MODE[2:0]: Operating Mode
These bits must be written to 0x5 to select the I2C master serial communication interface of the SERCOM.
These bits are not synchronized.
zBit 1 – ENABLE: Enable
0: The peripheral is disabled.
1: The peripheral is enabled.
Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRL.ENABLE will read back immediately and the Synchronization Enable Busy bit in the Sync-
Value Name Description
0x0 DIS Disabled
0x1 75NS 50-100ns hold time
0x2 450NS 300-600ns hold time
0x3 600NS 400-800ns hold time
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busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is
complete.
This bit is not enable-protected.
zBit 0 – SWRST: Software Reset
0: There is no reset operation ongoing.
1: The reset operation is ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SER-
COM will be disabled.
Writing a one to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-oper-
ation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading
any register will return the reset value of the register.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST
and SYNCBUSY.SWRST will both be cleared when the reset is complete.
This bit is not enable-protected.
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26.8.2.2 Control B
Name: CTRLB
Offset: 0x04
Reset: 0x00000000
Property: Write-Protected, Enable-Protected, Write-Synchronized
zBits 31:19 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 18 – ACKACT: Acknowledge Action
The Acknowledge Action (ACKACT) bit defines the I2C master's acknowledge behavior after a data byte is
received from the I2C slave. The acknowledge action is executed when a command is written to CTRLB.CMD, or if
smart mode is enabled (CTRLB.SMEN is written to one), when DATA.DATA is read.
0: Send ACK.
1: Send NACK.
This bit is not enable-protected.
This bit is not write-synchronized.
zBits 17:16 – CMD[1:0]: Command
Writing the Command bits (CMD) triggers the master operation as defined in Table 26-12. The CMD bits are
strobe bits, and always read as zero. The acknowledge action is only valid in master read mode. In master write
mode, a command will only result in a repeated start or stop condition. The CTRLB.ACKACT bit and the CMD bits
Bit3130292827262524
AccessRRRRRRRR
Reset00000000
Bit2322212019181716
ACKACT CMD[1:0]
Access R R R R R R/W R/W R/W
Reset00000000
Bit151413121110 9 8
QCEN SMEN
AccessRRRRRRRR/W
Reset00000000
Bit76543210
AccessRRRRRRRR
Reset00000000
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can be written at the same time, and then the acknowledge action will be updated before the command is
triggered.
Commands can only be issued when the Slave on Bus interrupt flag (INTFLAG.SB) or Master on Bus interrupt flag
(INTFLAG.MB) is one.
If CMD 0x1 is issued, a repeated start will be issued followed by the transmission of the current address in
ADDR.ADDR. If another address is desired, ADDR.ADDR must be written instead of the CMD bits. This will trigger
a repeated start followed by transmission of the new address.
Issuing a command will set STATUS.SYNCBUSY.
Table 26-12. Command Description
These bits are not enable-protected.
zBits 15:10 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 9 – QCEN: Quick Command Enable
Setting the Quick Command Enable bit (QCEN) enables quick command.
0: Quick Command is disabled.
1: Quick Command is enabled.
This bit is not write-synchronized.
zBit 8 – SMEN: Smart Mode Enable
This bit enables smart mode. When smart mode is enabled, acknowledge action is sent when DATA.DATA is
read.
0: Smart mode is disabled.
1: Smart mode is enabled.
This bit is not write-synchronized.
zBits 7:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
CMD[1:0] Direction Action
0x0 X(No action)
0x1 XExecute acknowledge action succeeded by repeated Start
0x2
0 (Write) No operation
1 (Read) Execute acknowledge action succeeded by a byte read operation
0x3 XExecute acknowledge action succeeded by issuing a stop condition
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26.8.2.3 Baud Rate
Name: BAUD
Offset: 0x0C
Reset: 0x0000
Property: Write-Protected, Enable-Protected
zBits 31:24 – HSBAUDLOW[7:0]: High Speed Master Baud Rate Low
HSBAUDLOW not equal to 0
HSBAUDLOW indicates the SCL low time according to the following formula.
HSBAUDLOW equal to 0
The HSBAUD register is used to time TLOW, THIGH, TSU;STO, THD;STA and TSU;STA.. TBUF is timed by the BAUD register.
zBits 23:16 – HSBAUD[7:0]: High Speed Master Baud Rate
The HSBAUD register indicates the SCL high time according to the following formula. When HSBAUDLOW is
zero, TLOW, THIGH, TSU;STO, THD;STA and TSU;STA are derived using this formula. TBUF is timed by the BAUD register.
zBits 15:8 – BAUDLOW[7:0]: Master Baud Rate Low
If the Master Baud Rate Low bit group (BAUDLOW) has a non-zero value, the SCL low time will be described by
the value written.
Bit3130292827262524
HSBAUDLOW[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
Bit2322212019181716
HSBAUD[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
Bit151413121110 9 8
BAUDLOW[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
Bit76543210
BAUD[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
1−= T
fLOW
GCLK
HSBAUDLOW
1−= T
fHIGH
GCLK
BAUD
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For more information on how to calculate the frequency, see “SERCOM I2C – SERCOM Inter-Integrated Circuit”
on page 505.
zBits 7:0 – BAUD[7:0]: Master Baud Rate
The Master Baud Rate bit group (BAUD) is used to derive the SCL high time if BAUD.BAUDLOW is non-zero. If
BAUD.BAUDLOW is zero, BAUD will be used to generate both high and low periods of the SCL.
For more information on how to calculate the frequency, see “SERCOM I2C – SERCOM Inter-Integrated Circuit”
on page 505.
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26.8.2.4 Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x14
Reset: 0x00
Property: Write-Protected
zBit 7– ERROR: Error Interrupt Enable
0: Error interrupt is disabled.
1: Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
zBits 6:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 1 – SB: Slave on Bus Interrupt Enable
0: The Slave on Bus interrupt is disabled.
1: The Slave on Bus interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Slave on Bus Interrupt Enable bit, which disables the Slave on Bus interrupt.
zBit 0 – MB: Master on Bus Interrupt Enable
0: The Master on Bus interrupt is disabled.
1: The Master on Bus interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Master on Bus Interrupt Enable bit, which disables the Master on Bus
interrupt.
Bit76543210
ERROR SB MB
AccessR/WRRRRRR/WR/W
Reset00000000
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26.8.2.5 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name: INTENSET
Offset: 0x16
Reset: 0x00
Property: Write-Protected
zBit 7 – ERROR: Error Interrupt Enable
0: Error interrupt is disabled.
1: Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.
zBits 6:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 1 – SB: Slave on Bus Interrupt Enable
0: The Slave on Bus interrupt is disabled.
1: The Slave on Bus interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Slave on Bus Interrupt Enable bit, which enables the Slave on Bus interrupt.
zBit 0 – MB: Master on Bus Interrupt Enable
0: The Master on Bus interrupt is disabled.
1: The Master on Bus interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Master on Bus Interrupt Enable bit, which enables the Master on Bus interrupt.
Bit76543210
ERROR SB MB
AccessR/WRRRRRR/WR/W
Reset00000000
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26.8.2.6 Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x18
Reset: 0x00
Property: -
zBit 7– ERROR: Error
This flag is cleared by writing a one to it.
This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STA-
TUS register. Errors that will set this flag are LENERR, SEXTTOUT, MEXTTOUT, LOWTOUT, ARBLOST, and
BUSERR.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the flag.
zBits 6:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 1 – SB: Slave on Bus
The Slave on Bus flag (SB) is set when a byte is successfully received in master read mode, i.e., no arbitration lost
or bus error occurred during the operation. When this flag is set, the master forces the SCL line low, stretching the
I2C clock period. The SCL line will be released and SB will be cleared on one of the following actions:
zWriting to ADDR.ADDR
zWriting to DATA.DATA
zReading DATA.DATA when smart mode is enabled (CTRLB.SMEN)
zWriting a valid command to CTRLB.CMD
Writing a one to this bit location will clear the SB flag. The transaction will not continue or be terminated until one of
the above actions is performed.
Writing a zero to this bit has no effect.
zBit 0 – MB: Master on Bus
The Master on Bus flag (MB) is set when a byte is transmitted in master write mode. The flag is set regardless of
the occurrence of a bus error or an arbitration lost condition. MB is also set when arbitration is lost during sending
of NACK in master read mode, and when issuing a start condition if the bus state is unknown. When this flag is set
and arbitration is not lost, the master forces the SCL line low, stretching the I2C clock period. The SCL line will be
released and MB will be cleared on one of the following actions:
zWriting to ADDR.ADDR
zWriting to DATA.DATA
zReading DATA.DATA when smart mode is enabled (CTRLB.SMEN)
zWriting a valid command to CTRLB.CMD
If arbitration is lost, writing a one to this bit location will clear the MB flag.
If arbitration is not lost, writing a one to this bit location will clear the MB flag. The transaction will not continue or be
terminated until one of the above actions is performed.
Bit76543210
ERROR SB MB
AccessR/WRRRRRR/WR/W
Reset00000000
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Writing a zero to this bit has no effect.
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26.8.2.7 Status
Name: STATUS
Offset: 0x1A
Reset: 0x0000
Property: Write-Synchronized
zBits 15:11 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 10 – LENERR: Transaction Length Error
This bit is set when automatic length is used for a DMA transaction and the slave sends a NACK before
ADDR.LEN bytes have been written by the master.
Writing a one to this bit location will clear STATUS.LENERR. This flag is automatically cleared when writing to the
ADDR register.
Writing a zero to this bit has no effect.
This bit is not write-synchronized.
zBit 9 – SEXTTOUT: Slave SCL Low Extend Time-Out
This bit is set if a slave SCL low extend time-out occurs.
Writing a one to this bit location will clear STATUS.SEXTTOUT. Normal use of the I2C interface does not require
the STATUS.SEXTTOUT flag to be cleared by this method. This flag is automatically cleared when writing to the
ADDR register.
Writing a zero to this bit has no effect.
This bit is not write-synchronized.
zBit 8 – MEXTTOUT: Master SCL Low Extend Time-Out
This bit is set if a master SCL low time-out occurs.
Writing a one to this bit location will clear STATUS.MEXTTOUT. Normal use of the I2C interface does not require
the STATUS.MEXTTOUT flag to be cleared by this method. This flag is automatically cleared when writing to the
ADDR register.
Writing a zero to this bit has no effect.
This bit is not write-synchronized.
zBit 7 – CLKHOLD: Clock Hold
The Master Clock Hold flag (STATUS.CLKHOLD) is set when the master is holding the SCL line low, stretching
the I2C clock. Software should consider this bit a read-only status flag that is set when INTFLAG.SB or INT-
Bit151413121110 9 8
LENERR SEXTTOUT MEXTTOUT
Access R R R R R R/W R/W R/W
Reset00000000
Bit76543210
CLKHOLD LOWTOUT BUSSTATE[1:0] RXNACK ARBLOST BUSERR
Access R R/W R R/W R R R/W R/W
Reset00000000
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FLAG.MB is set. When the corresponding interrupt flag is cleared and the next operation is given, this bit is
automatically cleared.
Writing a zero to this bit has no effect.
Writing a one to this bit has no effect.
This bit is not write-synchronized.
zBit 6 – LOWTOUT: SCL Low Time-Out
This bit is set if an SCL low time-out occurs.
Writing a one to this bit location will clear STATUS.LOWTOUT. Normal use of the I2C interface does not require
the LOWTOUT flag to be cleared by this method. This flag is automatically cleared when writing to the ADDR
register.
Writing a zero to this bit has no effect.
This bit is not write-synchronized.
zBits 5:4 – BUSSTATE[1:0]: Bus State
These bits indicate the current I2C bus state as defined in Table 26-13. After enabling the SERCOM as an I2C
master, the bus state will be unknown.
Table 26-13. Bus State
When the master is disabled, the bus-state is unknown. When in the unknown state, writing 0x1 to BUSSTATE
forces the bus state into the idle state. The bus state cannot be forced into any other state.
Writing STATUS.BUSSTATE to idle will set STATUS.SYNCBUSY.
zBit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 2 – RXNACK: Received Not Acknowledge
This bit indicates whether the last address or data packet sent was acknowledged or not.
0: Slave responded with ACK.
1: Slave responded with NACK.
Writing a zero to this bit has no effect.
Writing a one to this bit has no effect.
This bit is not write-synchronized.
zBit 1 – ARBLOST: Arbitration Lost
The Arbitration Lost flag (STATUS.ARBLOST) is set if arbitration is lost while transmitting a high data bit or a
NACK bit, or while issuing a start or repeated start condition on the bus. The Master on Bus interrupt flag (INT-
FLAG.MB) will be set when STATUS.ARBLOST is set.
Writing the ADDR.ADDR register will automatically clear STATUS.ARBLOST.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear it.
Value Name Description
0x0 Unknown The bus state is unknown to the I2C master and will wait for a stop condition
to be detected or wait to be forced into an idle state by software
0x1 Idle The bus state is waiting for a transaction to be initialized
0x2 Owner The I2C master is the current owner of the bus
0x3 Busy Some other I2C master owns the bus
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This bit is not write-synchronized.
zBit 0 – BUSERR: Bus Error
The Bus Error bit (STATUS.BUSERR) indicates that an illegal bus condition has occurred on the bus, regardless
of bus ownership. An illegal bus condition is detected if a protocol violating start, repeated start or stop is detected
on the I2C bus lines. A start condition directly followed by a stop condition is one example of a protocol violation. If
a time-out occurs during a frame, this is also considered a protocol violation, and will set BUSERR.
If the I2C master is the bus owner at the time a bus error occurs, STATUS.ARBLOST and INTFLAG.MB will be set
in addition to BUSERR.
Writing the ADDR.ADDR register will automatically clear the BUSERR flag.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear it.
This bit is not write-synchronized.
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26.8.2.8 Syncbusy
Name: SYNCBUSY
Offset: 0x1C
Reset: 0x00000000
Property:
zBits 31:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 2– SYSOP: System Operation Synchronization Busy
Writing CTRLB, STATUS.BUSSTATE, ADDR, or DATA when the SERCOM is enabled requires synchronization.
When written, the SYNCBUSY.SYSOP bit will be set until synchronization is complete.
0: System operation synchronization is not busy.
1: System operation synchronization is busy.
zBit 1 – ENABLE: SERCOM Enable Synchronization Busy
Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the SYNC-
BUSY.ENABLE bit will be set until synchronization is complete.
Writes to any register (except for CTRLA.SWRST) while enable synchronization is on-going will be discarded and
an APB error will be generated.
0: Enable synchronization is not busy.
1: Enable synchronization is busy.
Bit3130292827262524
AccessRRRRRRRR
Reset00000000
Bit2322212019181716
AccessRRRRRRRR
Reset00000000
Bit151413121110 9 8
AccessRRRRRRRR
Reset00000000
Bit76543210
SYSOP ENABLE SWRST
AccessRRRRRRRR
Reset00000000
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zBit 0 – SWRST: Software Reset Synchronization Busy
Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the SYNCBUSY.SWRST bit
will be set until synchronization is complete.
Writes to any register while synchronization is on-going will be discarded and an APB error will be generated.
0: SWRST synchronization is not busy.
1: SWRST synchronization is busy.
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26.8.2.9 Address
Name: ADDR
Offset: 0x24
Reset: 0x0000
Property: Write-Synchronized
zBits 31:24 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 23:16 – LEN[7:0]: Transaction Length
For DMA operation, this field represents the data length of the transaction from 0 to 255 bytes. The transaction
length enable (ADDR.LENEN) must be written to 1 for automatic transaction length to be used. After ADDR.LEN
bytes have been transmitted or received, a NACK (for master reads) and STOP are automatically generated.
zBit 15 – TENBITEN: Ten Bit Addressing Enable
This bit enables 10-bit addressing. This bit can be written simultaneously with ADDR to indicate a 10-bit or 7-bit
address transmission.
0: 10-bit addressing disabled.
1: 10-bit addressing enabled.
zBit 14 – HS: High Speed
This bit enables High-speed mode for the current transfer from repeated START to STOP. This bit can be written
simultaneously with ADDR for a high speed transfer.
0: High-speed transfer disabled.
Bit3130292827262524
AccessRRRRRRRR
Reset00000000
Bit2322212019181716
LEN[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
Bit151413121110 9 8
TENBITEN HS LENEN ADDR[10:8]
Access R/W R/W R/W R R R/W R/W R/W
Reset00000000
Bit76543210
ADDR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
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1: High-speed transfer enabled.
zBit 13 – LENEN: Transfer Length Enable
This bit enables automatic transfer length.
0: Automatic transfer length disabled.
1: Automatic transfer length enabled.
zBits 12:11 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 10:0 – ADDR[10:0]: Address
When ADDR is written, the consecutive operation will depend on the bus state:
Unknown: INTFLAG.MB and STATUS.BUSERR are set, and the operation is terminated.
Busy: The I2C master will await further operation until the bus becomes idle.
Idle: The I2C master will issue a start condition followed by the address written in ADDR. If the address is acknowl-
edged, SCL is forced and held low, and STATUS.CLKHOLD and INTFLAG.MB are set.
Owner: A repeated start sequence will be performed. If the previous transaction was a read, the acknowledge
action is sent before the repeated start bus condition is issued on the bus. Writing ADDR to issue a repeated start
is performed while INTFLAG.MB or INTFLAG.SB is set.
Regardless of winning or loosing arbitration, the entire address will be sent. If arbitration is lost, only ones are
transmitted from the point of loosing arbitration and the rest of the address length.
STATUS.BUSERR, STATUS.ARBLOST, INTFLAG.MB and INTFLAG.SB will be cleared when ADDR is written.
The ADDR register can be read at any time without interfering with ongoing bus activity, as a read access does not
trigger the master logic to perform any bus protocol related operations.
The I2C master control logic uses bit 0 of ADDR as the bus protocol’s read/write flag (R/W); 0 for write and 1 for
read.
zBits 31:24 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 23:16 – LEN[7:0]: Transaction Length
For DMA operation, this field represents the data length of the transaction from 0 to 255 bytes. The transaction
length enable (ADDR.LENEN) must be written to 1 for automatic transaction length to be used. After ADDR.LEN
bytes have been transmitted or received, a NACK (for master reads) and STOP are automatically generated.
zBit 15 – TENBITEN: Ten Bit Addressing Enable
This bit enables 10-bit addressing. This bit can be written simultaneously with ADDR to indicate a 10-bit or 7-bit
address transmission.
0: 10-bit addressing disabled.
1: 10-bit addressing enabled.
zBit 14 – HS: High Speed
This bit enables High-speed mode for the current transfer from repeated START to STOP. This bit can be written
simultaneously with ADDR for a high speed transfer.
0: .High-speed transfer disabled.
1: High-speed transfer enabled.
zBit 13 – LENEN: Transfer Length Enable
This bit enables automatic transfer length.
0: Automatic transfer length disabled.
1: Automatic transfer length enabled.
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zBits 12:11 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 10:0 – ADDR[10:0]: Address
When ADDR is written, the consecutive operation will depend on the bus state:
Unknown: INTFLAG.MB and STATUS.BUSERR are set, and the operation is terminated.
Busy: The I2C master will await further operation until the bus becomes idle.
Idle: The I2C master will issue a start condition followed by the address written in ADDR. If the address is acknowl-
edged, SCL is forced and held low, and STATUS.CLKHOLD and INTFLAG.MB are set.
Owner: A repeated start sequence will be performed. If the previous transaction was a read, the acknowledge
action is sent before the repeated start bus condition is issued on the bus. Writing ADDR to issue a repeated start
is performed while INTFLAG.MB or INTFLAG.SB is set.
Regardless of winning or loosing arbitration, the entire address will be sent. If arbitration is lost, only ones are
transmitted from the point of loosing arbitration and the rest of the address length.
STATUS.BUSERR, STATUS.ARBLOST, INTFLAG.MB and INTFLAG.SB will be cleared when ADDR is written.
The ADDR register can be read at any time without interfering with ongoing bus activity, as a read access does not
trigger the master logic to perform any bus protocol related operations.
The I2C master control logic uses bit 0 of ADDR as the bus protocol’s read/write flag (R/W); 0 for write and 1 for
read.
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26.8.2.10 Data
Name: DATA
Offset: 0x18
Reset: 0x0000
Property: Write-Synchronized, Read-Synchronized
zBits 15:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 7:0 – DATA[7:0]: Data
The master data register I/O location (DATA) provides access to the master transmit and receive data buffers.
Reading valid data or writing data to be transmitted can be successfully done only when SCL is held low by the
master (STATUS.CLKHOLD is set). An exception occurs when reading the last data byte after the stop condition
has been sent.
Accessing DATA.DATA auto-triggers I2C bus operations. The operation performed depends on the state of
CTRLB.ACKACT, CTRLB.SMEN and the type of access (read/write).
Writing or reading DATA.DATA when not in smart mode does not require synchronization.
Bit151413121110 9 8
AccessRRRRRRRR
Reset00000000
Bit76543210
DATA[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
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26.8.2.11 Debug Control
Name: DBGCTRL
Offset: 0x30
Reset: 0x00
Property: Write-Protected
zBits 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 0 – DBGSTOP: Debug Stop Mode
This bit controls functionality when the CPU is halted by an external debugger.
0: The baud-rate generator continues normal operation when the CPU is halted by an external debugger.
1: The baud-rate generator is halted when the CPU is halted by an external debugger.
Bit76543210
DBGSTOP
Access R R R R R R R R/W
Reset00000000
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27. TC – Timer/Counter
27.1 Overview
The TC consists of a counter, a prescaler, compare/capture channels and control logic. The counter can be set to count
events, or it can be configured to count clock pulses. The counter, together with the compare/capture channels, can be
configured to timestamp input events, allowing capture of frequency and pulse width. It can also perform waveform
generation, such as frequency generation and pulse-width modulation (PWM).
27.2 Features
zSelectable configuration
z8-, 16- or 32-bit TC, with compare/capture channels
zWaveform generation
zFrequency generation
zSingle-slope pulse-width modulation
zInput capture
zEvent capture
zFrequency capture
zPulse-width capture
zOne input event
zInterrupts/output events on:
zCounter overflow/underflow
zCompare match or capture
zInternal prescaler
zCan be used with DMA and to trigger DMA transactions
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27.3 Block Diagram
Figure 27-1. Timer/Counter Block Diagram
PERPER
PRESCALERPRESCALER
CONTROLCONTROL
LOGICLOGIC
WAVEFORM WAVEFORM
GENERATIONGENERATION
COUNTCOUNT
CC0CC0
BASE COUNTERBASE COUNTER
COUNTERCOUNTER
Compare / CaptureCompare / Capture
TopTop
ZeroZero
= 0= 0
=
match
match
UpdateUpdate
eventevent
=
OVF/UNF
OVF/UNF
(INT Req.)(INT Req.)
ERRERR
(INT Req.)(INT Req.)
WOx OutWOx Out
MCxMCx
(INT Req.)(INT Req.)
countcount
clearclear
loadload
directiondirection
CONTROLCONTROL
LOGICLOGIC
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27.4 Signal Description
Refer to “I/O Multiplexing and Considerations” on page 12 for details on the pin mapping for this peripheral. One signal
can be mapped on several pins.
27.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
27.5.1 I/O Lines
Using the TC’s I/O lines requires the I/O pins to be configured. Refer to “PORT” on page 373 for details.
27.5.2 Power Management
The TC can continue to operate in any sleep mode where the selected source clock is running. The TC interrupts can be
used to wake up the device from sleep modes. The events can trigger other operations in the system without exiting
sleep modes. Refer to “PM – Power Manager” on page 112 for details on the different sleep modes.
27.5.3 Clocks
The TC bus clock (CLK_TCx_APB, where x represents the specific TC instance number) can be enabled and disabled in
the Power Manager, and the default state of CLK_TCx_APB can be found in the Peripheral Clock Masking section in
“PM – Power Manager” on page 112.
The different TC instances are paired, even and odd, starting from TC0, and use the same generic clock, GCLK_TCx.
This means that the TC instances in a TC pair cannot be set up to use different GCLK_TCx clocks.
This generic clock is asynchronous to the user interface clock (CLK_TCx_APB). Due to this asynchronicity, accessing
certain registers will require synchronization between the clock domains. Refer to “Synchronization” on page 580 for
further details.
27.5.4 DMA
The DMA request lines (or line if only one request) are connected to the DMA Controller (DMAC). Using the TC DMA
requests requires the DMA Controller to be configured first. Refer to “DMAC – Direct Memory Access Controller” on page
267 for details.
27.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the TC interrupts requires the Interrupt Controller
to be configured first. Refer to “Nested Vector Interrupt Controller” on page 29 for details.
27.5.6 Events
To use the TC event functionality, the corresponding events need to be configured in the event system. Refer to “EVSYS
– Event System” on page 400 for details.
27.5.7 Debug Operation
When the CPU is halted in debug mode the TC will halt normal operation. The TC can be forced to continue operation
during debugging. Refer to the Debug Control (DBGCTRL) register for details.
Signal Name Type Description
WO[1:0] Digital output Waveform output
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27.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the
following registers:
zInterrupt Flag register (INTFLAG)
zStatus register (STATUS)
zRead Request register (READREQ)
zCount register (COUNT), “Counter Value” on page 602
zPeriod register (PER), “ Period Value” on page 605
zCompare/Capture Value registers (CCx), “ Compare/Capture” on page 606
Write-protection is denoted by the Write-Protection property in the register description.
When the CPU is halted in debug mode, all write-protection is automatically disabled.
Write-protection does not apply for accesses through an external debugger. Refer to “PAC – Peripheral Access
Controller” on page 36 for details.
27.5.9 Analog Connections
Not applicable.
27.6 Functional Description
27.6.1 Principle of Operation
The counter in the TC can be set to count on events from the Event System, or on the GCLK_TCx frequency. The pulses
from GCLK_TCx will go through the prescaler, where it is possible to divide the frequency down.
The value in the counter is passed to the compare/capture channels, where it can either be compared with user defined
values or captured on a predefined event.
The TC can be configured as an 8-, 16- or 32-bit counter. Which mode is chosen will determine the maximum range of
the counter. The counter range combined with the operating frequency will determine the maximum time resolution
achievable with the TC peripheral.
The TC can be count up or down. By default, the counter will operate in a continuous mode and count up, where the
counter will wrap to the zero when reaching the top value
When one of the compare/capture channels is used in compare mode, the TC can be used for waveform generation.
Upon a match between the counter and the value in one or more of the Compare/Capture Value registers (CCx), one or
more output pins on the device can be set to toggle. The CCx registers and the counter can thereby be used in frequency
generation and PWM generation.
Capture mode can be used to automatically capture the period and pulse width of signals.
27.6.2 Basic Operation
27.6.2.1 Initialization
The following register is enable-protected, meaning that it can only be written when the TC is disabled (CTRLA.ENABLE
is zero):
zControl A register (CTRLA), except the Run Standby (RUNSTDBY), Enable (ENABLE) and Software Reset
(SWRST) bits
The following bits are enable-protected:
zEvent Action bits in the Event Control register (EVCTRL.EVACT)
Enable-protected bits in the CTRLA register can be written at the same time as CTRLA.ENABLE is written to one, but not
at the same time as CTRLA.ENABLE is written to zero.
Before the TC is enabled, it must be configured, as outlined by the following steps:
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zThe TC bus clock (CLK_TCx_APB) must be enabled
zThe mode (8, 16 or 32 bits) of the TC must be selected in the TC Mode bit group in the Control A register
(CTRLA.MODE). The default mode is 16 bits
zOne of the wavegen modes must be selected in the Waveform Generation Operation bit group in the Control A
register (CTRLA.WAVEGEN)
zIf the GCLK_TCx frequency used should be prescaled, this can be selected in the Prescaler bit group in the
Control A register (CTRLA.PRESCALER)
zIf the prescaler is used, one of the presync modes must be chosen in the Prescaler and Counter Synchronization
bit group in the Control A register (CTRLA.PRESYNC)
zOne-shot mode can be selected by writing a one to the One-Shot bit in the Control B Set register
(CTRLBSET.ONESHOT)
zIf the counter should count down from the top value, write a one to the Counter Direction bit in the Control B Set
register (CTRLBSET.DIR)
zIf capture operations are to be used, the individual channels must be enabled for capture in the Capture Channel x
Enable bit group in the Control C register (CTRLC.CPTEN)
zThe waveform output for individual channels can be inverted using the Waveform Output Invert Enable bit group in
the Control C register (CTRLC.INVEN)
27.6.2.2 Enabling, Disabling and Resetting
The TC is enabled by writing a one to the Enable bit in the Control A register (CTRLA.ENABLE). The TC is disabled by
writing a zero to CTRLA.ENABLE.
The TC is reset by writing a one to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in the
TC, except DBGCTRL, will be reset to their initial state, and the TC will be disabled. Refer to the CTRLA register for
details.
The TC should be disabled before the TC is reset to avoid undefined behavior.
27.6.2.3 Prescaler Selection
As seen in Figure 27-2, the GCLK_TC clock is fed into the internal prescaler. Prescaler output intervals from 1 to 1/1024
are available. For a complete list of available prescaler outputs, see the register description for the Prescaler bit group in
the Control A register (CTRLA.PRESCALER).
The prescaler consists of a counter that counts to the selected prescaler value, whereupon the output of the prescaler
toggles.
When the prescaler is set to a value greater than one, it is necessary to choose whether the prescaler should reset its
value to zero or continue counting from its current value on the occurrence of an overflow or underflow. It is also
necessary to choose whether the TC counter should wrap around on the next GCLK_TC clock pulse or the next
prescaled clock pulse (CLK_TC_CNT of Figure 27-2). To do this, use the Prescaler and Counter Synchronization bit
group in the Control A register (CTRLA.PRESYNC).
If the counter is set to count events from the event system, these will not pass through the prescaler, as seen in Figure
27-2.
Figure 27-2. Prescaler
EVENT
CNT
PRESCALER
PRESCALER EVACT
GCLK_TC
GCLK_TC /
{1,2,4,8,64,256,1024 } CLK_TC_CNT
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27.6.2.4 TC Mode
The counter mode is selected with the TC Mode bit group in the Control A register (CTRLA.MODE). By default, the
counter is enabled in the 16-bit counter mode.
Three counter modes are available:
zCOUNT8: The 8-bit TC has its own Period register (PER). This register is used to store the period value that can
be used as the top value for waveform generation.
zCOUNT16: This is the default counter mode. There is no dedicated period register in this mode.
zCOUNT32: This mode is achieved by pairing two 16-bit TC peripherals. This pairing is explained in “Clocks” on
page 570. The even-numbered TC instance will act as master to the odd-numbered TC peripheral, which will act
as a slave. The slave status of the slave is indicated by reading the Slave bit in the Status register
(STATUS.SLAVE). The registers of the slave will not reflect the registers of the 32-bit counter. Writing to any of the
slave registers will not affect the 32-bit counter. Normal access to the slave COUNT and CCx registers is not
allowed.
27.6.2.5 Counter Operations
The counter can be set to count up or down. When the counter is counting up and the top value is reached, the counter
will wrap around to zero on the next clock cycle. When counting down, the counter will wrap around to the top value when
zero is reached. In one-shot mode, the counter will stop counting after a wraparound occurs.
To set the counter to count down, write a one to the Direction bit in the Control B Set register (CTRLBSET.DIR). To count
up, write a one to the Direction bit in the Control B Clear register (CTRLBCLR.DIR).
Each time the counter reaches the top value or zero, it will set the Overflow Interrupt flag in the Interrupt Flag Status and
Clear register (INTFLAG.OVF). It is also possible to generate an event on overflow or underflow when the
Overflow/Underflow Event Output Enable bit in the Event Control register (EVCTRL.OVFEO) is one.
The counter value can be read from the Counter Value register (COUNT) or a new value can be written to the COUNT
register. Figure 27-3 gives an example of writing a new counter value. The COUNT value will always be zero when
starting the TC, unless some other value has been written to it or if the TC has been previously reloaded at TOP value,
because stopped while TC was counting down.
Figure 27-3. Counter Operation
Stop Command
On the stop command, which can be evoked in the Command bit group in the Control B Set register (CTRLBSET.CMD),
the counter will retain its current value. All waveforms are cleared. The counter stops counting, and the Stop bit in the
Status register is set (STATUS.STOP).
DIR
COUNT
TOP
COUNT writtenDirection Change
Period (T)
BOT
"update "
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Retrigger Command and Event Action
Retriggering can be evoked either as a software command, using the Retrigger command in the Control B Set register
(CTRLBSET.CMD), or as a retrigger event action, using the Event Action bit group in the Event Control register
(EVCTRL.EVACT).
When a retrigger is evoked while the counter is running, the counter will wrap to the top value or zero, depending on the
counter direction..
When a retrigger is evoked with the counter stopped, the counter will continue counting from the value in the COUNT
register.
Note: When retrigger event action is configured and enabled as an event action, enabling the counter will not start the
counter. The counter will start at the next incoming event and restart on any following event.
Count Event Action
When the count event action is configured, every new incoming event will make the counter increment or decrement,
depending on the state of the direction bit (CTRLBSET.DIR).
Start Event Action
When the TC is configured with a start event action in the EVCTRL.EVACT bit group, enabling the TC does not make the
counter start; the start is postponed until the next input event or software retrigger action. When the counter is running,
an input event has not effect on the counter.
27.6.2.6 Compare Operations
When using the TC with the Compare/Capture Value registers (CCx) configured for compare operation, the counter
value is continuously compared to the values in the CCx registers. This can be used for timer or waveform operation.
Waveform Output Operations
The compare channels can be used for waveform generation on the corresponding I/O pins. To make the waveform
visible on the connected pin, the following requirements must be fulfilled:
zChoose a waveform generation operation
zOptionally, invert the waveform output by writing the corresponding Waveform Output Invert Enable bit in the
Control C register (CTRLC.INVx)
zEnable the corresponding multiplexor in the PORT
The counter value is continuously compared with each CCx available. When a compare match occurs, the Match or
Capture Channel x interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.MCx) is set on the next zero-to-
one transition of CLK_TC_CNT (see Figure 27-4). An interrupt and/or event can be generated on such a condition when
INTENSET.MCx and/or EVCTRL.MCEOx is one.
One of four configurations in the Waveform Generation Operation bit group in the Control A register (CTRLA.WAVEGEN)
must be chosen to perform waveform generation. This will influence how the waveform is generated and impose
restrictions on the top value. The four configurations are:
zNormal frequency (NFRQ)
zMatch frequency (MFRQ)
zNormal PWM (NPWM)
zMatch PWM (MPWM)
When using NPWM or NFRQ, the top value is determined by the counter mode. In 8-bit mode, the Period register (PER)
is used as the top value and the top value can be changed by writing to the PER register. In 16- and 32-bit mode, the top
value is fixed to the maximum value of the counter.
Frequency Operation
When NFRQ is used, the waveform output (WO[x]) toggles every time CCx and the counter are equal, and the interrupt
flag corresponding to that channel will be set.
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Figure 27-4. Normal Frequency Operation
When MFRQ is used, the value in CC0 will be used as the top value and WO[0] will toggle on every overflow/underflow.
Figure 27-5. Match Frequency Operation
PWM Operation
In PWM operation, the CCx registers control the duty cycle of the waveform generator output. Figure 27-6 shows how in
count-up the WO[x] output is set at a start or compare match between the COUNT value and the top value and cleared
on the compare match between the COUNT value and CCx register value.
In count-down the WO[x] output is cleared at start or compare match between the COUNT value and the top value and
set on the compare match between the COUNT value and CCx register value.
COUNT
Zero
"wraparound "
TOP
CNT written
CCx
WO[x]
COUNT
" wraparound "
TOP
COUNT writtenDirection Change
Period (T)
Zero
WO[0]
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Figure 27-6. Normal PWM Operation
In match operation, Compare/Capture register CC0 is used as the top value, in this case a negative pulse will appear on
WO[0] on every overflow/underflow.
The following equation is used to calculate the exact period for a single-slope PWM (RPWM_SS) waveform:
where N represent the prescaler divider used (1, 2, 4, 8, 16, 64, 256, 1024).
Changing the Top Value
Changing the top value while the counter is running is possible. If a new top value is written when the counter value is
close to zero and counting down, the counter can be reloaded with the previous top value, due to synchronization delays.
If this happens, the counter will count one extra cycle before the new top value is used.
Figure 27-7. Changing the Top Value when Counting Down
COUNT
TOP
Period (T)
"match "
Zero
WO[x]
CCn= BOT
CC n
CCn= TOP "wraparound "
RPWM_SS
TOP 1+()log
2()log
-----------------------------------
=
fPWM_SS
fCLK_TC
NTOP 1+()
------------------------------
=
COUNT
MAX
"reload"
"write"
ZERO
New TOP value
That is higher than
Current COUNT
New TOP value
That is Lower than
Current COUNT
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When counting up a change from a top value that is lower relative to the old top value can make the counter miss this
change if the counter value is larger than the new top value when the change occurred. This will make the counter count
to the max value. An example of this can be seen in Figure 27-8.
Figure 27-8. Changing the Top Value when Counting Up
27.6.2.7 Capture Operations
To enable and use capture operations, the event line into the TC must be enabled using the TC Event Input bit in the
Event Control register (EVCTRL.TCEI). The capture channels to be used must also be enabled in the Capture Channel x
Enable bit group in the Control C register (CTRLC.CPTENx) before capture can be performed.
Event Capture Action
The compare/capture channels can be used as input capture channels to capture any event from the Event System and
give them a timestamp. Because all capture channels use the same event line, only one capture channel should be
enabled at a time when performing event capture.
Figure 27-9 shows four capture events for one capture channel.
Figure 27-9. Input Capture Timing
When the Capture Interrupt flag is set and a new capture event is detected, there is nowhere to store the new timestamp.
As a result, the Error Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.ERR) is set.
COUNT
MAX
Counter Wraparound
" wraparound "
"write"
ZERO
New TOP value
That is Lower than
Current COUNT
New TOP value
That is higher than
Current COUNT
events
COUNT
TOP
ZERO
Capture 0 Capture 1 Capture 2 Capture 3
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Period and Pulse-Width Capture Action
The TC can perform two input captures and restart the counter on one of the edges. This enables the TC to measure the
pulse width and period. This can be used to characterize the frequency and duty cycle of an input signal:
When using PPW event action, the period (T) will be captured into CC0 and the pulse width (tp) in CC1. In PWP event
action, the pulse width (tp) will be captured in CC0 and the period (T) in CC1.
Selecting PWP (pulse-width, period) or PPW (period, pulse-width) in the Event Action bit group in the Event Control
register (EVCTRL.EVACT) enables the TC to performs two capture actions, one on the rising edge and one on the falling
edge.
The TC Inverted Event Input in the Event Control register (EVCTRL.TCINV) is used to select whether the wraparound
should occur on the rising edge or the falling edge. If EVCTRL.TCINV is written to one, the wraparound will happen on
the falling edge. The event source to be captured must be an asynchronous event.
To fully characterize the frequency and duty cycle of the input signal, activate capture on CC0 and CC1 by writing 0x3 to
the Capture Channel x Enable bit group in the Control C register (CTRLC.CPTEN). When only one of these
measurements is required, the second channel can be used for other purposes.
The TC can detect capture overflow of the input capture channels. When the Capture Interrupt flag is set and a new
capture event is detected, there is nowhere to store the new timestamp. Asa result, INTFLAG.ERR is set.
27.6.3 Additional Features
27.6.3.1 One-Shot Operation
When one-shot operation is enabled, the counter automatically stops on the next counter overflow or underflow
condition. When the counter is stopped, STATUS.STOP is automatically set by hardware and the waveform outputs are
set to zero.
One-shot operation can be enabled by writing a one into the One-Shot bit in the Control B Set register
(CTRLBSET.ONESHOT) and disabled by writing a one to the One-Shot bit in the Control B Clear register
(CTRLBCLR.ONESHOT). When enabled, it will count until an overflow or underflow occurs. The one-shot operation can
be restarted with a retrigger command, a retrigger event or a start event.
When the counter restarts its operation, the Stop bit in the Status register (STATUS.STOP) is automatically cleared by
hardware.
f1
T
---
=
dutyCycle tp
T
----
=
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27.6.4 DMA, Interrupts and Events
Note: 1. Two DMA requests lines are available, one for each compare/capture channel.
27.6.4.1 DMA Operation
The TC can generate the following DMA requests:
zOverflow (OVF): the request is set when an update condition (overflow, underflow) is detected. The request is
cleared on next clock cycle.
zChannel Match or Capture (MCx): for a compare channel, the request is set on each compare match detection and
cleared on next clock cycle. For a capture channel, the request is set when valid data is present in CCx register,
and cleared when CCx register is read.
When using the TC with the DMA OVF request, the new value will be transfered to the register after the update condition.
This means that the value is updated after the DMA and synchronization delay, and if the COUNT value has reached the
new value before PER or CCx is updated, a match will not happen.
When using the TC with the DMA MCx request and updating CCx with a value that is lower than the current COUNT
when down-counting, or higher than the current COUNT when up-counting, this value could cause a new compare match
before the counter overflows. This will trigger the next DMA transfer, update CCx again, and the previous value is
disregarded from the output signal WO[x].
Table 27-1. Module Request for TC
Condition Interrupt request Event output Event input DMA request
DMA request is
cleared
Overflow /
Underflow x x x Cleared on next
clock cycle
Channel
Compare Match
or Capture
x x x1
For compare
channel – Cleared
on next clock
cycle.
For capture
channel – cleared
when CCx
register is read
Capture Overflow
Error x
Synchronization
Ready x
Start Counter x
Retrigger
Counter x
Increment /
Decrement
counter
x
Simple Capture x
Period Capture x
Pulse Width
Capture x
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27.6.4.2 Interrupts
The TC has the following interrupt sources:
zOverflow/Underflow: OVF. This is an asynchronous interrupt and can be used to wake-up the device from any sleep
mode.
zCompare or Capture Channel: MCx. This is an asynchronous interrupt and can be used to wake-up the device from
any sleep mode.
zCapture Overflow Error: ERR. This is an asynchronous interrupt and can be used to wake-up the device from any
sleep mode.
zSynchronization Ready: SYNCRDY. This is an asynchronous interrupt and can be used to wake-up the device from
any sleep mode.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one
to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is
cleared, the interrupt is disabled or the TC is reset. See the INTFLAG register for details on how to clear interrupt flags.
The TC has one common interrupt request line for all the interrupt sources. The user must read the INTFLAG register to
determine which interrupt condition is present. Note that interrupts must be globally enabled for interrupt requests to be
generated. Refer to “Nested Vector Interrupt Controller” on page 29 for details.
27.6.4.3 Events
The TC can generate the following output events:
zOverflow/Underflow (OVF)
zMatch or Capture (MC)
Writing a one to an Event Output bit in the Event Control register (EVCTRL.MCEO) enables the corresponding output
event. Writing a zero to this bit disables the corresponding output event.
To enable one of the following event actions, write to the Event Action bit group (EVCTRL.EVACT).
zStart the counter
zRetrigger counter
zIncrement or decrement counter (depends on counter direction)
zCapture event
zCapture period
zCapture pulse width
Writing a one to the TC Event Input bit in the Event Control register (EVCTRL.TCEI) enables input events to the TC.
Writing a zero to this bit disables input events to the TC. Refer to “EVSYS – Event System” on page 400 for details on
configuring the Event System.
27.6.5 Sleep Mode Operation
The TC can be configured to operate in any sleep mode. To be able to run in standby, the RUNSTDBY bit in the Control
A register (CTRLA.RUNSTDBY) must be written to one. The TC can wake up the device using interrupts from any sleep
mode or perform actions through the Event System.
27.6.6 Synchronization
Due to the asynchronicity between CLK_TCx_APB and GCLK_TCx some registers must be synchronized when
accessed. A register can require:
zSynchronization when written
zSynchronization when read
zSynchronization when written and read
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zNo synchronization
When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. The Synchronization
Ready interrupt can be used to signal when synchronization is complete. This can be accessed via the Synchronization
Ready Interrupt Flag in the Interrupt Flag Status and Clear register (INTFLAG.SYNCRDY).
If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is
stalled.
The following bits need synchronization when written:
zSoftware Reset bit in the Control A register (CTRLA.SWRST)
zEnable bit in the Control A register (CTRLA.ENABLE)
Write-synchronization is denoted by the Write-Synchronized property in the register description.
The following registers need synchronization when written:
zControl B Clear register (CTRLBCLR)
zControl B Set register (CTRLBSET)
zControl C register (CTRLC)
zCount Value register (COUNT)
zPeriod Value register (PERIOD)
zCompare/Capture Value registers (CCx)
Write-synchronization is denoted by the Write-Synchronized property in the register description.
The following registers need synchronization when read:
zControl B Clear register (CTRLBCLR)
zControl B Set register (CTRLBSET)
zControl C register (CTRLC)
zCount Value register (COUNT)
zPeriod Value register (PERIOD)
zCompare/Capture Value registers (CCx)
Read-synchronization is denoted by the Read-Synchronized property in the register description.
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27.7 Register Summary
Table 27-2. Register Summary – 8-Bit Mode Registers
Offset Name Bit Pos.
0x00
CTRLA
7:0 WAVEGEN[1:0] MODE[1:0] ENABLE SWRST
0x01 15:8 PRESCSYNC[1:0] RUNSTDBY PRESCALER[2:0]
0x02
READREQ
7:0 ADDR[4:0]
0x03 15:8 RREQ RCONT
0x04 CTRLBCLR 7:0 CMD[1:0] ONESHOT DIR
0x05 CTRLBSET 7:0 CMD[1:0] ONESHOT DIR
0x06 CTRLC 7:0 CPTEN1 CPTEN0 INVEN1 INVEN0
0x07 Reserved
0x08 DBGCTRL 7:0 DBGRUN
0x09 Reserved
0x0A
EVCTRL
7:0 TCEI TCINV EVACT[2:0]
0x0B 15:8 MCEO1 MCEO0 OVFEO
0x0C INTENCLR 7:0 MC1 MC0 SYNCRDY ERR OVF
0x0D INTENSET 7:0 MC1 MC0 SYNCRDY ERR OVF
0x0E INTFLAG 7:0 MC1 MC0 SYNCRDY ERR OVF
0x0F STATUS 7:0 SYNCBUSY SLAVE STOP
0x10 COUNT 7:0 COUNT[7:0]
0x11 Reserved
0x12 Reserved
0x13 Reserved
0x14 PER 7:0 PER[7:0]
0x15 Reserved
0x16 Reserved
0x17 Reserved
0x18 CC0 7:0 CC[7:0]
0x19 CC1 7:0 CC[7:0]
0x1A Reserved
0x1B Reserved
0x1C Reserved
0x1D Reserved
0x1E Reserved
0x1F Reserved
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Table 27-3. Register Summary – 16-Bit Mode Registers
Offset Name Bit Pos.
0x00
CTRLA
7:0 WAVEGEN[1:0] MODE[1:0] ENABLE SWRST
0x01 15:8 PRESCSYNC[1:0] RUNSTDBY PRESCALER[2:0]
0x02
READREQ
7:0 ADDR[4:0]
0x03 15:8 RREQ RCONT
0x04 CTRLBCLR 7:0 CMD[1:0] ONESHOT DIR
0x05 CTRLBSET 7:0 CMD[1:0] ONESHOT DIR
0x06 CTRLC 7:0 CPTEN1 CPTEN0 INVEN1 INVEN0
0x07 Reserved
0x08 DBGCTRL 7:0 DBGRUN
0x09 Reserved
0x0A
EVCTRL
7:0 TCEI TCINV EVACT[2:0]
0x0B 15:8 MCEO1 MCEO0 OVFEO
0x0C INTENCLR 7:0 MC1 MC0 SYNCRDY ERR OVF
0x0D INTENSET 7:0 MC1 MC0 SYNCRDY ERR OVF
0x0E INTFLAG 7:0 MC1 MC0 SYNCRDY ERR OVF
0x0F STATUS 7:0 SYNCBUSY SLAVE STOP
0x10
COUNT
7:0 COUNT[7:0]
0x11 15:8 COUNT[15:8]
0x12 Reserved
0x13 Reserved
0x14 Reserved
0x15 Reserved
0x16 Reserved
0x17 Reserved
0x18
CC0
7:0 CC[7:0]
0x19 15:8 CC[15:8]
0x1A
CC1
7:0 CC[7:0]
0x1B 15:8 CC[15:8]
0x1C Reserved
0x1D Reserved
0x1E Reserved
0x1F Reserved
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Table 27-4. Register Summary – 32-Bit Mode Registers
Offset Name Bit Pos.
0x00
CTRLA
7:0 WAVEGEN[1:0] MODE[1:0] ENABLE SWRST
0x01 15:8 PRESCSYNC[1:0] RUNSTDBY PRESCALER[2:0]
0x02
READREQ
7:0 ADDR[4:0]
0x03 15:8 RREQ RCONT
0x04 CTRLBCLR 7:0 CMD[1:0] ONESHOT DIR
0x05 CTRLBSET 7:0 CMD[1:0] ONESHOT DIR
0x06 CTRLC 7:0 CPTEN1 CPTEN0 INVEN1 INVEN0
0x07 Reserved
0x08 DBGCTRL 7:0 DBGRUN
0x09 Reserved
0x0A
EVCTRL
7:0 TCEI TCINV EVACT[2:0]
0x0B 15:8 MCEO1 MCEO0 OVFEO
0x0C INTENCLR 7:0 MC1 MC0 SYNCRDY ERR OVF
0x0D INTENSET 7:0 MC1 MC0 SYNCRDY ERR OVF
0x0E INTFLAG 7:0 MC1 MC0 SYNCRDY ERR OVF
0x0F STATUS 7:0 SYNCBUSY SLAVE STOP
0x10
COUNT
7:0 COUNT[7:0]
0x11 15:8 COUNT[15:8]
0x12 23:16 COUNT[23:16]
0x13 31:24 COUNT[31:24]
0x14 Reserved
0x15 Reserved
0x16 Reserved
0x17 Reserved
0x18
CC0
7:0 CC[7:0]
0x19 15:8 CC[15:8]
0x1A 23:16 CC[23:16]
0x1B 31:24 CC[31:24]
0x1C
CC1
7:0 CC[7:0]
0x1D 15:8 CC[15:8]
0x1E 23:16 CC[23:16]
0x1F 31:24 CC[31:24]
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27.8 Register Description
Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters
and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by
the Write-Protected property in each individual register description. Refer to the “Register Access Protection” on page
571 and the “PAC – Peripheral Access Controller” on page 36 for details.
Some registers require synchronization when read and/or written. Synchronization is denoted by the Write-Synchronized
or Read-Synchronized property in each individual register description. Refer to “Synchronization” on page 580 for details.
Some registers are enable-protected, meaning they can only be written when the TC is disabled. Enable-protection is
denoted by the Enable-Protected property in each individual register description.
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27.8.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x0000
Property: Write-Protected, Enable-Protected, Write-Synchronized
zBits 15:14 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 13:12 – PRESCSYNC[1:0]: Prescaler and Counter Synchronization
These bits select whether on start or retrigger event the counter should wrap around on the next GCLK_TCx clock
or the next prescaled GCLK_TCx clock. It’s also possible to reset the prescaler.
The options are as shown in Table 27-5.
These bits are not synchronized.
Table 27-5. Prescaler and Counter Synchronization
zBit 11 – RUNSTDBY: Run in Standby
This bit is used to keep the TC running in standby mode:
0: The TC is halted in standby.
1: The TC continues to run in standby.
This bit is not synchronized.
zBits 10:8 – PRESCALER[2:0]: Prescaler
These bits select the counter prescaler factor, as shown in Table 27-6.
These bits are not synchronized.
Bit151413121110 9 8
PRESCSYNC[1:0] RUNSTDBY PRESCALER[2:0]
Access R R R/W R/W R/W R/W R/W R/W
Reset00000000
Bit76543210
WAVEGEN[1:0] MODE[1:0] ENABLE SWRST
Access R R/W R/W R R/W R/W R/W R/W
Reset00000000
Value Name Description
0x0 GCLK Reload or reset the counter on next generic clock
0x1 PRESC Reload or reset the counter on next prescaler clock
0x2 RESYNC Reload or reset the counter on next generic clock. Reset the prescaler counter
0x3 -Reserved
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Table 27-6. Prescaler
zBit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 6:5 – WAVEGEN[1:0]: Waveform Generation Operation
These bits select the waveform generation operation. They affect the top value, as shown in “Waveform Output
Operations” on page 574. It also controls whether frequency or PWM waveform generation should be used. How
these modes differ can also be seen from “Waveform Output Operations” on page 574.
These bits are not synchronized.
Table 27-7. Waveform Generation Operation
Note: 1. This depends on the TC mode. In 8-bit mode, the top value is the Period Value register (PER). In 16- and
32-bit mode it is the maximum value.
zBit 4 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 3:2 – MODE[1:0]: TC Mode
These bits select the TC mode, as shown in Table 27-8.
These bits are not synchronized.
Value Name Description
0x0 DIV1 Prescaler: GCLK_TC
0x1 DIV2 Prescaler: GCLK_TC/2
0x2 DIV4 Prescaler: GCLK_TC/4
0x3 DIV8 Prescaler: GCLK_TC/8
0x4 DIV16 Prescaler: GCLK_TC/16
0x5 DIV64 Prescaler: GCLK_TC/64
0x6 DIV256 Prescaler: GCLK_TC/256
0x7 DIV1024 Prescaler: GCLK_TC/1024
Value Name Operation Top Value
Waveform Output
on Match
Waveform Output
on Wraparound
0x0 NFRQ Normal frequency PER(1)/Max Tog gl e No action
0x1 MFRQ Match frequency CC0 To gg le No action
0x2 NPWM Normal PWM PER(1)/Max
Clear when
counting up
Set when counting
down
Set when counting
up
Clear when
counting down
0x3 MPWM Match PWM CC0
Clear when
counting up
Set when counting
down
Set when counting
up
Clear when
counting down
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Table 27-8. TC Mode
zBit 1 – ENABLE: Enable
0: The peripheral is disabled.
1: The peripheral is enabled.
Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRLA.ENABLE will read back immediately, and the Synchronization Busy bit in the Status regis-
ter (STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete.
zBit 0 – SWRST: Software Reset
0: There is no reset operation ongoing.
1: The reset operation is ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the TC, except DBGCTRL, to their initial state, and the TC will be
disabled.
Writing a one to CTRLA.SWRST will always take precedence; all other writes in the same write-operation will be
discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST
and STATUS.SYNCBUSY will both be cleared when the reset is complete.
Value Name Description
0x0 COUNT16 Counter in 16-bit mode
0x1 COUNT8 Counter in 8-bit mode
0x2 COUNT32 Counter in 32-bit mode
0x3 -Reserved
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27.8.2 Read Request
For a detailed description of this register and its use, refer to the“Synchronization” on page 580.
Name: READREQ
Offset: 0x02
Reset: 0x0000
Property: -
zBit 15 – RREQ: Read Request
Writing a zero to this bit has no effect.
This bit will always read as zero.
Writing a one to this bit requests synchronization of the register pointed to by the Address bit group (READ-
REQ.ADDR) and sets the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY).
zBit 14 – RCONT: Read Continuously
0: Continuous synchronization is disabled.
1: Continuous synchronization is enabled.
When continuous synchronization is enabled, the register pointed to by the Address bit group (READREQ.ADDR)
will be synchronized automatically every time the register is updated.
zBits 13:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 4:0 – ADDR[4:0]: Address
These bits select the offset of the register that needs read synchronization. In the TC, only COUNT and CCx are
available for read synchronization.
Bit151413121110 9 8
RREQ RCONT
AccessWR/WRRRRRR
Reset00000000
Bit76543210
ADDR[4:0]
Access R R R R/W R/W R/W R/W R/W
Reset00000000
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27.8.3 Control B Clear
This register allows the user to change this register without doing a read-modify-write operation. Changes in this register
will also be reflected in the Control B Set (CTRLBSET) register.
Name: CTRLBCLR
Offset: 0x04
Reset: 0x00
Property: Write-Protected, Write-Synchronized, Read-Synchronized
zBits 7:6 – CMD[1:0]: Command
These bits are used for software control of retriggering and stopping the TC. When a command has been exe-
cuted, the CMD bit group will read back as zero. The commands are executed on the next prescaled GCLK_TC
clock cycle.
Writing a zero to one of these bits has no effect.
Writing a one to one of these bits will clear the pending command.
Table 27-9. Command
zBits 5:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 2 – ONESHOT: One-Shot
This bit controls one-shot operation of the TC. When in one-shot mode, the TC will stop counting on the next over-
flow/underflow condition or a stop command.
0: The TC will wrap around and continue counting on an overflow/underflow condition.
1: The TC will wrap around and stop on the next underflow/overflow condition.
Writing a zero to this bit has no effect.
Writing a one to this bit will disable one-shot operation.
zBit 1 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 0 – DIR: Counter Direction
This bit is used to change the direction of the counter.
0: The timer/counter is counting up (incrementing).
Bit76543210
CMD[1:0] ONESHOT DIR
Access R/W R/W R R R R/W R R/W
Reset00000000
Value Name Description
0x0 NONE No action
0x1 RETRIGGER Force a start, restart or retrigger
0x2 STOP Force a stop
0x3 -Reserved
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1: The timer/counter is counting down (decrementing).
Writing a zero to this bit has no effect.
Writing a one to this bit will make the counter count up.
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27.8.4 Control B Set
This register allows the user to change this register without doing a read-modify-write operation. Changes in this register
will also be reflected in the Control B Set (CTRLBCLR) register.
Name: CTRLBSET
Offset: 0x05
Reset: 0x00
Property: Write-Protected, Write-Synchronized, Read-Synchronized
zBits 7:6 – CMD[1:0]: Command
These bits is used for software control of retriggering and stopping the TC. When a command has been executed,
the CMD bit group will be read back as zero. The commands are executed on the next prescaled GCLK_TC clock
cycle.
Writing a zero to one of these bits has no effect.
Writing a one to one of these bits will set a command.
Table 27-10. Command
zBits 5:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 2 – ONESHOT: One-Shot
This bit controls one-shot operation of the TC. When active, the TC will stop counting on the next overflow/under-
flow condition or a stop command.
0: The TC will wrap around and continue counting on an overflow/underflow condition.
1: The timer/counter will wrap around and stop on the next underflow/overflow condition.
Writing a zero to this bit has no effect.
Writing a one to this bit will enable one-shot operation.
zBit 1 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 0 – DIR: Counter Direction
This bit is used to change the direction of the counter.
0: The timer/counter is counting up (incrementing).
Bit76543210
CMD[1:0] ONESHOT DIR
Access R/W R/W R R R R/W R R/W
Reset00000000
Value Name Description
0x0 NONE No action
0x1 RETRIGGER Force a start, restart or retrigger
0x2 STOP Force a stop
0x3 -Reserved
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1: The timer/counter is counting down (decrementing).
Writing a zero to this bit has no effect
Writing a one to this bit will make the counter count down.
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27.8.5 Control C
Name: CTRLC
Offset: 0x06
Reset: 0x00
Property: Write-Protected, Write-Synchronized, Read-Synchronized
zBits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 5:4 – CPTENx: Capture Channel x Enable
These bits are used to select whether channel x is a capture or a compare channel.
Writing a one to CPTENx enables capture on channel x.
Writing a zero to CPTENx disables capture on channel x.
zBits 3:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 1:0 – INVENx: Waveform Output x Invert Enable
These bits are used to select inversion on the output of channel x.
Writing a one to INVENx inverts the output from WO[x].
Writing a zero to INVENx disables inversion of the output from WO[x].
Bit76543210
CPTEN1 CPTEN0 INVEN1 INVEN0
Access R R R/W R/W R R R/W R/W
Reset00000000
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27.8.6 Debug Control
Name: DBGCTRL
Offset: 0x08
Reset: 0x00
Property: Write-Protected
zBits 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 0 – DBGRUN: Debug Run Mode
This bit is not affected by a software reset, and should not be changed by software while the TC is enabled.
0: The TC is halted when the device is halted in debug mode.
1: The TC continues normal operation when the device is halted in debug mode.
Bit76543210
DBGRUN
Access R R R R R R R R/W
Reset00000000
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27.8.7 Event Control
Name: EVCTRL
Offset: 0x0A
Reset: 0x0000
Property: Write-Protected, Enable-Protected
zBits 15:14 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 13:12 – MCEOx: Match or Capture Channel x Event Output Enable
These bits control whether event match or capture on channel x is enabled or not and generated for every match
or capture.
0: Match/Capture event on channel x is disabled and will not be generated.
1: Match/Capture event on channel x is enabled and will be generated for every compare/capture.
These bits are not enable-protected.
zBits 11:9 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 8 – OVFEO: Overflow/Underflow Event Output Enable
This bit is used to enable the Overflow/Underflow event. When enabled an event will be generated when the coun-
ter overflows/underflows.
0: Overflow/Underflow event is disabled and will not be generated.
1: Overflow/Underflow event is enabled and will be generated for every counter overflow/underflow.
This bit is not enable-protected.
zBits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 5 – TCEI: TC Event Input
This bit is used to enable input events to the TC.
0: Incoming events are disabled.
1: Incoming events are enabled.
This bit is not enable-protected.
Bit151413121110 9 8
MCEO1 MCEO0 OVFEO
Access R R R/W R/W R R R R/W
Reset00000000
Bit76543210
TCEI TCINV EVACT[2:0]
Access R R R/W R/W R R/W R/W R/W
Reset00000000
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zBit 4 – TCINV: TC Inverted Event Input
This bit inverts the input event source when used in PWP or PPW measurement.
0: Input event source is not inverted.
1: Input event source is inverted.
This bit is not enable-protected.
zBit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 2:0 – EVACT[2:0]: Event Action
These bits define the event action the TC will perform on an event,as shown in Table 27-11.
Table 27-11. Event Action
Value Name Description
0x0 OFF Event action disabled
0x1 RETRIGGER Start, restart or retrigger TC on event
0x2 COUNT Count on event
0x3 START Start TC on event
0x4 -Reserved
0x5 PPW Period captured in CC0, pulse width in CC1
0x6 PWP Period captured in CC1, pulse width in CC0
0x7 -Reserved
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27.8.8 Interrupt Enable Clear
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x0C
Reset: 0x00
Property: Write-Protected
zBits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 5:4 – MCx: Match or Capture Channel x Interrupt Enable
0: The Match or Capture Channel x interrupt is disabled.
1: The Match or Capture Channel x interrupt is enabled.
Writing a zero to MCx has no effect.
Writing a one to MCx will clear the corresponding Match or Capture Channel x Interrupt Disable/Enable bit, which
disables the Match or Capture Channel x interrupt.
zBit 3 – SYNCRDY: Synchronization Ready Interrupt Enable
0: The Synchronization Ready interrupt is disabled.
1: The Synchronization Ready interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Disable/Enable bit, which disables the Syn-
chronization Ready interrupt.
zBit 2 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 1 – ERR: Error Interrupt Enable
0: The Error interrupt is disabled.
1: The Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Error Interrupt Disable/Enable bit, which disables the Error interrupt.
zBit 0 – OVF: Overflow Interrupt Enable
0: The Overflow interrupt is disabled.
1: The Overflow interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overflow Interrupt Disable/Enable bit, which disables the Overflow interrupt.
Bit76543210
MC1 MC0 SYNCRDY ERR OVF
Access R R/W R/W R/W R/W R R/W R/W
Reset00000000
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27.8.9 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name: INTENSET
Offset: 0x0D
Reset: 0x00
Property: Write-Protected
zBits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 5:4 – MCx: Match or Capture Channel x Interrupt Enable
0: The Match or Capture Channel x interrupt is disabled.
1: The Match or Capture Channel x interrupt is enabled.
Writing a zero to MCx has no effect.
Writing a one to MCx will set the corresponding Match or Capture Channel x Interrupt Enable bit, which enables
the Match or Capture Channel x interrupt.
zBit 3 – SYNCRDY: Synchronization Ready Interrupt Enable
0: The Synchronization Ready interrupt is disabled.
1: The Synchronization Ready interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Synchronization Ready Interrupt Disable/Enable bit, which enables the Syn-
chronization Ready interrupt.
zBit 2 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 1 – ERR: Error Interrupt Enable
0: The Error interrupt is disabled.
1: The Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Error Interrupt bit, which enables the Error interrupt.
zBit 0 – OVF: Overflow Interrupt Enable
0: The Overflow interrupt is disabled.
1: The Overflow interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt.
Bit76543210
MC1 MC0 SYNCRDY ERR OVF
Access R R R/W R/W R/W R R/W R/W
Reset00000000
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27.8.10 Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x0E
Reset: 0x00
Property: -
zBits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 5:4 – MCx: Match or Capture Channel x
This flag is set on the next CLK_TC_CNT cycle after a match with the compare condition or once CCx register
contain a valid capture value, and will generate an interrupt request if the corresponding Match or Capture Chan-
nel x Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.MCx) is one.
Writing a zero to one of these bits has no effect.
Writing a one to one of these bits will clear the corresponding Match or Capture Channel x interrupt flag
In capture mode, this flag is automatically cleared when CCx register is read.
zBit 3 – SYNCRDY: Synchronization Ready
This flag is set on a 1-to-0 transition of the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY),
except when the transition is caused by an enable or software reset, and will generate an interrupt request if the
Synchronization Ready Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.SYNCRDY) is one.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready interrupt flag
zBit 2 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 1 – ERR: Error
This flag is set if a new capture occurs on a channel when the corresponding Match or Capture Channel x interrupt
flag is one, in which case there is nowhere to store the new capture.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Error interrupt flag.
zBit 0 – OVF: Overflow
This flag is set on the next CLK_TC_CNT cycle after an overflow condition occurs, and will generate an interrupt if
INTENCLR/SET.OVF is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Overflow interrupt flag.
Bit 7 6 5 4 3 2 1 0
MC1 MC0 SYNCRDY ERR OVF
Access R R R/W R/W R/W R R/W R/W
Reset 0 0 0 0 0 0 0 0
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27.8.11 Status
Name: STATUS
Offset: 0x0F
Reset: 0x08
Property: -
zBit 7 – SYNCBUSY: Synchronization Busy
This bit is cleared when the synchronization of registers between the clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
zBits 6:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 4 – SLAVE: Slave
This bit is set when the even-numbered master TC is set to run in 32-bit mode. The odd-numbered TC will be the
slave.
zBit 3 – STOP: Stop
This bit is set when the TC is disabled, on a Stop command or on an overflow or underflow condition when the
One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT) is one.
0: Counter is running.
1: Counter is stopped.
zBits 2:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit76543210
SYNCBUSY SLAVE STOP
AccessRRRRRRRR
Reset00001000
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27.8.12 Counter Value
27.8.12.1 8-Bit Mode
Name: COUNT
Offset: 0x10
Reset: 0x00
Property: Write-Synchronized, Read-Synchronized
zBits 7:0 – COUNT[7:0]: Counter Value
These bits contain the current counter value.
Bit76543210
COUNT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
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27.8.12.2 16-Bit Mode
Name: COUNT
Offset: 0x10
Reset: 0x0000
Property: Write-Synchronized, Read-Synchronized
zBits 15:0 – COUNT[15:0]: Counter Value
These bits contain the current counter value.
Bit151413121110 9 8
COUNT[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
Bit76543210
COUNT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
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27.8.12.3 32-Bit Mode
Name: COUNT
Offset: 0x10
Reset: 0x00000000
Property: Write-Synchronized, Read-Synchronized
zBits 31:0 – COUNT[31:0]: Counter Value
These bits contain the current counter value.
Bit3130292827262524
COUNT[31:24]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
Bit151413121110 9 8
COUNT[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
Bit2322212019181716
COUNT[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
Bit76543210
COUNT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
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27.8.13 Period Value
The Period Value register is available only in 8-bit TC mode. It is not available in 16-bit and 32-bit TC modes.
27.8.13.1 8-Bit Mode
Name: PER
Offset: 0x14
Reset: 0xFF
Property: Write-Synchronized, Read-Synchronized
zBits 7:0 – PER[7:0]: Period Value
These bits contain the counter period value in 8-bitTC mode.
Bit76543210
PER[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset11111111
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27.8.14 Compare/Capture
27.8.14.1 8-Bit Mode
Name: CCx
Offset: 0x18+i*0x1 [i=0..3]
Reset: 0x00
Property: Write-Synchronized, Read-Synchronized
zBits 7:0 – CC[7:0]: Compare/Capture Value
These bits contain the compare/capture value in 8-bit TC mode. In frequency or PWM waveform match operation
(CTRLA.WAVEGEN), the CC0 register is used as a period register.
Bit76543210
CC[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
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27.8.14.2 16-Bit Mode
Name: CCx
Offset: 0x18+i*0x2 [i=0..3]
Reset: 0x0000
Property: Write-Synchronized, Read-Synchronized
zBits 15:0 – CC[15:0]: Compare/Capture Value
These bits contain the compare/capture value in 16-bit TC mode. In frequency or PWM waveform match operation
(CTRLA.WAVEGEN), the CC0 register is used as a period register.
Bit151413121110 9 8
CC[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
Bit76543210
CC[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
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27.8.14.3 32-Bit Mode
Name: CCx
Offset: 0x18+i*0x4 [i=0..3]
Reset: 0x00000000
Property: Write-Synchronized, Read-Synchronized
zBits 31:0 – CC[31:0]: Compare/Capture Value
These bits contain the compare/capture value in 32-bit TC mode. In frequency or PWM waveform match opera-
tion (CTRLA.WAVEGEN), the CC0 register is used as a period register.
Bit3130292827262524
CC[31:24]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
Bit2322212019181716
CC[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
Bit151413121110 9 8
CC[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
Bit76543210
CC[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
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28. TCC – Timer/Counter for Control Applications
28.1 Overview
The Timer/Counter for Control applications (TCC) consists of a counter, a prescaler, compare/capture channels and
control logic. The counter can be set to count events or clock pulses. The counter together with the compare/capture
channels can be configured to time stamp input events, allowing capture of frequency and pulse-width. It can also
perform waveform generation such as frequency generation and pulse-width modulation.
Waveform extensions are intended for motor control, ballast, LED, H-bridge, power converters, and other types of power
control applications. It enables low- and high-side output with optional dead-time insertion. It can also generate a
synchronized bit pattern across the waveform output pins. The fault options enable fault protection for safe and
deterministic handling, disabling and/or shut down of external drivers.
The Timer/Counter Block diagram (Figure 28-2 on page 610) shows all the features in TCC but table below shows the
configuration of each of the TCCs.
Figure 28-1. TCC Configuration Summary
28.2 Features
zUp to four compare/capture channels (CC) with:
zDouble buffered period setting
zDouble buffered compare or capture channel
zCircular buffer on period and compare channel registers
zWaveform generation:
zFrequency generation
zSingle-slope pulse-width modulation (PWM)
zDual-slope pulse-width modulation with half-cycle reload capability
zInput capture:
zEvent capture
zFrequency capture
zPulse-width capture
zWaveform extensions:
zConfigurable distribution of compare channels outputs across port pins
zLow- and high-side output with programmable dead-time insertion
zWaveform swap option with double buffer support
zPattern generation with double buffer support
zDithering support
zFault protection for safe drivers disabling:
zTwo recoverable fault sources
zTwo non-recoverable fault sources
zDebugger can be source of non-recoverable fault
zInput event:
zTwo input events for counter
TCC#
Channels
(CC_NUM)
Waveform
Output
(WO_NUM)
Counter
size Fault Dithering
Output
matrix
Dead
Time
Insertion
(DTI) SWAP
Pattern
generation
0 4 6 24-bit X X X X X X
1 2 4 24-bit X X X
2 2 2 16-bit X
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zOne input event for each channel
zOutput event:
zThree output events (Count, Retrigger and Overflow) available for counter
zOne Compare Match/Input Capture event output for each channel
zInterrupts:
zOverflow and Retrigger interrupt
zCompare Match/Input Capture interrupt
zInterrupt on fault detection
zCan be used with DMA and can trigger DMA transactions
28.3 Block Diagram
Figure 28-2. Timer/Counter Block Diagram
28.4 Signal Description
Refer to Table 5-1 in the “I/O Multiplexing and Considerations” on page 12 for details on the pin mapping for this
peripheral. One signal can be mapped on several pins.
Base Counter
Compare/Capture
(Unit x = {0,1,…,3})
Counter
=
CCx
CCBx
Waveform
Generation
BV
=
PERB
PER
COUNT
BV
= 0
"count"
"clear"
"direction"
"load" Control Logic
Prescaler
OVF (INT/Event/DMA Req.)
ERR (INT Req.)
TOP
"match" MCx (INT/Event/DMA Req.)
Control Logic
"capture"
"ev"
UPDATE
BOTTOM
Recoverable
Faults
Output
Matrix
Dead-Time
Insertion
SWAP
Pattern
Generation
Non-recoverable
Faults
WO[0]
WO[1]
WO[2]
WO[3]
WO[4]
WO[5]
WO[6]
WO[7]
Event
System
"TCCx_EV0"
"TCCx_EV1"
"TCCx_MCx"
Pin Name Type Description
TCCx/WO[0] Digital output Compare channel 0 waveform output
TCCx/WO[1] Digital output Compare channel 1 waveform output
…... ...
TCCx/WO[WO_NUM-1] Digital output Compare channel n waveform output
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28.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
28.5.1 I/O Lines
Using the TCC’s I/O lines requires the I/O pins to be configured. Refer to “PORT” on page 373 for details.
28.5.2 Power Management
The TCC will continue to operate in any sleep mode where the selected source clock is running. The TCC’s interrupts
can be used to wake up the device from sleep modes. Events connected to the event system can trigger other operations
in the system without exiting sleep modes. Refer to “PM – Power Manager” on page 112 for details on the different sleep
modes.
28.5.3 Clocks
The TCC bus clock (CLK_TCCx_APB, where x represents the specific TCC instance number) can be enabled and
disabled in the power manager, and the default state of CLK_TCCx_APB can be found in the Peripheral Clock Masking
section in “PM – Power Manager” on page 112
.
A generic clock (GCLK_TCCx) is required to clock the TCC. This clock must be configured and enabled in the generic
clock controller before using the TCC. Refer to “GCLK – Generic Clock Controller” on page 90 for details.
This generic clock is asynchronous to the bus clock (CLK_TCCx_APB). Due to this asynchronicity, writes to certain
registers will require synchronization between the clock domains. Refer to “Synchronization” on page 641 for further
details.
28.5.4 DMA
The DMA request lines are connected to the DMA Controller (DMAC). Using the TCC DMA requests, requires the DMA
Controller to be configured first. Refer to “DMAC – Direct Memory Access Controller” on page 267 for details.
28.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the TCC interrupts requires the interrupt
controller to be configured first. Refer to “Nested Vector Interrupt Controller” on page 29 for details.
28.5.6 Events
The events are connected to the Event System. Refer to “EVSYS – Event System” on page 400 for details on how to
configure the Event System.
28.5.7 Debug Operation
When the CPU is halted in debug mode the TCC will halt normal operation. The TCC can be forced to continue operation
during debugging. Refer to DBGCTRL for details.
28.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the
following registers:
zInterrupt Flag register (INTFLAG)
zStatus register (STATUS)
zPeriod and Period Buffer registers (PER, PERB)
zCompare/Capture and Compare/Capture Buffer registers (CCx, CCBx)
zControl Waveform and Control Waveform Buffer registers (WAVE, WAVEB)
zPattern Generation Value and Pattern Generation Value Buffer registers (PATT, PATTB)
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Write-protection is denoted by the Write-Protected property in the register description.
Write-protection does not apply to accesses through an external debugger. Refer to “PAC – Peripheral Access
Controller” on page 36 for details.
28.5.9 Analog Connections
Not applicable.
28.6 Functional Description
28.6.1 Principle of Operation
Each TCC instance has up to four compare/capture channels (CCx).
The following definitions are used throughout the documentation:
In general, the term “timer” is used when the timer/counter clock control is handled by an internal source, and the term
“counter” is used when the clock control is handled externally (e.g. counting external events). When used for compare
operations, the CC channels are referred to as “compare channels.” When used for capture operations, the CC channels
are referred to as “capture channels.”
The counter register (COUNT), period registers with buffer (PER and PERB), and compare and capture registers with
buffers (CCx and CCxB) are 16 or 24-bit registers, depending on each TCC instance. Each buffer register has a buffer
valid (BV) flag that indicates when the buffer contains a new value. During normal operation, the counter value is
continuously compared to the Period (TOP) and to ZERO value to determine whether the counter has reached TOP or
ZERO.
The counter value is also compared to the CCx registers. These comparisons can be used to generate interrupt
requests, request DMA transactions or generate events for the event system. The waveform generator modes use these
comparisons to set the waveform period or pulse width.
A prescaled generic clock (GCLK_TCCx) and events from the event system can be used to control the counter. The
event system is also used as a source to the input capture.
The recoverable fault module extension enables event controlled waveforms by acting directly on the generated
waveforms from TCC compare channels output. These events can restart, halt the timer/counter period or shorten the
output pulse active time, or disable waveform output as long as the fault condition is present. This can typically be used
for current sensing regulation or zero crossing and demagnetization retriggering.
The MCE0 and MCE1 event sources are shared with the recoverable fault module. Only asynchronous events are used
internally when fault unit extension is enabled. For further details on how to configure asynchronous events routing, refer
to section “EVSYS – Event System” on page 400.
By using digital filtering and/or input blanking, qualification options (as detailed in “Recoverable Faults” on page 629),
recoverable fault sources can be filtered and/or windowed to avoid false triggering, for example from I/O pin glitches.
Figure 28-3. Timer/Counter Definitions
Name Description
TOP
The counter reaches TOP when it becomes equal to the highest value in the count sequence. The TOP
value can be equal to the period (PER) or the compare channel A (CCA) register setting. This is selected by
the waveform generator mode.
BOTTOM The counter reaches BOTTOM when it becomes zero
MAX The counter reaches maximum when it becomes all ones
UPDATE The timer/counter signals an update when it reaches BOTTOM or TOP, depending on the direction settings.
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In addition as shown in Figure 28-2 on page 610, six optional independent and successive units primarily intended for
use with different types of motor control, ballast, LED, H-bridge, power converter, and other types of power switching
applications, are implemented in some of TCC instances.
The output matrix (OTMX) can distribute and route out the TCC waveform outputs across the port pins in different
configurations, each optimized for different application types.
The dead time insertion (DTI) unit splits the four lower OTMX outputs into two non-overlapping signals, the non-inverted
low side (LS) and inverted high side (HS) of the waveform output with optional dead-time insertion between LS and HS
switching.
The swap (SWAP) unit can be used to swap the LS and HS pin outputs, and can be used for fast decay motor control.
The pattern generation unit can be used to generate synchronized waveforms with constant logic level on TCC update
conditions. This is for example useful for easy stepper motor and full bridge control.
The non-recoverable fault module enables event controlled fault protection by acting directly on the generated
waveforms from timer/counter compare channels output. When a non-recoverable fault condition is detected, the output
waveforms are forced to a safe and pre-configured value that is safe for the application. This is typically used for instant
and predictable shut down and disabling high current or voltage drives.
The count event sources (TCE0 and TCE1) are shared with the non-recoverable fault extension. The events can be
optionally filtered. If the filter options are not used, the non-recoverable faults provide an immediate asynchronous action
on waveform output, even for cases where the clock is not present. For further details on how to configure asynchronous
events routing, refer to section “EVSYS – Event System” on page 400.
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28.6.2 Basic Operation
28.6.2.1 Initialization
The following registers are enable-protected, meaning that it can only be written when the TCC is disabled
(CTRLA.ENABLE is zero):
zControl A (CTRLA) register, except Run Standby (RUNSTDBY), Enable (ENABLE) and Software Reset
(SWRST) bits
zRecoverable Fault n Control register (FCTRLA and FCTRLB)
zWaveform Extension Control register (WEXCTRL)
zDrive Control register (DRVCTRL)
zEvent Control register
Enable-protected bits in the CTRLA register can be written at the same time as CTRLA.ENABLE is written to one, but not
at the same time as CTRLA.ENABLE is written to zero.
Enable-protection is denoted by the Enable-Protected property in the register description.
Before the TCC is enabled, it must be configured as outlined by the following steps:
zEnable the TCC bus clock (CLK_TCCx_APB) first
zIf Capture mode is required, enable the channel in capture mode by writing a one to Capture Enable bit in
Control A register (CTRLA.CAPTEN)
Optionally, the following configurations can be set before or after enabling TCC:
zSelect PRESCALER setting in the Control A register (CTRLA.PRESCALER)
zSelect Prescaler Synchronization setting in Control A register (CTRLA.PRESCSYNC)
zIf down-counting operation must be enabled, write a one to the Counter Direction bit in the Control B Set
register (CTRLBSET.DIR)
zSelect the Waveform Generation operation in WAVE register (WAVE.WAVEGEN)
zSelect the Waveform Output Polarity in the WAVE register (WAVE.POL)
zThe waveform output can be inverted for the individual channels using the Waveform Output Invert Enable
bit group in the Driver register (DRVCTRL.INVEN)
28.6.2.2 Enabling, Disabling and Resetting
The TCC is enabled by writing a one to the Enable bit in the Control A register (CTRLA.ENABLE). The TCC is disabled
by writing a zero to CTRLA.ENABLE.
The TCC is reset by writing a one to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in the
TCC, except DBGCTRL, will be reset to their initial state, and the TCC will be disabled. Refer to CTRLA register for
details.
The TCC should be disabled before the TCC is reset to avoid undefined behavior.
28.6.2.3 Prescaler Selection
The GCLK_TCCx is fed into the internal prescaler. Prescaler output intervals from 1 to 1/1024 are available. For a
complete list of available prescaler outputs, see the register description for the Prescaler bit group in the Control A
register (CTRLA.PRESCALER).
The prescaler consists of a counter that counts to the selected prescaler value, whereupon the output of the prescaler
toggles. When the prescaler is set to a value greater than one, it is necessary to choose whether the prescaler should
reset its value to zero or continue counting from its current value on the occurrence of an external re-trigger. It is also
necessary to choose whether the TCC counter should wrap around on the next GCLK_TCC clock pulse or the next
prescaled clock pulse (CLK_TCC_CNT in Figure 28-4). To do this, use the Prescaler and Counter synchronization bit
group in the Control A register (CTRLA.PRESYNC). If the counter is set to count events from the event system, these will
not pass through the prescaler.
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Figure 28-4. Prescaler
28.6.2.4 Counter Operation
Depending on the mode of operation, the counter is cleared, reloaded, incremented, or decremented at each TCC clock
cycle (CLK_TCC_CNT). A counter clear or reload mark the end of current counter cycle and the start of a new one.
The counter will count in the direction set by the direction (CTRLBSET.DIR or CTRLBCLR.DIR) bit for each clock until it
reaches TOP or ZERO. A clear operation occurs when the TOP is reached while up-counting, the counter will be set to
ZERO (cleared) on the next clock cycle. A reload operation occurs when the ZERO is reached while down-counting, the
counter is reloaded with the period register (PER) value.
The counter value is continuously compared with the period (PER) and ZERO value to determine if the counter has
reached TOP or ZERO. Based on this comparison, the Overflow Interrupt Flag in the Interrupt Flag Status and Clear
register (INTFLAG.OVF)is set whenever the counter value matches with TOP / ZERO. This can be used to trigger an
interrupt, a DMA request, or an event. If the One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT) is set, the
compare match (with TOP/ZERO) will stop the counting operation.
Up-counting is enabled by writing a one to the Direction bit in the Control B Clear register (CTRLBCLR.DIR). Down-
counting is enabled by writing a one to the Direction bit in the Control B Set register (CTRLBSET.DIR).
Figure 28-5. Counter Operation
As shown in Figure 28-5, it is possible to change the counter value (by writing directly in the Count register) even when
the counter is running. The write access has higher priority than count, clear, or reload. The direction of the counter can
also be changed during normal operation. Due to asynchronous clock domains, the internal counter settings are written
when the synchronization is complete.
Normal operation must be used when using the counter as timer base for the capture channels.
Stop Command and Event Action
A stop command can be issued from software by using TCC Command bits in Control B Set register (CTRLBSET.CMD =
STOP) or when the stop event action is configured in the Input Event1 Action bits in Event Control register
(EVCTRL.EVACT1 = STOP).
When a stop is detected while the counter is running, the counter will maintain its current value. If waveform generation
(WG) is used, all waveforms are set to a state defined in Non-Recoverable State x Output Enable bit and Non-
TCCx EV0/1
COUNT
PRESCALER
PRESCALER EVACT 0/1
GCLK_TCC
GCLK_TCC /
{1,2,4,8,64,256,1024 } CLK_TCC_COUNT
DIR
COUNT
MAX
"reload" update
TOP
COUNT writtenDirection Change
Period (T)
ZERO
"clear" update
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Recoverable State x Output Value bit in the Driver Control register.(DRVCTRL.NRE and DRVCTRL.NRV) and the Stop
bit in the Status register is set (STATUS.STOP).
Retrigger Command and Event Action
A retrigger command can be issued from software by using TCC Command bits in Control B Set register
(CTRLBSET.CMD = RETRIGGER) or when the retrigger event action is configured in the Input Event0/1 Action bits in
Event Control register (EVCTRL.EVACT1 = RETRIGGER).
When the command is detected during counting operation, the counter will be reloaded or cleared, depending on the
counting direction (CTRLSET.DIR or CTRLBCLR.DIR). The Retrigger bit will be set in the Interrupt Flag Status and Clear
register (INTFLAG.TRG). It is also possible to generate an event by writing a one to the Retrigger Event Output Enable
bit in the Event Control register (EVCTRL.TRGEO).
If the retrigger command is detected when the counter is stopped, the counter will resume counting operation from the
value in COUNT.
Note: When re-trigger event action is enabled, enabling the counter will not start the counter. The counter will start on the
next incoming event and restart on corresponding following event.
Start Event Action
The start action can be selected in the Event Control register (EVCTRL.EVACT0) and can be used to start the counting
operation when stopped. As consequence, the event has no effect if the counter is already counting. When the module is
enabled, the counter operation starts when the event is received or when a retrigger software command is applied.When
retrigger or start event action is enabled, enabling counter will not start the counter. The counter will start on the next
incoming event and restart on corresponding following event. If the event action is disabled, enabling counter will start
the counter.
Count Event Action
The count action can be selected in the Event Control register (EVCTRL.EVACT0) and can be used to count external
events (from pins for example). When an event is received, the counter is incremented or decremented, depending on
direction settings (CTRLBSET.DIR or CTRLBCLR.DIR).
Direction Event Action
The direction event action can be selected in the Event Control register (EVCTRL.EVACT1). When this event is used,
the asynchronous event path specified in the event system must be configured or selected. The direction event action
can be used to control the direction of the counter operation, depending on external events level. When received, the
event level overrides the Direction settings (CTRLBSET.DIR or CTRLBCLR.DIR) and the direction bit value is updated
accordingly.
Increment Event Action
The increment event action can be selected in the Event Control register (EVCTRL.EVACT0) and can be used to change
the counter state when an event is received. When the TCE0 event is received, the counter increments, whatever
direction settings (CTRLBSET.DIR or CTRLBCLR.DIR) is.
Decrement Event Action
The decrement event action can be selected in the Event Control register (EVCTRL.EVACT1) and can be used to
change the counter state when an event is received. When the TCE1 event is received, the counter decrements,
whatever direction settings (CTRLBSET.DIR or CTRLBCLR.DIR) is.
Non-Recoverable Fault Event Action
Non-recoverable fault actions can be selected in the Event Control register (EVCTRL.EVACT0 or EVCTRL.EVACT1).
When received, the counter will be stopped and compare channels outputs are overridden according to DRVCTRL
register settings (Non-Recoverable State x Output Enable bits and Non-Recoverable State x Output Value bits).
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TCE0 and TCE1 must be configured as asynchronous events.
28.6.2.5 Compare Operations
By default, Compare/Capture channel is configured for Compare operations. To perform capture operations, it must be
re-configured.
When using the TCC with the Compare/Capture Value registers (CCx) configured for compare operations, the counter
value is continuously compared to the values in the CCx registers. This can be used for timer or for waveform operation.
The compare buffer (CCBx) register provides double buffer capability. The double buffering synchronizes the update of
the CCx register with the buffer value at the UPDATE condition. For further details, refer to “Double Buffering” on page
621. The synchronization prevents the occurrence of odd-length, non-symmetrical pulses and ensures glitch-free output.
If Compare/Capture channel is not configured for capture operation Control A register), then compare operation will be
enabled.
Waveform Output Generation Operations
The compare channels can be used for waveform generation on output port pins. To make the waveform visible on the
connected pin, the following requirements must be fulfilled:
1. Choose a waveform generation mode in the Waveform Control register (WAVE.WAVEGEN)
2. Optionally invert the waveform output WO[x] by writing the corresponding Waveform Output Invert Enable
bit in the Driver Control register (DRVCTRL.INVENx)
3. Configure the PORT module to enable the peripheral function on the pin
The counter value is continuously compared with each CCx value. When a compare match occurs, the Match or Capture
Channel x bit in the Interrupt Flag Status and Clear register (INTFLAG.MCx) is set on the next zero-to-one transition of
CLK_TCC_COUNT. If Match/Capture occurs, interrupt can be generated when INTENSET.MCX is set. If
Compare/Match occurs, an event can be triggered when EVCTRL.MCEOx is set to one. Both interrupt and event can be
generated simultaneously. The same condition generates a DMA request.
Six waveform configurations are available through the Waveform Generation (WG) bit group in the Waveform Control
register (WAVE.WAVEGEN):
zNormal Frequency (NFRQ)
zMatch Frequency (MFRQ)
zSingle-slope PWM (NPWM)
zDual-slope, interrupt/event at Top (DSTOP)
zDual-slope, interrupt/event at ZERO (DSBOTTOM)
zDual-slope, interrupt/event at Top and ZERO (DSBOTH)
zDual-slope, critical interrupt/event at ZERO (DSCRITICAL)
When using MFRQ, the top value is defined by the CC0 register value, for all other waveforms operation the top value is
defined by Period (PER) register value.
For dual slope waveform operations update time occurs when counter reaches the zero value. For all other waveforms
generation modes, the update time occurs on counter wraparound, on overflow, underflow or retrigger.
Normal Frequency Generation
For normal frequency generation, the period time is controlled by the period register (PER). The waveform generation
output (WO[x]) is toggled on each compare match between COUNT and CCx, and the corresponding Match or Capture
Channel x will be set.
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Figure 28-6. Normal Frequency Operation
Match Frequency Generation
For match frequency generation, the period time is controlled by CC0 instead of PER. WO[0] toggles on each update
condition.
Figure 28-7. Match Frequency Operation
Single-Slope PWM Generation
For single-slope PWM generation, the period time is controlled by PER, while CCx control the duty cycle of the generated
waveform output. When up-counting, WO[x] is set at start or compare match between the COUNT and TOP values, and
cleared on compare match between COUNT and CCx register values.
When down-counting, WO[x] is cleared at start or compare match between the COUNT and TOP values, and set on
compare match between COUNT and CCx register values.
Figure 28-8. Single-Slope PWM Operation
COUNT
MAX
TOP
ZERO
CCx
WO[x]
Direction ChangePeriod (T) COUNT Written
"reload" update
"clear" update
"match"
COUNT
MAX
CC0
COUNT WrittenDirection Change
Period (T)
ZERO
WO[0]
"reload" update
"clear" update
COUNT
MAX
TOP
Period (T)
"match"
ZERO
CCx=ZERO
CCx
CCx=TOP
"clear" update
WO[x]
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The following equation calculates the exact resolution for a single-slope PWM (RPWM_SS) waveform:
The PWM frequency depends on the Period register value (PER) and the peripheral clock frequency (fGCLK_TCC), and can
be
calculated by the following equation:
Where N represent the prescaler divider used (1, 2, 4, 8, 16, 64, 256, 1024).
Dual-Slope PWM Generation
For dual-slope PWM generation, the period (TOP) is controlled by PER, while CCx control the duty cycle of the
generated waveform output. Figure 28-9 shows how the counter repeatedly counts from ZERO (BOTTOM) to PER and
then from PER to ZERO. The waveform generator output is set on compare match when up-counting, and cleared on
compare match when down-counting. An interrupt/event is generated on TOP and/or ZERO depend of Dual slope
operation selected Table 28-1. In DSBOTH operation, a second update time occur on TOP.
Figure 28-9. Dual-Slope Pulse Width Modulation
Using dual-slope PWM results in a lower maximum operation frequency compared to single-slope PWM generation.
The period (TOP) defines the PWM resolution. The minimum resolution is 1 bits (TOP=0x00000001).
The following equation calculates the exact resolution for dual-slope PWM (RPWM_DS):
The PWM frequency depends on the period setting (TOP) and the peripheral clock frequency (fGCLK_TCC), and can be
calculated by the following equation:
RPWM_SS
log(TOP+1)
log(2)
-----------------------------
=
fPWM_SS
fGCLK_TCC
N(TOP+1)
--------------------------
=
COUNT
Period (T) CCx=ZERO
CCx
CCx=TOP
WO[x]
ZERO
TOP
MAX "match"
"update"
RPWM_DS
log(PER+1)
log(2)
-----------------------------
=
fPWM_DS
fGCLK_TCC
2NPER⋅
--------------------------
=
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N represents the prescaler divider used. The waveform generated will have a maximum frequency of half of the TCC
clock frequency (fGCLK_TCC) when TOP is set to one (0x00000001) and no prescaling is used.
The pulse width (PPWM_DS) depends on the compare channel (CCx) register value and the peripheral clock frequency
(fGCLK_TCC), and can be calculated by the following equation:
Where N represents the prescaler divider used.
Note: In DSTOP, DSBOTTOM and DSBOTH operation, when TOP is lower than MAX/2 the CCx MSB bit defines the
ramp (rising if CCx[MSB] is 0, or falling if CCx[MSB] is 1) on which the CCx Match interrupt or event is generated.
Dual-Slope Critical PWM Generation
Critical mode operation allows generation of non-aligned centered pulses. In this mode, the period time is controlled by
PER, while CCx control the generated waveform output edge during up-counting and CC(x+CC_NUM/2) control the
generated waveform output edge during down-counting.
Figure 28-10.Dual-Slope Critical Pulse Width Modulation (N=CC_NUM)
The table below shows the update counter and overflow event/interrupt generation conditions in different operation
modes.
PPWM_DS
2N PER CCx–()⋅
fGCLK_TCC
---------------------------------------------
=
COUNT
Period (T)
CCx
WO[x]
ZERO
TOP
MAX "match"
"reload" update
CC(x+N/2) CCx CC(x+N/2) CCx CC(x+N/2)
Table 28-1. Counter Update and Overflow Event/Interrupt Conditions
Description Description
Name Operation Top Update
Output
Waveform
On Match
Output
Waveform
On Update
OVFIF/Event
Up Down
NFRQ Normal Frequency PER TOP/ZERO Toggle Stable TOP ZERO
MFRQ Match Frequency CC0 TOP/ZERO Toggle Stable TOP ZERO
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Output Polarity
The polarity (WAVE.POLx) is available in all waveform output generation. In single-slope and dual-slope PWM
generation, it is possible to invert individually the pulse edge alignment on start or end of PWM cycle for each compare
channels. Table 28-2 shows the waveform output set/clear conditions, depending on timer/counter settings, direction and
polarity setting.
In Normal and Match Frequency, the WAVE.POLx value represents the initial state of the waveform output.
28.6.2.6 Double Buffering
The Pattern (PATT), Waveform (WAVE), Period (PER) and the Compare Channels (CCx) registers are all double
buffered. Each buffer register has a Buffer Valid (PATTBV, WAVEBV, PERBV or CCBVx) bit in the STATUS register,
which indicates that the buffer register contains a value that can be copied into the corresponding register. When double
buffering is enabled by writing a one to the Lock Update bit in the Control B Clear register (CTRLBCLR.LUPD) and the
PER and CCx are used for a compare operation, the Buffer Valid bit is set when data has been written to a buffer register
and cleared on an update condition.
This is shown for a compare register in Figure 28-11.
NPWM Single-slope PWM PER TOP/ZERO
See Table 28-2
TOP ZERO
DSCRITICAL Dual-slope PWM PER ZERO -ZERO
DSBOTTOM Dual-slope PWM PER ZERO -ZERO
DSBOTH Dual-slope PWM PER TOP & ZERO TOP ZERO
DSTOP Dual-slope PWM PER ZERO TOP –
Table 28-1. Counter Update and Overflow Event/Interrupt Conditions (Continued)
Description Description
Name Operation Top Update
Output
Waveform
On Match
Output
Waveform
On Update
OVFIF/Event
Up Down
Table 28-2. Waveform Generation Set/Clear Conditions
Waveform
Generation
operation DIR POLx Waveform Generation Output Update
Set Clear
Single-Slope PWM
0
0Timer/counter matches TOP Timer/counter matches CCx
1Timer/counter matches CC Timer/counter matches TOP
1
0Timer/counter matches CC Timer/counter matches ZERO
1Timer/counter matches ZERO Timer/counter matches CC
Dual-Slope PWM x
0Timer/counter matches CC when
counting up
Timer/counter matches CC when
counting down
1Timer/counter matches CC when
counting down
Timer/counter matches CC when
counting up
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Figure 28-11.Compare Channel Double Buffering
As both the register (PATT/WAVE/PER/CCx) and corresponding buffer register (PATTB/WAVEB/PERB/CCBx) are
available in the I/O register map, the double buffering feature is not mandatory. The double buffering is disabled by
writing a one to CTRLSET.LUPD. This allows initialization and bypassing of the buffer register and the double buffering
feature.
Note: In normal frequency (NFRQ), match frequency (MFRQ) or PWM down-counting counter mode (CTRLBSET.DIR
is one), PER is written at the same time as PERB is written if CTRLB.LUPD is zero or as soon as CTRLB.LUPD
becomes zero.
Changing the Period
The counter period is changed by writing a new value to the Period register or the Period Buffer register. If double
buffering is not used, any update of PER is effective after the synchronization delay.
Figure 28-12.Unbuffered Single-Slope Up-Counting Operation
BV
UPDATE
"APB write enable" "data write"
=
COUNT
"match"
EN
EN CCBx
CCx
COUNT
MAX
New value written to
PER that is higher
than current COUNT
Counter Wraparound
New value written to
PER that is lower
than current COUNT
"clear" update
"write"
ZERO
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Figure 28-13.Unbuffered Single-Slope Down-Counting Operation
A counter wraparound can occur in any mode of operation when up-counting without buffering, as shown in Figure 28-12.
This due to the fact that COUNT and TOP are continuously compared, and if a new value that is lower than the current
COUNT is written to TOP, COUNT will wrap before a compare match happen.
Figure 28-14.Unbuffered Dual-Slope Operation
When double buffering is used, the buffer can be written at any time and the counter will still maintain correct operation.
The period register is always updated on the update condition, as shown for dual-slope operation in Figure 28-15. This
prevents wraparound and the generation of odd waveforms.
COUNT
MAX
New value written to
PER that is higher
than current COUNT
New value written to
PER that is lower
than current COUNT
"reload" update
"write"
ZERO
COUNT
New value written to
PER that is higher
than current COUNT
New value written to
PER that is lower
than current COUNT
"update"
"write"
Counter Wraparound
MAX
ZERO
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Figure 28-15.Changing the Period Using Buffering
28.6.2.7 Capture Operations
To enable and use capture operations, the Match or Capture Channel x Event Input Enable (MCEIx) bit must be enabled
in the Event Control register (EVCTRL.MCEIx). The capture channels to be used must also be enabled in the Capture
Channel x Enable bit in the Control A register (CTRLA.CPTENx) before capture can be performed.
Event Capture Action
The capture channels can be used to capture the COUNT value upon reception of any event. Since there is one event
line per capture channel, multiple capture operations can be enabled at the same time.
Figure 28-16 shows four capture events for one capture channel.
Figure 28-16.Input Capture Timing
For input capture, the buffer register and the corresponding CCx act like a FIFO. When CCx is empty or read, any
content in CCBx is transfered to CCx. The buffer valid flag is passed to set the CCx interrupt flag (IF) and generate the
optional interrupt, event or DMA request.
COUNT
New value written to
PERB that is higher than
current COUNT
New value written to
PERB that is lower
than current COUNT
"reload" update
"write"
PER is updated with
PERB value.
MAX
ZERO
events
COUNT
MAX
ZERO
Capture 0 Capture 1 Capture 2 Capture 3
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Figure 28-17.Capture Double Buffering
When the Capture x (MCx) bit and the buffer valid flag are set and a new capture event is detected, there is nowhere to
store the new timestamp. In that case the Error bit in the Interrupt Flag Status and Clear register (INTFLAG.ERR) is set.
Period and Pulse-Width Capture Action
The TCC can perform two input captures and restart the counter on one of the edges. This enables the TCC to measure
the pulse-width and period. This can be used to characterize an input signal in frequency and duty cycle:
When using PPW (Period, Pulse-width) event action, period (TOP) will be captured into CC0 and pulse-width (tp) into
CC1. In PWP (Pulse-width, Period) event action, pulse-width (tp) will be captured into CC0 and period (TOP) into CC1.
Figure 28-18.PWP Capture
Selecting PWP or PPW in the Event Action bit group in the Event Control register (EVCTRL.EVACT1) enables the TCC
to perform two capture actions, one on the rising edge and one on the falling edge.
The Timer/Counter Inverted Event 1 Input Enable bit in Event Control register (EVCTRL.TCEINV1) is used to select
which event input edge the counter restarts operation. The event source to be captured must be an asynchronous event.
BV
"capture"
IF
COUNT
CCBx
CCx
EN
EN
"INT/DMA
request" data read
f1
T
---
=
dutyCycle tp
T
-----
=
Period (T)
external
signal /event
capture times
COUNT
MAX
ZERO
"capture"
Pulsewitdh (tp)
CC0 CC0 CC1CC1
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For a period and width of the pulse of input signal in frequency and duty cycle, enable capture on CC0 and CC1 channels
by writing a one to the Capture Channel x Enable bit in the Control A register (CTRLA.CPTENx). When only one of these
measurements is required, the second channel can be used for other purposes.
The TCC can detect capture overflow of the input capture channels. Capture overflow occurs when the Capture Interrupt
Flag is set and a new capture event is detected, there is nowhere to store the new timestamp. In that case
INTFLAG.ERR is set.
Note: In dual-slope PWM operation, when TOP is lower than MAX/2 the CCx MSB captures the CTRLB.DIR state to
identify the ramp (rising if CCx[MSB] is zero, or falling if CCx[MSB] is one) on which the Counter capture has
been done.
28.6.3 Additional Features
28.6.3.1 One-Shot Operation
When one-shot is enabled, the counter automatically stops on the next counter overflow or underflow condition. When
the counter is stopped, STATUS.STOP is set and the waveform outputs are set to the value defined by the Non-
Recoverable State x Output Enable (NREx) and Non-Recoverable State x Output Value (NRVx) bits in the Drive Control
register (DRVCTRL.NREx and DRVCTRL.NRVx).
One-shot operation can be enabled by writing a one to the One-Shot bit in the Control B Set register
(CTRLBSET.ONESHOT) and disabled by writing a one to the One-Shot bit in the Control B Clear register
(CTRLBCLR.ONESHOT). When enabled, the TCC will count until an overflow or underflow occurs and stop counting.
The one-shot operation can be restarted by using retrigger software command, a retrigger event or a start event.
When the counter restarts its operation, the Stop bit in the Status register (STATUS.STOP) is cleared.
28.6.3.2 Circular Buffer
The Period register (PER) and the compare channels register (CC0 to CC3) support circular buffer operation. When
circular buffer operation is enabled, at each update condition, the (PER) or CCx values are copied into the corresponding
buffer registers. Circular buffer are dedicated to RAMP2, RAMP2A, and DSBOTH operations.
Figure 28-19.Circular Buffer on Channel 0
28.6.3.3 Dithering Operation
The TCC supports dithering on Pulse-width or Period on a 16, 32 or 64 PWM cycles frame.
BV
UPDATE
"write enable" "data write"
=
COUNT
"match"
EN
EN CCB0
CC0
UPDATE
CIRCC0EN
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Dithering consists in adding some extra clocks cycles in a frame of several PWM cycles, improving the accuracy of the
average output pulses width or period. The extra clock cycles are added on some of the compare match signals, one at a
time, through a "blue noise" process that minimizes the flickering on the resulting dither patterns.
Dithering makes possible to improve the accuracy of the average output pulse width or period.
Dithering is enabled by writing the corresponding configuration in the Enhanced Resolution bits in CTRLA register
(CTRLA.RESOLUTION):
zDITH4 enable dithering every 16 PWM frames
zDITH5 enable dithering every 32 PWM frames
zDITH6 enable dithering every 64 PWM frames
The DITHERCY bits of COUNT, PER and CCx define the number of extra cycles to add into the frame (DITHERCY bits
from the respective COUNT, PER or CCx registers). The remaining bits of COUNT, PER, CCx define the compare value
itself.
The pseudo code, giving the extra cycles insertion regarding the cycle is:
int extra_cycle(resolution, dithercy, cycle){
int MASK;
int value
switch (resolution){
DITH4: MASK = 0x0f;
DITH5: MASK = 0x1f;
DITH6: MASK = 0x3f;
}
value = cycle * dithercy;
if (((MASK & value) + dithercy) > MASK)
return 1;
return 0;
}
1.7.3.3.1: Dithering on Period
Writing DITHERCY in PER will lead to an average PWM period configured by the following formula:
If DITH4 mode is enabled, the last 4 significant bits from PER/CCx or COUNT register corresponds to the DITHERCY
value, Rest of the bits corresponds to PER/CCx or COUNT value.
The PWM resolution can be calculated using the following formulas.
DITH4 mode:
DITH5 mode:
DITH6 mode:
1.7.3.3.2: Dithering on Pulse Width
Writing DITHERCY in CCx will lead to an average PWM pulse width configured by the following formula:
DITH4 mode:
PwmPeriod DITHERCY
16
-------------------------------PER+=
PwmPeriod DITHERCY
32
-------------------------------PER+=
PwmPeriod DITHERCY
64
-------------------------------PER+=
PwmPulseWidth DITHERCY
16
-------------------------------CCx+=
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DITH5 mode:
DITH6 mode:
28.6.3.4 Ramp Operations
Three ramp operations are supported and all require the timer/counter running in single-slope PWM generation.
RAMP1 Operation
This is the default PWM operation, described in “Single-Slope PWM Generation” on page 618.
RAMP2 Operation
These operations are dedicated for PFC, Half-Brige and Push-Pull SMPS topologies, where two consecutive
timer/counter cycles are interleaved, as shown in Figure 28-20. In cycle A, odd channels output are disabled, and in cycle
B, even channels output are disabled. The ramp index changes after each update, but can be software modified using
the the Ramp index command bits in Control B Set register (CTRLBSET.IDXCMD).
Standard RAMP2 (RAMP2) Operation
Ramp A and B periods are controlled through PER register value. Period register value can have different values on
each ramp by enabling the circular buffer option (CIPEREN). This mode allows use of a two channels TCC to generate
two output signals, or one output signal with another CC channel enabled in capture mode.
Figure 28-20.RAMP2 Standard Operation
Alternate RAMP2 (RAMP2A) Operation
Alternate RAMP2 operation is similar to RAMP2 with the difference that CC0 controls both WO[0]/WO[1] waveforms
when the corresponding circular buffer option is enabled. The waveform polarity is the same on both outputs, and the
channel 1 can be used in capture mode.
PwmPulseWidth DITHERCY
32
-------------------------------CCx+=
PwmPulseWidth DITHERCY
64
-------------------------------CCx+=
COUNT
"match"
ZERO
"clear" update
A B A BRamp
WO[0]
WO[1]
TOP(A)
TOP(B)
CC0
CC1
TOP(B)
CC0
CC1
Retrigger
on
FaultA
Keep on FaultB
CIPEREN = 1
POL0 = 1
POL1 = 1
FaultA input
FaultB input
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Figure 28-21.RAMP2 Alternate Operation
28.6.3.5 Recoverable Faults
Recoverable faults can restart or halt the timer/counter. Two faults, called Fault A and Fault B, can trigger recoverable
fault actions on compare channels CC0 and CC1 from the timer/counter. The compare channels outputs can be clamped
to inactive state as long as the fault condition is present, or from the first valid fault condition detection and until the end
of the timer/counter cycle.
Fault Inputs
The first two channel input events (MC0 and TCCxMC1) can be used as Fault A and Fault B inputs respectively. Event
system channel connected to these fault inputs must be configured as asynchronous. In two ramp (RAMP2, RAMP2A)
operation.
Fault Filtering
Three filtering types are available. The recoverable faults can use all three filters independently or various filter
combinations.
zInput filtering: By default, the event detection is asynchronous. When the event occurs, the fault system will
immediately and asynchronously performs the selected fault action on the compare channel output,
including system power modes where the clock is not available. To avoid false fault detection on external
events (e.g. a glitch on I/O port) a digital filter can be enabled and set in FILTERVAL bits in the
corresponding recoverable Fault Control n register (FCTRLn.FILTERVAL). In this case, the event will be
delayed by the FILTERVAL value clock cycles. If the event width is less than the FILTERVAL, then the event
will be discarded.
zFault blanking: Provides a way to disable fault input just after a selected waveform output edge to prevent
false fault triggering because of signal bouncing on fault signal, as shown in Figure 28-22. Blanking can be
enabled by writing the edge triggering configuration to the Faultn Blanking Mode bits in the Recoverable
FaultnConfiguration register (FCTRLn.BLANK), and the number of clock cycles to blank is written to the
Faultn Blanking Time bits in the Recoverable Faultn Configuration register (FCTRLn.BLANKVAL). The
maximum blanking time is:
256 / (96 ×106) = 2.66us for 96MHz peripheral clock frequency (GCLK_TCCx)
256 / (1x106) = 256us for 1MHz peripheral clock frequency (GCLK_TCCx)
COUNT
"match"
ZERO
"clear" update
A B A BRamp
WO[0]
WO[1]
TOP(A)
TOP(B)
CC0(A)
CC0(B)
TOP(B)
CC0(A)
CC0(B)
Retrigger
on
FaultA
CIPEREN = 1
POL0 = 1
CICCEN0 = 1
FaultA input
Keep on FaultB
FaultB input
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Figure 28-22.Fault Blanking in RAMP1 Operation with Inverted Polarity
zFault Qualification can be enabled using Faultn Qualification bit in Recoverable Faultn Configuration
register (FCTRLn.QUAL). When the recoverable fault qualification is enabled (FCTRLn.QUAL), the fault
input is disabled all the time the corresponding channel output has an inactive level, as shown in Figure 28-
23.
Figure 28-23.Fault Qualification in RAMP1 Operation
COUNT
"match"
ZERO
"clear" update
FaultA Input
CC0
TOP
WO[0]
CMP0
FCTRLA.BLANKVAL = 0 FCTRLA.BLANKVAL > 0 FCTRLA.BLANKVAL > 0
9 9 9- -FaultA Blanking
x x x x
9"Fault input enabled"
-"Fault input disabled"
x
"Fault discarded"
COUNT
MAX
TOP
ZERO
Fault Input A
CC0
9-9 9 9 9- - --
9-9 9 99---Fault B Input Qual - -
Fault Input B
xxx xxxxxx
xxxxx xxxxxxx xxxx
xxx
CC1
Fault A Input Qual
"match"
"clear" update
9"Fault input enabled"
-"Fault input disabled"
x
"Fault discarded"
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Figure 28-24.Fault Qualification in RAMP2 Operation with Inverted Polarity
Fault Actions
Different fault actions can be configured individually for Fault A and Fault B. Most fault actions are not mutually exclusive;
hence two or more actions can be enabled at the same time to achieve a result that is a combination of fault actions.
zKeep action can be enabled using Faultn Keeper bit in Recoverable Faultn Configuration register
(FCTRLn.KEEP). When the keep action (FCTRLn.KEEP) is enabled, the corresponding channel output will
be clamped to zero when the fault condition is present. The clamp will be released on the start of the first
cycle after the fault condition is no longer present, as shown in Figure 28-25.
Figure 28-25.Waveform Generation with Fault Qualification and Keep Action
zRestart action can be enabled using Faultn Restart bit in Recoverable Faultn Configuration register
(FCTRLn.RESTART). When the restart action (FCTRLn.RESTART) is enabled, the timer/counter will be
restarted when the corresponding fault condition is present. The ongoing cycle is stopped and the
timer/counter starts a new cycle, as shown in Figure 28-26. When the new cycle starts, the compare outputs
will be clamped to inactive level as long as the fault condition is present. Note that in RAMP2 operation,
when a new timer/counter cycle starts, the cycle index will change automatically, as shown in Figure 28-27.
Fault A and Fault B are qualified only during the cycle A and cycle B respectively, i.e. the faultA and faultB is
disabled during cycle B or cycle A respectively.
COUNT
MAX
TOP
ZERO
Fault Input A
CC0
-9 9 9- -Fault A Input Qual
-9 9
-
Fault B Input Qual -
Fault Input B
AB A BCycle
CC1
xxx xxxxxxxxx
xxxxxxxxxxxxxxx
"match"
"clear" update
9"Fault input enabled"
-"Fault input disabled"
x
"Fault discarded"
KEEP
KEEP
COUNT
MAX
TOP
ZERO
Fault Input A
CC0
9-9 9 9 9---Fault A Input Qual
xxx x
-
WO[0]
"match"
"clear" update
9"Fault input enabled"
-"Fault input disabled"
x
"Fault discarded"
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Figure 28-26.Waveform Generation in RAMP1 Mode with Restart Action
Figure 28-27.Waveform Generation in RAMP2 Mode with Restart Action
zCapture action: Several capture actions can be selected using Faultn Capture Action bits in Faultn Control
register (FCTRLn.CAPTURE). When one of the capture operations (FCTRLn.CAPTURE) is selected, the
counter value is captured when the fault occurs. Several capture operations are available:
zCAPT is equivalent to a standard capture operation, for further details refer to “Capture Operations”
on page 624
zCAPTMIN allows to get the minimum time stamped value, with notification through event or interrupt
on each new local minimum captured value detection.
zCAPTMAX allows to get the maximum time stamped value, with notification through event or IT on
each new local maximum captured value, as shown in Figure 28-28.
zLOCMIN notifies through event or IT a local minimum captured value is detected.
zLOCMAX notifies through event or IT a local maximum captured value is detected.
zDERIV0 notifies through event or IT when a local extremum captured value is detected, as shown in
Figure 28-29.
In CAPT mode, on each filtered faultn, dedicated CCx channel capture counter value and an interrupt is generated. In
other mode interrupt is only generated on a extremum captured value.
COUNT
MAX
TOP "match"
ZERO
"clear" update
Fault Input A
CC0
CC1
Restart
Restart
WO[0]
WO[1]
COUNT
MAX
TOP
Period (T) "match"
ZERO
CCx=ZERO
CC0/CC1
CCx=TOP
"clear" update
A B B
Fault Input A
Cycle A
Restart
No fault A action
in cycle B
WO[1]
WO[0]
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In CAPT operation, capture is performed on each capture event. MCx interrupt flag is set on each new capture. In
CAPTMIN and CAPTMAX operation, capture is performed only when a new lower (for CAPTMIN) and new higher (for
CAPTMAX) value is detected. MCx interrupt flag is set on each new capture.
In LOCMIN and LOCMAX operation, capture is performed on each capture event. MCx interrupt flag is set only when the
captured value is lower (for LOCMIN) and higher (for LOCMAX) values respectively than the previous captured value.
DERIV0 is equivalent to a OR function of (LOCMIN, LOCMAX).
In CAPTMIN and CAPTMAX operation CCx keeps the extremum values respectively, as show in Figure 28-28, while in
LOCMIN, LOCMAX or DERIV0 operations, CCx follow the counter value at fault time, as show in Figure 28-29.
Figure 28-28.Capture Action “CAPTMAX”
Figure 28-29.Capture Action “DERIV0”
zHardware halt action can be configured using Faultn Halt mode bits in Recoverable Faultn configuration
register (FCTRLn.HALT = HW). When hardware halt action is enabled (FCTRLn.HALT = HW), the
timer/counter is halted and the cycle is extended as long as the corresponding fault is present. Figure 28-30
shows an example where restart and hardware halt actions are enabled for Fault A. The compare channel 0
output is clamped to inactive level as long as the timer/counter is halted. The timer/counter resumes the
counting operation as soon as the fault condition is no longer present. If the restart action is enabled, the
timer/counter is halted as long as the fault condition is present and restarted when the fault condition is no
longer present, as shown in Figure 28-31. Note that in RAMP2 and RAMP2A operations, when a new
timer/counter cycle starts, the cycle index will automatically change.
COUNT "match"
ZERO
"clear" update
FaultA Input
TOP
CC0
CC0 Event/
Interrupt
COUNT "match"
ZERO
"update"
FaultA Input
TOP
CC0
CC0 Event/
Interrupt
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Figure 28-30.Waveform Generation with Halt and Restart Actions
Figure 28-31.Waveform Generation with Fault Qualification, Halt and Restart Actions
zThe software halt action can be configured using Faultn Halt mode bits in Recoverable Faultn configuration
register (FCTRLn.HALT = SWHALT). Software halt action is similar to hardware halt action with one
exception. To restart the timer/counter, the corresponding fault condition should no longer be present and
the corresponding FAULTn bit in STATUS register must be cleared.
HALT
COUNT
MAX
TOP "match"
ZERO
"clear" update
Fault Input A
CC0
RestartRestart
WO[0]
KEEP
HALT
COUNT
MAX
TOP "match"
ZERO
"update"
Fault Input A
CC0
9-99 9- -Fault A Input Qual -
Resume
xxx
-
WO[0]
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Figure 28-32.Waveform Generation with Software Halt, Fault Qualification, Keep and Restart Actions
28.6.3.6 Non Recoverable Faults
The non-recoverable fault action will force all the compare outputs to a pre-defined level programmed into the Driver
Control register (DRVCTRL.NRE and DRVCTRL.NRV). The non recoverable fault input (EV0 and EV1) actions are
enabled in Event Control register (EVCTRL.EVACT0 and EVCTRL.EVACT1). To avoid false fault detection on external
events (e.g. a glitch on an I/O port) a digital filter can be enabled using Non-Recoverable Fault Input x Filter Value bits in
the Driver Control register (DRVCTRL.FILTERVALn). In this case, the event detection is synchronous, and event action
is delayed by the selected digital filter value clock cycles.
KEEP
HALT
COUNT
MAX
TOP "match"
ZERO
"update"
Fault Input A
CC0
9-99-Fault A Input Qual -
Software Clear
9
NO
KEEP
9
Restart Restart
xx
-
WO[0]
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28.6.3.7 Waveform Extension
Figure 28-33 shows a schematic diagram of action of the four optional units following the recoverable fault stage, on a
port pin pair. The DTI and SWAP units can be seen as a four port pair slices:
zSlice 0 DTI0 / SWAP0 acting on port pins (WO[0], WO[WO_NUM/2 +0])
zSlice 1 DTI1 / SWAP1 acting on port pins (WO[1], WO[WO_NUM/2 +1])
And more generally:
zSlice n DTIx / SWAPx acting on port pins (WO[x], WO[WO_NUM/2 +x])
Figure 28-33.Waveform Extension Stage Details
The output matrix (OTMX) unit distributes compare channels, according to the selectable configurations, as shown in
Table 28-3.
zConfiguration 0x0 is default configuration. The channel location is the default one and channels are distributed on
outputs modulo the number of channels. Channel 0 is routed to the Output matrix output OTMX[0], Channel 1 to
OTMX[1]. If there are more outputs than channels, then channel 0 is duplicated to the Output matrix output
OTMX[CC_NUM], channel 1 to OTMX[CC_NUM+1] and so on.
zConfiguration 0x1 distributes the channels on output modulo half the number of channels, this gives the lower
channels twice the number of output locations than the default configuration. This provides for example, control of
the four transistors of a full bridge using only two compare channels. Using pattern generation, some of these four
outputs can be overwritten by a constant level, enabling flexible drive of a full bridge in all quadrant configurations.
zConfiguration 0x2 distributes the compare channel 0 (CC0) to all port pins. With pattern generation, this
configuration can control a stepper motor.
zConfiguration 0x3 distributes the compare channel CC0 to first output and the channel CC1 to all other outputs.
Together with pattern generation and the fault extension this configuration can control up to seven LED strings,
with a boost stage.
Table 28-3. Output Matrix Channel Pin Routing Configuration
Value OTMX[x]
0x0 CC3 CC2 CC1 CC0 CC3 CC2 CC1 CC0
0x1 CC1 CC0 CC1 CC0 CC1 CC0 CC1 CC0
0x2 CC0 CC0 CC0 CC0 CC0 CC0 CC0 CC0
0x3 CC1 CC1 CC1 CC1 CC1 CC1 CC1 CC0
OTMX[x]
DTIx
LS
HS
OTMX[x+WO_NUM/2]
DTIxEN SWAPx
PGO[x+WO_NUM/2]
PGO[x]
PGV[x+WO_NUM/2]
PGV[x]
INV[x+WO_NUM/2]
P[x+WO_NUM/2]
INV[x]
P[x]
PORTSWEX
OTMX
OTMX DTI SWAP PATTERN
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An example of 4 compare channels on 4 outputs:.
The dead-time insertion (DTI) unit generates OFF time with the non-inverted low side (LS) and inverted high side (HS) of
the WG output forced at low level. This OFF time is called dead time, and dead-time insertion ensures that the LS and
HS will never switch simultaneously.
The DTI stage consists of four equal dead-time insertion generators; one for each of the first four compare channels.
Figure 28-34
shows the block diagram of one DTI generator. The four channels have a common register which controls
the dead time and is independent of high side and low side setting.
Figure 28-34.Dead-Time Generator Block Diagram
As shown in Figure 28-34, the 8-bit dead-time counter is decremented by one for each peripheral clock cycle, until it
reaches zero. A nonzero counter value will force both the low side and high side outputs into their OFF state. When the
output matrix (OTMX) output changes, the dead-time counter is reloaded according to the edge of the input. When the
output changes from low to high (positive edge) it initiates counter reload of the DTLS register, and when the output
changes from high to low (negative edge) reload the DTHS register.
Value OTMX[3] OTMX[2] OTMX[1] OTMX[0]
0x0 CC3 CC2 CC1 CC0
0x1 CC1 CC0 CC1 CC0
0x2 CC0 CC0 CC0 CC0
0x3 CC1 CC1 CC1 CC0
Dead Time Generator
Edge Detect
DQ
= 0
"DTLS"
(To PORT)
"DTHS"
(To PORT)
Counter
EN
LOAD
OTMX output
DTLS DTHS
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Figure 28-35.Dead-Time Generator Timing Diagram
The pattern generator unit produces a synchronized bit pattern across the port pins it is connected to. The pattern
generation features are primarily intended for handling the commutation sequence in brushless DC motor (BLDC),
stepper motor and full bridge control. A block diagram of the pattern generator is shown in Figure 28-36.
Figure 28-36.Pattern Generator Block Diagram
As with other double buffered timer/counter registers, the register update is synchronized to the UPDATE condition set
by the timer/counter waveform generation operation. If the synchronization is not required by the application, the
software can simply access directly the PATT.PGE, PATT.PGV bits registers.
"dti_cnt"
"OTMX output"
"DTLS"
"DTHS"
t
DTILS
t
DTIHS
T
t
P
COUNT
UPDATE
BV BVPGEB[7:0]
PGE[7:0]
PGVB[7:0]
PGV[7:0]
SWAP output
ENEN
WOx[7:0]
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28.6.4 DMA, Interrupts and Events
Notes: 1. DMA request set on overflow, underflow or retrigger conditions.
2. Can perform capture or generate recoverable fault on an event input.
3. Can retrigger counter / control counter direction / stop the counter / decrement the counter / perform period
and pulse width capture / generate non-recoverable fault on an event input.
4. Can retrigger counter / increment or decrement counter depending on direction / start the counter / incre-
ment or decrement counter based on direction / increment counter regardless of direction / generate non-
recoverable fault on an event input.
28.6.4.1 DMA Operation
The TCC generates the following DMA requests:
zOverflow (OVF): the request is set when an update condition (overflow, underflow or re-trigger) is detected.
zCompare Match or Capture (MCx): for a compare channel, the request is set on each compare match detection.
For a capture channel, the request is set when valid data is present in CCx register, and cleared when CCx
register is read.
28.6.4.2 Interrupts
The TCC has the following interrupt sources:
zOverflow/Underflow: OVF. This is an asynchronous interrupt and can be used to wake-up the device from any
sleep mode.
zRetrigger: TRG. This is an asynchronous interrupt and can be used to wake-up the device from any sleep mode.
Table 28-4. Module request for TCC
Condition
Interrupt
request
Event
output Event input DMA request DMA request is cleared
Overflow / Underflow X X X(1)
Cleared when PER/PERB,
CCx/CCBx, PATT/PATTB
or WAVE/WAVEB register is
written.
Channel Compare Match
or Capture X X X(2) X
For compare channel:
Cleared when CCBx register
is written.
For capture channel:
Cleared when CCx register
is read.
Retrigger X X
Count X X
Capture Overflow Error X
Synchronization Ready X
Debug Fault State X
Recoverable Faults X
Non-Recoverable Faults X
TCCx Event 0 input X(3)
TCCx Event 1 input X(4)
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zCount: CNT. This is an asynchronous interrupt and can be used to wake-up the device from any sleep mode. For
further details, refer to EVCTRL.CNTSEL description.
zCapture Overflow Error: ERR. This is an asynchronous interrupt and can be used to wake-up the device from any
sleep mode.
zDebug Fault State: DFS. This is an asynchronous interrupt and can be used to wake-up the device from any sleep
mode.
zRecoverable Faults: FAULTn. This is an asynchronous interrupt and can be used to wake-up the device from any
sleep mode.
zNon-recoverable Faults: FAULTx. This is an asynchronous interrupt and can be used to wake-up the device from
any sleep mode.
zCompare Match or Capture Channel: MCx. This is an asynchronous interrupt and can be used to wake-up the
device from any sleep mode.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
(INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one
to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a one to the
corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the interrupt
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is
cleared, the interrupt is disabled, or the TCC is reset. See the
INTFLAG
for details on how to clear interrupt flags. The
TCC has one common interrupt request line for all the interrupt sources. Refer to “Processor And Architecture” on page
28 for details. The user must read the INTFLAG register to determine which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to “Processor And
Architecture” on page 28 for details.
28.6.4.3 Events
The TCC can generate the following output events:
zOverflow/Underflow: OVF
zTrigger: TRG
zCounter: CNT. For further details, refer to EVCTRL.CNTSEL description.
zCompare Match or Capture on compare/capture channels: MCx
Writing a one to an Event Output bit in the Event Control Register (EVCTRL.xxEO) enables the corresponding output
event. Writing a zero to this bit disables the corresponding output event. Refer to “EVSYS – Event System” on page 400
for details on configuring the event system.
The TCC can take the following actions on a channel input event (MCx):
zCapture event
zGenerate a recoverable fault
The TCC can take the following actions on counter event 1 (TCCx EV1):
zCounter retrigger
zCounter direction control
zStop the counter
zDecrement the counter on event
zPeriod and pulse width capture
zNon-recoverable fault
The TCC can take the following actions on counter event 0 (TCCx EV0):
zCounter retrigger
zCount on event (increment or decrement, depending on counter direction)
zCounter start. Start counting on the event rising edge. Further events will not restart the counter; it keeps on
counting using prescaled GCLK_TCCx, until it reaches TOP or Zero depending on the direction.
zCounter increment on event. This will increment the counter irrespective of the counter direction.
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zCount during active state of an asynchronous event (increment or decrement, depending on counter
direction). In this case, the counter will be incremented or decremented on each cycle of the prescaled
clock, as long as the event is active.
zNon-recoverable fault
The counter Event Actions are available in Event Control register (EVCTRL.EVACT0 and EVCTRL.EVACT1). For further
details, refer to EVCTRL register description.
Writing a one to an Event Input bit in the Event Control register (EVCTRL.MCEIx or EVCTRL.TCEIx) enables the
corresponding action on input event. Writing a zero to this bit disables the corresponding action on input event. Note that
if several events are connected to the TCC, the enabled action will apply for each the incoming event. Refer to “EVSYS –
Event System” on page 400 for details on how to configure the event system.
28.6.5 Sleep Mode Operation
The TCC can be configured to operate in any sleep mode. To be able to run in standby the RUNSTDBY bit
(CTRLA.RUNSTDBY) must be written to one. The TCC can wake up the device using interrupts from any sleep mode or
performs internal actions through the event system.
28.6.6 Synchronization
Due to the asynchronicity between CLK_TCCx_APB and GCLK_TCCx some registers must be synchronized when
accessed. A register can require:
zSynchronization when written
zSynchronization when read
zSynchronization when written and read
zNo synchronization
When a register requiring synchronization is accessed, the corresponding synchronization bit is set in Synchronization
Busy register (SYNCBUSY) and cleared when the synchronization is complete.
An access to a register with synchronization busy bit set, will trigger an hardware interrupt.
The following bits need synchronization when written:
zSoftware Reset and Enable bits in Control A register (CTRLA.SWRST and CTRLA.ENABLE)
Write-synchronization is denoted by the Write-Synchronized property in the register description.
The following registers require synchronization when written:
zControl B Clear and Control B Set registers (CTRLBCLR and CTRLBSET)
zStatus register (STATUS)
zPattern and Pattern Buffer registers (PATT and PATTB)
zWaveform and Waveform Buffer registers (WAVE and WAVEB)
zCount Value register (COUNT)
zPeriod Value and Period Buffer Value registers (PER and PERB)
zCompare/Capture Value and Compare/Capture Buffer Value registers (CCx and CCBx)
Write-synchronization is denoted by the Write-Synchronized property in the register description.
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28.7 Register Summary
Table 28-5. Register Summary
Offset Name
Bit
Pos.
0x00
CTRLA
7:0 RESOLUTION[1:0] ENABLE SWRST
0x01 15:8 ALOCK PRESCSYNC[1:0] RUNSTDBY PRESCALER[2:0]
0x02 23:16
0x03 31:24 CPTEN3 CPTEN2 CPTEN1 CPTEN0
0x04 CTRLBCLR 7:0 CMD[2:0] IDXCMD[1:0] ONESHOT LUPD DIR
0x05 CTRLBSET 7:0 CMD[2:0] IDXCMD[1:0] ONESHOT LUPD DIR
0x06 Reserved
0x07 Reserved
0x08
SYNCBUSY
7:0 PER WAVE PATT COUNT STATUS CTRLB ENABLE SWRST
0x09 15:8 CC3 CC2 CC1 CC0
0x0A 23:16 CCB3 CCB2 CCB1 CCB0 PERB WAVEB PATTB
0x0B 31:24
0x0C
FCTRLA
7:0 RESTART BLANK[1:0] QUAL KEEP SRC[1:0]
0x0D 15:8 CAPTURE[2:0] CHSEL[1:0] HALT[1:0]
0x0E 23:16 BLANKVAL[7:0]
0x0F 31:24 FILTERVAL[3:0]
0x10
FCTRLB
7:0 RESTART BLANK[1:0] QUAL KEEP SRC[1:0]
0x11 15:8 CAPTURE[2:0] CHSEL[1:0] HALT[1:0]
0x12 23:16 BLANKVAL[7:0]
0x13 31:24 FILTERVAL[3:0]
0x14
WEXCTRL
7:0 OTMX[1:0]
0x15 15:8 DTIEN3 DTIEN2 DTIEN1 DTIEN0
0x16 23:16 DTLS[7:0]
0x17 31:24 DTHS[7:0]
0x18
DRVCTRL
7:0 NRE7 NRE6 NRE5 NRE4 NRE3 NRE2 NRE1 NRE0
0x19 15:8 NRV7 NRV6 NRV5 NRV4 NRV3 NRV2 NRV1 NRV0
0x1A 23:16 INVEN7 INVEN6 INVEN5 INVEN4 INVEN3 INVEN2 INVEN1 INVEN0
0x1B 31:24 FILTERVAL1[3:0] FILTERVAL0[3:0]
0x1C Reserved
0x1D Reserved
0x1E DBGCTRL 7:0 FDDBD DBGRUN
0x1F Reserved
0x20
EVCTRL
7:0 CNTSEL[1:0] EVACT1[2:0] EVACT0[2:0]
0x21 15:8 TCEI1 TCEI0 TCINV1 TCINV0 CNTEO TRGEO OVFEO
0x22 23:16 MCEI3 MCEI2 MCEI1 MCEI0
0x23 31:24 MCEO3 MCEO2 MCEO1 MCEO0
0x24
INTENCLR
7:0 ERR CNT TRG OVF
0x25 15:8 FAULT1 FAULT0 FAULTB FAULTA DFS
0x26 23:16 MC3 MC2 MC1 MC0
0x27 31:24
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0x28
INTENSET
7:0 ERR CNT TRG OVF
0x29 15:8 FAULT1 FAULT0 FAULTB FAULTA DFS
0x2A 23:16 MC3 MC2 MC1 MC0
0x2B 31:24
0x2C
INTFLAG
7:0 ERR CNT TRG OVF
0x2D 15:8 FAULT1 FAULT0 FAULTB FAULTA DFS
0x2E 23:16 MC3 MC2 MC1 MC0
0x2F 31:24
0x30
STATUS
7:0 PERBV WAVEBV PATTBV SLAVE DFS IDX STOP
0x31 15:8 FAULT1 FAULT0 FAULTB FAULTA FAULT1IN FAULT0IN FAULTBIN FAULTAIN
0x32 23:16 CCBV3 CCBV2 CCBV1 CCBV0
0x33 31:24 CMP3 CMP2 CMP1 CMP0
0x34
COUNT
7:0 COUNT[7:0]
0x35 15:8 COUNT[15:8]
0x36 23:16 COUNT[23:16]
0x37 31:24
0x38
PATT
7:0PGE7PGE6PGE5PGE4PGE3PGE2PGE1PGE0
0x39 15:8 PGV7 PGV6 PGV5 PGV4 PGV3 PGV2 PGV1 PGV0
0x3A Reserved
0x3B Reserved
0x3C
WAVE
7:0 CIPEREN RAMP[1:0] WAVEGEN[2:0]
0x3D 15:8 CICCEN3 CICCEN2 CICCEN1 CICCEN0
0x3E 23:16 POL3 POL2 POL1 POL0
0x3F 31:24 SWAP3 SWAP2 SWAP1 SWAP0
0x40
PER
7:0 PER[7:0]
0x41 15:8 PER[15:8]
0x42 23:16 PER[23:16]
0x43 31:24
0x44
CC0
7:0 CC[7:0]
0x45 15:8 CC[15:8]
0x46 23:16 CC[23:16]
0x47 31:24
0x48
CC1
7:0 CC[7:0]
0x49 15:8 CC[15:8]
0x4A 23:16 CC[23:16]
0x4B 31:24
0x4C
CC2
7:0 CC[7:0]
0x4D 15:8 CC[15:8]
0x4E 23:16 CC[23:16]
0x4F 31:24
0x50
CC3
7:0 CC[7:0]
0x51 15:8 CC[15:8]
0x52 23:16 CC[23:16]
0x53 31:24
Offset Name
Bit
Pos.
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0x54
...
0x63
Reserved
0x64
PATTB
7:0 PGEB7 PGEB6 PGEB5 PGEB4 PGEB3 PGEB2 PGEB1 PGEB0
0x65 15:8 PGVB7 PGVB6 PGVB5 PGVB4 PGVB3 PGVB2 PGVB1 PGVB0
0x66 Reserved
0x67 Reserved
0x68
WAVEB
7:0 CIPERENB RAMPB[1:0] WAVEGENB[2:0]
0x69 15:8 CICCENB3 CICCENB2 CICCENB1 CICCENB0
0x6A 23:16 POLB3 POLB2 POLB1 POLB0
0x6B 31:24 SWAPB3 SWAPB2 SWAPB1 SWAPB0
0x6C
PERB
7:0 PERB[7:0]
0x6D 15:8 PERB[15:8]
0x6E 23:16 PERB[23:16]
0x6F 31:24
0x70
CCB0
7:0 CCB[7:0]
0x71 15:8 CCB[15:8]
0x72 23:16 CCB[23:16]
0x73 31:24
0x74
CCB1
7:0 CCB[7:0]
0x75 15:8 CCB[15:8]
0x76 23:16 CCB[23:16]
0x77 31:24
0x78
CCB2
7:0 CCB[7:0]
0x79 15:8 CCB[15:8]
0x7A 23:16 CCB[23:16]
0x7B 31:24
0x7C
CCB3
7:0 CCB[7:0]
0x7D 15:8 CCB[15:8]
0x7E 23:16 CCB[23:16]
0x7F 31:24
Offset Name
Bit
Pos.
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28.8 Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters
and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by
the Write-Protected property in each individual register description. Refer to the “Register Access Protection” on page
611 and the PAC chapter for details.
Some registers require synchronization when read and/or written. Synchronization is denoted by the Write-Synchronized
or Read-Synchronized property in each individual register description. Refer to the “Synchronization” on page 641 for
details.
Some registers are enable-protected, meaning they can only be written when the TCC is disabled. Enable-protection is
denoted by the Enable-Protected property in each individual register description.
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28.8.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00000000
Property: Enable-Protected, Write-Protected, Write-Synchronized
zBits 31:28 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 27:24 – CPTENx [x=3..0]: Capture Channel x Enable
These bits are used to select the capture or compare operation on channel x. The number of available channels
depend on the TCC instance.
Writing a one to CAPTENx enables capture on channel x.
Writing a zero to CAPTENx disables capture on channel x.
These bits are not synchronized.
zBits 23:15 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 14 – ALOCK: Auto Lock
When this bit is set, Lock Update (LUPD) is set to one on each overflow/underflow or re-trigger event.
0: The LUPD bit is not affected on overflow/underflow, and re-trigger event.
1: The LUPD bit is set on each overflow/underflow or re-trigger event.
Bit 3130292827262524
CPTEN3 CPTEN2 CPTEN1 CPTEN0
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
AccessRRRRRRRR
Reset00000000
Bit 151413121110 9 8
ALOCK PRESCSYNC[1:0]
RUNSTDBY PRESCALER[2:0]
Access R R/W R/W R/W R/W R/W R/W R/W
Reset00000000
Bit 76543210
RESOLUTION[1:0] ENABLE SWRST
Access R R/W R/W R R R R/W R/W
Reset00000000
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This bit is not synchronized.
zBits 13:12 – PRESCSYNC[1:0]: Prescaler and Counter Synchronization Selection
These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCCx clock or
on the next prescaled GCLK_TCCx clock. It also makes possible to reset the prescaler on retrigger event, as
shown in the following table.
These bits are not synchronized.
Table 28-6. Prescaler and Counter Synchronization Selection
zBit 11 – RUNSTDBY: Run in Standby
This bit is used to keep the TCC running in standby mode:
0: The TCC is halted in standby.
1: The TCC continues to run in standby.
This bit is not synchronized.
zBits 10:8 – PRESCALER[2:0]: Prescaler
These bits select the Counter prescaler factor as shown in the following table.
These bits are not synchronized.
Table 28-7. Prescaler
zBit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 6:5 – RESOLUTION[1:0]: Enhanced Resolution
These bits increase the TCC resolution by enabling the dithering options, according to the following table.
These bits are not synchronized.
PRESCSYNC[1:0] Name Description
0x0 GCLK Reload or reset counter on next GCLK
0x1 PRESC Reload or reset counter on next prescaler clock
0x2 RESYNC Reload or reset counter on next GCLK and reset prescaler
counter
0x3 Reserved
PRESCALER[2:0] Name Description
0x0 DIV1 No division
0x1 DIV2 Divide by 2
0x2 DIV4 Divide by 4
0x3 DIV8 Divide by 8
0x4 DIV16 Divide by 16
0x5 DIV64 Divide by 64
0x6 DIV256 Divide by 256
0x7 DIV1024 Divide by 1024
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Table 28-8. Enhanced Resolution
zBits 4:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 1 – ENABLE: Enable
0: The peripheral is disabled.
1: The peripheral is enabled.
Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRLA.ENABLE will read back immediately and the ENABLE bit in the SYNCBUSY register
(SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.
zBit 0 – SWRST: Software Reset
0: There is no reset operation ongoing.
1: The reset operation is ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the TCC, except DBGCTRL, to their initial state, and the TCC will be
disabled.
Writing a one to CTRLA.SWRST will always take precedence; all other writes in the same write-operation will be
discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST
and SYNCBUSY.SWRST will both be cleared when the reset is complete.
RESOLUTION[1:0] Name Description
0x0 NONE Dithering is disabled
0x1 DITH4 Dithering is done every 16 PWM frames
0x2 DITH5 Dithering is done every 32 PWM frames
0x3 DITH6 Dithering is done every 64 PWM frames
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28.8.2 Control B Clear
This register allows the user to change the below mentioned functionalities without doing a read-modify-write operation.
Changes in this register will also be reflected in the Control B Set (CTRLBSET) register.
Name: CTRLBCLR
Offset: 0x04
Reset: 0x00
Property: Read-Synchronized, Write-Protected, Write-Synchronized
zBits 7:5 – CMD[2:0]: TCC Command
These bits can be used for software control of re-triggering and stop commands of the TCC. When a command
has been executed, the CMD bit field will read back zero. The commands are executed on the next prescaled
GCLK_TCC clock cycle.
Writing a zero to this bit group has no effect.
Writing a valid value to these bits will clear the corresponding pending command.
Table 28-9. TCC Command
zBits 4:3 – IDXCMD[1:0]: Ramp Index Command
These bits can be used to force cycle A and cycle B changes in RAMP2 and RAMP2A operation, according to the
following table. On timer/counter update condition, the command is executed, the IDX flag in STATUS register is
updated and the IDXCMD command is cleared.
Writing a zero to this field has no effect.
Writing a valid value to this field will clear the pending command.
Table 28-10. Ramp Index Command
Bit 76543210
CMD[2:0] IDXCMD[1:0] ONESHOT LUPD DIR
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
CMD[2:0] Name Description
0x0 NONE No action
0x1 RETRIGGER Clear start, restart or retrigger
0x2 STOP Force stop
0x3 UPDATE Force update of double buffered registers
0x4 READSYNC Force COUNT read synchronization
0x5-0x7 Reserved
IDXCMD[1:0] Name Description
0x0 DISABLE Command disabled: Index toggles between cycles A and B
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zBit 2 – ONESHOT: One-Shot
This bit controls one-shot operation of the TCC. When one-shot operation is enabled, the TCC will stop counting
on the next overflow/underflow condition or on a stop command.
0: The TCC will update the counter value on overflow/underflow condition and continues operation.
1: The TCC will stop counting on the next underflow/overflow condition.
Writing a zero to this bit has no effect
Writing a one to this bit will disable the one-shot operation.
zBit 1 – LUPD: Lock Update
This bit controls the update operation of the TCC buffered registers. When this bit is set, no update of the buffered
registers is performed, even though an UPDATE condition has occurred. Locking the update ensures that all buf-
fers registers are valid before an update is performed.
This bit has no effect when input capture operation is enabled.
1: The CCBx, PERB, PGVB, PGEB, and SWAPBx buffer registers value are not copied into the corresponding
CCx, PER, PGV, PGE and SWAPx registers.
0: The CCBx, PERB, PGVB, PGEB, and SWAPBx buffer registers value are copied into the corresponding CCx,
PER, PGV, PGE and SWAPx registers on counter update condition.
zBit 0 – DIR: Counter Direction
This bit is used to change the direction of the counter.
0: The timer/counter is counting up (incrementing).
1: The timer/counter is counting down (decrementing).
Writing a zero to this bit has no effect
Writing a one to this bit will make the counter count up.
0x1 SET Set index: cycle B will be forced in the next cycle
0x2 CLEAR Clear index: cycle A will be forced in the next cycle
0x3 HOLD Hold index: the next cycle will be the same as the current
cycle
IDXCMD[1:0] Name Description
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28.8.3 Control B Set
This register allows the user to change the below mentioned functionalities without doing a read-modify-write operation.
Changes in this register will also be reflected in the Control B Clear (CTRLBCLR) register.
Name: CTRLBSET
Offset: 0x05
Reset: 0x00
Property: Write-Protected, Write-Synchronized
zBits 7:5 – CMD[2:0]: TCC Command
These bits can be used for software control of re-triggering and stop commands of the TCC. When a command
has been executed, the CMD field will be read back as zero. The commands are executed on the next prescaled
GCLK_TCC clock cycle.
Writing a zero to this bit group has no effect
Writing a valid value into this bit group will set the associated command, as shown in the table below.
Table 28-11. TCC Command
zBits 4:3 – IDXCMD[1:0]: Ramp Index Command
These bits can be used to force cycle A and cycle B changes in RAMP2 and RAMP2A operation, according to the
table below. On timer/counter update condition, the command is executed, the IDX flag in STATUS register is
updated and the IDXCMD command is cleared.
Writing a zero to this field has no effect.
Writing a valid value into this field will set a command.
Table 28-12. Ramp Index Command
Bit 76543210
CMD[2:0] IDXCMD[1:0] ONESHOT LUPD DIR
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
CMD[2:0] Name Description
0x0 NONE No action
0x1 RETRIGGER Clear start, restart or retrigger
0x2 STOP Force stop
0x3 UPDATE Force update of double buffered registers
0x4 READSYNC Force COUNT read synchronization
0x5-0x7 Reserved
IDXCMD[1:0] Name Description
0x0 DISABLE Command disabled: Index toggles between cycles A and B
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zBit 2 – ONESHOT: One-Shot
This bit controls one-shot operation of the TCC. When in one-shot operation, the TCC will stop counting on the
next overflow/underflow condition or a stop command.
0: The TCC will count continuously.
1: The TCC will stop counting on the next underflow/overflow condition.
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the one-shot operation.
zBit 1 – LUPD: Lock Update
This bit controls the update operation of the TCC buffered registers. When this bit is set, no update of the buffered
registers is performed, even though an UPDATE condition has occurred. Locking the update can be used to
ensure that all buffer registers are loaded with the desired values, before an update is performed. After all the buf-
fer registers are loaded correctly, the buffered registers can be unlocked.
This bit has no effect when input capture operation is enabled.
1: The CCBx, PERB, PGVB, PGEB, and SWAPBx buffer registers value are not copied into CCx, PER, PGV, PGE
and SWAPx registers.
0: The CCBx, PERB, PGVB, PGEB, and SWAPBx buffer registers value are copied into CCx, PER, PGV, PGE
and SWAPx registers on timer Overflow/underflow or retrigger condition.
zBit 0 – DIR: Counter Direction
This bit is used to change the direction of the counter.
0: The timer/counter is counting up (incrementing).
1: The timer/counter is counting down (decrementing).
Writing a zero to this bit has no effect
Writing a one to this bit will make the counter count down.
0x1 SET Set index: cycle B will be forced in the next cycle
0x2 CLEAR Clear index: cycle A will be forced in the next cycle
0x3 HOLD Hold index: the next cycle will be the same as the current
cycle
IDXCMD[1:0] Name Description
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28.8.4 Synchronization Busy
Name: SYNCBUSY
Offset: 0x08
Reset: 0x00000000
Property: -
zBits 31:23 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 22:19 – CCBx [x=3..0]: Compare Channel Buffer x Busy
This bit is cleared when the synchronization of Compare/Capture Channel x Buffer register between the clock
domains is complete.
This bit is set when the synchronization of Compare/Capture Channel x Buffer register between clock domains is
started.
CCBx bit is available only for existing Compare/Capture Channels. For details on CC channels number, refer to
each TCC feature list.
This bit is set when the synchronization of CCBx register between clock domains is started.
zBit 18 – PERB: Period Buffer Busy
This bit is cleared when the synchronization of PERB register between the clock domains is complete.
This bit is set when the synchronization of PERB register between clock domains is started.
zBit 17 – WAVEB: Wave Buffer Busy
This bit is cleared when the synchronization of WAVEB register between the clock domains is complete.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
CCB3 CCB2 CCB1 CCB0 PERB WAVEB PATTB
AccessRRRRRRRR
Reset00000000
Bit 151413121110 9 8
CC3 CC2 CC1 CC0
AccessRRRRRRRR
Reset00000000
Bit 76543210
PER WAVE PATT COUNT STATUS CTRLB ENABLE SWRST
AccessRRRRRRRR
Reset00000000
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This bit is set when the synchronization of WAVEB register between clock domains is started.
zBit 16 – PATTB: Pattern Buffer Busy
This bit is cleared when the synchronization of PATTB register between the clock domains is complete.
This bit is set when the synchronization of PATTB register between clock domains is started.
zBits 15:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 11:8 – CCx [x=3..0]: Compare Channel x Busy
This bit is cleared when the synchronization of Compare/Capture Channel x register between the clock domains is
complete.
This bit is set when the synchronization of Compare/Capture Channel x register between clock domains is started.
CCx bit is available only for existing Compare/Capture Channels. For details on CC channels number, refer to
each TCC feature list.
This bit is set when the synchronization of CCx register between clock domains is started.
zBit 7 – PER: Period busy
This bit is cleared when the synchronization of PER register between the clock domains is complete.
This bit is set when the synchronization of PER register between clock domains is started.
zBit 6 – WAVE: Wave Busy
This bit is cleared when the synchronization of WAVE register between the clock domains is complete.
This bit is set when the synchronization of WAVE register between clock domains is started.
zBit 5 – PATT: Pattern Busy
This bit is cleared when the synchronization of PATT register between the clock domains is complete.
This bit is set when the synchronization of PATT register between clock domains is started.
zBit 4 – COUNT: Count Busy
This bit is cleared when the synchronization of COUNT register between the clock domains is complete.
This bit is set when the synchronization of COUNT register between clock domains is started.
zBit 3 – STATUS: Status Busy
This bit is cleared when the synchronization of STATUS register between the clock domains is complete.
This bit is set when the synchronization of STATUS register between clock domains is started.
zBit 2 – CTRLB: Ctrlb Busy
This bit is cleared when the synchronization of CTRLB register between the clock domains is complete.
This bit is set when the synchronization of CTRLB register between clock domains is started.
zBit 1 – ENABLE: Enable Busy
This bit is cleared when the synchronization of ENABLE register bit between the clock domains is complete.
This bit is set when the synchronization of ENABLE register bit between clock domains is started.
zBit 0 – SWRST: Swrst Busy
This bit is cleared when the synchronization of SWRST register bit between the clock domains is complete.
This bit is set when the synchronization of SWRST register bit between clock domains is started.
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28.8.5 Recoverable Fault A Configuration
Name: FCTRLA
Offset: 0x0C
Reset: 0x00000000
Property: Enable-Protected, Write-Protected
zBits 31:28 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 27:24 – FILTERVAL[3:0]: Fault A Filter Value
These bits define the filter value applied on MCEx (x=0,1) event input line. The value must be set to zero when
MCEx event is used as synchronous event.
zBits 23:16 – BLANKVAL[7:0]: Fault A Blanking Time
These bits are used to ignore potential glitches after selectable waveform edge is detected. The edge selection is
available in BLANK bits (FCTRLA.BLANK). When enabled, the fault input source is internally disabled during
BLANKVAL* prescaled GCLK_TCC periods after the detection of the waveform edge.
zBit 15 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 14:12 – CAPTURE[2:0]: Fault A Capture Action
These bits select the capture and Fault A interrupt/event conditions, as defined in the table below.
Bit 3130292827262524
FILTERVAL[3:0]
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
BLANKVAL[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
CAPTURE[2:0] CHSEL[1:0] HALT[1:0]
Access R R/W R/W R/W R/W R/W R/W R/W
Reset00000000
Bit 76543210
RESTART BLANK[1:0] QUAL KEEP SRC[1:0]
Access R/W R/W R/W R/W R/W R R/W R/W
Reset00000000
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Table 28-13. Fault A Capture Action
zBits 11:10 – CHSEL[1:0]: Fault A Capture Channel
These bits select the channel for capture operation triggered by recoverable Fault A, as defined in the table below.
Table 28-14. Fault A Capture Channel
zBits 9:8 – HALT[1:0]: Fault A Halt Mode
These bits select the halt action for recoverable Fault A as defined in the table below.
Table 28-15. Fault A Halt Mode
zBit 7 – RESTART: Fault A Restart
Setting this bit enables restart action for Fault A.
0: Fault A restart action is disabled.
1: Fault A restart action is enabled.
zBits 6:5 – BLANK[1:0]: Fault A Blanking Mode
These bits, select the blanking start point for recoverable Fault A as defined in the table below.
CAPTURE[2:0] Name Description
0x0 DISABLE No capture
0x1 CAPT Capture on fault
0x2 CAPTMIN Minimum capture
0x3 CAPTMAX Maximum capture
0x4 LOCMIN Minimum local detection
0x5 LOCMAX Maximum local detection
0x6 DERIV0 Minimum and maximum local detection
0x7 Reserved
CHSEL[1:0] Name Description
0x0 CC0 Capture value stored in channel 0
0x1 CC1 Capture value stored in channel 1
0x2 CC2 Capture value stored in channel 2
0x3 CC3 Capture value stored in channel 3
HALT[1:0] Name Description
0x0 DISABLE Halt action disabled
0x1 HW Hardware halt action
0x2 SW Software halt action
0x3 NR Non-recoverable fault
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Table 28-16. Fault A Blanking Mode
zBit 4 – QUAL: Fault A Qualification
Setting this bit, enables the recoverable Fault A input qualification.
0: The recoverable Fault A input is not disabled on CMPx value condition.
1: The recoverable Fault A input is disabled when output signal is at inactive level (CMPx == 0).
zBit 3 – KEEP: Fault A Keeper
Setting this bit enables the Fault A keep action.
0: The Fault A state is released as soon as the recoverable Fault A is released.
1: The Fault A state is released at the end of TCC cycle.
zBit 2 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 1:0 – SRC[1:0]: Fault A Source
These bits select the TCC event input for recoverable Fault A, as defined in the table below.
Event system channel connected to MCEx event input, must be configured to route the event asynchronously,
when used as a recoverable Fault A input.
Table 28-17. Fault A Source
BLANK[1:0] Name Description
0x0 NONE No Blanking applied
0x1 RISE Blanking applied from rising edge of the output waveform
0x2 FALL Blanking applied from falling edge of the output waveform
0x3 BOTH Blanking applied from each toggle of the output waveform
SRC[1:0] Name Description
0x0 DISABLE Fault input disabled
0x1 ENABLE MCEx (x=0,1) event input
0x2 INVERT Inverted MCEx (x=0,1) event input
0x3 ALTFAULT Alternate fault (A or B) state at the end of the previous period
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28.8.6 Recoverable Fault B Configuration
Name: FCTRLB
Offset: 0x10
Reset: 0x00000000
Property: Enable-Protected, Write-Protected
zBits 31:28 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 27:24 – FILTERVAL[3:0]: Fault B Filter Value
These bits define the filter value applied on MCEx (x=0,1) event input line. The value must be set to zero when
MCEx event is used as synchronous event.
zBits 23:16 – BLANKVAL[7:0]: Fault B Blanking Time
These bits are used to ignore potential glitches after selectable waveform edge is detected. The edge selection is
available in BLANK bits (FCTRLB.BLANK). When enabled, the fault input source is internally disabled during
BLANKVAL* prescaled GCLK_TCC periods after the detection of the edge.
zBit 15 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 14:12 – CAPTURE[2:0]: Fault B Capture Action
These bits select the capture and Fault B interrupt/event conditions, as defined in table below.
Bit 3130292827262524
FILTERVAL[3:0]
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
BLANKVAL[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
CAPTURE[2:0] CHSEL[1:0] HALT[1:0]
Access R R/W R/W R/W R/W R/W R/W R/W
Reset00000000
Bit 76543210
RESTART BLANK[1:0] QUAL KEEP SRC[1:0]
Access R/W R/W R/W R/W R/W R R/W R/W
Reset00000000
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Table 28-18. Fault B Capture Action
zBits 11:10 – CHSEL[1:0]: Fault B Capture Channel
These bits select the channel for capture operation triggered by recoverable Fault B, as defined in the table below.
Table 28-19. Fault B Capture Channel
zBits 9:8 – HALT[1:0]: Fault B Halt Mode
These bits select the halt action for recoverable Fault B as defined in the table below.
Table 28-20. Fault B Halt Mode
zBit 7 – RESTART: Fault B Restart
Setting this bit enables restart action for Fault B.
0: Fault B restart action is disabled.
1: Fault B restart action is enabled.
zBits 6:5 – BLANK[1:0]: Fault B Blanking Mode
These bits, select the blanking start point for recoverable Fault B as defined in the table below.
CAPTURE[2:0] Name Description
0x0 DISABLE No capture
0x1 CAPT Capture on fault
0x2 CAPTMIN Minimum capture
0x3 CAPTMAX Maximum capture
0x4 LOCMIN Minimum local detection
0x5 LOCMAX Maximum local detection
0x6 DERIV0 Minimum and maximum local detection
0x7 Reserved
CHSEL[1:0] Name Description
0x0 CC0 Capture value stored in channel 0
0x1 CC1 Capture value stored in channel 1
0x2 CC2 Capture value stored in channel 2
0x3 CC3 Capture value stored in channel 3
HALT[1:0] Name Description
0x0 DISABLE Halt action disabled
0x1 HW Hardware halt action
0x2 SW Software halt action
0x3 NR Non-recoverable fault
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Table 28-21. Fault B Blanking Mode
zBit 4 – QUAL: Fault B Qualification
Setting this bit, enables the recoverable Fault B input qualification.
0: The recoverable Fault B input is not disabled on CMPx value condition.
1: The recoverable Fault B input is disabled when output signal is at inactive level (CMPx == 0).
zBit 3 – KEEP: Fault B Keeper
Setting this bit enables the Fault B keep action.
0: The Fault B state is released as soon as the recoverable Fault B is released.
1: The Fault B state is released at the end of TCC cycle.
zBit 2 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 1:0 – SRC[1:0]: Fault B Source
These bits select the TCC event input for recoverable Fault B, as defined in the table below.
Event system channel connected to MCEx event input, must be configured to route the event asynchronously,
when used as a recoverable Fault B input.
Table 28-22. Fault B Source
BLANK[1:0] Name Description
0x0 NONE No Blanking applied
0x1 RISE Blanking applied from rising edge of the output waveform
0x2 FALL Blanking applied from falling edge of the output waveform
0x3 BOTH Blanking applied from each toggle of the output waveform
SRC[1:0] Name Description
0x0 DISABLE Fault input disabled
0x1 ENABLE MCEx (x=0,1) event input
0x2 INVERT Inverted MCEx (x=0,1) event input
0x3 ALTFAULT Alternate fault (A or B) state at the end of the previous period
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28.8.7 Waveform Extension Configuration
Name: WEXCTRL
Offset: 0x14
Reset: 0x00000000
Property: Enable-Protected, Write-Protected
zBits 31:24 – DTHS[7:0]: Dead-time High Side Outputs Value
This register holds the number of GCLK_TCC clock cycles for the dead-time high side.
zBits 23:16 – DTLS[7:0]: Dead-time Low Side Outputs Value
This register holds the number of GCLK_TCC clock cycles for the dead-time low side.
zBits 15:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 11:8 – DTIENx [x=3..0]: Dead-time Insertion Generator x Enable
Setting any of these bits enables the dead-time insertion generator for the corresponding output matrix. This will
override the output matrix [x] and [x+WO_NUM/2], with the low side and high side waveform respectively.
0: No dead-time insertion override.
1: Dead time insertion override on signal outputs[x] and [x+WO_NUM/2], from matrix outputs[x] signal.
zBits 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit 3130292827262524
DTHS[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
DTLS[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
DTIEN3 DTIEN2 DTIEN1 DTIEN0
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 76543210
OTMX[1:0]
AccessRRRRRRR/WR/W
Reset00000000
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zBits 1:0 – OTMX[1:0]: Output Matrix
These bits define the matrix routing of the TCC waveform generation outputs to the port pins, according to Table
28-3.
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28.8.8 Driver Control
Name: DRVCTRL
Offset: 0x18
Reset: 0x00000000
Property: Enable-Protected, Write-Protected
zBits 31:28 – FILTERVAL1[3:0]: Non-Recoverable Fault Input 1 Filter Value
These bits define the filter value applied on TCEx event input line. This value must be 0 when TCEx event input
line is configured as asynchronous event.
zBits 27:24 – FILTERVAL0[3:0]: Non-Recoverable Fault Input 0 Filter Value
These bits define the filter value applied on TCEx event input line. This value must be 0 when TCEx event input
line is configured as asynchronous event.
zBits 23:16 – INVENx [x=7..0]: Output Waveform x Inversion
These bits are used to select inversion on the output of channel x.
Writing a one to INVENx inverts output from WO[x].
Writing a zero to INVENx disables inversion of output from WO[x].
These bits define the value of the enabled override outputs, under non-recoverable fault condition.
zBits 15:8 – NRVx [x=7..0]: Non-Recoverable State x Output Value
These bits define the value of the enabled override outputs, under non-recoverable fault condition.
zBits 7:0 – NREx [x=7..0]: Non-Recoverable State x Output Enable
These bits enable the override of individual outputs by NRVx value, under non-recoverable fault condition.
Bit 3130292827262524
FILTERVAL1[3:0] FILTERVAL0[3:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
INVEN7 INVEN6 INVEN5 INVEN4 INVEN3 INVEN2 INVEN1 INVEN0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
NRV7 NRV6 NRV5 NRV4 NRV3 NRV2 NRV1 NRV0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
NRE7 NRE6 NRE5 NRE4 NRE3 NRE2 NRE1 NRE0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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0: Non-recoverable fault tri-state the output.
1: Non-recoverable faults set the output to NRVx level.
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28.8.9 Debug Control
Name: DBGCTRL
Offset: 0x1E
Reset: 0x00
Property: Write-Protected
zBits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 2 – FDDBD: Fault Detection on Debug Break Detection
This bit is not affected by software reset and should not be changed by software while the TCC is enabled.
By default this bit is zero, the on-chip debug (OCD) fault protection is enabled. OCD break request from the OCD
system will trigger non-recoverable fault. When this bit is set, OCD fault protection is disabled and OCD break
request will not trigger a fault.
0: No faults are generated when TCC is halted in debug mode.
1: A non recoverable fault is generated and DFS flag is set when TCC is halted in debug mode.
zBit 1 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 0 – DBGRUN: Debug Running Mode
This bit is not affected by software reset and should not be changed by software while the TCC is enabled.
0: The TCC is halted when the device is halted in debug mode.
1: The TCC continues normal operation when the device is halted in debug mode.
Bit 76543210
FDDBD DBGRUN
AccessRRRRRR/WRR/W
Reset00000000
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28.8.10 Event Control
Name: EVCTRL
Offset: 0x20
Reset: 0x00000000
Property: Write-Protected
zBits 31:28 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 27:24 – MCEOx [x=3..0]: Match or Capture Channel x Event Output Enable
These bits control if the Match/capture event on channel x is enabled and will be generated for every match or
capture.
0: Match/capture x event is disabled and will not be generated.
1: Match/capture x event is enabled and will be generated for every compare/capture on channel x.
zBits 23:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 19:16 – MCEIx [x=3..0]: Match or Capture Channel x Event Input Enable
These bits indicate if the Match/capture x incoming event is enabled
These bits are used to enable match or capture input events to the CCx channel of TCC.
0: Incoming events are disabled.
1: Incoming events are enabled.
Bit 3130292827262524
MCEO3 MCEO2 MCEO1 MCEO0
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
MCEI3 MCEI2 MCEI1 MCEI0
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
TCEI1 TCEI0 TCINV1 TCINV0 CNTEO TRGEO OVFEO
Access R/W R/W R/W R/W R R/W R/W R/W
Reset00000000
Bit 76543210
CNTSEL[1:0] EVACT1[2:0] EVACT0[2:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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zBits 15:14 – TCEIx [x=1..0]: Timer/counter Event x Input Enable
This bit is used to enable input event x to the TCC.
0: Incoming event x is disabled.
1: Incoming event x is enabled.
zBits 13:12 – TCINVx [x=1..0]: Inverted Event x Input Enable
This bit inverts the event x input.
0: Input event source x is not inverted.
1: Input event source x is inverted.
zBit 11 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 10 – CNTEO: Timer/counter Output Event Enable
This bit is used to enable the counter cycle event. When enabled, an event will be generated on begin or end of
counter cycle depending of CNTSEL[1:0] settings.
0: Counter cycle output event is disabled and will not be generated.
1: Counter cycle output event is enabled and will be generated depend of CNTSEL[1:0] value.
zBit 9 – TRGEO: Retrigger Output Event Enable
This bit is used to enable the counter retrigger event. When enabled, an event will be generated when the counter
retriggers operation.
0: Counter retrigger event is disabled and will not be generated.
1: Counter retrigger event is enabled and will be generated for every counter retrigger.
zBit 8 – OVFEO: Overflow/Underflow Output Event Enable
This bit is used to enable the overflow/underflow event. When enabled, an event will be generated when the coun-
ter reaches the TOP or the ZERO value.
0: Overflow/underflow counter event is disabled and will not be generated.
1: Overflow/underflow counter event is enabled and will be generated for every counter overflow/underflow.
zBits 7:6 – CNTSEL[1:0]: Timer/counter Output Event Mode
These bits define on which part of the counter cycle the counter event output is generated.
Table 28-23. Timer/counter Output Event Mode
zBits 5:3 – EVACT1[2:0]: Timer/counter Input Event1 Action
These bits define the action the TCC will perform on TCCx EV1 event input, as shown in the table below.
CNTSEL[1:0] Name Description
0x0 START An interrupt/event is generated when a new counter cycle
starts
0x1 END An interrupt/event is generated when a counter cycle ends
0x2 BETWEEN An interrupt/event is generated when a counter cycle ends,
except for the first and last cycles
0x3 BOUNDARY An interrupt/event is generated when a new counter cycle
starts or a counter cycle ends
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Table 28-24. Timer/counter Input Event1 Action
zBits 2:0 – EVACT0[2:0]: Timer/counter Input Event0 Action
These bits define the action the TCC will perform on TCCx EV0 event input 0, as shown in the table below.
Table 28-25. Timer/counter Input Event0 Action
EVACT1[2:0] Name Description
0x0 OFF Event action disabled
0x1 RETRIGGER Re-trigger counter on event
0x2 DIR Direction control
0x3 STOP Stop counter on event
0x4 DEC Decrement counter on event
0x5 PPW Period capture value in CC0 register, pulse width capture
value in CC1 register
0x6 PWP Period capture value in CC1 register, pulse width capture
value in CC0 register
0x7 FAULT Non-recoverable fault
EVACT0[2:0] Name Description
0x0 OFF Event action disabled
0x1 RETRIGGER Start, restart or re-trigger counter on event
0x2 COUNTEV Count on event
0x3 START Start counter on event
0x4 INC Increment counter on event
0x5 COUNT Count on active state of asynchronous event
0x6 Reserved
0x7 FAULT Non-recoverable fault
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28.8.11 Interrupt Enable Clear
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set (INTENSET) register.
Name: INTENCLR
Offset: 0x24
Reset: 0x00000000
Property: Write-Protected
zBits 31:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 19:16 – MCx [x=3..0]: Match or Capture Channel x Interrupt Enable
0: The Match or Capture Channel x interrupt is disabled.
1: The Match or Capture Channel x interrupt is enabled.
Writing a zero to MCx has no effect.
Writing a one to MCx will clear the corresponding Match or Capture Channel x Interrupt Disable/Enable bit, which
disables the Match or Capture Channel x interrupt.
zBit 15 – FAULT1: Non-Recoverable Fault 1 Interrupt Enable
0: The Non-Recoverable Fault 1 interrupt is disabled.
1: The Non-Recoverable Fault 1 interrupt is enabled.
Writing a zero to this bit has no effect.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
MC3 MC2 MC1 MC0
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
FAULT1 FAULT0 FAULTB FAULTA DFS
Access R/W R/W R/W R/W R/W R R R
Reset00000000
Bit 76543210
ERR CNT TRG OVF
AccessRRRRR/WR/WR/WR/W
Reset00000000
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Writing a one to this bit will clear the Non-Recoverable Fault 1 Interrupt Disable/Enable bit, which disables the
Non-Recoverable Fault 1 interrupt.
zBit 14 – FAULT0: Non-Recoverable Fault 0 Interrupt Enable
0: The Non-Recoverable Fault 0 interrupt is disabled.
1: The Non-Recoverable Fault 0 interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Non-Recoverable Fault 0 Interrupt Disable/Enable bit, which disables the
Non-Recoverable Fault 0 interrupt.
zBit 13 – FAULTB: Recoverable Fault B Interrupt Enable
0: The Recoverable Fault B interrupt is disabled.
1: The Recoverable Fault B interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Recoverable Fault B Interrupt Disable/Enable bit, which disables the Recover-
able Fault B interrupt.
zBit 12 – FAULTA: Recoverable Fault A Interrupt Enable
0: The Recoverable Fault A interrupt is disabled.
1: The Recoverable Fault A interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Recoverable Fault A Interrupt Disable/Enable bit, which disables the Recover-
able Fault A interrupt.
zBit 11 – DFS: Non-Recoverable Debug Fault Interrupt Enable
0: The Debug Fault State interrupt is disabled.
1: The Debug Fault State interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Debug Fault State Interrupt Disable/Enable bit, which disables the Debug
Fault State interrupt.
zBits 10:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 3 – ERR: Error Interrupt Enable
0: The Error interrupt is disabled.
1: The Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Error Interrupt Disable/Enable bit, which disables the Error interrupt.
zBit 2 – CNT: Counter Interrupt Enable
0: The Counter interrupt is disabled.
1: The Counter interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Counter Interrupt Disable/Enable bit, which disables the Counter interrupt.
zBit 1 – TRG: Retrigger Interrupt Enable
0: The Retrigger interrupt is disabled.
1: The Retrigger interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Retrigger Interrupt Disable/Enable bit, which disables the Retrigger interrupt.
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zBit 0 – OVF: Overflow Interrupt Enable
0: The Overflow interrupt is disabled.
1: The Overflow interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overflow Interrupt Disable/Enable bit, which disables the Overflow interrupt.
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28.8.12 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Name: INTENSET
Offset: 0x28
Reset: 0x00000000
Property: Write-Protected
zBits 31:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 19:16 – MCx [x=3..0]: Match or Capture Channel x Interrupt Enable
0: The Match or Capture Channel x interrupt is disabled.
1: The Match or Capture Channel x interrupt is enabled.
Writing a zero to MCx has no effect.
Writing a one to MCx will set the corresponding Match or Capture Channel x Interrupt Disable/Enable bit, which
enables the Match or Capture Channel x interrupt.
zBit 15 – FAULT1: Non-Recoverable Fault 1 Interrupt Enable
0: The Non-Recoverable Fault 1 interrupt is disabled.
1: The Non-Recoverable Fault 1 interrupt is enabled.
Writing a zero to this bit has no effect.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
MC3 MC2 MC1 MC0
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
FAULT1 FAULT0 FAULTB FAULTA DFS
Access R/W R/W R/W R/W R/W R R R
Reset00000000
Bit 76543210
ERR CNT TRG OVF
AccessRRRRR/WR/WR/WR/W
Reset00000000
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Writing a one to this bit will set the Non-Recoverable Fault 1 Interrupt Disable/Enable bit, which enables the Non-
Recoverable Fault 1 interrupt.
zBit 14 – FAULT0: Non-Recoverable Fault 0 Interrupt Enable
0: The Non-Recoverable Fault 0 interrupt is disabled.
1: The Non-Recoverable Fault 0 interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Non-Recoverable Fault 0 Interrupt Disable/Enable bit, which enables the Non-
Recoverable Fault 0 interrupt.
zBit 13 – FAULTB: Recoverable Fault B Interrupt Enable
0: The Recoverable Fault B interrupt is disabled.
1: The Recoverable Fault B interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Recoverable Fault B Interrupt Disable/Enable bit, which enables the Recover-
able Fault B interrupt.
zBit 12 – FAULTA: Recoverable Fault A Interrupt Enable
0: The Recoverable Fault A interrupt is disabled.
1: The Recoverable Fault A interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Recoverable Fault A Interrupt Disable/Enable bit, which enables the Recover-
able Fault A interrupt.
zBit 11 – DFS: Non-Recoverable Debug Fault Interrupt Enable
0: The Debug Fault State interrupt is disabled.
1: The Debug Fault State interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Debug Fault State Interrupt Disable/Enable bit, which enables the Debug Fault
State interrupt.
zBits 10:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 3 – ERR: Error Interrupt Enable
0: The Error interrupt is disabled.
1: The Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Error Interrupt Disable/Enable bit, which enables the Error interrupt.
zBit 2 – CNT: Counter Interrupt Enable
0: The Counter interrupt is disabled.
1: The Counter interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Retrigger Interrupt Disable/Enable bit, which enables the Counter interrupt.
zBit 1 – TRG: Retrigger Interrupt Enable
0: The Retrigger interrupt is disabled.
1: The Retrigger interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Retrigger Interrupt Disable/Enable bit, which enables the Retrigger interrupt.
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zBit 0 – OVF: Overflow Interrupt Enable
0: The Overflow interrupt is disabled.
1: The Overflow interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overflow Interrupt Disable/Enable bit, which enables the Overflow interrupt.
675
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Atmel-42223G–SAM-R21_Datasheet–05/2016
28.8.13 Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x2C
Reset: 0x00000000
Property: -
zBits 31:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 19:16 – MCx [x=3..0]: Match or Capture x
This flag is set on the next CLK_TCC_COUNT cycle after a match with the compare condition or once CCx regis-
ter contain a valid capture value.
Writing a zero to one of these bits has no effect.
Writing a one to one of these bits will clear the corresponding Match or Capture Channel x interrupt flag
In Capture operation, this flag is automatically cleared when CCx register is read.
zBit 15 – FAULT1: Non-Recoverable Fault 1
This flag is set on the next CLK_TCC_COUNT cycle after a Non-Recoverable Fault 1 occurs.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Non-Recoverable Fault 1 interrupt flag.
zBit 14 – FAULT0: Non-Recoverable Fault 0
This flag is set on the next CLK_TCC_COUNT cycle after a Non-Recoverable Fault 0 occurs.
Writing a zero to this bit has no effect.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
MC3 MC2 MC1 MC0
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
FAULT1 FAULT0 FAULTB FAULTA DFS
Access R/W R/W R/W R/W R/W R R R
Reset00000000
Bit 76543210
ERR CNT TRG OVF
AccessRRRRR/WR/WR/WR/W
Reset00000000
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Writing a one to this bit clears the Non-Recoverable Fault 0 interrupt flag.
zBit 13 – FAULTB: Recoverable Fault B
This flag is set on the next CLK_TCC_COUNT cycle after a Recoverable Fault B occurs.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Recoverable Fault B interrupt flag.
zBit 12 – FAULTA: Recoverable Fault A
This flag is set on the next CLK_TCC_COUNT cycle after a Recoverable Fault A occurs.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Recoverable Fault A interrupt flag.
zBit 11 – DFS: Non-Recoverable Debug Fault
This flag is set on the next CLK_TCC_COUNT cycle after an Debug Fault State occurs.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Debug Fault State interrupt flag.
zBits 10:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 3 – ERR: Error
This flag is set if a new capture occurs on a channel when the corresponding Match or Capture Channel x interrupt
flag is one. In which case there is nowhere to store the new capture.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Error interrupt flag.
zBit 2 – CNT: Counter
This flag is set on the next CLK_TCC_COUNT cycle after a counter event occurs.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the CNT interrupt flag.
zBit 1 – TRG: Retrigger
This flag is set on the next CLK_TCC_COUNT cycle after a counter retrigger occurs.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Retrigger interrupt flag.
zBit 0 – OVF: Overflow
This flag is set on the next CLK_TCC_COUNT cycle after an overflow condition occurs.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Overflow interrupt flag.
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28.8.14 Status
Name: STATUS
Offset: 0x30
Reset: 0x00000001
Property: -
zBits 31:28 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 27:24 – CMPx [x=3..0]: Compare Channel x Value
This bit reflects the channel x output compare value.
0: Channel compare output value is 0.
1: Channel compare output value is 1.
zBits 23:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 19:16 – CCBVx [x=3..0]: Compare Channel x Buffer Valid
For a compare channel, the bit is set when a new value is written to the corresponding CCBx register. The bit is
cleared by writing a one to the corresponding location or automatically cleared on an UPDATE condition.
For a capture channel, the bit is set when a valid capture value is stored in the CCBx register. The bit is automati-
cally cleared when the CCx register is read.
Bit 3130292827262524
CMP3 CMP2 CMP1 CMP0
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
CCBV3 CCBV2 CCBV1 CCBV0
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
FAULT1 FAULT0 FAULTB FAULTA
FAULT1IN FAULT0IN FAULTBIN FAULTAIN
AccessR/WR/WR/WR/WRRRR
Reset00000000
Bit 76543210
PERBV WAVEBV PATTBV SLAVE DFS IDX STOP
Access R/W R/W R/W R R/W R R R
Reset00000001
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zBit 15 – FAULT1: Non-Recoverable Fault 1 State
This bit is set by hardware as soon as non-recoverable Fault 1 condition occurs.
This bit is cleared by writing a one to this bit and when the corresponding FAULT1IN status bit is low.
Once this bit is clear, the timer/counter will restart from the last COUNT value. To restart the timer/counter from
BOTTOM, the timer/counter restart command must be executed before clearing the corresponding FAULT1 bit.
For further details on timer/counter commands, refer to available commands description (CTRLBSET.CMD).
zBit 14 – FAULT0: Non-Recoverable Fault 0 State
This bit is set by hardware as soon as non-recoverable Fault 0 condition occurs.
This bit is cleared by writing a one to this bit and when the corresponding FAULT0IN status bit is low.
Once this bit is clear, the timer/counter will restart from the last COUNT value. To restart the timer/counter from
BOTTOM, the timer/counter restart command must be executed before clearing the corresponding FAULT0 bit.
For further details on timer/counter commands, refer to available commands description (CTRLBSET.CMD).
zBit 13 – FAULTB: Recoverable Fault B State
This bit is set by hardware as soon as recoverable Fault B condition occurs.
This bit is cleared by hardware when Fault B action is resumed, or by writing a one to this bit when the correspond-
ing FAULTBIN bit is low. If software halt command is enabled (FCTRLB.HALT=SW), clearing this bit release the
timer/counter.
zBit 12 – FAULTA: Recoverable Fault A State
This bit is set by hardware as soon as recoverable Fault A condition occurs.
This bit is cleared by hardware when Fault A action is resumed, or by writing a one to this bit when the correspond-
ing FAULTAIN bit is low. If software halt command is enabled (FCTRLA.HALT=SW), clearing this bit release the
timer/counter.
zBit 11 – FAULT1IN: Non-Recoverable Fault1 Input
This bit is set while an active Non-Recoverable Fault 1 input is present.
zBit 10 – FAULT0IN: Non-Recoverable Fault0 Input
This bit is set while an active Non-Recoverable Fault 0 input is present.
zBit 9 – FAULTBIN: Recoverable Fault B Input
This bit is set while an active Recoverable Fault B input is present.
zBit 8 – FAULTAIN: Recoverable Fault A Input
This bit is set while an active Recoverable Fault A input is present.
zBit 7 – PERBV: Period Buffer Valid
This bit is set when a new value is written to the PERB register. This bit is automatically cleared by hardware on
UPDATE condition or by writing a one to this bit.
zBit 6 – WAVEBV: Wave Buffer Valid
This bit is set when a new value is written to the WAVEB register. This bit is automatically cleared by hardware on
UPDATE condition or by writing a one to this bit.
zBit 5 – PATTBV: Pattern Buffer Valid
This bit is set when a new value is written to the PATTB register. This bit is automatically cleared by hardware on
UPDATE condition or by writing a one to this bit.
zBit 4 – SLAVE: Slave
Tis bit is set when TCC is set in Slave mode. This bit follows the CTRLA.MSYNC bit state.
zBit 3 – DFS: Non-Recoverable Debug Fault State
This bit is set by hardware in debug mode when DBGCTRL.FDDBD bit is set. The bit is cleared by writing a one to
this bit and when the TCC is not in debug mode.
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When the bit is set, the counter is halted and the waveforms state depend on DRVCTRL.NRE and DRVCTRL.NRV
registers.
zBit 2 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 1 – IDX: Ramp
In RAMP2 and RAMP2A operation, the bit is cleared during the cycle A and set during the cycle B. In RAMP1
operation, the bit is always read zero. For details on ramp operations, refer to “Ramp Operations” on page 628.
zBit 0 – STOP: Stop
This bit is set when the TCC is disabled, on a STOP command or on an UPDATE condition when One-Shot oper-
ation mode is enabled (CTRLBSET.ONESHOT = 1).
This bit is clear on the next incoming counter increment or decrement.
0: Counter is running.
1: Counter is stopped.
680
Atmel | SMART SAM R21 [DATASHEET]
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28.8.15 Count
Mode: DITH4
Name: COUNT
Offset: 0x34
Reset: 0x00000000
Property: Read-Synchronized, Write-Protected, Write-Synchronized
zBits 31:24 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 23:4 – COUNT[19:0]: Counter Value
These bits hold the value of the counter register.
The number of bits in this field corresponds to the size of the counter.
zBits 3:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
COUNT[19:12]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
COUNT[11:4]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
COUNT[3:0]
AccessR/WR/WR/WR/WRRRR
Reset00000000
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Mode: DITH5
Name: COUNT
Offset: 0x34
Reset: 0x00000000
Property: Read-Synchronized, Write-Protected, Write-Synchronized
zBits 31:24 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 23:5 – COUNT[18:0]: Counter Value
These bits hold the value of the counter register.
The number of bits in this field corresponds to the size of the counter.
zBits 4:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
COUNT[18:11]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
COUNT[10:3]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
COUNT[2:0]
AccessR/WR/WR/WRRRRR
Reset00000000
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Mode: DITH6
Name: COUNT
Offset: 0x34
Reset: 0x00000000
Property: Read-Synchronized, Write-Protected, Write-Synchronized
zBits 31:24 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 23:6 – COUNT[17:0]: Counter Value
These bits hold the value of the counter register.
The number of bits in this field corresponds to the size of the counter.
zBits 5:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
COUNT[17:10]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
COUNT[9:2]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
COUNT[1:0]
AccessR/WR/WRRRRRR
Reset00000000
683
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Atmel-42223G–SAM-R21_Datasheet–05/2016
28.8.16 Pattern
Name: PATT
Offset: 0x38
Reset: 0x0000
Property: Write-Synchronized
zBits 15:8 – PGVx [x=7..0]: Pattern Generator x Output Value
This register holds the values of pattern for each waveform output.
zBits 7:0 – PGEx [x=7..0]: Pattern Generator x Output Enable
This register holds the enables of pattern generation for each waveform output. A bit position at one, overrides the
corresponding SWAP output with the corresponding PGVx value.
Bit 151413121110 9 8
PGV7 PGV6 PGV5 PGV4 PGV3 PGV2 PGV1 PGV0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
PGE7 PGE6 PGE5 PGE4 PGE3 PGE2 PGE1 PGE0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
684
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
28.8.17 Waveform Control
Name: WAVE
Offset: 0x3C
Reset: 0x00000000
Property: Write-Synchronized
zBits 31:28 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 27:24 – SWAPx [x=3..0]: Swap DTI Output Pair x
Setting these bits enables output swap of DTI outputs [x] and [x+WO_NUM/2]. Note the DTIxEN settings will not
affect the swap operation.
zBits 23:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 19:16 – POLx [x=3..0]: Channel x Polarity
Setting these bits enable the output polarity in single-slope and dual-slope PWM operations.
In single-slope PWM waveform generation:
0: Compare output is initialized to ~DIR and set to DIR when TCC counter matches CCx value
1: Compare output is initialized to DIR and set to ~DIR when TCC counter matches CCx value.
In dual-slope PWM waveform generation:
0: Compare output is set to ~DIR when TCC counter matches CCx value
Bit 3130292827262524
SWAP3 SWAP2 SWAP1 SWAP0
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
POL3 POL2 POL1 POL0
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
CICCEN3 CICCEN2 CICCEN1 CICCEN0
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 76543210
CIPEREN RAMP[1:0] WAVEGEN[2:0]
Access R/W R R/W R/W R R/W R/W R/W
Reset00000000
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Atmel | SMART SAM R21 [DATASHEET]
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1: Compare output is set to DIR when TCC counter matches CCx value.
zBits 15:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 11:8 – CICCENx [x=3..0]: Circular Channel x Enable
Setting these bits enable the compare circular buffer option on channel. When the bit is set, CCx register value is
copied-back into the CCx register on UPDATE condition.
zBit 7 – CIPEREN: Circular period Enable
Setting these bits enable the period circular buffer option. When the bit field is set, the PER register value is cop-
ied-back into the PERB register on UPDATE condition.
zBit 6 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 5:4 – RAMP[1:0]: Ramp Mode
These bits select Ramp operation (RAMP), as shown in the table below. These bits are not synchronized.
Table 28-26. Ramp Mode
zBit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 2:0 – WAVEGEN[2:0]: Waveform Generation
These bits select the waveform generation operation, as shown in the table below. The settings impact the top
value and select the frequency/PWM mode. These bits are not synchronized.
Table 28-27. Waveform Generation
RAMP[1:0] Name Description
0x0 RAMP1 RAMP1 operation
0x1 RAMP2A Alternative RAMP2 operation
0x2 RAMP2 RAMP2 operation
0x3 Reserved
WAVEGEN[2:0] Name Description
0x0 NFRQ Normal frequency
0x1 MFRQ Match frequency
0x2 NPWM Normal PWM
0x3 Reserved
0x4 DSCRITICAL Dual-slope critical
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0x5 DSBOTTOM Dual-slope with interrupt/event condition when COUNT
reaches ZERO
0x6 DSBOTH Dual-slope with interrupt/event condition when COUNT
reaches ZERO or TOP
0x7 DSTOP Dual-slope with interrupt/event condition when COUNT
reaches TOP
WAVEGEN[2:0] Name Description
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28.8.18 Period
Mode: DITH4
Name: PER
Offset: 0x40
Reset: 0x00FFFFFF
Property: Write-Synchronized
zBits 31:24 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 23:4 – PER[19:0]: Period Value
These bits hold the value of the period buffer register. The value is copied to PER register on UPDATE condition.
The number of bits in this field corresponds to the size of the counter.
zBits 3:0 – DITHERCY[3:0]: Dithering Cycle Number
These bits hold the number of extra cycles that are added on the PWM period each number of frames as specified
in Table 28-8 on page 648.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
PER[19:12]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset11111111
Bit 151413121110 9 8
PER[11:4]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset11111111
Bit 76543210
PER[3:0] DITHERCY[3:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset11111111
688
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Mode: DITH5
Name: PER
Offset: 0x40
Reset: 0x00FFFFFF
Property: Write-Synchronized
zBits 31:24 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 23:5 – PER[18:0]: Period Value
These bits hold the value of the period buffer register. The value is copied to PER register on UPDATE condition.
The number of bits in this field corresponds to the size of the counter.
zBits 4:0 – DITHERCY[4:0]: Dithering Cycle Number
These bits hold the number of extra cycles that are added on the PWM period each number of frames as specified
in Table 28-8 on page 648.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
PER[18:11]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset11111111
Bit 151413121110 9 8
PER[10:3]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset11111111
Bit 76543210
PER[2:0] DITHERCY[4:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset11111111
689
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Mode: DITH6
Name: PER
Offset: 0x40
Reset: 0x00FFFFFF
Property: Write-Synchronized
zBits 31:24 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 23:6 – PER[17:0]: Period Value
These bits hold the value of the period buffer register. The value is copied to PER register on UPDATE condition.
The number of bits in this field corresponds to the size of the counter.
zBits 5:0 – DITHERCY[5:0]: Dithering Cycle Number
These bits hold the number of extra cycles that are added on the PWM period each number of frames as specified
in Table 28-8 on page 648.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
PER[17:10]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset11111111
Bit 151413121110 9 8
PER[9:2]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset11111111
Bit 76543210
PER[1:0] DITHERCY[5:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset11111111
690
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Atmel-42223G–SAM-R21_Datasheet–05/2016
28.8.19 Compare and Capture
Mode: DITH4
Name: CCn
Offset: 0x44+n*0x4 [n=0..3]
Reset: 0x00000000
Property: -
zBits 31:24 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 23:4 – CC[19:0]: Channel Compare/Capture Value
These bits hold the value of the Channel x compare/capture register.
The number of bits in this field corresponds to the size of the counter.
zBits 3:0 – DITHERCY[3:0]: Dithering Cycle Number
These bits hold the number of extra cycles that are added on the PWM pulse width each number of frames as
specified in Table 28-8 on page 648.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
CC[19:12]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
CC[11:4]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
CC[3:0] DITHERCY[3:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
691
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Mode: DITH5
Name: CCn
Offset: 0x44+n*0x4 [n=0..3]
Reset: 0x00000000
Property: -
zBits 31:24 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 23:5 – CC[18:0]: Channel Compare/Capture Value
These bits hold the value of the Channel x compare/capture register.
The number of bits in this field corresponds to the size of the counter.
zBits 4:0 – DITHERCY[4:0]: Dithering Cycle Number
These bits hold the number of extra cycles that are added on the PWM pulse width each number of frames as
specified in Table 28-8 on page 648.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
CC[18:11]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
CC[10:3]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
CC[2:0] DITHERCY[4:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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Atmel-42223G–SAM-R21_Datasheet–05/2016
Mode: DITH6
Name: CCn
Offset: 0x44+n*0x4 [n=0..3]
Reset: 0x00000000
Property: -
zBits 31:24 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 23:6 – CC[17:0]: Channel Compare/Capture Value
These bits hold the value of the Channel x compare/capture register.
The number of bits in this field corresponds to the size of the counter.
zBits 5:0 – DITHERCY[5:0]: Dithering Cycle Number
These bits hold the number of extra cycles that are added on the PWM pulse width each number of frames as
specified in Table 28-8 on page 648.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
CC[17:10]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
CC[9:2]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
CC[1:0] DITHERCY[5:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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28.8.20 Pattern Buffer
Name: PATTB
Offset: 0x64
Reset: 0x0000
Property: -
zBits 15:8 – PGVBx [x=7..0]: Pattern Generator x Output Enable
These bits represent the PGV buffers. When the double buffering is enable, PGVB bits value is copied to the PGV
bits on an UPDATE condition.
zBits 7:0 – PGEBx [x=7..0]: Pattern Generator x Output Enable Buffer
These bits represent the PGE buffers. When the double buffering is enable, PGEB bits value is copied to the PGE
bits on an UPDATE condition.
Bit 151413121110 9 8
PGVB7 PGVB6 PGVB5 PGVB4 PGVB3 PGVB2 PGVB1 PGVB0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
PGEB7 PGEB6 PGEB5 PGEB4 PGEB3 PGEB2 PGEB1 PGEB0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
694
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Atmel-42223G–SAM-R21_Datasheet–05/2016
28.8.21 Waveform Control Buffer
Name: WAVEB
Offset: 0x68
Reset: 0x00000000
Property: -
zBits 31:28 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 27:24 – SWAPBx [x=3..0]: Swap DTI Output Pair x Buffer
These bits represent the SWAP buffers. When the double buffering is enable, SWAPB bits value is copied to the
SWAP bits on an UPDATE condition.
zBits 23:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 19:16 – POLBx [x=3..0]: Channel x Polarity Buffer
These bits represent the POL buffers. When the double buffering is enable, POLB bits value is copied to the POL
bits on an UPDATE condition.
zBits 15:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit 3130292827262524
SWAPB3 SWAPB2 SWAPB1 SWAPB0
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
POLB3 POLB2 POLB1 POLB0
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
CICCENB3 CICCENB2 CICCENB1 CICCENB0
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 76543210
CIPERENB RAMPB[1:0] WAVEGENB[2:0]
Access R/W R R/W R/W R R/W R/W R/W
Reset00000000
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zBits 11:8 – CICCENBx [x=3..0]: Circular Channel x Enable Buffer
These bits represent the CICCEN buffers. When the double buffering is enable, CICCENB bits value is copied to
the CICCEN bits on an UPDATE condition.
zBit 7 – CIPERENB: Circular Period Enable Buffer
This bit represents the CIPEREN buffer. When the double buffering is enable, CIPERENB bit value is copied to the
CIPEREN bit on an UPDATE condition.
zBit 6 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 5:4 – RAMPB[1:0]: Ramp Mode Buffer
These bits represent the RAMP buffers. When the double buffering is enable, RAMPB bits value is copied to the
RAMP bits on an UPDATE condition.
Table 28-28. Ramp Mode Buffer
zBit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 2:0 – WAVEGENB[2:0]: Waveform Generation Buffer
These bits represent the WAVEGEN buffers. When the double buffering is enable, WAVEGENB bits value is cop-
ied to the WAVEGEN bits on an UPDATE condition.
Table 28-29. Waveform Generation Buffer
RAMPB[1:0] Name Description
0x0 RAMP1 RAMP1 operation
0x1 RAMP2A Alternative RAMP2 operation
0x2 RAMP2 RAMP2 operation
0x3 Reserved
WAVEGENB[2:0] Name Description
0x0 NFRQ Normal frequency
0x1 MFRQ Match frequency
0x2 NPWM Normal PWM
0x3 Reserved
0x4 DSCRITICAL Dual-slope critical
0x5 DSBOTTOM Dual-slope with interrupt/event condition when COUNT
reaches ZERO
0x6 DSBOTH Dual-slope with interrupt/event condition when COUNT
reaches ZERO or TOP
0x7 DSTOP Dual-slope with interrupt/event condition when COUNT
reaches TOP
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28.8.22 Period Buffer
Mode: DITH4
Name: PERB
Offset: 0x6C
Reset: 0x00FFFFFF
Property: -
zBits 31:24 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 23:4 – PERB[19:0]: Period Buffer Value
These bits hold the value of the period register.
The number of bits in this field corresponds to the size of the counter.
zBits 3:0 – DITHERCYB[3:0]: Dithering Buffer Cycle Number
These bits represent the PER.DITHERCY bits buffer. When the double buffering is enable, DITHERCYB bits value
is copied to the PER.DITHERCY bits on an UPDATE condition.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
PERB[19:12]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset11111111
Bit 151413121110 9 8
PERB[11:4]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset11111111
Bit 76543210
PERB[3:0] DITHERCYB[3:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset11111111
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Mode: DITH5
Name: PERB
Offset: 0x6C
Reset: 0x00FFFFFF
Property: -
zBits 31:24 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 23:5 – PERB[18:0]: Period Buffer Value
These bits hold the value of the period register.
The number of bits in this field corresponds to the size of the counter.
zBits 4:0 – DITHERCYB[4:0]: Dithering Buffer Cycle Number
These bits represent the PER.DITHERCY bits buffer. When the double buffering is enable, DITHERCYB bits value
is copied to the PER.DITHERCY bits on an UPDATE condition.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
PERB[18:11]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset11111111
Bit 151413121110 9 8
PERB[10:3]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset11111111
Bit 76543210
PERB[2:0] DITHERCYB[4:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset11111111
698
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Mode: DITH6
Name: PERB
Offset: 0x6C
Reset: 0x00FFFFFF
Property: -
zBits 31:24 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 23:6 – PERB[17:0]: Period Buffer Value
These bits hold the value of the period register.
The number of bits in this field corresponds to the size of the counter.
zBits 5:0 – DITHERCYB[5:0]: Dithering Buffer Cycle Number
These bits represent the PER.DITHERCY bits buffer. When the double buffering is enable, DITHERCYB bits value
is copied to the PER.DITHERCY bits on an UPDATE condition.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
PERB[17:10]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset11111111
Bit 151413121110 9 8
PERB[9:2]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset11111111
Bit 76543210
PERB[1:0] DITHERCYB[5:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset11111111
699
Atmel | SMART SAM R21 [DATASHEET]
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28.8.23 Compare and Capture Buffer
Mode: DITH4
Name: CCBn
Offset: 0x70+n*0x4 [n=0..3]
Reset: 0x00000000
Property: -
zBits 31:24 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 23:4 – CCB[19:0]: Channel Compare/Capture Buffer Value
These bits hold the value of the channel x compare/capture buffer register. The register serves as the buffer for the
associated compare or capture registers (CCx). Accessing this register using the CPU or DMA will affect the corre-
sponding CCBVx status bit.
The number of bits in this field corresponds to the size of the counter.
zBits 3:0 – DITHERCYB[3:0]: Dithering Buffer Cycle Number
These bits represent the CCx.DITHERCY bits buffer. When the double buffering is enable, DITHERCYB bits value
is copied to the CCx.DITHERCY bits on an UPDATE condition.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
CCB[19:12]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
CCB[11:4]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
CCB[3:0] DITHERCYB[3:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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Mode: DITH5
Name: CCBn
Offset: 0x70+n*0x4 [n=0..3]
Reset: 0x00000000
Property: -
zBits 31:24 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 23:5 – CCB[18:0]: Channel Compare/Capture Buffer Value
These bits hold the value of the channel x compare/capture buffer register. The register serves as the buffer for the
associated compare or capture registers (CCx). Accessing this register using the CPU or DMA will affect the corre-
sponding CCBVx status bit.
The number of bits in this field corresponds to the size of the counter.
zBits 4:0 – DITHERCYB[4:0]: Dithering Buffer Cycle Number
These bits represent the CCx.DITHERCY bits buffer. When the double buffering is enable, DITHERCYB bits value
is copied to the CCx.DITHERCY bits on an UPDATE condition.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
CCB[18:11]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
CCB[10:3]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
CCB[2:0] DITHERCYB[4:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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Mode: DITH6
Name: CCBn
Offset: 0x70+n*0x4 [n=0..3]
Reset: 0x00000000
Property: -
zBits 31:24 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 23:6 – CCB[17:0]: Channel Compare/Capture Buffer Value
These bits hold the value of the channel x compare/capture buffer register. The register serves as the buffer for the
associated compare or capture registers (CCx). Accessing this register using the CPU or DMA will affect the corre-
sponding CCBVx status bit.
The number of bits in this field corresponds to the size of the counter.
zBits 5:0 – DITHERCYB[5:0]: Dithering Buffer Cycle Number
These bits represent the CCx.DITHERCY bits buffer. When the double buffering is enable, DITHERCYB bits value
is copied to the CCx.DITHERCY bits on an UPDATE condition.
Bit 3130292827262524
AccessRRRRRRRR
Reset00000000
Bit 2322212019181716
CCB[17:10]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
CCB[9:2]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
CCB[1:0] DITHERCYB[5:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
702
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
29. USB – Universal Serial Bus
29.1 Overview
The Universal Serial Bus interface (USB) module complies with the Universal Serial Bus (USB) 2.1 specification
supporting both device and embedded host modes.
The USB device mode supports 8 endpoint addresses. All endpoint addresses have one input and one output endpoint,
for a total of 16 endpoints. Each endpoint is fully configurable in any of the four transfer types: control, interrupt, bulk or
isochronous. The USB host mode supports up to 8 pipes. The maximum data payload size is selectable up to 1023
bytes.
Internal SRAM is used to keep the configuration and data buffer for each endpoint. The memory locations used for the
endpoint configurations and data buffers is fully configurable. The amount of memory allocated is dynamic according to
the number of endpoints in use, and the configuration of these. The USB module has a built-in Direct Memory Access
(DMA) and will read/write data from/to the system RAM when a USB transaction takes place. No CPU or DMA Controller
resources are required.
To maximize throughput, an endpoint can be configured for ping-pong operation. When this is done the input and output
endpoint with the same address are used in the same direction. The CPU or DMA Controller can then read/write one
data buffer while the USB module writes/reads from the other buffer. This gives double buffered communication.
Multi-packet transfer enables a data payload exceeding the maximum packet size of an endpoint to be transferred as
multiple packets without any software intervention. This reduces the number of interrupts and software intervention
needed for USB transfers.
For low power operation the USB module can put the microcontroller in any sleep mode when the USB bus is idle and a
suspend condition is given. Upon bus resume the USB module can wake the microcontroller from any sleep mode.
29.2 Features
zCompatible with the USB 2.1 specification
zUSB Embedded Host and Device mode
zSupports full (12Mbit/s) and low (1.5Mbit/s) speed communication
zSupports Link Power Management (LPM-L1) protocol
zOn-chip transceivers with built-in pull-ups and pull-downs
zOn-Chip USB serial resistors
z1kHz SOF clock available on external pin
zDevice mode
zSupports 8 IN endpoints and 8 OUT endpoints
zNo endpoint size limitations
zBuilt-in DMA with multi-packet and dual bank for all endpoints
zSupports feedback endpoint
zSupports crystal less clock
zHost mode
zSupports 8 physical pipes
zNo pipe size limitations
zSupports multiplexed virtual pipe on one physical pipe to allow an unlimited USB tree
zBuilt-in DMA with multi-packet support and dual bank for all pipes
zSupports feedback endpoint
zSupports the USB 2.0 Phase-locked SOFs feature
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29.3 USB Block Diagram
Figure 29-1. LS/FS Implementation: USB Block Diagram
29.4 Signal Description
Refer to “I/O Multiplexing and Considerations” on page 12 for details on the pin mapping for this peripheral. One signal
can be mapped to one of several pins.
29.5 Product Dependencies
In order to use this peripheral module, other parts of the system must be configured correctly, as described below.
29.5.1 I/O Lines
The USB pins may be multiplexed with the I/O lines Controller. The user must first configure the I/O Controller to assign
the USB pins to their peripheral functions.
A 1kHz SOF clock is available on external pin. The user must first configure the I/O Controller to assign the 1kHz SOF
clock to the peripheral function. The SOF clock is available for device and host.
User
interface
AHB Master
USB 2.0
Core
USB
AHB
APB
NVIC
GCLK
USB interrupts
GCLK_USB
System clock domain USB clock domain
DM
DP
SOF 1kHz
Pin Name Pin Description Type
DM Data -: Differential Data Line - Port Input/Output
DP Data +: Differential Data Line + Port Input/Output
SOF 1kHZ SOF Output Output
704
Atmel | SMART SAM R21 [DATASHEET]
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29.5.2 Power Management
The USB will continue to operate in any sleep mode where the selected source clock is running. The USB’s interrupts can be
used to wake up the device from sleep modes. Events connected to the event system can trigger other operations in the system
without exiting sleep modes. Refer to the “PM – Power Manager” on page 112 for details on the different sleep modes.
29.5.3 Clocks
The USB bus clock (CLK_USB_AHB) can be enabled and disabled in the Power Manager, and the default state of
CLK_USB_AHB can be found in the Peripheral Clock Masking section in “PM – Power Manager” on page 112.
A generic clock (GCLK_USB) is required to clock the USB. This clock must be configured and enabled in the Generic
Clock Controller before using the USB. Refer to “GCLK – Generic Clock Controller” on page 90 for further details.
This generic clock is asynchronous to the bus clock (CLK_USB_AHB). Due to this asynchronicity, writes to certain
registers will require synchronization between the clock domains. Refer to “Synchronization” on page 96 for further
details.
The USB module requires a GCLK_USB of 48 MHz ± 0.25% clock for low speed and full speed operation. To follow the
USB data rate at 12Mbit/s in full-speed mode, the CLK_USB_AHB clock should be at minimum 8MHz.
Clock recovery is achieved by a digital phase-locked loop in the USB module, which complies with the USB jitter
specifications. If crystal-less operation is used in USB device mode, please refer to “USB Clock Recovery Mode” on page
152.
29.5.4 DMA
The USB has a built-in Direct Memory Access (DMA) and will read/write data from/to the system RAM when a USB
transaction takes place. No CPU or DMA Controller resources are required.
29.5.5 Interrupts
The interrupt request lines are connected to the interrupt controller. Using the USB interrupts requires the interrupt controller to
be configured first. Refer to “Nested Vector Interrupt Controller” on page 29 for details.
29.5.6 Events
Not Applicable
29.5.7 Debug Operation
When the CPU is halted in debug mode the USB continues normal operation. If the USB is configured in a way that
requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result
during debugging.
29.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the
following registers:
zDevice Interrupt Flag (INTFLAG) register
zEndpoint Interrupt Flag (EPINTFLAG) register
zHost Interrupt Flag (INTFLAG) register
zPipe Interrupt Flag (PINTFLAG) register
Write-protection is denoted by the Write-Protected property in the register description.
Write-protection does not apply to accesses through an external debugger. Refer to “PAC – Peripheral Access
Controller” on page 36 for details.
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29.5.9 Analog Connections
Not applicable.
29.5.10 Calibration
The output drivers for the DP/DM USB line interface can be tuned with calibration values from the production test. The
calibration values must be loaded from the NVM Software Calibration Area into the USB Pad Calibration register
(PADCAL) by software, before enabling the USB, to achieve the specified accuracy. Refer to “NVM Software Calibration
Area Mapping” on page 26 for further details.
For details on Pad Calibration, refer to Pad Calibration register PADCAL.
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29.6 Functional Description
29.6.1 USB General Operation
29.6.1.1 Initialization
After a hardware reset, the USB is disabled. The user should first enable the USB (CTRLA.ENABLE) in either device
mode or host mode (CTRLA.MODE).
Figure 29-2. General States
After a hardware reset, the USB is in the idle state. In this state:
zThe module is disabled. The USB Enable bit in the Control A register (CTRLA.ENABLE) is reset.
zThe module clock is stopped in order to minimize power consumption.
zThe USB pad is in suspend mode.
zThe internal states and registers of the device and host are reset.
Before using the USB, the Pad Calibration register (PADCAL) must be loaded with production calibration values from the
NVM Software Calibration Area. Refer to “NVM Software Calibration Area Mapping” on page 26 for further details.
The USB is enabled by writing a one to CTRLA.ENABLE. The USB is disabled by writing a zero to CTRLA.ENABLE.
The USB is reset by writing a one to the Software Reset bit in CTRLA (CTRLA.SWRST). All registers in the USB will be
reset to their initial state, and the USB will be disabled. Refer to the CTRLA register for details.
The user can configure pads and speed before enabling the USB by writing to the Operating Mode bit in the Control A
register (CTRLA.MODE) and the Speed Configuration field in the Control B register (CTRLB.SPDCONF). These values
are taken into account once the USB has been enabled by writing a one to CTRLA.ENABLE.
Host
CTRLA.ENABLE = 0
CTRLA.ENABLE = 1
CTRLA.MODE = 1
Device
CTRLA.ENABLE = 0
CTRLA.ENABLE = 1
CTRLA.MODE = 0
Any state
HW RESET | CTRLA.SWRST
Idle
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After writing a one to CTRLA.ENABLE, the USB enters device or host mode (according to CTRLA.MODE). Please refer
Figure 29-2.
The USB can be disabled at any time by writing a zero to CTRLA.ENABLE.
Refer to “USB Device Operations” on page 707 for the basic operation of the device mode.
Refer to “Host Operations” on page 716 for the basic operation of the host mode.
29.6.2 USB Device Operations
This section gives an overview of the USB module device operation during normal transactions. For more details on
general USB and USB protocol, please refer to the Universal Serial Bus specification revision 2.1.
29.6.2.1 Initialization
To attach the USB device to start the USB communications from the USB host, a zero should be written to the Detach bit
in the Device Control B register (CTRLB.DETACH). To detach the device from the USB host, a one must be written to the
CTRLB.DETACH.
After the device is attached, the host will request the USB device descriptor using the default device address zero. On
successful transmission, it will send a USB reset. After that, it sends an address to be configured for the device. All
further transactions will be directed to this device address. This address should be configured in the Device Address field
in the Device Address register (DADD.DADD) and the Address Enable bit in DADD (DADD.ADDEN) should be written to
one to accept the communications directed to this address. DADD.ADDEN is automatically cleared on receiving a USB
reset.
29.6.2.2 Endpoint Configuration
Endpoint data can be placed anywhere in the device RAM. The USB controller accesses these endpoints directly
through the AHB master (built-in DMA) with the help of the endpoint descriptors. The base address of the endpoint
descriptors needs to be written in the Descriptor Address register (DESCADD) by the user. Please refer the Endpoint
Descriptor structure in “Endpoint Descriptor structure” on page 761.
Before using an endpoint, the user should configure the direction and type of the endpoint in Type of Endpoint field in the
Device Endpoint Configuration register (EPCFG.EPTYPE0/1). The endpoint descriptor registers should be initialized to
known values before using the endpoint, so that the USB controller does not read the random values from the RAM.
The Endpoint Size field in the Packet Size register (PCKSIZE.SIZE) should be configured as per the size reported to the
host for that endpoint. The Address of Data Buffer register (ADDR) should be set to the data buffer used for endpoint
transfers.
The Ram Access Interrupt bit in Device Interrupt Flag register (INTFLAG.RAMACER) is set when a RAM access
underflow error occurs during IN data stage.
When an endpoint is disabled, the following registers are cleared for that endpoint:
zDevice Endpoint Interrupt Enable Clear/Set (EPINTENCLR/SET) register
zDevice Endpoint Interrupt Flag (EPINTFLAG) register
zTransmit Stall 0 bit in the Endpoint Status register (EPSTATUS.STALLRQ0)
zTransmit Stall 1 bit in the Endpoint Status register (EPSTATUS.STALLRQ1)
29.6.2.3 Multi-Packet Transfers
Multi-packet transfer enables a data payload exceeding the endpoint maximum transfer size to be transferred as multiple
packets without software intervention. This reduces the number of interrupts and software intervention required to
manage higher level USB transfers. Multi-packet transfer is identical to the IN and OUT transactions described below
unless otherwise noted in this section.
The application software provides the size and address of the RAM buffer to be proceeded by the USB module for a
specific endpoint, and the USB module will split the buffer in the required USB data transfers without any software
intervention.
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Figure 29-3. Multi-Packet Feature - Reduction of CPU Overhead
29.6.2.4 USB Reset
The USB bus reset is initiated by a connected host and managed by hardware.
During USB reset the following registers are cleared:
zDevice Endpoint Configuration (EPCFG) register - except for Endpoint 0
zDevice Frame Number (FNUM) register
zDevice Address (DADD) register
zDevice Endpoint Interrupt Enable Clear/Set (EPINTENCLR/SET) register
zDevice Endpoint Interrupt Flag (EPINTFLAG) register
zTransmit Stall 0 bit in the Endpoint Status register (EPSTATUS.STALLRQ0)
zTransmit Stall 1 bit in the Endpoint Status register (EPSTATUS.STALLRQ1)
zEndpoint Interrupt Summary (EPINTSMRY) register
zUpstream resume bit in the Control B register (CTRLB.UPRSM)
At the end of the reset process, the End of Reset bit is set in the Interrupt Flag register (INTFLAG.EORST).
29.6.2.5 Start-of-Frame
When a Start-of-Frame (SOF) token is detected, the frame number from the token is stored in the Frame Number field in
the Device Frame Number register (FNUM.FNUM) and the Start-of-Frame interrupt bit in the Device Interrupt Flag
register (INTFLAG.SOF) is set. If there is a CRC or bit-stuff error, the Frame Number Error status flag (FNUM.FNCERR)
in the FNUM register is set.
29.6.2.6 Management of SETUP Transactions
When a SETUP token is detected and the device address of the token packet does not match DADD.DADD the packet is
discarded and the USB module returns to idle and waits for the next token packet.
When the address matches, the USB module checks if the endpoint is enabled in EPCFG. If the addressed endpoint is
disabled, the packet is discarded and the USB module returns to idle and waits for the next token packet.
When the endpoint is enabled, the USB module then checks on the EPCFG of the addressed endpoint. If the
EPCFG.EPTYPE0 is not set to control, the USB module returns to idle and waits for the next token packet.
When the EPCFG.EPTYPE0 matches, the USB module then fetches the Data Buffer Address (ADDR) from the
addressed endpoint's descriptor and waits for a DATA0 packet. If a PID error or any other PID than DATA0 is detected,
the USB module returns to idle and waits for the next token packet.
When the data PID matches and if Received Setup Complete interrupt bit in the Device Endpoint Interrupt Flag register
(EPINTFLAG.RXSTP) is equal to zero, ignoring the Bank 0 Ready bit in the Device Endpoint Status register
(EPSTATUS.BK0RDY), the incoming data is written to the data buffer pointed to by the Data Buffer Address (ADDR). If
the number of received data bytes exceeds the endpoint's maximum data payload size as specified by the
Maximum Endpoint size
Data Payload
Without Multi-packet support
With Multi-packet support
Transfer Complete Interrupt
&
Data Processing
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PCKSIZE.SIZE, the remainders of the received data bytes are discarded. The packet will still be checked for bit-stuff and
CRC errors. Software must never report a endpoint size to the host that is greater than the value configured in
PCKSIZE.SIZE. If a bit-stuff or CRC error is detected in the packet, the USB module returns to idle and waits for the next
token packet.
If data is successfully received, an ACK handshake is returned to the host, and the number of received data bytes,
excluding the CRC, is written to the Byte Count (PCKSIZE.BYTE_COUNT). If the number of received data bytes is the
maximum data payload specified by PCKSIZE.SIZE, no CRC data is written to the data buffer. If the number of received
data bytes is the maximum data payload specified by PCKSIZE.SIZE minus one, only the first CRC data is written to the
data buffer. If the number of received data is equal or less than the data payload specified by PCKSIZE.SIZE minus two,
both CRC data bytes are written to the data buffer.
Finally the EPSTATUS is updated. Data Toggle OUT bit (EPSTATUS.DTGLOUT), the Data Toggle IN bit
(EPSTATUS.DTGLIN), the current bank bit (EPSTATUS.CURRBK) and the Bank Ready 0 bit (EPSTATUS.BK0RDY) are
set. Bank Ready 1 bit (EPSTATUS.BK1RDY) and the Stall Bank 0/1 bit (EPSTATUS.STALLQR0/1) are cleared on
receiving the SETUP request. The RXSTP bit is set and triggers an interrupt if the Received Setup Interrupt Enable bit is
set in Endpoint Interrupt Enable Set/Clear register (EPINTENSET/CLR.RXSTP).
29.6.2.7 Management of OUT Transactions
Figure 29-4. OUT Transfer: Data Packet Host to USB Device
When a OUT token is detected and the device address of the token packet does not match DADD.DADD, the packet is
discarded and the USB module returns to idle and waits for the next token packet.
If the address matches, the USB module checks if the endpoint number received is enabled in the EPCFG of the
addressed endpoint. If the addressed endpoint is disabled, the packet is discarded and the USB module returns to idle
and waits for the next token packet.
When the endpoint is enabled, the USB module then checks the Endpoint Configuration register (EPCFG) of the
addressed output endpoint. If the type of the endpoint (EPCFG.EPTYPE0) is not set to OUT, the USB module returns to
idle and waits for the next token packet.
Internal RAM
USB Module
USB Endpoints
Descriptor Table
DESCADD
USB I/O Registers
USB Buffers
ENDPOINT 1 DATA
ENDPOINT 2 DATA
ENDPOINT 3 DATA
D
A
T
A
0
D
A
T
A
0
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
BULK OUT
EPT 2
BULK OUT
EPT 3
BULK OUT
EPT 1
DP
DM
HOST
time
Memory Map
I/O Register
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The USB module then fetches the Data Buffer Address (ADDR) from the addressed endpoint's descriptor, and waits for a
DATA0 or DATA1 packet. If a PID error or any other PID than DATA0 or DATA1 is detected, the USB module returns to
idle and waits for the next token packet.
If EPSTATUS.STALLRQ0 in EPSTATUS is set, the incoming data is discarded. If the endpoint is not isochronous, a
STALL handshake is returned to the host and the Transmit Stall Bank 0 interrupt bit in EPINTFLAG
(EPINTFLAG.STALL0) is set.
For isochronous endpoints, data from both a DATA0 and DATA1 packet will be accepted. For other endpoint types the
PID is checked against EPSTATUS.DTGLOUT. If a PID mismatch occurs, the incoming data is discarded, and an ACK
handshake is returned to the host.
If EPSTATUS.BK0RDY is set, the incoming data is discarded, the bit Transmit Fail 0 interrupt bit in EPINTFLAG
(EPINTFLAG.TRFAIL0) and the status bit STATUS_BK.ERRORFLOW are set. If the endpoint is not isochronous, a NAK
handshake is returned to the host.
The incoming data is written to the data buffer pointed to by the Data Buffer Address (ADDR). If the number of received
data bytes exceeds the maximum data payload specified as PCKSIZE.SIZE, the remainders of the received data bytes
are discarded. The packet will still be checked for bit-stuff and CRC errors. If a bit-stuff or CRC error is detected in the
packet, the USB module returns to idle and waits for the next token packet.
If the endpoint is isochronous and a bit-stuff or CRC error in the incoming data, the number of received data bytes,
excluding CRC, is written to PCKSIZE.BYTE_COUNT. Finally the EPINTFLAG.TRFAIL0 and CRC Error bit in the Device
Bank Status register (STATUS_BK.CRCERR) is set for the addressed endpoint.
If data was successfully received, an ACK handshake is returned to the host if the endpoint is not isochronous, and the
number of received data bytes, excluding CRC, is written to PCKSIZE.BYTE_COUNT. If the number of received data
bytes is the maximum data payload specified by PCKSIZE.SIZE no CRC data bytes are written to the data buffer. If the
number of received data bytes is the maximum data payload specified by PCKSIZE.SIZE minus one, only the first CRC
data byte is written to the data buffer If the number of received data is equal or less than the data payload specified by
PCKSIZE.SIZE minus two, both CRC data bytes are written to the data buffer.
Finally in EPSTATUS for the addressed output endpoint, EPSTATUS.BK0RDY is set and EPSTATUS.DTGLOUT is
toggled if the endpoint is not isochronous. The flag Transmit Complete 0 interrupt bit in EPINTFLAG
(EPINTFLAG.TRCPT0) is set for the addressed endpoint.
29.6.2.8 Multi-Packet Transfers for OUT Endpoint
The number of data bytes received is stored in endpoint PCKSIZE.BYTE_COUNT as for normal operation. Since
PCKSIZE.BYTE_COUNT is updated after each transaction, it must be set to zero when setting up a new transfer. The
total number of bytes to be received must be written to PCKSIZE.MULTI_PACKET_SIZE. This value must be a multiple
of PCKSIZE.SIZE, otherwise excess data may be written to SRAM locations used by other parts of the application.
EPSTATUS.DTGLOUT management for non-isochronous packets and EPINTFLAG.BK1RDY/BK0RDY management
are as for normal operation.
If a maximum payload size packet is received, PCKSIZE.BYTE_COUNT will be incremented by PCKSIZE.SIZE after the
transaction has completed, and EPSTATUS.DTGLOUT will be toggled if the endpoint is not isochronous. If the updated
PCKSIZE.BYTE_COUNT is equal to PCKSIZE.MULTI_PACKET_SIZE (i.e. the last transaction),
EPSTATUS.BK1RDY/BK0RDY, and EPINTFLAG.TRCPT0/TRCPT1 will be set.
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29.6.2.9 Management of IN Transactions
Figure 29-5. IN Transfer: Data Packet USB Device to Host After Request from Host
When a IN token is detected and if the device address of the token packet does not match DADD.DADD, the packet is
discarded and the USB module returns to idle and waits for the next token packet.
When the address matches, the USB module checks if the endpoint received is enabled in the EPCFG of the addressed
endpoint and if not the packet is discarded and the USB module returns to idle and waits for the next token packet.
When the endpoint is enabled, the USB module then checks on the EPCFG of the addressed input endpoint. If the
EPCFG.EPTYPE1 is not set to IN, the USB module returns to idle and waits for the next token packet.
If EPSTATUS.STALLRQ1 in EPSTATUS is set, and the endpoint is not isochronous, a STALL handshake is returned to
the host and EPINTFLAG.STALL1 is set.
If EPSTATUS.BK1RDY is cleared, the flag EPINTFLAG.TRFAIL1 is set. If the endpoint is not isochronous, a NAK
handshake is returned to the host.
The USB module then fetches the Data Buffer Address (ADDR) from the addressed endpoint's descriptor. The data
pointed to by the Data Buffer Address (ADDR) is sent to the host in a DATA0 packet if the endpoint is isochronous. For
non-isochronous endpoints a DATA0 or DATA1 packet is sent depending on the state of EPSTATUS.DTGLIN. When the
number of data bytes specified in endpoint PCKSIZE.BYTE_COUNT is sent, the CRC is appended and sent to the host.
For isochronous endpoints, EPSTATUS.BK1RDY is cleared and EPINTFLAG.TRCPT1 is set.
For all non-isochronous endpoints the USB module waits for an ACK handshake from the host. If an ACK handshake is
not received within 16 bit times, the USB module returns to idle and waits for the next token packet. If an ACK handshake
is successfully received EPSTATUS.BK1RDY is cleared, EPINTFLAG.TRCPT1 is set and EPSTATUS.DTGLIN is
toggled.
Figure 29-6.
29.6.2.10 Multi-Packet Transfers for IN Endpoint
The total number of data bytes to be sent is written to PCKSIZE.BYTE_COUNT as for normal operation. The Multi-
packet size register (PCKSIZE.MULTI_PACKET_SIZE) is used to store the number of bytes that are sent, and must be
written to zero when setting up a new transfer.
Internal RAM
USB Module
USB Endpoints
Descriptor Table
USB Buffers
ENDPOINT 1 DATA
ENDPOINT 2 DATA
ENDPOINT 3 DATA
D
A
T
A
0
D
A
T
A
0
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
EPT 2 EPT 3 EPT 1
DP
DM
HOST
CPU
I
N
T
O
K
E
N
I
N
T
O
K
E
N
I
N
T
O
K
E
N
EPT 2 EPT 3 EPT 1
time
USB I/O Registers
Memory Map
I/O Register
DESCADD
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When an IN token is received, PCKSIZE.BYTE_COUNT and PCKSIZE.MULTI_PACKET_SIZE are fetched. If
PCKSIZE.BYTE_COUNT minus PCKSIZE.MULTI_PACKET_SIZE is less than the endpoint PCKSIZE.SIZE, endpoint
BYTE_COUNT minus endpoint PCKSIZE.MULTI_PACKET_SIZE bytes are transmitted, otherwise PCKSIZE.SIZE
number of bytes are transmitted. If endpoint PCKSIZE.BYTE_COUNT is a multiple of PCKSIZE.SIZE, the last packet
sent will be zero-length if the AUTOZLP bit is set.
If a maximum payload size packet was sent (i.e. not the last transaction), MULTI_PACKET_SIZE will be incremented by
the PCKSIZE.SIZE. If the endpoint is not isochronous the EPSTATUS.DTLGIN bit will be toggled when the transaction
has completed. If a short packet was sent (i.e. the last transaction), MULTI_PACKET_SIZE is incremented by the data
payload. EPSTATUS.BK0/1RDY will be cleared and EPINTFLAG.TRCPT0/1 will be set.
29.6.2.11 Ping-Pong Operation
When an endpoint is configured for ping-pong operation, it uses both the input and output data buffers (banks) for a given
endpoint in a single direction. The direction is selected by enabling one of the IN or OUT direction in EPCFG.EPTYPE0/1
and configuring the opposite direction in EPCFG.EPTYPE1/0 as Dual Bank.
When ping-pong operation is enabled for an endpoint, the endpoint in the opposite direction must be configured as dual
bank. The data buffer, data address pointer and byte counter from the enabled endpoint are used as Bank 0, while the
matching registers from the disabled endpoint are used as Bank 1.
Figure 29-7. Ping-Pong Overview
The Bank Select flag in EPSTATUS.CURBK indicates which bank data will be used in the next transaction, and is
updated after each transaction. According to EPSTATUS.CURBK, EPINTFLAG.TRCPT0 or EPINTFLAG.TRFAIL0 or
EPINTFLAG.TRCPT1 or EPINTFLAG.TRFAIL1 in EPINTFLAG and Data Buffer 0/1 ready (EPSTATUS.BK0RDY and
EPSTATUS.BK1RDY) are set. The EPSTATUS.DTGLOUT and EPSTATUS.DTGLIN are updated for the enabled
endpoint direction only.
29.6.2.12 Feedback Operation
Feedback endpoints are endpoints with same address but in different direction. This is usually used in explicit feedback
mechanism in USB Audio, where a feedback endpoint is associated to one or more isochronous data endpoints to which
it provides feedback service. The feedback endpoint always has the opposite direction from the data endpoint.
The feedback endpoint always has the opposite direction from the data endpoint(s). The feedback endpoint has the
same endpoint number as the first (lower) data endpoint. A feedback endpoint can be created by configuring an endpoint
with different endpoint size (PCKSIZE.SIZE) and different endpoint type (EPCFG.EPTYPE0/1) for the IN and OUT
direction.
Example Configuration for Feedback Operation:
USB data packet
With Ping Pong
Without Ping Pong
Available time for data processing by CPU
to avoid NACK
t
t
Endpoint
single bank
Endpoint
dual bank
Bank0
Bank1
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Endpoint n / IN: EPCFG.EPTYPE1 = Interrupt IN, PCKSIZE.SIZE = 64.
Endpoint n / OUT: EPCFG.EPTYPE0= Isochronous OUT, PCKSIZE.SIZE = 512.
29.6.2.13 Suspend State and Pad Behavior
Figure 29-8
illustrates the behavior of the USB pad in device mode.
Figure 29-8. Pad Behavior
In Idle state, the pad is in low power consumption mode.
In Active state, the pad is active.
Figure 29-9 illustrates the pad events leading to a PAD state change.
Figure 29-9. Pad Events
The Suspend Interrupt bit in the Device Interrupt Flag register (INTFLAG.SUSPEND) is set when a USB Suspend state
has been detected on the USB bus. The USB pad is then automatically put in the Idle state. The detection of a non-idle
state sets the Wake Up Interrupt bit in INTFLAG(INTFLAG.WAKEUP) and wakes the USB pad.
The pad goes to the Idle state if the USB module is disabled or if CTRLB.DETACH is written to one. It returns to the
Active state when CTRLA.ENABLE is written to one and CTRLB.DETACH is written to zero.
29.6.2.14 Remote Wakeup
The remote wakeup request (also known as upstream resume) is the only request the device may send on its own
initiative. This should be preceded by a DEVICE_REMOTE_WAKEUP request from the host.
Idle
Active
CTRLA.ENABLE = 0
| CTRLB.DETACH = 1
| INTFLAG.SUSPEND = 1
CTRLA.ENABLE = 1
| CTRLB.DETACH = 0
| INTFLAG.SUSPEND = 0
SUSPEND
Suspend detected Cleared on Wakeup
Wakeup detected Cleared by software to acknowledge the interrupt
WAKEUP
PAD state
Active
Idle
Active
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First, the USB must have detected a “Suspend” state on the bus, i.e. the remote wakeup request can only be sent after
INTFLAG.SUSPEND has been set.
The user may then write a one to the Remote Wakeup bit in CTRLB(CTRLB.UPRSM) to send an Upstream Resume to
the host initiating the wakeup. This will automatically be done by the controller after 5 ms of inactivity on the USB bus.
When the controller sends the Upstream Resume INTFLAG.WAKEUP is set and INTFLAG.SUSPEND is cleared.
The CTRLB.UPRSM is cleared at the end of the transmitting Upstream Resume.
In case of a rebroadcast resume initiated by the host, the End of Resume bit in INTFLAG(INTFLAG.EORSM) flag is set
when the rebroadcast resume is completed.
In the case where the CTRLB.UPRSM bit is set while a host initiated downstream resume is already started, the
CTRLB.UPRSM is cleared and the upstream resume request is ignored.
29.6.2.15 Link Power Management L1 (LPM-L1) Suspend State Entry and Exit as Device
The LPM Handshake bit in CTRLB.LPMHDSK should be configured to accept the LPM transaction.
When a LPM transaction is received on any enabled endpoint n and a handshake has been sent in response by the
controller according to CTRLB.LPMHDSK, the Device Link Power Manager (EXTREG) register is updated in the bank 0
of the addressed endpoint's descriptor. It contains information such as the Best Effort Service Latency (BESL), the
Remote Wake bit (bRemoteWake), and the Link State parameter (bLinkState).
If the LPM transaction was positively acknowledged (ACK handshake), USB sets the Link Power Management Interrupt
bit in INTFLAG(INTFLAG.LPMSUSP) bit which indicates that the USB transceiver is suspended, reducing power
consumption. This suspend occurs 9 microseconds after the LPM transaction according to the specification.
To further reduce consumption, it is recommended to stop the USB clock while the device is suspended.
The MCU can also enter in one of the available sleep modes if the wakeup time latency of the selected sleep mode
complies with the host latency constraint (see the BESL parameter in EXTREG).
Recovering from this LPM-L1 suspend state is exactly the same as the Suspend state (see Section “Suspend State and
Pad Behavior” on page 713) except that the remote wakeup duration initiated by USB is shorter to comply with the Link
Power Management specification.
If the LPM transaction is responded with a NYET, the Link Power Management Not Yet Interrupt Flag
INTFLAG(INTFLAG.LPMNYET) is set. This generates an interrupt if the Link Power Management Not Yet Interrupt
Enable bit in INTENCLR/SET (INTENCLR/SET.LPMNYET) is set.
If the LPM transaction is responded with a STALL or no handshake, no flag is set, and the transaction is ignored.
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29.6.2.16 USB Device Interrupt
The WAKEUP is an asynchronous interrupt and can be used to wake-up the device from any sleep mode.
EPINTENSET7.TRFAIL0
EPINTFLAG7.TRFAIL0
EPINTENSET7.RXSTP
EPINTFLAG7.RXSTP
EPINTENSET7.TRCPT1
EPINTFLAG7.TRCPT1
EPINTENSET7.TRCPT0
EPINTFLAG7.TRCPT0
EPINT7
EPINTSMRY
EPINTENSET0.TRFAIL0
EPINTFLAG0.TRFAIL0
EPINTENSET0.RXSTP
EPINTFLAG0.RXSTP
EPINTENSET0.TRCPT1
EPINTFLAG0.TRCPT1
EPINTENSET0.TRCPT0
EPINTFLAG0.TRCPT0
EPINT0
EPINT6
EPINT1
ENDPOINT7
ENDPOINT0
USB EndPoint
Interrupt
INTENSET.RAMACER
INTFLAG.RAMACER
INTENSET.DDISC
INTFLAG.LPMNYET
INTENSET.UPRSM
INTFLAG.UPRSM
INTENSET.EORSM
INTFLAG.EORSM
INTENSET.WAKEUP
INTFLAG.WAKEUP *
INTFLAG
INTENSET.EORST
INTFLAG.EORST
INTENSET.SOF
INTFLAG.SOF
INTENSET.MSOF
INTFLAGA.MSOF
USB Device Interrupt
USB
Interrupt
INTENSET.LPMSUSP
INTFLAG.LPMSUSP
INTENSET.SUSPEND
INTFLAG.SUSPEND
* Asynchronous interrupt
EPINTENSET0.TRFAIL1
EPINTFLAG0.TRFAIL1
EPINTENSET7.TRFAIL1
EPINTFLAG7.TRFAIL1
EPINTFLAG0.STALL
EPINTENSET0.STALL0/STALL1
EPINTFLAG7.STALL
EPINTENSET7.STALL0/STALL1
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29.6.3 Host Operations
This section gives an overview of the USB module Host operation during normal transactions. For more details on
general USB and USB protocol, refer to Universal Serial Bus Specification revision 2.1.
29.6.3.1 Device Detection and Disconnection
Prior to device detection the software must set the VBUS is OK bit in CTRLB (CTRLB.VBUSOK) register when the VBUS
is available. This notifies the USB host that USB operations can be started. When the bit CTRLB.VBUSOK is zero and
even if the USB HOST is configured and enabled, host operation is halted. Setting the bit CTRLB.VBUSOK will allow
host operation when the USB is configured.
The Device detection is managed by the software using the Line State field in the Host Status (STATUS.LINESTATE)
register. The device connection is detected by the host controller when DP or DM is pulled high, depending of the speed
of the device.
The device disconnection is detected by the host controller when both DP and DM are pulled down using the
STATUS.LINESTATE registers.
The Device Connection Interrupt bit in INTFLAG (INTFLAG.DCONN) is set if a device connection is detected.
The Device Disconnection Interrupt bit in INTFLAG (INTFLAG.DDISC) is set if a device disconnection is detected.
29.6.3.2 Host Terminology
In host mode, the term pipe is used instead of endpoint. A host pipe corresponds to a device endpoint, refer to "Universal
Serial Bus Specification revision 2.1." for more information.
29.6.3.3 USB Reset
The USB sends a USB reset signal when the user writes a one to the USB Reset bit in CTRLB (CTRLB.BUSRESET).
When the USB reset has been sent, the USB Reset Sent Interrupt bit in the INTFLAG (INTFLAG.RST) is set and all
pipes will be disabled.
If the bus was previously in a suspended state (Start of Frame Generation Enable bit in CTRLB (CTRLB.SOFE) is zero)
the USB will switch it to the Resume state, causing the bus to asynchronously set the Host Wakeup Interrupt flag
(INTFLAG.WAKEUP). The CTRLB.SOFE bit will be set in order to generate SOFs immediately after the USB reset.
During USB reset the following registers are cleared:
zAll Host Pipe Configuration register (PCFG)
zHost Frame Number register (FNUM)
zInterval for the Bulk-Out/Ping transaction register (BINTERVAL)
zHost Start-of-Frame Control register (HSOFC)
zPipe Interrupt Enable Clear/Set register (PINTENCLR/SET)
zPipe Interrupt Flag register (PINTFLAG)
zPipe Freeze bit in Pipe Status register (PSTATUS.FREEZE)
After the reset the user should check the Speed Status field in the Status register (STATUS.SPEED) to find out the
current speed according to the capability of the peripheral.
29.6.3.4 Pipe Configuration
Pipe data can be placed anywhere in the RAM. The USB controller accesses these pipes directly through the AHB
master (built-in DMA) with the help of the pipe descriptors. The base address of the pipe descriptors needs to be written
in the Descriptor Address register (DESCADD) by the user. Please refer the Pipe Descriptor structure in “Pipe Descriptor
Structure” on page 793.
Before using a pipe, the user should configure the direction and type of the pipe in Type of Pipe field in the Host Pipe
Configuration register (PCFG.PTYPE). The pipe descriptor registers should be initialized to known values before using
the pipe, so that the USB controller does not read the random values from the RAM.
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The Pipe Size field in the Packet Size register (PCKSIZE.SIZE) should be configured as per the size reported by the
device for the endpoint associated with this pipe. The Address of Data Buffer register (ADDR) should be set to the data
buffer used for pipe transfers.
The Pipe Bank bit in PCFG (PCFG.BK) should be set to one if dual banking is desired. Dual bank is not supported for
Control pipes.
The Ram Access Interrupt bit in Host Interrupt Flag register (INTFLAG.RAMACER) is set when a RAM access underflow
error occurs during an OUT stage.
When a pipe is disabled, the following registers are cleared for that pipe:
zInterval for the Bulk-Out/Ping transaction register (BINTERVAL)
zPipe Interrupt Enable Clear/Set register (PINTENCLR/SET)
zPipe Interrupt Flag register (PINTFLAG)
zPipe Freeze bit in Pipe Status register (PSTATUS.FREEZE)
29.6.3.5 Pipe Activation
A disabled pipe is inactive, and will be reset along with its context registers (pipe registers for the pipe n). Pipes are
enabled by writing Type of the Pipe in PCFG (PCFG.PTYPE) to a value different than 0x0 (disabled).
When a pipe is enabled, the Pipe Freeze bit in Pipe Status register (PSTATUS.FREEZE) is set. This allow the user to
complete the configuration of the pipe, without starting a USB transfer.
When starting an enumeration, the user retrieves the device descriptor by sending an GET_DESCRIPTOR USB request.
This descriptor contains the maximal packet size of the device default control endpoint (bMaxPacketSize0) which the
user should use to reconfigure the size of the default control pipe.
29.6.3.6 Pipe Address Setup
Once the device has answered the first host requests with the default device address 0, the host assigns a new address
to the device. The host controller has to send a USB reset to the device and a SET_ADDRESS(addr) SETUP request
with the new address to be used by the device. Once this SETUP transaction is complete, the user writes the new
address to the Pipe Device Address field in the Host Control Pipe register (CTRL_PIPE.PDADDR) in Pipe descriptor. All
following requests by this pipe will be performed using this new address.
29.6.3.7 Suspend and Wakeup
Writing CTRLB.SOFE to zero when in host mode will cause the USB to cease sending Start-of-Frames on the USB bus
and enter the Suspend state. The USB device will enter the Suspend state 3ms later.
Before entering suspend by writing CTRLB.SOFE to zero, the user must freeze the active pipes by setting their
PSTATUS.FREEZE bit. Any current on-going pipe will complete its transaction, and then all pipes will be inactive. The
user should wait at least 1 complete frame before entering the suspend mode to avoid any data loss.
The device can awaken the host by sending an Upstream Resume (Remote Wakeup feature). When the host detects a
non-idle state on the USB bus, it sets the INTFLAG.WAKEUP. If the non-idle bus state corresponds to an Upstream
Resume (K state), the Upstream Resume Received Interrupt bit in INTFLAG (INTFLAG.UPRSM) is set and the user
must generate a Downstream Resume within 1 ms and for at least 20 ms. It is required to first write a one to the Send
USB Resume bit in CTRLB (CTRLB.RESUME) to respond to the upstream resume with a downstream resume.
Alternatively, the host can resume from a suspend state by sending a Downstream Resume on the USB bus
(CTRLB.RESUME set to 1). In both cases, when the downstream resume is completed, the CTRLB.SOFE bit is
automatically set and the host enters again the active state.
29.6.3.8 Phase-locked SOFs
To support the Synchronous Endpoints capability, the period of the emitted Start-of-Frame is maintained while the USB
connection is not in the active state. This does not apply for the disconnected/connected/reset states. It applies for
active/idle/suspend/resume states. The period of Start-of-Frame will be 1ms when the USB connection is in active state
and an integer number of milli-seconds across idle/suspend/resume states.
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To ensure the Synchronous Endpoints capability, the GCLK_USB clock must be kept running. If the GCLK_USB is
interrupted, the period of the emitted Start-of-Frame will be erratic.
29.6.3.9 Management of Control Pipes
A control transaction is composed of three stages:
zSETUP
zData (IN or OUT)
zStatus (IN or OUT)
The user has to change the pipe token according to each stage using the Pipe Token field in PCFG (PCFG.PTOKEN).
For control pipes only, the token is assigned a specific initial data toggle sequence:
zSETUP: Data0
zIN: Data1
zOUT: Data1
29.6.3.10 Management of IN Pipes
IN packets are sent by the USB device controller upon IN request reception from the host. All the received data from the
device to the host will be stored in the bank provided the bank is empty. The pipe and its descriptor in RAM must be
configured.
The host indicates it is able to receive data from the device by clearing the Bank 0/1 Ready bit in PSTATUS
(PSTATUS.BK0/1RDY), which means that the memory for the bank is available for new USB transfer.
The USB will perform IN requests as long as the pipe is not frozen by the user.
The generation of IN requests starts when the pipe is unfrozen (PSTATUS.PFREEZE is set to zero).
When the current bank is full, the Transmit Complete 0/1 bit in PINTFLAG (PINTFLAG.TRCPT0/1) will be set and trigger
an interrupt if enabled and the PSTATUS.BK0/1RDY bit will be set.
PINTFLAG.TRCPT0/1 must be cleared by software to acknowledge the interrupt. This is done by writing a one to the
PINTFLAG.TRCPT0/1 of the addressed pipe.
The user reads the PCKSIZE.BYTE_COUNT to know how many bytes should be read.
To free the bank the user must read the IN data from the address ADDR in the pipe descriptor and clear the
PKSTATUS.BK0/1RDY bit. When the IN pipe is composed of multiple banks, a successful IN transaction will switch to
the next bank. Another IN request will be performed by the host as long as the PSTATUS.BK0/1RDY bit for that bank is
set. The PINTFLAG.TRCPT0/1 and PSTATUS.BK0/1RDY will be updated accordingly.
The user can follow the current bank looking at Current Bank bit in PSTATUS (PSTATUS.CURBK) and by looking at
Data Toggle for IN pipe bit in PSTATUS (PSTATUS.DTGLIN).
When the pipe is configured as single bank (Pipe Bank bit in PCFG (PCFG.BK) is 0), only PINTFLAG.TRCPT0 and
PSTATUS.BK0 are used. When the pipe is configured as dual bank (PCFG.BK is 1), both PINTFLAG.TRCPT0/1 and
PSTATUS.BK0/1 are used.
29.6.3.11 Management of OUT Pipes
OUT packets are sent by the host. All the data stored in the bank will be sent to the device provided the bank is filled. The
pipe and its descriptor in RAM must be configured.
The host can send data to the device by writing to the data bank 0 in single bank or the data bank 0/1 in dual bank.
The generation of OUT packet starts when the pipe is unfrozen (PSTATUS.PFREEZE is zero).
The user writes the OUT data to the data buffer pointer by ADDR in the pipe descriptor and allows the USB to send the
data by writing a one to the PSTATUS.BK0/1RDY. This will also cause a switch to the next bank if the OUT pipe is part of
a dual bank configuration.
PINTFLAGn.TRCPT0/1 must be cleared before setting PSTATUS.BK0/1RDY to avoid missing an
PINTFLAGn.TRCPT0/1 event.
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29.6.3.12 Alternate Pipe
The user has the possibility to run sequentially several logical pipes on the same physical pipe. It allows addressing of
any device endpoint of any attached device on the bus.
Before switching pipe, the user should save the pipe context (Pipe registers and descriptor for pipe n).
After switching pipe, the user should restore the pipe context (Pipe registers and descriptor for pipe n) and in particular
PCFG, and PSTATUS.
29.6.3.13 Data Flow Error
This error exists only for isochronous and interrupt pipes for both IN and OUT directions. It sets the Transmit Fail bit in
PINTFLAG (PINTFLAG.TRFAIL), which triggers an interrupt if the Transmit Fail bit in
PINTENCLR/SET(PINTENCLR/SET.TRFAIL) is set. The user must check the Pipe Interrupt Summary register
(PINTSMRY) to find out the pipe which triggered the interrupt.Then the user must check the origin of the interrupt’s bank
by looking at the Pipe Bank Status register (STATUS_BK) for each bank. If the Error Flow bit in the STATUS_BK
(STATUS_BK.ERRORFLOW) is set then the user is able to determine the origin of the data flow error. As the user knows
that the endpoint is an IN or OUT the error flow can be deduced as OUT underflow or as an IN overflow.
An underflow can occur during an OUT stage if the host attempts to send data from an empty bank. If a new transaction
is successful, the relevant bank descriptor STATUS_BK.ERRORFLOW will be cleared.
An overflow can occur during an IN stage if the device tries to send a packet while the bank is full. Typically this occurs
when a CPU is not fast enough. The packet data is not written to the bank and is lost. If a new transaction is successful,
the relevant bank descriptor STATUS_BK.ERRORFLOW will be cleared.
29.6.3.14 CRC Error
This error exists only for isochronous IN pipes. It sets the PINTFLAG.TRFAIL, which triggers an interrupt if
PINTENCLR/SET.TRFAIL is set. The user must check the PINTSMRY to find out the pipe which triggered the interrupt.
Then the user must check the origin of the interrupt’s bank by looking at the bank descriptor STATUS_BK for each bank
and if the CRC Error bit in STATUS_BK (STATUS_BK.CRCERR) is set then the user is able to determine the origin of
the CRC error. A CRC error can occur during the IN stage if the USB detects a corrupted packet. The IN packet will
remain stored in the bank and PINTFLAG.TRCPT0/1 will be set.
29.6.3.15 PERR Error
This error exists for all pipes. It sets the PINTFLAG.PERR Interrupt, which triggers an interrupt if PINTFLAG.PERR is set.
The user must check the PINTSMRY register to find out the pipe which can cause an interrupt.
A PERR error occurs if one of the error field in the STATUS_PIPE register in the Host pipe descriptor is set and the Error
Count field in STATUS_PIPE (STATUS_PIPE.ERCNT) exceeds the maximum allowed number of Pipe error(s) as
defined in Pipe Error Max Number field in CTRL_PIPE (CTRL_PIPE.PERMAX). Refer to section STATUS_PIPE.
If one of the error field in the STATUS_PIPE register from the Host Pipe Descriptor is set and the STATUS_PIPE.ERCNT
is less than the CTRL_PIPE.PERMAX, the STATUS_PIPE.ERCNT is incremented.
29.6.3.16 Link Power Management L1 (LPM-L1) Suspend State Entry and Exit as Host.
An EXTENDED LPM transaction can be transmitted by any enabled pipe. The PCFGn.PTYPE should be set to
EXTENDED. Other fields as PCFG.PTOKEN, PCFG.BK PCKSIZE.SIZE are irrelevant in this configuration. The user
should also set the EXTREG.VARIABLE in the descriptor as described in EXTREG.
When the pipe is configured and enabled, an EXTENDED TOKEN followed by a LPM TOKEN are transmitted. The
device responds with a valid HANDSHAKE, corrupted HANDSHAKE or no HANDSHAKE (TIME-OUT).
If the valid HANDSHAKE is an ACK, the host will immediately proceed to L1 SLEEP and the PINTFLAG.TRCT0 is set.
The minimum duration of the L1 SLEEP state will be the TL1RetryAndResidency as defined in the reference document
"ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum". When entering the L1 SLEEP state,
the CTRLB.SOFE is cleared, avoiding Start-of-Frame generation.
If the valid HANDSHAKE is a NYET PINTFLAG.TRFAIL is set.
If the valid HANDSHAKE is a STALL the PINTFLAG.STALL is set.
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If there is no HANDSHAKE or corrupted HANDSHAKE, the EXTENDED/LPM pair of TOKENS will be transmitted again
until reaching the maximum number of retries as defined by the CTRL_PIPE.PERMAX in the pipe descriptor.
If the last retry returns no valid HANDSHAKE, the PINTFLAGn.PERR is set, and the STATUS_BK is updated in the pipe
descriptor.
All LPM transactions, should they end up with a ACK, a NYET, a STALL or a PERR, will set the PSTATUS.PFREEZE bit,
freezing the pipe before a succeeding operation. The user should unfreeze the pipe to start a new LPM transaction.
To exit the L1 STATE, the user initiate a DOWNSTREAM RESUME by setting the bit CTRLB.RESUME or a L1 RESUME
by setting the Send L1 Resume bit in CTRLB (CTRLB.L1RESUME). In the case of a L1 RESUME, the K STATE duration
is given by the BESL bit field in the EXTREG.VARIABLE field. See EXTREG.
When the host is in the L1 SLEEP state after a successful LPM transmitted, the device can initiate an UPSTREAM
RESUME. This will set the Upstream Resume Interrupt bit in INTFLAG (INTFLAG.UPRSM). The host should proceed
then to a L1 RESUME as described above.
After resuming from the L1 SLEEP state, the bit CTRLB.SOFE is set, allowing Start-of-Frame generation.
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29.6.3.17 Host Interrupt
The WAKEUP is an asynchronous interrupt and can be used to wake-up the device from any sleep mode.
PINTENSET.TRFAIL
PINTFLAG7.TRFAIL
PINTENSET.PERR
PINTFLAG7.PERR
PINTENSET.TXSTP
PINTFLAG7.TXSTP
PINTENSET.TRCPT1
PINTFLAG7.TRCPT1
PINTENSET.TRCPT0
PINTFLAG7.TRCPT0
PINT7
PINTSMRY
PINTENSET.TRFAIL
PINTFLAG0.TRFAIL
PINTENSET.PERR
PINTFLAG0.PERR
PINTENSET.TXSTP
PINTFLAG0.TXSTP
PINTENSET.TRCPT1
PINTFLAG0.TRCPT1
PINTENSET.TRCPT0
PINTFLAG0.TRCPT0
PINT0
PINT6
PINT1
PIPE7
PIPE0
USB PIPE
Interrupt
INTENSET.DCONN
INTFLAG.DCONN *
INTENSET.DDISC
INTFLAG.DDISC *
INTENSET.RAMACER
INTFLAG.RAMACER
INTENSET.UPRSM
INTFLAG.UPRSM
INTENSET.DNRSM
INTFLAG.DNRSM
INTFLAG
INTENSET.WAKEUP
INTFLAG.WAKEUP *
INTENSET.RST
INTFLAG.RST
INTENSET.HSOF
INTFLAG.HSOF
USB Host Interrupt
USB
Interrupt
* Asynchronous interrupt
PINTFLAG7.STALL
PINTENSET.STALL
PINTFLAG0.STALL
PINTENSET.STALL
29.7 Register Summary
The register mapping depends on the Operating Mode field in the Control A register (CTRLA.MODE). The
register summary is detailed below.
29.7.1 Common Device Host Summary
Table 29-1. Common Register Summary
29.7.2 Device Summary
Table 29-2. General Device Registers Summary
Offset Name
Bit
Pos.
0x00 CTRLA 7:0 MODE RUNSTBY ENABLE SWRST
0x01 Reserved
0x02 SYNCBUSY 7:0 ENABLE SWRST
0x03 QOSCTRL 7:0 DQOS[1:0] CQOS[1:0]
0x0D FSMSTATUS 7:0 FSMSTATE[6:0]
0x24
DESCADD
7:0 DESCADD[7:0]
0x25 15:8 DESCADD[15:8]
0x26 23:16 DESCADD[23:16]
0x27 31:24 DESCADD[31:24]
0x28
PADCAL
7:0 TRANSN[1:0] TRANSP[4:0]
0x29 15:8 TRIM[2:0] TRANSN[4:2]
Offset Name
Bit
Pos.
0x04 Reserved
0x05 Reserved
0x06 Reserved
0x07 Reserved
0x08
CTRLB
7:0 NREPLY SPDCONF[1:0] UPRSM DETACH
0x09 15:8 LPMHDSK[1:0] GNAK
0x0A DADD ADDEN DADD[6:0]
0x0B Reserved
0x0C STATUS 7:0 LINESTATE[1:0] SPEED[1:0]
0x0E Reserved
0x0F Reserved
0x10
FNUM
7:0 FNUM[4:0]
0x11 15:8 FNCERR FNUM[10:5]
0x12 Reserved
0x14
INTENCLR
7:0 RAMACER UPRSM EORSM WAKEUP EORST SOF SUSPEND
0x15 15:8 LPMSUSP LPMNYET
0x16 Reserved
0x17 Reserved
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Table 29-3. Device endpoint Register n
0x18
INTENSET
7:0 RAMACER UPRSM EORSM WAKEUP EORST SOF SUSPEND
0x19 15:8 LPMSUSP LPMNYET
0x1A Reserved
0x1B Reserved
0x1C
INTFLAG
7:0 RAMACER UPRSM EORSM WAKEUP EORST SOF SUSPEND
0x1D 15:8 LPMSUSP LPMNYET
0x1E Reserved
0x1F Reserved
0x20
EPINTSMRY
7:0 EPINT[7:0]
0x21 15:8 EPINT[15:8]
0x22 Reserved
0x23 Reserved
Offset Name
Bit
Pos.
0x1m0 EPCFGx 7:0 EPTYPE1[1:0] EPTYPE0[1:0]
0x1m1 Reserved
0x1m2 Reserved
0x1m3 Reserved
0x1m4 EPSTATUSCLR 7:0 BK1RDY BK0RDY STALLRQ1 STALLRQ0 CURBK DTGLIN DTGLOUT
0x1m5 EPSTATUSSET 7:0 BK1RDY BK0RDY STALLRQ1 STALLRQ0 CURBK DTGLIN DTGLOUT
0x1m6 EPSTATUS 7:0 BK1RDY BK0RDY STALLRQ1 STALLRQ0 CURBK DTGLIN DTGLOUT
0x1m7 EPINTFLAG 7:0 STALL1 STALL0 RXSTP TRFAIL1 TRFAIL0 TRCPT1 TRCPT0
0x1m8 EPINTENCLR 7:0 STALL1 STALL0 RXSTP TRFAIL1 TRFAIL0 TRCPT1 TRCPT0
0x1m9 EPINTENSET 7:0 STALL1 STALL0 RXSTP TRFAIL1 TRFAIL0 TRCPT1 TRCPT0
0x1mA Reserved
0x1mB Reserved
Offset Name
Bit
Pos.
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Table 29-4. Device endpoint n Descriptor Bank 0
Offset
0x n0 +
index Name
Bit
Pos.
0x00
ADDR
7:0 ADD[7:0]
0x01 15:8 ADD[15:8]
0x02 23:16 ADD[23:16]
0x03 31:24 ADD[31:24]
0x04
PCKSIZE
7:0 BYTE_COUNT[7:0]
0x05 15:8 MULTI_PACKET_SIZE[1:0] BYTE_COUNT[13:8]
0x06 23:16 MULTI_PACKET_SIZE[9:2]
0x07 31:24 AUTO_ZLP SIZE[2:0] MULTI_PACKET_SIZE[13:10]
0x08 EXTREG 7:0 VARIABLE[3:0] SUBPID[3:0]
0x09 15:8 VARIABLE[10:4]
0x0A STATUS_BK 7:0 ERRORFLOW CRCERR
0x0B Reserved 7:0
0x0C Reserved 7:0
0x0D Reserved 7:0
0x0E Reserved 7:0
0x0F Reserved 7:0
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Table 29-5. Device endpoint n Descriptor Bank 1
Offset
0x n0 +
0x10 +
index Name
Bit
Pos.
0x00
ADDR
7:0 ADD[7:0]
0x01 15:8 ADD[15:8]
0x02 23:16 ADD[23:16]
0x03 31:24 ADD[31:24]
0x04
PCKSIZE
7:0 BYTE_COUNT[7:0]
0x05 15:8 MULTI_PACKET_SIZE[1:0] BYTE_COUNT[13:8]
0x06 23:16 MULTI_PACKET_SIZE[9:2]
0x07 31:24 AUTO_ZLP SIZE[2:0] MULTI_PACKET_SIZE[13:10]
0x08 Reserved 7:0
0x09 Reserved 15:8
0x0A STATUS_BK 7:0 ERRORFLOW CRCERR
0x0B Reserved 7:0
0x0C Reserved 7:0
0x0D Reserved 7:0
0x0E Reserved 7:0
0x0F Reserved 7:0
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29.7.3 Host Summary
Table 29-6. General Host Registers Summary
Offset Name
Bit
Pos.
0x04 Reserved
0x05 Reserved
0x06 Reserved
0x07 Reserved
0x08
CTRLB
7:0 TSTK TSTJ SPDCONF[1:0] RESUME
0x09 15:8 L1RESUME VBUSOK BUSRESET SOFE
0x0A HSOFC 7:0 FLENCE FLENC[3:0]
0x0B Reserved
0x0C STATUS 7:0 LINESTATE[1:0] SPEED[1:0]
0x0E Reserved
0x0F Reserved
0x10
FNUM
7:0 FNUM[4:0]
0x11 15:8 FNUM[10:5]
0x12 FLENHIGH 7:0 FLENHIGH[7:0]
0x14
INTENCLR
7:0 RAMACER UPRSM DNRSM WAKEUP RST HSOF
0x15 15:8 DDISC DCONN
0x16 Reserved
0x17 Reserved
0x18
INTENSET
7:0 RAMACER UPRSM DNRSM WAKEUP RST HSOF
0x19 15:8 DDISC DCONN
0x1A Reserved
0x1B Reserved
0x1C
INTFLAG
7:0 RAMACER UPRSM DNRSM WAKEUP RST HSOF
0x1D 15:8 DDISC DCONN
0x1E Reserved
0x1F Reserved
0x20
PINTSMRY
7:0 PINT[7:0]
0x21 15:8 PINT[15:8]
0x22 Reserved
0x23
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Table 29-7. Host pipe Register n
Offset Name
Bit
Pos.
0x1m0 PCFGn 7:0 PTYPE[2:0] BK PTOKEN[1:0]
0x1m1 Reserved
0x1m2 Reserved
0x1m3 BINTERVAL 7:0 BINTERVAL[7:0]
0x1m4 PSTATUSCLR 7:0 BK1RDY BK0RDY PFREEZE CURBK DTGL
0x1m5 PSTATUSSET 7:0 BK1RDY BK0RDY PFREEZE CURBK DTGL
0x1m6 PSTATUS 7:0 BK1RDY BK0RDY PFREEZE CURBK DTGL
0x1m7 PINTFLAG 7:0 STALL TXSTP PERR TRFAIL TRCPT1 TRCPT0
0x1m8 PINTENCLR 7:0 STALL TXSTP PERR TRFAIL TRCPT1 TRCPT0
0x1m9 PINTENSET 7:0 STALL TXSTP PERR TRFAIL TRCPT1 TRCPT0
0x1mA Reserved
0x1mB Reserved
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Table 29-8. Host pipe n Descriptor Bank 0
Offset
0x n0 +
index Name
Bit
Pos.
0x00
ADDR
7:0 ADD[7:0]
0x01 15:8 ADD[15:8]
0x02 23:16 ADD[23:16]
0x03 31:24 ADD[31:24]
0x04
PCKSIZE
7:0 BYTE_COUNT[7:0]
0x05 15:8 MULTI_PACKET_SIZE[1:0] BYTE_COUNT[13:8]
0x06 23:16 MULTI_PACKET_SIZE[9:2]
0x07 31:24 AUTO_ZLP SIZE[2:0] MULTI_PACKET_SIZE[13:10]
0x08
EXTREG
7:0 VARIABLE[3:0] SUBPID[3:0]
0x09 15:8 VARIABLE[10:4]
0x0A STATUS_BK 7:0 ERRORFLOW CRCERR
0x0B 15:8
0x0C
CTRL_PIPE
7:0 PDADDR[6:0]
0x0D 15:8 PEPMAX[3:0] PEPNUM[3:0]
0x0E STATUS_PIP
E
7:0 ERCNT[2:0] CRC16ER TOUTER PIDER DAPIDER DTGLER
0x0F 15:8
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Table 29-9. Host pipe n Descriptor Bank 1
Offset
0x n0
+0x10
+index Name
Bit
Pos.
0x00
ADDR
7:0 ADD[7:0]
0x01 15:8 ADD[15:8]
0x02 23:16 ADD[23:16]
0x03 31:24 ADD[31:24]
0x04
PCKSIZE
7:0 BYTE_COUNT[7:0]
0x05 15:8 MULTI_PACKET_SIZE[1:0 BYTE_COUNT[13:8]
0x06 23:16 MULTI_PACKET_SIZE[9:2]
0x07 31:24 AUTO_ZLP SIZE[2:0] MULTI_PACKET_SIZE[13:10]
0x08 7:0
0x09 15:8
0x0A STATUS_BK 7:0 ERRORFLOW CRCERR
0x0B 15:8
0x0C 7:0
0x0D 15:8
0x0E
STATUS_PIPE
7:0 ERCNT[2:0] CRC16ER TOUTER PIDER DAPIDER DTGLER
0x0F 15:8
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29.8 Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters
and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by
Write-Protected property in each individual register description. Please refer to the “Register Access Protection” on page
704 section and the “PAC – Peripheral Access Controller” on page 36 for details.
Some registers require synchronization when read and/or written. Synchronization is denoted by the Write-Synchronized
or the Read-Synchronized property in each individual register description. Refer to “Synchronization” on page 96 for
details.
Some registers are enable-protected, meaning they can only be written when the USB is disabled. Enable-protection is
denoted by the Enable-Protected property in each individual register description.
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29.8.1 Common Device Host Registers
29.8.1.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x0000
Property: Write-Protected, Write-Synchronised
zBit 7– MODE: Operating Mode
This bit defines the operating mode of the USB.
0: USB Device mode
1: USB Host mode
zBits 6:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 2 – RUNSDTBY: Run in Standby Mode
0: USB clock is stopped in standby mode.
1: USB clock is running in standby mode
This bit is Enable-Protected.
zBit 1 – ENABLE: Enable
0: The peripheral is disabled or being disabled.
1: The peripheral is enabled or being enabled.
Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRLA.ENABLE will read back immediately and the Synchronization status enable bit in the syn-
chronization register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation
is complete.
This bit is Write-Synchronized
zBit 0 – SWRST: Software Reset
0: There is no reset operation ongoing.
1: The reset operation is ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the USB, to their initial state, and the USB will be disabled.
Writing a one to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-oper-
ation will be discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST
and SYNCBUSY.SWRST will both be cleared when the reset is complete.
This bit is Write-Synchronized.
Bit76543210
MODE RUNSTBY ENABLE SWRST
Access R/W R R R R R/W R/W R/W
Reset00000000
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29.8.1.2 Synchronization Busy
Name: SYNCBUSY
Offset: 0x02
Reset: 0x0000
Property: -
zBits 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 1 – ENABLE: Synchronization Enable status bit
This bit is cleared when the synchronization of ENABLE register between the clock domains is complete.
This bit is set when the synchronization of ENABLE register between clock domains is started.
zBit 0 – SWRST: Synchronization Software Reset status bit
This bit is cleared when the synchronization of SWRST register between the clock domains is complete.
This bit is set when the synchronization of SWRST register between clock domains is started.
Bit76543210
ENABLE SWRST
AccessRRRRRRRR
Reset00000000
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29.8.1.3 QOS Control
Name: QOSCTRL
Offset: 0x03
Reset: 0x00
Property: Write-Protected
zBits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 3:2 –DQOS[1:0]: Data Quality of Service
These bits define the memory priority access during the endpoint or pipe read/write data operation.Refer to “SRAM
Quality of Service” on page 34.
zBits 1:0 – CQOS[1:0]: Configuration Quality of Service
These bits define the memory priority access during the endpoint or pipe read/write configuration operation.Refer
to “SRAM Quality of Service” on page 34.
Bit76543210
DQOS[1:0] CQOS[1:0]
Access R R R R R/W R/W R/W R/W
Reset00000101
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29.8.1.4 Finite State Machine Status
Name: FSMSTATUS
Offset: 0x0D
Reset: 0xXXXX
Property: Read only
zBits 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 6:0 – FSMSTATE[6:0]: Fine State Machine Status
These bits indicate the state of the finite state machine of the USB controller.
Bit76543210
FSMSTATE[6:0]
AccessRRRRRRRR
Reset00000001
FSMSTATE[6:0] Description
0x01 OFF (L3). Corresponds to the powered-off, disconnected, and disabled state
0x02 ON (L0). Corresponds to the Idle and Active states
0x04 SUSPEND (L2)
0x08 SLEEP (L1)
0x10 DNRESUME. Down Stream Resume.
0x20 UPRESUME. Up Stream Resume.
0x40 RESET. USB lines Reset.
Others Reserved
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29.8.1.5 Descriptor Address
Name: DESCADD
Offset: 0x24
Reset: 0x00000000
Property: Write-Protected
zBits 31:0 – DESCADD[31:0]: Descriptor Address Value
These bits define the base address of the main USB descriptor in RAM. The two least significant bits must be writ-
ten to zero.
Bit3130292827262524
+3 DESCADD[31:24]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
Bit2322212019181716
+2 DESCADD[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
Bit151413121110 9 8
+1 DESCADD[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
Bit76543210
+0 DESCADD[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
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29.8.1.6 Pad Calibration
Name: PADCAL
Offset: 0x28
Reset: 0x0000
Property: Write-Protected
The Pad Calibration values must be loaded from the NVM Software Calibration Area into the USB Pad Calibration
register by software, before enabling the USB, to achieve the specified accuracy. Refer to “NVM Software Calibration
Area Mapping” on page 26 for further details.
zBit 15 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 14:12 – TRIM: Trim bits for DP/DM
These bits calibrate the matching of rise/fall of DP/DM.
zBit 11 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 10:6 – TRANSN: Trimmable Output Driver Impedance N
These bits calibrate the NMOS output impedance of DP/DM drivers.
zBit 5 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 4:0 – TRANSP: Trimmable Output Driver Impedance P
These bits calibrate the PMOS output impedance of DP/DM drivers.
Bit151413121110 9 8
TRIM[2:0] TRANSN[4:2]
Access R R/W R/W R/W R R/W R/W R/W
Reset00000000
Bit76543210
TRANSN[1:0] TRANSP[4:0]
Access R/W R/W R R/W R/W R/W R/W R/W
Reset00000000
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29.8.2 Device Registers - Common
29.8.2.1 Control B
Name: CTRLB
Offset: 0x08
Reset: 0x0001
Property: Write-Protected
zBits 15:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 11:10 – LPMHDSK[1:0]: Link Power Management Handshake
These bits select the Link Power Management Handshake configuration as shown in Table 29-10.
Table 29-10. LPMHDSK Selection
zBit 9 – GNAK: Global NAK
This bit configures the operating mode of the NAK.
0: The handshake packet reports the status of the USB transaction
1: A NAK handshake is answered for each USB transaction regardless of the current endpoint memory bank
status
This bit is not synchronized.
zBits 8:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 4 – NREPLY: No reply excepted SETUP Token
0: Disable the “NO_REPLY” feature: Any transaction to endpoint 0 will be handled according to the USB2.0
standard.
1: Enable the “NO_REPLY” feature: Any transaction to endpoint 0 will be ignored except SETUP.
This bit is cleared by hardware when receiving a SETUP packet.
Bits 15 14 13 12 11 10 9 8
LPMHD[1:0] GNAK
AccessRRRRR/WR/WR/WR/
Reset00000000
Bits76543210
NREPLY SPDCONF[1:0] UPRSM DETACH
AccessRRRRR/WR/WR/WR/W
Reset00000000
LPMHDSK[1:0] Description
0x0 No handshake. LPM is not supported
0x1 ACK
0x2 NYET
0x3 Reserved
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This bit has no effect for any other endpoint but endpoint 0.
zBits 3:2 – : Speed Configuration
These bits select the speed configuration as shown in Table 29-11.
zBit 1 – UPRSM: Upstream Resume
0: Writing a zero to this bit has no effect.
1: Writing a one to this bit will generate an upstream resume to the host for a remote wakeup.
This bit is cleared when the USB receives a USB reset or once the upstream resume has been sent.
zBit 0 – DETACH: Detach
0: The device is attached to the USB bus so that communications may occur.
1: It is the default value at reset. The internal device pull-ups are disabled, removing the device from the USB bus.
Table 29-11. SPDCONF Selection
SPDCONF [1:0] Description
0x0 FS: Full speed
0x1 LS: Low Speed
0x2 Reserved
0x3 Reserved
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29.8.2.2 Device Address
Name: DADD
Offset: 0x0A
Reset: 0x00
Property: Write-Protected
zBit 7 – ADDEN: Device Address Enable
0: Writing a zero will deactivate the DADD field (USB device address) and return the device to default address 0.
1: Writing a one will activate the DADD field (USB device address).
This bit is cleared when a USB reset is received.
zBits 6:0 – DADD: Device Address
These bits define the device address. The DADD register is reset when a USB reset is received.
Bit76543210
ADDEN DADD[6:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
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29.8.2.3 Status
Name: STATUS
Offset: 0x0C
Reset: 0x0000
Property: -
zBits 7:6 – LINESTATE[1:0]: USB Line State Status
These bits define the current line state DP/DM as showed in Table 29-12.
zBits 5:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 3:2 – SPEED [1:0]: Speed Status
These bits define the current speed used of the device
.
zBits 1:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit76543210
LINESTATE[1:0] SPEED[1:0]
AccessRRRRRRRR
Reset01000100
Table 29-12. USB Line State Status
LINESTATE[1:0] USB Line Status
0x0 SE0/RESET
0x1 FS-J or LS-K State
0x2 FS-K or LS-J State
Table 29-13. Speed Status
SPEED[1:0] SPEED STATUS
0x0 Low-speed mode
0x1 Full-speed mode
0x2 Reserved
0x3 Reserved
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29.8.2.4 Device Frame Number
Name: FNUM
Offset: 0x10
Reset: 0x0000
Property: Read only
zBit 15 – FNCERR: Frame Number CRC Error
This bit is cleared upon receiving a USB reset.
This bit is set when a corrupted frame number (or micro-frame number) is received.
This bit and the SOF (or MSOF) interrupt bit are updated at the same time.
zBit 14 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 13:3 – FNUM: Frame Number
These bits are cleared upon receiving a USB reset.
These bits are updated with the frame number information as provided from the last SOF packet even if a cor-
rupted SOF is received.
zBits 2:0 – MFNUM: Micro Frame Number
These bits are cleared upon receiving a USB reset or at the beginning of each Start-of-Frame (SOF interrupt).
These bits are updated with the micro-frame number information as provided from the last MSOF packet even if a
corrupted MSOF is received.
Bit151413121110 9 8
FNCERR FNUM[10:5]
AccessRRRRRRRR
Reset00000000
Bit76543210
FNUM[4:0] MFNUM[2:0]
AccessRRRRRRRR
Reset00000000
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29.8.2.5 Device Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set (INTENSET) register.
Name: INTENCLR
Offset: 0x14
Reset: 0x0000
Property: Write-Protected
zBits 15:10 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 9 – LPMSUSP: Link Power Management Suspend Interrupt Enable
0: The Link Power Management Suspend interrupt is disabled.
1: The Link Power Management Suspend interrupt is enabled and an interrupt request will be generated when the
Link Power Management Suspend interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Link Power Management Suspend Interrupt Enable bit and disable the corre-
sponding interrupt request.
zBit 8 – LPMNYET: Link Power Management Not Yet Interrupt Enable
0: The Link Power Management Not Yet interrupt is disabled.
1: The Link Power Management Not Yet interrupt is enabled and an interrupt request will be generated when the
Link Power Management Not Yet interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Link Power Management Not Yet interrupt Enable bit and disable the corre-
sponding interrupt request.
zBit 7 – RAMACER: RAM Access Interrupt Enable
0: The RAM Access interrupt is disabled.
1: The RAM Access interrupt is enabled and an interrupt request will be generated when the RAM Access interrupt
Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the RAM Access interrupt Enable bit and disable the corresponding interrupt
request.
zBit 6 – UPRSM: Upstream Resume Interrupt Enable
0: The Upstream Resume interrupt is disabled.
Bit151413121110 9 8
LPMSUSP LPMNYET
AccessRRRRRRR/WR/W
Reset00000000
Bit76543210
RAMACER UPRSM EORSM WAKEUP EORST SOF SUSPEND
Access R/W R/W R/W R/W R/W R/W R R/W
Reset00000000
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1: The Upstream Resume interrupt is enabled and an interrupt request will be generated when the Upstream
Resume interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Upstream Resume interrupt Enable bit and disable the corresponding inter-
rupt request.
zBit 5 – EORSM: End Of Resume Interrupt Enable
0: The End Of Resume interrupt is disabled.
1: The End Of Resume interrupt is enabled and an interrupt request will be generated when the End Of Resume
interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the End Of Resume interrupt Enable bit and disable the corresponding interrupt
request.
zBit 4 – WAKEUP: Wake-Up Interrupt Enable
0: The Wake Up interrupt is disabled.
1: The Wake Up interrupt is enabled and an interrupt request will be generated when the Wake Up interrupt Flag is
set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Wake Up interrupt Enable bit and disable the corresponding interrupt request.
zBit 3 – EORST: End of Reset Interrupt Enable
0: The End of Reset interrupt is disabled.
1: The End of Reset interrupt is enabled and an interrupt request will be generated when the End of Reset interrupt
Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the End of Reset interrupt Enable bit and disable the corresponding interrupt
request.
zBit 2 – SOF: Start-of-Frame Interrupt Enable
0: The Start-of-Frame interrupt is disabled.
1: The Start-of-Frame interrupt is enabled and an interrupt request will be generated when the Start-of-Frame
interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Start-of-Frame interrupt Enable bit and disable the corresponding interrupt
request.
zBit 1 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 0– SUSPEND: Suspend Interrupt Enable
0: The Suspend interrupt is disabled.
1: The Suspend interrupt is enabled and an interrupt request will be generated when the Suspend interrupt Flag is
set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Suspend Interrupt Enable bit and disable the corresponding interrupt request.
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29.8.2.6 Device Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Name: INTENSET
Offset: 0x18
Reset: 0x0000
Property: Write-Protected
zBits 15:10 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 9 – LPMSUSP: Link Power Management Suspend Interrupt Enable
0: The Link Power Management Suspend interrupt is disabled.
1: The Link Power Management Suspend interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Link Power Management Suspend Enable bit and enable the corresponding
interrupt request.
zBit 8 – LPMNYET: Link Power Management Not Yet Interrupt Enable
0: The Link Power Management Not Yet interrupt is disabled.
1: The Link Power Management Not Yet interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Link Power Management Not Yet interrupt bit and enable the corresponding
interrupt request.
zBit 7 – RAMACER: RAM Access Interrupt Enable
0: The RAM Access interrupt is disabled.
1: The RAM Access interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the RAM Access Enable bit and enable the corresponding interrupt request.
zBit 6 – UPRSM: Upstream Resume Interrupt Enable
0: The Upstream Resume interrupt is disabled.
1: The Upstream Resume interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Upstream Resume Enable bit and enable the corresponding interrupt request.
zBit 5 – EORSM: End Of Resume Interrupt Enable
0: The End Of Resume interrupt is disabled.
Bit151413121110 9 8
LPMSUSP LPMNYET
AccessRRRRRRR/WR/W
Reset00000000
Bit76543210
RAMACER UPRSM EORSM WAKEUP EORST SOF SUSPEND
Access R/W R/W R/W R/W R/W R/W R R/W
Reset00000000
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1: The End Of Resume interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the End Of Resume interrupt Enable bit and enable the corresponding interrupt
request.
zBit 4 – WAKEUP: Wake-Up Interrupt Enable
0: The Wake Up interrupt is disabled.
1: The Wake Up interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Wake Up interrupt Enable bit and enable the corresponding interrupt request.
zBit 3 – EORST: End of Reset Interrupt Enable
0: The End of Reset interrupt is disabled.
1: The End of Reset interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the End of Reset interrupt Enable bit and enable the corresponding interrupt
request.
zBit 2 – SOF: Start-of-Frame Interrupt Enable
0: The Start-of-Frame interrupt is disabled.
1: The Start-of-Frame interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Start-of-Frame interrupt Enable bit and enable the corresponding interrupt
request.
zBit 1 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 0 – SUSPEND: Suspend Interrupt Enable
0: The Suspend interrupt is disabled.
1: The Suspend interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Suspend interrupt Enable bit and enable the corresponding interrupt request.
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29.8.2.7 Device Interrupt Flag
Name: INTFLAG
Offset: 0x01C
Reset: 0x0000
Property: -
zBits 15:10 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 9 – LPMSUSP: Link Power Management Suspend Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB module acknowledge a Link Power Management Transaction (ACK handshake) and
has entered the Suspended state and will generate an interrupt if INTENCLR/SET.LPMSUSP is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the LPMSUSP Interrupt Flag.
zBit 8 – LPMNYET: Link Power Management Not Yet Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB module acknowledges a Link Power Management Transaction (handshake is NYET)
and will generate an interrupt if INTENCLR/SET.LPMNYET is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the LPMNYET Interrupt Flag.
zBit 7– RAMACER: RAM Access Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a RAM access underflow error occurs during IN data stage. This bit will generate an interrupt
if INTENCLR/SET.RAMACER is one.
Writing a zero to this bit has no effect.
zBit 6 – UPRSM: Upstream Resume Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB sends a resume signal called “Upstream Resume” and will generate an interrupt if
INTENCLR/SET.UPRSM is one.
Writing a zero to this bit has no effect.
zBit 5 – EORSM: End Of Resume Interrupt Flag
This flag is cleared by writing a one to the flag.
Bit151413121110 9 8
LPMSUSP LPMNYET
AccessRRRRRRR/WR/W
Reset00000000
Bit76543210
RAMACER UPRSM EORSM WAKEUP EORST SOF SUSPEND
Access R/W R/W R/W R/W R/W R/W R R/W
Reset00000000
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Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
This flag is set when the USB detects a valid “End of Resume” signal initiated by the host and will generate an
interrupt if INTENCLR/SET.EORSM is one.
Writing a zero to this bit has no effect.
zBit 4 – WAKEUP: Wake Up Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB is reactivated by a filtered non-idle signal from the lines and will generate an inter-
rupt if INTENCLR/SET.WAKEUP is one.
Writing a zero to this bit has no effect.
zBit 3 – EORST: End of Reset Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a USB “End of Reset” has been detected and will generate an interrupt if INTEN-
CLR/SET.EORST is one.
Writing a zero to this bit has no effect.
zBit 2 – SOF: Start-of-Frame Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a USB “Start-of-Frame” has been detected (every 1 ms) and will generate an interrupt if
INTENCLR/SET.SOF is one.
The FNUM is updated.
Writing a zero to this bit has no effect.
zBit 1 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 0 – SUSPEND: Suspend Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a USB “Suspend” idle state has been detected for 3 frame periods (J state for 3 ms) and will
generate an interrupt if INTENCLR/SET.SUSPEND is one.
Writing a zero to this bit has no effect.
748
Atmel | SMART SAM R21 [DATASHEET]
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29.8.2.8 Endpoint Interrupt Summary
Name: EPINTSMRY
Offset: 0x20
Reset: 0x00000000
Property: -
zBits 15:0 – EPINT[15:0]: EndPoint Interrupt Summary Register
The flag EPINT[n] is set when an interrupt is triggered by the EndPoint n. See “Device EndPoint Interrupt Flag” on
page 755 register in the device EndPoint section.
This bit will be cleared when no interrupts are pending for EndPoint n.
Bit151413121110 9 8
+1 EPINT[15:8]
AccessRRRRRRRR
Reset00000000
Bit76543210
+0 EPINT[7:0]
AccessRRRRRRRR
Reset00000000
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Atmel | SMART SAM R21 [DATASHEET]
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29.8.3 Device Registers - Endpoint
29.8.3.1 Device Endpoint Configuration register n
Name: EPCFGx
Offset: 0x100 + (n x 0x20)
Reset: 0x00
Property: Write-Protected
zBit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 6:4 – EPTYPE1[2:0]: Type of the Endpoint for IN direction
These bits contains the endpoint type for IN direction.
Table 29-14. Type of Endpoint
Upon receiving a USB reset EPCFGn.EPTYPE1 is cleared except for endpoint 0 which is unchanged.
zBit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
Bit76543210
ETYPE1[2:0] ETYPE0[2:0]
Access R R/W R/W R/W R R/W R/W R/W
Reset00000000
EPTYPE1[2:0] Description
0x0 Bank1 is disabled
0x1 Bank1 is enabled and configured as Control IN
0x2 Bank1 is enabled and configured as Isochronous IN
0x3 Bank1 is enabled and configured as Bulk IN
0x4 Bank1 is enabled and configured as Interrupt IN
0x5 Bank1 is enabled and configured as Dual-Bank OUT
(EndPoint type is the same as the one defined in EPTYPE0)
0x6-0x7 Reserved
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Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
zBits 2:0 – EPTYPE0[2:0]: Type of the Endpoint for OUT direction
These bits contains the endpoint type for OUT direction.
Table 29-15. Type of Endpoint
Upon receiving a USB reset EPCFGn.EPTYPE0 is cleared except for endpoint 0 which is unchanged.
EPTYPE0[2:0] Description
0x0 Bank0 is disabled
0x1 Bank0 is enabled and configured as Control SETUP / Control OUT
0x2 Bank0 is enabled and configured as Isochronous OUT
0x3 Bank0 is enabled and configured as Bulk OUT
0x4 Bank0 is enabled and configured as Interrupt OUT
0x5 Bank0 is enabled and configured as Dual Bank IN
(EndPoint type is the same as the one defined in EPTYPE1)
0x6-0x7 Reserved
751
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
29.8.3.2 EndPoint Status Clear Register n
Name: EPSTATUSCLR
Offset: 0x104 + (x * 0x20)
Reset: 0x00
Property: Write-Protected
zBit 7 – BK1RDY: Bank 1 Ready
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.BK1RDY bit.
zBit 6 – BK0RDY: Bank 0 Ready
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.BK0RDY bit.
zBit 5 – STALLRQ1:STALL bank 1 Request
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.STALLRQ1 bit.
zBit 4 – STALLRQ0:STALL bank 0 Request
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.STALLRQ0 bit.
zBit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 2 – CURBK: Current Bank
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.CURBK bit.
zBit 1 – DTGLIN: Data Toggle IN
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.DTGLIN bit.
zBit 0 – DTGLOUT: Data Toggle OUT
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the EPSTATUS.DTGLOUT bit.
Bit76543210
BK1RDY BK0RDY STALLRQ1 STALLRQ0 CURBK DTGLIN DTGLOUT
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
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Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
29.8.3.3 EndPoint Status Set n
Name: EPSTATUSSET
Offset: 0x105 + (n x 0x20)
Reset: 0x00
Property: Write-Protected
zBit 7 – BK1RDY: Bank 1 Ready
Writing a zero to this bit has no effect.
Writing a one to this bit will set EPSTATUS.BK1RDY bit.
zBit 6 – BK0RDY: Bank 0 Ready
Writing a zero to this bit has no effect.
Writing a one to this bit will set EPSTATUS.BK0RDY bit.
zBit 5 – STALLRQ1: STALL Request bank 1
Writing a zero to this bit has no effect.
Writing a one to this bit will set EPSTATUS.STALLRQ1 bit.
zBit 4 – STALLRQ0: STALL Request bank 0
Writing a zero to this bit has no effect.
Writing a one to this bit will set EPSTATUS.STALLRQ0 bit.
zBit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 2 – CURBK: Current Bank
Writing a zero to this bit has no effect.
Writing a one to this bit will set EPSTATUS.CURBK bit.
zBit 1 – DTGLIN: Data Toggle IN
Writing a zero to this bit has no effect.
Writing a one to this bit will set EPSTATUS.DTGLIN bit.
zBit 0 – DTGLOUT: Data Toggle OUT
Writing a zero to this bit has no effect.
Writing a one to this bit will set the EPSTATUS.DTGLOUT bit.
Bit76543210
BK1RDY BK0RDY STALLRQ1 STALLRQ0 CURBK DTGLIN DTGLOUT
Access R/W R/W R/W R/W R R/W R/W R/W
Reset00000000
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Atmel-42223G–SAM-R21_Datasheet–05/2016
29.8.3.4 EndPoint Status n
Name: EPSTATUS
Offset: 0x106 + (n x 0x20)
Reset: 0x00
Property: Write-Protected
zBit 7 – BK1RDY: Bank 1 is ready
0: The bank number 1 is not ready : For IN direction Endpoints, the bank is not yet filled in.
For Control/OUT direction Endpoints, the bank is empty.
1: The bank number 1 is ready: For IN direction Endpoints, the bank is filled in. For Control/OUT direction End-
points, the bank is full.
Writing a one to the bit EPSTATUSCLR.BK1RDY will clear this bit.
Writing a one to the bit EPSTATUSSET.BK1RDY will set this bit.
zBit 6 – BK0RDY: Bank 0 is ready
0: The bank number 0 is not ready : For IN direction Endpoints, the bank is not yet filled in. For Control/OUT direc-
tion Endpoints, the bank is empty.
1: The bank number 0 is ready: For IN direction Endpoints, the bank is filled in. For Control/OUT direction End-
points, the bank is full.
Writing a one to the bit EPSTATUSCLR.BK0RDY will clear this bit.
Writing a one to the bit EPSTATUSSET.BK0RDY will set this bit.
zBit 5 – STALLRQ1: STALL bank 1 request
0: Disable STALLRQ1 feature.
1: Enable STALLRQ1 feature: a STALL handshake will be sent to the host in regards to bank1.
Writing a zero to the bit EPSTATUSCLR.STALLRQ1 will clear this bit.
Writing a one to the bit EPSTATUSSET.STALLRQ1 will set this bit.
This bit is cleared by hardware when receiving a SETUP packet.
zBit 4 – STALLRQ0: STALL bank 0 request
0: Disable STALLRQ0 feature.
1: Enable STALLRQ0 feature: a STALL handshake will be sent to the host in regards to bank0.
Writing a zero to the bit EPSTATUSCLR.STALLRQ0 will clear this bit.
Writing a one to the bit EPSTATUSSET.STALLRQ0 will set this bit.
This bit is cleared by hardware when receiving a SETUP packet.
zBit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 2 – CURBK: Current Bank
0: The bank0 is the bank that will be used in the next single/multi USB packet.
1: The bank1 is the bank that will be used in the next single/multi USB packet.
Writing a zero to the bit EPSTATUSCLR.CURBK will clear this bit.
Bit76543210
BK1RDY BK0RDY STALLRQ1 STALLRQ0 CURBK DTGLIN DTGLOUT
AccessRRRRRRRR
Reset00000000
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Writing a one to the bit EPSTATUSSET.CURBK will set this bit.
zBit 1 – DTGLIN: Data Toggle IN Sequence
0: The PID of the next expected IN transaction will be zero: data 0.
1: The PID of the next expected IN transaction will be one: data 1.
Writing a zero to the bit EPSTATUSCLR.DTGLINCLR will clear this bit.
Writing a one to the bit EPSTATUSSET.DTGLINSET will set this bit.
zBit 0 – DTGLOUT: Data Toggle OUT Sequence
0: The PID of the next expected OUT transaction will be zero: data 0.
1: The PID of the next expected OUR transaction will be one: data 1.
Writing a zero to the bit EPSTATUSCLR.DTGLOUTCLR will clear this bit.
Writing a one to the bit EPSTATUSSET.DTGLOUTSET will set this bit.
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29.8.3.5 Device EndPoint Interrupt Flag
Name: EPINTFLAG
Offset: 0x107 + (n x 0x20)
Reset: 0x00
Property: -
zBits 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 6 – STALL1: Transmit Stall 1 Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Transmit Stall occurs and will generate an interrupt if EPINTENCLR/SET.STALL1 is one.
EPINTFLAG.STALL1 is set for a single bank IN endpoint or double bank IN/OUT endpoint when current bank is
"1".
Writing a zero to this bit has no effect.
Writing a one to this bit clears the STALL1 Interrupt Flag.
zBit 5 – STALL0: Transmit Stall 0 Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Transmit Stall occurs and will generate an interrupt if EPINTENCLR/SET.STALL0 is one.
EPINTFLAG.STALL0 is set for a single bank OUT endpoint or double bank IN/OUT endpoint when current bank is
"0".
Writing a zero to this bit has no effect.
Writing a one to this bit clears the STALL0 Interrupt Flag.
zBit 4 – RXSTP: Received Setup Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Received Setup occurs and will generate an interrupt if EPINTENCLR/SET.RXSTP is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the RXSTP Interrupt Flag.
zBit 3 – TRFAIL1: Transfer Fail 1 Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a transfer fail occurs and will generate an interrupt if EPINTENCLR/SET.TRFAIL1 is one.
EPINTFLAG.TRFAIL1 is set for a single bank IN endpoint or double bank IN/OUT endpoint when current bank is
"1".
Writing a zero to this bit has no effect.
Writing a one to this bit clears the TRFAIL1 Interrupt Flag.
Bit76543210
STALL1 STALL0 RXSTP TRFAIL1 TRFAIL0 TRCPT1 TRCPT0
Access R R/W R/W R/W R/W R/W R/W R/W
Reset00000000
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zBit 2 – TRFAIL0: Transfer Fail 0 Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a transfer fail occurs and will generate an interrupt if EPINTENCLR/SET.TRFAIL0 is one.
EPINTFLAG.TRFAIL0 is set for a single bank OUT endpoint or double bank IN/OUT endpoint when current bank
is "0".
Writing a zero to this bit has no effect.
Writing a one to this bit clears the TRFAIL0 Interrupt Flag.
zBit 1 – TRCPT1: Transfer Complete 1 interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Transfer Complete occurs and will generate an interrupt if EPINTENCLR/SET.TRCPT1 is
one. EPINTFLAG.TRCPT1 is set for a single bank IN endpoint or double bank IN/OUT endpoint when current
bank is "1".
Writing a zero to this bit has no effect.
Writing a one to this bit clears the TRCPT1 Interrupt Flag.
zBit 0 – TRCPT0: Transfer Complete 0 interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Transfer complete occurs and will generate an interrupt if EPINTENCLR/SET.TRCPT0 is
one. EPINTFLAG.TRCPT0 is set for a single bank OUT endpoint or double bank IN/OUT endpoint when current
bank is "0".
Writing a zero to this bit has no effect.
Writing a one to this bit clears the TRCPT0 Interrupt Flag.
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29.8.3.6 Device EndPoint Interrupt Enable
Name: EPINTENCLR
Offset: 0x108 + (n x 0x20)
Reset: 0x00
Property: Write-Protected
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Endpoint Interrupt Enable Set (EPINTENSET) register.
This register is cleared by USB reset or when EPEN[n] is zero.
zBits 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 6 – STALL1: Transmit STALL 1 Interrupt Enable
0: The Transmit Stall 1 interrupt is disabled.
1: The Transmit Stall 1 interrupt is enabled and an interrupt request will be generated when the Transmit Stall 1
Interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transmit Stall 1 Interrupt Enable bit and disable the corresponding interrupt
request.
zBit 5 – STALL0: Transmit STALL 0 Interrupt Enable
0: The Transmit Stall 0 interrupt is disabled.
1: The Transmit Stall 0 interrupt is enabled and an interrupt request will be generated when the Transmit Stall 0
Interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transmit Stall 0 Interrupt Enable bit and disable the corresponding interrupt
request.
zBit 4 – RXSTP: Received Setup Interrupt Enable
0: The Received Setup interrupt is disabled.
1: The Received Setup interrupt is enabled and an interrupt request will be generated when the Received Setup
Interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Received Setup Interrupt Enable bit and disable the corresponding interrupt
request.
zBit 3 – TRFAIL1: Transfer Fail 1 Interrupt Enable
0: The Transfer Fail 1 interrupt is disabled.
1: The Transfer Fail 1 interrupt is enabled and an interrupt request will be generated when the Transfer Fail 1 Inter-
rupt Flag is set.
Bit76543210
STALL1 STALL0 RXSTP TRFAIL1 TRFAIL0 TRCPT1 TRCPT0
Access R R/W R/W R/W R/W R/W R/W R/W
Reset00000000
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The user should look into the descriptor table status located in ram to be informed about the error condition :
ERRORFLOW, CRC.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Fail 1 Interrupt Enable bit and disable the corresponding interrupt
request.
zBit 2 – TRFAIL0: Transfer Fail 0 Interrupt Enable
0: The Transfer Fail bank 0 interrupt is disabled.
1: The Transfer Fail bank 0 interrupt is enabled and an interrupt request will be generated when the Transfer Fail 0
Interrupt Flag is set.
The user should look into the descriptor table status located in ram to be informed about the error condition :
ERRORFLOW, CRC.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Fail 0 Interrupt Enable bit and disable the corresponding interrupt
request.
zBit 1 – TRCPT1: Transfer Complete 1 Interrupt Enable
0: The Transfer Complete 1 interrupt is disabled.
1: The Transfer Complete 1 interrupt is enabled and an interrupt request will be generated when the Transfer
Complete 1 Interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Complete 1 Interrupt Enable bit and disable the corresponding inter-
rupt request.
zBit 0 – TRCPT0: Transfer Complete 0 interrupt Enable
0: The Transfer Complete bank 0 interrupt is disabled.
1: The Transfer Complete bank 0 interrupt is enabled and an interrupt request will be generated when the Transfer
Complete 0 Interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Complete 0 interrupt Enable bit and disable the corresponding inter-
rupt request.
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29.8.3.7 Device Interrupt EndPoint Set
Name: EPINTENSET
Offset: 0x109 + (n x 0x20)
Reset: 0x0000
Property: Write-Protected
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Endpoint Interrupt Enable Set (EPINTENCLR) register.
This register is cleared by USB reset or when EPEN[n] is zero.
zBits 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 6 – STALL1: Transmit Stall 1 Interrupt Enable
0: The Transmit Stall 1 interrupt is disabled.
1: The Transmit Stall 1 interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transmit bank 1 Stall interrupt.
zBit 5 – STALL0: Transmit Stall 0 Interrupt Enable
0: The Transmit Stall 0 interrupt is disabled.
1: The Transmit Stall 0 interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transmit bank 0 Stall interrupt.
zBit 4 – RXSTP: Received Setup Interrupt Enable
0: The Received Setup interrupt is disabled.
1: The Received Setup interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Received Setup interrupt.
zBit 3 – TRFAIL1: Transfer Fail bank 1 Interrupt Enable
0: The Transfer Fail interrupt is disabled.
1: The Transfer Fail interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Fail interrupt.
zBit 3 – TRFAIL0: Transfer Fail bank 0 Interrupt Enable
0: The Transfer Fail interrupt is disabled.
1: The Transfer Fail interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Fail interrupt.
Bit76543210
STALL1 STALL0 RXSTP TRFAIL1 TRFAIL0 TRCPT1 TRCPT0
Access R R/W R/W R/W R/W R/W R/W R/W
Reset00000000
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zBit 1 – TRCPT1: Transfer Complete bank 1 interrupt Enable
0: The Transfer Complete bank 1 interrupt is disabled.
1: The Transfer Complete bank 1 interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Complete 0 interrupt.
zBit 0 – TRCPT0: Transfer Complete bank 0 interrupt Enable
0: The Transfer Complete bank 0 interrupt is disabled.
1: The Transfer Complete bank 0 interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Complete 1 interrupt.
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Atmel | SMART SAM R21 [DATASHEET]
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29.8.4 Device Registers - Endpoint RAM
29.8.4.1 Endpoint Descriptor structure
EPn BK0
EPn BK1
Endpoint
descriptors
Data Buffers
EXTREG
PCKSIZE
ADDR DESCADD
Growing Memory Addresses
Descriptor E0
STATUS_BK
Reserved
Bank0
+0x000
+0x004
+0x008
+0x00A
+0x00B
Reserved
PCKSIZE
ADDR
STATUS_BK
Reserved
Bank1
+0x010
+0x014
+0x018
+0x01A
+0x01B
EXTREG
PCKSIZE
ADDR
Descriptor En
STATUS_BK
Reserved
Bank0
Reserved
PCKSIZE
ADDR
STATUS_BK
Bank1
Reserved
2 x 0xn0
(2 x 0xn0) + 0x10
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29.8.4.2 Address of Data Buffer
Name: ADDR
Offset: 0x00 & 0x10
Reset: 0xxxxxxxx
Property: NA
zBits 31:0 – ADDR[31:0]: Data Pointer Address Value
These bits define the data pointer address as an absolute word address in RAM.The two least significant bits must
be zero to ensure the start address is 32-bit aligned.
Bit3130292827262524
+3 ADDR[31:24]
Access R/W R/W R/W R/W R/W R/W R/W R/W
ResetXXXXXXXX
Bit2322212019181716
+2 ADDR[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
ResetXXXXXXXX
Bit151413121110 9 8
+1 ADDR[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
ResetXXXXXXXX
Bit76543210
+0 ADDR[7:0]
Access R/W R/W R/W R/W R/W R/W R R
ResetXXXXXXXX
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Atmel-42223G–SAM-R21_Datasheet–05/2016
29.8.4.3 Packet Size
Name: PCKSIZE
Offset: 0x04 & 0x14
Reset: 0xxxxxxxxx
Property: NA
zBit 31 – AUTO_ZLP: Automatic Zero Length Packet
This bit defines the automatic Zero Length Packet mode of the endpoint.
0: Automatic Zero Length Packet is disabled.
1: Automatic Zero Length Packet is enabled.
When enabled, the USB module will manage the ZLP handshake by hardware. This bit is for IN endpoints only.
When disabled the handshake should be managed by firmware.
zBits 30:28 – SIZE: Endpoint size
These bits contains the maximum packet size of the endpoint.
Bit3130292827262524
+3 AUTO_ZLP SIZE[2:0] MULTI_PACKET_SIZE[13:10]
Access R/W R/W R/W R/W R/W R/W R/W R/W
ResetXXXXXXXX
Bit2322212019181716
+2 MULTI_PACKET_SIZE[9:2]
Access R/W R/W R/W R/W R/W R/W R/W R/W
ResetXXXXXXXX
Bit151413121110 9 8
+1 MULTI_PACKET_SIZE[1:0] BYTE-COUNT[13:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
ResetXXXXXXXX
Bit76543210
+0 BYTE_COUNT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
ResetXXXXXXXX
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zBits 27:14 – MULTI_PACKET_SIZE: Multiple Packet Size
These bits define the 14-bit value that is used for multi-packet transfers.
For IN endpoints, MULTI_PACKET_SIZE holds the total number of bytes sent. MULTI_PACKET_SIZE should be
written to zero when setting up a new transfer.
For OUT endpoints, MULTI_PACKET_SIZE holds the total data size for the complete transfer. This value must be
a multiple of the maximum packet size.
zBits 13:0 – BYTE_COUNT: Byte Count
These bits define the 14-bit value that is used for the byte count.
For IN endpoints, BYTE_COUNT holds the number of bytes to be sent in the next IN transaction.
For OUT endpoint or SETUP endpoints, BYTE_COUNT holds the number of bytes received upon the last OUT or
SETUP transaction.
Table 29-16. Endpoint Size
SIZE[2:0] Description
0x0 8 Byte
0x1 16 Byte
0x2 32 Byte
0x3 64 Byte
0x4 128 Byte (1)
1. for Isochronous endpoints only.
0x5 256 Byte (1)
0x6 512 Byte (1)
0x7 1023 Byte (1)
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29.8.4.4 Extended Register
Name: EXTREG
Offset: 0x08
Reset: 0xxxxxxxx
Property: NA
zBits 15 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 14:4 – VARIABLE: VARIABLE
These bits define the VARIABLE field of a received extended token.These bits are updated when the USB has
answered by an handshake token ACK to a LPM transaction. See Section 2.1.1 Protocol Extension Token in the
reference document “ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum”.
To support the USB2.0 Link Power Management addition the VARIABLE field should be read as described below.
Table 29-17. VARIABLE bit fields for LPM application
(1) for a definition of LPM Token bRemoteWake and bLinkState fields, refer to "Table 2-3 in the reference document ENGINEERING CHANGE NOTICE,
USB 2.0 Link Power Management Addendum".
(2) for a definition of LPM Token BESL field, refer to "Table 2-3 in the reference document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Man-
agement Addendum" and "Table X-X1 in Errata for ECN USB 2.0 Link Power Management.
zBits 3:0 – SUBPID: SUBPID
These bits define the SUBPID field of a received extended token.These bits are updated when the USB has
answered by an handshake token ACK to a LPM transaction. See Section 2.1.1 Protocol Extension Token in the
reference document “ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum”.
Bit151413121110 9 8
+1 VARIABLE[10:4]
Access R R/W R/W R/W R/W R/W R/W R/W
ResetXXXXXXXX
Bit76543210
+0 VARIABLE[3:0] SUBPID[3:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
ResetXXXXXXXX
VARIABLES Description
VARIABLE[3:0] bLinkState (1)
VARIABLE[7:4] BESL (2)
VARIABLE[8] bRemoteWake (1)
VARIABLE[10:9] Reserved
766
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29.8.4.5 Device Status Bank
Name: STATUS_BK
Offset: 0x0A & 0x1A
Reset: 0xxxxxxxx
Property: NA
zBits 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 1 – ERROFLOW: Error Flow Status
This bit defines the Error Flow Status.
0: No Error Flow detected.
1: A Error Flow has been detected.
This bit is set when a Error Flow has been detected during transfer from/towards this bank.
For OUT transfer, a NAK handshake has been sent.
For Isochronous OUT transfer, an overrun condition has occurred.
For IN transfer, this bit is not valid. EPSTATUS.TRFAIL0 and EPSTATUS.TRFAIL1 should reflect the flow errors.
zBit 0 – CRCERR: CRC Error
This bit defines the CRC Error Status.
0: No CRC Error.
1: CRC Error detected.
This bit is set when a CRC error has been detected in an isochronous OUT endpoint bank.
Bit76543210
+0 ERROFLOW CRCERR
Access R/W R/W R/W R/W R/W R/W R/W R/W
ResetXXXXXXXX
767
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29.8.5 Host Registers - Common
29.8.5.1 Control B
Name: CTRLB
Offset: 0x08
Reset: 0x0000
Property: Write-Protected
zBits 15:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 11 – L1RESUME: Send USB L1 Resume
Writing 0 to this bit has no effect.
1: Generates a USB L1 Resume on the USB bus. This bit should only be set when the Start-of-Frame generation
is enabled (SOFE bit set). The duration of the USB L1 Resume is defined by the EXTREG.VARIABLE[7:4] bits
field also known as BESL (See LPM ECN).See also “Extended Register” on page 797.
This bit is cleared when the USB L1 Resume has been sent or when a USB reset is requested.
zBit 10 – VBUSOK: VBUS is OK
0: The USB module is notified that the VBUS on the USB line is not powered.
1: The USB module is notified that the VBUS on the USB line is powered.
This notifies the USB HOST that USB operations can be started. When this bit is zero and even if the USB HOST
is configured and enabled, HOST operation is halted. Setting this bit will allow HOST operation when the USB is
configured and enabled.
zBit 9 – BUSRESET: Send USB Reset
0: Reset generation is disabled. It is written to zero when the USB reset is completed or when a device disconnec-
tion is detected. Writing zero has no effect.
1: Generates a USB Reset on the USB bus.
zBit 8 – SOFE: Start-of-Frame Generation Enable
0: The SOF generation is disabled and the USB bus is in suspend state.
1: Generates SOF on the USB bus in full speed and keep it alive in low speed mode. This bit is automatically set at
the end of a USB reset (INTFLAG.RST) or at the end of a downstream resume (INTFLAG.DNRSM) or at the end
of L1 resume.
zBits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit151413121110 9 8
L1RESUME VBUSOK BUSRESET SOFE
Access R R R R R/W R/W R/W R/W
Reset00000000
Bit76543210
SPDCONF[1:0] RESUME
Access R R R R R/W R/W R/W R
Reset00000000
768
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zBits 3:2 – SPDCONF: Speed Configuration for Host
These bits select the host speed configuration as shown below
zBit 1 – RESUME: Send USB Resume
Writing 0 to this bit has no effect.
1: Generates a USB Resume on the USB bus.
This bit is cleared when the USB Resume has been sent or when a USB reset is requested.
zBit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
Table 29-18. SPDCONF Selection
SPDCONF[1:0] Description
0x0 Low and Full Speed capable
0x1 Reserved
0x2 Reserved
0x3 Reserved
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29.8.5.2 Host Start-of-Frame Control Register
Name: HSOFC
Offset: 0x0A
Reset: 0x0000
Property: Write-Protected
During a very short period just before transmitting a Start-of-Frame, this register is locked.Thus, after writing, it is
recommended to check the register value, and write this register again if necessary. This register is cleared upon
a USB reset.
zBit 7 – FLENCE: Frame Length Control Enable
When this bit is ‘1’ the time between Start-of Frames can be tuned by up to ±0.06% using FLENC[3:0].
Note: In Low Speed mode, FLENCE must be ‘0’.
zBits 3:0 – FLENC: Frame Length Control
These bits define the signed value of the 4-bit FLENC that is added to the Internal Frame Length when FLENCE is
‘1’.The internal Frame length is the top value of the frame counter when FLENCE is zero.
Bit76543210
FLENCE FLENC[3:0]
Access R/W R R R R/W R/W R/W R/W
Reset00000000
Table 29-19. Internal Frame Length Down-Counter
Value Description
0Start-of-Frame is generated every 1ms
1Start-of-Frame generation depends on the signed value of FLENC[3:0].
USB Start-of-Frame period equals 1ms + (FLENC[3:0]/12000)ms
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29.8.5.3 Status Register
Name: STATUS
Offset: 0x0C
Reset: 0x0000
Property: Read only
zBits 7:6 – LINESTATE: USB Line State Status
These bits define the current line state DP/DM.
Table 29-20. Line State
zBits 5:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 3:2 – SPEED[1:0]: Speed Status
These bits define the current speed used by the host.
zBits 1:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit76543210
LINESTATE[1:0] SPEED[1:0]
AccessRRRRRRRR
Reset00000000
LINESTATE[1:0] USB Line Status
0x0 SE0/RESET
0x1 FS-J or LS-K State
0x2 FS-K or LS-J State
Table 29-21. Speed Status
SPEED[1:0] Speed Status
0x0 Full-speed mode
0x1 Reserved
0x2 Low-speed mode
0x3 Reserved
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29.8.5.4 Host Frame Number Register
Name: FNUM
Offset: 0x10
Reset: 0x0000
Property: Write-Protected
Property:
zBits 15:14 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 13:3 – FNUM: Frame Number
These bits contains the current SOF number.
These bits can be written by software to initialize a new frame number value. In this case, at the next SOF, the
FNUM field takes its new value.
As the FNUM register lies across two consecutive byte addresses, writing byte-wise (8-bits) to the FNUM register
may produce incorrect frame number generation. It is recommended to write FNUM register word-wise (32-bits) or
half-word-wise (16-bits).
zBits 2:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit151413121110 9 8
FNUM[10:5]
Access R R R/W R/W R/W R/W R/W R/W
Reset00000000
Bit76543210
FNUM[4:0]
Access R/W R/W R/W R/W R/W R R R
Reset00000000
772
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29.8.5.5 Host Frame Length Register
Name: FLENHIGH
Offset: 0x12
Reset: 0x0000
Property: Read-Only
zBits 7:0 – FLENHIGH: Frame Length
These bits contains the 8 high-order bits of the internal frame counter.
Table 29-22. Counter description versus speed
Bit76543210
FLENHIGH[7:0]
AccessRRRRRRRR
Reset00000000
Table 29-23. Counter Description vs. Speed
Host Register
STATUS.SPEED Description
Full Speed With a USB clock running at 12MHz, counter length is 12000 to ensure a SOF
generation every 1 ms
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29.8.5.6 Host Interrupt Enable Register Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set (INTENSET) register.
Name: INTENCLR
Offset: 0x14
Reset: 0x0000
Property: Write-Protected
zBits 15:10 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 9 – DDISC: Device Disconnection Interrupt Enable
0: The Device Disconnection interrupt is disabled.
1: The Device Disconnection interrupt is enabled and an interrupt request will be generated when the Device Dis-
connection interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Device Disconnection interrupt Enable bit and disable the corresponding inter-
rupt request.
zBit 8 – DCONN: Device Connection Interrupt Enable
0: The Device Connection interrupt is disabled.
1: The Device Connection interrupt is enabled and an interrupt request will be generated when the Device Con-
nection interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Device Connection interrupt Enable bit and disable the corresponding inter-
rupt request.
zBit 7 – RAMACER: RAM Access Interrupt Enable
0: The RAM Access interrupt is disabled.
1: The RAM Access interrupt is enabled and an interrupt request will be generated when the RAM Access interrupt
Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the RAM Access interrupt Enable bit and disable the corresponding interrupt
request.
zBit 6 – UPRSM: Upstream Resume from Device Interrupt Enable
0: The Upstream Resume interrupt is disabled.
Bit151413121110 9 8
DDISC DCONN
AccessR/RRRRRR/WR/W
Reset00000000
Bit76543210
RAMACER UPRSM DNRSM WAKEUP RST HSOF
Access R/W R/W R/W R/W R/W R/W R R
Reset00000000
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1: The Upstream Resume interrupt is enabled and an interrupt request will be generated when the Upstream
Resume interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Upstream Resume interrupt Enable bit and disable the corresponding inter-
rupt request.
zBit 5 – DNRSM: Down Resume Interrupt Enable
0: The Down Resume interrupt is disabled.
1: The Down Resume interrupt is enabled and an interrupt request will be generated when the Down Resume
interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Down Resume interrupt Enable bit and disable the corresponding interrupt
request.
zBit 4 – WAKEUP: Wake Up Interrupt Enable
0: The Wake Up interrupt is disabled.
1: The Wake Up interrupt is enabled and an interrupt request will be generated when the Wake Up interrupt Flag is
set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Wake Up interrupt Enable bit and disable the corresponding interrupt request.
zBit 3 – RST: BUS Reset Interrupt Enable
0: The Bus Reset interrupt is disabled.
1: The Bus Reset interrupt is enabled and an interrupt request will be generated when the Bus Reset interrupt Flag
is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Bus Reset interrupt Enable bit and disable the corresponding interrupt
request.
zBit 2 – HSOF: Host Start-of-Frame Interrupt Enable
0: The Host Start-of-Frame interrupt is disabled.
1: The Host Start-of-Frame interrupt is enabled and an interrupt request will be generated when the Host Start-of-
Frame interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Host Start-of-Frame interrupt Enable bit and disable the corresponding inter-
rupt request.
zBits 1:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
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29.8.5.7 Host Interrupt Enable Register Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Name: INTENSET
Offset: 0x18
Reset: 0x0000
Property: Write-Protected
zBits 15:10 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 9 – DDISC: Device Disconnection Interrupt Enable
0: The Device Disconnection interrupt is disabled.
1: The Device Disconnection interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Device Disconnection interrupt bit and enable the DDSIC interrupt.
zBit 8 – DCONN: Device Connection Interrupt Enable
0: The Device Connection interrupt is disabled.
1: The Device Connection interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Device Connection interrupt bit and enable the DCONN interrupt.
zBit 7 – RAMACER: RAM Access Interrupt Enable
0: The RAM Access interrupt is disabled.
1: The RAM Access interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the RAM Access interrupt bit and enable the RAMACER interrupt.
zBit 6 – UPRSM: Upstream Resume from the device Interrupt Enable
0: The Upstream Resume interrupt is disabled.
1: The Upstream Resume interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Upstream Resume interrupt bit and enable the UPRSM interrupt.
zBit 5 – DNRSM: Down Resume Interrupt Enable
0: The Down Resume interrupt is disabled.
Bit151413121110 9 8
DDISC DCONN
AccessR/WRRRRRR/WR/W
Reset00000000
Bit76543210
RAMACER UPRSM DNRSM WAKEUP RST HSOF
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
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1: The Down Resume interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Down Resume interrupt Enable bit and enable the DNRSM interrupt.
zBit 4 – WAKEUP: Wake Up Interrupt Enable
0: The WakeUp interrupt is disabled.
1: The WakeUp interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Wake Up interrupt Enable bit and enable the WAKEUP interrupt request.
zBit 3 – RST: Bus Reset Interrupt Enable
0: The Bus Reset interrupt is disabled.
1: The Bus Reset interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Bus Reset interrupt Enable bit and enable the Bus RST interrupt.
zBit 2 – HSOF: Host Start-of-Frame Interrupt Enable
0: The Host Start-of-Frame interrupt is disabled.
1: The Host Start-of-Frame interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Host Start-of-Frame interrupt Enable bit and enable the HSOF interrupt.
zBits 1:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
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29.8.5.8 Host Interrupt Flag Register
Name: INTFLAG
Offset: 0x1C
Reset: 0x0000
Property: -
zBits 15:10 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 9 – DDISC: Device Disconnection Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the device has been removed from the USB Bus and will generate an interrupt if INTEN-
CLR/SET.DDISC is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DDISC Interrupt Flag.
zBit 8 – DCONN: Device Connection Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a new device has been connected to the USB BUS and will generate an interrupt if INTEN-
CLR/SET.DCONN is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DCONN Interrupt Flag.
zBit 7 – RAMACER: RAM Access Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a RAM access error occurs during an OUT stage and will generate an interrupt if INTEN-
CLR/SET.RAMACER is one.
Writing a zero to this bit has no effect.
zBit 6 – UPRSM: Upstream Resume from the Device Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB has received an Upstream Resume signal from the Device and will generate an
interrupt if INTENCLR/SET.UPRSM is one.
Writing a zero to this bit has no effect.
Bit151413121110 9 8
DDISC DCONN
AccessRRRRRRR/WR/W
Reset00000000
Bit76543210
RAMACER UPRSM DNRSM WAKEUP RST HSOF
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
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zBit 5 – DNRSM: Down Resume Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB has sent a Down Resume and will generate an interrupt if INTENCLR/SET.DRSM is
one.
Writing a zero to this bit has no effect.
zBit 4 – WAKEUP: Wake Up Interrupt Flag
This flag is cleared by writing a one.
This flag is set when:
zThe host controller is in suspend mode (SOFE is zero) and an upstream resume from the device is
detected.
zThe host controller is in suspend mode (SOFE is zero) and an device disconnection is detected.
zThe host controller is in operational state (VBUSOK is one) and an device connection is detected.
In all cases it will generate an interrupt if INTENCLR/SET.WAKEUP is one.
Writing a zero to this bit has no effect.
zBit 3 – RST: Bus Reset Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Bus “Reset” has been sent to the Device and will generate an interrupt if INTEN-
CLR/SET.RST is one.
Writing a zero to this bit has no effect.
zBit 2 – HSOF: Host Start-of-Frame Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a USB “Host Start-of-Frame” in Full Speed or a keep-alive in Low Speed has been sent
(every 1 ms) and will generate an interrupt if INTENCLR/SET.HSOF is one.
The value of the FNUM register is updated.
Writing a zero to this bit has no effect.
zBits 1:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
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29.8.5.9 Pipe Interrupt Summary Register
Name: PINTSMRY
Offset: 0x20
Reset: 0x00000000
Property: Read-only
zBits 15:0 – PINT: Pipe Interrupt Summary Register
The flag PINT[n] is set when an interrupt is triggered by the pipe n. See “Host Pipe Interrupt Flag Register” on
page 787 register in the Host Pipe Register section.
This bit will be cleared when there are no interrupts pending for Pipe n.
Writing to this bit has no effect.
Bit151413121110 9 8
+1 PINT[15:8]
AccessRRRRRRRR
Reset00000000
Bit76543210
+0 PINT[7:0]
AccessRRRRRRRR
Reset00000000
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29.8.6 Host Registers - Pipe
29.8.6.1 Host Pipe n Configuration Register
Name: PCFGn
Offset: 0x100 + (n x 0x20)
Reset: 0x0000
Property: Write-Protected
zBits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 5:3 – PTYPE: Type of the Pipe
These bits contains the pipe type.
Theses bits are cleared upon sending a USB reset.
zBit 2 – BK: Pipe Bank
0: A single bank is used for the pipe.
1: A dual bank is used for the pipe.
This bit selects the number of banks for the pipe.
For control endpoints writing a zero to this bit is required as only Bank0 is used for Setup/In/Out transactions.
This bit is cleared when a USB reset is sent.
Table 29-25. Bank
Bit76543210
PTYPE[2:0] BK PTOKEN[1:0]
Access R R R/W R/W R/W R/W R/W R/W
Reset00000000
Table 29-24. Type of the Pipe
PTYPE[2:0] Description
0x0 Pipe is disabled
0x1 Pipe is enabled and configured as CONTROL
0x2 Pipe is enabled and configured as ISO
0x3 Pipe is enabled and configured as BULK
0x4 Pipe is enabled and configured as INTERRUPT
0x5 Pipe is enabled and configured as EXTENDED
0x06-0x7 Reserved
BK (1) Description
0x0 Single-bank endpoint
0x1 Dual-bank endpoint
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zBits 1:0 – PTOKEN: Pipe Token
These bits contains the pipe token.
Table 29-26. Pipe Token
Theses bits are cleared upon sending a USB reset.
1. Bank field is ignored when PTYPE is configured as EXTENDED
PTOKEN[1:0] (1)
1. PTOKEN field is ignored when PTYPE is configured as EXTENDED
Description
0x0 SETUP (2)
2. Available only when PTYPE is configured as CONTROL
0x1 IN
0x2 OUT
0x3 Reserved
782
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29.8.6.2 Interval for the Bulk-Out/Ping transaction Register
Name: BINTERVAL
Offset: 0x103 + (n x 0x20)
Reset: 0x0000
Property: Write-Protected
zBits 7:0 – BINTERVAL: BINTERVAL
These bits contains the Ping/Bulk-out period.
These bits are cleared when a USB reset is sent or when PEN[n] is zero.
Depending from the type of pipe the desired period is defined as:
Table 29-27. Pipe Type
Bit76543210
BINTERVAL[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
BINTERVAL Description
=0 Multiple consecutive OUT token is sent in the same frame until it is acked by the peripheral
>0 One OUT token is sent every BINTERVAL frame until it is acked by the peripheral
PTYPE Description
Interrupt 1 ms to 255 ms
Isochronous 2^(Binterval) * 1 ms
Bulk or control 1 ms to 255 ms
EXT LPM bInterval ignored. Always 1 ms when a NYET is received.
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29.8.6.3 Pipe Status Clear Register n
Name: PSTATUSCLR
Offset: 0x104 + (n x 0x20)
Reset: 0x0000
Property: Write-Protected
zBit 7 – BK1RDY: Bank 1 Ready Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear PSTATUS.BK1RDY bit.
zBit 6 – BK0RDY: Bank 0 Ready Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear PSTATUS.BK0RDY bit.
zBit 5 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 4 – PFREEZE: Pipe Freeze Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear PSTATUS.PFREEZE bit.
zBit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 2 – CURBK: Current Bank Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear PSTATUS.CURBK bit.
zBit 1 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 0 – DTGL: Data Toggle Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear PSTATUS.DTGL bit.
Bit76543210
BK1RDY BK0RDY PFREEZE CURBK DTGL
Access RW1 RW1 R RW1 R RW1 R RW1
Reset00000000
784
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29.8.6.4 Pipe Status Set Register n
Name: PSTATUSSET
Offset: 0x105 + (n x 0x20)
Reset: 0x0000
Property: Write-Protected
zBit 7– BK1RDY: Bank 1 Ready Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set the bit PSTATUS.BK1RDY.
zBit 6 – BK0RDY: Bank 0 Ready Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set the bit PSTATUS.BK0RDY.
zBit 5 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 4 – PFREEZE: Pipe Freeze Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set PSTATUS.PFREEZE bit.
zBit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 2 – CURBK: Current Bank Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set PSTATUS.CURBK bit.
zBit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 0 – DTGL: Data Toggle Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set PSTATUS.DTGL bit.
Bit76543210
BK1RDY BK0RDY PFREEZE CURBK DTGL
Access RW1 RW1 R RW1 R RW1 R RW1
Reset00000000
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29.8.6.5 Pipe Status Register n
Name: PSTATUS
Offset: 0x106 + (n x 0x20)
Reset: 0x0000
Property: Write-Protected
zBit 7– BK1RDY: Bank 1 is ready
0: The bank number 1 is not ready: For IN the bank is empty. For Control/OUT the bank is not yet fill in.
1: The bank number 1 is ready: For IN the bank is filled full. For Control/OUT the bank is filled in.
Writing a one to the bit EPSTATUSCLR.BK1RDY will clear this bit.
Writing a one to the bit EPSTATUSSET.BK1RDY will set this bit.
This bank is not used for Control pipe.
zBit 6 – BK0RDY: Bank 0 is ready
0: The bank number 0 is not ready: For IN the bank is not empty. For Control/OUT the bank is not yet fill in.
1: The bank number 0 is ready: For IN the bank is filled full. For Control/OUT the bank is filled in.
Writing a one to the bit EPSTATUSCLR.BK0RDY will clear this bit.
Writing a one to the bit EPSTATUSSET.BK0RDY will set this bit.
This bank is the only one used for Control pipe.
zBit 5 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 4 – PFREEZE: Pipe Freeze
0: The Pipe operates in normal operation.
1: The Pipe is frozen and no additional requests will be sent to the device on this pipe address.
Writing a one to the bit EPSTATUSCLR.PFREEZE will clear this bit.
Writing a one to the bit EPSTATUSSET.PFREEZE will set this bit.
zThis bit is also set by the hardware:
zWhen a STALL handshake has been received.
zAfter a PIPE has been enabled (rising of bit PEN.N).
zWhen an LPM transaction has completed whatever handshake is returned or the transaction was timed-out.
zWhen a pipe transfer was completed with a pipe error. See “Host Pipe Interrupt Flag Register” on page 787.
When PFREEZE bit is set while a transaction is in progress on the USB bus, this transaction will be properly com-
pleted. PFREEZE bit will be read as “1” only when the ongoing transaction will have been completed.
zBit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 2 – CURBK: Current Bank
0: The bank0 is the bank that will be used in the next single/multi USB packet.
1: The bank1 is the bank that will be used in the next single/multi USB packet.
Bit76543210
BK1RDY BK0RDY PFREEZE CURBK DTGL
AccessRRRRRRRR
Reset00000000
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zBit 5 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBit 0 – DTGL: Data Toggle Sequence
0: The PID of the next expected transaction will be zero: data 0.
1: The PID of the next expected transaction will be one: data 1.
Writing a one to the bit EPSTATUSCLR.DTGL will clear this bit.
Writing a one to the bit EPSTATUSSET.DTGL will set this bit.
This bit is toggled automatically by hardware after a data transaction.
This bit will reflect the data toggle in regards of the token type (IN/OUT/SETUP).
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29.8.6.6 Host Pipe Interrupt Flag Register
Name: PINTFLAG
Offset: 0x107 + (n x 0x20)
Reset: 0x0000
Property: -
zBits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 5 – STALL: STALL Received Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a stall occurs and will generate an interrupt if PINTENCLR/SET.STALL is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the STALL Interrupt Flag.
zBit 4 – TXSTP: Transmitted Setup Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Transfer Complete occurs and will generate an interrupt if PINTENCLR/SET.TXSTP is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the TXSTP Interrupt Flag.
zBit 3 – PERR: Pipe Error Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a pipe error occurs and will generate an interrupt if PINTENCLR/SET.PERR is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the PERR Interrupt Flag.
zBit 2 – TRFAIL: Transfer Fail Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Transfer Fail occurs and will generate an interrupt if PINTENCLR/SET.TRFAIL is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the TRFAIL Interrupt Flag.
zBit 1 – TRCPT1: Transfer Complete 1 interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Transfer Complete occurs and will generate an interrupt if PINTENCLR/SET.TRCPT1 is
one. PINTFLAG.TRCPT1 is set for a double bank IN/OUT pipe when current bank is 1.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the TRCPT1 Interrupt Flag.
zBit 0 – TRCPT0: Transfer Complete 0 interrupt Flag
This flag is cleared by writing a one to the flag.
Bit76543210
STALL TXSTP PERR TRFAIL TRCPT1 TRCPT0
Access R R RW1 RW1 RW1 RW1 RW1 RW1
Reset00000000
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This flag is set when a Transfer complete occurs and will generate an interrupt if PINTENCLR/SET.TRCPT0 is
one. PINTFLAG.TRCPT0 is set for a single bank IN/OUT pipe or a double bank IN/OUT pipe when current bank is
0.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the TRCPT0 Interrupt Flag.
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29.8.6.7 Host Pipe Interrupt Enable Register
Name: PINTENCLR
Offset: 0x108 + (n x 0x20)
Reset: 0x0000
Property: Write-Protected
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Pipe Interrupt Enable Set (PINTENSET) register.
This register is cleared by USB reset or when PEN[n] is zero.
zBits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 5 – STALL: Received Stall Interrupt Enable
0: The received Stall interrupt is disabled.
1: The received Stall interrupt is enabled and an interrupt request will be generated when the received Stall inter-
rupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Received Stall interrupt Enable bit and disable the corresponding interrupt
request.
zBit 4 – TXSTP: Transmitted Setup Interrupt Enable
0: The Transmitted Setup interrupt is disabled.
1: The Transmitted Setup interrupt is enabled and an interrupt request will be generated when the Transmitted
Setup interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transmitted Setup interrupt Enable bit and disable the corresponding interrupt
request.
zBit 3 – PERR: Pipe Error Interrupt Enable
0: The Pipe Error interrupt is disabled.
1: The Pipe Error interrupt is enabled and an interrupt request will be generated when the Pipe Error interrupt Flag
is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Pipe Error interrupt Enable bit and disable the corresponding interrupt
request.
zBit 2 – TRFAIL: Transfer Fail Interrupt Enable
0: The Transfer Fail interrupt is disabled.
1: The Transfer Fail interrupt is enabled and an interrupt request will be generated when the Transfer Fail interrupt
Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Fail interrupt Enable bit and disable the corresponding interrupt
request.
Bit76543210
STALL TXSTP PERR TRFAIL TRCPT1 TRCPT0
Access R R RW1 RW1 RW1 RW1 RW1 RW1
Reset00000000
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zBit 1 – TRCPT1: Transfer Complete Bank 1 interrupt Enable
0: The Transfer Complete Bank 1 interrupt is disabled.
1: The Transfer Complete Bank 1 interrupt is enabled and an interrupt request will be generated when the Transfer
Complete interrupt Flag 1 is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Complete interrupt Enable bit 1 and disable the corresponding inter-
rupt request.
zBit 0 – TRCPT0: Transfer Complete Bank 0 interrupt Enable
0: The Transfer Complete Bank 0 interrupt is disabled.
1: The Transfer Complete Bank 0 interrupt is enabled and an interrupt request will be generated when the Transfer
Complete interrupt 0 Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Complete interrupt Enable bit 0 and disable the corresponding inter-
rupt request.
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29.8.6.8 Host Interrupt Pipe Set Register
Name: PINTENSET
Offset: 0x109 + (n x 0x20)
Reset: 0x0000
Property: Write-Protected
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Pipe Interrupt Enable Set (PINTENCLR) register.
This register is cleared by USB reset or when PEN[n] is zero.
zBits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 5 – STALL: Stall Interrupt Enable
0: The Stall interrupt is disabled.
1: The Stall interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Stall interrupt.
zBit 4 – TXSTP: Transmitted Setup Interrupt Enable
0: The Transmitted Setup interrupt is disabled.
1: The Transmitted Setup interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transmitted Setup interrupt.
zBit 3 – PERR: Pipe Error Interrupt Enable
0: The Pipe Error interrupt is disabled.
1: The Pipe Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Pipe Error interrupt.
zBit 2 – TRFAIL: Transfer Fail Interrupt Enable
0: The Transfer Fail interrupt is disabled.
1: The Transfer Fail interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Fail interrupt.
zBit 1 – TRCPT1: Transfer Complete 1 interrupt Enable
0: The Transfer Complete 1 interrupt is disabled.
1: The Transfer Complete 1 interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Complete interrupt Enable bit 1.
Bit76543210
STALL TXSTP PERR TRFAIL TRCPT1 TRCPT0
Access R R RW1 RW1 RW1 RW1 RW1 RW1
Reset00000000
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Atmel | SMART SAM R21 [DATASHEET]
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zBit 0 – TRCPT0: Transfer Complete 0 interrupt Enable
0: The Transfer Complete 0 interrupt is disabled.
1: The Transfer Complete 0 interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Complete interrupt Enable bit 0.
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29.8.7 Host Registers - Pipe RAM
29.8.7.1 Pipe Descriptor Structure
Pn BK0
EXTREG
PCKSIZE
ADDR DESCADD
Growing Memory Addresses
Descriptor P0
STATUS_BK
STATUS_PIPE
CTRL_PIPE
Reserved
Bank0
+0x000
+0x004
+0x008
+0x00A
+0x00C
+0x00E
+0x00F
Reserved
PCKSIZE
ADDR
STATUS_PIPE
CTRL_BK
Reserved
Bank1
+0x010
+0x014
+0x018
+0x01A
+0x01C
+0x01E
+0x01F
Pn BK1
Pipe descriptors
Data Buffers
EXTREG
PCKSIZE
ADDR
Descriptor Pn
STATUS_BK
STATUS_PIPE
CTRL_PIPE
Reserved
Bank0
Reserved
PCKSIZE
ADDR
STATUS_PIPE
CTRL_BK
Reserved
Bank1
2 x 0xn0
(2 x 0xn0) + 0x10
Reserved
Reserved
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29.8.7.2 Address of the Data Buffer
Name: ADDR
Offset: 0x00 & 0x10
Reset: 0xxxxxxxx
Property: NA
zBits 31:0 – ADDR[31:0]: Data Pointer Address Value
These bits define the data pointer address as an absolute double word address in RAM. The two least significant
bits must be zero to ensure the descriptor is 32-bit aligned.
Bit3130292827262524
+3 ADDR[31:24]
Access R/W R/W R/W R/W R/W R/W R/W R/W
ResetXXXXXXXX
Bit2322212019181716
+2 ADDR[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
ResetXXXXXXXX
Bit151413121110 9 8
+1 ADDR[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
ResetXXXXXXXX
Bit76543210
+0 ADDR[7:0]
Access R/W R/W R/W R/W R/W R/W R R
ResetXXXXXXXX
795
Atmel | SMART SAM R21 [DATASHEET]
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29.8.7.3 Packet Size
Name: PCKSIZE
Offset: 0x04 & 0x14
Reset: 0xxxxxxxx
Property: NA
zBit 31– AUTO_ZLP: Automatic Zero Length Packet
This bit defines the automatic Zero Length Packet mode of the pipe.
0: Automatic Zero Length Packet is disabled.
1: Automatic Zero Length Packet is enabled.
When enabled, the USB module will manage the ZLP handshake by hardware. This bit is for OUT pipes only.
When disabled the handshake should be managed by firmware.
zBits 30:28 – SIZE: Pipe size
These bits contains the size of the pipe.
Theses bits are cleared upon sending a USB reset.
Bit3130292827262524
+3 AUTO_ZLP SIZE[2:0] MULTI_PACKET_SIZE[13:10]
Access R/W R/W R/W R/W R/W R/W R/W R/W
ResetXXXXXXXX
Bit2322212019181716
+2 MULTI_PACKET_SIZE[9:2]
Access R/W R/W R/W R/W R/W R/W R/W R/W
ResetXXXXXXXX
Bit151413121110 9 8
+1 MULTI_PACKET_SIZE[1:0] BYTE-COUNT[13:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
ResetXXXXXXXX
Bit76543210
+0 BYTE_COUNT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
ResetXXXXXXXX
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Atmel | SMART SAM R21 [DATASHEET]
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(1) for Isochronous pipe only.
zBits 27:14 – MULTI_PACKET_SIZE: Multi Packet IN or OUT size
These bits define the 14-bit value that is used for multi-packet transfers.
For IN pipes, MULTI_PACKET_SIZE holds the total number of bytes sent. MULTI_PACKET_SIZE should be writ-
ten to zero when setting up a new transfer.
For OUT pipes, MULTI_PACKET_SIZE holds the total data size for the complete transfer. This value must be a
multiple of the maximum packet size.
zBits 13:0 – BYTE_COUNT: Byte Count
These bits define the 14-bit value that contains number of bytes sent in the last OUT or SETUP transaction for an
OUT pipe, or of the number of bytes to be received in the next IN transaction for an input pipe.
Table 29-28. Pipe Size
SIZE[2:0] Description
0x0 8 Byte
0x1 16 Byte
0x2 32 Byte
0x3 64 Byte
0x4 128 Byte (1)
0x5 256 Byte (1)
0x6 512 Byte (1)
0x7 1024 Byte in HS mode (1)
1023 Byte in FS mode (1)
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29.8.7.4 Extended Register
Name: EXTREG
Offset: 0x08
Reset: 0xxxxxxxx
Property: NA
zBits 15 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 14:4 – VARIABLE: Extended variable
These bits define the VARIABLE field sent with extended token. See “Section 2.1.1 Protocol Extension Token in
the reference document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum.”
To support the USB2.0 Link Power Management addition the VARIABLE field should be set as described below.
Table 29-29. VARIABLE bit fields for LPM application
zBits 3:0 – SUBPID: SUBPID
These bits define the SUBPID field sent with extended token. See “Section 2.1.1 Protocol Extension Token in the
reference document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum”.
To support the USB2.0 Link Power Management addition the SUBPID field should be set as described in “Table
2.2 SubPID Types in the reference document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Manage-
ment Addendum”.
Bit151413121110 9 8
+1 VARIABLE[10:4]
Access R R/W R/W R/W R/W R/W R/W R/W
ResetXXXXXXXX
Bit76543210
+0 VARIABLE[3:0] SUBPID[3:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
ResetXXXXXXXX
VARIABLE Description
VARIABLE[3:0] bLinkState (1)
1. for a definition of LPM Token bRemoteWake and bLinkState fields, refer to "Table 2-3 in the reference document ENGINEERING CHANGE NOTICE, USB
2.0 Link Power Management Addendum"
VARIABLE[7:4] BESL (See LPM ECN) (2)
2. for a definition of LPM Token BESL field, refer to "Table 2-3 in the reference document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power
Management Addendum" and "Table X-X1 in Errata for ECN USB 2.0 Link Power Management.
VARIABLE[8] bRemoteWake (1)
VARIABLE[10:9] Reserved
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29.8.7.5 Host Status Bank
Name: STATUS_BK
Offset: 0x0A & 0x1A
Reset: 0xxxxxxxx
Property: NA
zBits 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 2 – ERROFLOW: Error Flow Status
This bit defines the Error Flow Status.
0: No Error Flow detected.
1: A Error Flow has been detected.
This bit is set when a Error Flow has been detected during transfer from/towards this bank.
For IN transfer, a NAK handshake has been received. For OUT transfer, a NAK handshake has been received. For
Isochronous IN transfer, an overrun condition has occurred. For Isochronous OUT transfer, an underflow condition
has occurred.
zBit 0 – CRCERR: CRC Error
This bit defines the CRC Error Status.
0: No CRC Error.
1: CRC Error detected.
This bit is set when a CRC error has been detected in an isochronous IN endpoint bank.
Bit76543210
+0 ERROFLOW CRCERR
Access R/W R/W R/W R/W R/W R/W R/W R/W
ResetXXXXXXXX
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29.8.7.6 Host Control Pipe
Name: CTRL_PIPE
Offset: 0x0C
Reset: 0xxxxxxxx
Property: Write-Protected, Write-Synchronized, Read-Synchronized
zBits 15:12 – PERMAX: Pipe Error Max Number
These bits define the maximum number of error for this Pipe before freezing the pipe automatically.
zBits 11:8 – PEPNUM: Pipe EndPoint Number
These bits define the number of endpoint for this Pipe.
zBits 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 6:0 – PDADDR: Pipe Device Address
These bits define the Device Address for this pipe.
Bit151413121110 9 8
+1 PERMAX[3:0] PEPNUM[3:0]
Access R R/W R/W R/W R/W R/W R/W R/W
ResetXXXXXXXX
Bit76543210
+0 PDADDR[6:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
ResetXXXXXXXX
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29.8.7.7 Host Status Pipe
Name: STATUS_PIPE
Offset: 0x0E & 0x1E
Reset: 0xxxxxxxx
Property: Write-Protected, Write-Synchronized, Read-Synchronized
zBits 15:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 7:5 – ERCNT: Pipe Error Counter
These bits define the number of errors detected on the pipe.
zBit 4 – CRC16ER: CRC16 ERROR
This bit defines the CRC16 Error Status.
0: No CRC 16 Error detected.
1: A CRC 16 error has been detected.
This bit is set when a CRC 16 error has been detected during a IN transactions.
zBit 3 – TOUTER: TIME OUT ERROR
This bit defines the Time Out Error Status.
0: No Time Out Error detected.
1: A Time Out error has been detected.
This bit is set when a Time Out error has been detected during a USB transaction.
zBit 2 – PIDER: PID ERROR
This bit defines the PID Error Status.
0: No PID Error detected.
1: A PID error has been detected.
This bit is set when a PID error has been detected during a USB transaction.
zBit 1 – DAPIDER: Data PID ERROR
This bit defines the PID Error Status.
0: No Data PID Error detected.
1: A Data PID error has been detected.
This bit is set when a Data PID error has been detected during a USB transaction.
zBit 0 – DTGLER: Data Toggle Error
This bit defines the Data Toggle Error Status.
Bit151413121110 9 8
+1
Access R R/W R/W R/W R/W R/W R/W R/W
ResetXXXXXXXX
Bit76543210
+0 ERCNT[2:0] CRC16ER TOUTER PIDER DAPIDER DTGLER
AccessRRRRRR/WR/WR/W
ResetXXXXXXXX
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0: No Data Toggle Error.
1: Data Toggle Error detected.
This bit is set when a Data Toggle Error has been detected.
802
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30. ADC – Analog-to-Digital Converter
30.1 Overview
The Analog-to-Digital Converter (ADC) converts analog signals to digital values. The ADC has 12-bit resolution, and is
capable of converting up to 350ksps. The input selection is flexible, and both differential and single-ended measurements
can be performed. An optional gain stage is available to increase the dynamic range. In addition, several internal signal
inputs are available. The ADC can provide both signed and unsigned results.
ADC measurements can be started by either application software or an incoming event from another peripheral in the
device. ADC measurements can be started with predictable timing, and without software intervention.
Both internal and external reference voltages can be used.
An integrated temperature sensor is available for use with the ADC. The bandgap voltage as well as the scaled I/O and
core voltages can also be measured by the ADC.
The ADC has a compare function for accurate monitoring of user-defined thresholds, with minimum software intervention
required.
The ADC may be configured for 8-, 10- or 12-bit results, reducing the conversion time. ADC conversion results are
provided left- or right-adjusted, which eases calculation when the result is represented as a signed value. It is possible to
use DMA to move ADC results directly to memory or peripherals when conversions are done.
30.2 Features
z8-, 10- or 12-bit resolution
zUp to 350,000 samples per second (350ksps)
zDifferential and single-ended inputs
zUp to 8 analog inputs
z12 positive and 6 negative, including internal and external
zFour internal inputs
zBandgap
zTemperature sensor
zScaled core supply
zScaled I/O supply
z1/2x to 16x gain
zSingle, continuous and pin-scan conversion options
zWindowing monitor with selectable channel
zConversion range:
zVref [1v to VDDANA - 0.6V]
zADCx * GAIN [0V to -Vref ]
zBuilt-in internal reference and external reference options
zFour bits for reference selection
zEvent-triggered conversion for accurate timing (one event input)
zOptional DMA transfer of conversion result
zHardware gain and offset compensation
zAveraging and oversampling with decimation to support, up to 16-bit result
zSelectable sampling time
30.3 Block Diagram
Figure 30-1. ADC Block Diagram
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30.4 Signal Description
Note: 1. Refer to “Configuration Summary” on page 4 for details on exact number of analog input channels.
Refer to “I/O Multiplexing and Considerations” on page 12 for details on the pin mapping for this peripheral. One signal
can be mapped on several pins.
ADC
ADC0
ADCn
...
INT.SIG
ADC0
ADCn
INT.SIG
...
REFCTRL
INT1V
INTVCC
VREFB
OFFSETCORR
GAINCORRSWTRIG
EVCTRL
AVGCTRL
WINCTRL
SAMPCTRL WINUT
POST
PROCESSING
PRESCALER
CTRLA
WINLT
CTRLB
RESULT
INPUTCTRL
Signal Name Type Description
VREFB Analog input External reference voltage B
ADC[19..0](1) Analog input Analog input channels
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30.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
30.5.1 I/O Lines
Using the ADC's I/O lines requires the I/O pins to be configured using the port configuration (PORT).
Refer to “PORT” on page 373 for details.
30.5.2 Power Management
The ADC will continue to operate in any sleep mode where the selected source clock is running. The ADC’s interrupts
can be used to wake up the device from sleep modes. The events can trigger other operations in the system without
exiting the sleep modes. Refer to “PM – Power Manager” on page 112 for details on the different sleep modes.
30.5.3 Clocks
The ADC bus clock (CLK_ADC_APB) can be enabled and disabled in the Power Manager, and the default state of
CLK_ADC_APB can be found in the Table 14-1.
A generic clock (GCLK_ADC) is required to clock the ADC. This clock must be configured and enabled in the Generic
Clock Controller (GCLK) before using the ADC. Refer “GCLK – Generic Clock Controller” on page 90 for details.
This generic clock is asynchronous to the bus clock (CLK_ADC_APB). Due to this asynchronicity, writes to certain
registers will require synchronization between the clock domains. Refer to “Synchronization” on page 813 for further
details.
30.5.4 DMA
The DMA request lines are connected to the DMA controller (DMAC). Using the ADC DMA requests, requires the DMA
controller to be configured first. Refer ro “DMAC – Direct Memory Access Controller” on page 267 for details.
30.5.5 Interrupts
The interrupt request line is connected to the interrupt controller. Using ADC interrupts requires the interrupt controller to
be configured first. Refer to “Nested Vector Interrupt Controller” on page 29 for details.
30.5.6 Events
Events are connected to the Event System. Refer to “EVSYS – Event System” on page 400 for details.
30.5.7 Debug Operation
When the CPU is halted in debug mode, the ADC will halt normal operation. The ADC can be forced to continue
operation during debugging. Refer to the Debug Control register (DBGCTRL) for details.
30.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the
following register:
zInterrupt Flag Status and Clear register (INTFLAG)
Write-protection is denoted by the Write-Protection property in the register description.
When the CPU is halted in debug mode or the CPU reset is extended, all write-protection is automatically disabled.
Write-protection does not apply for accesses through an external debugger. Refer to “PAC – Peripheral Access
Controller” on page 36 for details.
30.5.9 Analog Connections
I/O-pins AIN0 to AIN19 as well as the VREFB reference voltage pin are analog inputs to the ADC.
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30.5.10 Calibration
The values BIAS_CAL and LINEARITY_CAL from the production test must be loaded from the NVM Software Calibration
Area into the ADC Calibration register (CALIB) by software to achieve specified accuracy.
Refer to “NVM Software Calibration Area Mapping” on page 26 for more details.
30.6 Functional Description
30.6.1 Principle of Operation
By default, the ADC provides results with 12-bit resolution. 8-bit or 10-bit results can be selected in order to reduce the
conversion time. The ADC has an oversampling with decimation option that can extend the resolution to 16 bits. The
input values can be either internal (e.g., internal temperature sensor) or external (connected I/O pins). The user can also
configure whether the conversion should be single-ended or differential.
30.6.2 Basic Operation
30.6.2.1 Initialization
Before enabling the ADC, the asynchronous clock source must be selected and enabled, and the ADC reference must be
configured. The first conversion after the reference is changed must not be used. All other configuration registers must
be stable during the conversion. The source for GCLK_ADC is selected and enabled in the System Controller
(SYSCTRL). Refer to “SYSCTRL – System Controller” on page 143 for more details.
When GCLK_ADC is enabled, the ADC can be enabled by writing a one to the Enable bit in the Control Register A
(CTRLA.ENABLE).
30.6.2.2 Enabling, Disabling and Reset
The ADC is enabled by writing a one to the Enable bit in the Control A register (CTRLA.ENABLE). The ADC is disabled
by writing a zero to CTRLA.ENABLE.
The ADC is reset by writing a one to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in the
ADC, except DBGCTRL, will be reset to their initial state, and the ADC will be disabled. Refer to the CTRLA register for
details.
The ADC must be disabled before it is reset.
30.6.2.3 Basic Operation
In the most basic configuration, the ADC sample values from the configured internal or external sources (INPUTCTRL
register). The rate of the conversion is dependent on the combination of the GCLK_ADC frequency and the clock
prescaler.
To convert analog values to digital values, the ADC needs first to be initialized, as described in “Initialization” on page
805. Data conversion can be started either manually, by writing a one to the Start bit in the Software Trigger register
(SWTRIG.START), or automatically, by configuring an automatic trigger to initiate the conversions. A free-running mode
could be used to continuously convert an input channel. There is no need for a trigger to start the conversion. It will start
automatically at the end of previous conversion.
The automatic trigger can be configured to trigger on many different conditions.
The result of the conversion is stored in the Result register (RESULT) as it becomes available, overwriting the result from
the previous conversion.
To avoid data loss if more than one channel is enabled, the conversion result must be read as it becomes available
(INTFLAG.RESRDY). Failing to do so will result in an overrun error condition, indicated by the OVERRUN bit in the
Interrupt Flag Status and Clear register (INTFLAG.OVERRUN).
To use an interrupt handler, the corresponding bit in the Interrupt Enable Set register (INTENSET) must be written to
one.
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30.6.3 Prescaler
The ADC is clocked by GCLK_ADC. There is also a prescaler in the ADC to enable conversion at lower clock rates.
Refer to CTRLB for details on prescaler settings.
Figure 30-2. ADC Prescaler
The propagation delay of an ADC measurement depends on the selected mode and is given by:
zSingle-shot mode:
zFree-running mode:
GCLK_ADC 9-BIT PRESCALER
CTRLB.PRESCALER[2:0]
DIV512
DIV256
DIV128
DIV64
DIV32
DIV16
DIV8
DIV4
CLK_ADC
PropagationDelay
1Resolution
2
---------------------------- DelayGain++
fCLK ADC–
--------------------------------------------------------------------------
=
PropagationDelay
Resolution
2
---------------------------- DelayGain+
fCLK ADC–
----------------------------------------------------------------
=
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30.6.4 ADC Resolution
The ADC supports 8-bit, 10-bit and 12-bit resolutions. Resolution can be changed by writing the Resolution bit group in
the Control B register (CTRLB.RESSEL). After a reset, the resolution is set to 12 bits by default.
30.6.5 Differential and Single-Ended Conversions
The ADC has two conversion options: differential and single-ended. When measuring signals where the positive input is
always at a higher voltage than the negative input, the single-ended conversion should be used in order to have full 12-
bit resolution in the conversion, which has only positive values. The negative input must be connected to ground. This
ground could be the internal GND, IOGND or an external ground connected to a pin. Refer to INPUTCTRL for selection
details. If the positive input may go below the negative input, creating some negative results, the differential mode should
be used in order to get correct results. The configuration of the conversion is done in the Differential Mode bit in the
Control B register (CTRLB.DIFFMODE). These two types of conversion could be run in single mode or in free-running
mode. When set up in free-running mode, an ADC input will continuously sample and do new conversions. The
INTFLAG.RESRDY bit will be set at the end of each conversion.
30.6.5.1 Conversion Timing
Figure 30-3 shows the ADC timing for a single conversion without gain. The writing of the ADC Start Conversion bit
(SWTRIG.START) or Start Conversion Event In bit (EVCTRL.STARTEI) must occur at least one CLK_ADC_APB cycle
before the CLK_ADC cycle on which the conversion starts. The input channel is sampled in the first half CLK_ADC
period. The sampling time can be increased by using the Sampling Time Length bit group in the Sampling Time Control
register (SAMPCTRL.SAMPLEN). Refer to Figure 30-4 for example on increased sampling time.
Table 30-1. Delay Gain
Delay Gain (in CLK_ADC Period)
INTPUTCTRL.GAIN[3:0]
Free-running mode Single shot mode
Name Differential Mode Single-Ended Mode Differential mode Single-Ended mode
1X 0x0 0 0 0 1
2X 0x1 0 1 0.5 1.5
4X 0x2 1 1 1 2
8X 0x3 1 2 1.5 2.5
16X 0x4 2 2 2 3
Reserved 0x5 ... 0xE Reserved Reserved Reserved Reserved
DIV2 0xF 0 1 0.5 1.5
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Figure 30-3. ADC Timing for One Conversion in Differential Mode without Gain
Figure 30-4. ADC Timing for One Conversion in Differential Mode without Gain, but with Increased Sampling Time
Figure 30-5. ADC Timing for Free Running in Differential Mode without Gain
12345678
C LK_ AD C
START
SAMPLE
INT
Converting Bi t
MSB10987654321LSB
12345678
C LK_ AD C
START
SAMPLE
INT
Converting Bi t
MSB10987654321LSB
91011
12345678
C LK_ AD C
START
SAMPLE
INT
Converting Bi t
9101112 13 14 15 16
1110987654321011 109876543210111098765
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Figure 30-6. ADC Timing for One Conversion in Single-Ended Mode without Gain
Figure 30-7. ADC Timing for Free Running in Single-Ended Mode without Gain
30.6.6 Accumulation
The result from multiple consecutive conversions can be accumulated. The number of samples to be accumulated is
specified by writing to the Number of Samples to be Collected field in the Average Control register
(AVGCTRL.SAMPLENUM) as described in Table 30-2. When accumulating more than 16 samples, the result will be too
large for the 16-bit RESULT register. To avoid overflow, the result is shifted right automatically to fit within the 16
available bits. The number of automatic right shifts are specified in Table 30-2. Note that to be able to perform the
accumulation of two or more samples, the Conversion Result Resolution field in the Control B register (CTRLB.RESSEL)
must be written to one.
Table 30-2. Accumulation
12345678
CLK_ADC
START
SAMPLE
INT
Converting Bit
91011
AMPLIFY
MSB10987654321LSB
12345678
C LK_ AD C
START
SAMPLE
INT
Converting Bi t
9101112 13 14 15 16
11109876543210 11 109876543210 1110
AMPLIFY
Number of
Accumulated Samples
AVGCTRL.
SAMPLENUM
Intermediate
Result Precision
Number of Automatic
Right Shifts
Final Result
Precision
Automatic
Division Factor
10x0 12 bits 012 bits 0
20x1 13 bits 013 bits 0
40x2 14 bits 014 bits 0
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30.6.7 Averaging
Averaging is a feature that increases the sample accuracy, though at the cost of reduced sample rate. This feature is
suitable when operating in noisy conditions. Averaging is done by accumulating m samples, as described in
“Accumulation” on page 809, and divide the result by m. The averaged result is available in the RESULT register. The
number of samples to be accumulated is specified by writing to AVGCTRL.SAMPLENUM as described in Table 30-3.
The division is obtained by a combination of the automatic right shift described above, and an additional right shift that
must be specified by writing to the Adjusting Result/Division Coefficient field in AVGCTRL (AVGCTRL.ADJRES) as
described in Table 30-3. Note that to be able to perform the averaging of two or more samples, the Conversion Result
Resolution field in the Control B register (CTRLB.RESSEL) must be written to one.
Averaging AVGCTRL.SAMPLENUM samples will reduce the effective sample rate by .
When the required average is reached, the INTFLAG.RESRDY bit is set.
Table 30-3. Averaging
80x3 15 bits 015 bits 0
16 0x4 16 bits 016 bits 0
32 0x5 17 bits 116 bits 2
64 0x6 18 bits 216 bits 4
128 0x7 19 bits 316 bits 8
256 0x8 20 bits 416 bits 16
512 0x9 21 bits 516 bits 32
1024 0xA 22 bits 616 bits 64
Reserved 0xB –0xF 12 bits 12 bits 0
Number of
Accumulated Samples
AVGCTRL.
SAMPLENUM
Intermediate
Result Precision
Number of Automatic
Right Shifts
Final Result
Precision
Automatic
Division Factor
1
AVGCTRL.SAMPLENUM
-------------------------------------------------------------------
Number of
Accumulated
Samples
AVGCTRL.
SAMPLENUM
Intermediate
Result
Precision
Number of
Automatic
Right Shifts
Division
Factor
AVGCTRL.
ADJRES
Total
Number
of Right
Shifts
Final
Result
Precision
Automatic
Division
Factor
10x0 12 bits 0 1 0x0 12 bits 0
20x1 13 0 2 0x1 112 bits 0
40x2 14 0 4 0x2 212 bits 0
80x3 15 0 8 0x3 312 bits 0
16 0x4 16 016 0x4 412 bits 0
32 0x5 17 116 0x4 512 bits 2
64 0x6 18 216 0x4 612 bits 4
128 0x7 19 316 0x4 712 bits 8
256 0x8 20 416 0x4 812 bits 16
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30.6.8 Oversampling and Decimation
By using oversampling and decimation, the ADC resolution can be increased from 12 bits to up to 16 bits. To increase
the resolution by n bits, 4n samples must be accumulated. The result must then be shifted right by n bits. This right shift is
a combination of the automatic right shift and the value written to AVGCTRL.ADJRES. To obtain the correct resolution,
the ADJRES must be configured as described in the table below. This method will result in n bit extra LSB resolution.
Table 30-4. Configuration Required for Oversampling and Decimation
30.6.9 Window Monitor
The window monitor allows the conversion result to be compared to some predefined threshold values. Supported
modes are selected by writing the Window Monitor Mode bit group in the Window Monitor Control register
(WINCTRL.WINMODE[2:0]). Thresholds are given by writing the Window Monitor Lower Threshold register (WINLT) and
Window Monitor Upper Threshold register (WINUT).
If differential input is selected, the WINLT and WINUT are evaluated as signed values. Otherwise they are evaluated as
unsigned values.
Another important point is that the significant WINLT and WINUT bits are given by the precision selected in the
Conversion Result Resolution bit group in the Control B register (CTRLB.RESSEL). This means that if 8-bit mode is
selected, only the eight lower bits will be considered. In addition, in differential mode, the eighth bit will be considered as
the sign bit even if the ninth bit is zero.
The INTFLAG.WINMON interrupt flag will be set if the conversion result matches the window monitor condition.
30.6.10 Offset and Gain Correction
Inherent gain and offset errors affect the absolute accuracy of the ADC. The offset error is defined as the deviation of the
actual ADC’s transfer function from an ideal straight line at zero input voltage. The offset error cancellation is handled by
the Offset Correction register (OFFSETCORR). The offset correction value is subtracted from the converted data before
writing the Result register (RESULT). The gain error is defined as the deviation of the last output step’s midpoint from the
ideal straight line, after compensating for offset error. The gain error cancellation is handled by the Gain Correction
register (GAINCORR). To correct these two errors, the Digital Correction Logic Enabled bit in the Control B register
(CTRLB.CORREN) must be written to one.
Offset and gain error compensation results are both calculated according to:
512 0x9 21 516 0x4 912 bits 32
1024 0xA 22 616 0x4 10 12 bits 64
Reserved 0xB –0xF 0x0 12 bits 0
Number of
Accumulated
Samples
AVGCTRL.
SAMPLENUM
Intermediate
Result
Precision
Number of
Automatic
Right Shifts
Division
Factor
AVGCTRL.
ADJRES
Total
Number
of Right
Shifts
Final
Result
Precision
Automatic
Division
Factor
Result
Resolution
Number of Samples
to Average AVGCTRL.SAMPLENUM[3:0]
Number of
Automatic Right
Shifts AVGCTRL.ADJRES[2:0]
13 bits 41 = 4 0x2 00x1
14 bits 42 = 16 0x4 00x2
15 bits 43 = 64 0x6 20x1
16 bits 44 = 256 0x8 40x0
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In single conversion, a latency of 13 GCLK_ADC is added to the availability of the final result. Since the correction time is
always less than the propagation delay, this latency appears in free-running mode only during the first conversion. After
that, a new conversion will be initialized when a conversion completes. All other conversion results are available at the
defined sampling rate.
Figure 30-8. ADC Timing Correction Enabled
30.6.11 DMA, Interrupts and Events
30.6.11.1 DMA Operation
The ADC generates the following DMA request:
zResult Conversion Ready (RESRDY): the request is set when a conversion result is available and cleared when
the RESULT register is read. When the averaging operation is enabled, the DMA request is set when the
averaging is completed and result is available.
30.6.11.2 Interrupts
The ADC has the following interrupt sources:
Result Conversion value OFFSETCORR–()GAINCORR⋅=
START
CONV0 CONV1 CONV2 CONV3
CORR0 CORR1 CORR2 CORR3
Table 30-5. Module Request for ADC
Condition Interrupt request Event output Event input DMA request
DMA request is
cleared
Result Ready x x x When result
register is read
Overrun x
Window Monitor x x
Synchronization
Ready x
Start Conversion x
ADC Flush x
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zResult Conversion Ready: RESRDY. This is an asynchronous interrupt and can be used to wake-up the device
from any sleep mode.
zOverrun: OVERRUN
zWindow Monitor: WINMON. This is an asynchronous interrupt and can be used to wake-up the device from any
sleep mode.
zSynchronization Ready: SYNCRDY. This is an asynchronous interrupt and can be used to wake-up the device
from any sleep mode.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one
to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR) register. An interrupt request is generated when the
interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag
is cleared, the interrupt is disabled or the peripheral is reset. An interrupt flag is cleared by writing a one to the
corresponding bit in the INTFLAG register. Each peripheral can have one interrupt request line per interrupt source or
one common interrupt request line for all the interrupt sources. This is device dependent.
Refer to “Nested Vector Interrupt Controller” on page 29 for details. If the peripheral has one common interrupt request
line for all the interrupt sources, the user must read the INTFLAG register to determine which interrupt condition is
present.
30.6.11.3 Events
The peripheral can generate the following output events:
zResult Ready (RESRDY)
zWindow Monitor (WINMON)
Output events must be enabled to be generated. Writing a one to an Event Output bit in the Event Control register
(EVCTRL.xxEO) enables the corresponding output event. Writing a zero to this bit disables the corresponding output
event. The events must be correctly routed in the Event System. Refer to “EVSYS – Event System” on page 400 for
details.
The peripheral can take the following actions on an input event:
zADC start conversion (START)
zADC conversion flush (FLUSH)
Input events must be enabled for the corresponding action to be taken on any input event. Writing a one to an Event
Input bit in the Event Control register (EVCTRL.xxEI) enables the corresponding action on the input event. Writing a zero
to this bit disables the corresponding action on the input event. Note that if several events are connected to the
peripheral, the enabled action will be taken on any of the incoming events. The events must be correctly routed in the
Event System. Refer to “EVSYS – Event System” on page 400 for details.
30.6.12 Sleep Mode Operation
The Run in Standby bit in the Control A register (CTRLA.RUNSTDBY) controls the behavior of the ADC during standby
sleep mode. When the bit is zero, the ADC is disabled during sleep, but maintains its current configuration. When
the bit is one, the ADC continues to operate during sleep. Note that when RUNSTDBY is zero, the analog
blocks are powered off for the lowest power consumption. This necessitates a start-up time delay when the system
returns from sleep.
When RUNSTDBY is one, any enabled ADC interrupt source can wake up the CPU. While the CPU is sleeping, ADC
conversion can only be triggered by events.
30.6.13 Synchronization
Due to the asynchronicity between CLK_ADC_APB and GCLK_ADC, some registers must be synchronized when
accessed. A register can require:
zSynchronization when written
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zSynchronization when read
zSynchronization when written and read
zNo synchronization
When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. The Synchronization
Ready interrupt can be used to signal when synchronization is complete.
If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is
stalled.
The following bits need synchronization when written:
zSoftware Reset bit in the Control A register (CTRLA.SWRST)
zEnable bit in the Control A register (CTRLA.ENABLE)
The following registers need synchronization when written:
zControl B (CTRLB)
zSoftware Trigger (SWTRIG)
zWindow Monitor Control (WINCTRL)
zInput Control (INPUTCTRL)
zWindow Upper/Lower Threshold (WINUT/WINLT)
Write-synchronization is denoted by the Write-Synchronized property in the register description.
The following registers need synchronization when read:
zSoftware Trigger (SWTRIG)
zInput Control (INPUTCTRL)
zResult (RESULT)
Read-synchronization is denoted by the Read-Synchronized property in the register description.
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30.7 Register Summary
Table 30-6. Register Summary
Offset Name
Bit
Pos.
0x00 CTRLA 7:0 RUNSTDBY ENABLE SWRST
0x01 REFCTRL 7:0 REFCOMP REFSEL[3:0]
0x02 AVGCTRL 7:0 ADJRES[2:0] SAMPLENUM[3:0]
0x03 SAMPCTRL 7:0 SAMPLEN[5:0]
0x04
CTRLB
7:0 RESSEL[1:0] CORREN FREERUN LEFTADJ DIFFMODE
0x05 15:8 PRESCALER[2:0]
0x06 Reserved
0x07 Reserved
0x08 WINCTRL 7:0 WINMODE[2:0]
0x09
...
0x0B
Reserved
0x0C SWTRIG 7:0 START FLUSH
0x0D
...
0x0F
Reserved
0x10
INPUTCTRL
7:0 MUXPOS[4:0]
0x11 15:8 MUXNEG[4:0]
0x12 23:16 INPUTOFFSET[3:0] INPUTSCAN[3:0]
0x13 31:24 GAIN[3:0]
0x14 EVCTRL 7:0 WINMONEO RESRDYEO SYNCEI STARTEI
0x15 Reserved
0x16 INTENCLR 7:0 SYNCRDY WINMON OVERRUN RESRDY
0x17 INTENSET 7:0 SYNCRDY WINMON OVERRUN RESRDY
0x18 INTFLAG 7:0 SYNCRDY WINMON OVERRUN RESRDY
0x19 STATUS 7:0 SYNCBUSY
0x1A
RESULT
7:0 RESULT[7:0]
0x1B 15:8 RESULT[15:8]
0x1C
WINLT
7:0 WINLT[7:0]
0x1D 15:8 WINLT[15:8]
0x1E Reserved
0x1F Reserved
0x20
WINUT
7:0 WINUT[7:0]
0x21 15:8 WINUT[15:8]
0x22 Reserved
0x23 Reserved
0x24
GAINCORR
7:0 GAINCORR[7:0]
0x25 15:8 GAINCORR[11:8]
0x26 OFFSETCOR
R
7:0 OFFSETCORR[7:0]
0x27 15:8 OFFSETCORR[11:8]
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0x28
CALIB
7:0 LINEARITY_CAL[7:0]
0x29 15:8 BIAS_CAL[2:0]
0x2A DBGCTRL 7:0 DBGRUN
Offset Name
Bit
Pos.
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30.8 Register Description
Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters
and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by
the Write-Protected property in each individual register description. Refer to “Register Access Protection” on page 804
for details.
Some registers require synchronization when read and/or written. Synchronization is denoted by the Write-Synchronized
or the Read-Synchronized property in each individual register description. Refer to “Synchronization” on page 813 for
details.
Some registers are enable-protected, meaning they can be written only when the ADC is disabled. Enable-protection is
denoted by the Enable-Protected property in each individual register description.
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30.8.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: Write-Protected
zBits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 2 – RUNSTDBY: Run in Standby
This bit indicates whether the ADC will continue running in standby sleep mode or not:
0: The ADC is halted during standby sleep mode.
1: The ADC continues normal operation during standby sleep mode.
zBit 1 – ENABLE: Enable
0: The ADC is disabled.
1: The ADC is enabled.
Due to synchronization, there is a delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRL.ENABLE will read back immediately and the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete.
zBit 0 – SWRST: Software Reset
0: There is no reset operation ongoing.
1: The reset operation is ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the ADC, except DBGCTRL, to their initial state, and the ADC will be
disabled.
Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-oper-
ation will be discarded.
Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST
and STATUS.SYNCBUSY will both be cleared when the reset is complete.
Bit 76543210
RUNSTDBY
ENABLE SWRST
AccessRRRRRR/WR/WR/W
Reset00000000
819
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
30.8.2 Reference Control
Name: REFCTRL
Offset: 0x01
Reset: 0x00
Property: Write-Protected
zBit 7 – REFCOMP: Reference Buffer Offset Compensation Enable
The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will
decrease the input impedance and thus increase the start-up time of the reference.
0: Reference buffer offset compensation is disabled.
1: Reference buffer offset compensation is enabled.
zBits 6:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 3:0 – REFSEL[3:0]: Reference Selection
These bits select the reference for the ADC according to Table 30-7.
Table 30-7. Reference Selection
Bit 76543210
REFCOMP REFSEL[3:0]
Access R/W R R R R/W R/W R/W R/W
Reset00000000
REFSEL[3:0] Name Description
0x0 INT1V 1.0V voltage reference
0x1 INTVCC0 1/1.48 VDDANA
0x2 INTVCC1 1/2 VDDANA (only for VDDANA > 2.0V)
0x3 -Reserved
0x4 VREFB External reference
0x5-0xF -Reserved
820
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
30.8.3 Average Control
Name: AVGCTRL
Offset: 0x02
Reset: 0x00
Property: Write-Protected
zBit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 6:4 – ADJRES[2:0]: Adjusting Result / Division Coefficient
These bits define the division coefficient in 2n steps.
zBits 3:0 – SAMPLENUM[3:0]: Number of Samples to be Collected
These bits define how many samples should be added together.The result will be available in the Result register
(RESULT). Note: if the result width increases, CTRLB.RESSEL must be changed.
Table 30-8. Number of Samples to be Collected
Bit 76543210
ADJRES[2:0] SAMPLENUM[3:0]
Access R R/W R/W R/W R/W R/W R/W R/W
Reset00000000
SAMPLENUM[3:0] Name Description
0x0 11 sample
0x1 22 samples
0x2 44 samples
0x3 88 samples
0x4 16 16 samples
0x5 32 32 samples
0x6 64 64 samples
0x7 128 128 samples
0x8 256 256 samples
0x9 512 512 samples
0xA 1024 1024 samples
0xB-0xF Reserved
821
Atmel | SMART SAM R21 [DATASHEET]
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30.8.4 Sampling Time Control
Name: SAMPCTRL
Offset: 0x03
Reset: 0x00
Property: Write-Protected
zBits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 5:0 – SAMPLEN[5:0]: Sampling Time Length
These bits control the ADC sampling time in number of half CLK_ADC cycles, depending of the prescaler value,
thus controlling the ADC input impedance. Sampling time is set according to the equation:
Bit 76543210
SAMPLEN[5:0]
Access R R R/W R/W R/W R/W R/W R/W
Reset00000000
Sampling time SAMPLEN 1+()
CLKADC
2
----------------------
⎝⎠
⎛⎞
⋅=
822
Atmel | SMART SAM R21 [DATASHEET]
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30.8.5 Control B
Name: CTRLB
Offset: 0x04
Reset: 0x0000
Property: Write-Protected, Write-Synchronized
zBits 15:11 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 10:8 – PRESCALER[2:0]: Prescaler Configuration
These bits define the ADC clock relative to the peripheral clock according to Table 30-9.
Table 30-9. Prescaler Configuration
zBits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 5:4 – RESSEL[1:0]: Conversion Result Resolution
These bits define whether the ADC completes the conversion at 12-, 10- or 8-bit result resolution.
Bit 151413121110 9 8
PRESCALER[2:0]
AccessRRRRRR/WR/WR/W
Reset00000000
Bit 76543210
RESSEL[1:0] CORREN FREERUN LEFTADJ
DIFFMODE
Access R R R/W R/W R/W R/W R/W R/W
Reset00000000
PRESCALER[2:0] Name Description
0x0 DIV4 Peripheral clock divided by 4
0x1 DIV8 Peripheral clock divided by 8
0x2 DIV16 Peripheral clock divided by 16
0x3 DIV32 Peripheral clock divided by 32
0x4 DIV64 Peripheral clock divided by 64
0x5 DIV128 Peripheral clock divided by 128
0x6 DIV256 Peripheral clock divided by 256
0x7 DIV512 Peripheral clock divided by 512
823
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Table 30-10. Conversion Result Resolution
zBit 3 – CORREN: Digital Correction Logic Enabled
0: Disable the digital result correction.
1: Enable the digital result correction. The ADC conversion result in the RESULT register is then corrected for gain
and offset based on the values in the GAINCAL and OFFSETCAL registers. Conversion time will be increased by
X cycles according to the value in the Offset Correction Value bit group in the Offset Correction register.
zBit 2 – FREERUN: Free Running Mode
0: The ADC run is single conversion mode.
1: The ADC is in free running mode and a new conversion will be initiated when a previous conversion completes.
zBit 1 – LEFTADJ: Left-Adjusted Result
0: The ADC conversion result is right-adjusted in the RESULT register.
1: The ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be
present in the upper part of the result register. Writing this bit to zero (default) will right-adjust the value in the
RESULT register.
zBit 0 – DIFFMODE: Differential Mode
0: The ADC is running in singled-ended mode.
1: The ADC is running in differential mode. In this mode, the voltage difference between the MUXPOS and MUX-
NEG inputs will be converted by the ADC.
RESSEL[1:0] Name Description
0x0 12BIT 12-bit result
0x1 16BIT For averaging mode output
0x2 10BIT 10-bit result
0x3 8BIT 8-bit result
824
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30.8.6 Window Monitor Control
Name: WINCTRL
Offset: 0x08
Reset: 0x00
Property: Write-Protected, Write-Synchronized
zBits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 2:0 – WINMODE[2:0]: Window Monitor Mode
These bits enable and define the window monitor mode. Table 30-11 shows the mode selections.
Table 30-11. Window Monitor Mode
Bit 76543210
WINMODE[2:0]
AccessRRRRRR/WR/WR/W
Reset00000000
WINMODE[2:0] Name Description
0x0 DISABLE No window mode (default)
0x1 MODE1 Mode 1: RESULT > WINLT
0x2 MODE2 Mode 2: RESULT < WINUT
0x3 MODE3 Mode 3: WINLT < RESULT < WINUT
0x4 MODE4 Mode 4: !(WINLT < RESULT < WINUT)
0x5-0x7 Reserved
825
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
30.8.7 Software Trigger
Name: SWTRIG
Offset: 0x0C
Reset: 0x00
Property: Write-Protected, Write-Synchronized
zBits 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 1 – START: ADC Start Conversion
0: The ADC will not start a conversion.
1: The ADC will start a conversion. The bit is cleared by hardware when the conversion has started. Setting this bit
when it is already set has no effect.
Writing this bit to zero will have no effect.
zBit 0 – FLUSH: ADC Conversion Flush
0: No flush action.
1: The ADC pipeline will be flushed. A flush will restart the ADC clock on the next peripheral clock edge, and all
conversions in progress will be aborted and lost. This bit is cleared until the ADC has been flushed.
After the flush, the ADC will resume where it left off; i.e., if a conversion was pending, the ADC will start a new
conversion.
Writing this bit to zero will have no effect.
Bit 76543210
START FLUSH
AccessRRRRRRR/WR/W
Reset00000000
826
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
30.8.8 Input Control
Name: INPUTCTRL
Offset: 0x10
Reset: 0x00000000
Property: Write-Protected, Write-Synchronized
zBits 31:28 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 27:24 – GAIN[3:0]: Gain Factor Selection
These bits set the gain factor of the ADC gain stage according to the values shown in Table 30-12.
Table 30-12. Gain Factor Selection
Bit 3130292827262524
GAIN[3:0]
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 2322212019181716
INPUTOFFSET[3:0] INPUTSCAN[3:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 151413121110 9 8
MUXNEG[4:0]
Access R R R R/W R/W R/W R/W R/W
Reset00000000
Bit 76543210
MUXPOS[4:0]
Access R R R R/W R/W R/W R/W R/W
Reset00000000
GAIN[3:0] Name Description
0x0 1X 1x
0x1 2X 2x
0x2 4X 4x
0x3 8X 8x
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zBits 23:20 – INPUTOFFSET[3:0]: Positive Mux Setting Offset
The pin scan is enabled when INPUTSCAN != 0. Writing these bits to a value other than zero causes the first con-
version triggered to be converted using a positive input equal to MUXPOS + INPUTOFFSET. Setting this register
to zero causes the first conversion to use a positive input equal to MUXPOS.
After a conversion, the INPUTOFFSET register will be incremented by one, causing the next conversion to be
done with the positive input equal to MUXPOS + INPUTOFFSET. The sum of MUXPOS and INPUTOFFSET gives
the input that is actually converted.
zBits 19:16 – INPUTSCAN[3:0]: Number of Input Channels Included in Scan
This register gives the number of input sources included in the pin scan. The number of input sources included is
INPUTSCAN + 1. The input channels included are in the range from MUXPOS + INPUTOFFSET to MUXPOS +
INPUTOFFSET + INPUTSCAN.
The range of the scan mode must not exceed the number of input channels available on the device.
zBits 15:13 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 12:8 – MUXNEG[4:0]: Negative Mux Input Selection
These bits define the Mux selection for the negative ADC input. Table 30-13 shows the possible input selections.
0x4 16X 16x
0x5-0xE Reserved
0xF DIV2 1/2x
Table 30-13. Negative Mux Input Selection
Value Name Description
0x00 PIN0 Reserved
0x01 PIN1 Reserved
0x02 PIN2 Reserved
0x03 PIN3 Reserved
0x04 PIN4 ADC AIN4 pin(1)
0x05 PIN5 ADC AIN5 pin(1)
0x06 PIN6 ADC AIN6 pin
0x07 PIN7 ADC AIN7 pin
0x08-0x17 –Reserved
0x18 GND Internal ground
0x19 IOGND I/O ground
0x1A-0x1F –Reserved
Note: 1. Only available in SAM R21G.
GAIN[3:0] Name Description
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zBits 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 4:0 – MUXPOS[4:0]: Positive Mux Input Selection
These bits define the Mux selection for the positive ADC input. Table 30-14 shows the possible input selections. If
the internal bandgap voltage or temperature sensor input channel is selected, then the Sampling Time Length bit
group in the SamplingControl register must be written.
Table 30-14. Positive Mux Input Selection
MUXPOS[4:0] Group configuration Description
0x00 Reserved
0x01 Reserved
0x02 Reserved
0x03 Reserved
0x04 PIN4 ADC AIN4 pin(1)
0x05 PIN5 ADC AIN5 pin(1)
0x06 PIN6 ADC AIN6 pin
0x07 PIN7 ADC AIN7 pin
0x08 Reserved
0x09 Reserved
0x0A PIN10 ADC AIN10 pin(1)
0x0B PIN11 ADC AIN11 pin(1)
0x0C Reserved
0x0D Reserved
0x0E Reserved
0x0F Reserved
0x10 PIN16 ADC AIN16 pin
0x11 PIN17 ADC AIN17 pin
0x12-0x17 Reserved
0x18 TEMP Temperature reference
0x19 BANDGAP Bandgap voltage
0x1A SCALEDCOREVCC 1/4 scaled core supply
0x1B SCALEDIOVCC 1/4 scaled I/O supply
0x1C-0x1F Reserved
Note: 1. Only available in SAM R21G.
829
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30.8.9 Event Control
Name: EVCTRL
Offset: 0x14
Reset: 0x00
Property: Write-Protected
zBits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 5 – WINMONEO: Window Monitor Event Out
This bit indicates whether the Window Monitor event output is enabled or not and an output event will be gener-
ated when the window monitor detects something.
0: Window Monitor event output is disabled and an event will not be generated.
1: Window Monitor event output is enabled and an event will be generated.
zBit 4 – RESRDYEO: Result Ready Event Out
This bit indicates whether the Result Ready event output is enabled or not and an output event will be generated
when the conversion result is available.
0: Result Ready event output is disabled and an event will not be generated.
1: Result Ready event output is enabled and an event will be generated.
zBits 3:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 1 – SYNCEI: Synchronization Event In
0: A flush and new conversion will not be triggered on any incoming event.
1: A flush and new conversion will be triggered on any incoming event.
zBit 0 – STARTEI: Start Conversion Event In
0: A new conversion will not be triggered on any incoming event.
1: A new conversion will be triggered on any incoming event.
Bit 76543210
WINMONEO RESRDYEO
SYNCEI STARTEI
Access R R R/W R/W R R R/W R/W
Reset00000000
830
Atmel | SMART SAM R21 [DATASHEET]
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30.8.10 Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x16
Reset: 0x00
Property: Write-Protected
zBits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 3 – SYNCRDY: Synchronization Ready Interrupt Enable
0: The Synchronization Ready interrupt is disabled.
1: The Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the Synchroni-
zation Ready interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Enable bit and the corresponding interrupt
request.
zBit 2 – WINMON: Window Monitor Interrupt Enable
0: The window monitor interrupt is disabled.
1: The window monitor interrupt is enabled, and an interrupt request will be generated when the Window Monitor
interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Window Monitor Interrupt Enable bit and the corresponding interrupt request.
zBit 1 – OVERRUN: Overrun Interrupt Enable
0: The Overrun interrupt is disabled.
1: The Overrun interrupt is enabled, and an interrupt request will be generated when the Overrun interrupt flag is
set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overrun Interrupt Enable bit and the corresponding interrupt request.
zBit 0 – RESRDY: Result Ready Interrupt Enable
0: The Result Ready interrupt is disabled.
1: The Result Ready interrupt is enabled, and an interrupt request will be generated when the Result Ready inter-
rupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Result Ready Interrupt Enable bit and the corresponding interrupt request.
Bit 76543210
SYNCRDY WINMON OVERRUN RESRDY
AccessRRRRR/WR/WR/WR/W
Reset00000000
831
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30.8.11 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name: INTENSET
Offset: 0x17
Reset: 0x00
Property: Write-Protected
zBits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 3 – SYNCRDY: Synchronization Ready Interrupt Enable
0: The Synchronization Ready interrupt is disabled.
1: The Synchronization Ready interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Synchronization Ready Interrupt Enable bit, which enables the Synchronization
Ready interrupt.
zBit 2 – WINMON: Window Monitor Interrupt Enable
0: The Window Monitor interrupt is disabled.
1: The Window Monitor interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Window Monitor Interrupt bit and enable the Window Monitor interrupt.
zBit 1 – OVERRUN: Overrun Interrupt Enable
0: The Overrun interrupt is disabled.
1: The Overrun interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overrun Interrupt bit and enable the Overrun interrupt.
zBit 0 – RESRDY: Result Ready Interrupt Enable
0: The Result Ready interrupt is disabled.
1: The Result Ready interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Result Ready Interrupt bit and enable the Result Ready interrupt.
Bit 76543210
SYNCRDY WINMON OVERRUN RESRDY
AccessRRRRR/WR/WR/WR/W
Reset00000000
832
Atmel | SMART SAM R21 [DATASHEET]
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30.8.12 Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x18
Reset: 0x00
Property: -
zBits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 3 – SYNCRDY: Synchronization Ready
This flag is cleared by writing a one to the flag.
This flag is set on a one-to-zero transition of the Synchronization Busy bit in the Status register (STATUS.SYNC-
BUSY), except when caused by an enable or software reset, and will generate an interrupt request if
INTENCLR/SET.SYNCRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Synchronization Ready interrupt flag.
zBit 2 – WINMON: Window Monitor
This flag is cleared by writing a one to the flag or by reading the RESULT register.
This flag is set on the next GCLK_ADC cycle after a match with the window monitor condition, and an interrupt
request will be generated if INTENCLR/SET.WINMON is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Window Monitor interrupt flag.
zBit 1 – OVERRUN: Overrun
This flag is cleared by writing a one to the flag.
This flag is set if RESULT is written before the previous value has been read by CPU, and an interrupt request will
be generated if INTENCLR/SET.OVERRUN is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Overrun interrupt flag.
zBit 0 – RESRDY: Result Ready
This flag is cleared by writing a one to the flag or by reading the RESULT register.
This flag is set when the conversion result is available, and an interrupt will be generated if INTEN-
CLR/SET.RESRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Result Ready interrupt flag.
Bit 76543210
SYNCRDY WINMON OVERRUN RESRDY
AccessRRRRR/WR/WR/WR/W
Reset00000000
833
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
30.8.13 Status
Name: STATUS
Offset: 0x19
Reset: 0x00
Property: -
zBit 7 – SYNCBUSY: Synchronization Busy
This bit is cleared when the synchronization of registers between the clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
zBits 6:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit 76543210
SYNCBUSY
AccessRRRRRRRR
Reset00000000
834
Atmel | SMART SAM R21 [DATASHEET]
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30.8.14 Result
Name: RESULT
Offset: 0x1A
Reset: 0x0000
Property: Read-Synchronized
zBits 15:0 – RESULT[15:0]: Result Conversion Value
These bits will hold up to a 16-bit ADC result, depending on the configuration.
In single-ended without averaging mode, the ADC conversion will produce a 12-bit result, which can be left- or
right-shifted, depending on the setting of CTRLB.LEFTADJ.
If the result is left-adjusted (CTRLB.LEFTADJ), the high byte of the result will be in bit position [15:8], while the
remaining 4 bits of the result will be placed in bit locations [7:4]. This can be used only if an 8-bit result is required;
i.e., one can read only the high byte of the entire 16-bit register.
If the result is not left-adjusted (CTRLB.LEFTADJ) and no oversampling is used, the result will be available in bit
locations [11:0], and the result is then 12 bits long.
If oversampling is used, the result will be located in bit locations [15:0], depending on the settings of the Average
Control register (AVGCTRL).
Bit 151413121110 9 8
RESULT[15:8]
AccessRRRRRRRR
Reset00000000
Bit 76543210
RESULT[7:0]
AccessRRRRRRRR
Reset00000000
835
Atmel | SMART SAM R21 [DATASHEET]
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30.8.15 Window Monitor Lower Threshold
Name: WINLT
Offset: 0x1C
Reset: 0x0000
Property: Write-Protected, Write-Synchronized
zBits 15:0 – WINLT[15:0]: Window Lower Threshold
If the window monitor is enabled, these bits define the lower threshold value.
Bit 151413121110 9 8
WINLT[15:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
WINLT[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
836
Atmel | SMART SAM R21 [DATASHEET]
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30.8.16 Window Monitor Upper Threshold
Name: WINUT
Offset: 0x20
Reset: 0x0000
Property: Write-Protected, Write-Synchronized
zBits 15:0 – WINUT[15:0]: Window Upper Threshold
If the window monitor is enabled, these bits define the upper threshold value.
Bit 151413121110 9 8
WINUT[15:8]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit 76543210
WINUT[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
837
Atmel | SMART SAM R21 [DATASHEET]
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30.8.17 Gain Correction
Name: GAINCORR
Offset: 0x24
Reset: 0x0000
Property: Write-Protected
zBits 15:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 11:0 – GAINCORR[11:0]: Gain Correction Value
If the CTRLB.CORREN bit is one, these bits define how the ADC conversion result is compensated for gain error
before being written to the result register. The gaincorrection is a fractional value, a 1-bit integer plusan 11-bit frac-
tion, and therefore 1/2 <= GAINCORR < 2. GAINCORR values range from 0.10000000000 to 1.11111111111.
Bit 151413121110 9 8
GAINCORR[11:8]
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 76543210
GAINCORR[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
838
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
30.8.18 Offset Correction
Name: OFFSETCORR
Offset: 0x26
Reset: 0x0000
Property: Write-Protected
zBits 15:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 11:0 – OFFSETCORR[11:0]: Offset Correction Value
If the CTRLB.CORREN bit is one, these bits define how the ADC conversion result is compensated for offset error
before being written to the Result register. This OFFSETCORR value is in two's complement format.
Bit 151413121110 9 8
OFFSETCORR[11:8]
AccessRRRRR/WR/WR/WR/W
Reset00000000
Bit 76543210
OFFSETCORR[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
839
Atmel | SMART SAM R21 [DATASHEET]
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30.8.19 Calibration
Name: CALIB
Offset: 0x28
Reset: 0x0000
Property: Write-Protected
zBits 15:11 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 10:8 – BIAS_CAL[2:0]: Bias Calibration Value
This value from production test must be loaded from the NVM software calibration area into the CALIB register by
software to achieve the specified accuracy.
The value must be copied only, and must not be changed.
zBits 7:0 – LINEARITY_CAL[7:0]: Linearity Calibration Value
This value from production test must be loaded from the NVM software calibration area into the CALIB register by
software to achieve the specified accuracy.
The value must be copied only, and must not be changed.
Bit 151413121110 9 8
BIAS_CAL[2:0]
AccessRRRRRR/WR/WR/W
Reset00000000
Bit 76543210
LINEARITY_CAL[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
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30.8.20 Debug Control
Name: DBGCTRL
Offset: 0x2A
Reset: 0x00
Property: Write-Protected
zBits 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 0 – DBGRUN: Debug Run
0: The ADC is halted during debug mode.
1: The ADC continues normal operation during debug mode.
This bit can be changed only while the ADC is disabled.
This bit should be written only while a conversion is not ongoing.
Bit 76543210
DBGRUN
AccessRRRRRRRR/W
Reset00000000
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31. AC – Analog Comparators
31.1 Overview
The Analog Comparator (AC) supports two individual comparators. Each comparator (COMP) compares the voltage
levels on two inputs, and provides a digital output based on this comparison. Each comparator may be configured to
generate interrupt requests and/or peripheral events upon several different combinations of input change.
Hysteresis and propagation delay are two important properties of the comparators; dynamic behavior. Both parameters
may be adjusted to achieve the optimal operation for each application.
The input selection includes four shared analog port pins and several internal signals. Each comparator output state can
also be output on a pin for use by external devices.
The comparators are always grouped in pairs on each port. The AC module may implement one pair. These are called
Comparator 0 (COMP0) and Comparator 1 (COMP1). They have identical behaviors, but separate control registers. The
pair can be set in window mode to compare a signal to a voltage range instead of a single voltage level.
31.2 Features
zTwo individual comparators
zSelectable propagation delay versus current consumption
zSelectable hysteresis
zOn/Off
zAnalog comparator outputs available on pins
zAsynchronous or synchronous
zFlexible input selection
zFour pins selectable for positive or negative inputs
zGround (for zero crossing)
zBandgap reference voltage
z64-level programmable VDDANA scaler per comparator
z Interrupt generation on:
zRising or falling edge
zToggle
zEnd of comparison
zWindow function interrupt generation on:
zSignal above window
zSignal inside window
zSignal below window
zSignal outside window
zEvent generation on:
zComparator output
zWindow function inside/outside window
zOptional digital filter on comparator output
zLow-power option
zSingle-shot support
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31.3 Block Diagram
Figure 31-1. Analog Comparator Block Diagram
31.4 Signal Description
Refer to “I/O Multiplexing and Considerations” on page 12 for details on the pin mapping for this peripheral. One signal
can be mapped on several pins.
31.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
31.5.1 I/O Lines
Using the AC’s I/O lines requires the I/O pins to be configured. Refer to the PORT chapter for details.
Refer to “PORT” on page 373 for details.
INTERRUPT MODE
ENABLE
ENABLE
HYSTERESIS
HYSTERESIS
VDDANA
SCALER
BANDGAP
+
-
+
-
CMP0
CMP1
INTERRUPTS
EVENTS
GCLK_AC
AIN3
AIN2
AIN1
AIN0
COMP0
COMP1
COMPCTRLn WINCTRL
INTERRUPT
SENSITIVITY
CONTROL
&
WINDOW
FUNCTION
Signal Name Type Description
AIN[3..0] Analog input Comparator inputs
CMP[1..0] Digital output Comparator outputs
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31.5.2 Power Management
The AC will continue to operate in any sleep mode where the selected source clock is running. The AC’s interrupts can
be used to wake up the device from sleep modes. The events can trigger other operations in the system without exiting
sleep modes. Refer to “PM – Power Manager” on page 112 for details on the different sleep modes.
31.5.3 Clocks
The AC bus clock (CLK_AC_APB) can be enabled and disabled in the Power Manager, and the default state of the
CLK_AC_APB can be found in the Peripheral Clock Masking section of “PM – Power Manager” on page 112.
Two generic clocks (GCLK_AC_DIG and GCLK_AC_ANA) are used by the AC. The digital clock (GCLK_AC_DIG) is
required to provide the sampling rate for the comparators, while the analog clock (GCLK_AC_ANA) is required for low-
voltage operation (VDDANA < 2.5V) to ensure that the resistance of the analog input multiplexors remains low. These
clocks must be configured and enabled in the Generic Clock Controller before using the peripheral.
Refer to “GCLK – Generic Clock Controller” on page 90 for details.
These generic clocks are asynchronous to the CLK_AC_APB clock. Due to this asynchronicity, writes to certain registers
will require synchronization between the clock domains. Refer to “Synchronization” on page 853 for further details.
31.5.4 DMA
Not applicable.
31.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the AC interrupts requires the Interrupt Controller
to be configured first. Refer to “Nested Vector Interrupt Controller” on page 29 for details.
31.5.6 Events
The events are connected to the Event System. Using the events requires the Event System to be configured first. Refer
to “EVSYS – Event System” on page 400 for details.
31.5.7 Debug Operation
When the CPU is halted in debug mode, the peripheral continues normal operation. If the peripheral is configured in a
way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss
may result during debugging.
31.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the
following registers:
zControl B register (CTRLB)
zInterrupt Flag register (INTFLAG)
Write-protection is denoted by the Write-Protected property in the register description.
Write-protection does not apply for accesses through an external debugger. Refer to “PAC – Peripheral Access
Controller” on page 36 for details.
31.5.9 Analog Connections
Each comparator has up to four I/O pins that can be used as analog inputs. Each pair of comparators shares the same
four pins. These pins must be configured for analog operation before using them as comparator inputs.
Any internal reference source, such as a bandgap reference voltage, must be configured and enabled prior to its use as
a comparator input.
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31.5.10 Other Dependencies
Not applicable.
31.6 Functional Description
31.6.1 Principle of Operation
Each comparator has one positive input and one negative input. Each positive input may be chosen from a selection of
analog input pins. Each negative input may be chosen from a selection of analog input pins or internal inputs, such as a
bandgap reference voltage. The digital output from the comparator is one when the difference between the positive and
the negative input voltage is positive, and zero otherwise.
The individual comparators can be used independently (normal mode) or grouped in pairs to generate a window
comparison (window mode).
31.6.2 Basic Operation
31.6.2.1 Initialization
Before enabling the AC, the input and output events must be configured in the Event Control register (EVCTRL). These
settings cannot be changed while the AC is enabled.
Each individual comparator must also be configured by its respective Comparator Control register (COMPCTRL0) before
that comparator is enabled. These settings cannot be changed while the comparator is enabled.
zSelect the desired measurement mode with COMPCTRLx.SINGLE. See “Starting a Comparison” on page
845 for more details
zSelect the desired hysteresis with COMPCTRLx.HYST. See “Input Hysteresis” on page 849 for more details
zSelect the comparator speed versus power with COMPCTRLx.SPEED. See “Propagation Delay vs. Power
Consumption” on page 849 for more details
zSelect the interrupt source with COMPCTRLx.INTSEL
zSelect the positive and negative input sources with the COMPCTRLx.MUXPOS and
COMPCTRLx.MUXNEG bits. See section “Selecting Comparator Inputs” on page 847 for more details
zSelect the filtering option with COMPCTRLx.FLEN
31.6.2.2 Enabling, Disabling and Resetting
The AC is enabled by writing a one to the Enable bit in the Control A register (CTRLA.ENABLE). The individual
comparators must be also enabled by writing a one to the Enable bit in the Comparator x Control registers
(COMPCTRLx.ENABLE). The AC is disabled by writing a zero to CTRLA.ENABLE. This will also disable the individual
comparators, but will not clear their COMPCTRLx.ENABLE bits.
The AC is reset by writing a one to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in the
AC, except DEBUG, will be reset to their initial state, and the AC will be disabled. Refer to the CTRLA register for details.
31.6.2.3 Starting a Comparison
Each comparator channel can be in one of two different measurement modes, determined by the Single bit in the
Comparator x Control register (COMPCTRLx.SINGLE):
zContinuous measurement
zSingle-shot
After being enabled, a start-up delay is required before the result of the comparison is ready. This start-up time is
measured automatically to account for environmental changes, such as temperature or voltage supply level, and is
specified in “Electrical Characteristics” on page 1055.
During the start-up time, the COMP output is not available. If the supply voltage is below 2.5V, the start-up time is also
dependent on the voltage doubler. If the supply voltage is guaranteed to be above 2.5V, the voltage doubler can be
disabled by writing the Low-Power Mux bit in the Control A register (CTRLA.LPMUX) to one.
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The comparator can be configured to generate interrupts when the output toggles, when the output changes from zero to
one (rising edge), when the output changes from one to zero (falling edge) or at the end of the comparison. An end-of-
comparison interrupt can be used with the single-shot mode to chain further events in the system, regardless of the state
of the comparator outputs. The interrupt mode is set by the Interrupt Selection bit group in the Comparator Control
register (COMPCTRLx.INTSEL). Events are generated using the comparator output state, regardless of whether the
interrupt is enabled or not.
Continuous Measurement
Continuous measurement is selected by writing COMPCTRLx.SINGLE to zero. In continuous mode, the comparator is
continuously enabled and performing comparisons. This ensures that the result of the latest comparison is always
available in the Current State bit in the Status A register (STATUSA.STATEx). After the start-up time has passed, a
comparison is done and STATUSA is updated. The Comparator x Ready bit in the Status B register
(STATUSB.READYx) is set, and the appropriate peripheral events and interrupts are also generated. New comparisons
are performed continuously until the COMPCTRLx.ENABLE bit is written to zero. The start-up time applies only to the
first comparison.
In continuous operation, edge detection of the comparator output for interrupts is done by comparing the current and
previous sample. The sampling rate is the GCLK_AC_DIG frequency. An example of continuous measurement is shown
in Figure 31-2.
Figure 31-2. Continuous Measurement Example
For low-power operation, comparisons can be performed during sleep modes without a clock. The comparator is enabled
continuously, and changes in the state of the comparator are detected asynchronously. When a toggle occurs, the Power
Manager will start GCLK_AC_DIG to register the appropriate peripheral events and interrupts. The GCLK_AC_DIG clock
is then disabled again automatically, unless configured to wake up the system from sleep.
Single-Shot
Single-shot operation is selected by writing COMPCTRLx.SINGLE to one. During single-shot operation, the comparator
is normally idle. The user starts a single comparison by writing a one to the respective Start Comparison bit in the write-
only Control B register (CTRLB.STARTx). The comparator is enabled, and after the start-up time has passed, a single
comparison is done and STATUSA is updated. Appropriate peripheral events and interrupts are also generated. No new
comparisons will be performed.
Writing a one to CTRLB.STARTx also clears the Comparator x Ready bit in the Status B register (STATUSB.READYx).
STATUSB.READYx is set automatically by hardware when the single comparison has completed. To remove the need
for polling, an additional means of starting the comparison is also available. A read of the Status C register (STATUSC)
will start a comparison on all comparators currently configured for single-shot operation. The read will stall the bus until
all enabled comparators are ready. If a comparator is already busy with a comparison, the read will stall until the current
comparison is compete, and a new comparison will not be started.
A single-shot measurement can also be triggered by the Event System. Writing a one to the Comparator x Event Input bit
in the Event Control Register (EVCTRL.COMPEIx) enables triggering on incoming peripheral events. Each comparator
can be triggered independently by separate events. Event-triggered operation is similar to user-triggered operation; the
difference is that a peripheral event from another hardware module causes the hardware to automatically start the
comparison and clear STATUSB.READYx.
GCLK_AC
STATUSB.READYx
Sampled
Comparator Output
COMPCTRLx.ENABLE
tSTARTUP
Write ‘1’
2-3 cycles
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To detect an edge of the comparator output in single-shot operation for the purpose of interrupts, the result of the current
measurement is compared with the result of the previous measurement (one sampling period earlier). An example of
single-shot operation is shown in Figure 31-3.
Figure 31-3. Single-Shot Example
For low-power operation, event-triggered measurements can be performed during sleep modes. When the event occurs,
the Power Manager will start GCLK_AC_DIG. The comparator is enabled, and after the startup time has passed, a
comparison is done and appropriate peripheral events and interrupts are also generated. The comparator and
GCLK_AC_DIG are then disabled again automatically, unless configured to wake up the system from sleep.
31.6.3 Selecting Comparator Inputs
Each comparator has one positive and one negative input. The positive input is fed from an external input pin (AINx). The
negative input can be fed either from an external input pin (AINx) or from one of the several internal reference voltage
sources common to all comparators. The user selects the input source as follows:
zThe positive input is selected by the Positive Input MUX Select bit group in the Comparator Control register
(COMPCTRLx.MUXPOS)
zThe negative input is selected by the Negative Input MUX Select bit group in the Comparator Control
register (COMPCTRLx.MUXNEG)
In the case of using an external I/O pin, the selected pin must be configured for analog usage in the PORT Controller by
disabling the digital input and output. The switching of the analog input multiplexors is controlled to minimize crosstalk
between the channels. The input selection must be changed only while the individual comparator is disabled.
31.6.4 Window Operation
Each comparator pair can be configured to work together in window mode. In this mode, a voltage range is defined, and
the comparators give information about whether an input signal is within this range or not. Window mode is enabled by
the Window Enable x bit in the Window Control register (WINCTRL.WENx). Both comparators in a pair must have the
same measurement mode setting in their respective Comparator Control Registers (COMPCTRLx.SINGLE).
To physically configure the pair of comparators for window mode, the same I/O pin should be chosen for each
comparator’s positive input to create the shared input signal. The negative inputs define the range for the window. In
Figure 31-4, COMP0 defines the upper limit and COMP1 defines the lower limit of the window, as shown but the window
will also work in the opposite configuration with COMP0 lower and COMP1 higher. The current state of the window
function is available in the Window x State bit group of the Status register (STATUS.WSTATEx).
Window mode can be configured to generate interrupts when the input voltage changes to below the window, when the
input voltage changes to above the window, when the input voltage changes into the window or when the input voltage
changes outside the window. The interrupt selections are set by the Window Interrupt Selection bit group in the Window
Control register (WINCTRL.WINTSELx[1:0]). Events are generated using the inside/outside state of the window,
regardless of whether the interrupt is enabled or not. Note that the individual comparator outputs, interrupts and events
continue to function normally during window mode.
When the comparators are configured for window mode and single-shot mode, measurements are performed
simultaneously on both comparators. Writing a one to either Start Comparison bit in the Control B register
(CTRLB.STARTx) starts a measurement. Likewise either peripheral event can start a measurement.
GCLK_AC
STATUSB.READYx
Sampled
Comparator Output
CTRLB.STARTx
tSTARTUP
Write ‘1’
tSTARTUP
Write ‘1’
2-3 cycles 2-3 cycles
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Figure 31-4. Comparators in Window Mode
31.6.5 Voltage Doubler
The AC contains a voltage doubler that can reduce the resistance of the analog multiplexors when the supply voltage is
below 2.5V. The voltage doubler is normally switched on/off automatically based on the supply level. When enabling the
comparators, additional start-up time is required for the voltage doubler to settle. If the supply voltage is guaranteed to be
above 2.5V, the voltage doubler can be disabled by writing the Low-Power Mux bit in the Control A register
(CTRLA.LPMUX) to one. Disabling the voltage doubler saves power and reduces the start-up time.
31.6.6 VDDANA Scaler
The VDDANA scaler generates a reference voltage that is a fraction of the device’s supply voltage, with 64 levels. One
independent voltage channel is dedicated for each comparator. The scaler is enabled when a comparator’s Negative
Input Mux bit group in its Comparator Control register (COMPCTRLx.MUXNEG) is set to five and the comparator is
enabled. The voltage of each channel is selected by the Value bit group in the Scaler x registers
(SCALERx.VALUE[5:0]).
+
-
+
-
STATE0
STATE1
WSTATE[1:0]
INTERRUPTS
EVENTS
INPUT SIGNAL
UPPER LIMIT OF WINDOW
COMP0
COMP1
INTERRUPT
SENSITIVITY
CONTROL
&
WINDOW
FUNCTION
LOWER LIMIT OF WINDOW
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Figure 31-5. VDDANA Scaler
31.6.7 Input Hysteresis
Application software can selectively enable/disable hysteresis for the comparison. Applying hysteresis will help prevent
constant toggling of the output, which can be caused by noise when the input signals are close to each other. Hysteresis
is enabled for each comparator individually by the Hysteresis Mode bit in the Comparator x Control register
(COMPCTRLx.HYST). Hysteresis is available only in continuous mode (COMPCTRLx.SINGLE=0).
31.6.8 Propagation Delay vs. Power Consumption
It is possible to trade off comparison speed for power efficiency to get the shortest possible propagation delay or the
lowest power consumption. The speed setting is configured for each comparator individually by the Speed bit group in
the Comparator x Control register (COMPCTRLx.SPEED). The Speed bits select the amount of bias current provided to
the comparator, and as such will also affect the start-up time.
31.6.9 Filtering
The output of the comparators can be digitally filtered to reduce noise using a simple digital filter. The filtering is
determined by the Filter Length bits in the Comparator Control x register (COMPCTRLx.FLEN), and is independent for
each comparator. Filtering is selectable from none, 3-bit majority (N=3) or 5-bit majority (N=5) functions. Any change in
the comparator output is considered valid only if N/2+1 out of the last N samples agree. The filter sampling rate is the
CLK_AC frequency scaled by the prescaler setting in the Control A register (CTRLA.PRESCALER).
Note that filtering creates an additional delay of N-1 sampling cycles from when a comparison is started until the
comparator output is validated. For continuous mode, the first valid output will occur when the required number of filter
samples is taken. Subsequent outputs will be generated every cycle based on the current sample plus the previous N-1
samples, as shown in Figure 31-6. For single-shot mode, the comparison completes after the Nth filter sample, as shown
in Figure 31-7.
COMPCTRLx.MUXNEG
== 5
SCALERx.
VALUE
to
COMPx
6
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Figure 31-6. Continuous Mode Filtering
Figure 31-7. Single-Shot Filtering
During sleep modes, filtering is supported only for single-shot measurements. Filtering must be disabled if continuous
measurements will be done during sleep modes, or the resulting interrupt/event may be generated incorrectly.
31.6.10 Comparator Output
The output of each comparator can be routed to an I/O pin by setting the Output bit group in the Comparator Control x
register (COMPCTRLx.OUT). This allows the comparator to be used by external circuitry. Either the raw, non-
synchronized output of the comparator or the CLK_AC-synchronized version, including filtering, can be used as the I/O
signal source. The output appears on the corresponding CMP[x] pin.
31.6.11 Offset Compensation
The Swap bit in the Comparator Control registers (COMPCTRLx.SWAP) controls switching of the input signals to a
comparator's positive and negative terminals. When the comparator terminals are swapped, the output signal from the
comparator is also inverted, as shown in Figure 31-8. This allows the user to measure or compensate for the comparator
input offset voltage. As part of the input selection, COMPCTRLx.SWAP can be changed only while the comparator is
disabled.
Figure 31-8. Input Swapping for Offset Compensation
Sampling Clock
Sampled
Comparator Output
3-bit Majority
Filter Output
5-bit Majority
Filter Output
Sampling Clock
3-bi t Sampled
Comparator Output
3-bit Majority
Filter Output
Start
5-bi t Sampled
Comparator Output
5-bit Majority
Filter Output
t
SUT
M
U
XP
OS
M
U
XNE
G
+
-
COMPx
S
WAP
ENABLE
HY
S
TERE
S
I
S
S
WA
P
C
MPx
COMPCTRLx
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31.7 Additional Features
31.7.1 DMA Operation
Not applicable.
31.7.2 Interrupts
The peripheral has the following interrupt sources:
zComparator (COMPx): this is an asynchronous interrupt and can be used to wake-up the device from any sleep
mode.
zWindow (WINx): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode.
Comparator interrupts are generated based on the conditions selected by the Interrupt Selection bit group in the
Comparator Control registers (COMPCTRLx.INTSEL). Window interrupts are generated based on the conditions
selected by the Window Interrupt Selection bit group in the Window Control register (WINCTRL.WINTSEL[1:0]).
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one
to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is
cleared, the interrupt is disabled or the peripheral is reset. An interrupt flag is cleared by writing a one to the
corresponding bit in the INTFLAG register.
Each peripheral can have one interrupt request line per interrupt source or one common interrupt request line for all the
interrupt sources. If the peripheral has one common interrupt request line for all the interrupt sources, the user must read
the INTFLAG register to determine which interrupt condition is present.
For details on clearing interrupt flags, refer to the INTFLAG register description.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to “Nested Vector Interrupt
Controller” on page 29 for details.
31.7.3 Events
The peripheral can generate the following output events:
zComparator: COMPEO0, COMPEO1(EVCTRL)
zWindow: WINEO0(EVCTRL)
Output events must be enabled to be generated. Writing a one to an Event Output bit in the Event Control register
(EVCTRL.COMPEOx) enables the corresponding output event. Writing a zero to this bit disables the corresponding
output event. The events must be correctly routed in the Event System. Refer to “EVSYS – Event System” on page 400
for details.
The peripheral can take the following actions on an input event:
zSingle-shot measurement
zSingle-shot measurement in window mode
Input events must be enabled for the corresponding action to be taken on any input event. Writing a one to an Event
Input bit in the Event Control register (EVCTRL.COMPEIx) enables the corresponding action on input event. Writing a
zero to a bit disables the corresponding action on input event. Note that if several events are connected to the peripheral,
the enabled action will be taken on any of the incoming events. The events must be correctly routed in the Event System.
Refer to “EVSYS – Event System” on page 400 for details.
When EVCTRL.COMPEIx is one, the event will start a comparison on COMPx after the start-up time delay. In normal
mode, each comparator responds to its corresponding input event independently. For a pair of comparators in window
mode, either comparator event will trigger a comparison on both comparators simultaneously.
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31.7.4 Sleep Mode Operation
The Run in Standby bit in the Control A register (CTRLA.RUNSTDBY) controls the behavior of the AC during standby
sleep mode. When the bit is zero, the comparator pair is disabled during sleep, but maintains its current configuration.
When the bit is one, the comparator pair continues to operate during sleep. Note that when RUNSTDBY is zero, the
analog blocks are powered off for the lowest power consumption. This necessitates a start-up time delay when the
system returns from sleep.
When RUNSTDBY is one, any enabled AC interrupt source can wake up the CPU. While the CPU is sleeping, single-
shot comparisons are only triggerable by events. The AC can also be used during sleep modes where the clock used by
the AC is disabled, provided that the AC is still powered (not in shutdown). In this case, the behavior is slightly different
and depends on the measurement mode, as listed in Table 31-1.
Table 31-1. Sleep Mode Operation
31.7.4.1 Continuous Measurement during Sleep
When a comparator is enabled in continuous measurement mode and GCLK_AC_DIG is disabled during sleep, the
comparator will remain continuously enabled and will function asynchronously. The current state of the comparator is
asynchronously monitored for changes. If an edge matching the interrupt condition is found, GCLK_AC_DIG is started to
register the interrupt condition and generate events. If the interrupt is enabled in the Interrupt Enable registers
(INTENCLR/SET), the AC can wake up the device; otherwise GCLK_AC_DIG is disabled until the next edge detection.
Filtering is not possible with this configuration.
Figure 31-9. Continuous Mode SleepWalking
31.7.4.2 Single-Shot Measurement during Sleep
For low-power operation, event-triggered measurements can be performed during sleep modes. When the event occurs,
the Power Manager will start GCLK_AC_DIG. The comparator is enabled, and after the start-up time has passed, a
comparison is done, with filtering if desired, and the appropriate peripheral events and interrupts are also generated, as
shown in Figure 31-10 The comparator and GCLK_AC_DIG are then disabled again automatically, unless configured to
wake the system from sleep. Filtering is allowed with this configuration.
Figure 31-10.Single-Shot SleepWalking
COMPCTRLx.MODE RUNSTDBY=0 RUNSTDBY=1
0 (Continuous) COMPx disabled GCLK_AC_DIG stopped, COMPx enabled
1 (Single-shot) COMPx disabled GCLK_AC_DIG stopped, COMPx enabled only
when triggered by an input event
GCLK_AC
Comparator
Output or Event
Comparator State
GCLK_AC
Comparator
Output or Event
Input Event
t
STARTUP
t
STARTUP
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31.7.5 Synchronization
Due to the asynchronicity between CLK_MODULE_APB and GCLK_MODULE, some registers must be synchronized
when accessed. A register can require:
zSynchronization when written
zSynchronization when read
zSynchronization when written and read
zNo synchronization
When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is
stalled.
The following bits need synchronization when written:
zSoftware Reset bit in Control A register (CTRLA.SWRST)
zEnable bit in Control A register (CTRLA.ENABLE)
zEnable bit in Comparator Control register (COMPCTRLn.ENABLE)
The following register need synchronization when written:
zWindow Control register (WINCTRL)
Refer to the Synchronization chapter for further details.
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31.8 Register Summary
Table 31-2. Register Summary
Offset Name
Bit
Pos.
0x00 CTRLA 7:0 LPMUX RUNSTDBY ENABLE SWRST
0x01 CTRLB 7:0 START1 START0
0x02
EVCTRL
7:0 WINEO0 COMPEO1 COMPEO0
0x03 15:8 COMPEI1 COMPEI0
0x04 INTENCLR 7:0 WIN0 COMP1 COMP0
0x05 INTENSET 7:0 WIN0 COMP1 COMP0
0x06 INTFLAG 7:0 WIN0 COMP1 COMP0
0x07 Reserved
0x08 STATUSA 7:0 WSTATE0[1:0] STATE1 STATE0
0x09 STATUSB 7:0 SYNCBUSY READY1 READY0
0x0A STATUSC 7:0 WSTATE0[1:0] STATE1 STATE0
0x0B Reserved
0x0C WINCTRL 7:0 WINTSEL0[1:0] WEN0
0x0D
...
0x0F
Reserved
0x10
COMPCTRL0
7:0 INTSEL[1:0] SPEED[1:0] SINGLE ENABLE
0x11 15:8 SWAP MUXPOS[1:0] MUXNEG[2:0]
0x12 23:16 HYST OUT[1:0]
0x13 31:24 FLEN[2:0]
0x14
COMPCTRL1
7:0 INTSEL[1:0] SPEED[1:0] SINGLE ENABLE
0x15 15:8 SWAP MUXPOS[1:0] MUXNEG[2:0]
0x16 23:16 HYST OUT[1:0]
0x17 31:24 FLEN[2:0]
0x18
...
0x1F
Reserved
0x20 SCALER0 7:0 VALUE[5:0]
0x21 SCALER1 7:0 VALUE[5:0]
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31.9 Register Description
Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters
and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by
the Write-Protected property in each individual register description. Refer to “Register Access Protection” on page 844
for details.
Some registers require synchronization when read and/or written. Synchronization is denoted by the Write-Synchronized
or the Read-Synchronized property in each individual register description. Refer to “Synchronization” on page 853 for
details.
Some registers are enable-protected, meaning they can be written only when the AC is disabled. Enable-protection is
denoted by the Enable-Protected property in each individual register description.
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31.9.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: Write-Protected, Write-Synchronized
zBit 7 – LPMUX: Low-Power Mux
0: The analog input muxes have low resistance, but consume more power at lower voltages (e.g., are driven by the
voltage doubler).
1: The analog input muxes have high resistance, but consume less power at lower voltages (e.g., the voltage dou-
bler is disabled).
This bit is not synchronized
zBits 6:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 2 – RUNSTDBY: Run in Standby
This bit controls the behavior of the comparators during standby sleep mode.
0: The comparator pair is disabled during sleep.
1: The comparator pair continues to operate during sleep.
This bit is not synchronized
zBit 1 – ENABLE: Enable
0: The AC is disabled.
1: The AC is enabled. Each comparator must also be enabled individually by the Enable bit in the Comparator
Control register (COMPCTRLn.ENABLE).
Due to synchronization, there is delay from updating the register until the peripheral is enabled/disabled. The value
written to CTRL.ENABLE will read back immediately after being written. STATUS.SYNCBUSY is set. STA-
TUS.SYNCBUSY is cleared when the peripheral is enabled/disabled.
zBit 0 – SWRST: Software Reset
0: There is no reset operation ongoing.
1: The reset operation is ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the AC to their initial state, and the AC will be disabled.
Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-oper-
ation will be discarded.
Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST
and STATUS.SYNCBUSY will both be cleared when the reset is complete.
Bit 76543210
LPMUX
RUNSTDBY
ENABLE SWRST
AccessR/WRRRRR/WR/WW
Reset00000000
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31.9.2 Control B
Name: CTRLB
Offset: 0x01
Reset: 0x00
Property: -
zBits 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 1:0 – STARTx [x=1..0]: Comparator x Start Comparison
Writing a zero to this field has no effect.
Writing a one to STARTx starts a single-shot comparison on COMPx if both the Single-Shot and Enable bits in the
Comparator x Control Register are one (COMPCTRLx.SINGLE and COMPCTRLx.ENABLE). If comparator x is
not implemented, or if it is not enabled in single-shot mode, writing a one has no effect.
This bit always reads as zero.
Bit 76543210
START1 START0
AccessRRRRRRWW
Reset00000000
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31.9.3 Event Control
Name: EVCTRL
Offset: 0x02
Reset: 0x0000
Property: Write-Protected
zBits 15:10 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 9:8 – COMPEIx [x=1..0]: Comparator x Event Input
Note that several actions can be enabled for incoming events. If several events are connected to the peripheral,
the enabled action will be taken for any of the incoming events. There is no way to tell which of the incoming
events caused the action.
These bits indicate whether a comparison will start or not on any incoming event.
0: Comparison will not start on any incoming event.
1: Comparison will start on any incoming event.
zBits 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 4 – WINEO: Window x Event Output Enable
These bits indicate whether the window x function can generate a peripheral event or not.
0: Window x Event is disabled.
1: Window x Event is enabled.
zBits 3:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 1:0 – COMPEOx [x=1..0]: Comparator x Event Output Enable
These bits indicate whether the comparator x output can generate a peripheral event or not.
0: COMPx event generation is disabled.
1: COMPx event generation is enabled.
Bit 151413121110 9 8
COMPEI1 COMPEI0
AccessRRRRRRR/WR/W
Reset00000000
Bit 76543210
WINEO0 COMPEO1 COMPEO0
Access R R R R/W R R R/W R/W
Reset00000000
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31.9.4 Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x04
Reset: 0x00
Property: Write-Protected
zBits 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 4 – WIN: Window x Interrupt Enable
Reading this bit returns the state of the Window x interrupt enable.
0: The Window x interrupt is disabled.
1: The Window x interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit disables the Window x interrupt.
zBits 3:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 1:0 – COMPx [x=1..0]: Comparator x Interrupt Enable
Reading this bit returns the state of the Comparator x interrupt enable.
0: The Comparator x interrupt is disabled.
1: The Comparator x interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit disables the Comparator x interrupt.
Bit 76543210
WIN0 COMP1 COMP0
Access R R R R/W R R R/W R/W
Reset00000000
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31.9.5 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name: INTENSET
Offset: 0x05
Reset: 0x00
Property: Write-Protected
zBits 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 4 – WIN: Window x Interrupt Enable
Reading this bit returns the state of the Window x interrupt enable.
0: The Window x interrupt is disabled.
1: The Window x interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit enables the Window x interrupt.
zBits 3:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 1:0 – COMPx [x=1..0]: Comparator x Interrupt Enable
Reading this bit returns the state of the Comparator x interrupt enable.
0: The Comparator x interrupt is disabled.
1: The Comparator x interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Ready interrupt bit and enable the Ready interrupt.
Bit 76543210
WIN0 COMP1 COMP0
Access R R R R/W R R R/W R/W
Reset00000000
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31.9.6 Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x06
Reset: 0x00
Property: -
zBits 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 4 – WIN: Window x
This flag is set according to the Window x Interrupt Selection bit group in the WINCTRL register (WINC-
TRL.WINTSELx) and will generate an interrupt if INTENCLR/SET.WINx is also one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Window x interrupt flag.
zBits 3:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 1:0 – COMPx [x=1..0]: Comparator x
Reading this bit returns the status of the Comparator x interrupt flag. If comparator x is not implemented, COMPx
always reads as zero.
This flag is set according to the Interrupt Selection bit group in the Comparator x Control register (COMPC-
TRLx.INTSEL) and will generate an interrupt if INTENCLR/SET.COMPx is also one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Comparator x interrupt flag.
Bit 76543210
WIN0 COMP1 COMP0
Access R R R R/W R R R/W R/W
Reset00000000
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31.9.7 Status A
Name: STATUSA
Offset: 0x08
Reset: 0x00
Property: -
zBits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 5:4 – WSTATE0[1:0]: Window 0 Current State
These bits show the current state of the signal if the window 0 mode is enabled, according to Table 31-3. If the win-
dow 0 function is not implemented, WSTATE0 always reads as zero.
Table 31-3. Window 0 Current State
zBits 3:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 1:0 – STATEx [x=1..0]: Comparator x Current State
This bit shows the current state of the output signal from COMPx. STATEx is valid only when STATUSB.READYx
is one.
Bit 76543210
WSTATE0[1:0] STATE1 STATE0
AccessRRRRRRRR
Reset00000000
WSTATE0[1:0] Name Description
0x0 ABOVE Signal is above window
0x1 INSIDE Signal is inside window
0x2 BELOW Signal is below window
0x3 Reserved
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31.9.8 Status B
Name: STATUSB
Offset: 0x09
Reset: 0x00
Property: -
zBit 7 – SYNCBUSY: Synchronization Busy
This bit is cleared when the synchronization of registers between the clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
zBits 6:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 1:0 – READYx [x=1..0]: Comparator x Ready
This bit is cleared when the comparator x output is not ready.
This bit is set when the comparator x output is ready.
If comparator x is not implemented, READYx always reads as zero.
Bit 76543210
SYNCBUSY
READY1 READY0
AccessRRRRRRRR
Reset00000000
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31.9.9 Status C
STATUSC is a copy of STATUSA (see STATUSA register), with the additional feature of automatically starting single-
shot comparisons. A read of STATUSC will start a comparison on all comparators currently configured for single-shot
operation. The read will stall the bus until all enabled comparators are ready. If a comparator is already busy with a
comparison, the read will stall until the current comparison is compete, and a new comparison will not be started.
Name: STATUSC
Offset: 0x0A
Reset: 0x00
Property: -
zBits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 5:4 – WSTATE0[1:0]: Window 0 Current State
These bits show the current state of the signal if the window 0 mode is enabled. If the window 0 function is not
implemented, WSTATE0 always reads as zero.
Table 31-4. Window 0 Current State
zBits 3:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 1:0 – STATEx [x=1..0]: Comparator x Current State
This bit shows the current state of the output signal from COMPx. If comparator x is not implemented, STATEx
always reads as zero. STATEx is only valid when STATUSB.READYx is one.
Bit 76543210
WSTATE0[1:0] STATE1 STATE0
AccessRRRRRRRR
Reset00000000
WSTATE0[1:0] Name Description
0x0 ABOVE Signal is above window
0x1 INSIDE Signal is inside window
0x2 BELOW Signal is below window
0x3 Reserved
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31.9.10 Window Control
Name: WINCTRL
Offset: 0x0C
Reset: 0x00
Property: Write-Protected, Write-Synchronized
zBits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 2:1 – WINTSEL0[1:0]: Window 0 Interrupt Selection
These bits configure the interrupt mode for the comparator window 0 mode.
Table 31-5. Window 0 Interrupt Selection
zBit 0 – WEN0: Window 0 Mode Enable
0: Window mode is disabled for comparators 0 and 1.
1: Window mode is enabled for comparators 0 and 1.
Bit 76543210
WINTSEL0[1:0] WEN0
AccessRRRRRR/WR/WR/W
Reset00000000
WINTSEL0[1:0] Name Description
0x0 ABOVE Interrupt on signal above window
0x1 INSIDE Interrupt on signal inside window
0x2 BELOW Interrupt on signal below window
0x3 OUTSIDE Interrupt on signal outside window
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31.9.11 Comparator Control n
The configuration of comparator n is protected while comparator n is enabled (COMPCTRLn.ENABLE=1). Changes to
the other bits in COMPCTRLn can only occur when COMPCTRLn.ENABLE is zero.
Name: COMPCTRLn
Offset: 0x10+n*0x4 [n=0..1]
Reset: 0x00000000
Property: Write-Protected, Write-Synchronized
zBits 31:27 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 26:24 – FLEN[2:0]: Filter Length
These bits configure the filtering for comparator n. COMPCTRLn.FLEN can only be written while COMPC-
TRLn.ENABLE is zero.
These bits are not synchronized.
Table 31-6. Filter Length
Bit 3130292827262524
FLEN[2:0]
AccessRRRRRR/WR/WR/W
Reset00000000
Bit 2322212019181716
HYST OUT[1:0]
AccessRRRRR/WRR/WR/W
Reset00000000
Bit 151413121110 9 8
SWAP MUXPOS[1:0] MUXNEG[2:0]
Access R/W R R/W R/W R R/W R/W R/W
Reset00000000
Bit 76543210
INTSEL[1:0] SPEED[1:0] SINGLE ENABLE
Access R R/W R/W R R/W R/W R/W R/W
Reset00000000
FLEN[2:0] Name Description
0x0 OFF No filtering
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zBits 23:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 19 – HYST: Hysteresis Enable
This bit indicates the hysteresis mode of comparator n. Hysteresis is available only for continuous mode (COMPC-
TRLn.SINGLE=0). COMPCTRLn.HYST can be written only while COMPCTRLn.ENABLE is zero.
0: Hysteresis is disabled.
1: Hysteresis is enabled.
This bit is not synchronized
zBit 18 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 17:16 – OUT[1:0]: Output
These bits configure the output selection for comparator n. COMPCTRLn.OUT can be written only while COMPC-
TRLn.ENABLE is zero.
These bits are not synchronized.
Table 31-7. Output
zBit 15 – SWAP: Swap Inputs and Invert
This bit swaps the positive and negative inputs to COMPn and inverts the output. This function can be used for off-
set cancellation. COMPCTRLn.SWAP can be written only while COMPCTRLn.ENABLE is zero.
0: The output of MUXPOS connects to the positive input, and the output of MUXNEG connects to the negative
input.
1: The output of MUXNEG connects to the positive input, and the output of MUXPOS connects to the negative
input.
This bit is not synchronized
zBit 14 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
0x1 MAJ3 3-bit majority function (2 of 3)
0x2 MAJ5 5-bit majority function (3 of 5)
0x3-0x7 Reserved
OUT[1:0] Name Description
0x0 OFF The output of COMPn is not routed to the COMPn I/O port
0x1 ASYNC The asynchronous output of COMPn is routed to the
COMPn I/O port
0x2 SYNC The synchronous output (including filtering) of COMPn is
routed to the COMPn I/O port
0x3 Reserved
FLEN[2:0] Name Description
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zBits 13:12 – MUXPOS[1:0]: Positive Input Mux Selection
These bits select which input will be connected to the positive input of comparator n. COMPCTRLn.MUXPOS can
be written only while COMPCTRLn.ENABLE is zero.
These bits are not synchronized.
Table 31-8. Positive Input Mux Selection
zBit 11 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 10:8 – MUXNEG[2:0]: Negative Input Mux Selection
These bits select which input will be connected to the negative input of comparator n. COMPCTRLn.MUXNEG can
only be written while COMPCTRLn.ENABLE is zero.
These bits are not synchronized.
Table 31-9. Negative Input Mux Selection
zBit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 6:5 – INTSEL[1:0]: Interrupt Selection
These bits select the condition for comparator n to generate an interrupt or event. COMPCTRLn.INTSEL can be
written only while COMPCTRLn.ENABLE is zero.
These bits are not synchronized.
MUXPOS[1:0] Name Description
0x0 PIN0 I/O pin 0
0x1 PIN1 I/O pin 1
0x2 PIN2 I/O pin 2
0x3 PIN3 I/O pin 3
Value Name Description
0x0 PIN0 I/O pin 0
0x1 PIN1 I/O pin 1
0x2 PIN2 I/O pin 2
0x3 PIN3 I/O pin 3
0x4 GND Ground
0x5 VSCALE VDDANA scaler
0x6 BANDGAP Internal bandgap voltage
0x7 Reserved
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Table 31-10. Interrupt Selection
zBit 4 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
zBits 3:2 – SPEED[1:0]: Speed Selection
This bit indicates the speed/propagation delay mode of comparator n. COMPCTRLn.SPEED can be written only
while COMPCTRLn.ENABLE is zero.
These bits are not synchronized.
Table 31-11. Speed Selection
zBit 1 – SINGLE: Single-Shot Mode
This bit determines the operation of comparator n. COMPCTRLn.SINGLE can be written only while COMPC-
TRLn.ENABLE is zero.
0: Comparator n operates in continuous measurement mode.
1: Comparator n operates in single-shot mode.
This bit is not synchronized
zBit 0 – ENABLE: Enable
Writing a zero to this bit disables comparator n.
Writing a one to this bit enables comparator n.
After writing to this bit, the value read back will not change until the action initiated by the writing is complete. Due
to synchronization, there is a latency of at least two GCLK_AC_DIG clock cycles from updating the register until
the comparator is enabled/disabled. The bit will continue to read the previous state while the change is in progress.
Writing a one to COMPCTRLn.ENABLE will prevent further changes to the other bits in COMPCTRLn. These bits
remain protected until COMPCTRLn.ENABLE is written to zero and the write is synchronized.
INTSEL[1:0] Name Description
0x0 TOGGLE Interrupt on comparator output toggle
0x1 RISING Interrupt on comparator output rising
0x2 FALLING Interrupt on comparator output falling
0x3 EOC Interrupt on end of comparison (single-shot mode only)
SPEED[1:0] Name Description
0x0 LOW Low speed
0x1 HIGH High speed
0x2-0x3 Reserved
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31.9.12 Scaler n
Name: SCALERn
Offset: 0x20+n*0x1 [n=0..1]
Reset: 0x00
Property: Write-Protected
zBits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBits 5:0 – VALUE[5:0]: Scaler Value
These bits define the scaling factor for channel n of the VDD voltage scaler. The output voltage, VSCALE, is:
Bit 76543210
VALUE[5:0]
Access R R R/W R/W R/W R/W R/W R/W
Reset00000000
VSCALE
VDD VALUE 1+()⋅
64
--------------------------------------------------
=
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32. PTC - Peripheral Touch Controller
32.1 Overview
The purpose of PTC is to acquire signals to detect touch on capacitive sensors. The external capacitive touch sensor is
typically formed on a PCB, and the sensor electrodes are connected to the analog front end of the PTC through the I/O
pins in the device. The PTC supports both self- and mutual-capacitance sensors.
In mutual-capacitance mode, sensing is done using capacitive touch matrices in various X-Y configurations, including
indium tin oxide (ITO) sensor grids. The PTC requires one pin per X-line and one pin per Y-line.
In self-capacitance mode, the PTC requires only one pin (Y-line) for each touch sensor.
32.2 Features
zLow-power, high-sensitivity, environmentally robust capacitive touch buttons, sliders, wheels and proximity sensing
zSupports mutual capacitance and self-capacitance sensing
z2/6 buttons in self-capacitance mode, for 32-/48- pins respectively
z12/48 buttons in mutual-capacitance mode, for 32-/48- pins respectively
zMix-and-match mutual-and self-capacitance sensors
zOne pin per electrode – no external components
zLoad compensating charge sensing
zParasitic capacitance compensation and adjustable gain for superior sensitivity
zZero drift over the temperature and VDD range
zAuto calibration and re-calibration of sensors
zSingle-shot and free-running charge measurement
zHardware noise filtering and noise signal de-synchronization for high conducted immunity
zSelectable channel change delay
zAllows choosing the settling time on a new channel, as required
zAcquisition-start triggered by command or interrupt event
zLow CPU utilization through interrupt on acquisition-complete
z5% CPU utilization scanning 10 channels at 50ms scan rate
zSupported by the Atmel® QTouch® Composer development tool, which comprises QTouch Library project builder and
QTouch analyzer
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32.3 Block Diagram
Figure 32-1. PTC Block Diagram Mutual-capacitance
Figure 32-2. PTC Block Diagram Self-capacitance
Compensation
Circuit
Acquisition Module
- Gain control
- ADC
- Filtering
R
S
100K
IRQ
Result
Y
0
Y
1
Y
15
X
0
X
1
X
15
X Line Driver
Input
Control
10
Compensation
Circuit
Acquisition Module
- Gain control
- ADC
- Filtering
R
S
100K
IRQ
Result
Y
0
Y
1
Y
15
X Line Driver
Input
Control
10
C
Y0
C
Y15
873
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
32.4 Signal Description
Note: 1. The number of X and Y lines are device dependent. Refer to “Configuration Summary” on page 4 for details.
Refer to “I/O Multiplexing and Considerations” on page 12 for details on the pin mapping for this peripheral. One signal
can be mapped on several pins.
32.5 Product Dependencies
In order to use this Peripheral, configure the other components of the system as described in the following sections.
32.5.1 I/O Lines
The I/O lines used for analog X-lines and Y-lines must be connected to external capacitive touch sensor electrodes.
External components are not required for normal operation. However, to improve the EMC performance, a series resistor
of 1 KΩ can be used on X-lines and Y-lines.
Mutual-capacitance Sensor Arrangement
A mutual-capacitance sensor is formed between two I/O lines - an X electrode for transmitting and Y electrode for
receiving. The mutual capacitance between the X and Y electrode is measured by the Peripheral Touch Controller.
Figure 32-3. Mutual Capacitance Sensor Arrangement
Name Type Description
X[n:0] Digital X-line (Output)
Y[m:0] Analog Y-line (Input/Output)
PTC
Module
MCU
X0
Xn
Y0
Ym
X1
Y1
Sensor Capacitance C
x,y
Cx0,y0 Cx0,y1 Cx0,ym
Cx1,y0 Cx1,y1 Cx1,ym
Cxn,y0 Cxn,y1 Cxn,ym
PTC
Module
874
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Self-capacitance Sensor Arrangement
The self-capacitance sensor is connected to a single pin on the Peripheral Touch Controller through the Y electrode for
receiving the signal. The sense electrode capacitance is measured by the Peripheral Touch Controller.
Figure 32-4. Self-capacitance Sensor Arrangement
For more information about designing the touch sensor, refer to Buttons, Sliders and Wheels Touch Sensor Design
Guide on http://www.atmel.com.
32.5.2 Clocks
The PTC is clocked by the GCLK_PTC clock. The PTC operates from an asynchronous clock source and the operation is
independent of the main system clock and its derivative clocks, such as the peripheral bus clock (CLK_APB). A number
of clock sources can be selected as the source for the asynchronous GCLK_PTC. The clock source is selected by
configuring the Generic Clock Selection ID in the Generic Clock Control register. For more information about selecting
the clock sources, refer to “GCLK – Generic Clock Controller” on page 90.
The selected clock must be enabled in the Power Manager, before it can be used by the PTC. By default these clocks are
disabled. The frequency range of GCLK_PTC is 400kHz to 4MHz.
For more details, refer to “PM – Power Manager” on page 112.
MCU
PTC
Module
Y
0
Y
1
Y
m
Cy0
Cy1
Cym
Sensor Capacitance C
y
875
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
32.6 Functional Description
In order to access the PTC, the user must use the QTouch Composer tool to configure and link the QTouch Library
firmware with the application code. QTouch Library can be used to implement buttons, sliders, wheels and proximity
sensor in a variety of combinations on a single interface.
For more information about QTouch library, refer to the Atmel QTouch Library Peripheral Touch Controller User Guide.
Figure 32-5. QTouch Library Usage
Custom Code
ApplicationLink
Atmel Qtouch
Library
Compiler
876
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
33. RFCTRL – AT86RF233 Front-End Control Signal Interface
33.1 Overview
The RFCTRL module provides a register and multiplexer for selecting the front-end control signal outputs of the
integrated transceiver as alternate pin functions for the SAMR21.
33.2 Features
zSupports up to 6 front-end control output signals
zSupports all front-end control input signals (DIG1, DIG2, DIG3 and DIG4) from the AT86RF233
33.3 Block Diagram
Figure 33-1. RFCTRL Block Diagram
33.4 Product Dependencies
In order to use the module, the I/O port pins used for front-end control signals must be configured as alternate pin
function outputs.
The RFCTRL module is enabled by writing the RFCTRL APB Clock Enable bit (APBCMASK.RFCTRL) in the Power
Manager to ‘1’. Refer to “Peripheral Clock Masking” on page 116 for details.
33.5 Functional Description
The RFCTRL module is intended to flexible route the PA/LNA and antenna diversity front-end control signals as well as
RX/TX frame time stamping to alternate pin functions of the Cortex-M0+ CPU without any further software action
required after initialization of the alternate pin function output.
The module provides six 2-bit registers which control the muxing of the DIG1, DIG2, DIG3 and DIG4 front-end control
signal outputs of the integrated transceiver to alternate pin functions of the SAMR21 device.
FECTRL[6]
DIG1
DIG2
DIG3
DIG4
FECTRL[0]
.
.
.
877
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
33.6 Register Summary
Offset Name
Bit
Position
0x00
FECTRL
7:0 F3CFG[1:0] F2CFG[1:0] F1CFG[1:0] F0CFG[1:0]
0x01 15:8 F5CFG[1:0] F4CFG[1:0]
0x02 Reserved 7:0
0x03 Reserved 7:0
878
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
33.7 Register Description
33.7.1 Front-end Control Register
Name: FECTRL
Offset: 0x00
Reset: 0x0000
Property: -
zBit 15:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
zBit 11:10 – F5CFG[1:0]: Front-end Control Signal 5 Configuration
These bits define the front-end output control signal 5, as shown in Table 33-1.
zBit 9:8 – F4CFG[1:0]: Front-end Control Signal 4 Configuration
These bits define the front-end output control signal 4, as shown in Table 33-1.
zBit 7:6 – F3CFG[1:0]: Front-end Control Signal 3 Configuration
These bits define the front-end output control signal 3, as shown in Table 33-1.
zBit 5:4 – F2CFG[1:0]: Front-end Control Signal 2 Configuration
These bits define the front-end output control signal 2, as shown in Table 33-1.
zBit 3:2 – F1CFG[1:0]: Front-end Control Signal 1 Configuration
These bits define the front-end output control signal 1, as shown in Table 33-1.
zBit 1:0 – F0CFG[1:0]: Front-end Control Signal 0 Configuration
These bits define the front-end output control signal 0, as shown in Table 33-1.
Bit 151413121112 9 8
0x01 F5CFG[1:0] F4CFG[1:0]
Access R R R R R/W R/W R/W R/W
Reset00000000
Bit76543210
0x00 F3CFG[1:0] F2CFG[1:0] F1CFG[1:0] F0CFG[1:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Table 33-1. Front-End Control Configuration
FnCFG[1:0] Operating Mode
0x0 Route transceiver DIG1 signal output to FECTRL[n] alternate pin function
0x1 Route transceiver DIG2 signal output to FECTRL[n] alternate pin function
0x2 Route transceiver DIG3 signal output to FECTRL[n] alternate pin function
0x3 Route transceiver DIG4 signal output to FECTRL[n] alternate pin function
879
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
34. Application Schematic
34.1 Basic Application Schematic
A basic application schematic of the SAM R21 with a single-ended RF connector is shown in Figure 34-1. The 50Ω
single-ended RF input is transformed to the 100Ω differential RF port impedance using balun B1. The capacitors C1 and
C2 provide AC coupling of the RF input to the RF port, optional capacitor C4 improves matching if required.
Figure 34-1. Basic Application Schematic
The power supply decoupling capacitors (CB2, CB4, CB5) are connected to the external analog supply VDDANA, the
external digital supplies VDDIO and VDDIN. Capacitors CB1, CB3 and CB6 are bypass capacitors for the integrated
analog and digital voltage regulators to ensure stable operation. All bypass capacitors should be placed as close as
possible to the pins and should have a low-resistance and low-inductance connection to ground to achieve the best
performance.
The crystal (XTAL), the two load capacitors (CX1, CX2), and the internal circuitry connected to pins XTAL1 and XTAL2
form the crystal oscillator. To achieve the best accuracy and stability of the reference frequency, large parasitic
capacitances should be avoided. Crystal lines should be routed as short as possible and not in proximity of digital I/O
signals. This is especially required for the High Data Rate Modes; refer to “High Data Rate Modes” on page 1013.
The ground plane of the application board should be separated into four independent fragments: the analog, the digital,
the antenna, and the XTAL ground plane. The exposed paddle shall act as the reference point of the individual grounds.
µF
10µF
C4
B1
C1
C2
GNDANA
GNDANA
RFP
RFN SAM R21
CB3 CB4
VDD
DVDD
VDDIO
CB6
CB5 10
VDD
VDD
SWDIO
SWCLK
VDDIN
VDDCORE
GND
RESET
Cortex
Debug
Connector
GNDANA
AVDD
VDDANA
GNDANA
XTAL1
XTAL2
CB1
VDD
CB2 CX1 CX2
XTAL
880
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Table 34-1. Exemplary Bill of Materials (BoM) for Basic Application Schematic
Symbol Description Value Manufacturer Part Number Commnt
B1 SMD balun 2.45GHz Wuerth 748421245 2.45GHz Balun
CB1
CB3
LDO VREG
bypass capacitor 100nF Generic X7R
(0402) 10% 16V
CB2
CB4
Power supply
decoupling 1µF AVX
Murata
0603YD105KAT2A
GRM188R61C105KA12
D
X5R
(0603) 10% 16V
CX1, CX2 Crystal load capacitor 12pF AVX
Murata
06035A120JA
GRM1555C1H120JA01
D
COG
(0402) 5% 50V
C1, C2 RF coupling capacitor 22pF
Murata
Epcos
AVX
GRM1555C1H220JA01J
B37920
06035A220JAT2A
C0G 5%
50V
(0402 or 0603)
C4 (optional) RF matching Value depends on final
PCB implementation
XTAL Crystal
CX-4025
16MHz
SX-4025 16MHz
ACAL Taitjen
Siward
XWBBPL-F-1
A207-011
881
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
34.2 Extended Feature Set Application Schematic
The Atmel AT86RF233 supports additional features like:
zSecurity Module (AES), “Security Module (AES)” on page 1005
zRandom Number Generator, “Random Number Generator” on page 1013
zHigh Data Rate Modes, “High Data Rate Modes” on page 1013
zAntenna Diversity, “Antenna Diversity” on page 1020
zUses internal DIG1(/2) signals available as alternate pin functions FECTRL[0..5] on pins PA08..15
zRX/TX Indicator, “RX/TX Indicator” on page 1025
zUses internal DIG3/4 signals available as alternate pin functions FECTRL[0..5] on pins PA08..15
zRx and Tx Frame Time Stamping (TX_ARET), “RX and TX Frame Time Stamping (TX_ARET)” on page 1027
zUses internal DIG2 signal available as alternate pin function FECTRL[0..5] on pins PA08..15
zFrame Buffer Empty Indicator, “Frame Buffer Empty Indicator” on page 1030
zUses internal IRQ signal connected to PB00
zDynamic Frame Buffer Protection, “Dynamic Frame Buffer Protection” on page 1032
zAlternate Start-Of-Frame Delimiter, “Alternate Start-Of-Frame Delimiter” on page 1033
zReduced Power Consumption Mode (RPC), “Reduced Power Consumption Mode (RPC)” on page 1034
zTime-Of-Flight Module (TOM) Measurements, “Time-Of-Flight Module (TOM)” on page 1039
zPhase Difference Measurement, “Phase Difference Measurement” on page 1050
An extended feature set application schematic illustrating the use of the AT86RF233 Extended Feature Set, see
“AT86RF233 Extended Feature Set” on page 1005, is shown in Figure 34-2. Although this example shows all additional
hardware features combined, it is possible to use all features separately or in various combinations.
882
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Figure 34-2. Extended Feature Application Schematic
In this example, a balun (B1) transforms the differential RF signal at the SAM R21 radio transceiver RF pins (RFP/RFN)
to a single ended RF signal, similar to the Basic Application Schematic; refer to Figure 34-1. During receive mode the
radio transceiver searches for the most reliable RF signal path using the Antenna Diversity algorithm. One antenna is
selected (SW2) by the Antenna Diversity RF switch control signal (DIG1), refer to “Antenna Diversity” on page 1020.
The RX signal is amplified by an optional low-noise amplifier (N2) and fed to the radio transceiver using the RX/TX switch
(SW1). During transmit mode the SAM R21 TX signal is amplified using an external PA (N1) and fed to the antennas via
an RF switch (SW2). These switches are controlled by the RX/TX Indicator, represented by the differential pin pair
DIG3/DIG4, refer to “RX/TX Indicator” on page 1025.
The Security Module (AES), Random Number Generator, High Data Rate Modes, Frame Buffer Empty Indicator,
Dynamic Frame Buffer Protection, Alternate Start-Of-Frame Delimiter or Reduced Power Consumption Mode (RPC) do
not require specific circuitry to operate, for details refer to “Security Module (AES)” on page 1005, “Random Number
Generator” on page 1013, “High Data Rate Modes” on page 1013, “Frame Buffer Empty Indicator” on page 1030,
“Dynamic Frame Buffer Protection” on page 1032, “Alternate Start-Of-Frame Delimiter” on page 1033 and “Reduced
Power Consumption Mode (RPC)” on page 1034.
CB1
µF
V
DD
µF
ANT0
ANT1
SW2
RF-
Switch
RF-
Switch
Balun
LNA
PA
SW1
N1
N2
B1
FECTRLk(DIG1)
FECTRLi(DIG3)
FECTRLj(DIG4)
GNDANA
GNDANA
RFP
RFN
DVDD
VDDIO
CB3 CB4
VDD
VDD
CB6
CB5 10
SWDIO
SWCLK
VDDIN
VDDCORE
RESET
GND
Cortex
Debug
Connector
SAM R21
GNDANA
GNDANA
AVDD
VDDANA
XTAL1
XTAL2
CB2
10
VDD CX1 CX2
XTAL
883
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
35. AT86RF233 Microcontroller Interface
35.1 Overview
This section describes the AT86RF233 to microcontroller interface. The interface comprises a slave SPI and additional
control signals, refer to Figure 35-1. The SPI timing and protocol are described below.
Figure 35-1. Microcontroller to AT86RF233 Interface
The SPI is used for register, Frame Buffer, SRAM and AES access. The additional control signals are connected to the
GCLK, EIC, GPIO and RFCTRL interface of the microcontroller. Table 35-1 introduces the radio transceiver I/O signals
and their functionality.
MOSI
MISO
SCLK
CLKM
IRQ
SLP_TR
RFCTRL
DIG1
DIG2
DIG3
DIG4
SAM R21
SAM D21
SERCOM 4
PAD1
PAD2
PAD0
PAD3
GCLK
GENERATOR 1(3)
EXTINT0
PORTx
AT86RF233
SPI-SLAVE
CONTROL
LOGIC
ANTENNA
DIVERSITY
CONTROL
External PA
and POWER
CONTROL
/SEL
/RST
Notes: 1. Alternate pin function and direction has to be configured by software.
2. Pin function is configured by hardware automatically after reset.
3. Die revision A uses GCLK GENERATOR 5.
PB31(F)(1)
PB30(F)(1)
PC19(F)(1)
PC18(F)(1)
PC16(F)(1)
PB00(A)(1)
PA20
PB15
PB16(2)
PB17(2)
PA10(2)
PA11(2)
884
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
35.2 SPI Timing Description
The CLKM signal can be used as clock input source for the Generic Clock Generator 1. If the microcontroller derives the
SPI master clock (SCLK) directly from CLKM, the SPI operates in synchronous mode, otherwise in asynchronous mode.
In asynchronous mode, the maximum SCLK frequency fasync is limited to 7.5MHz. The CLKM signal is not required to
derive SCLK and may be disabled to reduced power consumption and spurious emissions.
Figure 35-2 and Figure 35-3 illustrate the SPI timing and introduces its parameters. The corresponding timing parameter
definitions t1-t9 are defined in “Digital Interface Timing Characteristics” on page 1101.
Figure 35-2. SPI Timing, Global Map and Definition of Timing Parameters, t5, t6, t8, t9
Table 35-1. Signal Description of Microcontroller Interface
Signal Description
/SEL SPI select signal, active low
MOSI SPI data (master output slave input) signal
MISO SPI data (master input slave output) signal
SCLK SPI clock signal
CLKM
Optional, Clock output, refer to “Master Clock Signal Output (CLKM)” on page 991, usable as:
- microcontroller clock source and/or MAC timer reference
- high precision timing reference
IRQ Interrupt request signal, further used as:
- Frame Buffer Empty indicator, refer to “Frame Buffer Empty Indicator” on page 1030
SLP_TR
Multi purpose control signal (functionality is state dependent, see “Sleep/Wake-up and Transmit Signal
(SLP_TR)” on page 894):
- Sleep/Wakeup - enable/disable SLEEP state
- Sleep/Wakeup - enable/disable DEEP_SLEEP state
- TX start - BUSY_TX_(ARET) state
/RST AT86RF233 reset signal, active low
DIG2
Optional,
- IRQ_2 (RX_START) for RX Frame Time Stamping, see “RX and TX Frame Time Stamping (TX_ARET)” on
page 1027
- Signals frame transmit within TX_ARET mode for TX Time Stamping
SCLK
t8
MOSI 67 5 4 3 2 1 0 67 5 4 3 2 1 0
MISO Bit 6 Bit 5 Bit 3 Bit 2 Bit 1 Bit 0Bit 4 Bit 6 Bit 5 Bit 3 Bit 2 Bit 1 Bit 0Bit 4Bit 7
t6
Bit 7
t5
/SEL
t9
885
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Figure 35-3. SPI Timing, Detailed Drawing of Timing Parameters, t1 to t4
The SPI is based on a byte-oriented protocol and is always a bidirectional communication between the master and slave.
The SPI master starts the transfer by asserting /SEL = L. Then the master generates eight SPI clock cycles to transfer
one byte to the radio transceiver (via MOSI). At the same time, the slave transmits one byte to the master (via MISO).
When the master wants to receive one byte of data from the slave, it must also transmit one byte to the slave. All bytes
are transferred with the MSB first. An SPI transaction is finished by releasing /SEL = H.
An SPI register access consists of two bytes, a Frame Buffer or SRAM access of at least two or more bytes as described
in “SPI Protocol” on page 885.
/SEL = L enables the MISO output driver of the AT86RF233. The MSB of MISO is valid after t1 and is updated on each
SCLK falling edge. If the driver is disabled, there is no internal pull-up transistor connected to it. Driving the appropriate
signal level must be ensured by the microcontroller.
Note: 1. When both /SEL and /RST are active, the MISO output driver is also enabled.
Referring to Figure 35-2 and Figure 35-3, AT86RF233 MOSI is sampled at the rising edge of the SCLK signal and the
output is set at the falling edge of SCLK. The signal must be stable before and after the rising edge of SCLK as specified
by t3 and t4, refer to “Digital Interface Timing Characteristics” on page 1101.
This SPI operational mode is commonly known as “SPI mode 0”.
35.3 SPI Protocol
Each SPI sequence starts with transferring a command byte from the SPI master via MOSI (see Table 35-2) with the
MSB first. This command byte defines the SPI access mode and additional mode-dependent information.
Each SPI transfer returns bytes back to the SPI master on the MISO output signal. The content of the first byte (see value
“PHY_STATUS“ in Figure 35-4 to Figure 35-14) is set to zero after reset. To transfer status information of the radio
transceiver to the microcontroller, the content of the first byte can be configured with register bits SPI_CMD_MODE
(register 0x04, TRX_CTRL_1). For details, refer to “Register Description” on page 890.
Note: 1. Return values on MISO stated as XX shall be ignored by the microcontroller.
The different access modes are described within the following sections.
Bit 7 Bit 6
t1t2
Bit 5
t4
t3
Bit 7 Bit 6 Bit 5
SCLK
MOSI
MISO
/SEL
Table 35-2. SPI Command Byte Definition
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access Mode Access Type
1 0 Register address [5:0]
Register access
Read access
1 1 Register address [5:0] Write access
001 Reserved
Frame Buffer access
Read access
011 Reserved Write access
000 Reserved
SRAM access
Read access
010 Reserved Write access
886
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
35.3.1 Register Access Mode
Register Access Mode is used to read and write AT86RF233 registers (register address from 0x00 up to 0x3F).
A register access mode is a two-byte read/write operation initiated by /SEL = L. The first transferred byte on MOSI is the
command byte including an identifier bit (bit[7] = 1), a read/write select bit (bit[6]), and a 6-bit register address.
On read access, the content of the selected register address is returned in the second byte on MISO
(see Figure 35-4).
Figure 35-4. Packet Structure - Register Read Access
Note: 1. Each SPI access can be configured to return radio controller status information (PHY_STATUS) on MISO, for
details refer to “Radio Transceiver Status Information” on page 890.
On write access, the second byte transferred on MOSI contains the write data to the selected address
(see Figure 35-5).
Figure 35-5. Packet Structure - Register Write Access
Each register access must be terminated by setting /SEL = H.
Figure 35-6 illustrates a typical SPI sequence for a register access sequence for write and read respectively.
Figure 35-6. Example SPI Sequence - Register Access Mode
35.3.2 Frame Buffer Access Mode
Frame Buffer Access Mode is used to read and write Atmel AT86RF233 frame buffer. The frame buffer address is always
reset to zero and incremented to access PSDU, LQI, ED and RX_STATUS data.
The Frame Buffer can hold up to 128-byte of one PHY service data unit (PSDU) IEEE 802.15.4 data frame. A detailed
description of the Frame Buffer can be found in “Frame Buffer” on page 981. An introduction to the IEEE 802.15.4 frame
format can be found in “Introduction – IEEE 802.15.4-2006 Frame Format” on page 947.
Each access starts with /SEL = L followed by a command byte on MOSI. Each frame read or write access command byte
is followed by the PHR data byte, indicating the frame length, followed by the PSDU data, see Figure 35-7 and Figure 35-
8.
1ADDRESS[5:0]0XXMOSI
PHY_STATUS(1) READ DATA[7:0]MISO
byte 1 (command byte) byte 2 (data byte)
1ADDRESS[5:0]1WRITE DATA[7:0]MOSI
PHY_STATUS XXMISO
byte 1 (command byte) byte 2 (data byte)
PHY_STATUS XX PHY_STATUS READ DATA
WRITE COMMAND WRITE DATA READ COMMAND XX
Register Write Access Register Read Access
SCLK
MOSI
MISO
/SEL
887
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
In Frame Buffer Access Mode during buffer reads, the PHY header (PHR) and the PSDU data are transferred via MISO
following PHY_STATUS byte. Once the PSDU data is uploaded, three more bytes are transferred containing the link
quality indication (LQI) value, the energy detection (ED) value, and the status information (RX_STATUS) of the received
frame, for LQI details refer to “Link Quality Indication (LQI)” on page 972. The Figure 35-7 illustrates the packet structure
of a Frame Buffer read access.
Note: 1. The frame buffer read access can be terminated immediately at any time by setting /SEL = H, for example after
reading the PHR byte only.
Figure 35-7. Packet Structure - Frame Read Access
The structure of RX_STATUS is described in below.
Structure of RX_STATUS
Note: 1. Refer to the RX_CRC_VALID bit in the PHY_RSSI register and to TRAC_STATUS bits in the TRX_STATE for
more information.
On frame buffer write access the second byte transferred on MOSI contains the frame length (PHR field) followed by the
payload data (PSDU) as shown by Figure 35-8.
Figure 35-8. Packet Structure - Frame Write Access
The number of bytes n for one frame buffer access is calculated as follows:
Read Access: n = 5 + frame_length
[PHY_STATUS, PHR byte, PSDU data, LQI, ED, and RX_STATUS]
Write Access: n = 2 + frame_length
[command byte, PHR byte, and PSDU data]
The maximum value of frame_length is 127 bytes. That means that n ≤132 for Frame Buffer read and n≤129 for Frame
Buffer write accesses.
Each read or write of a data byte automatically increments the address counter of the Frame Buffer until the access is
terminated by setting /SEL = H. A Frame Buffer read access can be terminated at any time without any consequences by
setting /SEL = H, for example after reading the frame length byte only. A successive Frame Buffer read operation starts
again with the PHR field.
The content of the AT86RF233 Frame Buffer is overwritten by a new received frame or a Frame Buffer write access.
Figure 35-9 and Figure 35-10 illustrate an example SPI sequence of a Frame Buffer access to read a frame with 2-byte
PSDU and write a frame with 4-byte PSDU.
Bit 7 654 3 2 1 0
RX_CRC_VALID TRAC_STATUS
0reserved[4:0]0MOSI
PHY_STATUSMISO
byte 1 (com m and byte )
1XX
PHR[7:0]
byte 2 (data byte )
XX
PSDU[7:0]
byte 3 (data byte )
XX
ED[7:0]
byte n- 1 (data byte )
XX
RX_STATUS[7:0]
byte n(data byte )
0reserved[4:0]1MOSI
PHY_STATUSMISO
byte 1 (com m and byte )
1PHR[7:0]
XX
byte 2 (data byte )
PSDU[7:0]
XX
byte 3 (data byte )
PSDU[7:0]
XX
byte n-1 (data byte )
PSDU[7:0]
XX
byte n(data byte )
888
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Figure 35-9. Example SPI Sequence - Frame Buffer Read of a Frame with 2-byte PSDU
Figure 35-10.Example SPI Sequence - Frame Buffer Write of a Frame with 4-byte PSDU
Access violations during a Frame Buffer read or write access are indicated by interrupt IRQ_6 (TRX_UR). For further
details, refer to “Frame Buffer” on page 981.
Notes: 1. The Frame Buffer is shared between RX and TX operations, the frame data is overwritten by freshly received data
frames. If an existing TX payload data frame is to be retransmitted, it must be ensured that no TX data is overwrit-
ten by newly received RX data.
2. To avoid overwriting during receive Dynamic Frame Buffer Protection can be enabled, refer to “Dynamic Frame
Buffer Protection” on page 1032.
3. For exceptions, receiving acknowledgement frames in Extended Operating Mode (TX_ARET) refer to
“TX_ARET_ON – Transmit with Automatic Frame Retransmission and CSMA-CA Retry” on page 928.
35.3.3 SRAM Access Mode
The SRAM access mode is used to read and write AT86RF233 frame buffer beginning with a specified byte address. It
enables to access dedicated buffer data directly from a desired address without a need of incrementing the frame buffer
from the top.
The SRAM access mode allows accessing dedicated bytes within the Frame Buffer or AES address space, refer to
“Security Module (AES)” on page 1005. This may reduce the SPI traffic.
During frame receive, after occurrence of IRQ_2 (RX_START), an SRAM access can be used to upload the PHR field
while preserving Dynamic Frame Buffer Protection, see “Dynamic Frame Buffer Protection” on page 1032.
Each SRAM access starts with /SEL = L. The first transferred byte on MOSI shall be the command byte and must
indicate an SRAM access mode according to the definition in Table 35-2. The following byte indicates the start address
of the write or read access.
SRAM address space:
zFrame Buffer:0x00 to 0x7F
zAES:0x82 to 0x94
On SRAM read access, one or more bytes of read data are transferred on MISO starting with the third byte of the access
sequence; refer to Figure 35-11.
COMMAND XX XX XX XX XX
PHY_ STATU S PHR PSDU 2PSDU 1 EDLQI
XX
RX_STATUS
SCLK
MOSI
MISO
/SEL
COMMAND PHR PSDU 1 PSDU 2 PSDU 3 PSDU 4
PHY_STATUS XX XXXX XXXX
SCLK
MOSI
MISO
/SEL
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Figure 35-11.Packet Structure - SRAM Read Access
On SRAM write access, one or more bytes of write data are transferred on MOSI starting with the third byte of the access
sequence; refer to Figure 35-12. Do not attempt to read or write bytes beyond the SRAM buffer size.
Figure 35-12.Packet Structure - SRAM Write Access
As long as /SEL = L, every subsequent byte read or byte write increments the address counter of the Frame Buffer until
the SRAM access is terminated by /SEL = H.
Figure 35-13 and Figure 35-14 illustrate an example SPI sequence of an Atmel AT86RF233 SRAM access to read and
write a data package of five byte length, respectively.
Figure 35-13.Example SPI Sequence - SRAM Read Access of a 5-byte Data Package
Figure 35-14.Example SPI Sequence - SRAM Write Access of a 5-byte Data Package
Notes: 1. The SRAM access mode is not intended to be used as an alternative to the Frame Buffer access modes (see
“Frame Buffer Access Mode” on page 886).
2. Frame Buffer access violations are not indicated by a TRX_UR interrupt when using the SRAM access mode, for
further details refer to “Interrupt Handling” on page 983.
0reserved[4:0]0MOSI
PHY_STATUSMISO
byte 1 (com m and byte )
0ADDRESS[7:0]
XX
byte 2 (address )
XX
DATA[7:0]
byte 3 (data byte )
XX
DATA[7:0]
byte n-1 (data byte )
XX
DATA[7:0]
byte n(data byte )
0reserved[4:0]1MOSI
PHY_STATUSMISO
byte 1 (com m and byte )
0ADDRESS[7:0]
XX
byte 2 (address )
DATA[7:0]
XX
byte 3 (data byte )
DATA[7:0]
XX
byte n-1 (data byte )
DATA[7:0]
XX
byte n(data byte )
COMMAND ADDRESS XX XX XX XX
PHY_STATUS XX DATA 2DATA 1 DATA 4DATA 3
XX
DATA 5
SCLK
MOSI
MISO
/SEL
COMMAND ADDRESS DATA 1 DATA 2 DATA 3 DATA 4
PHY_STATUS XX XXXX XXXX
DATA 5
XX
SCLK
MOSI
MISO
/SEL
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35.4 Radio Transceiver Status Information
Each AT86RF233 SPI access can return radio transceiver status information which is a first byte transmitted out of MISO
output as the serial data is being shifted into MOSI input. Radio transceiver status information (PHY_STATUS) can be
configured using register bits SPI_CMD_MODE (register 0x04, TRX_CTRL_1) to return TRX_STATUS, PHY_RSSI or
IRQ_STATUS register as shown in below.
35.4.1 Register Description
Underlined values in the AT86RF233 register description indicate reset settings.
35.4.1.1 TRX_CTRL_1
Name: TRX_CTRL_1
Offset: 0x04
Reset: 0x22
Property: -
The TRX_CTRL_1 register is a multi-purpose register to control various operating modes and settings of the radio
transceiver.
zBit 3:2 - SPI_CMD_MODE
Each SPI transfer returns bytes back to the SPI master. The content of the first byte (PHY_STATUS) can be con-
figured using register bits SPI_CMD_MODE.
Bit 7 6543210
0x04 PA_EXT_EM IRQ_2_EXT_
EN
TX_AUTO_
CRC_ON
RX_BL_
CTRL SPI_CMD_MODE IRQ_MASK_
MODE
IRQ_
POLARITY
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0100010
Table 35-3. SPI_CMD_MODE
Value Description
0x0 Default (empty, all bits zero)
0x1 Monitor TRX_STATUS register
0x2 Monitor PHY_RSSI register
0x3 Monitor IRQ_STATUS register
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35.5 Radio Transceiver Identification
AT86RF233 can be identified by four registers. One 8-bit register contains a unique part number (PART_NUM) and one
register contains the corresponding 8-bit version number (VERSION_NUM). Two additional 8-bit registers contain the
JEDEC manufacture ID.
35.5.1 Register Description
35.5.1.1 PART_NUM
Name: PART_NUM
Offset: 0x1C
Reset: 0x0B
Property: -
The register PART_NUM can be used for the radio transceiver identification and includes the part number of the device.
zBit 7:0 - PART_NUM
Bit 7 6543210
0x1C PART_NUM
Access R RRRRRRR
Reset 0 0001011
Table 35-4. PART_NUM
Value Description
0x0B AT86RF233 part number
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35.5.1.2 VERSION_NUM
Name: VERSION_NUM
Offset: 0x1D
Reset: 0x02
Property: -
The register VERSION_NUM can be used for the radio transceiver identification and includes the version number of the
device.
zBit 7:0 - VERSION_NUM
35.5.1.3 MAN_ID_0
Name: MAN_ID_0
Offset: 0x1E
Reset: 0x1F
Property: -
Part one of the JEDEC manufacturer ID.
zBit 7:0 - MAN_ID_0
Bit 7 6543210
0x1D VERSION_NUM
Access R RRRRRRR
Reset 0 0000010
Table 35-5. VERSION_NUM
Value Description
0x02 Revision B
Bit 7 6543210
0x1E MAN_ID_0
Access R RRRRRRR
Reset 0 0011111
Table 35-6. MAN_ID_0
Value Description
0x1F
Atmel JEDEC manufacturer ID,
bits[7:0] of the 32-bit JEDEC manufacturer ID are stored in register bits MAN_ID_0. Bits [15:8] are stored in
register 0x1F (MAN_ID_1). The higher 16 bits of the ID are not stored in registers.
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35.5.1.4 MAN_ID_1
Name: MAN_ID_1
Offset: 0x1F
Reset: 0x00
Property: -
Part two of the JEDEC manufacturer ID.
zBit 7:0 - MAN_ID_1
Bit 7 6543210
0x1F MAN_ID_1
Access R RRRRRRR
Reset 0 0000000
Table 35-7. MAN_ID_1
Value Description
0x00
Atmel JEDEC manufacturer ID,
bits[15:8] of the 32-bit JEDEC manufacturer ID are stored in register bits MAN_ID_1. Bits [7:0] are stored in
register 0x1E (MAN_ID_0). The higher 16 bits of the ID are not stored in registers.
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35.6 Sleep/Wake-up and Transmit Signal (SLP_TR)
The internal SLP_TR input signal to the AT86RF233 is connected to PA20 and has multiple functions. Its function
relates to the current state of the AT86RF233 and is summarized in Table 35-8. The radio transceiver states are
explained in detail in “AT86RF233 Operating Modes” on page 902.
In states PLL_ON and TX_ARET_ON, the internal SLP_TR signal connected to PA20 is used as trigger input to initiate a
TX transaction. Here SLP_TR is sensitive on rising edge only.
After initiating a state change by a rising edge at of the SLP_TR signal in radio transceiver states TRX_OFF or
PREP_DEEP_SLEEP, the radio transceiver remains in the new state as long as the signal is logical high and returns to
the preceding state with the falling edge.
35.6.1 SLEEP state
The SLEEP state is used when radio transceiver functionality is not required, and thus the AT86RF233 can be powered
down to reduce the overall power consumption.
A power-down scenario is shown in Figure 35-15. When the radio transceiver is in TRX_OFF state the microcontroller
forces the AT86RF233 to SLEEP by setting SLP_TR = H. If the CLKM signal provides a clock to the microcontroller this
clock is switched off after 35 CLKM cycles. This enables a microcontroller in a synchronous system to complete its
power-down routine and prevent deadlock situations. The AT86RF233 awakes when the microcontroller releases the
SLP_TR signal. This concept provides the lowest possible power consumption.
The CLKM clock frequency settings for 250kHz and 62.5kHz are not intended to directly clock the microcontroller. When
using these clock rates, CLKM is turned off immediately when entering SLEEP state.
Table 35-8. SLP_TR Multi-Functional Signal
Transceiver Status Function Transition Description
PLL_ON TX start L Ö H Starts frame transmission
TX_ARET_ON TX start L Ö H Starts TX_ARET transaction
BUSY_RX_AACK TX start L Ö H
Starts ACK transmission during RX_AACK slotted operation, see
“RX_AACK Slotted Operation – Slotted Acknowledgement” on
page 926
TRX_OFF Sleep L Ö H Takes the radio transceiver into SLEEP state, CLKM disabled
PREP_DEEP_SLEEP Deep Sleep L Ö H Takes the radio transceiver into DEEP_SLEEP state, CLKM
disabled
SLEEP Wakeup H Ö L Takes the radio transceiver back into TRX_OFF state, level
sensitive
DEEP_SLEEP Wakeup H Ö L Takes the radio transceiver back into TRX_OFF state, level
sensitive
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Figure 35-15.Sleep and Wake-Up Initiated by Asynchronous Microcontroller Timer
Note: 1. Timing figures tTR3 and tTR1a refer to Table 36-1 on page 910.
35.6.2 DEEP_SLEEP state
The DEEP_SLEEP state is used when radio transceiver functionality is not required, and thus the Atmel AT86RF233 can
be powered down to reduce the overall power consumption.
When the radio transceiver is in PREP_DEEP_SLEEP state the microcontroller forces the AT86RF233 to DEEP_SLEEP
by setting SLP_TR = H. If CLKM provides a clock to the microcontroller this clock is switched off after 35 CLKM cycles.
This enables a microcontroller in a synchronous system to complete its power-down routine and prevent deadlock
situations. The AT86RF233 awakes when the microcontroller releases SLP_TR and goes into TRX_OFF state. This
concept provides the lowest possible power consumption.
The CLKM clock frequency settings for 250kHz and 62.5kHz are not intended to directly clock the microcontroller. When
using these clock rates, CLKM is turned off immediately when entering DEEP_SLEEP state.
Notes: 1. After leaving the DEEP_SLEEP state the CLKM clock frequency is set back to 1MHz.
2. If the radio transceiver is in DEEP_SLEEP state the register contents are cleared.
CLKM
SLP_TR
t
TR 3
(35 CLKM clock cycles) CLKM off
t
TR 1a
async timer elapses
(microcontroller)
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35.7 Interrupt Logic
35.7.1 Overview
AT86RF233 differentiates between nine interrupt events (eight physical interrupt registers, one shared by two functions).
Each interrupt is enabled by setting the corresponding bit in the interrupt mask register 0x0E (IRQ_MASK). Internally,
each pending interrupt is flagged in the interrupt status register. All interrupt events are OR-combined to a single interrupt
signal (IRQ). If an interrupt is issued, the signal IRQ = H, the microcontroller shall read the interrupt status
register 0x0F (IRQ_STATUS) to determine the source of the interrupt. A read access to this register clears the interrupt
status register and thus the IRQ signal to the MCU, too.
Interrupts are not cleared automatically when the event trigger for respective interrupt flag bit in the
register 0x0F (IRQ_STATUS) is no longer active. Only a read access to register 0x0F (IRQ_STATUS) clears the flag
bits. Exceptions are IRQ_0 (PLL_LOCK) and IRQ_1 (PLL_UNLOCK) where each is cleared in addition by the
appearance of the other.
The supported interrupts for the Basic Operating Mode are summarized in Table 35-9.
Note: 1. The IRQ_4 (AWAKE_END) interrupt can usually not be seen when the transceiver enters TRX_OFF state after P_ON,
DEEP_SLEEP, or RESET, because register 0x0E (IRQ_MASK) is reset to mask all interrupts. It is recommended to enable
IRQ_4 (AWAKE_END) to be notified once the TRX_OFF state is entered.
Table 35-9. Interrupt Description in Basic Operating Mode
IRQ_NAME Description Section
IRQ_7 (BAT_LOW) Indicates a supply voltage below the programmed threshold. “Interrupt Handling” on page
988
IRQ_6 (TRX_UR) Indicates a Frame Buffer access violation. “Interrupt Handling” on page
983
IRQ_5 (AMI) Indicates address matching. “Frame Filter” on page 952
IRQ_4 (CCA_ED_DONE) Multi-functional interrupt:
1. AWAKE_END:
Indicates finished transition to TRX_OFF state from P_ON,
SLEEP, DEEP_SLEEP, or RESET state.
2. CCA_ED_DONE:
Indicates the end of a CCA or ED measurement.
“TRX_OFF – Clock State” on
page 904
“Interrupt Handling” on page
966
“Interrupt Handling” on page
969
IRQ_3 (TRX_END) RX: Indicates the completion of a frame reception.
TX: Indicates the completion of a frame transmission.
“Interrupt Handling” on page
906
“Interrupt Handling” on page
906
IRQ_2 (RX_START) Indicates the start of a PSDU reception; the AT86RF233
state changed to BUSY_RX;
the PHR can be read from Frame Buffer.
“Interrupt Handling” on page
906
IRQ_1 (PLL_UNLOCK) Indicates PLL unlock. If the radio transceiver is in BUSY_TX
/ BUSY_TX_ARET state, the PA is turned off immediately.
“Interrupt Handling” on page
995
IRQ_0 (PLL_LOCK) Indicates PLL lock. “Interrupt Handling” on page
995
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The interrupt handling in Extended Operating Mode is described in “Interrupt Handling” on page 931.
35.7.2 Interrupt Mask Modes and IRQ Signal Polarity
If register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, an interrupt event can be read from IRQ_STATUS
register even if the interrupt itself is masked. However, in that case no timing information for this interrupt is provided. The
Table 35-10, Figure 35-16, and Figure 35-17 describes the function.
Figure 35-16.IRQ_MASK_MODE = 0
Figure 35-17.IRQ_MASK_MODE = 1
The AT86RF233 IRQ signal polarity can be configured with register bit IRQ_POLARITY (register 0x04, TRX_CTRL_1).
The default behavior is active high, which means that the signal IRQ = H issues an interrupt request.
If the “Frame Buffer Empty Indicator” is enabled during Frame Buffer read access, the IRQ signal has an alternative
functionality, refer to “Frame Buffer Empty Indicator” on page 1030 for details.
A solution to monitor the IRQ_STATUS register (without clearing it) is described in “Register Description” on page 890.
Table 35-10. IRQ Mask Configuration
IRQ_MASK Value IRQ_MASK Mode Description
0 0 IRQ is suppressed entirely and none of interrupt sources are shown in register
IRQ_STATUS.
0 1 IRQ is suppressed entirely but all interrupt causes are shown in register
IRQ_STATUS.
≠ 0 0All enabled interrupts are signaled on the internal IRQ signal to the
microcontroller and are also shown in register IRQ_STATUS.
≠ 0 1All enabled interrupts are signaled on the internal IRQ signal to the
microcontroller and all interrupt causes are shown in register IRQ_STATUS.
IRQ_MASK
(register 0x0E)
IRQ_STATUS
(register 0x0F) OR IRQ
Interrupt Sources
.
.
.
OR IRQ
Interrupt Sources
IRQ_MASK
(register 0x0E)
.
.
.
IRQ_STATUS
(register 0x0F)
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35.7.3 Register Description
35.7.3.1 IRQ_MASK
Name: IRQ_MASK
Offset: 0x0E
Reset: 0x00
Property: -
The IRQ_MASK register controls the interrupt signaling via the internal IRQ signal to the microcontroller.
zBit 7:0 - IRQ_MASK
Mask register for interrupts. IRQ_MASK[7] correspondents to IRQ_7 (BAT_LOW). IRQ_MASK[0] correspondents
to IRQ_0 (PLL_LOCK).
Bit 7 6543210
0x0E IRQ_MASK
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0000000
Table 35-11. IRQ_MASK
Value Description
0x00 The IRQ_MASK register is used to enable or disable individual interrupts. An interrupt is enabled if the
corresponding bit is set to one. All interrupts are disabled after power-on sequence (P_ON or DEEP_SLEEP state)
or reset (RESET state).
Valid values are [0xFF, 0xFE, …, 0x00].
Note: 1. If an interrupt is enabled it is recommended to read the interrupt status register 0x0F (IRQ_STATUS) first
to clear the history.
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35.7.3.2 IRQ_STATUS
Name: IRQ_STATUS
Offset: 0x0F
Reset: 0x00
Property: -
The IRQ_STATUS register contains the status of the pending interrupt requests.
For more information to meanings of interrupts, see Table 35-9.
By reading the register after an interrupt is signaled by the IRQ signal to the microcontroller the source of the issued
interrupt can be identified. A read access to this register resets all interrupt bits, and so clears the IRQ_STATUS register.
Notes: 1. If register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, an interrupt event can be read from
IRQ_STATUS register even if the interrupt itself is masked; refer to Figure 35-17. However in that case no timing
information for this interrupt is provided.
2. If register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, it is recommended to read the interrupt sta-
tus register 0x0F (IRQ_STATUS) first to clear the history.
Bit 7 6543210
0x0F IRQ_7_BAT_
LOW
IRQ_6_TRX_
UR IRQ_5_AMI
IRQ_4_
CCA_ED_
DONE
IRQ_3_TRX_
END
IRQ_2_RX_
START
IRQ_1_PLL_
UNLOCK
IRQ_0_PLL_
LOCK
Access R RRRRRRR
Reset 0 0000000
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35.7.3.3 TRX_CTRL_1
Name: TRX_CTRL_1
Offset: 0x04
Reset: 0x22
Property: -
The TRX_CTRL_1 register is a multi-purpose register to control various operating modes and settings of the radio
transceiver.
zBit 6 - IRQ_2_EXT_EN
The register bit IRQ_2_EXT_EN controls signaling for time stamping via DIG2 signal.
The timing of a received frame can be determined by the DIG2 signal. If register bit IRQ_2_EXT_EN is set to one, the
reception of a PHR field is directly issued on DIG2, similar to interrupt IRQ_2 (RX_START).
For further details refer to “RX and TX Frame Time Stamping (TX_ARET)” on page 1027.
zBit 1 - IRQ_MASK_MODE
The radio transceiver supports polling of interrupt events. Interrupt polling is enabled by setting register bit
IRQ_MASK_MODE.
With the interrupt polling enabled (IRQ_MASK_MODE = 1) the interrupt events are flagged in the
register 0x0F (IRQ_STATUS) when their respective mask bits are disabled in the register 0x0E (IRQ_MASK).
zBit 0 - IRQ_POLARITY
The register bit IRQ_POLARITY controls the polarity for IRQ signal to the microcontroller. The default polarity of
the IRQ signal is active high. The polarity can be configured to active low via register bit IRQ_POLARITY.
Bit 7 6543210
0x04 PA_EXT_EM IRQ_2_EXT_
EN
TX_AUTO_
CRC_ON
RX_BL_
CTRL SPI_CMD_MODE IRQ_MASK_
MODE
IRQ_
POLARITY
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0100010
Table 35-12. IRQ_2_EXT_EN
Value Description
0x0 Time stamping over the internal DIG2 signal to the microcontroller is disabled
0x1(1) Time stamping over the internal DIG2 signal to the microcontroller is enabled
Note: 1. The DIG2 signal is also active if the corresponding interrupt event IRQ_2 (RX_START) mask bit in regis-
ter 0x0E (IRQ_MASK) is set to zero. The signal remains at high level until the end of the frame receive or
transmit procedure.
Table 35-13. IRQ_MASK_MODE
Value Description
0x0 Interrupt polling is disabled.
Masked off IRQ bits will not appear in IRQ_STATUS register.
0x1 Interrupt polling is enabled.
Masked off IRQ bits will appear in IRQ_STATUS register.
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This setting does not affect the polarity of the “Frame Buffer Empty Indicator”, refer to “Frame Buffer Empty Indicator” on
page 1030. The Frame Buffer Empty Indicator is always active high.
Table 35-14. IRQ_POLARITY
Value Description
0x0 IRQ signal is high active
0x1 IRQ signal is low active
Note: 1. A modification of register bit IRQ_POLARITY has no influence to RX_BL_CTRL behavior.
902
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36. AT86RF233 Operating Modes
36.1 Basic Operating Mode
This section summarizes all states to provide the basic functionality of AT86RF233, such as receiving and transmitting
frames, the power-on sequence, sleep, and deep sleep. The Basic Operating Mode is designed for IEEE 802.15.4 and
general ISM band applications; the corresponding radio transceiver states are shown in Figure 36-1.
Figure 36-1. Basic Operating Mode State Diagram
For timing, refer to Table 36-1 on page 910
36.1.1 State Control
The radio transceiver’s states are controlled by shifting serial digital data using the SPI to write individual commands to
the command register bits TRX_CMD (register 0x02, TRX_STATE). Change of the transceiver state can also be
triggered by driving directly two signals SLP_TR and /RST. A successful state change can be verified by reading the
radio transceiver status from register bits TRX_STATUS (register 0x01, TRX_STATUS).
If TRX_STATUS = 0x1F (STATE_TRANSITION_IN_PROGRESS) the AT86RF233 is in a state transition. Do not try to
initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS.
PLL_ON
RX_ON
PLL_ON
TRX_OFF
(Clock State)
XOSCRF=ON
Pull=OFF
RX_ON
(all states except P_ON)
FORCE_TRX_OFF
(all states except SLEEP or
DEEP_SLEEP)
SHR
Detected
Frame
End
Frame
End
BUSY_TX
(Transmit State)
PLL_ON
(PLL State)
TX_START
or
TRX_OFF
TRX_OFF
4
57
6
8
9
11
10
12 13 /RST = H
FORCE_PLL_ON
(all states except DEEP_SLEEP,
SLEEP, or P_ON)
14
SLP_TR = H
Legend:
Blue: SPI Write to Register TRX_STATE (0x02)
Red: Control signals from the microcontroller
Green: Event
Basic Operating Mode States
State transition number
RX_ON
(Rx Listen State)
BUSY_RX
(Receive State)
RESET
X
(from all states)
/RST = L
2
TRX_OFF
SLP_TR = H
3
P_ON
(Power-on after V
DD
)
XOSCRF=ON
Pull=ON
SLEEP
(Sleep State)
XOSCRF=OFF
Pull=OFF
SLP_TR = L
DEEP_SLEEP
(Sleep State)
XOSCRF=OFF
Pull=ON
SLP_TR=H
XOSCRF=ON
Pull=OFF
PREP_
DEEP_SLEEP
(Prepare Sleep State)
SLP_TR=L
TRX_OFF
PREP_DEEP_SLEEP
15 16
17 18
19
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The SLP_TR signal that has to be driven by the microcontroller has multiple functions (refer to “Sleep/Wake-up and
Transmit Signal (SLP_TR)” on page 894). Depending on the radio transceiver state, a rising edge of the SLP_TR signal
causes the following state transitions:
A low level on /RST causes a reset of all registers (register bits CLKM_CTRL are shadowed, for details, refer to “Master
Clock Signal Output (CLKM)” on page 991) and forces the radio transceiver into TRX_OFF state. However, if the device
was in P_ON state it remains in the P_ON state.
For all states except SLEEP and DEEP_SLEEP, the state change commands FORCE_TRX_OFF or TRX_OFF lead to a
transition into TRX_OFF state. If the radio transceiver is in active receive or transmit states (BUSY_*), the command
FORCE_TRX_OFF interrupts these active processes, and forces an immediate transition to TRX_OFF. In contrast a
TRX_OFF command is stored until an active state (receiving or transmitting) has been finished. After that the transition to
TRX_OFF is performed.
For a fast transition from any non sleep states to PLL_ON state the command FORCE_PLL_ON is provided. Active
processes are interrupted. In contrast to FORCE_TRX_OFF, this command does not disable PLL and analog voltage
regulator (AVREG). It is not available in states P_ON, SLEEP, DEEP_SLEEP, or RESET.
The completion of each requested state change shall always be confirmed by reading the register bits TRX_STATUS
(register 0x01, TRX_STATUS).
Note: If FORCE_TRX_OFF and FORCE_PLL_ON commands are used, it is recommended to set SLP_TR = L before.
36.1.2 Basic Operating Mode Description
36.1.2.1 P_ON – Power-On after VDD
When the external supply voltage (VDD) is firstly applied to the AT86RF233, the radio transceiver goes into P_ON state
performing an on-chip reset. The crystal oscillator is activated and the master clock is provided at the CLKM clock signal
to the microcontroller after the crystal oscillator has stabilized. CLKM can be used as a clock source for the
microcontroller generic clock controller after it has been configured as described in “Master Clock Signal Output (CLKM)”
on page 991. The SPI interface and digital voltage regulator (DVREG) are enabled.
The on-chip power-on-reset sets all registers to their default values. A dedicated reset signal from the microcontroller at
/RST is not necessary, but recommended for hardware / software synchronization reasons.
All digital inputs are pulled-up or pulled-down during P_ON state, refer to “Pull-up and Pull-down Configuration” on page
19. This is necessary as the microcontroller GPIO signals are floating after power-on or reset. The input pull-up and pull-
down transistors are disabled when the radio transceiver leaves P_ON state towards TRX_OFF state. A reset during
P_ON state does not change the pull-up and pull-down configuration.
Leaving P_ON state, output signals DIG1/DIG2 are pulled-down to digital ground, whereas signals DIG3/DIG4 are
pulled-down to analog ground, unless their configuration is changed.
Prior to leaving P_ON, the microcontroller must set the Atmel AT86RF233 input signals to the default operating values:
SLP_TR = L, /RST = H and /SEL = H.
All interrupts are disabled by default. Thus, interrupts for state transition control are to be enabled first, for example
enable IRQ_4 (AWAKE_END) to indicate a state transition to TRX_OFF state or interrupt IRQ_0 (PLL_LOCK) to signal a
zTRX_OFF -> SLEEP (Level sensitive)
zPLL_ON -> BUSY_TX
zPREP_ DEEP_SLEEP -> DEEP_SLEEP (Level sensitive)
Whereas the falling edge of SLP_TR causes the following state transitions:
zSLEEP -> TRX_OFF (Level sensitive)
zDEEP_SLEEP -> TRX_OFF (Level sensitive)
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locked PLL in PLL_ON state. In P_ON state a first access to the radio transceiver registers is possible after a master
clock is provided at the internal CLKM clock signal to the microcontroller, refer to tTR1 in Table 36-1 on page 910.
Once the supply voltage has stabilized and the crystal oscillator has settled (refer to parameter tXTAL in Table 36-2 on
page 912), the interrupt mask for the AWAKE_END should be set. A valid SPI write access to register bits TRX_CMD
(register 0x02, TRX_STATE) with the command TRX_OFF or FORCE_TRX_OFF initiate a state change from P_ON
towards TRX_OFF state, which is then indicated by an interrupt IRQ_4 (AWAKE_END) if enabled.
36.1.2.2 SLEEP – Sleep State
In SLEEP state, the radio transceiver is disabled. No circuitry is operating beyond the circuitry monitoring SLP_TR and
/RST. This state can only be entered from state TRX_OFF, by setting the SLP_TR = H.
If CLKM is enabled with a clock rates higher than 250kHz, the SLEEP state is entered 35 CLKM cycles after the rising
edge of SLP_TR. At that time CLKM is turned off. If the CLKM output is already turned off (register bits
CLKM_CTRL = 0), the SLEEP state is entered immediately. At clock rates 250kHz and 62.5kHz, the main clock at CLKM
is turned off immediately.
Setting SLP_TR = L returns the radio transceiver back to the TRX_OFF state. During SLEEP state the radio transceiver
register contents and the AES register contents remain valid while the contents of the Frame Buffer are lost.
/RST = L in SLEEP state returns the radio transceiver to TRX_OFF state and thereby sets all registers to their default
values. Exceptions are register bits CLKM_CTRL (register 0x03, TRX_CTRL_0). These register bits require a specific
treatment, for details see “Master Clock Signal Output (CLKM)” on page 991.
36.1.2.3 PREP_DEEP_SLEEP – Deep Sleep Preparation State
The state PREP_DEEP_SLEEP is the preparation state for DEEP_SLEEP state. The state can be reached by writing the
command PREP_DEEP_SLEEP to register bits TRX_CMD (register 0x02, TRX_STATE).
If CLKM is enabled with a clock rates higher than 250kHz, the DEEP_SLEEP state is entered 35 CLKM cycles after the
rising edge of SLP_TR. At that time CLKM is turned off. If the CLKM output is already turned off (register bits
CLKM_CTRL = 0), the DEEP_SLEEP state is entered immediately. At clock rates 250kHz and 62.5kHz, the main clock
at CLKM is turned off immediately.
36.1.2.4 DEEP_SLEEP – Deep Sleep State
In DEEP_SLEEP state, the entire radio transceiver is disabled. No circuitry is operating beyond the circuitry monitoring
SLP_TR. The radio transceiver current consumption is reduced to leakage current only. This state can only be entered
from state PREP_DEEP_SLEEP, by setting the SLP_TR = H.
Setting SLP_TR = L returns the radio transceiver back to the TRX_OFF state. After DEEP_SLEEP state the radio
transceiver register contents and the AES register contents obtain the reset values while the contents of the Frame
Buffer are lost. The CLKM starts with the default 1MHz master clock at CLKM clock signal to the microcontroller after the
crystal oscillator has stabilized.
All AT86RF233 digital inputs are pulled-up or pulled-down during DEEP_SLEEP state, refer to “Pull-up and Pull-down
Configuration” on page 19, except SLP_TR.
36.1.2.5 TRX_OFF – Clock State
In TRX_OFF the crystal oscillator is running and the master clock is available if enabled. The SPI interface and digital
voltage regulator are enabled, thus the radio transceiver registers, the Frame Buffer and security engine (AES) are
accessible (see “Frame Buffer” on page 981 and “Security Module (AES)” on page 1005).
In contrast to P_ON state the pull-up and pull-down configuration is disabled.
Notes: 1. SLP_TR and /RST are available for state control.
2. The analog front-end is disabled during TRX_OFF state.
Entering the TRX_OFF state from P_ON, SLEEP, DEEP_SLEEP or RESET state is indicated by interrupt IRQ_4
(AWAKE_END) if enabled.
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36.1.2.6 PLL_ON – PLL State
Entering the PLL_ON state from TRX_OFF state enables the analog voltage regulator (AVREG) first. After the voltage
regulator has been settled (see Table 36-2 on page 912), the PLL frequency synthesizer is enabled. When the PLL has
been settled at the receive frequency to a channel defined by register bits CHANNEL (register 0x08, PHY_CC_CCA) or
register bits CC_NUMBER (register 0x13, CC_CTRL_0) and CC_BAND (register 0x14, CC_CTRL_1), refer to “RF
Channel Selection” on page 994, a successful PLL lock is indicated by issuing an interrupt IRQ_0 (PLL_LOCK).
If an RX_ON command is issued in PLL_ON state, the receiver is enabled immediately. If the PLL has not been settled
before the state change nevertheless takes place. Even if the register bits TRX_STATUS (register 0x01, TRX_STATUS)
indicates RX_ON, actual frame reception can only start once the PLL has locked.
The PLL_ON state corresponds to the TX_ON state in IEEE 802.15.4.
36.1.2.7 RX_ON and BUSY_RX – RX Listen and Receive State
In RX_ON state the receiver is in the RX data polling mode and the PLL frequency synthesizer is locked to its
preprogrammed frequency.
The AT86RF233 receive mode is internally separated into RX_ON state and BUSY_RX state. There is no difference
between these states with respect to the analog radio transceiver circuitry, which are always turned on. In both states,
the receiver and the PLL frequency synthesizer are enabled.
During RX_ON state, the receiver listens for incoming frames. After detecting a valid synchronization header (SHR), the
Atmel AT86RF233 automatically enters the BUSY_RX state. The reception of a valid PHY header (PHR) generates an
IRQ_2 (RX_START) if enabled.
During PSDU reception, the frame data are stored continuously in the Frame Buffer until the last byte was received. The
completion of the frame reception is indicated by an interrupt IRQ_3 (TRX_END) and the radio transceiver reenters the
state RX_ON. At the same time the register bit RX_CRC_VALID (register 0x06, PHY_RSSI) is updated with the result of
the FCS check (see “Frame Check Sequence (FCS)” on page 961).
Received frames are passed to the frame filtering unit, refer to “Frame Filter” on page 952. If the content of the MAC
addressing fields (refer to [2] IEEE 802.15.4-2006 Section 7.2.1) generates a match, IRQ_5 (AMI) interrupt is issued,
refer to “Interrupt Logic” on page 896. The expected address values are to be stored in registers 0x20 – 0x2B (Short
address, PAN-ID and IEEE address). Frame filtering is available in Basic Operating Mode and Extended Operating
Mode, refer to “Frame Filter” on page 952.
Leaving state RX_ON is possible by writing a state change command to register bits TRX_CMD in register 0x02
(TRX_STATE).
36.1.2.8 BUSY_TX – Transmit State
In the BUSY_TX state AT86RF233 is in the data transmission state.
A transmission can only be initiated from the PLL_ON state. The transmission can be started either by driving event such
as:
zA rising edge on SLP_TR, or
zA serial TX_START command via the SPI to register bits TRX_CMD (register 0x02, TRX_STATE).
Either of these takes the radio transceiver into the BUSY_TX state. Refer to “Frame Transmit Procedure” on page 1003
for more details.
During the transition to the BUSY_TX state, the PLL frequency shifts to the transmit frequency, refer to “PLL Settling
Time and Frequency Agility” on page 994. The actual transmission of the first data chip of the SHR starts after 16µs to
allow PLL settling and PA ramp-up, see Figure 36-7. After transmission of the SHR, the Frame Buffer content is
transmitted. In case the PHR indicates a frame length of zero, the transmission is aborted immediately after the PHR
field.
After the frame transmission has been completed, the AT86RF233 automatically turns off the power amplifier, generates
an IRQ_3 (TRX_END) interrupt and returns into PLL_ON state.
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36.1.2.9 RESET State
The RESET state is used to set back the state machine and to reset all registers of Atmel AT86RF233 to their default
values; exceptions are register bits CLKM_CTRL (register 0x03, TRX_CTRL_0). These register bits require a specific
treatment, for details see “Master Clock Signal Output (CLKM)” on page 991.
Once in RESET state a device enters TRX_OFF state by setting or pulling the internal reset signal /RST to the
AT86RF233 high. If the device is still in the P_ON state it remains in the P_ON state though. A reset is triggered by
pulling /RST low (/RST = L) and the state returns after setting /RST = H. The reset pulse should have a minimum length
as specified in “Reset Procedure” on page 909 (parameter t10). During reset, the microcontroller has to set the radio
transceiver control signals SLP_TR and /SEL to their default values.
An overview about the register reset values is provided in Table 41-2 on page 1054.
36.1.3 Interrupt Handling
All interrupts provided by the AT86RF233 (see Table 35-9 on page 896) are supported in Basic Operating Mode. For
example, interrupts are provided to observe the status of radio transceiver RX and TX operations.
When being in receive mode, IRQ_2 (RX_START) indicates the detection of a valid PHR first, IRQ_5 (AMI) an address
match, and IRQ_3 (TRX_END) the completion of the frame reception. During transmission, IRQ_3 (TRX_END) indicates
the completion of the frame transmission.
Figure 36-2 shows an example for a transmit/receive transaction between two devices and the related interrupt events in
Basic Operating Mode. Device 1 transmits a frame containing a MAC header (in this example of length seven), MAC
payload, and a valid FCS. The end of the frame transmission is indicated by IRQ_3 (TRX_END).
The frame is received by Device 2. Interrupt IRQ_2 (RX_START) indicates the detection of a valid PHR field and
IRQ_3 (TRX_END) the completion of the frame reception. If the frame passes the Frame Filter (refer to “Frame Filter” on
page 952), an address match interrupt IRQ_5 (AMI) is issued after the reception of the MAC header (MHR). The received
frame is stored in the Frame Buffer.
In Basic Operating Mode the third interrupt IRQ_3 (TRX_END) is issued at the end of the received frame. In Extended
Operating Mode, refer to “Extended Operating Mode” on page 915; the interrupt is only issued if the received frame
passes the address filter and the FCS is valid. Further exceptions are explained in “Extended Operating Mode” on page
915.
Processing delay tIRQ is a typical value, refer to “Digital Interface Timing Characteristics” on page 1101.
Figure 36-2. Timing of RX_START, AMI and TRX_END Interrupt in Basic Operation Modes
128 160 1920192+(9+m)*32-16 Time [µs]
RX
(Device 2)
IRQ_2 (RX_START)
tIRQ
RX_ON RX_ON
IRQ
TRX_STATE
Interrupt latency
TRX_ENDIRQ_5 (AMI)
tIRQ tIRQ
BUSY_RX
IRQ_3 (TRX_END)
TX
(Device1)
PLL_ON BUSY_TX PLL_ON
IRQ
SLP_TR
TRX_STATE
Typ. Processing Delay
Frame
on Air
Preamble SFD PHR MSDU
411 mNumber of Octets
Frame Content MHR
7
FCS
2
tTR10
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36.1.4 Basic Operating Mode Timing
This section depicts AT86RF233 state transitions and their timing properties. Timing figures are explained in Table 36-1,
Table 36-2 and “Digital Interface Timing Characteristics” on page 1101.
36.1.4.1 Power-on Procedure
The power-on procedure to P_ON state is shown in Figure 36-3.
Figure 36-3. Power-on Procedure to P_ON
When the external supply voltage (VDD) is initially supplied to the AT86RF233, the radio transceiver enables the crystal
oscillator (XOSCRF) and the internal 1.8V voltage regulator for the digital domain (DVREG). After tTR1 = 330µs (typ.), the
master clock signal is available at the internal CLKM clock signal to the microcontroller. As soon as CLKM is available the
SPI is enabled and can be used to control the transceiver. As long as no state change towards state TRX_OFF is
performed, the radio transceiver remains in P_ON state.
36.1.4.2 Wake-up Procedure from SLEEP
The wake-up procedure from SLEEP state is shown in Figure 36-4.
Figure 36-4. Wake-Up Procedure from SLEEP State
The radio transceiver’s SLEEP state is left by releasing SLP_TR to logic low. This restarts the XOSCRF and DVREG.
After tTR2 = 210µs (typ.) the radio transceiver enters TRX_OFF state. The internal clock signal is available and provided
by CLKM, if enabled.
This procedure is similar to the Power-on Procedure. However the radio transceiver automatically proceeds to the
TRX_OFF state. During this, transition the filter-tuning network (FTN) calibration is performed. Entering TRX_OFF state
is signaled by IRQ_4 (AWAKE_END), if this interrupt was enabled by the appropriate mask register bit.
36.1.4.3 Wake-up Procedure from DEEP_SLEEP
The wake-up procedure from DEEP_SLEEP state is shown in Figure 36-5.
XOSCRF, DVREG
0
Event
State
Block
CLKM on
Time [μs]
Time t
TR2
TRX_OFF
IRQ_4 (AWAKE_END)SLP_TR = L
SLEEP
XOSCRF, DVREG XOSCRF, DVREGFTN
200
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Figure 36-5. Wake-Up Procedure from DEEP_SLEEP State
The AT86RF233 radio transceiver’s DEEP_SLEEP state is left by releasing SLP_TR to logic low. This restarts the
XOSCRF and DVREG. After tTR18 = 360µs (typ.) the radio transceiver enters TRX_OFF state. The internal clock signal is
available and provided at a default rate of 1MHz to CLKM.
This procedure is similar to the Power-on Procedure. However the radio transceiver automatically proceeds to the
TRX_OFF state. During this, transition the filter-tuning network (FTN) calibration is performed.
36.1.4.4 PLL_ON and RX_ON States
The transition from TRX_OFF to PLL_ON or RX_ON mode is shown in Figure 36-6.
Figure 36-6. Transition from TRX_OFF to PLL_ON or RX_ON State
Notes: 1. If TRX_CMD = RX_ON in TRX_OFF state RX_ON state is entered immediately, even if the PLL has not settled.
2. Timing figures tTR4 and tTR8 refers to Table 36-1 on page 910.
In TRX_OFF state, entering the commands PLL_ON or RX_ON initiates a ramp-up sequence of the internal 1.8V voltage
regulator for the analog domain (AVREG). RX_ON state can be entered any time from PLL_ON state, regardless
whether the PLL has already locked, which is indicated by IRQ_0 (PLL_LOCK). Likewise, PLL_ON state can be entered
any time from RX_ON state.
36.1.4.5 BUSY_TX to RX_ON States
The transition from PLL_ON to BUSY_TX state and subsequently to RX_ON state is shown in Figure 36-7.
0
Event
State
Block
CLKM on
Time [μs]
Time t
TR18
TRX_OFF
IRQ_4 (AWAKE_END)SLP_TR = L
DEEP_
SLEEP
XOSCRF, DVREG XOSCRF, DVREGFTN
350
0
Event
State
Block
80 Time [µs]
Time t
TR4
IRQ_0 (PLL_LOCK)
TRX_OFF
AVREG
Command PLL_ON
PLL RX
PLL_ON
RX_ON
t
TR8
RX_ON
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Figure 36-7. PLL_ON to BUSY_TX to RX_ON Timing
Starting from PLL_ON state, it is further assumed that the PLL has already been locked. A transmission is initiated either
by a rising edge of SLP_TR or by command TX_START. The PLL settles to the transmit frequency and the PA is
enabled. After the duration of tTR10 = 16µs, the AT86RF233 changes into BUSY_TX state, transmitting the internally
generated SHR and the PSDU data of the Frame Buffer. After completing the frame transmission, indicated by
IRQ_3 (TRX_END), the PLL settles back to the receive frequency within tTR11 = 32µs and returns to state PLL_ON.
If during BUSY_TX the radio transmitter is requested to change to a receive state, it automatically proceeds to state
RX_ON upon completion of the transmission.
36.1.4.6 Reset Procedure
The radio transceiver reset procedure is shown in Figure 36-8.
Figure 36-8. Reset Procedure
Note: Timing figure tTR13 refers to Table 36-1, t10, t11 refers to “Digital Interface Timing Characteristics” on page 1101.
/RST = L sets all registers to their default values. Exceptions are register bits CLKM_CTRL (register 0x03,
TRX_CTRL_0), refer to “Master Clock Signal Output (CLKM)” on page 991. After releasing the reset /RST = H, the wake-
up sequence including an FTN calibration cycle is performed, refer to “Automatic Filter Tuning (FTN)” on page 1001.
After that the TRX_OFF state is entered.
Figure 36-8 illustrates the reset procedure once P_ON state was left and the radio transceiver was not in SLEEP or
DEEP_SLEEP state.
The reset procedure is identical for all originating radio transceiver states except of state P_ON, SLEEP, or
DEEP_SLEEP. Instead, the procedures described in “P_ON – Power-On after VDD” on page 903 must be followed to
enter the TRX_OFF state.
If the radio transceiver was in state SLEEP or DEEP_SLEEP, the XOSCRF and DVREG are enabled before entering
TRX_OFF state.
If register bits TRX_STATUS indicates STATE_TRANSITION_IN_PROGRESS during system initialization until the
AT86RF233 reaches TRX_OFF state, do not try to initiate a further state change while the radio transceiver is in this
Time [
µs
]
0 x
16 x
+
32
Time t
TR 11
t
TR 10
Command RX _ ON
State
Block
PLL _ ON RX _ ON BUSY _ TX
SLP_TR
PA PLL PA , TX RX PLL
or command TX _ START
x
Event
State
Block
Time [μs]
/RST
TRX_OFF
x + 30
[IRQ_4 (AWAKE_END)]
0
various
Time >t
10
t
TR13
>t
11
XOSCRF, DVREG XOSCRF, DVREG
x + 10
FTN
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state.
Notes: 1. The reset impulse should have a minimum length t10 = 625ns as specified in “Digital Interface Timing Characteris-
tics” on page 1101.
2. An access to the device should not occur earlier than t11 ≥625ns after releasing the /RST signal; refer to “Digital
Interface Timing Characteristics” on page 1101.
3. A reset overrides an SPI command request that might have been queued.
36.1.4.7 State Transition Timing Summary
The Atmel AT86RF233 transition numbers correspond to Figure 36-1 and do not include SPI access time unless
otherwise stated. See measurement setup in Figure 34-1.
Table 36-1. State Transition Timing
Symbol Parameter Condition Min. Typ. Max. Unit
tTR1 P_ON⇒CLKM is available
Depends on crystal oscillator
setup (CL= 10pF) and external
capacitor at DVDD (100nF
nom.).
330 1000 µs
tTR1a SLEEP⇒CLKM is available
Depends on crystal oscillator
setup (CL= 10pF) and external
capacitor at DVDD (100nF
nom.).
180 1000 µs
tTR1b DEEP_SLEEP⇒CLKM is available
Depends on crystal oscillator
setup (CL= 10pF) and external
capacitor at DVDD (100nF
nom.).
330 1000 µs
tTR2 SLEEP⇒TRX_OFF
Depends on crystal oscillator
setup (CL= 10pF) and external
capacitor at DVDD (100nF
nom.).
210 1000 µs
tTR3 TRX_OFF⇒SLEEP
For fCLKM > 250kHz. 35 CLKM
cycles
Otherwise. 0CLKM
cycles
tTR4 TRX_OFF⇒PLL_ON Depends on external capacitor at
AVDD (100nF nom.). 80 µs
tTR5 PLL_ON⇒TRX_OFF 1µs
tTR6 TRX_OFF⇒RX_ON Depends on external capacitor at
AVDD (100nF nom.). 80 µs
tTR7 RX_ON⇒TRX_OFF 1µs
tTR8 PLL_ON⇒RX_ON 1µs
tTR9 RX_ON⇒PLL_ON Transition time is also valid for
TX_ARET_ON, RX_AACK_ON. 1µs
tTR10 PLL_ON⇒BUSY_TX
When asserting SLP_TR or
TRX_CMD = TX_START first
symbol transmission is delayed
by one symbol period (PLL
settling and PA ramp-up).
16 µs
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The state transition timing is calculated based on the timing of the individual blocks shown in Figure 36-3 to Figure 36-8.
The worst case values include maximum operating temperature, minimum supply voltage, and device parameter
variations.
tTR11 BUSY_TX⇒PLL_ON PLL settling time. 32 µs
tTR12 Various states⇒TRX_OFF
Using TRX_CMD =
FORCE_TRX_OFF; not valid for
SLEEP or DEEP_SLEEP.
1µs
tTR13 RESET⇒TRX_OFF Not valid for P_ON, SLEEP, or
DEEP_SLEEP. 26 µs
tTR14 Various states⇒PLL_ON
Using TRX_CMD =
FORCE_PLL_ON; not valid for
P_ON, SLEEP, DEEP_SLEEP, or
RESET.
1µs
tTR15 P_ON⇒TRX_OFF Using TRX_CMD = TRX_OFF
directly after CLKM is available. 360 1000 µs
tTR16 PREP_DEEP_SLEEP⇒TRX_OFF 1µs
tTR17 TRX_OFF⇒PREP_DEEP_SLEEP 1µs
tTR18 DEEP_SLEEP⇒TRX_OFF
Depends on crystal oscillator
setup (CL= 10pF) and external
capacitor at DVDD (100nF
nom.).
360 1000 µs
tTR19 PREP_DEEP_SLEEP⇒DEEP_SLEEP
For fCLKM > 250kHz. 35 CLKM
cycles
Otherwise. 0CLKM
cycles
Table 36-1. State Transition Timing (Continued)
Symbol Parameter Condition Min. Typ. Max. Unit
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Table 36-2. Block Initialization and Settling Time
Symbol Parameter Condition Min. Typ. Max. Unit
tXTAL Reference oscillator settling time
Start XTAL⇒clock available at
CLKM. Depends on crystal Q
factor and load capacitor.
330 1000 µs
tFTN FTN calibration time 25 µs
tDVREG DVREG settling time
Depends on external bypass
capacitor at DVDD (CB3 = 100nF
nom., 10µF worst case).
50 1000 µs
tAVREG AVREG settling time
Depends on external bypass
capacitor at AVDD (CB1 = 100nF
nom., 10µF worst case).
50 1000 µs
tPLL_INIT Initial PLL settling time
PLL settling time
TRX_OFF⇒PLL_ON, including
40µs AVREG settling time.
80 250 µs
tPLL_SW PLL settling time on channel switch Duration of channel switch within
frequency band. 11 100 µs
tPLL_CF PLL CF calibration PLL center frequency calibration. 8 8 24 µs
tPLL_DCU PLL DCU calibration PLL DCU calibration. 6 6 µs
tRX_TX RX⇒TX Maximum settling time RX⇒TX. 16 µs
tTX_RX TX⇒RX Maximum settling time TX⇒RX. 32 µs
tSHR_SYNC SHR, sync SHR synchronization period. 32 96 160 µs
tRSSI RSSI, update RSSI update period in receive
states. 2µs
tED ED measurement ED measurement period is eight
symbols. 135 180 µs
tCCA CCA measurement CCA measurement period is
eight symbols. 135 180 µs
tRND Random value, update Random value update period. 1µs
tAES AES core cycle time 23.4 24 µs
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36.1.5 Register Description
36.1.5.1 TRX_STATUS
Name: TRX_STATUS
Offset: 0x01
Reset: 0x00, 0x08
Property: -
The read-only register TRX_STATUS signals the present state of the radio transceiver as well as the status of a CCA
operation.
zBit 4:0 - TRX_STATUS
The register bits TRX_STATUS signal the current radio transceiver status.
A read access to register bits TRX_STATUS reflects the current radio transceiver state. A state change is initiated by
writing a state transition command to register bits TRX_CMD (register 0x02, TRX_STATE). Alternatively, some state
transitions can be initiated by the rising edge of SLP_TR in the appropriate state.
These register bits are used for Basic and Extended Operating Mode, see “Extended Operating Mode” on page 915.
Bit 7 6 5 4 3 2 1 0
0x01 CCA_DONE CCA_STATUS TRX_STATUS
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Table 36-3. TRX_STATUS
Value Description
0x00 P_ON
0x01 BUSY_RX
0x02 BUSY_TX
0x06 RX_ON
0x08 TRX_OFF (CLK Mode)
0x09 PLL_ON (TX_ON)
0x0F(1) SLEEP
0x10 PREP_DEEP_SLEEP
0x11(2) BUSY_RX_AACK
0x12(2) BUSY_TX_ARET
0x16(2) RX_AACK_ON
0x19(2) TX_ARET_ON
0x1F(3) STATE_TRANSITION_IN_PROGRESS
All other values are reserved
Notes: 1. In SLEEP or DEEP_SLEEP state register not accessible.
2. Extended Operating Mode only.
3. Do not try to initiate a further state change while the radio transceiver is in
STATE_TRANSITION_IN_PROGRESS state.
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If the requested state transition has not been completed, the TRX_STATUS returns
STATE_TRANSITION_IN_PROGRESS value. Do not try to initiate a further state change while the radio transceiver is in
STATE_TRANSITION_IN_PROGRESS state. State transition timings are defined in Table 36-1 on page 910.
36.1.5.2 TRX_STATE
Name: TRX_STATE
Offset: 0x02
Reset: 0x00
Property: -
The radio transceiver states are advanced via register TRX_STATE by writing a command word into register bits
TRX_CMD. The read-only register bits TRAC_STATUS indicate the status or result of an Extended Operating Mode
transaction.
zBit 4:0 - TRX_CMD
A write access to register bits TRX_CMD initiate a radio transceiver state transition to the new state.
A write access to register bits TRX_CMD initiates a radio transceiver state transition towards the new state.
These register bits are used for Basic and Extended Operating Mode, see “Extended Operating Mode” on page 915
Bit 7 6 5 4 3 2 1 0
0x02 TRAC_STATUS TRX_CMD
Access R R R R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Table 36-4. TRX_CMD
Value Description
0x00(1) NOP
0x02(2) TX_START
0x03 FORCE_TRX_OFF
0x04(3) FORCE_PLL_ON
0x06 RX_ON
0x08 TRX_OFF (CLK Mode)
0x09 PLL_ON (TX_ON)
0x10 PREP_DEEP_SLEEP
0x16(4) RX_AACK_ON
0x19(4) TX_ARET_ON
All other values are reserved
Notes: 1. TRX_CMD = “0” after power on reset (POR).
2. The frame transmission starts one symbol after TX_START command.
3. FORCE_PLL_ON is not valid for states P_ON, SLEEP, DEEP_SLEEP, and RESET, as well as
STATE_TRANSITION_IN_PROGRESS towards these states.
4. Extended Operating Mode only.
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36.2 Extended Operating Mode
Extended Operating Mode makes up for a large set of automated functionality add-on’s which can be referred to as a
hardware MAC accelerator. These add-on’s go beyond the basic radio transceiver functionality provided by the Basic
Operating Mode. Extended Operating Mode functions handle time critical MAC tasks, requested by the IEEE 802.15.4
standard, in hardware, such as automatic acknowledgement, automatic CSMA-CA, and retransmission. This results in a
more efficient IEEE 802.15.4 software MAC implementation, including reduced code size, and may allow use of a smaller
microcontroller or operation at low clock rates.
The Extended Operating Mode is designed to support IEEE 802.15.4-2006 and IEEE 802.15.4-2011 compliant frames;
the mode is backward compatible to IEEE 802.15.4-2003 and supports non IEEE 802.15.4 compliant frames. This mode
comprises the following procedures:
Automatic acknowledgement (RX_AACK) divides into the tasks:
zFrame reception and automatic FCS check
zConfigurable addressing fields check
zInterrupt indicating address match
zInterrupt indicating frame reception, if it passes address filtering and FCS check
zAutomatic ACK frame transmission (if the received frame passed the address filter and FCS check and if an ACK
is required by the frame type and ACK request)
zSupport of slotted acknowledgment using SLP_TR signal (used for beacon-enabled operation)
Automatic CSMA-CA and Retransmission (TX_ARET) divides into the tasks:
zCSMA-CA, including automatic CCA retry and random backoff
zFrame transmission and automatic FCS field generation
zReception of ACK frame (if an ACK was requested)
zAutomatic retry of transmissions if ACK was expected but not received or accepted
zInterrupt signaling with transaction status
Automatic FCS check and generation, refer to “Frame Check Sequence (FCS)” on page 961, is used by the RX_AACK
and TX_ARET modes. In RX_AACK mode, an automatic FCS check is always performed for incoming frames.
In TX_ARET mode, an ACK which is received within the time required by IEEE 802.15.4 is automatically accepted if the
FCS is valid and the ACK sequence number must match the sequence number of the previously transmitted frame.
Dependent on the value of the frame pending subfield in the received acknowledgement frame received, the transaction
status is set, see register bits TRAC_STATUS (register 0x02, TRX_STATE), “Register Description” on page 933.
An AT86RF233 state diagram, including the Extended Operating Mode states, is shown in Figure 36-9. Orange marked
states represent the Basic Operating Mode; blue marked states represent the Extended Operating Mode.
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Figure 36-9. Extended Operating Mode State Diagram
36.2.1 State Control
The Extended Operating Mode include RX_AACK and TX_ARET modes and are controlled by writing respective
command to register bits TRX_CMD (register 0x02, TRX_STATE). Receive with Automatic Acknowledgement state
RX_AACK_ON and Transmit with Automatic Frame Retransmission and CSMA-CA Retry state TX_ARET_ON can be
Legend:
Blue: SPI Write to Register TRX_STATE (0x02)
Red: Control signals from the microcontroller
Green: Event
Basic Operating Mode States
Extended Operating Mode States
PLL_ON
RX_ON
PLL_ON
TRX_OFF
(Clock State)
XOSCRF =ON
Pull=OFF
RX_ON
(all states except P_ON)
FORCE_TRX_OFF
(all states except SLEEP or
DEEP_SLEEP)
Frame
End
RX_ON
(Rx Listen State)
BUSY_RX
(Receive State)
TRX_OFF
TRX_OFF
4
57
6
8
9
BUSY_RX_AACK BUSY_TX_ARET
SHR
Detected
Trans-
action
Finished
TX_ARET_ON
PLL_ON
SLP_TR=H
or
TX_START
Frame
End
PLL_ON
RX_AACK_ON
TX_ARET_ON
RX_AACK_ON
From / To
TRX_OFF From / To
TRX_OFF
/RST = H
12 13
FORCE_PLL_ON
14
SHR
Detected
TX_ARET_ONRX_AACK_ON
PLL_ON
(PLL State)
RESET
(from all states)
/RST = L
TRX_OFF
TRX_OFF
2
TRX_OFF
SLP_TR = H
3
P_ON
(Power-on after V
DD
)
XOSCRF =ON
Pull=ON
SLEEP
(Sleep State)
XOSCRF =OFF
Pull=OFF
SLP_TR = L
DEEP_SLEEP
(Sleep State)
XOSCRF =OFF
Pull=ON
RX_AACK_ON
TX_ARET_ON
RX_AACK_ON
RX_ON
TX_ARET_ON
RX_ON
XOSCRF =ON
Pull=OFF
PREP_
DEEP_SLEEP
(Prepare Sleep State)
TRX_OFF
PREP_DEEP_SLEEP
Frame
End
BUSY_TX
(Transmit State)
TX_START
or
11
10
SLP_TR = H
15 16
17
SLP_TR=H
SLP_TR=L
18
19
(all states except SLEEP or
DEEP_SLEEP or P_ON)
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entered either from TRX_OFF or PLL_ON state as illustrated in Figure 36-9. The completion of each change state
command shall always be confirmed by reading the register bits TRX_STATUS (register 0x01, TRX_STATUS).
RX_AACK - Receive with Automatic Acknowledgement
A state transition to RX_AACK_ON is initiated by writing the RX_AACK_ON command to the register bits TRX_CMD. On
success, reading register bits TRX_STATUS (register 0x01, TRX_STATUS) returns RX_AACK_ON or
BUSY_RX_AACK. The latter one is returned when a frame is being received.
The RX_AACK Extended Operating Mode is left by writing a new command to the register bits TRX_CMD. If the
AT86RF233 is within a frame receive or acknowledgment procedure (BUSY_RX_AACK), the state change is executed
after finishing. Alternatively, the commands FORCE_TRX_OFF or FORCE_PLL_ON can be used to cancel the
RX_AACK transaction and switch to TRX_OFF or PLL_ON state respectively.
TX_ARET - Transmit with Automatic Frame Retransmission and CSMA-CA Retry
A state transition to TX_ARET_ON is initiated by writing command TX_ARET_ON to register bits TRX_CMD
(register 0x02, TRX_STATE). The radio transceiver is in the TX_ARET_ON state when register bits TRX_STATUS
(register 0x01, TRX_STATUS) return TX_ARET_ON. The TX_ARET transaction (frame transmission) is actually started
by a rising edge on SLP_TR or by writing the command TX_START to register bits TRX_CMD.
The TX_ARET Extended Operating Mode is left by writing a new command to the register bits TRX_CMD. If the
AT86RF233 is in the middle of a CSMA-CA transaction, a frame transmission or an acknowledgment procedure
(BUSY_TX_ARET), the state change is executed after completing of the operation. Alternatively, the command
FORCE_TRX_OFF or FORCE_PLL_ON can be used to instantly terminate the TX_ARET transaction and change into
radio transceiver state TRX_OFF or PLL_ON, respectively.
Note: A state change request from TRX_OFF to RX_AACK_ON or TX_ARET_ON internally passes through PLL_ON state
to initiate the radio transceiver front end. Inserting PLL_ON state and associated delays while performing this transition
are indicated in Table 36-1 on page 910. State transitions can be tracked when interrupt IRQ_0 (PLL_LOCK) is used
as an indicator.
36.2.2 Configuration
As the usage of the Extended Operating Mode is based on Basic Operating Mode functionality, only features beyond the
basic radio transceiver functionality are described in the following sections. For details of the Basic Operating Mode, refer
to “Basic Operating Mode” on page 902.
When using the RX_AACK or TX_ARET modes, the following registers needs to be configured.
RX_AACK configuration steps:
zSet the short address, PAN-ID and IEEE address: Registers 0x20 – 0x2B
zConfigure RX_AACK properties: Registers 0x2C, 0x2E
zHandling of Frame Version Subfield
zHandling of Pending Data Indicator
zCharacterization as PAN coordinator
zHandling of Slotted Acknowledgement
zAdditional Frame Filtering Properties: Registers 0x17, 0x2E
zUse of Promiscuous Mode
zUse of automatic ACK generation
zHandling of reserved frame types
The configuration of the Frame Filter is described in “Configuration” on page 952. The addresses for the address match
algorithm are to be stored in the appropriate address registers. Additional control of the RX_AACK mode is done with
register 0x17 (XAH_CTRL_1) and register 0x2E (CSMA_SEED_1).
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As long as a short address is not set, only broadcast frames and frames matching the full 64-bit IEEE address can be
received.
Configuration examples for different device operating modes and handling of various frame types can be found in
“Description of RX_AACK Configuration Bits” on page 920.
TX_ARET configuration steps:
zSet register bit TX_AUTO_CRC_ON = 1: Register 0x04, TRX_CTRL_1
zConfigure CSMA-CA
zMAX_FRAME_RETRIES: Register 0x2C, XAH_CTRL_0
zMAX_CSMA_RETRIES: Register 0x2C, XAH_CTRL_0
zCSMA_SEED: Registers 0x2D, 0x2E
zMAX_BE, MIN_BE: Register 0x2F, CSMA_BE
zConfigure CCA (see “Clear Channel Assessment (CCA)” on page 968)
MAX_FRAME_RETRIES (register 0x2C, XAH_CTRL_0) defines the maximum number of frame retransmissions.
The register bits MAX_CSMA_RETRIES (register 0x2C, XAH_CTRL_0) configure the number of CSMA-CA retries after
a busy channel is detected.
The register bits CSMA_SEED (registers 0x2D, 0x2E) define a random seed for the backoff-time random-number
generator in the AT86RF233.
The register bits MAX_BE and MIN_BE (register 0x2F, CSMA_BE) set the maximum and minimum CSMA backoff
exponent (see [2]), respectively.
36.2.3 RX_AACK_ON – Receive with Automatic ACK
The RX_AACK Extended Operating Mode handles reception and automatic acknowledgement of IEEE 802.15.4
compliant frames.
The general functionality of the RX_AACK procedure is shown in Figure 36-10.
The gray shaded area is the standard flow of an RX_AACK transaction for IEEE 802.15.4 compliant frames, refer to
“Configuration of IEEE Compliant Scenarios” on page 922. All other procedures are exceptions for specific operating
modes or frame formats, refer to “Configuration of non IEEE 802.15.4 Compliant Scenarios” on page 924.
In RX_AACK_ON state, the Atmel AT86RF233 listens for incoming frames. After detecting a valid PHR, the radio
transceiver changes into BUSY_RX_AACK state and parses the frame content of the MAC header (MHR), refer to “MAC
Protocol Data Unit (MPDU)” on page 948.
If the content of the MAC addressing fields of the received frame (refer to [2] IEEE 802.15.4 Section 7.2.1) matches one
of the configured addresses, dependent on the addressing mode, an address match interrupt IRQ_5 (AMI) is issued,
refer to “Frame Filter” on page 952. The reference address values are to be stored in registers 0x20 – 0x2B (Short
address, PAN-ID and IEEE address). Frame filtering as described in “Frame Filter” on page 952 is also applied in Basic
Operating Mode. However, in Basic Operating Mode, the result of frame filtering or FCS check do not affect the
generation of an interrupt IRQ_3 (TRX_END).
Generally, at nodes configured as a normal device or a PAN coordinator, a frame is indicated by interrupt
IRQ_3 (TRX_END) if the frame passes the Frame Filter and the FCS is valid. The interrupt is issued after the completion
of the frame reception. The microcontroller can then read the frame data. An exception applies if promiscuous mode is
enabled, see “Configuration of IEEE Compliant Scenarios” on page 922. In this case, an interrupt IRQ_3 (TRX_END) is
issued for all frames.
During reception AT86RF233 parses bit[5] (ACK Request) of the frame control field of the received data or MAC
command frame to check if an acknowledgement (ACK) reply is expected. If the bit is set and if the frame passes the
third level of filtering, see IEEE 802.15.4-2006, Section 7.5.6.2, the radio transceiver automatically generates and
transmits an ACK frame. The sequence number is copied from the received frame.
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The content of the frame pending subfield of the ACK response is set by register bit AACK_SET_PD (register 0x2E,
CSMA_SEED_1) when the ACK frame is sent in response to a data request MAC command frame, otherwise this
subfield is set to zero.
By default, the acknowledgment frame is transmitted aTurnaroundTime (12 symbol periods; see [2] IEEE 802.15.4-2006,
Section 6.4.1) after the reception of the last symbol of a data or MAC command frame. Optionally, for non-compliant
networks, this delay can be reduced to two symbols by register bit AACK_ACK_TIME (register 0x17, XAH_CTRL_1).
If the register bit AACK_DIS_ACK (register 0x17, CSMA_SEED_1) is set, no acknowledgement frame is sent even if an
acknowledgment frame is requested. This is useful for operating the MAC hardware accelerator in promiscuous mode,
see “Configuration of IEEE Compliant Scenarios” on page 922.
For slotted operation, the start of the transmission of acknowledgement frames is controlled by SLP_TR, refer to
“RX_AACK Slotted Operation – Slotted Acknowledgement” on page 926.
The status of the RX_AACK operation is indicated by register bits TRAC_STATUS (register 0x02, TRAC_STATUS), see
“Register Description” on page 933.
During the operations described above, the AT86RF233 remains in BUSY_RX_AACK state.
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Figure 36-10.Flow Diagram of RX_AACK
36.2.3.1 Description of RX_AACK Configuration Bits
Overview
RX_AACK configuration as described below shall be done prior to switching the AT86RF233 into state RX_AACK_ON,
refer to “State Control” on page 916.
Reserved Frames
TRX_STATE = RX_AACK_ON
SHR detected
TRX_STATE = BUSY_RX_AACK
Scanning MHR
Frame reception
Frame
Filtering
ACK requested
(see Note 3)
Wait 12 symbol
periods
Transmit ACK
TRX_STATE = RX_AACK_ON
N
Y
N
Y
Generate IRQ_2 (RX_START)
AACK_PROM_MODE
== 1
Generate IRQ_5 (AMI)
Y
Generate IRQ_3 (TRX_END)
Frame reception
Note 3: Additional conditions:
- ACK requested &
- AACK_DIS_ACK==0 &
- frame_version<=AACK_FVN_MODE
Slotted Operation
== 0
Y
AACK_ACK_TIME
== 0
Y
Wait 2 symbol
periods
SLP_TR
rising edge
N
N
Generate IRQ_3
(TRX_END)
N
Y
N
Wait 2 symbol
periods
FCS valid
(see Note 2)
Y
N
AACK_UPLD_RES_FT
== 1
FCS valid
Generate IRQ_3
(TRX_END)
Y
Y
N
N
N
Note 2: FCS check is omitted for Promiscous Mode
FCF[2:0]
> 3
N
Y
Y
Promiscuous Mode
Note 1: Frame Filtering, Promiscuous Mode and
Reserved Frames:
- A radio transceiver in Promiscuous
Mode, or configured to receive Reserved
Frames handles received frames passing
the third level of filtering
- For details refer to the description of
Promiscuous Mode and Reserved
Frame Types
(see Note 1)
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Table 36-5 summarizes all register bits which affect the behavior of an RX_AACK transaction. For frame filtering it is
further required to setup address registers to match the expected address.
A graphical representation of various operating modes is illustrated in Figure 36-10.
The usage of the RX_AACK configuration bits for various operating modes of a node is explained in the following
sections. Configuration bits not mentioned in the following two sections should be set to their reset values according to
Table 41-2 on page 1054.
All registers mentioned in Table 36-5 are described in “Register Summary” on page 932.
The general behavior of the “AT86RF233 Extended Feature Set” on page 1005, settings:
zSFD_VALUE (alternative SFD value)
zANT_DIV (Antenna Diversity)
zRX_PDT_LEVEL (blocking frame reception of lower power signals)
zRPC (Reduced Power Consumption)
are completely independent from RX_AACK mode and can be arbitrarily combined.
Table 36-5. Overview of RX_AACK Configuration Bits
Register
Address
Register
Bits Register Name Description
0x20,0x21
0x22,0x23
0x24
…
0x2B
SHORT_ADDR_0/1
PAN_ID_0/1
IEEE_ADDR_0
…
IEEE_ADDR_7
Setup Frame Filter, see “Configuration” on page 952.
0x0C 7RX_SAFE_MODE Dynamic frame buffer protection, see “Dynamic Frame Buffer
Protection” on page 1032.
0x17 1AACK_PROM_MODE Support promiscuous mode.
0x17 2AACK_ACK_TIME Change auto acknowledge start time.
0x17 4AACK_UPLD_RES_FT
Enable reserved frame type reception, needed to receive non-
standard compliant frames, see “Configuration of non
IEEE 802.15.4 Compliant Scenarios” on page 924.
0x17 5AACK_FLTR_RES_FT
Filter reserved frame types like data frame type, needed for filtering
of non-standard compliant frames, see “Configuration of non
IEEE 802.15.4 Compliant Scenarios” on page 924.
0x2C 0SLOTTED_OPERATIO
N
If set, acknowledgment transmission has to be triggered by
SLP_TR, see “RX_AACK Slotted Operation – Slotted
Acknowledgement” on page 926.
0x2E 3AACK_I_AM_COORD
If set, the device is a PAN coordinator, that is responds to a null
address, see “Configuration of IEEE Compliant Scenarios” on page
922.
0x2E 4AACK_DIS_ACK Disable generation of acknowledgment.
0x2E 5AACK_SET_PD Set frame pending subfield in Frame Control Field (FCF), refer to
“Frame Control Field (FCF)” on page 948.
0x2E 7:6 AACK_FVN_MODE Controls the ACK behavior, depending on FCF frame version
number.
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36.2.3.2 Configuration of IEEE Compliant Scenarios
Device not operating as a PAN Coordinator
Table 36-6 shows a typical Atmel AT86RF233 RX_AACK configuration of an IEEE 802.15.4 device operating as a
normal device, rather than a PAN coordinator or router.
Table 36-6. Configuration of IEEE 802.15.4 Devices
Register
Address
Register
Bits Register Name Description
0x20,0x21
0x22,0x23
0x24
…
0x2B
SHORT_ADDR_0/1
PAN_ID_0/1
IEEE_ADDR_0
…
IEEE_ADDR_7
Setup Frame Filter, see “Configuration” on page 952.
0x0C 7RX_SAFE_MODE 0: Disable frame protection.
1: Enable frame protection.
0x2C 0SLOTTED_OPERATION
0: Slotted acknowledgment transmissions are not to be used.
1: Slotted acknowledgment transmissions are to be used, see
“RX_AACK Slotted Operation – Slotted Acknowledgement” on
page 926.
0x2E 7:6 AACK_FVN_MODE
Controls the ACK behavior, depending on FCF frame version
number.
b00: Acknowledges only frames with version number 0, that is
according to IEEE 802.15.4-2003 frames.
b01: Acknowledges only frames with version number 0 or 1,
that is frames according to IEEE 802.15.4-2006.
b10: Acknowledges only frames with version number 0 or 1 or
2.
b11: Acknowledges all frames, independent of the FCF frame
version number.
1. The default value of the short address is 0xFFFF. Thus, if no short address has been configured, only frames
with either the broadcast address or the IEEE address are accepted by the frame filter.
2. In the IEEE 802.15.4-2003 standard the frame version subfield does not yet exist but is marked as reserved.
According to this standard, reserved fields have to be set to zero. At the same time, the IEEE 802.15.4-2003
standard requires ignoring reserved bits upon reception. Thus, there is a contradiction in the standard which
can be interpreted in two ways:
1. If a network should only allow access to nodes compliant to IEEE 802.15.4-2003, then
AACK_FVN_MODE should be set to zero.
2. If a device should acknowledge all frames independent of its frame version, AACK_FVN_MODE should
be set to three. However, this may result in conflicts with co-existing IEEE 802.15.4-2006 standard com-
pliant networks.
The same holds for PAN coordinators, see below.
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PAN-Coordinator
Table 36-7 shows the AT86RF233 RX_AACK configuration for a PAN coordinator.
Promiscuous Mode or Sniffer
The promiscuous mode is described in IEEE 802.15.4-2006, Section 7.5.6.5. This mode is further illustrated in Figure 36-
10. According to IEEE 802.15.4-2006 when in promiscuous mode, the MAC sub layer shall pass received frames with
correct FCS to the next higher layer and shall not process them further. This implies that received frames should never
be automatically acknowledged.
In order to support sniffer application and promiscuous mode, only second level filter rules as defined by
IEEE 802.15.4-2006, Section 7.5.6.2, are applied to the received frame.
Table 36-8 shows a typical configuration of a device operating in promiscuous mode.
Table 36-7. Configuration of a PAN Coordinator
Register
Address
Register
Bits Register Name Description
0x20,0x21
0x22,0x23
0x24
…
0x2B
SHORT_ADDR_0/1
PAN_ID_0/1
IEEE_ADDR_0
…
IEEE_ADDR_7
Setup Frame Filter, see “Configuration” on page 952.
0x0C 7RX_SAFE_MODE 0: Disable frame protection.
1: Enable frame protection.
0x2C 0SLOTTED_OPERATION
0: Slotted acknowledgment transmissions are not to be used.
1: Slotted acknowledgment transmissions are to be used, see
“RX_AACK Slotted Operation – Slotted Acknowledgement” on
page 926.
0x2E 3AACK_I_AM_COORD 1: Device is PAN coordinator.
0x2E 5AACK_SET_PD 0: Frame pending subfield is not set in FCF.
1: Frame pending subfield is set in FCF.
0x2E 7:6 AACK_FVN_MODE
Controls the ACK behavior, depends on FCF frame version
number.
b00: Acknowledges only frames with version number 0, that is
according to IEEE 802.15.4-2003 frames.
b01: Acknowledges only frames with version number 0 or 1,
that is frames according to IEEE 802.15.4-2006.
b10: Acknowledges only frames with version number 0 or 1 or
2.
b11: Acknowledges all frames, independent of the FCF frame
version number.
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If the AT86RF233 radio transceiver is in promiscuous mode, second level of filtering according to IEEE 802.15.4-2006,
Section 7.5.6.2, is applied to a received frame. However, an IRQ_3 (TRX_END) is issued even if the FCS is invalid.
Thus, it is necessary to read register bit RX_CRC_VALID (register 0x06, PHY_RSSI) after IRQ_3 (TRX_END) in order to
verify the reception of a frame with a valid FCS. Alternatively, bit[7] of byte RX_STATUS can be evaluated, refer to
“Frame Buffer Access Mode” on page 886.
If a device, operating in promiscuous mode, receives a frame with a valid FCS which further passed the third level of
filtering according to IEEE 802.15.4-2006, Section 7.5.6.2, an acknowledgement (ACK) frame would be transmitted. But,
according to the definition of the promiscuous mode, a received frame shall not be acknowledged, even if requested.
Thus, register bit AACK_DIS_ACK (register 0x2E, CSMA_SEED_1) must be set to one to disable ACK generation.
In all receive modes IRQ_5 (AMI) interrupt is issued, when the received frame matches the node’s address according to
the filter rules described in “Frame Filter” on page 952.
Alternatively, in state RX_ON (Basic Operating Mode, refer to “Basic Operating Mode” on page 902), when a valid PHR
is detected, an IRQ_2 (RX_START) is generated and the frame is received. The end of the frame reception is signalized
with an IRQ_3 (TRX_END). At the same time the register bit RX_CRC_VALID (register 0x06, PHY_RSSI) is updated
with the result of the FCS check (see “Frame Check Sequence (FCS)” on page 961). According to the promiscuous
mode definition the register bit RX_CRC_VALID needs to be checked in order to dismiss corrupted frames.
However, the RX_AACK transaction additionally enables extended functionality like automatic acknowledgement and
non-destructive frame filtering.
36.2.3.3 Configuration of non IEEE 802.15.4 Compliant Scenarios
Sniffer
Table 36-9 shows an AT86RF233 RX_AACK configuration to setup a sniffer device. Other RX_AACK configuration bits,
refer to Table 36-5, should be set to their reset values.
All frames received are indicated by an IRQ_2 (RX_START) and IRQ_3 (TRX_END). After frame reception register bit
RX_CRC_VALID (register 0x06, PHY_RSSI) is updated with the result of the FCS check (see “Frame Check Sequence
(FCS)” on page 961). The RX_CRC_VALID bit needs to be checked in order to dismiss corrupted frames.
Table 36-8. Configuration of Promiscuous Mode
Register
Address
Register
Bits Register Name Description
0x20,0x21
0x22,0x23
0x24
…
0x2B
SHORT_ADDR_0/1
PAN_ID_0/1
IEEE_ADDR_0
…
IEEE_ADDR_7
Each address shall be set: 0x00.
0x17 1AACK_PROM_MODE 1: Enable promiscuous mode.
0x2E 4AACK_DIS_ACK 1: Disable generation of acknowledgment.
0x2E 7:6 AACK_FVN_MODE
Controls the ACK behavior, depends on FCF frame version number.
b00: Acknowledges only frames with version number 0, that is
according to IEEE 802.15.4-2003 frames.
b01: Acknowledges only frames with version number 0 or 1, that is
frames according to IEEE 802.15.4-2006.
b10: Acknowledges only frames with version number 0 or 1 or 2.
b11: Acknowledges all frames, independent of the FCF frame version
number.
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This operating mode is similar to the promiscuous mode.
Reception of Reserved Frames
In RX_AACK mode, frames with reserved frame types (refer to Table 37-3 on page 949) can also be handled. This might
be required when implementing proprietary, non-standard compliant, protocols. The reception of reserved frame types is
an extension of the AT86RF233 Frame Filter, see “Frame Filter” on page 952. Received frames are either handled like
data frames, or may be allowed to completely bypass the Frame Filter. The flow chart in Figure 36-10 shows the
corresponding state machine.
In addition to Table 36-6 or Table 36-7, the following Table 36-10 shows RX_AACK configuration registers required to
setup a node to receive reserved frame types.
There are three different options for handling reserved frame types.
1. AACK_UPLD_RES_FT = 1, AACK_FLTR_RES_FT = 0:
Any non-corrupted frame with a reserved frame type is indicated by an IRQ_3 (TRX_END) interrupt. No further
address filtering is applied on those frames. An IRQ_5 (AMI) interrupt is never generated and the acknowledgment
subfield is ignored.
2. AACK_UPLD_RES_FT = 1, AACK_FLTR_RES_FT = 1:
If AACK_FLTR_RES_FT = 1 any frame with a reserved frame type is filtered by the address filter similar to a data
frame as described in the standard. This implies the generation of the IRQ_5 (AMI) interrupts upon address match.
An IRQ_3 (TRX_END) interrupt is only generated if the address matched and the frame was not corrupted. An
acknowledgment is only send, when the ACK request subfield was set in the received frame and an
IRQ_3 (TRX_END) interrupt occurred.
3. AACK_UPLD_RES_FT = 0:
Any received frame with a reserved frame type is discarded.
Short Acknowledgment Frame (ACK) Start Timing
Register bit AACK_ACK_TIME (register 0x17, XAH_CTRL_1), see Table 36-11 defines the delay between the end of the
frame reception and the start of the transmission of an acknowledgment frame.
Table 36-9. Configuration of a Sniffer Device
Register
Address
Register
Bits Register Name Description
0x17 1AACK_PROM_MODE 1: Enable promiscuous mode.
0x2E 4AACK_DIS_ACK 1: Disable generation of acknowledgment.
Table 36-10. RX_AACKK Configuration to Receive Reserved Frame Types
Register
Address
Register
Bits Register Name Description
0x17 4AACK_UPLD_RES_FT 1: Enable reserved frame type reception.
0x17 5AACK_FLTR_RES_FT
Filter reserved frame types like data frame type, see note below.
0: Disable reserved frame types filtering.
1: Enable reserved frame types filtering.
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This feature can be used in all scenarios, independent of other configurations. Shorter acknowledgment timing is
especially useful when using High Data Rate Modes to increase battery lifetime and to improve the overall data
throughput; refer to “High Data Rate Modes” on page 1013.
36.2.3.4 RX_AACK Slotted Operation – Slotted Acknowledgement
In networks using slotted operation the start of the acknowledgment frame, and thus the exact timing, must be provided
by the microcontroller. Exact timing requirements for the transmission of acknowledgments in beacon-enabled networks
are explained in IEEE 802.15.4-2006, Section 7.5.6.4.2. In conjunction with the microcontroller the Atmel AT86RF233
supports slotted acknowledgement operation. This mode is invoked by setting register bit SLOTTED_OPERATION
(register 0x2C, XAH_CTRL_0) to one.
If an acknowledgment (ACK) frame is to be transmitted in RX_AACK mode, the radio transceiver expects a rising edge
on SLP_TR to actually start the transmission. During this waiting period, the transceiver reports
SUCCESS_WAIT_FOR_ACK through register bits TRAC_STATUS (register 0x02, TRX_STATE), see Figure 36-10. The
minimum delay between the occurrence of interrupt IRQ_3 (TRX_END) and pin start of the ACK frame in slotted
operation is two symbol periods.
Figure 36-11 illustrates the timing of an RX_AACK transaction in slotted operation. The acknowledgement frame is ready
to transmit three symbol times after the reception of the last symbol of a data or MAC command frame indicated by
IRQ_3 (TRX_END). The transmission of the acknowledgement frame is initiated by the microcontroller with the rising
edge of SLP_TR and starts tTR10 = 16µs later. The interrupt latency tIRQ is specified in “Digital Interface Timing
Characteristics” on page 1101.
Figure 36-11.Timing Example of an RX_AACK Transaction for Slotted Operation
Table 36-11. Overview of RX_AACK Configuration Bits
Register
Address
Register
Bits Register Name Description
0x17 2AACK_ACK_TIME
0: IEEE 802.15.4 standard compliant acknowledgement timing of 12
symbol periods. In slotted acknowledgement operation mode, the
acknowledgment frame transmission can be triggered two symbol
periods after reception of the frame earliest.
1: Non-standard IEEE 802.15.4 reduced acknowledgment timing is set
to 32µs (two symbol periods).
RX/TX Frame
on Air
RX_AACK_ON
TRX_STATE
Frame Type
RX_AACK_ON
RX/TX RX TX
TRX_END
IRQ
RX
Typ. Processing Delay t
IRQ
5120 704 time [μs]
64 1026
Data Frame (Length = 10, ACK=1) ACK Frame
SFD
32 μs
(2 symbols)
SLP_TR
t
TR10
TX RX
SLP_TR
ACK transmission initated by microcontroller
BUSY_RX_AACK
RX
waiting period signalled by register bits TRAC_STATUS
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36.2.3.5 RX_AACK Mode Timing
A timing example of an RX_AACK transaction is shown in Figure 36-12. In this example a data frame of length 10 with an
ACK request is received. The AT86RF233 changes to state BUSY_RX_AACK after SFD detection. The completion of
the frame reception is indicated by an IRQ_3 (TRX_END) interrupt. The interrupts IRQ_2 (RX_START) and IRQ_5 (AMI)
are disabled in this example. The ACK frame is automatically transmitted after aTurnaroundTime (12 symbols),
assuming default acknowledgment frame start timing. The interrupt latency tIRQ is specified in “Digital Interface Timing
Characteristics” on page 1101.
Figure 36-12.Timing Example of an RX_AACK Transaction
Note: If register bit AACK_ACK_TIME (register 0x17, XAH_CTRL_1) is set, an acknowledgment frame is sent already two
symbol times after the reception of the last symbol of a data or MAC command frame.
RX/TX Frame
on Air
RX_AACK_ON BUSY_RX_AACK
TRX_STATE
Frame Type
RX_AACK_ON
RX/TX RX TX
TRX_END
IRQ
RX
Typ. Processing Delay tIRQ
5120704
time [µs]
64 1088
Data Frame (Length = 10, ACK=1) ACK Frame
SFD
192 µs
(12 symbols)
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36.2.4 TX_ARET_ON – Transmit with Automatic Frame Retransmission and CSMA-CA Retry
Figure 36-13.Flow Diagram of TX_ARET
TRX_STATE = TX_ARET_ON
csma_rctr = 0
TRX_STATE = TX_ARET_ON
N
Y
Failure
Success
N
Y
frame_rctr = 0
Transmit Frame
frame_rctr = frame_rctr + 1
Y
N
N
Y
TRAC_STATUS =
NO_ACK
TRAC_STATUS =
SUCCESS
TRAC_STATUS =
CHANNEL_ACCESS_FAILURE
Issue IRQ_3 (TRX_END) interrupt
CCA
Result
ACK requested
ACK valid
TRAC_STATUS =
SUCCESS_DATA_PENDING
Y
N
Receive ACK
until timeout
Y
N
TRX_STATE = BUSY_TX_ARET
TRAC_STATUS = INVALID
MAX_CSMA_RETRIES
<7
Y
N
csma_rctr >
MAX_CSMA_RETRIES
Y
Note 1: If MAX_CSMA_RETRIES = 7 no retry is
performed
(see Note 1)
Random Back-Off
csma_rctr = csma_rctr + 1
CCA
Start TX
frame_rctr >
MAX_FRAME_RETRIES
Data Pending
N
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36.2.4.1 Overview
The implementation of TX_ARET algorithm is shown in Figure 36-13.
The TX_ARET Extended Operating Mode supports the frame transmission process as defined by IEEE 802.15.4-2006. It
is invoked as described in “State Control” on page 916 by writing TX_ARET_ON to register subfield TRX_CMD
(register 0x02, TRX_STATE).
If a transmission is initiated in TX_ARET mode, the AT86RF233 executes the CSMA-CA algorithm as defined by
[2]IEEE 802.15.4-2006, Section 7.5.1.4. If the CCA reports IDLE, the frame is transmitted from the Frame Buffer.
If an acknowledgement frame is requested, the radio transceiver checks for an ACK reply automatically. The CSMA-CA
based transmission process is repeated until a valid acknowledgement is received or the number of frame
retransmissions MAX_FRAME_RETRIES (register 0x2C, XAH_CTRL_0) is exceeded.
The completion of the TX_ARET transaction is indicated by the IRQ_3 (TRX_END) interrupt, see “Interrupt Handling” on
page 931.
36.2.4.2 Description
Prior to invoking AT86RF233 TX_ARET mode, the basic configuration steps as described in “Configuration” on page 917
shall be executed. It is further recommended to write the PSDU transmit data to the Frame Buffer in advance.
The transmit start event may either come from a rising edge on SLP_TR, refer to “Sleep/Wake-up and Transmit Signal
(SLP_TR)” on page 894, or by writing a TX_START command to register bits TRX_CMD (register 0x02, TRX_STATE).
If the CSMA-CA detects a busy channel, it is retried as specified by the register bits MAX_CSMA_RETRIES
(register 0x2C, XAH_CTRL_0). In case that CSMA-CA does not detect a clear channel after MAX_CSMA_RETRIES, it
aborts the TX_ARET transaction, issues interrupt IRQ_3 (TRX_END), and sets the value of the register bits
TRAC_STATUS to CHANNEL_ACCESS_FAILURE.
During transmission of a frame the radio transceiver parses bit[5] (ACK Request) of the MAC header (MHR) frame
control field of the PSDU data (PSDU octet #1) to be transmitted to check if an ACK reply is expected.
If no ACK is expected, the radio transceiver issues IRQ_3 (TRX_END) directly after the frame transmission has been
completed. The register bits TRAC_STATUS (register 0x02, TRX_STATE) are set to SUCCESS.
If an ACK is expected, after transmission the radio transceiver automatically switches to receive mode waiting for a valid
ACK reply (that is matching sequence number and correct FCS). After receiving a valid ACK frame, the “Frame Pending”
subfield of this frame is parsed and the status register bits TRAC_STATUS are updated to SUCCESS or
SUCCESS_DATA_PENDING accordingly, refer to Table 36-12. At the same time, the entire TX_ARET transaction is
terminated and interrupt IRQ_3 (TRX_END) is issued.
If no valid ACK is received or after timeout of 54 symbol periods (864µs), the radio transceiver retries the entire
transaction (CSMA-CA based frame transmission) until the maximum number of frame retransmissions is exceeded, see
register bits MAX_FRAME_RETRIES (register 0x2C, XAH_CTRL_0). In that case, the TRAC_STATUS is set to
NO_ACK, the TX_ARET transaction is terminated, and interrupt IRQ_3 (TRX_END) is issued.
The current CSMA-CA and frame retransmission counter values of an ongoing TX_ARET transaction can be retrieved by
the register bits ARET_FRAME_RETRIES and ARET_CSMA_RETRIES (register 0x19, XAH_CTRL_2).
Note: 1. The acknowledgment receive procedure does not overwrite the Frame Buffer content. Transmit data in the Frame
Buffer is not modified during the entire TX_ARET transaction. Received frames, other than the expected ACK
frame, are discarded automatically.
Additionally to the RX Frame Time stamping via DIG2, a TX Frame Time stamping within TX_ARET mode can be
activated, if the register bits IRQ_2_EXT_EN (register 0x04, TRX_CTRL_1) and ARET_TX_TS_EN (register 0x17,
XAH_CTRL_1) are set to one, see “RX and TX Frame Time Stamping (TX_ARET)” on page 1027.
After that, the microcontroller may read the value of the register bits TRAC_STATUS (register 0x02, TRX_STATE) to
verify whether the transaction was successful or not. The register bits are set according to the following cases, additional
exit codes are described in “Register Summary” on page 932.
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Table 36-12 summarizes the Extended Operating Mode result codes in register subfield TRAC_STATUS (register 0x02,
TRX_STATE) with respect to the TX_ARET transaction. Values are meaningful after an interrupt until the next frame
transmit.
A value of MAX_CSMA_RETRIES = 7 initiates an immediate TX_ARET transaction without performing CSMA-CA. This
can be used for example to transmit indirect data to a device. Further the value MAX_FRAME_RETRIES is ignored and
the TX_ARET transaction is performed only once.
A timing example of a TX_ARET transaction is shown in Figure 36-14.
Figure 36-14.Timing Example of a TX_ARET Transaction
Notes: 1. tCSMA-CA defines the random CSMA-CA backoff time.
2. Timing figure tTR10 and tTR11 refer to Table 36-1 on page 910.
Here an example data frame of length 10 with an ACK request is transmitted. After that, the AT86RF233 switches to
receive mode and expects an acknowledgement response. During the whole transaction including frame transmit, wait
for ACK and ACK receive the radio transceiver status register bits TRX_STATUS (register 0x01, TRX_STATUS) signals
BUSY_TX_ARET.
A successful reception of the acknowledgment frame is indicated by triggering of IRQ_3 (TRX_END). The status register
bits TRX_STATUS (register 0x01, TRX_STATUS) changes back to TX_ARET_ON state. When the frame pending
subfield of the received ACK frame is set to one (more data is to follow) register bits TRAC_STATUS (register 0x02,
TRX_STATE) are set either to SUCCESS_DATA_PENDING status instead of SUCCESS status.
Table 36-12. Interpretation of TRAC_STATUS Register Bits
Value Name Description
0SUCCESS The transaction was responded to by a valid ACK, or, if no ACK is
requested, after a successful frame transmission.
1SUCCESS_DATA_PENDING
Equivalent to SUCCESS and indicating that the “Frame Pending” bit (see
“Frame Control Field (FCF)” on page 948) of the received
acknowledgment frame was set.
3CHANNEL_ACCESS_FAILURE Channel is still busy after attempting MAX_CSMA_RETRIES of
CSMA-CA.
5NO_ACK No acknowledgement frames were received during all retry attempts.
7INVALID Transaction not yet finished.
RX/TX Frame
on Air
TX_ARET_ON BUSY_TX_ARET
TRX_STATE
FrameType
TX_ARET_ON
RX/TX RX
TRX_END
IRQ
Typ. Processing Delay tTR10
6720x
time [µs]
128 x+352
SLP_TR
TX
tIRQ
Data Frame (Length = 10, ACK=1) ACK Frame
tCSMA-CA
TXCSMA-CA RX
tTR11
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36.2.5 Interrupt Handling
The AT86RF233 interrupt handling in the Extended Operating Mode is similar to the Basic Operating Mode, refer to
“Interrupt Handling” on page 906. Interrupts can be enabled by setting the appropriate bit in register 0x0E (IRQ_MASK).
For RX_AACK and TX_ARET modes the following interrupts inform about the status of a frame reception and
transmission:
36.2.5.1 RX_AACK
For support of the RX_AACK functionality, it is recommended to enable IRQ_3 (TRX_END). This interrupt is issued only
if frames pass the frame filtering, refer to “Frame Filter” on page 952, and have a valid FCS to reflect data validity. This
functionality differs in Basic Operating Mode, refer to “Interrupt Handling” on page 906. The usage of other interrupts is
optional.
On reception of a valid PHR an IRQ_2 (RX_START) is issued. IRQ_5 (AMI) indicates address match, refer to filter rules
in “Frame Filter” on page 952, and the completion of a frame reception with a valid FCS is indicated by interrupt
IRQ_3 (TRX_END).
Thus, it can happen that an IRQ_2 (RX_START) and/or IRQ_5 (AMI) are issued, but the IRQ_3 (TRX_END) interrupt is
never triggered when a frame does not pass the FCS computation check.
36.2.5.2 TX_ARET
The IRQ_3 (TRX_END) interrupt is always generated after completing an TX_ARET transaction. Subsequently the
transaction status can be read from register bits TRAC_STATUS (register 0x02, TRX_STATE).
Several interrupts are automatically suppressed by the radio transceiver during TX_ARET transaction. In contrast to
“Clear Channel Assessment (CCA)” on page 968, the CCA algorithm (part of CSMA-CA) does not generate interrupt
IRQ_4 (CCA_ED_DONE). Furthermore, the interrupts IRQ_2 (RX_START) and/or IRQ_5 (AMI) are not generated during
the TX_ARET acknowledgment receive process.
All other interrupts as described in “Interrupt Logic” on page 896, are also available in Extended Operating Mode.
Table 36-13. Interrupt Handling in Extended Operating Mode
Mode Interrupt Description
RX_AACK
IRQ_2 (RX_START) Indicates a PHR reception
IRQ_5 (AMI) Issued at address match
IRQ_3 (TRX_END)
Signals completion of RX_AACK transaction if successful
A received frame must pass the address filter
The FCS is valid
TX_ARET IRQ_3 (TRX_END) Signals completion of TX_ARET transaction
RX_AACK / TX_ARET IRQ_0 (PLL_LOCK)
Entering RX_AACK_ON or TX_ARET_ON state from TRX_OFF
state, the PLL_LOCK interrupt signals that the transaction can be
started
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36.2.6 Register Summary
The following AT86RF233 registers are to be configured to control the Extended Operating Mode:
Table 36-14. Register Summary
Reg. Addr. Register Name Description
0x01 TRX_STATUS Radio transceiver status, CCA result
0x02 TRX_STATE Radio transceiver state control, TX_ARET status
0x04 TRX_CTRL_1 TX_AUTO_CRC_ON
0x08 PHY_CC_CCA CCA mode control, see “Register Description” on page 970
0x09 CCA_THRES CCA ED threshold settings, see “Register Description” on page 970
0x17 XAH_CTRL_1 TX_ARET and RX_AACK control
0x19 XAH_CTRL_2 TX_ARET control
0x20 – 0x2B
Frame Filter configuration
Short address, PAN ID, and IEEE address
See “Register Description” on page 954 and “Register Description – Address
Registers” on page 957
0x2C XAH_CTRL_0 TX_ARET control, retries value control
0x2D CSMA_SEED_0 CSMA-CA seed value
0x2E CSMA_SEED_1 CSMA-CA seed value, RX_AACK control
0x2F CSMA_BE CSMA-CA backoff exponent control
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36.2.7 Register Description
36.2.7.1 TRX_STATUS
Name: TRX_STATUS
Offset: 0x01
Reset: 0x00, 0x08
Property: -
The read-only register TRX_STATUS signals the present state of the radio transceiver as well as the status of a CCA
operation.
zBit 4:0 - TRX_STATUS
The register bits TRX_STATUS signal the current radio transceiver status.
Notes: 1. In SLEEP or DEEP_SLEEP state register not accessible.
2. Extended Operating Mode only.
3. Do not try to initiate a further state change while the radio transceiver is in
STATE_TRANSITION_IN_PROGRESS state.
Bit 76543210
0x01 CCA_DONE CCA_STATUS TRX_STATUS
Access R R R R R R R R
Reset00000000
Table 36-15. TRX_STATUS
Value Description
0x00 P_ON
0x01 BUSY_RX
0x02 BUSY_TX
0x06 RX_ON
0x08 TRX_OFF (CLK Mode)
0x09 PLL_ON (TX_ON)
0x0F(1) SLEEP
0x10 PREP_DEEP_SLEEP
0x11(2) BUSY_RX_AACK
0x12(2) BUSY_TX_ARET
0x16(2) RX_AACK_ON
0x19(2) TX_ARET_ON
0x1F(3) STATE_TRANSITION_IN_PROGRESS
All other values are reserved
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A read access to TRX_STATUS register signals the current radio transceiver state status. A state change is initiated by
writing a state transition command to register bits TRX_CMD (register 0x02, TRX_STATE). Alternatively, some state
transitions can be initiated by the rising edge of SLP_TR in the appropriate state.
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36.2.7.2 TRX_STATE
Name: TRX_STATE
Offset: 0x02
Reset: 0x00
Property: -
The radio transceiver states are advanced via register TRX_STATE by writing a command word into register bits
TRX_CMD. The read-only register bits TRAC_STATUS indicate the status or result of an Extended Operating Mode
transaction.
zBit 7:5 – TRAC_STATUS
Note: 1. Even though the reset value for register bits TRAC_STATUS is zero, the RX_AACK and TX_ARET proce-
dures set the register bits to TRAC_STATUS = 7 (INVALID) when they are started.
The status of the RX_AACK and TX_ARET procedure is indicated by register bits TRAC_STATUS. Values are
meaningful after an interrupt until the next frame transmit. Details of the algorithm and a description of the status
information are given in “RX_AACK_ON – Receive with Automatic ACK” on page 918 and “TX_ARET_ON –
Transmit with Automatic Frame Retransmission and CSMA-CA Retry” on page 928.
RX_AACK
SUCCESS_WAIT_FOR_ACK:
Indicates an ACK frame is about to be sent in RX_AACK slotted acknowledgement. Slotted acknowledgement
operation must be enabled with register bit SLOTTED_OPERATION (register 0x2C, XAH_XTRL_0). The micro-
controller must pulse SLP_TR at the next backoff slot boundary in order to initiate a transmission of the ACK
frame. For details refer to [2] IEEE 802.15.4-2006, Section 7.5.6.4.2.
TX_ARET
SUCCESS_DATA_PENDING:
Indicates a successful reception of an ACK frame with frame pending bit set to one.
Bit 76543210
0x02 TRAC_STATUS TRX_CMD
Access R R R R/W R/W R/W R/W R/W
Reset 00000000
Table 36-16. TRAC_STATUS
Value Description RX_AACK TX_ARET
0x0(1) SUCCESS X X
0x1 SUCCESS_DATA_PENDING X
0x2 SUCCESS_WAIT_FOR_ACK X
0x3 CHANNEL_ACCESS_FAILURE X
0x5 NO_ACK X
0x7(1) INVALID X X
All other values are reserved
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zBit 4:0 - TRX_CMD
A write access to register bits TRX_CMD initiate a radio transceiver state transition to the new state
Notes: 1. TRX_CMD = “0” after power on reset (POR).
2. The frame transmission starts one symbol after TX_START command.
3. FORCE_PLL_ON is not valid for states P_ON, SLEEP, DEEP_SLEEP, and RESET, as well as
STATE_TRANSITION_IN_PROGRESS towards these states.
4. Extended Operating Mode only.
A successful state transition shall be confirmed by reading register bits TRX_STATUS (register 0x01, TRX_STATUS).
The register bits TRX_CMD are used for Basic and Extended Operating Modes, refer to “Basic Operating Mode” on page
902.
Table 36-17. TRX_CMD
Value Description
0x00(1) NOP
0x02(2) TX_START
0x03 FORCE_TRX_OFF
0x04(3) FORCE_PLL_ON
0x06 RX_ON
0x08 TRX_OFF (CLK Mode)
0x09 PLL_ON (TX_ON)
0x10 PREP_DEEP_SLEEP
0x16(4) RX_AACK_ON
0x19(4) TX_ARET_ON
All other values are reserved
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36.2.7.3 TRX_CTRL_1
Name: TRX_CTRL_1
Offset: 0x04
Reset: 0x22
Property: -
The TRX_CTRL_1 register is a multi-purpose register to control various operating modes and settings of the radio
transceiver.
zBit 5 - TX_AUTO_CRC_ON
The register bit TX_AUTO_CRC_ON controls the automatic FCS generation for transmit operations.
.
For further details refer to “Frame Check Sequence (FCS)” on page 961.
Bit 76543210
0x04 PA_EXT_EN IRQ_2_EXT_
EN
TX_AUTO_
CRC_ON
RX_BL_
CTRL SPI_CMD_MODE IRQ_MASK_
MODE
IRQ_
POLARITY
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00100010
Table 36-18. TX_AUTO_CRC_ON
Value Description
0x0 Automatic FCS generation is disabled
0x1 Automatic FCS generation is enabled
Note: 1. The TX_AUTO_CRC_ON function can be used within Basic and Extended Operating Modes.
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36.2.7.4 XAH_CTRL_1
Name: XAH_CTRL_1
Offset: 0x17
Reset: 0x00
Property: -
The XAH_CTRL_1 register is a multi-purpose controls register for Extended Operating Mode.
zBit 7 - ARET_TX_TS_EN
If register bit ARET_TX_TS_EN = 1, then any frame transmission within TX_ARET mode is signaled via DIG2.
zBit 5 - AACK_FLTR_RES_FT
Filter reserved frame types like data frame type. The register bit AACK_FLTR_RES_FT shall only be set if register
bit AACK_UPLD_RES_FT = 1.
Notes: 1. If AACK_FLTR_RES_FT = 0 the received reserved frame is only checked for a valid FCS.
2. If AACK_FLTR_RES_FT = 1 reserved frame types are filtered similar to data frames as specified in IEEE
802.15.4–2006.
Reserved frame types are explained in IEEE 802.15.4 Section 7.2.1.1.1.
zBit 4 - AACK_UPLD_RES_FT
Upload reserved frame types within RX_AACK mode.
.
Bit 76543210
0x17 ARET_TX_T
S_EN
AACK_
FLTR_
RES_FT
AACK_
UPLD_RES_
FT
AACK_
ACK_TIME
AACK_
PROM_
MODE
AACK_
SPC_EN
Access R/WR/WR/WR/W R R/WR/WR/W
Reset00000000
Table 36-19. ARET_TX_TS_EN
Value Description
0x0 TX_ARET time stamping via DIG2 is disabled
0x1(1) TX_ARET time stamping via DIG2 is enabled
Note: 1. It is necessary to set register bit IRQ_2_EXT_EN (register 0x04, TRX_CTRL_1).
Table 36-20. AACK_FLTR_RES_FT
Value Description
0x0(1) Filtering reserved frame types is disabled
0x1(2) Filtering reserved frame types is enabled
Table 36-21. AACK_UPLD_RES_FT
Value Description
0x0 Upload of reserved frame types is disabled
0x1(1) Upload of reserved frame types is enabled
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Note: 1. If AACK_UPLD_RES_FT = 1 received frames indicated as a reserved frame are further processed. For
those frames, an IRQ_3 (TRX_END) interrupt is generated if the FCS is valid.
In conjunction with the configuration bit AACK_FLTR_RES_FT, these frames are handled like IEEE 802.15.4 com-
pliant data frames during RX_AACK transaction. An IRQ_5 (AMI) interrupt is issued, if the addresses in the
received frame match the node’s addresses.
That means, if a reserved frame passes the third level filter rules, an acknowledgement frame is generated and
transmitted if it was requested by the received frame. If this is not wanted register bit AACK_DIS_ACK
(register 0x2E, CSMA_SEED_1) has to be set.
zBit 2 - AACK_ACK_TIME
The register bit AACK_ACK_TIME controls the acknowledgment frame response time within RX_AACK mode.
According to [2] IEEE 802.15.4-2006, Section 7.5.6.4.2 the transmission of an acknowledgment frame shall com-
mence 12 symbol periods (aTurnaroundTime) after the reception of the last symbol of a data or MAC command
frame. This is achieved with the reset value of the register bit AACK_ACK_TIME.
Alternatively, if AACK_ACK_TIME = 1 an acknowledgment frame is sent already two symbol periods after the
reception of the last symbol of a data or MAC command frame. This may be applied to proprietary networks or net-
works using the High Data Rate Modes to increase battery lifetime and to improve the overall data throughput,
refer to “High Data Rate Modes” on page 1013.
zBit 1 - AACK_PROM_MODE
The register bit AACK_PROM_MODE enables the promiscuous mode, within the RX_AACK mode.
.
Refer to [2] IEEE 802.15.4-2006 Section 7.5.6.5.
If this register bit is set, every incoming frame with a valid PHR finishes with IRQ_3 (TRX_END) interrupt even if
the third level filter rules do not match or the FCS is not valid. However, register bit RX_CRC_VALID
(register 0x06, PHY_RSSI) is set accordingly.
In contrast to [2] IEEE 802.15.4-2006, if a frame passes the third level filter rules, an acknowledgement frame is
generated and transmitted unless disabled by register bit AACK_DIS_ACK (register 0x2E, CSMA_SEED_1), or
use Basic Operating Mode instead.
Table 36-22. AACK_ACK_TIME
Value Description
0x0 Acknowledgment time is 12 symbol periods (a Turnaround Time)
0x1 Acknowledgment time is two symbol periods
Table 36-23. AACK_PROM_MODE
Value Description
0x0 Promiscuous mode is disabled
0x1 Promiscuous mode is enabled
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36.2.7.5 XAH_CTRL_2
Name: XAH_CTRL_2
Offset: 0x19
Reset: 0x00
Property: -
The read-only register XAH_CTRL_2 retrieves the current counter values for Extended Operating Mode.
zBit 7:4 - ARET_FRAME_RETRIES
Retrieves current frame retry counter value.
Note: 1. A new CCA_BACKOFF cycle or new frame transmit cycle changed these value.
zBit 3:1 - ARET_CSMA_RETRIES
Retrieves current CSMA-CA retry counter value.
.
Note: 1. A new CCA_BACKOFF cycle or new frame transmit cycle changed these value.
Bit 76543210
0x19 ARET_FRAME_RETRIES ARET_CSMA_RETRIES
AccessRRRRRRRR
Reset 00000000
Table 36-24. ARET_FRAME_RETRIES
Value Description
0x0 Minimum possible frame retry counter value
0xF Maximum possible frame retry counter value
Table 36-25. ARET_CSMA_RETRIES
Value Description
0x0 Minimum possible CSMA-CA retry counter value
0x5 Maximum possible CSMA-CA retry counter value
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36.2.7.6 XAH_CTRL_0
Name: XAH_CTRL_0
Offset: 0x2C
Reset: 0x38
Property: -
The XAH_CTRL_0 register is a control register for Extended Operating Mode.
zBit 7:4 - MAX_FRAME_RETRIES
Number of retransmission attempts in TX_ARET mode before the transaction gets cancelled.
.
zBit 3:1 - MAX_CSMA_RETRIES
Number of retries in TX_ARET mode to repeat the CSMA-CA procedure before the transaction gets cancelled.
.
Notes: 1. MAX_CSMA_RETRIES specifies the number of retries in TX_ARET mode to repeat the CSMA-CA proce-
dure before the transaction gets cancelled. According to IEEE 802.15.4 the valid range of
MAX_CSMA_RETRIES is [5, 4, …, 0].
2. A value of MAX_CSMA_RETRIES = 7 initiates an immediate frame transmission without performing CSMA-
CA. No retry is performed. This may especially be required for slotted acknowledgement operation.
zBit 0 - SLOTTED_OPERATION
For RX_AACK mode, the register bit SLOTTED_OPERATION determines, if the transceiver will require a time
base for slotted operation.
Bit 7654321 0
0x2C MAX_FRAME_RETRIES MAX_CSMA_RETRIES SLOTTED_OPERATION
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0011100 0
Table 36-26. MAX_FRAME_RETRIES
Value Description
0x3
The setting of MAX_FRAME_RETRIES in TX_ARET mode specifies the number of attempts to retransmit a
frame, when it was not acknowledged by the recipient, before the transaction gets cancelled.
Valid values are [0x7, 0x6, …, 0x0].
Table 36-27. MAX_CSMA_RETRIES
Value Description
0x0(1) No retries
0x1(1) One retry
0x2(1) Two retries
0x3(1) Three retries
0x4(1) Four retries
0x5(1) Five retries
0x6 Reserved
0x7(2) Immediate frame transmission without performing CSMA-CA
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.
Using RX_AACK mode in networks operating in beacon or slotted mode, refer to [2] IEEE 802.15.4-2006,
Section 5.5.1, register bit SLOTTED_OPERATION indicates that acknowledgement frames are to be sent on
backoff slot boundaries (slotted acknowledgement), refer to “RX_AACK Slotted Operation – Slotted Acknowledge-
ment” on page 926.
If this register bit is set the acknowledgement frame transmission has to be initiated by the microcontroller using
the rising edge of SLP_TR. This waiting state is signaled in register bits TRAC_STATUS (register 0x02,
TRX_STATE) with value SUCCESS_WAIT_FOR_ACK.
Table 36-28. SLOTTED_OPERATION
Value Description
0x0 The radio transceiver operates in unslotted mode. An acknowledgment frame is automatically sent if requested.
0x1 The transmission of an acknowledgement frame has to be controlled by the microcontroller.
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36.2.7.7 CSMA_SEED_0
Name: CSMA_SEED_0
Offset: 0x2D
Reset: 0xEA
Property: -
The register CSMA_SEED_0 contains the lower 8-bit of CSMA_SEED.
zBit 7:0 - CSMA_SEED_0
Lower 8-bit of CSMA_SEED, bits [7:0]. Used as seed for random number generation in the CSMA-CA algorithm.
.
Notes: 1. It is recommended to initialize register bits CSMA_SEED_0 and CSMA_SEED_1 with random values. This
can be done using register bits RND_VALUE (register 0x06, PHY_RSSI), refer to “Random Number Gener-
ator” on page 1013.
2. The content of register bits CSMA_SEED_0 and CSMA_SEED_1 initializes the TX_ARET random backoff
generator after wakeup from DEEP_SLEEP state. It is recommended to re-initialize both registers after
every DEEP_SLEEP state with a random value.
Bit 76543210
0x2D CSMA_SEED_0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 11101010
Table 36-29. CSMA_SEED_0
Value Description
0xEA
This register contains the lower 8-bit of the CSMA_SEED, bits [7:0]. The higher 3-bit are part of register bits
CSMA_SEED_1 (register 0x2E, CSMA_SEED_1).
CSMA_SEED is the seed for the random number generation that determines the length of the backoff period in
the CSMA-CA algorithm.
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36.2.7.8 CSMA_SEED_1
Name: CSMA_SEED_1
Offset: 0x2E
Reset: 0x42
Property: -
The CSMA_SEED_1 register is a control register for RX_AACK and contains a part of the CSMA_SEED for the CSMA-
CA algorithm.
zBit 7:6 - AACK_FVN_MODE
The register bits AACK_FVN_MODE control the ACK behavior dependent on FCF frame version number within
RX_AACK mode.
Note: 1. AACK_FVN_MODE value one indicates frames according to [2] IEEE 802.15.4–2006, a value of three indi-
cates frames according to [1] IEEE 802.15.4–2003 standard.
The frame control field of the MAC header (MHR) contains a frame version subfield. The setting of register bits
AACK_FVN_MODE specifies the frame filtering behavior of the Atmel AT86RF233. According to the content of
these register bits the radio transceiver passes frames with a specific frame version number, number group, or
independent of the frame version number.
Thus the register bits AACK_FVN_MODE defines the maximum acceptable frame version. Received frames with a
higher frame version number than configured do not pass the frame filter and are not acknowledged.
The frame version field of the acknowledgment frame is set to zero according to [2] IEEE 802.15.4-2006,
Section 7.2.2.3.1 Acknowledgment frame MHR fields.
zBit 5 - AACK_SET_PD
The content of AACK_SET_PD bit is copied into the frame pending subfield of the acknowledgment frame if the
ACK is the response to a data request MAC command frame.
.
Bit 7 6 5 4 3 2 1 0
0x2E AACK_FVN_MODE AACK_SET_
PD
AACK_DIS_
ACK
AACK_I_AM_
COORD CSMA_SEED_1
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 01 0 0 0 0 1 0
Table 36-30. AACK_FVN_MODE
Value Description
0x0 Accept frames with version number 0
0x1 Accept frames with version number 0 or 1
0x2 Accept frames with version number 0 or 1 or 2
0x3 Accept frames independent of frame version number
Table 36-31. AACK_SET_PD
Value Description
0x0 Pending data bit set to zero
0x1 Pending data bit set to one
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In addition, if register bits AACK_FVN_MODE (register 0x2E, CSMA_SEED_1) are configured to accept frames
with a frame version other than zero or one, the content of register bit AACK_SET_PD is also copied into the frame
pending subfield of the acknowledgment frame for any MAC command frame with a frame version of two or three
that have the security enabled subfield set to one. This is done with the assumption that a future version of the [2]
IEEE 802.15.4-2006 standard might change the length or structure of the auxiliary security header.
zBit 4 - AACK_DIS_ACK
If this bit is set no acknowledgment frames are transmitted in RX_AACK Extended Operating Mode, even if
requested.
.
zBit 3 - AACK_I_AM_COORD
This register bit has to be set if the node is a PAN coordinator. It is used for frame filtering in RX_AACK.
.
If AACK_I_AM_COORD = 1 and if only source addressing fields are included in a data or MAC command frame,
the frame shall be accepted only if the device is the PAN coordinator and the source PAN identifier matches mac-
PANId, for details refer to [2] IEEE 802.15.4-2006, Section 7.5.6.2 (third-level filter rule six).
zBit 2:0 - CSMA_SEED_1
Higher 3-bit of CSMA_SEED, bits [10:8]. Seed for random number generation in the CSMA-CA algorithm.
.
Table 36-32. AACK_DIS_ACK
Value Description
0x0 Acknowledgment frames are transmitted
0x1 Acknowledgment frames are not transmitted
Table 36-33. AACK_I_AM_COORD
Value Description
0x0 PAN coordinator addressing is disabled
0x1 PAN coordinator addressing is enabled
Table 36-34. CSMA_SEED_1
Value Description
0x2 These register bits are the higher 3-bit of the CSMA_SEED, bits [10:8]. The lower part is in register 0x2D
(CSMA_SEED_0), see register CSMA_SEED_0 for details.
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36.2.7.9 CSMA_BE
Name: CSMA_BE
Offset: 0x2F
Reset: 0x53
Property: -
The register CSMA_BE contains the backoff exponents for the CSMA-CA algorithm.
Note: 1. If MIN_BE = 0 and MAX_BE = 0 the CCA backoff period is always set to zero.
zBits 7:4 - MAX_BE
Maximum backoff exponent in the CSMA-CA algorithm.
For details refer to [2] IEEE 802.15.4-2006, Section 7.5.1.4.
zBits 3:0 - MIN_BE
Minimum backoff exponent in the CSMA-CA algorithm.
.
For details refer to [2] IEEE 802.15.4-2006, Section 7.5.1.4.
Bit 76543210
0x2F MAX_BE[3:0] MIN_BE[3:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 01010011
Table 36-35. MAX_BE
Value Description
0x5
Register bits MAX_BE defines the maximum backoff exponent used in the CSMA-CA algorithm to generate a
pseudo random number for CCA backoff.
Valid values are [0x8, 0x7, …, 0x0].
Table 36-36. MIN_BE
Value Description
0x3
Register bits MIN_BE defines the minimum backoff exponent used in the CSMA-CA algorithm to generate a
pseudo random number for CCA backoff.
Valid values are [MAX_BE, (MAX_BE – 1), …, 0x0].
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37. AT86RF233 Functional Description
37.1 Introduction – IEEE 802.15.4-2006 Frame Format
Figure 37-1 provides an overview of the physical layer (PHY) frame structure as defined by the IEEE 802.15.4-2006
standard.Figure 37-2 shows the medium access control layer (MAC) frame structure.
Figure 37-1. IEEE 802.15.4 Frame Format - PHY Layer Frame Structure (PPDU)
37.1.1 PHY Protocol Data Unit (PPDU)
37.1.1.1 Synchronization Header (SHR)
The SHR consists of a four-octet preamble field (all zero), followed by a single byte start-of-frame delimiter (SFD) which
has the predefined value 0xA7. During transmission, the SHR is automatically generated by the AT86RF233, thus the
Frame Buffer shall contain PHR and PSDU only, see “Frame Buffer Access Mode” on page 886.
The transmission of the SHR requires 160µs (10 symbols). As the SPI data rate is normally higher than the over-air data
rate, this allows the microcontroller to initiate a transmission without having transferred the full frame data already.
Instead it is possible to subsequently write the frame content.
The fact that the SPI data rate is normally higher than over-the-air data rate, allows the microcontroller to first initiate a
frame transmission and then as the SHR is transmitted write the frame data. This is to minimize frame buffer data fill
overhead transmission delay.
During a frame reception, the SHR is used for synchronization purposes. The matching SFD determines the beginning of
the PHR and the following PSDU payload data.
37.1.1.2 PHY Header (PHR)
The PHY header is a single octet following the SHR. The least significant seven bits denote the frame length of the
following PSDU, while the most significant bit of that octet is reserved, and shall be set to zero for IEEE 802.15.4
compliant frames.
On reception, the PHR is returned as the first octet during Frame Buffer read access. While the IEEE 802.15.4-2006
standard declares bit seven of the PHR octet as being reserved, the AT86RF233 preserves this bit upon transmission
and reception so it can be used to carry additional information within proprietary networks. Nevertheless, this bit is not
considered to be a part of the frame length, so only frames between one and 127 octets are possible. For IEEE 802.15.4
compliant operation bit [7] has to be masked by software.
In transmit mode, the PHR needs to be supplied as the first octet during Frame Buffer write access, see “Frame Buffer
Access Mode” on page 886.
In receive mode, the PHR (that is frame length greater than zero) is returned as the first octet during Frame Buffer read
access (see “Frame Buffer Access Mode” on page 886) and is signaled by an interrupt IRQ_2 (RX_START).
37.1.1.3 PHY Payload (PHY Service Data Unit, PSDU)
The PSDU has a variable length between zero and aMaxPHYPacketSize (127, maximum PSDU size in octets). The
length of the PSDU is signaled by the frame length field (PHR), refer to Table 37-1. The PSDU contains the MAC
protocol data unit (MPDU), where the last two octets are used for the Frame Check Sequence (FCS), see “Frame Check
Sequence (FCS)” on page 961.
Received frames with a frame length field set to zero (invalid PHR) are not signaled to the microcontroller.
Maximum 127 octets
PHY Service Data Unit (PSDU)
1 octet
(PHR)
5 octets
Synchronization Header (SHR)
PHY Protocol Data Unit (PPDU)
Preamble Sequence SFD Frame Length PHY Payload
MAC Protocol Data Unit (MPDU)
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Table 37-1 summarizes the type of payload versus the frame length value.
37.1.1.4 Timing Summary
Table 37-2 shows timing information for the above mentioned frame structure depending on the selected data rate.
37.1.2 MAC Protocol Data Unit (MPDU)
Figure 37-2 shows the frame structure of the MAC layer.
Figure 37-2. IEEE 802.15.4-2006 Frame Format - MAC Layer Frame Structure (MPDU)
37.1.2.1 MAC Header (MHR) Fields
The MAC header consists of the Frame Control Field (FCF), a sequence number, and the addressing fields (which are of
variable length, and can even be empty in certain situations).
37.1.2.2 Frame Control Field (FCF)
The FCF consists of 16 bits, and occupies the first two octets of the MPDU or PSDU, respectively.
Table 37-1. Frame Length - PHR
Frame Length Value Payload
0 - 4 Reserved
5MPDU (Acknowledgement)
6 – 8 Reserved
9 - aMaxPHYPacketSize MPDU
Table 37-2. PPDU Timing
PHY Mode
PSDU
Bit Rate [kb/s]
Header
Bit Rate [kb/s]
Duration
SHR [µs] PHR [µs] Max. PSDU [ms]
O-QPSK (1) 250 250 160 32 4.064
O-QPSK(2)
500 250 160 32 2.032
1000 250 160 32 1.016
2000 250 160 32 0.508
Notes: 1. Compliant to IEEE 802.15.4-2006 [2]
2. “High Data Rate Modes” on page 1013.
Frame Control Field 2 octets
Frame
Pending Reserved Frame Version
ACK
Request
PAN ID
Comp.
Destination
addressing mode
Source
addressing mode
Sec.
Enabled
(MFR)MAC Service Data Unit (MSDU)
MAC Protocol Data Unit (MPDU)
MAC Payload FCS
Frame Type
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MAC Header (MHR)
FCF Addressing Fields
Sequence
Number
2 octets
CRC-16
0/5/6/10/14 octets
Auxiliary Security Header
0/4/6/8/10/12/14/16/18/20 octets
Destination
PAN ID
Destination
address
Source
PAN ID
Source
address
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Figure 37-3. IEEE 802.15.4-2006 Frame Control Field (FCF)
Bits [2:0]: describes the “Frame Type“. Table 37-3 summarizes frame types defined by IEEE 802.15.4-2006 [2],
Section 7.2.1.1.1.
This subfield is used for frame filtering by the third level filter rules. By default, only frame types 0 – 3 pass the third level
filter rules, refer to “Frame Filter” on page 952. Automatic frame filtering by the Atmel AT86RF233 is enabled when using
the RX_AACK mode, refer to “RX_AACK_ON – Receive with Automatic ACK” on page 918.
However, a reserved frame (frame type value > 3) can be received if register bit AACK_UPLD_RES_FT (register 0x17,
XAH_CTRL_1) is set, for details refer to “Configuration of non IEEE 802.15.4 Compliant Scenarios” on page 924.
Frame filtering is also provided in Basic Operating Mode, refer to “Basic Operating Mode” on page 902.
Bit 3: indicates whether security processing applies to this frame. This field is evaluated by the Frame Filter.
Bit 4: is the “Frame Pending” subfield. This field can be set in an acknowledgment frame (ACK) in response to a data
request MAC command frame. This bit indicates that the node, which transmitted the ACK, might have more data to send
to the node receiving the ACK.
Note: 1. For acknowledgment frames automatically generated by the AT86RF233, this bit is set according to the con-
tent of register bit AACK_SET_PD in register 0x2E (CSMA_SEED_1) if the received frame was a data
request MAC command frame.
Bit 5: forms the “Acknowledgment Request” subfield. If this bit is set within a data or MAC command frame that is not
broadcast, the recipient shall acknowledge the reception of the frame within the time specified by IEEE 802.15.4 (that is
within 192µs for non beacon-enabled networks).
The radio transceiver parses this bit during RX_AACK mode and transmits an acknowledgment frame if necessary.
In TX_ARET mode this bit indicates if an acknowledgement frame is expected after transmitting a frame. If this is the
case, the receiver waits for the acknowledgment frame, otherwise the TX_ARET transaction is finished.
Bit 6: the “PAN ID Compression” subfield, indicates that in a frame where both the destination and source addresses are
present, the PAN ID is omitted from the source addressing field. This bit is evaluated by the Frame Filter of the
AT86RF233. This subfield was previously named “Intra-PAN”.
Bits [11:10]: the “Destination Addressing Mode” subfield describes the format of the destination address of the frame.
The values of the address modes are summarized in Table 37-4, according to IEEE 802.15.4.
Table 37-3. Frame Control Field - Frame Type Subfield
Frame Control Field Bit Assignment Description
Frame Type Value
b2, b1, b0
Value
000 0Beacon
001 1Data
010 2Acknowledge
011 3MAC command
100 – 111 4 – 7 Reserved
Frame Control Field 2 octets
Frame
Pending Reserved Frame Version
ACK
Request
PAN ID
Comp.
Destination
addressing mode
Source
addressing mode
Sec.
Enabled
Frame Type
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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If the destination address mode is either two or three (that is if the destination address is present), it always consists of a
16-bit PAN-ID first, followed by either the 16-bit or 64-bit address as described by the mode.
Bits [13:12]: the “Frame Version” subfield specifies the version number corresponding to the frame, see Table 37-5.
These bits are reserved in IEEE 802.15.4-2003.
This subfield shall be set to zero to indicate a frame compatible with IEEE 802.15.4-2003 and one to indicate an
IEEE 802.15.4-2006 frame. All other subfield values shall be reserved for future use.
RX_AACK register bits AACK_FVN_MODE (register 0x2E, CSMA_SEED_1) controls the behavior of frame
acknowledgements. This register determines if, depending on the Frame Version Number, a frame is acknowledged or
not. This is necessary for backward compatibility to IEEE 802.15.4-2003 and for future use. Even if frame version
numbers two and three are reserved, it can be handled by the radio transceiver, for details refer to “Register Description”
on page 933.
See [2] IEEE 802.15.4-2006, Section 7.2.3, for details on frame compatibility.
Bits [15:14]: the “Source Addressing Mode” subfield, with similar meaning as “Destination Addressing Mode”, see Table
37-4.
The addressing field description bits of the FCF (Bits 0–2, 3, 6, 10–15) affect the AT86RF233 Frame Filter, see “Frame
Filter” on page 952.
37.1.2.3 Frame Compatibility between IEEE 802.15.4-2003 and IEEE 802.15.4-2006
All unsecured frames according to IEEE 802.15.4-2006 are compatible with unsecured frames compliant with
IEEE 802.15.4-2003 with two exceptions: a coordinator realignment command frame with the “Channel Page” field
present (see [2] IEEE 802.15.4-2006, Section 7.3.8) and any frame with a MAC Payload field larger than
aMaxMACSafePayloadSize octets.
Table 37-4. Frame Control Field - Destination and Source Addressing Mode
Frame Control Field Bit Assignments Description
Addressing Mode
b11 b10
b15 b14
Value
00 0PAN identifier and address fields are not present
01 1Reserved
10 2Address field contains a 16-bit short address
11 3Address field contains a 64-bit extended address
Table 37-5. Frame Control Field - Frame Version Subfield
Frame Control Field Bit Assignment Description
Frame Version
b13 b12
Value
00 0Frames are compatible with IEEE 802.15.4-2003
01 1Frames are compatible with IEEE 802.15.4-2006
10 2Reserved
11 3Reserved
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Compatibility for secured frames is shown in Table 37-6, which identifies the security operating modes for
IEEE 802.15.4-2003 and IEEE 802.15.4-2006.
37.1.2.4 Sequence Number
The one-octet sequence number following the FCF identifies a particular frame, so that duplicated frame transmissions
can be detected. While operating in RX_AACK mode, the content of this field is copied from the frame to be
acknowledged into the acknowledgment frame.
37.1.2.5 Addressing Fields
The addressing fields of the MPDU are used by the AT86RF233 for address matching indication. The destination
address (if present) is always first, followed by the source address (if present). Each address field consists of the PAN-ID
and a device address. If both addresses are present, and the “PAN ID compression” subfield in the FCF is set to one, the
source PAN-ID is omitted.
Note that in addition to these general rules, IEEE 802.15.4 further restricts the valid address combinations for the
individual possible MAC frame types. For example, the situation where both addresses are omitted (source addressing
mode = 0 and destination addressing mode = 0) is only allowed for acknowledgment frames. The address filter in the
AT86RF233 has been designed to apply to IEEE 802.15.4 compliant frames. It can be configured to handle other frame
formats and exceptions.
37.1.2.6 Auxiliary Security Header Field
The Auxiliary Security Header specifies information required for security processing and has a variable length. This field
determines how the frame is actually protected (security level) and which keying material from the MAC security PIB is
used (see [2] IEEE 802.15.4-2006, Section 7.6.1). This field shall be present only if the Security Enabled subfield b3, see
“Frame Compatibility between IEEE 802.15.4-2003 and IEEE 802.15.4-2006” on page 950, is set to one. For details of its
structure, see IEEE 802.15.4-2006, Section 7.6.2 Auxiliary security header.
37.1.2.7 MAC Service Data Unit (MSDU)
This is the actual MAC payload. It is usually structured according to the individual frame type. A description can be found
in IEEE 802.15.4-2006, Section 5.5.3.2.
37.1.2.8 MAC Footer (MFR) Fields
The MAC footer consists of a two octet Frame Checksum (FCS), for details refer to “Frame Check Sequence (FCS)” on
page 961.
Table 37-6. Frame Control Field- Security and Frame Version
Frame Control Field Bit Assignment Description
Security Enabled
b3
Frame Version
b13 b12
000 No security. Frames are compatible between IEEE 802.15.4-2003 and
IEEE 802.15.4-2006.
001 No security. Frames are not compatible between IEEE 802.15.4-2003 and
IEEE 802.15.4-2006.
100 Secured frame formatted according to IEEE 802.15.4-2003. This frame type
is not supported in IEEE 802.15.4-2006.
101 Secured frame formatted according to IEEE 802.15.4-2006.
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37.2 Frame Filter
Frame Filtering is a procedure that evaluates whether or not a received frame matches predefined criteria, like source or
destination address or frame types. A filtering procedure as described in IEEE 802.15.4-2006 Section 7.5.6.2 (Third level
of filtering) is applied to the frame to accept a received frame and to generate the address match interrupt IRQ_5 (AMI).
The AT86RF233 Frame Filter passes only frames that satisfy all of the following requirements/rules (quote from [2]
IEEE 802.15.4-2006, Section 7.5.6.2):
1. The Frame Type subfield shall not contain a reserved frame type.
2. The Frame Version subfield shall not contain a reserved value.
3. If a destination PAN identifier is included in the frame, it shall match macPANId or shall be the broadcast PAN iden-
tifier (0xFFFF).
4. If a short destination address is included in the frame, it shall match either macShortAddress or the broadcast
address (0xFFFF). Otherwise, if an extended destination address is included in the frame, it shall match
aExtendedAddress.
5. If the frame type indicates that the frame is a beacon frame, the source PAN identifier shall match macPANId
unless macPANId is equal to 0xFFFF, in which case the beacon frame shall be accepted regardless of the source
PAN identifier.
6. If only source addressing fields are included in a data or MAC command frame, the frame shall be accepted only if
the device is the PAN coordinator and the source PAN identifier matches macPANId.
Moreover the AT86RF233 has two additional requirements:
7. The frame type shall indicate that the frame is not an acknowledgment (ACK) frame.
8. At least one address field must be present.
Address match, indicated by interrupt IRQ_5 (AMI), is further controlled by the content of subfields of the frame control
field of a received frame according to the following rule:
If Destination Addressing Mode is 0/1 and Source Addressing Mode is zero (see “Frame Control Field (FCF)” on page
948), no interrupt IRQ_5 (AMI) is generated. This effectively causes all acknowledgement frames not to be announced,
which would otherwise always pass the filter, regardless of whether they are intended for this device or not.
For backward compatibility to IEEE 802.15.4-2003 third level filter rule two (Frame Version) can be disabled by register
bits AACK_FVN_MODE (register 0x2E, CSMA_SEED_1).
Frame filtering is available in Extended and Basic Operating Mode. A frame that passes the Frame Filter generates the
interrupt IRQ_5 (AMI) if not masked.
Notes: 1. Filter rule one is affected by register bits AACK_FLTR_RES_FT and AACK_UPLD_RES_FT, “Register
Description” on page 933.
2. Filter rule two is affected by register bits AACK_FVN_MODE, Section “Register Description” on page 933.
37.2.1 Configuration
The Frame Filter is configured by setting the appropriate address variables and several additional properties as
described in Table 37-7.
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37.2.2 Handling of Reserved Frame Types
Reserved frame types (as described in “Configuration of non IEEE 802.15.4 Compliant Scenarios” on page 924) are
treated according to bits AACK_UPLD_RES_FT and AACK_FLTR_RES_FT of register 0x17 (XAH_CTRL_1) with three
options:
1. AACK_UPLD_RES_FT = 1, AACK_FLTR_RES_FT = 0:
Any non-corrupted frame with a reserved frame type is indicated by an IRQ_3 (TRX_END) interrupt. No further
address filtering is applied on those frames. An IRQ_5 (AMI) interrupt is never generated and the acknowledgment
subfield is ignored.
2. AACK_UPLD_RES_FT = 1, AACK_FLTR_RES_FT = 1:
If AACK_FLTR_RES_FT = 1 any frame with a reserved frame type is filtered by the address filter similar to a data
frame as described in the standard. This implies the generation of the IRQ_5 (AMI) interrupts upon address match.
An IRQ_3 (TRX_END) interrupt is only generated if the address matched and the frame was not corrupted. An
acknowledgment is only send, when the ACK request subfield was set in the received frame and an
IRQ_3 (TRX_END) interrupt occurred.
Table 37-7. Frame Filter Configuration
Register
Address
Register
Bits Register Name Description
0x20,0x21
0x22,0x23
0x24
…
0x2B
SHORT_ADDR_0/1
PAN_ID_0/1
IEEE_ADDR_0
…
IEEE_ADDR_7
Set macShortAddress, macPANId , and aExtendedAddress as
described in [2].
0x17 1AACK_PROM_MODE 0: Disable promiscuous mode.
1: Enable promiscuous mode.
0x17 4AACK_UPLD_RES_FT
Enable reserved frame type reception, needed to receive non-
standard compliant frames, see “Handling of Reserved Frame Types”
on page 953.
0: Disable reserved frame type reception.
1: Enable reserved frame type reception.
0x17 5AACK_FLTR_RES_FT
Filter reserved frame types like data frame type, needed for filtering of
non-standard compliant frames.
0: Disable reserved frame types filtering.
1: Enable reserved frame types filtering.
0x2E 3AACK_I_AM_COORD 0: Device is not PAN coordinator.
1: Device is PAN coordinator.
0x2E 7:6 AACK_FVN_MODE
Controls the ACK behavior, depends on FCF frame version number.
b00: Acknowledges only frames with version number 0, that is
according to IEEE 802.15.4-2003 frames.
b01: Acknowledges only frames with version number 0 or 1, that is
frames according to IEEE 802.15.4-2006.
b10: Acknowledges only frames with version number 0 or 1 or 2.
b11: Acknowledges all frames, independent of the FCF frame version
number.
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3. AACK_UPLD_RES_FT = 0:
Any received frame with a reserved frame type is discarded.
37.2.3 Register Description
37.2.3.1 XAH_CTRL_1
Name: XAH_CTRL_1
Offset: 0x17
Reset: 0x00
Property: -
The XAH_CTRL_1 register is a multi-purpose controls register for Extended Operating Mode.
zBit 5 - AACK_FLTR_RES_FT
Filter reserved frame types like data frame type. The register bit AACK_FLTR_RES_FT shall only be set if register
bit AACK_UPLD_RES_FT = 1.
Reserved frame types are explained in IEEE 802.15.4 Section 7.2.1.1.1.
zBit 4 - AACK_UPLD_RES_FT
Upload reserved frame types within RX_AACK mode.
In conjunction with the configuration bit AACK_FLTR_RES_FT, these frames are handled like IEEE 802.15.4 com-
pliant data frames during RX_AACK transaction. An IRQ_5 (AMI) interrupt is issued, if the addresses in the
received frame match the node’s addresses.
Bit 7 6 5 4 3 2 1 0
0x17 ARET_TX_
TS_EN
AACK_FLTR_
RES_
FT
AACK_UPLD
_RES_
FT
AACK_ACK
_TIME
AACK_PROM_
MODE
AACK_
SPC_EN
Access R/W R/W R/W R/W R R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Table 37-8. AACK_FLTR_RES_FT
Value Description
0x0(1) Filtering reserved frame types is disabled
0x1(2) Filtering reserved frame types is enabled
Notes: 1. If AACK_FLTR_RES_FT = 0 the received reserved frame is only checked for a valid FCS.
2. If AACK_FLTR_RES_FT = 1 reserved frame types are filtered similar to data frames as specified in IEEE
802.15.4–2006.
Table 37-9. AACK_UPLD_RES_FT
Value Description
0x0 Upload of reserved frame types is disabled
0x1(1) Upload of reserved frame types is enabled
Note: 1. If AACK_UPLD_RES_FT = 1 received frames indicated as a reserved frame are further processed. For
those frames, an IRQ_3 (TRX_END) interrupt is generated if the FCS is valid.
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That means, if a reserved frame passes the third level filter rules, an acknowledgement frame is generated and
transmitted if it was requested by the received frame. If this is not wanted register bit AACK_DIS_ACK
(register 0x2E, CSMA_SEED_1) has to be set.
zBit 1 - AACK_PROM_MODE
The register bit AACK_PROM_MODE enables the promiscuous mode, within the RX_AACK mode.
Refer to [2] IEEE 802.15.4-2006 Section 7.5.6.5.
If this register bit is set, every incoming frame with a valid PHR finishes with IRQ_3 (TRX_END) interrupt even if
the third level filter rules do not match or the FCS is not valid. However, register bit RX_CRC_VALID
(register 0x06, PHY_RSSI) is set accordingly.
In contrast to IEEE 802.15.4-2006, if a frame passes the third level filter rules, an acknowledgement frame is gen-
erated and transmitted unless disabled by register bit AACK_DIS_ACK (register 0x2E, CSMA_SEED_1), or use
Basic Operating Mode instead.
37.2.3.2 CSMA_SEED_1
Name: CSMA_SEED_1
Offset: 0x2E
Reset: 0x42
Property: -
The CSMA_SEED_1 register is a control register for RX_AACK and contains a part of the CSMA_SEED for the CSMA-
CA algorithm.
zBit 7:6 - AACK_FVN_MODE
The register bits AACK_FVN_MODE control the ACK behavior dependent on FCF frame version number within
RX_AACK mode.
Table 37-10. AACK_PROM_MODE
Value Description
0x0 Promiscuous mode is disabled
0x1 Promiscuous mode is enabled
Bit 7 6 5 4 3 210
0x2E AACK_FVN_MODE AACK_SET_
PD
AACK_DIS_
ACK
AACK_I_AM_
COORD CSMA_SEED_1
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 1 0 0 0 010
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The frame control field of the MAC header (MHR) contains a frame version subfield. The setting of register bits
AACK_FVN_MODE specifies the frame filtering behavior of the AT86RF233. According to the content of these
register bits the radio transceiver passes frames with a specific frame version number, number group, or indepen-
dent of the frame version number.
Thus the register bits AACK_FVN_MODE defines the maximum acceptable frame version. Received frames with a
higher frame version number than configured do not pass the frame filter and are not acknowledged.
The frame version field of the acknowledgment frame is set to zero according to IEEE 802.15.4-2006,
Section 7.2.2.3.1 Acknowledgment frame MHR fields.
zBit 3 - AACK_I_AM_COORD
This register bit has to be set if the node is a PAN coordinator. It is used for frame filtering in RX_AACK.
If AACK_I_AM_COORD = 1 and if only source addressing fields are included in a data or MAC command frame,
the frame shall be accepted only if the device is the PAN coordinator and the source PAN identifier matches mac-
PANId, for details refer to IEEE 802.15.4-2006, Section 7.5.6.2 (third-level filter rule six).
Table 37-11. AACK_FVN_MODE
Value Description
0x0 Accept frames with version number 0
0x1 Accept frames with version number 0 or 1
0x2 Accept frames with version number 0 or 1 or 2
0x3 Accept frames independent of frame version number
Note: 1. AACK_FVN_MODE value one indicates frames according to IEEE 802.15.4–2006, a value of three indi-
cates frames according to IEEE 802.15.4–2003 standard.
Table 37-12. AACK_I_AM_COORD
Value Description
0x0 PAN coordinator addressing is disabled
0x1 PAN coordinator addressing is enabled
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37.2.4 Register Description – Address Registers
37.2.4.1 SHORT_ADDR_0
Name: SHORT_ADDR_0
Offset: 0x20
Reset: 0xFF
Property: -
This register contains the lower 8-bit of the MAC short address for Frame Filter address recognition, bits[7:0].
37.2.4.2 SHORT_ADDR_1
Name: SHORT_ADDR_1
Offset: 0x21
Reset: 0xFF
Property: -
This register contains the higher 8-bit of the MAC short address for Frame Filter address recognition, bits[15:8].
37.2.4.3 PAN_ID_0
Name: PAN_ID_0
Offset: 0x22
Reset: 0xFF
Property: -
This register contains the lower 8-bit of the MAC PAN ID for Frame Filter address recognition, bits[7:0].
Bit 76543210
0x20 SHORT_ADDR_0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 11111111
Bit 76543210
0x21 SHORT_ADDR_1
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 11111111
Bit 76543210
0x22 PAN_ID_0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 11111111
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37.2.4.4 PAN_ID_1
Name: PAN_ID_1
Offset: 0x23
Reset: 0xFF
Property: -
This register contains the higher 8-bit of the MAC PAN ID for Frame Filter address recognition, bits[15:8].
37.2.4.5 IEEE_ADDR_0
Name: IEEE_ADDR_0
Offset: 0x24
Reset: 0x00
Property: -
This register contains the lower 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[7:0].
37.2.4.6 IEEE_ADDR_1
Name: IEEE_ADDR_1
Offset: 0x25
Reset: 0x00
Property: -
This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[15:8].
Bit 76543210
0x23 PAN_ID_1
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 11111111
Bit 76543210
0x24 IEEE_ADDR_0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit 76543210
0x25 IEEE_ADDR_1
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
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37.2.4.7 IEEE_ADDR_2
Name: IEEE_ADDR_2
Offset: 0x26
Reset: 0x00
Property: -
This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[23:16].
37.2.4.8 IEEE_ADDR_3
Name: IEEE_ADDR_3
Offset: 0x27
Reset: 0x00
Property: -
This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[31:24].
37.2.4.9 IEEE_ADDR_4
Name: IEEE_ADDR_4
Offset: 0x28
Reset: 0x00
Property: -
This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[39:32].
Bit 76543210
0x26 IEEE_ADDR_2
Access R/WR/WR/WR/WR/WR/WR/WR/W
Reset 00000000
Bit 76543210
0x27 IEEE_ADDR_3
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit 76543210
0x28 IEEE_ADDR_4
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
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37.2.4.10 IEEE_ADDR_5
Name: IEEE_ADDR_5
Offset: 0x29
Reset: 0x00
Property: -
This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[47:40].
37.2.4.11 IEEE_ADDR_6
Name: IEEE_ADDR_6
Offset: 0x2A
Reset: 0x00
Property: -
This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[55:48].
37.2.4.12 IEEE_ADDR_7
Name: IEEE_ADDR_7
Offset: 0x2B
Reset: 0x00
Property: -
This register contains the higher 8-bit of the MAC IEEE Frame Filter address for address recognition, bits[63:56].
Bit 76543210
0x29 IEEE_ADDR_5
Access R/WR/WR/WR/WR/WR/WR/WR/W
Reset 00000000
Bit 76543210
0x2A IEEE_ADDR_6
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit 76543210
0x2B IEEE_ADDR_7
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
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37.3 Frame Check Sequence (FCS)
The Frame Check Sequence (FCS) is characterized by:
zIndication of bit errors, based on a cyclic redundancy check (CRC) of length 16 bit
zA use of International Telecommunication Union (ITU) CRC polynomial
zAutomatic evaluation during reception
zAutomatic generation during transmission
37.3.1 Overview
The FCS is intended for use at the MAC layer to detect corrupted frames at a first level of filtering. It is computed by
applying an ITU CRC polynomial to all transferred bytes following the length field (MHR and MSDU fields). The frame
check sequence has a length of 16 bit and is located in the last two bytes of a frame (MAC footer, see Figure 37-2).
The AT86RF233 applies an FCS check on each received frame. The FCS check result is stored in register bit
RX_CRC_VALID (register 0x06, PHY_RSSI).
On transmission the radio transceiver generates and appends the FCS bytes during the frame transmission. This
behavior can be disabled by setting register bit TX_AUTO_CRC_ON = 0 (register 0x04, TRX_CTRL_1).
37.3.2 CRC Calculation
The CRC polynomial used in IEEE 802.15.4 networks is defined by
.
The FCS shall be calculated for transmission using the following algorithm:
Let
be the polynomial representing the sequence of bits for which the checksum is to be computed. Multiply M(x) by x16,
giving the polynomial
.
Divide N(x) modulo two by the generator polynomial, G16(x), to obtain the remainder polynomial,
.
The FCS field is given by the coefficients of the remainder polynomial, R(x).
Example:
Considering a five octet ACK frame. The MHR field consists of
0100 0000 0000 0000 0101 0110.
The leftmost bit (b0) is transmitted first in time. The FCS is in this case
0010 0111 1001 1110.
The leftmost bit (r0) is transmitted first in time.
37.3.3 Automatic FCS Generation
The automatic FCS generation is activated with register bit TX_AUTO_CRC_ON = 1. This allows the AT86RF233 to
compute the FCS autonomously. For a frame with a frame length specified as N (3 ≤N≤127), the FCS is calculated on
the first N-2 octets in the Frame Buffer, and the resulting FCS field is transmitted in place of the last two octets from the
Frame Buffer.
1)( 51216
16 +++= xxxxG
12
2
1
1
0
)( −−
−− ++++= kk
kk bxbxbxbxM K
16
)()( xxMxN ⋅=
1514
14
1
15
0...)( rxrxrxrxR ++++=
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If the radio transceiver’s automatic FCS generation is enabled, the Frame Buffer write access can be stopped right after
MAC payload. There is no need to write FCS dummy bytes.
In RX_AACK mode, when a received frame needs to be acknowledged, the FCS of the ACK frame is always
automatically generated by the AT86RF233, independent of the TX_AUTO_CRC_ON setting.
Example:
A frame transmission of length five with TX_AUTO_CRC_ON set, is started with a Frame Buffer write access of five
bytes (the last two bytes can be omitted). The first three bytes are used for FCS generation; the last two bytes are
replaced by the internally calculated FCS.
37.3.4 Automatic FCS Check
An automatic FCS check is applied on each received frame with a frame length N≥2. Register bit RX_CRC_VALID
(register 0x06, PHY_RSSI) is set if the FCS of a received frame is valid. The register bit is updated when issuing interrupt
IRQ_3 (TRX_END) and remains valid until the next TRX_END interrupt caused by a new frame reception. In addition,
bit[7] of byte RX_STATUS is set accordingly, refer to “Frame Buffer Access Mode” on page 886.
In Extended Operating Mode, the RX_AACK procedure does not accept a frame if the corresponding FCS is not valid,
that is no IRQ_3 (TRX_END) interrupt is issued. When operating in TX_ARET mode, the FCS of a received ACK is
automatically checked. If it is not correct, the ACK is not accepted; refer to “TX_ARET_ON – Transmit with Automatic
Frame Retransmission and CSMA-CA Retry” on page 928 for automated retries.
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37.3.5 Register Description
37.3.5.1 TRX_CTRL_1
Name: TRX_CTRL_1
Offset: 0x04
Reset: 0x22
Property: -
The TRX_CTRL_1 register is a multi-purpose register to control various operating modes and settings of the radio
transceiver.
zBit 5 - TX_AUTO_CRC_ON
The register bit TX_AUTO_CRC_ON controls the automatic FCS generation for transmit operations.
37.3.5.2 PHY_RSSI
Name: PHY_RSSI
Offset: 0x06
Reset: 0x60
Property: -
The PHY_RSSI register is a multi-purpose register that indicates FCS validity, to provide random numbers, and a RSSI
value.
zBit 7 - RX_CRC_VALID
The register bit RX_CRC_VALID signals the FCS check status for a received frame.
Bit 7 6 5 4 3 2 1 0
0x04 PA_EXT_EN IRQ_2_EXT_
EN
TX_AUTO_C
RC_ON RX_BL_CTRL SPI_CMD_MODE IRQ_MASK_
MODE
IRQ_
POLARITY
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 1 0 0 0 1 0
Table 37-13. TX_AUTO_CRC_ON
Value Description
0x0 Automatic FCS generation is disabled
0x1 Automatic FCS generation is enabled
Note: 1. The TX_AUTO_CRC_ON function can be used within Basic and Extended Operating Modes.
Bit 7 6 5 4 3210
0x06 RX_CRC_VALID RND_VALUE RSSI
Access R R R R RRRR
Reset 0 1 1 0 0000
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Reading this register bit indicates whether the last received frame has a valid FCS or not. The register bit is
updated when issuing interrupt IRQ_3 (TRX_END) and remains valid until the next TRX_END interrupt is issued,
caused by a new frame reception.
37.4 Received Signal Strength Indicator (RSSI)
The AT86RF233 Received Signal Strength Indicator is characterized by:
zMinimum RSSI level is -94dBm (RSSIBASE_VAL)
zDynamic range is 87dB
zMinimum RSSI value is 0
zMaximum RSSI value is 28
37.4.1 Overview
The RSSI is a 5-bit value indicating the receive power in the selected channel, in steps of 3dB. No attempt is made to
distinguish IEEE 802.15.4 signals from others, only the received signal strength is evaluated. The RSSI provides the
basis for an ED measurement, see “Energy Detection (ED)” on page 965.
37.4.2 Reading RSSI
In Basic Operating Modes, the RSSI value is valid in any receive state and is updated every tRSSI = 2µs. The current
RSSI value can be accessed by reading register bits RSSI (register 0x06, PHY_RSSI).
It is not recommended reading the RSSI value when using the Extended Operating Modes or Smart Receiving, see
“ SRT – Smart Receiving Technology” on page 1034. Instead, the automatically generated ED value should be used, see
“Energy Detection (ED)” on page 965.
37.4.3 Data Interpretation
The RSSI value is a 5-bit value in a range of zero to 28, indicating the receiver input power in steps of about 3dB.
A RSSI value of zero indicates a receiver RF input power of PRF ≤-94dBm. For a RSSI value in the range of one to 28,
the RF input power can be calculated as follows:
PRF[dBm] = RSSIBASE_VAL[dBm] + 3[dB] x RSSI
Table 37-14. RX_CRC_VALID
Value Description
0x0 FCS is not valid
0x1 FCS is valid
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37.4.4 Register Description
37.4.4.1 PHY_RSSI
Name: PHY_RSSI
Offset: 0x06
Reset: 0x60
Property: -
The PHY_RSSI register is a multi-purpose register that indicates FCS validity, to provide random numbers, and a RSSI
value.
zBit 4:0 - RSSI
Received signal strength as a linear curve on a logarithmic input power scale with a resolution of 3dB.
The result of the automated RSSI measurement is stored in register bits RSSI (register 0x06, PHY_RSSI). The
value is updated every tRSSI = 2µs in any receive state.
The read value is a number between zero and 28 indicating the received signal strength as a linear curve on a log-
arithmic input power scale with a resolution of 3dB. An RSSI value of zero indicates an RF input power of
PRF ≤-94dBm (RSSIBASE_VAL), a value of 28 a power of PRF ≥-10dBm (see parameter RSSIMAX specified in
“Receiver Characteristics” on page 1104).
37.5 Energy Detection (ED)
The AT86RF233 Energy Detection (ED) module is characterized by:
z84 unique energy levels defined
z1dB resolution
zA measurement time of eight symbol periods for IEEE 802.15.4 compliant data rates
37.5.1 Overview
The receiver ED measurement (ED scan procedure) can be used as a part of a channel selection algorithm. It is an
estimation of the received signal power within the bandwidth of an IEEE 802.15.4 channel. No attempt is made to identify
or decode signals on the channel. The ED value is calculated by averaging RSSI values over eight symbols (128µs).
For High Data Rate Modes the automated ED measurement duration is reduced to 32?s, refer to “High Data Rate
Modes” on page 1013. For manually initiated ED measurements in these modes the measurement period is still 128?s as
long as the receiver is in RX_ON state.
Bit 7 6543210
0x06 RX_CRC_VALID RND_VALUE RSSI
Access R RRRRRRR
Reset 0 1100000
Table 37-15. RSSI
Value Description
0x00 Minimum RSSI value
0x1C Maximum RSSI value
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37.5.2 Measurement Description
There are two ways to initiate an ED measurement:
zManually, by writing an arbitrary value to register 0x07 (PHY_ED_LEVEL), or
zAutomatically, after detection of a valid SHR of an incoming frame.
37.5.2.1 Manually:
For manually initiated ED measurements, the radio transceiver needs to be either in the state RX_ON or BUSY_RX. The
end of the ED measurement time (eight symbol periods plus a processing time) is indicated by the interrupt
IRQ_4 (CCA_ED_DONE) and the measurement result is stored in register 0x07 (PHY_ED_LEVEL), refer to tED in Table
36-2 on page 912.
In order to avoid interference with an automatically initiated ED measurement, the SHR detection can be disabled by
setting register bit RX_PDT_DIS (register 0x15, RX_SYN), refer to “Receiver (RX)” on page 975.
Note: It is not recommended to manually initiate an ED measurement when using the Extended Operation Mode.
37.5.2.2 Automatically:
An automated ED measurement is started upon SHR detection. The end of the automated measurement is not signaled
by an interrupt.
When using Basic Operating Mode, a valid ED value from the currently received frame is accessible 108µs after
IRQ_2 (RX_START) and remains valid until a new RX_START interrupt is generated by the next incoming frame or until
another ED measurement is initiated.
When using the Extended Operating Mode, it is recommended to mask IRQ_2 (RX_START), thus the interrupt cannot be
used as timing reference. A successful frame reception is signalized by interrupt IRQ_3 (TRX_END). The minimum time
span between an IRQ_3 (TRX_END) interrupt and a following SFD detection is tSHR_SYNC = 96µs due to the length of the
SHR. Including the ED measurement time, the ED value needs to be read within 224µs after the TRX_END interrupt;
otherwise, it could be overwritten by the result of the next measurement cycle. This is important for time critical
applications or if interrupt IRQ_2 (RX_START) is not used to indicate the reception of a frame.
Note: The ED result is not updated during the rest of the frame reception, even by requesting an ED measurement
manually.
37.5.3 Data Interpretation
The PHY_ED_LEVEL is an 8-bit register. The ED_LEVEL value of the AT86RF233 has a valid range from 0x00 to 0x53
with a resolution of 1dB. Values 0x54 to 0xFE do not occur and a value of 0xFF indicates the reset value.
Due to environmental conditions (temperature, voltage, semiconductor parameters, etc.) the calculated ED_LEVEL value
has a maximum tolerance of ±5dB, this is to be considered as constant offset over the measurement range.
An ED_LEVEL value of zero indicates a receiver RF input power of PRF ≤-94dBm (see parameter RSSIBASE_VAL,
“Receiver Characteristics” on page 1104). For an ED_LEVEL value in the range of one to 83, the RF input power can be
calculated as follows:
PRF[dBm] = RSSIBASE_VAL[dBm] + 1[dB] x ED_LEVEL
37.5.4 Interrupt Handling
Interrupt IRQ_4 (CCA_ED_DONE) is issued at the end of a manually initiated ED measurement.
Note: 1. An ED request should only be initiated in receive states. Otherwise the radio transceiver generates an
IRQ_4 (CCA_ED_DONE); however no ED measurement was performed.
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37.5.5 Register Description
37.5.5.1 PHY_ED_LEVEL
Name: PHY_ED_LEVEL
Offset: 0x07
Reset: 0xFF
Property: -
The PHY_ED_LEVEL register contains the result of an ED measurement.
zBit 7:0 - ED_LEVEL
The register bits ED_LEVEL signals the ED level for the current channel.
The minimum ED value zero indicates receiver power less than or equal RSSIBASE_VAL. The range is 83dB with a
resolution of 1dB and an accuracy of ±5dB. The value 0xFF signals that no measurement has been started yet
(reset value).
A manual ED measurement can be initiated by a write access to the register.
The measurement duration is eight symbol periods (128µs) for a data rate of 250kb/s.
For High Data Rate Modes the automated measurement duration is reduced to 32?s, refer to “High Data Rate
Modes” on page 1013. For manually initiated ED measurements in these modes the measurement period is still
128?s as long as the receiver is in RX_ON state.
Bit 76543210
0x07 ED_LEVEL
AccessRRRRRRRR
Reset 11111111
Table 37-16. ED_LEVEL
Value Description
0x00 Minimum ED level value
0x53 Maximum ED level value
0xFF Reset value
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37.6 Clear Channel Assessment (CCA)
The main features of the Clear Channel Assessment (CCA) module are:
zAll four modes are available as defined by IEEE 802.15.4-2006 in Section 6.9.9
zAdjustable threshold for energy detection algorithm
37.6.1 Overview
A CCA measurement is used to detect a clear channel. Four CCA modes are specified by IEEE 802.15.4-2006:
37.6.2 Configuration and Request
The CCA modes are configurable via register 0x08 (PHY_CC_CCA).
When in Basic Operating Mode, an CCA request can be initiated manually by setting CCA_REQUEST = 1 (register 0x08,
PHY_CC_CCA), if the Atmel AT86RF233 is in any RX state. The current channel status (CCA_STATUS) and the CCA
completion status (CCA_DONE) are accessible through register 0x01 (TRX_STATUS).
The CCA evaluation is done over eight symbol periods and the result is accessible tCCA = 180µs (max.) (128µs
measurement duration and processing delay) after the request, refer to Table 36-2 on page 912. The end of a manually
initiated CCA measurement is indicated by an interrupt IRQ_4 (CCA_ED_DONE).
The register bits CCA_ED_THRES (register 0x09, CCA_THRES) defines the receive power threshold of the “energy
above threshold” algorithm. The threshold is calculated by:
PCCA_ED_THRES[dBm] = RSSIBASE_VAL[dBm] + 2[dB] x CCA_ED_THRES.
Any received power above this level is interpreted as a busy channel.
Note: It is not recommended to manually initiate and CCA measurement when using the Extended Operating Mode.
37.6.3 Data Interpretation
The AT86RF233 current channel status (CCA_STATUS) and the CCA completion status (CCA_DONE) are accessible
through register 0x01 (TRX_STATUS).
Note: The register bits CCA_DONE and CCA_STATUS are cleared in response to a CCA REQUEST.
The completion of a measurement cycle is indicated by CCA_DONE = 1. If the radio transceiver detects no signal (idle
channel) during the CCA evaluation period, the CCA_STATUS bit is set to one; otherwise, it is set to zero.
Table 37-17. CCA Mode Overview
CCA Mode Description
1Energy above threshold.
CCA shall report a busy medium upon detecting any energy above the ED threshold.
2
Carrier sense only.
CCA shall report a busy medium only upon the detection of a signal with the modulation and spreading
characteristics of an IEEE 802.15.4 compliant signal. The signal strength may be above or below the ED
threshold.
0, 3
Carrier sense with energy above threshold.
CCA shall report a busy medium using a logical combination of
Detection of a signal with the modulation and spreading characteristics of this standard and
Energy above the ED threshold.
Where the logical operator may be configured as either OR (mode 0) or AND (mode 3).
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When using the “energy above threshold” algorithm, a received power above PCCA_ED_THRES is interpreted as a busy
channel.
When using the “carrier sense” algorithm (that is CCA_MODE = 0, 2, and 3), the AT86RF233 reports a busy channel
upon detection of a PHY mode specific IEEE 802.15.4 signal above RSSIBASE_VAL (see “Receiver Characteristics” on
page 1104). The AT86RF233 is also capable of detecting signals below this value, but the detection probability
decreases with decreasing signal power. It is almost zero at the radio transceivers sensitivity level (see parameter PSENS
on “Receiver Characteristics” on page 1104).
37.6.4 Interrupt Handling
Interrupt IRQ_4 (CCA_ED_DONE) is issued at the end of a manually initiated CCA measurement.
Note: A CCA request should only be initiated in Basic Operating Mode receive states. Otherwise the radio transceiver
generates an IRQ_4 (CCA_ED_DONE) and sets the register bit CCA_DONE = 1, even though no CCA mea-
surement was performed.
37.6.5 Measurement Time
The response time for a manually initiated CCA measurement depends on the receiver state.
In RX_ON state, the CCA measurement is done over eight symbol periods and the result is accessible upon the event
IRQ_4 (CCA_ED_DONE) or upon CCA_DONE = 1 (register 0x01, TRX_STATUS).
In BUSY_RX state, the CCA measurement duration depends on the CCA mode and the CCA request relative to the
detection of the SHR. The end of the CCA measurement is indicated by IRQ_4 (CCA_ED_DONE). The variation of a
CCA measurement period in BUSY_RX state is described in Table 37-18.
It is recommended to perform CCA measurements in RX_ON state only. To avoid switching accidentally to BUSY_RX
state, the SHR detection can be disabled by setting register bit RX_PDT_DIS (register 0x15, RX_SYN), refer to
“Receiver (RX)” on page 975. The receiver remains in RX_ON state to perform a CCA measurement until the register bit
RX_PDT_DIS is set back to continue the frame reception. In this case, the CCA measurement duration is eight symbol
periods.
Table 37-18. CCA Measurement Period and Access in BUSY_RX state
CCA Mode Request within ED measurement(1) Request after ED measurement
1
Energy above threshold.
CCA result is available after finishing automated ED
measurement period. CCA result is immediately available after request.
2
Carrier sense only.
CCA result is immediately available after request.
3
Carrier sense with Energy above threshold (AND).
CCA result is available after finishing automated ED
measurement period. CCA result is immediately available after request.
0
Carrier sense with Energy above threshold (OR).
CCA result is available after finishing automated ED
measurement period. CCA result is immediately available after request.
Note: 1. After detecting the SHR, an automated ED measurement is started with a length of eight symbol periods
(two symbol periods for high rate PHY modes, refer to “Energy Detection (ED)” on page 965. This auto-
mated ED measurement must be finished to provide a result for the CCA measurement. Only one
automated ED measurement per frame is performed.
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37.6.6 Register Description
37.6.6.1 TRX_STATUS
Name: TRX_STATUS
Offset: 0x01
Reset: 0x00, 0x08
Property: -
The read-only register TRX_STATUS signals the present state of the radio transceiver as well as the status of a CCA
operation.
zBit 7 - CCA_DONE
The register bit CCA_DONE indicates if a CCA request is completed. This is also indicated by an interrupt
IRQ_4 (CCA_ED_DONE). The register bit CCA_DONE is cleared in response to a CCA_REQUEST.
zBit 6 - CCA_STATUS
After a CCA request is completed, the result of the CCA measurement is available in register bit CCA_STATUS.
The register bit CCA_STATUS is cleared in response to a CCA_REQUEST.
Bit 7 6 5 4 3 2 1 0
0x01 CCA_DONE CCA_STATUS TRX_STATUS
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Table 37-19. CCA_DONE
Value Description
0x0 CCA calculation not finished
0x1 CCA calculation finished
Table 37-20. CCA_STATUS
Value Description
0x0 Channel indicated as busy
0x1 Channel indicated as idle
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37.6.6.2 PHY_CC_CCA
Name: PHY_CC_CCA
Offset: 0x08
Reset: 0x2B
Property: -
The PHY_CC_CCA register is a multi-purpose register that controls CCA configuration, CCA measurement, and the
IEEE 802.15.4 channel setting.
zBit 7 - CCA_REQUEST
The register bit CCA_REQUEST initiates a manual started CCA measurement.
A manual CCA measurement is initiated with setting CCA_REQUEST = 1. The end of the CCA measurement is
indicated by interrupt IRQ_4 (CCA_ED_DONE). Register bits CCA_DONE and CCA_STATUS (register 0x01,
TRX_STATUS) are updated after a CCA_REQUEST. The register bit is automatically cleared after requesting a
CCA measurement with CCA_REQUEST = 1.
zBit 6:5 - CCA_MODE
The CCA mode can be selected using register bits CCA_MODE.
Bit 7 6543210
0x08 CCA_REQUEST CCA_MODE CHANNEL
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0101011
Table 37-21. CCA_REQUEST
Value Description
0x0 Reset value
0x1 Starts a CCA measurement
Notes: 1. The read value returns always with zero.
2. If a CCA request is initiated in states others than RX_ON or RX_BUSY the PHY generates an IRQ_4
(CCA_ED_DONE) and sets the register bit CCA_DONE, however no CCA was carried out.
Table 37-22. CCA_MODE
Value Description
0x0 Mode 3a, Carrier sense OR energy above threshold
0x1 Mode 1, Energy above threshold
0x2 Mode 2, Carrier sense only
0x3 Mode 3b, Carrier sense AND energy above threshold
Note: 1. IEEE 802.15.4–2006 CCA mode 3 defines the logical combination of CCA mode 1 and 2 with the logical
operators AND or OR
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37.6.6.3 CCA_THRES
Name: CCA_THRES
Offset: 0x09
Reset: 0xC7
Property: -
The CCA_THRES register sets the ED threshold level for CCA.
zBit 3:0 - CCA_ED_THRES
An ED value above the threshold signals the channel as busy during a CCA_ED measurement.
37.7 Link Quality Indication (LQI)
The IEEE 802.15.4 standard defines the LQI as a characterization of the strength and/or quality of a received frame. The
use of the LQI result by the network or application layer is not specified in this standard. The LQI value shall be an integer
ranging from zero to 255, with at least eight unique values. The minimum and maximum LQI values (0x00 and 0xFF)
should be associated with the lowest and highest quality compliant signals, respectively, and LQI values in between
should be uniformly distributed between these two limits.
37.7.1 Overview
The LQI measurement of the AT86RF233 is implemented as a measure of the link quality which can be described with
the packet error rate (PER) for this link. An LQI value can be associated with an expected packet error rate. The PER is
the ratio of erroneous received frames to the total number of received frames. A PER of zero indicates no frame error,
whereas at a PER of one no frame was received correctly.
The radio transceiver uses correlation results of multiple symbols within a frame to determine the LQI value. This is done
for each received frame. The minimum frame length for a valid LQI value is two octets PSDU. LQI values are integers
ranging from zero to 255.
As an example, Figure 37-4 shows the conditional packet error rate (PER) when receiving a certain LQI value.
Bit 76543210
0x09 CCA_ED_THRES
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 11000111
Table 37-23. CCA_ED_THRES
Value Description
0x7 For CCA_MODE = 1, a busy channel is indicated if the measured received power is above P_THRES[dBm] =
RSSI_BASE_VAL[dBm] + 2[dB] x CCA_ED_THRES. CCA modes 0 and 3 are logically related to this result.
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Figure 37-4. Conditional Packed Error Rate vs. LQI
That means that a large number of transmission with an identical LQI value results in a packet error rate shown in the
Figure 37-4. Lost packets have been discarded since in this case there is no LQI value available.
If, instead, the mean LQI over a large number of transmissions is computed, and the mean LQI is quantized to an LQI
value of the figure, the corresponding frame error rate is not strictly equal to the true error rate.
The values are taken from received frames of PSDU length of 20 octets on transmission channels with reasonable low
multipath delay spreads. If the transmission channel characteristic has higher multipath delay spread than assumed in
the example, the PER is slightly higher for a certain LQI value.
Since the packet error rate is a statistical value, the PER shown in Figure 37-4 is based on a huge number of
transactions. A reliable estimation of the packet error rate cannot be based on a single or a small number of LQI values.
37.7.2 Obtaining the LQI Value
The LQI value is available, once the corresponding frame has been completely received. This is indicated by the interrupt
IRQ_3 (TRX_END). The value can be obtained by means of a frame buffer read access, see “Frame Buffer Access
Mode” on page 886.
37.7.3 Data Interpretation
The reason for a low LQI value can be twofold: a low signal strength and/or high signal distortions, for example by
interference and/or multipath propagation. High LQI values, however, indicate a sufficient signal strength and low signal
distortions.
Notes: 1. The LQI value is almost always 255 for scenarios with very low signal distortions and a signal strength much
greater than the sensitivity level. In this case, the packet error rate tends towards zero and increase of the
signal strength, that is by increasing the transmission power, cannot decrease the error rate any further.
Received signal strength indication (RSSI) or energy detection (ED) can be used to evaluate the signal
strength and the link margin.
2. The received signal power as indicated by received signal strength indication (RSSI) value or energy detec-
tion (ED) value of the AT86RF233 do not characterize the signal quality and the ability to decode a signal.
ZigBee networks often require identification of the “best” routing between two nodes. LQI and RSSI/ED can be applied,
depending on the optimization criteria. If a low frame error rate (corresponding to a high throughput) is the optimization
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0 50 100 150 200 250
PER
LQI
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criteria, then the LQI value should be taken into consideration. If, however, the target is a low transmission power, then
the RSSI/ED value is also helpful.
Various combinations of LQI and RSSI/ED are possible for routing decisions. As a rule of thumb, information on RSSI/ED
is useful in order to differentiate between links with high LQI values. However, transmission links with low LQI values
should be discarded for routing decisions, even if the RSSI/ED values are high, since it is merely an information about
the received signal strength, whereas the source can be an interferer.
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38. AT86RF233 Module Description
38.1 Receiver (RX)
38.1.1 Overview
The AT86RF233 receiver is split into an analog radio front-end and a digital base band processor (RX BBP), see Figure
38-1.
Figure 38-1. Receiver Block Diagram
The differential RF signal is amplified by a low noise amplifier (LNA), filtered (PPF) and down converted to an
intermediate frequency by a mixer. Channel selectivity is performed using an integrated band pass filter (BPF). A limiting
amplifier (Limiter) provides sufficient gain to overcome the DC offset of the succeeding analog-to-digital converter (ADC)
and generates a digital RSSI signal. The ADC output signal is sampled and processed further by the digital base band
receiver (RX BBP).
The RX BBP performs additional signal filtering and signal synchronization. The frequency offset of each frame is
calculated by the synchronization unit and is used during the remaining receive process to correct the offset. The
receiver is designed to handle frequency and symbol rate deviations fSRD up to ±120ppm, caused by combined receiver
and transmitter deviations. For details refer to “General RF Specifications” on page 1102 parameter fSRD. Finally the
signal is demodulated and the data are stored in the Frame Buffer.
In Basic Operating Mode, refer to “Basic Operating Mode” on page 902, the reception of a frame is indicated by an
interrupt IRQ_2 (RX_START). Accordingly its end is signalized by an interrupt IRQ_3 (TRX_END). Based on the quality
of the received signal a link quality indicator (LQI) is calculated and appended to the frame, refer to “Link Quality
Indication (LQI)” on page 972. Additional signal processing is applied to the frame data to provide further status
information like ED value (register 0x07, PHY_ED_LEVEL) and FCS correctness (register 0x06, PHY_RSSI).
Beyond these features the Extended Operating Mode of the AT86RF233 supports address filtering and pending data
indication. For details refer to “Extended Operating Mode” on page 915.
38.1.2 Frame Receive Procedure
The frame receive procedure including the radio transceiver setup for reception and reading PSDU data from the Frame
Buffer is described in “Frame Receive Procedure” on page 1003 Frame Receive Procedure.
38.1.3 Configuration
In Basic Operating Mode the receiver is enabled by writing command RX_ON to register bits TRX_CMD
(register 0x02, TRX_STATE) in states TRX_OFF or PLL_ON. Similarly in Extended Operating Mode, the receiver is
enabled for RX_AACK operation from states TRX_OFF, PLL_ON or TX_ARET_ON by writing the command
RX_AACK_ON.
There is no additional configuration required to receive IEEE 802.15.4 compliant frames when using the Basic Operating
Mode. However, the frame reception in the AT86RF233 Extended Operating Mode requires further register
configurations, for details refer to “Extended Operating Mode” on page 915.
LNA PPF BPF Limiter ADC
AGC RSSI
RFP
RFN
Analog Domain Digital Domain
SPIRX BBP
Frame
Buffer
LO
Control, Registers
SPI
I/F
µC
I/F
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The AT86RF233 receiver has an outstanding sensitivity performance of -99dBm. At certain environmental conditions or
for High Data Rate Modes (“High Data Rate Modes” on page 1013) it may be useful to manually decrease this sensitivity.
This is achieved by adjusting the synchronization header detector threshold using register bits RX_PDT_LEVEL
(register 0x15, RX_SYN). Received signals with a RSSI value below the threshold do not activate the demodulation
process.
Furthermore, it may be useful to protect a received frame against overwriting by subsequent received frames. A Dynamic
Frame Buffer Protection is enabled with register bit RX_SAFE_MODE (register 0x0C, TRX_CTRL_2) set, see “Dynamic
Frame Buffer Protection” on page 1032. The receiver remains in RX_ON or RX_AACK_ON state until the whole frame is
uploaded by the microcontroller, indicated by /SEL = H during the SPI Frame Receive Mode. The Frame Buffer content is
only protected if the FCS is valid.
A Static Frame Buffer Protection is enabled with register bit RX_PDT_DIS (register 0x15, RX_SYN) set. The receiver
remains in RX_ON or RX_AACK_ON state and no further SHR is detected until the register bit RX_PDT_DIS is set back.
38.1.4 Register Description
38.1.4.1 RX_SYN
Name: RX_SYN
Offset: 0x15
Reset: 0x00
Property: -
The register RX_SYN controls the blocking of receiver path and the sensitivity threshold of the receiver.
zBit 7 - RX_PDT_DIS
The register bit RX_PDT_DIS prevents the reception of a frame during RX phase.
.
RX_PDT_DIS = 1 prevents the reception of a frame even if the radio transceiver is in receive modes. An ongoing
frame reception is not affected. This operation mode is independent of the setting of register bits RX_PDT_LEVEL.
zBit 3:0 - RX_PDT_LEVEL
The register bits RX_PDT_LEVEL desensitize the receiver in steps of 3dB.
Bit 7 6543210
0x15 RX_PDT_DIS RX_PDT_LEVEL
Access R/W R R R R/W R/W R/W R/W
Reset 0 0000000
Table 38-1. RX_PDT_DIS
Value Description
0x0 RX path is enabled
0x1 RX path is disabled
Table 38-2. RX_PDT_LEVEL
Value Description
0x00 Maximum RX sensitivity
0x0F RX input level[dBm] > RSSI_BASE_VAL[dBm] + 3[dB] x 14
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These register bits desensitize the receiver such that frames with an RSSI level below the RX_PDT_LEVEL
threshold level (if RX_PDT_LEVEL > 0) are not received. For a RX_PDT_LEVEL > 0 value the threshold level can
be calculated according to the following formula:
PRF[dBm] > RSSIBASE_VAL[dBm] + 3[dB] x (RX_PDT_LEVEL - 1).
Examples for certain register settings are given in Table 38-3.
If register bits RX_PDT_LEVEL = 0 (reset value) all frames with a valid SHR and PHR are received, independently
of their signal strength.
If register bits RX_PDT_LEVEL > 0, the current consumption of the receiver in all RX listening states is reduced to
IRX_ON_L0 = 11.3mA (typ.), refer to “Current Consumption Specifications” on page 1105.
Additional power saving techniques in receive modes are specified in “Reduced Power Consumption Mode (RPC)”
on page 1034.
38.1.4.2 TST_AGC
Name: TST_AGC
Offset: 0x3C
Reset: 0x00
Property: -
Note: 1. The register bits can be read or written, the values will effect the device operation only if the register bit
PMU_EN (register 0x03, TRX_CTRL_0) is set, otherwise reset values will be applied.
zBit 5 - AGC_HOLD_SEL
The register bit AGC_HOLD_SEL controls the AGC operation mode.
zBit 4 - AGC_RST
The register bit AGC_RST resets the AGC receiver gain control to maximum gain.
Table 38-3. Receiver Desensitization Threshold Level – RX_PDT_LEVEL
Register Value RX Input Threshold Level Value [dBm]
0x0 ≤ RSSI_BASE_VAL (reset value) RSSI value not considered
0x1 > RSSI_BASE_VAL + 3[db] x 0 > -94
…
0xE > RSSI_BASE_VAL + 3[db] x 13 > -55
0xF > RSSI_BASE_VAL + 3[db] x 14 > -52
Bit 76543210
0x3C AGC_HOLD_
SEL AGC_RST AGC_OFF AGC_HOLD GC
Access R R R/W R/W R/W R/W R/W R/W
Reset00000000
Table 38-4. AGC_HOLD_SEL
Value Description
0x0 Normal operation is selected
0x1 Manual control of AGC operation is selected. Used setting from register bit AGC_HOLD.
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zBit 3 - AGC_OFF
The register bit AGC_OFF disables automatic AGC gain regulation. Allows manual receiver gain setting with regis-
ter bits GC.
zBit 2 - AGC_HOLD
The register bit AGC_HOLD controls the AGC running mode.
zBit 1:0 - GC
The register bits GC control the receiver gain. A setting of register bits GC effect the device operation only if regis-
ter bit AGC_OFF is set.
Table 38-5. AGC_RST
Value Description
0x0 No AGC gain control reset
0x1 AGC gain control reset
Table 38-6. AGC_OFF
Value Description
0x0 Automatic AGC gain regulation is switched on
0x1 Automatic AGC gain regulation is switched off
Table 38-7. AGC_HOLD
Value Description
0x0 AGC is within free running mode
0x1 AGC running mode is frozen
Table 38-8. GC
Value Description
0x0 Set receiver path to maximum gain
0x1 Set receiver path to medium gain
0x2 Set receiver path to minimum gain
All other values are reserved
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38.2 Transmitter (TX)
38.2.1 Overview
The AT86RF233 transmitter consists of a digital base band processor (TX BBP) and an analog radio front end, see
Figure 38-2.
Figure 38-2. Transmitter Block Diagram
The TX BBP reads the frame data from the Frame Buffer and performs the bit-to-symbol and symbol-to-chip mapping as
specified by IEEE 802.15.4 in Section 6.5.2. The O-QPSK modulation signal is generated and fed into the analog radio
front end.
The fractional-N frequency synthesizer (PLL) converts the baseband transmit signal to the RF signal, which is amplified
by the power amplifier (PA). The PA output is internally connected to bidirectional differential antenna pins (RFP, RFN),
so that no external antenna switch is needed.
38.2.2 Frame Transmit Procedure
The frame transmit procedure including writing PSDU data in the Frame Buffer and initiating a transmission is described
in “Frame Transmit Procedure” on page 1003.
38.2.3 Configuration
The maximum output power of the transmitter is typically +4dBm. The output power can be configured via register bits
TX_PWR (register 0x05, PHY_TX_PWR). The output power of the transmitter can be controlled over a range of 21dB.
A transmission can be started from PLL_ON or TX_ARET_ON state by a rising edge of SLP_TR or by writing TX_START
command to register bits TRX_CMD (register 0x02, TRX_STATE).
Figure 38-3. TX Power Ramping for Maximum TX Power
PLL – TX Modulation PA
Ext. RF front-end and
Output Power Control
SPI
I/F
DIG3/4
RFP
RFN
TX Data
Analog Domain Digital Domain
TX BBP
Frame
Buffer
Control, Registers
SPI
µC
I/F
Buf
06810
TRX_STATE
SLP_TR
PLL_ON
212 14 16 18 Length [μs]
PA buffer
4
PA
Modulation 11 00 00001
BUSY_TX
10 01 0101101 10 1010001
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38.2.4 TX Power Ramping
To optimize the output power spectral density (PSD), the PA buffer and PA are enabled sequentially, see in Figure 38-3.
In this example the transmission is initiated with the rising edge of SLP_TR. The radio transceiver state changes from
PLL_ON to BUSY_TX. The modulation of the frame starts 16µs after SLP_TR rising edge.
38.2.5 Register Description
38.2.5.1 PHY_TX_PWR
Name: PHY_TX_PWR
Offset: 0x05
Reset: 0x00
Property: -
The PHY_TX_PWR register controls the output power of the transmitter.
zBit 3:0 – TX_PWR
The register bits TX_PWR determine the TX output power of the radio transceiver.
Bit 76543210
0x05 TX_PWR
Access R R/W R R R/W R/W R/W R/W
Reset 00000000
Table 38-9. TX_PWR
Value TX Output Power [dBm]
0x0 +4
0x1 +3.7
0x2 +3.4
0x3 +3
0x4 +2.5
0x5 +2
0x6 +1
0x7 0
0x8 -1
0x9 -2
0xA -3
0xB -4
0xC -6
0xD -8
0xE -12
0xF -17
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Notes: 1. A state change that is a command gets written to the TRX_CMD field resets the value of the TX_PWR fields
to the originally set value.
2. If the extended operating mode is used with RPC enabled (that is XAH_TX_RPC_EN is set to one), the read
value of the TX_PWR field provides the used transmit power for last transmitted frame including acknowl-
edgement frame. The TX_PWR field contains only the value of the RPC-controlled transmission if a frame
has already been sent. This allows monitoring the actual RPC handling used for transmitting.
38.2.5.2 PHY_TX_TIME for TOM_EN=0x01
Name: PHY_TX_TIME
Offset: 0x3B
Reset: 0x00
Property: -
Notes: 1. If PMU mode is active, signals 8-bit PMU measurement value.
2. If TOM mode is active, signals 4-bit IRC_TX_TIME value.
zBit 3:0 - IRC_TX_TIME
The register bits IRC_TX_TIME signals the alignment between rising edge of SLP_TR to 1MHz CLKM clock.
38.3 Frame Buffer
The AT86RF233 contains a 128 byte dual port SRAM. One port is connected to the SPI interface, the other one to the
internal transmitter and receiver modules. For data communication, both ports are independent and simultaneously
accessible.
The Frame Buffer utilizes the SRAM address space 0x00 to 0x7F for RX and TX operation of the radio transceiver and
can keep a single IEEE 802.15.4 RX or a single TX frame of maximum length at a time.
Frame Buffer access modes are described in “Frame Buffer Access Mode” on page 886. Frame Buffer access conflicts
are indicated by an under run interrupt IRQ_6 (TRX_UR).
Note: The IRQ_6 (TRX_UR) interrupt also occurs on the attempt to write frames longer than 127 octets to the Frame
Buffer (overflow). In that case the content of the Frame Buffer cannot be guaranteed.
Frame Buffer access is only possible if the digital voltage regulator (DVREG) is turned on. This is valid in all device states
except in SLEEP or DEEP_SLEEP state. An access in P_ON state is possible if CLKM provides a master clock.
38.3.1 Data Management
Data in Frame Buffer (received data or data to be transmitted) remains valid as long as:
zNo new frame or other data are written into the buffer over SPI
zNo new frame is received (in any BUSY_RX state)
zNo state change into SLEEP or DEEP_SLEEP state is made
zNo RESET took place
Bit 76543210
0x3B IRC_TX_TIME
AccessRRRRRRRR
Reset 00000000
Table 38-10. IRC_TX_TIME
Value Description
0x0 Signals 4-bit IRC_TX_TIME measurement value. The resolution is 1/16MHz.
Valid values are [0xF, 0xE, …, 0x0].
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By default there is no protection of the Frame Buffer against overwriting. Therefore, if a frame is received during Frame
Buffer read access of a previously received frame, interrupt IRQ_6 (TRX_UR) is issued and the stored data might be
overwritten.
Even so, the old frame data can be read, if the SPI data rate is higher than the effective over air data rate. For a data rate
of 250kb/s a minimum SPI clock rate of 1MHz is recommended. Finally the microcontroller should check the transferred
frame data integrity by an FCS check.
To protect the Frame Buffer content against being overwritten by newly incoming frames, the radio transceiver state
should be changed to PLL_ON state after reception. This can be achieved by writing immediately the command PLL_ON
to register bits TRX_CMD (register 0x02, TRX_STATE) after receiving the frame, indicated by IRQ_3 (TRX_END).
Alternatively, Dynamic Frame Buffer Protection can be used to protect received frames against overwriting, for details
refer to “Dynamic Frame Buffer Protection” on page 1032. Both procedures do not protect the Frame Buffer from
overwriting by the microcontroller.
In Extended Operating Mode during TX_ARET operation, see “TX_ARET_ON – Transmit with Automatic Frame
Retransmission and CSMA-CA Retry” on page 928, the radio transceiver switches to receive, if an acknowledgement of
a previously transmitted frame was requested. During this period received frames are evaluated, but not stored in the
Frame Buffer. This allows the radio transceiver to wait for an acknowledgement frame and retry the frame transmission
without writing them again.
A radio transceiver state change, except a transition to SLEEP, DEEP_SLEEP, or RESET state, does not affect the
Frame Buffer contents. If the radio transceiver is forced into SLEEP or DEEP_SLEEP, the Frame Buffer is powered off
and the stored data gets lost.
38.3.2 User accessible Frame Content
The AT86RF233 supports an IEEE 802.15.4 compliant frame format as shown in Figure 38-4.
Figure 38-4. AT86RF233 Frame Structure
Note: Stored into Frame Buffer during reception.
A frame comprises two sections, the radio transceiver internally generated SHR field and the user accessible part stored
in the Frame Buffer. The SHR contains the preamble and the SFD field. The variable frame section contains the PHR
and the PSDU including the FCS, see “Frame Check Sequence (FCS)” on page 961.
To access the data follow the procedures described in “Frame Buffer Access Mode” on page 886.
The frame length information (PHR field) and the PSDU are stored in the Frame Buffer. During frame reception, the link
quality indicator (LQI) value, the energy detection (ED) value, and the status information (RX_STATUS) of a received
frame are additionally stored, see “Link Quality Indication (LQI)” on page 972, “Energy Detection (ED)” on page 965, and
“Frame Buffer Access Mode” on page 886, respectively. The radio transceiver appends these values to the frame data
during Frame Buffer read access.
If the SRAM read access is used to read an RX frame, the frame length field (PHR) can be accessed at address zero.
The SHR (except the SFD value used to generate the SHR) cannot be read by the microcontroller.
For frame transmission, the PHR and the PSDU needs to be stored in the Frame Buffer. The maximum Frame Buffer
size supported by the radio transceiver is 128 bytes. If the register bit TX_AUTO_CRC_ON is set in register 0x04
(TRX_CTRL_1), the FCS field of the PSDU is replaced by the automatically calculated FCS during frame transmission.
There is no need to write the FCS field when using the automatic FCS generation.
Preamble Sequence SFD PHR Payload LQI
(1)
FCS
04 5 6 n + 3 n + 5 n + 6
Frame
Access SHR not accesible
RX: Frame Buffer content
PHY generated
Length [octets]
Duration 4 octets 1n octets (n <= 128) 3 octets
TX: Frame Buffer content
ED
(1)
RX_STATUS
(1)
n + 7 n + 8
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To manipulate individual bytes of the Frame Buffer a SRAM write access can be used instead.
For non IEEE 802.15.4 compliant frames, the minimum frame length supported by the radio transceiver is one byte
(Frame Length Field + one byte of data).
38.3.3 Interrupt Handling
Access conflicts may occur when reading and writing data simultaneously at the two independent ports of the Frame
Buffer, TX/RX BBP and SPI. These ports have their own address counter that points to the Frame Buffer’s current
address.
Access violations may cause data corruption and are indicated by IRQ_6 (TRX_UR) interrupt when using the Frame
Buffer access mode. Note that access violations are not indicated when using the SRAM access mode.
While receiving a frame, primarily the data needs to be stored in the AT86RF233 Frame Buffer before reading it. This can
be ensured by accessing the Frame Buffer 32µs after IRQ_2 (RX_START) at the earliest. When reading the frame data
continuously the SPI data rate shall be lower than 250kb/s to ensure no under run interrupt occurs. To avoid access
conflicts and to simplify the Frame Buffer read access Frame Buffer Empty indication may be used, for details refer to
“Frame Buffer Empty Indicator” on page 1030.
During transmission, an access violation occurs on Frame Buffer write access, when the SPI port’s address counter
value becomes less than or equal to that of TX BBP port.
Both these access violations may cause data corruption and are indicated by IRQ_6 (TRX_UR) interrupt when using the
Frame Buffer access mode. Access violations are not indicated when using the SRAM access mode.
Notes: 1. Interrupt IRQ_6 (TRX_UR) is valid 64µs after IRQ_2 (RX_START). The occurrence of the interrupt can be
disregarded when reading the first byte of the Frame Buffer between 32µs and 64µs after the RX_START
interrupt.
2. If a Frame Buffer read access is not finished until a new frame is received, an IRQ_6 (TRX_UR) interrupt
occurs. Nevertheless the old frame data can be read, if the SPI data rate is higher than the effective PHY
data rate. A minimum SPI clock rate of 1MHz is recommended in this case. Finally, the microcontroller
should check the integrity of the transferred frame data by calculating the FCS.
3. When writing data to the Frame Buffer during frame transmission, the SPI data rate shall be higher than the
PHY data rate to ensure no under run interrupt. The first byte of the PSDU data must be available in the
Frame Buffer before SFD transmission is complete, which takes 176µs (16µs PA ramp-up + 160µs SHR)
from the rising edge of SLP_TR (see Figure 36-2).
38.4 Voltage Regulators (AVREG, DVREG)
The main features of the Voltage Regulator blocks are:
zBandgap stabilized 1.8V supply for analog and digital domain
zLow dropout (LDO) voltage regulator
zAVREG/DVREG can be disabled when an external regulated voltage is supplied to AVDD/DVDD pin
38.4.1 Overview
The internal voltage regulators supply a stabilized voltage to the AT86RF233. The AVREG provides the regulated 1.8V
supply voltage for the analog section and the DVREG supplies the 1.8V supply voltage for the digital section.
A simplified schematic of the internal voltage regulator is shown in Figure 38-5.
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Figure 38-5. Simplified Schematic of AVREG
A simplified schematic of the internal digital voltage regulator is shown in Figure 38-6.
Figure 38-6. Simplified Schematic of DVREG
The block “Low power voltage regulator” within the “Digital voltage regulator” maintains the DVDD supply voltage at 1.5V
(typical) when the AT86RF233 voltage regulator is disabled in sleep mode. All configuration register values are stored.
The low power voltage regulator is always enabled. Therefore, its bias current contributes to the leakage current in sleep
mode with about 100nA (typical).
The voltage regulators (AVREG, DVREG) require bypass capacitors for stable operation. The value of the bypass
capacitors determine the settling time of the voltage regulators. The bypass capacitors shall be placed as close as
possible to the pins and shall be connected to ground with the shortest possible traces (see Table 34-1 on page 880).
38.4.2 Configuration
The voltage regulators can be configured by the register 0x10 (VREG_CTRL).
It is recommended to use the internal regulators, but it is also possible to supply the low voltage domains by an external
voltage supply. For this configuration, the internal regulators need to be switched off by setting the register bits to the
values AVREG_EXT = 1 and DVREG_EXT = 1. A regulated external supply voltage of 1.8V needs to be connected to
the DVDD and AVDD pins. When providing the external supply, ensure a sufficiently long stabilization time before
interacting with the AT86RF233.
Bandgap
voltage
reference
1.25 V
AVDD
EVDD
Bandgap
voltage
reference
1. 25 V
DVDD
DEVDD
BIAS
Voltage regulator
Low power voltage regulator
Digital voltage regulator
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38.4.3 Data Interpretation
The status bits AVDD_OK = 1 and DVDD_OK = 1 in register 0x10 (VREG_CTRL) indicate an enabled and stable internal
supply voltage. Reading value zero indicates a disabled or internal supply voltage not settled to the final value. Setting
AVREG_EXT = 1 and DVREG_EXT = 1 forces the signals AVDD_OK and DVDD_OK to one.
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38.4.4 Register Description
38.4.4.1 VREG_CTRL
Name: VREG_CTRL
Offset: 0x10
Reset: 0x00
Property: -
The VREG_CTRL register controls the use of the voltage regulators and indicates the status of these.
zBit 7 - AVREG_EXT
If set this register bit disables the internal analog voltage regulator to apply an external regulated 1.8V supply for
the analog building blocks.
zBit 6 - AVDD_OK
This register bit indicates if the internal 1.8V regulated voltage supply AVDD has settled. The bit is set to logic high,
if AVREG_EXT = 1.
zBit 3 - DVREG_EXT
If set this register bit disables the internal digital voltage regulator to apply an external regulated 1.8V supply for
the digital building blocks.
zBit 2 - DVDD_OK
This register bit indicates if the internal 1.8V regulated voltage supply DVDD has settled. The bit is set to logic
high, if DVREG_EXT = 1.
Bit 7 6 5 4 3 2 1 0
0x10 AVREG_EXT AVDD_OK DVREG_EXT DVDD_OK
Access R/W R R R R/W R R R
Reset 0 0 0 0 0 0 0 0
Table 38-11. AVREG_EXT
Value Description
0x0 Internal voltage regulator enabled, analog section
0x1 Internal voltage regulator disabled, use external regulated 1.8V supply voltage for the analog section
Table 38-12. AVDD_OK
Value Description
0x0 Analog voltage regulator is disabled or supply voltage not stable
0x1 Analog supply voltage is stable
Table 38-13. DVREG_EXT
Value Description
0x0 Internal voltage regulator enabled, digital section
0x1 Internal voltage regulator disabled, use external regulated 1.8V supply voltage for the digital section
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38.5 Battery Monitor (BATMON)
The main features of the battery monitor are:
zConfigurable voltage reference threshold from 1.70V to 3.675V
zInterrupt on low - supply voltage condition
zContinuous BATMON status monitor as a register flag
38.5.1 Overview
The AT86RF233 battery monitor (BATMON) detects and flags a low external supply voltage level provided on EVDD.
The external voltage supply EVDD is continuously compared with the internal threshold voltage to detect a low voltage
supply level. In this case BATMON_IRQ is triggered and BATMON_OK flag is cleared to indicate undervoltage condition,
see Figure 38-7.
Figure 38-7. Simplified Schematic of BATMON
38.5.2 Configuration
The BATMON can be configured using the register 0x11 (BATMON). Register bits BATMON_VTH sets the threshold
voltage. It is configurable with a resolution of 75mV in the upper voltage range (BATMON_HR = 1) and with a resolution
of 50mV in the lower voltage range (BATMON_HR = 0), for details refer to register 0x11 (BATMON).
38.5.3 Data Interpretation
The signal register bit BATMON_OK of register 0x11 (BATMON) monitors the current value of the battery voltage:
zIf BATMON_OK = 0, the battery voltage is lower than the threshold voltage
zIf BATMON_OK = 1, the battery voltage is higher than the threshold voltage
After setting a new threshold, the value BATMON_OK should be read out to verify the current supply voltage value.
Note: The battery monitor is inactive during P_ON, SLEEP, and DEEP_SLEEP states, see register bits TRX_STATUS
(register 0x01, TRX_STATUS).
Table 38-14. DVDD_OK
Value Description
0x0 Digital voltage regulator is disabled or supply voltage not stable
0x1 Digital supply voltage is stable
Note: 1. While the reset value of this bit is zero, any practical access to the register is only possible when DVREG
is active. So this bit is normally always read out as one.
BATMON_HR
BATMON_VTH
4
EVDD
Threshold
Voltage
BATMON_OK
„1“
BATMON_IRQ
For input-to-output mapping
see control register
0x11 (BATMON)
DAC
+
-
D
Q
clear
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38.5.4 Interrupt Handling
A supply voltage drop below the configured threshold value is indicated by an interrupt IRQ_7 (BAT_LOW), see “Interrupt
Logic” on page 896.
Note: The AT86RF233 IRQ_7 (BAT_LOW) interrupt is issued only if BATMON_OK changes from one to zero.
IRQ_7 (BAT_LOW) interrupt is not generated under following conditions:
zThe battery voltage remained below 1.8V threshold value on power-on (BATMON_OK was never one), or
zA new threshold is set, which is still above the current supply voltage (BATMON_OK remains zero).
When the battery voltage is close to the programmed threshold voltage, noise or temporary voltage drops may generate
unwanted interrupts. To avoid this:
zDisable the IRQ_7 (BAT_LOW) in register 0x0E (IRQ_MASK) and treat the battery as empty, or
zSet a lower threshold value.
38.5.5 Register Description
38.5.5.1 BATMON
Name: BATMON
Offset: 0x11
Reset: 0x02
Property: -
The BATMON register configures the battery monitor to compare the supply voltage at EVDD to the threshold.
Additionally, the supply voltage status at EVDD can be read from register bit BATMON_OK according to the actual
BATMON settings.
zBit 5 - BATMON_OK
The register bit BATMON_OK indicates the level of the external supply voltage with respect to the programmed
threshold BATMON_VTH.
zBit 4 - BATMON_HR
The register bit BATMON_HR sets the range and resolution of the battery monitor.
Bit 7 6 5 4 3210
0x11 BATMON_OK BATMON_HR BATMON_VTH
Access R R/W R R/W R/W R/W R/W R/W
Reset 0 0 0 0 0010
Table 38-15. BATMON_OK
Value Description
0x0 The battery voltage is below the threshold
0x1 The battery voltage is above the threshold
Table 38-16. BATMON_HR
Value Description
0x0 Enables the low range, see BATMON_VTH
0x1 Enables the high range, see BATMON_VTH
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zBit 3:0 – BATMON_VTH
The voltage threshold values for the battery monitor are set by register bits BATMON_VTH.
38.6 Crystal Oscillator (XOSCRF)
The main crystal oscillator features are:
z16MHz amplitude controlled crystal oscillator
z180µs typical settling time after leaving SLEEP state
z330µs typical settling time after leaving DEEP_SLEEP state
zConfigurable trimming capacitance array
zConfigurable clock output (CLKM)
38.6.1 Overview
The crystal oscillator generates the reference frequency for the AT86RF233. All other internally generated frequencies of
the radio transceiver are derived from this unique frequency. Therefore, the overall system performance is mainly
determined by the accuracy of crystal reference frequency. The external components of the crystal oscillator should be
selected carefully and the related board layout should be done with caution (see “Application Schematic” on page 879).
The register 0x12 (XOSC_CTRL) provides access to the control signals of the oscillator. Two operating modes are
supported. It is recommended to use the integrated oscillator setup as described in Figure 38-8. Alternatively, a
reference frequency can be fed to the internal circuitry by using an external clock reference as shown in Figure 38-9.
Table 38-17. BATMON_VTH
Value
BATMON_VTH
Voltage [V]
BATMON_HR = 1
Voltage [V]
BATMON_HR = 0
0x0 2.550 1.70
0x1 2.625 1.75
0x2 2.700 1.80
0x3 2.775 1.85
0x4 2.850 1.90
0x5 2.925 1.95
0x6 3.000 2.00
0x7 3.075 2.05
0x8 3.150 2.10
0x9 3.225 2.15
0xA 3.300 2.20
0xB 3.375 2.25
0xC 3.450 2.30
0xD 3.525 2.35
0xE 3.600 2.40
0xF 3.675 2.45
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38.6.2 Integrated Oscillator Setup
Using the internal oscillator, the oscillation frequency depends on the load capacitance between the crystal XTAL1 pin
and XTAL2 pin. The total load capacitance CL must be equal to the specified load capacitance of the crystal itself. It
consists of the external capacitors CX and parasitic capacitances connected to the XTAL nodes.
Figure 38-8 shows all parasitic capacitances, such as PCB stray capacitances and the pin input capacitance,
summarized to CPAR.
Figure 38-8. Simplified XOSCRF Schematic with External Components
Additional internal trimming capacitors CTRIM are available. Any value in the range from 0pF to 4.5pF with a 0.3pF
resolution is selectable using XTAL_TRIM of register 0x12 (XOSC_CTRL). To calculate the total load capacitance, the
following formula can be used:
CL[pF] = 0.5 x (CX[pF] + CTRIM[pF] + CPAR[pF])
The AT86RF233 trimming capacitors provide the possibility of reducing frequency deviations caused by production
process variations or by external components tolerances. Note that the oscillation frequency can only be reduced by
increasing the trimming capacitance. The frequency deviation caused by one step of CTRIM decreases with increasing
crystal load capacitor values.
An amplitude control circuit is included to ensure stable operation under different operating conditions and for different
crystal types. Enabling the crystal oscillator in P_ON state and after leaving SLEEP or DEEP_SLEEP state causes a
slightly higher current during the amplitude build-up phase to guarantee a short start-up time. At stable operation, the
current is reduced to the amount necessary for a robust operation. This also keeps the drive level of the crystal low.
Generally, crystals with a higher load capacitance are less sensitive to parasitic pulling effects caused by external
component variations or by variations of board and circuit parasitic. On the other hand, a larger crystal load capacitance
results in a longer start-up time and a higher steady state current consumption.
38.6.3 External Reference Frequency Setup
When using an external reference frequency, the signal must be connected to the XTAL1 pin as indicated in Figure 38-9
and the register bits XTAL_MODE (register 0x12, XOSC_CTRL) need to be set to the external oscillator mode for power
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saving reasons. The oscillation peak-to-peak amplitude shall be between 400mV and 1V. The XTAL2 pin should not be
wired. It is possible, among other waveforms, to use sine and square wave signals.
Note: The quality of the external reference (that is phase noise) determines the system performance.
Figure 38-9. Setup for Using an External Frequency Reference
38.6.4 Master Clock Signal Output (CLKM)
The generated reference clock signal can be fed to the microcontroller using CLKM. The internal 16MHz raw clock can
be divided by an internal prescaler. Thus, clock frequencies of 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 250kHz, or 62.5kHz
can be supplied by CLKM.
The CLKM frequency is configurable using register 0x03 (TRX_CTRL_0). There are two possibilities to change the
CLKM frequency. If CLKM_SHA_SEL = 0, changing the register bits CLKM_CTRL (register 0x03, TRX_CTRL_0)
immediately affects a glitch free the CLKM clock rate change. Otherwise (CLKM_SHA_SEL = 1 and CLKM_CTRL > 0
before changing the register bits CLKM_CTRL), the new clock rate is supplied when leaving the SLEEP state the next
time.
To reduced power consumption and spurious emissions, it is recommended to turn off the Atmel AT86RF233 CLKM
clock when not in use.
Notes: 1. During reset procedure, see “RESET State” on page 906, register bits CLKM_CTRL are shadowed.
Although the clock setting of CLKM remains after reset, a read access to register bits CLKM_CTRL delivers
the reset value one. For that reason it is recommended to write the previous configuration (before reset) to
register bits CLKM_CTRL (after reset) to align the radio transceiver behavior and register configuration.
Otherwise the CLKM clock rate is set back to the reset value (1MHz) after the next SLEEP cycle.
For example, if the CLKM clock rate is configured to 16MHz the CLKM clock rate remains at 16MHz after a
reset, however the register bits CLKM_CTRL are set back to one. Since CLKM_SHA_SEL reset value is
one, the CLKM clock rate changes to 1MHz after the next SLEEP cycle if the CLKM_CTRL setting is not
updated.
2. After leaving the DEEP_SLEEP state CLKM starts with the default 1MHz master clock at CLKM after the
crystal oscillator has stabilized.
SAM R21
PCB
XTAL2XTAL1
16MHz
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38.6.5 Register Description
38.6.5.1 TRX_CTRL_0
Name: TRX_CTRL_0
Offset: 0x03
Reset: 0x09
Property: -
The TRX_CTRL_0 register controls the CLKM clock rate.
zBit 3 - CLKM_SHA_SEL
The register bit CLKM_SHA_SEL defines whether a new clock rate (defined by CLKM_CTRL) is set immediately
or gets effective after the next SLEEP cycle.
zBit 2:0 - CLKM_CTRL
The register bits CLKM_CTRL set the clock rate of CLKM.
Bit 765 4 3210
0x03 TOM_EN PMU_EN PMU_IF_INVERSE CLKM_SHA_SEL CLKM_CTRL
Access R/W R R/W R/W R/W R/W R/W R/W
Reset 000 0 1001
Table 38-18. CLKM_SHA_SEL
Value Description
0x0 CLKM clock rate change appears immediately
0x1 CLKM clock rate change appears after SLEEP cycle
Table 38-19. CLKM_CTRL
Value Description
0x0 No clock at CLKM, signal set to logic low
0x1 1MHz
0x2 2MHz
0x3 4MHz
0x4 8MHz
0x5 16MHz
0x6 250kHz
0x7 62.5kHz (IEEE 802.15.4 symbol rate)
Note: 1. If a clock rate is selected between 1MHz and 16MHz and SLP_TR is set to logic high in state TRX_OFF, the
TRX delivers additional 35 clock cycles before entering state SLEEP or DEEP_SLEEP.
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38.6.5.2 XOSC_CTRL
Name: XOSC_CTRL
Offset: 0x12
Reset: 0x0F
Property: -
The XOSC_CTRL register controls the operation of the crystal oscillator.
zBit 7:4 - XTAL_MODE
The register bits XTAL_MODE sets the operating mode of the crystal oscillator.
For normal operation the default value is set to XTAL_MODE = 0xF after reset. Using an external clock source it is
recommended to set XTAL_MODE = 0x5.
zBit 3:0 - XTAL_TRIM
The register bits XTAL_TRIM control internal capacitance arrays connected to the XTAL1 and XTAL2 pins.
38.7 Frequency Synthesizer (PLL)
The main PLL features are:
zGenerate RX/TX frequencies for all IEEE 802.15.4 – 2.4GHz channels
zGenerate RX/TX frequencies from 2360MHz to 2480MHz
zAutonomous calibration loops for stable operation within the operating range
zTwo PLL-interrupts for status indication
zFast PLL settling to support frequency hopping
38.7.1 Overview
The PLL generates the RF frequencies for the AT86RF233. During receive operation the frequency synthesizer works as
a local oscillator on the radio transceiver receive frequency, during transmit operation the voltage-controlled oscillator
(VCO) is directly modulated to generate the RF transmit signal. The frequency synthesizer is implemented as a
fractional-N PLL.
Bit 76543210
0x12 XTAL_MODE XTAL_TRIM
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 11110000
Table 38-20. XTAL_MODE
Value Description
0x5 Internal crystal oscillator disabled, use external reference frequency
0xF Internal crystal oscillator enabled and XOSCRF voltage regulator enabled
All other values are reserved
Table 38-21. XTAL_TRIM
Value Description
0x0 A capacitance value in the range from 0pF to 4.5pF is selectable with a resolution of 0.3pF.
Valid values are [0xF, 0xE, …, 0x0].
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Two calibration loops ensure correct PLL functionality within the specified operating limits.
38.7.2 RF Channel Selection
The PLL is designed to support 16 channels in the 2.4GHz ISM band with channel spacing of 5MHz according to
IEEE 802.15.4. The center frequency of these channels is defined as follows:
Fc[MHz] = 2405[MHz] + 5[MHz] x (k – 11), for k = 11, 12, ..., 26
where k is the channel number.
The channel k is selected by register bits CHANNEL (register 0x08, PHY_CC_CA).
Additionally, the PLL supports all frequencies from 2360MHz to 2480MHz with 500kHz frequency spacing. The
frequency is selected by register bits CC_BAND (registers 0x14, CC_CTRL_1) and register bits CC_NUMBER
(registers 0x13, CC_CTRL_0).
Table 38-22 shows the settings of the register bits CC_BAND and CC_NUMBER.
38.7.3 PLL Settling Time and Frequency Agility
When the PLL is enabled during state transition from TRX_OFF to PLL_ ON or RX_ON, the settling time is typically
tTR4 = 80µs, including settling of the analog voltage regulator (AVREG) and PLL self calibration, refer to Table 36-2 on
page 912. A lock of the PLL is indicated with an interrupt IRQ_0 (PLL_LOCK).
Switching between 2.4GHz ISM band channels in PLL_ON or RX_ON states is typically done within tPLL_SW = 11µs. This
makes the radio transceiver highly suitable for frequency hopping applications.
The PLL frequency in PLL_ON and receive states is 2MHz below the PLL frequency in transmit states. When starting the
transmit procedure, the PLL frequency is changed to the transmit frequency within a period of tRX_TX = 16µs before really
starting the transmission. After the transmission, the PLL settles back to the receive frequency within a period of
tTX_RX = 32µs. This frequency step does not generate an interrupt IRQ_0 (PLL_LOCK) or IRQ_1 (PLL_UNLOCK) within
these periods.
38.7.4 Calibration Loops
Due to variation of temperature, supply voltage and part-to-part variations of the radio transceiver the VCO
characteristics may vary.
To ensure a stable operation, two automated control loops are implemented, center frequency (CF) tuning and delay cell
(DCU) calibration. Both calibration loops are initiated automatically when the PLL is enabled during state transition from
Table 38-22. Frequency Bands and Numbers
CC_BAND CC_NUMBER Description
0x0 Not used Channels according to IEEE 802.15.4; frequency selected by register bits CHANNEL
(register 0x08, PHY_CC_CCA)
0x1, …, 0x7 0x00 – 0xFF Reserved
0x8 0x00 – 0x6B Reserved
0x8 0x6C – 0xFF 2360MHz – 2433.5MHz
Fc[MHz] = 2306[MHz] + 0.5[MHz] x CC_NUMBER
0x9 0x00 – 0x5C 2434MHz – 2480MHz.
Fc[MHz] = 2434[MHz] + 0.5[MHz] x CC_NUMBER
0x9 0x5D – 0xFF Reserved
0xA, …, 0xF 0x00 – 0xFF Reserved
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TRX_OFF to PLL_ON or RX_ON state. Additionally, both calibration loops are initiated when the PLL changes to a
different frequency setting.
If the PLL operates for a long time on the same channel, for example more than five minutes, or the operating
temperature changes significantly, it is recommended to initiate the calibration loops manually.
Both AT86RF233 calibration loops can be initiated manually by SPI command. To start the calibration, the device should
be in state PLL_ON. The center frequency calibration can be initiated by setting PLL_CF_START = 1 (register 0x1A,
PLL_CF). The calibration loop is completed when the IRQ_0 (PLL_LOCK) occurs, if enabled. The duration of the center
frequency calibration loop depends on the difference between the current CF value and the final CF value. During the
calibration, the CF value is incremented or decremented. Each step takes tPLL_CF = 8µs. The minimum time is 8µs; the
maximum time is 24µs. The recommended procedure to start the center frequency calibration is to read the register 0x1A
(PLL_CF), to set the PLL_CF_START register bit to one, and to write the value back to the register.
The delay cell calibration can be initiated by setting the bit PLL_DCU_START of register 0x1B (PLL_DCU) to one. The
delay time of the programmable delay unit is adjusted to the correct value. The calibration works as successive
approximation and is independent of the values in the register 0x1B (PLL_DCU). The duration of the calibration is
tPLL_DCU =6µs.
During both calibration processes, no correct receive or transmit operation is possible. The recommended state for the
calibration is therefore PLL_ON, but calibration is not blocked at receive or transmit states.
Both calibrations can be executed concurrently.
38.7.5 Interrupt Handling
Two different interrupts indicate the PLL status (refer to register 0x0F). IRQ_0 (PLL_LOCK) indicates that the PLL has
locked. IRQ_1 (PLL_UNLOCK) interrupt indicates an unexpected unlock condition. A PLL_LOCK interrupt clears any
preceding PLL_UNLOCK interrupt automatically and vice versa.
An IRQ_0 (PLL_LOCK) interrupt is supposed to occur in the following situations:
zState change from TRX_OFF to PLL_ON / RX_ON / TX_ARET_ON / RX_AACK_ON
zFrequency setting change in states PLL_ON / RX_ON / TX_ARET_ON / RX_AACK_ON
zA manually started center frequency calibration has been completed
All other PLL_LOCK interrupt events indicate that the PLL locked again after a prior unlock happened.
An IRQ_1 (PLL_UNLOCK) interrupt occurs in the following situations:
zA manually initiated center frequency calibration in states PLL_ON / (RX_ON)
zFrequency setting change in states PLL_ON / RX_ON
Any other occurrences of IRQ_1 (PLL_UNLOCK) indicate erroneous behavior and require checking of the actual device
status.
PLL_LOCK and PLL_UNLOCK affect the behavior of the transceiver:
In states BUSY_TX and BUSY_TX_ARET the transmission is stopped and the transceiver returns into state PLL_ON.
During BUSY_RX and BUSY_RX_AACK, the transceiver returns to state RX_ON and RX_AACK_ON, respectively, once
the PLL has locked.
Notes: 1. An AT86RF233 interrupt IRQ_0 (PLL_LOCK) clears any preceding IRQ_1 (PLL_UNLOCK) interrupt auto-
matically and vice versa.
2. The state transition from BUSY_TX / BUSY_TX_ARET to PLL_ON / TX_ARET_ON after successful trans-
mission does not generate an IRQ_0 (PLL_LOCK) within the settling period.
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38.7.6 Register Description
38.7.6.1 PHY_CC_CCA
Name: PHY_CC_CCA
Offset: 0x08
Reset: 0x2B
Property: -
The PHY_CC_CCA register is a multi-purpose register that controls CCA configuration, CCA measurement, and the
IEEE 802.15.4 channel setting.
zBit 4:0 - CHANNEL
The register bits CHANNEL define the RX/TX channel. The channel assignment is according to IEEE 802.15.4.
Bit 7 6543210
0x08 CCA_REQUEST CCA_MODE CHANNEL
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0101011
Table 38-23. CHANNEL
Value Description
0x0B 2405MHz
0x0C 2410MHz
0x0D 2415MHz
0x0E 2420MHz
0x0F 2425MHz
0x10 2430MHz
0x11 2435MHz
0x12 2440MHz
0x13 2445MHz
0x14 2450MHz
0x15 2455MHz
0x16 2460MHz
0x17 2465MHz
0x18 2470MHz
0x19 2475MHz
0x1A 2480MHz
All other values are reserved
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38.7.6.2 CC_CTRL_0
Name: CC_CTRL_0
Offset: 0x13
Reset: 0x00
Property: -
The CC_CTRL_0 register controls the frequency selection, if the selection by CHANNEL (register 0x08, PHY_CC_CCA)
is not used.
zBit 7:0 - CC_NUMBER
38.7.6.3 CC_CTRL_1
Name: CC_CTRL_1
Offset: 0x14
Reset: 0x00
Property: -
The CC_CTRL_1 register controls the selection of the frequency bands.
zBit 3:0 - CC_BAND
The register bits CC_BAND control the selection for IEEE 802.15.4 channel band and additional frequencies
bands.
Bit 76543210
0x13 CC_NUMBER
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Table 38-24. CC_NUMBER
Value Description
0x00
Alternative frequency selection with 500kHz frequency spacing
CC_BAND = 0x0: Not used
CC_BAND = 0x8: Valid values are [0xFF, 0xFE, …, 0x6C]
CC_BAND = 0x9: Valid values are [0x5C, 0x5B, …, 0x00]
All other values are reserved
Bit 76543210
0x14 CC_BAND
Access R R R R R/W R/W R/W R/W
Reset 00000000
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If the register bits CC_BAND and CC_NUMBER are used, the frequency mapping is described in Table 38-22.
38.7.6.4 PLL_CF
Name: PLL_CF
Offset: 0x1A
Reset: 0x57
Property: -
The PLL_CF register controls the operation of the center frequency calibration loop.
zBit 7 - PLL_CF_START
Manual start of center frequency calibration cycle.
PLL_CF_START = 1 initiates the center frequency calibration. The calibration cycle has finished after tPLL_CF =8µs
(typ.). The register bit is cleared immediately after finishing the calibration.
Table 38-25. CC_BAND
Value Description
0x0 The IEEE 802.15.4 channel within register bits CHANNEL is selected
0x8 The frequency band 0x8 is selected
0x9 The frequency band 0x9 is selected
All other values are reserved
Bit 7 6 5 43210
0x1A PLL_CF_START PLL_CF
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 1 0 10111
Table 38-26. PLL_CF_START
Value Description
0x0 Center frequency calibration cycle is finished
0x1 Initiates center frequency calibration cycle
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38.7.6.5 PLL_DCU
Name: PLL_DCU
Offset: 0x1B
Reset: 0x20
Property: -
The PLL_DCU register controls the operation of the delay cell calibration loop.
zBit 7 - PLL_DCU_START
Manual start of delay cell calibration cycle.
PLL_DCU_START = 1 initiates the delay cell calibration. The calibration cycle has finished after tPLL_DCU =6µs.
The register bit is cleared immediately after finishing the calibration.
38.7.6.6 TST_SDM
Name: TST_SDM
Offset: 0x3D
Reset: 0x00
Property: -
Note: The register bits can be read or written, the values will effect the device operation only if the register bit PMU_EN
(register 0x03, TRX_CTRL_0) is set, otherwise reset values will be applied.
zBit 7 - MOD_SEL
The register bit MOD_SEL controls the modulation data source mode.
Bit 7 6543210
0x1B PLL_DCU_START
Access R/W R R/W R/W R/W R/W R/W R/W
Reset 0 0100000
Table 38-27. PLL_DCU_START
Value Description
0x0 Delay cell calibration cycle is finished
0x1 Initiates delay cell calibration cycle
Bit 7 6 5 4 3 2 1 0
0x3D MOD_SEL MOD TX_RX TX_RX_SEL
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Table 38-28. MOD_SEL
Value Description
0x0 Normal operation is selected
0x1 Manual control of modulation data source is selected. Used setting from register bit MOD.
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zBit 6 - MOD
The register bit MOD controls the manual modulation signal setting.
zBit 5 - TX_RX
The register bit TX_RX controls the TX and RX PLL frequency setting within manual control mode.
zBit 4 - TX_RX_SEL
The register bit TX_RX_SEL controls the PLL frequency control mode.
Table 38-29. MOD
Value Description
0x0 Continuous 0 chips
0x1 Continuous 1 chips
Table 38-30. TX_RX
Value Description
0x0 RX PLL frequency is selected
0x1 TX PLL frequency is selected
Table 38-31. TX_RX_SEL
Value Description
0x0 Normal operation is selected
0x1 Manual control of PLL TX/RX frequency mode is selected. Used setting from register bit TX_RX.
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38.8 Automatic Filter Tuning (FTN)
38.8.1 Overview
The AT86RF233 FTN is incorporated to compensate device tolerances for temperature, supply voltage variations as well
as part-to-part variations of the radio transceiver. The filter-tuning result is used to correct the analog baseband filter
transfer function and the PLL loop-filter time constant, refer to “General Circuit Description” on page 15.
An FTN calibration cycle is initiated automatically when entering the TRX_OFF state from the P_ON, SLEEP,
DEEP_SLEEP, or RESET state.
Although receiver and transmitter are very robust against these variations, it is recommended to initiate the FTN
manually if the radio transceiver does not use the SLEEP or DEEP_SLEEP states. If necessary, a calibration cycle is to
be initiated in states TRX_OFF, PLL_ON or RX_ON. This applies in particular for the High Data Rate Modes with a much
higher sensitivity against BPF transfer function variations. The recommended calibration interval is five minutes or less, if
the AT86RF233 operates always in an active state (PLL_ON, TX_ARET_ON, RX_ON, and RX_AACK_ON).
38.8.2 Register Description
38.8.2.1 FTN_CTRL
Name: FTN_CTRL
Offset: 0x18
Reset: 0x58
Property: -
The FTN_CTRL register controls the operation of the filter tuning network calibration loop.
zBit 7 - FTN_START
Manual start of a filter calibration cycle.
FTN_START = 1 initiates the filter tuning network calibration. When the calibration cycle has finished after tFTN = 25µs
(typ.). The register bit is cleared immediately after finishing the calibration.
zBit 5:0 - FTNV
Filter tuning value used for internal calibration loops.
Bit 7 6 543210
0x18 FTN_START FTNV
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 1 011000
Table 38-32. FTN_START
Value Description
0x0 Filter calibration is finished
0x1 Initiates filter calibration cycle
Table 38-33. FTNV
Value Description
0x18 Register bits FTNV defines the filter tuning value.
Valid values are [0x3F, 0x3E, …, 0x00].
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39. AT86RF233 Radio Transceiver Usage
39.1 Frame Receive Procedure
This section describes basic procedures to receive and transmit frames using the AT86RF233. For a detailed
programming description refer to reference [7].
A frame reception comprises of two actions: The transceiver listens for, receives, and demodulates the frame to the
Frame Buffer and signals the reception to the microcontroller. After or during that process, the microcontroller can read
the available frame data from the Frame Buffer via the SPI interface.
While being in state RX_ON or RX_AACK_ON, the radio transceiver searches for incoming frames on the selected
channel. Assuming the appropriate interrupts are enabled, the detection of a frame is indicated by interrupt IRQ_2
(RX_START). When the frame reception is completed, interrupt IRQ_3 (TRX_END) is issued.
Different Frame Buffer read access scenarios are recommended for:
Non-time critical applications read access starts after IRQ_3(TRX_END)
Time-critical applications read access starts after IRQ_2(RX_START)
For non-time-critical operations, it is recommended to wait for interrupt IRQ_3 (TRX_END) before starting a Frame Buffer
read access. Figure 39-1 illustrates the frame receive procedure using IRQ_3 (TRX_END).
Figure 39-1. Transactions between AT86RF233 and Microcontroller during Receive
Critical protocol timing could require starting the Frame Buffer read access after interrupt IRQ_2 (RX_START). The first
byte of the frame data can be read 32µs after the IRQ_2 (RX_START) interrupt. The microcontroller must ensure to read
slower than the frame is received. Otherwise a Frame Buffer under run occurs, IRQ_6 (TRX_UR) is issued, and the
frame data may be not valid. To avoid this, the Frame Buffer read access can be controlled by using a Frame Buffer
Empty indicator, refer to “Frame Buffer Empty Indicator” on page 1030.
39.2 Frame Transmit Procedure
A frame transmission comprises of two actions, a write to Frame Buffer and the transmission of its contents. Both actions
can be run in parallel if required by critical protocol timing.
Figure 39-2 illustrates the AT86RF233 frame transmit procedure, when writing and transmitting the frame consecutively.
After a Frame Buffer write access, the frame transmission is initiated by asserting the SLP_TR signal or writing command
TX_START to register bits TRX_CMD (register 0x02, TRX_STATE). The transceiver must be either in PLL_ON state for
basic operating mode or TX_ARET_ON state for extended operating mode. The completion of the transaction is
indicated by interrupt IRQ_3 (TRX_END).
AT86RF233
Microcontroller
IRQ issued (IRQ_2)
Read IRQ status, IRQ signal deasserted
IRQ issued (IRQ_3)
Read frame data (Frame Buffer access)
Read IRQ status, IRQ signal deasserted
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Figure 39-2. Transaction between AT86RF233 and Microcontroller during Transmit
Alternatively for time critical applications when the frame start transmission time needs to be minimized, a frame
transmission task can be started first. Then it can be followed by the Frame Buffer write access event (populating PSDU
data). This way the data to be transmitted is needs to be written in the transmit frame buffer as the transceiver initializes
and begins SHR transmission; refer to Figure 39-3.
By initiating a transmission, either by asserting the SLP_TR signal or writing a TX_START command to register bits
TRX_CMD (register 0x02, TRX_STATE), the radio transceiver starts transmitting the SHR, which is internally generated.
This first phase requires for PLL settling and 160µs for SHR transmission. The PHR must be available in the Frame
Buffer before this time elapses. Furthermore the SPI data rate must be higher than the PHY data rate selected by register
bits OQPSK_DATA_RATE (register 0x0C, TRX_CTRL_2) to ensure that no Frame Buffer under run occurs.
Figure 39-3. Time Optimized Frame Transmit Procedure.
AT86RF233
Microcontroller
Write frame data (Frame Buffer access)
Write TRX_CMD = TX_START, or assert SLP_TR signal
IRQ_3 (TRX_END) issued
Read IRQ_STATUS register, IRQ signal deasserted
IRQ_3 (TRX_END) issued
Write frame data (Frame Buffer access)
Write TRX_CMD = TX_START, or assert SLP_TR signal
AT86RF233
Microcontroller
Read IRQ_STATUS register, IRQ signal deasserted
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40. AT86RF233 Extended Feature Set
40.1 Security Module (AES)
The security module (AES) features include:
zHardware accelerated encryption and decryption
zCompatible with AES-128 standard (128-bit key and data block size)
zECB (encryption/decryption) mode and CBC (encryption) mode support
zStand-alone operation, independent of other blocks
40.1.1 Overview
The security module is based on an AES-128 core according to FIPS197 standard, refer to [6]. The security module
works independently of other building blocks of the AT86RF233. Encryption and decryption can be performed in parallel
with a frame transmission or reception.
The control of the security block is implemented as an SRAM access to address space 0x82 to 0x94. A Fast SRAM
access mode allows for simultaneous new data writes and reads of processed data within the same SPI transfer. This
access procedure is used to reduce the turnaround time for ECB and CBC modes, see “Data Transfer – Fast SRAM
Access” on page 1009.
In addition, the security module contains another 128-bit register to store the initial key used for security operations. This
initial key is not modified by the security module.
40.1.2 Security Module Preparation
The use of the security module requires a configuration of the security engine before starting a security operation. The
following steps are required:
Before starting any security operation, a key must be written to the security engine, refer to “Security Key Setup” on page
1006. The key set up requires the configuration of the AES engine KEY mode using register bits AES_MODE (SRAM
address 0x83, AES_CTRL).
The following step selects the AES mode, either electronic code book (ECB) or cipher block chaining (CBC). These
modes are explained in more detail in “Security Operation Modes” on page 1006. Further, encryption or decryption must
be selected with register bit AES_DIR (SRAM address 0x83, AES_CTRL).
After this, the 128-bit plain text or cipher text data has to be provided to the AES hardware engine. The data uses the
SRAM address range 0x84 – 0x93.
Table 40-1. AES Engine Configuration Steps
Step Description Section
1Key Setup Write encryption or decryption key to SRAM “Security Key Setup” on page 1006
2AES mode Select AES mode: ECB or CBC
Select encryption or decryption
“Electronic Code Book (ECB)” on page
1006
“Cipher Block Chaining (CBC)” on page
1008
3Write Data Write plaintext or cipher text to SRAM “Data Transfer – Fast SRAM Access” on
page 1009
4Start operation Start AES operation
5Read Data Read cipher text or plaintext from SRAM “Data Transfer – Fast SRAM Access” on
page 1009
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An encryption or decryption is initiated with register bit AES_REQUEST = 1 (SRAM address 0x83, that is AES_CTRL, or
the mirrored version SRAM address 0x94, that is AES_CTRL_MIRROR).
The AES module control registers are only accessible using SRAM read and write accesses on address space 0x82 to
0x94. Configuring the AES mode, providing the data, and starting a decryption or encryption operation can be combined
in a single SRAM access.
40.1.3 Security Key Setup
The setup of the key is prepared by setting register bits AES_MODE = 1 (SRAM address 0x83, AES_CTRL). Afterwards
the 128-bit key must be written to SRAM addresses 0x84 through 0x93 (registers AES_KEY). It is recommended to
combine the setting of control register 0x83 (AES_CTRL) and the 128-bit key transfer using only one SRAM access
starting from address 0x83.
The address space for the 128-bit key and 128-bit data is identical from programming point of view. However, both use
different pages which are selected by register bit AES_MODE before storing the data.
A read access to registers AES_KEY (0x84 – 0x93) returns the last round key of the preceding security operation. After
an ECB encryption operation, this is the key that is required for the corresponding ECB decryption operation. However,
the initial AES key, written to the security module in advance of an AES run, see step one in
Table 40-1 on page 1005, is not modified during the AES operation. This initial key is used for the next AES run even it
cannot be read from AES_KEY.
40.1.4 Security Operation Modes
40.1.4.1 Electronic Code Book (ECB)
ECB is the basic operating mode of the security module. After setting up the initial AES key, register bits AES_MODE = 0
(SRAM address 0x83, AES_CTRL) sets up ECB mode. Register bit AES_DIR (SRAM address 0x83, AES_CTRL)
selects the direction, either encryption or decryption. The data to be processed has to be written to SRAM addresses
0x84 through 0x93 (registers AES_STATE).
An example for a programming sequence is shown in Figure 40-1. This example assumes a suitable key has been
loaded before.
A security operation can be started within one SRAM access by appending the start command AES_REQUEST = 1
(register 0x94, AES_CTRL_MIRROR) to the SPI sequence. Register AES_CTRL_MIRROR is a mirrored version of
register 0x83 (AES_CTRL).
Notes: 1. No additional register access is required to operate the security block.
2. Access to the security block is not possible while the radio transceiver is in SLEEP, DEEP_SLEEP, or
RESET state.
3. All configurations of the security module, the SRAM content, and keys are reset during DEEP_SLEEP or
RESET state.
4. A read or write access to register 0x83 (AES_CTRL) during AES operation terminates the current
processing.
Note: 1. ECB decryption is not required for IEEE 802.15.4 or ZigBee security processing. The AT86RF233 provides
this functionality as an additional feature.
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Figure 40-1. ECB Programming SPI Sequence – Encryption
Summarizing, the following steps are required to perform a security operation using only one Atmel AT86RF233 SPI
access:
1. Configure SPI access:
1. SRAM write, refer to “SRAM Access Mode” on page 888
2. Start address 0x83
2. Configure AES operation:
1. address 0x83: select ECB mode, direction
3. Write 128-bit data block:
1. addresses 0x84 – 0x93: either plain or ciphertext
4. Start AES operation:
1. address 0x94: start AES operation, ECB mode
This sequence is recommended because the security operation is configured and started within one SPI transaction.
The ECB encryption operation is illustrated in Figure 40-2. Figure 40-3 shows the ECB decryption mode, which is
supported in a similar way.
Figure 40-2. ECB Mode – Encryption
0 0 0 0 0 0 0 01 0 0 0 0 0 1 10 1 0 0 0 0 0 0
byte 1 (address)byte 0 (cmd.) byte 18
…. 1 0 0 0 0 0 0 0data_15[7:0]
byte 19 (AES cmd)byte 2 (AES cmd)
data_0[7:0]
byte 3
ECB, encryption0x83SRAM write AES start
Block Cipher
Encryption
Encryption
Key
Plaintext
Ciphertext
Block Cipher
Encryption
Encryption
Key
Plaintext
Ciphertext
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Figure 40-3. ECB Mode – Decryption
When decrypting, due to the nature of AES algorithm, the initial key to be used is not the same as the one used for
encryption, but rather the last round key instead. This last round key is the content of the key address space stored after
running one full encryption cycle, and must be saved for decryption. If the decryption key has not been saved, it has to be
recomputed by first running a dummy encryption (of an arbitrary plaintext) using the original encryption key, then fetching
the resulting round key from the key memory, and writing it back into the key memory as the decryption key.
ECB decryption is not used by either IEEE 802.15.4 or ZigBee frame security. Both of these standards do not directly
encrypt the payload, but rather a nonce instead, and protect the payload by applying an XOR operation between the
resulting (AES-) cipher text and the original payload. As the nonce is the same for encryption and decryption only ECB
encryption is required. Decryption is performed by XORing the received cipher text with its own encryption result
respectively, which results in the original plaintext payload upon success.
40.1.4.2 Cipher Block Chaining (CBC)
In CBC mode, the result of a previous AES operation is XORed with the new incoming vector, forming the new plaintext
to encrypt, see Figure 40-4. This mode is used for the computation of a cryptographic checksum (message integrity
code, MIC).
Figure 40-4. CBC Mode – Encryption
After preparing the AES key and defining the AES operation direction using Atmel AT86RF233 SRAM register bit
AES_DIR, the data has to be provided to the AES engine and the CBC operation can be started.
The first CBC run has to be configured as ECB to process the initial data (plaintext XORed with an initialization vector
provided by the microcontroller). All succeeding AES runs are to be configured as CBC by setting register bits
AES_MODE = 2 (register 0x83, AES_CTRL). Register bit AES_DIR (register 0x83, AES_CTRL) must be set to
Block Cipher
Decryption
Decryption
Key
Plaintext
Ciphertext
Block Cipher
Decryption
Decryption
Key
Plaintext
Ciphertext
Block Cipher
Encryption
Encryption
Key
Ciphertext
Block Cipher
Encryption
Plaintext
Ciphertext
Plaintext Initialization Vector (IV)
Encryption
Key
ECB
mode
CBC
mode
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AES_DIR = 0 to enable AES encryption. The data to be processed has to be transferred to the SRAM starting with
address 0x84 to 0x93 (register AES_STATE). Setting register bit AES_REQUEST = 1 (register 0x94,
AES_CTRL_MIRROR) as described in “Security Operation Modes” on page 1006 starts the first encryption within one
SRAM access. This causes the next 128 bits of plaintext data to be XORed with the previous cipher text data, see Figure
40-4.
According to IEEE 802.15.4 the input for the very first CBC operation has to be prepared by a XORing a plaintext with an
initialization vector (IV). The value of the initialization vector is zero. However, for non-compliant usage any other
initialization vector can be used. This operation has to be prepared by the microcontroller.
40.1.5 Data Transfer – Fast SRAM Access
The ECB and CBC modules including the AES core are clocked with 16MHz. One AES operation takes tAES = 23.4µs to
execute, refer to Table 36-2 on page 912. That means that the processing of the data is usually faster than the transfer of
the data via the SPI interface.
To reduce the overall processing time the AT86RF233 provides a Fast SRAM access for the address space 0x82 to
0x94.
Figure 40-5. Packet Structure – Fast SRAM Access Mode
In contrast to a standard SRAM access, refer to “SRAM Access Mode” on page 888, the Fast SRAM access allows
writing and reading of data simultaneously during one SPI access for consecutive AES operations (AES run).
For each byte P0 transferred to MOSI for example in “AES access #1”, see Figure 40-5 (lower part), the previous content
of the respective AES register C0 is clocked out at MISO with an offset of one byte.
In the example shown in Figure 40-5 the initial plaintext P0 –P15 is written to the SRAM within “AES access #0”. The last
command on address 0x94 (AES_CTRL_MIRROR) starts the AES operation (“AES run #0”). In the next “AES
access #1” new plaintext data P0 – P15 is written to the SRAM for the second AES run, in parallel the ciphertext
C0 –C15 from the first AES run is clocked out at MISO. To read the ciphertext from the last “AES run #(n)” one dummy
“AES access #(n+1)” is needed.
The Fast SRAM access automatically applies to all write operations to SRAM addresses 0x82 to 0x94.
Note: 1. The IEEE 802.15.4-2006 standard MIC algorithm requires CBC mode encryption only, as it implements a one-
way hash function.
Note: 1. Byte 19 is the mirrored version of register AES_CTRL on SRAM address 0x94, see register description
AES_CTRL_MIRROR for details.
Note: 2. The SRAM write access always overwrites the previous processing result.
SRAM writeMOSI
PHY_STATUSMISO
byte 0 (cmd)
address 0x83
XX
<AES_CTRL>
XX
byte 1 (addr.) byte 2 (cfg)
P0[7:0]
XX
byte 3 byte 4 byte 18
<AES_CTRL>(1)
byte 19 (start)
0x83 0x850x84 0x93 0x94Address
MOSI
MISO
AES access #0
Address
P0 P15...cmd add cfg start
xx xx...stat xx xx xx
0x83 0x94...
AES access #1
P0 P15...cmd add cfg start
xx C14...stat xx xx C15
0x83 0x94...
AES access #n+1
xx xx...cmd add cfg start
xx C14...stat xx xx C15
0x83 0x94...
P1 P14
xx xx
P1 P14
C0 C13
xx xx
C0 C13
...
...C0[7:0]
P1[7:0]
C14[7:0] C15[7:0]
P15[7:0]
AES run #0 AES run #n
...
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40.1.6 Start of Security Operation and Status
A security operation is started within one AT86RF233 SRAM access by appending the start command
AES_REQUEST = 1 (register 0x94, AES_CTRL_MIRROR) to the SPI sequence. Register AES_CTRL_MIRROR is a
mirrored version of register 0x83 (AES_CTRL).
The status of the security processing is indicated by register 0x82 (AES_STATUS). After tAES = 24µs (max.) AES
processing time register bit AES_DONE changes to one (register 0x82, AES_STATUS) indicating that the security
operation has finished.
40.1.7 SRAM Register Summary
The following registers are required to control the security module:
These registers are only accessible using SRAM write and read accesses, for details refer to “SRAM Access Mode” on
page 888.
Note: 1. The AES registers are reset when entering the DEEP_SLEEP state.
40.1.8 SRAM Register Description
40.1.8.1 AES_STATUS
Name: AES_STATUS
Offset: 0x82
Reset: 0x00
Property: -
The read-only register AES_STATUS signals the status of the security module and operation.
zBit 7 – AES_ER
This SRAM register bit indicates an error of the AES module. An error may occur for instance after an access to
SRAM register 0x83 (AES_CTRL) while an AES operation is running or after reading less than 128-bits from
SRAM register space 0x84 – 0x93 (AES_STATE).
Table 40-2. SRAM Security Module Address Space Overview
ARAM Addr Register Name Description
0x80 – 0x81 Reserved
0x82 AES_STATUS AES status
0x83 AES_CTRL Security module control, AES mode
0x84 – 0x93 AES_KEY
AES_STATE
Depends on AES_MODE setting:
AES_MODE = 1:
- Contains AES_KEY (key)
AES_MODE = 0 or 2:
- Contains AES_STATE (128 bit data block)
0x94 AES_CTRL_MIRROR Mirror of register 0x83 (AES_CTRL)
0x95 – 0xFF Reserved
Bit 76543210
0x82 AES_ER AES_DONE
AccessRRRRRRRR
Reset 00000000
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zBit 0 – AES_DONE: AES Done
The bit AES_DONE signals the status of AES operation.
40.1.8.2 AES_CTRL
Name: AES_CTRL
Offset: 0x83
Reset: 0x00
Property: -
The AES_CTRL register controls the operation of the security module.
Notes: 1. Do not access this register during AES operation to read the AES core status. A read or write access during
AES operation stops the actual processing.
2. To read the AES status use register bit AES_DONE in “AES_STATUS” on page 1010.
zBit 7 – AES_REQUEST
A write access with AES_REQUEST = 1 initiates the AES operation.
zBit 6:4 – AES_MODE
This register bit sets the AES operation mode.
Table 40-3. AES Error
Value Description
0x0 No error of the AES module
0x1 AES module error
Table 40-4. AES Done
Value Description
0x0 AES operation has not been completed
0x1 AES operation has been completed
Bit 7 6543210
0x83 AES_REQUEST AES_MODE AES_DIR
Access W R/W R/W R/W R/W R R R
Reset 0 0000000
Table 40-5. AES Request
Value Description
0x0 Security module, AES core idle
0x1 A write access starts the AES operation
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zBit 3 – AES_DIR: AES Direction
The register bit AES_DIR sets the AES operation direction, either encryption or decryption.
40.1.8.3 AES_CTRL_MIRROR
Name: AES_CTRL_MIRROR
Offset: 0x94
Reset: 0x00
Property: -
AES_CTRL_MIRROR is a mirrored version of “AES_CTRL” on page 1011. Refer to “AES_CTRL” on page 1011 for
details.
This register could be used to start a security operation within a single SRAM access by appending it to the data stream
and setting register bit AES_REQUEST = 1.
Table 40-6. AES Mode
Value Description
0x0 ECB mode
0x1 KEY mode
0x2 CBC mode
0x3 - 0x7 Reserved
Table 40-7. AES Direction
Value Description
0x0 AES encryption (ECB, CBC)
0x1 AES decryption (ECB)
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40.2 Random Number Generator
40.2.1 Overview
The AT86RF233 incorporates a two bit truly random number generator by observation of noise. This random number can
be used to:
zGenerate random seeds for CSMA-CA algorithm, see “Extended Operating Mode” on page 915
zGenerate random values for AES key generation, see “Security Module (AES)” on page 1005
Random numbers are stored in register bits RND_VALUE (register 0x06, PHY_RSSI). The random number is updated
every tRND = 1µs in Basic Operation Mode receive states. The Random Number Generator does not work if the preamble
detector is disabled (RX_PDT_DIS = 1, refer to “Register Description” on page 976).
40.2.2 Register Description
40.2.2.1 PHY_RSSI
Name: PHY_RSSI
Offset: 0x06
Reset: 0x60
Property: -
The PHY_RSSI register is a multi-purpose register that indicates FCS validity, to provide random numbers, and a RSSI
value.
zBit 6:5 – RND_VALUE
The 2-bit random value can be retrieved by reading register bits RND_VALUE.
40.3 High Data Rate Modes
Note: Only applicable for T = -40°C to 85°C.
The main features are:
zHigh Data Rate Transmission up to 2000kb/s.
zSupport of Basic and Extended Operating Mode
zSupport of other features of the Extended Feature Set
40.3.1 Overview
The AT86RF233 also supports alternative data rates, higher than 250kb/s for applications beyond IEEE 802.15.4
compliant networks.
Bit 7 6 5 4 3 2 1 0
0x06 RX_CRC_VALID RND_VALUES RSSI
Access R R R R R R R R
Reset 0 1 1 0 0 0 0 0
Table 40-8. RND Value
Value Description
0x3 Deliver two bit noise value within receive state.
Valid values are [3, 2, …, 0].
Note: 1. The radio transceiver shall be in Basic Operating Mode receive state.
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The selection of a data rate does not affect the remaining functionality. Thus it is possible to run all features and
operating modes of the radio transceiver in various combinations.
The data rate can be selected by writing to register bits OQPSK_DATA_RATE (register 0x0C, TRX_CTRL_2).
The High Data Rate Modes occupy the same RF channel bandwidth as the IEEE 802.15.4 – 2.4GHz 250kb/s standard
mode. Due to the decreased spreading factor, the sensitivity of the receiver is reduced accordingly. Table 40-9 shows
typical values of the sensitivity for different data rates.
By default there is no header based signaling of the data rate within a transmitted frame. Thus nodes using a data rate
other than the default IEEE 802.15.4 data rate of 250kb/s are to be configured in advance and consistently. Alternatively,
the configurable start of frame delimiter (SFD) could be used as an indicator of the PHY data rate, see “Alternate Start-
Of-Frame Delimiter” on page 1033.
40.3.2 High Data Rate Packet Structure
In order to allow appropriate frame synchronization, AT86RF233 higher data rate modulation is restricted to the payload
octets only. The SHR and the PHR field are transmitted with the IEEE 802.15.4 compliant data rate of 250kb/s, refer to
“PHY Protocol Data Unit (PPDU)” on page 947.
A comparison of the general packet structure for different data rates with an example PSDU length of 80 octets is shown
in Figure 40-6.
Figure 40-6. High Data Rate Frame Structure
Due to the overhead caused by the SHR, PHR as well as the FCS, the effective data rate is lower than the selected data
rate. This is also affected by the length of the PSDU. A graphical representation of the effective PSDU data rate is shown
in Figure 40-7.
Table 40-9. High Data Rate Sensitivity for AWGN channel
High Data Rate Sensitivity Description
250kb/s -101dBm PER ≤1%, PSDU length of 20 octets
500kb/s -96dBm PER ≤1%, PSDU length of 20 octets
1000kb/s -94dBm PER ≤1%, PSDU length of 20 octets
2000kb/s -88dBm PER ≤1%, PSDU length of 20 octets
250 kb/s
0time [µs]192
SFD
PHR
832 1472 2752
500 kb/s
SFD
PHR
1000 kb/s
SFD
PHR
2000 kb/s
SFD
PHR
512
FCS
FCS
PSDU: 80 octets
PSDU: 80 octets
PSDU: 80 octets
PSDU: 80 octets
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Figure 40-7. Effective Data Rate “B” for O-QPSK High Data Rate Modes
The effective throughput is further affected by the MAC overhead, the acknowledgment scheme as well as the
microcontroller processing capability. Consequently, High Data Rate transmission and reception is useful for large PSDU
lengths due to the higher effective data rate, or to reduce the power consumption of the system. When using High Data
Rate Modes the active on-air time is significantly reduced.
40.3.3 High Data Rate Frame Buffer Access
The AT86RF233 Frame Buffer access to read or write frames for High Data Rate transmission is similar to the procedure
described in “Frame Buffer Access Mode” on page 886. However, during Frame Buffer read access the next byte
transferred after the PSDU data is the LQI value. This value is invalid for the High Data Rates.
Figure 40-5 illustrates the packet structure of a High Data Rate Frame Buffer read access.
Figure 40-8. Package Structure - High Data Rate Frame Buffer Read Access
The structure of RX_STATUS is described in “Structure of RX_STATUS” on page 887.
40.3.4 High Data Rate Energy Detection
According to IEEE 802.15.4 the ED measurement duration is eight symbol periods. For frames operated at higher data
rates the automated ED measurement duration is reduced to 32µs to take the reduced frame length into account, refer to
“Energy Detection (ED)” on page 965.
During Frame Buffer read access the ED value is appended to the PSDU data, refer to “High Data Rate Frame Buffer
Access” on page 1015.
0
200
400
600
800
1000
1200
1400
1600
0 20406080100120
PSDU length in octets
B [kb/s]
2000
1000
500
250
2000 kb/s
1000 kb/s
500 kb/s
250 kb/s
0reserved[4:0]0MOSI
PHY_STATUSMISO
byte 1 (com m and byte )
1XX
PHR[7:0]
byte 2 (data byte )
XX
PSDU[7:0]
byte 3 (data byte )
XX
ED[7:0]
byte n- 1 (data byte )
XX
RX_STATUS[7:0]
byte n(data byte )
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40.3.5 High Data Rate Mode Options
40.3.5.1 Receiver Sensitivity Control
The different data rates between PPDU header (SHR and PHR) and PHY payload (PSDU) cause a different sensitivity
between header and payload. This can be adjusted by defining sensitivity threshold levels of the receiver. With a
sensitivity threshold level RX_PDT_LEVEL > 0 (register 0x15, RX_SYN), the receiver does not receive frames with an
RSSI level below that threshold.
Enabling receiver sensitivity control with at least RX_PDT_LEVEL = 1 is recommended for the 2000kb/s rate with a
PSDU sensitivity of -88dBm. In the case of receiving with the default setting of RX_PDT_LEVEL, a high data rate frame
may be detected even if the PSDU sensitivity is above the received signal strength. In this case the frame is rejected.
A description of the settings to control the sensitivity threshold RX_PDT_LEVEL (register 0x15, RX_SYN) can be found
in “Register Description” on page 976.
40.3.5.2 Scrambler
For data rate 2000kb/s, additional chip scrambling is applied per default, in order to mitigate data dependent spectral
properties. Scrambling can be disabled if AT86RF233 register bit OQPSK_SCRAM_EN (register 0x0C, TRX_CTRL_2) is
set to zero.
40.3.5.3 Carrier Sense
For clear channel assessment, IEEE 802.15.4-2006 specifies several modes which may either apply Energy above
threshold or Carrier sense (CS) or a combination of both. In High Data Rate Modes only “Energy above threshold” is
supported, since the modulation spreading is not compliant to IEEE 802.15.4-2006.
40.3.5.4 Link Quality Indicator (LQI)
For the High Data Rate Modes, the link quality indicator does not contain useful information and should be discarded.
40.3.5.5 Reduced Acknowledgment Timing
On higher data rates the IEEE 802.15.4 compliant acknowledgment frame response time of 192µs significantly reduces
the effective data rate of the network. To minimize this influence in Extended Operating Mode RX_AACK, refer to
“RX_AACK_ON – Receive with Automatic ACK” on page 918, the acknowledgment frame response time can be reduced
to 32µs. Figure 40-9 illustrates an example for a reception and acknowledgement of a frame with a data rate of 2000kb/s
and a PSDU length of 80 symbols. The PSDU length of the acknowledgment frame is five octets according to
IEEE 802.15.4.
Figure 40-9. High Data Rate AACK Timing
If register bit AACK_ACK_TIME (register 0x17, XAH_CTRL_1) is set the acknowledgment time is reduced from 192µs to
32µs.
0time [µs]
192 512
AACK_ACK_TIME = 0 PSDU: 80 octets
SFD
PHR
SFD
PHR
704 916
32 µs
PSDU: 80 octets
SFD
PHR
SFD
PHR
192 µs
544
AACK_ACK_TIME = 1
ACK
ACK
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40.3.6 Register Description
40.3.6.1 TRX_CTRL_2
Name: TRX_CTRL_2
Offset: 0x0C
Reset: -
Property: -
The TRX_CTRL_2 register is a multi-purpose control register to control various settings of the radio transceiver.
zBit 5 – OQPSK_SCRAM_EN
If register bit OQPSK_SCRAM_EN is enabled, an additional chip scrambling is applied for 2000kb/s data rate.
zBit 2:0 – OQPSK_DATA_RATE [2:0]
A write access to these register bits set the OQPSK PSDU data rate used by the radio transceiver. The reset value
O-QPSK_DATA_RATE = 0 is the PSDU data rate according to IEEE 802.15.4.
Bit 7 6 5 4 3 210
0x0C RX_SAFE_MODE OQPSK_SCRAM_EN OQPSK_DATA_RATE
Access R/W R R/W R R R/W R/W R/W
Reset 0 0 1 0 0 000
Table 40-10. OQPSK Scrambler Enabled
Value Description
0Scrambler is disabled
1Scrambler is enabled
Table 40-11. OQPSK Data Rate
Value Description
0x0(1) 250kb/s
0x1 500kb/s
0x2 1000kb/s
0x3 2000kb/s
0x4 - 0x7 All other values are reserved
Note: 1. EEE 802.15.4 compliant.
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40.3.6.2 RX_SYN
Name: RX_SYN
Offset: 0x15
Reset: -
Property: -
The register RX_SYN controls the blocking of receiver path and the sensitivity threshold of the receiver.
zBit 3:0 - RX_PDT_LEVEL
The register bits RX_PDT_LEVEL desensitize the receiver in steps of 3dB.
Bit 7 6 5 4 3 2 1 0
0x15 RX_PDT_DIS RX_PDT_LEVEL
Access R/W R R R R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Table 40-12. RX_PDT_LEVEL
Value Description
0x00 Maximum RX sensitivity
0x01 - 0x0E Reserved
0x0F RX input level > RSSI_BASE_VAL + 3[dB] x 14
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40.3.6.3 XAH_CTRL_1
Name: XAH_CTRL_1
Offset: 0x17
Reset: -
Property: -
The XAH_CTRL_1 register is a multi-purpose controls register for Extended Operating Mode.
zBit 2 – AACK_ACK_TIME
The register bit AACK_ACK_TIME controls the acknowledgment frame response time within RX_AACK mode.
According to IEEE 802.15.4-2006, Section 7.5.6.4.2 the transmission of an acknowledgment frame shall commence
12 symbol periods (aTurnaroundTime) after the reception of the last symbol of a data or MAC command frame. This is
achieved with the reset value of the register bit AACK_ACK_TIME.
Alternatively, if AACK_ACK_TIME = 1 an acknowledgment frame is sent already two symbol periods after the reception
of the last symbol of a data or MAC command frame. This may be applied to proprietary networks or networks using the
High Data Rate Modes to increase battery lifetime and to improve the overall data throughput.
Bit 7 6 5 4 3 2 1 0
0x17 ARET_TX_TS_EN AACK_FLTR
_RES_FT
AACK_ULD
_RES_FT
AACK_
ACK_TIME
AACK_
PROM_
MODE
AACK_
SPC_EN
Access R/W R R/W R/W R R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Table 40-13. AACK_ACK_TIME
Value Description
0x0 Acknowledgment time is 12 symbol periods (aTurnaroundTime)
0x1 Acknowledgment time is two symbol periods
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40.4 Antenna Diversity
The Antenna Diversity implementation is characterized by:
zImproves signal path robustness between nodes
zAT86RF233 self-contained antenna diversity algorithm
zDirect register based antenna selection
40.4.1 Overview
Due to multipath propagation effects between network nodes, the receive signal strength may vary and affect the link
quality, even for small variance of the antenna location. These fading effects can result in an increased error floor or loss
of the connection between devices.
To improve the reliability of an RF connection between network nodes Antenna Diversity can be applied to reduce effects
of multipath propagation and fading. Antenna Diversity uses two antennas to select the most reliable RF signal path. To
ensure highly independent receive signals on both antennas, the antennas should be carefully separated from each
other.
If a valid IEEE 802.15.4 frame is detected on one antenna, this antenna is selected for reception. Otherwise the search is
continued on the other antenna and vice versa.
Antenna Diversity can be used in Basic and Extended Operating Modes and can also be combined with other features
and operating modes like High Data Rate and RX/TX Indication.
40.4.2 Antenna Diversity Application Example
A block diagram for an application using an antenna switch is shown in Figure 40-10.
Figure 40-10.Antenna Diversity - Block Diagram
Generally, when the external RF-Switch (SW1) is to be controlled by antenna diversity algorithm, the antenna diversity
enable must be activated by register bit ANT_EXT_SW_EN (register 0x0D, ANT_DIV). Then the internal digital control
signals DIG1 and DIG2 are enabled (refer to “Digital I/O Signals” on page 18) to drive the antenna switch control signals
to the differential inputs of the RF Switch (SW1) to switch between ANT0 and ANT1.
SAM R21
GNDANA
GNDANA
RFP
RFN
RFCTRL
DIG1
DIG2
DIG3
DIG4
SAM D21
RF-
SWITCH BALUN
ANT1
ANT0
SW1 B1
FECTRLi(DIG1)
FECTRLj(DIG2)
AT86RF233
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If the AT86RF233 is not in a receive or transmit state, it is recommended to disable register bit ANT_EXT_SW_EN to
reduce the power consumption or avoid leakage current of an external RF switch, especially during SLEEP or
DEEP_SLEEP state. If register bit ANT_EXT_SW_EN = 0, output signals DIG1/DIG2 are pulled-down to digital ground.
40.4.2.1 User Defined Antenna Selection
A microcontroller defined selection of a certain antenna can be done by disabling the automated Antenna Diversity
algorithm (ANT_DIV_EN = 0) and selecting one antenna using register bits ANT_CTRL = 1 / 2.
The antenna defined by register bits ANT_CTRL (register 0x0D, ANT_DIV) is used for transmission and reception.
40.4.2.2 Autonomous Antenna Selection
The autonomous Antenna Diversity algorithm is enabled with register bits ANT_DIV_EN = 1 and ANT_CTRL = 0 / 3
(register 0x0D, ANT_DIV). It allows the use of Antenna Diversity even if the microcontroller does currently not control the
radio transceiver, for instance in Extended Operating Mode.
Upon reception of a frame, the AT86RF233 selects one antenna. The selected antenna is then indicated by register bit
ANT_SEL (register 0x0D, ANT_DIV). If required, it is recommended to read register bit ANT_SEL after
IRQ_2 (RX_START). After the frame reception is completed, the antenna selection continues searching for new frames
on both antennas. However, the register bit ANT_SEL maintains its previous value (from the last received frame) until a
new IEEE 802.15.4 frame has been detected, and the selection algorithm locked into one antenna again. At this time the
register bit ANT_SEL is updated again.
If a device is in RX_AACK mode, receiving a frame containing an ACK request, the ACK frame is transmitted using the
same antenna as used during receive.
If a device performs a transaction in TX_ARET mode, it starts to listen for an ACK on the transmit antenna. If no ACK
was received, the next transmission attempt is done on the other transmit antenna. This will be repeated with each retry.
40.4.3 Antenna Diversity Sensitivity Control
Due to a different receive algorithm used by the Antenna Diversity algorithm, the correlator threshold of the receiver has
to be adjusted. It is recommended to set register bits PDT_THRES (register 0x0A, RX_CTRL) to three.
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40.4.4 Register Description
40.4.4.1 RX_CTRL
Name: RX_CTRL
Offset: 0x0A
Reset: 0x37
Property: -
The RX_CTRL register controls the sensitivity of the Antenna Diversity mode and indicates the receiver synchronization
behavior.
zBit 3:0 - PDT_THRES
The register bits PDT_THRES control the sensitivity of the receiver correlation unit.
Bit 7 6 5 4 3 2 1 0
0x0A PEL_SHIFT_VALUES PDT_THRES
Access R R R/W R/W R/W R/W R/W R/W
Reset 0 0 1 1 0 1 1 1
Table 40-14. PDT_THRES
Value Description
0x0 - 0x2 Reserved
0x3(1) Recommended correlator threshold for Antenna Diversity operation
0x4 - 0x6 Reserved
0x7 To be used if Antenna Diversity algorithm is disabled
0x8 - 0xF Reserved
Note: 1. If the Antenna Diversity algorithm is enabled (ANT_DIV_EN = 1), the value shall be set to
PDT_THRES = 3, otherwise it shall be set back to the reset value. This is not automatically done by the
hardware.
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40.4.4.2 ANT_DIV
Name: ANT_DIV
Offset: 0x0D
Reset: 0x00
Property: -
The ANT_DIV register controls Antenna Diversity.
zBit 7 - ANT_SEL
Signals selected antenna, related to the last received frame.
This register bit signals the currently selected antenna path. The selection may be based either on the last antenna
diversity cycle (ANT_DIV_EN = 1) or on the content of register bits ANT_CTRL, for details refer to
“Antenna Diversity Application Example” on page 1020.
zBit 3 - ANT_DIV_EN
The register bit ANT_DIV_EN activates the autonomous Antenna Diversity algorithm.
If register bit ANT_DIV_EN is set the Antenna Diversity algorithm is enabled. On reception of a frame the algorithm
selects an antenna autonomously during SHR search. This selection is kept until:
zA new SHR search starts
zLeaving receive states
zRegister bits ANT_CTRL are manually programmed
zBit 2 - ANT_EXT_SW_EN
The register bit ANT_EXT_SW_EN controls the external antenna switch.
Bit 7 6 5 4 3 2 1 0
0x0D ANT_SEL ANT_DIV_EN ANT_EXT
_SW_EN ANT_CTRL
Access R R R R R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Table 40-15. ANT_SEL
Value Description
0x0 Antenna 0
0x1 Antenna 1
Note: 1. If the autonomous Antenna Diversity algorithm is enabled, the register bit ANT_SEL maintains its previ-
ous value (from the last received frame) until a new SHR has been found.
Table 40-16. ANT_DIV_EN
Value Description
0x0 Antenna Diversity algorithm is disabled
0x1 Antenna Diversity algorithm is enabled
Note: 1. If ANT_DIV_EN = 1 register bit ANT_EXT_SW_EN shall be set to one, too. This is not automatically done
by the hardware.
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If enabled, DIG1 and DIG2 provides a differential control signal for an Antenna Diversity switch. The selection of a
specific antenna is done either by the automated Antenna Diversity algorithm (ANT_DIV_EN = 1), or according to
register bits ANT_CTRL if Antenna Diversity algorithm is disabled.
If the AT86RF233 is not in receive or transmit state, it is recommended to disable register bit ANT_EXT_SW_EN to
reduce the power consumption or avoid leakage current of an external RF switch, especially during SLEEP or
DEEP_SLEEP state. If register bit ANT_EXT_SW_EN = 0, DIG1 and DIG2 are pulled-down to digital ground.
DIG2 is overloaded with RX and TX Frame Time Stamping, see “RX and TX Frame Time Stamping (TX_ARET)” on page
1027, if IRQ_2_EXT_EN is set.
zBit 1:0 - ANT_CTRL
These register bits provide a static control of an Antenna Diversity switch.
These register bits provide a static control of an Antenna Diversity switch if ANT_DIV_EN = 0 and
ANT_EXT_SW_EN = 1. Although it is possible to change register bits ANT_CTRL in state TRX_OFF, this change will be
effective at DIG1 and DIG2 in states PLL_ON and RX_ON.
Table 40-17. ANT_EXT_SW_EN
Value Description
0x0 Antenna Diversity RF switch control is disabled
0x1 Antenna Diversity RF switch control is enabled
Table 40-18. ANT_CTRL
Value Description
0x0 Mandatory setting for applications not using Antenna Diversity and if autonomous antenna selection is enabled
0x1
Antenna 0
DIG1 = L
DIG2 = H
0x2
Antenna 1
DIG1 = H
DIG2 = L
0x3 Same behavior as value zero
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40.5 RX/TX Indicator
The main features are:
zRX/TX indicator to control an external RF front-end
zMicrocontroller independent RF front-end control
zProviding TX timing information
40.5.1 Overview
While IEEE 802.15.4 is targeting low cost and low power applications, solutions supporting higher transmit output power
are occasionally desirable. To simplify the control of an optional external RF front-end, a differential control signal pair
can indicate that the AT86RF233 is currently in transmit mode.
The control of an external RF front-end is done via internal digital control signals DIG3/4 available as alternate pin
functions FECTRL[0..5] on pins PA08..15, refer to “Block Diagrams” on page 8. The function of this signal pair is enabled
with register bit PA_EXT_EN (register 0x04, TRX_CTRL_1). While the transmitter is turned off, the DIG3 signal is set to
low level and DIG4 signal to high level. If the radio transceiver starts to transmit, the two signals change the polarity. This
differential signal pair can be used to control PA, LNA, and RF switches.
If the AT86RF233 is not in a receive or transmit state, it is recommended to disable register bit PA_EXT_EN
(register 0x04, TRX_CTRL_1) to reduce the power consumption or avoid leakage current of external RF switches and
other building blocks, especially during SLEEP or DEEP_SLEEP state. If register bit PA_EXT_EN = 0, the output signals
DIG3/DIG4 are pulled-down to analog ground.
40.5.2 External RF-Front End Control
The timing of an external RF front-end relative to the radio transceiver sequencing is shown in Figure 40-11 and Figure
40-12, focusing on the TX indication.
A rising edge of the internal SLP_TR signal initiates a transmission, refer to “Receiver (RX)” on page 975. The radio
transceiver control switches the differential signal pair DIG3/DIG4 6µs after TX request recognition to TX operating mode
indication. After finishing the transmission, as shown in Figure 40-12, signal pair DIG3/DIG4 is switched back to RX
operating mode indication 3µs after disabling the AT86RF233 internal PA.
Figure 40-11.TX Power Up Ramping Control for RF Front-End for Maximum TX Power
06810
TRX_STATE
SLP_TR
PLL_ON
212 14 16 18 Length [μs]
PA buffer
4
PA
DIG3
DIG4
Modulation 11 00 00001
BUSY_TX
10 01 0101101 10 1010001
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Figure 40-12.TX Power Down Ramping for Maximum TX Power
40.5.3 Register Description
40.5.3.1 TRX_CTRL_1
Name: TRX_CTRL_1
Offset: 0x04
Reset: 0x22
Property: -
The TRX_CTRL_1 register is a multi-purpose register to control various operating modes and settings of the radio
transceiver.
zBit 7 – PA_EXT_EN
The register bit PA_EXT_EN enables RF front-end control signals DIG3 and DIG4 to indicate the transmit state of
the radio transceiver.
0 6
TRX_STATE BUSY_TX
2Length [μs]
PA buffer
4
PA
DIG3
DIG4
Modulation 11 0 001
PLL_ON
01 10 101001
Bit 7 6 5 4 3 2 1 0
0x04 PA_EXT_EN IRQ_2_EXT_E
N
TX_AUTO_
CRC_ON
RX_BL_
CTRL SPI_CMD_MODE IRQ_MASK_M
ODES
IRQ_
POLARITY
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 1 0 0 0 1 0
Table 40-19. PA_EXT_EN
PA_EXT_EN State Signal Value Description
0x0 n/a
DIG3 L
External RF front-end control disabled
DIG4 L
0x1(1)
TX_BUSY
DIG3 H
External RF front-end control enabled
DIG4 L
Other
DIG3 L
DIG4 H
Note: 1. It is recommended to set PA_EXT_EN = 1 only in receive or transmit states to reduce the power con-
sumption or avoid leakage current of external RF switches or other building blocks, especially during
SLEEP or DEEP_SLEEP state.
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40.6 RX and TX Frame Time Stamping (TX_ARET)
40.6.1 Overview
An exact timing of received and transmitted frames is signaled by the AT86RF233 DIG2, refer to “Block Diagrams” on
page 8. A valid PHR reception or start of frame transmission (start of modulation at beginning of first synchronization
byte) is indicated by a DIG2 rising edge. The signal remains high during frame reception or transmission. TX Frame Time
Stamping is limited to TX_ARET, whereas the RX Frame Time Stamping is available for all receive modes. Exemplary,
Figure 40-13 illustrates a frame reception example.
If this signal is not used for RX Frame Time Stamping, it can be configured for Antenna Diversity, refer to “Antenna
Diversity” on page 1020. Otherwise, this signal is internally connected to ground.
Figure 40-13.Timing of RX_START and DIG2 for RX Frame Time Stamping
Note: 1. Timing figures tIRQ refer to “Digital Interface Timing Characteristics” on page 1101.
128 160 1920192 + m * 32 Time [µs]
RX Frame
on Air
IRQ_2 (RX_START)
tIRQ
RX_ON RX_ON
IRQ
TRX_STATE
Interrupt latency
Preamble SFD PHR PSDU (250 kb/s)
411 m < 128
Number of Octets
Frame Content
TRX_END
tIRQ
BUSY_RX
DIG2 (RX Frame Time Stamp)
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40.6.2 Register Description
40.6.2.1 TRX_CTRL_1
Name: TRX_CTRL_1
Offset: 0x04
Reset: 0x22
Property: -
The TRX_CTRL_1 register is a multi-purpose register to control various operating modes and settings of the radio
transceiver.
zBit 6 - IRQ_2_EXT_EN
The register bit IRQ_2_EXT_EN controls external signaling for time stamping via DIG2.
40.6.2.2 XAH_CTRL_1
Name: XAH_CTRL_1
Offset: 0x17
Reset: 0x00
Property: -
The XAH_CTRL_1 register is a multi-purpose controls register for Extended Operating Mode.
zBit 7 - ARET_TX_TS_EN
If register bit ARET_TX_TS_EN = 1, then any frame transmission within TX_ARET mode is signaled via DIG2.
Bit 7 6 5 4 3 2 1 0
0x04 PA_EXT_EN IRQ_2_EXT_E
N
TX_AUTO_
CRC_ON
RX_BL_
CTRL SPI_CMD_MODE IRQ_MASK_M
ODES
IRQ_
POLARITY
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 1 0 0 0 1 0
Table 40-20. IRQ_2_EXT_EN
Value Description
0x0 Time stamping over DIG2 is disabled
0x1(1) Time stamping over DIG2 is enabled
Note: 1. DIG2 is also active if the corresponding interrupt event IRQ_2 (RX_START) mask bit in register 0x0E
(IRQ_MASK) is set to zero. The signal remains at high level until the end of the frame receive or transmit
procedure.
Bit 7 6 5 4 3 2 1 0
0x17 ARET_TX_
TS_EN
AACK_FLTR_
RES_FT
AACK_UPLD_
RES_FT
AACK
_ACK_
TIME
AACK_PROM_
MODE
AACK_SPC_
EN
Access R/W R/W R/W R/W R R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
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Table 40-21. ARET_TX_TS_EN
Value Description
0x0 TX_ARET time stamping via DIG2 is disabled
0x1(1) TX_ARET time stamping via DIG2 is enabled
Note: 1. It is necessary to set register bit IRQ_2_EXT_EN (register 0x04, TRX_CTRL_1).
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40.7 Frame Buffer Empty Indicator
40.7.1 Overview
For time critical applications that want to start reading the frame data as early as possible, the Atmel AT86RF233 Frame
Buffer status can be indicated to the microcontroller through a dedicated signal. This signal indicates to the
microcontroller if an access to the Frame Buffer is not possible since valid PSDU data are missing.
The IRQ signal connected to the microcontroller port PB00 can be configured as a Frame Buffer Empty Indicator during
a Frame Buffer read access. This mode is enabled by register bit RX_BL_CTRL (register 0x04, TRX_CTRL_1). The IRQ
signal turns into Frame Buffer Empty Indicator after the Frame Buffer read access command, see note (1) in Figure 40-
14, has been transferred on the SPI bus until the Frame Buffer read procedure has finished indicated by /SEL = H, see
note (4).
Figure 40-14.Timing Diagram of Frame Buffer Empty Indicator
Notes: 1. Timing figure t12 refer to “Digital Interface Timing Characteristics” on page 1101.
2. A Frame Buffer read access can proceed as long as IRQ = L.
3. IRQ = H indicates that the Frame Buffer is currently not ready for another SPI cycle.
4. The Frame Buffer read procedure has finished indicated by /SEL = H.
The microcontroller has to observe the IRQ signal internally connected to PB00 during the Frame Buffer read procedure.
A Frame Buffer read access can proceed as long as IRQ = L(2). When the IRQ output is pulled high (IRQ = H), the Frame
Buffer is not ready for another SPI cycle(3) above. The read operation can be resumed as the IRQ output is pulled low
again (IRQ = L) to indicate new data in the buffer.
On Frame Buffer read access, three more byte are transferred via MISO after PHR and PSDU data, namely LQI, ED, and
RX_STATUS; refer to “Frame Buffer Access Mode” on page 886. Because these bytes are appended and physically not
stored in the frame buffer, they are ignored for Frame Buffer empty indication.
The Frame Buffer Empty Indicator IRQ becomes valid after t12 = 750ns starting from the last SCLK rising edge while
reading a Frame Buffer command byte, see figure above.
Upon completing the SPI frame data receive task, SPI read access can be disabled by pulling /SEL = H, note (4). At this
time the IRQ output can be used to flag pending interrupts to the processor.
If during the Frame Buffer read access a receive error occurs (for example an PLL unlock), the Frame Buffer Empty
Indicator locks on 'empty' ((IRQ) = H) too. To prevent possible deadlocks, the microcontroller should impose a timeout
counter that checks whether the Frame Buffer Empty Indicator remains logic high for more than two octet periods. A new
byte must have been arrived at the frame buffer during that period. If not, the Frame Buffer read access should be
aborted.
/SEL
MOSI
MISO
IRQ
SCLK
Command
PHY_STATUS
XX
IRQ_STATUS
Command
TRX_STATUS
XX
PHR[7:0]
XX
PSDU[7:0]
IRQ_2 (RX_START)
XX
PSDU[7:0]
XX
PSDU[7:0]
t12
XX
RX_STATUS
Command
TRX_STATUS
XX
IRQ_STATUS
IRQ_3 (TRX_END)
Frame Buffer Empty Indicator
(1) (4)(3)Notes (2)
XX
LQI[7:0]
XX
ED[7:0]
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40.7.2 Register Description
40.7.2.1 TRX_CTRL_1
Name: TRX_CTRL_1
Offset: 0x04
Reset: 0x22
Property: -
The TRX_CTRL_1 register is a multi-purpose register to control various operating modes and settings of the radio
transceiver.
zBit 4 - RX_BL_CTRL
The register bit RX_BL_CTRL controls the Frame Buffer Empty Indicator.
If this register bit is set, the Frame Buffer Empty Indicator is enabled. After sending a Frame Buffer read command
(refer to “SPI Protocol” on page 885), signal IRQ indicates that an access to the Frame Buffer is not possible since
PSDU data are not available yet.
The IRQ signal does not indicate any interrupts during this time.
Bit 7 6 5 4 3 2 1 0
0x04 PA_EXT_EN IRQ_2_EXT_
EN
TX_AUTO_
CRC_ON RX_BL_CTRL SPI_CMD_MODE IRQ_MASK_
MODES
IRQ_
POLARITY
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 1 0 0 0 1 0
Table 40-22. RX_BL_CTRL
Value Description
0x0 Frame Buffer Empty Indicator disabled
0x1 Frame Buffer Empty Indicator enabled
Note: 1. A modification of register bit IRQ_POLARITY has no influence to RX_BL_CTRL behavior.
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40.8 Dynamic Frame Buffer Protection
40.8.1 Overview
The Atmel AT86RF233 continues the reception of incoming frames as long as it is in any receive state. When a frame
was successfully received and stored into the Frame Buffer, the following frame will overwrite the Frame Buffer content
again.
To relax the timing requirements for a Frame Buffer read access the Dynamic Frame Buffer Protection prevents that a
new valid frame passes to the Frame Buffer until a Frame Buffer read access has ended (indicated by /SEL = H, refer to
“SPI Protocol” on page 885).
A received frame is automatically protected against overwriting:
zin Basic Operating Mode, if its FCS is valid
zin Extended Operating Mode, if an IRQ_3 (TRX_END) is generated.
The Dynamic Frame Buffer Protection is enabled with RX_SAFE_MODE (register 0x0C, TRX_CTRL_2) set and
applicable in transceiver states RX_ON and RX_AACK_ON.
Note: 1. The Dynamic Frame Buffer Protection only prevents write accesses from the air interface – not from the SPI inter-
face. A Frame Buffer or SRAM write access may still modify the Frame Buffer content.
40.8.2 Register Description
40.8.2.1 TRX_CTRL_2
Name: TRX_CTRL_2
Offset: 0x0C
Reset: 0x20
Property: -
The TRX_CTRL_2 register is a multi-purpose control register to control various settings of the radio transceiver.
zBit 7 - RX_SAFE_MODE
Protect Frame Buffer after frame reception with valid FCF check.
This operation mode is independent of the setting of register bits RX_PDT_LEVEL, (register 0x15, RX_SYN), refer
to “Configuration” on page 975.
Bit 7 6 5 4 3 2 1 0
0x0C RX_SAFE_
MODE OQPSK_DATA_RATE
Access R/W R R/W R R R/W R/W R/W
Reset 0 0 1 0 0 0 0 0
Table 40-23. RX_SAFE_MODE
Value Description
0x0 Disable Dynamic Frame Buffer protection
0x1(1) Enable Dynamic Frame Buffer protection
Note: 1. Dynamic Frame Buffer Protection is released on the rising edge of /SEL during a Frame Buffer read
access, or on the radio transceiver’s state change from RX_ON or RX_AACK_ON to another state.
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zBit 2:0 – OQPSK_DATA_RATE [2:0]
A write access to these register bits set the OQPSK PSDU data rate used by the radio transceiver. The reset value
O-QPSK_DATA_RATE = 0 is the PSDU data rate according to IEEE 802.15.4.
40.9 Alternate Start-Of-Frame Delimiter
40.9.1 Overview
The SFD (start of frame delimiter) is a field indicating the end of the SHR and the start of the packet data. The length of
the SFD is one octet (two symbols for O-QPSK). The octet is used for byte synchronization only and is not included in the
Atmel AT86RF233 Frame Buffer.
The value of the SFD can be changed if it is needed to operate in non-IEEE 802.15.4 compliant networks. A node with a
non-standard SFD value cannot synchronize with any of the IEEE 802.15.4 network nodes.
Due to the way the SHR is formed, it is not recommended to set the low-order four bits to zero. The LSB of the SFD is
transmitted first, that is right after the last bit of the preamble sequence.
40.9.2 Register Description
40.9.2.1 SFD_VALUE
Name: SFD_VALUE
Offset: 0x0B
Reset: 0xA7
Property: -
The SFD_VALUE register contains the one octet start-of-frame delimiter (SFD).
zBit 7:0 - SFD_VALUE
The register bits SFD_VALUE are required for transmit and receive operation.
For IEEE 802.15.4 compliant networks, set SFD_VALUE = 0xA7 as specified in [2]. This is the default value of the
register.
To establish non IEEE 802.15.4 compliant networks, the SFD value can be changed to any other value. If enabled,
IRQ_2 (RX_START) is issued only if the received SFD matches SFD_VALUE and a valid PHR is received.
Table 40-24. OQPSK Data Rate
Value Description
0x0(1) 250kb/s
0x1 - 0x7 All other values are reserved
Note: 1. IEEE 802.15.4 compliant.
Bit 7 6 5 4 3 2 1 0
0x0B SFD_VALUE
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 0 1 0 0 1 1 1
Table 40-25. SFD_VALUE
Value Description
0xA7 For transmission this value is copied into start-of-frame delimiter (SFD) field of frame header. For reception this
value is checked for incoming frames.
The default value is according to IEEE 802.15.4 specification.
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40.10 Reduced Power Consumption Mode (RPC)
The Reduced Power Consumption mode is characterized by:
zSignificant power reduction for several operating modes
zSelf-contained, self-calibrating and adaptive power reduction schemes
40.10.1 Overview
AT86RF233 RPC offers a variety independent techniques and methods to significantly reduce the power consumption.
RPC is applicable to several operating modes and transparent to other extended features.
Notes: 1. To achieve the lowest power consumption set register 0x16, TRX_RPC to 0xFF
2. or disabling the Reduced Power Consumption modes set register 0x16, TRX_RPC to 0xC1 or 0x01.
40.10.2 RPC Methods and Elements
40.10.2.1 PES – PLL Energy Saving
The PES mode is activated with register bit PLL_RPC_EN (register 0x16, TRX_RPC) set to one.
Applicable to states: PLL_ON and TX_ARET_ON
A state change towards PLL_ON or TX_ARET_ON causes an initial PLL calibration run, immediately followed by
entering the PES mode. A state change towards RX or TX states, a channel switch or PLL calibration causes a PLL
wake-up. After finishing such an operation, the PLL automatically enters the PES mode.
The typical current consumption IPLL_ON reduces from 5.2mA to 450µA.
40.10.2.2 SRT – Smart Receiving Technology
The SRT mode is activated with register bit RX_RPC_EN (register 0x16, TRX_RPC) set to one.
Applicable to states: RX_ON, RX_AACK_ON and TX_ARET
SRT reduces the average power consumption during RX listening periods. In typical environment situations SRT reduces
the average current consumption IRX_ON by up to 50%. A configuration of SRT is done with register bits RX_RPC_CTRL
(register 0x16, TRX_RPC).
Notes: 1. It’s recommended to disable SRT during RSSI measurements or random number generation, “Received
Signal Strength Indicator (RSSI)” on page 964 and “Random Number Generator” on page 1013.
2. During CCA or/and ED scan the SRT is disabled automatically.
3. If autonomous antenna diversity is enabled, SRT cannot achieve the maximum effect.
4. Depending on operating conditions (traffic, temperature, channel noise, frequency settings) the effective
reduction of current consumption may vary.
40.10.2.3 ERD – Extended Receiver Desensitizing
AT86RF233 ERD is activated with register bit PDT_RPC_EN (register 0x16, TRX_RPC) set to one.
Applicable to states: RX, RX_AACK and TX_ARET
In combination with RX_PDT_LEVEL settings, the average RX current is further significantly reduced, for details refer to
“Current Consumption Specifications” on page 1105.
An RX_PDT_LEVEL = 0x08 setting requires special attention. In contrast to definitions in Table 38-3, the sensitivity is
reduced to -83dBm only, but at much lower average RX listen current than comparable register settings.
Notes: 1. With RX_PDT_LEVEL = 0x08, RSSI/ED can not resolve RX input levels from -83dBm to -70dBm.
2. During CCA or/and ED scan the ERD is disabled automatically.
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40.10.2.4 TPH – Automated TX Power Handling
TPH is activated with register bit XAH_TX_RPC_EN (register 0x16, TRX_RPC) set to one.
Applicable to states: RX_AACK
ACK frame TX output power setting is automatically adapted according to a combination of received RX frame ED and
LQI values. If an expected frame has been successfully received with ED > -77dBm and LQI > 224, the TX output power
is reduced. The minimum power is -17dBm (ED > -45dBm and LQI > 224), whereas the maximum is set be register bits
TX_PWR (register 0x05, PHY_TX_PWR).
Reading the TX_PWR field provides the used transmit power for last transmitted frame including acknowledgement
frame. This allows monitoring the actual RPC handling used for transmitting. See register bits TX_PWR description for
further information.
The Table 40-26 shows the typical current consumption for dedicated TX output power values.
Notes: 1. The upper limit will be declared by register bits TX_PWR (register 0x05, PHY_TX_PWR), refer to “Register
Description” on page 980.
2. If the sequence number, refer to “MAC Protocol Data Unit (MPDU)” on page 948, from previous received frame
equal to the current frame sequence number, then no automatic TX power reduction will be activated.
Applicable to states: TX_ARET
If the first frame transmission fails, using a reduced TX output power as set by register bits TX_PWR (register 0x05,
PHY_TX_PWR), the next frame retry starts with maximum TX output power (+4dBm).
Note: 1. The lower limit for the first frame transmitting will be declared by register bits TX_PWR (register 0x05,
PHY_TX_PWR), refer to “Register Description” on page 980.
Achievable TX current consumption IBUSY_TX reductions are shown in “Current Consumption Specifications” on page
1105 or Table 40-26.
40.10.2.5 PAM – PAN Address Match Recognition
AT86RF233 PAM is activated with register bit IPAN_RPC_EN (register 0x16, TRX_RPC) set to one.
Applicable to states: RX_AACK
Address match fail indication of the IEEE 802.15.4 frame filtering causes stopping of the receive procedure in two ways:
1. If PAN address does not match, a new listen period starts immediately,
2. If PAN address matches, the radio transceiver enters power saving mode for the remaining frame and ACK period,
if an ACK is requested.
Notes: 1. PAM is applicable to short ACK time and reserved frames types as set by register bit AACK_ACK_TIME and reg-
ister bit AACK_FLTR_RES_FT (register 0x17, XAH_CTRL_1), respectively.
2. If promiscuous mode is enabled with AACK_PROM_MODE (register 0x17, XAH_CTRL_1) set, PAM is disabled
automatically.
Table 40-26. TX Output Power vs. Current Consumption (Extraction)
Register Bits TX Output Power [dBm] Current Consumption [mA]
TX_PWR
+4 13.8
+0 11.8
-17 7.2
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40.10.2.6 Miscellaneous Power Reduction Functions
Applicable to states: RX and RX_AACK
In addition to Dynamic Frame Buffer Protection, refer to “Dynamic Frame Buffer Protection” on page 1032:
During Dynamic Frame Buffer Protection, the radio transceiver automatically enters the power save mode.
Applicable to states: TX_ARET
In addition to CSMA-CA retry, refer to “TX_ARET_ON – Transmit with Automatic Frame Retransmission and CSMA-CA
Retry” on page 928:
After starting the TX_ARET transaction, a random backoff period is performed. Within this backoff period the radio
transceiver automatically enters power saving mode.
Applicable to states: TX_ARET and RX_AACK
In addition to TX/RX turnaround time, refer to “Extended Operating Mode” on page 915:
The radio transceiver automatically enters power saving mode in:
zTX_ARET: during the time waiting for an ACK frame, or
zRX_AACK: during the time waiting for ACK transmission
Note: 1. To handle nodes configured with a RX/TX turnaround time less than 12 symbols, register bits are to be set to
RX_RPC_CTRL = 0 within TX_ARET. Alternatively, register bit AACK_ACK_TIME (register 0x17, XAH_CTRL_1)
can be set to one.
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40.10.3 Register Description
40.10.3.1 TRX_RPC
Name: TRX_RPC
Offset: 0x16
Reset: 0xC1
Property: -
The TRX_RPC register controls the Reduce Power Consumption modes.
Note: 1. The reserved bit needs to be set one for write access.
zBit 7:6 - RX_RPC_CTRL
The register bits RX_RPC_CTRL are used for internal performance settings within Smart Receiving mode.
zBit 5 - RX_RPC_EN
The register bit RX_RPC_EN activates the Smart Receiving mode for all RX listening modes.
zBit 4 - PDT_RPC_EN
The register bit PDT_RPC_EN controls in combination with the RX_PDT_LEVEL value the reduced sensitivity
behavior under the RPC mode.
zBit 3 - PLL_RPC_EN
The register bit PLL_RPC_EN controls the extended PLL behavior within PLL_ON and TX_ARET_ON modes.
Bit 7 6 5 4 3 2 1 0
0x16 RX_RPC_CTRL RX_RPC
_EN
PDT_RPC_
EN
PLL_RPC
_EN
XAH_TX
_RPC_EN
IPAN_RPC
_EN
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 0 0 0 0 0 1
Table 40-27. RX_RPC_CTRL
Value Description
0x0 Activates minimum power saving behavior for Smart Receiving mode
0x01 - 0x02 Reserved
0x3 Activates maximum power saving behavior for Smart Receiving mode
Table 40-28. RX_RPC_EN
Value Description
0x0 Smart receiving mode is disabled
0x1 Smart receiving mode is enabled
Table 40-29. PDT_RPC_EN
Value Description
0x0 The reduced sensitivity RPC mode is disabled
0x1 The reduced sensitivity RPC mode is enabled
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zBit 2 - XAH_TX_RPC_EN
The register bit XAH_TX_RPC_EN controls in combination with the TX_PWR value the automatic TX power han-
dling within the Extended Operating Mode.
zBit 1 - IPAN_RPC_EN
The register bit IPAN_RPC_EN controls the own PAN handling within the RPC mode.
Table 40-30. PLL_RPC_EN
Value Description
0x0 The extended PLL behavior is disabled
0x1 The extended PLL behavior is enabled
Table 40-31. XAH_TX_RPC_EN
Value Description
0x0 The automatic TX power handling is disabled
0x1 The automatic TX power handling is enabled
Table 40-32. IPAN_RPC_EN
Value Description
0x0 The RPC PAN handling is disabled
0x1 The RPC PAN handling is enabled
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40.11 Time-Of-Flight Module (TOM)
The time-of-flight measurement functions are characterized by:
z24-bit Timer/Counter (T/C)
zAutomated T/C start, capturing and reset
zReference frequency error measurement
zPreamble synchronization monitoring
40.11.1 Overview
The AT86RF233 includes a set of means to trigger time measurements during message transfer.
40.11.2 Interrupt Handling
If TOM mode is enabled, it causes the generation of IRQ_2 (RX_START) interrupts for all received frames, even with
PHR set to zero and IRQ_2 (RX_START) is enabled.
40.11.3 TOM Measurements
40.11.3.1 24-bit Timer/Counter
The AT86RF233 features a 24-bit Timer/Counter (T/C), which is automatically started, captured or reset. The actual
action depends on specified events and operating modes. The T/C is operated at 16MHz. If a timer event occurs, the
current time stamp is captured to the Frame Buffer. The timer is reset and started automatically. An exception is the RX
synchronization mode: if the SFD is not equal to 0xA7. In this case, the current counter value is only captured to the
Frame Buffer.
T/C Content Access
With TOM mode enabled, the 24-bit T/C value (TIM) is mapped to Frame Buffer address space 0x7D, …, 0x7F.
zTIM_0: Frame Buffer Address (0x7D): T/C [7:0]
zTIM_1: Frame Buffer Address (0x7E): T/C [15:8]
zTIM_2: Frame Buffer Address (0x7F): T/C [23:16]
Events
The Timer/Counter is controlled as follow:
40.11.3.2 Reference Frequency Error Measurement
During frame reception and register bit TOM_EN is set within the AT86RF233, the frequency error between two peer
devices is estimated. The frequency error calculation (FEC) value is accessible from Frame Buffer address 0x7C.
The 8-bit value represents the drift between two successive received chips (0.5µs) with a granularity of 180°/256. The
value is accessible after IRQ_2 (RX_START) and updated after IRQ_3 (TRX_END). It is interpreted as a
two’s complement signed value in range of -500kHz, …, < 500kHz, respectively.
Table 40-33. 24-bit Timer/Counter Event Overview
Event Delay [µs] Capture Reset Start
TX start (rising edge of signal SLP_TR) 16.125 x x x
RX Synchronization; at detection of SFD
(SFD is equal 0xA7) 80 x x x
RX Synchronization; at detection of SFD
(SFD is not equal 0xA7) 80 x - -
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The frequency offset can be calculated as follow:
foffs[ppm] = FEC x (500000 / 128) / fRF[MHz]
40.11.3.3 Preamble Fine Synchronization Monitoring
During receive the radio transceiver searches for SHR symbols and SFD initially. The register bits PEL_SHIFT_VALUE
(register 0x0A, RX_CTRL) signals an early/late behavior relative to the determined discrete, 16MHz based,
synchronization time stamp.
As an alternative to the PEL_SHIFT_VALUE value the complex magnitude values from the synchronization module can
be used for a better time stamp estimation. With TOM mode enabled, the complex magnitude values (CPM) from the
symbol cross correlator are mapped to Frame Buffer address space 0x73, …, 0x7C.
zCPM_0: Frame Buffer Address (0x73)
z…
zCPM_8: Frame Buffer Address (0x7C)
40.11.3.4 Storage of Measurement Results
Using TOM mode, the Frame Buffer address space 0x73, …, 0x7F is reserved to store captured T/C content and other
data. This limits the number of usable PSDU octets for standard operation to 114. Any received frame exceeding this
number corrupts data stored in the Frame Buffer address starting from address 0x73.
Notes: 1. Basic Operating Mode within TX states: If TOM_EN is still set, but not required for the actual transaction, it
is possible to transmit up to 127 octets by writing PSDU data to the Frame Buffer after initiating the transmis-
sion with rising edge of SLP_TR or TX_START command.
2. Extended Operating Mode within TX_ARET states: If TOM_EN is still set, but not required for the actual
transaction, it is possible to transmit up to 127 octets by writing PSDU data to the Frame Buffer after initiat-
ing the transmission with rising edge of SLP_TR or TX_START command and MAX_FRAME_RETRIES
(register 0x2C, XAH_CTRL_0) set to zero.
3. Reception of an ACK frame causes mapping of TOM measurement results to Frame Buffer address space
0x73, …, 0x7F.
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40.11.4 Register Description
40.11.4.1 TRX_CTRL_0
Name: TRX_CTRL_0
Offset: 0x03
Reset: 0x09
Property: -
The TRX_CTRL_0 register controls the CLKM clock rate.
zBit 7 - TOM_EN
The register bit TOM_EN controls the Time-Of-Flight Measurement mode.
40.11.4.2 RX_CTRL
Name: RX_CTRL
Offset: 0x0A
Reset: 0x37
Property: -
The RX_CTRL register controls the sensitivity of the Antenna Diversity mode and indicates the receiver synchronization
behavior.
zBit 7:6 - PEL_SHIFT_VALUE
The register bits PEL_SHIFT_VALUE signals the synchronization shift behavior.
Bit 7 6 5 4 3 2 1 0
0x03 TOM_EN PMU_EN PMU_IF
_INVERSE
CLKM_SHA_
SEL CLKM_CTRL
Access R/W R R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 1 0 0 1
Table 40-34. TOM_EN
Value Description
0x0 TOM mode is disabled
0x1 TOM mode is enabled
Bit 7 6 5 4 3 2 1 0
0x0A PEL_SHIFT_VALUES PDT_THRES
Access R R R/W R/W R/W R/W R/W R/W
Reset 0 0 1 1 0 1 1 1
Table 40-35. PEL_SHIFT_VALUE
Value Description
0x0 Synchronization behavior is normal
0x1 Synchronization behavior is early
0x2 Synchronization behavior is late
0x3 Reserved
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40.11.4.3 XAH_CTRL_1
Name: XAH_CTRL_1
Offset: 0x17
Reset: 0x00
Property: -
The XAH_CTRL_1 register is a multi-purpose controls register for Extended Operating Mode.
zBit 0 - AACK_SPC_EN
The register bit AACK_SPC_EN enables the synchronization point correction (SPC) within RX_AACK mode. If
SPC is enabled, then acknowledgement frame start time will be corrected against PEL_SHIFT_VALUE content.
Bit 7 6 5 4 3 2 1 0
0x17 ARET_TX_T
S_EN
AACK_FLTR_
RES_FT
AACK_UPLD_
RES_FT
AACK
_ACK_
TIME
AACK_PROM_
MODE
AACK_SPC_E
N
Access R/W R/W R/W R/W R R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Table 40-36. AACK_SPC_EN
Value Description
0x0 Synchronization point correction is disabled
0x1 Synchronization point correction is enabled
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40.11.5 Frame Buffer Content Summary
40.11.5.1 TOM_CPM_0 for TOM_EN=0x01
Name: TOM_CPM_0
Offset: 0x73
Reset: 0x00
Property: -
The TOM_CPM_0 register contains the result of synchronization correlator.
zBit 7:0 - CPM_0
This register contains the CPM_0 value.
40.11.5.2 TOM_CPM_1 for TOM_EN=0x01
Name: TOM_CPM_1
Offset: 0x74
Reset: 0x00
Property: -
The TOM_CPM_1 register contains the result of synchronization correlator.
zBit 7:0 - CPM_1
This register contains the CPM_1 value.
Bit 7 6 5 4 3 2 1 0
0x73 CPM_0
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Table 40-37. CPM_0
Value Description
0x00 Complex magnitude value; distance from main peak minus 1000ns.
Valid values are [0xFF, 0xFE, …, 0x00].
Bit 7 6 5 4 3 2 1 0
0x74 CPM_1
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Table 40-38. CPM_1
Value Description
0x00 Complex magnitude value; distance from main peak minus 750ns.
Valid values are [0xFF, 0xFE, …, 0x00].
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40.11.5.3 TOM_CPM_2 for TOM_EN=0x01
Name: TOM_CPM_2
Offset: 0x75
Reset: 0x00
Property: -
The TOM_CPM_2 register contains the result of synchronization correlator.
zBit 7:0 - CPM_2
This register contains the CPM_2 value.
40.11.5.4 TOM_CPM_3 for TOM_EN=0x01
Name: TOM_CPM_3
Offset: 0x76
Reset: 0x00
Property: -
The TOM_CPM_3 register contains the result of synchronization correlator.
zBit 7:0 - CPM_3
This register contains the CPM_3 value.
Bit 7 6 5 4 3 2 1 0
0x75 CPM_2
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Table 40-39. CPM_2
Value Description
0x00 Complex magnitude value; distance from main peak minus 500ns.
Valid values are [0xFF, 0xFE, …, 0x00].
Bit 7 6 5 4 3 2 1 0
0x76 CPM_3
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Table 40-40. CPM_3
Value Description
0x00 Complex magnitude value; distance from main peak minus 250ns.
Valid values are [0xFF, 0xFE, …, 0x00].
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40.11.5.5 TOM_CPM_4 for TOM_EN=0x01
Name: TOM_CPM_4
Offset: 0x77
Reset: 0x00
Property: -
The TOM_CPM_4 register contains the result of synchronization correlator.
zBit 7:0 - CPM_4
This register contains the CPM_4 value.
40.11.5.6 TOM_CPM_5) for TOM_EN=0x01
Name: TOM_CPM_5
Offset: 0x78
Reset: 0x00
Property: -
The TOM_CPM_5 register contains the result of synchronization correlator.
zBit 7:0 - CPM_5
This register contains the CPM_5 value.
Bit 7 6 5 4 3 2 1 0
0x77 CPM_4
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Table 40-41. CPM_4
Value Description
0x00 Complex magnitude value; distance from main peak 0ns.
Valid values are [0xFF, 0xFE, …, 0x00].
Bit 7 6 5 4 3 2 1 0
0x78 CPM_5
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Table 40-42. CPM_5
Value Description
0x00 Complex magnitude value; distance from main peak plus 250ns.
Valid values are [0xFF, 0xFE, …, 0x00].
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40.11.5.7 TOM_CPM_6) for TOM_EN=0x01
Name: TOM_CPM_6
Offset: 0x79
Reset: 0x00
Property: -
The TOM_CPM_6 register contains the result of synchronization correlator.
zBit 7:0 - CPM_6
This register contains the CPM_6 value.
40.11.5.8 TOM_CPM_7 for TOM_EN=0x01
Name: TOM_CPM_7
Offset: 0x7A
Reset: 0x00
Property: -
The TOM_CPM_7 register contains the result of synchronization correlator.
zBit 7:0 - CPM_7
This register contains the CPM_7 value.
Bit 7 6 5 4 3 2 1 0
0x79 CPM_6
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Table 40-43. CPM_6
Value Description
0x00 Complex magnitude value; distance from main peak plus 500ns.
Valid values are [0xFF, 0xFE, …, 0x00].
Bit 7 6 5 4 3 2 1 0
0x7A CPM_7
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Table 40-44. CPM_7
Value Description
0x00 Complex magnitude value; distance from main peak plus 750ns.
Valid values are [0xFF, 0xFE, …, 0x00].
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40.11.5.9 TOM_CPM_8 for TOM_EN=0x01
Name: TOM_CPM_8
Offset: 0x7B
Reset: 0x00
Property: -
The TOM_CPM_8 register contains the result of synchronization correlator.
zBit 7:0 - CPM_8
This register contains the CPM_8 value.
40.11.5.10 TOM_FEC for TOM_EN=0x01
Name: TOM_FEC
Offset: 0x7C
Reset: 0x00
Property: -
The TOM_FEC register contains the result of a frequency offset measurement.
zBit 7:0 - FEC
This register contains the FEC value. An initial frequency offset estimation is available after PHR field detection.
An accumulated frequency offset measurement value over the frame duration is available at frame end.
Bit 7 6 5 4 3 2 1 0
0x7B CPM_8
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Table 40-45. CPM_8
Value Description
0x00 Complex magnitude value; distance from main peak plus 1000ns.
Valid values are [0xFF, 0xFE, …, 0x00].
Bit 7 6 5 4 3 2 1 0
0x7C FEC
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Table 40-46. FEC
Value Description
0x00 Two’s complement signed value in range of -500kHz, …, 500kHz.
Valid values are [0xFF, 0xFE, …, 0x00].
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40.11.5.11 TOM_TIM_0 for TOM_EN=0x01
Name: TOM_TIM_0
Offset: 0x7D
Reset: 0x00
Property: -
This register contains the lower 8-bit of the time-of-flight measurement, bits[7:0].
zBit 7:0 - TIM_0
Lower 8-bit of time-of-flight measurement, bits[7:0].
40.11.5.12 TOM_TIM_1 for TOM_EN=0x01
Name: TOM_TIM_1
Offset: 0x7E
Reset: 0x00
Property: -
This register contains 8-bit of the time-of-flight measurement, bits[15:8].
zBit 7:0 - TIM_1
8-bit of time-of-flight measurement, bits[15:8].
Bit 7 6 5 4 3 2 1 0
0x7D TIM_0
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Table 40-47. TIM_0
Value Description
0x00 Timer/Counter measurement value based on 16MHz.
Valid values are [0xFF, 0xFE, …, 0x00].
Bit 7 6 5 4 3 2 1 0
0x7E TIM_1
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Table 40-48. TIM_1
Value Description
0x00 Timer/Counter measurement value based on 16MHz.
Valid values are [0xFF, 0xFE, …, 0x00].
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40.11.5.13 TOM_TIM_2 for TOM_EN=0x01
Name: TOM_TIM_2
Offset: 0x7F
Reset: 0x00
Property: -
This register contains the higher 8-bit of the time-of-flight measurement, bits[23:16].
zBit 7:0 - TIM_2
Higher 8-bit of time-of-flight measurement, bits[23:16].
Bit 7 6 5 4 3 2 1 0
0x7F TIM_2
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Table 40-49. TIM_2
Value Description
0x00 Timer/Counter measurement value based on 16MHz.
Valid values are [0xFF, 0xFE, …, 0x00].
1050
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40.12 Phase Difference Measurement
The Phase Difference Measurement Unit (PMU) is characterized by:
zRelative phase measurement of received signal
40.12.1 Overview
The AT86RF233 performs a phase measurement of a received signal relative to an internal reference. The derived value
represents the phase delay of the received signal referenced to an internal reference signal in the receiver low-IF
domain, see “Receiver (RX)” on page 975. The measured value is captured in register bits PMU_VALUE (register 0x3B,
PHY_PMU_VALUE) and periodically updated.
40.12.2 Register Description
40.12.2.1 TRX_CTRL_0
Name: TRX_CTRL_0
Offset: 0x03
Reset: 0x09
Property: -
The TRX_CTRL_0 register controls the CLKM clock rate.
zBit 5 - PMU_EN
The register bit PMU_EN controls the Phase Difference Measurement Unit mode.
zBit 4 - PMU_IF_INVERSE
The register bit PMU_IF_INVERSE controls the PMU Intermediate Frequency path.
Bit 7 6 5 4 3 2 1 0
0x03 TOM_EN PMU_EN PMU_IF_
INVERSE
CLKM_
SHA_SEL CLKM_CTRL
Access R/W R R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 1 0 0 1
Table 40-50. PMU_EN
Value Description
0x0 PMU mode is disabled
0x1 PMU mode is enabled
Table 40-51. PMU_IF_INVERSE
Value Description
0x0 Normal IF position
0x1 Inverse IF position
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40.12.2.2 PHY_PMU_VALUE for PMU_EN=0x01:
Name: PHY_PMU_VALUE
Offset: 0x3B
Reset: 0x00
Property: -
zBit 7:0 - PMU_VALUE
The register bits PMU_VALUE signals the PMU measurement value.
Bit 7 6 5 4 3 2 1 0
0x03 PMU_VALUE
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Table 40-52. PMU_VALUE
Value Description
0x00 Signals 8-bit PMU measurement value. The value is updated every 8µs.
Valid values are [0xFF, 0xFE, …, 0x00].
1052
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41. AT86RF233 Register Reference
The AT86RF233 provides a register space of 64 8-bit registers used to configure, control and monitor the radio
transceiver.
Note: All registers not mentioned within the following table are reserved for internal use and must not be overwritten.
When writing to a register, any reserved bits shall be overwritten only with their reset value.
Table 41-1. AT86RF233 Register Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
0x01 TRX_STATUS CCA_DONE CCA_STATUS RESERVED TRX_STATUS 913, 933,
970
0x02 TRX_STATE TRAC_STATUS TRX_CMD 914, 935
0x03 TRX_CTRL_0 TOM_EN RESERVED PMU_EN PMU_IF_
INVERSE
CKLM_SHA_
SEL CLKM_CTRL 992, 1041,
1050
0x04 TRX_CTRL_1 PA_EXTN_EN IRQ_2_EXT_EN TX_AUTO_CRC_
ON
RX_BL_
CTRL SPI_CMD_MODE IRQ_MASK_
MODE
IRQ_
POLARITY
890, 900,
937, 963,
1026, 1028,
1031
0x05 PHY_TX_PWR RESERVED RESERVED RESERVED TX_PWR 980
0x06 PHY_RSSI RX_CRC_VALID RND_VALUE RSSI 963, 965,
1013
0x07 PHY_ED_LEVEL ED_LEVEL 967
0x08 PHY_CC_CCA CCA_REQUEST CCA_MODE CHANNEL 971, 996
0x09 CCA_THRES RESERVED CCA_ED_THRES 972
0x0A RX_CTRL PEL_SHIFT_VALUE RESERVED RESERVED PDT_THRES 1022, 1041
0x0B SFD_VALUE SFD_VALUE 1033
0x0C TRX_CTRL_2 RX_SAFE_MODE RESERVED RESERVED RESERVED OQPSK_DATA_RATE 1032
0x0D ANT_DIV ANT_SEL RESERVED ANT_DIV_EN ANT_EXT_
SW_EN ANT_CTRL 1023
0x0E IRQ_MASK IRQ_MASK 898
0x0F IRQ_STATUS IRQ_7_BAT_LOW IRQ_6_TRX_UR IRQ_5_AMI IRQ_4_CCA_
ED_DONE
IRQ_3_TRX_
END
IRQ_2_
RX_START
IRQ_1_PLL_
UNLOCK
IRQ_0_PLL_
LOCK 899
0x10 VREG_CTRL AVREG_EXT AVDD_OK RESERVED DVREG_EXT DVDD_OK RESERVED 986
0x11 BATMON RESERVED RESERVED BATMON_OK BATMON_
HR BATMON_VTH 988
0x12 XOSC_CTRL XTAL_MODE XTAL_TRIM 993
0x13 CC_CTRL_0 CC_NUMBER 997
0x14 CC_CTRL_1 RESERVED CC_BAND 997
0x15 RX_SYN RX_PDT_DIS RESERVED RX_PDT_LEVEL 976
0x16 TRX_RPC RX_RPC_CTRL RX_RPC_EN PDT_RPC_
EN PLL_RPC_EN XAH_TX_
RPC_EN
IPAN_RPC_
EN RESERVED 1037
0x17 XAH_CTRL_1 ARET_TC_TS_EN RESERVED AACK_FLTR_
RES_FT
AACK_UPLD_
RES_FT RESERVED AACK_ACK
_TIME
AACK_PRO
M_MODE
AACK_SPC_
EN
938, 954,
1028, 1042
0x18 FTN_CTRL FTN_START RESERVED FTNV 1001
0x19 XAH_CTRL_2 ARET_FRAME_RETIRES ARET_CSMA_RETRIES RESERVED 940
0x1A PLL_CF PLL_CF_START RESERVED RESERVED PLL_CF 998
0x1B PLL_DCU PLL_DCU_START RESERVED RESERVED 999
0x1C PART_NUM PART_NUM 891
0x1D VERSION_NUM VERSION_NUM 892
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The reset values of the AT86RF233 registers in state P_ON(1, 2, 3) are shown in Table 41-2 on page 1054.
Note: All reset values in Table 41-2 on page 1054 are only valid after a power on reset. After a reset procedure
(/RST = L) as described in “Reset Procedure” on page 909, the reset values of selected registers (for example
registers 0x01, 0x10, 0x11, 0x30) can differ from that in Table 41-2 on page 1054.
0x1E MAN_ID_0 MAN_ID_0 892
0x1F MAN_ID_1 MAN_ID_1 893
0x20 SHORT_ADDR_0 SHORT_ADDR_0 957
0x21 SHORT_ADDR_1 SHORT_ADDR_1 957
0x22 PAN_ ID _0 PAN_ID_0 957
0x23 PAN_ ID _1 PAN_ID_1 958
0x24 IEEE_ADDR_0 IEEE_ADDR_0 958
0x25 IEEE_ADDR_1 IEEE_ADDR_1 958
0x26 IEEE_ADDR_2 IEEE_ADDR_2 959
0x27 IEEE_ADDR_3 IEEE_ADDR_3 959
0x28 IEEE_ADDR_4 IEEE_ADDR_4 959
0x29 IEEE_ADDR_5 IEEE_ADDR_5 960
0x2A IEEE_ADDR_6 IEEE_ADDR_6 960
0x2B IEEE_ADDR_7 IEEE_ADDR_7 960
0x2C XAH_CTRL_0 MAX_FRAME_RETRIES MAX_CSMA_RETRIES SLOTTED_
OPERATION 941
0x2D CSMA_SEED_0 CSMA_SEED_0 943
0x2E CSMA_SEED_1 AACK_FVN_MODE AACK_SET_PD AACK_DIS_
ACK
AACK_I_AM_
COORD CSMA_SEED_1 944, 955
0x2F CSMA_BE MAX_BE MIN_BE 946
0x36 TST_CTRL_DIGI RESERVED RESERVED RESERVED RESERVED TST_CTRL_DIGI 1169
0x3C TST_AGC RESERVED AGC_HOLD_SEL AGC_RST AGC_OFF AGC_HOLD GC 977
0x3D TST_SDM MOD_SEL MOD TX_RX TX_RX_SEL RESERVED 999
Register Page - TOM_EN=0x01
0x3B PHY_TX_TIME RESERVED IRC_TX_TIME 981
Register Page - PMU_EN=0x01
0x3B PHY_PMU_VALUE PMU_VALUE 1051
Table 41-1. AT86RF233 Register Summary (Continued)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
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Notes: 1. While the reset value of register 0x10 is 0x00, any practical access to the register is only possible when
DVREG is active. So this register is always read out as 0x04. For details, refer to “Voltage Regulators
(AVREG, DVREG)” on page 983.
2. While the reset value of register 0x11 is 0x02, any practical access to the register is only possible when
BATMON is activated. So this register is always read out as 0x22 in P_ON state. For details, refer to “Bat-
tery Monitor (BATMON)” on page 987.
3. While the reset value of register 0x30 is 0x00, any practical access to the register is only possible when the
radio transceiver is accessible. So the register is usually read out as:
z0x11 after a reset in P_ON state
z0x07 after a reset in any other state
Table 41-2. AT86RF233 Register Summary – Reset Values
Address Reset
Value
Address Reset
Value
Address Reset
Value
Address Reset
Value
0x00 0x00 0x10 0x00 0x20 0xFF 0x30 0x00
0x01 0x00 0x11 0x02 0x21 0xFF 0x31 0x00
0x02 0x00 0x12 0xF0 0x22 0xFF 0x32 0x00
0x03 0x09 0x13 0x00 0x23 0xFF 0x33 0x00
0x04 0x22 0x14 0x00 0x24 0x00 0x34 0x00
0x05 0x00 0x15 0x00 0x25 0x00 0x35 0x00
0x06 0x60 0x16 0xC1 0x26 0x00 0x36 0x00
0x07 0xFF 0x17 0x00 0x27 0x00 0x37 0x00
0x08 0x2B 0x18 0x58 0x28 0x00 0x38 0x00
0x09 0xC7 0x19 0x00 0x29 0x00 0x39 0x40
0x0A 0X37 0x1A 0x57 0x2A 0x00 0x3A 0x00
0x0B 0xA7 0x1B 0x20 0x2B 0x00 0x3B 0x00
0x0C 0x20 0x1C 0x0B 0x2C 0x38 0x3C 0x00
0x0D 0x00 0x1D 0x02 0x2D 0xEA 0x3D 0x00
0x0E 0x00 0x1E 0x1F 0x2E 0x42 0x3E 0x00
0x0F 0x00 0x1F 0x00 0x2F 0x53 0x3F 0x00
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42. Electrical Characteristics
42.1 Disclaimer
All typical values are measured at T = 25°C unless otherwise specified. All minimum and maximum values are valid
across operating temperature and voltage unless otherwise specified.
42.2 Absolute Maximum Ratings
Stresses beyond those listed in Table 42-1 may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Table 42-1. Absolute Maximum Ratings
Symbol Parameter Condition Min. Max. Units
VDD Power supply voltage 03.8 V
IVDD Current into a VDD pin -92 mA
IGND Current out of a GND pin -130 mA
VPIN
Pin voltage with respect to
GND and VDD
GND-0.3V VDD+0.3V V
VANA
Voltage on RFP, RFN,
AVDD and DVDD -0.3 2.0 V
VESD ESD robustness
Human Body Model (HBM) [4] 4 kV
Charged Device Model (CDM)
[5]550 V
PRF Input RF level +10 dBm
TLEAD Lead temperature
T = 10s
(soldering profile compliant with
IPC/JEDEC J STD 020B)
260 °C
Tstorage Storage temperature -60 150 °C
Caution! ESD sensitive device.
Precaution should be used when handling the device in order to prevent permanent damage.
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42.3 General Operating Ratings
The device must operate within the ratings listed in Table 42-2 in order for all other electrical characteristics and typical
characteristics of the device to be valid.
Notes: 1. With BOD33 disabled. If the BOD33 is enabled, check Table 42-17.
2. Even if an implementation uses the external 1.8V voltage supply VDD1.8 it is required to connect VDD.
3. AT86RF233 register 0x10 (VREG_CTRL) needs to be programmed to disable internal voltage regulators and sup-
ply blocks by an external 1.8V supply, refer to “Voltage Regulators (AVREG, DVREG)” on page 983.
Table 42-2. General Operating Conditions
Symbol Parameter Condition Min. Typ. Max. Units
VDD Power supply voltage Voltage on VDDIN, VDDIO and
VDDANA(2) 1.8(1) 3.3 3.6 V
VDD1.8
Power supply voltage
(on AVDD and DVDD) External supply voltage(3) 1.7 1.8 1.9 V
VDDANA Analog supply voltage 1.8(1) 3.3 3.6 V
TATemperature range -40 25 125 °C
TJJunction temperature - - 100 °C
1057
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42.4 Supply Characteristics
The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C, unless otherwise
specified and are valid for a junction temperature up to TJ = 100°C. Refer to “Power Supply and Start-Up Considerations”
on page 20.
Table 42-3. Supply Characteristics
Table 42-4. Supply Rise Rates
42.5 Maximum Clock Frequencies
Symbol Conditions
Voltage
Min. Max. Units
VDDIO
VDDIN
VDDANA
Full Voltage Range 1.8 3.6 V
Symbol Parameter
Rise Rate
UnitsMax.
VDDIO
VDDIN
VDDANA
DC supply peripheral I/Os, internal regulator and analog supply
voltage 0.1 V/µs
Table 42-5. Maximum GCLK Generator Output Frequencies
Symbol Description Conditions Max. Units
fGCLKGEN0 / fGCLK_MAIN
fGCLKGEN1
fGCLKGEN2
fGCLKGEN3
fGCLKGEN4
fGCLKGEN5
fGCLKGEN6
fGCLKGEN7
fGCLKGEN8
GCLK Generator Output
Frequency
Undivided 96 MHz
Divided 48 MHz
Table 42-6. Maximum Peripheral Clock Frequencies
Symbol Description Max. Units
fCPU CPU clock frequency 48 MHz
fAHB AHB clock frequency 48 MHz
fAPBA APBA clock frequency 48 MHz
fAPBB APBB clock frequency 48 MHz
fAPBC APBC clock frequency 48 MHz
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fGCLK_DFLL48M_REF DFLL48M Reference clock frequency 33 KHz
fGCLK_DPLL FDPLL96M Reference clock frequency 2MHz
fGCLK_DPLL_32K FDPLL96M 32k Reference clock frequency 32 KHz
fGCLK_WDT WDT input clock frequency 48 MHz
fGCLK_RTC RTC input clock frequency 48 MHz
fGCLK_EIC EIC input clock frequency 48 MHz
fGCLK_USB USB input clock frequency 48 MHz
fGCLK_EVSYS_CHANNEL_0 EVSYS channel 0 input clock frequency 48 MHz
fGCLK_EVSYS_CHANNEL_1 EVSYS channel 1 input clock frequency 48 MHz
fGCLK_EVSYS_CHANNEL_2 EVSYS channel 2 input clock frequency 48 MHz
fGCLK_EVSYS_CHANNEL_3 EVSYS channel 3 input clock frequency 48 MHz
fGCLK_EVSYS_CHANNEL_4 EVSYS channel 4 input clock frequency 48 MHz
fGCLK_EVSYS_CHANNEL_5 EVSYS channel 5 input clock frequency 48 MHz
fGCLK_EVSYS_CHANNEL_6 EVSYS channel 6 input clock frequency 48 MHz
fGCLK_EVSYS_CHANNEL_7 EVSYS channel 7 input clock frequency 48 MHz
fGCLK_EVSYS_CHANNEL_8 EVSYS channel 8 input clock frequency 48 MHz
fGCLK_EVSYS_CHANNEL_9 EVSYS channel 9 input clock frequency 48 MHz
fGCLK_EVSYS_CHANNEL_10 EVSYS channel 10 input clock frequency 48 MHz
fGCLK_EVSYS_CHANNEL_11 EVSYS channel 11 input clock frequency 48 MHz
fGCLK_SERCOMx_SLOW
Common SERCOM slow input clock
frequency 48 MHz
fGCLK_SERCOM0_CORE SERCOM0 input clock frequency 48 MHz
fGCLK_SERCOM1_CORE SERCOM1 input clock frequency 48 MHz
fGCLK_SERCOM2_CORE SERCOM2 input clock frequency 48 MHz
fGCLK_SERCOM3_CORE SERCOM3 input clock frequency 48 MHz
fGCLK_SERCOM4_CORE SERCOM4 input clock frequency 48 MHz
fGCLK_SERCOM5_CORE SERCOM5 input clock frequency 48 MHz
fGCLK_TCC0, GCLK_TCC1 TCC0,TCC1 input clock frequency 96 MHz
fGCLK_TCC2, GCLK_TC3 TCC2,TC3 input clock frequency 96 MHz
fGCLK_TC4, GCLK_TC5 TC4,TC5 input clock frequency 48 MHz
fGCLK_ADC ADC input clock frequency 48 MHz
Table 42-6. Maximum Peripheral Clock Frequencies (Continued)
Symbol Description Max. Units
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fGCLK_AC_DIG AC digital input clock frequency 48 MHz
fGCLK_AC_ANA AC analog input clock frequency 64 KHz
fGCLK_PTC PTC input clock frequency 48 MHz
Table 42-6. Maximum Peripheral Clock Frequencies (Continued)
Symbol Description Max. Units
1060
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42.6 Power Consumption
The values in are measured values of power consumption under the following conditions, except where noted:
zOperating conditions
zVVDDIN = 3.3V
zWake up time from sleep mode is measured from the edge of the wakeup signal to the execution of the first
instruction fetched in flash.
zOscillators
zXOSC (crystal oscillator) stopped
zXOSC32K (32kHz crystal oscillator) running with external 32kHz crystal
zDFLL48M using XOSC32K as reference and running at 48MHz
zClocks
zDFLL48M used as main clock source, except otherwise specified
zCPU, AHB clocks undivided
zAPBA clock divided by 4
zAPBB and APBC bridges off
zThe following AHB module clocks are running: NVMCTRL, APBA bridge
zAll other AHB clocks stopped
zThe following peripheral clocks running: PM, SYSCTRL, RTC
zAll other peripheral clocks stopped
zI/Os are inactive with internal pull-up
zCPU is running on flash with 1 wait states
zNVMCTRL cache enabled
zBOD33 disabled
zAT86RF233 has to be set in Deep Sleep
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Table 42-7. Current Consumption
Mode Conditions TAMin. Typ. Max. Units
ACTIVE
CPU running a While(1) algorithm
25°C 3.11 3.37 3.64
mA
85°C 3.24 3.48 3.76
CPU running a While(1) algorithm VDDIN=1.8V,
CPU is running on Flash with 3 wait states
25°C 3.10 3.36 3.64
85°C 3.24 3.48 3.75
CPU running a While(1) algorithm, CPU is
running on Flash with 3 wait states with
GCLKIN as reference
25°C 60*freq +
74
60*freq +
136
62*freq +
196 µA
(with freq
in MHz)
85°C 62*freq +
154
62*freq +
228
62*freq +
302
CPU running a Fibonacci algorithm
25°C 4.12 4.53 4.92
mA
85°C 4.27 4.63 4.98
CPU running a Fibonacci algorithm
VDDIN=1.8V, CPU is running on flash with 3
wait states
25°C 4.12 4.53 4.92
85°C 4.27 4.63 4.98
CPU running a Fibonacci algorithm, CPU is
running on Flash with 3 wait states with
GCLKIN as reference
25°C 86*freq +
76
88*freq +
136
88*freq +
196 µA
(with freq
in MHz)
85°C 88*freq +
156
88*freq +
230
88*freq +
302
CPU running a CoreMark algorithm
25°C 5.78 6.32 6.80
mA
85°C 5.93 6.47 7.00
CPU running a CoreMark algorithm
VDDIN=1.8V, CPU is running on flash with 3
wait states
25°C 5.17 5.60 5.96
85°C 5.35 5.73 6.10
CPU running a CoreMark algorithm, CPU is
running on Flash with 3 wait states with
GCLKIN as reference
25°C 106*freq +
78
106*freq +
136
108*freq +
196 µA
(with freq
in MHz)
85°C 106*freq +
154
108*freq +
232
108*freq +
310
IDLE0 Default operating conditions
25°C 1.89 2.04 2.20
mA
85°C 1.98 2.14 2.33
IDLE1
I
Default operating conditions 25°C 1.34 1.46 1.58
85°C 1.41 1.55 1.71
IDLE2
I
Default operating conditions 25°C 1.07 1.17 1.28
85°C 1.13 1.27 1.40
STANDBY
XOSC32K running
RTC running at 1kHz
25°C -4.06 12.8
µA
85°C -55.2 100
XOSC32K and RTC stopped
25°C -2.70 12.2
85°C -53.3 100
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Figure 42-1. Measurement Schematic
STANDBY
(SAMR21E19A)
XOSC32K running
RTC running at 1kHz
25°C -5.1 17.8
µA
85°C -60.2 105.0
XOSC32K and RTC stopped
25°C -3.7 17.2
85°C -58.3 105.0
Table 42-7. Current Consumption (Continued)
Mode Conditions TAMin. Typ. Max. Units
Table 42-8. Wake-up Time
Mode Conditions TAMin. Typ. Max. Units
IDLE0 OSC8M used as main clock source, Cache disabled
25°C -4.0 -
µs
85°C -4.0 -
IDLE1
I
OSC8M used as main clock source, Cache disabled
25°C -12.1 -
85°C -13.6 -
IDLE2
I
OSC8M used as main clock source, Cache disabled
25°C -13.0 -
85°C -14.5 -
STANDBY
I
OSC8M used as main clock source, Cache disabled
25°C -19.6 -
85°C -19.7 -
1063
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42.7 Peripheral Power Consumption
Since USB peripheral complies with the Universal Serial Bus (USB) v2.0 standard, USB peripheral power consumption is
described a specific section
42.7.1 All peripheral except USB
Default conditions, except where noted:
zOperating conditions
zVVDDIN = 3.3V
zOscillators
zXOSC (crystal oscillator) stopped
zXOSC32K (32kHz crystal oscillator) running with external 32kHz crystal
zOSC8M at 8MHz
zClocks
zOSC8M used as main clock source
zCPU, AHB and APBn clocks undivided
zThe following AHB module clocks are running: NVMCTRL, HPB2 bridge, HPB1 bridge, HPB0 bridge
zAll other AHB clocks stopped
zThe following peripheral clocks running: PM, SYSCTRL
zAll other peripheral clocks stopped
zI/Os are inactive with internal pull-up
zCPU in IDLE0 mode
zCache enabled
zBOD33 disabled
In this default conditions, the power consumption Idefault is measured.
Operating mode for each peripheral in turn:
zConfigure and enable the peripheral GCLK (When relevant, see conditions)
zUnmask the peripheral clock
zEnable the peripheral (when relevant)
zSet CPU in IDLE0 mode
zMeasurement Iperiph
zWake-up CPU via EIC (async: level detection, filtering disabled)
zDisable the peripheral (when relevant)
zMask the peripheral clock
zDisable the peripheral GCLK (when relevant, see conditions)
Each peripheral power consumption provided in table x.y is the value (Iperiph - Idefault), using the same measurement
method as for global power consumption measurement
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Notes: 1. All TCs from 4 to 7 share the same power consumption values.
2. All SERCOMs from 0 to 5 share the same power consumption values.
3. The value includes the power consumption of the R/W access to the RAM.
42.7.2 USB Peripheral Power Consumption
Default conditions, except where noted:
zOperating conditions
zVVDDIN = 3.3V
zOscillators
zXOSC32K (32kHz crystal oscillator) running with external 32kHz crystal in USB Host mode
zClocks
zUSB Device mode: DFLL48M in USB recovery mode (Crystal less)
zUSB Host mode: DFLL48M in closed loop with XOSC32K (32kHz crystal oscillator) running with external
32kHz crystal
zCPU, AHB and APBn clocks undivided
zThe following AHB module clocks are running: NVMCTRL, HPB2 bridge, HPB1 bridge, HPB0 bridge
zAll other AHB clocks stopped
zI/Os are inactive with internal pull-up
zCPU in IDLE0 mode
zCache enabled
zBOD33 disabled
In this default conditions, the power consumption Idefault is measured.
Table 42-9. Typical Peripheral Current Consumption
Peripheral Conditions Typ. Units
RTC fGCLK_RTC = 32kHz, 32bit counter mode 7.4 µA
WDT fGCLK_WDT=32kHz, normal mode with EW 5.5 µA
AC Both fGCLK=8MHz, Enable both COMP 31.3 µA
TCx(1) fGCLK=8MHz, Enable + COUNTER in 8bit mode 50 µA
TCC2 fGCLK=8MHz, Enable + COUNTER 95.5 µA
TCC1 fGCLK=8MHz, Enable + COUNTER 167.5 µA
TCC0 fGCLK=8MHz, Enable + COUNTER 180.3 µA
SERCOMx.
I2CM(2) fGCLK=8MHz, Enable 69.7 µA
SERCOMx.
I2CS fGCLK=8MHz, Enable 29.2 µA
SERCOMx.
SPI fGCLK=8MHz, Enable 64.6 µA
SERCOMx.
USART fGCLK=8MHz, Enable 65.5 µA
DMAC(3) RAM to RAM transfer 399.5 µA
1065
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Measurements do not include consumption of clock source (ex: DFLL48M or FDPLL96M) and CPU. However no CPU
activity is required during all states (Suspend, IDLE, Data transfer).
Measurements have been done with an USB cable of 1.5m.
For USB Device mode, measurements include the maximum consumption (200 µA) through pull-up resistor on the D+
line for USB attach. This value depends on USB Host characteristic.
Operating modes:
zRun the USB Device/Host states in regards of the Universal Serial Bus (USB) v2.0 standard.
USB power consumption is provided in the following tables.
Table 42-10. Typical USB Device Full Speed mode Current Consumption
USB Device state Conditions Typ. Units
Suspend GCLK_USB is off, using USB wakeup asynchronous interrupt.
USB bus in suspend mode. 201 μA
Suspend GCLK_USB is on.
USB bus in suspend mode. 0.83 mA
IDLE Start Of Frame is running.
No packet transferred. 1.17 mA
Active OUT Start Of Frame is running.
Bulk OUT on 100% bandwidth. 2.17 mA
Active IN Start Of Frame is running.
Bulk IN on 100% bandwidth. 10.3 mA
Table 42-11. Typical USB Host Full Speed mode Current Consumption
USB Device state Conditions Typ. Units
Wait connection GCLK_USB is off, using USB wakeup asynchronous interrupt.
USB bus not connected. 0.10 µA
Wait connection GCLK_USB is on.
USB bus not connected. 0.19 mA
Suspend GCLK_USB is off, using USB wakeup asynchronous interrupt.
USB bus in suspend mode. 201 μA
Suspend GCLK_USB is on.
USB bus in suspend mode. 0.83 mA
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IDLE Start Of Frame is running.
No packet transferred. 1.17 mA
Active OUT Start Of Frame is running.
Bulk OUT on 100% bandwidth. 2.17 mA
Active IN Start Of Frame is running.
Bulk IN on 100% bandwidth. 10.3 mA
Table 42-11. Typical USB Host Full Speed mode Current Consumption (Continued)
USB Device state Conditions Typ. Units
1067
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42.8 I/O Pin Characteristics
42.8.1 Normal I/O Pins
Note: 1. These values are based on simulation. These values are not covered by test limits in production or
characterization.
Table 42-12. Normal I/O Pins Characteristics
Symbol Parameter Conditions Min. Typ. Max. Units
RPULL Pull-up - Pull-down resistance
I
20 40 60 kΩ
VIL Input low-level voltage
VDD=1.8V-2.7V - - 0.25*VDD
V
VDD=2.7V-3.6V - - 0.3*VDD
VIH Input high-level voltage
VDD=1.8V-2.7V 0.7*VDD - -
VDD=2.7V-3.6V 0.55*VDD - -
VOL Output low-level voltage VDD>1.6V, IOL max
I
-0.1*VDD 0.2*VDD
VOH Output high-level voltage VDD>1.6V, IOH max
II
0.8*VDD 0.9*VDD -
IOL Output low-level current
VDD=1.8V-3V,
PORT.PINCFG.DRVSTR=0 - - 1
mA
VDD=3V-3.6V,
PORT.PINCFG.DRVSTR=0 - - 2.5
VDD=1.8V-3V,
PORT.PINCFG.DRVSTR=1 - - 3
VDD=3V-3.6V,
PORT.PINCFG.DRVSTR=1 - - 10
IOH Output high-level current
VDD=1.8V-3V,
PORT.PINCFG.DRVSTR=0 - - 0.70
VDD=3V-3.6V,
PORT.PINCFG.DRVSTR=0 - - 2
VDD=1.8V-3V,
PORT.PINCFG.DRVSTR=1 - - 2
VDD=3V-3.6V,
PORT.PINCFG.DRVSTR=1 - - 7
tRISE Rise time(1)
PORT.PINCFG.DRVSTR=0
load = 5pF, VDD = 3.3V - - 15
nS
PORT.PINCFG.DRVSTR=1
load = 20pF, VDD = 3.3V - - 15
tFALL Fall time(1)
PORT.PINCFG.DRVSTR=0
load = 5pF, VDD = 3.3V - - 15
nS
PORT.PINCFG.DRVSTR=1
load = 20pF, VDD = 3.3V - - 15
ILEAK Input leakage current Pull-up resistors disabled -1 +/-0.015 1µA
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42.8.2 I2C Pins
Refer to “I/O Multiplexing and Considerations” on page 12 to get the list of I2C pins.
I2C pins timing characteristics can be found in “SERCOM in I2C Mode Timing” on page 1098.
42.8.3 XOSC Pin
XOSC pins behave as normal pins when used as normal I/Os. Refer to table “Normal I/O Pins Characteristics”.
42.8.4 XOSC32 Pin
XOSC32 pins behave as normal pins when used as normal I/Os. Refer to table “Normal I/O Pins Characteristics”.
42.8.5 External Reset Pin
Reset pin has the same electrical characteristics as normal I/O pins. Refer to table “Normal I/O Pins Characteristics”.
Table 42-13. I2C Pins Characteristics in I2C configuration
Symbol Parameter Condition Min. Typ. Max. Units
RPULL Pull-up - Pull-down resistance
I
20 40 60 kΩ
VIL Input low-level voltage
VDD=1.8V-2.7V
I
- - 0.25*VDD
V
VDD=2.7V-3.6V - - 0.3*VDD
VIH Input high-level voltage
VDD=1.8V-2.7V 0.7*VDD - -
VDD=2.7V-3.6V
I
0.55*VDD - -
VHYS Hysteresis of Schmitt trigger inputs 0.08*VDD - -
VOL Output low-level voltage
VDD> 2.0V
I,
IOL=3mA - - 0.4
VDD≤2.0V
IOL=2mA - - 0.2*VDD
CICapacitance for each I/O Pin
I
pF
IOL Output low-level current
VOL =0.4V
Standard, Fast
and HS Modes
3
mA
VOL =0.4V
Fast Mode + 20 - -
VOL =0.6V 6 - -
fSCL SCL clock frequency
I
- - 3.4 MHz
RPValue of pull-up resistor
fSCL ≤ 100kHz
Ω
fSCL > 100kHz
1069
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42.9 Analog Characteristics
42.9.1 Voltage Regulator Characteristics
Table 42-14. Voltage Regulator Electrical Characteristics
Note: Supplying any external components using VDDCORE pin is not allowed to assure the integrity of the core supply
voltage.
Table 42-15. Decoupling requirements
42.9.2 Power-On Reset (POR) Characteristics
Table 42-16. POR Characteristics
Symbol Parameter Conditions Min. Typ. Max. Units
VDDCORE DC calibrated output voltage Voltage regulator
normal mode 1.1 1.23 1.30 V
Symbol Parameter Conditions Min. Typ. Max. Units
CIN
Input regulator capacitor,
between VDDIN and GND
I
- 1 - µF
COUT
Output regulator capacitor,
between VDDCORE and GND 0.8 1 - µF
Symbol Parameter Conditions Min. Typ. Max. Units
VPOT+
Voltage threshold on VDD
rising
I
VDD falls at 1V/ms or slower
1.27 1.45 1.58 V
VPOT-
Voltage threshold on VDD
falling 0.72 0.99 1.32 V
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Figure 42-2. POR Operating Principle
42.9.3 Brown-Out Detectors Characteristics
42.9.3.1 BOD33
Figure 42-3. BOD33 Hysteresis OFF
Figure 42-4. BOD33 Hysteresis ON
Reset VDD
V
POT+
V
Time
POT-
VCC
RESET
VBOD
VCC
RESET
VBOD-
VBOD+
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Table 42-17. BOD33 LEVEL Value
Note: See chapter Memories table “NVM User Row Mapping” on page 25 for the BOD33 default value settings.
Table 42-18. BOD33 Characteristics
Note: 1. These values are based on simulation. These values are not covered by test limits in production or
characterization.
Symbol BOD33.LEVEL Conditions Min. Typ. Max. Units
VBOD+
6
Hysteresis ON
-1.715 1.745
V
7 - 1.750 1.779
39 -2.84 2.92
48 -3.2 3.3
VBOD-
or
VBOD
6
Hysteresis ON
or
Hysteresis OFF
1.62 1.64 1.67
71.64 1.675 1.71
39 2.72 2.77 2.81
48 3.0 3.07 3.2
Symbol Parameter Conditions Temp. Min. Typ. Max. Units
I
Step size, between
adjacent values in
BOD33.LEVEL
I
-34 -mV
VHYST VBOD+ - VBOD- Hysteresis ON 35 -170 mV
tDET Detection time
Time with
VDDANA < VTH
necessary to
generate a reset
signal
-0.9(1) -µs
tSTARTUP Startup time
I
-40 to 85°C -2.2(1) -µs
IIdleBOD33
Current
consumption in
Active/Idle Mode
Continuous mode
25°C 25 48
µA
-40 to 85°C - - 50
Sampling mode
25°C -0.034 0.21
-40 to 85°C - - 1.62
ISbyBOD33
Current
Consumption in
Standby mode
Sampling mode
25°C -0.132 0.38
µA
-40 to 85°C - - 1
1072
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
42.9.4 Analog-to-Digital (ADC) Characteristics
Notes: 1. These values are based on characterization. These values are not covered by test limits in production.
2. These values are based on simulation. These values are not covered by test limits in production or
characterization.
3. In this condition and for a sample rate of 350ksps, 1 Conversion at gain 1x takes 6 clock cycles of the ADC
clock.
Table 42-19. Operating Conditions
Symbol Parameter Conditions Min. Typ. Max. Units
RES Resolution
I
8 - 12 bits
fCLK_ADC ADC Clock frequency
I
30 -2100 kHz
Conversion speed 10 1000 ksps
Sample rate(1) Single shot 5 - 300 ksps
Free running 5 - 350 ksps
Sampling time(1) 0.5 - - cycles
Conversion time(1) 1x Gain 6 - - cycles
VREF Voltage reference range 1.0 - VDDANA-0.6 V
VREFINT1V Internal 1V reference (2) -1.0 - V
VREFINTVCC0
Internal ratiometric
reference 0(2) - VDDANA/1.48 - V
VREFINTVCC0
Voltage Error
Internal ratiometric
reference 0(2) error
2.0V <
VDDANA<3.63V -1.0 -+1.0 %
VREFINTVCC1
Internal ratiometric
reference 1(2) VDDANA>2.0V - VDDANA/2 - V
VREFINTVCC1
Voltage Error
Internal ratiometric
reference 1(2) error
2.0V <
VDDANA<3.63V -1.0 -+1.0 %
Conversion range(1) Differential mode -VREF/GAIN -+VREF/GAIN V
Single-ended mode 0.0 -+VREF/GAIN V
CSAMPLE Sampling capacitance(2) -3.5 -pF
RSAMPLE
Input channel source
resistance(2) - - 3.5 kΩ
IDD DC supply current(1) fCLK_ADC = 2.1MHz
I
(3) -1.25 1.79 mA
1073
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Notes: 1. Maximum numbers are based on characterization and not tested in production, and valid for 5% to 95% of the input
voltage range.
2. Dynamic parameter numbers are based on characterization and not tested in production.
3. Respect the input common mode voltage through the following equations (where VCM_IN is the Input channel com-
mon mode voltage):
a. If |VIN| > VREF/4
zVCM_IN < 0.95*VDDANA + VREF/4 – 0.75V
zVCM_IN > VREF/4 -0.05*VDDANA -0.1V
b. If |VIN| < VREF/4
zVCM_IN < 1.2*VDDANA - 0.75V
zVCM_IN > 0.2*VDDANA - 0.1V
4. The ADC channels on pins PA08, PA09 are powered from the VDDIO power supply. The ADC performance of these
pins will not be the same as all the other ADC channels on pins powered from the VDDANA power supply.
5. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x 100) /
(2*Vref/GAIN)
Table 42-20. Differential Mode
Symbol Parameter Conditions Min. Typ. Max. Units
ENOB Effective Number Of Bits With gain compensation -10.5 11.1 bits
TUE Total Unadjusted Error
I
1x Gain
n
1.5 4.3 15.0 LSB
INL
I
Integral Non Linearity 1x Gain
n
1.0 1.3 4.5 LSB
DNL Differential Non Linearity 1x Gain
n
+/-0.3 +/-0.5 +/-0.95 LSB
I
I
I
Gain Error
Ext. Ref 1x -10.0 2.5 +10.0 mV
VREF=VDDANA/1.48 -15.0 -1.5 +10.0 mV
Bandgap -20.0 -5.0 +20.0 mV
Gain Accuracy(5) Ext. Ref. 0.5x +/-0.1 +/-0.2 +/-0.45 %
Ext. Ref. 2x to 16x +/-0.05 +/-0.1 +/-0.11 %
Offset Error
Ext. Ref. 1x -5.0 -1.5 +5.0 mV
VREF=VDDANA/1.48 -5.0 0.5 +5.0 mV
Bandgap -5.0 3.0 +5.0 mV
SFDR Spurious Free Dynamic Range 1x Gain
FCLK_ADC = 2.1MHz
FIN = 40kHz
AIN = 95%FSR
62.7 70.0 75.0 dB
SINAD Signal-to-Noise and Distortion 54.1 65.0 68.5 dB
SNR Signal-to-Noise Ratio 54.5 65.5 68.6 dB
THD Total Harmonic Distortion -77.0 -64.0 -63.0 dB
Noise RMS T=25°C 0.6 1.0 1.6 mV
1074
Atmel | SMART SAM R21 [DATASHEET]
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Notes: 1. Maximum numbers are based on characterization and not tested in production, and for 5% to 95% of the input voltage
range.
2. Respect the input common mode voltage through the following equations (where VCM_IN is the Input channel com-
mon mode voltage) for all VIN:
zVCM_IN < 0.7*VDDANA + VREF/4 – 0.75V
zVCM_IN > VREF/4 – 0.3*VDDANA - 0.1V
3. The ADC channels on pins PA08, PA09 are powered from the VDDIO power supply. The ADC performance of these
pins will not be the same as all the other ADC channels on pins powered from the VDDANA power supply.
4. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x 100) /
(Vref/GAIN)
42.9.4.1 Performance with the Averaging Digital Feature
Averaging is a feature which increases the sample accuracy. ADC automatically computes an average value of multiple
consecutive conversions. The numbers of samples to be averaged is specified by the Number-of-Samples-to-be-
collected bit group in the Average Control register (AVGCTRL.SAMPLENUM[3:0]) and the averaged output is available
in the Result register (RESULT).
Table 42-21. Single-Ended Mode
Symbol Parameter Conditions Min. Typ. Max. Units
ENOB Effective Number of Bits With gain compensation -9.5 9.8 Bits
TUE Total Unadjusted Error 1x gain -10.5 14.0 LSB
INL Integral Non-Linearity 1x gain 1.0 1.6 3.5 LSB
DNL Differential Non-Linearity 1x gain +/-0.5 +/-0.6 +/-0.95 LSB
Gain Error Ext. Ref. 1x -5.0 0.7 +5.0 mV
Gain Accuracy(4) Ext. Ref. 0.5x +/-0.2 +/-0.34 +/-0.4 %
Ext. Ref. 2x to 16X +/-0.01 +/-0.1 +/-0.2 %
Offset Error Ext. Ref. 1x -5.0 1.5 +5.0 mV
SFDR Spurious Free Dynamic Range 1x Gain
FCLK_ADC = 2.1MHz
FIN = 40kHz
AIN = 95%FSR
63.1 65.0 67.0 dB
SINAD Signal-to-Noise and Distortion 47.5 59.5 61.0 dB
SNR Signal-to-Noise Ratio 48.0 60.0 64.0 dB
THD Total Harmonic Distortion -65.4 -63.0 -62.1 dB
Noise RMS T = 25°C -1.0 -mV
Table 42-22. Averaging Feature
Average
Number Conditions SNR (dB) SINAD (dB) SFDR (dB)
ENOB
(bits)
1
In differential mode, 1x gain,
VDDANA=3.0V, VREF=1.0V, 350kSps at
25°C
66.0 65.0 72.8 9.75
867.6 65.8 75.1 10.62
32 69.7 67.1 75.3 10.85
128 70.4 67.5 75.5 10.91
1075
Atmel | SMART SAM R21 [DATASHEET]
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42.9.4.2 Performance with the hardware offset and gain correction
Inherent gain and offset errors affect the absolute accuracy of the ADC. The offset error cancellation is handled by the
Offset Correction register (OFFSETCORR) and the gain error cancellation, by the Gain Correction register
(GAINCORR). The offset and gain correction value is subtracted from the converted data before writing the Result
register (RESULT).
Table 42-23. Offset and Gain correction feature
42.9.4.3 Inputs and Sample and Hold Acquisition Times
The analog voltage source must be able to charge the sample and hold (S/H) capacitor in the ADC in order to achieve
maximum accuracy. Seen externally the ADC input consists of a resistor ( ) and a capacitor ( ). In
addition, the source resistance ( ) must be taken into account when calculating the required sample and hold
time. Figure 42-5 shows the ADC input channel equivalent circuit.
Figure 42-5. ADC Input
To achieve n bits of accuracy, the capacitor must be charged at least to a voltage of
Gain Factor Conditions
Offset Error
(mV)
Gain Error
(mV)
Total Unadjusted Error
(LSB)
0.5x
In differential mode, 1x gain,
VDDANA=3.0V, VREF=1.0V, 350kSps
at 25°C
0.25 1.0 2.4
1x 0.20 0.10 1.5
2x 0.15 -0.15 2.7
8x -0.05 0.05 3.2
16x 0.10 -0.05 6.1
RSAMPLE
CSAMPLE
RSOURCE
RSOURCE RSAMPLE
Analog Input
AINx CSAMPLE
VIN
VDDANA/2
CSAMPLE
VCSAMPLE V≥IN 12
n1+()–
–()×
1076
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
The minimum sampling time for a given can be found using this formula:
for a 12 bits accuracy:
where
Table 42-24. Clock and Timing(1)
Note: 1. These values are based on simulation. These values are not covered by test limits in production or
characterization.
Symbol Parameter Conditions Min. Typ. Max. Units
Conversion rate Cload=100pF
Rload > 5kΩ
Normal mode - - 350
ksps
For ΔDATA=+/-1 - - 1000
I
Startup time
VDDNA > 2.6V - - 2.85 µs
VDDNA < 2.6V - - 10 µs
tSAMPLEHOLD
RSOURCE
tSAMPLEHOLD RSAMPLE R+SOURCE
()CSAMPLE
()×n1+() 2()ln××≥
tSAMPLEHOLD RSAMPLE R+SOURCE
()CSAMPLE
()×9.02×≥
tSAMPLEHOLD
1
2fADC
×
---------------------
=
1077
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Note: 1. All values measured using a conversion rate of 350ksps.
Table 42-25. Accuracy Characteristics(1)
Symbol Parameter Conditions Min. Typ. Max. Units
RES Input resolution
I
- - 10 Bits
INL Integral non-linearity
VREF= Ext 1.0V
VDD = 1.6V 0.75 1.1 2.5
LSB
VDD = 3.6V 0.6 1.2 1.5
VREF = VDDANA
VDD = 1.6V 1.4 2.2 2.5
VDD = 3.6V 0.9 1.4 1.5
VREF= INT1V
VDD = 1.6V 0.75 1.3 1.5
VDD = 3.6V 0.8 1.2 1.5
DNL Differential non-linearity
VREF= Ext 1.0V
VDD = 1.6V +/-0.9 +/-1.2 +/-1.5
LSB
VDD = 3.6V +/-0.9 +/-1.1 +/-1.2
VREF= VDDANA
VDD = 1.6V +/-1.1 +/-1.5 +/-1.7
VDD = 3.6V +/-1.0 +/-1.1 +/-1.2
VREF= INT1V
VDD = 1.6V +/-1.1 +/-1.4 +/-1.5
VDD = 3.6V +/-1.0 +/-1.5 +/-1.6
I
Gain error Ext. VREF +/-1.5 +/-5 +/-10 mV
I
Offset error Ext. VREF +/-2 +/-3 +/-6 mV
1078
Atmel | SMART SAM R21 [DATASHEET]
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42.9.5 Analog Comparator Characteristics
Notes: 1. According to the standard equation V(X)=VLSB*(X+1); VLSB=VDDANA/64
2. Data computed with the Best Fit method
3. Data computed using histogram
42.9.6 Internal 1.1V Bandgap Reference Characteristics
Table 42-27. Bandgap and Internal 1.1V reference characteristics
Table 42-26. Electrical and Timing
Symbol Parameter Conditions Min. Typ. Max. Units
I
Positive input voltage
range
I
0 - VDDANA
V
I
Negative input voltage
range
I
0 - VDDANA
I
Offset
Hysteresis = 0, Fast mode -15 0.0 +15 mV
Hysteresis = 0, Low power mode -25 0.0 +25 mV
Hysteresis
Hysteresis = 1, Fast mode 20 50 80 mV
Hysteresis = 1, Low power mode 15 40 75 mV
Propagation delay
Changes for VACM=VDDANA/2
100mV overdrive, Fast mode -60 116 ns
Changes for VACM=VDDANA/2
100mV overdrive, Low power
mode
-225 370 ns
tSTARTUP Startup time
Enable to ready delay
Fast mode - 1 2 µs
Enable to ready delay
Low power mode -12 19 µs
VSCALE
INL(3) -1.4 0.75 +1.4 LSB
DNL(3) -0.9 0.25 +0.9 LSB
Offset Error (1)(2) -0.200 0.260 +0.920 LSB
Gain Error (1)(2) -0.89 0.215 0.89 LSB
Symbol Parameter Conditions Min. Typ. Max. Units
INT1V Internal 1.1V Bandgap
reference
After calibration at T= 25°C,
over [-40, +85]C 1.08 1.1 1.12 V
Over voltage at 25°C 1.09 1.1 1.11 V
1079
Atmel | SMART SAM R21 [DATASHEET]
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42.9.7 Temperature Sensor Characteristics
42.9.7.1 Temperature Sensor Characteristics
Note: 1. These values are based on characterization. These values are not covered by test limits in production.
42.9.7.2 Software-based Refinement of the Actual Temperature
The temperature sensor behavior is linear but it depends on several parameters such as the internal voltage reference
which itself depends on the temperature. To take this into account, each device contains a Temperature Log row with
data measured and written during the production tests. These calibration values should be read by software to infer the
most accurate temperature readings possible.
This Software Temperature Log row can be read at address 0x00806030
This section specifies the Temperature Log row content and explains how to refine the temperature sensor output using
the values in the Temperature Log row.
Temperature Log Row
All values in this row were measured in the following conditions:
zVDDIN = VDDIO = VDDANA = 3.3V
zADC Clock speed = 1MHz
zADC mode: Free running mode, ADC averaging mode with 4 averaged samples
zADC voltage reference = 1.0V internal reference (INT1V)
zADC input = temperature sensor
Table 42-28. Temperature Sensor Characteristics(1)
Symbol Parameter Conditions Min. Typ. Max. Units
I
Temperature sensor output
voltage T= 25°C, VDDANA = 3.3V -0.667 - V
I
Temperature sensor slope 2.3 2.4 2.5 mV/°C
I
Variation over VDDANA voltage VDDANA=1.8V to 3.6V -1.7 13.7 mV/V
I
Temperature Sensor
accuracy
Using the method described in
the “Software-based
Refinement of the Actual
Temperature” on page 1079
-10 -10 °C
1080
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
The temperature sensor values are logged during test production flow for Room and Hot insertions:
zROOM_TEMP_VAL_INT and ROOM_TEMP_VAL_DEC contains the measured temperature at room
insertion (e.g. for ROOM_TEMP_VAL_INT=25 and ROOM_TEMP_VAL_DEC=2, the measured
temperature at room insertion is 25.2°C).
zHOT_TEMP_VAL_INT and HOT_TEMP_VAL_DEC contains the measured temperature at hot insertion
(e.g. for HOT_TEMP_VAL_INT=83 and HOT_TEMP_VAL_DEC=3, the measured temperature at room
insertion is 83.3°C).
The temperature log row also contains the corresponding 12bit ADC conversions of both Room and Hot temperatures:
zROOM_ADC_VAL contains the 12bit ADC value corresponding to (ROOM_TEMP_VAL_INT,
ROOM_TEMP_VAL_DEC)
zHOT_ADC_VAL contains the 12bit ADC value corresponding to (HOT_TEMP_VAL_INT,
HOT_TEMP_VAL_DEC)
The temperature log row also contains the corresponding 1V internal reference of both Room and Hot temperatures:
zROOM_INT1V_VAL is the 2’s complement of the internal 1V reference value corresponding to
(ROOM_TEMP_VAL_INT, ROOM_TEMP_VAL_DEC)
zHOT_INT1V_VAL is the 2’s complement of the internal 1V reference value corresponding to
(HOT_TEMP_VAL_INT, HOT_TEMP_VAL_DEC)
zROOM_INT1V_VAL and HOT_INT1V_VAL values are centered around 1V with a 0.001V step. In other
words, the range of values [0,127] corresponds to [1V, 0.873V] and the range of values [-1, -127]
corresponds to [1.001V, 1.127V]. INT1V == 1 - (VAL/1000) is valid for both ranges.
Using Linear Interpolation
For concise equations, we’ll use the following notations:
z(ROOM_TEMP_VAL_INT, ROOM_TEMP_VAL_DEC) is denoted tempR
z(HOT_TEMP_VAL_INT, HOT_TEMP_VAL_DEC) is denoted tempH
zROOM_ADC_VAL is denoted ADCR, its conversion to Volt is denoted VADCR
zHOT_ADC_VAL is denoted ADCH, its conversion to Volt is denoted VADCH
Table 42-29. Temperature Log Row Content
Bit Position Name Description
7:0 ROOM_TEMP_VAL_INT Integer part of room temperature in °C
11:8 ROOM_TEMP_VAL_DEC Decimal part of room temperature
19:12 HOT_TEMP_VAL_INT Integer part of hot temperature in °C
23:20 HOT_TEMP_VAL_DEC Decimal part of hot temperature
31:24 ROOM_INT1V_VAL 2’s complement of the internal 1V reference drift at room
temperature (versus a 1.0 centered value)
39:32 HOT_INT1V_VAL 2’s complement of the internal 1V reference drift at hot
temperature (versus a 1.0 centered value)
51:40 ROOM_ADC_VAL 12bit ADC conversion at room temperature
63:52 HOT_ADC_VAL 12bit ADC conversion at hot temperature
1081
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
zROOM_INT1V_VAL is denoted INT1VR
zHOT_INT1V_VAL is denoted INT1VH
Using the (tempR, ADCR) and (tempH, ADCH) points, using a linear interpolation we have the following equation:
Given a temperature sensor ADC conversion value ADCm, we can infer a coarse value of the temperature tempC as:
[Equation 1]
Notes: 1. In the previous expression, we’ve added the conversion of the ADC register value to be expressed in V.
2. This is a coarse value because we assume INT1V=1V for this ADC conversion.
Using the (tempR, INT1VR) and (tempH, INT1VH) points, using a linear interpolation we have the following equation:
Then using the coarse temperature value, we can infer a closer to reality INT1V value during the ADC conversion as:
Back to [Equation 1], we replace INT1V=1V by INT1V = INT1Vm, we can then deduce a finer temperature value as:
[Equation 1bis]
VADC VADCR
–
temp tempR
–
-------------------------------------
⎝⎠
⎛⎞
VADCH VADCR
–
tempHtempR
–
----------------------------------------
⎝⎠
⎛⎞
=
tempCtempR
ADCm
1
212 1–()
---------------------
⋅
⎝⎠
⎛⎞
ADCR
INT1VR
212 1–()
---------------------
⋅
⎝⎠
⎜⎟
⎛⎞
–
⎩⎭
⎨⎬
⎧⎫
tempHtempR
–()⋅
ADCH
INT1VH
212 1–()
---------------------
⋅
⎝⎠
⎜⎟
⎛⎞
ADCR
INT1VR
212 1–()
---------------------
⋅
⎝⎠
⎜⎟
⎛⎞
–
⎩⎭
⎨⎬
⎧⎫
------------------------------------------------------------------------------------------------------------------------------------------------------------
+=
INT1VINT1VR
–
temp tempR
–
-------------------------------------------
⎝⎠
⎛⎞
INT1VHINT1VR
–
tempHtempR
–
-----------------------------------------------
⎝⎠
⎛⎞
=
INT1VmINT1VR
INT1VHINT1VR
–()tempCtempR
–()⋅
tempHtempR
–()
---------------------------------------------------------------------------------------------------
⎝⎠
⎛⎞
+=
tempftempR
ADCm
INT1Vm
212 1–()
---------------------
⋅
⎝⎠
⎜⎟
⎛⎞
ADCR
INT1VR
212 1–()
---------------------
⋅
⎝⎠
⎜⎟
⎛⎞
–
⎩⎭
⎨⎬
⎧⎫
tempHtempR
⋅()⋅
ADCH
INT1VH
212 1–()
---------------------
⋅
⎝⎠
⎜⎟
⎛⎞
ADCR
INT1VR
212 1–()
---------------------
⋅
⎝⎠
⎜⎟
⎛⎞
–
⎩⎭
⎨⎬
⎧⎫
----------------------------------------------------------------------------------------------------------------------------------------------------------
+=
1082
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
42.10 NVM Characteristics
Table 42-30. Maximum Operating Frequency
Note that on this flash technology, a max number of 8 consecutive write is allowed per row. Once this number is reached,
a row erase is mandatory.
Table 42-31. Flash Endurance and Data Retention
Note: 1. An endurance cycle is a write and an erase operation.
Table 42-32. EEPROM Emulation(1) Endurance and Data Retention
Notes: 1. The EEPROM emulation is a software emulation described in the App note AT03265.
2. An endurance cycle is a write and an erase operation.
VDD range NVM Wait States Maximum Operating Frequency Units
1.8V to 2.7V
014
MHz
128
242
348
2.7V to 3.6V
024
148
Symbol Parameter Conditions Min. Typ. Max. Units
RetNVM25k Retention after up to 25k Average ambient 55°C 10 50 -Years
RetNVM2.5k Retention after up to 2.5k Average ambient 55°C 20 100 -Years
RetNVM100 Retention after up to 100 Average ambient 55°C 25 >100 -Years
CycNVM Cycling Endurance(1) -40°C < Ta < 85°C 25k 150k -Cycles
Symbol Parameter Conditions Min. Typ. Max. Units
RetEEPROM100k Retention after up to 100k Average ambient 55°C 10 50 -Years
RetEEPROM10k Retention after up to 10k Average ambient 55°C 20 100 -Years
CycEEPROM Cycling Endurance(2) -40°C < Ta < 85°C 100k 600k -Cycles
Table 42-33. NVM Characteristics
Symbol Parameter Conditions Min. Typ. Max. Units
tFPP Page programming time - - - 2.5 ms
tFRE Row erase time
I
- - - 6 ms
tFCE
DSU chip erase time
(CHIP_ERASE) - - - 240 ms
1083
Atmel | SMART SAM R21 [DATASHEET]
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42.11 Oscillators Characteristics
42.11.1 Crystal Oscillator (XOSC) Characteristics
42.11.1.1 Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN.
Table 42-34. Digital Clock Characteristics
42.11.1.2 Crystal Oscillator Characteristics
The following table describes the characteristics for the oscillator when a crystal is connected between XIN and XOUT as
shown in Figure 42-6. The user must choose a crystal oscillator where the crystal load capacitance CL is within the range
given in the table. The exact value of CL can be found in the crystal datasheet. The capacitance of the external capacitors
(CLEXT) can then be computed as follows:
where CSTRAY is the capacitance of the pins and PCB, CSHUNT is the shunt capacitance of the crystal.
Symbol Parameter Conditions Min. Typ. Max. Units
fCPXIN XIN clock frequency
I
- - 32 MHz
Table 42-35. Crystal Oscillator Characteristics
Symbol Parameter Conditions Min. Typ. Max. Units
fOUT Crystal oscillator frequency
I
0.4 -32 MHz
ESR
Crystal Equivalent Series
Resistance
Safety Factor = 3
The AGC doesn’t have any
noticeable impact on these
measurements.
f = 0.455MHz, CL = 100pF
XOSC.GAIN = 0 - - 5.6K
Ω
f = 2MHz, CL = 20pF
XOSC.GAIN = 0 - - 416
f = 4MHz, CL = 20pF
XOSC.GAIN = 1 - - 243
f = 8MHz, CL = 20pF
XOSC.GAIN = 2 - - 138
f = 16MHz, CL = 20pF
XOSC.GAIN = 3 - - 66
f = 32MHz, CL = 18pF
XOSC.GAIN = 4 - - 56
CXIN Parasitic capacitor load
I
-5.9 -pF
CXOUT Parasitic capacitor load -3.2 -pF
CLEXT 2C
LCSTRAY CSHUNT
––()=
1084
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Figure 42-6. Oscillator Connection
IXOSC Current Consumption
f = 2MHz, CL = 20pF, AGC off 27 65 85
µA
f = 2MHz, CL = 20pF, AGC on 14 52 73
f = 4MHz, CL = 20pF, AGC off 61 117 150
f = 4MHz, CL = 20pF, AGC on 23 74 100
f = 8MHz, CL = 20pF, AGC off 131 226 296
f = 8MHz, CL = 20pF, AGC on 56 128 172
f = 16MHz, CL = 20pF, AGC off 305 502 687
f = 16MHz, CL = 20pF, AGC on 116 307 552
f = 32MHz, CL = 18pF, AGC off 1031 1622 2200
f = 32MHz, CL = 18pF, AGC on 278 615 1200
tSTARTUP Startup time
f = 2MHz, CL = 20pF,
XOSC.GAIN = 0, ESR = 600Ω-14K 48K
cycles
f = 4MHz, CL = 20pF,
XOSC.GAIN = 1, ESR = 100Ω-6800 19.5K
f = 8MHz, CL = 20pF,
XOSC.GAIN = 2, ESR = 35Ω-5550 13K
f = 16MHz, CL = 20pF,
XOSC.GAIN = 3, ESR = 25Ω-6750 14.5K
f = 32MHz, CL = 18pF,
XOSC.GAIN = 4, ESR = 40Ω-5.3K 9.6K
Table 42-35. Crystal Oscillator Characteristics (Continued)
Symbol Parameter Conditions Min. Typ. Max. Units
C
SHUNT
L
M
R
M
C
M
C
STRAY
C
LEXT
C
LEXT
Xin
Crystal
Xout
1085
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
42.11.2 External 32kHz Crystal Oscillator (XOSC32K) Characteristics
42.11.2.1 Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN32 pin.
Table 42-36. Digital Clock Characteristics
42.11.2.2 Crystal Oscillator Characteristics
Figure 42-6 and the equation in “Crystal Oscillator Characteristics” on page 1083 also applies to the 32kHz oscillator
connection. The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in
the table. The exact value of CL can be found in the crystal datasheet.
Symbol Parameter Conditions Min. Typ. Max. Units
fCPXIN32 XIN32 clock frequency
I
-32.768 -kHz
I
XIN32 clock duty cycle
I
-50 - %
Table 42-37. 32kHz Crystal Oscillator Characteristics
Symbol Parameter Conditions Min. Typ. Max. Units
fOUT Crystal oscillator frequency
I
-32768 -Hz
tSTARTUP Startup time ESRXTAL = 39.9kΩ, CL = 12.5pF -28K 30K cycles
CLCrystal load capacitance
I
- - 12.5
pF
CSHUNT Crystal shunt capacitance
I
-0.1 -
CXIN32 Parasitic capacitor load
TQFP64/48/32 packages
-3.1 -
CXOUT32 Parasitic capacitor load -3.3 -
IXOSC32K Current consumption -1.22 2.19 µA
ESR
Crystal equivalent series
resistance f=32.768kHz
Safety Factor = 3
CL=12.5pF - - 141 kΩ
1086
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
42.11.3 Digital Frequency Locked Loop (DFLL48M) Characteristics
Table 42-39. DFLL48M Characteristics - Open Loop Mode(1)
Note: 1. DFLL48M in Open loop after calibration at room temperature.
Table 42-38. 32kHz Crystal Oscillator Characteristics
Symbol Parameter Conditions Min. Typ. Max. Units
fOUT Crystal oscillator frequency
I
-32768 -Hz
tSTARTUP Startup time ESRXTAL = 39.9kΩ, CL = 12.5pF -28K 30K cycles
CLCrystal load capacitance
I
- - 12.5
pF
CSHUNT Crystal shunt capacitance
I
-0.1 -
CXIN32 Parasitic capacitor load
TQFP64/48/32 packages
-3.2 -
CXOUT32 Parasitic capacitor load -3.7 -
IXOSC32K Current consumption -1.22 2.19 µA
ESR
Crystal equivalent series
resistance f=32.768kHz
Safety Factor = 3
CL=12.5pF - - 100 kΩ
Symbol Parameter Conditions Min. Typ. Max. Units
fOUT Output frequency
I
DFLLVAL.COARSE =
DFLL48M COARSE CAL
DFLLVAL.FINE = 512
47 48 49 MHz
IDFLL Power consumption on VDDIN
I
DFLLVAL.COARSE =
DFLL48M COARSE CAL
DFLLVAL.FINE = 512
-403 453 µA
tSTARTUP Startup time
DFLLVAL.COARSE =
DFLL48M COARSE CAL
DFLLVAL.FINE = 512
fOUT within 90% of final value
7 8 9 µs
1087
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Note: 1. To insure that the device stays within the maximum allowed clock frequency, any reference clock for DFLL in close
loop must be within a 2% error accuracy.
42.11.4 32.768kHz Internal oscillator (OSC32K) Characteristics
Table 42-41. 32kHz RC Oscillator Characteristics
Table 42-40. DFLL48M Characteristics - Closed Loop Mode(1)
Symbol Parameter Conditions Min. Typ. Max. Units
fOUT Average Output frequency fREF = 32.768kHz 47 48 49 MHz
fREF Reference frequency
I
0.732 32.768 33 kHz
Jitter Cycle to Cycle jitter fREF = 32.768kHz - - 0.42 ns
IDFLL Power consumption on VDDIN fREF = 32 768kHz -425 482 µA
tLOCK Lock time
fREF = 32.768kHz
DFLLVAL.COARSE =
DFLL48M COARSE CAL
DFLLVAL.FINE = 512
DFLLCTRL.BPLCKC = 1
DFLLCTRL.QLDIS = 0
DFLLCTRL.CCDIS = 1
DFLLMUL.FSTEP = 10
100 200 500 µs
Symbol Parameter Conditions Min. Typ. Max. Units
fOUT Output frequency
Calibrated against a 32.768kHz
reference at 25°C, over [-40, +85]C,
over [1.8, 3.6]V
28.508 32.768 34.734
kHzCalibrated against a 32.768kHz
reference at 25°C, at VDD=3.3V 32.276 32.768 33.260
Calibrated against a 32.768kHz
reference at 25°C, over [1.8, 3.6]V 31.457 32.768 34.079
IOSC32K Current consumption
I
-0.67 1.31 µA
tSTARTUP Startup time
I
- 1 2 cycle
Duty Duty Cycle
I
-50 - %
1088
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
42.11.5 Ultra Low Power Internal 32kHz RC Oscillator (OSCULP32K) Characteristics
Notes: 1. These values are based on simulation. These values are not covered by test limits in production or
characterization.
2. This oscillator is always on.
42.11.6 8MHz RC Oscillator (OSC8M) Characteristics
Table 42-43. Internal 8MHz RC Oscillator Characteristics
Table 42-42. Ultra Low Power Internal 32kHz RC Oscillator Characteristics
Symbol Parameter Conditions Min. Typ. Max. Units
fOUT Output frequency
Calibrated against a 32.768kHz
reference at 25°C, over [-40, +85]C,
over [1.8, 3.6]V
25.559 32.768 38.011
kHzCalibrated against a 32.768kHz
reference at 25°C, at VDD=3.3V 31.293 32.768 34.570
Calibrated against a 32.768kHz
reference at 25°C, over [1.8, 3.6]V 31.293 32.768 34.570
IOSCULP32K
(1)(2) - - 125 nA
tSTARTUP Startup time
I
-10 -cycles
Duty Duty Cycle
I
-50 - %
Symbol Parameter Conditions Min. Typ. Max. Units
fOUT Output frequency
I
Calibrated against a 8MHz reference
at 25°C, over [-40, +85]C, over [1.8,
3.6]V
7.8 88.16
MHzCalibrated against a 8MHz reference
at 25°C, at VDD=3.3V 7.94 88.06
Calibrated against a 8MHz reference
at 25°C, over [1.8, 3.6]V 7.92 88.08
IOSC8M Current consumption
IIDLE
IDLE2 on OSC32K versus IDLE2 on
calibrated OSC8M enabled at 8MHz
(FRANGE=1, PRESC=0)
64 96 µA
tSTARTUP Startup time
I
-2.1 3µs
Duty Duty cycle
I
-50 - %
1089
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
42.11.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics
Note: 1. All values have been characterized with FILTSEL[1/0] as default value.
Table 42-44. FDPLL96M Characteristics(1)
Symbol Parameter Conditions Min. Typ. Max. Units
fIN Input frequency 32 -2000 KHz
fOUT Output frequency 48 -96 MHz
IFDPLL96M Current consumption
fIN= 32 kHz, fOUT= 48 MHz 500 700
µA
fIN= 32 kHz, fOUT= 96 MHz 900 1200
Jp Period jitter
fIN= 32 kHz, fOUT= 48 MHz -1.5 2.0
%
fIN= 32 kHz, fOUT= 96 MHz 3.0 10.0
fIN= 2 MHz, fOUT= 48 MHz 1.3 2.0
fIN= 2 MHz, fOUT= 96 MHz 3.0 7.0
tLOCK Lock Time
After startup, time to get lock
signal.
fIN= 32 kHz, fOUT= 96 MHz
1.3 2ms
fIN= 2 MHz, fOUT= 96 MHz 25 50 µs
Duty Duty cycle 40 50 60 %
Table 42-45. FDPLL96M Characteristics(1)
Symbol Parameter Conditions Min. Typ. Max. Units
fIN Input frequency 32 -2000 KHz
fOUT Output frequency 48 -96 MHz
IFDPLL96M Current consumption
fIN= 32 kHz, fOUT= 48 MHz 500 700
µA
fIN= 32 kHz, fOUT= 96 MHz 900 1200
Jp Period jitter
fIN= 32 kHz, fOUT= 48 MHz -1.5 2.1
%
fIN= 32 kHz, fOUT= 96 MHz 410.0
fIN= 2 MHz, fOUT= 48 MHz 1.6 2.2
fIN= 2 MHz, fOUT= 96 MHz 4.6 10.2
tLOCK Lock Time
After startup, time to get lock
signal.
fIN= 32 kHz, fOUT= 96 MHz
1.2 2ms
fIN= 2 MHz, fOUT= 96 MHz 25 50 µs
Duty Duty cycle 40 50 60 %
1090
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
42.12 PTC Typical Characteristics
Figure 42-7. Power Consumption [µA]
1 sensor, noise countermeasures disabled, f=48MHz, Vcc=3.3V
Figure 42-8. Power Consumption [µA]
1 sensor, noise countermeasures Enabled, f=48MHz, Vcc=3.3V
0
20
40
60
80
100
120
140
1
2
4
8
16
32
64
Sample averaging
Scan rate 10ms
Scan rate 50ms
Scan rate 100ms
Scan rate 200ms
0
20
40
60
80
100
120
140
160
180
200
1 2 4 8 16 32 64
Sample averaging
Scan rate 10ms
Scan rate 50ms
Scan rate 100ms
Scan rate 200ms
1091
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Figure 42-9. Power Consumption [µA]
10 sensors, noise countermeasures disabled, f=48MHz, Vcc=3.3V
Figure 42-10.Power Consumption [µA]
10 sensors, noise countermeasures Enabled, f=48MHz, Vcc=3.3V
0
200
400
600
800
1000
1200
1248163264
Sample averaging
Scan rate 10ms
Scan rate 50ms
Scan rate 100ms
Scan rate 200ms
Linear (Scan rate 50ms)
0
100
200
300
400
500
600
700
800
900
1 2 4 8 16 32 64
Sample averaging
Scan rate 10ms
Scan rate 50ms
Scan rate 100ms
Scan rate 200ms
1092
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Figure 42-11.Power Consumption [µA]
100 sensors, noise countermeasures disabled, f=48MHz, Vcc=3.3V
Figure 42-12.Power Consumption [µA]
100 sensors, noise countermeasures Enabled, f=48MHz, Vcc=3.3V
0
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
1248163264
Sample averaging
Scan rate 10ms
Scan rate 50ms
Scan rate 100ms
Scan rate 200ms
0
200
400
600
800
1000
1200
1400
1600
1800
1 2 4 8 16 32 64
Sample averaging
Scan rate 10ms
Scan rate 50ms
Scan rate 100ms
Scan rate 200ms
1093
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Figure 42-13.CPU Utilization
0 %
10 %
20 %
30 %
40 %
50 %
60 %
70 %
80 %
10
50
100
200
Channel count 1
Channel count 10
Channel count 100
1094
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
42.13 USB Characteristics
The USB on-chip buffers comply with the Universal Serial Bus (USB) v2.0 standard. All AC parameters related to these
buffers can be found within the USB 2.0 electrical specifications.
The USB interface is USB-IF certified:
- TID 40001583 - Peripheral Silicon > Low/Full Speed > Silicon Building Blocks
- TID 120000272 - Embedded Hosts > Full Speed
Electrical configuration required to be USB compliance:
- The CPU frequency must be higher 8MHz when USB is active (No constraint for USB suspend mode)
- The operating voltages must be 3.3V (Min. 3.0V, Max. 3.6V).
- The GCLK_USB frequency accuracy source must be less than:
- In USB device mode, 48MHz +/-0.25%
- In USB host mode, 48MHz +/-0.05%
Table 42-46. GCLK_USB Clock Setup Recommendations
Notes: 1. When using DFLL48M in USB recovery mode, the Fine Step value must be Ah to guarantee a USB clock at
+/-0.25% before 11ms after a resume.
2. Very high signal quality and crystal less. It is the best setup for USB Device mode.
3. FDPLL lock time is short when the clock frequency source is high (> 1MHz). Thus, FDPLL and external
OSC can be stopped during USB suspend mode to reduce consumption and guarantee a USB wakeup time
(See TDRSMDN in USB specification).
Clock setup USB Device USB Host
DFLL48M
Open loop No No
Closed loop, any internal OSC source No No
Closed loop, any external XOSC source Yes No
Closed loop, USB SOF source (USB recovery mode)(1) Yes(2) N/A
FDPLL96M
Any internal OSC source (32K, 8M, ... ) No No
Any external XOSC source (< 1MHz) Yes No
Any external XOSC source (> 1MHz) Yes(3) Yes
1095
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
42.14 Timing Characteristics
42.14.1 External Reset
Table 42-47. External Reset Characteristics
42.14.2 SERCOM in SPI Mode Timing
Figure 42-14.SPI Timing Requirements in Master Mode
Symbol Parameter Condition Min. Typ. Max. Units
tEXT Minimum reset pulse width
I
10 - - ns
MSB LSB
BSLBSM
t
MOS
t
MIS
t
MIH
t
SCKW
t
SCK
t
MOH
t
MOH
t
SCKF
t
SCKR
t
SCKW
MOSI
(Data Output)
MISO
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
1096
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Figure 42-15.SPI Timing Requirements in Slave Mode
MSB LSB
BSLBSM
t
SIS
t
SIH
t
SSCKW
t
SSCKW
t
SSCK
t
SSH
t
SOSSH
t
SCKR
t
SCKF
t
SOS
t
SSS
t
SOSSS
MISO
(Da
ta Output)
MOSI
(
Data Input)
SCK
(
CPOL = 1)
SCK
(
CPOL = 0)
SS
1097
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Table 42-48. SPI Timing Characteristics and Requirements(1)
Notes: 1. These values are based on simulation. These values are not covered by test limits in production.
2. See “I/O Pin Characteristics” on page 1067
Symbol Parameter Conditions Min. Typ. Max. Units
tSCK SCK period Master 84
ns
tSCKW SCK high/low width Master -0.5*tSCK -
tSCKR SCK rise time(2) Master - - -
tSCKF SCK fall time(2) Master - - -
tMIS MISO setup to SCK Master -21 -
tMIH MISO hold after SCK Master -13 -
tMOS MOSI setup SCK Master - tSCK/2 - 3 -
tMOH MOSI hold after SCK Master - 3 -
tSSCK Slave SCK Period Slave 1*tCLK_APB - -
tSSCKW SCK high/low width Slave 0.5*tSSCK - -
tSSCKR SCK rise time(2) Slave - - -
tSSCKF SCK fall time(2) Slave - - -
tSIS MOSI setup to SCK Slave tSSCK/2 - 9 - -
tSIH MOSI hold after SCK Slave tSSCK/2 - 3 - -
tSSS SS setup to SCK Slave
PRELOADEN=1 2*tCLK_APB
+ tSOS
- -
PRELOADEN=0 tSOS+7 - -
tSSH SS hold after SCK Slave tSIH - 4 - -
tSOS MISO setup SCK Slave - tSSCK/2 - 18 -
tSOH MISO hold after SCK Slave -18 -
tSOSS MISO setup after SS low Slave -18 -
tSOSH MISO hold after SS high Slave -10 -
1098
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
42.14.3 SERCOM in I2C Mode Timing
Table 42-49 describes the requirements for devices connected to the I2C Interface Bus. Timing symbols refer to Figure
42-16.
Figure 42-16.I2C Interface Bus Timing
t
SU;STA
t
LOW
t
HIGH
t
LOW
t
OF
t
HD;STA
t
HD;DAT
t
SU;DAT
t
SU;STO
t
BUF
SCL
t
R
SDA
1099
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Notes: 1. These values are based on simulation. These values are not covered by test limits in production.
2. Cb = Capacitive load on each bus line. Otherwise noted, value of Cb set to 20pF.
Table 42-49. I2C Interface Timing(1)
Symbol Parameter Conditions Min. Typ. Max. Units
tRRise time for both SDA and SCL
Standard /
Fast Mode
I
Cb(2) = 400pF -215 300
ns
Fast
Mode +
I
Cb(2) = 550pF 60 100
High
Speed
Mode
I
Cb(2) = 100pF 20 40
tOF
Output fall time from VIHmin to VILmax
Standard /
Fast Mode 10pF < Cb(2) < 400pF 20.0 50.0
Fast
Mode + 10pF < Cb(2) < 550pF 15.0 50.0
High
Speed
Mode
10pF < Cb(2) < 100pF 10.0 40.0
tHD;STA Hold time (repeated) START condition fSCL > 100kHz,
Master tLOW-9 - -
tLOW Low period of SCL Clock fSCL > 100kHz 113 - -
tBUF
Bus free time between a STOP and a
START condition fSCL > 100kHz tLOW - -
tSU;STA Setup time for a repeated START condition fSCL > 100kHz,
Master tLOW+7 - -
tHD;DAT Data hold time fSCL > 100kHz,
Master 9 - 12
tSU;DAT Data setup time fSCL > 100kHz,
Master 104 - -
tSU;STO Setup time for STOP condition fSCL > 100kHz,
Master tLOW+9 - -
tSU;DAT;rx Data setup time (receive mode) fSCL > 100kHz, Slave 51 -56
tHD;DAT;tx Data hold time (send mode) fSCL > 100kHz, Slave 71 90 138
1100
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
42.14.4 SWD Timing
Figure 42-17.SWD Interface Signals
Table 42-50. SWD Timings(1)
Note: 1. These values are based on simulation. These values are not covered by test limits in production or
characterization.
Symbol Parameter Conditions Min. Max. Units
Thigh SWDCLK High period
VVDDIO from 3.0V to 3.6V,
maximum external capacitor =
40pF
10 500000
ns
Tlow SWDCLK Low period 10 500000
Tos SWDIO output skew to falling edge
SWDCLK -5 5
Tis Input Setup time required between
SWDIO 4 -
Tih Input Hold time required between
SWDIO and rising edge SWDCLK 1 -
Stop Park Tri State
AcknowledgeTri State Tri State
Parity Sta
rt
Data Data
Stop Park Tri State
AcknowledgeTri State
Sta
rt
Read Cycle
W
rite Cycle
Tos Thigh Tlow
Tis
Data Data Parity Tri State
Tih
Fro
m debugger to
SWDIO pin
Fro
m debugger to
S
WDCLK pin
S
WDIO pin to
debugger
Fro
m debugger to
SWDIO pin
Fro
m debugger to
S
WDCLK pin
S
WDIO pin to
debugger
1101
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
42.15 AT86RF233 Electrical Characteristics
42.15.1 Digital Interface Timing Characteristics
Test Conditions: TOP = +25°C, VDD =3.0V, C
Load = 50pF (unless otherwise stated).
Symbol Parameter Condition Min. Typ. Max. Unit
fsync SCLK frequency Synchronous operation 8MHz
fasync SCLK frequency Asynchronous operation 7.5 MHz
t1/SEL falling edge to MISO active 180 ns
t2SCLK falling edge to MISO out Data hold time 25 ns
t3MOSI setup time 10 ns
t4MOSI hold time 10 ns
t5LSB last byte to MSB next byte SPI read/write, standard SRAM
and frame access modes 250(1) ns
t5a LSB last byte to MSB next byte Fast SRAM read/write access
mode 500(1) ns
t6/SEL rising edge to MISO tri state 10 ns
t7SLP_TR pulse width TX start trigger 62.5 Note(2) ns
t8SPI idle time: SEL rising to falling edge
SPI read/write, standard SRAM
and frame access modes
Idle time between consecutive
SPI accesses
250(1) ns
t8a SPI idle time: SEL rising to falling edge
Fast SRAM read/write access
mode
Idle time between consecutive
SPI accesses
500((1) ns
t9
Last SCLK rising edge to /SEL rising
edge 250 ns
t10 Reset pulse width ≥ 10 clock cycles at 16MHz 625 ns
t11 SPI access latency after reset ≥ 10 clock cycles at 16MHz 625 ns
t12 Frame buffer empty indicator latency
rising edge of last SCLK clock of
the Frame Buffer read command
byte to rising edge of IRQ
750 ns
tIRQ IRQ_2, IRQ_3, IRQ_4 latency Relative to the event to be
indicated 9µs
1102
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
42.15.2 General RF Specifications
Test Conditions (unless otherwise stated):
vDD =3.0V, t
RF = 2445MHz, TOP = +25°C, Measurement setup see Figure 34-1.
42.15.3 Transmitter Characteristics
Test Conditions (unless otherwise stated):
VDD = 3.0V, fRF = 2445MHz, TOP = +25°C, Measurement setup see Figure 34-1.
fCLKM CLKM output clock frequency
Configurable in register 0x03
CLKM_CTRL = 0 0MHz
CLKM_CTRL = 1 1MHz
CLKM_CTRL = 2 2MHz
CLKM_CTRL = 3 4MHz
CLKM_CTRL = 4 8MHz
CLKM_CTRL = 5 16 MHz
CLKM_CTRL = 6 250 kHz
CLKM_CTRL = 7 62.5 kHz
Notes: 1. For Fast SRAM read/write accesses on address space 0x82 – 0x94 the time t5(Min.) and t8(Min.) increases to
500ns.
2. Maximum pulse width less than (TX frame length + 16µs).
Symbol Parameter Condition Min. Typ. Max. Unit
Symbol Parameter Condition Min. Typ. Max. Unit
fRF Frequency range
As specified in [1], [2]2405 2445 2480 MHz
500kHz spacing 2360 2480 MHz
fCH Channel spacing
As specified in [1], [2] 5 MHz
500kHz spacing 500 kHz
fHDR Header bit rate (SHR, PHR) As specified in [1], [2]250 kb/s
fPSDU PSDU bit rate As specified in [1], [2]250 kb/s
fCHIP Chip rate As specified in [1], [2]2000 kchip/
s
fCLK Crystal oscillator frequency Reference oscillator 16 MHz
fSRD
Symbol rate deviation
Reference frequency accuracy for correct functionality
PSDU bit rate
250kb/s -60(1) +60 ppm
f20dB 20dB bandwidth 2.8 MHz
Note: 1. A reference frequency accuracy of ±40ppm is required by [1] [2].
1103
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Symbol Parameter Condition Min. Typ. Max. Unit
PTX_MAX TX Output power
Maximum configurable TX output
power value
Register bit TX_PWR = 0
+4 dBm
PRANGE Output power range 16 steps, configurable in register
0x05 (PHY_TX_PWR) 21 dB
PACC Output power tolerance ±2 dB
EVM Error vector magnitude 15 %rms
PHARM Harmonics(2) 2nd harmonic -28 dBm
3rd harmonic -45 dBm
PSPUR_TX Spurious Emissions(1)
30 – 1000MHz -36 dBm
1 – 12.75GHz -30 dBm
1.8 – 1.9GHz -47 dBm
5.15 – 5.3GHz -47 dBm
Notes: 1. Complies with EN 300 328/440, FCC-CFR-47 part 15, ARIB STD-66, RSS-210.
2. Measured single ended @ RFP/ RFN into 50Ω; termination of the other pin with 50Ω; constant wave signal.
Compliance with EN 300 328/400, FCC-CFR-47 part 15, ARIB STD-66, RSS-210 might require an appropriate
balun and/or harmonics filter.
1104
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
42.15.4 Receiver Characteristics
Test Conditions (unless otherwise stated):
VDD = 3.0V, fRF = 2445MHz, TOP = +25°C, fPSDU = 250kb/s, Measurement setup see Figure 34-1.
Symbol Parameter Condition Min. Typ. Max. Unit
PSENS Receiver sensitivity 250kb/s(1) -99 dBm
NF Noise figure 6dB
PRX_MAX Maximum RX input level 250kb/s(1) 8dBm
PACRN
Adjacent channel rejection:
-5MHz PRF= -82dBm(1) 32 dB
PACRP
Adjacent channel rejection:
+5MHz PRF= -82dBm(1) 35 dB
PAACRN
Adjacent channel rejection:
-10MHz PRF= -82dBm(1) 48 dB
PAACRP
Adjacent channel rejection:
+10MHz PRF= -82dBm(1) 48 dB
PAACR2N
2nd alternate channel rejection:
-15MHz PRF= -82dBm(1) 54 dB
PAACR2P
2nd alternate channel rejection:
+15MHz PRF= -82dBm(1) 54 dB
PSPUR_RX Spurious emissions
LO leakage(3) -57 dBm
30 – 1000MHz -57 dBm
1 – 12.75GHz -47 dBm
fCAR_OFFS TX/RX carrier frequency offset Sensitivity loss ≤ 3dB -300(2) +300 kHz
IIP3 3rd– order intercept point
At maximum gain
Offset freq. interf. 1 = 5MHz
Offset freq. interf. 2 = 10MHz
-10 dBm
IIP2 2nd– order intercept point
At maximum gain
Offset freq. interf. 1 = 60MHz
Offset freq. interf. 2 = 62MHz
31 dBm
RSSITOL RSSI tolerance Tolerance within gain step ±5 dB
RSSIRANGE RSSI dynamic range 87 dB
RSSIRES RSSI resolution 3dB
RSSIBASE_VAL RSSI sensitivity Defined as RSSI_BASE_VAL -94 dBm
1105
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
42.15.5 Current Consumption Specifications
Test Conditions (unless otherwise stated):
VDD = 3.0V, fRF = 2445MHz, TOP = +25°C, Measurement setup see Figure 34-1.
RSSIMIN Minimum RSSI value PRF ≤RSSI_BASE_VAL 0
RSSIMAX Maximum RSSI value PRF ≥RSSI_BASE_VAL + 84dB 28
Notes: 1. AWGN channel, PER ≤ 1%, PSDU length 20 octets.
2. Offset equals ±120ppm.
3. Measured single ended @ RFP/ RFN into 50Ω; termination of the other pin with 50Ω; constant wave signal.
Compliance with EN 300 328/400, FCC-CFR-47 part 15, ARIB STD-66, RSS-210 might require an appropriate
balun.
Symbol Parameter Condition Min. Typ. Max. Unit
Symbol Parameter Condition Min. Typ. Max. Unit
IBUSY_TX Supply current transmit state
PTX= +4dBm 13.8 mA
PTX= +0dBm 11.8 mA
PTX= -17dBm 7.2 mA
IRX_ON Supply current RX_ON state
high sensitivity
RX_PDT_LEVEL = [0x0] 11.8 mA
with active RPC mode(2)
may further reduce current
consumptions
IRX_ON_L0
Supply current RX_ON state
with active receiver desensitize
receiver desensitize
RX_PDT_LEVEL = [0x1,.., 0xE,
0xF](1)
11.3 mA
with active RPC mode(2)
may further reduce current
consumptions;
using RX_PDT_LEVEL = [0x8,
..., 0xE, 0xF](1)reduces current
consumption further by about
1mA
IPLL_ON Supply current PLL_ON state
5.2 mA
with active RPC mode(2) 450 µA
ITRX_OFF Supply current TRX_OFF state 300 µA
ISLEEP Supply current SLEEP state 0.2 µA
IDEEP_SLEEP Supply current DEEP_SLEEP state 0.02 µA
Notes: 1. Refer to “Receiver (RX)” on page 975.
2. Refer to “Reduced Power Consumption Mode (RPC)” on page 1034.
3. All power consumption measurements are performed with CLKM disabled.
4. The SAMD21 supply current has to be added to the AT86RF233 supply currents specified in the table above.
1106
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
42.15.6 XOSCRF Crystal Parameter Requirements
Test Conditions: TOP = +25°C, VDD = 3.0V (unless otherwise stated).
Symbol Parameter Condition Min. Typ. Max, Unit
f0Crystal frequency 16 MHz
CLLoad capacitance 814 pF
C0Crystal shunt capacitance 7pF
ESR Equivalent series resistance 100 Ω
1107
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
43. Packaging Information
43.1 Thermal Considerations
43.1.1 Thermal Resistance Data
Table 43-1 summarizes the thermal resistance data depending on the package.
Table 43-1. Thermal Resistance Data
43.1.2 Junction Temperature
The average chip-junction temperature, TJ, in °C can be obtained from the following:
where:
zθJA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 43-1.
zθJC = package thermal resistance, Junction-to-case thermal resistance (°C/W), provided in Table 43-1.
zθHEATSINK = cooling device thermal resistance (°C/W), provided in the device datasheet.
zPD = device power consumption (W).
zTA = ambient temperature (°C).
From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary
or not. If a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average
chip-junction temperature TJ in °C.
Package Type θJA θJC
32-pin QFN 37.2 °C/W 3.1 °C/W
48-pin QFN 33 °C/W 11.4 °C/W
1108
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
43.2 Package Drawings
43.2.1 48-pin QFN
Table 43-2. Device and Package Maximum Weight
100 mg
Table 43-3. Package Characteristics
Moisture Sensitivity Level MSL3
Table 43-4. Package Reference
JEDEC Drawing Reference MO-220
JESD97 Classification E3
1109
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
43.2.2 32-pin QFN (PG)
GPC:ZKV
Table 43-5. Device and Package Maximum Weight
90 mg
Table 43-6. Package Characteristics
Moisture Sensitivity Level MSL3
Table 43-7. Package Reference
JEDEC Drawing Reference MO-220
JESD97 Classification E3
1110
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
43.2.3 32-pin QFN (32M5)
GPC: ZSA
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k
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Table 43-8. Device and Package Maximum Weight
78.5 mg
Table 43-9. Package Characteristics
Moisture Sensitivity Level MSL3
Table 43-10. Package Reference
JEDEC Drawing Reference MO-220
JESD97 Classification E3
1111
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
44. Soldering Profile
The following table gives the recommended soldering profile from J-STD-20.
A maximum of three reflow passes is allowed per component.
SVNREVISION
Profile Feature Green Package
Average Ramp-up Rate (217°C to peak) 3°C/s max
Preheat Temperature 175°C +/-25°C 150-200°C
Time Maintained Above 217°C 60-150s
Time within 5°C of Actual Peak Temperature 30s
Peak Temperature Range 260°C
Ramp-down Rate 6°C/s max
Time 25°C to Peak Temperature 8 minutes max
1112
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
45. Schematic Checklist
45.1 Introduction
This chapter describes a common checklist which should be used when starting and reviewing the schematics for a
SAM R21 design. This chapter illustrates a recommended power supply connection, how to connect external analog
references, programmer, debugger, oscillator and crystal.
45.1.1 Operation in Noisy Environment
If the microcontroller is operating in an environment with much electromagnetic noise it must be protected from this noise
to ensure reliable operation. In addition to following best practice EMC design guidelines, the recommendations listed in
the schematic checklist sections must be followed. In particular placing decoupling capacitors very close to the power
pins, a RC-filter on the RESET pin, and a pull-up resistor on the SWCLK pin is critical for reliable operations. It is also
relevant to eliminate or attenuate noise in order to avoid that it reaches supply pins, I/O pins and crystals.
45.2 Power Supply
The SAM R21 supports a single power supply from 1.8 to 3.6V.
45.2.1 Power Supply Connections
Figure 45-1. Power Supply Schematic
10μF
100nF
1.8V - 3.6V Close to device
(for every pin)
VDDANA
GNDANA
VDDIO
VDDIN
VDDCORE
GND
10μF 100nF
100nF
1μF
100nF
DVDD
AVDD
1113
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Notes: 1. These values are only given as typical examples.
2. Decoupling capacitor should be placed close to the device for each supply pin pair in the signal group, low
ESR caps should be used for better decoupling.
3. An inductor should be added between the external power and the VDD for power filtering.
4. Ferrite bead has better filtering performance than the common inductor at high frequencies. It can be added
between VDD and VDDANA for preventing digital noise from entering the analog power domain. The bead
should provide enough impedance (e.g. 50Ω at 20MHz and 220Ω at 100MHz) for separating the digital
power from the analog power domain. Make sure to select a ferrite bead designed for filtering applications
with a low DC resistance to avoid a large voltage drop across the ferrite bead.
45.3 External Analog Reference Connections
The following schematic checklist is only necessary if the application is using external analog references. If the internal
references are used instead, the following circuits in Figure 45-2 and Figure 45-2 are not necessary.
Figure 45-2. External Analog Reference Schematic With One Reference
Table 45-1. Power Supply Connections, VDDCORE From Internal Regulator
Signal Name Recommended Pin Connection Description
VDDIO
1.8V to 3.6V
Decoupling/filtering capacitors 100nF(1)(2) and 10µF(1)
Decoupling/filtering inductor 10µH(1)(3)
Digital supply voltage
VDDANA
1.8V to 3.6V
Decoupling/filtering capacitors 100nF(1)(2) and 10µF(1)
Ferrite bead(4) prevents the VDD noise interfering the
VDDANA
Analog supply voltage
GND Ground
GNDANA Ground for the analog power domain
Table 45-2. External Analog Reference Connections
Signal Name Recommended Pin Connection Description
VREFB
1.0V to VDDANA - 0.6V for ADC
Decoupling/filtering capacitors
100nF(1)(2) and 4.7µF(1)
External reference from VREFB pin on
the analog port
GND Ground
GND
VREFB
EXTERNAL
REFERENCE 4.7µF 100nF
Close to device
(for every pin)
1114
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Notes: 1. These values are given as a typical example.
2. Decoupling capacitor should be placed close to the device for each supply pin pair in the signal group.
1115
Atmel | SMART SAM R21 [DATASHEET]
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45.4 External Reset Circuit
The external reset circuit is connected to the RESET pin when the external reset function is used. If the external reset
function has been disabled, the circuit is not necessary. The reset switch can also be removed, if the manual reset is not
necessary. The RESET pin itself has an internal pull-up resistor, hence it is optional to also add an external pull-up
resistor.
Figure 45-3. External Reset Circuit Example Schematic
A pull-up resistor makes sure that the reset does not go low unintended causing a device reset. An additional resistor has
been added in series with the switch to safely discharge the filtering capacitor, i.e. preventing a current surge when
shorting the filtering capacitor which again causes a noise spike that can have a negative effect on the system.
Notes: 1. These values are given as a typical example.
2. The SAM R21 features an internal pull-up resistor on the RESET pin, hence an external pull-up is optional.
45.5 Unused or Unconnected Pins
For unused pins the default state of the pins for the will give the lowest current leakage. There is thus no need to do any
configuration of the unused pins in order to lower the power consumption.
Table 45-3. Reset Circuit Connections
Signal Name Recommended Pin Connection Description
RESET
Reset low level threshold voltage
VDDIO = 1.8V - 2.0V: Below 0.33 * VDDIO
VDDIO = 2.7V - 3.6V: Below 0.36 * VDDIO
Decoupling/filter capacitor 100nF(1)
Pull-up resistor 10kΩ(1)(2)
Resistor in series with the switch 330Ω(1)
Reset pin
GND
RESET
100nF
10kΩ
VDD
330Ω
1116
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
45.6 Clocks and Crystal Oscillators
The SAM R21 can be run from internal or external clock sources, or a mix of internal and external sources. An example
of usage will be to use the internal 8MHz oscillator as source for the system clock, and an external 32.768kHz watch
crystal as clock source for the Real-Time counter (RTC).
45.6.1 External Clock Source
Figure 45-4. External Clock Source Example Schematic
45.6.2 Crystal Oscillator
Figure 45-5. Crystal Oscillator Example Schematic
The crystal should be located as close to the device as possible. Long signal lines may cause too high load to operate
the crystal, and cause crosstalk to other parts of the system.
Table 45-5. Crystal Oscillator Checklist
Notes: 1. These values are given only as typical example.
2. Decoupling capacitor should be placed close to the device for each supply pin pair in the signal group.
Table 45-4. External Clock Source Connections
Signal Name Recommended Pin Connection Description
XIN XIN is used as input for an external clock signal Input for inverting oscillator pin
XOUT/GPIO Can be left unconnected or used as normal GPIO
XOUT/GPIO
XIN
NC/GPIO
External
Clock
Signal Name Recommended Pin Connection Description
XIN Load capacitor 15pF(1)(2)
External crystal between 0.4 to 30MHz
XOUT Load capacitor 15pF(1)(2)
XOUT
XIN
15pF
15pF
1117
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
45.6.3 External Real Time Oscillator
The low frequency crystal oscillator is optimized for use with a 32.768kHz watch crystal. When selecting crystals, load
capacitance and crystal’s Equivalent Series Resistance (ESR) must be taken into consideration. Both values are
specified by the crystal vendor.
The SAM R21 oscillator (not available in SAMR21E) is optimized for very low power consumption, hence close attention
should be made when selecting crystals, see Table 45-6 for maximum ESR recommendations on 9pF and 12.5pF
crystals.
The Low-frequency Crystal Oscillator provides an internal load capacitance of typical values available in Table 42-37,
“32kHz Crystal Oscillator Characteristics,” on page 1085. This internal load capacitance and PCB capacitance can allow
to use a Crystal inferior to 12.5pF load capacitance without external capacitors as shown in Figure 45-6.
Note: Maximum ESR is typical value based on characterization. These values are not covered by test limits in
production.
Figure 45-6. External Real Time Oscillator without Load Capacitor
However, to improve Crystal accuracy and Safety Factor, it can be recommended by crystal datasheet to add external
capacitors as shown in Figure 45-7.
To find suitable load capacitance for a 32.768kHz crystal, consult the crystal datasheet.
Figure 45-7. External Real Time Oscillator with Load Capacitor
Notes: 1. These values are given only as typical examples.
2. Decoupling capacitor should be placed close to the device for each supply pin pair in the signal group.
Table 45-6. Maximum ESR Recommendation for 32.768kHz Crystal
Crystal CL (pF) Max ESR [kΩ]
12.5 313
Table 45-7. External Real Time Oscillator Checklist
Signal Name Recommended Pin Connection Description
XIN32 Load capacitor 22pF(1)(2) Timer oscillator input
XOUT32 Load capacitor 22pF(1)(2) Timer oscillator output
XOUT32
XIN32
32.768kHz
XOUT32
XIN32
32.768kHz
22pF
22pF
1118
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
45.6.4 Calculating the Correct Crystal Decoupling Capacitor
In order to calculate correct load capacitor for a given crystal one can use the model shown in Figure 45-8 which includes
internal capacitors CLn, external parasitic capacitance CELn and external load capacitance CPn.
Figure 45-8. Crystal Circuit With Internal, External and Parasitic Capacitance
Using this model the total capacitive load for the crystal can be calculated as shown in the equation below:
where Ctot is the total load capacitance seen by the crystal, this value should be equal to the load capacitance value
found in the crystal manufacturer datasheet.
The parasitic capacitance CELn can in most applications be disregarded as these are usually very small. If accounted for
the value is dependent on the PCB material and PCB layout.
For some crystal the internal capacitive load provided by the device itself can be enough. To calculate the total load
capacitance in this case. CELn and CPn are both zero, CL1 = CL2 = CL, and the equation reduces to the following:
For device equivalent internal pin capacitance, refer to “External 32kHz Crystal Oscillator (XOSC32K) Characteristics” on
page 1085.
XOUT
Internal
CEL1
CL1 CL2
CP1 CP2 CEL2
External
XIN
Ctot
∑CL1CP1CEL1
++ )CL2CP2CEL2
++ )((
CL1CP1CEL1CL2CP2CEL2
++ +++
--------------------------------------------------------------------------------------------------------
=
Ctot
∑CL
2
-------
=
1119
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
45.7 Programming and Debug Ports
For programming and/or debugging the SAM R21 the device should be connected using the Serial Wire Debug (SWD)
interface. Currently, the SWD interface is supported by several Atmel and third party programmers and debuggers, such
as the SAM-ICE, JTAGICE3 or SAM R21 Xplained Pro (SAM R21 evaluation kit) Embedded Debugger.
Refer to the SAM-ICE, JTAGICE3 or SAM R21 Xplained Pro user guides for details on debugging and programming
connections and options. For connecting to any other programming or debugging tool, refer to that specific programmer’s
or debugger’s user guide.
The SAM R21 Xplained Pro evaluation board for the SAM R21 supports programming and debugging through the
onboard embedded debugger so no external programmer or debugger is needed.
Note that a pull-up resistor on the SWCLK pin is critical for reliable operations. Refer to “Operation in Noisy Environment”
on page 1112.
Figure 45-9. SWCLK Circuit Connections
45.7.1 Cortex Debug Connector (10-pin)
For debuggers and/or programmers that support the Cortex Debug Connector (10-pin) interface the signals should be
connected as shown in Figure 45-10 with details described in Table 45-9.
Table 45-8. SWCLK Circuit Connections
Pin Name Description Recommended Pin Connection
SWCLK Serial wire clock pin Pull-up resistor 1kΩ
SWCLK
1kΩ
V
DD
1120
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Figure 45-10.Cortex Debug Connector (10-pin)
Table 45-9. Cortex Debug Connector (10-pin)
Header Signal Name Description Recommended Pin Connection
SWDCLK Serial wire clock pin Pull-up resistor 1kΩ
SWDIO Serial wire bidirectional data pin
RESET Refer to “External Reset Circuit” on page 1115
RESET Target device reset pin, active low
VTref Target voltage sense, should be connected to
the device VDD
GND Ground
1
Cortex Debug Connector
(10-pin)
V
DD
VTref
GND
GND
NC
NC
NC
NC
SWDCLK
SWDIO
RESET
RESET
SWDIO
SWCLK
GND
1121
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
45.7.2 10-pin JTAGICE3 Compatible Serial Wire Debug Interface
The JTAGICE3 debugger and programmer does not support the Cortex Debug Connector (10-pin) directly, hence a
special pinout is needed to directly connect the SAM R21 to the JTAGICE3, alternatively one can use the JTAGICE3
squid cable and manually match the signals between the JTAGICE3 and SAM R21. Figure 45-11 describes how to
connect a 10-pin header that support connecting the JTAGICE3 directly to the SAM R21 without the need for a squid
cable.
To connect the JTAGICE3 programmer and debugger to the SAM R21, one can either use the JTAGICE3 squid cable, or
use a 10-pin connector as shown in Figure 45-11 with details given in Table 45-10 to connect to the target using the
JTAGICE3 50 mil cable directly.
Figure 45-11.10-pin JTAGICE3 Compatible Serial Wire Debug Interface
Table 45-10. 10-pin JTAGICE3 Compatible Serial Wire Debug Interface
Header Signal Name Description
SWDCLK Serial wire clock pin
SWDIO Serial wire bidirectional data pin
RESET Target device reset pin, active low
VTG Target voltage sense, should be connected to the device VDD
GND Ground
VTG
GND
NC
NC
SWDIO
SWDCLK
NC
NC
RESET
10-pin JTAGICE3 Compatible
Serial Wire Debug Header
GND
SWDIO
SWCLK
RESET
VDD
1
NC
1122
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
45.7.3 20-pin IDC JTAG Connector
For debuggers and/or programmers that support the 20-pin IDC JTAG Connector, e.g. the SAM-ICE, the signals should
be connected as shown in Figure 45-12 with details described in Table 45-11.
Figure 45-12.20-pin IDC JTAG Connector
Table 45-11. 20-pin IDC JTAG Connector
Header Signal Name Description
SWDCLK Serial wire clock pin
SWDIO Serial wire bidirectional data pin
nRESET Target device reset pin, active low
VCC Target voltage sense, should be connected to the device VDD
GND Ground
GND* These pins are reserved for firmware extension purposes. They can be left open or connected to
GND in normal debug environment. They are not essential for SWD in general.
1
VCC
NC
NC
SWDIO
SWDCLK
NC
NC
nRESET
NC
NC
NC
GND
GND
GND
GND
GND
GND*
GND*
GND*
GND*
20-pin IDC JTAG Connector
GND
SWDIO
SWCLK
RESET
VDD
1123
Atmel | SMART SAM R21 [DATASHEET]
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45.8 USB Interface
The USB interface consists of a differential data pair (D+/D-) and a power supply (VBUS, GND).
Refer to the “Electrical Characteristics” on page 1055 for operating voltages which will allow USB operation.
Figure 45-13.Low Cost USB Interface Example Schematic
It is recommended to increase ESD protection on the USB D+, D-, and VBUS lines using dedicated transient
suppressors. These protections should be located as close as possible to the USB connector to reduce the potential
discharge path and reduce discharge propagation within the entire system.
The USB FS cable includes a dedicated shield wire that should be connected to the board with caution. Special attention
should be paid to the connection between the board ground plane and the shield from the USB connector and the cable.
Tying the shield directly to ground would create a direct path from the ground plane to the shield, turning the USB cable
into an antenna. To limit the USB cable antenna effect, it is recommended to connect the shield and ground through an
RC filter.
Table 45-12. USB Interface Checklist
Signal Name Recommended Pin Connection Description
D+
zThe impedance of the pair should be
matched on the PCB to minimize
reflections.
zUSB differential tracks should be routed
with the same characteristics (length,
width, number of vias, etc.)
zSignals should be routed as parallel as
possible, with a minimum number of
angles and vias
USB full speed / low speed positive data upstream
pin
D- USB full speed / low speed negative data
upstream pin
VBUS
USB
Connector
VBUS
D+
D-
GND
Shield
GND (Board)
USB_D+
USB_D-
USB
Differential
Data Line Pair
1124
Atmel | SMART SAM R21 [DATASHEET]
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Figure 45-14.Protected USB Interface Example Schematic
4.5nF
1MO
VBUS
USB
Connector
VBUS
D+
D-
GND
Shield
USB Transient
protection
RC Filter
(GND/Shield
Connection) GND (Board)
USB_D+
USB_D-
USB
Differential
Data Line Pair
1125
Atmel | SMART SAM R21 [DATASHEET]
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46. About This Document
46.1 Conventions
46.1.1 Numerical Notation
Table 46-1. Numerical notation
46.1.2 Memory Size and Type
46.1.3 Frequency and Time
165 Decimal number
0101b Binary number (example 0b0101 = 5 decimal)
0101 Binary numbers are given without suffix if unambiguous
0x3B24 Hexadecimal number
XRepresents an unknown or don't care value
ZRepresents a high-impedance (floating) state for either a signal or a bus
Table 46-2. Memory Size and Bit Rate
Symbol Description
kB/kbyte kilobyte (210 = 1024)
MB/Mbyte megabyte (220 = 1024*1024)
GB/Gbyte gigabyte (230 = 1024*1024*1024)
bbit (binary 0 or 1)
Bbyte (8 bits)
1kbit/s 1,000 bit/s rate (not 1,024 bit/s)
1Mbit/s 1,000,000 bit/s rate
1Gbit/s 1,000,000,000 bit/s rate
Table 46-3. Frequency and Time
Symbol Description
kHz 1kHz = 103Hz = 1,000Hz
MHz 106 = 1,000,000Hz
GHz 109 = 1,000,000,000Hz
ssecond
ms millisecond
µs microsecond
ns nanosecond
1126
Atmel | SMART SAM R21 [DATASHEET]
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46.1.4 Registers and Bits
Table 46-4. Register and bit mnemonics
46.2 Acronyms and Abbreviations
Table 46-5 contains acronyms and abbreviations used in this document.
R/W Read/Write accessible register bit. The user can read from and write to this bit.
RRead-only accessible register bit. The user can only read this bit. Writes will be ignored.
WWrite-only accessible register bit. The user can only write this bit. Reading this bit will return an
undefined value.
BIT Bit names are shown in uppercase. (Example PINA1)
BITS[n:m] A set of bits from bit n down to m. (Example: PINA3..0 = {PINA3, PINA2, PINA1, PINA0}
Reserved Reserved bits are unused and reserved for future use. For compatibility with future devices, always
write reserved bits to zero when the register is written. Reserved bits will always return zero when read.
PERIPHERALiIf several instances of a peripheral exist, the peripheral name is followed by a number to indicate the
number of the instance in the range 0-n. PERIPHERALi denotes one specific instance.
Reset Value of a register after a power reset. This is also the value of registers in a peripheral after
performing a software reset of the peripheral, except for the Debug Control registers.
SET/CLR
Registers with SET/CLR suffix allows the user to clear and set bits in a register without doing a read-
modify-write operation. These registers always come in pairs. Writing a one to a bit in the CLR register
will clear the corresponding bit in both registers, while writing a one to a bit in the SET register will set
the corresponding bit in both registers. Both registers will return the same value when read. If both
registers are written simultaneously, the write to the CLR register will take precedence.
Table 46-5. Acronyms and Abbreviations
Abbreviation Description
AACK Automatic Acknowledgement
ACK Acknowledgement
AC Analog Comparator
AD Antenna Diversity
ADC Analog-to-Digital Converter
ADDR Address
AES Advanced Encryption Standard
AGC Automatic Gain Control
AHB AMBA Advanced High-performance Bus
APB AMBA Advanced Peripheral Bus
AREF Analog reference voltage
ARET Automatic Retransmission
AVDD Analog supply voltage
AVREG Analog Voltage Regulator
1127
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AWGN Additive White Gaussian Noise
BATMON Battery Monitor
BBP Base-Band Processor
BLB Boot Lock Bit
BOD Brown-out detector
BPF Band-Pass Filter
CBC Cipher Block Chaining
CAL Calibration
CC Compare/capture
CCA Clear Channel Assessment
CF Center Frequency
CLK Clock
CRC Cyclic Redundancy Check
CS Carrier Sense
CSMA-CA Carrier Sense Multiple Access - Collision Avoidance
CW Continuous Wave
CTRL Control
DAC Digital to Analog converter
DFLL Digital Frequency Locked Loop
DSU Device service unit
DVREG Digital Voltage Regulator
ECB Electronic Code Book
ED Energy Detect
EEPROM Electrically Erasable Programmable Read-Only Memory
EIC External interrupt controller
ESD Electrostatic Discharge
EVM Error Vector Magnitude
EVSYS Event System
FCChannel Center Frequency
FCF Frame Control Field
FCS Frame Check Sequence
FIFO First In, First Out
FTN Filter Tuning Network
Table 46-5. Acronyms and Abbreviations (Continued)
Abbreviation Description
1128
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GCLK Generic clock
GND Ground
GPIO General Purpose Input/Output
I2CInter-integrated circuit
IEEE Institute of Electrical and Electronic Engineers
IF Interrupt Flag
INT Interrupt
IOBUS I/O Bus
IRQ Interrupt Request
ISM Industrial Scientific Medical
LDO Low Dropout
LNA Low-Noise Amplifier
LO Local Oscillator
LPF Low-Pass Filter
LQI Link Quality Indication
LSB Least Significant Bit
MAC Medium Access Control
MFR MAC Footer
MHR MAC Header
MIC Message Integrity Code
MISO Master Input, Slave Output
MOSI Master Output, Slave Input
MSB Most Significant Bit
MSDU MAC Service Data Unit
MPDU MAC Protocol Data Unit
MSK Minimum Shift Key
NMI Non-Maskable Interrupt
NOP No Operation
NVIC Nested vector interrupt controller
NVMCTRL Non-Volatile Memory controller
O-QPSK Offset Quadrature Phase Shift Keying
OSC Oscillator
PA Power Amplifier
Table 46-5. Acronyms and Abbreviations (Continued)
Abbreviation Description
1129
Atmel | SMART SAM R21 [DATASHEET]
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PAC Peripheral access controller
PAN Personal Area Network
PC Program counter
PCB Printed Circuit Board
PER Period
PHR PHY Header
PHY Physical Layer
PLL Phase-Locked Loop
PM Power manager
POR Power-on reset
PPDU PHY Protocol Data Unit
PPF Poly-Phase Filter
PRBS Pseudo Random Binary Sequence
PSD Power Spectrum Density
PSDU PHY Service Data Unit
PTC Peripheral touch controller
PWM Pulse Width Modulation
RAM Random-access memory
REF Reference
RF Radio Frequency
RMW Read-modify-write
RSSI Received Signal Strength Indicator
RTC Real-time counter
RX Receiver
SERCOM Serial communication interface
SFD Start-Of-Frame Delimiter
SHR Synchronization Header
SMBus System Management Bus
SP Stack Pointer
SPI Serial peripheral interface
SRAM Static random-access memory
SRD Short Range Device
SSBF Single Side Band Filter
Table 46-5. Acronyms and Abbreviations (Continued)
Abbreviation Description
1130
Atmel | SMART SAM R21 [DATASHEET]
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SYSCTRL System controller
SWD Single-wire debug
TC Timer/Counter
TRX Transceiver
TX Transmitter
ULP Ultra Low Power
USART Universal synchronous and asynchronous serial receiver and transmitter
VDD Digital supply voltage
VCO Voltage Controlled Oscillator
VREF Voltage reference
WDT Watchdog timer
WPAN Wireless Personal Area Network
XOSC Crystal oscillator
XTAL Crystal
Table 46-5. Acronyms and Abbreviations (Continued)
Abbreviation Description
1131
Atmel | SMART SAM R21 [DATASHEET]
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47. Errata
47.1 Revision A
47.1.1 Device
1 - CLKM is internally connected to GCLK/IO[5] on PC16. As this clock
source cannot be used as GCLK_MAIN it is not possible to clock the CPU
from the AT86RF233 CLKM clock output. Errata reference: 13152
Fix/Workaround:
None
2 - In single shot mode and at 125°C, the ADC conversions have linearity
errors. Errata reference: 13277
Fix/Workaround:
- Workaround 1: At 125°C, do not use the ADC in single shot mode; use the
ADC in free running mode only.
- Workaround 2: At 125°C, use the ADC in single shot mode only with
VDDANA > 3V.
3 - TCC0/WO[6] on PA16 and TCC0/WO[7] on PA17 are not available. Errata
reference: 11622
Fix/Workaround:
None
4 - On pin PA24 and PA25 the pull-up and pull-down configuration is not
disabled automatically when alternative pin function is enabled. Errata
reference: 12368
Fix/Workaround:
For pin PA24 and PA25, the GPIO pull-up and pull-down must be disabled before
enabling alternative functions on them.
5 - If APB clock is stopped and GCLK clock is running, APB read access to
read-synchronized registers will freeze the system. The CPU and the DAP
AHB-AP are stalled, as a consequence debug operation is impossible.
Errata reference: 10416
Fix/Workaround:
Do not make read access to read-synchronized registers when APB clock is
stopped and GCLK is running. To recover from this situation, power cycle the
device or reset the device using the RESETN pin.
6 - In I2C Slave mode, writing the CTRLB register when in the AMATCH or
DRDY interrupt service routines can cause the state machine to reset. Errata
reference: 13574
1132
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Fix/Workaround:
Write CTRLB.ACKACT to 0 using the following sequence:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = 0;
// Re-enable interrupts if applicable.
Write CTRLB.ACKACT to 1 using the following sequence:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
// Re-enable interrupts if applicable.
Otherwise, only write to CTRLB in the AMATCH or DRDY interrupts if it is to close
out a transaction.
When not closing a transaction, clear the AMATCH interrupt by writing a 1 to its bit
position instead of using CTRLB.CMD. The DRDY interrupt is automatically
cleared by reading/writing to the DATA register in smart mode. If not in smart
mode, DRDY should be cleared by writing a 1 to its bit position.
Code replacements examples:
Current:
SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
Change to:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
// Re-enable interrupts if applicable.
Current:
SERCOM - CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
Change to:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = 0;
// Re-enable interrupts if applicable.
1133
Atmel | SMART SAM R21 [DATASHEET]
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Current:
/* ACK or NACK address */
SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
Change to:
// CMD=0x3 clears all interrupts, so to keep the result similar,
// PREC is cleared if it was set.
if (SERCOM - INTFLAG.bit.PREC) SERCOM - INTFLAG.reg =
SERCOM_I2CS_INTFLAG_PREC;
SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
7 - PA24 and PA25 cannot be used as input when configured as GPIO with
continuous sampling (cannot be read by PORT). Errata reference: 12005
Fix/Workaround:
- Use PA24 and PA25 for peripherals or only as output pins.
- Or configure PA31 to PA24 for on-demand sampling (CTRL[31:24] all zeroes)
and access the IN register through the APB (not the IOBUS), to allow waiting for
on-demand sampling.
8 - The SYSTICK calibration value is incorrect. Errata reference: 14154
Fix/Workaround:
The correct SYSTICK calibration value is 0x40000000. This value should not be
used to initialize the Systick RELOAD value register, which should be initialized
instead with a value depending on the main clock frequency and on the tick period
required by the application. For a detailed description of the SYSTICK module,
refer to the official ARM Cortex-M0+ documentation.
9 - In Standby, Idle1 and Idle2 sleep modes the device might not wake up
from sleep. An External Reset, Power on Reset or Watch Dog Reset will start
the device again. Errata reference: 13140
Fix/Workaround:
the SLEEPPRM bits in the NVMCTRL.CTRLB register must be written to 3
(NVMCTRL - CTRLB.bit.SLEEPPRM = 3) to ensure correct operation of the
device. The average power consumption of the device will increase with 20uA
compared to numbers in the electrical characteristics chapter.
10 - While the internal startup is not completed, PA07 pin is driven low by
the chip. Then as all the other pins it is configured as an High Impedance
pin. Errata reference: 12118
Fix/Workaround:
None
1134
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
11 - Digital pin outputs from Timer/Counters, AC (Analog Comparator),
GCLK (Generic Clock Controller), and SERCOM (I2C and SPI) do not change
value during standby sleep mode. Errata reference: 12537
Fix/Workaround:
Set the voltage regulator in Normal mode before entering STANDBY sleep mode
in order to keep digital pin output enabled. This is done by setting the RUNSTDBY
bit in the VREG register.
12 - The voltage regulator in low power mode is not functional at
temperatures above 85C. Errata reference: 12291
Fix/Workaround:
Enable normal mode on the voltage regulator in standby sleep mode.
Example code:
// Set the voltage regulator in normal mode configuration in standby sleep mode
SYSCTRL->VREG.bit.RUNSTDBY = 1;
13 - If the external XOSC32K is broken, neither the external pin RST nor the
GCLK software reset can reset the GCLK generators using XOSC32K as
source clock. Errata reference: 12164
Fix/Workaround:
Do a power cycle to reset the GCLK generators after an external XOSC32K
failure.
47.1.2 DSU
1 - If a debugger has issued a DSU Cold-Plugging procedure and then
released the CPU from the resulting ""CPU Reset Extension"", the CPU will
be held in ""CPU Reset Extension"" after any upcoming reset event. Errata
reference: 12015
Fix/workaround:
The CPU must be released from the ""CPU Reset Extension"" either by writing a
one in the DSU STATUSA.CRSTEXT register or by applying an external reset
with SWCLK high or by power cycling the device.
2 - The MBIST ""Pause-on-Error"" feature is not functional on this device.
Errata reference: 14324
Fix/Workaround: Do not use the ""Pause-on-Error"" feature.
47.1.3 PM
1 - In debug mode, if a watchdog reset occurs, the debug session is lost.
Errata reference: 12196
Fix/Workaround:
A new debug session must be restart after a watchdog reset.
1135
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
47.1.4 XOSC32K
1 - The automatic amplitude control of the XOSC32K does not work. Errata
reference: 10933
Fix/Workaround:
Use the XOSC32K with Automatic Amplitude control disabled
(XOSC32K.AAMPEN = 0)
47.1.5 DFLL48M
1 - The DFLL clock must be requested before being configured otherwise a
write access to a DFLL register can freeze the device. Errata reference: 9905
Fix/Workaround:
Write a zero to the DFLL ONDEMAND bit in the DFLLCTRL register before
configuring the DFLL module.
2 - If the DFLL48M reaches the maximum or minimum COARSE or FINE
calibration values during the locking sequence, an out of bounds interrupt
will be generated. These interrupts will be generated even if the final
calibration values at DFLL48M lock are not at maximum or minimum, and
might therefore be false out of bounds interrupts. Errata reference: 10669
Fix/Workaround:
Check that the lockbits: DFLLLCKC and DFLLLCKF in the SYSCTRL Interrupt
Flag Status and Clear register (INTFLAG) are both set before enabling the
DFLLOOB interrupt.
3 - The DFLL status bits in the PCLKSR register during the USB clock
recovery mode can be wrong after a USB suspend state. Errata reference:
11938
Fix/Workaround:
Do not monitor the DFLL status bits in the PCLKSR register during the USB clock
recovery mode.
47.1.6 FDPLL
1 - The lock flag (DPLLSTATUS.LOCK) may clear randomly. When the lock
flag randomly clears, DPLLLCKR and DPLLLCKF interrupts will also trigger,
and the DPLL output is masked. Errata reference: 11791
Fix/Workaround:
Set DPLLCTRLB.LBYPASS to 1 to disable masking of the DPLL output by the
lock status.
2 - FDPLL lock time-out values are different from the parameters in the
datasheet. Errata reference: 12145
1136
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Fix/Workaround:
The time-out values are:
- DPLLCTRLB.LTIME[2:0] = 4 : 10ms
- DPLLCTRLB.LTIME[2:0] = 5 : 10ms
- DPLLCTRLB.LTIME[2:0] = 6 : 11ms
- DPLLCTRLB.LTIME[2:0] = 7 : 11ms
47.1.7 DMAC
1 - If data is written to CRCDATAIN in two consecutive instructions, the CRC
computation may be incorrect. Errata reference: 13507
Fix/Workaround:
Add a NOP instruction between each write to CRCDATAIN register.
47.1.8 NVMCTRL
1 - Default value of MANW in NVM.CTRLB is 0. Errata reference: 13134
This can lead to spurious writes to the NVM if a data write is done through a
pointer with a wrong address corresponding to NVM area.
Fix/Workaround:
Set MANW in the NVM.CTRLB to 1 at startup
2 - When the part is secured and EEPROM emulation area configured to
none, the CRC32 is not executed on the entire flash area but up to the on-
chip flash size minus half a row. Errata reference: 11988
Fix/Workaround:
When using CRC32 on a protected device with EEPROM emulation area
configured to none, compute the reference CRC32 value to the full chip flash size
minus half row.
3 - When external reset is active it causes a high leakage current on VDDIO.
Errata reference: 13446
Fix/Workaround:
Minimize the time external reset is active.
47.1.9 SERCOM
1 - The I2C Slave SCL Low Extend Time-out (CTRLA.SEXTTOEN) and Master
SCL Low Extend Time-out (CTRLA.MEXTTOEN) cannot be used if SCL Low
Time-out (CTRLA.LOWTOUT) is disabled. When SCTRLA.LOWTOUT=0, the
GCLK_SERCOM_SLOW is not requested. Errata reference: 12003
Fix/Workaround:
1137
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
To use the Master or Slave SCL low extend time-outs, enable the SCL Low Time-
out (CTRLA.LOWTOUT=1).
2 - In USART autobaud mode, missing stop bits are not recognized as
inconsistent sync (ISF) or framing (FERR) errors. Errata reference: 13852
Fix/Workaround:
None
3 - If the SERCOM is enabled in SPI mode with SSL detection enabled
(CTRLB.SSDE) and CTRLB.RXEN=1, an erroneous slave select low interrupt
(INTFLAG.SSL) can be generated. Errata reference: 13369
Fix/Workaround:
Enable the SERCOM first with CTRLB.RXEN=0. In a subsequent write, set
CTRLB.RXEN=1.
4 - In TWI master mode, an ongoing transaction should be stalled
immediately when DBGCTRL.DBGSTOP is set and the CPU enters debug
mode. Instead, it is stopped when the current byte transaction is completed
and the corresponding interrupt is triggered if enabled. Errata reference:
12499
Fix/Workaround:
In TWI master mode, keep DBGCTRL.DBGSTOP=0 when in debug mode.
47.1.10 USB
1 - The FLENC register negative sign management is not correct. Errata
reference: 11472
Fix/Workaround:
The following rule must be used for negative values:
- FLENC 8h is equal to 0 decimal.
- FLENC 9h to Fh are equal to -1 to -7 decimal instead of -7 to -1.
47.1.11 TC
1 - Spurious TC overflow and Match/Capture events may occur. Errata
reference: 13268
Fix/Workaround:
Do not use the TC overflow and Match/Capture events. Use the corresponding
Interrupts instead.
47.1.12 TCC
1 - The TCC interrupts FAULT1, FAULT0, FAULTB, FAULTA, DFS, ERR,and
CNT cannot wake up the chip from standby mode. Errata reference: 11951
1138
Atmel | SMART SAM R21 [DATASHEET]
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Fix/Workaround:
Do not use the TCC interrupts FAULT1, FAULT0, FAULTB, FAULTA, DFS, ERR,
or CNT to wake up the chip from standby mode.
2 - If the OVF flag in the INTFLAG register is already set when enabling the
DMA, this will trigger an immediate DMA transfer and overwrite the current
buffered value in the TCC register. Errata reference: 12127
Fix/Workaround:
None
3 - In RAMP 2 mode with Fault keep, qualified and restart: Errata reference:
13262
If a fault occurred at the end of the period during the qualified state, the switch to
the next ramp can have two restarts.
Fix/Workaround:
Avoid faults few cycles before the end or the beginning of a ramp.
4 - With blanking enabled, a recoverable fault that occurs during the first
increment of a rising TCC is not blanked. Errata reference: 12519
Fix/Workaround:
None
5 - In Dual slope mode a Retrigger Event does not clear the TCC counter.
Errata reference: 12354
Fix/Workaround:
None
6 - In two ramp mode, two events will be generated per cycle, one on each
ramp’s end. EVCTRL.CNTSEL.END cannot be used to identify the end of a
double ramp cycle. Errata reference: 12224
Fix/Workaround:
None
7 - If an input event triggered STOP action is performed at the same time as
the counter overflows, the first pulse width of the subsequent counter start
can be altered with one prescaled clock cycle. Errata reference: 12107
Fix/Workaround:
None
8 - When the RUNSTDBY bit is written after the TCC is enabled, the
respective TCC APB bus is stalled and the RUNDSTBY bit in the TCC CTRLA
register is not enabled-protected. Errata reference: 12477
1139
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Fix/Workaround:
None.
9 - TCC fault filtering on inverted fault is not working. Errata reference:
12512
Fix/Workaround:
Use only non-inverted faults.
10 - When waking up from the STANDBY power save mode, the
SYNCBUSY.CTRLB and SYNCBUSY.STATUS bits may be locked to 1. Errata
reference: 12227
Fix/Workaround:
After waking up from STANDBY power save mode, perform a software reset of
the TCC if you are using the SYNCBUSY.CTRLB and SYNCBUSY.STATUS bits
11 - When the Peripheral Access Controller (PAC) protection is enabled,
writing to WAVE or WAVEB registers will not cause a hardware exception.
Errata reference: 11468
Fix/Workaround:
None
12 - If the MCx flag in the INTFLAG register is set when enabling the DMA,
this will trigger an immediate DMA transfer and overwrite the current
buffered value in the TCC register. Errata reference: 12155
Fix/Workaround:
None
47.1.13 PTC
1 - WCOMP interrupt flag is not stable. The WCOMP interrupt flag will not
always be set as described in the datasheet. Errata reference: 12860
Fix/Workaround:
Do not use the WCOMP interrupt. Use the WCOMP event.
47.2 Revision B
47.2.1 Device
1 - In single shot mode and at 125°C, the ADC conversions have linearity
errors. Errata reference: 13277
Fix/Workaround:
- Workaround 1: At 125°C, do not use the ADC in single shot mode; use the
ADC in free running mode only.
1140
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
- Workaround 2: At 125°C, use the ADC in single shot mode only with
VDDANA > 3V.
2 - On pin PA24 and PA25 the pull-up and pull-down configuration is not
disabled automatically when alternative pin function is enabled. Errata
reference: 12368
Fix/Workaround:
For pin PA24 and PA25, the GPIO pull-up and pull-down must be disabled before
enabling alternative functions on them.
3 - The PDM2 mode (i.e. when using two PDM microphones) does not work.
Errata reference: 13410
Fix/Workaround:
None. Only one PDM microphone can be connected. Thus, the I2S controller
should be configured in normal Receive mode with one slot.
4 - The I2S is non-functional in the slave mode (i.e. when (FSSEL=1,
SCKSEL=1). Errata reference: 13407
Fix/Workaround:
None. FSSEL and SCKSEL must be 0.
5 - If APB clock is stopped and GCLK clock is running, APB read access to
read-synchronized registers will freeze the system. The CPU and the DAP
AHB-AP are stalled, as a consequence debug operation is impossible.
Errata reference: 10416
Fix/Workaround:
Do not make read access to read-synchronized registers when APB clock is
stopped and GCLK is running. To recover from this situation, power cycle the
device or reset the device using the RESETN pin.
6 - In I2C Slave mode, writing the CTRLB register when in the AMATCH or
DRDY interrupt service routines can cause the state machine to reset. Errata
reference: 13574
Fix/Workaround:
Write CTRLB.ACKACT to 0 using the following sequence:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = 0;
// Re-enable interrupts if applicable.
Write CTRLB.ACKACT to 1 using the following sequence:
// If higher priority interrupts exist, then disable so that the
1141
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
// Re-enable interrupts if applicable.
Otherwise, only write to CTRLB in the AMATCH or DRDY interrupts if it is to close
out a transaction.
When not closing a transaction, clear the AMATCH interrupt by writing a 1 to its bit
position instead of using CTRLB.CMD. The DRDY interrupt is automatically
cleared by reading/writing to the DATA register in smart mode. If not in smart
mode, DRDY should be cleared by writing a 1 to its bit position.
Code replacements examples:
Current:
SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
Change to:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
// Re-enable interrupts if applicable.
Current:
SERCOM - CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
Change to:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = 0;
// Re-enable interrupts if applicable.
Current:
/* ACK or NACK address */
SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
Change to:
// CMD=0x3 clears all interrupts, so to keep the result similar,
// PREC is cleared if it was set.
if (SERCOM - INTFLAG.bit.PREC) SERCOM - INTFLAG.reg =
SERCOM_I2CS_INTFLAG_PREC;
SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
1142
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
7 - PA24 and PA25 cannot be used as input when configured as GPIO with
continuous sampling (cannot be read by PORT). Errata reference: 12005
Fix/Workaround:
- Use PA24 and PA25 for peripherals or only as output pins.
- Or configure PA31 to PA24 for on-demand sampling (CTRL[31:24] all zeroes)
and access the IN register through the APB (not the IOBUS), to allow waiting for
on-demand sampling.
8 - Rx serializer in the RIGHT Data Slot Formatting Adjust mode
(SERCTRL.SLOTADJ clear) does not work when the slot size is not 32 bits.
Errata reference: 13411
Fix/Workaround:
In SERCTRL.SERMODE RX, SERCTRL.SLOTADJ RIGHT must be used with
CLKCTRL.SLOTSIZE 32.
9 - The SYSTICK calibration value is incorrect. Errata reference: 14154
Fix/Workaround:
The correct SYSTICK calibration value is 0x40000000. This value should not be
used to initialize the Systick RELOAD value register, which should be initialized
instead with a value depending on the main clock frequency and on the tick period
required by the application. For a detailed description of the SYSTICK module,
refer to the official ARM Cortex-M0+ documentation.
10 - Depending CPU clock/ I2S clock ratio, the SYNCBUSY.CKEN0 flag
occasionally stuck at 1 when starting a new audio stream with
CTRLA.SWRST=1, then CTRLA.ENABLE=1, then CTRLA.CKEN0=1 Errata
reference: 13408
Fix/Workaround:
Disable the IP by writing 0 to CTRLA.ENABLE before resetting it
(CTRLA.SWRST=1).
11 - In Standby, Idle1 and Idle2 sleep modes the device might not wake up
from sleep. An External Reset, Power on Reset or Watch Dog Reset will start
the device again. Errata reference: 13140
Fix/Workaround:
the SLEEPPRM bits in the NVMCTRL.CTRLB register must be written to 3
(NVMCTRL - CTRLB.bit.SLEEPPRM = 3) to ensure correct operation of the
device. The average power consumption of the device will increase with 20uA
compared to numbers in the electrical characteristics chapter.
12 - While the internal startup is not completed, PA07 pin is driven low by
the chip. Then as all the other pins it is configured as an High Impedance
pin. Errata reference: 12118
1143
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Fix/Workaround:
None
13 - Digital pin outputs from Timer/Counters, AC (Analog Comparator),
GCLK (Generic Clock Controller), and SERCOM (I2C and SPI) do not change
value during standby sleep mode. Errata reference: 12537
Fix/Workaround:
Set the voltage regulator in Normal mode before entering STANDBY sleep mode
in order to keep digital pin output enabled. This is done by setting the RUNSTDBY
bit in the VREG register.
14 - The voltage regulator in low power mode is not functional at
temperatures above 85C. Errata reference: 12291
Fix/Workaround:
Enable normal mode on the voltage regulator in standby sleep mode.
Example code:
// Set the voltage regulator in normal mode configuration in standby sleep mode
SYSCTRL->VREG.bit.RUNSTDBY = 1;
15 - If the external XOSC32K is broken, neither the external pin RST nor the
GCLK software reset can reset the GCLK generators using XOSC32K as
source clock. Errata reference: 12164
Fix/Workaround:
Do a power cycle to reset the GCLK generators after an external XOSC32K
failure.
47.2.2 DSU
1 - If a debugger has issued a DSU Cold-Plugging procedure and then
released the CPU from the resulting ""CPU Reset Extension"", the CPU will
be held in ""CPU Reset Extension"" after any upcoming reset event. Errata
reference: 12015
Fix/workaround:
The CPU must be released from the ""CPU Reset Extension"" either by writing a
one in the DSU STATUSA.CRSTEXT register or by applying an external reset
with SWCLK high or by power cycling the device.
2 - The MBIST ""Pause-on-Error"" feature is not functional on this device.
Errata reference: 14324
Fix/Workaround: Do not use the ""Pause-on-Error"" feature.
1144
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
47.2.3 PM
1 - In debug mode, if a watchdog reset occurs, the debug session is lost.
Errata reference: 12196
Fix/Workaround:
A new debug session must be restart after a watchdog reset.
47.2.4 XOSC32K
1 - The automatic amplitude control of the XOSC32K does not work. Errata
reference: 10933
Fix/Workaround:
Use the XOSC32K with Automatic Amplitude control disabled
(XOSC32K.AAMPEN = 0)
47.2.5 DFLL48M
1 - The DFLL clock must be requested before being configured otherwise a
write access to a DFLL register can freeze the device. Errata reference: 9905
Fix/Workaround:
Write a zero to the DFLL ONDEMAND bit in the DFLLCTRL register before
configuring the DFLL module.
2 - If the DFLL48M reaches the maximum or minimum COARSE or FINE
calibration values during the locking sequence, an out of bounds interrupt
will be generated. These interrupts will be generated even if the final
calibration values at DFLL48M lock are not at maximum or minimum, and
might therefore be false out of bounds interrupts. Errata reference: 10669
Fix/Workaround:
Check that the lockbits: DFLLLCKC and DFLLLCKF in the SYSCTRL Interrupt
Flag Status and Clear register (INTFLAG) are both set before enabling the
DFLLOOB interrupt.
3 - The DFLL status bits in the PCLKSR register during the USB clock
recovery mode can be wrong after a USB suspend state. Errata reference:
11938
Fix/Workaround:
Do not monitor the DFLL status bits in the PCLKSR register during the USB clock
recovery mode.
47.2.6 DMAC
1 - If data is written to CRCDATAIN in two consecutive instructions, the CRC
computation may be incorrect. Errata reference: 13507
Fix/Workaround:
1145
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Add a NOP instruction between each write to CRCDATAIN register.
47.2.7 NVMCTRL
1 - Default value of MANW in NVM.CTRLB is 0. Errata reference: 13134
This can lead to spurious writes to the NVM if a data write is done through a
pointer with a wrong address corresponding to NVM area.
Fix/Workaround:
Set MANW in the NVM.CTRLB to 1 at startup
2 - When the part is secured and EEPROM emulation area configured to
none, the CRC32 is not executed on the entire flash area but up to the on-
chip flash size minus half a row. Errata reference: 11988
Fix/Workaround:
When using CRC32 on a protected device with EEPROM emulation area
configured to none, compute the reference CRC32 value to the full chip flash size
minus half row.
3 - When external reset is active it causes a high leakage current on VDDIO.
Errata reference: 13446
Fix/Workaround:
Minimize the time external reset is active.
47.2.8 SERCOM
1 - The I2C Slave SCL Low Extend Time-out (CTRLA.SEXTTOEN) and Master
SCL Low Extend Time-out (CTRLA.MEXTTOEN) cannot be used if SCL Low
Time-out (CTRLA.LOWTOUT) is disabled. When SCTRLA.LOWTOUT=0, the
GCLK_SERCOM_SLOW is not requested. Errata reference: 12003
Fix/Workaround:
To use the Master or Slave SCL low extend time-outs, enable the SCL Low Time-
out (CTRLA.LOWTOUT=1).
2 - In USART autobaud mode, missing stop bits are not recognized as
inconsistent sync (ISF) or framing (FERR) errors. Errata reference: 13852
Fix/Workaround:
None
3 - If the SERCOM is enabled in SPI mode with SSL detection enabled
(CTRLB.SSDE) and CTRLB.RXEN=1, an erroneous slave select low interrupt
(INTFLAG.SSL) can be generated. Errata reference: 13369
Fix/Workaround:
1146
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Enable the SERCOM first with CTRLB.RXEN=0. In a subsequent write, set
CTRLB.RXEN=1.
4 - In TWI master mode, an ongoing transaction should be stalled
immediately when DBGCTRL.DBGSTOP is set and the CPU enters debug
mode. Instead, it is stopped when the current byte transaction is completed
and the corresponding interrupt is triggered if enabled. Errata reference:
12499
Fix/Workaround:
In TWI master mode, keep DBGCTRL.DBGSTOP=0 when in debug mode.
47.2.9 TC
1 - Spurious TC overflow and Match/Capture events may occur. Errata
reference: 13268
Fix/Workaround:
Do not use the TC overflow and Match/Capture events. Use the corresponding
Interrupts instead.
47.2.10 TCC
1 - In RAMP 2 mode with Fault keep, qualified and restart: Errata reference:
13262
If a fault occurred at the end of the period during the qualified state, the switch to
the next ramp can have two restarts.
Fix/Workaround:
Avoid faults few cycles before the end or the beginning of a ramp.
2 - With blanking enabled, a recoverable fault that occurs during the first
increment of a rising TCC is not blanked. Errata reference: 12519
Fix/Workaround:
None
3 - In Dual slope mode a Retrigger Event does not clear the TCC counter.
Errata reference: 12354
Fix/Workaround:
None
4 - In two ramp mode, two events will be generated per cycle, one on each
ramp’s end. EVCTRL.CNTSEL.END cannot be used to identify the end of a
double ramp cycle. Errata reference: 12224
Fix/Workaround:
None
1147
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
5 - If an input event triggered STOP action is performed at the same time as
the counter overflows, the first pulse width of the subsequent counter start
can be altered with one prescaled clock cycle. Errata reference: 12107
Fix/Workaround:
None
6 - When the RUNSTDBY bit is written after the TCC is enabled, the
respective TCC APB bus is stalled and the RUNDSTBY bit in the TCC CTRLA
register is not enabled-protected. Errata reference: 12477
Fix/Workaround:
None.
7 - TCC fault filtering on inverted fault is not working. Errata reference:
12512
Fix/Workaround:
Use only non-inverted faults.
8 - When waking up from the STANDBY power save mode, the
SYNCBUSY.CTRLB and SYNCBUSY.STATUS bits may be locked to 1. Errata
reference: 12227
Fix/Workaround:
After waking up from STANDBY power save mode, perform a software reset of
the TCC if you are using the SYNCBUSY.CTRLB and SYNCBUSY.STATUS bits
9 - When the Peripheral Access Controller (PAC) protection is enabled,
writing to WAVE or WAVEB registers will not cause a hardware exception.
Errata reference: 11468
Fix/Workaround:
None
10 - If the MCx flag in the INTFLAG register is set when enabling the DMA,
this will trigger an immediate DMA transfer and overwrite the current
buffered value in the TCC register. Errata reference: 12155
Fix/Workaround:
None
47.2.11 PTC
1 - WCOMP interrupt flag is not stable. The WCOMP interrupt flag will not
always be set as described in the datasheet. Errata reference: 12860
Fix/Workaround:
Do not use the WCOMP interrupt. Use the WCOMP event.
1148
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
47.3 Revision C
47.3.1 Device
1 - In single shot mode and at 125°C, the ADC conversions have linearity
errors. Errata reference: 13277
Fix/Workaround:
- Workaround 1: At 125°C, do not use the ADC in single shot mode; use the
ADC in free running mode only.
- Workaround 2: At 125°C, use the ADC in single shot mode only with
VDDANA > 3V.
2 - In the table ""NVM User Row Mapping"", the WDT Window bitfield default
value on silicon is not as specified in the datasheet. The datasheet defines
the default value as 0x5, while it is 0xB on silicon. Errata reference: 13951
Fix/Workaround:
None.
3 - On pin PA24 and PA25 the pull-up and pull-down configuration is not
disabled automatically when alternative pin function is enabled. Errata
reference: 12368
Fix/Workaround:
For pin PA24 and PA25, the GPIO pull-up and pull-down must be disabled before
enabling alternative functions on them.
4 - If APB clock is stopped and GCLK clock is running, APB read access to
read-synchronized registers will freeze the system. The CPU and the DAP
AHB-AP are stalled, as a consequence debug operation is impossible.
Errata reference: 10416
Fix/Workaround:
Do not make read access to read-synchronized registers when APB clock is
stopped and GCLK is running. To recover from this situation, power cycle the
device or reset the device using the RESETN pin.
5 - In I2C Slave mode, writing the CTRLB register when in the AMATCH or
DRDY interrupt service routines can cause the state machine to reset. Errata
reference: 13574
Fix/Workaround:
Write CTRLB.ACKACT to 0 using the following sequence:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = 0;
1149
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
// Re-enable interrupts if applicable.
Write CTRLB.ACKACT to 1 using the following sequence:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
// Re-enable interrupts if applicable.
Otherwise, only write to CTRLB in the AMATCH or DRDY interrupts if it is to close
out a transaction.
When not closing a transaction, clear the AMATCH interrupt by writing a 1 to its bit
position instead of using CTRLB.CMD. The DRDY interrupt is automatically
cleared by reading/writing to the DATA register in smart mode. If not in smart
mode, DRDY should be cleared by writing a 1 to its bit position.
Code replacements examples:
Current:
SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
Change to:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
// Re-enable interrupts if applicable.
Current:
SERCOM - CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
Change to:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = 0;
// Re-enable interrupts if applicable.
Current:
/* ACK or NACK address */
SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
Change to:
// CMD=0x3 clears all interrupts, so to keep the result similar,
1150
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
// PREC is cleared if it was set.
if (SERCOM - INTFLAG.bit.PREC) SERCOM - INTFLAG.reg =
SERCOM_I2CS_INTFLAG_PREC;
SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
6 - PA24 and PA25 cannot be used as input when configured as GPIO with
continuous sampling (cannot be read by PORT). Errata reference: 12005
Fix/Workaround:
- Use PA24 and PA25 for peripherals or only as output pins.
- Or configure PA31 to PA24 for on-demand sampling (CTRL[31:24] all zeroes)
and access the IN register through the APB (not the IOBUS), to allow waiting for
on-demand sampling.
7 - Rx serializer in the RIGHT Data Slot Formatting Adjust mode
(SERCTRL.SLOTADJ clear) does not work when the slot size is not 32 bits.
Errata reference: 13411
Fix/Workaround:
In SERCTRL.SERMODE RX, SERCTRL.SLOTADJ RIGHT must be used with
CLKCTRL.SLOTSIZE 32.
8 - The SYSTICK calibration value is incorrect. Errata reference: 14154
Fix/Workaround:
The correct SYSTICK calibration value is 0x40000000. This value should not be
used to initialize the Systick RELOAD value register, which should be initialized
instead with a value depending on the main clock frequency and on the tick period
required by the application. For a detailed description of the SYSTICK module,
refer to the official ARM Cortex-M0+ documentation.
9 - In Standby, Idle1 and Idle2 sleep modes the device might not wake up
from sleep. An External Reset, Power on Reset or Watch Dog Reset will start
the device again. Errata reference: 13140
Fix/Workaround:
the SLEEPPRM bits in the NVMCTRL.CTRLB register must be written to 3
(NVMCTRL - CTRLB.bit.SLEEPPRM = 3) to ensure correct operation of the
device. The average power consumption of the device will increase with 20uA
compared to numbers in the electrical characteristics chapter.
10 - While the internal startup is not completed, PA07 pin is driven low by
the chip. Then as all the other pins it is configured as an High Impedance
pin. Errata reference: 12118
Fix/Workaround:
None
1151
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
11 - The voltage regulator in low power mode is not functional at
temperatures above 85C. Errata reference: 12291
Fix/Workaround:
Enable normal mode on the voltage regulator in standby sleep mode.
Example code:
// Set the voltage regulator in normal mode configuration in standby sleep mode
SYSCTRL->VREG.bit.RUNSTDBY = 1;
12 - If the external XOSC32K is broken, neither the external pin RST nor the
GCLK software reset can reset the GCLK generators using XOSC32K as
source clock. Errata reference: 12164
Fix/Workaround:
Do a power cycle to reset the GCLK generators after an external XOSC32K
failure.
47.3.2 DSU
1 - If a debugger has issued a DSU Cold-Plugging procedure and then
released the CPU from the resulting ""CPU Reset Extension"", the CPU will
be held in ""CPU Reset Extension"" after any upcoming reset event. Errata
reference: 12015
Fix/workaround:
The CPU must be released from the ""CPU Reset Extension"" either by writing a
one in the DSU STATUSA.CRSTEXT register or by applying an external reset
with SWCLK high or by power cycling the device.
2 - The MBIST ""Pause-on-Error"" feature is not functional on this device.
Errata reference: 14324
Fix/Workaround: Do not use the ""Pause-on-Error"" feature.
47.3.3 PM
1 - In debug mode, if a watchdog reset occurs, the debug session is lost.
Errata reference: 12196
Fix/Workaround:
A new debug session must be restart after a watchdog reset.
47.3.4 XOSC32K
1 - The automatic amplitude control of the XOSC32K does not work. Errata
reference: 10933
Fix/Workaround:
Use the XOSC32K with Automatic Amplitude control disabled
(XOSC32K.AAMPEN = 0)
1152
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
47.3.5 DFLL48M
1 - The DFLL clock must be requested before being configured otherwise a
write access to a DFLL register can freeze the device. Errata reference: 9905
Fix/Workaround:
Write a zero to the DFLL ONDEMAND bit in the DFLLCTRL register before
configuring the DFLL module.
2 - If the DFLL48M reaches the maximum or minimum COARSE or FINE
calibration values during the locking sequence, an out of bounds interrupt
will be generated. These interrupts will be generated even if the final
calibration values at DFLL48M lock are not at maximum or minimum, and
might therefore be false out of bounds interrupts. Errata reference: 10669
Fix/Workaround:
Check that the lockbits: DFLLLCKC and DFLLLCKF in the SYSCTRL Interrupt
Flag Status and Clear register (INTFLAG) are both set before enabling the
DFLLOOB interrupt.
3 - The DFLL status bits in the PCLKSR register during the USB clock
recovery mode can be wrong after a USB suspend state. Errata reference:
11938
Fix/Workaround:
Do not monitor the DFLL status bits in the PCLKSR register during the USB clock
recovery mode.
47.3.6 DMAC
1 - If data is written to CRCDATAIN in two consecutive instructions, the CRC
computation may be incorrect. Errata reference: 13507
Fix/Workaround:
Add a NOP instruction between each write to CRCDATAIN register.
47.3.7 NVMCTRL
1 - Default value of MANW in NVM.CTRLB is 0. Errata reference: 13134
This can lead to spurious writes to the NVM if a data write is done through a
pointer with a wrong address corresponding to NVM area.
Fix/Workaround:
Set MANW in the NVM.CTRLB to 1 at startup
2 - When the part is secured and EEPROM emulation area configured to
none, the CRC32 is not executed on the entire flash area but up to the on-
chip flash size minus half a row. Errata reference: 11988
1153
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Fix/Workaround:
When using CRC32 on a protected device with EEPROM emulation area
configured to none, compute the reference CRC32 value to the full chip flash size
minus half row.
3 - When external reset is active it causes a high leakage current on VDDIO.
Errata reference: 13446
Fix/Workaround:
Minimize the time external reset is active.
47.3.8 SERCOM
1 - The I2C Slave SCL Low Extend Time-out (CTRLA.SEXTTOEN) and Master
SCL Low Extend Time-out (CTRLA.MEXTTOEN) cannot be used if SCL Low
Time-out (CTRLA.LOWTOUT) is disabled. When SCTRLA.LOWTOUT=0, the
GCLK_SERCOM_SLOW is not requested. Errata reference: 12003
Fix/Workaround:
To use the Master or Slave SCL low extend time-outs, enable the SCL Low Time-
out (CTRLA.LOWTOUT=1).
2 - In USART autobaud mode, missing stop bits are not recognized as
inconsistent sync (ISF) or framing (FERR) errors. Errata reference: 13852
Fix/Workaround:
None
3 - If the SERCOM is enabled in SPI mode with SSL detection enabled
(CTRLB.SSDE) and CTRLB.RXEN=1, an erroneous slave select low interrupt
(INTFLAG.SSL) can be generated. Errata reference: 13369
Fix/Workaround:
Enable the SERCOM first with CTRLB.RXEN=0. In a subsequent write, set
CTRLB.RXEN=1.
4 - In TWI master mode, an ongoing transaction should be stalled
immediately when DBGCTRL.DBGSTOP is set and the CPU enters debug
mode. Instead, it is stopped when the current byte transaction is completed
and the corresponding interrupt is triggered if enabled. Errata reference:
12499
Fix/Workaround:
In TWI master mode, keep DBGCTRL.DBGSTOP=0 when in debug mode.
47.3.9 TC
1 - Spurious TC overflow and Match/Capture events may occur. Errata
reference: 13268
1154
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Fix/Workaround:
Do not use the TC overflow and Match/Capture events. Use the corresponding
Interrupts instead.
47.3.10 TCC
1 - In RAMP 2 mode with Fault keep, qualified and restart: Errata reference:
13262
If a fault occurred at the end of the period during the qualified state, the switch to
the next ramp can have two restarts.
Fix/Workaround:
Avoid faults few cycles before the end or the beginning of a ramp.
2 - With blanking enabled, a recoverable fault that occurs during the first
increment of a rising TCC is not blanked. Errata reference: 12519
Fix/Workaround:
None
3 - In Dual slope mode a Retrigger Event does not clear the TCC counter.
Errata reference: 12354
Fix/Workaround:
None
4 - In two ramp mode, two events will be generated per cycle, one on each
ramp’s end. EVCTRL.CNTSEL.END cannot be used to identify the end of a
double ramp cycle. Errata reference: 12224
Fix/Workaround:
None
5 - If an input event triggered STOP action is performed at the same time as
the counter overflows, the first pulse width of the subsequent counter start
can be altered with one prescaled clock cycle. Errata reference: 12107
Fix/Workaround:
None
6 - When the RUNSTDBY bit is written after the TCC is enabled, the
respective TCC APB bus is stalled and the RUNDSTBY bit in the TCC CTRLA
register is not enabled-protected. Errata reference: 12477
Fix/Workaround:
None.
7 - TCC fault filtering on inverted fault is not working. Errata reference:
12512
1155
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
Fix/Workaround:
Use only non-inverted faults.
8 - When waking up from the STANDBY power save mode, the
SYNCBUSY.CTRLB and SYNCBUSY.STATUS bits may be locked to 1. Errata
reference: 12227
Fix/Workaround:
After waking up from STANDBY power save mode, perform a software reset of
the TCC if you are using the SYNCBUSY.CTRLB and SYNCBUSY.STATUS bits
9 - When the Peripheral Access Controller (PAC) protection is enabled,
writing to WAVE or WAVEB registers will not cause a hardware exception.
Errata reference: 11468
Fix/Workaround:
None
10 - If the MCx flag in the INTFLAG register is set when enabling the DMA,
this will trigger an immediate DMA transfer and overwrite the current
buffered value in the TCC register. Errata reference: 12155
Fix/Workaround:
None
47.3.11 PTC
1 - WCOMP interrupt flag is not stable. The WCOMP interrupt flag will not
always be set as described in the datasheet. Errata reference: 12860
Fix/Workaround:
Do not use the WCOMP interrupt. Use the WCOMP event.
47.4 Revision D
47.4.1 Device
1 - In single shot mode and at 125°C, the ADC conversions have linearity
errors. Errata reference: 13277
Fix/Workaround:
- Workaround 1: At 125°C, do not use the ADC in single shot mode; use the
ADC in free running mode only.
- Workaround 2: At 125°C, use the ADC in single shot mode only with
VDDANA > 3V.
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2 - In the table ""NVM User Row Mapping"", the WDT Window bitfield default
value on silicon is not as specified in the datasheet. The datasheet defines
the default value as 0x5, while it is 0xB on silicon. Errata reference: 13951
Fix/Workaround:
None.
3 - On pin PA24 and PA25 the pull-up and pull-down configuration is not
disabled automatically when alternative pin function is enabled. Errata
reference: 12368
Fix/Workaround:
For pin PA24 and PA25, the GPIO pull-up and pull-down must be disabled before
enabling alternative functions on them.
4 - If APB clock is stopped and GCLK clock is running, APB read access to
read-synchronized registers will freeze the system. The CPU and the DAP
AHB-AP are stalled, as a consequence debug operation is impossible.
Errata reference: 10416
Fix/Workaround:
Do not make read access to read-synchronized registers when APB clock is
stopped and GCLK is running. To recover from this situation, power cycle the
device or reset the device using the RESETN pin.
5 - In I2C Slave mode, writing the CTRLB register when in the AMATCH or
DRDY interrupt service routines can cause the state machine to reset. Errata
reference: 13574
Fix/Workaround:
Write CTRLB.ACKACT to 0 using the following sequence:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = 0;
// Re-enable interrupts if applicable.
Write CTRLB.ACKACT to 1 using the following sequence:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
// Re-enable interrupts if applicable.
Otherwise, only write to CTRLB in the AMATCH or DRDY interrupts if it is to close
out a transaction.
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When not closing a transaction, clear the AMATCH interrupt by writing a 1 to its bit
position instead of using CTRLB.CMD. The DRDY interrupt is automatically
cleared by reading/writing to the DATA register in smart mode. If not in smart
mode, DRDY should be cleared by writing a 1 to its bit position.
Code replacements examples:
Current:
SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
Change to:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
// Re-enable interrupts if applicable.
Current:
SERCOM - CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
Change to:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = 0;
// Re-enable interrupts if applicable.
Current:
/* ACK or NACK address */
SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
Change to:
// CMD=0x3 clears all interrupts, so to keep the result similar,
// PREC is cleared if it was set.
if (SERCOM - INTFLAG.bit.PREC) SERCOM - INTFLAG.reg =
SERCOM_I2CS_INTFLAG_PREC;
SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
6 - PA24 and PA25 cannot be used as input when configured as GPIO with
continuous sampling (cannot be read by PORT). Errata reference: 12005
Fix/Workaround:
- Use PA24 and PA25 for peripherals or only as output pins.
- Or configure PA31 to PA24 for on-demand sampling (CTRL[31:24] all zeroes)
and access the IN register through the APB (not the IOBUS), to allow waiting for
on-demand sampling.
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7 - Rx serializer in the RIGHT Data Slot Formatting Adjust mode (SERCTRL.SLOTADJ clear)
does not work when the slot size is not 32 bits. Errata reference: 13411
Fix/Workaround:
In SERCTRL.SERMODE RX, SERCTRL.SLOTADJ RIGHT must be used with
CLKCTRL.SLOTSIZE 32.
8 - The SYSTICK calibration value is incorrect. Errata reference: 14154
Fix/Workaround:
The correct SYSTICK calibration value is 0x40000000. This value should not be used to initialize
the Systick RELOAD value register, which should be initialized instead with a value depending on
the main clock frequency and on the tick period required by the application. For a detailed
description of the SYSTICK module, refer to the official ARM Cortex-M0+ documentation.
9 - While the internal startup is not completed, PA07 pin is driven low by the chip. Then as all
the other pins it is configured as an High Impedance pin. Errata reference: 12118
Fix/Workaround:
None
10 - If the external XOSC32K is broken, neither the external pin RST nor the GCLK software
reset can reset the GCLK generators using XOSC32K as source clock. Errata reference:
12164
Fix/Workaround:
Do a power cycle to reset the GCLK generators after an external XOSC32K failure.
11 - The voltage regulator in low power mode is not functional at temperatures above 85C.
Errata reference: 12291
Fix/Workaround:
Enable normal mode on the voltage regulator in standby sleep mode.
Example code:
// Set the voltage regulator in normal mode configuration in standby sleep mode
SYSCTRL->VREG.bit.RUNSTDBY = 1;
47.4.2 DSU
1 - If a debugger has issued a DSU Cold-Plugging procedure and then released the CPU
from the resulting ""CPU Reset Extension"", the CPU will be held in ""CPU Reset
Extension"" after any upcoming reset event. Errata reference: 12015
Fix/workaround:
The CPU must be released from the ""CPU Reset Extension"" either by writing a one in the DSU
STATUSA.CRSTEXT register or by applying an external reset with SWCLK high or by power
cycling the device.
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2 - The MBIST ""Pause-on-Error"" feature is not functional on this device. Errata reference:
14324
Fix/Workaround: Do not use the ""Pause-on-Error"" feature.
47.4.3 PM
1 - In debug mode, if a watchdog reset occurs, the debug session is lost. Errata reference:
12196
Fix/Workaround:
A new debug session must be restart after a watchdog reset.
47.4.4 XOSC32K
1 - The automatic amplitude control of the XOSC32K does not work. Errata reference: 10933
Fix/Workaround:
Use the XOSC32K with Automatic Amplitude control disabled (XOSC32K.AAMPEN = 0)
47.4.5 DFLL48M
1 - The DFLL clock must be requested before being configured otherwise a write access to a
DFLL register can freeze the device. Errata reference: 9905
Fix/Workaround:
Write a zero to the DFLL ONDEMAND bit in the DFLLCTRL register before configuring the DFLL
module.
2 - If the DFLL48M reaches the maximum or minimum COARSE or FINE calibration values
during the locking sequence, an out of bounds interrupt will be generated. These interrupts
will be generated even if the final calibration values at DFLL48M lock are not at maximum or
minimum, and might therefore be false out of bounds interrupts. Errata reference: 10669
Fix/Workaround:
Check that the lockbits: DFLLLCKC and DFLLLCKF in the SYSCTRL Interrupt Flag Status and
Clear register (INTFLAG) are both set before enabling the DFLLOOB interrupt.
3 - The DFLL status bits in the PCLKSR register during the USB clock recovery mode can be
wrong after a USB suspend state. Errata reference: 11938
Fix/Workaround:
Do not monitor the DFLL status bits in the PCLKSR register during the USB clock recovery mode.
47.4.6 DMAC
1 - If data is written to CRCDATAIN in two consecutive instructions, the CRC computation
may be incorrect. Errata reference: 13507
Fix/Workaround:
Add a NOP instruction between each write to CRCDATAIN register.
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47.4.7 NVMCTRL
1 - Default value of MANW in NVM.CTRLB is 0. Errata reference: 13134
This can lead to spurious writes to the NVM if a data write is done through a pointer with a wrong
address corresponding to NVM area.
Fix/Workaround:
Set MANW in the NVM.CTRLB to 1 at startup
2 - When the part is secured and EEPROM emulation area configured to none, the CRC32 is
not executed on the entire flash area but up to the on-chip flash size minus half a row. Errata
reference: 11988
Fix/Workaround:
When using CRC32 on a protected device with EEPROM emulation area configured to none,
compute the reference CRC32 value to the full chip flash size minus half row.
3 - When external reset is active it causes a high leakage current on VDDIO. Errata
reference: 13446
Fix/Workaround:
Minimize the time external reset is active.
47.4.8 SERCOM
1 - The I2C Slave SCL Low Extend Time-out (CTRLA.SEXTTOEN) and Master SCL Low
Extend Time-out (CTRLA.MEXTTOEN) cannot be used if SCL Low Time-out
(CTRLA.LOWTOUT) is disabled. When SCTRLA.LOWTOUT=0, the GCLK_SERCOM_SLOW is
not requested. Errata reference: 12003
Fix/Workaround:
To use the Master or Slave SCL low extend time-outs, enable the SCL Low Time-out
(CTRLA.LOWTOUT=1).
2 - In USART autobaud mode, missing stop bits are not recognized as inconsistent sync
(ISF) or framing (FERR) errors. Errata reference: 13852
Fix/Workaround:
None
3 - If the SERCOM is enabled in SPI mode with SSL detection enabled (CTRLB.SSDE) and
CTRLB.RXEN=1, an erroneous slave select low interrupt (INTFLAG.SSL) can be generated.
Errata reference: 13369
Fix/Workaround:
Enable the SERCOM first with CTRLB.RXEN=0. In a subsequent write, set CTRLB.RXEN=1.
4 - In TWI master mode, an ongoing transaction should be stalled immediately when
DBGCTRL.DBGSTOP is set and the CPU enters debug mode. Instead, it is stopped when the
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current byte transaction is completed and the corresponding interrupt is triggered if
enabled. Errata reference: 12499
Fix/Workaround:
In TWI master mode, keep DBGCTRL.DBGSTOP=0 when in debug mode.
47.4.9 TC
1 - Spurious TC overflow and Match/Capture events may occur. Errata reference: 13268
Fix/Workaround:
Do not use the TC overflow and Match/Capture events. Use the corresponding Interrupts instead.
47.4.10 TCC
1 - In RAMP 2 mode with Fault keep, qualified and restart: Errata reference: 13262
If a fault occurred at the end of the period during the qualified state, the switch to the next ramp can
have two restarts.
Fix/Workaround:
Avoid faults few cycles before the end or the beginning of a ramp.
2 - With blanking enabled, a recoverable fault that occurs during the first increment of a
rising TCC is not blanked. Errata reference: 12519
Fix/Workaround:
None
3 - In Dual slope mode a Retrigger Event does not clear the TCC counter. Errata reference:
12354
Fix/Workaround:
None
4 - In two ramp mode, two events will be generated per cycle, one on each ramp’s end.
EVCTRL.CNTSEL.END cannot be used to identify the end of a double ramp cycle. Errata
reference: 12224
Fix/Workaround:
None
5 - If an input event triggered STOP action is performed at the same time as the counter
overflows, the first pulse width of the subsequent counter start can be altered with one
prescaled clock cycle. Errata reference: 12107
Fix/Workaround:
None
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6 - When the RUNSTDBY bit is written after the TCC is enabled, the respective TCC APB bus
is stalled and the RUNDSTBY bit in the TCC CTRLA register is not enabled-protected. Errata
reference: 12477
Fix/Workaround:
None.
7 - TCC fault filtering on inverted fault is not working. Errata reference: 12512
Fix/Workaround:
Use only non-inverted faults.
8 - When waking up from the STANDBY power save mode, the SYNCBUSY.CTRLB and
SYNCBUSY.STATUS bits may be locked to 1. Errata reference: 12227
Fix/Workaround:
After waking up from STANDBY power save mode, perform a software reset of the TCC if you are
using the SYNCBUSY.CTRLB and SYNCBUSY.STATUS bits
9 - When the Peripheral Access Controller (PAC) protection is enabled, writing to WAVE or
WAVEB registers will not cause a hardware exception. Errata reference: 11468
Fix/Workaround:
None
10 - If the MCx flag in the INTFLAG register is set when enabling the DMA, this will trigger an
immediate DMA transfer and overwrite the current buffered value in the TCC register. Errata
reference: 12155
Fix/Workaround:
None
47.4.11 PTC
1 - WCOMP interrupt flag is not stable. The WCOMP interrupt flag will not always be set as
described in the datasheet. Errata reference: 12860
Fix/Workaround:
Do not use the WCOMP interrupt. Use the WCOMP event.
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48. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The referring revision in this
section are referring to the document revision.
48.1 Rev. G – 05/2016
48.2 Rev. F – 11/2015
General:
Removed references to device variant B.
Removed references to EEPROM Read While Write (RWW).
“I/O Multiplexing and Considerations” on page 12:
SWDIO added to the COM column in Table 5-1.
“EVSYS – Event System” on page 400:
CTRL.SWRST bit description updated.
“TCC – Timer/Counter for Control Applications” on page 609:
Table 28-1 on page 609: Number of waveform output (WO_NUM) for TCC0 updated from 8 to 6.
Register Summary: INTENCLR, INTENSET and INTFLAG registers updated.
“USB – Universal Serial Bus” on page 702:
HSOFC.FLENCE bit description updated.
“Schematic Checklist” on page 1112:
“External Real Time Oscillator” on page 1117: Table listing equivalent internal pin capacitance removed and replaced
with a reference to the electrical characteristics chapter.
Introduced 256KB+512KB Flash Offering:
“Ordering Information” on page 6: Added ATSAMR21E19A-MF and -MFT.
“Product Mapping” on page 23: Added SAM R21E19A to “Physical Memory Map” on page 24.
“Block Diagrams” on page 8: Updated “SAM R21 Interconnection” on page 9.
“DSU – Device Service Unit” on page 45: Added SAM R21E18A to Table 11-8.
“Electrical Characteristics” on page 1055: Added STANDBY current consumption numbers for SAM R21E19A in
“Power Consumption” on page 1060.
“Packaging Information” on page 1107: Added “32-pin QFN (32M5)” on page 1110.
“Electrical Characteristics at 125°C” on page 1171: Added VDD minimum voltage for SAM R21E19 in “General
Operating Ratings” on page 1171 and added section “Supply Characteristics” on page 1172.
“AT86RF233 Extended Feature Set” on page 1005
Added “High Data Rate Modes” on page 1013 (Only applicable for T= -40°C to 85°C).
“I/O Multiplexing and Considerations” on page 12:
Added USB/SOF1kHz to PA23 in the COM column in Table 5-1.
“SYSCTRL – System Controller” on page 143:
Updated description in “Drift Compensation” on page 151.
“NVMCTRL – Non-Volatile Memory Controller” on page 350
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48.3 Rev. E – 02/2015
48.4 Rev. D – 02/2015
Updated Product Dependencies, Clocks section: Removed reference to the AUTOWS bit.
“ADC – Analog-to-Digital Converter” on page 802:
Table 30-14: ADC AIN9 pin removed.
References to AREFB replaced with VREFB.
INPUTCTRL Register: Updated Table 30-14.
REFCTRL.REFSEL: Value 0x3 corrected to “Reserved” in Table 30-7.
“RFCTRL – AT86RF233 Front-End Control Signal Interface” on page 876
Updated Product Dependencies section.
“Electrical Characteristics” on page 1055
“Digital Frequency Locked Loop (DFLL48M) Characteristics” on page 1086: Removed note from Table 42-40.
“Schematic Checklist” on page 1112:
“Power Supply Connections” on page 1112: VDDCORE decoupling capacitor value updated from 100nF to 1µF.
References to AREFB replaced with VREFB.
“Electrical Characteristics at 125°C” on page 1171
“Digital Frequency Locked Loop (DFLL48M) Characteristics” on page 1187: Removed note from DFLL48M
Characteristics - Closed Loop Mode table.
“Power Consumption” on page 1174: Power consumption units updated.
“Description” on page 1
CoreMark score updated from 2.14 to 2.46 CoreMark/MHz.
“Processor And Architecture” on page 28:
“Configuration” on page 33: Removed green connection dots between DMAC Data and AHB-APB Bridge A and
Bridge B.
“AT86RF233 Microcontroller Interface” on page 883:
Figure 35-1: EXTINT1 replaced by EXTINT0.
“Schematic Checklist” on page 1112
Updated description in “Unused or Unconnected Pins” on page 1115.
“References” on page 1170:
Removed reference [7] AT86RF233 Software Programming Model.
“Description” on page 1 and “Features” on page 2:
Updated 250kB/s to 250kb/s.
“PORT” on page 373:
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48.5 Rev. C – 01/2015
48.6 Rev. B – 09/2014
“I/O Pin Configuration” on page 378: Removed reference to “open-drain”.
Access for DRVSTR bit in Pin Configuration n register (PINCFGn.DRVCTR) updated from W to R/W.
Errata:
Updated errata for revision A, B, C, D: Added Errata Reference 13507.
“DSU – Device Service Unit” on page 45:
Register Description: DID.DEVSEL, Table 11-8 Device Selection updated.
“SYSCTRL – System Controller” on page 143:
Removed references to XOSC32K and OSC32K 1kHz clock output option:
- XOSC32K: “32kHz External Crystal Oscillator (XOSC32K) Operation” on page 148
- OSC32K: “32kHz Internal Oscillator (OSC32K) Operation” on page 149
1kHz Output Enable (EN1K) bit set as reserved bit:
- Bit 4 in XOSC32K
- Bit 3 in OSC32K
“Electrical Characteristics” on page 1055:
“Brown-Out Detectors Characteristics” on page 1070: Added Figure 42-3 and Figure 42-4 and updated conditions in
Table 42-17 and Table 42-18.
Errata:
Updated errata for revision A: Added Errata Reference 10933, 12015, 12291, 12354, 12368, 12499, 13268, 13277,
13574.
Updated errata for revision B: Added Errata Reference 10933, 12015, 12291, 12368, 12499, 13268, 13277, 13574.
Updated errata for revision C: Added Errata Reference 12291, 13574, 13951.
Added errata for revision D.
“Electrical Characteristics at 125°C” on page 1171:
Electrical characteristics for 125°C added.
“Block Diagrams” on page 8
NVM Controller bus connection changed from Master to Slave.
“Clock System” on page 82
“Register Synchronization” on page 83 updated by splitting the section into “Common Synchronizer Register
Synchronization” on page 83 and “Distributed Synchronizer Register Synchronization” on page 86.
“Electrical Characteristics” on page 1055
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48.7 Rev. A – 07/2014
“Analog-to-Digital (ADC) Characteristics” on page 1072: Added note defining gain accuracy parameter in:
- ADC Differential Mode, Table 42-20
- ADC Single-Ended Mode, Table 42-21
Errata
Updated errata for revision A and B: Added Errata Reference 13140, 12860.
Added errata for revision C.
Initial revision
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Appendix A. Continuous Transmission Test Mode
A.1 Overview
The AT86RF233 offers a Continuous Transmission Test Mode to support final application / production tests as well as
certification tests. Using this test mode, the radio transceiver transmits continuously a previously transferred frame
(PRBS mode) or a continuous wave signal (CW mode).
In CW mode, two different signal frequencies per channel can be transmitted:
zf1[MHz] = Fc[MHz] = 2405[MHz] + 5[MHz] x (k – 11), for k = 11, 12, ..., 26[MHz] + 0.5MHz
zf2[MHz] = Fc[MHz] = 2405[MHz] + 5[MHz] x (k – 11), for k = 11, 12, ..., 26[MHz] - 0.5MHz
Where Fc is the channel center frequency, refer to “RF Channel Selection” on page 994.
Note: 1. In CW mode, it is not possible to transmit a RF signal directly on the channel center frequency.
PSDU data in the Frame Buffer must contain at least a valid PHR (see “Introduction – IEEE 802.15.4-2006 Frame
Format” on page 947). It is recommended to use a frame of maximum length (127 bytes) and arbitrary PSDU data for the
PRBS mode. The SHR and the PHR are not transmitted. The transmission starts with the PSDU data and is repeated
continuously.
A.2 Configuration
Before enabling Continuous Transmission Test Mode all register configurations should be done as follow:
zTX channel setting (optional)
zTX output power setting (optional)
zMode selection (PRBS / CW)
A register access to register 0x36 and 0x1C enables the Continuous Transmission Test Mode.
The transmission is started by enabling the PLL (TRX_CMD = PLL_ON) and writing the TX_START command to
register 0x02.
Even for CW signal transmission, it is required to write valid PSDU data to the Frame Buffer. For PRBS mode it is
recommended to write a frame of maximum length.
The detailed programming sequence is shown in Table 48-1. The column R/W informs about writing (W) or reading (R) a
register or the Frame Buffer.
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Table 48-1. Continuous Transmission Programming Sequence.
Step Action Register R/W Value Description
1RESET Reset AT86RF233
2Register
Access 0x0E W0x01 Set IRQ mask register, enable IRQ_0 (PLL_LOCK)
3Register
Access 0x04 W0x00 Disable TX_AUTO_CRC_ON
4Register
Access 0x02 W0x03 Set radio transceiver state TRX_OFF
5Register
Access 0x03 W0x01 Set clock at internal pad CLKM)
6Register
Access 0x08 W0x33 Set IEEE 802.15.4 CHANNEL, for example channel 19
7Register
Access 0x05 W0x00 Set TX output power, for example to PTX_MAX
8Register
Access 0x01 R0x08 Verify TRX_OFF state
9Register
Access 0x36 W0x0F Enable Continuous Transmission Test Mode – step # 1
10(1) Register
Access 0x0C W0x03 Enable raw data mode
11(1) Register
Access 0x0A W0x37 Enable raw data mode
12(2) Frame Buffer
Write Access W
Write packet header containing the following number of
bytes for with PSDU data (even for CW mode), refer to
Table 48-2
13 Register
Access 0x1C W0x54 Enable Continuous Transmission Test Mode – step # 2
14 Register
Access 0x1C W0x46 Enable Continuous Transmission Test Mode – step # 3
15 Register
Access 0x02 W0x09 Enable PLL_ON state
16 Interrupt event 0x0F R0x01 Wait for IRQ_0 (PLL_LOCK)
17 Register
Access 0x02 W0x02 Initiate Transmission,
enter BUSY_TX state
18 Measurement Perform measurement
19 Register
Access 0x1C W0x00 Disable Continuous Transmission Test Mode
20 RESET Reset AT86RF233
Notes: 1. Only required for CW mode, do not configure for PRBS mode.
2. Frame Buffer content varies for different modulation schemes.
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The content of the Frame Buffer has to be defined for Continuous Transmission PRBS mode or CW mode. To measure
the power spectral density (PSD) mask of the transmitter it is recommended to use a random sequence of maximum
length for the PSDU data.
To measure CW signals it is necessary to write either 0x00 or 0xFF to the Frame Buffer, for details refer to Table 48-2.
A.3 Register Description
A.3.1 TST_CTRL_DIGI
The TST_CTRL_DIG register enables the continuous transmission test mode.
Name: TST_CTRL_DIGI
Offset: 0x36
Reset: 0x00
Property: -
zBit 3:0 - TST_CTRL_DIG
The register bits TST_CTRL_DIG with value 0xF enables continuous transmission.
Table 48-2. Frame Buffer Content for various Continuous Transmission Modulation Schemes.
Step Action Frame Content Comment
12 Frame Buffer Access
Random Sequence Modulated RF signal
Number of bytes and 0x00 (each byte of
PSDU) Fc – 0.5MHz, CW signal
Number of bytes and 0xFF (each byte of
PSDU) Fc + 0.5MHz, CW signal
Note: 1. It is recommended to use a frame of maximum length (127 bytes).
Bit 7 6 5 4 3 2 1 0
0x36 TST_CTRL_DIG
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Table 48-3. TST_CTRL_DIG
Value Description
0x0 No mode is active
0xF Continuous Transmission enabled
All other values are reserved
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Appendix B. References
1. IEEE Standard 802.15.4™ 2003: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifica-
tions for Low-Rate Wireless Personal Area Networks (WPANs).
2. IEEE Standard 802.15.4™ 2006: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifica-
tions for Low-Rate Wireless Personal Area Networks (WPANs).
3. IEEE Standard 802.15.4™ 2011: Low-Rate Wireless Personal Area Networks (WPANs).
4. ANSI/ESD STM5.1 - 2007, Electrostatic Discharge Sensitivity Testing - Human Body Model (HBM); JESD22-
A114E - 2006; CEI/IEC 60749-26 - 2006; AEC-Q100-002-Ref-D.
5. ESD-STM5.3.1-1999: ESD Association Standard Test Method for electrostatic discharge sensitivity testing -
Charged Device Model (CDM).
6. NIST FIPS PUB 197: Advanced Encryption Standard (AES), Federal Information Processing Standards Publica-
tion 197, US Department of Commerce/NIST, November 26, 2001.
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Appendix C. Electrical Characteristics at 125°C
C.1 Disclaimer
All typical values are measured at T = 25°C unless otherwise specified. All minimum and maximum values are valid
across operating temperature and voltage unless otherwise specified.
C.2 Absolute Maximum Ratings
Stresses beyond those listed in Table C-1 may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Note: 1. Maximum source current is 14mA and maximum sink current is 19.5mA per cluster. A cluster is a group of GPIOs as
shown in . Also note that each VDD/GND pair is connected to 2 clusters so current consumption through the pair will
be a sum of the clusters source/sink currents.
C.3 General Operating Ratings
The device must operate within the ratings listed in Table C-2 in order for all other electrical characteristics and typical
characteristics of the device to be valid.
Table C-1. Absolute Maximum Ratings
Symbol Parameter Condition Min. Max. Units
VDD Power supply voltage 03.8 V
IDD Current into a VDD pin -28 mA
IGND Current out of a GND pin -39 mA
VPIN
Pin voltage with respect to GND
and VDD
GND-0.3V VDD+0.3V V
VANA
Voltage on RFP, RFN, AVDD and
DVDD -0.3 2.0 V
VESD ESD robustness
Human Body Model (HBM) [4] 4 kV
Charged Device Model (CDM)
[5]550 V
PRF Input RF level +10 dBm
TLEAD Lead temperature
T = 10s
(soldering profile compliant with
IPC/JEDEC J STD 020B)
260 C
Tstorgae Storage temperature -60 150 C
Caution! ESD sensitive device.
Precaution should be used when handling the device in order to prevent permanent damage.
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Notes: 1. With BOD33 disabled. If the BOD33 is enabled, check Table 42-17.
2. Even if an implementation uses the external 1.8V voltage supply VDD1.8 it is required to connect VDD.
3. AT86RF233 register 0x10 (VREG_CTRL) needs to be programmed to disable internal voltage regulators and sup-
ply blocks by an external 1.8V supply, refer to “Voltage Regulators (AVREG, DVREG)” on page 983.
4. Applicable for the SAM R21E19 due to the VDD minimum supply voltage of the Serial Flash.
C.4 Supply Characteristics
The following characteristics are applicable to the operating temperature range: TA = -40°C to 125°C, unless otherwise
specified and are valid for a junction temperature up to TJ = 100 C. Refer to “Power Supply and Start-Up Considerations”
on page 20.
Table 48-4. Supply Characteristics
Note: 1. 2.35V is only applicable for the SAM R21E19 due to the VDD minimum supply voltage of the Serial Flash.
Table C-2. General Operating Conditions
Symbol Parameter Condition Min. Typ. Max. Units
VDD Power supply voltage Voltage on VDDIN, VDDIO and
VDDANA(2)
1.8(1)
2.35(4) 3.3 3.6 V
VDD1.8
Power supply voltage
(on AVDD and DVDD) External supply voltage(3) 1.7 1.8 1.9 V
VDDANA Analog supply voltage 1.8(1) 3.3 3.6 V
TATemperature range -40 25 125 °C
TJJunction temperature - - 145 °C
Symbol Conditions
Voltage
Min. Max. Units
VDDIO
VDDIN
VDDANA
Full Voltage Range 1.8 / 2.35(1) 3.6 V
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C.5 Maximum Clock Frequencies
Table C-3. Maximum GCLK Generator Output Frequencies
Symbol Description Conditions Max. Units
fGCLKGEN0 / fGCLK_MAIN
fGCLKGEN1
fGCLKGEN2
fGCLKGEN3
fGCLKGEN4
fGCLKGEN5
fGCLKGEN6
fGCLKGEN7
fGCLKGEN8
GCLK Generator Output
Frequency
Undivided 96 MHz
Divided 32 MHz
Table C-4. Maximum Peripheral Clock Frequencies
Symbol Description Max. Units
fCPU CPU clock frequency 32 MHz
fAHB AHB clock frequency 32 MHz
fAPBA APBA clock frequency 32 MHz
fAPBB APBB clock frequency 32 MHz
fAPBC APBC clock frequency 32 MHz
fGCLK_DFLL48M_REF DFLL48M Reference clock frequency 33 KHz
fGCLK_DPLL FDPLL96M Reference clock frequency 2MHz
fGCLK_DPLL_32K FDPLL96M 32k Reference clock frequency 32 KHz
fGCLK_WDT WDT input clock frequency 48 MHz
fGCLK_RTC RTC input clock frequency 48 MHz
fGCLK_EIC EIC input clock frequency 48 MHz
fGCLK_USB USB input clock frequency 48 MHz
fGCLK_EVSYS_CHANNEL_0 EVSYS channel 0 input clock frequency 48 MHz
fGCLK_EVSYS_CHANNEL_1 EVSYS channel 1 input clock frequency 48 MHz
fGCLK_EVSYS_CHANNEL_2 EVSYS channel 2 input clock frequency 48 MHz
fGCLK_EVSYS_CHANNEL_3 EVSYS channel 3 input clock frequency 48 MHz
fGCLK_EVSYS_CHANNEL_4 EVSYS channel 4 input clock frequency 48 MHz
fGCLK_EVSYS_CHANNEL_5 EVSYS channel 5 input clock frequency 48 MHz
fGCLK_EVSYS_CHANNEL_6 EVSYS channel 6 input clock frequency 48 MHz
fGCLK_EVSYS_CHANNEL_7 EVSYS channel 7 input clock frequency 48 MHz
fGCLK_EVSYS_CHANNEL_8 EVSYS channel 8 input clock frequency 48 MHz
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C.6 Power Consumption
The values in Table C-5 are measured values of power consumption under the following conditions, except where noted:
zOperating conditions
zVVDDIN = 3.3V
zWake up time from sleep mode is measured from the edge of the wakeup signal to the execution of the first
instruction fetched in flash.
zOscillators
zXOSC32K (32kHz crystal oscillator) stopped
zXOSC (crystal oscillator) running with external 32MHz clock on XIN
zDFLL48M stopped
zClocks
zXOSC used as main clock source, except otherwise specified
zCPU, AHB clocks undivided
zAPBA clock divided by 4
zAPBB and APBC bridges off
zThe following AHB module clocks are running: NVMCTRL, APBA bridge
zAll other AHB clocks stopped
zThe following peripheral clocks running: PM, SYSCTRL, RTC
zAll other peripheral clocks stopped
fGCLK_EVSYS_CHANNEL_9 EVSYS channel 9 input clock frequency 48 MHz
fGCLK_EVSYS_CHANNEL_10 EVSYS channel 10 input clock frequency 48 MHz
fGCLK_EVSYS_CHANNEL_11 EVSYS channel 11 input clock frequency 48 MHz
fGCLK_SERCOMx_SLOW
Common SERCOM slow input clock
frequency 48 MHz
fGCLK_SERCOM0_CORE SERCOM0 input clock frequency 48 MHz
fGCLK_SERCOM1_CORE SERCOM1 input clock frequency 48 MHz
fGCLK_SERCOM2_CORE SERCOM2 input clock frequency 48 MHz
fGCLK_SERCOM3_CORE SERCOM3 input clock frequency 48 MHz
fGCLK_SERCOM4_CORE SERCOM4 input clock frequency 48 MHz
fGCLK_SERCOM5_CORE SERCOM5 input clock frequency 48 MHz
fGCLK_TCC0, GCLK_TCC1 TCC0,TCC1 input clock frequency 80 MHz
fGCLK_TCC2, GCLK_TC3 TCC2,TC3 input clock frequency 80 MHz
fGCLK_TC4, GCLK_TC5 TC4,TC5 input clock frequency 48 MHz
fGCLK_ADC ADC input clock frequency 48 MHz
fGCLK_AC_DIG AC digital input clock frequency 48 MHz
fGCLK_AC_ANA AC analog input clock frequency 64 KHz
fGCLK_PTC PTC input clock frequency 48 MHz
Table C-4. Maximum Peripheral Clock Frequencies (Continued)
Symbol Description Max. Units
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zI/Os are inactive with internal pull-up
zCPU is running on flash with 1 wait states
zCache enabled
zBOD33 disabled
zAT86RF233 has to be set in Deep Sleep
zStacked serial Flash not included
Note: 1. Measurements were done with SYSCTRL->VREG.bit.RUNSTDBY = 1
Table C-5. Current Consumption
Mode Conditions TAMin. Typ. Max. Units
ACTIVE
CPU running a While(1) algorithm
125 C
-3.75 4.12
mA
CPU running a While(1) algorithm VDDIN=1.8V,
CPU is running on Flash with 3 wait states -3.77 4.13
CPU running a While(1) algorithm, CPU is
running on Flash with 3 wait states with
GCLKIN as reference
-62*freq
+422
62*freq
+484
µA
(with freq
in MHz)
CPU running a Fibonacci algorithm -4.85 5.29
mA
CPU running a Fibonacci algorithm
VDDIN=1.8V, CPU is running on flash with 3
wait states
-4.87 5.29
CPU running a Fibonacci algorithm, CPU is
running on Flash with 3 wait states with
GCLKIN as reference
-88*freq
+424
88*freq
+486
µA
(with freq
in MHz)
CPU running a CoreMark algorithm -6.70 7.30
mA
CPU running a CoreMark algorithm
VDDIN=1.8V, CPU is running on flash with 3
wait states
-5.98 6.41
CPU running a CoreMark algorithm, CPU is
running on Flash with 3 wait states with
GCLKIN as reference
-108*freq
+426
108*freq
+492
µA
(with freq
in MHz)
IDLE0 -2.40 2.69
mAIDLE1 -1.79 2.05
IDLE2 -1.50 1.76
STANDBY
XOSC32K running
RTC running at 1kHz(1) -350.0 852
µA
XOSC32K and RTC stopped() -348.0 850
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Figure C-1. Measurement Schematic
Table C-6. Wake-up Time
Mode Conditions TAMin. Typ. Max. Units
IDLE0 OSC8M used as main clock source, Cache
disabled
125 C
3.9 44.1
µs
IDLE1
I
OSC8M used as main clock source, Cache
disabled 13.5 14.9 16.4
IDLE2
I
OSC8M used as main clock source, Cache
disabled 14.4 15.8 17.2
STANDBY
I
OSC8M used as main clock source, Cache
disabled 19.2 20.6 22.1
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C.7 Analog Characteristics
C.7.1 Power-On Reset (POR) Characteristics
Table C-7. POR Characteristics
Figure C-2. POR Operating Principle
Symbol Parameter Conditions Min. Typ. Max. Units
VPOT+
Voltage threshold on VDD
rising
I
VDD falls at 1V/ms or slower
1.27 1.45 1.58 V
VPOT- Voltage threshold on VDD falling 0.53 0.99 1.32 V
Reset VDD
V
POT+
V
Time
POT-
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C.7.2 Brown-Out Detectors Characteristics
BOD33
Note: 1. These values are based on simulation. These values are not covered by test limits in production or
characterization.
C.7.3 Analog-to-Digital (ADC) Characteristics
Table C-8. BOD33 Characteristics
Symbol Parameter Conditions Temp. Min. Typ. Max. Units
I
Step size, between
adjacent values in
BOD33.LEVEL
-34 -mV
VHYST VBOD+ - VBOD- Hysteresis ON 35 -170 mV
tDET Detection time
Time with
VDDANA < VTH
necessary to
generate a
reset signal
-0.9(1) - s
IIdleBOD33
Current
consumption om
Active/Idle mode
Continuous mode
25 C -25 48
µA
-40- to 125 C - - 50
Sampling mode
25 C -0.034 0.21
-40- to 125 C - - 2.92
ISbyBOD33
Current
consumption in
Standby mode
Sampling mode
25 C 0.132 0.38
µ A
-40- to 125 C 1.62
tSTARTUP Startup time -40- to 125 C -1.2(1) - s
Table C-9. Operating Conditions
Symbol Parameter Conditions Min. Typ. Max. Units
RES Resolution
I
8 - 12 bits
fCLK_ADC ADC Clock frequency
I
30 -2100 kHz
Sample rate(1)
Single shot (with
VDDANA > 3.0V)(4) 5 - 300 ksps
Free running 5 - 350 ksps
Sampling time(1) 0.5 - - cycles
Conversion time(1) 1x Gain - 6 - cycles
VREF Voltage reference range 1.0 - VDDANA-0.6 V
VREFINT1V Internal 1V reference (2) -1.0 - V
VREFINTVCC0 Internal ratiometric reference 0(2) - VDDANA/1.48 - V
VREFINTVCC0
Voltage Error
Internal ratiometric reference 0(2)
error
2.0V <
VDDANA<3.63V -1.0 -+1.0 %
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Notes: 1. These values are based on characterization. These values are not covered by test limits in production.
2. These values are based on simulation. These values are not covered by test limits in production or characterization.
3. In this condition and for a sample rate of 350ksps, a conversion takes 6 clock cycles of the ADC clock (conditions: 1X gain, 12-bit resolution, differ-
ential mode, free-running).
4. All single-shot measurements are performed with VDDANA > 3.0V (cf. ADC errata)
Notes: 1. Maximum numbers are based on characterization and not tested in production, and valid for 5% to 95% of the input
voltage range.
2. Dynamic parameter numbers are based on characterization and not tested in production.
VREFINTVCC1 Internal ratiometric reference 1(2) VDDANA>2.0V - VDDANA/2 - V
VREFINTVCC1
Voltage Error
Internal ratiometric reference 1(2)
error
2.0V <
VDDANA<3.63V -1.0 -+1.0 %
Conversion range(1) Differential mode -VREF/GAIN -+VREF/GAIN V
Single-ended mode 0.0 -+VREF/GAIN V
CSAMPLE Sampling capacitance(2) -3.5 -pF
RSAMPLE Input channel source resistance(2) - - 3.5 kΩ
IDD DC supply current(1) fCLK_ADC = 2.1MHz
I
(3) -1.25 1.85 mA
Table C-9. Operating Conditions (Continued)
Symbol Parameter Conditions Min. Typ. Max. Units
Table C-10. Differential Mode
Symbol Parameter Conditions Min. Typ. Max. Units
ENOB Effective Number Of Bits With gain compensation -10.5 10.9 bits
TUE Total Unadjusted Error
I
1x Gain
n
1.5 4.3 17.0 LSB
INL
I
Integral Non Linearity 1x Gain
n
1.0 1.3 6.5 LSB
DNL Differential Non Linearity 1x Gain
n
+/-0.3 +/-0.5 +/-0.95 LSB
I
I
I
Gain Error
Ext. Ref 1x -15.0 2.5 +20.0 mV
VREF=VDDANA/1.48 -20 -1.5 +20.0 mV
Bandgap -15.0 -5.0 +15.0 mV
Gain Accuracy(5) Ext. Ref. 0.5x +/-0.1 +/-0.2 +/-0.45 %
Ext. Ref. 2x to 16x +/-0.1 +/-0.2 +/-2.0 %
Offset Error
Ext. Ref. 1x -10.0 -1.5 +10.0 mV
VREF=VDDANA/1.48 -10.0 0.5 +15.0 mV
Bandgap -10.0 3.0 +15.0 mV
SFDR Spurious Free Dynamic Range 1x Gain
FCLK_ADC = 2.1MHz
FIN = 40kHz
AIN = 95%FSR
64.2 70.0 78.9 dB
SINAD Signal-to-Noise and Distortion 61.4 65.0 66 dB
SNR Signal-to-Noise Ratio 64.3 65.5 66.0 dB
THD Total Harmonic Distortion -74.8 -64.0 -65.0 dB
Noise RMS T=25 C 0.6 1.0 1.6 mV
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3. Respect the input common mode voltage through the following equations (where VCM_IN is the Input channel com-
mon mode voltage):
c. If |VIN| > VREF/4
zVCM_IN < 0.95*VDDANA + VREF/4 – 0.75V
zVCM_IN > VREF/4 -0.05*VDDANA -0.1V
d. If |VIN| < VREF/4
zVCM_IN < 1.2*VDDANA - 0.75V
zVCM_IN > 0.2*VDDANA - 0.1V
4. The ADC channels on pins PA08, PA09 are powered from the VDDIO power supply. The ADC performance of these
pins will not be the same as all the other ADC channels on pins powered from the VDDANA power supply.
5. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x 100) /
(2*Vref/GAIN)
Notes: 1. Maximum numbers are based on characterization and not tested in production, and for 5% to 95% of the input voltage
range.
2. Respect the input common mode voltage through the following equations (where VCM_IN is the Input channel com-
mon mode voltage) for all VIN:
zVCM_IN < 0.7*VDDANA + VREF/4 – 0.75V
zVCM_IN > VREF/4 – 0.3*VDDANA - 0.1V
3. The ADC channels on pins PA08, PA09 are powered from the VDDIO power supply. The ADC performance of these
pins will not be the same as all the other ADC channels on pins powered from the VDDANA power supply.
4. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x 100) /
(Vref/GAIN)
Inputs and Sample and Hold Acquisition Times
The analog voltage source must be able to charge the sample and hold (S/H) capacitor in the ADC in order to achieve
maximum accuracy. Seen externally the ADC input consists of a resistor ( ) and a capacitor ( ). In
addition, the source resistance ( ) must be taken into account when calculating the required sample and hold
time. Figure C-3 shows the ADC input channel equivalent circuit.
Table C-11. Single-Ended Mode
Symbol Parameter Conditions Min. Typ. Max. Units
ENOB Effective Number of Bits With gain compensation -9.5 9.8 Bits
TUE Total Unadjusted Error 1x gain -10.5 40.0 LSB
INL Integral Non-Linearity 1x gain 1.0 1.6 7.5 LSB
DNL Differential Non-Linearity 1x gain +/-0.5 +/-0.6 +/-0.95 LSB
Gain Error Ext. Ref. 1x -10.0 0.7 +10.0 mV
Gain Accuracy(4) Ext. Ref. 0.5x +/-0.1 +/-0.34 +/-0.4 %
Ext. Ref. 2x to 16X +/-0.01 +/-0.1 +/-0.15 %
Offset Error Ext. Ref. 1x -5.0 1.5 +10.0 mV
SFDR Spurious Free Dynamic Range 1x Gain
FCLK_ADC = 2.1MHz
FIN = 40kHz
AIN = 95%FSR
63.1 65.0 66.5 dB
SINAD Signal-to-Noise and Distortion 50.7 59.5 61.0 dB
SNR Signal-to-Noise Ratio 49.9 60.0 64.0 dB
THD Total Harmonic Distortion -65.4 -63.0 -62.1 dB
Noise RMS T = 25 C -1.0 -mV
RSAMPLE
CSAMPLE
RSOURCE
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Figure C-3. ADC Input
To achieve n bits of accuracy, the capacitor must be charged at least to a voltage of
The minimum sampling time for a given can be found using this formula:
for a 12 bits accuracy:
where
RSOURCE RSAMPLE
Analog Input
AINx CSAMPLE
VIN
VDDANA/2
CSAMPLE
VCSAMPLE V≥IN 12
n1+()–
–()×
tSAMPLEHOLD
RSOURCE
tSAMPLEHOLD RSAMPLE R+SOURCE
()CSAMPLE
()×n1+() 2()ln××≥
tSAMPLEHOLD RSAMPLE R+SOURCE
()CSAMPLE
()×9.02×≥
tSAMPLEHOLD
1
2fADC
×
---------------------
=
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C.7.4 Analog Comparator Characteristics
Notes: 1. According to the standard equation V(X)=VLSB*(X+1); VLSB=VDDANA/64
2. Data computed with the Best Fit method
3. Data computed using histogram
C.7.5 Temperature Sensor Characteristics
Note: 1. These values are based on characterization. These values are not covered by test limits in production.
Table C-12. Electrical and Timing
Symbol Parameter Conditions Min. Typ. Max. Units
I
Positive input voltage
range
I
0 - VDDANA
V
I
Negative input voltage
range
I
0 - VDDANA
I
Offset
Hysteresis = 0, Fast mode -15 0.0 +15 mV
Hysteresis = 0, Low power mode -25 0.0 +25 mV
Hysteresis
Hysteresis = 1, Fast mode 20 50 83 mV
Hysteresis = 1, Low power mode 15 40 75 mV
Propagation delay
Changes for VACM=VDDANA/2
100mV overdrive, Fast mode -60 116 ns
Changes for VACM=VDDANA/2
100mV overdrive, Low power
mode
-225 370 ns
tSTARTUP Startup time
Enable to ready delay
Fast mode - 1 2 s
Enable to ready delay
Low power mode -12 19 s
VSCALE
INL(3) -0.75 1.58 LSB
DNL(3) -0.25 0.95 LSB
Offset Error (1)(2) -0.200 0.260 +1.035 LSB
Gain Error (1)(2) 0.55 1.2 2.0 LSB
Table C-13. Temperature Sensor Characteristics(1)
Symbol Parameter Conditions Min. Typ. Max. Units
I
Temperature sensor output
voltage T= 25 C, VDDANA = 3.3V -0.667 - V
I
Temperature sensor slope 2.2 2.4 2.7 mV/ C
I
Variation over VDDANA voltage VDDANA=1.8V to 3.6V -9 114 mV/V
I
Temperature sensor
accuracy
Using the method described in
section 36.9.8.2 -13.0 -13.0 C
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C.8 NVM Characteristics
Note that on this flash technology, a max number of 4 consecutive write is allowed per row. Once this number is reached,
a row erase is mandatory.
Table C-15. Flash Endurance and Data Retention
Note: 1. An endurance cycle is a write and an erase operation.
Table C-16. EEPROM Emulation(1) Endurance and Data Retention
Notes: 1. The EEPROM emulation is a software emulation described in the App note AT03265.
2. An endurance cycle is a write and an erase operation.
Table C-14. Maximum Operation Frequency
VDD range NVM Wait States Maximum Operating Frequency Units
1.8V to 2.7V
014
MHz
128
240
2.7V to 3.6V
024
140
Symbol Parameter Conditions Min. Typ. Max. Units
RetNVM25k Retention after up to 25k Average ambient 55°C 10 50 -Years
RetNVM2.5k Retention after up to 2.5k Average ambient 55°C 20 100 -Years
RetNVM100 Retention after up to 100 Average ambient 55°C 25 >100 -Years
CycNVM Cycling Endurance(1) -40°C < Ta < 125°C 25k 150k -Cycles
Symbol Parameter Conditions Min. Typ. Max. Units
RetEEPROM100k Retention after up to 100k Average ambient 55 C 10 50 -Yea rs
RetEEPROM10k Retention after up to 10k Average ambient 55 C 20 100 -Years
CycEEPROM Cycling Endurance(2) -40 C < Ta < 125 C 100k 600k -Cycles
Table C-17. NVM Characteristics
Symbol Parameter Conditions Min. Typ. Max. Units
tFPP Page programming time - - - 2.5 ms
tFRE Row erase time
I
- - - 6 ms
tFCE
DSU chip erase time
(CHIP_ERASE) - - - 240 ms
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C.9 Oscillators Characteristics
C.9.1 Crystal Oscillator (XOSC) Characteristics
Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN.
Table C-18. Digital Clock Characteristics
Crystal Oscillator Characteristics
The following table describes the characteristics for the oscillator when a crystal is connected between XIN and XOUT as
shown in Figure C-4. The user must choose a crystal oscillator where the crystal load capacitance CL is within the range
given in the table. The exact value of CL can be found in the crystal datasheet. The capacitance of the external capacitors
(CLEXT) can then be computed as follows:
where CSTRAY is the capacitance of the pins and PCB, CSHUNT is the shunt capacitance of the crystal.
Symbol Parameter Conditions Min. Typ. Max. Units
fCPXIN XIN clock frequency
I
- - 32 MHz
Table C-19. Crystal Oscillator Characteristics
Symbol Parameter Conditions Min. Typ. Max. Units
fOUT Crystal oscillator frequency
I
0.4 -32 MHz
ESR
Crystal Equivalent Series
Resistance
Safety Factor = 3
The AGC doesn t have any
noticeable impact on these
measurements.
f = 0.455MHz, CL = 100pF
XOSC.GAIN = 0 - - 5.6K
Ω
f = 2MHz, CL = 20pF
XOSC.GAIN = 0 - - 416
f = 4MHz, CL = 20pF
XOSC.GAIN = 1 - - 243
f = 8MHz, CL = 20pF
XOSC.GAIN = 2 - - 138
f = 16MHz, CL = 20pF
XOSC.GAIN = 3 - - 66
f = 32MHz, CL = 18pF
XOSC.GAIN = 4 - - 56
CXIN Parasitic capacitor load
I
-5.9 -pF
CXOUT Parasitic capacitor load -3.2 -pF
CLEXT 2C
LCSTRAY CSHUNT
––()=
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Figure C-4. Oscillator Connection
IXOSC Current Consumption
f = 2MHz, CL = 20pF, AGC off 27 65 90
µA
f = 2MHz, CL = 20pF, AGC on 14 52 79
f = 4MHz, CL = 20pF, AGC off 61 117 161
f = 4MHz, CL = 20pF, AGC on 23 74 110
f = 8MHz, CL = 20pF, AGC off 131 226 319
f = 8MHz, CL = 20pF, AGC on 56 128 193
f = 16MHz, CL = 20pF, AGC off 305 502 742
f = 16MHz, CL = 20pF, AGC on 116 307 627
f = 32MHz, CL = 18pF, AGC off 1031 1622 2344
f = 32MHz, CL = 18pF, AGC on 278 615 1422
tSTARTUP Startup time
f = 2MHz, CL = 20pF,
XOSC.GAIN = 0, ESR = 600Ω-14K 48K
cycles
f = 4MHz, CL = 20pF,
XOSC.GAIN = 1, ESR = 100Ω-6800 19.5K
f = 8MHz, CL = 20pF,
XOSC.GAIN = 2, ESR = 35Ω-5550 13K
f = 16MHz, CL = 20pF,
XOSC.GAIN = 3, ESR = 25Ω-6750 14.5K
f = 32MHz, CL = 18pF,
XOSC.GAIN = 4, ESR = 40Ω-5.3K 9.6K
Table C-19. Crystal Oscillator Characteristics (Continued)
Symbol Parameter Conditions Min. Typ. Max. Units
C
SHUNT
L
M
R
M
C
M
C
STRAY
C
LEXT
C
LEXT
Xin
Crystal
Xout
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C.9.2 External 32kHz Crystal Oscillator (XOSC32K) Characteristics
Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN32 pin.
Table C-20. Digital Clock Characteristics
Crystal Oscillator Characteristics
Figure C-4 and the equation in “Crystal Oscillator (XOSC) Characteristics” on page 1184 also applies to the 32kHz
oscillator connection. The user must choose a crystal oscillator where the crystal load capacitance CL is within the range
given in the table. The exact value of CL can be found in the crystal datasheet.
Symbol Parameter Conditions Min. Typ. Max. Units
fCPXIN32 XIN32 clock frequency
I
-32.768 -kHz
I
XIN32 clock duty cycle
I
-50 - %
Table C-21. 32kHz Crystal Oscillator Characteristics
Symbol Parameter Conditions Min. Typ. Max. Units
fOUT Crystal oscillator frequency
I
-32768 -Hz
tSTARTUP Startup time ESRXTAL = 39.9kΩ, CL = 12.5pF -28K 31K cycles
CLCrystal load capacitance
I
- - 12.5
pF
CSHUNT Crystal shunt capacitance
I
-0.1 -
CXIN32 Parasitic capacitor load
TQFP64/48/32 packages
-3.1 -
CXOUT32 Parasitic capacitor load -3.3 -
IXOSC32K Current consumption -1.22 2.44 µA
ESR
Crystal equivalent series
resistance f=32.768kHz
Safety Factor = 3
CL=12.5pF - - 141 kΩ
1187
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C.9.3 Digital Frequency Locked Loop (DFLL48M) Characteristics
Table C-22. DFLL48M Characteristics - Open Loop Mode(1) (Device Variant A)
Note: 1. DFLL48M in Open loop after calibration at room temperature.
Table C-23. DFLL48M Characteristics - Closed Loop Mode (Device Variant A)
C.9.4 32.768kHz Internal oscillator (OSC32K) Characteristics
Table C-24. 32kHz RC Oscillator Characteristics (Device Variant A)
Symbol Parameter Conditions Min. Typ. Max. Units
fOUT Output frequency
I
DFLLVAL.COARSE =
DFLL48M COARSE CAL
DFLLVAL.FINE = 512
47 48 49 MHz
IDFLL Power consumption on VDDIN
I
DFLLVAL.COARSE =
DFLL48M COARSE CAL
DFLLVAL.FINE = 512
-403 457 A
tSTARTUP Startup time
DFLLVAL.COARSE =
DFLL48M COARSE CAL
DFLLVAL.FINE = 512
fOUT within 90% of final value
7 8 9 s
Symbol Parameter Conditions Min. Typ. Max. Units
fOUT Average Output frequency fREF = 32.768kHz 47.76 48 48.24 MHz
fREF Reference frequency
I
0.732 32.768 33 kHz
Jitter Period Jitter fREF = 32.768kHz - - 1.04 ns
IDFLL Power consumption on VDDIN fREF = 32.768kHz -425 482 A
tLOCK Lock time
fREF = 32.768kHz
DFLLVAL.COARSE =
DFLL48M COARSE CAL
DFLLVAL.FINE = 512
DFLLCTRL.BPLCKC = 1
DFLLCTRL.QLDIS = 0
DFLLCTRL.CCDIS = 1
DFLLMUL.FSTEP = 10
100 200 500 s
Symbol Parameter Conditions Min. Typ. Max. Units
fOUT Output frequency
Calibrated against a 32.768kHz
reference at 25 C, over [-40, +125]C,
over [1.8, 3.6]V
28.508 32.768 35.389
kHzCalibrated against a 32.768kHz
reference at 25 C, at VDD=3.3V 32.276 32.768 33.260
Calibrated against a 32.768kHz
reference at 25 C, over [1.8, 3.6]V 31.457 32.768 34.079
1188
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C.9.5 Ultra Low Power Internal 32kHz RC Oscillator (OSCULP32K) Characteristics
Notes: 1. These values are based on simulation. These values are not covered by test limits in production or
characterization.
2. This oscillator is always on.
C.9.6 8MHz RC Oscillator (OSC8M) Characteristics
Figure C-5. Internal 8MHz RC Oscillator Characteristics (Device Variant A)
IOSC32K Current consumption
I
-0.79 1.80 A
tSTARTUP Startup time
I
- 1 2 cycle
Duty Duty Cycle
I
-50 - %
Symbol Parameter Conditions Min. Typ. Max. Units
Table C-25. Ultra Low Power Internal 32kHz RC Oscillator Characteristics
Symbol Parameter Conditions Min. Typ. Max. Units
fOUT Output frequency
Calibrated against a 32.768kHz
reference at 25 C, over [-40,
+125]C, over [1.8, 3.6]V
25.559 32.768 40.305
kHzCalibrated against a 32.768kHz
reference at 25 C, at VDD=3.3V 31.293 32.768 34.570
Calibrated against a 32.768kHz
reference at 25 C, over [1.8, 3.6]V 31.293 32.768 34.570
IOSCULP32K
(1)(2) - - 180 nA
tSTARTUP Startup time
I
-10 -cycles
Duty Duty Cycle
I
-50 - %
Symbol Parameter Conditions Min. Typ. Max. Units
fOUT Output frequency
I
Calibrated against a 8MHz reference
at 25 C, over [-40, +125]C, over [1.8,
3.6]V
7.54 88.19
MHzCalibrated against a 8MHz reference
at 25 C, at VDD=3.3V 7.94 88.06
Calibrated against a 8MHz reference
at 25 C, over [1.8, 3.6]V 7.92 88.08
IOSC8M Current consumption
IIDLE
IDLE2 on OSC32K versus IDLE2 on
calibrated OSC8M enabled at 8MHz
(FRANGE=1, PRESC=0)
-64 100 A
tSTARTUP Startup time
I
-2.1 3 s
Duty Duty cycle
I
-50 - %
1189
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C.9.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics
Table C-26. FDPLL96M Characteristics(1) (Device Variant A)
Note: 1. All values have been characterized with FILTSEL[1/0] as default value.
C.9.8 USB Characteristics
The USB shares the same characteristics as in the -40 C to 85 C.
Symbol Parameter Conditions Min. Typ. Max. Units
fIN Input frequency 32 -2000 KHz
fOUT Output frequency 48 -96 MHz
IFDPLL96M Current consumption
fIN= 32 kHz, fOUT= 48 MHz 500 700
A
fIN= 32 kHz, fOUT= 96 MHz 900 1200
Jp Period jitter
fIN= 32 kHz, fOUT= 48 MHz -1.5 2.0
%
fIN= 32 kHz, fOUT= 96 MHz 3.0 10.0
fIN= 2 MHz, fOUT= 48 MHz 1.3 2.0
fIN= 2 MHz, fOUT= 96 MHz 3.0 7.0
tLOCK Lock Time
After startup, time to get lock
signal.
fIN= 32 kHz, fOUT= 96 MHz
1.3 2ms
fIN= 2 MHz, fOUT= 96 MHz 25 50 s
Duty Duty cycle 40 50 60 %
1190
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C.10 Timing Characteristics
C.10.1 SERCOM in SPI Mode Timing
Data are not available in this current datasheet revision
C.10.2 SERCOM in I2C Mode Timing
Data are not available in this current datasheet revision
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Table of Contents
Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1. Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 SAM R21E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 SAM R21G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.1 MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 SAM R21 Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4. Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1 SAM R21G - QFN48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2 SAM R21E - QFN32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5. I/O Multiplexing and Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1 Multiplexed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2 Internal Multiplexed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3 Other Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4 Analog and RF Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.5 Digital I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6. Power Supply and Start-Up Considerations . . . . . . . . . . . . . . . . . . . 20
6.1 Power Domain Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.2 Power Supply Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.3 Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.4 Power-On Reset and Brown-Out Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7. Product Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8. Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.1 Embedded Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.2 Physical Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.3 NVM Calibration and Auxiliary Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9. Processor And Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.1 Cortex M0+ Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.2 Nested Vector Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9.3 Micro Trace Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.4 High-Speed Bus System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.5 AHB-APB Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.6 PAC – Peripheral Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10. Peripherals Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . 43
11. DSU – Device Service Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
11.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
11.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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11.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
11.5 Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
11.6 Debug Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
11.7 Chip-Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
11.8 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
11.9 Intellectual Property Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
11.10 Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11.11 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.12 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
11.13 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
12. Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
12.1 Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
12.2 Synchronous and Asynchronous Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
12.3 Register Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
12.4 Enabling a Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
12.5 On-demand, Clock Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
12.6 Power Consumption vs Speed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
12.7 Clocks after Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
13. GCLK – Generic Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
13.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
13.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
13.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
13.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
13.5 Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
13.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
13.7 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
13.8 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
14. PM – Power Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
14.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
14.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
14.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
14.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
14.5 Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
14.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
14.7 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
14.8 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
15. SYSCTRL – System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
15.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
15.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
15.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
15.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
15.5 Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
15.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
15.7 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
15.8 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
16. WDT – Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
16.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
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16.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
16.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
16.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
16.5 Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
16.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
16.7 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
16.8 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
17. RTC – Real-Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
17.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
17.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
17.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
17.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
17.5 Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
17.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
17.7 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
17.8 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
18. DMAC – Direct Memory Access Controller . . . . . . . . . . . . . . . . . . .267
18.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
18.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
18.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
18.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
18.5 Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
18.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
18.7 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
18.8 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
19. EIC – External Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . 331
19.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
19.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
19.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
19.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
19.5 Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
19.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
19.7 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
19.8 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
20. NVMCTRL – Non-Volatile Memory Controller . . . . . . . . . . . . . . . . 350
20.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
20.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
20.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
20.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
20.5 Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
20.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
20.7 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
20.8 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
21. PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
21.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
21.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
21.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
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21.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
21.5 Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
21.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
21.7 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
21.8 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
22. EVSYS – Event System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
22.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
22.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
22.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
22.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
22.5 Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
22.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
22.7 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
22.8 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
23. SERCOM – Serial Communication Interface . . . . . . . . . . . . . . . . . 426
23.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
23.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
23.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
23.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
23.5 Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
23.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
24. SERCOM USART – SERCOM Universal Synchronous and Asynchronous Receiver and
Transmitter 434
24.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
24.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
24.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
24.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
24.5 Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
24.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
24.7 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
24.8 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
25. SERCOM SPI – SERCOM Serial Peripheral Interface . . . . . . . . . . 472
25.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
25.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
25.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
25.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
25.5 Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
25.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
25.7 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
25.8 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
26. SERCOM I2C – SERCOM Inter-Integrated Circuit . . . . . . . . . . . . . 505
26.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
26.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
26.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
26.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
26.5 Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
26.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
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26.7 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
26.8 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
27. TC – Timer/Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
27.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
27.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
27.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
27.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
27.5 Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
27.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
27.7 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
27.8 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
28. TCC – Timer/Counter for Control Applications . . . . . . . . . . . . . . . . 609
28.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
28.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
28.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
28.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
28.5 Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
28.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
28.7 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
28.8 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
29. USB – Universal Serial Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
29.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
29.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
29.3 USB Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
29.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
29.5 Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
29.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706
29.7 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
29.8 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730
30. ADC – Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . 802
30.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
30.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
30.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
30.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
30.5 Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
30.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805
30.7 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815
30.8 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
31. AC – Analog Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842
31.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842
31.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842
31.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
31.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
31.5 Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
31.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845
31.7 Additional Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
31.8 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854
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31.9 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855
32. PTC - Peripheral Touch Controller . . . . . . . . . . . . . . . . . . . . . . . . . 871
32.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871
32.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871
32.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872
32.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873
32.5 Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873
32.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875
33. RFCTRL – AT86RF233 Front-End Control Signal Interface . . . . . . 876
33.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876
33.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876
33.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876
33.4 Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876
33.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876
33.6 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877
33.7 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878
34. Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
34.1 Basic Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
34.2 Extended Feature Set Application Schematic . . . . . . . . . . . . . . . . . . . . . . . 881
35. AT86RF233 Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . 883
35.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883
35.2 SPI Timing Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884
35.3 SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885
35.4 Radio Transceiver Status Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
35.5 Radio Transceiver Identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
35.6 Sleep/Wake-up and Transmit Signal (SLP_TR). . . . . . . . . . . . . . . . . . . . . . 894
35.7 Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896
36. AT86RF233 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902
36.1 Basic Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902
36.2 Extended Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915
37. AT86RF233 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . 947
37.1 Introduction – IEEE 802.15.4-2006 Frame Format . . . . . . . . . . . . . . . . . . . 947
37.2 Frame Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952
37.3 Frame Check Sequence (FCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961
37.4 Received Signal Strength Indicator (RSSI) . . . . . . . . . . . . . . . . . . . . . . . . . 964
37.5 Energy Detection (ED) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965
37.6 Clear Channel Assessment (CCA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968
37.7 Link Quality Indication (LQI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972
38. AT86RF233 Module Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
38.1 Receiver (RX). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
38.2 Transmitter (TX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979
38.3 Frame Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981
38.4 Voltage Regulators (AVREG, DVREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983
38.5 Battery Monitor (BATMON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987
38.6 Crystal Oscillator (XOSCRF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 989
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38.7 Frequency Synthesizer (PLL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993
38.8 Automatic Filter Tuning (FTN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
39. AT86RF233 Radio Transceiver Usage . . . . . . . . . . . . . . . . . . . . . 1003
39.1 Frame Receive Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003
39.2 Frame Transmit Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003
40. AT86RF233 Extended Feature Set . . . . . . . . . . . . . . . . . . . . . . . . 1005
40.1 Security Module (AES). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005
40.2 Random Number Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013
40.3 High Data Rate Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013
40.4 Antenna Diversity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1020
40.5 RX/TX Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025
40.6 RX and TX Frame Time Stamping (TX_ARET) . . . . . . . . . . . . . . . . . . . . . 1027
40.7 Frame Buffer Empty Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030
40.8 Dynamic Frame Buffer Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032
40.9 Alternate Start-Of-Frame Delimiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033
40.10 Reduced Power Consumption Mode (RPC) . . . . . . . . . . . . . . . . . . . . . . . 1034
40.11 Time-Of-Flight Module (TOM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039
40.12 Phase Difference Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050
41. AT86RF233 Register Reference . . . . . . . . . . . . . . . . . . . . . . . . . . 1052
42. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055
42.1 Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055
42.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055
42.3 General Operating Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056
42.4 Supply Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057
42.5 Maximum Clock Frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057
42.6 Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060
42.7 Peripheral Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063
42.8 I/O Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067
42.9 Analog Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069
42.10 NVM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082
42.11 Oscillators Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083
42.12 PTC Typical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1090
42.13 USB Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094
42.14 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095
42.15 AT86RF233 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1101
43. Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1107
43.1 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1107
43.2 Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1108
44. Soldering Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1111
45. Schematic Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1112
45.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1112
45.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1112
45.3 External Analog Reference Connections . . . . . . . . . . . . . . . . . . . . . . . . . . 1113
45.4 External Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1115
45.5 Unused or Unconnected Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1115
45.6 Clocks and Crystal Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1116
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45.7 Programming and Debug Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1119
45.8 USB Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1123
46. About This Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125
46.1 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125
46.2 Acronyms and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1126
47. Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1131
47.1 Revision A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1131
47.2 Revision B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1139
47.3 Revision C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1148
47.4 Revision D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1155
48. Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1163
48.1 Rev. G – 05/2016. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1163
48.2 Rev. F – 11/2015 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1163
48.3 Rev. E – 02/2015 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164
48.4 Rev. D – 02/2015 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164
48.5 Rev. C – 01/2015 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1165
48.6 Rev. B – 09/2014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1165
48.7 Rev. A – 07/2014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166
Appendix A. Continuous Transmission Test Mode . . . . . . . . . . . . . . .1167
A.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1167
A.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1167
A.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1169
Appendix B. References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1170
Appendix C. Electrical Characteristics at 125°C . . . . . . . . . . . . . . . . . 1171
C.1 Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1171
C.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1171
C.3 General Operating Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1171
C.4 Supply Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1172
C.5 Maximum Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1173
C.6 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1174
C.7 Analog Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1177
C.8 NVM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1183
C.9 Oscillators Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1184
C.10 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1190
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192
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