1/20
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20
1
2.2
-
Rev.C
© 2012 ROHM Co., Ltd. All rights reserved.
High Reliability Series Serial EEPROM Series
I
2
C BUS
Serial EEPROMs
BR24G□□
□□□□
□□□
□□
□-3A Series
☆
☆☆
☆
BR24G01-3A,
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BR24G02-3A,
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BR24G04-3A,
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BR24G08-3A,
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BR24G16-3A,
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BR24G32-3A,
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BR24G64-3A, BR24G128-3A, BR24G256-3A,
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BR24G512-3A,
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BR24G1M-3A
☆
☆☆
☆:BR24G01/02/04/08/16/32/64/512/1M-3A are model, the description matters are target all specifications because of the
model under development.
ROHM's series of serial EEPROMs represent the highest level of reliability on the market. A double cell structure provides a
failsafe method of data reliability, while a double reset function prevents data miswriting, pushing the boundaries of reliability
to the limit.
Contents
BR24G□□
□□□□
□□□
□□
□-3A Series
BR24G01-3A, BR24G02-3A, BR24G04-3A, BR24G08-3A,
BR24G16-3A, BR24G32-3A, BR24G64-3A, BR24G128-3A,
BR24G256-3A, BR24G512-3A, BR24G1M-3A
2/20
BR24G□□□
□□□□□□
□□□-3A Series
www.rohm.com
20
1
2.2
-
Rev.C
© 2012 ROHM Co., Ltd. All rights reserved.
I
2
C BUS Serial EEPROMs
BR24G□
□□
□□
□□
□□
□□
□-3A Series
BR24G01-3A, BR24G02-3A, BR24G04-3A, BR24G08-3A, BR24G16-3A, BR24G32-3A,
BR24G64-3A, BR24G128-3A, BR24G256-3A, BR24G512-3A, BR24G1M-3A
●Description
BR24G□□□-3A series is a serial EEPROM of I
2
C BUS interface method
●Features
・ All controls available by 2 ports of serial clock(SCL) and serial data(SDA)
・ Other devices than EEPROM can be connected to the same port, saving microcontroller port
・ 1.7V～5.5V single power source action most suitable for battery use
・ 1.7V～5.5Ｖwide limit of action voltage, possible 1MHz action
・ Page write mode useful for initial value write at factory shipment
・ Auto erase and auto end function at data write
・ Low current consumption
・ Write mistake prevention function
Write (write protect) function added
Write mistake prevention function at low voltage
・ DIP-T8/SOP8/SOP-J8/SSOP-B8/TSSOP-B8/TSSOP-B8J/MSOP8/VSON008X2030 various package
・ Data rewrite up to 1,000,000 times
・ Data kept for 40 years
・ Noise filter built in SCL / SDA terminal
・ Shipment data all address FFh
●BR24G series
Capacity
Bit format Type
Power source
Voltage DIP-T8 SOP8 SOP-J8 SSOP-B8 TSSOP-B8
TSSOP-B8J MSOP8 VSON008
X2030
1Kbit 128×8 BR24G01-3A 1.7～5.5V
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2Kbit 256×8 BR24G02-3A 1.7～5.5V
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4Kbit 512×8 BR24G04-3A 1.7～5.5V
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8Kbit 1K×8 BR24G08-3A 1.7～5.5V
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16Kbit 2K×8 BR24G16-3A 1.7～5.5V
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32Kbit 4K×8 BR24G32-3A 1.7～5.5V
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64Kbit 8K×8 BR24G64-3A 1.7～5.5V
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128Kbit 16K×8 BR24G128-3A 1.7～5.5V
● ● ● ● ● ● ● ●
256Kbit 32K×8 BR24G256-3A 1.7～5.5V
● ● ● ●
●
512Kbit 64K×8 BR24G512-3A 1.7～5.5V
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1024Kbit
128K×8 BR24G1M-3A 1.7～5.5V
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☆:Developing
3/20
BR24G□□□
□□□□□□
□□□-3A Series
www.rohm.com
20
1
2.2
-
Rev.C
© 2012 ROHM Co., Ltd. All rights reserved.
SCL
SDA
(input)
SDA
(output)
tR tF1 tHIGH
tSU:DAT tLOW tHD:DAT
tDH
tPD
tBUF
tHD:STA
70%
30%
70%
70%
30%
70% 70%
30% 30%
70% 70%
30%
70% 70%
70%
70%
30%
30%
30% 30%
tF2
●Sync data input / output timing
○
Input read at the rise edge of SCL
○
Data output in sync with the fall of SCL
Fig.1-(a) Sync data input / output timing
Fig.1-(b) Start-stop bit timing
Fig.1-(c) Write cycle timing
Fig.1-(d) WP timing at write execution
Fig.1-(e) WP timing at write cancel
●Absolute maximum ratings (Ta=25℃)
Parameter symbol Limits Unit
Impressed voltage V
CC
-0.3～+6.5 V
Permissible
dissipation Pd
450 (SOP8)
*1
mW
450 (SOP-J8)
*2
300 (SSOP-B8)
*3
330 (TSSOP-B8)
*4
310 (TSSOP-B8J)
*5
310 (MSOP8)
*6
300 (VSON008X2030)
*7
800 (DIP-T8)
*8
Storage temperature range Tstg －65～+150 ℃
Action temperature range Topr －40～+85 ℃
Terminal voltage ‐ －0.3～Vcc+1.0
*9
V
Junction Temperature
*10
Tjmax 150 ℃
●Memory cell characteristics (Ta=25℃, Vcc=1.7～5.5V)
Parameter Limits Unit
Min. Typ. Max
Number of data rewrite times *1 1,000,000 － － Times
Data hold years *1 40 － － Years
*1
Not 100% TESTED
●Recommended operating conditions
Parameter Symbol Limits Unit
Power source voltage Vcc 1.7～5.5 V
Input voltage V
IN
0～Vcc
When using at Ta=25℃ or higher, 8.0mW(*8), 4.5mW(*1,*2),
3.0mW(*3,*7), 3.3mW(*4), 3.1mW(*5, *6) to be reduced per 1℃.
*9 The Max value of Terminal Voltage is not over 6.5V.
When the pulse width is 50ns or less,
the Min value of Terminal Voltage is not under -1.0V. (BR24G16/32/64/128/256/512/1M-3A)
the Min value of Terminal Voltage is not under -0.8V. (BR24G01/02/04/08-3A)
*10 Junction temperature at the storage condition.
●Electrical characteristics
(
Unless otherwise specified, Ta=－40～+85
℃、
VCC=1.7～5.5V
)
Parameter
Symbol
Limits
Unit
Conditions
Min. Typ. Max.
“H” input voltage 1 V
IH1
0.7Vcc － Vcc+1.0 V
“L” input voltage 1 V
IL1
－0.3
*1
－ 0.3Vcc V
“L” output voltage 1 V
OL1
－ － 0.4 V I
OL
=3.0mA, 2.5V≦Vcc≦5.5V (SDA)
“L” output voltage 2 V
OL2
－ － 0.2 V I
OL
=0.7mA, 1.7V≦Vcc＜2.5V (SDA)
Input leak current I
LI
－1 － 1 µA V
IN
=0～Vcc
Output leak current I
LO
－1 － 1 µA V
OUT
=0～Vcc (SDA)
Current consumption
at action
I
CC1
－ － 2.0 mA Vcc=5.5V,f
SCL
=400kHz, t
WR
=5ms,
Byte write, Page write
BR24G01/02/04/08/16/32/64-3A
－ － 2.5 mA Vcc=5.5V,f
SCL
=400kHz, t
WR
=5ms,
Byte write, Page write
BR24G128/256-3A
－ － 4.5 mA Vcc=5.5V,f
SCL
=400kHz, t
WR
=5ms,
Byte write, Page write
BR24G512/1M-3A
I
CC2
－ － 0.5 mA
Vcc=5.5V,f
SCL
=1MHz
Random read, current read,
sequential read
BR24G01/02/04/08/16/32/64-3A
－ － 2.0 mA
Vcc=5.5V,f
SCL
=1MHz
Random read, current read,
sequential read
BR24G128/256/512/1M-3A
Standby current I
SB
－ － 2.0
µA
Vcc=5.5V, SDA・SCL=Vcc
A0,A1,A2=GND,WP=GND
BR24G01/02/04/08/16/32/64/128/256-3A
－ － 3.0
µA
Vcc=5.5V, SDA・SCL=Vcc
A0,A1,A2=GND,WP=GND
BR24G512/1M-3A
○Radiation resistance design is not made.
*1
When the pulse width is 50ns or less, it is -1.0V. (BR24G16/32/64/128/256/512/1M-3A)
When the pulse width is 50ns or less, it is -0.8V. (BR24G01/02/04/08-3A)
◇ AC OPERATING CHARACTERISTICS
(Unless otherwise specified, Ta=－40～+85℃, VCC=1.7～5.5V)
Parameter Symbol Limit Unit
Min. Typ. Max.
SCL frequency fSCL － － 1000 kHz
Data clock “HIGH“ time tHIGH 0.3 － － μs
Data clock “LOW“ time tLOW 0.5 － － μs
SDA and SCL rise time
*1
tR － － 0.12 μs
SDA and SCL fall time
*1
tF1 － － 0.12 μs
SDA (OUT) fall time
*1
tF2 － － 0.12 μs
Start condition hold time tHD:STA 0.25 － － μs
Start condition setup time tSU:STA 0.25 － － μs
Input data hold time tHD:DAT 0 － － μs
Input data setup time tSU:DAT 50 － － ns
Output data delay time tPD 0.05 － 0.45 μs
Output data hold time tDH 0.05 － － μs
Stop condition setup time tSU:STO 0.25 － － μs
Bus release time before transfer start tBUF 0.5 － － μs
Internal write cycle time tWR － － 5 ms
Noise removal valid period (SDA, SCL terminal) tI － － 0.05 μs
WP hold time tHD:WP 1.0 － － μs
WP setup time tSU:WP 0.1 － － μs
WP valid time tHIGH:WP 1.0 － － μs
*1 Not 100% TESTED.
●AC TIMING CHARACTERISTICS CONDITION
Parameter
Symbol
Condition
Unit
Load Capacitance
CL 100 pF
SDA and SCL rise time
tR 20 ns
SDA and SCL fall time
tF1 20 ns
Input Data Level
VIL/VIH 0.2Vcc/0.8Vcc V
Input/Output Data Timing Refence Level
－ 0.3Vcc/0.7Vcc V
*1
70% 70%
tSU:STA tHD:STA
START CONDITION
tSU:STO
STOP CONDITION
30%
30%
70%
70%
D0 ACK
tWRwrite data
(n-th address)
START CONDITION
STOP CONDITION
70%
70%
DATA(1)
D0 ACK
D1
DATA(n)
ACK tWR
30%
70%
STOP CONDITION
tHD:WP
tSU:WP
30%
70%
DATA(1)
D0
D1 ACK
DATA(n)
ACK
tHIGH:WP
70% 70%
tWR
70%
4/20
BR24G□□□
□□□□□□
□□□-3A Series
www.rohm.com
20
1
2.2
-
Rev.C
© 2012 ROHM Co., Ltd. All rights reserved.
●Block diagram
●Pin assignment and description
●Characteristic data (The following values are Typ. ones.)
0
1
2
3
4
5
6
0123456
SUPPLY VOLTAGE : Vcc(V)
H INPUT VOLTAGE : VIH1(V)
0
0.2
0.4
0.6
0.8
1
1.2
0 1 2 3 4 5 6
SUPPLYVOLTAGE : Vcc(V)
INPUT LEAK CURRENT : ILI(uA)
0
0.2
0.4
0.6
0.8
1
0123456
L OUTPUT CURRENT : IOL(mA)
L OUTPUT VOLTAGE : VOL2(V)
0
0.2
0.4
0.6
0.8
1
1.2
0123456
SUPPLY VOLTAGE : Vcc(V)
OUTPUT LEAK CURRENT : I LO(uA)
0
0.2
0.4
0.6
0.8
1
0123456
L OUTPUT CURRENT : IOL(mA)
L OUTPUT VOLTAGE : VOL1(V)
Fig.5 'L' output voltage VOL1-IOL(Vcc=1.7V)
0
1
2
3
4
5
6
0123456
SUPPLY VOLTAGE : Vcc(V)
L INPUT VOLTAGE : VIL1(V)
Fig.6　'L' output voltage VOL2-IOL(Vcc=2.5V) Fig.7　Input leak current ILI
(A0,A1,A2,SCL,WP) Fig.8　Output leak current ILO(SDA)
Fig.4　'L' input voltage VIL1
(A0,A1,A2,SCL,SDA,WP)
Fig.3　'H' input voltage VIH1
(A0,A1,A2,SCL,SDA,WP)
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
SPEC
SPEC
SPEC
SPEC SPEC
8
7
6
5
4
3
2
1
SDA
SCL
WP
V
cc
GND
A2
A1
A0
Address
decoder
Word
address
register
Data
register
Control circuit
High voltage
generating circuit
Power source
voltage detection
8bit
ACK
START
STOP
1
Kbit
～
1024
Kbit EEPROM
array
*1
*1
*2
*2
*2
14bit
8bit
9
bit
bit
1
0
bit
1
1
bit
1
2
13bit
Fig.2
Block diagram
＊
1 7bit: BR24G01-3A
8bit: BR24G02-3A
9bit: BR24G04-3A
10bit: BR24G08-3A
11bit: BR24G16-3A
12bit: BR24G32-3A
Vcc
SCL
GND
BR
24G
01
-
3A
BR
24G
02
-
3A
BR
24G
04
-
3A
BR
24G
08
-
3A
BR
24G
16
-
3A
BR
24G
32
-
3A
BR
24G
64
-
3A
1
2
3
4
5
6
7
8
WP
SDA
A2
A1
A0
Terminal
Name Input/
Output BR24G01-3A
BR24G02-3A
BR24G04-3A
BR24G08-3A
BR24G16-3A BR24G32/64/128/256/512-3A BR24G1M-3A
A0 Input Slave address setting Don’t use＊ Slave address setting Don’t use＊
A1 Input Slave address setting Don’t use＊ Slave address setting
A2 Input Slave address setting Don’t use＊ Slave address setting
GND － Reference voltage of all input / output, 0V
SDA
Input/
output
Serial data input serial data output
SCL Input Serial clock input
WP Input Write protect terminal
Vcc － Connect the power source.
＊Pins not used as device address may be set to any of ‘H’, 'L', and 'Hi-Z'.
13bit: BR24G64-3A
14bit: BR24G128-3A
15bit: BR24G256-3A
16bit: BR24G512-3A
17bit: BR24G1M-3A
*2 A0= Don't use : BR24G04/1M-3A
A0, A1=Don't use : BR24G08-3A
A0, A1, A2=Don't use : BR24G16-3A
BR
BR
BR
BR
24G
24G
24G
24G
128
256
512
1M
-
-
-
-
3A
3A
3A
3A
7bit
15bit
16bit
17bit
5/20
BR24G□□□
□□□□□□
□□□-3A Series
www.rohm.com
20
1
2.2
-
Rev.C
© 2012 ROHM Co., Ltd. All rights reserved.
0
0.5
1
1.5
2
2.5
0123456
STANBY CURRENT : I
SB
(uA)
SUPPLY VOLTAGE : Vcc(V)
0
0.5
1
1.5
2
2.5
3
3.5
0123456
CURRENT CONSUMPTION
AT WRITING : Icc1(mA)
SUPPLY VOLTAGE : Vcc(V)
0
0.5
1
1.5
2
2.5
0123456
STANBY CURRENT : I
SB
(uA)
SUPPLY VOLTAGE : Vcc(V)
-0.1
0.1
0.3
0.5
0.7
0.9
1.1
0 1 2 3 4 5 6
START CONDITION
SET UP TIME : tSU:STA(us)
SUPPLY VOLTAGE : Vcc(V)
0.1
1
10
100
1000
10000
0123456
SCL FREQUENCY : fｓｃｌ（ｋHZ）
SUPPLY VOLTAGE : Vcc(V)
-200
-150
-100
-50
0
50
0 1 2 3 4 5 6
INPUT DATA HOLD TIME : t
HD: STA
(ns)
SUPPLY VOLTAGE : Vcc(V)
0
0.2
0.4
0.6
0.8
1
0 1 2 3 4 5 6
DATA CLK H TIME : t
HIGH
(us)
SUPPLY VOLTAGE : Vcc(V)
0
0.5
1
1.5
2
2.5
0123456
CURRENT CONSUMPTION
AT WRITING : Icc1(mA)
SUPPLY VOLTAGE : Vcc(V)
Fig.9 Current consumption at WRITE operation I
CC
1
(fscl=1MHz BR24G01/02/04/08/16/32/64-3A) Fig.10 Current consumption at WRITE operation Icc1
(fscl=1MHz BR24G128/256-3A)
Fig.14 Standby operation I
SB
(BR24G01/02/04/08/16/32/64/128/256-3A)
Fig.17 Data clock High Period t
HIGH
0
0.3
0.6
0.9
1.2
1.5
0123456
ＤＡＴＡ CLK L TIME : tLOW(us)
SUPPLY VOLTAGE : Vcc（V）
Fig.18 Data clock Low Period t
LOW
0
0.2
0.4
0.6
0.8
1
0 1 2 3 4 5 6
START CONDITION HOLD TIME : t
HD : STA
(us)
SUPPLY VOLTAGE : Vcc(V)
Fig.19 Start Condition Hold Time t
HD : STA
Fig.20 Start Condition Setup Time t
SU : STA
Fig.21 Input Data Hold Time t
HD : DAT
（HIGH） Fig.23 Input Data Setup Time ｔ
SU: DAT
(HIGH)
-200
-150
-100
-50
0
50
0123456
INPUT DATA HOLD TIME : t
HD :DAT
(ns)
SUPPLY VOLTAGE : Vcc(V)
-200
-100
0
100
200
300
0123456
INPUT DATA SET UP TIME : t
SU: DAT
(ns)
SUPPLY VOLTAGE : Vcc(V)
Fig.16 SCL frequency f
SCL
Fig.12 Current consumption at READ operation I
CC
2
(fscl=1MHz BR24G01/02/04/08/16/32/64/-3A)
0
1
2
3
4
5
6
0123456
CURRENT CONSUMPTION
AT WRITING : Icc1(mA)
SUPPLY VOLTAGE : Vcc(V)
Fig.11 Current consumption at WRITE operation Icc1
(fscl=1MHz BR24G512/1M-3A)
0
0.1
0.2
0.3
0.4
0.5
0.6
0123456
CURRENT CONSUMPTION
AT READING : Icc2(mA)
SUPPLY VOLTAGE : Vcc(V)
Fig.13 Current consumption at READ operation I
CC
2
(fscl=1MHz BR24G128/256/512/1M-W)
Fig.15 Standby operation I
SB
(BR24G512/1M-3A)
0
0.1
0.2
0.3
0.4
0.5
0.6
0123456
CURRENT CONSUMPTION
AT READING : Icc2(mA)
SUPPLY VOLTAGE : Vcc(V)
SPEC
SPEC
SPEC
The plan for
inserting data.
(BR24G128/256/512/
1M-3A)
The plan for
inserting data.
(BR24G512/1M-3A)
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
The plan for
inserting data.
(BR24G512/1M-3A)
The plan for
inserting data.
(BR24G01/02/08/16/
32/64-3A)
The plan for
inserting data.
The plan for
inserting data.
The plan for
inserting data. The plan for
inserting data. The plan for
inserting data.
The plan for
inserting data. The plan for
inserting data. The plan for
inserting data.
Ta=-40℃
Ta=25℃
Ta=85℃
Fig.22 Input Data Hold Time ｔ
HD : DAT
(LOW）
●Characteristic data (The following values are Typ. ones.)
6/20
BR24G□□□
□□□□□□
□□□-3A Series
www.rohm.com
20
1
2.2
-
Rev.C
© 2012 ROHM Co., Ltd. All rights reserved.
0
0.5
1
1.5
2
0 1 2 3 4 5 6
BUS OPEN TIME
BEFORE TRANSMISSION : t
BUF
(us)
SUPPLY VOLTAGE : Vcc(V)
0
1
2
3
4
5
6
0123456
INTERNAL WRITING
CYCLE TIME : t
WR
(ms)
SUPPLY VOLTAGE : Vcc(V)
-200
-100
0
100
200
300
0123456
INPUT DATA SET UP TIME : t
SU : DAT
(ns)
SUPPLY VOLTAGE : Vcc(V)
0.0
0.5
1.0
1.5
2.0
0123456
OUTPUT DATA DELAY TIME : t
PD
(us)
SUPPLY VOLTAGE : Vcc(V)
Fig.24 Input Data setup time t
SU : DAT
(LOW) Fig.25 'L' Data output delay time t
PD
0Fig.26 'H' Data output delay time ｔ
PD
1
Fig.28 BUS open time before transmission ｔ
BUF
Fig.29 Internal writing cycle time ｔ
WR
0
0.1
0.2
0.3
0.4
0.5
0.6
0123456
NOISE REDUCTION
EFECTIVE TIME : t
l
(SCL H) (us)
SUPPLY VOLTAGE : Vcc(V)
Fig.30 Noise reduction efection time t
l
（SCL H） Fig.31 Noise reduction efective time t
l
（SCL L）
0
0.1
0.2
0.3
0.4
0.5
0.6
0 1 2 3 4 5 6
NOISE REDUCTION
EFECTIVE TIME : t
l
(SCL L)(us)
SUPPLY VOLTAGE : Vcc(V)
Fig.32 Noise resuction efecctive time ｔ
ｌ
（SDA H）
0
0.1
0.2
0.3
0.4
0.5
0.6
0123456
NOISE REDUCTION
EFECTIVE TIME : t
l
(SDA H)(us)
SUPPLY VOLATGE : Vcc(V)
Fig.33 Noise reduction efective time t
l
（SDA L）
0
0.1
0.2
0.3
0.4
0.5
0.6
0123456
NOISE REDUCTION
EFFECTIVE TIME : t
l
(SAD L)(us)
SUPPLY VOLTAGE : Vcc(V)
Fig.35 WP setup time t
SU : WP
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0 1 2 3 4 5 6
WP SET UP TIME : t
SU : WP
(us)
SUPPLY VOLTAGE : Vcc(V)
Fig.36 WP efective time t
HIGH : WP
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0 1 2 3 4 5 6
WP EFFECTIVE TIME : t
HIGH : WP
(us)
SUPPLYVOLTAGE : Vcc(V)
SPEC
SPEC
0.0
0.5
1.0
1.5
2.0
0123456
OUTPUT DATA DELAY TIME : t
PD
(us)
SUPPLY VOLTAGE : Vcc(V)
-0.5
0.0
0.5
1.0
1.5
2.0
0123456
STOP CONDITION SETUP TIME : t
su
:STO(us)
SUPPLY VOLTAGE : Vcc(V)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0123456
WP DATA HOLD TIME : t
HD : WP
(us)
SUPPLYVOLTAGE : Vcc(V)
Fig.27 Stop condition setup time
ｔ
SU
:STO
Ta=-40℃
Ta=25℃
Ta=85℃
Fig.34 WP data hold time tHD:WP
SPEC
The plan for
inserting data. The plan for
inserting data.
The plan for
inserting data.
The plan for
inserting data.
The plan for
inserting data.
The plan for
inserting data.
The plan for
inserting data.
The plan for
inserting data.
The plan for
inserting data.
The plan for
inserting data.
The plan for
inserting data.
Ta=-40℃
Ta=25℃
Ta=85℃
●Characteristic data (The following values are Typ. ones.)
7/20
BR24G□□□
□□□□□□
□□□-3A Series
www.rohm.com
20
1
2.2
-
Rev.C
© 2012 ROHM Co., Ltd. All rights reserved.
●I
2
C BUS communication
○I
2
C BUS data communication
I
2
C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, and
acknowledge is always required after each byte. I
2
C BUS carries out data transmission with plural devices connected by 2
communication lines of serial data (SDA) and serial clock (SCL).
Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is
controlled by address peculiar to devices. EEPROM becomes “slave”. And the device that outputs data to bus during data
communication is called “transmitter”, and the device that receives data is called “receiver”.
○Start condition (Start bit recognition)
・Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is
'HIGH' is necessary.
・This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition is
satisfied, any command is executed.
○Stop condition (stop bit recongnition)
・Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'
○Acknowledge (ACK) signal
・This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In
master and slave, the device (μ-COM at slave address input of write command, read command, and this IC at data
output of read command) at the transmitter (sending) side releases the bus after output of 8bit data.
・The device (this IC at slave address input of write command, read command, and μ-COM at data output of read
command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK
signal) showing that it has received the 8bit data.
・This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.
・Each write action outputs acknowledge signal (ACK signal) 'LOW', at receiving 8bit data (word address and write data).
・Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'. When acknowledge
signal (ACK signal) is detected, and stop condition is not sent from the master (μ-COM) side, this IC continues data
output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and recognizes stop condition
(stop bit), and ends read action. And this IC gets in status.
○Device addressing
・Output slave address after start condition from master.
・The significant 4 bits of slave address are used for recognizing a device type.
The device code of this IC is fixed to '1010'.
・Next slave addresses (A2 A1 A0 --- device address) are for selecting devices, and plural ones can be used on a same
bus according to the number of device addresses.
・ The most insignificant bit (R/W --- READ / WRITE) of slave address is used for designating write or read action, and is
as shown below.
Setting R /
W
――
to 0 ------- write (setting 0 to word address setting of random read)
Setting R /
W
――
to 1 ------- read
P0
～
P2 are page select bits.
Type
Slave address
Maximum number of
Connected buses
BR24G01-3A,BR24G02-3A 1 0 1 0 A2 A1 A0 R/
W
――
8
BR24G04-3A 1 0 1 0 A2 A1 P0 R/
W
――
4
BR24G08-3A 1 0 1 0 A2 P1 P0 R/
W
――
2
BR24G16-3A 1 0 1 0 P2 P1 P0 R/
W
――
1
BR24G32-3A, BR24G64-3A,
BR24G128-3A,BR24G256-3A,
BR24G512-3A 1 0 1 0 A2 A1 A0 R/
W
――
8
BR24G1M-3A 1 0 1 0 A2 A1 P0 R/
W
――
4
8 9 8 9 8 9
S P
condition condition
ACK STOPACKDATA DATA
ADDRESS
START R/W ACK
1-7
SDA
SCL 1-7 1-7
Fig.37 Data transfer timing
8/20
BR24G□□□
□□□□□□
□□□-3A Series
www.rohm.com
20
1
2.2
-
Rev.C
© 2012 ROHM Co., Ltd. All rights reserved.
●Write Command
○Write cycle
・Arbitrary data is written to EEPROM. When to write only 1 byte, byte write is normally used, and when to write continuous data of 2 bytes or
more, simultaneous write is possible by page write cycle. The maximum number of write bytes is specified per device of each capacity.
up to 256 arbitrary bytes can be written. (In the case of BR24G1M-3A)
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
WORD
ADDRESS(n)
DATA(n)
SDA
LINE
A
C
K
A
C
K
DATA(n+15)
A
C
K
SLAVE
ADDRESS
1
0
0
0
1
0
A0
A1
A2
WA
7
D0
D7
D0
WA
0
A1 A2 WA
7 D7
1 1 0 0
W
R
I
T
E
S
T
A
R
T
R
/
W
S
T
O
P
WORD
ADDRESS DATA
SLAVE
ADDRESS
A0 WA
0 D0
A
C
K
SDA
LINE
A
C
K
A
C
K
Note
)
Fig.38
Byte write cycle
(BR24G01/02/04/08/16-3A)
A1 A2
WA
14
1 1 0 0
W
R
I
T
E
S
T
A
R
T
R
/
W
S
T
O
P
1st WORD
ADDRESS DATA
SLAVE
ADDRESS
A0 D0
A
C
K
SDA
LINE
A
C
K
A
C
K
Note
)
WA
13 WA
12 WA
11 WA
0
A
C
K
2nd WORD
ADDRESS
D7
*1
WA
15
*1 As for WA12, BR24G32-3A becomes Don't care.
As for WA13, BR24G32/64-3A becomes Don't care.
As for WA14, BR24G32/64/128-3A becomes Don't care.
As for WA15, BR24G32/64/128/256-3A becomes Don't care.
Fig.39
Byte write cycle
(BR24G32/64/128/256/512/1M -3A)
Fig.40
Page write cycle
(BR24G01/02/04/08/16-3A)
Fig.41
Page write cycle
(BR24G32/64/128/256/512/1M -3A)
*1 As for WA12, BR24G32-3A becomes Don't care.
As for WA13, BR24G32/64-3A becomes Don't care.
As for WA14, BR24G32/64/128-3A becomes Don't care.
As for WA15, BR24G32/64/128/256-3A becomes Don't care.
*2 As for BR24G128/256-3A becomes (n+63)
As for BR24G128/256-3A becomes (n+127)
As for BR24G128/256-3A becomes (n+255)
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
1st WORD
ADDRESS(n)
SDA
LINE
A
C
K
A
C
K
DATA(n+31)
A
C
K
SLAVE
ADDRESS
1
0
0
0
1
0
A0
A1
A2
WA
14
D0
*1
DATA(n)
D0
D7
A
C
K
2nd WORD
ADDRESS(n)
WA
0
WA
13
WA
12
WA
11
10
0
1 A0
A1
A2
*1 *2 *3
Note)
Fig.42 Difference of slave address of each type
As for
WA7, BR24G01-3A becomes Don't care.
*1
As for
WA7, BR24G01-3A becomes Don't care.
*2
As for
BR24G01/02-3A becomes (n+7)
*2
*1
WA
15
*1 In BR24G16-3A, A2 becomes P2.
*2 In BR24G08/16-3A, A1 becomes P1.
*3 In BR24G04/08/16/1M-3A A0 becomes P0.
Note)
Note)
*2
9/20
BR24G□□□
□□□□□□
□□□-3A Series
www.rohm.com
20
1
2.2
-
Rev.C
© 2012 ROHM Co., Ltd. All rights reserved.
・During internal write execution, all input commands are ignored, therefore ACK is not sent back.
・Data is written to the address designated by word address (n-th address)
・By issuing stop bit after 8bit data input, write to memory cell inside starts.
・When internal write is started, command is not accepted for tWR (5ms at maximum).
・By page write cycle, the following can be written in bulk : Up to 8Byte (BR24G01-3A, BR24G02-3A）
Up to 16Byte (BR24G04-3A, BR24G08-3A, BR24G16-3A）
Up to 32Byte (BR24G32-3A, BR24G64-3A）
Up to 64Byte (BR24G128-3A, BR24G256-3A）
Up to 128Byte (BR24G512 -3A）
Up to 256Byte (BR24G1M-3A）
And when data of the maximum bytes or higher is sent, data from the first byte is overwritten.
(Refer to "Internal address increment" of "Notes on page write cycle" in P10.)
・ As for page write cycle of BR24G01-3A and BR24G02-3A, after the significant 4 bits (in the case of BR24G01-3A) of word address,
or the significant 5 bits (in the case of BR24G02-3A) of word address are designated arbitrarily, by continuing data input of 2 bytes
or more, the address of insignificant 3 bits is incremented internally, and data up to 8 bytes can be written.
・ As for page write command of BR24G04-3A, BR24G08-3A and BR24G16-3A, after page select bit ’P0’(in the case of
BR24G04-3A), after page select bit ’P0,P1’(in the case of BR24G08-3A), after page select bit ’P0,P1,P2’(in the case of
BR24G16-3A) of slave address are designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 4
bits is incremented internally, and data up to 16 bytes can be written.
・ As for page write cycle of BR24G32-3A and BR24G64-3A, after the significant 7 bits (in the case of BR24G32-3A) of word address,
or the significant 8 bits (in the case of BR24G64-3A) of word address are designated arbitrarily, by continuing data input of 2 bytes
or more, the address of insignificant 5 bits is incremented internally, and data up to 32 bytes can be written.
・ As for page write cycle of BR24G128-3A and BR24G256-3A, after the significant 8 bits (in the case of BR24G128-3) of word
address, or the significant 9 bits (in the case of BR24G256-3A) of word address are designated arbitrarily, by continuing data input
of 2 bytes or more, the address of insignificant 6 bits is incremented internally, and data up to 64 bytes can be written.
・ As for page write cycle of BR24G512-3A after the significant 9 bits of word address are designated arbitrarily, by continuing data
input of 2 bytes or more, the address of insignificant 7 bits is incremented internally, and data up to 128 bytes can be written.
・ As for page write cycle of BR24G1M-3A after page select bit ‘P0’ and the significant 8 bits of word address are designated
arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 8 bits is incremented internally, and data up to
256 bytes can be written.
10/20
BR24G□□□
□□□□□□
□□□-3A Series
www.rohm.com
20
1
2.2
-
Rev.C
© 2012 ROHM Co., Ltd. All rights reserved.
○Notes on page write cycle
List of numbers of page write
Number of
Pages 8Byte 16Byte 32Byte 64Byte 128Byte 256Byte
Product
number BR24G01-3A
BR24G02-3A
BR24G04-3A
BR24G08-3A
BR24G16-3A
BR24G32-3A
BR24G64-3A BR24G128-3A
BR24G256-3A BR24G512-3A BR24G1M-3A
The above numbers are maximum bytes for respective types.
Any bytes below these can be written.
In the case BR24G256-3A, 1 page=64bytes, but the page
write cycle time is 5ms at maximum for 64byte bulk write.
It does not stand 5ms at maximum × 64byte=320ms(Max.)
○Internal address increment
Page write mode (in the case of BR24G16-3A）
○Write protect (WP) terminal
・Write protect (WP) function
When WP terminal is set Vcc (H level), data rewrite of all addresses is prohibited. When it is set GND (L level), data rewrite of all
address is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level. Do not use it open.
In the case of use it as an ROM, it is recommended to connect it to pull up or Vcc.
At extremely low voltage at power ON / OFF, by setting the WP terminal 'H', mistake write can be prevented.
For example, when it is started from address 0Eh,
therefore, increment is made as below,
0Eh→0Fh→00h→01h･･･ which please note.
※0Eh･･･0E in hexadecimal, therefore, 00001110 becomes a
binary number.
WA7 WA4 WA3 WA2 WA1 WA0
0 00000
0 00001
0 00010
0 01110
0 01111
0 00000
Increment
0Eh
Significant bit is fixed.
No digit up
11/20
BR24G□□□
□□□□□□
□□□-3A Series
www.rohm.com
20
1
2.2
-
Rev.C
© 2012 ROHM Co., Ltd. All rights reserved.
●Read Command
○Read cycle
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.
Random read cycle is a command to read data by designating address, and is used generally.
Current read cycle is a command to read data of internal address register without designating address, and is used when to verify just
after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can be read in succession.
・In random read cycle, data of designated word address can be read.
・When the command just before current read cycle is random read cycle, current read cycle (each including sequential read cycle), data of
incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.
・When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (μ-COM) side, the next address data can be
read in succession.
・Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal 'H' .
・When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to input 'H' to ACK
signal after D0, and to start SDA at SCL signal 'H'.
・Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL signal 'H'.
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
WORD
ADDRESS(n)
SDA
LINE
A
C
K
A
C
K
DATA(n)
A
C
K
SLAVE
ADDRESS
1 0
0
1
A0
A1
A2
WA
7 A0
D0
SLAVE
ADDRESS
1 0
0
1 A1
A2
S
T
A
R
T
D7
R
/
W
R
E
A
D
WA
0
Note)
*1
Fig.43 Random read cycle (BR24G01/02/04/08/16-3A)
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
1st WORD
ADDRESS（ｎ）
SDA
LINE
A
C
K
A
C
K
DATA(n)
A
C
K
SLAVE
ADDRESS
10
0
1A0 A1
A2
WA
14
D7 D0
2nd WORD
ADDRESS（ｎ）
A
C
K
S
T
A
R
T
SLAVE
ADDRESS
10
0
1A2
A1
R
/
W
R
E
A
D
A0
WA
0
Note
)
*1
WA
13
WA
12
WA
11
WA
15
Fig.44 Random read cycle (BR24G32/64/128/256/512/1M-3A)
*1
As for WA12, BR24G32-3A become Don’t care.
As for WA13, BR24G32/64-3A become Don’t care.
As for WA14, BR24G32/64/128-3A become Don’t care.
As for WA15, BR24G32/64/128/256-3A become Don’t care.
S
T
A
R
T
S
T
O
P
SDA
LINE
A
C
K
DATA(n)
A
C
K
SLAVE
ADDRESS
1 0 0 1 A0 A1 A2 D0 D7
R
/
W
R
E
A
D
Note)
Fig.45 Current read cycle
R
E
A
D
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
DATA(n)
SDA
LINE
A
C
K
A
C
K
DATA(n+x)
A
C
K
SLAVE
ADDRESS
1 0
0
1A0
A1
A2
D0
D7
D0
D7
Note）
Fig.46 Sequential read cycle (in the case of current read cycle)
10
0
1 A0
A1
A2
*1 *2 *3
*1
In BR24G16
-
3
A
, A2 becomes P2.
*2 In BR24G08/16-3A, A1 becomes P1.
*3 In BR24G08/16/1M-3A, A0 becomes P0.
Note)
*1
As for WA7,BR24G01-3A become Don’t care.
Fig.47 Difference of slave address of each type
12/20
BR24G□□□
□□□□□□
□□□-3A Series
www.rohm.com
20
1
2.2
-
Rev.C
© 2012 ROHM Co., Ltd. All rights reserved.
●Software reset
Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset has several kinds,
and 3 kinds of them are shown in the figure below. (Refer to Fig.45-(a), Fig.45-(b), Fig.45-(c).) In dummy clock input area, release the
SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L' level) may be output from EEPROM, therefore, if 'H' is
input forcibly, output may conflict and over current may flow, leading to instantaneous power failure of system power source or influence
upon devices.
●
Acknowledge polling
During internal write execution, all input commands are ignored, therefore ACK is not sent back. During internal automatic write execution
after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then it means end of write action,
while if it sends back 'H', it means now in writing. By use of acknowledge polling, next command can be executed without waiting for tWR =
5ms.
When to write continuously, R/W = 0, when to carry out current read cycle after write, slave address R/W = 1 is sent, and if ACK signal
sends back 'L', then execute word address input and data output and so forth.
1 2 13 14
SCL
Dummy clock×14 Start×2
SCL
Fig.48-(a) The case of dummy clock +START+START+ command input
スタート
※Start command from START input.
2 1 8 9
Dummy clock×9
Start
Fig.48-(b) The case of START +9 dummy clocks +START+ command input
Start
Normal command
Normal command
Normal command
Normal command
Start×9
SDA
SDA
SCL
SD
1 2 3 8 9 7
Fig.48-(c) START×9+ command input
Normal command
Normal command
SDA
Slave
address
Word
address
…
…
S
T
A
R
T
First write command
A
C
K
H
A
C
K
L
Slave
address
Slave
address
Slave
address Data
Write command
During internal write,
ACK = HIGH is sent back.
After completion of internal write,
ACK=LOW is sent back, so input
next word address and data in
succession.
tWR
tWR
Second write command
S
T
A
R
T
S
T
A
R
T
S
T
A
R
T
S
T
A
R
T
S
T
O
P
S
T
O
P
A
C
K
H
A
C
K
H
A
C
K
L
A
C
K
L
Fig.49 Case to continuously write by acknowledge polling
13/20
BR24G□□□
□□□□□□
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●
WP valid timing (write cancel)
WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP valid timing. During
write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte write cycle and page write cycle, the
area from the first start condition of command to the rise of clock to taken in D0 of data(in page write cycle, the first byte data) is cancel
invalid area.
WP input in this area becomes Don't care. The area from the rise of SCL to take in D0 to input the stop condition is cancel valid area. And,
after execution of forced end by WP, standby status gets in.
●
Command cancel by start condition and stop condition
During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Fig.51)
However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop condition cannot be
input, so reset is not available. Therefore, execute software reset. And when command is cancelled by start, stop condition, during random
read cycle, sequential read cycle, or current read cycle, internal setting address is not determined, therefore, it is not possible to carry out
current read cycle in succession. When to carry out read cycle in succession, carry out random read cycle.
・
Rise of D0 taken clock
SCL
D0 ACK
Enlarged view
SCL
SDA ACK D0
・Rise of SDA
SDA
WP
WP cancel invalid area WP cancel valid area
Data is not written.
Fig.50 WP valid timing
Slave
address D7 D6 D5 D4 D3 D2 D1 D0 Data tWR
SDA D1
S
T
A
R
T
A
C
K
L
A
C
K
L
A
C
K
L
A
C
K
L
S
T
O
P
Word
address
Fig.51 Case of cancel by start, stop condition during slave address input
SCL
SDA 1 1 0 0
Start condition
Stop condition
Enlarged view
WP cancel invalid area
14/20
BR24G□□□
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●
I/O peripheral circuit
○Pull up resistance of SDA terminal
SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (R
PU
), select an appropriate value to this resistance
value from microcontroller V
IL
, I
L
,
and V
OL
-I
OL
characteristics of this IC. If R
PU
is large, action frequency is limited. The smaller the R
PU
, the
larger the consumption current at action.
○Maximum value of R
PU
The maximum value of R
PU
is determined by the following factors.
①SDA rise time to be determined by the capacitance (CBUS) of bus line of R
PU
and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
②The bus electric potential A to be determined by input leak total (I
L
) of device connected to bus at output of 'H' to SDA bus and R
PU
should sufficiently secure the input 'H' level (V
IH
) of microcontroller and EEPROM including recommended noise margin 0.2Vcc.
V
CC
－
I
L
R
PU
－
0.2 V
CC
≧ V
IH
∴R
PU
≦0.8V
CC－
V
IH
I
L
Ex.) V
CC
=3V I
L
=10µA V
IH
=0.7 V
CC
from②
≦
300 ［kΩ］
R
PU
≦
0.8×3－0.7×3
10×10
-6
○ Minimum value of R
PU
The minimum value of R
PU
is determined by the following factors.
When IC outputs LOW, it should be satisfied that V
OLMAX
=0.4V and I
OLMAX
=3mA.
②V
OLMAX
= should secure the input 'L' level (V
IL
) of microcontroller and EEPROM including recommended noise margin 0.1Vcc.
V
OLMAX
≦ V
IL
－
0.1 V
CC
Ex.) V
CC
=3V、V
OL
=0.4V、I
OL
=3mA、microcontroller, EEPROM V
IL
=0.3Vcc
And V
OL
=0.4［V］
V
IL
=0.3×3
=0.9［V］
Therefore, the condition ② is satisfied.
○Pull up resistance of SCL terminal
When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes 'Hi-Z', add a pull
up resistance. As for the pull up resistance, one of several kΩ ~ several ten kΩ is recommended in consideration of drive performance
of output port of microcontroller.
I
OL
R
PU
≧V
CC－
V
OL
I
OL
∴
V
CC－
V
OL
R
PU
≦
≧867 ［Ω］
R
PU
≧3－0.4
3×10
-3
from①
Microcontroller
R
PU
A SDA
terminal
I
L
I
L
Bus line
capacity
CBUS
Fig.52 I/O circuit diagram
BR24GXX
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BR24G□□□
□□□□□□
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●Cautions on microcontroller connection
○R
S
In I
2
C BUS, it is recommended that SDA port is of open drain input/output. However, when using CMOS input / output of tri state to SDA
port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM. This controls over current that
occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON simultaneously. Rs also plays the role of protection of
SDA terminal against surge. Therefore, even when SDA port is open drain input/output, Rs can be used.
○Maximum value of Rs
The maximum value of Rs is determined by the following relations.
①SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
②The bus electric potential A to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus sufficiently secure
the input 'L' level (V
IL
) of microcontroller including recommended noise margin 0.1Vcc.
○Minimum value of Rs
The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source line, and
instantaneous power failure of power source may occur. When allowable over current is defined as I, the following relation must be
satisfied. Determine the allowable current in consideration of impedance of power source line in set and so forth. Set the over current to
EEPROM 10mA or below.
R
PU
Microcontroller
R
S
EEPROM
Fig.53 I/O circuit diagram Fig.54 Input / output collision timing
ACK
'L' output of EEPROM
'H' output of microcontroller
Over current flows to SDA line by 'H'
output of microcontroller and 'L'
output of EEPROM.
SCL
SDA
Microcontroller EEPROM
'L'output
R
S
R
PU
'H' output
Over current I
Fig.56 I/O circuit diagram
≦1.67［kΩ］
≦0.3×3－0.4－0.1×3 ×20×10
3
1.1×3－0.3×3
R
S
× R
PU
1.1V
CC
-V
IL
Ex.）V
CC
=3V　V
IL
=0.3V
CC
　V
OL
=0.4V　R
PU
=20kΩ
∴R
S
≦V
IL－
V
OL－
0.1V
CC
(V
CC－
V
OL
)×R
S
+ V
OL
+0.1V
CC
≦V
IL
R
PU
+R
S
V
CC
R
S
V
CC
I
≧300［Ω］
∴
Ex.) VCC=3V, I=10mA
RS≧3
10×10
-3
≦I
RS≧
R
PU
Micro controller
R
S
EEPROM
I
OL
A
Bus line
capacity
CBUS
V
OL
V
CC
V
IL
Fig.55 I/O Circuit Diagram
16/20
BR24G□□□
□□□□□□
□□□-3A Series
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2.2
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●I
2
C BUS input / output circuit
○Input (A0, A1, A2, SCL, WP)
○Input / output (SDA)
Fig.57 Input pin circuit diagram
Fig.58 Input / output pin circuit diagram
17/20
BR24G□□□
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●Notes on power ON
At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset, and
malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action, observe the following
conditions at power on.
1. Set SDA = 'H' and SCL ='L' or 'H’
2. Start power source so as to satisfy the recommended conditions of t
R
, t
OFF
, and Vbot for operating POR circuit.
tOFF
tR
Vbot
0
V
CC
3. Set SDA and SCL so as not to become 'Hi-Z'.
When the above conditions 1 and 2 cannot be observed, take the following countermeasures.
a) In the case when the above condition 1 cannot be observed. When SDA becomes 'L' at power on .
→Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'.
ｂ)
In the case when the above condition 2 cannot be observed.
→After power source becomes stable, execute software reset(P12).
ｃ)
In the case when the above conditions 1 and 2 cannot be observed.
→Carry out a), and then carry out b).
● Low voltage malfunction prevention function
LVCC circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. =1.2V) or below, it prevent data
rewrite.
●Vcc noise countermeasures
○Bypass capacitor
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended to attach a by
pass capacitor (0.1µF) between IC Vcc and GND. At that moment, attach it as close to IC as possible.
And, it is also recommended to attach a bypass capacitor between board Vcc and GND.
● Cautions on use
(1)
Described numeric values and data are design representative values, and the values are not guaranteed.
(2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In the
case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static
characteristics and transition characteristics and fluctuations of external parts and our LSI.
(3)
Absolute maximum ratings
If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI may be
destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute
maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum
ratings should not be impressed to LSI.
(4) GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of GND terminal.
(5) Terminal design
In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin.
(6) Terminal to terminal shortcircuit and wrong packaging
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in
the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be
destructed.
(7)
Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
Fig.59 Rise waveform diagram
Recommended conditions of tR, tOFF,Vbot
tR tOFF Vbot
10ms or below
10ms or larger 0.3V or below
100 or below 10ms or larger 0.2V or below
Fig.60 When SCL=’H’ and SDA=’L’ Fig.61 When SCL=’L’ and SDA=’L’
18/20
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2.2
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BR24G□□
□□□□
□□-3A Series
●Order part number
●
●●
●Package specifications
B R
2 4
G
5
F
3
ROHM type
name
BUS type
24：I
2
C
Operating
temperature/
Power source
Voltage
G:-40℃～+85℃/
1.7V～5.5V
White Reel
Process Code
E
Package specifications
E2：reel shape emboss taping
TR：reel shape emboss taping
2
Package
Blank
:DIP-T8
F :SOP8
FJ :SOP-J8
FV : SSOP-B8
FVT : TSSOP-B8
FVJ : TSSOP-B8J
FVM : MSOP8
NUX : VSON008X2030
A
G
2
Revision
Halogen free
6
Capacity
01=1K 64＝64K
02=2K 128=128K
04=4K 256=256K
08=8K 512=512K
16=16K 1M=1024K
32＝32K
T
100% Sn
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BR24G□□
□□□□
□□-3A Series
20/20
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20
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2.2
-
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© 2012 ROHM Co., Ltd. All rights reserved.
BR24G□□
□□□□
□□-3A Series