FUJITSU SEMICONDUCTOR
DATA SHEET
Copyright©2007-2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2011.7
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
8-bit Microcontrollers
CMOS
F2MC-8FX MB95130MB Series
MB95136MB/F133MBS/F133NBS/F133JBS/F134MBS/F134NBS/F134JBS/
MB95F136MBS/F136NBS/F136JBS/F133MBW/F133NBW/F133JBW/F134MBW/
MB95F134NBW/F134JBW/F136MBW/F136NBW/F136JBW/FV100D-103
■DESCRIPTION
The MB95130MB series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,
the microcontrollers contain a variety of peripheral functions.
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■FEATURES
• F2MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instruction
• Bit manipulation instructions etc.
• Clock
• Main clock
• Main PLL clock
• Sub clock (for dual clock product)
• Sub PLL clock (for dual clock product)
(Continued)
DS07-12621-3E
MB95130MB Series
2DS07-12621-3E
(Continued)
• Timer
• 8/16-bit compound timer × 1 channel
• 8/16-bit PPG × 1 channel
• 16-bit PPG × 1 channel
• Time-base timer × 1 channel
• Watch prescaler (for dual clock product) × 1 channel
• LIN-UART × 1 channel
• LIN function, Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
• Full duplex double buffer
• UART/SIO × 1 channel
• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
• Full duplex double buffer
• External interrupt × 8 channels
• Interrupt by edge detection (rising, falling, or both edges can be selected)
• Can be used to recover from low-power consumption (standby) modes.
• 8/10-bit A/D converter × 8 channels
• 8-bit or 10-bit resolution can be selected.
• Low-power consumption (standby) mode
• Stop mode
• Sleep mode
• Watch mode (for dual clock product)
• Time-base timer mode
• I/O port
• The number of maximum ports
• Single clock product : 19 ports
• Dual clock product : 17 ports
• Configuration
General-purpose I/O ports (COMS) : Single clock product : 19 ports
Dual clock product : 17 ports
• Power-on reset
A power-on reset is generated when the power is switched on.
• Programmable input voltage levels of port
Automotive input level / CMOS input level / hysteresis input level
• Flash memory security function
Protects the content of Flash memory (Flash memory device only)
MB95130MB Series
DS07-12621-3E 3
■MEMORY LINEUP
Flash memory RAM
MB95F133MBS/F133NBS/F133JBS 8 Kbytes 256 bytes
MB95F133MBW/F133NBW/F133JBW
MB95F134MBS/F134NBS/F134JBS 16 Kbytes 512 bytes
MB95F134MBW/F134NBW/F134JBW
MB95F136MBS/F136NBS/F136JBS 32 Kbytes 1 Kbyte
MB95F136MBW/F136NBW/F136JBW
MB95130MB Series
4DS07-12621-3E
■PRODUCT LINEUP
(Continued)
Part number
Parameter
MB95136MB
MB95
F133MBS/
F134MBS/
F136MBS
MB95
F133NBS/
F134NBS/
F136NBS
MB95
F133MBW/
F134MBW/
F136MBW
MB95
F133NBW/
F134NBW/
F136NBW
MB95
F133JBS/
F134JBS/
F136JBS
MB95
F133JBW/
F134JBW/
F136JBW
Type MASK ROM
product Flash memory product
ROM capacity*132 Kbytes (Max)
RAM capacity*11 Kbyte (Max)
Power-on reset Yes
Reset output Not
selectable*2Yes No
Option*2
Clock
system
Selectable
single/dual
clock*3
Single clock Dual clock Single clock Dual clock
Low voltage
detection
reset
Yes/No No Yes No Yes
Clock
supervisor Yes/No No Yes
CPU functions
Number of basic instructions : 136
Instruction bit length : 8 bits
Instruction length : 1 to 3 bytes
Data bit length : 1, 8, and 16 bits
Minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25 MHz)
Interrupt processing time : 0.6 μs (at machine clock frequency 16.25 MHz)
Peripheral functions
General-
purpose
I/O port
• Single clock product : 19 ports
• Dual clock product : 17 ports
Programmable input voltage levels of port :
Automotive input level / CMOS input level / hysteresis input level
Time-base
timer
(1 channel)
Interval time : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz)
Watchdog
timer
Reset generated cycle
At main oscillation clock 10 MHz : Min 105 ms
At sub oscillation clock 32.768 kHz (for dual clock product) : Min 250 ms
Wild register Capable of replacing 3 bytes of ROM data
UART/SIO
(1 channel)
Data transfer capable in UART/SIO
Full duplex double buffer, variable data length (5/6/7/8-bit), built-in baud rate generator
NRZ type transfer format, error detected function
LSB-first or MSB-first can be selected.
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
LIN-UART
(1 channel)
Dedicated reload timer allowing a wide range of communication speeds to be set.
Full duplex double buffer.
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
LIN functions available as the LIN master or LIN slave.
MB95130MB Series
DS07-12621-3E 5
(Continued)
*1 : For ROM capacity and RAM capacity, refer to “■ MEMORY LINEUP”.
*2 : For details of option, refer to “■ MASK OPTION”.
*3 : Specify clock mode when ordering MASK ROM.
Note: Part number of evaluation product in MB95130MB series is MB95FV100D-103.
When using it, the MCU board (MB2146-303A-E) is required.
Part number
Parameter
MB95136MB
MB95
F133MBS/
F134MBS/
F136MBS
MB95
F133NBS/
F134NBS/
F136NBS
MB95
F133MBW/
F134MBW/
F136MBW
MB95
F133NBW/
F134NBW/
F136NBW
MB95
F133JBS/
F134JBS/
F136JBS
MB95
F133JBW/
F134JBW/
F136JBW
Peripheral functions
8/10-bit
A/D
converter
(8 channels)
8-bit or 10-bit resolution can be selected.
8/16-bit
compound
timer
(1 channel)
Each channel of the timer can be used as “8-bit timer x 2 channels” or “16-bit timer x 1 channel”.
Built-in timer function, PWC function, PWM function, capture function and square wave-form output
Count clock: 7 internal clocks and external clock can be selected.
16-bit PPG
(1 channel)
PWM mode or one-shot mode can be selected.
Counter operating clock: Eight selectable clock sources
Support for external trigger start
8/16-bit PPG
(1 channel)
Each channel of the PPG can be used as “8-bit PPG x 2 channels” or “16-bit PPG x 1 channel”.
Counter operating clock: Eight selectable clock sources
Watch
counter
(for dual
clock
product)
(1 channel)
Count clock : Four selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)
Counter value can be set from 0 to 63. (Capable of counting for 1 minute when selecting clock
source 1 second and setting counter value to 60)
Watch
prescaler
(for dual
clock
product)
(1 channel)
Four selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)
External
interrupt
(8 channels)
Interrupt by edge detection (rising, falling, or both edges can be selected.)
Can be used to recover from standby modes.
Flash memory
Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of write/erase cycles (Minimum) : 10000 times
Data retention time : 20 years
Erase can be performed on each block
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash
(MB95F136MBS/F136NBS/F136JBS/F136MBW/F136NBW/F136JBW)
Standby mode Sleep, stop, watch (for dual clock product), and time-base timer
MB95130MB Series
6DS07-12621-3E
■OSCILLATION STABILIZATION WAIT TIME
The initial value of the main clock oscillation stabilization wait time is fixed to the maximum value. The maximum
value is shown below.
■PACKAGES AND CORRESPONDING PRODUCTS
: Available
: Unavailable
Oscillation stabilization wait time Remarks
(214-2) /FCH Approx. 4.10 ms (at main oscillation clock 4 MHz)
Part number
Package
MB95136MB
MB95F133MBS
MB95F133NBS
MB95F134MBS
MB95F134NBS
MB95F136MBS
MB95F136NBS
MB95F133JBS
MB95F134JBS
MB95F136JBS
MB95F133MBW
MB95F133NBW
MB95F134MBW
MB95F134NBW
MB95F136MBW
MB95F136NBW
MB95F133JBW
MB95F134JBW
MB95F136JBW
MB95FV100D-103
FPT-28P-M17
FPT-30P-M02
BGA-224P-M08
MB95130MB Series
DS07-12621-3E 7
■ DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS
• Notes on using evaluation products
The Evaluation product has not only the functions of the MB95130MB series but also those of other products to
support software development for multiple series and models of the F
2
MC-8FX. The I/O addresses for peripheral
resources not used by the MB95130MB series are therefore access-barred. Read/write access to those access-
barred addresses may cause peripheral resources supposed to be unused to operate, resulting in unexpected
malfunctions of hardware or software.
Particularly, do not use word access to an odd-numbered-byte address in the prohibited areas (If such access is
used, the address may be read or written unexpectedly) .
Also, as the read values of prohibited addresses on the evaluation product are different to the values on the flash
memory and mask ROM products, do not use these values in the software processing.
The Evaluation product does not support the functions of some bits in single-byte registers. Read/write access
to these bits does not cause hardware malfunctions. No particular precautions are required to the flash memory
and mask ROM products, as they have the identical read/write operation to the evaluation products.
• Difference of memory spaces
If the amount of memory on the Evaluation product is different from that of the Flash memory or MASK ROM
product, carefully check the difference in the amount of memory from the model to be actually used when
developing software.
For details of memory space, refer to “■ CPU CORE”.
• Current consumption
• The current consumption of Flash memory product is greater than for MASK ROM product.
• For details of current consumption, refer to “■ ELECTRICAL CHARACTERISTICS”.
• Package
For details of information on each package, refer to “■ PACKAGES AND CORRESPONDING PRODUCTS”
and “■ PACKAGE DIMENSION”.
• Operating voltage
The operating voltage is different among the Evaluation, Flash memory, and MASK ROM products.
For details of the operating voltage, refer to “■ ELECTRICAL CHARACTERISTICS”.
• Difference MOD Pins
A pull-down resistor is provided for the MOD pin of the MASK ROM product.
MB95130MB Series
8DS07-12621-3E
■PIN ASSIGNMENT
(Continued)
(TOP VIEW)
(FPT-28P-M17)
* : Single clock product is general-purpose port, and dual clock product is sub clock oscillation pin.
P15
P14/PPG0
P13/TRG0/ADTG
P12/UCK0/EC0
P11/UO0
P10/UI0
P07/INT07/AN07
P06/INT06/AN06/TO01
P01/INT01/AN01/PPG01
P00/INT00/AN00/PPG00
P05/INT05/AN05/TO00
P04/INT04/AN04/SIN
P03/INT03/AN03/SOT
P02/INT02/AN02/SCK
P16
PF0
PF1
MOD
X0
X1
VSS
VCC
AVCC
AVSS
C
PG2/X1A*
PG1/X0A*
RST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SOP-28
MB95130MB Series
DS07-12621-3E 9
(Continued)
(TOP VIEW)
(FPT-30P-M02)
* : Single clock product is general-purpose port, and dual clock product is sub clock oscillation pin.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
P16
PF0
PF1
MOD
X0
X1
VSS
VCC
C
PG2/X1A*
PG1/X0A*
RST
AVCC
AVSS
P00/INT00/AN00/PPG00
P15
P14/PPG0
P13/TRG0/ADTG
P12/UCK0/EC0
NC
P11/UO0
P10/UI0
P07/INT07/AN07
P06/INT06/AN06/TO01
P05/INT05/AN05/TO00
P04/INT04/AN04/SIN
NC
P03/INT03/AN03/SOT
P02/INT02/AN02/SCK
P01/INT01/AN01/PPG01
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SSOP-30
MB95130MB Series
10 DS07-12621-3E
■PIN DESCRIPTION
(Continued)
Pin no.
Pin name
I/O
circuit
type*3
Function
SSOP*1SOP*2
1 1 P16 H General-purpose I/O port
22 PF0 K General-purpose I/O port for large current
33 PF1
4 4 MOD B Operating mode designation pin
55 X0 AMain clock oscillation input pin
6 6 X1 Main clock oscillation input/output pin
77 V
SS ⎯Power supply pin (GND)
88 V
CC ⎯Power supply pin
99 C ⎯Capacity connection pin
10 10 PG2/X1A
H/A
Single clock product is general-purpose port (PG2) .
Dual clock product is sub clock input/output oscillation pin (32 kHz) .
11 11 PG1/X0A Single clock product is general-purpose port (PG1) .
Dual clock product is sub clock input oscillation pin (32 kHz) .
12 12 RST B’ Reset pin
13 13 AVCC ⎯A/D converter power supply pin
14 14 AVSS ⎯A/D converter power supply pin (GND)
15 15
P00/INT00/
AN00/
PPG00
D
General-purpose I/O port
Shared with external interrupt input (INT00), A/D converter analog
input (AN00) and 8/16-bit PPG ch.0 output (PPG00).
16 16
P01/INT01/
AN01/
PPG01
General-purpose I/O port
Shared with external interrupt input (INT01), A/D converter analog
input (AN01) and 8/16-bit PPG ch.0 output (PPG01).
17 17 P02/INT02/
AN02/SCK
General-purpose I/O port
Shared with external interrupt input (INT02), A/D converter analog
input (AN02) and LIN-UART clock I/O (SCK).
18 18 P03/INT03/
AN03/SOT
General-purpose I/O port
Shared with external interrupt input (INT03), A/D converter analog
input (AN03) and LIN-UART data output (SOT).
20 19 P04/INT04/
AN04/SIN E
General-purpose I/O port
Shared with external interrupt input (INT04), A/D converter analog
input (AN04) and LIN-UART data input (SIN).
21 20 P05/INT05/
AN05/TO00
D
General-purpose I/O port
Shared with external interrupt input (INT05 & INT06), A/D converter
analog input (AN05 & AN06) and 8/16-bit compound timer ch.0
output (TO00 & TO01).
22 21 P06/INT06/
AN06/TO01
23 22 P07/INT07/
AN07
General-purpose I/O port
Shared with external interrupt input (INT07) and A/D converter
analog input (AN07).
MB95130MB Series
DS07-12621-3E 11
(Continued)
*1 : FPT-30P-M02
*2 : FPT-28P-M17
*3 : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.
Pin no.
Pin name
I/O
circuit
type*3
Function
SSOP*1SOP*2
24 23 P10/UIO G General-purpose I/O port
Shared with UART/SIO ch.0 data input (UI0)
25 24 P11/UO0
H
General-purpose I/O port
Shared with UART/SIO ch.0 data output (UO0)
27 25 P12/UCK0/
EC0
General-purpose I/O port
Shared with UART/SIO ch.0 clock I/O (UCK0) and 8/16-bit compound
timer ch.0 clock input (EC0)
28 26 P13/TRG0/
ADTG
General-purpose I/O port
Shared with 16-bit PPG ch.0 trigger input (TRG0) and A/D converter
trigger input (ADTG)
29 27 P14/PPG0 General-purpose I/O port
Shared with 16-bit PPG ch.0 output (PPG0)
30 28 P15 General-purpose I/O port
19,26 ⎯NC ⎯Internally connected pins.
Be sure to leave it open.
MB95130MB Series
12 DS07-12621-3E
■I/O CIRCUIT TYPE
(Continued)
Type Circuit Remarks
A • Oscillation circuit
• High-speed side
Feedback resistance: approx. 1 MΩ
• Low-speed side
Feedback resistance: approx. 10 MΩ
B Only for input
• Hysteresis input
• Pull-down resistor available only to MASK
ROM product
B’ • Hysteresis input only for MASK ROM
product
• Reset output
D • CMOS output
• Hysteresis input
• Analog input
• Pull-up control available
• Automotive input
X0 (X0A)
X1 (X1A)
N-ch
X0 (X0A)
X1 (X1A)
N-ch
Standby control
Clock
input
R
Mode input
Reset input
Reset output
R
N-ch
P-ch
P-ch
Pull-up control
A/D control
Digital output
Digital output
Analog input
Automotive input
Hysteresis input
Standby control
External
interrupt control
MB95130MB Series
DS07-12621-3E 13
(Continued)
Type Circuit Remarks
E • CMOS output
• CMOS input
• Hysteresis input
• Analog input
• Pull-up control available
• Automotive input
G • CMOS output
• CMOS input
• Hysteresis input
• Pull-up control available
• Automotive input
H • CMOS output
• Hysteresis input
• Pull-up control available
• Automotive input
K • CMOS output
• Hysteresis input
• Automotive input
R
N-ch
P-ch
P-ch
Pull-up control
Digital output
Digital output
Hysteresis input
Automotive input
CMOS input
A/D control
Standby control
External
interrupt control
Analog input
R
P-ch
N-ch
P-ch
Pull-up control
Standby
control
Digital output
Digital output
Hysteresis input
CMOS input
Automotive input
P-ch
P-ch
N-ch
R
Pull-up control
Standby
control
Digital output
Digital output
Hysteresis input
Automotive input
P-ch
N-ch
Standby
control
Digital output
Digital output
Hysteresis input
Automotive input
MB95130MB Series
14 DS07-12621-3E
■HANDLING DEVICES
• Preventing latch-up
Care must be taken to ensure that maximum voltage ratings are not exceeded when the devices are used.
Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- and high-withstand voltage pins or if voltage higher than the rating voltage is applied between
VCC pin and VSS pin.
When latch-up occurs, power supply current increases rapidly and might thermally damage elements.
Also, take care to prevent the analog power supply voltage (AVCC) and analog input voltage from exceeding the
digital power supply voltage (VCC) when the analog system power supply is turned on or off.
• Stable supply voltage
Supply voltage should be stabilized.
A sudden change in power supply voltage may cause a malfunction even within the guaranteed operating range
of the VCC power supply voltage.
For stabilization, in principle, keep the variation in VCC ripple (p-p value) in a commercial frequency range
(50 / 60 Hz) not to exceed 10% of the standard VCC value and suppress the voltage variation so that the transient
variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched.
• Precautions for use of external clock
Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up
from the sub clock mode or stop mode.
PIN CONNECTION
• Treatment of unused pins
Leaving unused input pins unconnected can cause abnormal operation or latch-up, leading to permanent
damage. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ.
Any unused input/output pins may be set to the output mode and left open, or set to the input mode and treated
the same as unused input pins. If there is any unused output pin, make it open.
• Treatment of power supply pins on A/D converter
Connect to be AVCC = VCC and AVSS = VSS even if the A/D converter is not in use.
Noise riding on the AVCC pin may cause accuracy degradation. So, connect approx. 0.1 μF ceramic capacitor
as a bypass capacitor between AVCC and AVSS pins in the vicinity of this device.
• Power Supply Pins
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However, all the pins must be connected to external power
supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe
signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect
the current supply source with the VCC and VSS pins of this device at the low impedance.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 μF between VCC and VSS pins
near this device.
• Mode pin (MOD)
Connect the mode pin directly to VCC or VSS pins.
To prevent the device unintentionally entering the test mode due to noise, lay out the printed circuit board so as
to minimize the distance from the mode pins to VCC or VSS pins and to provide a low-impedance connection.
MB95130MB Series
DS07-12621-3E 15
Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of VCC pin
must have a capacitance value higher than CS. For connection of smoothing capacitor CS, refer to the diagram
below.
• Analog power supply
Always set the same potential to AVCC pin and VCC pin. When VCC > AVCC, the current may flow through the
AN00 to AN07 pins.
• NC pins
Any pins marked “NC”(not connected) must be left open.
CS
C
• C Pin Connection Diagram
MB95130MB Series
16 DS07-12621-3E
■PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL PROGRAMMER
• Supported parallel programmers and adapters
The following table lists supported parallel programmers and adapters.
Note: : For information about applicable adapter models and parallel programmers, contact the following:
Flash Support Group, Inc. TEL: +81-53-428-8380
• Sector configuration
The following table shows sector-specific addresses for data access by CPU and by the parallel programmer.
• Programming method
1) Set the type code of the parallel programmer to “17237”.
2) Load program data to programmer addresses 18000H to 1FFFFH.
3) Write data with the parallel programmer.
• Programming method
1) Set the type code of the parallel programmer to “17237”.
2) Load program data to programmer addresses 1C000H to 1FFFFH.
3) Write data with the parallel programmer.
Package Applicable adapter model Parallel programmers
FPT-28P-M17 TEF110-95F136HSPF AF9708 (Since Rev 02.43E )
AF9709/B (Since Rev 02.43E )
FPT-30P-M02 TEF110-95F136MB
*: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer
programs data into Flash memory.
These programmer addresses are used for the parallel programmer to program or erase data in
Flash memory.
Flash memory CPU address Programmer address*
32 Kbytes
8000H18000H
FFFFH1FFFFH
• MB95F136MBS/F136NBS/F136MBW/F136NBW/F136JBS/F136JBW (32 Kbytes)
*: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer
programs data into Flash memory.
These programmer addresses are used for the parallel programmer to program or erase data in
Flash memory.
Flash memory CPU address Programmer address*
16 Kbytes
C000H1C000H
FFFFH1FFFFH
• MB95F134MBS/F134NBS/F134JBS/F134MBW/F134NBW/F134JBW (16 Kbytes)
MB95130MB Series
DS07-12621-3E 17
• Programming method
1) Set the type code of the parallel programmer to “17237”.
2) Load program data to programmer addresses 1E000H to 1FFFFH.
3) Write data with the parallel programmer.
*: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer
programs data into Flash memory.
These programmer addresses are used for the parallel programmer to program or erase data in
Flash memory.
Flash memory CPU address Programmer address*
8 Kbytes
E000H1E000H
FFFFH1FFFFH
• MB95F133MBS/F133NBS/F133JBS/F133MBW/F133NBW/F133JBW (8 Kbytes)
MB95130MB Series
18 DS07-12621-3E
■BLOCK DIAGRAM
F2MC-8FX CPU
UART/SIO
1 channel
Watch prescaler
ROM 32 Kbytes
RAM 1 Kbyte
LIN-UART
1 channel
8/16-bit PPG
2 channels
RST
X0/X1
PG2/(X1A)*
PG1/(X0A)*
P00/INT00 to P07/INT07 (P00/PPG00)
(P01/PPG01)
(P05/TO00)
(P06/TO01)
(P12/EC0)
PF0/PF1
(P02/SCK)
(P03/SOT)
(P04/SIN)
P00/AN00 to P07/AN07
P10/U10
P11/UO0
P12/UCK0
P14/PPG0
P15/P16
AVCC
AVSS
MOD, VCC, VSS, C
P13/TRG0/ADTG
*: Single clock product is a general-purpose port, and dual clock product is a sub clock oscillation pin.
Reset control
Clock control
Watch counter
External interrupt
8 channels
Port
Internal bus
Interrupt control
Wild register
8/16-bit
compound timer
1 channel
Port
Other pins
8/10-bit
A/D converter
8 channels
16-bit PPG
1 channel
MB95130MB Series
DS07-12621-3E 19
■CPU CORE
1. Memory Space
Memory space of the MB95130MB series is 64 Kbytes and consists of I/O area, data area, and program area.
The memory space includes special-purpose areas such as the general-purpose registers and vector table.
Memory map of the MB95130MB series is shown below.
Flash memory RAM Address #1 Address #2
MB95F133MBS/F133NBS/F133JBS 8 Kbytes 256 bytes 0180HE000H
MB95F133MBW/F133NBW/F133JBW
MB95F134MBS/F134NBS/F134JBS 16 Kbytes 512 bytes 0280HC000H
MB95F134MBW/F134NBW/F134JBW
MB95F136MBS/F136NBS/F136JBS 32 Kbytes 1 Kbyte 0480H8000H
MB95F136MBW/F136NBW/F136JBW
0000
H
0080
H
0100
H
0200
H
0F80
H
1000
H
FFFF
H
Extended I/O
Flash memory
60 Kbytes
RAM 3.75 Kbytes
MB95FV100D-103
I/O
0000
H
0080
H
0100
H
0200
H
0F80
H
1000
H
FFFF
H
Flash memory
MB95F133MBS/F133NBS/F133JBS
MB95F134MBS/F134NBS/F134JBS
MB95F136MBS/F136NBS/F136JBS
MB95F133MBW/F133NBW/F133JBW
MB95F134MBW/F134NBW/F134JBW
MB95F136MBW/F136NBW/F136JBW
I/O
RAMRAM 1 Kbyte
Extended I/O
MASK ROM
32 Kbytes
Extended I/O
0000
H
0080
H
0100
H
0200
H
0480
H
0F80
H
1000
H
FFFF
H
MB95136MB
I/O
8000
H
Address #1
Address #2
• Memory Map
RegisterRegister
Access
prohibited
Access
prohibited
Access
prohibited
Access
prohibited
Register
MB95130MB Series
20 DS07-12621-3E
2. Register
The MB95130MB series has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The dedicated registers are as include:
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer
(DP) and the lower 8 bits for use as a condition code register (CCR). (Refer to the diagram below.)
Program counter (PC) : A 16-bit register to indicate locations where instructions are stored.
Accumulator (A) : A 16-bit register for temporary storage of arithmetic operations. In the case of
an 8-bit data processing instruction, the lower 1-byte is used.
Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator.
In the case of an 8-bit data processing instruction, the lower 1-byte is used.
Index register (IX) : A 16-bit register for index modification
Extra pointer (EP) : A 16-bit pointer to point to a memory address.
Stack pointer (SP) : A 16-bit register to indicate a stack area.
Program status (PS) : A 16-bit register for storing a register bank pointer, a direct bank pointer, and
a condition code register
PC
ALAH
TLTH
IX
EP
SP
PS
16 bits
: Program counter
: Accumulator
: Temporary accumulator
: Index register
: Extra pointer
: Stack pointer
: Program status
Initial Value
FFFDH
0000H
0000H
0000H
0000H
0000H
0030H
PS
RP CCR
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
DP2 DP1 DP0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
R4 R3 R2 R1 R0 H I IL1 IL0 N Z VC
DP
• Structure of the program status
MB95130MB Series
DS07-12621-3E 21
The RP indicates the address of the register bank currently being used. The relationship between the content
of RP and the real address conforms to the conversion rule illustrated below:
The DP specifies the area for mapping instructions (16 different types of instructions such as MOV A and dir)
using direct addresses to 0080H to 00FFH.
The CCR consists of the bits indicating arithmetic operation results or transfer data content and the bits that
control CPU operations at interrupt.
Direct bank pointer (DP2 to DP0) Specified address area Mapping area
XXXB (no effect to mapping) 0000H to 007FH0000H to 007FH (without mapping)
000B (initial value)
0080H to 00FFH
0080H to 00FFH (without mapping)
001B0100H to 017FH
010B0180H to 01FFH
011B0200H to 027FH
100B0280H to 02FFH
101B0300H to 037FH
110B0380H to 03FFH
111B0400H to 047FH
H flag : Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.
Cleared to “0” otherwise. This flag is for decimal adjustment instructions.
I flag : Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”.
The flag is cleared to “0” when reset.
IL1, IL0 : Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level
is higher than the value indicated by these bits.
IL1 IL0 Interrupt level Priority
0 0 0 High
Low (no interruption)
01 1
10 2
11 3
N flag : Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the
bit is set to “0”.
Z flag : Set to “1” when an arithmetic operation results in “0”. Cleared to “0” otherwise.
V flag : Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0”
otherwise.
C flag : Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared
to “0” otherwise. Set to the shift-out value in the case of a shift instruction.
• Rule for Conversion of Actual Addresses in the General-purpose Register Area
Generated address
RP upper OP code lower
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0
A7 A6 A5 A4 A3 A2 A1 A0
A15 A14 A13 A12 A11 A10 A9 A8
MB95130MB Series
22 DS07-12621-3E
The following general-purpose registers are provided:
General-purpose registers: 8-bit data storage registers
The general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains 8
registers. Up to a total of 32 banks can be used on the MB95130MB series. The bank currently in use is specified
by the register bank pointer (RP), and the lower 3 bits of OP code indicates the general-purpose register 0 (R0)
to general-purpose register 7 (R7).
R0
R1
R2
R3
R4
R5
R6
R7
R0
This address = 0100
H
+ 8 × (RP)
R1
R2
R3
R4
R5
R6
R7
R0
R1
R2
R3
R4
R5
R6
R7
Address 100
H
107
H
1F8
H
1FF
H
Bank 31
Bank 0
8-bit
• Register Bank Configuration
32 banks
Memory area
32 banks (RAM area)
The number of banks is
limited by the usable RAM
capacitance.
MB95130MB Series
DS07-12621-3E 23
■I/O MAP
(Continued)
Address Register
abbreviation Register name R/W Initial value
0000HPDR0 Port 0 data register R/W 00000000B
0001HDDR0 Port 0 direction register R/W 00000000B
0002HPDR1 Port 1 data register R/W 00000000B
0003HDDR1 Port 1 direction register R/W 00000000B
0004H⎯ (Disabled) ⎯⎯
0005HWATR Oscillation stabilization wait time setting register R/W 11111111B
0006HPLLC PLL control register R/W 00000000B
0007HSYCC System clock control register R/W 1010X011B
0008HSTBC Standby control register R/W 00000000B
0009HRSRR Reset source register R/W XXXXXXXXB
000AHTBTC Timebase timer control register R/W 00000000B
000BHWPCR Watch prescaler control register R/W 00000000B
000CHWDTC Watchdog timer control register R/W 00000000B
000DH
to
0027H
⎯ (Disabled) ⎯⎯
0028HPDRF Port F data register R/W 00000000B
0029HDDRF Port F direction register R/W 00000000B
002AHPDRG Port G data register R/W 00000000B
002BHDDRG Port G direction register R/W 00000000B
002CHPUL0 Port 0 pull-up register R/W 00000000B
002DHPUL1 Port 1 pull-up register R/W 00000000B
002EH
to
0034H
⎯ (Disabled) ⎯⎯
0035HPULG Port G pull-up register R/W 00000000B
0036HT01CR1 8/16-bit compound timer 01 control status register 1 ch.0 R/W 00000000B
0037HT00CR1 8/16-bit compound timer 00 control status register 1 ch.0 R/W 00000000B
0038H,
0039H⎯ (Disabled) ⎯⎯
003AHPC01 8/16-bit PPG1 control register ch.0 R/W 00000000B
003BHPC00 8/16-bit PPG0 control register ch.0 R/W 00000000B
003CH
to
0041H
⎯ (Disabled) ⎯⎯
0042HPCNTH0 16-bit PPG control status register (Upper byte) ch.0 R/W 00000000B
0043HPCNTL0 16-bit PPG control status register (Lower byte) ch.0 R/W 00000000B
MB95130MB Series
24 DS07-12621-3E
(Continued)
Address Register
abbreviation Register name R/W Initial value
0044H
to
0047H
⎯ (Disabled) ⎯⎯
0048HEIC00 External interrupt circuit control register ch.0,ch.1 R/W 00000000B
0049HEIC10 External interrupt circuit control register ch.2,ch.3 R/W 00000000B
004AHEIC20 External interrupt circuit control register ch.4,ch.5 R/W 00000000B
004BHEIC30 External interrupt circuit control register ch.6,ch.7 R/W 00000000B
004CH
to
004FH
⎯ (Disabled) ⎯⎯
0050HSCR LIN-UART serial control register R/W 00000000B
0051HSMR LIN-UART serial mode register R/W 00000000B
0052HSSR LIN-UART serial status register R/W 00001000B
0053HRDR/TDR LIN-UART reception/transmission data register R/W 00000000B
0054HESCR LIN-UART extended status control register R/W 00000100B
0055HECCR LIN-UART extended communication control register R/W 000000XXB
0056HSMC10 UART/SIO serial mode control register 1 ch.0 R/W 00000000B
0057HSMC20 UART/SIO serial mode control register 2 ch.0 R/W 00100000B
0058HSSR0 UART/SIO serial status register ch.0 R/W 00000001B
0059HTDR0 UART/SIO serial output data register ch.0 R/W 00000000B
005AHRDR0 UART/SIO serial input data register ch.0 R 00000000B
005BH
to
006BH
⎯ (Disabled) ⎯⎯
006CHADC1 8/10-bit A/D converter control register 1 R/W 00000000B
006DHADC2 8/10-bit A/D converter control register 2 R/W 00000000B
006EHADDH 8/10-bit A/D converter data register (Upper byte) R/W 00000000B
006FHADDL 8/10-bit A/D converter data register (Lower byte) R/W 00000000B
0070HWCSR Watch counter status register R/W 00000000B
0071H⎯ (Disabled) ⎯⎯
0072HFSR Flash memory status register R/W 000X0000B
0073H⎯ (Disabled) ⎯⎯
0074H⎯ (Disabled) ⎯⎯
0075H⎯ (Disabled) ⎯⎯
0076HWREN Wild register address compare enable register R/W 00000000B
0077HWROR Wild register data test setting register R/W 00000000B
MB95130MB Series
DS07-12621-3E 25
(Continued)
Address Register
abbreviation Register name R/W Initial value
0078H⎯(Register bank pointer (RP)
Mirror of direct bank pointer (DP) ⎯⎯
0079HILR0 Interrupt level setting register 0 R/W 11111111B
007AHILR1 Interrupt level setting register 1 R/W 11111111B
007BHILR2 Interrupt level setting register 2 R/W 11111111B
007CHILR3 Interrupt level setting register 3 R/W 11111111B
007DHILR4 Interrupt level setting register 4 R/W 11111111B
007EHILR5 Interrupt level setting register 5 R/W 11111111B
007FH⎯ (Disabled) ⎯⎯
0F80HWRARH0 Wild register address setting register (Upper byte) ch.0 R/W 00000000B
0F81HWRARL0 Wild register address setting register (Lower byte) ch.0 R/W 00000000B
0F82HWRDR0 Wild register data setting register ch.0 R/W 00000000B
0F83HWRARH1 Wild register address setting register (Upper byte) ch.1 R/W 00000000B
0F84HWRARL1 Wild register address setting register (Lower byte) ch.1 R/W 00000000B
0F85HWRDR1 Wild register data setting register ch.1 R/W 00000000B
0F86HWRARH2 Wild register address setting register (Upper byte) ch.2 R/W 00000000B
0F87HWRARL2 Wild register address setting register (Lower byte) ch.2 R/W 00000000B
0F88HWRDR2 Wild register data setting register ch.2 R/W 00000000B
0F89H
to
0F91H
⎯ (Disabled) ⎯⎯
0F92HT01CR0 8/16-bit compound timer 01 control status register 0 ch.0 R/W 00000000B
0F93HT00CR0 8/16-bit compound timer 00 control status register 0 ch.0 R/W 00000000B
0F94HT01DR 8/16-bit compound timer 01 data register ch.0 R/W 00000000B
0F95HT00DR 8/16-bit compound timer 00 data register ch.0 R/W 00000000B
0F96HTMCR0 8/16-bit compound timer 00/01 timer mode control register
ch.0 R/W 00000000B
0F97H
to
0F9BH
⎯ (Disabled) ⎯⎯
0F9CHPPS01 8/16-bit PPG1 cycle setting buffer register ch.0 R/W 11111111B
0F9DHPPS00 8/16-bit PPG0 cycle setting buffer register ch.0 R/W 11111111B
0F9EHPDS01 8/16-bit PPG1 duty setting buffer register ch.0 R/W 11111111B
0F9FHPDS00 8/16-bit PPG0 duty setting buffer register ch.0 R/W 11111111B
0FA0H
to
0FA3H
⎯ (Disabled) ⎯⎯
MB95130MB Series
26 DS07-12621-3E
(Continued)
Address Register
abbreviation Register name R/W Initial value
0FA4HPPGS 8/16-bit PPG start register R/W 00000000B
0FA5HREVC 8/16-bit PPG output inversion register R/W 00000000B
0FA6H
to
0FA9H
⎯ (Disabled) ⎯⎯
0FAAHPDCRH0 16-bit PPG down counter register (Upper byte) ch.0 R 00000000B
0FABHPDCRL0 16-bit PPG down counter register (Lower byte) ch.0 R 00000000B
0FACHPCSRH0 16-bit PPG cycle setting buffer register (Upper byte) ch.0 R/W 11111111B
0FADHPCSRL0 16-bit PPG cycle setting buffer register (Lower byte) ch.0 R/W 11111111B
0FAEHPDUTH0 16-bit PPG duty setting buffer register (Upper byte) ch.0 R/W 11111111B
0FAFHPDUTL0 16-bit PPG duty setting buffer register (Lower byte) ch.0 R/W 11111111B
0FB0H
to
0FBBH
⎯ (Disabled) ⎯⎯
0FBCHBGR1 LIN-UART baud rate generator register 1 R/W 00000000B
0FBDHBGR0 LIN-UART baud rate generator register 0 R/W 00000000B
0FBEHPSSR0 UART/SIO dedicated baud rate generator
prescaler selection register ch.0 R/W 00000000B
0FBFHBRSR0 UART/SIO dedicated baud rate generator
baud rate setting register ch.0 R/W 00000000B
0FC0H
to
0FC2H
⎯ (Disabled) ⎯⎯
0FC3HAIDRL A/D input disable register (Lower byte) R/W 00000000B
0FC4H
to
0FE2H
⎯ (Disabled) ⎯⎯
0FE3HWCDR Watch counter data register R/W 00111111B
0FE4H
to
0FE6H
⎯ (Disabled) ⎯⎯
0FE7HILSR2 Input level select register 2 (option) R/W 00000000B
0FE8H,
0FE9H⎯ (Disabled) ⎯⎯
0FEAHCSVCR Clock supervisor control register R/W 00011100B
0FEBH
to
0FEDH
⎯ (Disabled) ⎯⎯
0FEEHILSR Input level select register R/W 00000000B
0FEFHWICR Interrupt pin control register R/W 01000000B
0FF0H
to
0FFFH
⎯ (Disabled) ⎯⎯
MB95130MB Series
DS07-12621-3E 27
• R/W access symbols
• Initial value symbols
Note: : Do not write to the “ (Disabled) ”. Reading the “ (Disabled) ” returns an undefined value.
R/W : Readable / Writable
R : Read only
W : Write only
0 : The initial value of this bit is “0”.
1 : The initial value of this bit is “1”.
X : The initial value of this bit is undefined.
MB95130MB Series
28 DS07-12621-3E
■INTERRUPT SOURCE TABLE
Interrupt source
Interrupt
request
number
Vector table address Bit name of
interrupt level
setting register
Same level
priority order
(at simultaneous
occurrence)
Upper Lower
External interrupt ch.0 IRQ0 FFFAHFFFBHL00 [1 : 0]
High
External interrupt ch.4
External interrupt ch.1 IRQ1 FFF8HFFF9HL01 [1 : 0]
External interrupt ch.5
External interrupt ch.2 IRQ2 FFF6HFFF7HL02 [1 : 0]
External interrupt ch.6
External interrupt ch.3 IRQ3 FFF4HFFF5HL03 [1 : 0]
External interrupt ch.7
UART/SIO ch.0 IRQ4 FFF2HFFF3HL04 [1 : 0]
8/16-bit compound timer ch.0 (Lower) IRQ5 FFF0HFFF1HL05 [1 : 0]
8/16-bit compound timer ch.0 (Higher) IRQ6 FFEEHFFEFHL06 [1 : 0]
LIN-UART (reception) IRQ7 FFECHFFEDHL07 [1 : 0]
LIN-UART (transmission) IRQ8 FFEAHFFEBHL08 [1 : 0]
(Unused) IRQ9 FFE8HFFE9HL09 [1 : 0]
(Unused) IRQ10 FFE6HFFE7HL10 [1 : 0]
(Unused) IRQ11 FFE4HFFE5HL11 [1 : 0]
8/16-bit PPG ch.0 (Upper) IRQ12 FFE2HFFE3HL12 [1 : 0]
8/16-bit PPG ch.0 (Lower) IRQ13 FFE0HFFE1HL13 [1 : 0]
(Unused) IRQ14 FFDEHFFDFHL14 [1 : 0]
16-bit PPG ch.0 IRQ15 FFDCHFFDDHL15 [1 : 0]
(Unused) IRQ16 FFDAHFFDBHL16 [1 : 0]
(Unused) IRQ17 FFD8HFFD9HL17 [1 : 0]
8/10-bit A/D converter IRQ18 FFD6HFFD7HL18 [1 : 0]
Timebase timer IRQ19 FFD4HFFD5HL19 [1 : 0]
Watch prescaler/Watch counter IRQ20 FFD2HFFD3HL20 [1 : 0]
(Unused) IRQ21 FFD0HFFD1HL21 [1 : 0]
(Unused) IRQ22 FFCEHFFCFHL22 [1 : 0]
Flash memory IRQ23 FFCCHFFCDHL23 [1 : 0] Low
MB95130MB Series
DS07-12621-3E 29
■ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(Continued)
Parameter Symbol Rating Unit Remarks
Min Max
Power supply voltage*1VCC
AVCC VSS − 0.3 VSS + 6.0 V *2
Input voltage*1VIVSS − 0.3 VSS + 6.0 V *3
Output voltage*1VOVSS − 0.3 VSS + 6.0 V *3
Maximum clamp current ICLAMP − 2.0 + 2.0 mA Applicable to pins*4
Total maximum clamp
current Σ|ICLAMP|⎯20 mA Applicable to pins*4
“L” level maximum
output current
IOL1 ⎯15 mA Other than PF0, PF1
IOL2 15 PF0, PF1
“L” level average
current
IOLAV1
⎯
4
mA
Other than PF0, PF1
Average output current =
operating current × operating ratio
(1 pin)
IOLAV2 12
PF0, PF1
Average output current =
operating current × operating ratio
(1 pin)
“L” level total maximum
output current ΣIOL ⎯100 mA
“L” level total average
output current ΣIOLAV ⎯50 mA
Total average output current =
operating current × operating ratio
(Total of pins)
“H” level maximum
output current
IOH1 ⎯ − 15 mA Other than PF0, PF1
IOH2 − 15 PF0, PF1
“H” level average
current
IOHAV1
⎯
− 4
mA
Other than PF0, PF1
Average output current =
operating current × operating ratio
(1 pin)
IOHAV2 − 8
PF0, PF1
Average output current =
operating current × operating ratio
(1 pin)
“H” level total maximum
output current ΣIOH ⎯ − 100 mA
“H” level total average
output current ΣIOHAV ⎯ − 50 mA
Total average output current =
operating current × operating ratio
(Total number of pins)
Power consumption Pd ⎯320 mW
Operating temperature TA − 40 + 105 °C
Storage temperature Tstg − 55 + 150 °C
MB95130MB Series
30 DS07-12621-3E
(Continued)
*1: These parameters are based on the condition that both AVSS and VSS are 0.0 V.
*2: Apply equal potential to AVCC and VCC.
*3: VI and VO should not exceed Vcc + 0.3 V. VI must not exceed the rating voltage. However, if the maximum
current to/from an input is limited by some means with external components, the ICLAMP rating supersedes
the VI rating.
*4: Applicable pins: P10 to P15, PF0, PF1 (Inapplicable pins: PG1, PG2)
• Use within recommended operating conditions.
• Use at DC voltage (current).
• +B signal is an input signal that exceeds VCC voltage. The + B signal should always be applied a limiting
resistance placed between the + B signal and the microcontroller.
• The value of the limiting resistance should be set so that when the + B signal is applied the input current
to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this affects
other devices.
• Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the + B input is applied during power-on, the power supply is provided from the pins and the
resulting power supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the + B input pin open.
•Note that analog system input/output pins other than the A/D input pins (LCD drive pins, etc.) cannot accept
+B signal input.
• Sample recommended circuits :
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
P-ch
N-ch
Vcc
R
• Input/Output Equivalent circuits
+ B input (0 V to 16 V)
Limiting
resistance
Protective diode
MB95130MB Series
DS07-12621-3E 31
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
*1: The value varies depending on the operating frequency.
*2: The value is 2.88 V when the low-voltage detection reset is used.
*3: Use ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of VCC pin
must have a capacitance value higher than CS. For connection of smoothing capacitor CS, refer to the diagram
below.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
Parameter Symbol Value Unit Remarks
Min Max
Power supply voltage VCC,
AVCC
2.42*25.5*1
VAt normal operation
2.3 5.5 Holds condition in stop mode
Smoothing capacitor CS0.1 1.0 μF*3
Operating temperature TA − 40 + 105 °C
C
C
S
• C pin connection diagram
MB95130MB Series
32 DS07-12621-3E
3. DC Characteristics
(VCC = = AVCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
(Continued)
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ Max
“H” level
input
voltage
VIHI
P04 (selectable
in SIN),
P10 (selectable
in UI0)
⎯0.7 VCC ⎯VCC + 0.3 V Hysteresis input
VIHSI
P00 to P07,
P10 to P16, PF0,
PF1,
PG1, PG2
⎯0.8 VCC ⎯VCC + 0.3 V Hysteresis input
VIHA
P00 to P07,
P10 to P16, PF0,
PF1,
PG1, PG2
⎯0.8 Vcc ⎯VCC + 0.3 V
Pin input at selecting
of Automotive
input level
VIHM RST, MOD
⎯0.7 VCC ⎯VCC + 0.3 V
CMOS input
(Flash memory
product)
⎯0.8 VCC ⎯VCC + 0.3 V
Hysteresis input
(MASK ROM
product)
“L” level
input
voltage
VIL
P04 (selectable
in SIN),
P10 (selectable
in UI0)
⎯VSS − 0.3 ⎯0.3 VCC V Hysteresis input
VILS
P00 to P07,
P10 to P16, PF0,
PF1,
PG1, PG2
⎯VSS − 0.3 ⎯0.2 VCC V Hysteresis input
VILA
P00 to P07,
P10 to P16, PF0,
PF1,
PG1, PG2
⎯VSS − 0.3 ⎯0.5 VCC V
Pin input at selecting
of Automotive
input level
VILM RST, MOD
⎯VSS − 0.3 ⎯0.3 VCC V
CMOS input
(Flash memory
product)
⎯VSS − 0.3 ⎯0.2 VCC V
Hysteresis input
(MASK ROM
product)
“H” level
output
voltage
VOH1 Output pins other
than PF0, PF1 IOH = − 4.0 mA VCC − 0.5 ⎯⎯ V
VOH2 PF0, PF1 IOH = − 8.0 mA VCC − 0.5 ⎯⎯ V
“L” level
output
voltage
VOL1
Output pins other
than PF0 to PF7,
RST*1
IOL = 4.0 mA ⎯⎯0.4 V
VOL2 PF0, PF1 IOL = 12 mA ⎯⎯0.4 V
MB95130MB Series
DS07-12621-3E 33
(VCC = AVCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
(Continued)
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ Max
Input
leakage
current
(Hi-Z out-
put leakage
current)
ILI
P00 to P07, P10
to P16, PF0,
PF1, PG1, PG2
0.0 V < VI < VCC − 5 ⎯ + 5 μA
When the
pull-up
prohibition
setting
Pull-up
resistor RPULL
P00 to P07, P10
to P16, PG1,
PG2
VI = 0.0 V 25 50 100 kΩ
When the
pull-up
permission
setting
Pull-down
resistor RMOD MOD VI = VCC 50 100 200 kΩMASK ROM
product only
Input
capacity CIN
Other than
AVCC, AVss, C,
Vcc and Vss
f = 1 MHz ⎯515pF
Power
supply
current*2
ICC
VCC
(External clock
operation)
VCC = 5.5 V
FCH = 20 MHz
FMP = 10 MHz
Main clock mode
(divided by 2)
⎯9.5 12.5 mA
Flash memory
product
(at other than
Flash memory
writing and
erasing)
⎯30 35 mA
Flash memory
product
(at Flash
memory writing
and erasing)
⎯7.2 9.5 mA MASK ROM
product
FCH = 32 MHz
FMP = 16 MHz
Main clock mode
(divided by 2)
⎯15.2 20.0 mA
Flash memory
product
(at other than
Flash memory
writing and
erasing)
⎯35.7 42.5 mA
Flash memory
product
(at Flash
memory writing
and erasing)
⎯11.6 15.2 mA MASK ROM
product
MB95130MB Series
34 DS07-12621-3E
(VCC = AVCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
(Continued)
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ Max
Power
supply
current*2
ICCS
VCC
(External clock
operation)
VCC = 5.5 V
FCH = 20 MHz
FMP = 10 MHz
Main Sleep mode
(divided by 2)
⎯4.5 7.5 mA
FCH = 32 MHz
FMP = 16 MHz
Main Sleep mode
(divided by 2)
⎯7.2 12.0 mA
ICCL
VCC = 5.5 V
FCL = 32 kHz
FMPL = 16 kHz
Sub clock mode
(divided by 2) ,
TA = + 25 °C
⎯45 100 μADual clock
product only
ICCLS
VCC = 5.5 V
FCL = 32 kHz
FMPL = 16 kHz
Sub sleep mode
(divided by 2) ,
TA = + 25 °C
⎯10 81 μADual clock
product only
ICCT
VCC = 5.5 V
FCL = 32 kHz
Watch mode
Main stop mode
TA = + 25 °C
⎯4.6 27 μADual clock
product only
ICCMPLL
VCC = 5.5 V
FCH = 4 MHz
FMP = 10 MHz
Main PLL mode
(multiplied by 2.5)
⎯9.3 12.5 mA Flash memory
product
⎯79.5mA
MASK ROM
product
FCH = 6.4 MHz
FMP = 16 MHz
Main PLL mode
(multiplied by 2.5)
⎯14.9 20.0 mA Flash memory
product
⎯11.2 15.2 mA MASK ROM
product
ICCSPLL
VCC = 5.5 V
FCL = 32 kHz
FMPL = 128 kHz
Sub PLL mode
(multiplied by 4) ,
TA = + 25 °C
⎯160 400 μADual clock
product only
MB95130MB Series
DS07-12621-3E 35
(Continued)
(VCC = AVCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
*1: Product without clock supervisor only
*2: •The power supply current is specified by the external clock. When the low-voltage detection and clock
supervisor options are selected, the consumption current values of both the low-voltage detection circuit (ILV D )
and the built-in CR oscillator (ICSV) must also be added to the power supply current value.
•Refer to “4. AC Characteristics: (1) Clock Timing” for FCH and FCL.
•Refer to “4. AC Characteristics: (2) Source Clock / Machine Clock” for FMP and FMPL.
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ Max
Power
supply
current*2
ICTS VCC
(External clock
operation)
VCC = 5.5 V
FCH = 10 MHz
Timebase timer
mode
TA = + 25 °C
⎯0.15 1.1 mA
ICCH
VCC = 5.5 V
Sub stop mode
TA = + 25 °C
⎯3.5 20.0 μA
Main stop mode
for single clock
product
IA
AVcc
VCC = 5.5 V
FCH = 16 MHz
When A/D conver-
sion is in operation
⎯2.4 4.7 mA
IAH
VCC = 5.5 V
FCH = 16 MHz
When A/D conver-
sion is stopped
TA = + 25 °C
⎯15μA
MB95130MB Series
36 DS07-12621-3E
4. AC Characteristics
(1) Clock Timing
(VCC = 2.42 V to 5.0 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Parameter Sym-
bol Pin name Condi-
tion
Value Unit Remarks
Min Typ Max
Clock frequency
FCH X0, X1
⎯
1.00 ⎯16.25 MHz When using main
oscillation circuit
1.00 ⎯32.50 MHz When using external clock
3.00 ⎯10.00 MHz Main PLL multiplied by 1
3.00 ⎯8.13 MHz Main PLL multiplied by 2
3.00 ⎯6.50 MHz Main PLL multiplied by 2.5
3.00 ⎯4.06 MHz Main PLL multiplied by 4
FCL X0A, X1A
⎯32.768 ⎯kHz When using sub
oscillation circuit
⎯32.768 ⎯kHz When using sub PLL
VCC = 2.3 V to 3.6 V
Clock cycle time
tHCYL X0, X1 61.5 ⎯1000 ns When using main
oscillation circuit
30.8 ⎯1000 ns When using external clock
tLCYL X0A, X1A ⎯30.5 ⎯ μsWhen using sub
oscillation circuit
Input clock pulse width
tWH1
tWL1 X0 61.5 ⎯⎯ns When using external clock
duty ratio is about 30% to
70%.
tWH2
tWL2 X0A ⎯15.2 ⎯ μs
Input clock rise/fall time tCR
tCF X0, X0A ⎯⎯ 5 ns When using external clock
MB95130MB Series
DS07-12621-3E 37
tHCYL
tWH1
tCR
0.2 VCC
X0 0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
tCF
tWL1
• Input wave form for using external clock (main clock)
X0 X1
F
CH
X0
F
CH
X1
C1 C2
• Figure of Main Clock Input Port External Connection
When using crystal or
ceramic oscillator When using external clock
Open
Microcontroller Microcontroller
t
LCYL
t
WH2
t
CR
0.2 V
CC
X0A 0.8 V
CC
0.8 V
CC
0.2 V
CC
0.2 V
CC
t
CF
t
WL2
• Input wave form for using external clock (sub clock)
X0A X1A
F
CL
X0A
F
CL
X1A
C1 C2
• Figure of Sub clock Input Port External Connection
When using crystal or
ceramic oscillator When using external clock
Open
Microcontroller Microcontroller
MB95130MB Series
38 DS07-12621-3E
(2) Source Clock / Machine Clock
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This
source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it
becomes the machine clock. Further, the source clock can be selected as follows.
•Main clock divided by 2
•PLL multiplication of main clock (select from 1, 2, 2.5, 4 multiplication)
•Sub clock divided by 2
•PLL multiplication of sub clock (select from 2, 3, 4 multiplication)
*2 : Operation clock of the microcontroller. Machine clock can be selected as follows.
•Source clock (no division)
•Source clock divided by 4
•Source clock divided by 8
•Source clock divided by 16
Parameter Symbol Pin
name
Value Unit Remarks
Min Typ Max
Source clock
cycle time*1
(Clock before
setting division)
tSCLK ⎯
61.5 ⎯2000 ns
When using main clock
Min : FCH = 8.125 MHz, PLL multiplied by 2
Max : FCH = 1 MHz, divided by 2
7.6 ⎯61.0 μs
When using sub clock
Min : FCL = 32 kHz, PLL multiplied by 4
Max : FCL = 32 kHz, divided by 2
Source clock
frequency
FSP ⎯0.50 ⎯16.25 MHz When using main clock
FSPL ⎯16.384 ⎯131.072 kHz When using sub clock
Machine clock
cycle time*2
(Minimum
instruction
execution time)
tMCLK ⎯
61.5 ⎯32000 ns
When using main clock
Min : FSP = 16.25 MHz, no division
Max : FSP = 0.5 MHz, divided by 16
7.6 ⎯976.5 μs
When using sub clock
Min : FSPL = 131 kHz, no division
Max : FSPL = 16 kHz, divided by 16
Machine clock
frequency
FMP ⎯0.031 ⎯16.250 MHz When using main clock
FMPL 1.024 ⎯131.072 kHz When using sub clock
MB95130MB Series
DS07-12621-3E 39
F
CH
(main oscillation)
F
CL
(sub oscillation)
Divided by 2
Main PLL
× 1
× 2
× 2.5
× 4
Divided by 2
Sub PLL
× 2
× 3
× 4
SCLK
(source clock)
Clock mode select bit
(SYCC: SCS1, SCS0)
MCLK
(machine clock)
Division
circuit
× 1
× 1/4
× 1/8
× 1/16
• Outline of clock generation block
MB95130MB Series
40 DS07-12621-3E
• Operating voltage - Operating frequency (When TA = − 40 °C to + 105 °C)
• MB95136MB/F133MBS/F133NBS/F133JBS/F134MBS/F134NBS/F134JBS/F136MBS/F136NBS/F136JBS/
MB95F133MBW/F133NBW/F133JBW/F134MBW/F134NBW/F134JBW/F136MBW/F136NBW/
MB95F136JBW
• Operating voltage - Operating frequency (When TA = + 5 °C to + 35 °C)
• MB95FV100D-103
16.25 MHz0.5 MHz
2.42
3 MHz
5.5
131.072 kHz16.384 kHz
2.42
32 kHz
5.5
10 MHz
3.5
Source clock frequency (FSPL)
Operating voltage (V)
Sub PLL, sub clock mode and
watch mode operation guarantee range
PLL operation guarantee range
Source clock frequency (FSP)
Operating voltage (V)
PLL operation guarantee range
Main clock operation guarantee range
Main clock mode and main PLL mode
operation guarantee range
2.7
5.5
131.072 kHz16.384 kHz
2.7
32 kHz
5.5
16.25 MHz0.5 MHz 3 MHz 10 MHz
3.5
Source clock frequency (FSPL)
Operating voltage (V)
Sub PLL, sub clock mode and
watch mode operation guarantee range
PLL operation guarantee range
Source clock frequency (FSP)
Operating voltage (V)
PLL operation guarantee range
Main clock operation guarantee range
Main clock mode and main PLL mode
operation guarantee range
MB95130MB Series
DS07-12621-3E 41
• Main PLL operation frequency
[MHz]
16.25
16
15
12
10
7.5
6
5
3
0 3 4
4.062 5 6.4
6.5
8 8.125 10 [MHz]
Main oscillation (FCH)
Source clock frequency (FSP)
× 2.5
× 2 × 1
× 4
MB95130MB Series
42 DS07-12621-3E
(3) External Reset
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
*1 : Refer to “ (2) Source Clock / Machine Clock” for tMCLK.
*2 : Oscillation start time of oscillator is the time that the amplitude reaches 90 %. In the crystal oscillator, the
oscillation time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between
hundreds of μs and several ms. In the external clock, the oscillation time is 0 ms.
Parameter Symbol Pin
name
Value Unit Remarks
Min Max
RST “L” level
pulse width tRSTL RST
2 tMCLK*1⎯ns At normal operation
Oscillation time of oscillator*2
+ 100 ⎯μsAt stop mode, sub clock mode,
sub sleep mode & watch mode
100 ⎯μs At timebase timer mode
tRSTL
0.2 VCC
RST
0.2 VCC
tRSTL
0.2 VCC 0.2 VCC
100 μs
RST
X0
• At normal operation
• At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on
Internal
operating
clock
Internal reset
90% of
amplitude
Oscillation time
of oscillator Oscillation stabilization wait time
Execute instruction
MB95130MB Series
DS07-12621-3E 43
(4) Power-on Reset
(AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Note: Complete the power-on process within the selected oscillation stabilization wait time.
Note: Sudden change of power supply voltage may activate the power-on reset function. When changing power
supply voltages during operation, set the slope of rising within 30 mV/ms as shown below.
Parameter Symbol Pin
name Condition Value Unit Remarks
Min Max
Power supply rising time tR
VCC
⎯⎯50 ms
Power supply cutoff time tOFF ⎯1⎯ms Waiting time until
power-on
0.2 V0.2 V
tOFFtR
2.5 V
0.2 V
VCC
V
CC
2.3 V
V
SS
Hold Condition in stop mode
Limiting the slope of rising within
30 mV/ms is recommended.
MB95130MB Series
44 DS07-12621-3E
(5) Peripheral Input Timing
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
* : Refer to “ (2) Source Clock / Machine Clock” for tMCLK.
Parameter Symbol Pin name Value Unit
Min Max
Peripheral input “H” pulse tILIH INT00 to INT07,
EC0, TRG0/ADTG
2 tMCLK*⎯ns
Peripheral input “L” pulse tIHIL 2 tMCLK*⎯ns
tILIH
INT00 to INT07,
EC0,TRG0/ADTG
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
tIHIL
MB95130MB Series
DS07-12621-3E 45
(6) UART/SIO Serial I/O Timing
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
* : Refer to “ (2) Source Clock / Machine Clock” for tMCLK.
Parameter Symbol Pin name Condition Value Unit
Min Max
Serial clock cycle time tSCYC UCK0
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
4 tMCLK*⎯ns
UCK ↓ → UO time tSLOV UCK0, UO0 − 190 +190 ns
Valid UI → UCK ↑tIVSH UCK0, UI0 2 tMCLK*⎯ns
UCK ↑→ valid UI hold time tSHIX UCK0, UI0 2 tMCLK*⎯ns
Serial clock “H” pulse width tSHSL UCK0
External clock
operation output pin :
CL = 80 pF + 1 TTL.
4 tMCLK*⎯ns
Serial clock “L” pulse width tSLSH UCK0 4 tMCLK*⎯ns
UCK ↓ → UO time tSLOV UCK0, UO0 ⎯190 ns
Valid UI → UCK ↑tIVSH UCK0, UI0 2 tMCLK*⎯ns
UCK ↑→ valid UI hold time tSHIX UCK0, UI0 2 tMCLK*⎯ns
tSCYC
tIVSH
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tSHIX
tSLOV
0.8 V
2.4 V
0.8 V
2.4 V
UCK0
UO0
UI0
0.8 V
tSLSH
tIVSH tSHIX
tSLOV
0.2 VCC 0.2 VCC
0.8 VCC 0.8 VCC
tSHSL
2.4 V
UCK0
UO0
UI0
0.8 V
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
• Internal shift clock mode
• External shift clock mode
MB95130MB Series
46 DS07-12621-3E
(7) LIN-UART Timing
Sampling at the rising edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0)
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock / Machine Clock” for tMCLK.
Parameter Sym-
bol Pin name Condition Value Unit
Min Max
Serial clock cycle time tSCYC SCK
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
5 tMCLK*3⎯ns
SCK ↓ → SOT delay time tSLOVI SCK, SOT − 95 +95 ns
Valid SIN → SCK ↑tIVSHI SCK, SIN tMCLK*3 + 190 ⎯ns
SCK ↑ → valid SIN hold time tSHIXI SCK, SIN 0 ⎯ns
Serial clock “L” pulse width tSLSH SCK
External clock
operation output pin :
CL = 80 pF + 1 TTL.
3 tMCLK*3 − tR⎯ns
Serial clock “H” pulse width tSHSL SCK tMCLK*3 + 95 ⎯ns
SCK ↓ → SOT delay time tSLOVE SCK, SOT ⎯2 tMCLK*3 + 95 ns
Valid SIN → SCK ↑tIVSHE SCK, SIN 190 ⎯ns
SCK ↑ → valid SIN hold time tSHIXE SCK, SIN tMCLK*3 + 95 ⎯ns
SCK fall time tFSCK ⎯10 ns
SCK rise time tRSCK ⎯10 ns
MB95130MB Series
DS07-12621-3E 47
0.8 V 0.8 V
2.4 V
tSLOVI
tIVSHI tSHIXI
2.4 V
0.8 V
SCK
SOT
SIN
tSCYC
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tSLOVE
tIVSHE tSHIXE
2.4 V
0.8 V
tR
tF
SCK
SOT
SIN
tSLSH tSHSL
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
0.8 VCC 0.8 VCC0.8 VCC
0.2 VCC 0.2 VCC
• Internal shift clock mode
• External shift clock mode
MB95130MB Series
48 DS07-12621-3E
Sampling at the falling edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0)
(VCC = 5.0 V± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “(2) Source Clock / Machine Clock” for tMCLK.
Parameter Sym-
bol Pin name Condition Value Unit
Min Max
Serial clock cycle time tSCYC SCK
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
5 tMCLK*3⎯ns
SCK ↑ → SOT delay time tSHOVI SCK, SOT − 95 +95 ns
Valid SIN → SCK ↓tIVSLI SCK, SIN tMCLK*3 + 190 ⎯ns
SCK ↓ → valid SIN hold time tSLIXI SCK, SIN 0 ⎯ns
Serial clock “H” pulse width tSHSL SCK
External clock
operation output pin :
CL = 80 pF + 1 TTL.
3 tMCLK*3 − tR⎯ns
Serial clock “L” pulse width tSLSH SCK tMCLK*3 + 95 ⎯ns
SCK ↑ → SOT delay time tSHOVE SCK, SOT ⎯2 tMCLK*3 + 95 ns
Valid SIN → SCK ↓tIVSLE SCK, SIN 190 ⎯ns
SCK ↓ → valid SIN hold time tSLIXE SCK, SIN tMCLK*3 + 95 ⎯ns
SCK fall time tFSCK ⎯10 ns
SCK rise time tRSCK ⎯10 ns
MB95130MB Series
DS07-12621-3E 49
0.8 V
2.4 V 2.4 V
tSHOVI
tIVSLI tSLIXI
2.4 V
0.8 V
SCK
SOT
SIN
tSCYC
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
• Internal shift clock mode
• External shift clock mode
0.2 VCC 0.2 VCC
tSHOVE
tIVSLE tSLIXE
2.4 V
0.8 V
tF
tR
SCK
SOT
SIN
tSHSL tSLSH
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
0.8 VCC 0.8 VCC
MB95130MB Series
50 DS07-12621-3E
Sampling at the rising edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1)
(VCC = 5.0 V± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock / Machine Clock” for tMCLK.
Parameter Sym-
bol Pin name Condition Value Unit
Min Max
Serial clock cycle time tSCYC SCK
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
5 tMCLK*3⎯ns
SCK ↑ → SOT delay time tSHOVI SCK, SOT − 95 +95 ns
Valid SIN → SCK ↓tIVSLI SCK, SIN tMCLK*3 + 190 ⎯ns
SCK ↓ → valid SIN hold
time tSLIXI SCK, SIN 0 ⎯ns
SOT → SCK ↓ delay time tSOVLI SCK, SOT ⎯4 tMCLK*3ns
SCK
SOT
SIN
2.4 V
0.8 V
0.8 V
t
SHOVI
2.4 V
0.8 V
0.8 V
CC
0.2 V
CC
0.8 V
CC
0.2 V
CC
2.4 V
0.8 V
t
SCYC
t
SOVLI
t
IVSLI
t
SLIXI
MB95130MB Series
DS07-12621-3E 51
Sampling at the falling edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1)
(VCC = 5.0 V± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock / Machine Clock” for tMCLK.
Parameter Sym-
bol Pin name Condition Value Unit
Min Max
Serial clock cycle time tSCYC SCK
Internal clock
operating output pin :
CL = 80 pF + 1 TTL.
5 tMCLK*3⎯ns
SCK ↓ → SOT delay time tSLOVI SCK, SOT − 95 +95 ns
Valid SIN → SCK ↑tIVSHI SCK, SIN tMCLK*3 + 190 ⎯ns
SCK ↑ → valid SIN hold time tSHIXI SCK, SIN 0 ⎯ns
SOT → SCK ↑ delay time tSOVHI SCK, SOT ⎯4 tMCLK*3ns
SCK
SOT
SIN
2.4 V 2.4 V
0.8 V
tSLOVI
2.4 V
0.8 V
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
2.4 V
0.8 V
tSCYC
tSOVHI
tIVSHI tSHIXI
MB95130MB Series
52 DS07-12621-3E
(8) Low voltage Detection
(AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Parameter Sym-
bol
Value Unit Remarks
Min Typ Max
Release voltage VDL+2.52 2.70 2.88 V At power-supply rise
Detection voltage VDL−2.42 2.60 2.78 V At power-supply fall
Hysteresis width VHYS 70 100 ⎯mV
Power-supply start voltage Voff ⎯⎯2.3 V
Power-supply end voltage Von 4.9 ⎯⎯V
Power-supply voltage
change time
(at power supply rise)
tr
0.3 ⎯⎯μsSlope of power supply that reset re-
lease signal generates
⎯3000 ⎯μs
Slope of power supply that reset re-
lease signal generates within rating
(VDL+)
Power-supply voltage
change time
(at power supply fall)
tf
300 ⎯⎯μsSlope of power supply that reset
detection signal generates
⎯300 ⎯μs
Slope of power supply that reset
detection signal generates within rat-
ing (VDL-)
Reset release delay time td1 ⎯⎯400 μs
Reset detection delay time td2 ⎯⎯30 μs
Consumption current ILVD ⎯38 50 μAConsumption current of low voltage
detection circuit only
MB95130MB Series
DS07-12621-3E 53
VHYS
td2 td1
tr
tf
VCC
VCC
Von
Voff
VDL+
VDL-
Time
Internal reset
signal
Time
MB95130MB Series
54 DS07-12621-3E
(9) Clock Supervisor Clock
(VCC = AVCC = 5 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Parameter Sym-
bol
Value Unit Remarks
Min Typ Max
Oscillation frequency fOUT 50 100 200 kHz
Oscillation start time twk ⎯⎯10 μs
Current consumption ICSV ⎯20 36 μA
Current consumption of built-in
CR oscillator at 100 kHz
oscillation
MB95130MB Series
DS07-12621-3E 55
5. A/D Converter
(1) A/D Converter Electrical Characteristics
(AVCC = VCC = 4.0 V to 5.5 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Parameter Symbol Value Unit Remarks
Min Typ Max
Resolution
⎯
⎯⎯10 bit
Total error − 3.0 ⎯ + 3.0 LSB
Linearity error − 2.5 ⎯ + 2.5 LSB
Differential linear
error − 1.9 ⎯ + 1.9 LSB
Zero transition
voltage VOT AVSS − 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB V
Full-scale transition
voltage VFST AVCC − 4.5 LSB AVCC − 1.5 LSB AVCC + 0.5 LSB V
Compare time ⎯0.9 ⎯16500 μs 4.5 V ≤ AVCC ≤ 5.5 V
1.8 ⎯16500 μs 4.0 V ≤ AVCC < 4.5 V
Sampling time ⎯
0.6 ⎯∞μs
4.5 V ≤ AVcc ≤ 5.5 V,
At external impedance
< at 5.4 kΩ
1.2 ⎯∞μs
4.0 V ≤ AVcc ≤ 4.5 V,
At external impedance
< at 2.4 kΩ
Analog input current IAIN − 0.3 ⎯ + 0.3 μA
Analog input voltage VAIN AVSS ⎯AVCC V
MB95130MB Series
56 DS07-12621-3E
(2) Notes on Using A/D Converter
• External impedance of analog input and its sampling time
• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision. Therefore to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the register value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value.
Also, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 μF to the analog input pin.
• Errors
As |AVCC − AVSS| becomes smaller, values of relative errors grow larger.
R
C
Analog input
Note : The values are reference values.
• Analog input equivalent circuit
RC
4.5 V ≤ AVCC ≤ 5.5 V 2.0 kΩ (Max) 16 pF (Max)
4.0 V ≤ AVCC < 4.5 V 8.2 kΩ (Max) 16 pF (Max)
Comparator
During sampling : ON
20
18
16
14
12
10
8
6
4
2
0
02134
100
90
80
70
60
50
40
30
20
10
0
0 2 4 6 8 10 12 14
(External impedance = at 0 kΩ to 100 kΩ)(External impedance = at 0 kΩ to 20 kΩ)
Minimum sampling time [μs]
External impedance [kΩ]
Minimum sampling time [μs]
External impedance [kΩ]
AVCC ≥ 4.0 V
• The relationship between external impedance and minimum sampling time
AVCC ≥ 4.5 V AVCC ≥ 4.5 V
AVCC ≥ 4.0 V
MB95130MB Series
DS07-12621-3E 57
(3) Definition of A/D Converter Terms
• Resolution
The level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit : LSB)
The deviation between the value along a straight line connecting the zero transition point
(“00 0000 0000” ← → “00 0000 0001”) of a device and the full-scale transition point
(“11 1111 1111” ← → “11 1111 1110”) compared with the actual conversion values obtained.
• Differential linear error (Unit : LSB)
Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
• Total error (unit: LSB)
Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error,
linearity error, quantum error, and noise.
(Continued)
V
FST
1.5 LSB
3FF
H
3FE
H
3FD
H
004
H
003
H
002
H
001
H
3FF
H
3FE
H
3FD
H
004
H
003
H
002
H
001
H
1 LSB
0.5 LSB
V
OT
AV
SS
AV
CC
AV
SS
V
NT
AV
CC
{1 LSB × (N − 1) + 0.5 LSB}
1 LSB =AVCC − AVSS
1024 (V) Total error of
digital output N
VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB
Ideal I/O characteristics Total error
Digital output
Analog input Analog input
Digital output
[LSB]
Actual conversion
characteristic
Actual conversion
characteristic
Ideal characteristics
N : A/D converter digital output value
VNT : Voltage at which digital output transits from (N-1) H to NH.
=
MB95130MB Series
58 DS07-12621-3E
(Continued)
V (N + 1) T − VNT
1 LSB
AVSS AVCC
AVSS AVCC AVSS AVCC
VNT
AVSS AVCC
001H
002H
003H
004H
3FCH
3FDH
3FEH
3FFH
001H
002H
003H
004H
3FDH
3FEH
3FFH
(N-2)H
(N-1)H
NH
(N+1)H
{1 LSB × N + VOT}
VNT
V (N+1)T
Full-scale transition error
Digital output
Actual conversion
characteristics
Actual conversion
characteristics
Ideal
characteristics
Analog input
VFST
(Actual value)
Zero transition error
Digital output
Actual conversion
characteristics
Actual conversion
characteristics
Analog input
VOT (Actual value)
− 1
Differential linear error
of digital output N
Linear error of
digital output N
VNT − {1 LSB × N + VOT}
1 LSB
Linearity error
Digital output
Actual conversion
characteristics
Actual conversion
characteristics
Analog input
Ideal characteristics
Differential linear error
Digital output
Actual conversion
characteristics
Actual conversion
characteristics
Analog input
Ideal characteristics
VFST
(Actual value)
VOT (Actual value)
N : A/D converter digital output value
VNT : Voltage at which digital output transits from (N - 1)H to NH.
VOT (Ideal value) = AVSS + 0.5 LSB [V]
VFST (Ideal value) = AVCC − 1.5 LSB [V]
Ideal
characteristics
=
=
MB95130MB Series
DS07-12621-3E 59
6. Flash Memory Program/Erase Characteristics
*1 : TA = + 25 °C, VCC = 5.0 V, 10000 cycles
*2 : TA = + 85 °C, VCC = 4.5 V, 10000 cycles
*3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at +85 °C) .
Parameter Value Unit Remarks
Min Typ Max
Chip erase time ⎯1.0*115.0*2s Excludes 00H programming prior erasure.
Byte programming time ⎯32 3600 μs Excludes system-level overhead.
Erase/program cycle 10000 ⎯⎯cycle
Power supply voltage at erase/
program 4.5 ⎯5.5 V
Flash memory data retention
time 20*3⎯⎯year Average TA = +85 °C
MB95130MB Series
60 DS07-12621-3E
■MASK OPTION
*: Refer to table below about clock mode select, low voltage detection reset, clock supervisor select and reset
output.
No.
Part number MB95136MB
MB95F133MBS
MB95F133NBS
MB95F133JBS
MB95F134MBS
MB95F134NBS
MB95F134JBS
MB95F136MBS
MB95F136NBS
MB95F136JBS
MB95F133MBW
MB95F133NBW
MB95F133JBW
MB95F134MBW
MB95F134NBW
MB95F134JBW
MB95F136MBW
MB95F136NBW
MB95F136JBW
MB95FV100D-103
Specifying procedure
Specify when
ordering
MASK
Setting
disabled
Setting
disabled
Setting
disabled
1
Clock mode select
• Single-system clock mode
• Dual-system clock mode
selectable Single-system
clock mode
Dual-system clock
mode
Changing by the
switch on MCU board
2
Low voltage detection reset*
• With low voltage detection
reset
• Without low voltage
detection reset
Specify when
ordering
MASK
Specified by
part number
Specified by
part number
Change by the switch
on MCU board
3
Clock supervisor*
• With clock supervisor
• Without clock supervisor
Specify when
ordering
MASK
Specified by part
number
Specified by part
number
Change by the switch
on MCU board
4
Reset output*
• With reset output
• Without reset output
Not selectable Not selectable Not selectable
MCU board switch set
as following ;
• With supervisor :
Without reset output
•Without supervisor :
With reset output
5Oscillation stabilization
wait time
Fixed to
oscillation
stabilization
wait time of
(214 − 2) /FCH
Fixed to oscillation
stabilization wait
time of
(214 − 2) /FCH
Fixed to oscillation
stabilization wait
time of
(214 − 2) /FCH
Fixed to oscillation
stabilization wait time
of (214 − 2) /FCH
MB95130MB Series
DS07-12621-3E 61
*: If the clock supervisor is selected, reset output is always disabled.
Part number Clock mode select Low-voltage
detection reset Clock supervisor Reset output*
MB95136MB
Single - system
No No Yes
Yes No Yes
Yes Yes No
Dual - system
No No Yes
Yes No Yes
Yes Yes No
MB95F133MBS
Single - system
No No Yes
MB95F133NBS Yes No Yes
MB95F133JBS Yes Yes No
MB95F134MBS No No Yes
MB95F134NBS Yes No Yes
MB95F134JBS Yes Yes No
MB95F136MBS No No Yes
MB95F136NBS Yes No Yes
MB95F136JBS Yes Yes No
MB95F133MBW
Dual - system
No No Yes
MB95F133NBW Yes No Yes
MB95F133JBW Yes Yes No
MB95F134MBW No No Yes
MB95F134NBW Yes No Yes
MB95F134JBW Yes Yes No
MB95F136MBW No No Yes
MB95F136NBW Yes No Yes
MB95F136JBW Yes Yes No
MB95FV100D-103
Single - system
No No Yes
Yes No Yes
Yes Yes No
Dual - system
No No Yes
Yes No Yes
Yes Yes No
MB95130MB Series
62 DS07-12621-3E
■ORDERING INFORMATION
Part number Package
MB95136MBPF
MB95F133MBSPF
MB95F133NBSPF
MB95F133JBSPF
MB95F134MBSPF
MB95F134NBSPF
MB95F134JBSPF
MB95F136MBSPF
MB95F136NBSPF
MB95F136JBSPF
MB95F133MBWPF
MB95F133NBWPF
MB95F133JBWPF
MB95F134MBWPF
MB95F134NBWPF
MB95F134JBWPF
MB95F136MBWPF
MB95F136NBWPF
MB95F136JBWPF
28-pin plastic SOP
(FPT-28P-M17)
MB95136MBPFV
MB95F133MBSPFV
MB95F133NBSPFV
MB95F133JBSPFV
MB95F134MBSPFV
MB95F134NBSPFV
MB95F134JBSPFV
MB95F136MBSPFV
MB95F136NBSPFV
MB95F136JBSPFV
MB95F133MBWPFV
MB95F133NBWPFV
MB95F133JBWPFV
MB95F134MBWPFV
MB95F134NBWPFV
MB95F134JBWPFV
MB95F136MBWPFV
MB95F136NBWPFV
MB95F136JBWPFV
30-pin plastic SSOP
(FPT-30P-M02)
MB2146-303A-E
(MB95FV100D-103PBT)
MCU board
()
224-pin plastic PFBGA
(BGA-224P-M08)
MB95130MB Series
DS07-12621-3E 63
■PACKAGE DIMENSION
(Continued)
28-pin plastic SOP Lead pitch 1.27 mm
Package width
×
package length
8.6 × 17.75 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 2.80 mm MAX
Weight 0.82 g
Code
(Reference) P-SOP28-8.6×17.75-1.27
28-pin plastic SOP
(FPT-28P-M17)
(FPT-28P-M17)
C
2002-2010 FUJITSUSEMICONDUCTOR LIMITED F28048S-c-3-6
.699 –.008
+.010
–0.20
+0.25
17.75
1
1.27(.050)
8.60±0.20
(.339±.008)
11.80±0.30
(.465±.012)
M
0.13(.005)
14
15
28
0.10(.004)
0.47±0.08
(.019±.003)
INDEX
"A"
–0.04
+0.03
0.17
.007 +.001
–.002
0~8°
0.25(.010)
Details of "A" part
(Mounting height)
2.65±0.15
(.104±.006)
0.20±0.15
(.008±.006)
(Stand off)
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
*
1
*
2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1) *1 : These dimensions include resin protrusion.
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3)Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
MB95130MB Series
64 DS07-12621-3E
(Continued)
30-pin plastic SSOP Lead pitch 0.65 mm
Package width
×
package length
5.60 × 9.70 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height 1.45 mm MAX
Code
(Reference) P-SSOP30-5.6×9.7-0.65
30-pin plastic SSOP
(FPT-30P-M02)
(FPT-30P-M02)
C
2003-2010 FUJITSUSEMICONDUCTOR LIMITED F30003S-c-3-6
9.70±0.10(.382±.004)
5.60±0.10 7.60±0.20
(.220±.004) (.299±.008)
"A"
(.007±.001)
0.17±0.03
.009 –.003
+.003
–0.07
+0.08
0.24
INDEX
*1
*2
0.25(.010)
0.10±0.10
(.004±.004)
(Stand off)
Details of "A" part
(Mounting height)
1.25 +0.20
–0.10
–.004
+.008
.049
0~8°
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10(.004)0.10(.004)
1 15
3016
0.65(.026)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max).
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
MB95130MB Series
DS07-12621-3E 65
■MAJOR CHANGES IN THIS EDITION
A change on a page is indicated by a vertical line drawn on the left side of that page.
Page Section Change Results
2■ FEATURES Added “• Power-on reset”.
4■ PRODUCT LINEUP Added the parameter “Power-on reset”.
Changed the reset output of MB95136MB.
Ye s → Not selectable
29 ■ ELECTRICAL
CHARACTERISTICS
1. Absolute Maximum Ratings
Changed the maximum rating of the operating temperature.
85 → 105
40 ■ ELECTRICAL
CHARACTERISTICS
4. AC Characteristics
(2) Source Clock / Machine Clock
Added MB95136MB to the part numbers in “• Operating voltage -
Operating frequency”.
41 Changed the x-axis of the graph in “ • Main PLL operation fre-
quency”.
Machine clock frequency (FMP) → Main oscillation (FCH)
60 ■ MASK OPTION Changed the “Reset output” of the products listed below to “Not
selectable”.
MB95136MB
MB95F133MBS
MB95F133NBS
MB95F133JBS
MB95F134MBS
MB95F134NBS
MB95F134JBS
MB95F136MBS
MB95F136NBS
MB95F136JBS
MB95F133MBW
MB95F133NBW
MB95F133JBW
MB95F134MBW
MB95F134NBW
MB95F134JBW
MB95F136MBW
MB95F136NBW
MB95F136JBW
61 Added the following note.
If the clock supervisor is selected, reset output is always disabled.
MB95130MB Series
66 DS07-12621-3E
MEMO
MB95130MB Series
DS07-12621-3E 67
MEMO
MB95130MB Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
FUJITSU SEMICONDUCTOR AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://us.fujitsu.com/micro/
Europe
FUJITSU SEMICONDUCTOR EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/semiconductor/
Korea
FUJITSU SEMICONDUCTOR KOREA LTD.
902 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fsk/
Asia Pacific
FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://sg.fujitsu.com/semiconductor/
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fss/
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fsp/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does
not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
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The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
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weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages aris-
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Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-
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Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations
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