Datasheet RAA730300 Monolithic Programmable Analog IC R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Overview The RAA730300 is a monolithic programmable analog IC that supports low voltages and features a range of on-chip circuits such as configurable amplifiers, general-purpose operational amplifiers, D/A converters, and a temperature sensor, allowing the RAA730300 to be used as an analog front-end device for processing minute sensor signals. The RAA730300 uses a Serial Peripheral Interface (SPI) to allow external devices to control each on-chip circuit, enabling a more compact package and a reduction in the number of control pins. The compact package used by the RAA730300--a 48-pin LQFP--in turns enables a more compact set design. Features * On-chip configurable amplifier x 3 ch * On-chip general-purpose operational amplifier x 2 ch * On-chip low-pass filter x 1 ch * On-chip high-pass filter x 1 ch * On-chip D/A converter x 7 ch * On-chip variable output voltage regulator x 1 ch * On-chip temperature sensor x 1 ch * On-chip SPI x 1 ch * Includes a low-current mode. * Operating voltage range: 2.2 V VDD 3.6 V * Operating temperature range: -40C TA 105C * Package: 48-pin plastic LQFP (fine pitch) (7 x 7) Applications * Home appliances * Industrial equipment * Healthcare equipment R02DS0011EJ0110 May. 31, 2014 Rev.1.10 Page 1 of 117 RAA730300 Ordering Information Pin count 48 pins Package 48-pin plastic LQFP (fine pitch) (7 x 7) Part Number RAA730300CFP, RAA730300DFP Part No. R A A 7 3 0 3 0 0 D F P Package type FP: LQFP Classification C: Industrial applications D: Consumer applications Smart Analog IC group ASSP product Analog ASIC Device Mixed signal IC Renesas semiconductor product How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering, electronic circuits. * To gain a general understanding of functions: Read this manual in the order of the CONTENTS. * To check the revised points : The mark <R> shows major revised points. The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what: " field. Conventions Data significance Active low representations Note Caution Remark Numerical representations R02DS0011EJ0110 May. 31, 2014 Rev.1.10 : Higher digits on the left and lower digits on the right : xxx (overscore over pin and signal name) : Footnote for item marked with Note in the text : Information requiring particular attention : Supplementary information : Binary ...xxxx or xxxxB Decimal ...xxxx Hexadecimal ...xxxxH Page 2 of 117 RAA730300 Contents 1. Pin Configuration ............................................................................................................................... 5 1.1 1.2 1.3 1.4 1.5 Pin Layout ............................................................................................................................................................. 5 Block Diagram ...................................................................................................................................................... 6 Pin Functions ........................................................................................................................................................ 7 Connection of Unused Pins ................................................................................................................................... 9 Pin I/O Circuits ................................................................................................................................................... 10 2. Configurable Amplifiers .................................................................................................................. 14 2.1 2.2 2.3 2.4 Overview of Configurable Amplifier Features ................................................................................................... 14 Block Diagram .................................................................................................................................................... 15 Registers Controlling the Configurable Amplifiers ............................................................................................ 18 Procedure for Operating the Configurable Amplifiers ........................................................................................ 36 3. General-Purpose Operational Amplifier .......................................................................................... 53 3.1 3.2 3.3 3.4 Overview of General-Purpose Operational Amplifier Features .......................................................................... 53 Block Diagram .................................................................................................................................................... 54 Registers Controlling the General-Purpose Operational Amplifier .................................................................... 55 Procedure for Operating the General-Purpose Operational Amplifier ................................................................ 57 4. D/A Converters ................................................................................................................................ 59 4.1 4.2 4.3 4.4 4.5 Overview of D/A Converter Features ................................................................................................................. 59 Block Diagram .................................................................................................................................................... 60 Registers Controlling the D/A Converters .......................................................................................................... 61 Procedure for Operating the D/A Converters ...................................................................................................... 64 Notes on Using D/A Converters ......................................................................................................................... 65 5. Low-Pass Filter ................................................................................................................................ 66 5.1 5.2 5.3 5.4 Overview of Low-Pass Filter Features ................................................................................................................ 66 Block Diagram .................................................................................................................................................... 66 Registers Controlling the Low-Pass Filter .......................................................................................................... 67 Procedure for Operating the Low-Pass Filter ...................................................................................................... 69 6. High-Pass Filter ............................................................................................................................... 70 6.1 6.2 6.3 6.4 Overview of High-Pass Filter Features ............................................................................................................... 70 Block Diagram .................................................................................................................................................... 70 Registers Controlling the High-Pass Filter.......................................................................................................... 71 Procedure for Operating the High-Pass Filter ..................................................................................................... 73 7. Temperature Sensor ......................................................................................................................... 74 7.1 7.2 7.3 7.4 Overview of Temperature Sensor Features ......................................................................................................... 74 Block Diagram .................................................................................................................................................... 74 Registers Controlling the Temperature Sensor ................................................................................................... 75 Procedure for Operating the Temperature Sensor ............................................................................................... 76 8. Variable Output Voltage Regulator ................................................................................................. 77 8.1 8.2 8.3 8.4 Overview of Variable Output Voltage Regulator Features ................................................................................. 77 Block Diagram .................................................................................................................................................... 77 Registers Controlling the Variable Output Voltage Regulator............................................................................ 78 Procedure for Operating the Variable Output Voltage Regulator ....................................................................... 80 R02DS0011EJ0110 May. 31, 2014 Rev.1.10 Page 3 of 117 RAA730300 9. SPI .................................................................................................................................................... 81 9.1 9.2 Overview of SPI Features ................................................................................................................................... 81 SPI Communication ............................................................................................................................................ 82 10. Reset ............................................................................................................................................... 84 10.1 10.2 Overview of Reset Feature .................................................................................................................................. 84 Registers Controlling the Reset Feature .............................................................................................................. 87 11. Electrical Specifications................................................................................................................. 88 11.1 11.2 11.3 11.4 Absolute Maximum Ratings ............................................................................................................................... 88 Operating Condition............................................................................................................................................ 89 Supply Current Characteristics ........................................................................................................................... 90 Electrical Specifications of Each Block .............................................................................................................. 92 12. Package Drawing ......................................................................................................................... 111 R02DS0011EJ0110 May. 31, 2014 Rev.1.10 Page 4 of 117 RAA730300 1. Pin Configuration 1. Pin Configuration 1.1 Pin Layout MPXIN11 MPXIN20 MPXIN10 AGND3 I.C AVDD2 LDO_OUT AMP4_OUT AMP4_INN AMP4_INP TEMP_OUT RESET 48-pin plastic LQFP (fine pitch) (7 x 7) 36 35 34 33 32 31 30 29 28 27 26 25 40 21 MPXIN31 CS 41 20 MPXIN41 DGND 42 19 DAC1_OUT/VREFIN1 DAC4_OUT/VREFIN4 43 18 DAC2_OUT/VREFIN2 HPF_OUT 44 17 AVDD1 CLK_HPF 45 16 AMP1_OUT CLK_LPF 46 15 AGND1 AGND4 47 14 AMP2_OUT LPF_OUT 48 13 DAC3_OUT/VREFIN3 4 5 6 7 8 9 10 11 12 AMP3_OUT 3 MPXIN50 2 MPXIN60 1 MPXIN51 MPXIN40 SDI MPXIN61 22 AMP5_INP 39 AGND2 MPXIN30 SDO AMP5_INN 23 AMP5_OUT MPXIN21 38 TEST 24 SCLK SC_IN 37 AVDD3 DVDD Cautions 1. Make the potential of AGND1, AGND2, AGND3, AGND4, and DGND the same. 2. Make the potential of AVDD1, AVDD2, AVDD3, and DVDD the same. 3. Connect the LDO_OUT pin to AGND3 via a capacitor (1.0 F: recommended). 4. Connect the DAC4_OUT/VREFIN4 pin to AGND4 via a capacitor (470 pF: recommended). 5. Connect the I.C pin to AGND3. 6. Connect the TEST pin to AGND4. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 5 of 117 RAA730300 1.2 1. Pin Configuration Block Diagram AGND1 AGND2 AGND3 AVDD1 AVDD2 DAC1_OUT/VREFIN1 DAC2_OUT/VREFIN2 DAC3_OUT/VREFIN3 Configurable amplifierx3 ch MPXIN10 MPXIN11 MPXIN20 MPXIN21 AMP1_OUT Ch1 D/A converterx6 ch (Ch1, Ch2, Ch3, Ch5, Ch6, Ch7) AGND1 MPXIN30 MPXIN31 MPXIN40 MPXIN41 AMP2_OUT Ch2 AVDD1 Variable output voltage regulator MPXIN50 MPXIN51 MPXIN60 MPXIN61 AMP3_OUT Ch3 LDO_OUT AGND1 AVDD1 Temperature sensor Filter circuits SC_IN CLK_LPF LPF_OUT TEMP_OUT AGND1 DVDD SCLK SDI SDO CS DGND RESET Low-pass filter SPI CLK_HPF HPF_OUT High-pass filter AVDD3 AGND4 D/A converterx1 ch (Ch4) DAC4_OUT /VREFIN4 AGND4 R02DS0011EJ0110 Rev.1.10 May. 31, 2014 AVDD1 General-purpose operational amplifierx2 ch Ch1 AMP4_INN AMP4_INP AMP4_OUT Ch2 AMP5_INN AMP5_INP AMP5_OUT AGND1 Page 6 of 117 RAA730300 1.3 1. Pin Configuration Pin Functions Table 1-1. Pin No. Pin Name Pin Functions (1/2) I/O Pin Functions 1 AVDD3 - Power supply pin for low-pass filter, high-pass filter and D/A converter Ch4 2 SC_IN Input 3 TEST - 4 AMP5_OUT 5 AGND2 6 AMP5_INN Input Pin for inputting inverted signal to general-purpose operational amplifier Ch2 7 AMP5_INP Input Pin for inputting non-inverted signal to general-purpose operational amplifier Ch2 8 MPXIN61 Input Multiplexer 6 input pin 1 9 MPXIN51 Input Multiplexer 5 input pin 1 10 MPXIN60 Input Multiplexer 6 input pin 0 11 MPXIN50 Input Multiplexer 5 input pin 0 12 AMP3_OUT Output Configurable amplifier Ch3 output pin 13 DAC3_OUT/ VREFIN3 Output/ D/A converter Ch3 output pin/ input configurable amplifier Ch3 reference voltage input pin 14 AMP2_OUT Output Configurable amplifier Ch2 output pin 15 AGND1 16 AMP1_OUT 17 AVDD1 18 DAC2_OUT/ VREFIN2 Output/ D/A converter Ch2 output pin/ input configurable amplifier Ch2 reference voltage input pin 19 DAC1_OUT/ VREFIN1 Output/ D/A converter Ch1 output pin/ input configurable amplifier Ch1 reference voltage input pin 20 MPXIN41 Input Multiplexer 4 input pin 1 21 MPXIN31 Input Multiplexer 3 input pin 1 22 MPXIN40 Input Multiplexer 4 input pin 0 23 MPXIN30 Input Multiplexer 3 input pin 0 24 MPXIN21 Input Multiplexer 2 input pin 1 25 MPXIN11 Input Multiplexer 1 input pin 1 26 MPXIN20 Input Multiplexer 2 input pin 0 27 MPXIN10 Input Multiplexer 1 input pin 0 28 AGND3 - 29 I.C - - 30 AVDD2 - Power supply pin for configurable amplifier channels Ch1 to Ch3, general-purpose operational amplifiers channels Ch1 to Ch2, D/A converter channels Ch1 to Ch3, Ch5 to Ch7, variable output voltage regulator and temperature sensor Input pin for filter signal processing TEST pin Output General-purpose operational amplifier Ch2 output pin - - GND pin for configurable amplifier channels Ch1 to Ch3,general-purpose operational amplifiers channels Ch1 to Ch2, D/A converter channels Ch1 to Ch3, Ch5 to Ch7, variable output voltage regulator and temperature sensor GND pin for configurable amplifier channels Ch1 to Ch3, general-purpose operational amplifiers channels Ch1 to Ch2, D/A converter channels Ch1 to Ch3, Ch5 to Ch7, variable output voltage regulator and temperature sensor Output Configurable amplifier Ch1 output pin - R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Power supply pin for configurable amplifier channels Ch1 to Ch3, general-purpose operational amplifiers channels Ch1 to Ch2, D/A converter channels Ch1 to Ch3, Ch5 to Ch7, variable output voltage regulator and temperature sensor. GND pin for configurable amplifier channels Ch1 to Ch3, general-purpose operational amplifiers channels Ch1 to Ch2, D/A converter channels Ch1 to Ch3, Ch5 to Ch7, variable output voltage regulator and temperature sensor Page 7 of 117 RAA730300 1. Table 1-1. Pin No. Pin Name Pin Configuration Pin Functions (2/2) I/O Pin Functions 31 LDO_OUT Output Variable output voltage regulator output pin 32 AMP4_OUT Output General-purpose operational amplifier Ch1 output pin 33 AMP4_INN Input Pin for inputting inverted signal to general-purpose operational amplifier Ch1 34 AMP4_INP Input Pin for inputting non-inverted signal to general-purpose operational amplifier Ch1 35 TEMP_OUT 36 RESET 37 DVDD - 38 SCLK Input 39 SDO 40 SDI Input Serial data input pin for SPI 41 CS Input Chip select input pin for SPI 42 DGND 43 DAC4_OUT/ VREFIN4 Output/ D/A converter Ch4 output pin and pin for inputting reference voltage to low-pass input filter, high-pass filter, and general-purpose operational amplifier Ch2 44 HPF_OUT Output High-pass filter output pin 45 CLK_HPF Input Pin for inputting high-pass filter control clock 46 CLK_LPF Input Pin for inputting low-pass filter control clock 47 AGND4 48 LPF_OUT Output Temperature sensor output pin Input External reset input pin Power supply pin for SPI Serial clock input pin for SPI Output Serial data output pin for SPI - - GND pin for SPI GND pin for low-pass filter, high-pass filter and D/A converter Ch4 Output Low-pass filter output pin R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 8 of 117 RAA730300 1.4 1. Pin Configuration Connection of Unused Pins Table 1-2. Pin Name I/O Connection of Unused Pins Recommended Connection of Unused Pins SC_IN Input Directly connect to AGND4. AMP5_OUT Output Leave open. AMP5_INN Input Directly connect to AGND1. AMP5_INP Input MPXIN61 Input MPXIN51 Input MPXIN60 Input MPXIN50 Input AMP3_OUT Output Leave open. DAC3_OUT/VREFIN3 Output/input AMP2_OUT Output AMP1_OUT Output DAC2_OUT/VREFIN2 Output/input DAC1_OUT/VREFIN1 Output/input MPXIN41 Input MPXIN31 Input MPXIN40 Input MPXIN30 Input MPXIN21 Input MPXIN11 Input MPXIN20 Input MPXIN10 Input AMP4_OUT Output Leave open. AMP4_INN Input Directly connect to AGND1. AMP4_INP Input TEMP_OUT Output Leave open. SCLK Input Connect to Ground. SDO Output Leave open. SDI Input Connect to Ground. CS Input DAC4_OUT/VREFIN4 Output/input HPF_OUT Output CLK_HPF Input CLK_LPF Input LPF_OUT Output LDO_OUT Output RESET Input Directly connect to AGND1. Note Note Leave open. Connect to DVDD directly or via a resistor. Note Ground means the same electrical potential as AGND1, AGND2, AGND3, AGND4 and DGND. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 9 of 117 RAA730300 1.5 1. Pin Configuration Pin I/O Circuits Figure 1-1. Pin Name Pin I/O Circuit Type (1/4) Equivalent Circuit RESET Pin Name Equivalent Circuit MPXIN10 MPXIN11 MPXIN20 MPXIN21 MPXIN30 MPXIN31 IN MPXIN40 IN MPXIN41 Schmitt-triggered input with hysteresis characteristics MPXIN50 MPXIN51 MPXIN60 MPXIN61 SC_IN CLK_LPF SCLK CLK_HPF SDI CS DVDD Schmitt-triggered input with hysteresis characteristics IN IN AGND4 Schmitt-triggered input with hysteresis characteristics R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 10 of 117 RAA730300 1. Figure 1-1. Pin Name Pin Configuration Pin I/O Circuit Type (2/4) Equivalent Circuit Pin Name LPF_OUT Equivalent Circuit DAC1_OUT/ VREFIN1 HPF_OUT DAC2_OUT/ VREFIN2 AVDD3 DAC3_OUT/ VREFIN3 AVDD1 OUT IN/OUT AGND1 AGND4 AGND1 LDO_OUT DAC4_OUT/ VREFIN4 AVDD2 AVDD3 OUT IN/OUT AGND4 AGND3 AGND3 AGND4 R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 11 of 117 RAA730300 1. Figure 1-1. Pin Name Pin Configuration Pin I/O Circuit Type (3/4) Equivalent Circuit Pin Name Equivalent Circuit AMP3_OUT TEMP_OUT AVDD2 AVDD1 OUT OUT AGND3 AGND3 AGND1 AMP4_OUT AMP1_OUT AMP2_OUT OUT AMP5_OUT AVDD1 OUT AGND1 R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 12 of 117 RAA730300 1. Figure 1-1. Pin Name Pin Configuration Pin I/O Circuit Type (4/4) Equivalent Circuit Pin Name Equivalent Circuit AMP4_INP SDO AVDD2 DVDD DVDD IN OUT DGND AGND1 AMP4_INN AMP5_INP AMP5_INN AVDD1 AVDD1 IN IN AGND1 R02DS0011EJ0110 Rev.1.10 May. 31, 2014 AGND1 Page 13 of 117 RAA730300 2. Configurable Amplifiers 2. Configurable Amplifiers The RAA730300 has three on-chip configurable amplifier channels. 2.1 Overview of Configurable Amplifier Features By specifying settings in the SPI control registers, the configurable amplifiers can be used to realize the following features: * * Single-channel operation Non-inverting amplifier * The gain can be specified between 9.5 dB and 40.1 dB in 18 steps * Four operating modes are available * Includes an input mode switching function * Includes a power-off function Inverting amplifier * The gain can be specified between 6 dB and 40 dB in 18 steps * Four operating modes are available * Includes an input mode switching function * Includes a power-off function Differential amplifier * The gain can be specified between 6 dB and 40 dB in 18 steps * Four operating modes are available * Includes an input mode switching function * Includes a power-off function Transimpedance amplifier * The feedback resistance can be specified between 20 k and 640 k in 6 steps * Four operating modes are available * Includes an input mode switching function * Includes a power-off function General-purpose operational amplifier * Four operating modes are available * Includes an input mode switching function * Includes a power-off function Multiple-channel operation Instrumentation amplifier * The gain can be specified between 15.5 dB and 33.5 dB in 10 steps * Four operating modes are available * Includes an input mode switching function * Includes a power-off function <R> And also, the output signal from D/A converter Ch n (n = 1 to 3, 5 to 7) can be used as the reference voltage for each configurable amplifier. If D/A converters are powered off, the external reference voltage is to be input to DACn_OUT/VREFINn (n = 1 to 3) pin. For details about use of D/A converter, see 4. D/A Converter. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 14 of 117 RAA730300 2.2 2. Configurable Amplifiers Block Diagram Figure 2-1. Block Diagram of Configurable Amplifier Ch1 Internal bus Input mode control register (IMS) IMS1 SW00 Configuration register 2 (CONFIG2) SW01 SW10 SW11 Configuration register 1 (CONFIG1) SW12 SW13 AMPG14 AMPG13 AMP operation mode control register (AOMC) Gain control register 1 (GC1) AMPG12 AMPG11 CC11 AMPG10 DAC57 CC10 D AC5 6 D AC5 5 MPX1 MPXIN11 DAC54 DAC53 DAC52 DAC51 D AC5 0 AVDD1 Selector MPXIN10 DAC control register 5 (DAC5C) AGND1 SW11 SW10 - SW01 AMP1_OUT + MPX2 MPX5, MPX6, MPX7 Selector MPXIN20 MPXIN21 SW12 DAC1_OUT/VREFIN1 SW13 8-bit DAC1 8-bit DAC5 MPX3 MPXIN31 D/A converter Ch6 output signal MPX11 MPX10 MPX21 SW00 Selector MPXIN30 MPX20 MPX31 Source of configurable amp Ch2 non-inverted input MPX30 MPX setting register 1 (MPX1) R02DS0011EJ0110 Rev.1.10 May. 31, 2014 DAC1OF AMP1OF DAC5OF Power control register 1 (PC1) DAC17 D AC1 6 Power control register 2 (PC2) Internal bus D AC1 5 DAC14 DAC13 DAC12 DAC11 D AC1 0 DAC control register 1 (DAC1C) VRT1 VRT0 VRB1 VRB0 DAC reference voltage control register (DACRC) Page 15 of 117 RAA730300 2. Figure 2-2. <R> Configurable Amplifiers Block Diagram of Configurable Amplifier Ch2 Internal bus Input mode control register (IMS) I MS2 SW00 Configuration register 2 (CONFIG2) SW02 SW20 SW21 Configuration register 1 (CONFIG1) SW22 SW23 AMPG24 AMPG23 AMP operation mode control register (AOMC) Gain control register 2 (GC2) AMPG22 AMPG21 AMPG20 CC21 DAC67 CC20 D AC6 6 D AC6 5 MPX3 MPXIN31 DAC64 DAC63 DAC62 DAC61 D AC6 0 AVDD1 Selector MPXIN30 DAC control register 6 (DAC6C) AGND1 SW21 SW20 - SW02 AMP2_OUT + MPX4 MPX5, MPX6, MPX7 Selector MPXIN40 MPXIN41 SW22 DAC2_OUT/VREFIN2 SW23 8-bit DAC2 8-bit DAC6 MPX1 MPXIN11 D/A converter Ch5 output signal MPX11 MPX10 MPX31 SW00 Selector MPXIN10 MPX30 MPX41 Source of configurable amp Ch1 non-inverted input MPX40 MPX setting register 1 (MPX1) DAC2OF AMP2OF DAC6OF Power control register 1 (PC1) DAC27 D AC2 6 Power control register 2 (PC2) D AC2 5 DAC24 DAC23 DAC22 DAC21 D AC2 0 DAC control register 2 (DAC2C) VRT1 VRT0 VRB1 VRB0 DAC reference voltage control register (DACRC) Internal bus R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 16 of 117 RAA730300 2. Figure 2-3. Configurable Amplifiers Block Diagram of Configurable Amplifier Ch3 Internal bus Configuration register 2 (CONFIG2) Input mode control register (IMS) SW30 I MS3 SW31 SW32 SW33 AMPG34 AMP operation mode control register (AOMC) Gain control register 3 (GC3) AMPG33 AMPG32 AMPG31 AMPG30 CC31 DAC77 CC30 D AC7 6 D AC7 5 DAC control register 7 (DAC7C) DAC74 DAC73 DAC72 DAC71 D AC7 0 MPX5 AVDD1 MPXIN50 Selector MPXIN51 Configurable amplifier Ch1 output signal Configurable amplifier Ch2 output signal AGND1 SW31 SW30 - AMP3_OUT + MPX6 MPXIN60 MPX7 Selector MPXIN61 Configurable amplifier Ch1 output signal Configurable amplifier Ch2 output signal SW32 DAC3_OUT/VREFIN3 SW33 8-bit DAC3 8-bit DAC7 MPX52 MPX51 MPX50 MPX62 MPX61 MPX60 MPX setting register 2 (MPX2) DAC3OF AMP3OF DAC7OF Power control register 1 (PC1) DAC37 D AC3 6 Power control register 2 (PC2) D AC3 5 DAC34 DAC33 DAC32 DAC31 D AC3 0 DAC control register 3 (DAC3C) VRT1 VRT0 VRB1 VRB0 DAC reference voltage control register (DACRC) Internal bus R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 17 of 117 RAA730300 2.3 2. Configurable Amplifiers Registers Controlling the Configurable Amplifiers The configurable amplifiers are controlled by the following 10 registers: * Configuration register 1 (CONFIG1) * Configuration register 2 (CONFIG2) * MPX setting register 1 (MPX1) * MPX setting register 2 (MPX2) * Gain control register 1 (GC1) * Gain control register 2 (GC2) * Gain control register 3 (GC3) * AMP operation mode control register (AOMC) * Power control register 1 (PC1) * Input mode control register (IMS) R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 18 of 117 RAA730300 (1) 2. Configurable Amplifiers Configuration register 1 (CONFIG1) This register is used to turn on or off each switch of configurable amplifier channels Ch1 and Ch2. Reset signal input sets this register to 88H. Address: 00H After reset: 88H R/W CONFIG1 7 6 5 4 3 2 1 0 SW10 SW11 SW12 SW13 SW20 SW21 SW22 SW23 SW10 Control of SW10 0 Turn off SW10. 1 Turn on SW10. SW11 Control of SW11 0 Turn off SW11. 1 Turn on SW11. SW12 Control of SW12 0 Turn off SW12. 1 Turn on SW12. SW13 Control of SW13 0 Turn off SW13. 1 Turn on SW13. SW20 Control of SW20 0 Turn off SW20. 1 Turn on SW20. SW21 Control of SW21 0 Turn off SW21. 1 Turn on SW21. SW22 Control of SW22 0 Turn off SW22. 1 Turn on SW22. SW23 Control of SW23 0 Turn off SW23. 1 Turn on SW23. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 19 of 117 RAA730300 (2) 2. Configurable Amplifiers Configuration register 2 (CONFIG2) This register is used to turn on or off each switch of configurable amplifier channels Ch1 to Ch3. Reset signal input sets this register to 80H. Address: 01H After reset: 80H R/W CONFIG2 7 6 5 4 3 2 1 0 SW30 SW31 SW32 SW33 0 SW02 SW01 SW00 SW30 Control of SW30 0 Turn off SW30. 1 Turn on SW30. SW31 Control of SW31 0 Turn off SW31. 1 Turn on SW31. SW32 Control of SW32 0 Turn off SW32. 1 Turn on SW32. SW33 Control of SW33 0 Turn off SW33. 1 Turn on SW33. SW02 Control of SW02 0 Turn off SW02. 1 Turn on SW02. SW01 Control of SW01 0 Turn off SW01. 1 Turn on SW01. SW00 0 1 Remark Control of SW00 Turn off SW00. Turn on SW00. Bit 3 can be set to 1, but this has no effect on the function. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 20 of 117 RAA730300 (3) 2. Configurable Amplifiers MPX setting register 1 (MPX1) This register is used to control MPX1, MPX2, MPX3, and MPX4. This register is used to select the signal input to configurable amplifier channels Ch1 and Ch2. Reset signal input clears this register to 00H. Address: 03H After reset: 00H R/W MPX1 7 6 5 4 3 2 1 0 MPX11 MPX10 MPX21 MPX20 MPX31 MPX30 MPX41 MPX40 MPX11 MPX10 0 0 MPXIN10 pin 0 1 MPXIN11 pin 1 0 D/A converter Ch5 output signal 1 1 Open pin MPX21 MPX20 0 0 MPXIN20 pin 0 1 MPXIN21 pin 1 0 D/A converter Ch5 output signal 1 1 Open pin MPX31 MPX30 0 0 MPXIN30 pin 0 1 MPXIN31 pin 1 0 D/A converter Ch6 output signal 1 1 Open pin MPX41 MPX40 0 0 MPXIN40 pin 0 1 MPXIN41 pin 1 0 D/A converter Ch6 output signal 1 1 Open pin R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Source of configurable amplifier Ch1 inverted input Source of configurable amplifier Ch1 non-inverted input Source of configurable amplifier Ch2 inverted input Source of configurable amplifier Ch2 non-inverted input Page 21 of 117 RAA730300 (4) 2. Configurable Amplifiers MPX setting register 2 (MPX2) This register is used to control MPX5 and MPX6. This register is used to select the signal input to configurable amplifier Ch3. Reset signal input clears this register to 00H. Address: 04H After reset: 00H R/W MPX2 7 6 5 4 3 2 1 0 0 MPX52 MPX51 MPX50 0 MPX62 MPX61 MPX60 MPX52 MPX51 MPX50 0 0 0 MPXIN50 pin 0 0 1 MPXIN51 pin 0 1 0 Configurable amplifier Ch1 output signal 0 1 1 Configurable amplifier Ch2 output signal 1 0 0 D/A converter Ch7 output signal Other than above Source of configurable amplifier Ch3 inverted input Setting prohibited MPX62 MPX61 MPX60 0 0 0 MPXIN60 pin 0 0 1 MPXIN61 pin 0 1 0 Output signal of configurable amplifier Ch1 0 1 1 Configurable amplifier Ch2 output signal 1 0 0 D/A converter Ch7 output signal Other than above Remark Source of configurable amplifier Ch3 non-inverted input Setting prohibited Bits 7 and 3 can be set to 1, but this has no effect on the function. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 22 of 117 RAA730300 (5) 2. Configurable Amplifiers Gain control register 1 (GC1) This register is used to specify the gain and feedback resistance of configurable amplifier Ch1. The value to specify depends on the configuration of configurable amplifier Ch1. When using configurable amplifier channels Ch1 to Ch3 together as an instrumentation amplifier, be sure to set gain control register 1 (GC1) to 00H. Reset signal input clears this register to 00H. Address: 06H After reset: 00H R/W GC1 7 6 5 4 3 2 1 0 0 0 0 AMPG14 AMPG13 AMPG12 AMPG11 AMPG10 Table 2-1. Gain of Configurable Amplifier Ch1 (Non-Inverting Amplifier) AMPG14 AMPG13 AMPG12 AMPG11 AMPG10 0 0 0 0 0 9.5 dB 0 0 0 0 1 10.9 dB 0 0 0 1 0 12.4 dB 0 0 0 1 1 14.0 dB 0 0 1 0 0 15.6 dB 0 0 1 0 1 17.3 dB 0 0 1 1 0 19.0 dB 0 0 1 1 1 20.8 dB 0 1 0 0 0 22.7 dB 0 1 0 0 1 24.5 dB 0 1 0 1 0 26.4 dB 0 1 0 1 1 28.3 dB 0 1 1 0 0 30.3 dB 0 1 1 0 1 32.2 dB 0 1 1 1 0 34.2 dB 0 1 1 1 1 36.1 dB 1 0 0 0 0 38.1 dB 1 0 0 0 1 40.1 dB Other than above Remark Gain of Configurable Amplifier Ch1 (Typ.) Setting prohibited Bits 7 to 5 can be set to 1, but this has no effect on the function. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 23 of 117 RAA730300 2. Configurable Amplifiers Table 2-2. Gain of Configurable Amplifier Ch1 (Inverting Amplifier and Differential Amplifier) AMPG14 AMPG13 AMPG12 AMPG11 AMPG10 0 0 0 0 0 6 dB 0 0 0 0 1 8 dB 0 0 0 1 0 10 dB 0 0 0 1 1 12 dB 0 0 1 0 0 14 dB 0 0 1 0 1 16 dB 0 0 1 1 0 18 dB 0 0 1 1 1 20 dB 0 1 0 0 0 22 dB 0 1 0 0 1 24 dB 0 1 0 1 0 26 dB 0 1 0 1 1 28 dB 0 1 1 0 0 30 dB 0 1 1 0 1 32 dB 0 1 1 1 0 34 dB 0 1 1 1 1 36 dB 1 0 0 0 0 38 dB 1 0 Other than above 0 0 1 40 dB Setting prohibited R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Gain of Configurable Amplifier Ch1 (Typ.) Page 24 of 117 RAA730300 2. Table 2-3. Configurable Amplifiers Feedback Resistance of Configurable Amplifier Ch1 (Transimpedance Amplifier) AMPG14 AMPG13 AMPG12 AMPG11 AMPG10 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 Other than above 0 0 1 R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Feedback Resistance of Configurable Amplifier Ch1 (Typ.) 20 k 40 k 80 k 160 k 320 k 640 k Setting prohibited Page 25 of 117 RAA730300 (6) 2. Configurable Amplifiers Gain control register 2 (GC2) This register is used to specify the gain and feedback resistance of configurable amplifier Ch2. The value to specify depends on the configuration of configurable amplifier Ch2. When using configurable amplifier channels Ch1 to Ch3 together as an instrumentation amplifier, be sure to set gain control register 2 (GC2) to 00H. Reset signal input clears this register to 00H. Address: 07H After reset: 00H R/W GC2 7 6 5 4 3 2 1 0 0 0 0 AMPG24 AMPG23 AMPG22 AMPG21 AMPG20 Table 2-4. Gain of Configurable Amplifier Ch2 (Non-Inverting Amplifier) AMPG24 AMPG23 AMPG22 AMPG21 AMPG20 0 0 0 0 0 9.5 dB 0 0 0 0 1 10.9 dB 0 0 0 1 0 12.4 dB 0 0 0 1 1 14.0 dB 0 0 1 0 0 15.6 dB 0 0 1 0 1 17.3 dB 0 0 1 1 0 19.0 dB 0 0 1 1 1 20.8 dB 0 1 0 0 0 22.7 dB 0 1 0 0 1 24.5 dB 0 1 0 1 0 26.4 dB 0 1 0 1 1 28.3 dB 0 1 1 0 0 30.3 dB 0 1 1 0 1 32.2 dB 0 1 1 1 0 34.2 dB 0 1 1 1 1 36.1 dB 1 0 0 0 0 38.1 dB 1 0 0 0 1 40.1 dB Other than above Remark Gain of Configurable Amplifier Ch2 (Typ.) Setting prohibited Bits 7 to 5 can be set to 1, but this has no effect on the function. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 26 of 117 RAA730300 2. Configurable Amplifiers Table 2-5. Gain of Configurable Amplifier Ch2 (Inverting Amplifier and Differential Amplifier) AMPG24 AMPG23 AMPG22 AMPG21 AMPG20 0 0 0 0 0 6 dB 0 0 0 0 1 8 dB 0 0 0 1 0 10 dB 0 0 0 1 1 12 dB 0 0 1 0 0 14 dB 0 0 1 0 1 16 dB 0 0 1 1 0 18 dB 0 0 1 1 1 20 dB 0 1 0 0 0 22 dB 0 1 0 0 1 24 dB 0 1 0 1 0 26 dB 0 1 0 1 1 28 dB 0 1 1 0 0 30 dB 0 1 1 0 1 32 dB 0 1 1 1 0 34 dB 0 1 1 1 1 36 dB 1 0 0 0 0 38 dB 1 0 0 0 1 40 dB Other than above R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Gain of Configurable Amplifier Ch2 (Typ.) Setting prohibited Page 27 of 117 RAA730300 2. Table 2-6. Configurable Amplifiers Feedback Resistance of Configurable Amplifier Ch2 (Transimpedance Amplifier) AMPG24 AMPG23 AMPG22 AMPG21 AMPG20 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 Other than above R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Feedback Resistance of Configurable Amplifier Ch2 (Typ.) 20 k 40 k 80 k 160 k 320 k 640 k Setting prohibited Page 28 of 117 RAA730300 (7) 2. Configurable Amplifiers Gain control register 3 (GC3) This register is used to specify the gain and feedback resistance of configurable amplifier Ch3. The value to specify depends on the configuration of configurable amplifier Ch3. When using configurable amplifier channels Ch1 to Ch3 together as an instrumentation amplifier, be sure to set gain control register 1 (GC1) and gain control register 2 (GC2) to 00H, respectively. Reset signal input clears this register to 00H. Address: 08H After reset: 00H R/W GC3 7 6 5 4 3 2 1 0 0 0 0 AMPG34 AMPG33 AMPG32 AMPG31 AMPG30 Table 2-7. Gain of Configurable Amplifier Ch3 (Non-Inverting Amplifier) AMPG34 AMPG33 AMPG32 AMPG31 AMPG30 0 0 0 0 0 9.5 dB 0 0 0 0 1 10.9 dB 0 0 0 1 0 12.4 dB 0 0 0 1 1 14.0 dB 0 0 1 0 0 15.6 dB 0 0 1 0 1 17.3 dB 0 0 1 1 0 19.0 dB 0 0 1 1 1 20.8 dB 0 1 0 0 0 22.7 dB 0 1 0 0 1 24.5 dB 0 1 0 1 0 26.4 dB 0 1 0 1 1 28.3 dB 0 1 1 0 0 30.3 dB 0 1 1 0 1 32.2 dB 0 1 1 1 0 34.2 dB 0 1 1 1 1 36.1 dB 1 0 0 0 0 38.1 dB 1 0 0 0 1 40.1 dB Other than above Remark Gain of Configurable Amplifier Ch3 (Typ.) Setting prohibited Bits 7 to 5 can be set to 1, but this has no effect on the function. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 29 of 117 RAA730300 2. Configurable Amplifiers Table 2-8. Gain of Configurable Amplifier Ch3 (Inverting Amplifier and Differential Amplifier) AMPG34 AMPG33 AMPG32 AMPG31 AMPG30 0 0 0 0 0 6 dB 0 0 0 0 1 8 dB 0 0 0 1 0 10 dB 0 0 0 1 1 12 dB 0 0 1 0 0 14 dB 0 0 1 0 1 16 dB 0 0 1 1 0 18 dB 0 0 1 1 1 20 dB 0 1 0 0 0 22 dB 0 1 0 0 1 24 dB 0 1 0 1 0 26 dB 0 1 0 1 1 28 dB 0 1 1 0 0 30 dB 0 1 1 0 1 32 dB 0 1 1 1 0 34 dB 0 1 1 1 1 36 dB 1 0 0 0 0 38 dB 1 0 0 0 1 40 dB Other than above R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Gain of Configurable Amplifier Ch3 (Typ.) Setting prohibited Page 30 of 117 RAA730300 2. Table 2-9. Configurable Amplifiers Feedback Resistance of Configurable Amplifier Ch3 (Transimpedance Amplifier) AMPG34 AMPG33 AMPG32 AMPG31 AMPG30 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 Other than above R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Feedback Resistance of Configurable Amplifier Ch3 (Typ.) 20 k 40 k 80 k 160 k 320 k 640 k Setting prohibited Page 31 of 117 RAA730300 2. Configurable Amplifiers Table 2-10. Gain of Configurable Amplifier Ch3 (Instrumentation Amplifier) AMPG34 AMPG33 AMPG32 AMPG31 AMPG30 0 0 0 0 0 15.5 dB 0 0 0 0 1 17.5 dB 0 0 0 1 0 19.5 dB 0 0 0 1 1 21.5 dB 0 0 1 0 0 23.5 dB 0 0 1 0 1 25.5 dB 0 0 1 1 0 27.5 dB 0 0 1 1 1 29.5 dB 0 1 0 0 0 31.5 dB 0 1 0 0 1 33.5 dB Other than above R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Gain of Configurable Amplifier Ch3 (Typ.) Setting prohibited Page 32 of 117 RAA730300 (8) 2. Configurable Amplifiers AMP operation mode control register (AOMC) This register is used to specify the operating mode of configurable amplifiers Ch1 to Ch3. Reset signal input clears this register to 00H. Address: 09H After reset: 00H R/W AOMC 7 6 5 4 3 2 1 0 0 0 CC31 CC30 CC21 CC20 CC11 CC10 CC31 CC30 0 0 High-speed mode 0 1 Mid-speed mode 2 1 0 Mid-speed mode 1 1 1 Low-speed mode CC21 CC20 0 0 High-speed mode 0 1 Mid-speed mode 2 1 0 Mid-speed mode 1 1 1 Low-speed mode CC11 CC10 0 0 High-speed mode 0 1 Mid-speed mode 2 1 0 Mid-speed mode 1 1 1 Low-speed mode Remark Operating mode of configurable amplifier Ch3 Operating mode of configurable amplifier Ch2 Operating mode of configurable amplifier Ch1 Bits 7 and 6 can be set to 1, but this has no effect on the function. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 33 of 117 RAA730300 <R> (9) 2. Configurable Amplifiers Power control register 1 (PC1) This register is used to enable or disable operation of the configurable amplifiers, general-purpose operational amplifiers, and the D/A converters. Use this register to stop unused functions to reduce power consumption and noise. When using one of configurable amplifier channels Ch1 to Ch3, be sure to set the control bit that corresponds to the channel (bits 2 to 0) to 1. Reset signal input clears this register to 00H. Address: 11H After reset: 00H R/W PC1 7 6 5 4 3 2 1 0 DAC4OF DAC3OF DAC2OF DAC1OF AMP4OF AMP3OF AMP2OF AMP1OF AMP3OF Operation of configurable amplifier Ch3 0 Stop operation of configurable amplifier Ch3. 1 Enable operation of configurable amplifier Ch3. AMP2OF Operation of configurable amplifier Ch2 0 Stop operation of configurable amplifier Ch2. 1 Enable operation of configurable amplifier Ch2. AMP1OF Operation of configurable amplifier Ch1 0 Stop operation of configurable amplifier Ch1. 1 Enable operation of configurable amplifier Ch1. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 34 of 117 RAA730300 2. Configurable Amplifiers (10) Input mode control register (IMS) This register is used to specify the input mode of the configurable amplifiers, general-purpose operational amplifiers, the low-pass filter, and high-pass filter. When using one of configurable amplifier channels Ch1 to Ch3, be sure to set the control bit that corresponds to the channel (bits 2 to 0). Address: 14H After reset: 00H R/W IMS 7 6 5 4 3 2 1 0 0 0 IMS6 IMS5 IMS4 IMS3 IMS2 IMS1 IMS3 Input mode of configurable amplifier Ch3 0 Rail-to-rail input mode 1 P-ch single-ended input mode IMS2 Input mode of configurable amplifier Ch2 0 Rail-to-rail input mode 1 P-ch single-ended input mode IMS1 Input mode of configurable amplifier Ch1 0 Rail-to-rail input mode 1 P-ch single-ended input mode Remark Bits 7 and 6 can be set to 1, but this has no effect on the function. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 35 of 117 RAA730300 2.4 (1) 2. Configurable Amplifiers Procedure for Operating the Configurable Amplifiers Procedure when using the amplifiers as non-inverting amplifiers When using the configurable amplifiers as non-inverting amplifiers, follow the procedures below to start and stop the amplifiers. Example of procedure for starting configurable amplifier Ch1 (non-inverting amplifier) Start Set CONFIG1 register Specify the circuit configuration of configurable amplifier Ch1. (SW10, SW11, SW12, SW13 = 1, 0, 1, 0) Set MPX1 register Set the input pins. (MPX11, MPX10, MPX21, MPX20 = 1, 0, 0, *) Set IMS register Specify the input mode. (IMS1 = *) Set AOMC register Specify the amplifier operation mode. (CC11, CC10 = *, *) Set GC1 register Specify the gain. (GC1 = **H) Set CONFIG2 register Set PC1 register Set the output switches. (SW01 = 1) Start operation of configurable amplifier Ch1. (AMP1OF = 1) Operation starts Remark *: don't care Example of procedure for stopping configurable amplifier Ch1 (non-inverting amplifier) Operating Set PC1 register Stop operation of configurable amplifier Ch1. (AMP1OF = 0) Operation stops R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 36 of 117 RAA730300 2. Configurable Amplifiers Example of procedure for starting configurable amplifier Ch2 (non-inverting amplifier) Example of procedure for stopping configurable amplifier Ch2 (non-inverting amplifier) Operating Set PC1 register Stop operation of configurable amplifier Ch2. (AMP2OF = 0) Operation stops R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 37 of 117 RAA730300 2. Configurable Amplifiers Example of procedure for starting configurable amplifier Ch3 (non-inverting amplifier) Start Set CONFIG2 register Set MPX2 register Set IMS register Set AOMC register Specify the circuit configuration of configurable amplifier Ch3. (SW30, SW31, SW32, SW33 = 1, 0, 1, 0) Set the input pins. (MP52, MPX51, MPX50, MPX62, MPX61, MPX60 = 1, 0, 0, 0, 0, *) Specify the input mode. (IMS3 = *) Specify the amplifier operation mode. (CC31, CC30 = *, *) Specify the gain. (GC3 = **H) Set GC3 register Set PC1 register Start operation of configurable amplifier Ch3. (AMP3OF = 1) Operation starts Remark *: don't care Example of procedure for stopping configurable amplifier Ch3 (non-inverting amplifier) Operating Set PC1 register Stop operation of configurable amplifier Ch3. (AMP3OF = 0) Operation stops R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 38 of 117 RAA730300 (2) 2. Configurable Amplifiers Procedure when using the amplifiers as inverting amplifiers When using the configurable amplifiers as inverting amplifiers, follow the procedures below to start and stop the amplifiers. Example of procedure for starting configurable amplifier Ch1 (inverting amplifier) Start Set CONFIG1 register Set MPX1 register Set IMS register Set AOMC register Specify the circuit configuration of configurable amplifier Ch1. (SW10, SW11, SW12, SW13 = 1, 0, 1, 0) Set the input pins. (MPX11, MPX10, MPX21, MPX20 = 0, *, 1, 0) Specify the input mode. (IMS1 = *) Specify the amplifier operation mode. (CC11, CC10 = *, *) Specify the gain. (GC1 = **H) Set GC1 register Set CONFIG2 register Set PC1 register Set the output switches. (SW01 = 1) Start operation of configurable amplifier Ch1. (AMP1OF = 1) Operation starts Remark *: don't care Example of procedure for stopping configurable amplifier Ch1 (inverting amplifier) Operating Set PC1 register Stop operation of configurable amplifier Ch1. (AMP1OF = 0) Operation stops R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 39 of 117 RAA730300 2. Configurable Amplifiers Example of procedure for starting configurable amplifier Ch2 (inverting amplifier) Example of procedure for stopping configurable amplifier Ch2 (inverting amplifier) Operating Set PC1 register Stop operation of configurable amplifier Ch2. (AMP2OF = 0) Operation stops R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 40 of 117 RAA730300 2. Configurable Amplifiers Example of procedure for starting configurable amplifier Ch3 (inverting amplifier) Start Set CONFIG2 register Set MPX2 register Set IMS register Set AOMC register Set GC3 register Set PC1 register Specify the circuit configuration of configurable amplifier Ch3. (SW30, SW31, SW32, SW33 = 1, 0, 1, 0) Set the input pins. (MP52, MPX51, MPX50, MPX62, MPX61, MPX60 = 0, 0, *, 1, 0, 0) Specify the input mode. (IMS3 = *) Specify the amplifier operation mode. (CC31, CC30 = *, *) Specify the gain (GC3 = **H) Start operation of configurable amplifier Ch3. (AMP3OF = 1) Operation starts Remark *: don't care Example of procedure for stopping configurable amplifier Ch3 (inverting amplifier) Operating Set PC1 register Stop operation of configurable amplifier Ch3. (AMP3OF = 0) Operation stops R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 41 of 117 RAA730300 (3) 2. Configurable Amplifiers Procedure when using the amplifiers as differential amplifiers When using the configurable amplifiers together as a differential amplifier, follow the procedures below to start and stop the amplifier. Example of procedure for starting configurable amplifier Ch1 (differential amplifier) Start Set CONFIG1 register Set MPX1 register Set IMS register Set AOMC register Specify the circuit configuration of configurable amplifier Ch1. (SW10, SW11, SW12, SW13 = 1, 0, 0, 1) Set the input pins. (MPX11, MPX10, MPX21, MPX20 = 0, *, 0, *) Specify the input mode. (IMS1 = *) Specify the amplifier operation mode. (CC11, CC10 = *, *) Specify the gain. (GC1 = **H) Set GC1 register Set the output switches. (SW01 = 1) Set CONFIG2 register Set PC1 register Start operation of configurable amplifier Ch1. (AMP1OF = 1) Operation starts Remark *: don't care Example of procedure for stopping configurable amplifier Ch1 (differential amplifier) Operating Set PC1 register Stop operation of configurable amplifier Ch1. (AMP1OF = 0) Operation stops R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 42 of 117 RAA730300 2. Configurable Amplifiers Example of procedure for starting configurable amplifier Ch2 (differential amplifier) Start Set CONFIG1 register Set MPX1 register Set IMS register Set AOMC register Set GC2 register Set CONFIG2 register Set PC1 register Specify the circuit configuration of configurable amplifier Ch2. (SW20, SW21, SW22, SW23 = 1, 0, 0, 1) Set the input pins. (MPX31, MPX30, MPX41, MPX40 = 0, *, 0, *) Specify the input mode. (IMS2 = *) Specify the amplifier operation mode. (CC21, CC20 = *, *) Specify the gain. (GC2 = **H) Set the output switches. (SW02 = 1) Start operation of configurable amplifier Ch2. (AMP2OF = 1) Operation starts Remark *: don't care Example of procedure for stopping configurable amplifier Ch2 (differential amplifier) Operating Set PC1 register Stop operation of configurable amplifier Ch2. (AMP2OF = 0) Operation stops R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 43 of 117 RAA730300 2. Configurable Amplifiers Example of procedure for starting configurable amplifier Ch3 (differential amplifier) Start Set CONFIG2 register Set MPX2 register Set IMS register Set AOMC register Specify the circuit configuration of configurable amplifier Ch3. (SW30, SW31, SW32, SW33 = 1, 0, 0, 1) Set the input pins. (MP52, MPX51, MPX50, MPX62, MPX61, MPX60 = 0, 0, *, 0, 0, *) Specify the input mode. (IMS3 = *) Specify the amplifier operation mode. (CC31, CC30 = *, *) Specify the gain. (GC3 = **H) Set GC3 register Set PC1 register Start operation of configurable amplifier Ch3. (AMP3OF = 1) Operation starts Remark *: don't care Example of procedure for stopping configurable amplifier Ch3 (differential amplifier) Operating Set PC1 register Stop operation of configurable amplifier Ch3. (AMP3OF = 0) Operation stops R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 44 of 117 RAA730300 (4) 2. Configurable Amplifiers Procedure when using the amplifiers as a transimpedance amplifier When using the configurable amplifiers as transimpedance amplifiers, follow the procedures below to start and stop the amplifiers. Example of procedure for starting configurable amplifier Ch1 (transimpedance amplifier) Start Set CONFIG1 register Set MPX1 register Set IMS register Set AOMC register Set GC1 register Set CONFIG2 register Set PC1 register Specify the circuit configuration of configurable amplifier Ch1. (SW10, SW11, SW12, SW13 = 1, 1, 1, 0) Set the input pins. (MPX11, MPX10, MPX21, MPX20 = 0, *, 1, 0) Specify the input mode. (IMS1 = *) Specify the amplifier operation mode. (CC11, CC10 = *, *) Specify the feedback resistance. (GC1 = **H) Set the output switches. (SW01 = 1) Start operation of configurable amplifier Ch1. (AMP1OF = 1) Operation starts Remark *: don't care Example of procedure for stopping configurable amplifier Ch1 (transimpedance amplifier) Operating Set PC1 register Stop operation of configurable amplifier Ch1. (AMP1OF = 0) Operation stops R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 45 of 117 RAA730300 2. Configurable Amplifiers Example of procedure for starting configurable amplifier Ch2 (transimpedance amplifier) Start Set CONFIG1 register Set MPX1 register Set IMS register Set AOMC register Set GC2 register Specify the circuit configuration of configurable amplifier Ch2. (SW20, SW21, SW22, SW23 = 1, 1, 1, 0) Set the input pins. (MPX31, MPX30, MPX41, MPX40 = 0, *, 1, 0) Specify the input mode. (IMS2 = *) Specify the amplifier operation mode. (CC21, CC20 = *, *) Specify the feedback resistance. (GC2 = **H) Set the output switches. (SW02 = 1) Set CONFIG2 register Set PC1 register Start operation of configurable amplifier Ch2. (AMP2OF = 1) Operation starts Remark *: don't care Example of procedure for stopping configurable amplifier Ch2 (transimpedance amplifier) Operating Set PC1 register Stop operation of configurable amplifier Ch2. (AMP2OF = 0) Operation stops R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 46 of 117 RAA730300 2. Configurable Amplifiers Example of procedure for starting configurable amplifier Ch3 (transimpedance amplifier) Start Set CONFIG2 register Set MPX2 register Set IMS register Set AOMC register Specify the circuit configuration of configurable amplifier Ch3. (SW30, SW31, SW32, SW33 = 1, 1, 1, 0) Set the input pins. (MP52, MPX51, MPX50, MPX62, MPX61, MPX60 = 0, 0, *, 1, 0, 0) Specify the input mode. (IMS3 = *) Specify the amplifier operation mode. (CC31, CC30 = *, *) Set GC3 register Specify the feedback resistance. (GC3 = **H) Set PC1 register Start operation of configurable amplifier Ch3. (AMP3OF = 1) Operation starts Remark *: don't care Example of procedure for stopping configurable amplifier Ch3 (transimpedance amplifier) Operating Set PC1 register Stop operation of configurable amplifier Ch3. (AMP3OF = 0) Operation stops R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 47 of 117 RAA730300 (5) 2. Configurable Amplifiers Procedure when using the amplifiers as a general-purpose operational amplifier When using the configurable amplifiers as general-purpose operational amplifiers, follow the procedures below to start and stop the amplifiers. Example of procedure for starting configurable amplifier Ch1 (general-purpose operational amplifier) Example of procedure for stopping configurable amplifier Ch1 (general-purpose operational amplifier) Operating Set PC1 register Stop operation of configurable amplifier Ch1. (AMP1OF = 0) Operation stops R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 48 of 117 RAA730300 2. Configurable Amplifiers Example of procedure for starting configurable amplifier Ch2 (general-purpose operational amplifier) Start Set CONFIG1 register Set MPX1 register Set IMS register Set AOMC register Specify the circuit configuration of configurable amplifier Ch2. (SW20, SW21, SW22, SW23 = 0, 1, 1, 0) Set the input pins. (MPX31, MPX30, MPX41, MPX40 = 0, *, 0, *) Specify the input mode. (IMS2 = *) Specify the amplifier operation mode. (CC21, CC20 = *, *) Set the output switches. (SW02 = 1) Set CONFIG2 register Set PC1 register Start operation of configurable amplifier Ch2. (AMP2OF = 1) Operation starts Remark *: don't care Example of procedure for stopping configurable amplifier Ch2 (general-purpose operational amplifier) Operating Set PC1 register Stop operation of configurable amplifier Ch2. (AMP2OF = 0) Operation stops R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 49 of 117 RAA730300 2. Configurable Amplifiers Example of procedure for starting configurable amplifier Ch3 (general-purpose operational amplifier) Start Set CONFIG2 register Set MPX2 register Set IMS register Specify the circuit configuration of configurable amplifier Ch3. (SW30, SW31, SW32, SW33 = 0, 1, 1, 0) Set the input pins. (MP52, MPX51, MPX50, MPX62, MPX61, MPX60 = 0, 0, *, 0, 0, *) Specify the input mode. (IMS3 = *) Set AOMC register Specify the amplifier operation mode. (CC31, CC30 = *, *) Set PC1 register Start operation of configurable amplifier Ch3. (AMP3OF = 1) Operation starts Remark *: don't care Example of procedure for stopping configurable amplifier Ch3 (general-purpose operational amplifier) Operating Set PC1 register Stop operation of configurable amplifier Ch3. (AMP3OF = 0) Operation stops R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 50 of 117 RAA730300 (6) 2. Configurable Amplifiers Procedure when using the amplifiers as an instrumentation amplifier When using the configurable amplifiers together as an instrumentation amplifier, follow the procedures below to start and stop the amplifier. Example of procedure for starting configurable amplifiers (instrumentation amplifier) Start Set CONFIG1 register Set CONFIG2 register Set MPX1 register Set MPX2 register Set IMS register Set AOMC register Specify the circuit configuration of configurable amplifier channels Ch1 and Ch2. (SW10, SW11, SW12, SW13, SW20, SW21, SW22, SW23 = 1, 0, 1, 0, 1, 0, 1, 0) Specify the circuit configuration and switches of configurable amplifier Ch3. (SW30, SW31, SW32, SW33, SW02, SW01, SW00 = 1, 0, 0, 1, 0, 0, 1) Set the input pins. of configurable amplifier channels Ch1 and Ch2. (MPX11, MPX10, MPX21, MPX20, MPX31, MPX30, MPX41, MPX40 = 1, 1, 0, *, 1, 1, 0, *) Set the input pins. of configurable amplifier Ch3. (MP52, MPX51, MPX50, MPX62, MPX61, MPX60 = 0, 1, 0, 0, 1, 1) Specify the input mode. (IMS3, IMS2, IMS1 = *, *, *) Specify the amplifier operation mode. (CC31, CC30, CC21, CC20, CC11, CC10 = *, *, *, *, *, *) Set GC1 register Specify the gain of configurable amplifier Ch1. (GC1 = 00H) Set GC2 register Specify the gain of configurable amplifier Ch2. (GC2 = 00H) Set GC3 register Specify the gain of configurable amplifier Ch3 (GC3 =**H) Set PC1 register Start operation of configurable amplifier channels Ch1 to Ch3. (AMP1OF, AMP2OF, AMP3OF = 1, 1, 1) Operation starts Remark *: don't care R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 51 of 117 RAA730300 2. Configurable Amplifiers Example of procedure for stopping configurable amplifiers (instrumentation amplifier) Operating Set PC1 register Stop operation of configurable amplifier channels Ch1 to Ch3. (AMP1OF, AMP2OF, AMP3OF = 0, 0, 0) Operation stops R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 52 of 117 RAA730300 3. General-Purpose Operational Amplifier 3. General-Purpose Operational Amplifier The RAA730300 has two on-chip general-purpose operational amplifier channels. <R> 3.1 Overview of General-Purpose Operational Amplifier Features The general-purpose operational amplifiers have the following features: * Includes an input mode switching function * Includes a power-off function. And also, the output signal from D/A converter Ch4 can be used as the reference voltage for a general-purpose operational amplifier Ch2. If D/A converter Ch4 is powered off, the external reference voltage is to be input to DAC4_OUT/VREFIN4 pin. For details about use of D/A converter, see 4. D/A Converter. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 53 of 117 RAA730300 3.2 3. General-Purpose Operational Amplifier Block Diagram Figure 3-1. Block Diagram of General-Purpose Operational Amplifier Ch1 AVDD1 AGND1 AMP4_INP + AMP4_INN - AMP4_OUT AMP4OF IMS4 Input mode control register (IMS) Power control register 1 (PC1) Internal bus Figure 3-2. <R> Block Diagram of General-Purpose Operational Amplifier Ch2 AVDD1 AGND1 AMP5_INP + AMP5_INN - AMP5_OUT DAC4_OUT/VREFIN4 SW53 8-bit DAC4 DAC4OF DACRC Power control register 1 (PC1) DAC reference voltage control register DAC4C IMS5 SW53 DAC control register 4 MPX setting register 3 (MPX3) AMP5OF Input mode control register (IMS) Power control register 2 (PC2) Internal bus R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 54 of 117 RAA730300 <R> 3.3 3. General-Purpose Operational Amplifier Registers Controlling the General-Purpose Operational Amplifier The general-purpose operational amplifier is controlled by the following 4 registers: * Power control register 1 (PC1) * Power control register 2 (PC2) * MPX setting register 3 (MPX3) * Input mode control register (IMS) (1) Power control register 1 (PC1) This register is used to enable or disable operation of the configurable amplifiers, general-purpose operational amplifiers, and D/A converters. Use this register to stop unused functions to reduce power consumption and noise. When using a general-purpose operational amplifier Ch1, be sure to set the control bit that corresponds to the channel (bit 3) to 1. Reset signal input clears this register to 00H. Address: 11H After reset: 00H R/W PC1 7 6 5 4 3 2 1 0 DAC4OF DAC3OF DAC2OF DAC1OF AMP4OF AMP3OF AMP2OF AMP1OF AMP4OF (2) Operation of general-purpose operational amplifier Ch1 0 Stop operation of general-purpose operational amplifier Ch1. 1 Enable operation of general-purpose operational amplifier Ch1. Power control register 2 (PC2) This register is used to enable or disable operation of the D/A converters, general-purpose operational amplifiers, the low-pass filter, high-pass filter, variable output voltage regulator, and temperature sensor. Use this register to stop unused functions to reduce power consumption and noise. When using general-purpose operational amplifier Ch2, be sure to set the control bit that corresponds to the channel (bit 4) to 1. Reset signal input clears this register to 00H. Address: 12H After reset: 00H R/W PC2 7 6 5 4 3 2 1 0 DAC7OF DAC6OF DAC5OF AMP5OF LPFOF HPFOF LDOOF TEMPOF AMP5OF Operation of general-purpose operational amplifier Ch2 0 Stop operation of general-purpose operational amplifier Ch2. 1 Enable operation of general-purpose operational amplifier Ch2. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 55 of 117 RAA730300 (3) 3. General-Purpose Operational Amplifier MPX setting register 3 (MPX3) This register is used to control MPX7, MPX8, MPX9, and MPX10. This register is used to turn on or off the reference voltage input to general-purpose operational amplifier Ch2. Reset signal input clears this register to 00H. Address: 05H After reset: 00H R/W MPX3 7 6 5 4 3 2 1 0 0 0 SCF2 SCF1 SCF0 SW53 MPX71 MPX70 SW53 0 Turn off SW53. 1 Turn on SW53. Remark (4) Control of SW53 Bits 7 and 6 can be set to 1, but this has no effect on the function. Input mode control register (IMS) This register is used to specify the input mode of the configurable amplifiers, general-purpose operational amplifiers, the low-pass filter, and high-pass filter. When using one of general-purpose operational amplifier channels Ch1 and Ch2, be sure to set the control bit that corresponds to the channel (bits 4 and 3). Address: 14H After reset: 00H R/W IMS 7 6 5 4 3 2 1 0 0 0 IMS6 IMS5 IMS4 IMS3 IMS2 IMS1 IMS5 Input mode of general-purpose operational amplifier Ch2 0 Rail-to-rail input mode 1 P-ch single-ended input mode IMS4 Input mode of general-purpose operational amplifier Ch1 0 Rail-to-rail input mode 1 P-ch single-ended input mode Remark Bits 7 and 6 can be set to 1, but this has no effect on the function. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 56 of 117 RAA730300 3.4 3. General-Purpose Operational Amplifier Procedure for Operating the General-Purpose Operational Amplifier Follow the procedures below to start and stop the general-purpose operational amplifier. Example of procedure for starting the general-purpose operational amplifier Ch1 Start Set IMS register Specify the input mode. (IMS4 = *) Set PC1 register Start operation of the general-purpose operational amplifier. (AMP4OF = 1) Operation starts Example of procedure for stopping the general-purpose operational amplifier Ch1 Operating Set PC1 register Stop operation of the general-purpose operational amplifier. (AMP4OF = 0) Operation stops R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 57 of 117 RAA730300 3. General-Purpose Operational Amplifier Example of procedure for starting the general-purpose operational amplifier Ch2 Start Set IMS register Specify the input mode. (IMS5 = *) Set PC2 register Start operation of the general-purpose operational amplifier. (AMP5OF = 1) Operation starts Example of procedure for stopping the general-purpose operational amplifier Ch2 Operating Set PC2 register Stop operation of the general-purpose operational amplifier. (AMP5OF = 0) Operation stops R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 58 of 117 RAA730300 4. D/A Converters 4. D/A Converters The RAA730300 has seven on-chip D/A converter channels. Channel D/A Converter Output Pins 1 to 4 Provided 5 to 7 Not provided Note Note Output pins are not provided although the channels are incorporated. <R> 4.1 Overview of D/A Converter Features The D/A converters are 8-bit resolution converters that convert digital input signals into analog signals. The D/A converters have the following features: * 8-bit resolution (x 7 ch: Ch1 to Ch7) * R-2R ladder method * Analog output voltage: Output voltage can be calculated with the equation shown below. Output voltage = {(Reference voltage upper limit - Reference voltage lower limit) x m/256} + Reference voltage lower limit (m = 0 to 255: Value set to DACnC register) * Controls the reference voltage for the configurable amplifier channels, general-purpose operational amplifier Ch2, low-pass filter, and high-pass filter * Includes a power-off function. Remark n = 1 to 7 R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 59 of 117 RAA730300 4.2 4. D/A Converters Block Diagram Figure 4-1. Block Diagram of D/A Converter Channels Ch1 to Ch4 AV DD1 Selector - AV DD1 + AGND1 8-bit DACn + DACn_OUT/VREFINn - Selector + DACnOF DACn7 D ACn 6 D ACn 5 DACn4 Power control register 1 (PC1) DACn3 DACn2 DACn1 D ACn 0 VRT1 VRT0 VRB1 VRB0 DAC reference voltage control register (DACRC) DAC control register n (DACnC) Internal bus Remark n = 1 to 4 Figure 4-2. Block Diagram of D/A Converter Channels Ch5 to Ch7 AV DD1 Selector - AV DD1 + AGND1 8-bit DACn + DACn_OUT output signal - Selector + DACnOF DACn7 D ACn 6 Power control register 2 (PC2) D ACn 5 DACn4 DACn3 DACn2 DACn1 D ACn 0 DAC control register n (DACnC) VRT1 VRT0 VRB1 VRB0 DAC reference voltage control register (DACRC) Internal bus Remark n = 5 to 7 R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 60 of 117 RAA730300 4.3 4. D/A Converters Registers Controlling the D/A Converters The D/A converters are controlled by the following 4 registers: * DAC reference voltage control register (DACRC) * DAC control registers 1, 2, 3, 4, 5, 6, 7 (DAC1C, DAC2C, DAC3C, DAC4C, DAC5C, DAC6C, DAC7C) * Power control register 1 (PC1) * Power control register 2 (PC2) <R> (1) DAC reference voltage control register (DACRC) This register is used to specify the upper (VRT) and lower (VRB) limits of the reference voltage for D/A converter channels Ch1 to Ch7. When selecting the upper limit of the reference voltage, use bits 3 and 2. When selecting the lower limit of the reference voltage, use bits 1 and 0. Reset signal input clears this register to 00H. Address: 0CH After reset: 00H R/W DACRC 7 6 5 4 3 2 1 0 0 0 0 0 VRT1 VRT0 VRB1 VRB0 VRT1 VRT0 Reference voltage upper limit (Typ.) 0 0 AVDD1 0 1 AVDD1 x 4/5 1 0 AVDD1 x 3/5 1 1 AVDD1 VRB1 VRB0 Reference voltage lower limit (Typ.) 0 0 AGND1 0 1 AVDD1 x 1/5 1 0 AVDD1 x 2/5 1 1 AGND1 Remark Bits 7 to 4 can be set to 1, but this has no effect on the function. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 61 of 117 RAA730300 (2) 4. D/A Converters DAC control registers 1, 2, 3, 4, 5, 6, 7 (DAC1C, DAC2C, DAC3C, DAC4C, DAC5C, DAC6C, DAC7C) This register is used to specify the analog voltage output from each D/A converter. The output signal from D/A converter can be used as the reference voltage for the configurable amplifier channels, general-purpose operational amplifier Ch2, low-pass filter, and high-pass filter. Reset signal input sets this register to 80H. Address: 0DH (n = 1), 0EH (n = 2), 0FH (n = 3), 10H (n = 4), 15H (n = 5), 16H (n = 6), 17H (n = 7) After reset: 80H R/W DACnC 7 6 5 4 3 2 1 0 DACn7 DACn6 DACn5 DACn4 DACn3 DACn2 DACn1 DACn0 Remark1. n = 1 to 7 2. To calculate the output voltage, see 4. 1 Overview of D/A converter features. (3) Power control register 1 (PC1) This register is used to enable or disable operation of the configurable amplifiers, the general-purpose operational amplifier, and the D/A converters. Use this register to stop unused functions to reduce power consumption and noise. When using one of D/A converter channels Ch1 to Ch4, be sure to set the control bit that corresponds to the channel (bits 7 to 4) to 1. Reset signal input clears this register to 00H. Address: 11H After reset: 00H R/W PC1 7 6 5 4 3 2 1 0 DAC4OF DAC3OF DAC2OF DAC1OF AMP4OF AMP3OF AMP2OF AMP1OF DAC4OF Operation of D/A converter Ch4 0 Stop operation of D/A converter Ch4. 1 Enable operation of D/A converter Ch4. DAC3OF Operation of D/A converter Ch3 0 Stop operation of D/A converter Ch3. 1 Enable operation of D/A converter Ch3. DAC2OF Operation of D/A converter Ch2 0 Stop operation of D/A converter Ch2. 1 Enable operation of D/A converter Ch2. DAC1OF Operation of D/A converter Ch1 0 Stop operation of D/A converter Ch1. 1 Enable operation of D/A converter Ch1. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 62 of 117 RAA730300 (4) 4. D/A Converters Power control register 2 (PC2) This register is used to enable or disable operation of the D/A converters, the general-purpose operational amplifier, lowpass filter, high-pass filter, variable output voltage regulator, and temperature sensor. Use this register to stop unused functions to reduce power consumption and noise. When using one of D/A converter channels Ch5 to Ch7, be sure to set the control bit that corresponds to the channel (bits 7 to 5) to 1. Reset signal input clears this register to 00H. Address: 12H After reset: 00H R/W PC2 7 6 5 4 3 2 1 0 DAC7OF DAC6OF DAC5OF AMP5OF LPFOF HPFOF LDOOF TEMPOF DAC7OF Operation of D/A converter Ch7 0 Stop operation of D/A converter Ch7. 1 Enable operation of D/A converter Ch7. DAC6OF Operation of D/A converter Ch6 0 Stop operation of D/A converter Ch6. 1 Enable operation of D/A converter Ch6. DAC5OF Operation of D/A converter Ch5 0 Stop operation of D/A converter Ch5. 1 Enable operation of D/A converter Ch5. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 63 of 117 RAA730300 4.4 4. D/A Converters Procedure for Operating the D/A Converters Follow the procedures below to start and stop the D/A converters. Example of procedure for starting the D/A converters Start Set DACRC register Set DACnC register Set PC1 register Specify the reference voltage upper and lower limits. (VRT1, VRT0, VRB1, VRB0 = *, *, *, *) Specify the analog voltage output to the DACn_OUT pin. (DACnC = **H) Start operation of the D/A converter. (DACnOF = 1) Operation starts Example of procedure for stopping the D/A converters Operating Set PC1 register Stop operation of the D/A converter. (DACnOF = 0) Operation stops Remark *: don't care n = 1 to 7 R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 64 of 117 RAA730300 4.5 4. D/A Converters Notes on Using D/A Converters Observe the following points when using the D/A converters: (1) Only a very small current can flow from the DACn_OUT pin because the output impedance of the D/A converters is high. If the load input impedance is low, insert a follower amplifier between the load and the DACn_OUT pin. Also, make sure that the wiring between the pin and the follower amplifier or load is as short as possible (because of the high output impedance). If it is not possible to keep the wiring short, take measures such as surrounding the pin with a ground pattern. (2) If inputting an external reference power supply to the VREFINn pin, be sure to set the DACnOF bit to 0. Remark n = 1 to 4 R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 65 of 117 RAA730300 5. Low-Pass Filter 5. Low-Pass Filter The RAA730300 has one on-chip switched-capacitor low-pass filter channel. <R> 5.1 Overview of Low-Pass Filter Features The low-pass filter has the following features: * Butterworth characteristics (Q value = 0.702) * Cutoff frequency (fc) range: 9 Hz to 900 Hz * External input clock frequency (fCLK_LPF) range: 2 x fC/0.0087 = 2 kHz to 200 kHz * Includes a power-off function. And also, the output signal from D/A converter Ch4 can be used as the reference voltage for low-pass filter. If D/A converter Ch4 is powered off, the external reference voltage is to be input to DAC4_OUT/VREFIN4 pin. For details about use of D/A converter, see 4. D/A Converter. Remarks 1. The internal control clock (fs) of the low-pass filter has a duty of 50%, so the external input clock is divided by two at the internal D flip-flop before being used for the low-pass filter. If the internal control clock frequency (fs) is 100 kHz, therefore, input a 200 kHz clock signal to the CLK_LPF pin. 2. The phase of the signal input to the low-pass filter inverts after passing through the low-pass filter. 5.2 Block Diagram AV DD3 AGND4 fs=fCLK_LPF/2 D fCLK_LPF CLK_LPF MPX7 CLK Q MPX8 SC_IN MPX9 Selector General-purpose operational amplifier Ch2 output signal Selector Selector Configurable amplifier Ch1 output signal Configurable amplifier Ch2 output signal Configurable amplifier Ch3 output signal Q - - + - + LPF_OUT + HPF_OUT MPX10 MPX10 8-bit DAC4 IMS6 MPX71 MPX70 Input mode control register (IMS) SCF2 SCF1 SCF0 MPX setting register 3 (MPX3) DAC4_OUT/VREFIN4 Source of general-purpose operational amplifier Ch1 non-inverted input SW53 DAC4OF DAC47 D AC4 6 Power control register 1 (PC1) D AC4 5 DAC44 DAC43 DAC42 DAC41 D AC4 0 DAC control register 4 (DAC4C) LPFOF VRT1 Power control register 2 (PC2) VRT0 VRB1 VRB0 DAC reference voltage control register (DACRC) Internal bus R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 66 of 117 RAA730300 5.3 5. Low-Pass Filter Registers Controlling the Low-Pass Filter The low-pass filter is controlled by the following 3 registers: * MPX setting register 3 (MPX3) * Power control register 2 (PC2) * Input mode control register (IMS) (1) MPX setting register 3 (MPX3) This register is used to control MPX7, MPX8, MPX9, and MPX10. When selecting the signal to be input to the filter circuits, use bits 5 and 4. When switching the order in which signals are processed by the low-pass and high-pass filters, use bit 3. When switching the output signal from MPX7, use bits 1 and 0. Reset signal input clears this register to 00H. Address: 05H After reset: 00H R/W MPX3 7 6 5 4 3 2 1 0 0 0 SCF2 SCF1 SCF0 SW53 MPX71 MPX70 SCF2 SCF1 0 0 SC_IN pin 0 1 MPX7 output signal 1 0 General-purpose operational amplifier Ch2 output signal 1 1 Setting prohibited SCF0 Source of input to filter circuits Specification of the order of filter signal processing 0 The MPX9 output signal passes the low-pass filter and then is input to the high-pass filter. 1 The MPX9 output signal passes the high-pass filter and then is input to the low-pass filter. MPX71 MPX70 0 0 Open pin 0 1 Configurable amplifier Ch1 output signal 1 0 Configurable amplifier Ch2 output signal 1 1 Configurable amplifier Ch3 output signal Remark Specification of MPX7 output signal Bits 7 and 6 can be set to 1, but this has no effect on the function. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 67 of 117 RAA730300 (2) 5. Low-Pass Filter Power control register 2 (PC2) This register is used to enable or disable operation of the D/A converters, general-purpose operational amplifiers, the low-pass filter, high-pass filter, variable output voltage regulator, and temperature sensor. Use this register to stop unused functions to reduce power consumption and noise. When using the low-pass filter, be sure to set bit 3 to 1. Reset signal input clears this register to 00H. Address: 12H After reset: 00H R/W PC2 7 6 5 4 3 2 1 0 DAC7OF DAC6OF DAC5OF AMP5OF LPFOF HPFOF LDOOF TEMPOF LPFOF (3) Operation of low-pass filter 0 Stop operation of the low-pass filter. 1 Enable operation of the low-pass filter. Input mode control register (IMS) This register is used to specify the input mode of the configurable amplifiers, general-purpose operational amplifiers, the low-pass filter, and high-pass filter. When using the low-pass filter or the high-pass filter, be sure to set the control bit that corresponds to the channel (bit 5). Reset signal input clears this register to 00H. Address: 14H After reset: 00H R/W IMS 7 6 5 4 3 2 1 0 0 0 IMS6 IMS5 IMS4 IMS3 IMS2 IMS1 IMS6 Input mode of low-pass filter and high-pass filter 0 Rail-to-rail input mode 1 P-ch single-ended input mode Remark Bits 7 and 6 can be set to 1, but this has no effect on the function. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 68 of 117 RAA730300 5.4 5. Low-Pass Filter Procedure for Operating the Low-Pass Filter Follow the procedures below to start and stop the low-pass filter. Example of procedure for starting the low-pass filter Start Set MPX3 register Set IMS register Select the filter input signal and signal processing route. (MPX71, MPX70, SCF2, SCF1, SCF0 = *, *, *, *, *) Specify the input mode. (IMS6 = *) Input control clock to CLK_LPF pin Set PC2 register Start operation of the high-pass filter. (LPFOF = 1) Operation starts Remark *: don't care Example of procedure for stopping the low-pass filter Operating Set PC2 register Stop operation of the low-pass filter. (LPFOF = 0) Operation stops R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 69 of 117 RAA730300 6. High-Pass Filter 6. High-Pass Filter The RAA730300 has one on-chip switched-capacitor high-pass filter channel. <R> 6.1 Overview of High-Pass Filter Features The high-pass filter has the following features: * Butterworth characteristics (Q value = 0.702) * Cutoff frequency (fc) range: 8 Hz to 800 Hz * External input clock frequency (fCLK_HPF) range: 2 x fC / 0.0074 = 2 kHz to 200 kHz * Includes a power-off function. And also, the output signal from D/A converter Ch4 can be used as the reference voltage for high-pass filter. If D/A converter Ch4 is powered off, the external reference voltage is to be input to DAC4_OUT/VREFIN4 pin. For details about use of D/A converter, see 4. D/A Converter. Remarks1. The internal control clock (fs) of the high-pass filter has a duty of 50%, so the external input clock is divided by two at the internal D flip-flop before being used for the low-pass filter. If the internal control clock frequency (fs) is 100 kHz, therefore, input a 200 kHz clock signal to the CLK_HPF pin. 2. 6.2 The phase of the signal input to the high-pass filter inverts after passing through the low-pass filter. Block Diagram AV DD3 CLK_HPF D Q CLK Q MPX10 LPF_OUT - Selector MPX8 output AGND4 fs - + - + HPF_OUT + 8-bit DAC4 Input mode control register (IMS) SW53 DAC4OF SCF0 IMS6 MPX9 MPX setting register 3 (MPX3) DAC4_OUT/VREFIN4 Source of general-purpose operational amplifier Ch2 non-inverted input DAC47 D AC4 6 Power control register 1 (PC1) D AC4 5 DAC44 DAC43 DAC42 DAC41 D AC4 0 DAC control register 4 (DAC4C) HPFOF VRT1 Power control register 2 (PC2) VRT0 VRB1 VRB0 DAC reference voltage control register (DACRC) Internal bus R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 70 of 117 RAA730300 6.3 6. High-Pass Filter Registers Controlling the High-Pass Filter The high-pass filter is controlled by the following 3 registers: * MPX setting register 3 (MPX3) * Power control register 2 (PC2) * Input mode control register (IMS) <R> (1) MPX setting register 3 (MPX3) This register is used to control MPX7, MPX8, MPX9, and MPX10. When selecting the signal to be input to the filter circuits, use bits 5 and 4. When switching the order in which signals are processed by the low-pass and high-pass filters, use bit 3. When switching the output signal from MPX7, use bits 1 and 0. Reset signal input clears this register to 00H. Address: 05H After reset: 00H R/W MPX3 7 6 5 4 3 2 1 0 0 0 SCF2 SCF1 SCF0 SW53 MPX71 MPX70 SCF2 SCF1 0 0 SC_IN pin 0 1 MPX7 output signal 1 0 General-purpose operational amplifier Ch2 output signal 1 1 Setting prohibited SCF0 Source of input to filter circuits Specification of the order of filter signal processing 0 The MPX9 output signal passes the low-pass filter and then is input to the high-pass filter. 1 The MPX9 output signal passes the high-pass filter and then is input to the low-pass filter. MPX71 MPX70 0 0 Open pin 0 1 Configurable amplifier Ch1 output signal 1 0 Configurable amplifier Ch2 output signal 1 1 Configurable amplifier Ch3 output signal Remark Specification of MPX7 output signal Bits 7 and 6 can be set to 1, but this has no effect on the function. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 71 of 117 RAA730300 (2) 6. High-Pass Filter Power control register 2 (PC2) This register is used to enable or disable operation of the D/A converters, general-purpose operational amplifiers, the low-pass filter, high-pass filter, variable output voltage regulator, and temperature sensor. Use this register to stop unused functions to reduce power consumption and noise. When using the high-pass filter, be sure to set bit 2 to 1. Reset signal input clears this register to 00H. Address: 12H After reset: 00H R/W PC2 7 6 5 4 3 2 1 0 DAC7OF DAC6OF DAC5OF AMP5OF LPFOF HPFOF LDOOF TEMPOF HPFOF (3) Operation of high-pass filter 0 Stop operation of the high-pass filter. 1 Enable operation of the high-pass filter. Input mode control register (IMS) This register is used to specify the input mode of the configurable amplifiers, general-purpose operational amplifiers, the low-pass filter, and high-pass filter. When using the low-pass filter or the high-pass filter, be sure to set the control bit that corresponds to the channel (bit 5). Reset signal input clears this register to 00H. Address: 14H After reset: 00H R/W IMS 7 6 5 4 3 2 1 0 0 0 IMS6 IMS5 IMS4 IMS3 IMS2 IMS1 IMS6 Input mode of low-pass filter and high-pass filter 0 Rail-to-rail input mode 1 P-ch single-ended input mode Remark Bits 7 and 6 can be set to 1, but this has no effect on the function. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 72 of 117 RAA730300 6.4 6. High-Pass Filter Procedure for Operating the High-Pass Filter Follow the procedures below to start and stop the high-pass filter. Example of procedure for starting the high-pass filter Start Set MPX3 register Set IMS register Select the signal processing route. (SCF0 = *) Specify the input mode. (IMS6 = *) Input control clock to CLK_HPF pin Set PC2 register Start operation of the high-pass filter. (HPFOF = 1) Operation starts Remark *: don't care Example of procedure for stopping the high-pass filter Operating Set PC2 register Stop operation of the high-pass filter. (HPFOF = 0) Operation stops R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 73 of 117 RAA730300 7. Temperature Sensor 7. Temperature Sensor The RAA730300 has one on-chip temperature sensor channel. 7.1 Overview of Temperature Sensor Features The temperature sensor has the following features: * Output voltage temperature coefficient: -4 mV/C (Typ.) * Includes a power-off function. 7.2 Block Diagram AVDD2 AVDD2 AGND3 + TEMP_OUT - TEMPOF Power control register 2 (PC2) Internal bus R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 74 of 117 RAA730300 7.3 7. Temperature Sensor Registers Controlling the Temperature Sensor The temperature sensor is controlled by power control register 2 (PC2). (1) Power control register 2 (PC2) This register is used to enable or disable operation of the D/A converters, general-purpose operational amplifiers, the low-pass filter, high-pass filter, variable output voltage regulator, and temperature sensor. Use this register to stop unused functions to reduce power consumption and noise. When selecting the signal to be input to the temperature sensor, be sure to set bit 0 to 1. Reset signal input clears this register to 00H. Address: 12H After reset: 00H R/W PC2 7 6 5 4 3 2 1 0 DAC7OF DAC6OF DAC5OF AMP5OF LPFOF HPFOF LDOOF TEMPOF TEMPOF Operation of temperature sensor 0 Stop operation of the temperature sensor. 1 Enable operation of the temperature sensor. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 75 of 117 RAA730300 7.4 7. Temperature Sensor Procedure for Operating the Temperature Sensor Follow the procedures below to start and stop the temperature sensor. Example of procedure for starting the temperature sensor Start Set PC2 register Start operation of the temperature sensor. (TEMPOF = 1) Operation starts Example of procedure for stopping the temperature sensor Operating Set PC2 register Stop operation of the temperature sensor. (TEMPOF = 0) Operation stops R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 76 of 117 RAA730300 8. Variable Output Voltage Regulator 8. Variable Output Voltage Regulator The RAA730300 has one on-chip variable output voltage regulator channel. This is a series regulator that generates a voltage of 1.8 V (default) from a supplied voltage of 3 V. 8.1 Overview of Variable Output Voltage Regulator Features The variable output voltage regulator has the following features: * Output voltage range: 1.8 to 3.1 V (Typ.) * Output current: * Includes a power-off function. 8.2 15 mA (Max.) Block Diagram AVDD2 AVDD2 BGR AGND3 + LDO_OUT LDOOF LDO3 Power control register 2 (PC2) LDO2 LDO1 LDO0 LDO control register (LDOC) Internal bus R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 77 of 117 RAA730300 8.3 8. Variable Output Voltage Regulator Registers Controlling the Variable Output Voltage Regulator The variable output voltage regulator is controlled by the following 2 registers: * LDO control register (LDOC) * Power control register 2 (PC2) (1) LDO control register (LDOC) This register is used to specify the output voltage of the variable output voltage regulator. Reset signal input clears this register to 00H. Address: 0BH After reset: 00H R/W LDOC 7 6 5 4 3 2 1 0 0 0 0 0 LDO3 LDO2 LDO1 LDO0 LDO3 LDO2 LDO1 LDO0 0 0 0 0 1.8 V 0 0 0 1 1.9 V 0 0 1 0 2.0 V 0 0 1 1 2.1 V 0 1 0 0 2.2 V 0 1 0 1 2.3 V 0 1 1 0 2.4 V 0 1 1 1 2.5 V 1 0 0 0 2.6 V 1 0 0 1 2.7 V 1 0 1 0 2.8 V 1 0 1 1 2.9 V 1 1 0 0 3.0 V 1 1 0 1 3.1 V Other than above Output Voltage of Variable Output Voltage Note Regulator (Typ.) Setting prohibited Note Output voltage is determined in consideration of dropout voltage. Remark Bits 7 to 4 can be set to 1, but this has no effect on the function. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 78 of 117 RAA730300 (2) 8. Variable Output Voltage Regulator Power control register 2 (PC2) This register is used to enable or disable operation of the D/A converters, general-purpose operational amplifiers, the low-pass filter, high-pass filter, variable output voltage regulator, and temperature sensor. Use this register to stop unused functions to reduce power consumption and noise. When using the variable output voltage regulator, be sure to set bit 1 to 1. Reset signal input clears this register to 00H. Address: 12H After reset: 00H R/W PC2 7 6 5 4 3 2 1 0 DAC7OF DAC6OF DAC5OF AMP5OF LPFOF HPFOF LDOOF TEMPOF LDOOF Operation of variable output voltage regulator 0 Stop operation of the variable output voltage regulator. 1 Enable operation of the variable output voltage regulator. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 79 of 117 RAA730300 8.4 8. Variable Output Voltage Regulator Procedure for Operating the Variable Output Voltage Regulator Follow the procedures below to start and stop the variable output voltage regulator. Example of procedure for starting the variable output voltage regulator Start Set LDOC register Set PC2 register Select the output voltage value. (LDOC = **H) Start operation of the variable output voltage regulator. (LDOOF = 1) Operation starts Remark *: don't care Example of procedure for stopping the variable output voltage regulator Operating Set PC2 register Stop operation of the variable output voltage regulator. (LDOOF = 0) Operation stops R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 80 of 117 RAA730300 9. SPI 9. SPI 9.1 Overview of SPI Features The SPI is used to allow control from external devices by using clocked communication via four lines: a serial clock line (SCLK), two serial data lines (SDI and SDO), and a chip select input line (CS). Data transmission/reception: * 16-bit data unit * MSB first Figure 9-1. Microcontroller Master SPI Configuration Example RAA730300 Slave 1 SPI SPI SCK SCLK SDI SDO SDO Port SDI CS Port Slave 2 SPI SCLK SDO SDI CS <R> Caution After turning on DVDD, be sure to generate external reset by inputting a reset signal to RESET pin before starting SPI communication. For details, see 10 Reset. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 81 of 117 RAA730300 9.2 9. SPI SPI Communication The SPI transmits and receives data in 16-bit units. Data can be transmitted and received when CS is low. Data is transmitted one bit at a time in synchronization with the falling edge of the serial clock, and is received one bit at a time in synchronization with the rising edge of the serial clock. When the R/W bit is 1, data is written to the SPI control register in accordance with the address/data setting after the 16th rising edge of SCLK has been detected following the fall of CS. The operation specified by the data is then executed. When the R/W bit is 0, the data is output from the register in accordance with the address/data setting in synchronization with the 9th and later falling edges of SCLK following the fall of CS. Figure 9-2. SPI Communication Timing CS SCLK R/W = 0, slave output data (register read) SDO D7 Read/write and address data SDI R/W A6 A5 A4 A3 Rising edge: Data sampling R/W data is latched R02DS0011EJ0110 Rev.1.10 May. 31, 2014 A2 D6 D5 D4 D3 D2 D1 D0 R/W = 1, slave input data (register write) A1 A0 D7 D6 D5 D4 D3 D2 D1 Falling edge: Transmission data is shifted by 1 bit D0 R/W = 1 and data is latched The R/W bit and the address data bits (A6 to A0) are latched. Page 82 of 117 RAA730300 9. Table 9-1. Address SPI Control Registers SPI Control Register R/W After Reset 00H Configuration register 1 (CONFIG1) R/W 88H 01H Configuration register 2 (CONFIG2) R/W 80H 03H MPX setting register 1 (MPX1) R/W 00H 04H MPX setting register 2 (MPX2) R/W 00H 05H MPX setting register 3 (MPX3) R/W 00H 06H Gain control register 1 (GC1) R/W 00H 07H Gain control register 2 (GC2) R/W 00H 08H Gain control register 3 (GC3) R/W 00H 09H AMP operation mode control register (AOMC) R/W 00H 0BH LDO control register (LDOC) R/W 00H 0CH DAC reference voltage control register (DACRC) R/W 00H 0DH DAC control register 1 (DAC1C) R/W 80H 0EH DAC control register 2 (DAC2C) R/W 80H 0FH DAC control register 3 (DAC3C) R/W 80H 10H DAC control register 4 (DAC4C) R/W 80H 11H Power control register 1 (PC1) R/W 00H 12H Power control register 2 (PC2) R/W 00H 13H Reset control register (RC) R/W 14H Input mode control register (IMS) R/W 00H 15H DAC control register 5 (DAC5C) R/W 80H 16H DAC control register 6 (DAC6C) R/W 80H 17H DAC control register 7 (DAC7C) R/W 80H Note SPI 00H Note The reset control register (RC) is not initialized to 00H by generating internal reset of the reset control register (RC). For details, see 10. Reset. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 83 of 117 RAA730300 <R> 10. Reset 10. Reset 10.1 Overview of Reset Feature The RAA730300 has an on-chip reset function. The SPI control registers are initialized by reset. A reset can be generated in the following two ways: * External reset by inputting an external reset signal to the RESET pin * Internal reset by writing 1 to the RESET bit of the reset control register (RC) The functions of the external reset and the internal reset are described below. * After turning on DVDD, be sure to generate external reset by inputting a reset signal to RESET pin before starting SPI communication. * During reset, each function is shifted to the status shown in Table 10-1. The status of each SPI control register after reset has been acknowledged is shown in Table 10-2. After reset, the status of each pin is shown in Table 10-3. * External reset is generated when a low-level signal is input to the RESET pin. On the other hand, internal reset is generated when 1 is written to the RESET bit of the reset control register (RC). * External reset is subsequently cancelled by inputting a high-level signal to RESET pin after a low-level signal is input to this pin. On the other hand, internal reset is subsequently cancelled by writing 0 to the RESET bit of the reset control register (RC) after 1 is written to the same bit of this register. Caution When generating an external reset, input a low-level signal to the RESET pin for at least 10 s. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 84 of 117 RAA730300 10. Reset Table 10-1. Statuses During Reset Function Block Internal Reset External Reset from RESET Pin by Reset Control Register (RC) Configurable amplifier Operation stops. General-purpose operational amplifier Operation stops. D/A converter Operation stops. Low-pass filter Operation stops. High-pass filter Operation stops. Temperature sensor Operation stops. Variable output voltage regulator Operation stops. SPI Operation stops. Operation is enabled. Table 10-2. Statuses of SPI Control Registers After a Reset Is Acknowledged Address SPI Control Register Status After a Reset Is Acknowledged External Reset Internal Reset 00H Configuration register 1 (CONFIG1) 88H 88H 01H Configuration register 2 (CONFIG2) 80H 80H 03H MPX setting register 1 (MPX1) 00H 00H 04H MPX setting register 2 (MPX2) 00H 00H 05H MPX setting register 3 (MPX3) 00H 00H 06H Gain control register 1 (GC1) 00H 00H 07H Gain control register 2 (GC2) 00H 00H 08H Gain control register 3 (GC3) 00H 00H 09H AMP operation mode control register (AOMC) 00H 00H 0BH LDO control register (LDOC) 00H 00H 0CH DAC reference voltage control register (DACRC) 00H 00H 0DH DAC control register 1 (DAC1C) 80H 80H 0EH DAC control register 2 (DAC2C) 80H 80H 0FH DAC control register 3 (DAC3C) 80H 80H 10H DAC control register 4 (DAC4C) 80H 80H 11H Power control register 1 (PC1) 00H 00H 12H Power control register 2 (PC2) 00H 00H 13H Reset control register (RC) 00H 01H 14H Input mode control register (IMS) 00H 00H 15H DAC control register 5 (DAC5C) 80H 80H 16H DAC control register 6 (DAC6C) 80H 80H 17H DAC control register 7 (DAC7C) 80H 80H Note Note The reset control register (RC) is not initialized by generating internal reset of the reset control register (RC), but it can be done to 00H by generating external reset from RESET pin or by writing 0 to the RESET bit of the reset control register (RC). R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 85 of 117 RAA730300 10. Reset Table 10-3. Pin Statuses After a Reset Pin Name Internal Reset External Reset from RESET Pin by Reset Control Register (RC) SC_IN Hi-Z Hi-Z AMP5_OUT Hi-Z Hi-Z AMP5_INN Hi-Z Hi-Z AMP5_INP Hi-Z Hi-Z MPXIN61 Hi-Z Hi-Z MPXIN51 Hi-Z Hi-Z MPXIN60 Hi-Z Hi-Z MPXIN50 Hi-Z Hi-Z AMP3_OUT Hi-Z Hi-Z DAC3_OUT/VREFIN3 Hi-Z Hi-Z AMP2_OUT Hi-Z Hi-Z AMP1_OUT Hi-Z Hi-Z DAC2_OUT/VREFIN2 Hi-Z Hi-Z DAC1_OUT/VREFIN1 Hi-Z Hi-Z MPXIN41 Hi-Z Hi-Z MPXIN31 Hi-Z Hi-Z MPXIN40 Hi-Z Hi-Z MPXIN30 Hi-Z Hi-Z MPXIN21 Hi-Z Hi-Z MPXIN11 Hi-Z Hi-Z MPXIN20 Hi-Z Hi-Z MPXIN10 Hi-Z Hi-Z LDO_OUT Pull-down Pull-down AMP4_OUT Hi-Z Hi-Z AMP4_INN Hi-Z Hi-Z AMP4_INP Hi-Z Hi-Z TEMP_OUT Pull down Pull down SCLK Pull-up input Hi-Z SDO Pull-up Hi-Z SDI Pull-up input Hi-Z CS Pull-up input Hi-Z DAC4_OUT/VREFIN4 Hi-Z Hi-Z HPF_OUT Hi-Z Hi-Z CLK_HPF Pull-down input Pull-down input CLK_LPF Pull-down input Pull-down input LPF_OUT Hi-Z Hi-Z R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 86 of 117 RAA730300 10.2 (1) 10. Reset Registers Controlling the Reset Feature Reset control register (RC) This register is used to control the reset feature. An internal reset can be generated by writing 1 to the RESET bit. The reset control register (RC) is initialized to 00H by generating external reset from RESET pin or by writing 0 to the RESET bit of the reset control register (RC). Note Address: 13H After reset: 00H RC R/W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 RESET RESET Reset request by internal reset signal 0 Do not make a reset request by using the internal reset signal, or cancel the reset. 1 Make a reset request by using the internal reset signal, or the reset signal is currently being input. Note The reset control register (RC) is not initialized by generating internal reset of the reset control register (RC), but it can be done to 00H by generating external reset from RESET pin or by writing 0 to the RESET bit of the reset control register (RC). Caution When the RESET bit is 1, writing to any register other than the reset control register (RC) is ignored. Initializing the reset control register (RC) to 00H by external reset, or writing 0 to the RESET bit enable writing to all the registers. Remark Bits 7 to 1 are fixed at 0 of read only. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 87 of 117 RAA730300 11. Electrical Specifications 11. Electrical Specifications 11.1 Absolute Maximum Ratings (TA = 25C) Parameter Power supply voltage Input voltage Output voltage Output current <R> Symbol Conditions Ratings Unit AVDD AVDD1, AVDD2, AVDD3 -0.3 to +4.0 V DVDD DVDD -0.3 to +4.0 V AGND AGND1, AGND2, AGND3, AGND4 -0.3 to +0.3 V DGND DGND -0.3 to +0.3 V Note V VI1 MPXIN10, MPXIN11, MPXIN20, MPXIN21, MPXIN30, MPXIN31, MPXIN40, MPXIN41, MPXIN50, MPXIN51, MPXIN60, MPXIN61, SC_IN, VREFIN1, VREFIN2, VREFIN3, VREFIN4, AMP4_INN, AMP4_INP, AMP5_INN, AMP5_INP, CLK_LPF, CLK_HPF, RESET -0.3 to AVDD + 0.3 VI2 SCLK, SDI, CS -0.3 to DVDD + 0.3 Note V Note V Note V VO1 LDO_OUT, BGR_OUT, AMP1_OUT, AMP2_OUT, AMP3_OUT, AMP4_OUT, AMP5_OUT, LPF_OUT, HPF_OUT, DAC1_OUT, DAC2_OUT, DAC3_OUT, DAC4_OUT, TEMP_OUT, LDO_OUT -0.3 to AVDD + 0.3 VO2 SDO -0.3 to DVDD + 0.3 IO1 AMP1_OUT, AMP2_OUT, AMP3_OUT, AMP4_OUT, AMP5_OUT, LPF_OUT, HPF_OUT, DAC1_OUT, DAC2_OUT, DAC3_OUT, DAC4_OUT, TEMP_OUT 1 mA IO2 SDO 4 mA ILDOOUT LDO_OUT 15 mA Operating ambient temperature TA -40 to +105 C Storage temperature Tstg -40 to +125 C Note Must be 4.0 V or lower. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 88 of 117 RAA730300 <R> 11.2 11. Electrical Specifications Operating Condition Parameter Power supply Symbol VDDOP Conditions AVDD1, AVDD2, AVDD3, DVDD Ratings Unit MIN TYP MAX 2.2 - 3.6 V -40 - +105 C voltage Range Operating temperature Range TOP R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 89 of 117 RAA730300 11.3 11. Electrical Specifications Supply Current Characteristics (-40C TA 105C, AVDD1 = AVDD2 = AVDD3 = DVDD = 3.0 V) Parameter Supply current Note Symbol Note Istby11 Conditions PC1 = 00H, PC2 = 00H Ratings Unit MIN TYP MAX TA = 25C - 0.11 0.35 A TA = 85C - 0.75 5 A TA = 105C - 1.80 10 A Note Im111 PC1 = 47H, PC2 = 03H (configurable amplifier channels Ch1 to Ch3, D/A converter Ch3 (instrumentation amplifier), variable output voltage regulator, and temperature sensor are operating), CCn1, CCn0 = 0, 0 - 1.25 1.90 mA Im112Note PC1 = 7FH, PC2 = 13H (configurable amplifier channels Ch1 to Ch3, general-purpose operational amplifier channels Ch1 to Ch2, D/A converter channels Ch5 to Ch7, variable output voltage regulator, and temperature sensor are operating), CCn1, CCn0 = 0, 0 - 2.10 3.15 mA Im113Note PC1 = FFH, PC2 = 1FH (configurable amplifier channels Ch1 to Ch3, general-purpose operational amplifier channels Ch1 to Ch2, D/A converter channels Ch4 to Ch7, low-pass filter, high-pass filter, variable output voltage regulator, and temperature sensor are operating), CCn1, CCn0 = 0, 0 - 3.70 5.60 mA Im114Note PC1 = FFH, PC2 = FFH (configurable amplifier channels Ch1 to Ch3, general-purpose operational amplifier channels Ch1 to Ch2, D/A converter channels Ch1 to Ch7, low-pass filter, high-pass filter, variable output voltage regulator, and temperature sensor are operating), CCn1, CCn0 = 0, 0 - 4.15 6.25 mA Im121Note PC1 = 47H, PC2 = 03H (configurable amplifier channels Ch1 to Ch3, D/A converter Ch3 (instrumentation amplifier), variable output voltage regulator, and temperature sensor are operating), CCn1, CCn0 = 1, 1 - 0.60 0.90 mA Im122Note PC1 = 7FH, PC2 = 13H (configurable amplifier channels Ch1 to Ch3, general-purpose operational amplifier channels Ch1 to Ch2, D/A converter channels Ch5 to Ch7, variable output voltage regulator, and temperature sensor are operating), CCn1, CCn0 = 1, 1 - 1.45 2.20 mA Im123Note PC1 = FFH, PC2 = 1FH (configurable amplifier channels Ch1 to Ch3, general-purpose operational amplifier channels Ch1 to Ch2, D/A converter channels Ch4 to Ch7, low-pass filter, high-pass filter, variable output voltage regulator, and temperature sensor are operating), CCn1, CCn0 = 1, 1 - 3.10 4.65 mA Im124Note PC1 = FFH, PC2 = FFH (configurable amplifier channels Ch1 to Ch3, general-purpose operational amplifier channels Ch1 to Ch2, D/A converter channels Ch1 to Ch7, low-pass filter, high-pass filter, variable output voltage regulator, and temperature sensor are operating), CCn1, CCn0 = 1, 1 - 3.50 5.25 mA Total current flowing to internal power supply pins AVDD1, AVDD2, AVDD3, and DVDD. Current flowing through the pull-up resistor is not included. The input leakage current flowing when the level of the input pin is fixed to AVDD1, AVDD2, AVDD3 or DVDD, or AGND1, AGND2, AGND3, AGND4, or DGND is included. See the table below to check the definition of those symbols of the current flowing. Remark n = 1 to 3 R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 90 of 117 RAA730300 11. Electrical Specifications Analog function with power on GeneralParameter Configurable purpose amplifier Variable Low- High- operational pass pass amplifier filter filter D/A converter Symbol Temperature output sensor voltage regulator Ch1 Ch2 Ch3 Ch1 Ch2 Ch1 Ch2 Ch3 Ch4 Ch5 Ch6 Ch7 Im111Note1 ON ON ON - - - - ON - - - - - - ON ON Note1 ON ON ON ON ON - - - - ON ON ON - - ON ON Im113 Note1 ON ON ON ON ON - - - ON ON ON ON ON ON ON ON Supply Im114 Note1 ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON current Im121 Note2 ON ON ON - - - - ON - - - - - - ON ON Im122 Note2 ON ON ON ON ON - - - - ON ON ON - - ON ON Note2 ON ON ON ON ON - - - ON ON ON ON ON ON ON ON Im124 Note2 ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON Im112 Im123 Note1. CCn1, CCn0 = 0, 0 2. CCn1, CCn0 = 1, 1 R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 91 of 117 RAA730300 11.4 (1) 11. Electrical Specifications Electrical Specifications of Each Block Configurable amplifier block characteristics (-40C TA 105C, AVDD1 = AVDD2 = AVDD3 = DVDD = 3.0 V, VREFIN1 = VREFIN2 = VREFIN3 = 1.5 V, AMP1OF = AMP2OF = AMP3OF = 1, DAC1OF = DAC2OF = DAC3OF = 0, non-inverting amplifier) Parameter Current consumption Note Input voltage 1 Input voltage 2 Output voltage Settling time Gain bandwidth Symbol Conditions Ratings Unit MIN TYP MAX Icc00 CCn1, CCn0 = 0, 0 - 330 500 A Icc01 CCn1, CCn0 = 0, 1 - 250 380 A Icc10 CCn1, CCn0 = 1, 0 - 170 260 A Icc11 CCn1, CCn0 = 1, 1 - 90 150 A VINL1 IMSn = 0 AGND1 - 0.05 - - V VINH1 IMSn = 0 - - AVDD1 + 0.1 V VINL2 IMSn = 1 AGND1 - 0.05 - - V VINH2 IMSn = 1 - - AVDD1 - 1.4 V VOUTL IOL = -200 A - - AGND1 + 0.1 V VOUTH IOH = 200 A AVDD1 - 0.1 - - V tSET_AMP00 GCn = 00H (9.5 dB), CCn1, CCn0 = 0, 0, CL = 30 pF, output voltage = 1VPP, output convergence voltage VPP = 999 mV - - 8 s tSET_AMP01 GCn = 00H (9.5 dB), CCn1, CCn0 = 0, 1, CL = 30 pF, output voltage = 1VPP, output convergence voltage VPP = 999 mV - - 10 s tSET_AMP10 GCn = 00H (9.5 dB), CCn1, CCn0 = 1, 0, CL = 30 pF, output voltage = 1VPP, output convergence voltage VPP = 999 mV - - 16 s tSET_AMP11 GCn = 00H (9.5 dB), CCn1, CCn0 = 1, 1, CL = 30 pF, output voltage = 1VPP, output convergence voltage VPP = 999 mV - - 42 s GBW00 CLMAX = 30 pF, CCn1, CCn0 = 0, 0 - 1.35 - MHz - 1.1 - MHz - 0.75 - MHz - 0.4 - MHz - 67 - nV/ Hz GCn = 11H (40.1 dB) GBW01 CLMAX = 30 pF, CCn1, CCn0 = 0, 1 GCn = 11H (40.1 dB) GBW10 CLMAX = 30 pF, CCn1, CCn0 = 1, 0 GCn = 11H (40.1 dB) GBW11 CLMAX = 30 pF, CCn1, CC0 = 1, 1 En00 CCn1, CCn0 = 0, 0 GCn = 11H (40.1 dB) Equivalent input noise f = 1 kHz, GCn = 11H (40.1 dB) En01 CCn1, CCn0 = 0, 1 f = 1 kHz, GCn = 11H (40.1 dB) - 75 - nV/ Hz En10 CCn1, CCn0 = 1, 0 f = 1 kHz, GCn = 11H (40.1 dB) - 110 - nV/ Hz En11 CCn1, CCn0 = 1, 1 f = 1 kHz, GCn = 11H (40.1 dB) - 145 - nV/ Hz Note These are the values for one channel of configurable amplifier. Remark n = 1 to 3 R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 92 of 117 RAA730300 11. Parameter Input conversion offset voltage Input conversion offset voltage temperature coefficient Slew rate Symbol Conditions Electrical Specifications Ratings Unit MIN TYP MAX VOFF1 CCn1, CCn0 = 0, 0, TA = 25C GCn = 0AH (26.4 dB) -7 - 7 mV VOFF2 CCn1, CCn0 = 0, 1, TA = 25C GCn = 0AH (26.4 dB) -10 - 10 mV VOFF3 CCn1, CCn0 = 1, 0, TA = 25C GCn = 0AH (26.4 dB) -10 - 10 mV VOFF4 CCn1, CCn0 = 1, 1, TA = 25C GCn = 0AH (26.4 dB) -12 - 12 mV VOTC00 CCn1, CCn0 = 0, 0 - 3.5 - V/ VOTC01 CCn1, CCn0 = 0, 1 - 3.5 - V/ VOTC10 CCn1, CCn0 = 1, 0 - 4.0 - V/ VOTC11 CCn1, CCn0 = 1, 1 - 4.5 - V/ SR00 CCn1, CCn0 = 0, 0, CL = 30 pF - 1.1 - V/s - 0.8 - V/s - 0.5 - V/s - 0.25 - V/s GCn = 00H (9.5 dB) SR01 CCn1, CCn0 = 0, 1, CL = 30 pF GCn = 00H (9.5 dB) SR10 CCn1, CCn0 = 1, 0, CL = 30 pF GCn = 00H (9.5 dB) SR11 CCn1, CCn0 = 1, 1, CL = 30 pF GCn = 00H (9.5 dB) Power supply rejection ratio Gain setting error PSRR00 CCn1, CCn0 = 0, 0, GCn = 00H (9.5 dB) , f = 1 KHz - 80 - dB PSRR01 CCn1, CCn0 = 0, 1, GCn = 00H (9.5 dB) , f = 1 KHz - 80 - dB PSRR10 CCn1, CCn0 = 1, 0, GCn = 00H (9.5 dB) , f = 1 KHz - 75 - dB PSRR11 CCn1, CCn0 = 1, 1, GCn = 00H (9.5 dB) , f = 1 KHz - 75 - dB GAIN_Accu1 TA = 25C -0.6 - 0.6 dB GAIN_Accu2 TA = -40 to 105C -1.0 - 1.0 dB Remark n = 1 to 3 R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 93 of 117 RAA730300 11. Electrical Specifications (-40C TA 105C, AVDD1 = AVDD2 = AVDD3 = DVDD = 3.0 V, VREFIN1 = VREFIN2 = VREFIN3 = 1.5 V, AMP1OF = AMP2OF = AMP3OF = 1, DAC1OF = DAC2OF = DAC3OF, inverting amplifier) Parameter Current consumption Note Input voltage 1 Input voltage 2 Output voltage Settling time Gain bandwidth Symbol Conditions Ratings Unit MIN TYP MAX Icc100 CCn1, CCn0 = 0, 0 - 330 500 A Icc101 CCn1, CCn0 = 0, 1 - 250 380 A Icc110 CCn1, CCn0 = 1, 0 - 170 260 A Icc111 CCn1, CCn0 = 1, 1 - 90 150 A VINL1 IMSn = 0 AGND1 - 0.05 - - V VINH1 IMSn = 0 - - AVDD1 + 0.1 V VINL2 IMSn = 1 AGND1 - 0.05 - - V VINH2 IMSn = 1 - - AVDD1 - 1.4 V VOUTL IOL = -200 A - - AGND1 + 0.1 V VOUTH IOH = 200 A AVDD1 - 0.1 - - V tSET_AMP00 GCn = 00H (6 dB), CCn1, CCn0 = 0, 0, CL = 30 pF, output voltage = 1VPP, output convergence voltage VPP = 999 mV - - 8 s tSET_AMP01 GCn = 00H (6 dB), CCn1, CCn0 = 0, 1, CL = 30 pF, output voltage = 1VPP, output convergence voltage VPP = 999 mV - - 10 s tSET_AMP10 GCn = 00H (6 dB), CCn1, CCn0 = 1, 0, CL = 30 pF, output voltage = 1VPP, output convergence voltage VPP = 999 mV - - 16 s tSET_AMP11 GCn = 00H (6 dB), CCn1, CCn0 = 1, 1, CL = 30 pF, output voltage = 1VPP, output convergence voltage VPP = 999 mV - - 42 s GBW100 CLMAX = 30 pF, CCn1, CCn0 = 0, 0 - 1.0 - MHz - 0.85 - MHz - 0.60 - MHz - 0.30 - MHz - 67 - nV/ Hz - 75 - nV/ Hz - 110 - nV/ Hz - 145 - nV/ Hz GCn = 11H (40 dB) GBW101 CLMAX = 30 pF, CCn1, CCn0 = 0, 1 GBW110 CLMAX = 30 pF, CCn1, CCn0 = 1, 0 GCn = 11H (40 dB) GCn = 11H (40 dB) GBW111 CLMAX = 30 pF, CCn1, CCn0 = 1, 1 GCn = 11H (40 dB) Equivalent input noise En100 CCn1, CCn0 = 0, 0 f = 1 kHz, GCn = 11H (40 dB) En101 CCn1, CCn0 = 0, 1 f = 1 kHz, GCn = 11H (40 dB) En110 CCn1, CCn0 = 1, 0 f = 1 kHz, GCn = 11H (40 dB) En111 CCn1, CCn0 = 1, 1 f = 1 kHz, GCn = 11H (40 dB) Note These are the values for one channel of configurable amplifier. Remark n = 1 to 3 R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 94 of 117 RAA730300 11. Parameter Input conversion offset voltage Input conversion offset voltage temperature coefficient Slew rate Symbol Conditions Electrical Specifications Ratings Unit MIN TYP MAX VOFF1 CCn1, CCn0 = 0, 0, TA = 25C GCn = 0AH (26 dB) -7 - 7 mV VOFF2 CCn1, CCn0 = 0, 1, TA = 25C GCn = 0AH (26 dB) -10 - 10 mV VOFF3 CCn1, CCn0 = 1, 0, TA = 25C GCn = 0AH (26 dB) -10 - 10 mV VOFF4 CCn1, CCn0 = 1, 1, TA = 25C GCn = 0AH (26 dB) -12 - 12 mV VOTC00 CCn1, CCn0 = 0, 0 - 3.5 - V/ VOTC01 CCn1, CCn0 = 0, 1 - 3.5 - V/ VOTC10 CCn1, CCn0 = 1, 0 - 4.0 - V/ VOTC11 CCn1, CCn0 = 1, 1 - 4.5 - V/ SR100 CCn1, CCn0 = 0, 0, CL = 30 pF - 1.2 - V/s - 0.9 - V/s - 0.6 - V/s - 0.3 - V/s GCn = 00H (6 dB) SR101 CCn1, CCn0 = 0, 1, CL = 30 pF GCn = 00H (6 dB) SR110 CCn1, CCn0 = 1, 0, CL = 30 pF GCn = 00H (6 dB) SR111 CCn1, CCn0 = 1, 1, CL = 30 pF GCn = 00H (6 dB) Power supply rejection ratio Gain setting error PSRR100 CCn1, CCn0 = 0, 0, GCn = 00H (6 dB), f = 1 kHz - 80 - dB PSRR101 CCn1, CCn0 = 0, 1, GCn = 00H (6 dB) , f = 1 kHz - 80 - dB PSRR110 CCn1, CCn0 = 1, 0, GCn = 00H (6 dB) , f = 1 kHz - 80 - dB PSRR111 CCn1, CCn0 = 1, 1, GCn = 00H (6 dB) , f = 1 kHz - 80 - dB GAIN_Accu1 TA = 25C -0.6 - 0.6 dB GAIN_Accu2 TA = -40 to 105C -1.0 - 1.0 dB Remark n = 1 to 3 R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 95 of 117 RAA730300 11. Electrical Specifications (-40C TA 105C, AVDD1 = AVDD2 = AVDD3 = DVDD = 3.0 V, VREFIN = VREFIN2 = VREFIN3 = 1.5 V, AMP1OF = AMP2OF = AMP3OF = 1, DAC1OF = DAC2OF = DAC3OF = 0, differential amplifier) Parameter Current consumption Note Input voltage 1 Input voltage 2 Output voltage Settling time Gain bandwidth Symbol Conditions Ratings Unit MIN TYP MAX Icc00 CCn1, CCn0 = 0, 0 - 330 500 A Icc01 CCn1, CCn0 = 0, 1 - 250 380 A Icc10 CCn1, CCn0 = 1, 0 - 170 260 A Icc11 CCn1, CCn0 = 1, 1 - 90 150 A VINL1 IMSn = 0 AGND1 - 0.05 - - V VINH1 IMSn = 0 - - AVDD1 + 0.1 V VINL2 IMSn = 1 AGND1 - 0.05 - - V VINH2 IMSn = 1 - - AVDD1 - 1.4 V VOUTL IOL = -200 A - - AGND1 + 0.1 V VOUTH IOH = 200 A AVDD1 - 0.1 - - V tSET_AMP00 GCn = 00H (6 dB), CCn1, CCn0 = 0, 0, CL = 30 pF, output voltage = 1VPP, output convergence voltage VPP = 999 mV - - 8 s tSET_AMP01 GCn = 00H (6 dB), CCn1, CCn0 = 0, 1, CL = 30 pF, output voltage = 1VPP, output convergence voltage VPP = 999 mV - - 10 s tSET_AMP10 GCn = 00H (6 dB), CCn1, CCn0 = 1, 0, CL = 30 pF, output voltage = 1VPP, output convergence voltage VPP = 999 mV - - 16 s tSET_AMP11 GCn = 00H (6 dB), CCn1, CCn0 = 1, 1, CL = 30 pF, output voltage = 1VPP, output convergence voltage VPP = 999 mV - - 42 s GBW00 CLMAX = 30 pF, CCn1, CCn0 = 0, 0 - 1.0 - MHz - 0.85 - MHz - 0.60 - MHz - 0.30 - MHz GCn = 11H (40 dB) GBW01 CLMAX = 30 pF, CCn1, CCn0 = 0, 1 GBW10 CLMAX = 30 pF, CCn1, CCn0 = 1, 0 GCn = 11H (40 dB) GCn = 11H (40 dB) GBW11 CLMAX = 30 pF, CCn1, CCn0 = 1, 1 GCn = 11H (40 dB) Equivalent input noise En00 CCn1, CCn0 = 0, 0 f = 1 kHz, GCn = 11H (40 dB) - 67 - nV/ Hz En01 CCn1, CCn0 = 0, 1 f = 1 kHz, GCn = 11H (40 dB) - 75 - nV/ Hz En10 CCn1, CCn0 = 1, 0 f = 1 kHz, GCn = 11H (40 dB) - 110 - nV/ Hz En11 CCn1, CCn0 = 1, 1 f = 1 kHz, GCn = 11H (40 dB) - 145 - nV/ Hz Note These are the values for one channel of configurable amplifier. Remark n = 1 to 3 R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 96 of 117 RAA730300 11. Parameter Input conversion offset voltage Input conversion offset voltage temperature coefficient Slew rate Symbol Conditions Electrical Specifications Ratings Unit MIN TYP MAX VOFF1 CCn1, CCn0 = 0, 0, TA = 25C GCn = 0AH (26 dB) -7 - 7 mV VOFF2 CCn1, CCn0 = 0, 1, TA = 25C GCn = 0AH (26 dB) -10 - 10 mV VOFF3 CCn1, CCn0 = 1, 0, TA = 25C GCn = 0AH (26 dB) -10 - 10 mV VOFF4 CCn1, CCn0 = 1, 1, TA = 25C GCn = 0AH (26 dB) -12 - 12 mV VOTC00 CCn1, CCn0 = 0, 0 - 3.5 - V/ VOTC01 CCn1, CCn0 = 0, 1 - 3.5 - V/ VOTC10 CCn1, CCn0 = 1, 0 - 4.0 - V/ VOTC11 CCn1, CCn0 = 1, 1 - 4.5 - V/ SR00 CCn1, CCn0 = 0, 0, CL = 30 pF - 1.15 - V/s - 0.85 - V/s - 0.6 - V/s - 0.3 - V/s GCn = 00H (6 dB) SR01 CCn1, CCn0 = 0, 1, CL = 30 pF GCn = 00H (6 dB) SR10 CCn1, CCn0 = 1, 0, CL = 30 pF GCn = 00H (6 dB) SR11 CCn1, CCn0 = 1, 1, CL = 30 pF GCn = 00H (6 dB) Common mode rejection ratio Power supply rejection ratio Gain setting error CMRR00 CCn1, CCn0 = 0, 0, GCn = 11H (40 dB), f = 1 kHz - 80 - dB CMRR01 CCn1, CCn0 = 0, 1, GCn = 11H (40 dB), f = 1 kHz - 80 - dB CMRR10 CCn1, CCn0 = 1, 0, GCn = 11H (40 dB), f = 1 kHz - 80 - dB CMRR11 CCn1, CCn0 = 1, 1, GCn = 11H (40 dB), f = 1 kHz - 80 - dB PSRR00 CCn1, CCn0 = 0, 0, GCn = 00H (6 dB), f = 1 kHz - 80 - dB PSRR01 CCn1, CCn0 = 0, 1, GCn = 00H (6 dB), f = 1 kHz - 80 - dB PSRR10 CCn1, CCn0 = 1, 0, GCn = 00H (6 dB), f = 1 kHz - 80 - dB PSRR11 CCn1, CCn0 = 1, 1, GCn = 00H (6 dB), f = 1 kHz - 80 - dB GAIN_Accu1 TA = 25C -0.6 - 0.6 dB GAIN_Accu2 TA = -40 to 105C -1.0 - 1.0 dB Remark n = 1 to 3 R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 97 of 117 RAA730300 11. Electrical Specifications (-40C TA 105C, AVDD1 = AVDD2 = AVDD3 = DVDD = 3.0 V, VREFIN1 = VREFIN2 = VREFIN3 = 1.5 V, AMP1OF = AMP2OF = AMP3OF = 1, DAC1OF = DAC2OF = DAC3OF = 0, transimpedance amplifier) Parameter Current consumption Note Input voltage1 Input voltage2 Output voltage Settling time Current-to-voltage conversion gain bandwidth Note Symbol Conditions Ratings Unit MIN TYP MAX Icc00 CCn1, CCn0 = 0, 0 - 330 500 A Icc01 CCn1, CCn0 = 0, 1 - 250 380 A Icc10 CCn1, CCn0 = 1, 0 - 170 260 A Icc11 CCn1, CCn0 = 1, 1 - 90 150 A VINL1 IMSn = 0 AGND1 - 0.05 - - V VINH1 IMSn = 0 - - AVDD1 + 0.1 V VINL2 IMSn = 1 AGND1 - 0.05 - - V VINH2 IMSn = 1 - - AVDD1 - 1.4 V VOUTL IOL = -200 A - - AGND1 + 0.1 V VOUTH IOH = 200 A AVDD1 - 0.1 - - V tSET_AMP00 GCn = 00H (20 k), CCn1, CCn0 = 0, 0, CL = 30 pF, output voltage = 1VPP, output convergence voltage VPP = 999 mV - - 8 s tSET_AMP01 GCn = 00H (20 k), CCn1, CCn0 = 0, 1, CL = 30 pF, output voltage = 1VPP, output convergence voltage VPP = 999 mV - - 10 s tSET_AMP10 GCn = 00H (20 k), CCn1, CCn0 = 1, 0, CL = 30 pF, output voltage = 1VPP, output convergence voltage VPP = 999 mV - - 16 s tSET_AMP11 GCn = 00H (20 k), CCn1, CCn0 = 1, 1, CL = 30 pF, output voltage = 1VPP, output convergence voltage VPP = 999 mV - - 42 s GBW00_0 CLMAX = 30 pF, CCn1, CCn0 = 0, 0, GCn = 00H (Rfb = 20 k) - 0.75 - MHz GBW00_1 CLMAX = 30 pF, CCn1, CCn0 = 0, 0, GCn = 0FH (Rfb = 640 k) - 0.75 - MHz GBW01_0 CLMAX = 30 pF, CCn1, CCn0 = 0, 1, GCn = 00H (Rfb = 20 k) - 0.65 - MHz GBW01_1 CLMAX = 30 pF, CCn1, CCn0 = 0, 1, GCn = 0FH (Rfb = 640 k) - 0.7 - MHz GBW10_0 CLMAX = 30 pF, CCn1, CCn0 = 1, 0, GCn = 00H (Rfb = 20 k) - 0.45 - MHz GBW10_1 CLMAX = 30 pF, CCn1, CCn0 = 1, 0, GCn = 0FH (Rfb = 640 k) - 0.5 - MHz GBW11_0 CLMAX = 30 pF, CCn1, CCn0 = 1, 1, GCn = 00H (Rfb = 20 k) - 0.25 - MHz GBW11_1 CLMAX = 30 pF, CCn1, CCn0 = 1, 1, GCn = 0FH (Rfb = 640 k) - 0.3 - MHz These are the values for one channel of configurable amplifier. Remark n = 1 to 3 R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 98 of 117 RAA730300 11. Parameter Equivalent input noise Input conversion offset voltage Symbol Conditions Electrical Specifications Ratings Unit MIN TYP MAX En00 CCn1, CCn0 = 0, 0 f = 1 kHz, GCn = 00H (Rfb = 20 k) - 3 - pA/Hz En01 CCn1, CCn0 = 0, 1 f = 1 kHz, GCn = 00H (Rfb = 20 k) - 4 - pA/Hz En10 CCn1, CCn0 = 1, 0 f = 1 kHz, GCn = 00H (Rfb = 20 k) - 5 - pA/Hz En11 CCn1, CCn0 = 1, 1 f = 1 kHz, GCn = 00H (Rfb = 20 k) - 7 - pA/Hz VOFF1 CCn1, CCn0 = 0, 0, TA = 25C GCn = 0AH (Rfb = 160 k) -7 - 7 mV VOFF2 CCn1, CCn0 = 0, 1, TA = 25C GCn = 0AH (Rfb = 160 k) -10 - 10 mV VOFF3 CCn1, CCn0 = 1, 0, TA = 25C GCn = 0AH (Rfb = 160 k) -10 - 10 mV VOFF4 CCn1, CCn0 = 1, 1, TA = 25C GCn = 0AH (Rfb = 160 k) -12 - 12 mV Input conversion offset voltage temperature coefficient VOTC00 CCn1, CCn0 = 0, 0 - 3.5 - V/ VOTC01 CCn1, CCn0 = 0, 1 - 3.5 - V/ VOTC10 CCn1, CCn0 = 1, 0 - 4.0 - V/ VOTC11 CCn1, CCn0 = 1, 1 - 4.5 - V/ Slew rate SR00 CCn1, CCn0 = 0, 0, GCn = 00H (Rfb = 20 k) - 1.15 - V/s SR01 CCn1, CCn0 = 0, 1, GCn = 00H (Rfb = 20 k) - 0.85 - V/s SR10 CCn1, CCn0 = 1, 0, GCn = 00H (Rfb = 20 k) - 0.6 - V/s SR11 CCn1, CCn0 = 1, 1, GCn = 00H (Rfb = 20 k) - 0.3 - V/s PSRR00 CCn1, CCn0 = 0, 0, GCn = 00H (Rfb = 20 k), f = 1 kHz - 60 - dB PSRR01 CCn1, CCn0 = 0, 1, GCn = 00H (Rfb = 20 k), f = 1 kHz - 60 - dB PSRR10 CCn1, CCn0 = 1, 0, GCn = 00H (Rfb = 20 k), f = 1 kHz - 60 - dB PSRR11 CCn1, CCn0 = 1, 1, GCn = 00H (Rfb = 20 k), f = 1 kHz - 60 - dB Rfb_Accu1 TA = 25C -25 - 25 % Rfb_Accu2 TA = -40 to 105C -35 - 35 % Power supply rejection ratio Rfb setting error Remark n = 1 to 3 R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 99 of 117 RAA730300 11. Electrical Specifications (-40C TA 105C, AVDD1 = AVDD2 = AVDD3 = DVDD = 3.0 V, VREFIN1 = VREFIN2 = VREFIN3 = 1.5 V, AMP1OF = AMP2OF = AMP3OF = 1, DAC1OF = DAC2OF = DAC3OF = 0, GC1 = GC2 = 00H, instrumentation amplifier) Parameter Current consumption Input voltage 1 Input voltage 2 Output voltage Settling time Gain bandwidth Symbol Conditions Ratings Unit MIN TYP MAX Icc00 AMP1OF = AMP2OF = AMP3OF = 1, CCn1, CCn0 = 0, 0 - 960 1400 A Icc01 AMP1OF = AMP2OF = AMP3OF = 1, CCn1, CCn0 = 0, 1 - 750 1100 A Icc10 AMP1OF = AMP2OF = AMP3OF = 1, CCn1, CCn0 = 1, 0 - 520 750 A Icc11 AMP1OF = AMP2OF = AMP3OF = 1, CCn1, CCn0 = 1, 1 - 310 450 A VINL1 IMSn = 0 AGND1 - 0.05 - - V VINH1 IMSn = 0 - - AVDD1 + 0.1 V VINL2 IMSn = 1 AGND1 - 0.05 - - V VINH2 IMSn = 1 - - AVDD1 - 1.4 V VOUTL IOL = -200 A - - AGND1 + 0.05 V VOUTH IOH = 200 A AVDD1 - 0.05 - - V tSET_AMP00 GCn = 00H (15.5 dB), CCn1, CCn0 = 0, 0, CL = 30 pF, output voltage = 1VPP, output convergence voltage VPP = 999 mV - - 9 s tSET_AMP01 GCn = 00H (15.5 dB), CCn1, CCn0 = 0, 1, CL = 30 pF, output voltage = 1VPP, output convergence voltage VPP = 999 mV - - 12 s tSET_AMP10 GCn = 00H (15.5 dB), CCn1, CCn0 = 1, 0, CL = 30 pF, output voltage = 1VPP, output convergence voltage VPP = 999 mV - - 20 s tSET_AMP11 GCn = 00H (15.5 dB), CCn1, CCn0 = 1, 1, CL = 30 pF, output voltage = 1VPP, output convergence voltage VPP = 999 mV - - 56 s GBW00 CLMAX = 30 pF, CCn1, CCn0 = 0, 0 GC3 = 09H (33.5 dB) - 1.0 - MHz GBW01 CLMAX = 30 pF, CCn1, CCn0 = 0, 1 - 0.9 - MHz - 0.65 - MHz - 0.35 - MHz - 95 - nV/ Hz - 110 - nV/ Hz - 135 - nV/ Hz - 200 - nV/ Hz GC3 = 09H (33.5 dB) GBW10 CLMAX = 30 pF, CCn1, CCn0 = 1, 0 GC3 = 09H (33.5 dB) GBW11 CLMAX = 30 pF, CCn1, CCn0 = 1, 1 En00 CCn1, CCn0 = 0, 0 GC3 = 09H (33.5 dB) Equivalent input noise GC3 = 09H (33.5 dB), f = 1 kHz En01 CCn1, CCn0 = 0, 1 GC3 = 09H (33.5 dB), f = 1 kHz En10 CCn1, CCn0 = 1, 0 GC3 = 09H (33.5 dB), f = 1 kHz En11 CCn1, CCn0 = 1, 1 GC3 = 09H (33.5 dB), f = 1 kHz Remark n = 1 to 3 R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 100 of 117 RAA730300 11. Parameter Input conversion offset voltage Input conversion offset voltage temperature coefficient Slew rate Symbol Conditions Electrical Specifications Ratings Unit MIN TYP MAX VOFF1 CCn1, CCn0 = 0, 0, TA = 25C GC3 = 05H (25.5 dB) -7 - 7 mV VOFF2 CCn1, CCn0 = 0, 1, TA = 25C GC3 = 05H (25.5 dB) -10 - 10 mV VOFF3 CCn1, CCn0 = 1, 0, TA = 25C GC3 = 05H (25.5 dB) -10 - 10 mV VOFF4 CCn1, CCn0 = 1, 1, TA = 25C GC3 = 05H (25.5 dB) -12 - 12 mV VOTC00 CCn1, CCn0 = 0, 0 - 2.5 - V/ VOTC01 CCn1, CCn0 = 0, 1 - 2.5 - V/ VOTC10 CCn1, CCn0 = 1, 0 - 3.0 - V/ VOTC11 CCn1, CCn0 = 1, 1 - 4.5 - V/ SR00 CCn1, CCn0 = 0, 0, CL = 30 pF - 1.1 - V/s - 0.8 - V/s - 0.5 - V/s - 0.25 - V/s GC3 = 00H (15.5 dB) SR01 CCn1, CCn0 = 0, 1, CL = 30 pF GC3 = 00H (15.5 dB) SR10 CCn1, CCn0 = 1, 0, CL = 30 pF GC3 = 00H (15.5 dB) SR11 CCn1, CCn0 = 1, 1, CL = 30 pF GC3 = 00H (15.5 dB) Common mode rejection ratio CMRR00 CCn1, CCn0 = 0, 0 GC3 = 09H (33.5 dB), f = 1 kHz - 70 - dB CMRR01 CCn1, CCn0 = 0, 1 GC3 = 09H (33.5 dB), f = 1 kHz - 70 - dB CMRR10 CCn1, CCn0 = 1, 0 GC3 = 09H (33.5 dB), f = 1 kHz - 70 - dB CMRR11 CCn1, CCn0 = 1, 1 - 70 - dB GC3 = 09H (33.5 dB), f = 1 kHz Power supply rejection ratio PSRR00 CCn1, CCn0 = 0, 0 GC3 = 00H (15.5 dB), f = 1 kHz - 75 - dB PSRR01 CCn1, CCn0 = 0, 1 - 70 - dB - 70 - dB - 65 - dB GC3 = 00H (15.5 dB), f = 1 kHz PSRR10 CCn1, CCn0 = 1, 0 GC3 = 00H (15.5 dB), f = 1 kHz PSRR11 CCn1, CCn0 = 1, 1 GAIN_Accu TA = 25C -0.8 0.8 dB TA = -40 to 105C -1.2 1.2 dB GC3 = 00H (15.5 dB), f = 1 kHz Gain setting error Remark n = 1 to 3 R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 101 of 117 RAA730300 11. Electrical Specifications (-40C TA 105C, AVDD1 = AVDD2 = AVDD3 = DVDD = 3.0 V, VREFIN1 = VREFIN2 = VREFIN3 = 1.5 V, AMP1OF = AMP2OF = AMP3OF = 1, DAC1OF = DAC2OF = DAC3OF = 0, general-purpose operational amplifier) Parameter Symbol Conditions Ratings MIN Current consumption Note Input voltage 1 Input voltage 2 Output voltage Gain bandwidth Equivalent input noise Input conversion offset voltage Unit TYP MAX Icc00 CCn1, CCn0 = 0, 0 330 500 A Icc01 CCn1, CCn0 = 0, 1 250 380 A Icc10 CCn1, CCn0 = 1, 0 170 260 A Icc11 CCn1, CCn0 = 1, 1 90 150 A VINL1 IMSn = 0 AGND1 - 0.05 - - V VINH1 IMSn = 0 - - AVDD1 + 0.1 V VINL2 IMSn = 1 AGND1 - 0.05 - - V VINH2 IMSn = 1 - - AVDD1 - 1.4 V VOUTL IOL = -200 A - - AGND1 + 0.1 V VOUTH IOH = 200 A AVDD1 - 0.1 - - V GBW00 Configured as an inverting amplifier with 20 dB gain, CLMAX = 30 pF, CCn1, CCn0 = 0, 0 - 1.6 - MHz GBW01 Configured as an inverting amplifier with 20 dB gain, CLMAX = 30 pF, CCn1, CCn0 = 0, 1 - 1.1 - MHz GBW10 Configured as an inverting amplifier with 20 dB gain, CLMAX = 30 pF, CC1n, CCn0 = 1, 0 - 0.65 - MHz GBW11 Configured as an inverting amplifier with 20 dB gain, CLMAX = 30 pF, CCn1, CCn0 = 1, 1 - 0.25 - MHz En00 Configured as an inverting amplifier with 20 dB gain, CCn1, CCn0 = 0, 0, f = 1 kHz - 76 - nV/ Hz En01 Configured as an inverting amplifier with 20 dB gain, CCn1, CCn0 = 0, 1, f = 1 kHz - 90 - nV/ Hz En10 Configured as an inverting amplifier with 20 dB gain, CCn1, CCn0 = 1, 0, f = 1 kHz - 110 - nV/ Hz En11 Configured as an inverting amplifier with 20 dB gain, CCn1, CCn0 = 1, 1, f = 1 kHz - 165 - nV/ Hz VOFF1 Configured as an inverting amplifier with 20 dB gain, CCn1, CCn0 = 0, 0, TA = 25C -7 - 7 mV VOFF2 Configured as an inverting amplifier with 20 dB gain, CCn1, CCn0 = 0, 1, TA = 25C -10 - 10 mV VOFF3 Configured as an inverting amplifier with 20 dB gain, CCn1, CCn0 = 1, 0, TA = 25C -10 - 10 mV VOFF4 Configured as an inverting amplifier with 20 dB gain, CCn1, CCn0 = 1, 1, TA = 25C -12 - 12 mV Note These are the values for one channel of configurable amplifier. Remark n = 1 to 3 R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 102 of 117 RAA730300 11. Parameter Input conversion offset voltage temperature coefficient Slew rate Symbol Conditions Electrical Specifications Ratings Unit MIN TYP MAX VOTC00 Configured as an inverting amplifier with 20 dB gain, CCn1, CCn0 = 0, 0 - 3.5 - V/ VOTC01 Configured as an inverting amplifier with 20 dB gain, CCn1, CCn0 = 0, 1 - 3.5 - V/ VOTC10 Configured as an inverting amplifier with 20 dB gain, CCn1, CCn0 = 1, 0 - 4.0 - V/ VOTC11 Configured as an inverting amplifier with 20 dB gain, CCn1, CCn0 = 1, 1 - 4.5 - V/ SR00 Configured as a voltage follower, - 0.98 - V/s - 0.74 - V/s - 0.49 - V/s - 0.22 - V/s CCn1, CCn0 = 0, 0, CL = 30 pF SR01 Configured as a voltage follower, CCn1, CCn0 = 0, 1, CL = 30 pF SR10 Configured as a voltage follower, CCn1, CCn0 = 1, 0, CL = 30 pF SR11 Configured as a voltage follower, CCn1, CCn0 = 1, 1, CL = 30 pF Common mode rejection ratio CMRR00 Configured as a differential amplifier with 20 dB gain, CCn1, CCn0 = 0, 0, f = 1 kHz - 85 - dB CMRR01 Configured as a differential amplifier with 20 dB gain, CCn1, CCn0 = 0, 1, f = 1 kHz - 85 - dB CMRR10 Configured as a differential amplifier with 20 dB gain, CCn1, CCn0 = 1, 0, f = 1 kHz - 85 - dB CMRR11 Configured as a differential amplifier with 20 dB gain, CCn1, CCn0 = 1, 1, - 85 - dB - 80 - dB - 80 - dB - 80 - dB - 80 - dB f = 1 kHz Power supply rejection ratio PSRR00 Configured as a voltage follower, CCn1, CCn0 = 0, 0, f = 1 kHz PSRR01 Configured as a voltage follower, CCn1, CCn0 = 0, 1, f = 1 kHz PSRR10 Configured as a voltage follower, CCn1, CCn0 = 1, 0, f = 1 kHz PSRR11 Configured as a voltage follower, CCn1, CCn0 = 1, 1, f = 1 kHz Remark n = 1 to 3 R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 103 of 117 RAA730300 (2) 11. Electrical Specifications General-purpose operational amplifier (-40C TA 105C, AVDD1 = AVDD2 = AVDD3 = DVDD = 3.0 V, AMP4OF = AMP5OF = 1) Parameter Symbol Conditions Ratings MIN Unit TYP MAX 320 450 A Current consumption IccA Input voltage 1 VINL1 IMSn = 0 AGND1 - 0.05 - - V VINH1 IMSn = 0 - - AVDD1 + 0.1 V VINL2 IMSn = 1 AGND1 - 0.05 - - V VINH2 IMSn = 1 - - AVDD1 - 1.4 V Input voltage 2 VOUTL IOL = -200 A - - AGND1 + 0.05 V VOUTH IOH = 200 A AVDD1 - 0.05 - - V Gain bandwidth GBW Configured as an inverting amplifier with 20 dB gain, CLMAX = 30 pF - 2.0 - MHz Input conversion offset voltage VOFF Configured as an inverting amplifier with 20 dB gain, TA = 25C, AMP4_INP = AMP5_INP = 1.5 V -7 - 7 mV Input conversion offset voltage temperature coefficient VOTC Configured as an inverting amplifier with 20 dB gain - 2.0 - V/C Slew rate SR Configured as a voltage follower, - 0.9 - V/s Output voltage CL = 30 pF Equivalent input noise En_Gain Configured as an inverting amplifier with 20 dB gain, f = 1 kHz - 77 - nV/ Hz Common mode rejection ratio CMRR Configured as a differential amplifier with 20 dB gain, f = 1 kHz - 75 - dB Power supply rejection ratio PSRR Configured as an inverting amplifier with 20 dB gain, f = 1 kHz - 55 - dB Remark n = 4, 5 R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 104 of 117 RAA730300 (3) 11. Electrical Specifications D/A converter (-40C TA 105C, AVDD1 = AVDD2 = AVDD3 = DVDD = 3.0 V, DAC1OF = DAC2OF = DAC3OF = DAC4OF = DAC5OF = DAC6OF = DAC7OF = 1) Parameter <R> <R> Symbol Conditions DAC ALL ON current consumption 1 I_DAC_ON1 DAC ALL ON current consumption 2 I_DAC_ON2 Buffer AMP ON current consumption 1 Note1 I_DAC_Buff1 Buffer AMP ON current consumption 2 Note1 I_DAC_Buff2 DACx GAMP ON current consumption I_DAC_AMP1 DACxOF = 1 I_DAC_AMP2 (x = 1, 2, 3, 5, 6, 7) (x = 1, 2, 3, 5, 6, 7) DAC1OF = DAC2OF = DAC3OF = Ratings Unit MIN TYP MAX - 1.10 1.65 mA - 1.25 1.85 mA - 180 220 A - 330 400 A - 110 180 A - 260 350 A DAC4OF = DAC5OF = DAC6OF = DAC7OF = 1, VRB1, VRB0 = 0, 0 DAC1OF = DAC2OF = DAC3OF = DAC4OF = DAC5OF = DAC6OF = DAC7OF = 1, VRB1, VRB0 = 0, 1 DACxOF = 1, VRB1, VRB0 = 0, 0 (x = 1, 2, 3, 4, 5, 6, 7) DACxOF = 1, VRB1, VRB0 = 0, 1 (x = 1, 2, 3, 4, 5, 6, 7) I_DAC_AMP3 I_DAC_AMP5 I_DAC_AMP6 I_DAC_AMP7 DAC4 GAMP ON current consumption I_DAC_AMP4 DAC4OF = 1 Resolution RES - - 8 bit Settling time tSET - - 50 s Differential nonlinearity error Note2 DNL VRT1 = VRT0 = 0, VRB1 = VRB0 = 0 -2 - 2 LSB Integral nonlinearity error INL VRT1 = VRT0 = 0, VRB1 = VRB0 = 0 -2 - 2 LSB Note1. Buffer amplifier is powered on when one of DACx (x = 1, 2, 3, 4, 5, 6, 7) is powered on at least. For example, the current consumption (I_EXAMPLE) is shown as a following equation when "DAC1OF=DAC2OF=1", and "VRB1, VRB0=0, 0". I_EXAMPLE = I_DAC_Buff1 + I_DAC_AMP1 + I_DAC_AMP2 2. Guaranteed monotonic. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 105 of 117 RAA730300 (4) 11. Electrical Specifications Low-pass filter (-40C TA 105C, AVDD1 = AVDD2 = AVDD3 = DVDD = 3.0 V, LPFOF = 1) Parameter Symbol Conditions Ratings Unit MIN TYP MAX - 800 1200 A Current consumption IccA Input voltage 1 VILLPF1 IMSn = 0 AGND4 + 0.2 - - V VIHLPF1 IMSn = 0 - - AVDD3 - 0.2 V VILLPF2 IMSn = 1 AGND4 + 0.2 - - V VIHLPF2 IMSn = 1 - - AVDD3 - 1.4 V VOLLPF IOL = -200 A - - AGND4 - 0.2 V VOHLPF IOH = 200 A AVDD3 - 0.2 - - V Input conversion offset voltage VOFF DAC4OF = 1, DAC4C = 80H -100 - 100 mV Cutoff frequency fc1 fCLK_LPF = 2 kHz - 8.7 - Hz fc2 fCLK_LPF = 200 kHz - 870 - Hz 0.3 x AVDD3 V Input voltage 2 Output voltage CLK_LPF VILCLK_LPF low-level input voltage CLK_LPF 0.7 x AVDD3 VIHCLK_LPF V high-level input voltage CLK_LPF fCLK_LPF 2 - 200 kHz CLK_LPF tILW_LPF 200 - - ns Input low-level-width tIHW_LPF Input frequency Input high-level-width Remark n = 6 Clock Timing tILW_LPF tIHW_LPF 0.7VDD CLK_LPF 0.3VDD R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 106 of 117 RAA730300 (5) 11. Electrical Specifications High-pass filter (-40C TA 105C, AVDD1 = AVDD2 = AVDD3 = DVDD = 3.0 V, HPFOF = 1) Parameter Symbol Conditions Ratings Unit MIN TYP MAX - 800 1200 A Current consumption IccA Input voltage 1 VILHPF1 IMSn = 0 AGND4 + 0.2 - - V VIHHPF1 IMSn = 0 - - AVDD3 - 0.2 V VILHPF2 IMSn = 1 AGND4 + 0.2 - - V VIHHPF2 IMSn = 1 - - AVDD3 - 1.4 V VOLHPF IOL = -200 A - - AGND4 - 0.2 V VOHHPF IOH = 200 A AVDD3 - 0.2 - - V Input conversion offset voltage VOFF DAC4OF = 1, DAC4C = 80H -100 - 100 mV Cutoff frequency fc1 fCLK_HPF = 2 kHz - 7.4 - Hz fc2 fCLK_HPF = 200 kHz - 740 - Hz 0.3 x AVDD3 V Input voltage 2 Output voltage CLK_HPF VILCLK_HPF low-level input voltage CLK_HPF 0.7 x AVDD3 VIHCLK_HPF V high-level input voltage CLK_HPF fCLK_HPF 2 - 200 kHz CLK_HPF tILW_HPF 200 - - ns Input low-level-width tIHW_HPF Input frequency Input high-level-width Remark n = 6 Clock Timing tILW_HPF tIHW_HPF 0.7VDD CLK_HPF 0.3VDD R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 107 of 117 RAA730300 (6) 11. Electrical Specifications Temperature sensor (-40C TA 105C, AVDD1 = AVDD2 = AVDD3 = DVDD = 3.0 V, TEMPOF = 1) Parameter Symbol Current consumption IccA Output voltage VO Temperature sensitivity TSE (7) Conditions TA = 25C Ratings Unit MIN TYP MAX - 90 140 A - 1.28 - V - -4.0 - mV/C Variable output voltage regulator (-40C TA 105C, AVDD1 = AVDD2 = AVDD3 = DVDD = 3.0 V, LDOOF = 1) Parameter Symbol Conditions Ratings Unit MIN TYP MAX Current consumption IccON Iout = 0 mA - 80 120 A Output voltage accuracy V_Accu Iout = 0 mA -10 - 10 % Load current characteristics Vout_load Iout = 0 to 5 mA - 15 30 mV - - 15 mA Output current Dropout voltage Power supply rejection ratio Iout Note1 Vd Iout = 15 mA - - 0.4 V PSRR f = 1 kHz, CL = 1.0 F, Iout = 5 mA, AVDD2 = 3.0 V, LDOC = 08H (2.6 V) - 45 - dB LDOOF = 0 - 1.0 1.5 k CL = 1.0 F, Iout = 0 mA, LDOC = 08H (2.6 V) - - 200 s CL = 1.0 F, Iout = 0 mA, LDOC = 08H (2.6 V) - - 5 ms Discharge resistance Rs Settling time Tset_rise Note2 Tset_fall Note2 Note1. The output voltage range is determined not only by dropout voltage but also by output voltage accuracy. 2. Tset_rise is defined as the time between operation enabled by power control register PC2 to output voltage being at 90% of its nominal value. 3. Tset_fall is defined as the time between operation disabled by power control register PC2 to output voltage being at 10% of its nominal value. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 108 of 117 RAA730300 (8) 11. Electrical Specifications SPI (-40C TA 105C, AVDD1 = AVDD2 = AVDD3 = DVDD = 3.0 V) Parameter Symbol Conditions Ratings Unit MIN TYP MAX Input voltage, high VIH CS pin, SDI pin, SCLK pin, RESET pin DVDD x 0.7 - DVDD + 0.1 V Input voltage, low VIL CS pin, SDI pin, SCLK pin, RESET pin DGND - 0.1 - DVDD x 0.3 V Leakage current during high level input Ileak_Hi1 CS pin, SDI pin, SCLK pin -2 - 2 A Ileak_Hi2 RESET pin -2 - 2 A Leakage current during low level input Ileak_Lo1 CS pin, SDI pin, SCLK pin -2 - 2 A Ileak_Lo2 RESET pin -2 - 2 A Low-level output voltage at SDO pin VSDO_Lo IO = -4 mA - 250 400 mV Leakage current when SDO pin is off Ileak_SDO -2 - 2 A Pull-up resistance RSPI - 50 75 k CS pin, SDI pin, SCLK pin RESET = L SCLK cycle time tKCYA 100 - - ns SCLK tKHA, tKLA 0.8tKCYA/2 - - ns SDI setup time (to SCLK ) tSIKA 40 - - ns SDI hold time (from SCLK ) tKSIA 10 - - ns CL = 5 pF, VSDO = 3 V - - 40 ns CL = 5 pF, VSDO = 3 V - - 40 ns high-level width low-level width Delay time from tKSOAR SCLK to SDO output tKSOAF CS high-level width tSHA 200 - - ns Delay time from CS to SCLK tSKA 200 - - ns Delay time from SCLK to CS tKSA 200 - - ns R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 109 of 117 RAA730300 11. Electrical Specifications SPI transfer clock timing R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 110 of 117 RAA730300 12. Package Drawing 12. Package Drawing HD D detail of lead end 36 25 37 A3 24 c E L Lp HE L1 (UNIT:mm) 13 48 12 1 ZE e ZD b x M S A ITEM D DIMENSIONS 7.000.20 E 7.000.20 HD 9.000.20 HE 9.000.20 A 1.60 MAX. A1 0.100.05 A2 1.400.05 A3 b A2 c L S y S NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. R02DS0011EJ0110 Rev.1.10 May. 31, 2014 A1 0.25 0.220.05 0.145 +0.055 -0.045 0.50 Lp 0.600.15 L1 1.000.20 3 +5 -3 e 0.50 x 0.08 y 0.08 ZD 0.75 ZE 0.75 Page 111 of 117 RAA730300 Characteristics Curve Characteristics Curve (TA = 25C, TYP.) (reference value) * Configurable amplifier G vs. f (Inverting amplifier) G vs. f (Instrumentation amplifier) 50 AVDD1=3V CCx1, CCx0 = 0, 0 (x=1, 2, 3) 40 Voltage gain G (dB) Voltage gain G (dB) 50 30 20 10 0 100 AVDD1=3V CCx1, CCx0 = 1, 1 (x=1, 2, 3) 1K 10K 100K 1M Frequency f (Hz) R02DS0011EJ0110 Rev.1.10 May. 31, 2014 10M AVDD1=3V CCx1, CCx0 = 0, 0 (x=1, 2, 3) 40 30 20 10 0 100 AVDD1=3V CCx1, CCx0 = 1, 1 (x=1, 2, 3) 1K 10K 100K 1M 10M Frequency f (Hz) Page 112 of 117 RAA730300 Characteristics Curve Output response (Non-inverting amplifier) Output response (Non-inverting amplifier) CCx1, CCx0 = 0, 0 (x=1, 2, 3) 3 2 1 0 AVDD1=3V GCx = 00H (9.5dB) 2.0 1.0 0.0 0 10 20 30 40 Output voltage VO (V) 4 Input voltage VI (V) Input voltage VI (V) Output voltage VO (V) 4 CCx1, CCx0 = 1, 1 (x=1, 2, 3) 3 2 1 0 AVDD1=3V GCx = 00H (9.5dB) 2.0 1.0 0.0 0 10 20 30 40 Time t (s) Time t (s) Output response (Instrumentation amplifier) Output response (Instrumentation amplifier) 2 1 0 AVDD1=3V GC1 = GC2 = GC3 = 00H (15.5dB) 2.0 1.5 1.0 0 4 8 Time t (s) R02DS0011EJ0110 Rev.1.10 May. 31, 2014 12 16 Output voltage VO (V) CCx1, CCx0 = 0, 0 (x=1, 2, 3) 3 Input voltage VI (V) Input voltage VI (V) Output voltage VO (V) 4 4 CCx1, CCx0 = 1, 1 (x=1, 2, 3) 3 2 1 0 AVDD1=3V GC1 = GC2 = GC3 = 00H (15.5dB) 2.0 1.5 1.0 0 20 40 60 80 Time t (s) Page 113 of 117 RAA730300 Characteristics Curve CMRR (Differential amplifier) CMRR (Differential amplifier) 0 0 AVDD1=3V GCx = 11H (40dB) -20 CCx1, CCx0 = 0, 0 (x=1, 2, 3) -40 CMRR (dB) CMRR (dB) -20 -60 -80 -40 CCx1, CCx0 = 1, 1 (x=1, 2, 3) -60 -80 -100 100 1k 10k 100k 1M -100 100 Frequency f (Hz) CMRR (Instrumentation amplifier) 1M 100k CMRR (Instrumentation amplifier) AVDD1=3V GC1 = GC2 = 00H, GC3 = 09H (33.5dB) -20 -40 -60 -80 -100 100 10k 0 CMRR (dB) -20 1k Frequency f (Hz) 0 CMRR (dB) AVDD1=3V GCx = 11H (40dB) 10k 100k Frequency f (Hz) R02DS0011EJ0110 Rev.1.10 May. 31, 2014 -40 -60 -80 CCx1, CCx0 = 0, 0 (x=1, 2, 3) 1k AVDD1=3V GC1 = GC2 = 00H, GC3 = 09H (33.5dB) 1M -100 100 CCx1, CCx0 = 1, 1 (x=1, 2, 3) 1k 10k 100k 1M Frequency f (Hz) Page 114 of 117 RAA730300 Characteristics Curve AVDD1=3V GCx = 11H (40.1dB) 1000 300 100 30 CCx1, CCx0 = 0, 0 (x=1, 2, 3) 10 0.01 0.1 1 10 100 1000 Equivalent input noise En (nV/Hz) 3000 En vs. f (Non-inverting amplifier) 3000 AVDD1=3V GCx = 11H (40.1dB) 1000 300 100 30 10 0.01 CCx1, CCx0 = 1, 1 (x=1, 2, 3) 0.1 1 10 100 1000 Frequency f (kHz) Frequency f (kHz) En vs. f (Instrumentation amplifier) En vs. f (Instrumentation amplifier) 3000 AVDD1=3V GC1 = GC2 = 00H, GC3 = 09H (33.5dB) 1000 300 100 30 CCx1, CCx0 = 0, 0 (x=1, 2, 3) 10 0.01 0.1 1 10 100 Frequency f (kHz) R02DS0011EJ0110 Rev.1.10 May. 31, 2014 1000 Equivalent input noise En (nV/Hz) Equivalent input noise En (nV/Hz) Equivalent input noise En (nV/Hz) En vs. f (Non-inverting amplifier) 3000 AVDD1=3V GC1 = GC2 = 00H, GC3 = 09H (33.5dB) 1000 300 100 30 10 0.01 CCx1, CCx0 = 1, 1 (x=1, 2, 3) 0.1 1 10 100 1000 Frequency f (kHz) Page 115 of 117 RAA730300 * Characteristics Curve Low-pass filter and high-pass filter G vs. f G vs. f 10 10 AVDD1=3V Voltage gain G (dB) Voltage gain G (dB) AVDD1=3V 0 -10 fCLK_LPF = 200kHz -20 fCLK_LPF= 20kHz 0 -10 fCLK_LPF = 200kHz -20 -30 -30 fCLK_LPF= 20kHz -40 -40 10 100 10k 1k 10 100 Frequency f (Hz) * 10k 1k Frequency f (Hz) Temperature sensor Output voltage VTEMP_OUT V VTEMP_OUT vs. TA 1.6 AVDD1=3V 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 -50 -25 0 25 50 75 100 125 Temperature TA () R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 116 of 117 RAA730300 * Characteristics Curve Variable output voltage regulator Output voltage vs. Load current Output voltage VOUT (V) 1.820 AVDD1 = 3V LDOC = 00H (1.8V) 1.810 1.800 1.790 1.780 1.770 0.0 5.0 10.0 15.0 Load current IOUT (mA) Output voltage vs. Load current Output voltage VOUT (V) 2.620 AVDD1 = 3V LDOC = 08H (2.6V) 2.610 2.600 2.590 2.580 2.570 0.0 5.0 10.0 15.0 Load current IOUT (mA) R02DS0011EJ0110 Rev.1.10 May. 31, 2014 Page 117 of 117 Revision History Rev. 1.00 1.10 RAA730300 Monolithic Programmable Analog IC Date Mar. 29, 2013 May. 31, 2014 Page - 14 16 34 53 54 55 59 61 66 70 71 81 84 88 89 105 Description Summary First edition issued. Change of description about reference voltage in 2. 1 Configurable Amplifiers Correction of the register name controlling SW02 in Figure 2-2. Change of description in 2. 3 (9) Power control register 1 (PC1) Change of description about reference voltage in 3. 1 General-Purpose Operational Amplifier Addition of the register controlling SW53 to Figure 3-2. Change of description in 3. 3 (1) Power control register 1 (PC1) Change of the calculating formula about output voltage in 4. 1 D/A Converters Change of description in 4. 3 (1) DAC reference voltage control register (DACRC) Change of description about reference voltage in 5. 1 Low-pass Filter Change of description about reference voltage in 6. 1 High-Pass Filter Change of description in 6. 3 (1) MPX setting register3 (MPX3) Addition of Caution about external reset to 9. SPI Change of description in 10. Reset Deletion of Junction temperature from 11. 1 Absolute Maximum Ratings Change of the title to Operation condition in 11. 2 Correction of the units of DAC ALL ON current consumption 1 and DAC ALL ON current consumption 2 in 11. 4 (3) All trademarks and registered trademarks are the property of their respective owners. C-1 NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). (2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. (4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 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