June 2008
Sensors
Datasheet
Rev 1.0
TLE4946-2L
High Precision Hall Effect Latch
TLE4946-2L
Edition 2008-06
Published by
Infineon Technologies AG
81726 München, Germany
© 2007 Infineon Technologies AG
All Rights Reserved.
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TLE4946-2L High Precision Hall Effect Latch
Revision History: 2008-06, Rev 1.0
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TLE4946-2L
Datasheet 3 Rev 1.0, 2008-06
Datasheet 4 Rev 1.0, 2008-06
TLE4946-2L
1 Product Description 5
1.1 Overview 5
1.2 Features 5
1.3 Target Applications 5
2 Functional Description 5
2.1 General 5
2.2 Pin Configuration 6
2.3 Pin Description 6
2.4 Block Diagram 6
2.5 Operating Modes and States 7
2.6 Functional Block Description 7
3 Specification 8
3.1 Application Circuit 8
3.2 Absolute Maximum Ratings 8
3.3 Operating Range 9
3.4 Characteristics 9
4 Package Information 10
4.1 Package Outline 10
Product Name Product Type Ordering Code Package
Hall Effect Latch TLE4946-2L SP000398352 PG-SSO-3-2
Datasheet 5 Rev 1.0, 2008-06
High Precision Hall Effect Latch
TLE4946-2L
1 Product Description
1.1 Overview
The TLE4946-2L is a high precision Hall effect latch
with highly accurate switching thresholds for operating
temperatures up to 150°C.
1.2 Features
•2.7 V to 18 V supply voltage operation
• Operation from unregulated power supply
• High sensitivity and high stability of the magnetic switching points
• High resistance to mechanical stress by active error compensation
• Reverse battery protection (Vs = -18V)
• Superior temperature stability
• Peak temperatures up to 195°C without damage
• Low jitter (typ. 1µs)
• High ESD performance (± 4 kV HBM)
• Digital output signal
1.3 Target Applications
The TLE4946-2L is an integrated circuit Hall-effect sensor with low switching thresholds and low hysteresis. It is
specially designed for high sensitivity applications and is ideally suited to detect the rotor position in a BLDC motor.
Also for index counting with small pole wheels and large air gaps the sensor provides a reliable switching
information.
2 Functional Description
2.1 General
Precise magnetic switching thresholds and high temperature stability are achieved by active compensation circuits
and chopper techniques on chip. Offset voltages, generated by temperature induced stress or overmolding are
canceled and high accuracy is achieved. The IC has an open collector output stage with 20mA current sink
capability. A wide operating voltage range form 2.7V to 18V with reverse polarity protection up to -18V makes the
device suitable for a wide range of applications. A magnetic south pole with field strength above Bop turns the
output on and a magnetic north pole exceeding Brp turns it off.
Datasheet 6 Rev 1.0, 2008-06
TLE4946-2L
Functional Description
2.2 Pin Configuration
Center of
Sensitive Area
321
PG-SSO-3-2
± 0.1
1.35
± 0.1
2.08
Figure 1 Pin Configuration and sensitive area (Top View, Figure not to Scale)
2.3 Pin Description
Table 1 Pin Description
Pin or Ball
No.
Name Pin
Type
Function Comments
1Vs ISupply voltage
2GND OGround
3Q O Output
2.4 Block Diagram
Ref
Chopped
Hall Probe
V
S
Q
GND
Amplifier Low
Pass
Filter
Comparator
with
Hysteresis
Voltage Regulator
reverse polarity protected
Oscillator
and
Sequencer
Bias and
Compensation
Circuits
Figure 2 TLE4946-2L Block Diagram
Datasheet 7 Rev 1.0, 2008-06
TLE4946-2L
Functional Description
2.5 Operating Modes and States
Field Direction Definition:
Positive magnetic fields are related with the south pole of the magnet to the branded side of package.
Applied
Magnetic
Field
90%
10%
V
Q
t
f
t
d
t
r
t
d
B
OP
B
RP
Figure 3 Timing diagram
V
Q
B
op
B
rp
0
B
Figure 4 Output Signal
2.6 Functional Block Description
The chopped Hall IC switch comprises a Hall probe, bias generator, compensation circuits, oscillator and output
transistor.
The bias generator provides currents for the Hall probe and the active circuits. Compensation circuits stabilize the
temperature behavior and reduce technology variations.
The Active Error Compensation rejects offsets in signal stages and the influence of mechanical stress to the Hall
probe caused by molding and soldering processes and other thermal stresses in the package.
This chopper technique together with the threshold generator and the comparator ensure high accurate magnetic
switching points
Datasheet 8 Rev 1.0, 2008-06
TLE4946-2L
Specification
3 Specification
3.1 Application Circuit
VS
Q
GND
TLE4946-2L
200Ω
1.2kΩ
VS
GND
4.7nF 4. 7nF
Q
Figure 5 Application circuit
It is recommended to use a serial resistor of 200Ω in the supply line for current limitation in the case of a
overvoltage pulse. Two capacitors of 4.7nF enhance the EMC performance. The pull-up resistor of 1.2kΩ limits
the current through the output transistor.
3.2 Absolute Maximum Ratings
Table 2 Absolute Maximum Ratings
Parameter Symbol Values Unit Note/Test Condition
Min. Typ. Max.
Max. junction temperature TJ-40 –150 °C
– – 155 for 2000 h (not
additive)
– – 165 for 1000 h (not additive
– – 175 for 168 h (not additive)
– – 195 for 3 x 1 h (additive)
Supply voltage VDD -18
-18
-18
–
–
–
18
24
26
V
for 1h, Rs ≥ 200Ω
for 5min, Rs ≥ 200Ω
Supply current through
protection device
IS– 50 – + 50 mA
Output voltage VQ-0.7 –18 V
-0.7 –26 for 5min @ 1.2kΩ pull
up
Storage temperature TS– 40 –150 °C
Magnetic flux density B – unlimited mT
ESD robustness
HBM: 1.5 kΩ, 100 pF
VESD,HBM 4kV According to
EIA/JESD22-A114-B
Datasheet 9 Rev 1.0, 2008-06
TLE4946-2L
Specification
Attention: Stresses above the max. values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the integrated circuit.
3.3 Operating Range
The following operating conditions must not be exceeded in order to ensure correct operation of the TLE4946-2L.
All parameters specified in the following sections refer to these operating conditions unless otherwise mentioned.
Table 3 Operating Range
Parameter Symbol Values Unit Note/ Test Condition
Min. Typ. Max.
Supply voltage VS2.7 –18 V
Output voltage VQ– 0.7 –18 V
Junction temperature Tj– 40 –150 °C
Output current IQ0 – 20 mA
3.4 Characteristics
Product characteristics involve the spread of values guaranteed within the specified voltage and ambient
temperature range. Typical characteristics are the median of the production (at Vs = 12V and TA= 25°C).
Table 4 Electrical Characteristics
Parameter Symbol Values Unit Note/ Test Condition
Min. Typ. Max.
Supply current IS2 4 6 mA VS = 2.7 V ... 18 V
Reverse current ISR 00.2 1mA VS = – 18 V
Output saturation voltage VQSAT –0.3 0.6 VIQ = 20 mA
Output leakage current IQLEAK –0.05 10 µA for VQ = 18 V
Output fall time tf–0.02 1µs RL = 1.2 kΩ;
CL = 50 pF
Output rise time tr–0.4 1µs
Chopper frequency fOSC –320 –kHz
Switching frequency fSW 0 – 15
1) To operate the sensor at the max. switching frequency, the value of the magnetic signal amplitude must be 1.4 times higher
than for static fields.
This is due to the - 3 dB corner frequency of the low pass filter in the signal path.
1) kHz
Delay time
2) Systematic delay between magnetic threshold reached and output switching
2) td–13 –µs
Output jitter
3) Jitter is the unpredictable deviation of the output switching delay
3) tQJ – 1 – µsRMS Typ. value for square
wave signal 1 kHz
Power-on time
4) Time from applying VS ≥ 2.7 V to the sensor until the output state is valid
4) tPON –13 –µs VS ≥ 2.7 V
Thermal resistance
5) Thermal resistance from junction to ambient
5) RthJA –190 K/W PG-SSO-3-2
Table 5 Magnetic Characteristics
Parameter Symbol Values Unit Note/ Test Condition
Min. Typ. Max.
Operate point BOP 0.5 2.0 3.5 mT
Release point BRP -3.5
-2.0 -0.5
mT
Hysteresis BHYS 1.0 46.0 mT
Magnetic Offset
1) Boff = (Bop + Brp)/2
1) BOFF -1.5 01.5 mT
Temperature compensation of
magn. thresholds
TC -350 ppm/°C
Repeatability of magnetic
thresholds
2) BREP is equivalent to the noise constant
2)
BREP 20 µTRMS
Datasheet 10 Rev 1.0, 2008-06
TLE4946-2L
Package Information
4 Package Information
4.1 Package Outline
PG-SSO-3-2 : 0.57
d : Distance chip to upper side of I
C
mm
±0.08
AEA02510
-1
Hall-Probe
Branded Side
d
AEA03644
Year (y) = 0...9
Calendar Week (ww) = 01...52
yww
46 2
S
Figure 6 Marking of TLE4946-2L and Distance of chip to upper side of IC
Total tolerance at 10 pitches ±1
1
) No solder function area
±0.3
±0.4
6.35 12.7
12.7
±1
±0.5
-0.5
+0.75
4
±0.3
9
GPO0535
8
-0.15
±0.1
Tape
Adhesiv
e
Tape
0.25
0.39
±0.5
A
18
6
23.8
±0.5
38 MAX.
-1
1
132
1.27
±0.25
1.27
±0.25
0.6 MAX.
0.4
±0.05
1)
1 MAX.
0.15 MAX.
1.9 MAX.
4.06
±0.08
4.16
±0.05
±0.08
3.29
3
±0.06
0.2
(0.25)
x 45˚0.8
±0.1
7˚
x 45˚
±0.1
0.35
0.2
+0.1
7˚
(0.79)
A
2
1.52
±0.05
Datasheet 11 Rev 1.0, 2008-06
TLE4946-2L
Package Information
Figure 7 Package outline
