Rev. 1.1 6/18 Copyright © 2018 by Silico n Laboratories Si597
QUAD FREQUENCY VOLTAGE-CONTROLLED CRYSTAL
OSCILLATOR (VCXO) 10 TO 810 MHZ
Features
Applications
Description
The Si597 quad frequency VCXO utilizes Silicon Laboratories’ advanced
DSPLL
®
circuitry to provide a low-jitter clock for all output frequencies . The
Si597 is available with one of four pin-selectable oupu t frequencies from 1 0
to 810 MHz. Unlike traditional VCXOs, where a different crystal is required
for each output frequency, the Si597 uses one fixed crystal to provide a wide
range of output frequencies. This IC-based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In
addition, DSPLL clock synth esis provid es supp ly noise r ejection, simplifying
the task of gene rating low-jitter clo cks in n oisy environme nts. The Si597 IC-
based quad frequency VCXO is factory-configurable for a wide variety of
user specifications including frequencies, supply voltage, output format,
tuning slope, and absolute pull range (APR). Specific configurations are
factory programmed at time of shipment, thereby eliminating the long lead
times associated with custom oscillators.
Functional Block Diagram
Available with any-frequency
output from 10 to 810 MHz
4 selectable output frequencies
3rd generation DSPLL® with
superior jitter performance
Internal fixed fundamental mode
crystal frequency ensures high
reliability and low aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
–40 to +85 ºC operating range
SONET/SDH (OC-3/12/48)
Networking
SD/HD SDI/3G SDI video
OTN
Clock recovery and jitter cleanup PLLs
FPGA/ASIC clock generation
Any Frequency
10–810 M Hz
DS PLL
C lock Synthesis
CLK+
CLK-
VDD
Pow er Supply Filtering
Pow er Supply F iltering
OE
GND
Control
FS0 FS1
Fixed
Frequency
Oscillator
VcADC
Ordering Information:
See page 8.
Pin Assignments:
See page 7.
(Top View)
Si5602
1
2
3
6
5
4
VC
GND
OE
VDD
CLK+
CLK–
7
8
FS[1]
FS[0]
Si597
Si597
2 Rev. 1.1
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4. Outline Diagram and Suggested Pad Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
5. 8-Pin PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
6. Si597 Mark Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Si597
Rev. 1.1 3
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Symbol Test Condition Min Typ Max Unit
Supply Voltage1VDD 3.3 V op tio n 2.97 3.3 3.63 V
2.5 V option 2.25 2.5 2.75 V
1.8 V option 1.71 1.8 1.89 V
Supply Current IDD Output enabled
LVPECL
CML
LVDS
CMOS
—
—
—
—
120
110
100
90
135
120
110
100
mA
mA
mA
mA
Tristate mode — 60 75 mA
Output Enable (OE)2 and
Frequency Select (F S[1:0]) VIH 0.75 x VDD ——V
VIL ——0.5V
Operating Temperature Range TA–40 — 85 °C
Notes:
1. Selectable parameter specified by part number. See 3. "Ordering Information" on page 8 for further details.
2. OE pin includes an internal 17 k pullup resistor to VDD for output enable active high or a 17 k pull-down resistor to
GND for output enable active low. See 3. "Ordering Information" on page 8. FS[1:0] includes internal 17 kpull-up to
VDD.
Table 2. VC Control Voltage Input
Parameter Symbol Test Conditio n Min Typ Max Unit
Control Voltage Tuning Slope1,2,3 KV10 to 90% of VDD —
—
—
—
—
45
95
125
185
380
—
—
—
—
—
ppm/V
Control Voltage Linearity4LVC BSL –5 ±1 +5 %
Incremental –10 ±5 +10 %
Modulation Bandwidth BW 9.3 10.0 10.7 kHz
VC Input Impedance ZVC 500 — — k
VC Input Capacitance CVC —50—pF
Nominal Control Voltage VCNOM @ fO—V
DD/2 — V
Control Voltage Tuning Range VC0—V
DD V
Notes:
1. Positive slope; selectable option by part number. See 3. "Ordering Information" on page 8.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absol ute Pull Range (APR)” for more inform ation.
3. KV variation is ±10% of typical values.
4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope
determined with VC ranging from 10 to 90% of VDD.
Si597
4 Rev. 1.1
Table 3. CLK± Output Frequency Characteristics
Parameter Symbol Test Condition Min Typ Max Unit
Nominal Frequency 1,2,3 fOLVDS/CML/LVPECL 10 — 810 MHz
CMOS 10 — 160 MHz
Temperature Stability1,4 TA= –40 to +85 ºC –20
–50 —
—+20
+50 ppm
ppm
Absolute Pull Range1,4 APR VDD = 3.3 V ±15 — ±370 ppm
Power up Time5tOSC ——10ms
Notes:
1. See Section 3. "Ordering Information" on page 8 for further details.
2. Specified at time of order by part number.
3. Nominal output frequency set by VCNOM =V
DD/2.
4. Selectable parameter specified by part number. See “Ordering Information”.
5. Time from power up or tristate mode to fO.
Table 4. CLK± Output Levels and Symmetry
Parameter Symbol Test Condition Min Typ Max Unit
LVPECL Output Option1VOmid-level VDD – 1.42 — VDD – 1.25 V
VOD swing (diff) 1.1 —1.9 VPP
VSE swing (single-ended) 0.55 —0.95 VPP
LVDS Output Option2VOmid-level 1.125 1.20 1.275 V
VOD swing (diff) 0.5 0.7 0.9 VPP
CML Output Option2VO2.5/3.3 V option mid-level — VDD – 1.30 — V
1.8 V option mid-level — VDD – 0.36 — VPP
VOD 2.5/3.3 V option swing (diff) 1.10 1.50 1.90 V
1.8 V option swing (diff) 0.35 0.425 0.50 VPP
CMOS Output Option3VOH 0.8 x VDD —VDD V
VOL ——0.4
V
Rise/Fall time (20/80%) tR, tFLVPECL/LVDS/CML — — 350 ps
CMOS with CL=15pF — 2 — ns
Symmetry (duty cycle) SYM LVPECL: VDD – 1.3 V (diff)
LVDS: 1.25 V (diff)
CMOS: VDD/2 45 — 55 %
Notes:
1. 50 to VDD – 2.0 V.
2. Rterm = 100 (differential).
3. CL = 15 pF. Sinking or sourcing 12 mA for VDD = 3.3V, 6mA for V
DD = 2.5V, 3mA for V
DD = 1.8 V.
Si597
Rev. 1.1 5
Table 5. CLK± Output Phase Jitter
Parameter Symbol Test Condition Min Typ Max Unit
Phase Jitter (RMS)1,2
for FOUT of 50 MHz < FOUT <
810 MHz
JKv = 45 ppm/V
12 kHz to 20 MHz —0.5—ps
Kv = 95 ppm/V
12 kHz to 20 MHz —0.5—ps
Kv = 125 ppm/V
12 kHz to 20 MHz —0.5—ps
Kv = 185 ppm/V
12 kHz to 20 MHz —0.5—ps
Kv = 380 ppm/V
12 kHz to 20 MHz —0.7—ps
Notes:
1. Differential Modes: LVPECL/LVDS/CML. Refer to AN256 and AN266 for further information.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absol ute Pull Range (APR)” for more inform ation.
Table 6. CLK± Output Period Jitter
Parameter Symbol Test Condition Min Typ Max Unit
Period Jitter* JPER RMS — 3 — ps
Peak-to-Peak — 35 — ps
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
Table 7. CLK± Output Phase Noise (Typical)
Offset Frequency 74.25 MHz
185 ppm/V
LVPECL
148.5 MHz
185 ppm/V
LVPECL
155.52 MHz
95 ppm/V
LVPECL
Unit
100 Hz
1kHz
10 kHz
100 kHz
1MHz
10 MHz
20 MHz
–77
–101
–121
–134
–149
–151
–150
–68
–95
–116
–128
–144
–147
–148
–77
–101
–119
–127
–144
–147
–148
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Si597
6 Rev. 1.1
Table 8. Environmental Compliance and Package Information
Parameter Conditions/Test Method
Mechanical Shock MIL-STD-883, Method 2002
Mechanical Vibration MIL-STD-883, Method 2007
Solderability MIL-STD-883, Method 2003
Gross and Fine Leak MIL-STD-883, Method 1014
Resistance to Solder Heat MIL-STD-883, Method 2036
Moisture Sensitivity Level J-STD-020, MSL1
Contact Pads Gold over Nickel
Table 9. Thermal Characteristics
(Typical values TA = 25 ºC, VDD =3.3V)
Parameter Symbol Test Condition Min Typ Max Unit
Thermal Resistance Junction to Ambient JA Still Air — 84.6 — °C/W
Thermal Resistance Junction to Case JC Still Air — 38.8 — °C/W
Ambient Temperature TA–40 — 85 °C
Junction Temperature TJ——125°C
Table 10. Absolute Maximum Ratings1
Parameter Symbol Rating Unit
Maximum Op er at ing Temperature TAMAX 85 ºC
Supply Voltage, 1.8 V Option VDD –0.5 to +1.9 V
Supply Voltage, 2.5/3.3 V Option VDD –0.5 to +3.8 V
Input Voltage (any input pin) VI–0.5 to VDD + 0.3 V
Storage Temperature TS–55 to +125 ºC
ESD Sensitivity (HBM, per JESD22-A114) ESD 2000 V
Soldering Temperature (Pb -f re e pr of ile)2TPEAK 260 ºC
Soldering Temperature Time @ TPEAK (Pb-free profile)2tP20–40 seconds
Notes:
1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation or specification compliance is not implied at th ese conditions. Exposure to maximum rating conditio ns for
extended periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at
www.silabs.com/VCXO for further information, including soldering profiles.
Si597
Rev. 1.1 7
2. Pin Descriptions
Table 11. Si597 Pin Descriptions
Pin Name Type Function
1 VCAnalog Input Control Voltage
2OE* Input Output Enable
3GND Ground Electrical and Case Gr ou n d
4CLK+ Output Oscillator Output
5CLK–
(N/C for CMOS) Output Complementary Output
(N/C for CMOS, do not make external connection)
6 VDD Power Power Supply Voltage
7FS[1] Input Frequency select. Internal 17 kpull-up to VDD.
8FS[0] Input Frequency select. Internal 17 kpull-up to VDD.
*Note: OE pin includes a 17 k resistor to VDD for OE active high option or 17 k to GND for OE active low option.
See 3. "Ordering Information" on page 8.
1
2
3
6
5
4
VC
GND
OE
VDD
CLK+
CLK–
7
8
FS[0]
FS[1]
(Top View)
Si597
8 Rev. 1.1
3. Ordering Information
The Si597 supports a variety of options including frequency, temperature stability, tuning slope, output format, and
VDD. Specific device configurations are programmed into the Si597 at time of shipment. Configurations are
specified using the Part Number Configu ration chart show n below. Silicon Labs provides a web browser-based part
number configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to access this tool
and for further ordering instructions. The Si597 VCXO series is supplied in an industr y-standard, RoHS compliant,
lead-free, 8-pad, 5 x 7 mm package. Tape and reel packaging is an ordering option.
Figure 1. Part Number Convention
R = Tape and Reel
Blank = Coil Tape
Operating Temp Range (°C)
G –40 to +85 ° C
Device Revision Letter
597 Quad V CX O
Product Family
597 X X XXXXXX D G R
1st Option Code
VDD Output Format Output Enable Polarity
A 3.3 LVPECL High
B 3.3 LVDS High
C 3.3 CMOS High
D3.3CML High
E 2.5 LVPECL High
F 2.5 LVDS High
G 2.5 CMOS High
H2.5CML High
J 1.8 CMOS High
K1.8CML High
M 3.3 LVPECL Low
N 3.3 LVDS Low
P 3.3 CMOS Low
Q 3.3 CML Low
R 2.5 LVPECL Low
S 2.5 LVDS Low
T 2.5 CMOS Low
U 2.5 CML Low
V 1.8 CMOS Low
W 1.8 CML Low
Note:
CMOS available to 160 MHz.
2nd Option Code
Temper ature Tuning Slope Minimum APR
Stability Kv (±ppm) for VDD @
Code ± ppm (max) ppm/V (typ) 3.3 V 2.5 V 1.8 V
A 20 380 370 275 200
B 20 185 160 110 80
C 50 185 130 80 50
D 20 125 100 75 40
E20 95 655025
F 50 125 70 45 10
G 50 95 35 20 N/A
H20 45 15N/AN/A
Notes:
1. For best jitter and phase noise per form ance, always choose the smallest Kv that meets
the application’s minim um APR requirements. Lower Kv options minimize noise
coupling and jitter in real-world PLL designs. See AN266 for mo re information.
2. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an
APR of ±100 ppm is able to lock to a clock with a ±100 ppm stability over 15 years over
all operating conditions.
3. No minal Pull range (±) = 0.5 x VDD x tuning slope.
4. Minimum APR values noted above include worst case values for all par ameters.
6-digit Frequency Designator Code
Four unique frequencies can be specified within the following
frequency range: 10 to 810 MHz. A six digit code will be assigned for
the specified comb ination of frequencies. Codes > 000100 refer to
VCXOs programmed with the lowest frequency value selected when
FS [1:0] = 00, and the highest value when FS[1:0] = 11. Six digit codes
< 000100 refer to VCXOs programmed with the highest frequency
value selected when FS[1:0] = 00, and the lowest value when FS[1:0]
= 11.
Si597
Rev. 1.1 9
4. Outline Diagram and Suggested Pad Layout
Figure 2 illustrates the package details for the Si598/Si599. Table 12 lists the values for the dimensions shown in
the illustration.
Figure 2. Si597 Outline Diagram
Table 12. Package Diagram Dimensions (mm)
Dimension Min Nom Max
A 1.50 1.65 1.80
b 1.30 1.40 1.50
b1 0.90 1.00 1.10
c 0.50 0.60 0.70
c1 0.30 — 0.60
D 5.00 BSC
D1 4.30 4.40 4.50
e 2.54 BSC
E 7 .00 BSC
E1 6.10 6.20 6.30
H 0.55 0.65 0.75
L 1.17 1.27 1.37
L1 1.07 1.17 1.27
p 1.80 — 2.60
R0.70 REF
aaa — — 0.15
bbb — — 0.15
ccc — — 0.10
ddd — — 0.10
eee — — 0.05
Note:
1. All dimensions shown are in millimeters (mm) unl ess oth erwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-19 94.
Si597
10 Rev. 1.1
5. 8-Pin PCB Land Pattern
Figure 3 illustrates the 8-pin PCB land pattern for the Si597. Table 13 lists the values for the dimensions shown in
the illustration.
Figure 3. Si597 PCB Land Pattern
Table 13. PCB Land Pattern Dimensions (mm)
Dimension Min Max
D2 5.08 REF
D3 5.705 REF
e 2.54 BSC
E2 4.20 REF
GD 0.84 —
GE 2.00 —
VD 8.20 REF
VE 7.30 REF
X1 1.70 TYP
X2 1.545 TYP
Y1 2.15 REF
Y2 1.3 REF
ZD — 6.78
ZE — 6.30
Note:
1. Dimensioning and tolerancing per the ANSI Y14.5M-1994
specification.
2. Land pattern design follows IPC-7351 guidelines.
3. All dimensions shown are at maximum material condition (MMC).
4. Controlling dimension is in millimeters (mm).
Si597
Rev. 1.1 11
6. Si597 Mark Specification
Figure 4 illustrates the mark specification for the Si597. Table 14 lists the line information.
Figure 4. Mark Specification
Table 14. Si5xx Top Mark Description
Line Position Description
1 1–10 “SiLabs”+ Part Family Number, 597 (First 3 characters in part number)
2 1–10 Si597: Option1+Option2+Freq(6)+Temp
3 Trace Code
Position 1 Pin 1 orientation mark (dot)
Position 2 Product Revision (D)
Position 3–6 Tiny Trace Code (4 alphanumeric characters per assembly release instructions)
Position 7 Year (least significant year digit), to be assigned by assembly site (ex: 2009 = 9)
Position 8–9 Calendar Work Week number (1–53), to be assigned by assembly site
Position 10 “+” to indicate Pb-Free and RoHS-compliant
Si597
12 Rev. 1.1
REVISION HISTORY
Revision 1.1
June, 2018
Changed “Trays” to “Coil Tape” in 3. "Ordering Information" on page 8.
Revision 1.0
Changed frequency r ange to 10 to 810 MHz.
Changed output frequencies in Description section on page 1.
Updated functional block diagram on page 1.
Corrected the mechanical drawing’s pinout to match the device on page 1.
Deleted frequency information from Note 2 in Table 3 on page 3.
Changed CML output option table specs in Table 4 on page 3.
Added Table 9 on page 6.
Updated Figu re 2 on page 9.
Corrected marking information in Figure 4 on page 11.
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intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
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