Copyright 2001 Cirrus Logic (All Rights Reserved) July ’01
DS506PP1
1
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
High-Performance,
Low-Power System on Chip with
SDRAM and Enhanced Digital
Audio Interface
EP7311 Data Sheet
OVERVIEW
BLOCK DIAGRAM
FEATURES
(cont.) (cont.)
ARM720T Processor
—ARM7TDMI CPU
8 KB of four-way set-associative cache
MMU with 64-entry TLB
Thumb code support enabled
Ultra low power
90 mW at 74 MHz typical
30 mW at 18 MHz typical
10 mW in the Idle State
<1 mW in the Standby State
48 KB of on-chip SRAM
MaverickKey IDs
32-bit unique ID can be used for SDMI compliance
128-bit random ID
Dynamically programmable clock speeds of
18, 36, 49, and 74 MHz
LCD
Controller
Boot
ROM
MaverickKey
TM
ARM7TDMI CPU Core
MMU
8 KB
Cache
Write
Buffer
Internal Data Bus
EPB Bus
Memory Controller
SDRAM I/FSRAM I/F
On-chip SRAM
48 KB
ICE-JTAG
Clocks &
Timers
Keypad&
Touch
Screen I/F
Interrupts,
PWM & GPIO
Bus
Bridge
(2) UARTs
w/ IrDA
Power
Management
Serial
Interface
Multimedia
Codec Port
ARM720T
MEMORY AND STORAGE
USER INTERFACE
SERIAL PORTS
The Maverick EP7311 is designed for ultra-low-power
applications such as PDAs, smart cellular phones, and
industrial hand held information appliances. The core-
logic functionality of the device is built around an
ARM720T processor with 8 KB of four-way set-
associative unified cache and a write buffer. Incorporated
into the ARM720T is an enhanced memory management
unit (MMU) which allows for support of sophisticated
operating systems like Linux®.
2Copyright 2001 Cirrus Logic (All Rights Reserved) DS506PP1
EP7311
High-Performance, Low-Power System on Chip
FEATURES (cont)
LCD controller
Interfaces directly to a single-scan panel
monochrome STN LCD
Interfaces to a single-scan panel color STN LCD
with minimal external glue logic
Full JTAG boundary scan and Embedded ICE
support
Integrated Peripheral Interfaces
32-bit SDRAM Interface up to 2 external banks
8/32/16-bit SRAM/FLASH/ROM Interface
Multimedia Codec Port
Two Synchronous Serial Interfaces (SSI1, SSI2)
CODEC Sound Interface
8×8Keypad Scanner
27 General Purpose Input/Output pins
Dedicated LED flasher pin from the RTC
Internal Peripherals
Two 16550 compatible UARTs
IrDA Interface
Two PWM Interfaces
Real-time Clock
Two general purpose 16-bit timers
Interrupt Controller
Boot ROM
Package
208-Pin LQFP
256-Ball PBGA
204-Ball TFBGA
The fully static EP7311 is optimized for low power
dissipation and is fabricated on a 0.25 micron CMOS
process
Development Kits
EDB7312: Development Kit with color STN LCD
on board.
EDB7312-LW: EDB7312 with Lynuxworks
BlueCat Linux Tools and software for Windows
host (free 30 day BlueCat support from
Lynuxworks).
EDB7312-LL: EDB7312 with Lynuxworks BlueCat
Linux Tools and software for Linux host (free 30
day BlueCat support from Lynuxworks).
Note: * BlueCat available separately through Lynuxworks
only.
* Use the EDB7312 Development Kit for all the EP73xx
devices.
OVERVIEW (cont.)
The EP7311 is designed for low-power operation. Its core
operates at only 2.5 V, while its I/O has an operation
range of 2.5 V3.3 V. The device has three basic power
states: operating, idle and standby.
One of its notable features is MaverickKey unique IDs.
These are factory programmed IDs in response to the
growing concern over secure web content and commerce.
With Internet security playing an important role in the
delivery of digital media such as books or music,
traditional software methods are quickly becoming
unreliable. The MaverickKey unique IDs consist of two
registers, one 32-bit series register and one random 128-
bit register that may be used by an OEM for an
authentication mechanism.
Simply by adding desired memory and peripherals to the
highly integrated EP7311 completes a low-power system
solution. All necessary interface logic is integrated on-
chip.
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/sales.cfm
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information de-
scribes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this
document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied).
No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property
of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval
system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from
any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval
system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore,
no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus
Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some
jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
DS506PP1 Copyright 2001 Cirrus Logic (All Rights Reserved) 3
EP7311
High-Performance, Low-Power System on Chip
Processor Core - ARM720T
The EP7311 incorporates an ARM 32-bit RISC
microcontroller that controls a wide range of on-chip
peripherals. The processor utilizes a three-stage pipeline
consisting of fetch, decode and execute stages. Key
features include:
ARM (32-bit) and Thumb (16-bit compressed)
instruction sets
Enhanced MMU for Microsoft Windows CE and other
operating systems
8 KB of 4-way set-associative cache.
Translation Look Aside Buffers with 64 Translated
Entries
Power Management
The EP7311 is designed for ultra-low-power operation.
Its core operates at only 2.5 V, while its I/O has an
operation range of 2.5 V3.3 V allowing the device to
achieve a performance level equivalent to 60 MIPS. The
device has three basic power states:
Operating This state is the full performance
state. All the clocks and peripheral logic are
enabled.
Idle This state is the same as the Operating
State, except the CPU clock is halted while
waiting for an event such as a key press.
Standby This state is equivalent to the
computer being switched off (no display), and
the main oscillator shut down. An event such as
a key press can wake-up the processor.
MaverickKey Unique ID
MaverickKey unique hardware programmed IDs are a
solution to the growing concern over secure web content
and commerce. With Internet security playing an
important role in the delivery of digital media such as
books or music, traditional software methods are quickly
becoming unreliable. The MaverickKey unique IDs
provide OEMs with a method of utilizing specific
hardware IDs such as those assigned for SDMI (Secure
Digital Music Initiative) or any other authentication
mechanism.
Both a specific 32-bit ID as well as a 128-bit random ID is
programmed into the EP7311 through the use of laser
probing technology. These IDs can then be used to match
secure copyrighted content with the ID of the target
device the EP7311 is powering, and then deliver the
copyrighted information over a secure connection. In
addition, secure transactions can benefit by also
matching device IDs to server IDs. MaverickKey IDs
provide a level of hardware security required for todays
Internet appliances.
Memory Interfaces
There are two main external memory interfaces. The first
one is the ROM/SRAM/FLASH-style interface that has
programmable wait-state timings and includes burst-
mode capability, with six chip selects decoding six
256 MB sections of addressable space. For maximum
flexibility, each bank can be specified to be 8-, 16-, or 32-
bits wide. This allows the use of 8-bit-wide boot ROM
options to minimize overall system cost. The on-chip
boot ROM can be used in product manufacturing to
serially download system code into system FLASH
memory. To further minimize system memory
requirements and cost, the ARM Thumb instruction set is
supported, providing for the use of high-speed 32-bit
operations in 16-bit op-codes and yielding industry-
leading code density.
Note: Pins are multiplexed. See Table S on page 8 for more
information.
Pin Mnemonic I/O Pin Description
BATOK I Battery ok input
nEXTPWR I External power supply sense
input
nPWRFL I Power fail sense input
nBATCHG I Battery changed sense input
Table A. Power Management Pin Assignments
Pin Mnemonic I/O Pin Description
nCS[5:0] O Chip select out
A[27:0] O Address output
D[31:0] I/O Data I/O
nMOE/nSDCAS (Note) O ROM expansion OP enable
nMWE/nSDWE (Note) O ROM expansion write enable
HALFWORD O Halfword access select
output
WORD O Word access select output
WRITE/nSDRAS (Note) O Transfer direction
Table B. Static Memory Interface Pin Assignments
4Copyright 2001 Cirrus Logic (All Rights Reserved) DS506PP1
EP7311
High-Performance, Low-Power System on Chip
The second is the programmable 16- or 32-bit-wide
SDRAM interface that allows direct connection of up to
two banks of SDRAM, totaling 512 Mb. To assure the
lowest possible power consumption, the EP7311
supports self-refresh SDRAMs, which are placed in a
low-power state by the device when it enters the low-
power Standby State.
Note: 1. Pins A[27:13] map to DRA[0:14] respectively.
(i.e. A[27}/DRA[0}, A[26}/DRA[1], etc.) This is to
balance the load for large memory systems.
2. Pins are multiplexed. See Table S on page 8 for
more information.
Digital Audio Capability
The EP7311 uses its powerful 32-bit RISC processing
engine to implement audio decompression algorithms in
software. The nature of the on-board RISC processor, and
the availability of efficient C-compilers and other
software development tools, ensures that a wide range of
audio decompression algorithms can easily be ported to
and run on the EP7311
Universal Asynchronous
Receiver/Transmitters (UARTs)
The EP7311 includes two 16550-type UARTs for RS-232
serial communications, both of which have two 16-byte
FIFOs for receiving and transmitting data. The UARTs
support bit rates up to 115.2 kbps. An IrDA SIR protocol
encoder/decoder can be optionally switched into the
RX/TX signals to/from UART 1 to enable these signals
to drive an infrared communication interface directly.
Multimedia Codec Port (MCP)
The Multimedia Codec Port provides access to an audio
codec, a telecom codec, a touchscreen interface, four
general purpose analog-to-digital converter inputs, and
ten programmable digital I/O lines.
Note: See Table R on page 8 for information on pin
multiplexes.
Pin Mnemonic I/O Pin Description
SDCLK O SDRAM clock output
SDCKE O SDRAM clock enable output
nSDCS[1:0] O SDRAM chip select out
WRITE/nSDRAS (Note 2) O SDRAM RAS signal output
nMOE/nSDCAS (Note 2) O SDRAM CAS control signal
nMWE/nSDWE (Note 2) O SDRAM write enable control
signal
A[27:15]/DRA[0:12] (Note 1) O SDRAM address
A[14:13]/DRA[12:14] O SDRAM internal bank select
PD[7:6]/SDQM[1:0] (Note 2) I/O SDRAM byte lane mask
SDQM[3:2] O SDRAM byte lane mask
D[31:0] I/O Data I/O
Table C. SDRAM Interface Pin Assignments
Pin Mnemonic I/O Pin Description
TXD[1] O UART 1 transmit
RXD[1] I UART 1 receive
CTS I UART 1 clear to send
DCD I UART 1 data carrier detect
DSR I UART 1 data set ready
TXD[2] O UART 2 transmit
RXD[2] I UART 2 receive
LEDDRV O Infrared LED drive output
PHDIN I Photo diode input
Table D. Universal Asynchronous Receiver/Transmitters Pin
Assignments
Pin Mnemonic I/O Pin Description
SIBCLK O Serial bit clock
SIBDOUT O Serial data out
SIBDIN I Serial data in
SIBSYNC O Sample clock
Table E. MCP Interface Pin Assignments
DS506PP1 Copyright 2001 Cirrus Logic (All Rights Reserved) 5
EP7311
High-Performance, Low-Power System on Chip
CODEC Interface
The EP7311 includes an interface to telephony-type
CODECs for easy integration into voice-over-IP and
other voice communications systems. The CODEC
interface is multiplexed to the same pins as the MCP and
SSI2.
Note: See Table R on page 8 for information on pin
multiplexes.
SSI2 Interface
An additional SPI/Microwire1-compatible interface is
available for both master and slave mode
communications. The SSI2 unit shares the same pins as
the MCP and CODEC interfaces through a multiplexer.
Synchronous clock speeds of up to 512 kHz
Separate 16 entry TX and RX half-word wide FIFOs
Half empty/full interrupts for FIFOs
Separate RX and TX frame sync signals for
asymmetric traffic
Note: See Table R on page 8 for information on pin
multiplexes.
Synchronous Serial Interface
ADC (SSI) Interface: Master mode only; SPI and
Microwire1-compatible (128 kbps operation)
Selectable serial clock polarity
LCD Controller
A DMA address generator is provided that fetches video
display data for the LCD controller from memory. The
display frame buffer start address is programmable,
allowing the LCD frame buffer to be in SDRAM, internal
SRAM or external SRAM.
Interfaces directly to a single-scan panel monochrome
STN LCD
Interfaces to a single-scan panel color STN LCD with
minimal external glue logic
Panel width size is programmable from 32 to 1024
pixels in 16-pixel increments
Video frame buffer size programmable up to
128 KB
Bits per pixel of 1, 2, or 4 bits
Pin Mnemonic I/O Pin Description
PCMCLK O Serial bit clock
PCMOUT O Serial data out
PCMIN I Serial data in
PCMSYNC O Frame sync
Table F. CODEC Interface Pin Assignments
Pin Mnemonic I/O Pin Description
SSICLK I/O Serial bit clock
SSITXDA O Serial data out
SSIRXDA I Serial data in
SSITXFR I/O Transmit frame sync
SSIRXFR I/O Receive frame sync
Table G. SSI2 Interface Pin Assignments
Pin Mnemonic I/O Pin Description
ADCLK O SSI1 ADC serial clock
ADCIN I SSI1 ADC serial input
ADCOUT O SSI1 ADC serial output
nADCCS O SSI1 ADC chip select
SMPCLK O SSI1 ADC sample clock
Table H. Serial Interface Pin Assignments
Pin Mnemonic I/O Pin Description
CL1 O LCD line clock
CL2 O LCD pixel clock out
DD[3:0] O LCD serial display data bus
FRM O LCD frame synchronization pulse
M O LCD AC bias drive
Table I. LCD Interface Pin Assignments
6Copyright 2001 Cirrus Logic (All Rights Reserved) DS506PP1
EP7311
High-Performance, Low-Power System on Chip
64-Keypad Interface
Matrix keyboards and keypads can be easily read by the
EP7311. A dedicated 8-bit column driver output
generates strobes for each keyboard column signal. The
pins of Port A, when configured as inputs, can be
selectively ORed together to provide a keyboard
interrupt that is capable of waking the system from a
STANDBY or IDLE state.
Column outputs can be individually set high with the
remaining bits left at high-impedance
Column outputs can be driven all-low, all-high, or all-
high-impedance
Keyboard interrupt driven by OR'ing together all Port
A bits
Keyboard interrupt can be used to wake up the
system
8×8 keyboard matrix usable with no external logic,
extra keys can be added with minimal glue logic
Interrupt Controller
When unexpected events arise during the execution of a
program (i.e., interrupt or memory fault) an exception is
usually generated. When these exceptions occur at the
same time, a fixed priority system determines the order
in which they are handled. The EP7311 interrupt
controller has two interrupt types: interrupt request
(IRQ) and fast interrupt request (FIQ). The interrupt
controller has the ability to control interrupts from 22
different FIQ and IRQ sources.
Supports 22 interrupts from a variety of sources (such
as UARTs, SSI1, and key matrix.)
Routes interrupt sources to the ARM720Ts IRQ or
FIQ (Fast IRQ) inputs
Five dedicated off-chip interrupt lines operate as level
sensitive interrupts
.
Note: Pins are multiplexed. See Table S on page 8 for more
information.
Real-Time Clock
The EP7311 contains a 32-bit Real Time Clock (RTC) that
can be written to and read from in the same manner as
the timer counters. It also contains a 32-bit output match
register which can be programmed to generate an
interrupt.
Driven by an external 32.768 kHz crystal oscillator
PLL and Clocking
Processor and Peripheral Clocks operate from a single
3.6864 MHz crystal or external 13 MHz clock
Programmable clock speeds allow the peripheral bus
to run at 18 MHz when the processor is set to 18 MHz
and at 36 MHz when the processor is set to 36, 49 or
74 MHz
Pin Mnemonic I/O Pin Description
COL[7:0] O Keyboard scanner column drive
Table J. Keypad Interface Pin Assignments
Pin Mnemonic I/O Pin Description
nEINT[2:1] I External interrupt
EINT[3] I External interrupt
nEXTFIQ I External Fast Interrupt input
nMEDCHG/nBROM (Note) I Media change interrupt input
Table K. Interrupt Controller Pin Assignments
Pin Mnemonic Pin Description
RTCIN Real-Time Clock Oscillator Input
RTCOUT Real-Time Clock Oscillator Output
VDDRTC Real-Time Clock Oscillator Power
VSSRTC Real-Time Clock Oscillator Ground
Table L. Real-Time Clock Pin Assignments
Pin Mnemonic Pin Description
MOSCIN Main Oscillator Input
MOSCOUT Main Oscillator Output
VDDOSC Main Oscillator Power
VSSOSC Main Oscillator Ground
Table M. PLL and Clocking Pin Assignments
DS506PP1 Copyright 2001 Cirrus Logic (All Rights Reserved) 7
EP7311
High-Performance, Low-Power System on Chip
DC-to-DC converter interface (PWM)
Provides two 96 kHz clock outputs with
programmable duty ratio (from 1-in-16 to 15-in-16)
that can be used to drive a positive or negative DC to
DC converter
Timers
Internal (RTC) timer
Two internal 16-bit programmable hardware count-
down timers
General Purpose Input/Output (GPIO)
Three 8-bit and one 3-bit GPIO ports
Supports scanning keyboard matrix
Note: Pins are multiplexed. See Table S on page 8 for more
information.
Hardware debug Interface
Full JTAG boundary scan and Embedded ICE
support
LED Flasher
A dedicated LED flasher module can be used to generate
a low frequency signal on Port D pin 0 for the purpose of
blinking an LED without CPU intervention. The LED
flasher feature is ideal as a visual annunciator in battery
powered applications, such as a voice mail indicator on a
portable phone or an appointment reminder on a PDA.
Software adjustable flash period and duty cycle
Operates from 32 kHz RTC clock
Will continue to flash in IDLE and STANDBY states
4 mA drive current
Note: Pins are multiplexed. See Table S on page 8 for more
information.
Internal Boot ROM
The internal 128 byte Boot ROM facilitates download of
saved code to the on-board SRAM/FLASH.
Packaging
The EP7311 is available in a 208-pin LQFP package, 256-
ball PBGA package or a 204-ball TFBGA package.
Pin Mnemonic I/O Pin Description
DRIVE[1:0] I/O PWM drive output
FB[1:0] I PWM feedback input
Table N. DC-to-DC Converter Interface Pin Assignments
Pin Mnemonic I/O Pin Description
PA[7:0] I GPIO port A
PB[7:0] I GPIO port B
PD[0]/LEDFLSH (Note) I/O GPIO port D
PD[5:1] I/O GPIO port D
PD[7:6]/SDQM[1:0] (Note) I/O GPIO port D
PE[1:0]/BOOTSEL[1:0] (Note) I GPIO port E
PE[2]/CLKSEL (Note) I GPIO port E
Table O. General Purpose Input/Output Pin Assignments
Pin Mnemonic I/O Pin Description
TCLK I JTAG clock
TDI I JTAG data input
TDO O JTAG data output
nTRST I JTAG async reset input
TMS I JTAG mode select
Table P. Hardware Debug Interface Pin Assignments
Pin Mnemonic I/O Pin Description
PD[0]/LEDFLSH (Note) O LED flasher driver
Table Q. LED Flasher Pin Assignments
8Copyright 2001 Cirrus Logic (All Rights Reserved) DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Pin Multiplexing
The following table shows the pin multiplexing of the
MCP, SSI2 and the CODEC. The selection between SSI2
and the CODEC is controlled by the state of the SERSEL
bit in SYSCON2. The choice between the SSI2, CODEC,
and the MCP is controlled by the MCPSEL bit in
SYSCON3 (see the EP73xx Users Manual for more
information).
The following table shows the pins that have been
multiplexed in the EP7311.
Pin
Mnemonic I/O MCP SSI2 CODEC
SSICLK I/O SIBCLK SSICLK PCMCLK
SSITXDA O SIBDOUT SSITXDA PCMOUT
SSIRXDA I SIBDIN SSIRXDA PCMIN
SSITXFR I/O SIBSYNC SSITXFR PCMSYNC
SSIRXFR I p/u SSIRXFR p/u
BUZ O
Table R. MCP/SSI2/CODEC Pin Multiplexing
Signal Block Signal Block
nMOE Static Memory nSDCAS SDRAM
nMWE Static Memory nSDWE SDRAM
WRITE Static Memory nSDRAS SDRAM
A[27:15] Static Memory DRA[0:12] SDRAM
A[14:13] Static Memory DRA[13:14] SDRAM
PD[7:6] GPIO SDQM[1:0] SDRAM
RUN System
Configuration CLKEN System
Configuration
nMEDCHG Interrupt
Controller nBROM Boot ROM
select
PD[0] GPIO LEDFLSH LED Flasher
PE[1:0] GPIO BOOTSEL[1:0] System
Configuration
PE[2] GPIO CLKSEL System
Configuration
Table S. Pin Multiplexing
DS506PP1 Copyright 2001 Cirrus Logic (All Rights Reserved) 9
EP7311
High-Performance, Low-Power System on Chip
System Design
As shown in system block diagram, simply adding
desired memory and peripherals to the highly integrated
EP7311 completes a low-power system solution. All
necessary interface logic is integrated on-chip.
Figure 1. A Maximum EP7311 Based System
Note: A system can only use one of the following peripheral
interfaces at any given time: SSI2,CODEC or MCP.
LCD
KEYBOARD
BATTERY
DC-TO-DC
CONVERTERS
ADC DIGITIZER
IR LED AND
PHOTODIODE
2× RS-232
TRANSCEIVERS
ADDITIONAL I/O
PC CARD
CONTROLLER
PC CARD
SOCKET
nCS[4]
PB0
EXPCLK
DD[0-3]
CL1
CL2
FRM
M
D[0-31]
A[0-27]
COL[0-7]
PA[0-7]
DC
INPUT
nMOE
WRITE
PB[0-7]
PD[0-7]
PE[0-2]
nPOR
nPWRFL
BATOK
nEXTPWR
nBATCHG
RUN
WAKEUP
nCS[0]
nCS[1]
DRIVE[0-1]
FB[0-1]
EP7311
ADCCLK
nADCCS
ADCOUT
ADCIN
SMPCLK
LEDDRV
PHDIN
RXD1/2
TXD1/2
DSR
CTS
DCD
CS[n]
WORD
nCS[2]
nCS[3]
×16
FLASH
×16
FLASH
×16
FLASH
EXTERNAL MEMORY-
MAPPED EXPANSION BUFFERS
BUFFERS
AND
LATCHES
×16
FLASH
POWER
SUPPLY UNIT
AND
COMPARATORS
CRYSTAL
CODEC/SSI2/
MCP
SSICLK
SSITXFR
SSITXDA
SSIRXDA
SSIRXFR
RTCIN
LEDFLSH
CRYSTAL MOSCIN
×16
SDRAM
×16
SDRAM
×16
SDRAM
×16
SDRAM
SDCS[1]
SDQM[0-3]
SDCS[0]
SDQM[0-3]
SDRAS/
SDCAS
10 Copyright 2001 Cirrus Logic (All Rights Reserved) DS506PP1
EP7311
High-Performance, Low-Power System on Chip
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Recommended Operating Conditions
DC Characteristics
All characteristics are specified at VDD = 2.5 V and VSS = 0 V over an operating temperature of 0°C to +70°C for all
frequencies of operation. The current consumption figures relate to typical conditions at 2.5 V, 18.432 MHz operation
with the PLL switched on.
DC Core, PLL, and RTC Supply Voltage 2.9 V
DC I/O Supply Voltage (Pad Ring) 3.6 V
DC Pad Input Current ±10 mA/pin; ±100 mA cumulative
Storage Temperature, No Power 40°C to +125°C
DC core, PLL, and RTC Supply Voltage 2.5 V ± 0.2 V
DC I/O Supply Voltage (Pad Ring) 2.3 V - 3.6 V
DC Input / Output Voltage OI/O supply voltage
Operating Temperature Extended -20°C to +70°C; Commercial 0°C to +70°C;
Industrial -40°C to +85°C
Symbol Parameter Min Typ Max Unit Conditions
VIH CMOS input high voltage 0.65 × VDDIO VDDIO + 0.3 VVDDIO = 2.5 V
VIL CMOS input low voltage -0.3 0.25 × VDDIO VVDDIO = 2.5 V
VT+ Schmitt trigger positive going
threshold 1.6 (Typ) 2.0 V
VT- Schmitt trigger negative going
threshold 0.8 1.2 (Typ) V
Vhst Schmitt trigger hysteresis 0.1 0.4 V VIL to VIH
VOH
CMOS output high voltagea
Output drive 1a
Output drive 2a
VDD 0.2
2.5
2.5
V
V
V
IOH = 0.1 mA
IOH = 4 mA
IOH = 12 mA
VOL
CMOS output low voltagea
Output drive 1a
Output drive 2a
0.3
0.5
0.5
V
V
V
IOL = 0.1 mA
IOL = 4mA
IOL = 12 mA
IIN Input leakage current 1.0 µA VIN = VDD or GND
IOZ Bidirectional 3-state leakage
currentb c 25 100 µA VOUT = VDD or GND
CIN Input capacitance 8 10.0 pF
DS506PP1 Copyright 2001 Cirrus Logic (All Rights Reserved) 11
EP7311
High-Performance, Low-Power System on Chip
Note: 1) All power dissipation values can be derived from taking the particular IDD current and multiplying by 2.5 V.
2) The RTC of the EP7311 should be brought up at room temperature. This is required because the RTC OSC will NOT function
properly if it is brought up at –40°C. Once operational, it will continue to operate down to –20°C extended and 0°C
commercial.
3) A typical design will provide 3.3 V to the I/O supply (i.e., VDDIO), and 2.5 V to the remaining logic. This is to allow the I/O to be
compatible with 3.3 V powered external logic (i.e., 3.3 V SDRAMs).
4) Pull-up current = 50 µA typical at VDD = 3.3 V.
COUT Output capacitance 8 10.0 pF
CI/O Transceiver capacitance 8 10.0 pF
IDDstandby
Standby current consumption
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
TBD
TBD
300 µA
Only 32 kHz oscillator running,
Cache disabled, all other I/O
static, VIH = VDD ± 0.1 V,
VIL = GND ± 0.1 V
IDDidle
Idle current consumption
Core, Osc, RTC @2.5 V
I/O @ 2.5 V
TBD
TBD
4.2 mA
Both oscillators running, CPU
static, Cache disabled, LCD
refresh active, VIH = VDD ± 0.1 V,
VIL = GND ± 0.1 V
At 13 MHz
IDDoperatin
Operating current consumption
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
TBD
TBD
mA
All system active, running typical
program, cache disabled, and
LCD inactive
VDDstandby Standby supply voltage TBD V
Minimum standby voltage for
state retention and RTC
operation only
a. See Table T on page 29.
b. Assumes buffer has no pull-up or pull-down resistors.
c. The leakage value given assumes that the pin is configured as an input pin but is not currently being driven.
Symbol Parameter Min Typ Max Unit Conditions
12 Copyright 2001 Cirrus Logic (All Rights Reserved) DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Timings
Timing Diagram Conventions
This data sheet contains one or more timing diagrams. The following key explains the components used in these
diagrams. Any variations are clearly labelled when they occur. Therefore, no additional meaning should be attached
unless specifically stated.
Timing Conditions
Unless specified otherwise, the following conditions are true for all timing measurements. All characteristics are
specified at VDD = 2.3 - 2.7 V and VSS = 0 V over an operating temperature of 0°C to +70°C. Those characteristics
marked with a # will be significantly different for 13 MHz mode because the EXPCLK is provided as an input rather
than generated internally. These timings are estimated at present. The timing values are referenced to 1/2 VDD.
Clock
High to Low
High/Low to High
Bus Change
Bus Valid
Undefined/Invalid
Valid Bus to Tristate
Bus/Signal Omission
DS506PP1 Copyright 2001 Cirrus Logic (All Rights Reserved) 13
EP7311
High-Performance, Low-Power System on Chip
SDRAM Interface
Figure 2 through Figure 5 define the timings associated with all phases of the SDRAM. The following table contains the
values for the timings of each of the SDRAM modes.
Parameter Symbol Min Typ Max Unit
SDCLK rising edge to SDCS assert delay time tCSa TBD 0 TBD ns
SDCLK rising edge to SDCS deassert delay time tCSd TBD 0 TBD ns
SDCLK rising edge to SDRAS assert delay time tRAa TBD 0 TBD ns
SDCLK rising edge to SDRAS deassert delay time tRAd TBD 0 TBD ns
SDCLK rising edge to SDRAS invalid delay time tRAnv TBD 0 TBD ns
SDCLK rising edge to SDCAS assert delay time tCAa TBD 0 TBD ns
SDCLK rising edge to SDCAS deassert delay time tCAd TBD 0 TBD ns
SDCLK rising edge to ADDR transition time tADv TBD 0 TBD ns
SDCLK rising edge to ADDR invalid delay time tADx TBD 0 TBD ns
SDCLK rising edge to SDMWE assert delay time tMWa TBD 0 TBD ns
SDCLK rising edge to SDMWE deassert delay time tMWd TBD 0 TBD ns
DATA transition to SDCLK rising edge time tDAs TBD - TBD ns
SDCLK rising edge to DATA transition hold time tDAh TBD - TBD ns
SDCLK rising edge to DATA transition delay time tDAd TBD - TBD ns
14 Copyright 2001 Cirrus Logic (All Rights Reserved) DS506PP1
EP7311
High-Performance, Low-Power System on Chip
SDRAM Load Mode Register Cycle
Figure 2. SDRAM Load Mode Register Cycle Timing Measurement
SDCLK
SDCS
SDRAS
SDCAS
ADDR
DATA
SDQM
SDMWE
tCSa
tRAa
tCAa
tMWa
tADv tADx
tRAd
tCSd
tCAd
tMWd
DS506PP1 Copyright 2001 Cirrus Logic (All Rights Reserved) 15
EP7311
High-Performance, Low-Power System on Chip
SDRAM Burst Read Cycle
Note: 1. Timings are shown with CAS latency = 2
2. Depending on clock line loading, SDCLK may be phase shifted to the right.
Figure 3. SDRAM Burst Read Cycle Timing Measurement
ADRAS ADCAS
SDCLK
SDCS
SDRAS
SDCAS
SDQM
[0:3]
ADDR
DATA
SDMWE
D1 D4D3D2
tADv tADv
tCSd
tCSa tCSa
tCAa
tRAd
tCSd
tCAd
tRAa
tDAh
tDAs
tDAh
tDAs
tDAh
tDAs
tDAh
tDAs
tRAnv
16 Copyright 2001 Cirrus Logic (All Rights Reserved) DS506PP1
EP7311
High-Performance, Low-Power System on Chip
SDRAM Burst Write Cycle
Figure 4. SDRAM Burst Write Cycle Timing Measurement
SDCLK
SDCS
SDRAS
SDCAS
SDQM
ADDR
DATA
SDMWE
0
D1
ADRAS ADCAS
D4D3D2
tCSa
tRAa
tCAa
tCSa
tCSd
tRAd
tCSd
tCAd
tADv
tDAd
tADv
tDAd tDAd tDAd
tMWa tMWd
DS506PP1 Copyright 2001 Cirrus Logic (All Rights Reserved) 17
EP7311
High-Performance, Low-Power System on Chip
SDRAM Refresh Cycle
Figure 5. SDRAM Refresh Cycle Timing Measurement
SDCLK
SDCS
SDRAS
SDCAS
SDQM
[3:0]
SDMWE
SDATA
ADDR
tCSa
tRAa
tCSd
tRAd
tCAa
tCAd
18 Copyright 2001 Cirrus Logic (All Rights Reserved) DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Static Memory
Figure 6 through Figure 9 define the timings associated with all phases of the Static Memory. The following table
contains the values for the timings of each of the Static Memory modes.
Parameter Symbol Min Typ Max Unit
EXPCLK rising edge to nCS assert delay time tCSd TBD 8 TBD ns
EXPCLK falling edge to nCS deassert hold time tCSh TBD 4 TBD ns
EXPCLK rising edge to A assert delay time tAd TBD 4 TBD ns
EXPCLK falling edge to A deassert hold time tAh TBD 8 TBD ns
EXPCLK rising edge to nMWE assert delay time tMWd TBD 4 TBD ns
EXPCLK rising edge to nMWE deassert hold time tMWh TBD 4 TBD ns
EXPCLK falling edge to nMOE assert delay time tMOEd TBD 4 TBD ns
EXPCLK falling edge to nMOE deassert hold time tMOEh TBD 4 TBD ns
EXPCLK falling edge to HALFWORD deassert delay time tHWd TBD 4 TBD ns
EXPCLK falling edge to WORD assert delay time tWDd TBD 4 TBD ns
EXPCLK rising edge to data valid delay time tDv TBD 20 TBD ns
EXPCLK falling edge to data invalid delay time tDnv TBD 8 TBD ns
Data setup to EXPCLK falling edge time tDs TBD - TBD ns
EXPCLK falling edge to data hold time tDh TBD - TBD ns
EXPCLK rising edge to WRITE assert delay time tWRd TBD 8 TBD ns
EXPREADY setup to EXPCLK falling edge time tEXs TBD - TBD ns
EXPCLK falling edge to EXPREADY hold time tEXh TBD - TBD ns
DS506PP1 Copyright 2001 Cirrus Logic (All Rights Reserved) 19
EP7311
High-Performance, Low-Power System on Chip
Static Memory Single Read Cycle
Note: 1. The cycle time can be extended by integer multiples of the clock period (27 ns at 36 MHz, 54 ns at 18.432 MHz, and
77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on
the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where
EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
Figure 6. Static Memory Single Read Cycle Timing Measurement
EXPCLK
nCS
A
nMWE
HALF-
WORD
WORD
D
WRITE
nMOE
tCSd
tAd
tCSh
tMOEh
tDh
tDs
tHWd
tWDd
tWRd
tMOEd
EXPRDY
tEXh
tEXs
20 Copyright 2001 Cirrus Logic (All Rights Reserved) DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Static Memory Single Write Cycle
Note: 1. The cycle time can be extended by integer multiples of the clock period (27 ns at 36 MHz, 54 ns at 18.432 MHz, and
77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on
the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where
EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
2. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with
valid timing under zero wait state conditions.
Figure 7. Static Memory Single Write Cycle Timing Measurement
EXPCLK
nCS
A
nMWE
HALF-
WORD
WORD
D
WRITE
tHWd
tWDd
tCSd
tAd
tMWd
tDv
tMWh
tCSh
nMOE
EXPRDY
tEXh
tEXs
DS506PP1 Copyright 2001 Cirrus Logic (All Rights Reserved) 21
EP7311
High-Performance, Low-Power System on Chip
Static Memory Burst Read Cycle
Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-0-0-0). This is the maximum number of consecutive
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
2. The cycle time can be extended by integer multiples of the clock period (27 ns at 36 MHz, 54 ns at 18.432 MHz, and
77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on
the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where
EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
3. Consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to
determine the number of wait states, and no idle cycles are inserted between successive non-sequential ROM/expansion
cycles. This improves performance so the SQAEN bit should always be set where possible.
Figure 8. Static Memory Burst Read Cycle Timing Measurement
EXPCLK
nCS
A
nMOE
HALF
WORD
WORD
D
nMWE
EXPRDY
WRITE
tCSd
tAd tAh
tAh tAh
tCSh
tMOEh
tMOEd
tEXs tEXh
tDs tDh tDs tDs tDs
tDh tDh tDh
tWRd
tHWd
tWDd
22 Copyright 2001 Cirrus Logic (All Rights Reserved) DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Static Memory Burst Write Cycle
Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-1-1-1). This is the maximum number of consecutive
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
2. The cycle time can be extended by integer multiples of the clock period (27 ns at 36 MHz, 54 ns at 18.432 MHz, and
77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on
the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where
EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
3. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with
valid timing under zero wait state conditions.
Figure 9. Static Memory Burst Write Cycle Timing Measurement
EXPCLK
nCS
A
nMOE
HALF
WORD
WORD
D
nMWE
EXPRDY
WRITE
tCSd
tAd
tMWd
tMWh
tMWd tMWd tMWd
tMWh tMWh tMWh
tAh tAh tAh
tEXs tEXh
tCSh
tDv tDv tDv
tDnv tDnv tDnv tDv
tHWd
tWDd
DS506PP1 Copyright 2001 Cirrus Logic (All Rights Reserved) 23
EP7311
High-Performance, Low-Power System on Chip
SSI1 Interface
Parameter Symbol Min Max Unit
ADCCLK falling edge to nADCCSS deassert delay time tCd TBD TBD ns
ADCIN data setup to ADCCLK rising edge time tINs TBD TBD ns
ADCIN data hold from ADCCLK rising edge time tINh TBD TBD ns
ADCCLK falling edge to data valid delay time tOvd TBD TBD ns
ADCCLK falling edge to data invalid delay time tOd TBD TBD ns
Figure 10. SSI1 Interface Timing Measurement
ADC
CLK
nADC
CSS
ADCIN
ADC
OUT
tINs tINh
tCd
tOd
tOvd
24 Copyright 2001 Cirrus Logic (All Rights Reserved) DS506PP1
EP7311
High-Performance, Low-Power System on Chip
SSI2 Interface
Parameter Symbol Min Max Unit
SSICLK period (slave mode) tclk_per 0 512 ns
SSICLK high time tclk_high 925 1025 ns
SSICLK low time tclk_low 925 1025 ns
SSICLK rise/fall time tclkrf 7ns
SSICLK rising edge to RX and/or TX frame sync high time tFRd 528 ns
SSICLK rising edge to RX and/or TX frame sync low time tFRa 448 ns
SSIRXFR and/or SSITXFR period tFR_per 750 ns
SSIRXDA setup to SSICLK falling edge time tRXs 30 ns
SSIRXDA hold from SSICLK falling edge time tRXh 40 ns
SSICLK rising edge to SSITXDA data valid delay time tTXd 80 ns
SSITXDA valid time tTXv ns
Figure 11. SSI2 Interface Timing Measurement
SSI
CLK
SSIRXFR/
SSITXFR
SSI
TXDA
SSI
RXDA D1D7
D7
D2
D2 D1
D0
D0
tclk_per tclk_high tclk_low
tFRd tFR_per
tRXs
tTXd
tFRa
tRXh
tclkrf
tTXv
DS506PP1 Copyright 2001 Cirrus Logic (All Rights Reserved) 25
EP7311
High-Performance, Low-Power System on Chip
LCD Interface
Parameter Symbol Min Max Unit
CL[1] falling to CL[2] falling time tclk 200 6,950 ns
LCD CL[2] low time tclk_low 80 3,475 ns
LCD CL[2] high time tclk_high 80 3,475 ns
CL[2] falling to CL[1] rising delay time tCL1d 025ns
CL[1] falling to CL[2] rising delay time tCL2d 80 3,475 ns
LCD CL[1] high time tCL2h 80 3,475 ns
CL[1] falling to FRM transition time tFRMd 300 10,425 ns
CL[1] falling to M transition time tMd 10 20 ns
CL[2] rising to DD (display data) transition time tDDd 10 20 ns
Figure 12. LCD Controller Timing Measurement
CL[2]
CL[1]
FRM
M
DD
[3:0]
tCL1d
tFRMd
tCL2h
tMd
tDDd
tCL2d
tclk tclk_high
tclk_low
26 Copyright 2001 Cirrus Logic (All Rights Reserved) DS506PP1
EP7311
High-Performance, Low-Power System on Chip
JTAG
Parameter Symbol Min Max Units
TCK clock period tclk_per 100 - ns
TCK clock high time tclk_high 50 - ns
TCK clock low time tclk_low 50 - ns
JTAG port setup time tJPs 20 - ns
JTAG port hold time tJPh 45 - ns
JTAG port clock to output tJPco -25ns
JTAG port high impedance to valid output tJPzx -25ns
JTAG port valid output to high impedance tJPxz -25ns
Figure 13. JTAG Timing Measurement
TDO
TCK
TDI
TMS
tJPh
tclk_high tclk_low
tJPzx tJPco tJPxz
tclk_per
tJPs
DS506PP1 Copyright 2001 Cirrus Logic (All Rights Reserved) 27
EP7311
High-Performance, Low-Power System on Chip
Packages
208-Pin LQFP Package Characteristics
208-Pin LQFP Package Specifications
Note: 1) Dimensions are in millimeters (inches), and controlling dimension is millimeter.
2) Drawing above does not reflect exact package pin count.
3) Before beginning any new design with this device, please contact Cirrus Logic for the latest package information.
4) For pin locations, please see Figure 15. For pin descriptions see the EP7311 Users Manual.
Figure 14. 208-Pin LQFP Package Outline Drawing
Pin 1 Indicator
29.60 (1.165)
30.40 (1.197)
0.17 (0.007)
0.27 (0.011)
27.80 (1.094)
28.20 (1.110)
0.50
(0.0197)
BSC
29.60 (1.165)
30.40 (1.197)
27.80 (1.094)
28.20 (1.110)
1.35 (0.053)
1.45 (0.057)
0° MIN
7° MAX
0.09 (0.004)
0.20 (0.008)
1.40 (0.055)
0.45 (0.018)
0.75 (0.030)
0.05 (0.002)
1.00 (0.039) BSC
Pin 1
Pin 208
1.60 (0.063) 0.15 (0.006)
EP7311
208-Pin LQFP
28 Copyright 2001 Cirrus Logic (All Rights Reserved) DS506PP1
EP7311
High-Performance, Low-Power System on Chip
208-Pin LQFP Pin Diagram
Note: 1. N/C should not be grounded but left as no connects.
2. Pin differences between the EP7211 and the EP7311 are bolded.
160
159
158
157
53
54
55
56
57
58
59
60
61
62
63
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
106
107
108
109
110
112
113
114
115
116
117
118
119
120
121
64
65
67
68
69
70
71
72
73
74
75
66
98
99
100
101
102
103
104
122
124
125
126
127
128
129
130
105
131
132
133
134
156
155
154
153
152
151
150
149
148
147
146
145
144
143
140
139
138
137
136
141
142
135
161
162
163
164
165
166
167
168
169
170
171
172
173
174
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
201
202
203
204
205
206
207
208
200
175
176
177
178
179
123
111
EP7311
208-Pin LQFP
(Top View)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
51
50
52
1
nEXTPWR
BATOK
nPOR
VSSOSC
VDDOSC
MOSCIN
MOSCOUT
nURESET
WAKEUP
A[6]
D[6]
A[5]
D[5]
VDDIO
VSSIO
A[4]
D[4]
A[3]
D[3]
nPWRFL
A[2]
D[2]
A[1]
A[0]
D[0]
VDDCORE
VSSIO
VDDIO
CL[2]
CL[1]
FRM
M
DD[2]
DD[1]
DD[0]
nSDCS[1]
SDQM[3]
SDQM[2]
VDDIO
VSSIO
SDCLK
nMWE/nSDWE
nMOE/nSDCAS
nCS[0]
nCS[1]
nCS[2]
nCS[3]
D[7]
A[7]
D[8]
A[8]
D[9]
D[10]
A[10]
VSSIO
VDDIO
A[11]
D[12]
A[12]
D[13]
A[13]\DRA[14]
D[14]
DD[3]
D[17]
D[15]
A[17]
/DRA[10]
nTRST
VSSIO
VDDIO
D[18]
A[18
/DRA[9]
D[19]
A[19]
/DRA[8]
D[20]
VSSIO
A[21]
/DRA[6]
D[22]
D[23]
A[23]
/DRA[4]
D[24]
VSSIO
VDDIO
A[24]
/DRA[3]
HALFWORD
A[14]/DRA[13]
nBATCHG
A[25]/DRA[2]
D[25]
D[27]
A[27]/DRA[0]
VSSIO
D[28]
D[29]
D[30]
D[31]
BUZ
COL[0]
COL[1]
TCLK
VDDIO
COL[2]
COL[3]
COL[4]
COL[5]
COL[6]
COL[7]
FB[0]
VSSIO
FB[1]
ADCOUT
ADCCLK
DRIVE[0]
VDDIO
PD[2]
VSSIO
VSSCORE
nADCCS
ADCIN
SSIRXDA
SSIRXFR
SSITXDA
SSITXFR
VSSIO
SSICLK
PD[0]/LEDFLSH
PD[1]
PD[3]
A[22]
/DRA[5]
PD[4]
VDDIO
PD[5]
PD[6]/SDQM[0]
DRIVE[1]
PD[7]/SDQM[1]
D[26]
A[15]
/DRA[12]
D[16]
A[16]
/DRA[11]
nCS[4]
VDDCORE
A[26]/DRA[1]
D[21]
TMS
A[20]
/DRA[7]
SMPCLK
D[11]
A[9]
D[1]
VSSCORE
nSDCS[0
]
SDCKE
VSSIO
VSSIO
VSSIO
VSSIO
EXPCLK
WORD
WRITE/nSDRAS
RUN/CLKEN
EXPRDY
PB[7]
PB[6]
PB[5]
PB[4]
PB[3]
PB[2]
PB[1]
VSSIO
TDI
VDDIO
TDO
PE[2]/CLKSEL
nEXTFIQ
PA[6]
PA[5]
PA[4]
PA[3]
PA[2]
PA[1]
PA[0]
LEDDRV
TXD[2]
PHDIN
CTS
RXD[2]
DCD
DSR
RTCOUT
RTCIN
VSSIO
PA[7]
VDDIO
VSSIO
nCS[5]
PB[0]
TXD[1]
RXD[1]
nTEST[1]
nTEST[0]
EINT[3]
nEINT[2]
nEINT[1]
PE[1]BOOTSEL[1]
PE[0]BOOTSEL[0]
N/C
VSSRTC
VDDRTC
Figure 15. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram
nMEDCHG/nBROM
DS506PP1 Copyright 2001 Cirrus Logic (All Rights Reserved) 29
EP7311
High-Performance, Low-Power System on Chip
208-Pin LQFP Numeric Pin Listing
Table T. 208-Pin LQFP Numeric Pin Listing
Pin
No. Signal Type Strength Reset
State
1nCS[5] O 1 Low
2 VDDIO Pad Pwr
3 VSSIO Pad Gnd
4 EXPCLK I/O 1
5WORD Out 1 Low
6 WRITE/nSDRAS Out 1 Low
7 RUN/CLKEN O 1 Low
8EXPRDY I 1
9 TXD[2] O 1 High
10 RXD[2] I
11 TDI I with p/u*
12 VSSIO Pad Gnd
13 PB[7] I/O 1 Input
14 PB[6] I/O 1 Input
15 PB[5] I/O 1 Input
16 PB[4] I/O 1 Input
17 PB[3] I/O 1 Input
18 PB[2] I/O 1 Input
19 PB[1]/PRDY2 I/O 1 Input
20 PB[0]/PRDY1 I/O 1 Input
21 VDDIO Pad Pwr
22 TDO O 1 Three state
23 PA[7] I/O 1 Input
24 PA[6] I/O 1 Input
25 PA[5] I/O 1 Input
26 PA[4] I/O 1 Input
27 PA[3] I/O 1 Input
28 PA[2] I/O 1 Input
29 PA[1] I/O 1 Input
30 PA[0] I/O 1 Input
31 LEDDRV O 1 Low
32 TXD[1] O 1 High
33 VSSIO Pad Gnd 1 High
34 PHDIN I
35 CTS I
36 RXD[1] I
37 DCD I
38 DSR I
39 nTEST[1] I With p/u*
40 nTEST[0] I With p/u*
41 EINT[3] I
42 nEINT[2] I
43 nEINT[1] I
44 nEXTFIQ I
45 PE[2]/CLKSEL I/O 1 Input
46 PE[1]/
BOOTSEL[1] I/O 1 Input
47 PE[0]/
BOOTSEL[0] I/O 1 Input
48 VSSRTC RTC Gnd
49 RTCOUT O
50 RTCIN I
51 VDDRTC RTC power
52 N/C
53 PD[7]/SDQM[1] I/O 1 Low
54 PD[6]/SDQM[0] I/O 1 Low
55 PD[5] I/O 1 Low
56 PD[4] I/O 1 Low
57 VDDIO Pad Pwr
58 TMS I with p/u*
59 PD[3] I/O 1 Low
60 PD[2] I/O 1 Low
61 PD[1] I/O 1 Low
62 PD[0]/LEDFLSH I/O 1 Low
63 SSICLK I/O 1 Input
64 VSSIO Pad Gnd
65 SSITXFR I/O 1 Low
66 SSITXDA O 1 Low
67 SSIRXDA I
68 SSIRXFR I/O Input
69 ADCIN I
70 nADCCS O 1 High
71 VSSCORE Core Gnd
72 VDDCORE Core Pwr
73 VSSIO Pad Gnd
Table T. 208-Pin LQFP Numeric Pin Listing (Continued)
Pin
No. Signal Type Strength Reset
State
30 Copyright 2001 Cirrus Logic (All Rights Reserved) DS506PP1
EP7311
High-Performance, Low-Power System on Chip
74 VDDIO Pad Pwr
75 DRIVE[1] I/O 2 High /
Low
76 DRIVE[0] I/O 2 High /
Low
77 ADCCLK O 1 Low
78 ADCOUT O 1 Low
79 SMPCLK O 1 Low
80 FB[1] I
81 VSSIO Pad Gnd
82 FB[0] I
83 COL[7] O 1 High
84 COL[6] O 1 High
85 COL[5] O 1 High
86 COL[4] O 1 High
87 COL[3] O 1 High
88 COL[2] O 1 High
89 VDDIO Pad Pwr
90 TCLK I
91 COL[1] O 1 High
92 COL[0] O 1 High
93 BUZ O 1 Low
94 D[31] I/O 1 Low
95 D[30] I/O 1 Low
96 D[29] I/O 1 Low
97 D[28] I/O 1 Low
98 VSSIO Pad Gnd
99 A[27]/DRA[0] O 2 Low
100 D[27] I/O 1 Low
101 A[26]/DRA[1] O 2 Low
102 D[26] I/O 1 Low
103 A[25]/DRA[2] O 2 Low
104 D[25] I/O 1 Low
105 HALFWORD O 1 Low
106 A[24]/DRA[3] O 1 Low
107 VDDIO Pad Pwr
108 VSSIO Pad Gnd
109 D[24] I/O 1 Low
110 A[23]/DRA[4] O 1 Low
Table T. 208-Pin LQFP Numeric Pin Listing (Continued)
Pin
No. Signal Type Strength Reset
State
111 D[23] I/O 1 Low
112 A[22]/DRA[5] O 1 Low
113 D[22] I/O 1 Low
114 A[21]/DRA[6] O 1 Low
115 D[21] I/O 1 Low
116 VSSIO Pad Gnd
117 A[20]/DRA[7] O 1 Low
118 D[20] I/O 1 Low
119 A[19]/DRA[8] O 1 Low
120 D[19] I/O 1 Low
121 A[18]/DRA[9] O 1 Low
122 D[18] I/O 1 Low
123 VDDIO Pad Pwr
124 VSSIO Pad Gnd
125 nTRST I
126 A[17]/DRA[10] O 1 Low
127 D[17] I/O 1 Low
128 A[16]/DRA[11] O 1 Low
129 D[16] I/O 1 Low
130 A[15]/DRA[12] O 1 Low
131 D[15] I/O 1 Low
132 A[14]/DRA[13] O 1 Low
133 D[14] I/O 1 Low
134 A[13]/DRA[14] O 1 Low
135 D[13] I/O 1 Low
136 A[12] O 1 Low
137 D[12] I/O 1 Low
138 A[11] O 1 Low
139 VDDIO Pad Pwr
140 VSSIO Pad Gnd
141 D[11] I/O 1 Low
142 A[10] O 1 Low
143 D[10] I/O 1 Low
144 A[9] O 1 Low
145 D[9] I/O 1 Low
146 A[8] O 1 Low
147 D[8] I/O 1 Low
148 A[7] O 1 Low
Table T. 208-Pin LQFP Numeric Pin Listing (Continued)
Pin
No. Signal Type Strength Reset
State
DS506PP1 Copyright 2001 Cirrus Logic (All Rights Reserved) 31
EP7311
High-Performance, Low-Power System on Chip
*With p/u means with internal pull-up on the pin.
149 VSSIO Pad Gnd
150 D[7] I/O 1 Low
151 nBATCHG I
152 nEXTPWR I
153 BATOK I
154 nPOR I Schmitt
155 nMEDCHG/
nBROM I
156 nURESET I Schmitt
157 VDDOSC Osc Pwr
158 MOSCIN Osc
159 MOSCOUT Osc
160 VSSOSC Osc Gnd
161 WAKEUP I Schmitt
162 nPWRFL I
163 A[6] O 1 Low
164 D[6] I/O 1 Low
165 A[5] Out 1 Low
166 D[5] I/O 1 Low
167 VDDIO Pad Pwr
168 VSSIO Pad Gnd
169 A[4] O 1 Low
170 D[4] I/O 1 Low
171 A[3] O 2 Low
172 D[3] I/O 1 Low
173 A[2] O 2 Low
174 VSSIO Pad Gnd
175 D[2] I/O 1 Low
176 A[1] O 2 Low
177 D[1] I/O 1 Low
178 A[0] O 2 Low
179 D[0] I/O 1 Low
180 VSS CORE Core Gnd
181 VDD CORE Core Pwr
182 VSSIO Pad Gnd
183 VDDIO Pad Pwr
184 CL[2] O 1 Low
185 CL[1] O 1 Low
186 FRM O 1 Low
Table T. 208-Pin LQFP Numeric Pin Listing (Continued)
Pin
No. Signal Type Strength Reset
State
187 M O 1 Low
188 DD[3] I/O 1 Low
189 DD[2] I/O 1 Low
190 VSSIO Pad Gnd
191 DD[1] I/O 1 Low
192 DD[0] I/O 1 Low
193 nSDCS[1] O 1 High
194 nSDCS[0] O 1 High
195 SDQM[3] I/O 2 Low
196 SDQM[2] I/O 2 Low
197 VDDIO Pad Pwr
198 VSSIO Pad Gnd
199 SDCKE I/O 2 Low
200 SDCLK I/O 2 Low
201 nMWE/nSDWE O 1 High
202 nMOE/nSDCAS O 1 High
203 VSSIO Pad Gnd
204 nCS[0] O 1 High
205 nCS[1] O 1 High
206 nCS[2] O 1 High
207 nCS[3] O 1 High
208 nCS[4] O 1 High
Table T. 208-Pin LQFP Numeric Pin Listing (Continued)
Pin
No. Signal Type Strength Reset
State
32 Copyright 2001 Cirrus Logic (All Rights Reserved) DS506PP1
EP7311
High-Performance, Low-Power System on Chip
204-Ball TFBGA Package Characteristics
204-Ball TFBGA Package Specifications
Figure 16. 204-Ball TFBGA Package
Ø0.25~0.35(204X)
Ø0.15 M C A B
Ø0.08 M C
0.15(4X) C
0.20~0.30
1.20 MAX.
SEATING PLANE
0.36 0.53±0.05
0.20 C
TOP VIEW BOTTOM VIEW
13±0.05
13±0.05
A
B
C
0.10 C
Ball Diameter :
Ball Pitch :
0.530.3
Substrate Thickness :
Mold Thickness :
0.65 0.36
20
Y
0.65
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
19181716151413121110987654321
12.35
0.65
17 19 20181614 1512 139101178456231
C
K
J
H
G
F
E
D
A
B
Y
W
V
U
T
R
P
N
M
L
A1 CORNER A1 CORNER
12.35
DS506PP1 Copyright 2001 Cirrus Logic (All Rights Reserved) 33
EP7311
High-Performance, Low-Power System on Chip
204-Ball TFBGA Pinout (Top View)
1 2 3 4 5 6 7 8 910111213141516 17 18 19 20
A VDDIO EXPCLK nCS3 nCS1 nMWE/
nSDWE SDQM2 nSDCS1 DD2 FRM CL1 GNDCOR
ED1 A2 D4 A5 nPWRFL MOSCOUT GNDIO GNDIO GNDIO A
B WORD VDDIO nCS5 nCS2 nMOE/
nSDCAS SDCKE nSDCS0 DD1 M CL2 D0 A1 D3 A4 D6 WAKEUP MOSCIN GNDIO GNDIO nURESET B
CRUN/
CLKEN EXPRDY VDDIO nCS4 nCS0 SDCLK SDQM3 DD0 DD3 VDDCO
RE A0 D2 A3 D5 A6 GNDOS
CVDDOSC GNDIO BATOK nPOR C
D PB7 RXD2 VDDIO GNDIO nBATCHG A7 D
E PB4 TXD2 WRITE/
nSDRAS
nMEDCHG
/nBROM nEXTPWR D9 E
F PB3 PB6 TDI D7 A8 D10 F
GPB1/
PRDY2 PB2 PB5 D8 A9 D11 G
HPA7 TDO PB0/
PRDY1 A10 D12 A12 H
J PA4 PA5 PA6 A11 D13 A13/
DRA14 J
K PA1 PA2 VDDIO D14 A14/
DRA13 D15 K
L TXD1 LEDDRV PA3 VDDIO D16 A16/
DRA11 L
MRXD1 CTS PA0 A15/
DRA12
A17/
DRA10 nTRST M
N DSR nTEST1 PHDIN D17 D19 A18/
DRA9 N
P EINT3 nEINT2 DCD D18 A20/
DRA7 D20 P
RnEXTFIQ PE2/
CLKSEL nTEST0 A19/
DRA8 D22 A21/
DRA6 R
T
PE1/
BOOT
SEL1
PE0/
BOOT
SEL0
nEINT1 D21 D23 A22/
DRA5 T
U GNDRTCRTCOUT RTCIN HALF
WORD D24 A23/
DRA4 U
V VDDRTC GNDIO GNDIO PD7/
SDQM1 PD4 PD2 SSICLK SSIRXDA nADCCS VDDIO ADCCLK COL7 COL4 TCLK BUZ D29 A26/
DRA1 VDDIO VDDIO A24/
DRA3 V
W GNDIO GNDIO GNDIO PD6/SD
QM0 TMS PD1 SSITXFR SSIRXFR GNDCO
RE DRIVE1 ADCOUT FB0 COL5 COL2 COL0 D30 A27/
DRA0 D26 VDDIO D25 W
Y GNDIO GNDIO GNDIO PD5 PD3
PD0/
LED
FLSH
SSITXDA ADCIN VDDCO
RE DRIVE0 SMPLCK FB1 COL6 COL3 COL1 D31 D28 D27 A25/
DRA2 VDDIO Y
34 Copyright 2001 Cirrus Logic (All Rights Reserved) DS506PP1
EP7311
High-Performance, Low-Power System on Chip
TFBGA Ball List
Table U. 204-Ball TFBGA Ball List
Die Pad Bond Pad Package Ball Signal
U2.1 1 B3 nCS5
U2.2 2 Y20 VDDIO
U2.3 3 B18 GNDIO
U2.4 4 A2 EXPCLK
U2.5 5 B1 WORD
U2.6 6 E3 WRITE/nSDRAS
U2.7 7 C1 RUN/CLKEN
U2.8 8 C2 EXPRDY
U2.9 9 E2 TXD2
U2.10 10 D2 RXD2
U2.11 11 F3 TDI
U2.12 12 B18 GNDIO
U2.13 13 D1 PB7
U2.14 14 F2 PB6
U2.15 15 G3 PB5
U2.16 16 E1 PB4
U2.17 17 F1 PB3
U2.18 18 G2 PB2
U2.19 19 G1 PB1/PRDY2
U2.20 20 H3 PB0/PRDY1
U2.21 21 Y20 VDDIO
U2.22 22 H2 TDO
U2.23 23 H1 PA7
U2.24 24 J3 PA6
U2.25 25 J2 PA5
U2.26 26 J1 PA4
U2.27 27 L3 PA3
U2.28 28 K2 PA2
U2.29 29 K1 PA1
U2.30 30 M3 PA0
U2.31 31 L2 LEDDRV
U2.32 32 L1 TXD1
U2.33 33 B18 GNDIO
U2.34 34 N3 PHDIN
U2.35 35 M2 CTS
U2.36 36 M1 RXD1
U2.37 37 P3 DCD
U2.38 38 N1 DSR
U2.39 39 N2 nTEST1
U2.40 40 R3 nTEST0
U2.41 41 P1 EINT3
U2.42 42 P2 nEINT2
U2.43 43 T3 nEINT1
U2.44 44 R1 nEXTFIQ
U2.45 45 R2 PE2/CLKSEL
U2.46 46 T1 PE1/BOOTSEL1
U2.47 47 T2 PE0/BOOTSEL0
U2.48 48 U1 GNDRTC
U2.49 49 U2 RTCOUT
U2.50 50 U3 RTCIN
U2.51 51 V1 VDDRTC
U2.53 52 V4 PD7/SDQM1
U2.54 53 W4 PD6/SDQM0
U2.55 54 Y4 PD5
U2.56 55 V5 PD4
U2.57 56 L18 VDDIO
U2.58 57 W5 TMS
U2.59 58 Y5 PD3
U2.60 59 V6 PD2
U2.61 60 W6 PD1
U2.62 61 Y6 PD0/LEDFLSH
U2.63 62 V7 SSICLK
U2.64 63 D18 GNDIO
U2.65 64 W7 SSITXFR
U2.66 65 Y7 SSITXDA
U2.67 66 V8 SSIRXDA
U2.68 67 W8 SSIRXFR
U2.69 68 Y8 ADCIN
U2.70 69 V9 nADCCS
U2.71 70 W9 GNDCORE
U2.72 71 Y9 VDDCORE
U2.73 72 W3 GNDIO
U2.74 73 V10 VDDIO
U2.75 74 L18 VDDIO
U2.76 75 W10 DRIVE1
U2.77 76 Y10 DRIVE0
U2.78 77 V11 ADCCLK
Table U. 204-Ball TFBGA Ball List (Continued)
Die Pad Bond Pad Package Ball Signal
DS506PP1 Copyright 2001 Cirrus Logic (All Rights Reserved) 35
EP7311
High-Performance, Low-Power System on Chip
U2.79 78 W11 ADCOUT
U2.80 79 Y11 SMPLCK
U2.81 80 Y12 FB1
U2.82 81 Y3 GNDIO
U2.83 82 W12 FB0
U2.84 83 V12 COL7
U2.85 84 Y13 COL6
U2.86 85 W13 COL5
U2.87 86 V13 COL4
U2.88 87 Y14 COL3
U2.89 88 W14 COL2
U2.90 89 A1 VDDIO
U2.91 90 V14 TCLK
U2.92 91 Y15 COL1
U2.93 92 W15 COL0
U2.94 93 V15 BUZ
U2.95 94 Y16 D31
U2.96 95 W16 D30
U2.97 96 V16 D29
U2.98 97 Y17 D28
U2.99 98 Y3 GNDIO
U2.100 99 W17 A27/DRA0
U2.101 100 Y18 D27
U2.102 101 V17 A26/DRA1
U2.103 102 W18 D26
U2.104 103 Y19 A25/DRA2
U2.105 104 W20 D25
U2.106 105 U18 HALFWORD
U2.107 106 V20 A24/DRA3
U2.108 107 A1 VDDIO
U2.109 108 Y3 GNDIO
U2.110 109 U19 D24
U2.111 110 U20 A23/DRA4
U2.112 111 T19 D23
U2.113 112 T20 A22/DRA5
U2.114 113 R19 D22
U2.115 114 R20 A21/DRA6
U2.116 115 T18 D21
U2.117 116 Y3 GNDIO
Table U. 204-Ball TFBGA Ball List (Continued)
Die Pad Bond Pad Package Ball Signal
U2.118 117 P19 A20/DRA7
U2.119 118 P20 D20
U2.120 119 R18 A19/DRA8
U2.121 120 N19 D19
U2.122 121 N20 A18/DRA9
U2.123 122 P18 D18
U2.124 123 A1 VDDIO
U2.125 124 Y3 GNDIO
U2.126 125 M20 nTRST
U2.127 126 M19 A17/DRA10
U2.128 127 N18 D17
U2.129 128 L20 A16/DRA11
U2.130 129 L19 D16
U2.131 130 M18 A15/DRA12
U2.132 131 K20 D15
U2.133 132 K19 A14/DRA13
U2.134 133 K18 D14
U2.135 134 J20 A13/DRA14
U2.136 135 J19 D13
U2.137 136 H20 A12
U2.138 137 H19 D12
U2.139 138 J18 A11
U2.140 139 K3 VDDIO
U2.141 140 Y3 GNDIO
U2.142 141 G20 D11
U2.143 142 H18 A10
U2.144 143 F20 D10
U2.145 144 G19 A9
U2.146 145 E20 D9
U2.147 146 F19 A8
U2.148 147 G18 D8
U2.149 148 D20 A7
U2.150 149 Y3 GNDIO
U2.151 150 F18 D7
U2.152 151 D19 nBATCHG
U2.153 152 E19 nEXTPWR
U2.154 153 C19 BATOK
U2.155 154 C20 nPOR
U2.156 155 E18 nMEDCHG/nBROM
Table U. 204-Ball TFBGA Ball List (Continued)
Die Pad Bond Pad Package Ball Signal
36 Copyright 2001 Cirrus Logic (All Rights Reserved) DS506PP1
EP7311
High-Performance, Low-Power System on Chip
U2.157 156 B20 nURESET
U2.158 157 C17 VDDOSC
U2.159 158 B17 MOSCIN
U2.160 159 A17 MOSCOUT
U2.161 160 C16 GNDOSC
U2.162 161 B16 WAKEUP
U2.163 162 A16 nPWRFL
U2.164 163 C15 A6
U2.165 164 B15 D6
U2.166 165 A15 A5
U2.167 166 C14 D5
U2.168 167 A1 VDDIO
U2.169 168 Y3 GNDIO
U2.170 169 B14 A4
U2.171 170 A14 D4
U2.172 171 C13 A3
U2.173 172 B13 D3
U2.174 173 A13 A2
U2.175 174 Y3 GNDIO
U2.176 175 C12 D2
U2.177 176 B12 A1
U2.178 177 A12 D1
U2.179 178 C11 A0
U2.180 179 B11 D0
U2.181 180 A11 GNDCORE
U2.182 181 C10 VDDCORE
U2.183 182 Y3 GNDIO
U2.184 183 Y20 VDDIO
U2.185 184 B10 CL2
U2.186 185 A10 CL1
U2.187 186 A9 FRM
U2.188 187 B9 M
U2.189 188 C9 DD3
U2.190 189 A8 DD2
U2.191 190 Y3 GNDIO
U2.192 191 B8 DD1
U2.193 192 C8 DD0
U2.194 193 A7 nSDCS1
U2.195 194 B7 nSDCS0
Table U. 204-Ball TFBGA Ball List (Continued)
Die Pad Bond Pad Package Ball Signal
U2.196 195 C7 SDQM3
U2.197 196 A6 SDQM2
U2.198 197 V18 VDDIO
U2.199 198 B18 GNDIO
U2.200 199 B6 SDCKE
U2.201 200 C6 SDCLK
U2.202 201 A5 nMWE/nSDWE
U2.203 202 B5 nMOE/nSDCAS
U2.204 203 B18 GNDIO
U2.205 204 C5 nCS0
U2.206 205 A4 nCS1
U2.207 206 B4 nCS2
U2.208 207 A3 nCS3
U2.209 208 C4 nCS4
A1 VDDIO
B2 VDDIO
C3 VDDIO
D3 VDDIO
K3 VDDIO
L18 VDDIO
V18 VDDIO
V19 VDDIO
W19 VDDIO
Y20 VDDIO
A18 GNDIO
A19 GNDIO
A20 GNDIO
B18 GNDIO
B19 GNDIO
C18 GNDIO
D18 GNDIO
V2 GNDIO
V3 GNDIO
W1 GNDIO
W2 GNDIO
W3 GNDIO
Y1 GNDIO
Y2 GNDIO
Y3 GNDIO
Table U. 204-Ball TFBGA Ball List (Continued)
Die Pad Bond Pad Package Ball Signal
DS506PP1 Copyright 2001 Cirrus Logic (All Rights Reserved) 37
EP7311
High-Performance, Low-Power System on Chip
256-Ball PBGA Package Characteristics
256-Ball PBGA Package Specifications
Figure 17. 256-Ball PBGA Package
Note: 1) For pin locations see Table V.
2) Dimensions are in millimeters (inches), and controlling dimension is millimeter
3) Before beginning any new EP7311 design, contact Cirrus Logic for the latest package information.
TOP VIEW
17.00 (0.669)
15.00 (0.590)
SIDE VIEW
BOTTOM VIEW
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
1.00 (0.040)
Pin 1 Indicator
Pin 1 Corner
Pin 1 Corner
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
15.00 (0.590)
2 Layer
17.00 (0.669)
17.00 (0.669)
1.00 (0.040)
1.00 (0.040)
1.00 (0.040)
30° TYP
REF
REF
0.50
3 Places
0.85 (0.034)
±0.05 (.002)
0.40 (0.016)
±0.05 (.002)
0.36 (0.014)
17.00 (0.669)
R
D1
E1
D
E
±0.20 (.008)
±0.20 (.008)
±0.20 (.008)
±0.20 (.008)
±0.09 (0.004)
JEDEC #: MO-151
Ball Diameter: 0.50 mm ± 0.10 mm
17 ¥ 17 ¥ 1.61 mm body
38 Copyright 2001 Cirrus Logic (All Rights Reserved) DS506PP1
EP7311
High-Performance, Low-Power System on Chip
256-Ball PBGA Pinout (Top View)
1 2 3 4 5 6 7 8 910111213141516
A VDDIO nCS[4] nCS[1] SDCLK SDQM[3] DD[1] M VDDIO D[0] D[2] A[3] VDDIO A[6] MOSCOUT VDDOSC VSSIO A
B nCS[5] VDDIO nCS[3] nMOE/
nSDCAS VDDIO nSDCS[1] DD[2] CL[1] VDDCORE D[1] A[2] A[4] A[5] WAKEUP VDDIO nURESET B
C VDDIO EXPCLK VSSIO VDDIO VSSIO VSSIO VSSIO VDDIO VSSIO VSSIO VSSIO VDDIO VSSIO VSSIO nPOR nEXTPWR C
DWRITE/
nSDRAS EXPRDY VSSIO VDDIO nCS[2] nMWE/
nSDWE nSDCS[0] CL[2] VSSRTC D[4] nPWRFL MOSCIN VDDIO VSSIO D[7] D[8] D
E RXD[2] PB[7] TDI WORD VSSIO nCS[0] SDQM[2] FRM A[0] D[5] VSSOSC VSSIO nMEDCHG/
nBROM VDDIO D[9] D[10] E
F PB[5] PB[3] VSSIO TXD[2] RUN/
CLKEN VSSIO SDCKE DD[3] A[1] D[6] VSSRTC BATOK nBATCHG VSSIO D[11] VDDIO F
G PB[1] VDDIO TDO PB[4] PB[6] VSSRTC VSSRTC DD[0] D[3] VSSRTC A[7] A[8] A[9] VSSIO D[12] D[13] G
H PA[7] PA[5] VSSIO PA[4] PA[6] PB[0] PB[2] VSSRTC VSSRTC A[10] A[11] A[12] A[13]/
DRA[14] VSSIO D[14] D[15] H
J PA[3] PA[1] VSSIO PA[2] PA[0] TXD[1] CTS VSSRTC VSSRTC A[17]/
DRA[10]
A[16]/
DRA[11]
A[15]/
DRA[12]
A[14]/
DRA[13] nTRST D[16] D[17] J
K LEDDRV PHDIN VSSIO DCD nTEST[1] EINT[3] VSSRTC ADCIN COL[4] TCLK D[20] D[19] D[18] VSSIO VDDIO VDDIO K
L RXD[1] DSR VDDIO nEINT[1] PE[2]/
CLKSEL VSSRTC PD[0]/
LEDFLSH VSSRTC COL[6] D[31] VSSRTC A[22]/
DRA[5]
A[21]/
DRA[6] VSSIO A[18]/
DRA[9]
A[19]/
DRA[8] L
M nTEST[0] nEINT[2] VDDIO PE[0]/
BOOTSEL[0] TMS VDDIO SSITXFR DRIVE[1] FB[0] COL[0] D[27] VSSIO A[23]/
DRA[4] VDDIO A[20]/
DRA[7] D[21] M
N nEXTFIQ PE[1]/
BOOTSEL[1] VSSIO VDDIO PD[5] PD[2] SSIRXDA ADCCLK SMPCLK COL[2] D[29] D[26] HALFWORD VSSIO D[22] D[23] N
P VSSRTC RTCOUT VSSIO VSSIO VDDIO VSSIO VSSIO VDDIO VSSIO VDDIO VSSIO VSSIO VDDIO VSSIO D[24] VDDIO P
R RTCIN VDDIO PD[4] PD[1] SSITXDA nADCCS VDDIO ADCOUT COL[7] COL[3] COL[1] D[30] A[27]/
DRA[0]
A[25]/
DRA[2] VDDIO A[24]\
DRA[3] R
T VDDRTC PD[7]/
SDQM[1]
PD[6]/
SDQM[0] PD[3] SSICLK SSIRXFR VDDCORE DRIVE[0] FB[1] COL[5] VDDIO BUZ D[28] A[26]/
DRA[1] D[25] VSSIO T
DS506PP1 Copyright 2001 Cirrus Logic (All Rights Reserved) 39
EP7311
High-Performance, Low-Power System on Chip
256-Ball PBGA Ball Listing
The list is ordered by ball location.
Table V. 256-Ball PBGA Ball Listing
Ball Location Name Type Description
A1 VDDIO Pad power Digital I/O power, 3.3V
A2 nCS[4] O Chip select out
A3 nCS[1] O Chip select out
A4 SDCLK O SDRAM clock out
A5 SDQM[3] O SDRAM byte lane mask
A6 DD[1] O LCD serial display data
A7 M O LCD AC bias drive
A8 VDDIO Pad power Digital I/O power, 3.3V
A9 D[0] I/O Data I/O
A10 D[2] I/O Data I/O
A11 A[3] O System byte address
A12 VDDIO Pad power Digital I/O power, 3.3V
A13 A[6] O System byte address
A14 MOSCOUT O Main oscillator out
A15 VDDOSC Oscillator
power Oscillator power in, 2.5V
A16 VSSIO Pad ground I/O ground
B1 nCS[5] O Chip select out
B2 VDDIO Pad power I/O ground
B3 nCS[3] O Chip select out
B4 nMOE/nSDCAS O ROM, expansion OP enable/SDRAM
CAS control signal
B5 VDDIO Pad power Digital I/O power, 3.3V
B6 nSDCS[1] O SDRAM chip select out
B7 DD[2] O LCD serial display data
B8 CL[1] O LCD line clock
B9 VDDCORE Core power Digital core power, 2.5V
B10 D[1] I/O Data I/O
B11 A[2] O System byte address
B12 A[4] O System byte address
B13 A[5] O System byte address
B14 WAKEUP I System wake up input
B15 VDDIO Pad power Digital I/O power, 3.3V
B16 nURESET I User reset input
C1 VDDIO Pad power Digital I/O power, 3.3V
C2 EXPCLK I Expansion clock input
C3 VSSIO Pad ground I/O ground
C4 VDDIO Pad power Digital I/O power, 3.3V
C5 VSSIO Pad ground I/O ground
C6 VSSIO Pad ground I/O ground
C7 VSSIO Pad ground I/O ground
C8 VDDIO Pad power Digital I/O power, 3.3V
C9 VSSIO Pad ground I/O ground
C10 VSSIO Pad ground I/O ground
C11 VSSIO Pad ground I/O ground
C12 VDDIO Pad power Digital I/O power, 3.3V
C13 VSSIO Pad ground I/O ground
C14 VSSIO Pad ground I/O ground
C15 nPOR I Power-on reset input
C16 nEXTPWR I External power supply sense input
D1 WRITE/nSDRAS O Transfer direction / SDRAM RAS signal
output
D2 EXPRDY I Expansion port ready input
D3 VSSIO Pad ground I/O ground
D4 VDDIO Pad power Digital I/O power, 3.3V
D5 nCS[2] O Chip select out
D6 nMWE/nSDWE O ROM, expansion write enable/ SDRAM
write enable control signal
D7 nSDCS[0] O SDRAM chip select out
D8 CL[2] O LCD pixel clock out
D9 VSSRTC Core ground Real time clock ground
D10 D[4] I/O Data I/O
D11 nPWRFL I Power fail sense input
D12 MOSCIN I Main oscillator input
D13 VDDIO Pad power Digital I/O power, 3.3V
D14 VSSIO Pad ground I/O ground
D15 D[7] I/O Data I/O
D16 D[8] I/O Data I/O
E1 RXD[2] I UART 2 receive data input
E2 PB[7] I GPIO port B
E3 TDI I JTAG data input
E4 WORD O Word access select output
E5 VSSIO Pad ground I/O ground
E6 nCS[0] O Chip select out
E7 SDQM[2] O SDRAM byte lane mask
E8 FRM O LCD frame synchronization pulse
E9 A[0] O System byte address
E10 D[5] I/O Data I/O
E11 VSSOSC Oscillator
ground PLL ground
E12 VSSIO Pad ground I/O ground
E13 nMEDCHG/nBROM I Media change interrupt input / internal
ROM boot enable
E14 VDDIO Pad power Digital I/O power, 3.3V
E15 D[9] I/O Data I/O
E16 D[10] I/O Data I/O
F1 PB[5] I GPIO port B
F2 PB[3] I GPIO port B
F3 VSSIO Pad ground I/O ground
F4 TXD[2] O UART 2 transmit data output
F5 RUN/CLKEN O Run output / clock enable output
F6 VSSIO Pad ground I/O ground
Table V. 256-Ball PBGA Ball Listing (Continued)
Ball Location Name Type Description
40 Copyright 2001 Cirrus Logic (All Rights Reserved) DS506PP1
EP7311
High-Performance, Low-Power System on Chip
F7 SDCKE O SDRAM clock enable output
F8 DD[3] O LCD serial display data
F9 A[1] O System byte address
F10 D[6] I/O Data I/O
F11 VSSRTC RTC ground Real time clock ground
F12 BATOK I Battery ok input
F13 nBATCHG I Battery changed sense input
F14 VSSIO Pad ground I/O ground
F15 D[11] I/O Data I/O
F16 VDDIO Pad power Digital I/O power, 3.3V
G1 PB[1] I GPIO port B
G2 VDDIO Pad power Digital I/O power, 3.3V
G3 TDO O JTAG data out
G4 PB[4] I GPIO port B
G5 PB[6] I GPIO port B
G6 VSSRTC Core ground Real time clock ground
G7 VSSRTC RTC ground Real time clock ground
G8 DD[0] O LCD serial display data
G9 D[3] I/O Data I/O
G10 VSSRTC RTC ground Real time clock ground
G11 A[7] O System byte address
G12 A[8] O System byte address
G13 A[9] O System byte address
G14 VSSIO Pad ground I/O ground
G15 D[12] I/O Data I/O
G16 D[13] I/O Data I/O
H1 PA[7] I GPIO port A
H2 PA[5] I GPIO port A
H3 VSSIO Pad ground I/O ground
H4 PA[4] I GPIO port A
H5 PA[6] I GPIO port A
H6 PB[0] I GPIO port B
H7 PB[2] I GPIO port B
H8 VSSRTC RTC ground Real time clock ground
H9 VSSRTC RTC ground Real time clock ground
H10 A[10] O System byte address
H11 A[11] O System byte address
H12 A[12] O System byte address
H13 A[13]/DRA[14] O System byte address / SDRAM address
H14 VSSIO Pad ground I/O ground
H15 D[14] I/O Data I/O
H16 D[15] I/O Data I/O
J1 PA[3] I GPIO port A
J2 PA[1] I GPIO port A
J3 VSSIO Pad ground I/O ground
J4 PA[2] I GPIO port A
J5 PA[0] I GPIO port A
J6 TXD[1] O UART 1 transmit data out
Table V. 256-Ball PBGA Ball Listing (Continued)
Ball Location Name Type Description
J7 CTS I UART 1 clear to send input
J8 VSSRTC RTC ground Real time clock ground
J9 VSSRTC RTC ground Real time clock ground
J10 A[17]/DRA[10] O System byte address / SDRAM address
J11 A[16]/DRA[11] O System byte address / SDRAM address
J12 A[15]/DRA[12] O System byte address / SDRAM address
J13 A[14]/DRA[13] O System byte address / SDRAM address
J14 nTRST I JTAG async reset input
J15 D[16] I/O Data I/O
J16 D[17] I/O Data I/O
K1 LEDDRV O IR LED drivet
K2 PHDIN I Photodiode input
K3 VSSIO Pad ground I/O ground
K4 DCD I UART 1 data carrier detect
K5 nTEST[1] I Test mode select input
K6 EINT[3] I External interrupt
K7 VSSRTC RTC ground Real time clock ground
K8 ADCIN I SSI1 ADC serial input
K9 COL[4] O Keyboard scanner column drive
K10 TCLK I JTAG clock
K11 D[20] I/O Data I/O
K12 D[19] I/O Data I/O
K13 D[18] I/O Data I/O
K14 VSSIO Pad ground I/O ground
K15 VDDIO Pad power Digital I/O power, 3.3V
K16 VDDIO Pad power Digital I/O power, 3.3V
L1 RXD[1] I UART 1 receive data input
L2 DSR I UART 1 data set ready input
L3 VDDIO Pad power Digital I/O power, 3.3V
L4 nEINT[1] I External interrupt input
L5 PE[2]/CLKSEL I GPIO port E / clock input mode select
L6 VSSRTC RTC ground Real time clock ground
L7 PD[0]/LEDFLSH I/O GPIO port D / LED blinker output
L8 VSSRTC Core ground Real time clock ground
L9 COL[6] O Keyboard scanner column drive
L10 D[31] I/O Data I/O
L11 VSSRTC RTC ground Real time clock ground
L12 A[22]/DRA[5] O System byte address / SDRAM address
L13 A[21]/DRA[6] O System byte address / SDRAM address
L14 VSSIO Pad ground I/O ground
L15 A[18]/DRA[9] O System byte address / SDRAM address
L16 A[19]/DRA[8] O System byte address / SDRAM address
M1 nTEST[0] I Test mode select input
M2 nEINT[2] I External interrupt input
M3 VDDIO Pad power Digital I/O power, 3.3V
M4 PE[0]/BOOTSEL[0] I GPIO port E / Boot mode select
M5 TMS I JTAG mode select
M6 VDDIO Pad power Digital I/O power, 3.3V
Table V. 256-Ball PBGA Ball Listing (Continued)
Ball Location Name Type Description
DS506PP1 Copyright 2001 Cirrus Logic (All Rights Reserved) 41
EP7311
High-Performance, Low-Power System on Chip
M7 SSITXFR I/O MCP/CODEC/SSI2 frame sync
M8 DRIVE[1] I/O PWM drive output
M9 FB[0] I PWM feedback input
M10 COL[0] O Keyboard scanner column drive
M11 D[27] I/O Data I/O
M12 VSSIO Pad ground I/O ground
M13 A[23]/DRA[4] O System byte address / SDRAM address
M14 VDDIO Pad power Digital I/O power, 3.3V
M15 A[20]/DRA[7] O System byte address / SDRAM address
M16 D[21] I/O Data I/O
N1 nEXTFIQ I External fast interrupt input
N2 PE[1]/BOOTSEL[1] I GPIO port E / boot mode select
N3 VSSIO Pad ground I/O ground
N4 VDDIO Pad power Digital I/O power, 3.3V
N5 PD[5] I/O GPIO port D
N6 PD[2] I/O GPIO port D
N7 SSIRXDA I/O MCP/CODEC/SSI2 serial data input
N8 ADCCLK O SSI1 ADC serial clock
N9 SMPCLK O SSI1 ADC sample clock
N10 COL[2] O Keyboard scanner column drive
N11 D[29] I/O Data I/O
N12 D[26] I/O Data I/O
N13 HALFWORD O Halfword access select output
N14 VSSIO Pad ground I/O ground
N15 D[22] I/O Data I/O
N16 D[23] I/O Data I/O
P1 VSSRTC RTC ground Real time clock ground
P2 RTCOUT O Real time clock oscillator output
P3 VSSIO Pad ground I/O ground
P4 VSSIO Pad ground I/O ground
P5 VDDIO Pad power Digital I/O power, 3.3V
P6 VSSIO Pad ground I/O ground
P7 VSSIO Pad ground I/O ground
P8 VDDIO Pad power Digital I/O power, 3.3V
P9 VSSIO Pad ground I/O ground
P10 VDDIO Pad power Digital I/O power, 3.3V
P11 VSSIO Pad ground I/O ground
P12 VSSIO Pad ground I/O ground
P13 VDDIO Pad power Digital I/O power
P14 VSSIO Pad ground I/O ground
P15 D[24] I/O Data I/O
P16 VDDIO Pad power Digital I/O power, 3.3V
R1 RTCIN I/O Real time clock oscillator input
R2 VDDIO Pad power Digital I/O power, 3.3V
R3 PD[4] I/O GPIO port D
R4 PD[1] I/O GPIO port D
R5 SSITXDA O MCP/CODEC/SSI2 serial data output
R6 nADCCS O SSI1 ADC chip select
Table V. 256-Ball PBGA Ball Listing (Continued)
Ball Location Name Type Description
R7 VDDIO Pad power Digital I/O power, 3.3V
R8 ADCOUT O SSI1 ADC serial data output
R9 COL[7] O Keyboard scanner column drive
R10 COL[3] O Keyboard scanner column drive
R11 COL[1] O Keyboard scanner column drive
R12 D[30] I/O Data I/O
R13 A[27]/DRA[0] O System byte address / SDRAM address
R14 A[25]/DRA[2] O System byte address / SDRAM address
R15 VDDIO Pad power Digital I/O power, 3.3V
R16 A[24]/DRA[3] O System byte address / SDRAM address
T1 VDDRTC RTC power Real time clock power, 2.5V
T2 PD[7]/SDQM[1] I/O GPIO port D / SDRAM byte lane mask
T3 PD[6]/SDQM[0] I/O GPIO port D / SDRAM byte lane mask
T4 PD[3] I/O GPIO port D
T5 SSICLK I/O MCP/CODEC/SSI2 serial clock
T6 SSIRXFR MCP/CODEC/SSI2 frame sync
T7 VDDCORE Core power Core power, 2.5V
T8 DRIVE[0] I/O PWM drive output
T9 FB[1] I PWM feedback input
T10 COL[5] O Keyboard scanner column drive
T11 VDDIO Pad power Digital I/O power, 3.3V
T12 BUZ O Buzzer drive output
T13 D[28] I/O Data I/O
T14 A[26]/DRA[1] O System byte address / SDRAM address
T15 D[25] I/O Data I/O
T16 VSSIO Pad ground I/O ground
Table V. 256-Ball PBGA Ball Listing (Continued)
Ball Location Name Type Description
42 Copyright 2001 Cirrus Logic (All Rights Reserved) DS506PP1
EP7311
High-Performance, Low-Power System on Chip
JTAG Boundary Scan Signal Ordering
Table W. JTAG Boundary Scan Signal Ordering
LQFP
Pin No.
TFBGA
Ball
PBGA
Ball Signal Type Position
1B3B1 nCS[5] O 1
4 A2 C2 EXPCLK I/O 3
5B1E4 WORD O 6
6 E3 D1 WRITE/nSDRAS O 8
7 C1 F5 RUN/CLKEN O 10
8 C2 D2 EXPRDY I 13
9E2F4 TXD2 O 14
10 D2 E1 RXD2 I 16
13 F3 E2 PB[7] I/O 17
14 D1 G5 PB[6] I/O 20
15 F2 F1 PB[5] I/O 23
16 G3 G4 PB[4] I/O 26
17 E1 F2 PB[3] I/O 29
18 F1 H7 PB[2] I/O 32
19 G2 G1 PB[1]/PRDY2 I/O 35
20 G1 H6 PB[0]/PRDY1 I/O 38
23 H3 H1 PA[7] I/O 41
24 H1 H5 PA[6] I/O 44
25 J3 H2 PA[5] I/O 47
26 J2 H4 PA[4] I/O 50
27 J1 J1 PA[3] I/O 53
28 L3 J4 PA[2] I/O 56
29 K2 J2 PA[1] I/O 59
30 K1 J5 PA[0] I/O 62
31 M3 K1 LEDDRV O 65
32 L2 J6 TXD1 O 67
34 L1 K2 PHDIN I 69
35 N3 J7 CTS I 70
36 M2 L1 RXD1 I 71
37 M1 K4 DCD I 72
38 P3 L2 DSR I 73
39 N1 K5 nTEST1 I 74
40 N2 M1 nTEST0 I 75
41 R3 K6 EINT3 I 76
42 P1 M2 nEINT2 I 77
43 P2 L4 nEINT1 I 78
DS506PP1 Copyright 2001 Cirrus Logic (All Rights Reserved) 43
EP7311
High-Performance, Low-Power System on Chip
44 T3 N1 nEXTFIQ I 79
45 R1 L5 PE[2]/CLKSEL I/O 80
46 R2 N2 PE[1]/BOOTSEL1 I/O 83
47 T1 M4 PE[0]/BOOTSEL0 I/O 86
53 T2 T2 PD[7]/SDQM[1] I/O 89
54 V4 T3 PD[6/SDQM[0]] I/O 92
55 W4 N5 PD[5] I/O 95
56 Y4 R3 PD[4] I/O 98
59 V5 T4 PD[3] I/O 101
60 W5 N6 PD[2] I/O 104
61 Y5 R4 PD[1] I/O 107
62 V6 L7 PD[0]/LEDFLSH O 110
68 W6 T6 SSIRXFR I/O 122
69 Y6 K8 ADCIN I 125
70 W8 R6 nADCCS O 126
75 Y8 M8 DRIVE1 I/O 128
76 V9 T8 DRIVE0 I/O 131
77 W10 N8 ADCCLK O 134
78 Y10 R8 ADCOUT O 136
79 V11 N9 SMPCLK O 138
80 W11 T9 FB1 I 140
82 Y11 M9 FB0 I 141
83 Y12 R9 COL7 O 142
84 W12 L9 COL6 O 144
85 V12 T10 COL5 O 146
86 Y13 K9 COL4 O 148
87 W13 R10 COL3 O 150
88 V13 N10 COL2 O 152
91 Y14 R11 COL1 O 154
92 W14 M10 COL0 O 156
93 A1 T12 BUZ O 158
94 V14 L10 D[31] I/O 160
95 Y15 R12 D[30] I/O 163
96 W15 N11 D[29] I/O 166
97 V15 T13 D[28] I/O 169
99 Y16 R13 A[27]/DRA[0] Out 172
100 W16 M11 D[27] I/O 174
101 V16 T14 A[26]/DRA[1] O 177
Table W. JTAG Boundary Scan Signal Ordering (Continued)
LQFP
Pin No.
TFBGA
Ball
PBGA
Ball Signal Type Position
44 Copyright 2001 Cirrus Logic (All Rights Reserved) DS506PP1
EP7311
High-Performance, Low-Power System on Chip
102 Y17 N12 D[26] I/O 179
103 W17 R14 A[25]/DRA[2] O 182
104 Y18 T15 D[25] I/O 184
105 V17 N13 HALFWORD O 187
106 W18 R16 A[24]/DRA[3] O 189
109 Y19 P15 D[24] I/O 191
110 W20 M13 A[23]/DRA[4] O 194
111 U18 N16 D[23] I/O 196
112 V20 L12 A[22]/DRA[5] O 199
113 U19 N15 D[22] I/O 201
114 U20 L13 A[21]/DRA[6] O 204
115 T19 M16 D[21] I/O 206
117 T20 M15 A[20]/DRA[7] O 209
118 R19 K11 D[20] I/O 211
119 R20 L16 A[19]/DRA[8] O 214
120 T18 K12 D[19] I/O 216
121 P19 L15 A[18]/DRA[9] O 219
122 P20 K13 D[18] I/O 221
126 R18 J10 A[17]/DRA[10] O 224
127 N19 J16 D[17] I/O 226
128 N20 J11 A[16]/DRA[11] O 229
129 P18 J15 D[16] I/O 231
130 M19 J12 A[15]/DRA[12] O 234
131 N18 H16 D[15] I/O 236
132 L20 J13 A[14]/DRA[13] O 239
133 L19 H15 D[14] I/O 241
134 M18 H13 A[13]/DRA[14] O 244
135 K20 G16 D[13] I/O 246
136 K19 H12 A[12] O 249
137 K18 G15 D[12] I/O 251
138 J20 H11 A[11] O 254
141 J19 F15 D[11] I/O 256
142 H20 H10 A[10] O 259
143 H19 E16 D[10] I/O 261
144 J18 G13 A[9] O 264
145 K3 E15 D[9] I/O 266
146 Y3 G12 A[8] O 269
147 G20 D16 D[8] I/O 271
Table W. JTAG Boundary Scan Signal Ordering (Continued)
LQFP
Pin No.
TFBGA
Ball
PBGA
Ball Signal Type Position
DS506PP1 Copyright 2001 Cirrus Logic (All Rights Reserved) 45
EP7311
High-Performance, Low-Power System on Chip
148 H18 G11 A[7] O 274
150 F20 D15 D[7] I/O 276
151 G19 F13 nBATCHG I 279
152 E20 C16 nEXTPWR I 280
153 F19 F12 BATOK I 281
154 G18 C15 nPOR I 282
155 D20 E13 nMEDCHG/nBROM I 283
156 F18 B16 nURESET I 284
161 D19 B14 WAKEUP I 285
162 E19 D11 nPWRFL I 286
163 C19 A13 A[6] O 287
164 C20 F10 D[6] I/O 289
165 E18 B13 A[5] O 292
166 B20 E10 D[5] I/O 294
169 B16 B12 A[4] O 297
170 A16 D10 D[4] I/O 299
171 C15 A11 A[3] O 302
172 B15 G9 D[3] I/O 304
173 A15 B11 A[2] O 307
175 C14 A10 D[2] I/O 309
176 B14 F9 A[1] O 312
177 A14 B10 D[1] I/O 314
178 C13 E9 A[0] O 317
179 B13 A9 D[0] I/O 319
184 A13 D8 CL2 O 322
185 C12 B8 CL1 O 324
186 B12 E8 FRM O 326
187 A12 A7 M O 328
188 C11 F8 DD[3] I/O 330
189 B11 B7 DD[2] I/O 333
191 B10 A6 DD[1] I/O 336
192 A10 G8 DD[0] I/O 339
193 A9 B6 nSDCS[1] O 342
194 B9 D7 nSDCS[0] O 344
195 C9 A5 SDQM[3] I/O 346
196 A8 E7 SDQM[2] I/O 349
199 B8 F7 SDCKE I/O 352
200 C8 A4 SDCLK I/O 355
Table W. JTAG Boundary Scan Signal Ordering (Continued)
LQFP
Pin No.
TFBGA
Ball
PBGA
Ball Signal Type Position
46 Copyright 2001 Cirrus Logic (All Rights Reserved) DS506PP1
EP7311
High-Performance, Low-Power System on Chip
1) See EP7311 Users Manual for pin naming / functionality.
2) For each pad, the JTAG connection ordering is input,
output, then enable as applicable.
201 A7 D6 nMWE/nSDWE O 358
202 B7 B4 nMOE/nSDCAS O 360
204 C7 E6 nCS[0] O 362
205 A6 A3 nCS[1] O 364
206 B6 D5 nCS[2] O 366
207 C6 B3 nCS[3] O 368
208 A5 A2 nCS[4] O 370
Table W. JTAG Boundary Scan Signal Ordering (Continued)
LQFP
Pin No.
TFBGA
Ball
PBGA
Ball Signal Type Position
DS506PP1 Copyright 2001 Cirrus Logic (All Rights Reserved) 47
EP7311
High-Performance, Low-Power System on Chip
CONVENTIONS
This section presents acronyms, abbreviations, units of
measurement, and conventions used in this data sheet.
Acronyms and Abbreviations
Table X lists abbreviations and acronyms used in this
data sheet.
Units of Measurement
Table X. Acronyms and Abbreviations
Acronym/
Abbreviation Definition
A/D analog-to-digital
ADC analog-to-digital converter
CODEC coder / decoder
D/A digital-to-analog
DMA direct-memory access
EPB embedded peripheral bus
FCS frame check sequence
FIFO first in / first out
FIQ fast interrupt request
GPIO general purpose I/O
ICT in circuit test
IR infrared
IRQ standard interrupt request
IrDA Infrared Data Association
JTAG Joint Test Action Group
LCD liquid crystal display
LED light-emitting diode
LQFP low profile quad flat pack
LSB least significant bit
MIPS millions of instructions per second
MMU memory management unit
MSB most significant bit
PBGA plastic ball grid array
PCB printed circuit board
PDA personal digital assistant
PLL phase locked loop
p/u pull-up resistor
RISC reduced instruction set computer
RTC Real-Time Clock
SIR slow (9600115.2 kbps) infrared
SRAM static random access memory
SSI synchronous serial interface
TAP test access port
TLB translation lookaside buffer
UART universal asynchronous receiver
Table Y. Unit of Measurement
Symbol Unit of Measure
°Cdegree Celsius
fs sample frequency
Hz hertz (cycle per second)
kbps kilobits per second
KB kilobyte (1,024 bytes)
kHz kilohertz
kkilohm
Mbps megabits (1,048,576 bits) per second
MB megabyte (1,048,576 bytes)
MBps megabytes per second
MHz megahertz (1,000 kilohertz)
µA microampere
µFmicrofarad
µWmicrowatt
µs microsecond (1,000 nanoseconds)
mA milliampere
mW milliwatt
ms millisecond (1,000 microseconds)
ns nanosecond
Vvolt
Wwatt
Table X. Acronyms and Abbreviations (Continued)
Acronym/
Abbreviation Definition
48 Copyright 2001 Cirrus Logic (All Rights Reserved) DS506PP1
EP7311
High-Performance, Low-Power System on Chip
General Conventions
Hexadecimal numbers are presented with all letters in
uppercase and a lowercase h appended or with a 0x at
the beginning. For example, 0x14 and 03CAh are
hexadecimal numbers. Binary numbers are enclosed in
single quotation marks when in text (for example, 11
designates a binary number). Numbers not indicated by
an h, 0x or quotation marks are decimal.
Registers are referred to by acronym, with bits listed in
brackets separated by a colon (:) (for example,
CODR[7:0]), and are described in the EP7311 Users
Manual. The use of TBD indicates values that are to
be determined, n/a designates not available, and
n/c indicates a pin that is a no connect.
Pin Description Conventions
Abbreviations used for signal directions are listed in
Table Z.
Table Z. Pin Description Conventions
Abbreviation Direction
I Input
OOutput
I/O Input or Output
DS506PP1 Copyright 2001 Cirrus Logic (All Rights Reserved) 49
EP7311
High-Performance, Low-Power System on Chip
ORDERING INFORMATION
The order number for the device is:
Note: Contact Cirrus Logic for up-to-date information on revisions. Go to the Cirrus Logic Internet site at
http://cirrus.com/corporate/contacts to find contact information for your local sales representative.
EP7312 CV C
Product Line:
Embedded Processor
Part Number
Temperature Range:
Package Type:
V = Low Profile Quad Flat Pack
B = Plastic Ball Grid Array (17 mm x 17 mm)
Revision
R = Reduced Ball Grid Array (13 mm x 13 mm)
C = Commercial
E = Extended Operating Version
I = Industrial Operating Version