935044180112 - NXP SEMICONDUCTORS

74HCT9046A

PLL with band gap controlled VCO

Rev. 9 — 20 March 2020 Product data sheet

1. General description

The 74HCT9046A. This device features reduced input threshold levels to allow interfacing to TTL

logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to

interface inputs to voltages in excess of VCC.

2. Features and benefits

•Operation power supply voltage range from 4.5 V to 5.5 V

•Low power consumption

•Complies with JEDEC standard no. 7A

•Inhibit control for ON/OFF keying and for low standby power consumption

•Center frequency up to 17 MHz (typical) at VCC = 5.5 V

•Choice of two phase comparators:

•PC1: EXCLUSIVE-OR

•PC2: Edge-triggered JK flip-flop

•No dead zone of PC2

•Charge pump output on PC2, whose current is set by an external resistor Rbias

•Center frequency tolerance ±10 %

•Excellent Voltage Controlled Oscillator (VCO) linearity

•Low frequency drift with supply voltage and temperature variations

•On-chip band gap reference

•Glitch free operation of VCO, even at very low frequencies

•Zero voltage offset due to operational amplifier buffering

•ESD protection:

•HBM JESD22-A114F exceeds 2000 V

•MM JESD22-A115-A exceeds 200 V

3. Applications

•FM modulation and demodulation where a small center frequency tolerance is essential

•Frequency synthesis and multiplication where a low jitter is required (e.g. video

picture-in-picture)

•Frequency discrimination

•Tone decoding

•Data synchronization and conditioning

•Voltage-to-frequency conversion

•Motor-speed control

4. Ordering information

Table 1. Ordering information

PackageType number

Temperature range Name Description Version

74HCT9046AD -40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Nexperia 74HCT9046A

PLL with band gap controlled VCO

5. Functional diagram

PHASE

COMPARATOR

PHASE

COMPARATOR

SIG_IN

COMP_INC1A C1B

fout

fin VCC

DEM_OUT

INH VCO_IN

3 14 16476

5 10 9

GND

9046A

VCO

R1 R4

PC2_OUT

mbd040

PC1_OUT/

PCP_OUT

VCO_OUT

Rbias

Fig. 1. Block diagram

mbd038

PC1_OUT/

PCP_OUT

VCO_OUT

C1A

C1B

VCO_IN DEM_OUT

SIG_IN

INH

VCO

15 PC2_OUT

COMP_IN

Fig. 2. Logic symbol

mbd039

SIG_IN

INH

COMP_IN

PLL

9046A

PC1_OUT/

PCP_OUT

VCO_OUT

C1A

C1B

VCO_IN

DEM_OUT

PC2_OUT

Fig. 3. IEC logic symbol

Product data sheet Rev. 9 — 20 March 2020 2 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

mbd102

PCP

D Q

logic

D Q

logic

down

CHARGE

PUMP

Vref2

Vref1

PC1_OUT/

PCP_OUT

PC2_OUT

Rbias

COMP_IN SIG_IN

3 14

PC1

BAND

GAP

INH

VCO

DEM_OUT

VCO_OUTC1BC1A

76 4

fout fin

VCO_IN

R3' = Rbias /17

R3'

(1)

Fig. 4. Logic diagram

Product data sheet Rev. 9 — 20 March 2020 3 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

6. Pinning information

6.1. Pinning

74HCT9046A

GND VCC

PC1_OUT/PCP_OUT RB

COMP_IN SIG_IN

VCO_OUT PC2_OUT

INH R2

C1A R1

C1B DEM_OUT

GND VCO_IN

001aae500

Fig. 5. Pin configuration

6.2. Pin description

Table 2. Pin description

Symbol Pin Description

GND 1 ground (0 V) of phase comparators

PC1_OUT/PCP_OUT 2 phase comparator 1 output or phase comparator pulse output

COMP_IN 3 comparator input

VCO_OUT 4 VCO output

INH 5 inhibit input

C1A 6 capacitor C1 connection A

C1B 7 capacitor C1 connection B

GND 8 ground (0 V) VCO

VCO_IN 9 VCO input

DEM_OUT 10 demodulator output

R1 11 resistor R1 connection

R2 12 resistor R2 connection

PC2_OUT 13 phase comparator 2 output; current source adjustable with Rbias

SIG_IN 14 signal input

RB 15 bias resistor (Rbias) connection

VCC 16 supply voltage

Product data sheet Rev. 9 — 20 March 2020 4 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

7. Functional description

The 74HCT9046A is a phase-locked-loop circuit that comprises a linear VCO and two different

phase comparators (PC1 and PC2) with a common signal input amplifier and a common

comparator input, see Fig. 1. The signal input can be directly coupled to large voltage signals

(CMOS level), or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias

input circuit keeps small voltage signals within the linear region of the input amplifiers. With a

passive low-pass filter, the 74HCT9046A forms a second-order loop PLL.

The principle of this phase-locked-loop is based on the familiar 74HCT4046A. However extra

features are built-in, allowing very high-performance phase-locked-loop applications. This is done,

at the expense of PC3, which is skipped in this 74HCT9046A. The PC2 is equipped with a current

source output stage here. Further a band gap is applied for all internal references, allowing a small

center frequency tolerance. The details are summed up in Section 7.1. If one is familiar with the

74HCT4046A already, it will do to read this section only.

7.1. Differences with respect to the familiar 74HCT4046A

•A center frequency tolerance of maximum ±10 %.

•The on board band gap sets the internal references resulting in a minimal frequency shift at

supply voltage variations and temperature variations.

•The value of the frequency offset is determined by an internal reference voltage of 2.5 V instead

of VCC - 0.7 V; In this way the offset frequency will not shift over the supply voltage range.

•A current switch charge pump output on pin PC2_OUT allows a virtually ideal performance of

PC2; The gain of PC2 is independent of the voltage across the low-pass filter; Further a passive

low-pass filter in the loop achieves an active performance. The influence of the parasitic

capacitance of the PC2 output plays no role here, resulting in a true correspondence of the

output correction pulse and the phase difference even up to phase differences as small as a

few nanoseconds.

•Because of its linear performance without dead zone, higher impedance values for the filter,

hence lower C-values, can be chosen; correct operation will not be influenced by parasitic

capacitances as in case of the voltage source output using the 74HCT4046A.

•No PC3 on pin RB but instead a resistor connected to GND, which sets the load/unload

currents of the charge pump (PC2).

•Extra GND pin 1 to allow an excellent FM demodulator performance even at 10 MHz and

higher.

•Combined function of pin PC1_OUT/PCP_OUT. If pin RB is connected to VCC (no bias resistor

Rbias) pin PC1_OUT/PCP_OUT has its familiar function viz. output of PC1. If at pin RB a

resistor (Rbias) is connected to GND it is assumed that PC2 has been chosen as phase

comparator. Connection of Rbias is sensed by internal circuitry and this changes the function of

pin PC1_OUT/PCP_OUT into a lock detect output (PCP_OUT) with the same characteristics as

PCP_OUT of pin 1 of the 74HCT4046A.

•The inhibit function differs. For the 74HCT4046A a HIGH-level at the inhibit input (pin INH)

disables the VCO and demodulator, while a LOW-level turns both on. For the 74HCT9046A

a HIGH-level on the inhibit input disables the whole circuit to minimize standby power

consumption.

7.2. VCO

The VCO requires one external capacitor C1 (between pins C1A and C1B) and one external

resistor R1 (between pins R1 and GND) or two external resistors R1 and R2 (between pins R1 and

GND, and R2 and GND). Resistor R1 and capacitor C1 determine the frequency range of the VCO.

Resistor R2 enables the VCO to have a frequency offset if required (see Fig. 4).

The high input impedance of the VCO simplifies the design of the low-pass filters by giving the

designer a wide choice of resistor/capacitor ranges. In order not to load the low-pass filter, a

demodulator output of the VCO input voltage is provided at pin DEM_OUT. The DEM_OUT voltage

equals that of the VCO input. If DEM_OUT is used, a series resistor (Rs) should be connected

from pin DEM_OUT to GND; if unused, DEM_OUT should be left open. The VCO output (pin

VCO_OUT) can be connected directly to the comparator input (pin COMP_IN), or connected via a

Product data sheet Rev. 9 — 20 March 2020 5 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

frequency divider. The output signal has a duty cycle of 50 % (maximum expected deviation 1 %), if

the VCO input is held at a constant DC level. A LOW-level at the inhibit input (pin INH) enables the

VCO and demodulator, while a HIGH-level turns both off to minimize standby power consumption.

7.3. Phase comparators

The signal input (pin SIG_IN) can be directly coupled to the self-biasing amplifier at pin SIG_IN,

provided that the signal swing is between the standard HC family input logic levels. Capacitive

coupling is required for signals with smaller swings.

7.3.1. Phase Comparator 1 (PC1)

This circuit is an EXCLUSIVE-OR network. The signal and comparator input frequencies (fi) must

have a 50 % duty cycle to obtain the maximum locking range. The transfer characteristic of PC1,

assuming ripple (fr = 2fi) is suppressed, is:

where:

•VDEM_OUT is the demodulator output at pin DEM_OUT

•VDEM_OUT = VPC1_OUT (via low-pass)

The phase comparator gain is:

The average output voltage from PC1, fed to the VCO input via the low-pass filter and seen at

the demodulator output at pin DEM_OUT (VDEM_OUT), is the resultant of the phase differences

of signals (SIG_IN) and the comparator input (COMP_IN) as shown in Fig. 6. The average of

VDEM_OUT is equal to 0.5VCC when there is no signal or noise at SIG_IN and with this input the

VCO oscillates at the center frequency (f0). Typical waveforms for the PC1 loop locked at f0 are

shown in Fig. 7. This figure also shows the actual waveforms across the VCO capacitor at pins

C1A and C1B (VC1A and VC1B) to show the relation between these ramps and the VCO_OUT

voltage.

The frequency capture range (2f0) is defined as the frequency range of input signals on which the

PLL will lock if it was initially out-of-lock. The frequency lock range (2fL) is defined as the frequency

range of the input signals on which the loop will stay locked if it was initially in lock. The capture

range is smaller or equal to the lock range.

With PC1, the capture range depends on the low-pass filter characteristics and can be made as

large as the lock range. This configuration remains locked even with very noisy input signals.

Typical behavior of this type of phase comparator is that it may lock to input frequencies close to

the harmonics of the VCO center frequency.

Product data sheet Rev. 9 — 20 March 2020 6 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

mbd101

180o

0o90 o

0.5VCC

VCC

VDEM_OUT(AV)

ΦPC_IN

Fig. 6. Phase comparator 1; average output voltage as a function of input phase

difference

mbd100

PC1_OUT

VCO_IN

VCC

GND

VCO_OUT

COMP_IN

SIGN_IN

C1A

C1B

VC1A

VC1B

Fig. 7. Typical waveforms for PLL using phase comparator 1; loop-locked at f0

7.3.2. Phase Comparator 2 (PC2)

This is a positive edge-triggered phase and frequency detector. When the PLL is using this

comparator, the loop is controlled by positive signal transitions and the duty cycles of SIG_IN and

COMP_IN are not important. PC2 comprises two D-type flip-flops, control gating and a 3-state

output stage with sink and source transistors acting as current sources, henceforth called charge

pump output of PC2. The circuit functions as an up-down counter (see Fig. 4) where SIG_IN

causes an up-count and COMP_IN a down count. The current switch charge pump output allows

a virtually ideal performance of PC2, due to appliance of some pulse overlap of the up and down

signals, see Fig. 8a. The pump current Icp is independent from the supply voltage and is set by the

internal band gap reference of 2.5 V.

Where Rbias is the external bias resistor between pin RB and ground.

The current and voltage transfer function of PC2 are shown in Fig. 9.

The phase comparator gain is:

Product data sheet Rev. 9 — 20 March 2020 7 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

mbd046

PC2_OUT

VCC

Icp

down

Δ Φ = ΦPC_IN

pulse overlap of

approximately 15 ns

mbd099

R3'

Icp

down C2

VCC

PC2_OUT

VC2_OUT

a. At every ΔΦ, even at zero ΔΦ both switches are

closed simultaneously for a short period (typically

15 ns).

b. Comparable voltage-controlled switch

Fig. 8. The current switch charge pump output of PC2

001aak442

0ΦPC_IN

+Icp

- Icp

- 2π+2π

001aak443

0.5VCC

VCC

VDEM_OUT(AV)

Icp × R

ΦPC_IN

- 2π+2π

a. Current transfer b. Voltage transfer. This transfer can be observed

at PC2_OUT by connecting a resistor (R = 10 kΩ)

between PC2_OUT and 0.5VCC.

Fig. 9. Phase comparator 2 current and voltage transfer characteristics

When the frequencies of SIG_IN and COMP_IN are equal but the phase of SIG_IN leads that of

COMP_IN, the up output driver at PC2_OUT is held ‘ON’ for a time corresponding to the phase

difference (ΦPC_IN). When the phase of SIG_IN lags that of COMP_IN, the down or sink driver is

held ‘ON’.

When the frequency of SIG_IN is higher than that of COMP_IN, the source output driver is held

‘ON’ for most of the input signal cycle time and for the remainder of the cycle time both drivers

are ‘OFF’ (3-state). If the SIG_IN frequency is lower than the COMP_IN frequency, then it is the

sink driver that is held ‘ON’ for most of the cycle. Subsequently the voltage at the capacitor (C2) of

the low-pass filter connected to PC2_OUT varies until the signal and comparator inputs are equal

in both phase and frequency. At this stable point the voltage on C2 remains constant as the PC2

output is in 3-state and the VCO input at pin 9 is a high-impedance. Also in this condition the signal

at the phase comparator pulse output (PCP_OUT) has a minimum output pulse width equal to the

overlap time, so can be used for indicating a locked condition.

Product data sheet Rev. 9 — 20 March 2020 8 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

Thus for PC2 no phase difference exists between SIG_IN and COMP_IN over the full frequency

range of the VCO. Moreover, the power dissipation due to the low-pass filter is reduced because

both output drivers are OFF for most of the signal input cycle.

It should be noted that the PLL lock range for this type of phase comparator is equal to the capture

range and is independent of the low-pass filter. With no signal present at SIG_IN the VCO adjust,

via PC2, to its lowest frequency.

By using current sources as charge pump output on PC2, the dead zone or backlash time could

be reduced to zero. Also, the pulse widening due to the parasitic output capacitance plays no

role here. This enables a linear transfer function, even in the vicinity of the zero crossing. The

differences between a voltage switch charge pump and a current switch charge pump are shown in

Fig. 11.

mbd047

SIG_IN

COMP_IN

VCO_OUT

high-impedance OFF-state,

(zero current)

15 ns typical

DOWN

CURRENT AT

PC2_OUT

PC2_OUT/VCO_IN

PCP_OUT

PC_IN

The pulse overlap of the up and down signals (typically 15 ns).

Fig. 10. Timing diagram for PC2

Product data sheet Rev. 9 — 20 March 2020 9 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

001aak444

- 25

2.50

2.75

2.25

VCO_IN

0 25

phase error (ns)

(1)

(2)

001aak445

VCO_IN

- 25

2.50

2.75

2.25

0 25

phase error (ns)

(1) Due to parasitic capacitance on PC2_OUT.

(2) Backlash time (dead zone).

a. Response with traditional voltage-switch

charge-pump PC2_OUT (74HCT4046A).

b. Response with current switch charge-pump

PC2_OUT as applied in the 74HCT9046A.

Fig. 11. The response of a locked-loop in the vicinity of the zero crossing of the phase error

The design of the low-pass filter is somewhat different when using current sources. The external

resistor R3 is no longer present when using PC2 as phase comparator. The current source is set

by Rbias. A simple capacitor behaves as an ideal integrator now, because the capacitor is charged

by a constant current. The transfer function of the voltage switch charge pump may be used.

In fact it is even more valid, because the transfer function is no longer restricted for small changes

only. Further the current is independent from both the supply voltage and the voltage across the

filter. For one that is familiar with the low-pass filter design of the 74HCT4046A a relation may show

how Rbias relates with a fictive series resistance, called R3'.

This relation can be derived by assuming first that a voltage controlled switch PC2 of the

74HCT4046A is connected to the filter capacitance C2 via this fictive R3' (see Fig. 8b). Then during

the PC2 output pulse the charge current equals:

With the initial voltage VC2(0) at: 0.5VCC = 2.5 V,

As shown before the charge current of the current switch of the 74HCT9046A is:

Hence:

Using this equivalent resistance R3' for the filter design the voltage can now be expressed as a

transfer function of PC2; assuming ripple (fr = fi) is suppressed, as:

Again this illustrates the supply voltage independent behavior of PC2.

Product data sheet Rev. 9 — 20 March 2020 10 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

7.4. Loop filter component selection

Examples of PC2 combined with a passive filter are shown in Fig. 14 and Fig. 15.

Fig. 14 shows that PC2 with only a C2 filter behaves as a high-gain filter. For stability the damped

version of Fig. 15 with series resistance R4 is preferred.

Practical design values for Rbias are between 25 kΩ and 250 kΩ with R3' = 1.5 kΩ to 15 kΩ for

the filter design. Higher values for R3' require lower values for the filter capacitance which is very

advantageous at low values of the loop natural frequency ωn.

001aak449

OUTPUTINPUT C2

Icp

Rbias

001aak450

F(jω)

1/Aτ1

001aak451

- 1/Aτ1

a. Simple loop filter for PC2

without damping

b. Amplitude characteristic

Fig. 12.

c. Pole zero diagram

Fig. 13.

A = DC gain limit, due to leakage

Fig. 14. Simple loop filter for PC2 without damping

001aak446

OUTPUTINPUT

Icp

Rbias

001aak447

F(jω)

1 / ω

1/Aτ1Aτ2

001aak448

- 1/τ2

1/Aτ1

a. Simple loop filter for PC2

with damping

b. Amplitude characteristic c. Pole zero diagram

A = DC gain limit, due to leakage

Fig. 15. Simple loop filter for PC2 with damping

Product data sheet Rev. 9 — 20 March 2020 11 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

8. Limiting values

Table 3. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage -0.5 +7 V

IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V - ±20 mA

IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V - ±20 mA

IOoutput current -0.5 V < VO < VCC + 0.5 V - ±25 mA

ICC supply current - +50 mA

IGND ground current -50 - mA

Tstg storage temperature -65 +150 °C

Ptot total power dissipation Tamb = -40 °C to +125 °C [1] - 500 mW

[1] For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C.

9. Recommended operating conditions

Table 4. Operating conditions

Symbol Parameter Conditions Min Typ Max Unit

VCC supply voltage 4.5 5.0 5.5 V

VIinput voltage 0 - VCC V

VOoutput voltage 0 - VCC V

Tamb ambient temperature -40 +125 °C

Δt/ΔV input transition rise and fall rate pin INH; VCC = 4.5 V - 1.67 139 ns/V

10. Static characteristics

Table 5. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ Max Unit

Tamb = 25 °C

Phase comparator section

VIH HIGH-level input voltage pins SIG_IN and COMP_IN;

VCC = 4.5 V; DC coupled

3.15 2.4 - V

VIL LOW-level input voltage pins SIG_IN and COMP_IN;

VCC = 4.5 V; DC coupled

- 2.1 1.35 V

pins PCP_OUT and PCn_OUT;

VCC = 4.5 V; VI = VIH or VIL

IO = -20 μA 4.4 4.5 - V

VOH HIGH-level output voltage

IO = -4.0 mA 3.98 4.32 - V

pins PCP_OUT and PCn_OUT;

VCC = 4.5 V; VI = VIH or VIL

IO = 20 μA - 0 0.1 V

VOL LOW-level output voltage

IO = 4.0 mA - 0.15 0.26 V

IIinput leakage current pins SIG_IN and COMP_IN;

VCC = 5.5 V; VI = VCC or GND

- - ±30 μA

Product data sheet Rev. 9 — 20 March 2020 12 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

Symbol Parameter Conditions Min Typ Max Unit

IOZ OFF-state output current pin PC2_OUT;

VCC = 5.5 V; VI = VIH or VIL; VO = VCC or GND

- - ±0.5 μA

RIinput resistance SIG_IN and COMP_IN; VCC = 4.5 V;

VI at self-bias operating point; ΔVI = 0.5 V;

see Fig. 16, Fig. 17 and Fig. 18

- 250 - kΩ

Rbias bias resistance VCC = 4.5 V 25 - 250 kΩ

Icp charge pump current VCC = 4.5 V; Rbias = 40 kΩ ±0.53 ±1.06 ±2.12 mA

VCO section

VIH HIGH-level input voltage pin INH; VCC = 4.5 V to 5.5 V; DC coupled 2.0 1.6 - V

VIL LOW-level input voltage pin INH; VCC = 4.5 V to 5.5 V; DC coupled - 1.2 0.8 V

pin VCO_OUT; VCC = 4.5 V; VI = VIH or VIL

IO = -20 μA 4.4 4.5 - V

VOH HIGH-level output voltage

IO = -4.0 mA 3.98 4.32 - V

pin VCO_OUT; VCC = 4.5 V; VI = VIH or VIL

IO = 20 μA - 0 0.1 V

IO = 4.0 mA - 0.15 0.26 V

VOL LOW-level output voltage

pins C1A and C1B;

VCC = 4.5 V; VI = VIH or VIL; IO = 4.0 mA

- - 0.40 V

IIinput leakage current pins INH and VCO_IN;

VCC = 5.5 V; VI = VCC or GND

- - ±0.1 μA

R1 resistor 1 VCC = 4.5 V 3 - 300 kΩ

R2 resistor 2 VCC = 4.5 V 3 - 300 kΩ

C1 capacitor 1 VCC = 4.5 V 40 - no

limit

over the range specified for R1

VCC = 4.5 V 1.1 - 3.4 V

VCC = 5.0 V 1.1 - 3.9 V

VVCO_IN voltage on pin VCO_IN

VCC = 5.5 V 1.1 - 4.4 V

Demodulator section

Rsseries resistance VCC = 4.5 V; at Rs > 300 kΩ the leakage current

can influence VDEM_OUT

50 - 300 kΩ

Voffset offset voltage VCO_IN to VDEM_OUT;

VCC = 4.5 V; VI = VVCO_IN = 0.5VCC;

values taken over Rs range; see Fig. 19

- ±20 - mV

Rdyn dynamic resistance DEM_OUT; VCC = 4.5 V; VDEM_OUT = 0.5 VCC - 25 - Ω

General

ICC supply current disabled; VCC = 5.5 V; pin INH at VCC - - 8.0 μA

ΔICC additional supply current pin INH; VI = VCC - 2.1 V; VCC = 4.5 V;

other inputs at VCC or GND;

- 100 360 μA

CIinput capacitance - 3.5 - pF

Product data sheet Rev. 9 — 20 March 2020 13 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

Symbol Parameter Conditions Min Typ Max Unit

Tamb = -40 °C to +85 °C

Phase comparator section

VIH HIGH-level input voltage pins SIG_IN and COMP_IN;

VCC = 4.5 V; DC coupled

3.15 - - V

VIL LOW-level input voltage pins SIG_IN and COMP_IN;

VCC = 4.5 V; DC coupled

- - 1.35 V

pins PCP_OUT and PCn_OUT;

VCC = 4.5 V; VI = VIH or VIL

IO = -20 μA 4.4 - - V

VOH HIGH-level output voltage

IO = -4.0 mA 3.84 - - V

pins PCP_OUT and PCn_OUT;

VCC = 4.5 V; VI = VIH or VIL

IO = 20 μA - - 0.1 V

VOL LOW-level output voltage

IO = 4.0 mA - - 0.33 V

IIinput leakage current SIG_IN and COMP_IN;

VCC = 5.5 V; VI = VCC or GND

- - ±38 μA

IOZ OFF-state output current PC2_OUT;

VCC = 5.5 V; VI = VIH or VIL; VO = VCC or GND

- - ±5.0 μA

VCO section

VIH HIGH-level input voltage pin INH; VCC = 4.5 V to 5.5 V; DC coupled 2.0 - - V

VIL LOW-level input voltage pin INH; VCC = 4.5 V to 5.5 V; DC coupled - - 0.8 V

pin VCO_OUT; VCC = 4.5 V; VI = VIH or VIL

IO = -20 μA 4.4 - - V

VOH HIGH-level output voltage

IO = -4.0 mA 3.84 - - V

pin VCO_OUT; VCC = 4.5 V; VI = VIH or VIL

IO = 20 μA - - 0.1 V

IO = 4.0 mA - - 0.33 V

VOL LOW-level output voltage

pins C1A and C1B;

VCC = 4.5 V; VI = VIH or VIL; IO = 4.0 mA

- - 0.47 V

IIinput leakage current pins INH and VCO_IN;

VCC = 5.5 V; VI = VCC or GND

- - ±1.0 μA

General

ICC supply current disabled; VCC = 5.5 V; pin INH at VCC - - 80.0 μA

ΔICC additional supply current per input pin; VI = VCC - 2.1 V; VCC = 4.5 V;

other inputs at VCC or GND;

- - 450 μA

Product data sheet Rev. 9 — 20 March 2020 14 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

Symbol Parameter Conditions Min Typ Max Unit

Tamb = -40 °C to +125 °C

Phase comparator section

VIH HIGH-level input voltage pins SIG_IN and COMP_IN;

VCC = 4.5 V; DC coupled

3.15 - - V

VIL LOW-level input voltage pins SIG_IN and COMP_IN;

VCC = 4.5 V; DC coupled

- - 1.35 V

pins PCP_OUT and PCn_OUT;

VCC = 4.5 V; VI = VIH or VIL

IO = -20 μA 4.4 - - V

VOH HIGH-level output voltage

IO = -4.0 mA 3.7 - - V

pins PCP_OUT and PCn_OUT;

VCC = 4.5 V; VI = VIH or VIL

IO = 20 μA - - 0.1 V

VOL LOW-level output voltage

IO = 4.0 mA - - 0.4 V

IIinput leakage current pins SIG_IN and COMP_IN;

VCC = 5.5 V; VI = VCC or GND

- - ±45 μA

IOZ OFF-state output current pin PC2_OUT;

VCC = 5.5 V; VI = VIH or VIL; VO = VCC or GND

- - ±10.0 μA

VCO section

VIH HIGH-level input voltage pin INH; VCC = 4.5 V to 5.5 V; DC coupled 2.0 - - V

VIL LOW-level input voltage pin INH; VCC = 4.5 V to 5.5 V; DC coupled - - 0.8 V

pin VCO_OUT; VCC = 4.5 V; VI = VIH or VIL

IO = -20 μA 4.4 - - V

VOH HIGH-level output voltage

IO = -4.0 mA 3.7 - - V

pin VCO_OUT; VCC = 4.5 V; VI = VIH or VIL

IO = 20 μA - - 0.1 V

IO = 4.0 mA - - 0.4 V

VOL LOW-level output voltage

pins C1A and C1B; VCC = 4.5 V; VI = VIH or VIL;

IO = 4.0 mA

- - 0.54 V

IIinput leakage current pins INH and VCO_IN; VCC = 5.5 V; VCC or GND - - ±1.0 μA

General

ICC supply current disabled; VCC = 5.5 V; pin INH at VCC - - 160.0 μA

ΔICC additional supply current per input pin; VI = VCC - 2.1 V; VCC = 4.5 V;

other inputs at VCC or GND

- - 490 μA

Product data sheet Rev. 9 — 20 March 2020 15 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

mbd108

self-bias operating point

ΔVI

Fig. 16. Typical input resistance curve at SIG_IN and

COMP_IN

800

600

200

400

mga956 - 1

VI (V)

(0.5 VCC) - 0.25 0.5 VCC (0.5 VCC) + 0.25

(kΩ)

5.5 V

VCC =

4.5 V

Fig. 17. Input resistance at SIG_IN; COMP_IN with

ΔVI = 0.5 V at self-bias point

- 5

mga957

VI (V)

(0.5 VCC) - 0.25 0.5 VCC (0.5 VCC) + 0.25

(µA)

4.5 V

VCC = 5.5V

5.5 V

4.5 V

Fig. 18. Input current at SIG_IN; COMP_IN with

ΔVI = 0.5 V at self-bias point

- 40

mga958

(0.5 VCC) - 2 (0.5 VCC) + 20.5 VCC

- 20

Voffset

(mV)

VVCO_IN (V)

5.5 V

4.5 VVCC =

___ Rs = 50 kΩ

- - - Rs = 300 kΩ

Fig. 19. Offset voltage at demodulator output as a

function of VCO_IN and Rs

Product data sheet Rev. 9 — 20 March 2020 16 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

11. Dynamic characteristics

Table 6. Dynamic characteristics

GND = 0 V; tr = tf = 6 ns; CL = 50 pF. [1]

Symbol Parameter Conditions Min Typ Max Unit

Tamb = 25 °C

Phase comparator section

SIG_IN, COMP_IN to PC1_OUT;

VCC = 4.5 V; see Fig. 20

- 23 40 nstpd propagation delay

SIG_IN, COMP_IN to PCP_OUT;

VCC = 4.5 V; see Fig. 20

- 35 68 ns

ten enable time SIG_IN, COMP_IN to PC2_OUT;

VCC = 4.5 V; see Fig. 21

- 30 56 ns

tdis disable time SIG_IN, COMP_IN to PC2_OUT;

VCC = 4.5 V; see Fig. 21

- 36 65 ns

tttransition time VCC = 4.5 V; see Fig. 20 - 7 15 ns

Vi(p-p) peak-to-peak input voltage pin SIGN_IN or COMP_IN; VCC = 4.5 V;

AC coupled; fi = 1 MHz

[2] - 50 - mV

VCO section

Δf frequency deviation VCC = 5.0 V; VVCO_IN = 3.9 V; R1 = 10 kΩ;

R2 = 10 kΩ; C1 = 1 nF

[3] -10 - +10 %

VCC = 4.5 V; duty cycle = 50 %;

VVCO_IN = 0.5VCC; R1 = 4.3 kΩ; R2 = ∞ Ω;

C1 = 40 pF; see Fig. 25 and Fig. 33

11.0 15.0 - MHzf0center frequency

VCC = 5 V; duty cycle = 50 %;

VVCO_IN = 0.5VCC; R1 = 3 kΩ; R2 = ∞ Ω;

C1 = 40 pF; see Fig. 25 and Fig. 33

- 16.0 - MHz

Δf/f relative frequency variation VCC = 4.5 V; R1 = 100 kΩ; R2 = ∞ Ω;

C1 = 100 pF; see Fig. 26 and Fig. 27

[4] - 0.4 - %

δ duty cycle VCO_OUT; VCC = 4.5 V - 50 - %

General

CPD power dissipation capacitance [5][6] - 20 - pF

Tamb = -40 °C to +85 °C

Phase comparator section

SIG_IN, COMP_IN to PC1_OUT;

VCC = 4.5 V; see Fig. 20

- - 50 nstpd propagation delay

SIG_IN, COMP_IN to PCP_OUT;

VCC = 4.5 V; see Fig. 20

- - 85 ns

ten enable time SIG_IN, COMP_IN to PC2_OUT;

VCC = 4.5 V; see Fig. 21

- - 70 ns

tdis disable time SIG_IN, COMP_IN to PC2_OUT;

VCC = 4.5 V; see Fig. 21

- - 81 ns

tttransition time VCC = 4.5 V; see Fig. 20 - - 19 ns

VCO section

Δf/ΔT frequency variation with

temperature

VCC = 4.5 V; VVCO_IN = 0.5VCC;

recommended range: R1 = 10 kΩ;

R2 = 10 kΩ; C1 = 1 nF;

see Fig. 22, Fig. 23 and Fig. 24

[7] - 0.06 - %/K

Product data sheet Rev. 9 — 20 March 2020 17 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

Symbol Parameter Conditions Min Typ Max Unit

Tamb = -40 °C to +125 °C

Phase comparator section

SIG_IN, COMP_IN to PC1_OUT;

VCC = 4.5 V; see Fig. 20

- - 60 nstpd propagation delay

SIG_IN, COMP_IN to PCP_OUT;

VCC = 4.5 V; see Fig. 20

- - 102 ns

ten enable time SIG_IN, COMP_IN to PC2_OUT;

VCC = 4.5 V; see Fig. 21

- - 84 ns

tdis disable time SIG_IN, COMP_IN to PC2_OUT;

VCC = 4.5 V; see Fig. 21

- - 98 ns

tttransition time VCC = 4.5 V; see Fig. 20 - - 22 ns

[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH; tt is the same as tTLH and tTHL.

[2] This is the (peak to peak) input sensitivity.

[3] This is the center frequency tolerance.

[4] This is the frequency linearity.

[5] CPD is used to determine the dynamic power dissipation (PD in μW).

PD = CPD x VCC

2 x fi x N + ∑(CL x VCC

2 x fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in V;

N = total load switching outputs;

∑(CL x VCC

2 x fo) = sum of outputs.

[6] Applies to the phase comparator section only (pin INH = HIGH). For power dissipation of the VCO and demodulator sections,

see Fig. 28, Fig. 29 and Fig. 30.

[7] This is the frequency stability with temperature change.

mbd106

tPHL

tTHL

tPLH

tTLH

SIG_IN, COMP_IN

inputs

PCP_OUT, PC1_OUT

outputs

VM = 0.5VCC; VI = GND to VCC.

Fig. 20. Waveforms showing input (SIG_IN and COMP_IN) to output (PCP_OUT and PC1_OUT) propagation delays

and the output transition times

Product data sheet Rev. 9 — 20 March 2020 18 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

mga941

tPLZ

tPZH

tPHZ

10%

90%

tPZL

SIG_IN

input

COMP_IN

input

PC2_OUT

output

VM = 0.5VCC; VI = GND to VCC.

Fig. 21. Waveforms showing the enable and disable times for PC2_OUT

- 50 0 50 150

- 10

- 20

mbd115

100

Δ f

(%)

5.5 V

4.5 V

VCC =

Tamb (°C)

mbd116

Tamb (°C)

(%)

150100500- 50

- 15

- 10

- 5

5.5 V

4.5 V

VCC =

a. R1 = 3 kΩ; R2 = ∞ Ω; C1 = 100 pF. b. R1 = 10 kΩ; R2 = ∞ Ω; C1 = 100 pF.

Fig. 22. Frequency stability of the VCO as a function of ambient temperature with supply voltage as a parameter

Product data sheet Rev. 9 — 20 March 2020 19 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

- 50 0 50 150

- 5

- 10

mbd124

100

Δ f

(%)

5.5 V

4.5 V

VCC =

Tamb (°C)

mbd117

Tamb (°C)

(%)

150100500- 50

- 20

- 15

- 10

5.5 V

4.5 V

VCC =

- 5

a. R1 = 300 kΩ; R2 = ∞ Ω; C1 = 100 pF. b. R1 = ∞ Ω; R2 = 3 kΩ; C1 = 100 pF.

Fig. 23. Frequency stability of the VCO as a function of ambient temperature with supply voltage as a parameter

mbd118

Tamb (°C)

(%)

150100500- 50

- 12

- 8

- 4

5.5 V

4.5 V

VCC =

mbd119

Tamb (°C)

(%)

150100500- 50

- 10

- 5

5.5 V

4.5 V

VCC =

a. R1 = ∞ Ω; R2 = 10 kΩ; C1 = 100 pF. b. R1 = ∞ Ω; R2 = 300 kΩ; C1 = 100 pF.

Fig. 24. Frequency stability of the VCO as a function of ambient temperature with supply voltage as a parameter

Product data sheet Rev. 9 — 20 March 2020 20 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

0 2 4 6

mbd112

VVCO_IN (V)

fVCO

(MHz)

5.5 V

4.5 V

VCC =

0 2 4 6

mbd113

fVCO

(kHz)

5.5 V4.5 V

VCC =

VVCO_IN (V)

a. R1 = 4.3 kΩ; C1 = 39 pF. b. R1 = 4.3 kΩ; C1 = 100 nF.

0 2 4 6

800

600

200

400

mbd120

fVCO

(kHz)

VVCO_IN (V)

VCC = 5.5 V

4.5 V

0 2 4 6

400

300

100

200

mbd111

fVCO

(Hz)

frequency

4.5 V

5.5 VVCC =

VVCO_IN (V)

c. R1 = 300 kΩ; C1 = 39 pF. d. R1 = 300 kΩ; C1 = 100 nF.

Fig. 25. Graphs showing VCO frequency as a function of the VCO input voltage (VVCO_IN)

Product data sheet Rev. 9 — 20 March 2020 21 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

mga937

(MHz)

max

min 0.5 VCC

f'0

VVCO_IN (V)

V V

- 4

mbd114

10 102103

- 8

fVCO

(%)

R1 (kΩ)

C1 = 1 µF

4.5 V

5.5 V

C1 =

39 pF

4.5 V

5.5 V

linearity = R2 = ∞ Ω and ΔV = 0.5 V

Fig. 26. Definition of VCO frequency linearity: ΔV = 0.5 V

over the VCC range

Fig. 27. Frequency linearity as a function of R1, C1 and

VCC

3000 100

mbd121

10 1

200

10 2

R1 (kΩ)

4.5 V

C1 = 1 µF

5.5 V

C1 = 39 pF

4.5 V

C1 = 39 pF

5.5 V

C1 = 1 µF

VCC =

(W)

R2 = ∞ Ω

Fig. 28. Power dissipation as a function of R1

3000 100

mbd110

10 1

200

10 2

R2 (kΩ)

PD5.5 V

C1 = 39 pF

5.5 V

4.5 V

C1 = 1 µF

4.5 V

C1 = 39 pF

VCC =

(W)

R1 = ∞ Ω

Fig. 29. Power dissipation as a function of R2

Product data sheet Rev. 9 — 20 March 2020 22 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

103

mbd109

102

10 4

PDEM

(W)

Rs (kΩ)

10 5

10 3

VCC =

5.5 V

4.5 V

Fig. 30. Typical power dissipation as a function of Rs

12. Application information

This information is a guide for the approximation of values of external components to be used with

the 74HCT9046A in a phase-locked-loop system.

Values of the selected components should be within the ranges shown in Table 7.

Table 7. Survey of components

Component Value

R1 between 3 kΩ and 300 kΩ

R2 between 3 kΩ and 300 kΩ

R1 + R2 parallel value > 2.7 kΩ

C1 > 40 pF

Table 8. Design considerations for VCO section

Subject Phase comparator Design consideration

PC1, PC2 VCO frequency characteristic. With R2 = ∞ and R1 within the range

3 kΩ < R1 < 300 kΩ, the characteristics of the VCO operation will be as

shown in Fig. 31a. (Due to R1, C1 time constant a small offset remains

when R2 = ∞ Ω).

PC1 Selection of R1 and C1. Given f0, determine the values of R1 and C1

using Fig. 33.

VCO frequency

without extra offset

PC2 Given fmax and f0 determine the values of R1 and C1 using Fig. 33;

use Fig. 35 to obtain 2fL and then use this to calculate fmin.

PC1, PC2 VCO frequency characteristic. With R1 and R2 within the ranges

3 kΩ < R1 < 300 kΩ; 3 kΩ < R2 < 300 kΩ, the characteristics of the VCO

operation is as shown in Fig. 31b.

VCO frequency

with extra offset

PC1, PC2 Selection of R1, R2 and C1. Given f0 and fL determine the value

of product R1C1 by using Fig. 35. Calculate foff from the equation

foff = f0 - 1.6fL. Obtain the values of C1 and R2 by using Fig. 34. Calculate

the value of R1 from the value of C1 and the product R1C1.

PC1 VCO adjusts to f0 with ΦPC_IN = 90° and VVCO_IN = 0.5VCC

PLL conditions with no

signal at pin SIG_IN PC2 VCO adjusts to foffset with ΦPC_IN = -360° and VVCO_IN = minimum

Product data sheet Rev. 9 — 20 March 2020 23 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

mga938

fVCO

fmax

fmin

1.1 V 0.5 VCC VCC

VCC- 1.1 V

VCO_IN

2f Ldue to

R1,C1

a. Operating without offset; f0 = center frequency; 2fL = frequency lock range.

0.6fL

foff

fVCO

fmax

fmin

1.1 V

VCO_IN

2fLdue to

R1,C1

due to

R2,C1

mga939

0.5 VCC VCC

VCC- 1.1 V

b. Operating with offset; f0 = center frequency; 2fL = frequency lock range.

Fig. 31. Frequency characteristic of VCO

Product data sheet Rev. 9 — 20 March 2020 24 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

12.1. Filter design considerations for PC1 and PC2 of the

74HCT9046A

Fig. 32 shows some examples of passive and active filters to be used with the phase comparators

of the 74HCT9046A. Transfer functions of phase comparators and filters are given in Table 9.

Table 9. Transfer functions of phase comparators and filters

Phase

comparator

Explanation Figure Filter type Transfer function

Fig. 32a passive filter without damping

Fig. 32b passive filter with damping

PC1

= R3 x C2;

= R4 x C2;

= R4 x C3;

A = 105 = DC

gain amplitude

Fig. 32c active filter with damping

Fig. 32d passive filter with damping

A = 105 = DC gain amplitude

PC2

= R3’ x C2;

= R4 x C2;

= R4 x C3;

R3' = Rbias/17;

Rbias = 25 kΩ to 250 kΩ

Fig. 32e active filter with

damping

A = 105 = DC gain amplitude

Table 10. General design considerations

Subject Phase comparator Design consideration

PC1 yesPLL locks on harmonics at

center frequency PC2 no

PC1 highNoise rejection at signal input

PC2 low

PC1 fr = 2fi; large ripple content at ΦPC_IN = 90°AC ripple content when PLL is

locked PC2 fr = fi; small ripple content at ΦPC_IN = 0°

Product data sheet Rev. 9 — 20 March 2020 25 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

mbd107

1/ τ

F(jω)

C3 R4

R3'

AR3'

τ1τ2

1/ τ21/ τ3

1/ Aτ

1/ τ21/ τ3

1/ τ1

1/ τ21/ τ3

τ1

1/A

1/ τ21/ τ3

CIRCUIT

AMPLITUDE

CHARACTERISTIC

POLE ZERO

DIAGRAM

1/ τ11

τ1τ2

1/ τ1

PC2

PC1

(a)

(b)

(c)

(d)

(e)

τ1

1/A

R3'

F(jω)

Fig. 32. Passive and active filters for 74HCT9046A

Product data sheet Rev. 9 — 20 March 2020 26 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

mbd103

107

105

104

103

101

105

103

102

104

106

C1 (pF)

107

108

102

(Hz)

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(1) VCC = 5.5 V; R1 = 3 kΩ.

(2) VCC = 4.5 V; R1 = 3 kΩ.

(3) VCC = 5.5 V; R1 = 10 kΩ.

(4) VCC = 4.5 V; R1 = 10 kΩ.

(5) VCC = 5.5 V; R1 = 150 kΩ.

(6) VCC = 4.5 V; R1 = 150 kΩ.

(7) VCC = 5.5 V; R1 = 300 kΩ.

(8) VCC = 4.5 V; R1 = 300 kΩ.

R2 = ∞ Ω; VVCO_IN = 0.5VCC; INH = GND; Tamb = 25 °C.

Fig. 33. Typical value of VCO center frequency (f0) as a function of C1

mbd104

107

105

104

103

101

105

103

102

104

106

C1 (pF)

107

108

102

foff

(Hz)

(2)

(1)

(3)

(4)

(1) VCC = 4.5 V to 5.5 V; R2 = 3 kΩ.

(2) VCC = 4.5 V to 5.5 V; R2 = 10 kΩ.

(3) VCC = 4.5 V to 5.5 V; R2 = 150 kΩ.

(4) VCC = 4.5 V to 5.5 V; R2 = 300 kΩ.

R1 = ∞ Ω; VVCO_IN = 0.5VCC; INH = GND; Tamb = 25 °C.

Fig. 34. Typical value of frequency offset as a function of C1

Product data sheet Rev. 9 — 20 March 2020 27 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

mbd105

10- 7

105

103

102

104

106

R1C1 (s)

107

108

2fL

(Hz)

VCC =

10- 6 10- 5 10- 4 10- 3 10- 2 10- 1 1

5.5 V

4.5 V

VVCO_IN = 1.1 V to (VCC - 1.1) V

Fig. 35. Typical frequency lock range 2fL as a function of the product R1 and C1

Product data sheet Rev. 9 — 20 March 2020 28 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

12.2. PLL design example

The frequency synthesizer used in the design example shown in Fig. 36 has the following

parameters:

•Output frequency: 2 MHz to 3 MHz

•Frequency steps: 100 kHz

•Settling time: 1 ms

•Overshoot: < 20 %

The open loop gain is:

and the closed loop:

where:

•Kp = phase comparator gain

•Kf = low-pass filter transfer gain

•Ko = Kv/s VCO gain

•Kn = 1⁄n divider ratio

The programmable counter ratio Kn can be found as follows:

The VCO is set by the values of R1, R2 and C1; R2 = 10 kΩ (adjustable).

The values can be determined using the information in Table 8.

With f0 = 2.5 MHz and fL = 500 kHz this gives the following values (VCC = 5.0 V):

•R1 = 30 kΩ

•R2 = 30 kΩ

•C1 = 100 pF

The VCO gain is:

The gain of the phase comparator PC2 is:

Using PC2 with the passive filter as shown in Fig. 36 results in a high gain loop with the same

performance as a loop with an active filter. Hence loop filter equations as for a high gain loop

should be used. The current source output of PC2 can be simulated then with a fictive filter

resistance:

Product data sheet Rev. 9 — 20 March 2020 29 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

The transfer functions of the filter is given by:

Where:

The characteristic equation is:

This results in:

or:

This can be written as:

with the natural frequency ωn defined as:

and the damping value given as:

In Fig. 37 the output frequency response to a step of input frequency is shown.

The overshoot and settling time percentages are now used to determine ωn. From Fig. 37 it can

be seen that the damping ratio ζ = 0.707 will produce an overshoot of less than 20 % and settle to

within 5 % at ωnt = 5. The required settling time is 1 ms. This results in:

Rewriting the equation for natural frequency results in:

The maximum overshoot occurs at Nmax = 30; hence Kn = 1⁄30:

When C2 = 470 nF, it follows:

Hence the current source bias resistance

With ζ = 0.707 (0.5 x × ωn) it follows:

For extra ripple suppression a capacitor C3 can be connected in parallel with R4, with an extra

= R4 x C3.

For stability reasons should be < 0.1 , hence C3 < 0.1C2 or C3 = 39 nF.

Product data sheet Rev. 9 — 20 March 2020 30 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

mbd098

C2 R2R1

VCO

R3'

PHASE

COMPARATOR

PC2

DIVIDE BY 10

"190"

OSCILLATOR

"HCU04"

100 kHz

4fOUT

PROGRAMMABLE

DIVIDER

"4059"

11 12 6 7 5

1 MHz

KfKo

(1)

Rbias

Φu

(1) R3'= fictive resistance

R3’ =

C1 = 100 pF

C2 = 470 nF

C3 = 39 nF

R1 = 30 kΩ

R2 = 30 kΩ

R3' = 2 550 Ω

Rbias = 43 kΩ

R4 = 600 Ω

Fig. 36. Frequency synthesizer

0 1 2 4

1.6

1.0

0.6

0.8

mga959

1.4

1.2

0.4

0.2

5 6 7 8

ωnt

ΔΦe(t)

ΔΦe/ωn

Δωe(t)

Δωe/ωn

- 0.6

0.4

1.0

0.2

- 0.4

- 0.2

0.6

0.8

= 5.0

0.5

0.707

1.0

= 0.3

= 2.0

Fig. 37. Type 2, second order frequency step response

Product data sheet Rev. 9 — 20 March 2020 31 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

mga952

3.1

2.9

2.1

2.0

1.9 0 0.5 1.0 1.5 2.0 2.5

time (ms)

proportional

to output

frequency

(MHz)

N = 30

N stepped from 29 to 30

step input

N stepped from 21 to 20

Fig. 38. Frequency compared to the time response

Since the output frequency is proportional to the VCO control voltage, the PLL frequency response

can be observed with an oscilloscope by monitoring pin VCO_IN of the VCO. The average

frequency response, as calculated by the Laplace method, is found experimentally by smoothing

this voltage at pin VCO_IN with a simple RC filter, whose time constant is long compared with the

phase detector sampling rate but short compared with the PLL response time.

Product data sheet Rev. 9 — 20 March 2020 32 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

13. Package outline

w M

detail X

v M A

(A )

pin 1 index

UNIT A

max. A

1 A

2 A

3 b

p c D

(1) E

(1) (1)

e H

E L L

p Q Z y w v θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10

1.45

1.25 0.25 0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8 1.27 6.2

5.8

0.7

0.6

0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1 99-12-27

03-02-19

076E07 MS-012

0.069 0.010

0.004

0.057

0.049 0.01 0.019

0.014

0.0100

0.0075

0.39

0.38

0.16

0.15 0.05

1.05

0.041

0.244

0.228

0.028

0.020

0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Fig. 39. Package outline SOT109-1 (SO16)

Product data sheet Rev. 9 — 20 March 2020 33 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

14. Abbreviations

Table 11. Abbreviations

Acronym Description

CMOS Complementary Metal Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

PLL Phase Locked Loop

TTL Transistor-Transistor Logic

VCO Voltage Controlled Oscillator

15. Revision history

Table 12. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74HCT9046A v.9 20190320 Product data sheet - 74HCT9046A v.8

Modifications: •Fig. 34: typo corrected in the conditions

74HCT9046A v.8 20190131 Product data sheet - 74HCT9046A v.7

Modifications: •The format of this data sheet has been redesigned to comply with the identity guidelines of

Nexperia.

•Legal texts have been adapted to the new company name where appropriate.

•Type number 74HCT9046APW (SOT403-1/TSSOP16) removed.

74HCT9046A v.7 20160229 Product data sheet - 74HCT9046A v.6

Modifications: •Type number 74HCT9046AN (SOT38-4) removed.

74HCT9046A v.6 20090915 Product data sheet - 74HCT9046A v.5

Modifications: •The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

•Vi(p-p) value changed from 15 mV to 50 mV in Section 11.

•Δf/ΔT value moved from minimum to typical column Section 11.

•Package version SOT38-1 changed to SOT38-4.

74HCT9046A v.5 20031030 Product specification - 74HCT9046A v.4

74HCT9046A v.4 20030515 Product specification - 74HCT9046A v.3

74HCT9046A v.3 19990111 Product specification - -

Product data sheet Rev. 9 — 20 March 2020 34 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

16. Legal information

Data sheet status

Document status

[1][2]

Product

status [3]

Definition

Objective [short]

data sheet

Development This document contains data from

the objective specification for

product development.

Preliminary [short]

data sheet

Qualification This document contains data from

the preliminary specification.

Product [short]

data sheet

Production This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have

changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

the internet at https://www.nexperia.com.

Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. Nexperia does not give any representations or

warranties as to the accuracy or completeness of information included herein

and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the relevant

full data sheet, which is available on request via the local Nexperia sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

Nexperia and its customer, unless Nexperia and customer have explicitly

agreed otherwise in writing. In no event however, shall an agreement be

valid in which the Nexperia product is deemed to offer functions and qualities

beyond those described in the Product data sheet.

Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, Nexperia does not give any

representations or warranties, expressed or implied, as to the accuracy

or completeness of such information and shall have no liability for the

consequences of use of such information. Nexperia takes no responsibility

for the content in this document if provided by an information source outside

of Nexperia.

In no event shall Nexperia be liable for any indirect, incidental, punitive,

special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, Nexperia’s aggregate and cumulative liability towards customer

for the products described herein shall be limited in accordance with the

Terms and conditions of commercial sale of Nexperia.

Right to make changes — Nexperia reserves the right to make changes

to information published in this document, including without limitation

specifications and product descriptions, at any time and without notice. This

document supersedes and replaces all information supplied prior to the

publication hereof.

Suitability for use — Nexperia products are not designed, authorized or

warranted to be suitable for use in life support, life-critical or safety-critical

systems or equipment, nor in applications where failure or malfunction

of an Nexperia product can reasonably be expected to result in personal

injury, death or severe property or environmental damage. Nexperia and its

suppliers accept no liability for inclusion and/or use of Nexperia products in

such equipment or applications and therefore such inclusion and/or use is at

the customer’s own risk.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no representation

or warranty that such applications will be suitable for the specified use

without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using Nexperia products, and Nexperia accepts no liability for

any assistance with applications or customer product design. It is customer’s

sole responsibility to determine whether the Nexperia product is suitable

and fit for the customer’s applications and products planned, as well as

for the planned application and use of customer’s third party customer(s).

Customers should provide appropriate design and operating safeguards to

minimize the risks associated with their applications and products.

Nexperia does not accept any liability related to any default, damage, costs

or problem which is based on any weakness or default in the customer’s

applications or products, or the application or use by customer’s third party

customer(s). Customer is responsible for doing all necessary testing for the

customer’s applications and products using Nexperia products in order to

avoid a default of the applications and the products or of the application or

use by customer’s third party customer(s). Nexperia does not accept any

liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — Nexperia products are

sold subject to the general terms and conditions of commercial sale, as

published at http://www.nexperia.com/profile/terms, unless otherwise agreed

in a valid written individual agreement. In case an individual agreement is

concluded only the terms and conditions of the respective agreement shall

apply. Nexperia hereby expressly objects to applying the customer’s general

terms and conditions with regard to the purchase of Nexperia products by

customer.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific Nexperia product is automotive qualified, the

product is not suitable for automotive use. It is neither qualified nor tested in

accordance with automotive testing or application requirements. Nexperia

accepts no liability for inclusion and/or use of non-automotive qualified

products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards,

customer (a) shall use the product without Nexperia’s warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

Nexperia’s specifications such use shall be solely at customer’s own risk,

and (c) customer fully indemnifies Nexperia for any liability, damages or failed

product claims resulting from customer design and use of the product for

automotive applications beyond Nexperia’s standard warranty and Nexperia’s

product specifications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Trademarks

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

Product data sheet Rev. 9 — 20 March 2020 35 / 36

Nexperia 74HCT9046A

PLL with band gap controlled VCO

Contents

1. General description...................................................... 1

2. Features and benefits.................................................. 1

3. Applications.................................................................. 1

4. Ordering information....................................................1

5. Functional diagram.......................................................2

6. Pinning information......................................................4

6.1. Pinning.........................................................................4

6.2. Pin description............................................................. 4

7. Functional description................................................. 5

7.1. Differences with respect to the familiar 74HCT4046A..5

7.2. VCO............................................................................. 5

7.3. Phase comparators......................................................6

7.3.1. Phase Comparator 1 (PC1)...................................... 6

7.3.2. Phase Comparator 2 (PC2)...................................... 7

7.4. Loop filter component selection.................................11

8. Limiting values........................................................... 12

9. Recommended operating conditions........................12

10. Static characteristics................................................12

11. Dynamic characteristics...........................................17

12. Application information........................................... 23

12.1. Filter design considerations for PC1 and PC2 of

the 74HCT9046A............................................................... 25

12.2. PLL design example................................................ 29

13. Package outline........................................................ 33

14. Abbreviations............................................................ 34

15. Revision history........................................................34

16. Legal information......................................................35

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 20 March 2020

Product data sheet Rev. 9 — 20 March 2020 36 / 36