PRELIMINARY W942516AH 4M x 4 BANKS x 16 BIT DDR SDRAM GENERAL DESCRIPTION W942516AH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM), organized as 4,194,304 words x 4 banks x 16 bits. Using pipelined architecture and 0.175 m process technology, W942516AH delivers a data bandwidth of up to 286M words per second (-7). To fully comply with the personal computer industrial standard, W942516AH is sorted into three speed grades: -7, -75 and -8. The -7 is compliant to the 143 MHz/CL2.5 or DDR266/CL2 specification, the 75 is compliant to the DDR266/CL2.5 specification, the -8 is compliant to the DDR200/CL2 specification All Inputs reference to the positive edge of CLK (except for DQ, DM, and CKE). The timing reference point for the differential clock is when the CLK and CLK signals cross during a transition. And Write and Read data are synschronized with the both edges of DQS (Data Strobe). By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W942516AH is ideal for main memory in high performance applications. FEATURES * 2.5V 0.2V Power Supply * Up to 143 MHz Clock Frequency * Double Data Rate architecture; two data transfers per clock cycle * Differential clock inputs (CLK and CLK ) * DQS is edge-aligned with data for Read; center-aligned with data for Write * CAS Latency: 2 and 2.5 * Burst Length: 2, 4, and 8 * Auto Refresh and Self Refresh * Precharged Power Down and Active Power-Down * Write Data Mask * Write Latency = 1 * 8K Refresh cycles / 64 mS * Interface: SSTL-2 * Packaged: TSOP II 66 pin, 400 x 875mil , 0.65mm pin pitch KEY PARAMETERS SYM. tCK tRAS tRC IDD1 IDD4 IDD6 DESCRIPTION Clock Cycle Time CL=2 CL=2.5 Active to Precharge Command Period Active to Ref/Active Command Period Operation Current (Single bank) Burst Operation Current Self-Refresh Current -1- MIN. /MAX. -7 -75 -8 min. min. min. min. max. max. max. 7.5 nS 7 nS 45 nS 65 nS 110mA 165mA 3mA 8 nS 7.5 nS 45 nS 65 nS 110mA 155mA 3mA 10 nS 8 nS 50 nS 70 nS 100mA 150mA 3mA Publication Release Date: May 2001 Revision .0.0 W942516AH PIN CONFIGURATION (TOP VIEW) VDD 1 66 VSS DQ0 2 65 DQ15 VDDQ 3 64 VSSQ DQ1 4 63 DQ14 DQ2 5 62 DQ13 VSSQ 6 61 VDDQ DQ3 7 60 DQ12 DQ4 8 59 DQ11 VDDQ 9 58 VSSQ DQ5 10 57 DQ10 DQ6 11 56 DQ9 VSSQ 12 55 VDDQ DQ7 13 54 DQ8 NC 14 53 NC VDDQ 15 52 VSSQ LDQS 16 51 UDQS NC 17 50 NC VDD 18 49 VREF NC 19 48 VSS LDM 20 47 UDM WE 21 46 CLK CAS 22 45 CLK RAS 23 44 CKE CS 24 43 NC NC 25 42 A12 BS0 26 41 A11 BS1 27 40 A9 A10/AP 28 39 A8 A0 29 38 A7 A1 30 37 A6 A2 31 36 A5 A3 32 35 A4 VDD 33 34 VSS -2- W942516AH PIN DESCRIPTION Pin Number Pin Name Description Function Multiplexed pins for row and column address. Row address : A0 - A12. Column address: A0 - A8. (A10 is used for Auto Precharge) Select bank to activate during row address latch time, or bank to read/write during column address latch time. 28-32,35-42 A0 - A12 Address 26,27 BS0, BS1 Bank Select DQ0 - DQ15 Data Input/ Output The DQ0 - DQ15 input and output data are synchronized with both edges of DQS. 51 DQS Data Strobe DQS is Bi-directional signal. DQS is input signal during write operation and output signal during read operation. It is Edgealigned with read data, Center-aligned with write data. 24 CS Chip Select Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. 2,4,5,7,8,10,11, 13,54,56,57,59, 60,62,63,65 23,22,21 RAS , CAS , WE 47 45,46 DM CLK, CLK Command Inputs Command inputs (along with CS ) define the command being entered. Write mask Differential clock Clock inputs, all inputs reference to the positive edge of CLK inputs (except for DQ, DM and CKE). 44 CKE Clock Enable 49 VREF Reference Voltage 1,18,33 VDD 34,48,66 VSS 3,9,15,55,61 VDDQ 6,12,52,58,64 VSSQ 14,17,19,25,43, 50,53 NC When DM is asserted "high" in burst write, the input data is masked. DM is synchronized with both edges of DQS. CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self Refresh mode is entered. VREF is reference voltage for inputs buffers. Power ( +2.5V ) Power for logic circuit inside DDR SDRAM. Ground Ground for logic circuit inside DDR SDRAM. Power ( + 2.5V ) Separated power from VDD, used for output buffer, to improve for I/O buffer noise. Ground for I/O buffer Separated ground from VSS, used for output buffer, to improve noise. No Connection No connection -3- Publication Release Date: May 2001 Revision 0.0 W942516AH BLOCK DIAGRAM CLK CLK DLL CLOCK BUFFER CKE CONTROL CS RAS SIGNAL GENERATOR COMMAND CAS DECODER COLUMN DECODER A10 CELL ARRAY BANK #0 COLUMN DECODER ROW DECODER ROW DECODER WE MODE REGISTER A0 SENSE AMPLIFIER SENSE AMPLIFIER ADDRESS BUFFER PREFETCH REGISTER DQ DATA CONTROL BUFFER DQ0 DQ15 CIRCUIT COLUMN COUNTER COUNTER LDQS, UDQS LDM, UDM COLUMN DECODER CELL ARRAY BANK #2 COLUMN DECODER ROW DECODER REFRESH ROW DECODER A9 A11 A12 BA1 BA0 CELL ARRAY BANK #1 SENSE AMPLIFIER NOTE: The cell array configuration is 8912 * 512 * 16 -4- CELL ARRAY BANK #3 SENSE AMPLIFIER W942516AH ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT NOTES Input, Output Voltage VIN, VOUT -0.3 ~ VDDQ +0.3 V 1 Power Supply Voltage VDD, VDDQ -0.3 ~ 3.6 V 1 Operating Temperature TOPR 0 ~ 70 C 1 Storage Temperature TSTG -55 ~ 150 C 1 TSOLDER 260 C 1 PD 1 W 1 IOUT 50 mA 1 Soldering Temperature (10s) Power Dissipation Short Circuit Output Current RECOMMENDED DC OPERATING CONDITIONS (Ta = 0 to 70C) PARAMETER Power Supply Voltage SYMBOL MIN. TYP. MAX. UNIT NOTES VDD 2.3 2.5 2.7 V 2 Power Supply Voltage (for I/O Buffer) VDDQ 2.3 2.5 VDD V 2 Input reference Voltage VREF 0.49 x VDDQ 0.50 x VDDQ 0.51 x VDDQ V 2,3 VTT VREF - 0.04 VREF VREF + 0.04 V 2,8 VIH (DC) VREF + 0.15 - VDDQ + 0.3 V 2 Termination Voltage (System) Input High Voltage (DC) Input Low Voltage (DC) VIL (DC) -0.3 - VREF - 0.15 V 2 Differential Clock DC Input Voltage VICK (DC) -0.3 - VDDQ + 0.3 V 15 Input Differential Voltage. CLK and VID (DC) 0.36 - VDDQ + 0.6 V 13,15 VIH (AC) VREF + 0.31 - - V 2 CLK inputs (DC) Input High Voltage (AC) Input Low Voltage (AC) VIL (AC) - - VREF - 0.31 V 2 Input Differential Voltage. CLK and VID (AC) 0.7 - VDDQ + 0.6 V 13,15 Differential AC input Cross Point Voltage VX (AC) VDDQ/2 - 0.2 - VDDQ/2 + 0.2 V 12, 15 Differential Clock AC Middle Point VISO (AC) VDDQ/2 - 0.2 - VDDQ/2 + 0.2 V 14, 15 CLK inputs (AC) Note : Undershoot Limit : VIL(min) = -0.9V with a pulse width < 5 nS Overshoot Limit : VIH(max) = VDDQ+0.9V with a pulse width < 5 nS VIH(DC) and VIL(DC) are levels to maintain the current logic state. VIH(AC) and VIL(AC) are levels to change to the new logic state. -5- Publication Release Date: May 2001 Revision 0.0 W942516AH CAPACITANCE (VDD = VDDQ = 2.5V 0.2V, f = 1 MHz, TA = 25C, VOUT(DC) = VDDQ/2, VOUT(Peak to Peak) = 0.2V) PARAMETER DELTA UNIT SYMBOL MIN. MAX. CIN 2.0 3.5 - pF CCLK 2.0 3.5 - pF DQ, DQS, DM capacitance CI/O 4.0 5.0 0.5 pF NC pin capacitance CNC - 1.5 - pF Input Capacitance (except for CLK pins) Input Capacitance (CLK pins) Note: These parameters are periodically sampled and not 100% tested. -6- (MAX.) W942516AH DC CHARACTERISTICS PARAMETER SYM. Max. -7 -75 -8 UNIT NOTES OPERATING CURRENT : One Bank Active-Precharge; tRC = tRC min; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle; Address and control inputs changing once per clock cycle IDD0 110 110 100 7 OPERATING CURRENT : One Bank Active-Read-Precharge; Burst=2; tRC = tRC min; CL=2.5; tCK = tCK min; IOUT=0mA; Address and control inputs changing once per clock cycle. IDD1 110 110 100 7,9 PRECHARGE-POWER-DOWN STANDBY CURRENT : All Banks Idle; Power down mode; CKE < VIL max; tCK = tCK min; Vin = VREF for DQ, DQS and DM IDD2P 2 2 2 IDLE FLOATING STANDBY CURRENT : CS > VIH min; All Banks Idle; CKE > VIH min; Address and other control inputs changing once per clock cycle; Vin = Vref for DQ, DQS and DM IDD2F 45 40 35 7 IDLE STANDBY CURRENT : CS > VIH min; All Banks Idle; CKE > VIH min; tCK = tCK min; Address and other control inputs changing once per clock cycle; Vin > VIH min or Vin < VIL max for DQ, DQS and DM IDD2N 45 40 35 7 IDLE QUIET STANDBY CURRENT : CS > VIH min; All Banks Idle; CKE > VIH min; tCK = tCK min; Address and other control inputs stable; Vin > VREF for DQ, DQS and DM IDD2Q 40 35 30 ACTIVE POWER-DOWN STANDBY CURRENT : One Bank Active; Power down mode; CKE < VIL max; tCK = tCK min IDD3P 20 20 20 ACTIVE STANDBY CURRENT : CS > VIH min; CKE > VIH min; One Bank Active-Precharge; tRC = tRAS max; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD3N 70 65 60 7 OPERATING CURRENT : Burst=2; Reads; Continuous burst; One Bank Active; Address and control inputs changing once per clock cycle; CL=2.5; tCK = tCK min; IOUT=0mA IDD4R 165 155 150 7,9 OPERATING CURRENT : Burst=2; Write; Continuous burst; One Bank Active; Address and control inputs changing once per clock cycle; CL=2.5; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle IDD4W 165 155 150 7 AUTO REFRESH CURRENT : tRC = tRFC min IDD5 190 190 170 7 SELF REFRESH CURRENT : CKE < 0.2V IDD6 3 3 3 RANDOM READ CURRENT : 4 Banks Active Read with activate every 20ns, Auto-Precharge Read every 20ns; Burst=4; tRCD= 3; IOUT= 0mA; DQ, DM and DQS inputs changing twice per clock cycle; Address changing once per clock cycle IDD7 270 270 270 -7- mA 7 Publication Release Date: May 2001 Revision 0.0 W942516AH RANDOM READ CURRENT TIMING (IDD7) tCK = 10ns tRC CK CK tRCD COMMAND ADDRESS ACT READ AP ACT READ AP ACT READ AP ACT READ AP ACT Bank 0 Row d Bank 3 Row c Bank 1 Row e Bank 0 Row d Bank 2 Row f Bank 1 Row e Bank 3 Row q Bank 2 Col f Bank 0 Row h DQS DQ Qa Qa Qb Qb Qb Qb Qc Qc Qc Qc Qd Qd Qd Qd Qe Qe LEAKAGE AND OUTPUT BUFFER STRENGTH PARAMETER SYMBOL MIN. MAX. UNITS II(L) -2 2 uA IO(L) -5 5 uA VOH VTT + 0.76 - V VOL - VTT - 0.76 V Output minimum source DC current IOH (DC) -15.2 - mA 4,6 Output minimum sink DC current IOL (DC) 15.2 - mA 4,6 IOH (DC) -10.4 - mA 5 IOL (DC) 10.4 - mA 5 Input leakage current (0V < VIN < VDDQ All other pins not under test = 0V) Output leakage current (Output disabled, 0V < VOUT < VDDQ ) Output High voltage (under AC test load condition) Output Low voltage (under AC test load condition) Output minimum source DC current Full Strength Half Strength Output minimum sink DC current -8- NOTES W942516AH AC CHARACTERISTICS AND OPERATING CONDITIONS (NOTES: 10, 12) SYMBOL tRC tRFC tRAS tRCD tRAP tCCD tRP tRRD tWR tDAL tCK PARAMETER Active to Ref/Active Command Period Ref to Ref/Active Command Period Active to Precharge Command Period Active to Read/Write Command Delay Time Active to Read with Auto Precharge enable Read/Write(a) to Read/Write(b) Command Period Precharge to Active Command Period Active(a) to Active(b) Command Period Write Recovery time Auto Precharge Write Recovery + Precharge time CLK Cycle Time CL=2 tAC tDQSQ tCH tCL tHP tQH tRPRE tRPST tDS tDH tDIPW tDQSH tDQSL tDSS tDSH tWPRES tWPRE tWPST tDQSS tDSSK tIS tIH tIPW tHZ tLZ tT(SS) tWTR tXSNR tXSRD tREF tMRD -75 MAX. 100000 MIN. 65 75 45 15 15 1 20 15 15 30 -8 MAX. 100000 MIN. 70 80 50 20 20 1 20 15 15 35 UNITS 100000 15 8 15 10 15 15 7.5 15 8 15 Data Access time from CLK, CLK -0.75 0.75 -0.75 0.75 -0.8 0.8 DQS output access time from CLK, CLK Data Strobe Edge to Output Data Edge Skew CLk Hight level width CLK Low level width CLK half period (minmum of actual tCH, tCL) -0.75 0.75 -0.75 0.75 -0.8 0.8 DQ output data hold time from DQS DQS Read Preamble Time DQS Read Postamble Time DQ and DM Setup Time DQ and DM Hold Time DQ and DM input pulse width (for each input) DQS input high pulse width DQS input low pulse width DQS falling edge to CLK setup time DQS falling edge hold time from CLK Clock to DQS Write Preamble Set-up Time DQS Write Preamble Time DQS Write Postamble Time Write command to first DQS latching transition UDQS - LDQS Skew (x16) Input Setup Time Input Hold Time Control & Address input pulse width (for each input) 0.5 0.55 0.55 1.1 0.6 1.25 0.25 0.45 0.45 min (tCL,tCH) tHP -0.75 0.9 0.4 0.5 0.5 1.75 0.35 0.35 0.2 0.2 0 0.25 0.4 0.75 -0.25 0.9 0.9 2.2 0.5 0.55 0.55 0.45 0.45 min (tCL,tCH) 0.6 0.55 0.55 1.25 0.25 0.9 0.4 0.6 0.6 2 0.35 0.35 0.2 0.2 0 0.25 0.4 0.75 -0.25 1.2 1.2 2.5 1.1 0.6 1.25 0.25 -0.75 0.75 -0.8 0.8 Data-out Low-impedance Time from CLK, CLK SSTL Input Transition Internal Write to Read command delay Exit Self Refresh to non-Read command Exit Self Refresh to Read command Refresh Time (8K) Mode Register Set cycle time -0.75 0.75 -0.75 0.75 -0.8 0.8 0.5 1 75 10 1.5 0.5 1 75 10 1.5 0.5 1 80 10 1.5 -9- 64 64 16 11 tCK 11 11 ns 0.75 15 tCK tCK -0.75 64 16 ns Data-out High-impedance Time from CLK, CLK 15 ns ns tHP-1.0 1.1 0.6 ns tCK 7 0.45 0.45 min (tCL,tCH) tHP -0.75 0.9 0.4 0.5 0.5 1.75 0.35 0.35 0.2 0.2 0 0.25 0.4 0.75 -0.25 0.9 0.9 2.2 NOTES MAX. 7.5 CL=2.5 tDQSCK -7 MIN. 65 75 45 15 15 1 20 15 15 30 tCK 11 ns tCK ns tCK ms ns Publication Release Date: May 2001 Revision 0.0 W942516AH AC TEST CONDITIONS PARAMETER SYMBOL VIH VIL VREF VTT VSWING Vr VID(AC) SLEW VOTR VALUE UNIT NOTE Input High voltage (AC) Input Low voltage (AC) Input reference voltage Termination voltage Input signal peak to peak swing Differential Clock Input Reference Voltage VREF+0.31 VREF-0.31 0.5xVDDQ 0.5xVDDQ 1.0 Vx(AC) V V V V V V Input Difference Voltage. CLK and CLK inputs (AC) Input signal minmum slew rate Output timing measurement refernece voltage 1.5 V 1.0 0.5xVDDQ V/ns V VTT VDDQ V SWING(max) VIHmin(AC) VREF VILmax(AC) CLK RT = 50 ohms Vss Rs = 50 ohms 30pF t t SLEW=V IHmin(AC)-V ILmax(AC)/ t A.C TEST LOAD - 10 - W942516AH Note: (1) Conditions outside the limits listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the device. (2) All voltages are referenced to VSS, VSSQ. (3) Peak to peak AC noise on VREF may not exceed 2% of VREF(DC). (4) VOH=1.95V,VOL=0.35V (5) VOH=1.9V,VOL=0.4V (6) The values of IOH(DC) is based on VDDQ=2.3V and VTT=1.19V. The values of IOL(DC) is based on VDDQ=2.3V and VTT=1.11V. (7) These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimun values of tCK and tRC. (8) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. (9) These parameters depend on the output loading.Specified values are obtained with the output open. (10) Transition times are measured between VIH min(AC) and VIL max(AC).Transition (rise and fall) of input signals have a fixed slope. (11) If the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to the nearest decimal place. (i.e., tDQSS=0.75xtCK, tCK=7.5ns, 0.75 x 7.5ns = 5.625ns is rounded up to 5.6ns.) (12) VX is the differential clock cross point voltage where input timing measurement is referenced. (13) VID is magnitude of the difference between CLK input level and CLK input level. (14) VISO means {VICK(CLK) + VICK( CLK )}/2. (15) Refer to the figure below. CLK VX VX VX VICK VX VICK VX VID(AC) CLK VICK VICK VSS VID(AC) 0 V Differential VISO VISO(min) VISO(max) VSS (16) tAC and tDQSCK depend on the clock jitter. These timing are measured at stable clock. - 11 - Publication Release Date: May 2001 Revision 0.0 W942516AH OPERATION MODE The following table shows the operation commands. Simplified Truth Table (Note (1) and (2)) A12, Symbol Command Device State CKEn- CKEn (4) DM 1 BS0, A10 A11, CS RAS CAS WE A9-A0 BS1 (3) H X X V V V L L H H (3) H X X V L X L L H L H X X X H X L L H L (3) H X X V L V L H L L (3) H X X V H V L H L L (3) H X X V L V L H L H (3) ACT Bank Active Idle PRE Bank Precharge Any PREA Precharge All WRIT Write Any Active WRITA Write with Auto Active READ Read Active READA Read with Auto Active H X X V H V L H L H MRS Mode Register Set Idle H X X L,L C C L L L L EMRS Extended Idle H X X H,L V V L L L L NOP No Operation Any H X X X X X L H H H BST Burst Read Stop Active H X X X X X L H H L DSL Device Deselect Any H X X X X X H X X X AREF Auto Refresh Idle H H X X X X L L L H SELF Self Refresh Entry Idle H L X X X X L L L H SELEX Self Refresh Exit Idle (Self Refresh) L H X X X X H X X X L H H X PD PDEX Mode (5) Power down mode entry Idle/Active H Power down mode exit Any (Power Down) L L H X X X X X X X H X X X L H H X X H X X X H X H X X X X X X WDE Data write enable Active H X L X X X L X WDD Data write disable Active H X H X X X X Note:1. V=Valid X=Don't Care L=Low level H=High level 2. CKEn signal is input levell when commands are issued. CKEn-1 signal is input level one clock cycle before the commands are issued. 3. These are state designated by the BS0,BS1 signals. 4. LDM, UDM (W942516AH) 5. Power Down Mode can not entry in the burst cycle. - 12 - W942516AH Function Truth Table(Note 1) Current State CS Idle H L L Row active Read Write Address Command Action Notes CAS WE X X X X DSL Nop H H X X NOP/BST Nop H L H BS,CA,A10 READ/READ ILLEGAL 3 L H L L BS,CA,A10 WRIT/WRIT ILLEGAL 3 L L H H BS,RA ACT Row activating L L H L BS,A10 PRE/PREA Nop L L L H X AREF/SELF Refresh or Self refresh 2 L L L L Op-Code MRS/EMRS Mode register accessing 2 H X X X X DSL Nop L H H X X NOP/BST Nop L H L H BS,CA,A10 READ/READ Begin read: Determine AP 4 L H L L BS,CA,A10 WRIT/WRIT Begin write: Determine AP 4 L L H H BS,RA ACT ILLEGAL 3 L L H L BS,A10 PRE/PREA Precharge 5 L L L H X AREF/SELF ILLEGAL RAS L L L L Op-Code MRS/EMRS ILLEGAL H X X X X DSL Continue burst to end L H H H X NOP Continue burst to end L H H L X BST Burst stop L H L H BS,CA,A10 READ/READ Term burst, new read: Determine AP L H L L BS,CA,A10 WRIT/WRIT ILLEGAL L L H H BS,RA ACT ILLEGAL L L H L BS,A10 PRE/PREA Term burst, precharging L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL H X X X X DSL Continue burst to end L H H H X NOP Continue burst to end L H H L X BST ILLEGAL L H L H BS,CA,A10 READ/READ Term burst, start read: Determine AP 6.7 L H L L BS,CA,A10 WRIT/WRIT Term burst, start read: Determine AP 6 L L H H BS,RA ACT ILLEGAL 3 L L H L BS,A10 PRE/PREA Term burst. precharging 8 L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL - 13 - 6 3 Publication Release Date: May 2001 Revision 0.0 W942516AH Current State CS RAS CAS WE Read with auto prechange H X X X X DSL Continue burst to end L H H H X NOP Continue burst to end L H H L X BST ILLEGAL L H L H BS,CA,A10 READ/READA ILLEGAL L H L L BS,CA,A10 WRIT/WRITA ILLEGAL 3 L L H H BS,RA ACT ILLEGAL 3 L L H L BS,A10 PRE/PREA ILLEGAL L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL H X X X X DSL Continue burst to end L H H H X NOP Continue burst to end L H H L X BST ILLEGAL L H L H BS,CA,A10 READ/READA ILLEGAL 3 L H L L BS,CA,A10 WRIT/WRITA ILLEGAL 3 L L H H BS,RA ACT ILLEGAL 3 L L H L BS,A10 PRE/PREA ILLEGAL 3 L L L H X AREF/SELF ILLEGAL Write with auto precharge Precharging Row activating Address Command Action Notes 3 L L L L Op-Code MRS/EMRS ILLEGAL H X X X X DSL Nop-> Idle after tRP L H H H X NOP Nop-> Idle after tRP L H H L X BST ILLEGAL L H L H BS,CA,A10 READ/READA ILLEGAL 3 L H L L BS,CA,A10 WRIT/WRITA ILLEGAL 3 L L H H BS,RA ACT ILLEGAL 3 L L H L BS,A10 PRE/PREA ILLEGAL L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL H X X X X DSL Nop-> Row active after tRCD L H H H X NOP Nop-> Row active after tRCD L H H L X BST ILLEGAL L H L H BS,CA,A10 READ/READA ILLEGAL 3 L H L L BS,CA,A10 WRIT/WRITA ILLEGAL 3 L L H H BS,RA ACT ILLEGAL 3 L L H L BS,A10 PRE/PREA ILLEGAL 3 L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL - 14 - W942516AH Address Command Action Notes Current State CS Write H X X X X DSL Nop->dle after tRC recovering L H H H X NOP Nop->Idle after tRC L H H L X BST ILLEGAL L H L H BS,CA,A READ/READA ILLEGAL 3 L H L L BS,CA,A WRIT/WRITA ILLEGAL 3 L L H H BS,RA ACT ILLEGAL 3 L L H L BS,A10 PRE/PREA ILLEGAL 3 L L L H X AREF/SELF ILLEGAL Write recovering with auto precharge Refreshing Mode register accessing RAS CAS WE L L L L Op-Code MRS/EMRS ILLEGAL H X X X X DSL Nop->Enter precharge after tWR L H H H X NOP Nop->Enter precharge after tWR L H H L X BST ILLEGAL L H L H BS,CA,A READ/READA ILLEGAL 3 L H L L BS,CA,A WRIT/WRITA ILLEGAL 3 L L H H BS,RA ACT ILLEGAL 3 L L H L BS,A10 PRE/PREA ILLEGAL 3 L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL H X X X X DSL Nop->Idle after tRC L H H H X NOP Nop->Idle after tRC L H H L X BST ILLEGAL L H L H X READ/WRIT ILLEGAL L L H X X ACT/PRE/PREA ILLEGAL L L L X X AREF/SELF/MRS/EMRS ILLEGAL H X X X X DSL Nop->Row after tMRD L H H H X NOP Nop->Row after tMRD L H H L X BST ILLEGAL L H L X X READ/WRIT ILLEGAL L L X X X ACT/PRE/PREA/AREF/S ILLEGAL Note: 1. All entries assume that CKE was active (High level) during the preceding clock cycle and the current clock cycle. 2. Illegal if any bandk is not idle. 3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BS), depending on the state of that bank. 4. Illegal if tRCD is not satisfied. 5. Illegal if tRAS is not satisfied. 6. Must satisifty burst interrupt condition. 7. Must avoid bus contention, bus turn around, and/or satisfy write recovery requirements. 8. Must mask preceding data which don't satisfy tWR Remark: H = High level, L = Low level, X = High or Low level (Don't care), V=Valid data - 15 - Publication Release Date: May 2001 Revision 0.0 W942516AH Function Truth Table for CKE Current State Self refresh Power Down All banks idle Row Active Any state other than listed above CKE n-1 n CS RAS CAS WE Address Action H X X X X X X INVALID L H H X X X X Exit Self Refresh->Idle after tXSNR L H L H H X X Exit Self Refresh->Idle after tXSNR L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X Maintain Self Refresh H X X X X X X INVALID L H X X X X X Enter Power down->Idle after tIS L L X X X X X Maintain power down mode H H X X X X X Refer to Function Truth Table H L H X X X X Enter Power down 2 H L L H H X X Enter Power down 2 H L L L L H X Self Refresh 1 H L L H L X X ILLEGAL H L L L X X X ILLEGAL L X X X X X X Power down H H X X X X X Refer to Function Truth Table H L H X X X X Enter Power down 2 H L L H H X X Enter Power down 2 H L L L L H X ILLEGAL H L L H L X X ILLEGAL H L L L X X X ILLEGAL L X X X X X X Power down H H X X X X X Refer to Function Truth Table Note: 1. Self refresh can enter only from the all banks idle state. 2. Notes Power down can enter only from bank idle or row active state. Remark: H = High level, L = Low level, X = High or Low level (Don't care), V=Valid data - 16 - 2 W942516AH SIMPLIFIED STATE DIAGRAM SELF REFRESH SREF SREFX MRS/EMRS MODE REGISTER SET AREF IDLE AUTO REFRESH PD PDEX ACT POWER DOWN ACTIVE POWERDOWN PDEX PD ROW ACTIVE Write BST Read Write Read Read Write Read Read A Write A Read A Write A Read A PRE Write A POWER APPLIED POWER ON PRE PRE PRE Read A PRE CHARGE Automatic Sequence Command Sequence - 17 - Publication Release Date: May 2001 Revision 0.0 W942516AH FUNCTIONAL DESCRIPTION 1. Power Up Sequence (1) Apply power and attempt to CKE at a low state( 0.2V) (all other inputs may be undefined) 1) Apply VDD before or at the same time as VDDQ. 2) Apply VDDQ before or at the same time as VTT and VREF. (2) Start Clock and maintain stable condition for 200s(min). (3) After stable power and clock, apply NOP and take CKE high. (4) Issue EMRS (Extended Mode Register Set) to enable DLL and establish Output Driver Type. (5) Issue MRS (Mode Register Set) to reset DLL and set device to idle with bit A8. (an additional 200 cycles(min) of clock are required for DLL Lock) (6) Issue precharge command for all banks of the device. (7) Issue two or more Auto Refresh commands. (8) Issue MRS-Initialize device operation. (If device operation mode is set at sequence 5, sequence 8 can be skipped.) 2. Command Function 2-1 Bank Activate command ( RAS ="L", CAS ="H", WE ="H", BS0, BS1=Bank, A0 to A12=Row Address) The Bank Activate command activates the bank designated by the BS (Bank address) signal. Row addresses are latched on A0 to A12 when this command is issued and the cell data is read out of the sense amplifiers. The maximum time that each bank can be held in the active state is specified as tRAS (max). After this command is issued, Read or Write operation can be executed. 2-2 Bank Precharge command ( RAS ="L", CAS ="H", WE ="L", BS0, BS1=Bank, A10="L", A0 to A9, A11, A12=Don't care) The Bank Precharge command percharges the bank designated by BS. The precharged bank is switched from the active state to the idle state. 2-3 Precharge All command ( RAS ="L", CAS ="H", WE ="L", BS0, BS1=Don't care, A10="H", A0 to A9, A11, A12= Don't care) The Precharge All command precharges all banks simultaneously. Then all banks are switched to the idle state. 2-4 Write command ( RAS ="H", CAS ="L", WE ="L", BS0, BS1=Bank, A10="L", A0 to A9, A11=Column Address) The write command performs a Write operation to the bank designated by BS. The write data are latched at both edges of DQS. The length of the write data (Burst Length) and column access sequence (Addressing Mode) must be in the Mode Register at power-up prior to the Write operation. 2-5 Write with Auto Precharge command - 18 - W942516AH ( RAS ="H", CAS ="L", WE ="L", BS0, BS1=Bank, A10="H", A0 to A9, A11=Column Address) The Write with Auto Precharge command performs the Precharge operation automatically after the Write operation. This command must not be interrupted by any other commands. 2-6 Read command ( RAS ="H", CAS ="L", WE ="H", BS0, BS1=Bank, A10="L", A0 to A9, A11=Column Address) The Read command performs a Read operation to the bank designated by BS. The read data are synchronized with both edges of DQS. The length of read data (Burst Length), Addressing Mode and CAS Latency (access time from CAS command in a clock cycle) must be programmed in the Mode Register at power-up prior to the Read operation. 2-7 Read with Auto Precharge command ( RAS ="H", CAS ="L", WE ="H", BS0, BS1=Bank, A10="H", A0 to A9, A11=Column Address) The Read with Auto precharge command automatically performs the Precharge operation after the Read operation. 1) READA tRAS (min) - (BL/2) x tCK Internal precharge operation begins after BL/2 cycle from Read with Auto Precharge command. 2) tRCD(min) READA < tRAS(min) - (BL/2) x tCK Data can be read with shortest latency, but the internal Precharge operation does not begin until after tRAS (min) has completed. This command must not be interrupted by any other command. 2-8 Mode Register Set command ( RAS ="L", CAS ="L", WE ="L", BS0="L", BS1="L", A0 to A12=Register Data) The Mode Register Set command programs the values of CAS latency, Addressing Mode, Burst Length and DLL reset in the Mode Register. The default values in the Mode Register after powerup are undefined, therefore this command must be issued during the power-up sequence. Also, this command can be issued while all banks are in the idle state. Refer to the table for specific codes. 2-9 Extended Mode Register Set command ( RAS ="L", CAS ="L", WE ="L", BS0="H", BS1="L", A0 to A12=Register data) The Extended Mode Register Set command can be implemented as needed for function extensions to the standard (SDR-SDRAM). Currently the only available mode in EMRS is DLL enable/disable, decoded by A0. The default value of the extended mode register is not defined; therefore this command must be issued during the power-up sequence for enabling DLL. Refer to the table for specific codes. 2-10 No-Operation command ( RAS ="H", CAS ="H", WE ="H") The No-Operation command simply performs no operation (same command as Device Deselect). 2-11 Burst Read stop command - 19 - Publication Release Date: May 2001 Revision 0.0 W942516AH ( RAS ="H", CAS ="H", WE ="L") The Burst stop command is used to stop the burst operation. This command is only valid during a Burst Read operation. 2-12 Device Deselect command ( CS ="H") The Device Deselect command disables the command decoder so that the RAS , CAS , WE and Address inputs are ignored. This command is similar to the No-Operation command. 2-13 Auto Refresh command ( RAS ="L", CAS ="L", WE ="H", CKE="L", BS0, BS1, A0 to A12=Don't care) The Auto Refresh command is used to refresh the row address provided by the internal refresh counter. The Refresh operation must be performed 8192 times within 64ms. The next command can be issued after tREF from the end of the Auto Refresh command. When the Auto Refresh command is used, all banks must be in the idle state. 2-14 Self Refresh Entry command ( RAS ="L", CAS ="L", WE ="H", CKE="L", BS0, BS1, A0 to A12=don't care) The Self Refresh Entry command is used to enter Self Refresh mode. While the device is in Self Refresh mode, all input and output buffer (except the CKE buffer) are disabled and the Refresh operation is automatically performed. Self Refresh mode is exited by taking CKE "high" (the Self Refresh Exit command). During self refresh, DLLl is disable. 2-15 Self Refresh Exit command (CKE="L", CS ="H" or CKE="H", RAS ="H", CAS ="H") This command is used to exit from Self Refresh mode. Any subsequent commands can be issued after tXSNR (tXSRD for Read Command) from the end of this command. 2-16 Data Write Enable /Disable command (DM="L/H" or LDM, UDM="L/H") During a Write cycle, the DM or LDM, UDM signal functions as Data Mask and can control every word of the input data. The LDM signal controls DQ0 to DQ7 and UDM signal controls DQ8 to DQ15. 3. Read Operation Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read command is issued after tRCD from the Bank Activate command, the data is read out sequentially, synchronized with both edges of DQS (Burst Read operation). The initial read data becomes available after CAS latency from the issuing of the Read command. The CAS latency must be set in the Mode Register at power-up. When the Precharge Operation is performed on a bank during a Burst Read and operation, the Burst operation is terminated. When the Read with Auto Precharge command is issued, the Precharge operation is performed automatically after the Read cycle, then the bank is switched to the idle state. This command cannot be interrupted by any other commands. Refer to the diagrams for Read operation. - 20 - W942516AH 4. Write Operation Issuing the Write command after tRCD from the bank activate command. The input data is latched sequentially, synchronizing with both edges(rising &falling) of DQS after the Write command (Burst write operation). The burst length of the Write data (Burst Length) and Addressing Mode must be set in the Mode Register at power-up. When the Precharge operation is performed in a bank during a Burst Write operation, the Burst operation is terminated. When the Write with Auto Precharge command is issued, the Precharge operation is performed automatically after the Write cycle, then the bank is switched to the idle state, The Write with Auto Precharge command cannot be interrupted by any other command for the entire burst data duration. Refer to the diagrams for Write operation. 5. Precharge There are two Commands, which perform the precharge operation (Bank Precharge and Precharge All). When the Bank Precharge command is issued to the active bank, the bank is precharged and then switched to the idle state. The Bank Precharge command can precharge one bank independently of the other bank and hold the unprecharged bank in the active state. The maximum time each bank can be held in the active state is specified as tRAS (max). Therefore, each bank must be precharged within tRAS(max) from the bank activate command. The Precharge All command can be used to precharge all banks simultaneously. Even if banks are not in the active state, the Precharge All command can still be issued. In this case, the Precharge operation is performed only for the active bank and the precharge bank is then switched to the idle state. 6. Burst Termination When the Precharge command is used for a bank in a Burst cycle, the Burst operation is terminated. When Burst Read cycle is interrupted by the Precharge command, read operation is disabled after clock cycle of ( CAS latency) from the Precharge command. When the Burst Write cycle is interrupted by the Precharge command . the input circuit is reset at the same clock cycle at which the precharge command is issued. In this case, the DM signal must be asserted "high: during tWR to prevent writing the invalided data to the cell array. When the Burst Read Stop command is issued for the bank in a Burst Read cycle, the Burst Read operation is terminated. The Burst read Stop command is not supported during a write burst operation. Refer to the diagrams for Burst termination. 7. Refresh Operation Two types of Refresh operation can be performed on the device: Auto Refresh and Self Refresh. By repeating the Auto Refresh cycle, each bank in turn refreshed automatically. The Refresh operation must be performed 8912 times(rows)within 64ms. The period between the Auto Refresh command and the next command is specified by tRFC. Self Refresh mode enter issuing the Self Refresh command (CKE asserted "low"). while all banks are in the idle state. The device is in Self Refresh mode for as long as cke held "low". In the case of 8192 burst Auto Refresh commands, 8192 burst Auto Refresh commands must be performed within 7.8us before entering and after exiting the Self Refresh mode. In the case of distributed Auto Refresh commands, distributed auto refresh commands must be issued every 7.8us and the last distributed - 21 - Publication Release Date: May 2001 Revision 0.0 W942516AH Auto Refresh commands must be performed within 7.8us before entering the self refresh mode. After exiting from the Self Refresh mode, the refresh operation must be performed within 7.8us. In Self Refresh mode, all input/output buffers are disable, resulting in lower power dissipation (except CKE buffer). Refer to the diagrams for Refresh operation. 8. Power Down Mode Two types of Power Down Mode can be performed on the device: Active Standby Power Down Mode and Precharge Standby Power Down Mode. When the device enters the Power Down Mode, all input/output buffers and DLL are disabled resulting in low power dissipation (except CKE buffer). Power Down Mode enter asserting CKE "low" while the device is not running a burst cycle. Taking cke :high" can exit this mode. When CKE goes high, a No operation command must be input at next CLK rising edge. Refer to the diagrams for Power Down Mode. - 22 - W942516AH 9. Mode Register Operation The mode register is programmed by the Mode Register Set command (MRS/EMRS) when all banks are in the idle state. The data to be set in the Mode Register is transferred using the A0 to A12 and BS0, BS1 address inputs. The Mode Register designates the operation mode for the read or write cycle. The register is divided into five filed: (1) Burst Length field to set the length of burst data (2) Addressing Mode selected bit to designate the column access sequence in a Burst cycle (3) CAS Latency field to set the assess time in clock cycle (4) DLL reset field to reset the dll (5) Regular/Extended Mode Register filed to select a type of MRS (Regular/Extended MRS). EMRS cycle can be implemented the extended function (DLL enable/Disable mode) The initial value of the Mode Register (including EMRS) after power up is undefined; therefore the Mode Register Set command must be issued before power operation. (1) Burst Length field (A2 to A0) This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length to be 2, 4, and 8 words. A2 A1 A0 Burst Length 0 0 0 Reserved 0 0 1 2 words 0 1 0 4 words 0 1 1 8 words 1 x x Reserved (2) Addressing Mode Select (A3) The Addressing Mode can be one of two modes; Interleave mode or Sequential Mode, When the A3 bit is "0", Sequential mode is selected. When the A3 bit is "1", Interleave mode is selected. Both addressing Mode support burst length 2, 4, and 8 words. A3 Addressing mode 0 Sequential 0 Interleave - 23 - Publication Release Date: May 2001 Revision 0.0 W942516AH * Address sequence of Sequential mode A column access is performed by incrementing the column address input to the device. The address is varied by the Burst Length as the following. Addressing Sequence of Sequential Mode * DATA ACCESS ADDRESS BURST LENGTH Data 0 n 2 words (address bits is A0) Data 1 n+1 No carried from A0 to A1 Data 2 n+2 4 words (address bit A0, A1) Data 3 n+3 Not carried from A1 to A2 Data 4 n+4 Data 5 n+5 8 words(address bits A2, A1 and A0) Data 6 n+6 Not carried from A2 to A3 Data 7 n+7 Addressing sequence of Interleave mode A Column access is started from the inputted column address and is performed by interleaving the address bits in the sequence shown as the following. Address Sequence for Interleave Mode DATA ACCESS ADDRESS Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 1 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 2 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 3 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 4 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 5 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 6 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 7 A8 A7 A6 A5 A4 A3 A2 A1 A0 - 24 - BURST LENGTH 2 words 4 words 8 words W942516AH (3) CAS Latency field (A6 to A4) This field specifies the number of clock cycles from the assertion of the Read command to the first data read. The minimum values of CAS Latency depends on the frequency of CLK. A6 A5 A4 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CAS Latency Reserved Reserved 2 Reserved Reserved Reserved 2.5 Reserved (4) DLL Reset bit (A8) This bit is used to reset DLL. When the A8 bit is "1", DLL is reset. (5) Mode Register /Extended Mode register change bits (BS0, BS1) These bits are used to select MRS/EMRS. BS1 BS0 A12-A0 0 0 Regular MRS cycle 0 1 Extended MRS cycle 1 x Reserved (6) Extended Mode Register field 1) DLL Switch field (A0) This bit is used to select DLL enable or disable A0 0 1 DLL Enable Disable 2) Output Driver Size Control field (A1) This bit is used to select Output Driver Size, both Full strength and Half strength are based on JEDEC standard. A1 0 1 Output driver Full strength Half strength (7) Reserved field * Test mode entry bit (A7) This bit is used to enter Test mode and must be set to "0" for normal operation. * Reserved bits (A9, A10, A11, A12) These bits are reserved for future operations. They must be set to "0" for normal operation. - 25 - Publication Release Date: May 2001 Revision 0.0 W942516AH PACKAGE DIMENSION 66L TSOP - 400 mil - 26 -