PRELIMINARY W942516AH
4M ×× 4 BANKS ×× 16 BIT DDR SDRAM
Publication Release Date: May 2001
- 1 - Revision .0.0
GENERAL DESCRIPTION
W942516AH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR
SDRAM), organized as 4,194,304 words × 4 banks × 16 bits. Using pipelined architecture and 0.175
µm process technology, W942516AH delivers a data bandwidth of up to 286M words per second (-7).
To fully comply with the personal computer industrial standard, W942516AH is sorted into three speed
grades: -7, -75 and -8. The -7 is compliant to the 143 MHz/CL2.5 or DDR266/CL2 specification, the -
75 is compliant to the DDR266/CL2.5 specification, the -8 is compliant to the DDR200/CL2
specification
All Inputs reference to the positive edge of CLK (except for DQ, DM, and CKE). The timing reference
point for the differential clock is when the CLK and CLK signals cross during a transition. And Write
and Read data are synschronized with the both edges of DQS (Data Strobe).
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W942516AH is ideal for main memory in
high performance applications.
FEATURES
• 2.5V ± 0.2V Power Supply
• Up to 143 MHz Clock Frequency
• Double Data Rate architecture; two data transfers per clock cycle
• Differential clock inputs (CLK and CLK )
• DQS is edge-aligned with data for Read; center-aligned with data for Write
• CAS Latency: 2 and 2.5
• Burst Length: 2, 4, and 8
• Auto Refresh and Self Refresh
• Precharged Power Down and Active Power-Down
• Write Data Mask
• Write Latency = 1
• 8K Refresh cycles / 64 mS
• Interface: SSTL-2
• Packaged: TSOP II 66 pin, 400 x 875mil , 0.65mm pin pitch
KEY PARAMETERS
SYM. DESCRIPTION MIN.
/MAX. -7 -75 -8
tCK Clock Cycle Time CL=2 min. 7.5 nS 8 nS 10 nS
CL=2.5 min. 7 nS 7.5 nS 8 nS
tRAS Active to Precharge Command Period min. 45 nS 45 nS 50 nS
tRC Active to Ref/Active Command Period min. 65 nS 65 nS 70 nS
IDD1 Operation Current (Single bank) max. 110mA 110mA 100mA
IDD4 Burst Operation Current max. 165mA 155mA 150mA
IDD6 Self-Refresh Current max. 3mA 3mA 3mA
W942516AH
- 2 -
PIN CONFIGURATION (TOP VIEW)
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQS
CLK
CKE
A11
A9
A8
A7
A6
A5
A4
VSS
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
BS0
BS1
A10/AP
A0
A1
A2
A3
CS
RAS
CAS
WE
28
29
30
31
32
33
39
38
37
36
35
34VDD
LDM
NC
LDQS
NC
VDD
NC
VSSQ
NC
A12
NC
CLK
UDM
VREF
W942516AH
Publication Release Date: May 2001
- 3 - Revision 0.0
PIN DESCRIPTION
Pin Number Pin Name
Function Description
28−32,35−42 A0 − A12 Address Multiplexed pins for row and column address.
Row address : A0 − A12.
Column address: A0 − A8. (A10 is used for Auto Precharge)
26,27 BS0, BS1 Bank Select
Select bank to activate during row address latch time, or bank to
read/write during column address latch time.
2,4,5,7,8,10,11,
13,54,56,57,59,
60,62,63,65 DQ0 −
DQ15 Data Input/
Output The DQ0 – DQ15 input and output data are synchronized with
both edges of DQS.
51 DQS Data Strobe DQS is Bi-directional signal. DQS is input signal during write
operation and output signal during read operation. It is Edge-
aligned with read data, Center-aligned with write data.
24 CS Chip Select Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and previous
operation continues.
23,22,21 RAS , CAS
,
WE Command Inputs
Command inputs (along with CS ) define the command being
entered.
47 DM Write mask When DM is asserted “high” in burst write, the input data is
masked. DM is synchronized with both edges of DQS.
45,46 CLK, CLK
Differential clock
inputs Clock inputs, all inputs reference to the positive edge of CLK
(except for DQ, DM and CKE).
44 CKE Clock Enable
CKE controls the clock activation and deactivation. When CKE is
l
ow, Power Down mode, Suspend mode, or Self Refresh mode is
entered.
49 VREF Reference
Voltage VREF is reference voltage for inputs buffers.
1,18,33 VDD Power ( +2.5V ) Power for logic circuit inside DDR SDRAM.
34,48,66 VSS Ground Ground for logic circuit inside DDR SDRAM.
3,9,15,55,61 VDDQ Power ( + 2.5V )
for I/O buffer Separated power from VDD, used for output buffer, to improve
noise.
6,12,52,58,64 VSSQ Ground for I/O
buffer Separated ground from VSS, used for output buffer, to improve
noise.
14,17,19,25,43,
50,53 NC No Connection No connection
W942516AH
- 4 -
BLOCK DIAGRAM
LDQS, UDQS
CKE
A10
DLL
CLOCK
BUFFER
COMMAND
DECODER
ADDRESS
BUFFER
REFRESH
COUNTER
COLUMN
COUNTER
CONTROL
SIGNAL
GENERATOR
MODE
REGISTER
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #2
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #0
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #3
DATA CONTROL
CIRCUIT
DQ
BUFFER
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #1
NOTE:
The cell array configuration is 8912 * 512 * 16
ROW DECODER ROW DECODER
ROW DECODERROW DECODER
A0
A9
A11
A12
BA0
BA1
CS
RAS
CAS
WE
CLK
CLK
LDM, UDM
DQ0
DQ15
PREFETCH REGISTER
W942516AH
Publication Release Date: May 2001
- 5 - Revision 0.0
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT NOTES
Input, Output Voltage VIN, VOUT -0.3 ~ VDDQ +0.3 V 1
Power Supply Voltage VDD, VDDQ -0.3 ~ 3.6 V 1
Operating Temperature TOPR 0 ~ 70 °C 1
Storage Temperature TSTG -55 ~ 150 °C 1
Soldering Temperature (10s) TSOLDER 260 °C 1
Power Dissipation PD 1 W 1
Short Circuit Output Current IOUT 50 mA 1
RECOMMENDED DC OPERATING CONDITIONS
(Ta = 0 to 70°C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES
Power Supply Voltage VDD 2.3 2.5 2.7 V 2
Power Supply Voltage (for I/O Buffer) VDDQ 2.3 2.5 VDD V 2
Input reference Voltage VREF 0.49 x VDDQ 0.50 x VDDQ 0.51 x VDDQ V 2,3
Termination Voltage (System) VTT VREF - 0.04 VREF VREF + 0.04 V 2,8
Input High Voltage (DC) VIH (DC) VREF + 0.15 - VDDQ + 0.3 V 2
Input Low Voltage (DC) VIL (DC) -0.3 - VREF - 0.15 V 2
Differential Clock DC Input Voltage VICK (DC) -0.3 - VDDQ + 0.3 V 15
Input Differential Voltage. CLK and
CLK inputs (DC) VID (DC) 0.36 - VDDQ + 0.6 V 13,15
Input High Voltage (AC) VIH (AC) VREF + 0.31 - - V 2
Input Low Voltage (AC) VIL (AC) - - VREF - 0.31 V 2
Input Differential Voltage. CLK and
CLK inputs (AC) VID (AC) 0.7 - VDDQ + 0.6 V 13,15
Differential AC input Cross Point
Voltage VX (AC) VDDQ/2 - 0.2 - VDDQ/2 + 0.2 V 12, 15
Differential Clock AC Middle Point VISO (AC) VDDQ/2 - 0.2 - VDDQ/2 + 0.2 V 14, 15
Note : Undershoot Limit : VIL(min) = -0.9V with a pulse width < 5 nS
Overshoot Limit : VIH(max) = VDDQ+0.9V with a pulse width < 5 nS
VIH(DC) and VIL(DC) are levels to maintain the current logic state.
VIH(AC) and VIL(AC) are levels to change to the new logic state.
W942516AH
- 6 -
CAPACITANCE
(VDD = VDDQ = 2.5V± 0.2V, f = 1 MHz, TA = 25°C, VOUT(DC) = VDDQ/2, VOUT(Peak to Peak) = 0.2V)
PARAMETER SYMBOL MIN. MAX. DELTA
(MAX.) UNIT
Input Capacitance (except for CLK pins) CIN 2.0 3.5 - pF
Input Capacitance (CLK pins) CCLK 2.0 3.5 - pF
DQ, DQS, DM capacitance CI/O 4.0 5.0 0.5 pF
NC pin capacitance CNC - 1.5 - pF
Note: These parameters are periodically sampled and not 100% tested.
W942516AH
Publication Release Date: May 2001
- 7 - Revision 0.0
DC CHARACTERISTICS
Max.
PARAMETER SYM. -7 -75 -8 UNIT NOTES
OPERATING CURRENT : One Bank Active-Precharge; tRC = tRC min;
tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle;
Address and control inputs changing once per clock cycle IDD0 110 110 100 7
OPERATING CURRENT : One Bank Active-Read-Precharge;
Burst=2; tRC = tRC min; CL=2.5; tCK = tCK min; IOUT=0mA; Address and
control inputs changing once per clock cycle. IDD1 110 110 100 7,9
PRECHARGE-POWER-DOWN STANDBY CURRENT : All Banks
Idle; Power down mode; CKE < VIL max; tCK = tCK min; Vin = VREF for
DQ, DQS and DM IDD2P 2 2 2
IDLE FLOATING STANDBY CURRENT : CS > VIH min; All Banks
Idle; CKE > VIH min; Address and other control inputs changing once
per clock cycle; Vin = Vref for DQ, DQS and DM IDD2F 45 40 35 7
IDLE STANDBY CURRENT : CS > VIH min; All Banks Idle; CKE >
VIH min; tCK = tCK min; Address and other control inputs changing once
per clock cycle; Vin > VIH min or Vin < VIL max for DQ, DQS and DM IDD2N 45 40 35 7
IDLE QUIET STANDBY CURRENT : CS > VIH min; All Banks Idle;
CKE > VIH min; tCK = tCK min; Address and other control inputs stable;
Vin > VREF for DQ, DQS and DM IDD2Q 40 35 30 mA 7
ACTIVE POWER-DOWN STANDBY CURRENT : One Bank Active;
Power down mode; CKE < VIL max; tCK = tCK min IDD3P 20 20 20
ACTIVE STANDBY CURRENT : CS > VIH min; CKE > VIH min; One
Bank Active-Precharge; tRC = tRAS max; tCK = tCK min; DQ, DM and
DQS inputs changing twice per clock cycle; Address and other control
inputs changing once per clock cycle
IDD3N 70 65 60 7
OPERATING CURRENT : Burst=2; Reads; Continuous burst; One
Bank Active; Address and control inputs changing once per clock
cycle; CL=2.5; tCK = tCK min; IOUT=0mA IDD4R 165 155 150 7,9
OPERATING CURRENT : Burst=2; Write; Continuous burst; One
Bank Active; Address and control inputs changing once per clock
cycle; CL=2.5; tCK = tCK min; DQ, DM and DQS inputs changing twice
per clock cycle
IDD4W 165 155 150 7
AUTO REFRESH CURRENT : tRC = tRFC min IDD5 190 190 170 7
SELF REFRESH CURRENT : CKE < 0.2V IDD6 3 3 3
RANDOM READ CURRENT : 4 Banks Active Read with activate
every 20ns, Auto-Precharge Read every 20ns; Burst=4; tRCD= 3; IOUT=
0mA; DQ, DM and DQS inputs changing twice per clock cycle;
Address changing once per clock cycle
IDD7 270 270 270
W942516AH
- 8 -
RANDOM READ CURRENT TIMING (IDD7)
CK
CK
DQS
tRCD
tRC
tCK = 10ns
Bank 0
Row d Bank 3
Row c Bank 1
Row e Bank 1
Row e
ADDRESS Bank 0
Row d Bank 2
Row f Bank 3
Row q Bank 2
Col f
ACT READ
AP ACT READ
AP
COMMAND READ
AP ACT ACT READ
AP ACT
DQ Qa Qb Qb Qb Qb Qc Qc Qc Qc Qd Qd Qd Qd Qe QeQa
Bank 0
Row h
LEAKAGE AND OUTPUT BUFFER STRENGTH
PARAMETER SYMBOL MIN. MAX. UNITS NOTES
Input leakage current
(0V < VIN < VDDQ All other pins not under test = 0V) II(L) -2 2 uA
Output leakage current
(Output disabled, 0V < VOUT < VDDQ ) IO(L) -5 5 uA
Output High voltage
(under AC test load condition) VOH VTT + 0.76 - V
Output Low voltage
(under AC test load condition) VOL - VTT - 0.76 V
Output minimum source DC current IOH (DC) -15.2 - mA 4,6
Output minimum sink DC current
Full Strength
IOL (DC) 15.2 - mA 4,6
Output minimum source DC current IOH (DC) -10.4 - mA 5
Output minimum sink DC current Half Strength IOL (DC) 10.4 - mA 5
W942516AH
Publication Release Date: May 2001
- 9 - Revision 0.0
AC CHARACTERISTICS AND OPERATING CONDITIONS (NOTES: 10, 12)
SYMBOL PARAMETER -7 -75 -8 UNITS NOTES
MIN. MAX. MIN. MAX. MIN. MAX.
tRC Active to Ref/Active Command Period 65 65 70
tRFC Ref to Ref/Active Command Period 75 75 80
tRAS Active to Precharge Command Period 45 100000
45 100000
50 100000
tRCD Active to Read/Write Command Delay Time 15 15 20
tRAP Active to Read with Auto Precharge enable 15 15 20
ns
tCCD Read/Write(a) to Read/Write(b) Command Period 1 1 1 tCK
tRP Precharge to Active Command Period 20 20 20
tRRD Active(a) to Active(b) Command Period 15 15 15
tWR Write Recovery time 15 15 15
tDAL Auto Precharge Write Recovery + Precharge time 30 30 35
CL=2 7.5 15 8 15 10 15
tCK CLK Cycle Time
CL=2.5 7 15 7.5 15 8 15
tAC Data Access time from CLK, CLK -0.75 0.75 -0.75 0.75 -0.8 0.8
tDQSCK DQS output access time from CLK, CLK -0.75 0.75 -0.75 0.75 -0.8 0.8
16
tDQSQ Data Strobe Edge to Output Data Edge Skew 0.5 0.5 0.6
ns
tCH CLk Hight level width 0.45 0.55 0.45 0.55 0.45 0.55
tCL CLK Low level width 0.45 0.55 0.45 0.55 0.45 0.55 tCK 11
tHP CLK half period (minmum of actual tCH, tCL) min
(tCL,tCH)
min
(tCL,tCH)
min
(tCL,tCH)
tQH DQ output data hold time from DQS tHP
-0.75 tHP
-0.75 tHP-1.0
ns
tRPRE DQS Read Preamble Time 0.9 1.1 0.9 1.1 0.9 1.1
tRPST DQS Read Postamble Time 0.4 0.6 0.4 0.6 0.4 0.6 tCK 11
tDS DQ and DM Setup Time 0.5 0.5 0.6
tDH DQ and DM Hold Time 0.5 0.5 0.6
tDIPW DQ and DM input pulse width (for each input) 1.75 1.75 2
ns
tDQSH DQS input high pulse width 0.35 0.35 0.35
tDQSL DQS input low pulse width 0.35 0.35 0.35
tDSS DQS falling edge to CLK setup time 0.2 0.2 0.2
tDSH DQS falling edge hold time from CLK 0.2 0.2 0.2
tCK
11
tWPRES Clock to DQS Write Preamble Set-up Time 0 0 0 ns
tWPRE DQS Write Preamble Time 0.25 0.25 0.25
tWPST DQS Write Postamble Time 0.4 0.4 0.4
tDQSS Write command to first DQS latching transition 0.75 1.25 0.75 1.25 0.75 1.25
11
tDSSK UDQS – LDQS Skew (x16) -0.25 0.25 -0.25 0.25 -0.25 0.25
tCK
tIS Input Setup Time 0.9 0.9 1.2
tIH Input Hold Time 0.9 0.9 1.2
tIPW Control & Address input pulse width (for each input) 2.2 2.2 2.5
tHZ Data-out High-impedance Time from CLK, CLK -0.75 0.75 -0.75 0.75 -0.8 0.8
tLZ Data-out Low-impedance Time from CLK, CLK -0.75 0.75 -0.75 0.75 -0.8 0.8
tT(SS) SSTL Input Transition 0.5 1.5 0.5 1.5 0.5 1.5
ns
tWTR Internal Write to Read command delay 1 1 1 tCK
tXSNR Exit Self Refresh to non-Read command 75 75 80 ns
tXSRD Exit Self Refresh to Read command 10 10 10 tCK
tREF Refresh Time (8K) 64 64 64 ms
tMRD Mode Register Set cycle time 15 15 16 ns
W942516AH
- 10 -
AC TEST CONDITIONS
SYMBOL PARAMETER VALUE UNIT NOTE
VIH Input High voltage (AC) VREF+0.31 V
VIL Input Low voltage (AC) VREF-0.31 V
VREF Input reference voltage 0.5xVDDQ V
VTT Termination voltage 0.5xVDDQ V
VSWING Input signal peak to peak swing 1.0 V
Vr Differential Clock Input Reference Voltage Vx(AC) V
VID(AC) Input Difference Voltage. CLK and CLK inputs (AC) 1.5 V
SLEW Input signal minmum slew rate 1.0 V/ns
VOTR Output timing measurement refernece voltage 0.5xVDDQ V
CLK
Vss
V
DDQ
VREF
V
ILmax
(AC)
V
IHmin
(AC)
V
SWING
(max)
SLEW=V
IHmin(AC)
-V
ILmax(AC)
/ ∆t
∆t∆t
R
T
=
50 ohms
VTT
A.C TEST LOAD
Rs = 50 ohms 30pF
W942516AH
Publication Release Date: May 2001
- 11 - Revision 0.0
Note:
(1) Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage
to the device.
(2) All voltages are referenced to VSS, VSSQ.
(3) Peak to peak AC noise on VREF may not exceed ±2% of VREF(DC).
(4) VOH=1.95V,VOL=0.35V
(5) VOH=1.9V,VOL=0.4V
(6) The values of IOH(DC) is based on VDDQ=2.3V and VTT=1.19V.
The values of IOL(DC) is based on VDDQ=2.3V and VTT=1.11V.
(7) These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimun values of
tCK and tRC.
(8) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set
equal to VREF and must track variations in the DC level of VREF.
(9) These parameters depend on the output loading.Specified values are obtained with the output open.
(10) Transition times are measured between VIH min(AC) and VIL max(AC).Transition (rise and fall) of input signals have a fixed
slope.
(11) If the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to
the nearest decimal place.
(i.e., tDQSS=0.75×tCK, tCK=7.5ns, 0.75 × 7.5ns = 5.625ns is rounded up to 5.6ns.)
(12) VX is the differential clock cross point voltage where input timing measurement is referenced.
(13) VID is magnitude of the difference between CLK input level and CLK input level.
(14) VISO means {VICK(CLK) + VICK(CLK )}/2.
(15) Refer to the figure below.
CLK
CLK
VSS
VICK
VXVXVXVX
VX
VICK
VICK VICK VID(AC)
VID(AC)
0 V Differential
VISO
VISO(min) VISO(max)
VSS
(16) tAC and tDQSCK depend on the clock jitter. These timing are measured at stable clock.
W942516AH
- 12 -
OPERATION MODE
The following table shows the operation commands.
Simplified Truth Table (Note (1) and (2))
Symbol
Command
Device State
CKEn-
1
CKEn
DM(4)
BS0,
BS1
A10
A12,
A11,
A9-A0
CS
RAS
CAS
WE
ACT
Idle
(3)
H
X
X
V
V
V
L
L
H
H
PRE
Any
(3)
H
X
X
V
L
X
L
L
H
L
PREA
Any
H
X
X
X
H
X
L
L
H
L
WRIT
Active
(3)
H
X
X
V
L
V
L
H
L
L
WRITA
Active
(3)
H
X
X
V
H
V
L
H
L
L
READ
Active
(3)
H
X
X
V
L
V
L
H
L
H
READA
Active
(3)
H
X
X
V
H
V
L
H
L
H
MRS
Idle
H
X
X
L,L
C
C
L
L
L
L
EMRS
Idle
H
X
X
H,L
V
V
L
L
L
L
NOP
Any
H
X
X
X
X
X
L
H
H
H
BST
Active
H
X
X
X
X
X
L
H
H
L
DSL
Any
H
X
X
X
X
X
H
X
X
X
AREF
Idle
H
H
X
X
X
X
L
L
L
H
SELF
Idle
H
L
X
X
X
X
L
L
L
H
H
X
X
X
SELEX Self Refresh Exit Idle (Self
Refresh) L H X X X X L H H X
H
X
X
X
PD Power down mode
entry Idle/Active(5) H L X X X X
L
H
H
X
H
X
X
X
PDEX Power down mode
exit Any (Power
Down) L H X X X X
L
H
H
X
WDE
Active
H
X
L
X
X
X
X
X
X
X
WDD
Active
H
X
H
X
X
X
X
X
X
X
Note:1. V=Valid X=Don’t Care L=Low level H=High level
2. CKEn signal is input levell when commands are issued.
CKEn-1 signal is input level one clock cycle before the commands are issued.
3. These are state designated by the BS0,BS1 signals.
4. LDM, UDM (W942516AH)
5. Power Down Mode can not entry in the burst cycle.
W942516AH
Publication Release Date: May 2001
- 13 - Revision 0.0
Function Truth Table(Note 1)
Current State CS
RAS
CAS
WE
Address Command Action Notes
H
X
X
X
X
DSL
Nop
L
H
H
X
X
NOP/BST
Nop
L
H
L
H
BS,CA,A10
READ/READ
ILLEGAL
3
L
H
L
L
BS,CA,A10
WRIT/WRIT
ILLEGAL
3
L
L
H
H
BS,RA
ACT
Row activating
L
L
H
L
BS,A10
PRE/PREA
Nop
L
L
L
H
X
AREF/SELF
Refresh or Self refresh
2
Idle
L
L
L
L
Op-Code
MRS/EMRS
Mode register accessing
2
H X X X X DSL Nop
L
H
H
X
X
NOP/BST
Nop
L
H
L
H
BS,CA,A10
READ/READ
Begin read: Determine AP
4
L
H
L
L
BS,CA,A10
WRIT/WRIT
Begin write: Determine AP
4
L
L
H
H
BS,RA
ACT
ILLEGAL
3
L
L
H
L
BS,A10
PRE/PREA
Precharge
5
L
L
L
H
X
AREF/SELF
ILLEGAL
Row active
L
L
L
L
Op-Code
MRS/EMRS
ILLEGAL
H X X X X DSL Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
Burst stop
L
H
L
H
BS,CA,A10
READ/READ
Term burst, new read: Determine AP
6
L
H
L
L
BS,CA,A10
WRIT/WRIT
ILLEGAL
L
L
H
H
BS,RA
ACT
ILLEGAL
3
L
L
H
L
BS,A10
PRE/PREA
Term burst, precharging
L
L
L
H
X
AREF/SELF
ILLEGAL
Read
L
L
L
L
Op-Code
MRS/EMRS
ILLEGAL
H X X X X DSL Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BS,CA,A10
READ/READ
Term burst, start read: Determine AP
6.7
L
H
L
L
BS,CA,A10
WRIT/WRIT
Term burst, start read: Determine AP
6
L
L
H
H
BS,RA
ACT
ILLEGAL
3
L
L
H
L
BS,A10
PRE/PREA
Term burst. precharging
8
L
L
L
H
X
AREF/SELF
ILLEGAL
Write
L
L
L
L
Op-Code
MRS/EMRS
ILLEGAL
W942516AH
- 14 -
Current State CS RAS
CAS WE Address Command Action Notes
H
X
X
X
X
DSL
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
ILLEGAL
3
L
H
L
H
BS,CA,A10
READ/READA
ILLEGAL
L
H
L
L
BS,CA,A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BS,RA
ACT
ILLEGAL
3
L
L
H
L
BS,A10
PRE/PREA
ILLEGAL
L
L
L
H
X
AREF/SELF
ILLEGAL
Read with auto
prechange
L
L
L
L
Op-Code
MRS/EMRS
ILLEGAL
H
X
X
X
X
DSL
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BS,CA,A10
READ/READA
ILLEGAL
3
L
H
L
L
BS,CA,A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BS,RA
ACT
ILLEGAL
3
L
L
H
L
BS,A10
PRE/PREA
ILLEGAL
3
L
L
L
H
X
AREF/SELF
ILLEGAL
Write with auto
precharge
L
L
L
L
Op-Code
MRS/EMRS
ILLEGAL
H X X X X DSL Nop-> Idle after tRP
L
H
H
H
X
NOP
Nop-> Idle after t
RP
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BS,CA,A10
READ/READA
ILLEGAL
3
L
H
L
L
BS,CA,A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BS,RA
ACT
ILLEGAL
3
L
L
H
L
BS,A10
PRE/PREA
ILLEGAL
L
L
L
H
X
AREF/SELF
ILLEGAL
Precharging
L
L
L
L
Op-Code
MRS/EMRS
ILLEGAL
H
X
X
X
X
DSL
Nop-> Row active after t
RCD
L
H
H
H
X
NOP
Nop-> Row active after t
RCD
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BS,CA,A10
READ/READA
ILLEGAL
3
L
H
L
L
BS,CA,A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BS,RA
ACT
ILLEGAL
3
L
L
H
L
BS,A10
PRE/PREA
ILLEGAL
3
L
L
L
H
X
AREF/SELF
ILLEGAL
Row activating
L
L
L
L
Op-Code
MRS/EMRS
ILLEGAL
W942516AH
Publication Release Date: May 2001
- 15 - Revision 0.0
Current State CS
RAS
CAS
WE
Address Command Action Notes
H X X X X DSL Nop->dle after tRC
L
H
H
H
X
NOP
Nop->Idle after t
RC
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BS,CA,A
READ/READA
ILLEGAL
3
L
H
L
L
BS,CA,A
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BS,RA
ACT
ILLEGAL
3
L
L
H
L
BS,A10
PRE/PREA
ILLEGAL
3
L
L
L
H
X
AREF/SELF
ILLEGAL
Write
recovering
L
L
L
L
Op-Code
MRS/EMRS
ILLEGAL
H X X X X DSL Nop->Enter precharge after tWR
L
H
H
H
X
NOP
Nop->Enter precharge after t
WR
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BS,CA,A
READ/READA
ILLEGAL
3
L
H
L
L
BS,CA,A
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BS,RA
ACT
ILLEGAL
3
L
L
H
L
BS,A10
PRE/PREA
ILLEGAL
3
L
L
L
H
X
AREF/SELF
ILLEGAL
Write
recovering
with auto
precharge
L
L
L
L
Op-Code
MRS/EMRS
ILLEGAL
H X X X X DSL Nop->Idle after tRC
L
H
H
H
X
NOP
Nop->Idle after t
RC
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
X
READ/WRIT
ILLEGAL
L
L
H
X
X
ACT/PRE/PREA
ILLEGAL
Refreshing
L
L
L
X
X
AREF/SELF/MRS/EMRS
ILLEGAL
H X X X X DSL Nop->Row after tMRD
L
H
H
H
X
NOP
Nop->Row after t
MRD
L
H
H
L
X
BST
ILLEGAL
L
H
L
X
X
READ/WRIT
ILLEGAL
Mode
register
accessing
L
L
X
X
X
ACT/PRE/PREA/AREF/S
ILLEGAL
Note: 1. All entries assume that CKE was active (High level) during the preceding clock cycle and the current clock cycle.
2. Illegal if any bandk is not idle.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BS), depending on
the state of that bank.
4. Illegal if tRCD is not satisfied.
5. Illegal if tRAS is not satisfied.
6. Must satisifty burst interrupt condition.
7. Must avoid bus contention, bus turn around, and/or satisfy write recovery requirements.
8. Must mask preceding data which don’t satisfy tWR
Remark: H = High level, L = Low level, X = High or Low level (Don’t care), V=Valid data
W942516AH
- 16 -
Function Truth Table for CKE
CKE
Current State
n-1
n
CS
RAS
CAS
WE
Address Action Notes
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit Self Refresh->Idle after t
XSNR
L
H
L
H
H
X
X
Exit Self Refresh->Idle after t
XSNR
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
Self refresh
L
L
X
X
X
X
X
Maintain Self Refresh
H X X X X X X INVALID
L
H
X
X
X
X
X
Enter Power down->Idle after t
IS
Power Down
L
L
X
X
X
X
X
Maintain power down mode
H H X X X X X Refer to Function Truth Table
H
L
H
X
X
X
X
Enter Power down
2
H
L
L
H
H
X
X
Enter Power down
2
H
L
L
L
L
H
X
Self Refresh
1
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
All banks idle
L
X
X
X
X
X
X
Power down
2
H H X X X X X Refer to Function Truth Table
H
L
H
X
X
X
X
Enter Power down
2
H
L
L
H
H
X
X
Enter Power down
2
H
L
L
L
L
H
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
Row Active
L
X
X
X
X
X
X
Power down
Any state other
than listed
above
H H X X X X X Refer to Function Truth Table
Note: 1. Self refresh can enter only from the all banks idle state.
2. Power down can enter only from bank idle or row active state.
Remark: H = High level, L = Low level, X = High or Low level (Don’t care), V=Valid data
W942516AH
Publication Release Date: May 2001
- 17 - Revision 0.0
SIMPLIFIED STATE DIAGRAM
POWER
APPLIED
Automatic Sequence
Command Sequence
Read A
Write Read
ROW
ACTIVE
POWER
DOWN
IDLE
MODE
REGISTER
SET
AUTO
REFRESH
SELF
REFRESH
Read
Read A
Write
Write A
PRE
CHARGE
POWER
ON
MRS/EMRS AREF
SREF
SREFX
PD
PDEX
ACT
BST
Read
Write
Write A Write A Read A
PRE
PRE
PRE
PRE
ACTIVE
POWERDOWN
PD
PDEX
Read
Read A
W942516AH
- 18 -
FUNCTIONAL DESCRIPTION
1. Power Up Sequence
(1) Apply power and attempt to CKE at a low state(
≤
0.2V)
(all other inputs may be undefined)
1) Apply VDD before or at the same time as VDDQ.
2) Apply VDDQ before or at the same time as VTT and VREF.
(2) Start Clock and maintain stable condition for 200µs(min).
(3) After stable power and clock, apply NOP and take CKE high.
(4) Issue EMRS (Extended Mode Register Set) to enable DLL and establish Output Driver Type.
(5) Issue MRS (Mode Register Set) to reset DLL and set device to idle with bit A8.
(an additional 200 cycles(min) of clock are required for DLL Lock)
(6) Issue precharge command for all banks of the device.
(7) Issue two or more Auto Refresh commands.
(8) Issue MRS-Initialize device operation.
(If device operation mode is set at sequence 5, sequence 8 can be skipped.)
2. Command Function
2-1 Bank Activate command
(RAS =”L”, CAS=”H”,
WE
=”H”, BS0, BS1=Bank, A0 to A12=Row Address)
The Bank Activate command activates the bank designated by the BS (Bank address) signal.
Row addresses are latched on A0 to A12 when this command is issued and the cell data is read
out of the sense amplifiers. The maximum time that each bank can be held in the active state is
specified as tRAS (max). After this command is issued, Read or Write operation can be executed.
2-2 Bank Precharge command
(RAS =”L”, CAS=”H”,
WE
=”L”, BS0, BS1=Bank, A10=”L”, A0 to A9, A11, A12=Don’t care)
The Bank Precharge command percharges the bank designated by BS. The precharged bank is
switched from the active state to the idle state.
2-3 Precharge All command
(RAS =”L”, CAS =”H”,
WE
=”L”, BS0, BS1=Don’t care, A10=”H”, A0 to A9, A11, A12= Don’t
care)
The Precharge All command precharges all banks simultaneously. Then all banks are switched to
the idle state.
2-4 Write command
(RAS =”H”, CAS=”L”,
WE
=”L”, BS0, BS1=Bank, A10=”L”, A0 to A9, A11=Column Address)
The write command performs a Write operation to the bank designated by BS. The write data are
latched at both edges of DQS. The length of the write data (Burst Length) and column access
sequence (Addressing Mode) must be in the Mode Register at power-up prior to the Write
operation.
2-5 Write with Auto Precharge command
W942516AH
Publication Release Date: May 2001
- 19 - Revision 0.0
(RAS =”H”, CAS=”L”,
WE
=”L”, BS0, BS1=Bank, A10=”H”, A0 to A9, A11=Column Address)
The Write with Auto Precharge command performs the Precharge operation automatically after
the Write operation. This command must not be interrupted by any other commands.
2-6 Read command
(RAS =”H”, CAS=”L”,
WE
=”H”, BS0, BS1=Bank, A10=”L”, A0 to A9, A11=Column Address)
The Read command performs a Read operation to the bank designated by BS. The read data are
synchronized with both edges of DQS. The length of read data (Burst Length), Addressing Mode
and CASLatency (access time from CAS command in a clock cycle) must be programmed in
the Mode Register at power-up prior to the Read operation.
2-7 Read with Auto Precharge command
(RAS =”H”, CAS=”L”,
WE
=”H”, BS0, BS1=Bank, A10=”H”, A0 to A9, A11=Column Address)
The Read with Auto precharge command automatically performs the Precharge operation after
the Read operation.
1) READA
≥
tRAS (min) - (BL/2) x tCK
Internal precharge operation begins after BL/2 cycle from Read with Auto Precharge
command.
2) tRCD(min)
≤
READA < tRAS(min) - (BL/2) x tCK
Data can be read with shortest latency, but the internal Precharge operation does not begin
until after tRAS (min) has completed.
This command must not be interrupted by any other command.
2-8 Mode Register Set command
(RAS =”L”, CAS=”L”,
WE
=”L”, BS0=”L”, BS1=”L”, A0 to A12=Register Data)
The Mode Register Set command programs the values of CAS latency, Addressing Mode, Burst
Length and DLL reset in the Mode Register. The default values in the Mode Register after power-
up are undefined, therefore this command must be issued during the power-up sequence. Also,
this command can be issued while all banks are in the idle state. Refer to the table for specific
codes.
2-9 Extended Mode Register Set command
(RAS =”L”, CAS=”L”,
WE
=”L”, BS0=”H”, BS1=”L”, A0 to A12=Register data)
The Extended Mode Register Set command can be implemented as needed for function
extensions to the standard (SDR-SDRAM). Currently the only available mode in EMRS is DLL
enable/disable, decoded by A0. The default value of the extended mode register is not defined;
therefore this command must be issued during the power-up sequence for enabling DLL. Refer to
the table for specific codes.
2-10 No-Operation command
(RAS =”H”, CAS=”H”,
WE
=”H”)
The No-Operation command simply performs no operation (same command as Device Deselect).
2-11 Burst Read stop command
W942516AH
- 20 -
(RAS =”H”, CAS=”H”,
WE
=”L”)
The Burst stop command is used to stop the burst operation. This command is only valid during a
Burst Read operation.
2-12 Device Deselect command
(CS=”H”)
The Device Deselect command disables the command decoder so that the RAS ,CAS,
WE
and
Address inputs are ignored. This command is similar to the No-Operation command.
2-13 Auto Refresh command
(RAS =”L”, CAS=”L”,
WE
=”H”, CKE=”L”, BS0, BS1, A0 to A12=Don’t care)
The Auto Refresh command is used to refresh the row address provided by the internal refresh
counter. The Refresh operation must be performed 8192 times within 64ms. The next command
can be issued after tREF from the end of the Auto Refresh command. When the Auto Refresh
command is used, all banks must be in the idle state.
2-14 Self Refresh Entry command
(RAS =”L”, CAS=”L”,
WE
=”H”, CKE=”L”, BS0, BS1, A0 to A12=don’t care)
The Self Refresh Entry command is used to enter Self Refresh mode. While the device is in Self
Refresh mode, all input and output buffer (except the CKE buffer) are disabled and the Refresh
operation is automatically performed. Self Refresh mode is exited by taking CKE “high” (the Self
Refresh Exit command). During self refresh, DLLl is disable.
2-15 Self Refresh Exit command
(CKE=”L”, CS=”H” or CKE=”H”, RAS =”H”, CAS=”H”)
This command is used to exit from Self Refresh mode. Any subsequent commands can be issued
after tXSNR (tXSRD for Read Command) from the end of this command.
2-16 Data Write Enable /Disable command
(DM=”L/H” or LDM, UDM=”L/H”)
During a Write cycle, the DM or LDM, UDM signal functions as Data Mask and can control every
word of the input data. The LDM signal controls DQ0 to DQ7 and UDM signal controls DQ8 to
DQ15.
3. Read Operation
Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read
command is issued after tRCD from the Bank Activate command, the data is read out sequentially,
synchronized with both edges of DQS (Burst Read operation). The initial read data becomes available
after CAS latency from the issuing of the Read command. TheCASlatency must be set in the Mode
Register at power-up.
When the Precharge Operation is performed on a bank during a Burst Read and operation, the
Burst operation is terminated.
When the Read with Auto Precharge command is issued, the Precharge operation is performed
automatically after the Read cycle, then the bank is switched to the idle state. This command cannot
be interrupted by any other commands. Refer to the diagrams for Read operation.
W942516AH
Publication Release Date: May 2001
- 21 - Revision 0.0
4. Write Operation
Issuing the Write command after tRCD from the bank activate command. The input data is latched
sequentially, synchronizing with both edges(rising &falling) of DQS after the Write command (Burst
write operation). The burst length of the Write data (Burst Length) and Addressing Mode must be set
in the Mode Register at power-up.
When the Precharge operation is performed in a bank during a Burst Write operation, the Burst
operation is terminated.
When the Write with Auto Precharge command is issued, the Precharge operation is performed
automatically after the Write cycle, then the bank is switched to the idle state, The Write with Auto
Precharge command cannot be interrupted by any other command for the entire burst data duration.
Refer to the diagrams for Write operation.
5. Precharge
There are two Commands, which perform the precharge operation (Bank Precharge and Precharge
All). When the Bank Precharge command is issued to the active bank, the bank is precharged and
then switched to the idle state. The Bank Precharge command can precharge one bank independently
of the other bank and hold the unprecharged bank in the active state. The maximum time each bank
can be held in the active state is specified as tRAS (max). Therefore, each bank must be precharged
within tRAS(max) from the bank activate command.
The Precharge All command can be used to precharge all banks simultaneously. Even if banks are
not in the active state, the Precharge All command can still be issued. In this case, the Precharge
operation is performed only for the active bank and the precharge bank is then switched to the idle
state.
6. Burst Termination
When the Precharge command is used for a bank in a Burst cycle, the Burst operation is
terminated. When Burst Read cycle is interrupted by the Precharge command, read operation is
disabled after clock cycle of (CAS latency) from the Precharge command. When the Burst Write cycle
is interrupted by the Precharge command . the input circuit is reset at the same clock cycle at which
the precharge command is issued. In this case, the DM signal must be asserted “high: during tWR to
prevent writing the invalided data to the cell array.
When the Burst Read Stop command is issued for the bank in a Burst Read cycle, the Burst Read
operation is terminated. The Burst read Stop command is not supported during a write burst operation.
Refer to the diagrams for Burst termination.
7. Refresh Operation
Two types of Refresh operation can be performed on the device: Auto Refresh and Self Refresh. By
repeating the Auto Refresh cycle, each bank in turn refreshed automatically. The Refresh operation
must be performed 8912 times(rows)within 64ms. The period between the Auto Refresh command
and the next command is specified by tRFC.
Self Refresh mode enter issuing the Self Refresh command (CKE asserted “low”). while all banks
are in the idle state. The device is in Self Refresh mode for as long as cke held “low”. In the case of
8192 burst Auto Refresh commands, 8192 burst Auto Refresh commands must be performed within
7.8us before entering and after exiting the Self Refresh mode. In the case of distributed Auto Refresh
commands, distributed auto refresh commands must be issued every 7.8us and the last distributed
W942516AH
- 22 -
Auto Refresh commands must be performed within 7.8us before entering the self refresh mode. After
exiting from the Self Refresh mode, the refresh operation must be performed within 7.8us. In Self
Refresh mode, all input/output buffers are disable, resulting in lower power dissipation (except CKE
buffer). Refer to the diagrams for Refresh operation.
8. Power Down Mode
Two types of Power Down Mode can be performed on the device: Active Standby Power Down
Mode and Precharge Standby Power Down Mode.
When the device enters the Power Down Mode, all input/output buffers and DLL are disabled
resulting in low power dissipation (except CKE buffer).
Power Down Mode enter asserting CKE “low” while the device is not running a burst cycle. Taking
cke :high” can exit this mode. When CKE goes high, a No operation command must be input at next
CLK rising edge. Refer to the diagrams for Power Down Mode.
W942516AH
Publication Release Date: May 2001
- 23 - Revision 0.0
9. Mode Register Operation
The mode register is programmed by the Mode Register Set command (MRS/EMRS) when all
banks are in the idle state. The data to be set in the Mode Register is transferred using the A0 to A12
and BS0, BS1 address inputs.
The Mode Register designates the operation mode for the read or write cycle. The register is
divided into five filed: (1) Burst Length field to set the length of burst data (2) Addressing Mode
selected bit to designate the column access sequence in a Burst cycle (3) CAS Latency field to set
the assess time in clock cycle (4) DLL reset field to reset the dll (5) Regular/Extended Mode Register
filed to select a type of MRS (Regular/Extended MRS). EMRS cycle can be implemented the extended
function (DLL enable/Disable mode)
The initial value of the Mode Register (including EMRS) after power up is undefined; therefore the
Mode Register Set command must be issued before power operation.
(1) Burst Length field (A2 to A0)
This field specifies the data length for column access using the A2 to A0 pins and sets the Burst
Length to be 2, 4, and 8 words.
A2 A1 A0 Burst Length
0 0 0 Reserved
0 0 1 2 words
0 1 0 4 words
0 1 1 8 words
1 x x Reserved
(2) Addressing Mode Select (A3)
The Addressing Mode can be one of two modes; Interleave mode or Sequential Mode, When
the A3 bit is “0”, Sequential mode is selected. When the A3 bit is “1”, Interleave mode is
selected. Both addressing Mode support burst length 2, 4, and 8 words.
A3 Addressing mode
0 Sequential
0 Interleave
W942516AH
- 24 -
• Address sequence of Sequential mode
A column access is performed by incrementing the column address input to the device. The
address is varied by the Burst Length as the following.
Addressing Sequence of Sequential Mode
DATA ACCESS ADDRESS BURST LENGTH
Data 0 n 2 words (address bits is A0)
Data 1 n + 1 No carried from A0 to A1
Data 2 n + 2 4 words (address bit A0, A1)
Data 3 n + 3 Not carried from A1 to A2
Data 4 n + 4
Data 5 n + 5 8 words(address bits A2, A1 and A0)
Data 6 n + 6 Not carried from A2 to A3
Data 7 n + 7
• Addressing sequence of Interleave mode
A Column access is started from the inputted column address and is performed by
interleaving the address bits in the sequence shown as the following.
Address Sequence for Interleave Mode
DATA ACCESS ADDRESS BURST LENGTH
Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 2 words
Data 1 A8 A7 A6 A5 A4 A3 A2 A1
A0
Data 2 A8 A7 A6 A5 A4 A3 A2
A1
A0 4 words
Data 3 A8 A7 A6 A5 A4 A3 A2
A1
A0
Data 4 A8 A7 A6 A5 A4 A3
A2
A1 A0 8 words
Data 5 A8 A7 A6 A5 A4 A3
A2
A1
A0
Data 6 A8 A7 A6 A5 A4 A3
A2
A1
A0
Data 7 A8 A7 A6 A5 A4 A3
A2
A1
A0
W942516AH
Publication Release Date: May 2001
- 25 - Revision 0.0
(3) CASLatency field (A6 to A4)
This field specifies the number of clock cycles from the assertion of the Read command to the
first data read. The minimum values of CAS Latency depends on the frequency of CLK.
A6 A5 A4 CAS Latency
0 0 0 Reserved
0 0 1 Reserved
0 1 0 2
0 1 1 Reserved
1 0 0 Reserved
1 0 1 Reserved
1 1 0 2.5
1 1 1 Reserved
(4) DLL Reset bit (A8)
This bit is used to reset DLL. When the A8 bit is “1”, DLL is reset.
(5) Mode Register /Extended Mode register change bits (BS0, BS1)
These bits are used to select MRS/EMRS.
BS1
BS0
A12-A0
0 0 Regular MRS cycle
0 1 Extended MRS cycle
1 x Reserved
(6) Extended Mode Register field
1) DLL Switch field (A0)
This bit is used to select DLL enable or disable
A0 DLL
0 Enable
1 Disable
2) Output Driver Size Control field (A1)
This bit is used to select Output Driver Size, both Full strength and Half strength are based on
JEDEC standard. A1 Output driver
0 Full strength
1 Half strength
(7) Reserved field
• Test mode entry bit (A7)
This bit is used to enter Test mode and must be set to “0” for normal operation.
• Reserved bits (A9, A10, A11, A12)
These bits are reserved for future operations. They must be set to “0” for normal operation.
W942516AH
- 26 -
PACKAGE DIMENSION
66L TSOP - 400 mil