NEC pPD7 1082, 71083 NEC Electronics Inc. 8-Bit Latches Description Pin Configurations pPDT1082 and pPDT1083 are CMOS 6-bit transparent latches with three-state output buffers. Thay are used as 20-Pin Plastic DIP bus buffers or bus multiplexers in microprocessor sys- tems. Their high-drive capability makes them suitable for one q 1 \ 20 ; yan oc 1 z 13 data latch, buffer, or |/O port applications. ocd i ee Feat Bis 4 17 O Dow DOs ures Dig ] 5 18 9 Dow Bt Dis Ce z 15 DO Dow DO, Oo CMOS technology Big C7 = 14 OF Dog By O 86-bit parallel data register Dh Cs 13 1) Dog De CEOs 12 DF Dow BG; O Three-state output butfer ves G0 a hen 0 High drive capability output buffer (lo, = 12 mA) snore O pPDSO85A, 8048, 8086, 8088, pPD70108/116, anc pPD70208/216 system compatible 20-Pin Plastic SOP G pPD7T082 non-inverted output; pPD71083 inverted output De OF 1 20 710 Yoo O Single +5 V =10% power supply Cy Ol 2 "8 FID Doo! Diz OF 3 18 ID Geta O Transparent operation Dig C1 4 = 17 (0 bos/B0g Industrial temperature range: -40 to +85C D4 OL] 18 [I] DOs/DOs ts Ol] 6 15 1D OOy/BGy Ordering Information Ms OF] F 14 DD Dos'DOs Cy Cr) 13 [2D Dog DD Part Number Package Output BF ons 12 0D o> BGy aPorie2c 20-pin plastic CIP Non-inverted Ves OL] 1 110 ste aPorioe2a 20-pin plastic SOP aware aPDTOesC 20-pin plastic Du inverted Symbol Funetion DlprDty Data input, bits 0-7 Seo DODO Data output, bits 0-7; noninverted (uPOT waz) 55, of inverted (un PO? 1083) STB Strobe input cE Qutput enable input Voo +5'V power supply Ves Ground 5H-|NEC pPD71082, 71083 PIN FUNCTIONS latch. Data is latched on the falling edge of STB. When STB Is low, the DO,-DO7/D outputs do not Dlo-Dly (Data Input) change. Dip-Dl7 are data input lines to the 8-bit data latch. Data on DI lines passes through the latch while STB is high, O& (Output Enable) The data Is latched to DO/D6 with the falling edge of STB. DOp-D07/DGo-DO, (Data Output) DOg-DO7/DOy-D0, are the three-state data output lines from the 8-bit data latch. When 6E is high, these lines go into the high-impedance state. When OE is low, data from the latch Is output, either non-inverted (oPD71082) or inverted (aPD7 1083). STB (Strobe) STB is the input strobe signal for the 8-bit latch. When STB Is high, data on the DI lines passes through the B-bit Block Diagram OE input is the output enable signal for the three-state DODO lines. When OE Is high, DO/DO lines are high impedance. When OE is low, data from the 8-bit latch Is output to DO,-DO,/D0_-DO;. See table 1. Table 1. Latch Operation STB Oe DQ ;D0,D6,-50, Low Low Latehed data from B-bit data laich is enabled High impedance Data on Dig Diz High impedance 8-Bit Data Lateh Bl bree debe hes been latched with falling edge of STB (high te low! CH passed through to poviG High g/g pPiDT i bad BE o Se Ree reeNEC FUNCTIONAL DESCRIPTION The PD71082 and wPD71083 are 8-bit data latches strobed by the STB signal. They have high-drive capa- bility output buffers controlled by the OE signal. Data on the DI lines is latched by the trailing edge of STB (high to low). When STB is high, data passes through the latch. When OE is high, DO lines are high impedance. When OE is low, the contents of the latches are output on DOg- DOy,. The DO lines are isolated from OE switching noise. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Ta = 25C; Vgg = OV Power supply voltage, Vpp ~0.5 to +7.0V -1,0 tO Vpp + 1V ~0.5 to Vop + OSV Input voltage, V; Output voltage, Vo Power dissipation, Pomax, DIP 500 mW Power dissipation, Pomax, SO 200 mW Operating temperature, Topt 40 to +85C Storage temperature, Tstg -65 to + 150C Exposing the device to stresses above those listed in the absolute maximum ratings could cause permanent damage. Exposure to absolute maximum ratings for extended periods may affect device reliability. DC Characteristics Ta = 40 to +85C; Vop = SV +10% Parameter Symbol Min Max Units Conditions Input voltage, Vin 2.2 Vo Voi = 0.45 V high VoH = Vop -0.8V Input voltage, Vit 08 Vo VoL = 0.45 V low Vou Vop / -08V Output voltage, Voy Vop ~ 0.8 Vo oilon = -4mA high Output voltage, VoL 045 V Ig. = 12mA low Input current lh ~1.0 10 pA Vi=Vpp. Vss Leakage lorF -10 10 pA SOE=Vop current, high impedance Power supply Ibb 80 wA Vi=Vpp Vss current (static) Power supply 'pbayn 20 mA fin = 10MHz current C = 200 pF (dynamic) pPD71082, 71083 Capacitance Ta = 25C; Vpp =+5V Parameter Symbol Min Max Units Conditions Input capacitance Cn 12 pF f= 1MHz AC Characteristics Ta = 40 to +85C; Vop = SV +10% Parameter Symbol Min Max Units Conditions Input to tp1o 5 40 ns __ Loading clreult (a) output delay STB to output tpsteo 10 38660 ns delay Data float tecto 5 30 ns Loading circuit (b) time from OE high Data output tocto 10 40 ns delay from OF low Input to STB tsists 0 ns _ Loading circult (a) setup time Input to STB tustBI 25 ns hold time STB high tpwsta 20 ns pulse width Signal rise tty 20 ns 0.8to 2.0V time Signai falt tHL 12 ns 2.0to0.8V time Loading Circuits for AC Testing [a] VOL. VOH Outputs [b] Three-State Output 2.87V 2.87V 2069 360 200 pF 675.0 200 pF 1 Loading Conditions: lo, = 12 mA, loH = 4mA, C, = 200 pF 83-000228A, SH-3pPD71082, 71083 Timing Waveforms . x tsiSTB tpwsTB OE tocTo tole tFcTo I tosTBO _ e ye a 3 pods ___--__{ x x K, Z B3-0042166 Timing Measurement Points input Output 24v 22aV 2.2V 22 2.2 Measurement Paints Measurement Points 0.8V OB8v OBv 0.8 V 0.4aV 83-004211B