[AK1110AEU] AK1110AEU 2ch Output, Ultra High PSRR, Ultra Low Noise LDO Regulator 1. General Description The AK1110AEU is a dual output low dropout linear regulator with ON/OFF control. Each output can supply 100mA and 200mA load current. The AK1110AEU is an integrated circuit achieving excellent ripple rejection and low output noise characteristics with silicon monolithic bipolar structure. In addition, over current and thermal protections are integrated. It is especially well suited for noise sensitive applications. The AK1110AEU is housed in a small and thin type PLP10-2725 package with an exposed pad. It is designed for space saving requiring systems. 2. Feature Operating Voltage Range Maximum Output Current 6V to 14V LDO1 200mA LDO2 100mA High Precision output voltage LDO1 5.0V LDO2 5.0V Dropout Voltage LDO1 600mV at Io=200mA LDO2 600mV at Io=100mA Output Noise LDO1 2 VRMS at 10Hz to 100kHz LDO2 1 VRMS at 10Hz to 100kHz Ripple Rejection Ratio LDO1 83dB at f=1kHz LDO2 100dB at f=1kHz NP terminal to reduce output noise On/Off Control Function Over Current Protection, Thermal Protection Ceramic Capacitor Available Small Package PLP10-2725 (2.7mmx2.5mmx0.6mm) 3. Application High precision DAC applications, RF, PLL, etc. 016016348-E-00 -1- 2016/12 [AK1110AEU] 4. Table of Contents 1. 2. 3. 4. 5. 6. General Description .................................................................................................................. 1 Feature ..................................................................................................................................... 1 Application ................................................................................................................................ 1 Table of Contents ..................................................................................................................... 2 Block Diagram .......................................................................................................................... 3 Pin Configurations and Functions ............................................................................................. 4 Pin Configurations.............................................................................................................................. 4 Pin Functions ..................................................................................................................................... 4 7. Absolute Maximum Ratings ...................................................................................................... 5 8. Recommended Operating Conditions ....................................................................................... 6 9. Electrical Characteristics .......................................................................................................... 6 10. Functional Descriptions ............................................................................................................ 8 Output Capacitor and Stability ........................................................................................................... 8 Noise Bypass Capacitor .................................................................................................................... 8 Output Enable Control ....................................................................................................................... 8 Over Current Protection ..................................................................................................................... 8 Thermal Protection ............................................................................................................................ 8 Attention to PCB Layout .................................................................................................................... 8 Characteristic Examples .................................................................................................................... 9 11. Definition of Terms ................................................................................................................. 16 12. Recommended External Circuits ............................................................................................ 17 13. Package ................................................................................................................................. 18 Outline Dimensions.......................................................................................................................... 18 Marking ............................................................................................................................................ 18 14. Ordering Guide ....................................................................................................................... 18 15. Revision History ..................................................................................................................... 19 IMPORTANT NOTICE .................................................................................................................. 19 016016348-E-00 -2- 2016/12 [AK1110AEU] 5. Block Diagram VOUT_LDO1 VIN_LDO1 EN VIN_LDO2 VOUT_LDO2 5 4 3 2 1 VREG OCL/TSD OCL/TSD 6 7 8 9 GND_LDO1 NP_LDO GND_REG NP_LDO 10 GND_LDO2 Figure 1. Block Diagram 016016348-E-00 -3- 2016/12 [AK1110AEU] 6. Pin Configurations and Functions Pin Configurations VOUT_LDO2 1 10 GND_LDO2 VIN_LDO2 2 9 NP_LDO2 EN 3 8 GND_REG VIN_LDO1 4 7 NP_LDO1 6 GND_LDO1 VOUT_LDO1 5 Exposed Pad Figure 2. Pin Configurations (Top View) Pin Functions No. Name 1 VOUT_LDO2 2 VIN_LDO2 I/O O P Internal Equivalent Circuit Figure 3 Figure 3 Description LOD2 Output LOD2 Input On/Off Control Terminal of the LDO1 and LDO2 (High active) 3 EN I Figure 4 The pull-down resister (300k) is built-in. 4 VIN_LDO1 P Figure 3 LDO1 Input 5 VOUT_LDO1 O Figure 3 LDO1 Output 6 GND_LDO1 LDO1 Ground Noise Bypass Terminal of the LDO1 7 NP_LDO1 O Figure 5 Connect a bypass capacitor between NP_LDO1 and GND. 8 GND_REG GND terminal of the internal 5V regulator Noise Bypass Terminal of the LDO2 9 NP_LDO2 O Figure 5 Connect a bypass capacitor between NP_LDO2 and GND. 10 GND_LDO2 LDO2 Ground Exposed Pad Heat Dissipation Pad (Note 2) It is connected to GND internally. Note 1. I(Input terminal), O(Output terminal), P(Power terminal) Note 2. The exposed pad should be connected to the GND plane. Equivalent Circuits Figure 3 016016348-E-00 Figure 4 -4- Figure 5 2016/12 [AK1110AEU] 7. Absolute Maximum Ratings (GND_LDO1 = GND_LDO2 = GND_REG =0V) Parameter Symbol Min. Max. Supply Voltage VIN -0.3 16 (VIN_LDO1, VIN_LDO2) Reverse Bias VREV -0.3 6 (VOUT_LDO1, VOUT_LDO2) Np Terminal Voltage VNP -0.3 16 (NP_LDO1, NP_LDO2) EN Terminal Voltage (EN) VEN -0.3 16 GND_LDO1- GND_LDO2 GND_LDO1- GND_REG VGND -0.3 0.3 GND_LDO2- GND_REG Junction Temperature Tj 150 Storage Temperature Range TSTG -55 150 Unit Condition V V V V V C C Power Dissipation PD 1800 mW (Note 5) Note 3. All voltages are with respect to GND. GND=0V Note 4. The exposed pad should be connected to the GND plane. Note 5. When the temperature is more than 25C, derating by -18mW is needed. Thermal resistance JA= 55.4 C /W (Mounted on the four-layer board that conforms to the JEDEC51) WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Power dissipation, Pd(W) 2.5 RJA=55.4/W at 4-layer PCB 2.0 1.5 1.0 0.5 0.0 0 25 50 75 100 125 Temperature () 150 Figure 6. Thermal Derating Curve 016016348-E-00 -5- 2016/12 [AK1110AEU] 8. Recommended Operating Conditions Parameter Symbol Min. -40 Operating Temperature Range Ta -40 Operating junction temperature Tj Operating Voltage Range VIN 6 Note 6. All voltages are with respect to GND. GND=0V Typ. - Max. 85 125 14 Unit C C V Comments 9. Electrical Characteristics (Ta= -40C ~ +85C, VIN=VEN=6.0V, CIN=1.0uF, CNP1=CNP2=10uF, COUT1=COUT2=10uF) Parameter Symbol Test Conditions Min. Typ. Max. Common items of LDO1 and LDO2 Quiescent Current IQ IOUT = 0mA 3.0 5.0 Ground Terminal IGND IOUT1+IOUT2 =32mA 5.0 7.0 Current Standby Current ISTANDBY VEN=0V 0.01 2.0 Unit mA mA A EN terminal high level VENH 1.8 - - V EN terminal Low level EN Terminal Current EN terminal on time (Note 10) Thermal protection Shutdown Temperature LDO1 VENL IENLKG - 50 0.35 150 V A tENON - 55 100 ms TTSD 135 - 155 C Output Voltage VOUT1 4.90 5.0 5.10 V Line Regulation LinReg1 VIN1 = 5V 6 20 mV Load Regulation Dropout Voltage Maximum Output Current (Note 9) LoaReg1 VDROP1 IOUT1= 1mA to 200mA IOUT1 = 200mA 50 600 mV mV IOUTMAX1 VOUT1 = VOUT1(typ)x0.9 Output noise(Note 8) Ripple rejection (Note 8) Vnoise1 PSRR1 VEN=1.8V IOUT1= 1mA to 200mA 220 IOUT1=100mA, f=10Hz to100kHz IOUT1 = 100mA, f=1kHz mA 2.0 VRMS 83 dB IOUT1 = 100mA, f=100kHz 80 dB IOUT1 = 100mA, f=1MHz 70 dB LDO2 Output Voltage VOUT2 Line Regulation LinReg2 VIN2 = 5V Load Regulation LoaReg2 Dropout Voltage Maximum Output Current (Note 9) 016016348-E-00 IOUT2= 1mA to 100mA 5.0 5.10 V 5 15 mV IOUT2 = 1mA to 100mA 25 mV VDROP2 IOUT2 = 100mA 600 mV IOUTMAX2 VOUT2 = VOUT2(typ)x0.9 -6- 4.90 120 mA 2016/12 [AK1110AEU] (Ta= -40C ~ +85C, VIN= VEN =6.0V, CIN=1.0uF, CNP1= CNP2=10uF, COUT1= COUT2=10uF) Parameter Symbol Test Conditions Min. Typ. Max. Output Noise (Note 8) Vnoise2 IOUT2 = 1mA, f=10Hz to100kHz 1.0 Unit VRMS IOUT2 = 1mA, f=1kHz 100 dB IOUT2 = 1mA, f=100kHz 83 dB IOUT2 = 1mA, f=1MHz 76 dB Ripple Rejection (Note 8) PSRR2 Note 7. All voltages are with respect to GND. GND=0V Note 8. Guaranteed by design. This value is not tested. Note 9. The maximum output current is limited by Ta and power dissipation. Note 10. Definition of rise time is shown below. VEN_H EN 90% VOUT tEN_ON 016016348-E-00 -7- 2016/12 [AK1110AEU] 10. Functional Descriptions Output Capacitor and Stability To ensure loop stability, select output capacitors that have more than 3.3uF effective capacitance and 0.1 or less ESR. If the capacity of the output capacitor is increased, peak voltage fluctuation caused by load current variation is reduced. Therefore, the transient response characteristics are improved. DC bias and temperature characteristics must be considered when using ceramic capacitors. Noise Bypass Capacitor It is recommended that the effective capacitance of the capacitor connected to the NP pin is 3.3 F or higher. Increase the capacitance of a capacitor at the NP pin to prioritize the output noise and ripple rejection characteristics in the system design. The NP pin capacitance does not affect output stability. Output Enable Control Output ON/OFF control is available by the EN pin. When output is turned OFF, IC current consumption can be minimized. EN terminal voltage (VEN) Operating state VEN > 1.8V ON VEN < 0.35V OFF Over Current Protection The AK1110 limits the output current for IC protection when the output current exceeds the maximum rating such as when it is shorted to ground. The AK1110 automatically returns to normal operation when the output current decreases. Thermal Protection If the junction temperature exceeds the maximum rating as power loss of the AK1110 is large, the output of the AK1110 is turned off by the thermal protection function. The AK1110 automatically returns to normal operation when the junction temperature decreases. Attention to PCB Layout Package: PLP10-2725 Board Material: 4-layer glass epoxy substrate, (x=25mm, y=25mm, t=1.6mm, Copper pattern thickness 18um) 1. CIN should be located as close as possible to the VIN1, VIN2 pin and GND. 2. COUT1, COUT2 should be located as close as possible to the VOUT1, VOUT2 pin and GND. 3. CNP1, CNP2 should be located as close as possible to the NP1, NP2 pin and GND. 4. GND plane should be large as much as possible. 5. The exposed pad is a common ground of the IC. It must be connected to the PCB GND. 6. Via halls are effective for heat dissipation to each layer of PCB. Figure 7. Recommended Layout 016016348-E-00 -8- 2016/12 [AK1110AEU] Characteristic Examples CIN=1.0uF, CNP1= CNP2=10uF, COUT1= COUT2=10uF Noise Characteristics LDO1 LDO2 100 O u tput Noise [nV/Hz] O u tput Noise [nV/Hz] 100 10 1 1E+01 1E+02 1E+03 1E+04 Fr equency [Hz] 10 1 1E+01 1E+05 1E+03 1E+04 1E+02 Fr equency [Hz] 1E+05 Figure 8. Output Noise Level (1/f) To reduce the output noise, increase capacitance of the NP capacitors. A 3.3 uF or higher NP capacitor is recommended. 016016348-E-00 -9- 2016/12 [AK1110AEU] LDO2 VIN=6V, Iout2=1mA -20 -20 -40 -40 P S RR [dB] P S RR [dB] Ripple Rejection Characteristics LDO1 VIN=6V, Iout1=100mA -60 -80 -60 -80 -100 -100 -120 1E+01 1E+02 1E+03 1E+04 1E+05 1E+06 Fr equency [Hz] -120 1E+01 1E+02 1E+03 1E+04 1E+05 1E+06 Fr equency [Hz] Figure 98. Ripple Rejection LDO1 LDO2 VIN=6V, f=1kHz -20 -20 -40 -40 P S RR [dB] P S RR [dB] VIN=6V, f=1kHz -60 -80 -100 -60 -80 -100 -120 -120 0 50 100 150 200 0 20 O u tput Current [mA] 40 60 80 O u tput Current [mA] 100 Figure 90. Ripple Rejection vs. Iout The ripple rejection characteristic depends on the capacity and characteristics of the output capacitor. Ripple rejection characteristics over 50 kHz are greatly affected by the output capacitor capacitance and PCB pattern. 016016348-E-00 - 10 - 2016/12 [AK1110AEU] LDO2 Iout2=1mA 5.2 5.2 5.1 5.1 Output Voltage [V] Output Voltage [V] DC Characteristics LDO1 Iout1=1mA 5.0 4.9 4.8 5.0 4.9 4.8 5 7 9 11 13 15 5 9 7 11 13 15 Operating Voltage [V] Operating Voltage [V] Figure 101. Input voltage fluctuation LDO1 LDO2 VIN=6V 5.2 5.2 5.1 5.1 Output Voltage [V] Output Voltage [V] VIN=6V 5.0 4.9 4.8 5.0 4.9 4.8 0 50 150 100 200 0 Output Current [mA] 20 40 60 80 100 Output Current [mA] Figure 112. Load fluctuation LDO1 LDO2 5.2 5.2 Iout1=1mA Iout1=200mA Iout1=1mA Iout1=100mA 5.1 Output Voltage [V] Output Voltage [V] 5.1 5.0 4.9 4.8 4.7 5.0 4.9 4.8 4.7 4.5 5.0 5.5 6.0 4.5 5.0 5.5 6.0 Operating Voltage [V] Operating Voltage [V] Figure 123. Input vs Output Voltage 016016348-E-00 - 11 - 2016/12 [AK1110AEU] LDO1 LDO2 300 Droppout Voltage [mV] Droppout Voltage [mV] 300 200 100 0 200 100 0 0 50 100 150 200 0 40 20 Output Current [mA] 60 80 100 Output Current [mA] Figure 134. Dropout Voltage LDO1 LDO2 VIN=6V VIN=6V 20 Ground Terminal Current [mA] Ground Terminal Current [mA] 20 15 10 5 0 0 50 100 150 200 15 10 5 0 0 20 Output Current [mA] 40 60 80 100 Output Current [mA] Figure 145. Ground Terminal Current VIN=6V VIN=6V 8 EN Terminal Current [mA] 3 I Q [mA] 6 4 2 0 2 1 0 5 7 9 11 13 15 0 Operating Voltage [V] 4 6 8 10 12 14 EN Terminal Voltage [V] Figure 156. Quiescent Current 016016348-E-00 2 Figure 167. VEN vs. IEN - 12 - 2016/12 [AK1110AEU] LDO1 LDO2 VIN=6V 6 5 5 O u tput Voltage [V] O u tput Voltage [V] VIN=6V 6 4 3 2 1 4 3 2 1 0 0 0 100 200 300 400 500 0 100 Output Current[mA] 200 300 Output Current[mA] Figure 178. Overcurrent protection characteristics LDO1 LDO2 VIN=6V 6 6 5 5 O u tput Voltage [V] O u tput Voltage [V] VIN=6V 4 3 2 4 3 2 1 1 0 125 130 135 140 0 125 145 Ambient Temperature [] 130 135 140 145 Ambient Temperature [] Figure19. Thermal Protection Temperature Characteristic LDO1 VIN=6V LDO2 VIN=6V 500 Maxim um Output Current [mA] Maxim um Output Current [mA] 500 400 300 200 100 -50 -25 0 25 50 75 100 Am bient Temperature [] 400 300 200 100 -50 -25 0 25 50 75 Am bient Temperature [] 100 Figure 180. Maximum Output Current 016016348-E-00 - 13 - 2016/12 [AK1110AEU] LDO1 LDO2 VIN=6V, Iout=200mA VIN=6V, Iout=100mA 20 Ground Terminal Current [A] Ground Terminal Current [A] 20 15 10 5 0 -50 -25 0 25 50 75 Am bient Temperature [] 100 15 10 5 0 -50 -25 0 25 50 75 100 Am bient Temperature [] Figure 191. Ground Terminal Current LDO1 LDO2 400 Iout1=1mA Iout1=200mA Dropout Voltage [mV] Dropout Voltage [mV] 400 300 200 100 0 Iout2=1mA Iout2=100mA 300 200 100 0 -50 -25 0 25 50 75 Am bient Temperature [] 100 -50 -25 0 25 50 75 Am bient Temperature [] 100 Figure 202. Dropout Voltage LDO1 LDO2 VIN=6V VIN=6V 5.2 Iout1=1mA Iout1=200mA 5.1 Output Voltage [V] Output Voltage[V] 5.2 5.0 4.9 4.8 Iout1=1mA Iout1=100mA 5.1 5.0 4.9 4.8 -50 -25 0 25 50 75 Am bient Temperature [] 100 -50 -25 0 25 50 75 Am bient Temperature [] 100 Figure 213. Output Voltage Temperature Characteristic 016016348-E-00 - 14 - 2016/12 [AK1110AEU] VIN=6V, EN=1.8V VIN=6V 2.5 EN Threshold Voltage[V] EN Terminal Current[uA] 100 80 60 40 20 OFFON ONOFF 2.0 1.5 1.0 0.5 0.0 0 -25 0 25 50 75 Am bient Temperature [] -50 -50 100 Figure 224. EN Terminal Current Transient Characteristic LDO1 Vin=6V, EN=01.8V, RL=25 -25 0 25 50 75 Am bient Temperature [] Figure 235. EN Threshold Voltage LDO2 Vin=6V, EN=01.8V, RL=50 V out 2 : 1V/div V out 2 : 1V/div E N : 2V/div E N : 2V/div -25 0 25 50 Tim e [ms] 75 100 -25 100 0 25 50 75 100 Tim e [ms] Figure 246. Starting Characteristic LDO1 LDO2 Vin=511V, SR=50mV/us Vin=511V, SR=50mV/us V out1 : 25mV/div V out2 : 25mV/div V i n : 2V/div V i n : 2V/div 0.0 0.4 1.2 0.8 Tim e [ms] 1.6 2.0 0.0 0.4 1.2 0.8 Tim e [ms] 1.6 2.0 Figure 25. Line Transient 016016348-E-00 - 15 - 2016/12 [AK1110AEU] LDO1 LDO2 Iout = 1200mA, SR = 100mA/us Iout = 1100mA, SR = 100mA/us V out 25mV/div V out 25mV/div Iout 100mA/div Iout 100mA/div 0 20 40 60 Tim e [us] 80 100 0 20 40 60 Tim e [us] 80 100 Figure 268. Load Transient 11. Definition of Terms Maximum Output Current (IOUT_MAX) It is defined as the output current that the output voltage with 1mA load current becomes 90%. Dropout Voltage (VDROP ) It is a difference between the input voltage and the output voltage when the output voltage drops 100mV from its nominal value by decreasing the input voltage gradually. Line Regulation (LinReg) It is the fluctuation of the output voltage caused by input voltage variation. Load Regulation (LoaReg) It is the fluctuation of the output voltage with load current variation when assuming the input voltage is 6V. Ripple Rejection (PSRR) It is a voltage ratio between the input and the output waveforms when 200 mVp-p AC input is superimposed to the 6.5V input voltage. Standby Current (ISTANDBY) It is the input current that flows when the output voltage is turned OFF by setting the EN pin. 016016348-E-00 - 16 - 2016/12 [AK1110AEU] 12. Recommended External Circuits External Circuit 6V to 14V 5V/100mA VOUT_LDO2 1 10 2 9 GND_LDO2 COUT2 VIN_LDO2 ON EN NP_LDO2 3 AK1110 CNP2 GND_REG 8 OFF VIN_LDO1 5V/200mA COUT1 VOUT_LDO1 NP_LDO1 4 5 7 Exposed Pad 6 CNP1 GND_LDO1 CIN Figure 2927. External Circuit (Top View) Table 1. Recommended External Parts List Symbol Effective Value Remarks Input Capacitor CIN 1.0F or higher LDO1 Output Capacitor COUT1 3.3F or higher ESR 0.1 LDO2 Output Capacitor COUT2 3.3F or higher ESR 0.1 LDO1 NP Capacitor CNP1 3.3F or higher LDO2 NP Capacitor CNP2 3.3F or higher Note 11. The table above is recommended examples. Please confirm and select optimal values with your system board. 016016348-E-00 - 17 - 2016/12 [AK1110AEU] 13. Package Outline Dimensions PLP10-2725 (Unit: mm) +0.02 0.58 -0.03 2.500.05 2.700.05 S 1 0.05 S 1.500.05 0.250.05 0.30 2.30 0.05 0.50 0.200.05 0.05 M Marking (1) 1pin Indication (2) (3) (4) (5) (2) Market No. (3) Year code (last1digit) (4) Week code (5) Management code (1) 14. Ordering Guide AK1110AEU50 016016348-E-00 Ta = -40 to 85C PLP10-2725 - 18 - 2016/12 [AK1110AEU] 15. Revision History Date (Y/M/D) 16/12/26 Revision 00 Reason First Edition Page Contents IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation ("AKM") reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document ("Product"), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products. 1. 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This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of AKM. 016016348-E-00 - 19 - 2016/12