[AK1110AEU]
016016348-E-00 - 1 - 2016/12
1. General Description
The AK1110AEU is a dual output low dropout linear regulator with O N/OFF control. Each output can
supply 100mA and 200mA load current. The AK1110AEU is an integrat ed circuit achieving excellent ripple
rejection and low output noise characteristics wit h silicon monolithic bipolar structure. In addition, over
current and thermal protections are integrated. It is especially well suited for noise sensitive applications.
The AK1110AEU is housed in a small and thin type PLP10-2725 package with an exposed pad. It is
designed for space saving requiring systems.
2. Feature
Operating Voltage Range 6V to 14V
Maximum Output Current LDO1 200mA
LDO2 100mA
High Precision output voltage LDO1 5.0V
LDO2 5.0V
Dropout Voltage LDO1 600mV at Io=200mA
LDO2 600mV at Io=100mA
Output Noise LDO1 2µ VRMS at 10Hz to 100kHz
LDO2 1µ VRMS at 10Hz to 100kHz
Ripple Rejection Ratio LDO1 83dB at f=1kHz
LDO2 100dB at f=1kHz
NP terminal to reduce output noise
On/Off Control Function
Over Current Protection, Thermal Protection
Ceramic Capacitor Available
Small Package PLP10-2725 (2.7mm×2.5mm×0.6mm)
3. Application
High precision DAC applications, RF, PLL, etc.
2ch Output, Ultra High PSRR, Ultra Low Noise LDO Regulator
AK1110AEU
[AK1110AEU]
016016348-E-00 - 2 - 2016/12
4. Table of Contents
1. General Descr ipt ion .................................................................................................................. 1
2. Feature ..................................................................................................................................... 1
3. Application ................................................................................................................................ 1
4. Table of Contents ..................................................................................................................... 2
5. Block Diag ram .......................................................................................................................... 3
6. Pin Config ur ations and Functions ............................................................................................. 4
■ Pin Configurations.............................................................................................................................. 4
■ Pin Functions ..................................................................................................................................... 4
7. Absolute Maximum Ratings ...................................................................................................... 5
8. Recommended O per at ing Conditions ....................................................................................... 6
9. Elect rical Charact e ristic s .......................................................................................................... 6
10. Functional Descriptions ............................................................................................................ 8
■ Output Capacitor and St ability ........................................................................................................... 8
■ Noise Bypass Capacitor .................................................................................................................... 8
■ Output Enable Control ....................................................................................................................... 8
■ Over Curr ent Protection ..................................................................................................................... 8
■ Thermal Protection ............................................................................................................................ 8
■ Attention to PCB Lay out .................................................................................................................... 8
■ Characteristic Examples .................................................................................................................... 9
11. Definit ion of Ter ms ................................................................................................................. 16
12. Recommended External Circuit s ............................................................................................ 17
13. Package ................................................................................................................................. 18
■ Outline Dimensions .......................................................................................................................... 18
■ Marking ............................................................................................................................................ 18
14. Order ing Guide ....................................................................................................................... 18
15. Revision History ..................................................................................................................... 19
IMPORTANT NOTICE .................................................................................................................. 19
[AK1110AEU]
016016348-E-00 - 3 - 2016/12
5. Block Diagram
GND_REG
NP_LDO
EN
VOUT_LDO1
NP_LDO
VIN_LDO2
VIN_LDO1
GND_LDO1
GND_LDO2
VOUT_LDO2
VREG
OCL/TSD
OCL/TSD
5
6
7
8
9
10
1
2
3
4
Figure 1. Block Diagram
[AK1110AEU]
016016348-E-00 - 4 - 2016/12
6. Pin Configurat i ons and Functions
■ Pin Configurat i ons
VOUT_LDO2
VIN_LDO2
EN
VIN_LDO1
VOUT_LDO1
GND_LDO2
NP_LDO2
GND_REG
NP_LDO1
GND_LDO1
1
2
3
4
5
6
7
8
9
10
Exposed Pad
Figure 2. Pin Configurations (Top View)
■ Pin Functions
No.
Name
I/O
Internal Equivalent Circuit
Description
1
VOUT_LDO2
O
Figure 3
LOD2 Output
2
VIN_LDO2
P
Figure 3
LOD2 Input
3 EN I Figure 4
On/Off Control Terminal of the LDO1 and
LDO2 (High active)
The pull-down resister (300kΩ) is bu ilt-in.
4
VIN_LDO1
P
Figure 3
LDO1 Input
5
VOUT_LDO1
O
Figure 3
LDO1 Output
6
GND_LDO1
-
-
LDO1 Ground
7 NP_LDO1 O Figure 5
Noise Bypass Terminal of the LDO1
Connect a bypass capacitor bet ween
NP_LDO1 and GND.
8
GND_REG
-
-
GND terminal of the internal 5V regulator
9 NP_LDO2 O Figure 5
Noise Bypass Terminal of the LDO2
Connect a bypass capacitor bet ween
NP_LDO2 and GND.
10
GND_LDO2
-
-
LDO2 Ground
-
Exposed Pad
(Note 2)
- -
Heat Dissipation Pad
It is connected to GND internally.
Note 1. I(Input ter minal), O(Output t er m inal), P(Power terminal)
Note 2. The exposed pad should be connected to the GND plane.
Equivalent Circuits
Figure 3 Figure 4 Figure 5
[AK1110AEU]
016016348-E-00 - 5 - 2016/12
7. Absolut e M aximum Rati ngs
(GND_LDO1 = GND_LDO2 = GND_REG =0V)
Parameter
Symbol
Min.
Max.
Unit
Condition
Supply Voltage
(VIN_LDO1, VIN_LDO2)
VIN -0.3 16 V
Reverse Bias
(VOUT_LDO1, VOUT_LDO2)
VREV -0.3 6 V
Np Terminal Voltage
(NP_LDO1, NP_LDO2)
VNP -0.3 16 V
EN Terminal Voltage (EN) VEN -0.3 16 V
GND_LDO1- GND_LDO2
GND_LDO1- GND_REG
GND_LDO2- GND_REG
VGND -0.3 0.3 V
Junction Temperature Tj - 150 °C
Storage Temperature Range TSTG -55 150 °C
Power Dissipation PD - 1800 mW (Note 5)
Note 3. All voltages are with respect to GND. GND=0V
Note 4. The exposed pad should be connected t o t he G ND plane.
Note 5. When the temperature is more t han 25°C, derating by -18mW is needed. Thermal resistance
θJA= 55.4 °C /W (Mounted on the four-layer board that conforms to the JEDEC51)
WARNING: Operat ion at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these ex t r emes.
0.0
0.5
1.0
1.5
2.0
2.5
025 50 75 100 125 150
Power dissipation, Pd(W)
Temperature (℃)
RθJA=55.4℃/W at 4-layer PCB
Figure 6. Thermal Derating Curve
[AK1110AEU]
016016348-E-00 - 6 - 2016/12
8. Recommended Operat i ng Condi t i ons
Parameter
Symbol
Min.
Typ.
Max.
Unit
Comments
Operating Temperature Range
Ta
-40
-
85
°C
Operating junction temperatur e
Tj
-40
125
°C
Operating Voltage Range
VIN
6
-
14
V
Note 6. All voltages are with respect to GND. GND=0V
9. Electrical Characteri st i cs
(Ta= −40°C ~ + 85° C, VIN=VEN=6.0V, CIN=1.0uF, CNP1=CNP2=10uF, COUT1=COUT2=10uF)
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Common it em s of LDO 1 a nd LDO 2
Quiescent Current IQ IOUT = 0mA - 3.0 5.0 mA
Ground Terminal
Current
IGND IOUT1+IOUT2 =32mA - 5.0 7.0 mA
Standby Current
ISTANDBY
V
EN
=0V
-
0.01
2.0
µA
EN terminal high level
VENH
1.8
-
-
V
EN terminal Low level
VENL
-
-
0.35
V
EN Terminal Current
IENLKG
V
EN
=1.8V
-
50
150
µA
EN terminal on time
(Note 10)
tENON - 55 100 ms
Thermal protection
Shutdown Temperature
TTSD 135 - 155 °C
LDO1
Output Voltage VOUT1 IOUT1= 1mA to 200mA 4.90 5.0 5.10 V
Line Regulation LinReg
1
∆
VIN1 = 5V
6 20 mV
Load Regulation
LoaReg1
IOUT1= 1mA to 200mA
50
mV
Dropout Voltage
VDROP1
IOUT1 = 200mA
600
mV
Maximum Output
Current (Note 9)
IOUTMAX1 VOUT1 = VOUT1(typ)×0.9 220 mA
Output noise(Note 8) Vnoise1
I
OUT1
=100mA, f=10Hz
to100kHz
2.0 µVRMS
Ripple rejection
(Note 8) PSRR1 I
OUT1
= 100mA, f=1kHz
83 dB
IOUT1 = 100mA, f=100kHz 80 dB
I
OUT1
= 100mA, f=1MHz 70 dB
LDO2
Output Voltage VOUT2 IOUT2= 1mA to 100mA 4.90 5.0 5.10 V
Line Regulation LinReg2 ∆V
IN2
= 5V 5 15 mV
Load Regulation LoaReg2 IOUT2 = 1mA to 100mA 25 mV
Dropout Voltage VDROP2 IOUT2 = 100mA 600 mV
Maximum Output
Current (Note 9)
IOUTMAX2 VOUT2 = VOUT2(typ)×0.9 120 mA
[AK1110AEU]
016016348-E-00 - 7 - 2016/12
(Ta= −40°C ~ +85°C, VIN= VEN =6.0V, CIN=1.0uF, CNP1= CNP2=10uF, COUT1= COUT2=10uF)
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Output Noise (Note 8) Vnoise2 IOUT2 = 1mA, f=10Hz to100kHz 1.0 µVRMS
Ripple Rejection
(Note 8) PSRR2 IOUT2 = 1mA, f=1kHz 100 dB
I
OUT2
= 1mA, f=100kHz
83
dB
IOUT2 = 1mA, f=1MHz 76 dB
Note 7. All voltages are with respect to GND. GND=0V
Note 8. Guar ant eed by design. This value is not tested.
Note 9. The maximum output current is limited by Ta and power dissipation.
Note 10. Definition of rise time is shown below.
V
OUT
EN
V
EN_H
90%
t
EN_ON
[AK1110AEU]
016016348-E-00 - 8 - 2016/12
10. Functional Descriptions
■ Output Capacit or and Stability
To ensure loop stability, select output capacitors that have more than 3.3uF effective capacitance and
0.1Ω or less ESR. If the capacity of the output capacitor is increased, peak voltage fluctuation caused by
load current v ar iation is reduced. Therefore, the tr ans ient r esponse char ac t er istics ar e improv ed. DC
bias and temperature charact erist ics must be considered when using ceramic capacitors.
■ Noise Bypass Capacitor
It is recommended that the effectiv e c apacitance of t he capacitor c onnect ed t o the NP pin is 3.3 μF or
higher. Incr eas e t he capacit ance of a capacitor at the NP pin to prioritize the output noise and ripple
rejection characteristics in the system design. The NP pin capacitance does not affect output st ability .
■ Output Enable Control
Output ON/OFF control is available by the EN pin. When output is turned OFF, IC curr ent consumption
can be minimized.
EN terminal voltage (VEN)
Operating state
VEN > 1.8V
ON
VEN < 0.35V
OFF
■ Over Current Prot ect i on
The AK1110 limits the output cur r ent for I C prot ection when the output cur r ent exceeds t he maximum
rating such as when it is shorted to ground. The AK1110 automatically returns to normal operation when
the output cur r ent decreases.
■ Thermal Protecti on
If the junction temperature exceeds the maximum rating as power loss of the AK1110 is large, the output
of the AK1110 is turned off by the thermal protection function. The AK1110 automatically returns to
normal operation when the junction temperatur e decr eases .
■ Attention to PCB Layout
Package: PLP10-2725
Board Material: 4-layer glass epoxy substrate, (x=25mm, y=25mm, t=1.6mm, Copper patter n t hickness
18um)
1. CIN should be located as close as possible to
the VIN1, VIN2 pin and GND.
2. COUT1, COUT2 should be located as close
as possible to the VOUT1, VOUT2 pin and
GND.
3. CNP1, CNP2 should be located as close as
possible to the NP1, NP2 pin and GND.
4. GND plane should be large as much as
possible.
5. The exposed pad is a com mon ground of the
IC. It must be connected to t he PCB GND.
6. Via halls are effective for heat dissipation to
each layer of PCB.
Figure 7. Recommended Layout
[AK1110AEU]
016016348-E-00 - 9 - 2016/12
■ Characterist i c Exam pl es
CIN=1.0uF, CNP1= CNP2=10uF, COUT1= COUT2=10uF
Noise Characteristics
LDO1
LDO2
1
10
100
1E+01 1E+02 1E+03 1E+04 1E+05
Ou tput Noise [n V/√Hz]
Frequency [Hz]
1
10
100
1E+01 1E+02 1E+03 1E+04 1E+05
Ou tput Noise [n V/√Hz]
F r e quency [Hz]
Figure 8. Output Noise Level (1/f )
To reduce the output noise, increase capacitance of t he NP capacitors. A 3.3 uF or higher NP
capacitor is r ecommended.
[AK1110AEU]
016016348-E-00 - 10 - 2016/12
Ripple Rejection Characteristics
LDO1
LDO2
VIN=6V, Iout1=100mA
-120
-100
-80
-60
-40
-20
1E+01 1E+02 1E+03 1E+04 1E+05 1E+06
P S RR [d B]
Frequency [Hz]
VIN=6V, Iout2=1mA
-120
-100
-80
-60
-40
-20
1E+01 1E+02 1E+03 1E+04 1E+05 1E+06
P S RR [d B]
F r e quency [Hz]
Figure 98. Ripple Rejection
LDO1
LDO2
VIN=6V, f=1kHz
-120
-100
-80
-60
-40
-20
050 100 150 200
P S RR [d B]
O u tput Cu rrent [mA]
VIN=6V, f=1kHz
-120
-100
-80
-60
-40
-20
020 40 60 80 100
P S RR [d B]
O u tput Cu rrent [mA]
Figure 90. Ripple Rejection vs. Iout
The ripple rej ection character ist ic depends on t he capac it y and charact er ist ics of the out put
capacitor. Ripple rejection char ac t er istics over 50 kHz are g r eatly affected by the out put c apacit or
capacitance and PCB pattern.
[AK1110AEU]
016016348-E-00 - 11 - 2016/12
DC Characteristics
LDO1
LDO2
Iout1=1mA
4.8
4.9
5.0
5.1
5.2
57 9 11 13 15
O utput Voltag e [V]
O perating Volt age [V]
Iout2=1mA
4.8
4.9
5.0
5.1
5.2
5 7 911 13 15
O utput Voltag e [V]
O perating Volt age [V]
Figure 101. Input voltage fluctuation
LDO1
LDO2
VIN=6V
4.8
4.9
5.0
5.1
5.2
050 100 150 200
O utput Voltag e [V]
O utput Current [mA]
VIN=6V
4.8
4.9
5.0
5.1
5.2
020 40 60 80 100
O utput Voltag e [V]
O utput Current [mA]
Figure 112. Load fluctuation
LDO1
LDO2
4.7
4.8
4.9
5.0
5.1
5.2
4.5 5.0 5.5 6.0
O utput Voltag e [V]
O perating Volt age [V]
Iout1=1mA
Iout1=200mA
4.7
4.8
4.9
5.0
5.1
5.2
4.5 5.0 5.5 6.0
O utput Voltag e [V]
O perating Volt age [V]
Iout1=1mA
Iout1=100mA
Figure 123. Input vs Output Voltage
[AK1110AEU]
016016348-E-00 - 12 - 2016/12
LDO1
LDO2
0
100
200
300
050 100 150 200
D roppout Volt ag e [mV]
O utput Current [mA]
0
100
200
300
020 40 60 80 100
D roppout Volt ag e [mV]
O utput Current [mA]
Figure 134. Dropout Voltage
LDO1
LDO2
VIN=6V
0
5
10
15
20
050 100 150 200
G round Termin al Current [mA]
O utput Current [mA]
VIN=6V
0
5
10
15
20
020 40 60 80 100
G round Termin al Current [mA]
O utput Current [mA]
Figure 145. Ground Terminal Current
VIN=6V
0
2
4
6
8
57911 13 15
IQ [mA]
O perating Volt age [V]
VIN=6V
0
1
2
3
0246810 12 14
EN Terminal Current [mA]
E N Terminal Voltage [V]
Figure 156. Quiescent Curr ent Figure 167. VEN vs. IEN
[AK1110AEU]
016016348-E-00 - 13 - 2016/12
LDO1
LDO2
VIN=6V
0
1
2
3
4
5
6
0100 200 300 400 500
Ou tput Voltage [V]
O utput Current [ mA]
VIN=6V
0
1
2
3
4
5
6
0100 200 300
Ou tput Voltage [V]
O utput Current [ mA]
Figure 178. Ov er c urr ent protection characteristics
LDO1
LDO2
VIN=6V
0
1
2
3
4
5
6
125 130 135 140 145
Ou tput Voltage [V]
A m bient Temperature [℃]
VIN=6V
0
1
2
3
4
5
6
125 130 135 140 145
Ou tput Voltage [V]
A m bient Temperature [℃]
Figure19. Thermal Protection
Temperature Characteristic
LDO1
LDO2
VIN=6V
100
200
300
400
500
-50 -25 025 50 75 100
Maximu m O utput Curren t [mA ]
Ambient Temperature [℃]
VIN=6V
100
200
300
400
500
-50 -25 025 50 75 100
Maximu m O utput Curren t [mA ]
Ambient Temperature [℃]
Figure 180. Maximum Output Current
[AK1110AEU]
016016348-E-00 - 14 - 2016/12
LDO1
LDO2
VIN=6V, Iout=200mA
0
5
10
15
20
-50 -25 025 50 75 100
G round Termin al Current [ｍA]
Ambient Temperature [℃]
VIN=6V, Iout=100mA
0
5
10
15
20
-50 -25 025 50 75 100
G round Termin al Current [ｍA]
Ambient Temperature [℃]
Figure 191. Ground Term inal Curr ent
LDO1
LDO2
0
100
200
300
400
-50 -25 025 50 75 100
D ropout Voltag e [mV]
Ambient Temperature [℃]
Iout1=1mA
Iout1=200mA
0
100
200
300
400
-50 -25 025 50 75 100
D ropout Voltag e [mV]
Ambient Temperature [℃]
Iout2=1mA
Iout2=100mA
Figure 202. Dropout Voltage
LDO1
LDO2
VIN=6V
4.8
4.9
5.0
5.1
5.2
-50 -25 025 50 75 100
O utput Voltag e[V]
Ambient Temperature [℃]
Iout1=1mA
Iout1=200mA
VIN=6V
4.8
4.9
5.0
5.1
5.2
-50 -25 025 50 75 100
O utput Voltag e [V]
Ambient Temperature [℃]
Iout1=1mA
Iout1=100mA
Figure 213. Output Voltage Temperature Characteristic
[AK1110AEU]
016016348-E-00 - 15 - 2016/12
VIN=6V, EN=1.8V
0
20
40
60
80
100
-50 -25 025 50 75 100
EN Terminal Current[uA]
Ambient Temperature [℃]
VIN=6V
0.0
0.5
1.0
1.5
2.0
2.5
-50 -25 025 50 75 100
EN Thresh old Volt age[ V]
Ambient Temperature [℃]
OFF→ON
ON→OFF
Figure 224. EN Terminal Current Figure 235. EN Threshold Voltage
Transient Characteristic
LDO1
LDO2
Vin=6V, EN=0→1.8V, RL=25Ω
-25 025 50 75 100
Time [ms]
V out 2 : 1V/div
EN : 2V/div
Vin=6V, EN=0→1.8V, RL=50Ω
-25 025 50 75 100
Time [ms]
V out 2 : 1V/div
EN : 2V/div
Figure 246. Starting Characteristic
LDO1
LDO2
Vin=5⇔11V, SR=50mV/us
0.0 0.4 0.8 1.2 1.6 2.0
Time [ms]
V out1 : 25mV/div
Vin : 2V/div
Vin=5⇔11V, SR=50mV/us
0.0 0.4 0.8 1.2 1.6 2.0
Time [ms]
V out2 : 25mV/div
Vin : 2V/div
Figure 25. Line Transient
[AK1110AEU]
016016348-E-00 - 16 - 2016/12
LDO1
LDO2
Iout = 1
⇔
200mA, SR = 100mA/us
020 40 60 80 100
Time [us]
V out 25mV/div
Iout 100mA/div
Iout = 1
⇔
100mA, SR = 100mA/us
020 40 60 80 100
Time [us]
V out 25mV/div
Iout 100mA/div
Figure 268. Load Transient
11. Definition of Terms
Maximum O ut put Cur r ent (IOUT_MAX)
It is defined as the output curr ent that the output voltage w ith 1mA load current becomes 90%.
Dropout Voltage (VDROP )
It is a difference between the input voltage and the output voltage when the output voltage drops
100mV fr om its nominal value by decreasing the input voltag e gradually.
Line Regulation (LinReg)
It is the fluctuation of the output voltag e caus ed by input voltage variation.
Load Regulation (LoaReg)
It is the fluctuat ion of the out put voltage with load current variation when assuming the input
voltage is 6V.
Ripple Rejection (PSRR)
It is a voltage ratio between the input and t he out put waveforms when 200 mVp-p AC input is
superimposed to the 6.5V input voltage.
Standby Current (ISTANDBY)
It is the input curr ent t hat f lows when the output voltage is t ur ned OFF by setting the EN pin.
[AK1110AEU]
016016348-E-00 - 17 - 2016/12
12. Recommended External Circuits
Externa l Circuit
VOUT_LDO2
VIN_LDO2
EN
VIN_LDO1
VOUT_LDO1
GND_LDO2
NP_LDO2
GND_REG
NP_LDO1
GND_LDO1
1
2
3
4
5
6
7
8
9
10
Exposed Pad
AK1110
C
IN
6V to 14V
C
OUT1
C
OUT2
C
NP2
C
NP1
5V/100mA
5V/200mA
OFF
ON
Figure 2927. External Circuit (Top View)
Table 1. Recommended External Parts List
Symbol
Effective Value
Remarks
Input Capacitor
CIN
1.0µF or higher
LDO1 Output Capacitor
COUT1
3.3µF or higher
ESR ≤ 0.1Ω
LDO2 Output Capacitor
COUT2
3.3µF or higher
ESR ≤ 0.1Ω
LDO1 NP Capacitor
CNP1
3.3
µ
F or higher
LDO2 NP Capacitor
CNP2
3.3µF or higher
Note 11. The table above is recommended examples. Please confirm and select optimal values with your
system board.
[AK1110AEU]
016016348-E-00 - 18 - 2016/12
13. Package
■ Outli ne Di m ensi ons
・PLP10-2725 (Unit: mm)
■ Marking
１０Ａ５０
ＹＷＷＡＡ
(1)
(2)
(3)
(4)
(5)
(1) 1pin Indic ati on
(2) Market No.
(3) Year code (last1digit)
(4) Week code
(5) Management code
14. Ordering Guide
AK1110AEU50 Ta = −40 to 85°C PLP10-2725
0.50
0.25±0.05
1.50±0.05
2.30 ± 0.05
2.70
±0.05
2.50
±0.05
0.05
M
1
S
0.05 S
0.20±0.05
0.58+0.02
−0.03
0.30
[AK1110AEU]
016016348-E-00 - 19 - 2016/12
15. Revision History
Date (Y/M/D)
Revision
Reason
Page
Contents
16/12/26
00
First Ed ition
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the
information contained in this document without notice. When you consider any use or
application of AKM product stipulated in this document (“Product”), please make inquiries the
sales office of AKM or authoriz ed dist ribut ors as to current stat us of the Products.
1. All information included in this document are provided only to illustrate the operation and
application examples of AKM Products. AKM neither makes warranties or representations with
respect to the accuracy or completeness of the information contained in this document nor
grants any license to any intellectual property r ights or any other right s of AKM or any t hird party
with respect to the information in this document. You are fully responsible for use of such
information contained in this document in your product design or applications. AKM ASSUMES
NO LIABILI TY FOR ANY LO SSES INCURRED BY Y OU OR THIRD PARTIES ARISI NG FROM
THE USE OF SUCH INFORMATIO N IN YOUR PRODUCT DESIGN OR APPLICAT IONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require
extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may
cause loss of human life, bodily injury, serious property damage or serious public impact,
including but not limited to, equipment used in nuclear facilities, equipment used in the
aerospace industry, medical equipment, equipment used for automobiles, trains, ships and
other transportation, traffic signaling equipment, equipment used to control combustions or
explosions, safety devices, elevators and escalators, devices related to electric power, and
equipment used in finance-related fields. Do not use Product for the above use unless
specifically agr eed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are
responsible for complying with safety standards and for providing adequate designs and
safeguards for your hardware, softwar e and systems which minimize risk and avoid situations in
which a malfunction or failure of the Product could cause loss of human life, bodily injury or
damage to property , including data loss or cor r upt ion.
4. Do not use or otherwise make available the Product or related technology or any information
contained in this document for any military purposes, including without limitation, for the design,
development, use, stock pili ng or manufacturing of nuclear, chemical, or biological weapons or
missile technology products (mass destruction weapons). When exporting the Products or
related technology or any information contained in this docum ent, you should compl y with the
applicable export control laws and regulations and follow the procedures required by such laws
and regulations. The Product s and related technology may not be used for or incorpor at ed into
any products or systems whose manufacture, use, or sale is prohibited under any applicable
domestic or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the
RoHS compatibility of the Product. Please use the Product in compliance with all applicable
laws and regulations that regulate the inclusion or use of controlled substances, including
without limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses
occurring as a result of noncompliance with applicable laws and regulations.
6. Resale of the Product with pr ovisions different from the statement and/ or t echnical features set
forth in t his document shall immediately void any warrant y granted by AKM for the Product and
shall not create or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without
prior writt en consent of AKM.
