FemtoClockTM SAS/SATA Clock Generator ICS844441I PRELIMINARY DATA SHEET General Description Features The ICS844441I is a low jitter, high performance clock generator and a member of the FemtoClockTM family HiPerClockSTM of silicon timing products. The ICS844441I is designed for use in applications using the SAS and SATA interconnect. The ICS844441I uses an external, 25MHz, parallel resonant crystal to generate four selectable output frequencies: 75MHz, 100MHz, 150MHz, and 300MHz. This silicon based approach provides excellent frequency stability and reliability. The ICS844441I features down and center spread spectrum (SSC) clocking techniques. * * * * * * Designed for use in SAS, SAS-2, and SATA systems * External fundamental crystal frequency ensures high reliability and low aging Applications * * * * * * * * Selectable output frequencies: 75MHz, 100MHz, 150MHz, 300MHz * * Output frequency is tunable with external capacitors * * * 2.5V operating supply ICS SAS/SATA Host Bus Adapters SATA Port Multipliers SAS I/O Controllers TapeDrive and HDD Array Controllers SAS Edge and Fanout Expanders HDDs and TapeDrives Disk Storage Enterprise Center (0.25%) Spread Spectrum Clocking (SSC) Down (-0.23% or -0.5%) SSC Better frequency stability than SAW oscillators One differential 2.5V LVDS output Crystal oscillator interface designed for 25MHz (CL = 18pF) frequency RMS phase jitter @ 100MHz, using a 25MHz crystal (12kHz - 20MHz): 1.1936ps (typical) -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) packages Pin Assignment Block Diagrams XTAL_OUT XTAL_IN SSC_SEL0 SSC_SEL1 XTAL_IN 25MHz XTAL OSC FemtoClockTM PLL XTAL_OUT SSC_SEL(1:0) 00 = SSC Off 01 = 0.5% Down-spread 10 = 0.23% Down-spread 11 = 0.5% Center-spread 8-Lead SOIC nPLL_SEL GND 25MHz XTAL OSC FemtoClockTM PLL XTAL_OUT SSC_SEL(1:0) GND nQ Q VDD Pulldown XTAL_IN F_SEL(1:0) 8 7 6 5 ICS844441I 8-Lead SOIC, 150 mil 3.90mm x 4.90mm x 1.375mm package body M Package Top View Q nQ SSC Output Control Logic Pulldown:Pulldown 1 2 3 4 0 1 00 = 75MHz 01 = 100MHz 10 = 150MHz (default) 11 = 300MHz Q nQ nc nc SSC_SEL1 Pullup:Pulldown Pulldown:Pulldown XTAL_OUT XTAL_IN SSC_SEL0 nc Clock Output Control Logic 16-Lead TSSOP 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 F_SEL1 GND nPLL_SEL nQ Q VDD F_SEL0 VDD ICS844441I 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package Top View The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. ICS844441DGI REVISION B OCTOBER 13, 2009 1 (c)2009 Integrated Device Technology, Inc. ICS844441I Preliminary Data Sheet FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR Table 1. Pin Descriptions Name Type Description XTAL_OUT, XTAL_IN Input SSC_SEL0, SSC_SEL1 Input Pulldown SSC select pins. See Table 3A. LVCMOS/LVTTL interface levels. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. F_SEL0 Input Pulldown Output frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels. F_SEL1 Input Pullup Output frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels. nPLL_SEL Input Pulldown Q, nQ Output Differential clock outputs. LVDS interface levels. GND Power Power supply ground. VDD Power Power supply pin. nc Unused PLL Bypass pin. LVCMOS/LVTTL interface levels. No connect. NOTE: Pullup/Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 k RPULLUP Input Pullup Resistor 51 k Function Tables Table 3A. SSC_SEL[1:0] Function Table Table 3B. F_SEL[1:0] Function Table Inputs Inputs SSC_SEL1 SSC_SEL0 Mode F_SEL1 F_SEL0 Output Frequency (MHz) 0 (default) 0 (default) SSC Off 0 0 75 0 1 0.5% Down-spread 0 1 100 1 0 0.23% Down-spread 1 (default) 0 (default) 150 1 1 0.5% Center-spread 1 1 300 ICS844441DGI REVISION B OCTOBER 13, 2009 2 (c)2009 Integrated Device Technology, Inc. ICS844441I Preliminary Data Sheet FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, JA 16 Lead TSSOP 8 Lead SOIC 92.4C/W (0 mps) 96.0C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 2.5V 5%, TA = -40C to 85C Symbol Parameter Test Conditions VDD Power Supply Voltage IDD Power Supply Current Minimum Typical Maximum Units 2.375 2.5 2.625 V 45 mA Table 4B. LVCMOS/LVTTL DC Characteristics,VDD = 2.5V 5%, TA = -40C to 85C Symbol Parameter Test Conditions VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Minimum Typical Maximum Units 1.7 VDD + 0.3 V -0.3 0.7 V F_SEL1 VDD = VIN = 2.5V 5 A SSC_SEL[0:1], F_SEL0, nPLL_SEL VDD = VIN = 2.5V 150 A F_SEL1 VDD = 2.5V, VIN = 0V -150 A SSC_SEL[0:1], F_SEL0, nPLL_SEL VDD = 2.5V, VIN = 0V -5 A Table 4C. LVDS DC Characteristics, VDD = 2.5V 5%, TA = -40C to 85C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change ICS844441DGI REVISION B OCTOBER 13, 2009 Test Conditions Minimum Typical Maximum 350 mV 50 1.25 mV V 50 3 Units mV (c)2009 Integrated Device Technology, Inc. ICS844441I Preliminary Data Sheet FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR Table 4D. Crystal Characteristics Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 25 MHz Equivalent Series Resistance (ESR) 50 Ohm Shunt Capacitance 7 pF AC Electrical Characteristics Table 5. AC Characteristics, VDD = 2.5V 5%, TA = -40C to 85C Symbol fOUT tjit(O) Parameter Output Frequency RMS Phase Jitter (Random); NOTE 1 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical Maximum Units F_SEL(1:0) = 00 75 MHz F_SEL(1:0) = 01 100 MHz F_SEL(1:0) = 10 150 MHz F_SEL(1:0) = 11 300 MHz 75MHz, Integration Range: 12kHz - 20MHz 1.19602 ps 100MHz, Integration Range: 12kHz - 20MHz 1.1936 ps 150MHz, Integration Range: 12kHz - 20MHz 1.22743 ps 300MHz, Integration Range: 12kHz - 20MHz 1.15011 ps 20% to 80% 400 ps 50 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: Using a 25MHz, 18pF quartz crystal. NOTE 1: Please refer to the Phase Noise plot. ICS844441DGI REVISION B OCTOBER 13, 2009 4 (c)2009 Integrated Device Technology, Inc. ICS844441I Preliminary Data Sheet FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR Noise Power dBc Hz Typical Phase Noise at 100MHz Offset Frequency (Hz) ICS844441DGI REVISION B OCTOBER 13, 2009 5 (c)2009 Integrated Device Technology, Inc. ICS844441I Preliminary Data Sheet FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR Parameter Measurement Information Noise Power Phase Noise Plot SCOPE Qx VDD 2.5V5% POWER SUPPLY + Float GND - LVDS Phase Noise Mask nQx f1 Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot 2.5V LVDS Output Load AC Test Circuit RMS Phase Jitter nQ nQ 80% Q 80% t PW VOD Q t PERIOD 20% 20% tF tR odc = t PW x 100% t PERIOD Output Rise/Fall Time Output Duty Cycle/Pulse Width/Period VDD VDD out LVDS out out DC Input LVDS 100 VOD/ VOD VOS/ VOS out DC Input Offset Voltage Setup ICS844441DGI REVISION B OCTOBER 13, 2009 Differential Output Voltage Setup 6 (c)2009 Integrated Device Technology, Inc. ICS844441I Preliminary Data Sheet FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR Application Information Crystal Input Interface The ICS844441I has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 1 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL_IN C1 27p X1 18pF Parallel Crystal XTAL_OUT C2 27p Figure 1. Crystal Input Interface LVCMOS to XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 2. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals VCC the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. VCC R1 Ro Rs 0.1f 50 XTAL_IN Zo = Ro + Rs R2 XTAL_OUT Figure 2. General Diagram for LVCMOS Driver to XTAL Input Interface ICS844441DGI REVISION B OCTOBER 13, 2009 7 (c)2009 Integrated Device Technology, Inc. ICS844441I Preliminary Data Sheet FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR Recommendations for Unused Input Pins Inputs: LVCMOS Control Pins All control pins have internal pull-ups; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. 2.5V LVDS Driver Termination Figure 3 shows a typical termination for LVDS driver in characteristic impedance of 100 differential (50 single) transmission line environment. For buffer with multiple LVDS driver, it is recommended to terminate the unused outputs. 2.5V 50 2.5V LVDS Driver + R1 100 - 50 100 Differential Transmission Line Figure 3. Typical LVDS Driver Termination ICS844441DGI REVISION B OCTOBER 13, 2009 8 (c)2009 Integrated Device Technology, Inc. ICS844441I Preliminary Data Sheet FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR Schematic Example Figure 4 shows an example of the ICS844441I application schematic. In this ecample, the device is operated at VDD = 2.5V. The 18pF parallel resonant 25MHz crystal is used. The C1 = 27pF and C2 = 27pF are recommended for frequency accuracy. for different board F p 8 1 25 MHz C2 27pF layouts, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. Two examples of LVDS for receiver without built-in termination are shown in this schematic. U1 X1 XTAL_OUT XTAL_IN SSC_SEL0 SSC_SEL1 C1 27pF 1 2 3 4 XTAL_OUT XTAL_IN SSC_SEL0 SSC_SEL1 GND nQ Q VDD Q 8 7 6 5 R1 100 VDD nQ VDD RU1 1K RU2 Not Install To Logic Input pins RD1 Not Install - Zo = 50 Ohm VDD=2.5V Set Logic Input to '0' VDD + C3 0.01u Logic Input Pin Examples Set Logic Input to '1' Zo = 50 Ohm Q Zo = 50 Ohm To Logic Input pins R3 50 RD2 1K nQ Zo = 50 Ohm C9 0.1uF R4 50 + - Alternate LVDS Termination Figure 4. ICS844441I Schematic Example ICS844441DGI REVISION B OCTOBER 13, 2009 9 (c)2009 Integrated Device Technology, Inc. ICS844441I Preliminary Data Sheet FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR Power Considerations This section provides information on power dissipation and junction temperature for the ICS844441I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS844441I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results. Total Power MAX = VDD_MAX * IDD_MAX = 2.625V * 45mA = 118.125mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. Limiting the internal transistor junction temperature, Tj, to 125C ensures that the bond wire and bond pad temperature remains below 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 96C/W per Table 6B below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.118W * 96C/W = 96.3C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the supply voltage, air flow and the type of board (multi-layer). Table 6A. Thermal Resistance JA for 16 Lead TSSOP, Forced Convection JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 92.4C/W 88.0C/W 85.9C/W 0 200 500 96C/W 87C/W 82C/W Table 6B. Thermal Resistance JA for 8 Lead SOIC, Forced Convection JA vs. Air Flow Linear Feet per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS844441DGI REVISION B OCTOBER 13, 2009 10 (c)2009 Integrated Device Technology, Inc. ICS844441I Preliminary Data Sheet FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR Reliability Information Table 7A. JA vs. Air Flow Table for a 16 Lead TSSOP JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 92.4C/W 88.0C/W 85.9C/W 0 200 500 96C/W 87C/W 82C/W Table 7B. JA vs. Air Flow Table for a 8 Lead SOIC JA vs. Air Flow Linear Feet per Second Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count for ICS844441I is: 6431 ICS844441DGI REVISION B OCTOBER 13, 2009 11 (c)2009 Integrated Device Technology, Inc. ICS844441I Preliminary Data Sheet FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR Package Outline and Package Dimensions Package Outline - G Suffix for 16-Lead TSSOP Package Outline - M Suffix for 8 Lead SOIC Table 8B. Package Dimensions for 8 Lead SOIC Table 8A. Package Dimensions for 16 Lead TSSOP All Dimensions in Millimeters Symbol Minimum Maximum N 8 A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 Basic H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 0 8 All Dimensions in Millimeters Symbol Minimum Maximum N 16 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0 8 aaa 0.10 Reference Document: JEDEC Publication 95, MS-012 Reference Document: JEDEC Publication 95, MO-153 ICS844441DGI REVISION B OCTOBER 13, 2009 12 (c)2009 Integrated Device Technology, Inc. ICS844441I Preliminary Data Sheet FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR Ordering Information Table 9. Ordering Information Part/Order Number 844441DGILF 844441DGILFT 844441DMI-75LF 844441DMI-75LFT 844441DMI-100LF 844441DMI-100LFT 844441DMI-150LF 844441DMI-150LFT 844441DMI-300LF 844441DMI-300LFT Marking 44441DIL 44441DIL TBD TBD TBD TBD 41DI150L 41DI150L 41DI300L 41DI300L Package 16 Lead "Lead-Free" TSSOP 16 Lead "Lead-Free" TSSOP 8 Lead "Lead-Free" SOIC 8 Lead "Lead-Free" SOIC 8 Lead "Lead-Free" SOIC 8 Lead "Lead-Free" SOIC 8 Lead "Lead-Free" SOIC 8 Lead "Lead-Free" SOIC 8 Lead "Lead-Free" SOIC 8 Lead "Lead-Free" SOIC Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Tube 2500 Tape & Reel Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. Table 10. Additional Ordering Information Part/Order Number 844441DGI 844441DMI-75 844441DMI-100 844441DMI-150 844441DMI-300 Package 16 TSSOP 8 SOIC 8 SOIC 8 SOIC 8 SOIC Output Frequency (MHz) 75, 100, 150, 300 75 100 150 300 While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS844441DGI REVISION B OCTOBER 13, 2009 13 (c)2009 Integrated Device Technology, Inc. ICS844441I Preliminary Data Sheet 6024 Silver Creek Valley Road San Jose, California 95138 FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT's sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2009. All rights reserved.