3aE D> uiueiia anneaes 5 BERN F:M-23-10 64K x 4 SRAM WITH OUTPUT ENABLE FEATURES ; High speed: 20, 25, 30, 35, and 45ns High-performance, low-power, CMOS double metal process * Single +5V (410%) power supply * Easy memory expansion with CE and OE options Allinputs and outputs are TTL compatible MARKING OPTIONS Timing 20ns access . -20 25ns access -25 30ns access : -30 35ns access -35 45ns access 45 Packages Plastic DIP (300 mil) None Ceramic DIP (300 mil) c Plastic SOJ (300 mil) DJ Ceramic LCC ; EC * Two Volt Data Retention L GENERAL DESCRIPTION The Micron SRAM family employs high-speed, low- power CMOS designs using a four-transistor memory cell. Micron SRAMs are fabricated using double-layer metal, double-layer polysilicon technology. For flexibility in high speed memory applications, Micron offers chip enable Ce) and output enable (OE) on this or- ganization. These enhancements can place the outputs ina high impedance state for additional flexibility in. system design Writing to these devices is accomplished when write . enable (WE) and CE inputs are both LOW. Reading is ac- complished when WE remains HIGH and CE and OE go LOW. The device offers a reduced power standby mode when disabled. This allows system designs to achieve low standby power requirements. All devices operate from a single +5V power supply and all inputs and outputs are fully TTL compatible. PIN ASSIGNMENT (Top View) 28L/300 DIP (A-9, B-9) NCd1 281 Vee AOv2 271 Ais A143 260 A14 A214 250 A13 AS15 240 A12 A4u6 230 Att A5N7 220 Ato ABU8 210NC A749 200-NG A810 191 Da4 Agd11 18/ p03 CE412 171 a2 OE 113 161 pat Vss 114 150 WE 28L/300 SOJ (E-8) NG 4 28 fl Vec Aoy 2 27 AMS Aig3 26 fl A14 agg 4 25 ff AtS Agq 5 24 1 AI2 A4q 6 23 Att AS 7 22 f Ato Ag 8 21 NC A7q9 20 fT NC Asqio =: 19 Das Agi = 18 fDas CEqi2 17002 Ofq13 16) DaI Ves 14 9 18 WE 28L/LCC (F-4) o8e 2228s 32 i128 27 261 Als 251) Al4 2411 Ai3 230 Ai2 Ait i A10 1 DQ4 1] DQ3 DQ2 MTsCeses REV. 141 4-89 Micron Technology, inc., reserves the right to change products or specifications without notice. INVUS LSV4 & oa Jentina epensab eens Amide tap oe ye, Moar he eae heh srtyersareni doe - ay at ORSON Faia *Rh cate eek es 2 ilies cata, het, aah al ak El Ti ia ein i oie ahd JaE D MM G1L2LS44 oooeseb ? MENRN. MICRON TECHNOLOGY INC _, FUNCTIONAL BLOCK DIAGRAM ~ Veo GND { 4 _ T-46-23-10 COLUMN DECODER | nd . a ha > , Dad on =| Agn oc : ~ W ae) : wv As | 8 262,144 - BIT Ee > ui D> MEMORY ARRAY 5 | = a, | 2 Q pat 5 Q A, > oy" A, o 4. | (LSB) ran ( bts Co he POWER DOWN Ay Ag As A, Ag Ais Aig Aig TRUTH TABLE MODE OE} cE | WE pa POWER STANDBY x | H X HIGH-Z | STANDBY READ tft H a ACTIVE : | READ H[| t | 4H HIGH-Z | ACTIVE WRITE, x[ Lt L D ACTIVE Adesso AEA Se ay ae EHOW, SS saa . wt. tek Tae SET nin dent on pan aapm 5s Te Le foeTT ra] = ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under Absolute Maxi- Voltage on Vcc supply relative to Vss wu 1.0Vto+7.0V -s mum Ratings may cause permanent damage to the device. Storage Temperature (Ceramic) suse 65C to +150C This is a stress rating only and functional operation of the Storage Temperature (Plastic) .asssesseeee -55C to +150C device at these or any other conditions above those indi- Power Dissipation "LW cated in the operational sections of this specification is not Short Circuit Output Current wesccssseessessescesnseneetase 50mA implied. Exposure to absolute maximum rating conditions . for extended periods may affect reliability. ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (OCs Ty = 70C; Vee = 5.0V + 10%) DESCRIPTION CONDITIONS SYMBOL} MIN MAX UNITS {| NOTES Input High (Logic 1) Voltage Vii 2.2 Veo+1 1 Input Low (Logic 0) Voltage Vit -0.5 0.8 Vv. 1,2 Input Leakage Current OV < Vin s Voc fui 5 5 pA Output Leakage Current Output(s) Disabled, ILo 5 5 pA OV < Vour < Veco Output High Voltage lou = -4.0mMA Von 2.4 Vv 1 Output Low Voltage lo. = 8.0mMA Vou 0.4 Vv 1 : _ MAX DESCRIPTION CONDITIONS SYMBOL -20 | -25 | -30 | -35 | -40 junmrs|Notes| Power Supply CE < Vit; Veo = MAX Current: Operating f = MAX = 1/'RC, Ico 105} 95 | 95 | 90] 90 |mA!} 3 Outputs Open Power Supply CE > Vin; Veco = MAX Current: Standby .. f= MAX = 1/'RC, IsBt 30 | 25 | 25 } 25] 25 |mA Outputs Open GE 2 Vee -0.2V; Voc = MAX Vii < Vss +0,2V; Isa2 5}5/]51)71 7 |mA Vin 2 Voc -0.2V; f=0 CAPACITANCE DESCRIPTION CONDITIONS SYMBOL | MIN MAX UNITS NOTES Input Capacitance Ty = 25C; f = 1MHz Cr 7 pF 4 Output Capacitance Voc = 5V Co 5 pF 4 INVYS LSV4 E pO cane a Cay ot aa : ery wn gh ony ow hy She se Ma adPe fn vs Lsv- f ae. ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 5, 13) (0C <T, < 70C; Voo = 5V + 10%) -20 -25 -30 -35 -45 DESCRIPTION . SYM MIN | MAX | MIN | MAX | MIN | MAX | MIN | MAX | MIN | MAX | UNITS |NQTES READ Cycle READ cycle time 'Rc 20 25 30 35 45 ns Address access time AA 20 25 30 35 . 45 | ns Chip Enable access time 'ACE 20 25 30 35 45 ns Output hold from address change OH 3 5 5 5 5 ns Chip Enable to output in Low-Z LZCE | 6 6 6 6 6 ns Chip Disable to output in High-Z_ | HZCE 9 9 12 15 | 18 | ns | 6,7 Chip Enable to power-up time tpu 0. 0 0 0 0 ns Chip Disable to power-down time Pp 20 25 30 35 45 ns Output Enable access time AOE 8 8 10 12 15 | ns Output Enable to output inLow-Z | ZOE | oO 0 0 0 0 ns Output Disable to out put in High-Z } 'HZOE 7 -7 10 12 15 | ns WRITE Cycle WRITE cycle time two 20 20 26 30 35 ns Chip Enable fo end of write tow 15 15 18 20 25 ns Address valid to end of write taw 15 15 18 20 25. ns Address setup time as 0 0 - 0 0 0 ns Address hold from end of write AH 0 0 0 0 0 ns Write pulse width we 15 15 18 20 25 ns Data setup time Ds 10 10 12 15 20 ns Data hold time DH 0 0 0 0 0 ns Write Disable to output in Low-Z | LZWE | 5 5 5 5 5 ns Write Enable to output in High-Z | 'HZWE 10 10 12 15 18 | ns 6 4-92 wy Lael eect asnyeted sh bu ee he oH wax phe, ine wt TR aah atAC TEST CONDITIONS Input pulse loVElS .....cscscsssscerrseatenseseers Vss to 3.0V Input rise and fall times SNS Input timing reference levels ........ tseveneesesneesenneas 1.5V Output reference lovels ....scsssscseccesersesrescorees 1.5V Output load vc essecccsecessssesesens See Figures 1 and 2 NOTES TA SNe s All voltages referenced to Vss (GND). ~3.0V for pulse width < 20ns. Icc is dependent on output loading and cycle rates. This parameter is sampled. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. 'HZCE, 'HZOE and HZWE are specified with CL = 5pF as in Fig. 2. Transition is measured + 500mV from. steady state voltage. At any given temperature and voltage condition, 'HZCE is less than LZCE, = 30 pF V Fig. 1 OUTPUT LOAD EQUIVALENT 255 = pF. Fig. 2 OUTPUT LOAD EQUIVALENT 8. WE is HIGH forREAD cycle. 9. Device is continuously selected. All chip enables held in their active state. 10. Address valid prior to or coincident with latest 11. RC = Read Cycle Time. 12. Chip enable CH 13. For automotive, industrial and extended temperature occurring chip enable, and terminate a WRITE cycle. specifications refer to page 4-169. CE) and write enable (WE) can initiate DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only) DESCRIPTION CONDITIONS SYMBOL MIN TYP MAX UNITS | NOTES Vcc for Retention Data Vor 2 _ Vv Data Retention Current CE (Vee -0.2V) | Vcc = 2v!]_ Iccoa 95 300 pA Vin 2 (Vcc -0.2V . : orsQ.2V Vcc = 3v 350 400 pA Chip Deselect to Data Retention Time cpR 0 ns 4 Operation Recovery Time 'R aC ns 4,41 LOW Vcc DATA RETENTION WAVEFORM DATA RETENTION MODE AL ASV 4.5V. Veo . K Vor >2V 7 toon tr Vi = eT Ul DON'T CARE B33] UNDEFINED 4-93 tac bee Na ney A Socata oo aes iD yer Mares WVHS LSV-I A Gat BA Me ettega 8MICRON TECHNOLOGY INC 38E D MM 6122545 0002830 9 MMNRN READ CYCLE NO. 1 89 tac at = ! ADDR 4 VALID y . s taa ton Q PREVIOUS DATA VALID DATA VALID IVS sv ff READ CYCLE NO. 2 7:8 10 3 tac tLZ0E {_ tHZOE tLzcE tuzce DQ HIGH-Z c DATA VALID a tpu ee oo . tep Ice | DON'T CARE RRQ unDeFINeD a 4-94Seba pan aee Beta ce aie es E ETS i (=i) EGE. = s BS: 3 - ss ee! Se etn aa a WRITE CYCLE NO. 1 4 (Write Enable Controlled) 7: 12 ( a two wt ADDR - cE > We = tos tou & D DATA VALID > L2we = ; : a 4 WRITE CYCLE NO. 2 (Chip Enable Controlled) 12 two ADDR x 1@ taw tas L. tow taH hs cE \ j twp 2 e 4% WE WLLL } WT, | ps | tou 3 t 3 a= o DATA VALID pe . tHzwe : AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AD ORK RR RR) HIGH-Z Ae sankeN a Mende at ys DON'T CARE BRA) UNDEFINED