W29N08GV
Release Date: August 26th 2016
1 – Revision A
2 chip stack 8G-Bit
W29N08GV
NAND FLASH MEMORY
W29N08GV
Release Date: August 26th 2016
2 – Revision A
Table of Contents
1. GENERAL DESCRIPTION ..................................................................................................... 3
2. PACKAGE TYPES AND PIN CONFIGURATIONS ................................................................ 4
3. MEMORY ARRAY ORGANIZATION ...................................................................................... 8
4. DEVICE ID .............................................................................................................................. 9
5. DC ELECTRICAL CHARACTERISTICS ............................................................................... 10
6. INVALID BLOCKS ................................................................................................................. 11
7. PACKAGE DIMENSIONS ..................................................................................................... 12
8. ORDERING INFORMATION................................................................................................. 14
9. REVISION HISTORY ............................................................................................................ 15
List of Tables
Table 1 Addressing ............................................................................................................................. 8
Table 2 Device ID and configuration codes for Address 00h .............................................................. 9
Table 3 DC Electrical Characteristics ................................................................................................ 10
Table 5 Valid Block Number .............................................................................................................. 11
Table 6 History Table ........................................................................................................................ 15
List of Figures
Figure 1 Pin Assignment 48-pin TSOP1 1CE Type (Package code S) .............................................. 4
Figure 2 Pin Assignment 48-pin TSOP1 2CE Type (Package code S) .............................................. 5
Figure 3 Ball Assignment 63-ball FBGA 1CE Type (Package code B) ............................................... 6
Figure 4 Ball Assignment 63-ball FBGA 2CE Type (Package code B) ............................................... 7
Figure 5 TSOP 48-PIN 12X20mm ..................................................................................................... 12
Figure 6 Fine-Pitch Ball Grid Array 63-Ball ....................................................................................... 13
Figure 7 Ordering Part Number Description ...................................................................................... 14
W29N08GV
Release Date: August 26th 2016
3 – Revision A
1. GENERAL DESCRIPTION
The W29N08GV (8G-bit) NAND Flash memory provides a storage solution for embedded systems
with limited space, pins and power. It is ideal for code shadowing to RAM, solid state applications
and storing media data such as, voice, video, text and photos. The device operates on a single 2.7V
to 3.6V power supply with active current consumption as low as 25mA and 10uA for CMOS standby
current.
The memory array totals 1,107,296bytes, and organized into 8,192 erasable blocks. Each block
consists of 64 programmable pages of 2,112-bytes (1056 words) each. Each page consists of
2,048-bytes (1024 words) for the main data storage area and 64-bytes (32words) for the spare data
area (The spare area is typically used for error management functions).
The W29N08GV is double chip stack of W29N04GV. Then, this document shows specified features,
functions of W29N08GV. Detail functions, commands operation, AC, DC characteristics and
restrictions refer to W29N04GV datasheet.
W29N08GV
Release Date: August 26th 2016
4 – Revision A
2. PACKAGE TYPES AND PIN CONFIGURATIONS
2.1 W29N08GVSIAA Pin assignment 48-pin TSOP1
Figure 1 Pin Assignment 48-pin TSOP1 1CE Type (Package code S)
3
4
1
2
Top View
7
8
5
6
11
12
9
10
15
16
13
14
19
20
17
18
23
24
21
22
46
45
48
47
42
41
44
43
38
37
40
39
34
33
36
35
30
29
32
31
26
25
28
27
48-pin TSOP1
Standard package
12mm x 20mm
N.C
N.C
Vss1
N.C
IO5
IO4
IO7
IO6
DNU
Vcc
N.C
Vcc1
Vcc1
N.C
Vss
N.C
IO1
IO0
IO3
IO2
N.C
Vss1
N.C
N.C
N.C
N.C
N.C
N.C
RY/#BY
#RE
N.C
N.C
N.C
Vcc
#CE
N.C
N.C
CLE
Vss
N.C
#WP
DNU
ALE
#WE
N.C
N.C
N.C
N.C
X8X8
W29N08GV
Release Date: August 26th 2016
5 – Revision A
2.2 W29N08GVSIAD Pin assignment 48-pin TSOP1
Figure 1.1 Pin Assignment 48-pin TSOP1 (Package code S)
Figure 2 Pin Assignment 48-pin TSOP1 2CE Type (Package code S)
Note:
1. These pins might not be connected in the package. Winbond recommends connecting these pins to the
designed external sources for ONFI compatibility.
3
4
1
2
Top View
7
8
5
6
11
12
9
10
15
16
13
14
19
20
17
18
23
24
21
22
46
45
48
47
42
41
44
43
38
37
40
39
34
33
36
35
30
29
32
31
26
25
28
27
48-pin TSOP1
Standard package
12mm x 20mm
N.C
N.C
Vss1
N.C
IO5
IO4
IO7
IO6
DNU
Vcc
N.C
Vcc1
Vcc1
N.C
Vss
N.C
IO1
IO0
IO3
IO2
N.C
Vss1
N.C
N.C
N.C
N.C
N.C
N.C
RY/#BY1
#RE
N.C
RY/BY2
N.C
Vcc
#CE1
#CE2
N.C
CLE
Vss
N.C
#WP
DNU
ALE
#WE
N.C
N.C
N.C
N.C
X8X8
W29N08GV
Release Date: August 26th 2016
6 – Revision A
2.3 W29N08GVBIAA Ball assignment 63-ball VFBGA63
Figure 3 Ball Assignment 63-ball FBGA 1CE Type (Package code B)
3
4
1
2
7
8
5
6
A
B
9
10
E
F
C
D
J
K
G
H
L
M
N
.
C
N
.
C
N
.
C
RY
/
#
BY
#
RE
N
.
C
N
.
C
#
CE
N.
C
CLE
Vss
N
..
C
#
WP
ALE
#
WE
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N.C
N.C
N
.
C
N.C
N.C
N.C
N.C
N.C
N.C
IO
5
IO
4
IO
7
IO
6
N
.
C
N.C
IO
1
IO
0
IO
3
IO
2
Vss
Vcc
Vcc
Vss
DNU
DNU
Top View
,
ball down
W29N08GV
Release Date: August 26th 2016
7 – Revision A
2.4 W29N08GVBIAD Ball assignment 63-ball VFBGA63
Figure 4 Ball Assignment 63-ball FBGA 2CE Type (Package code B)
3
4
1
2
7
8
5
6
A
B
9
10
E
F
C
D
J
K
G
H
L
M
N
.
C
N
.
C
N
.
C
RY
/
#
BY
1
#
RE
N
.
C
N
.
C
#
CE
1
#
CE
2
CLE
Vss
RY
/
#
BY
2
#
WP
ALE
#
WE
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N
.
C
N.C
N.C
N
.
C
N.C
N.C
N.C
N.C
N.C
N.C
IO
5
IO
4
IO
7
IO
6
N
.
C
N.C
IO
1
IO
0
IO
3
IO
2
Vss
Vcc
Vcc
Vss
DNU
DNU
Top View
,
ball down
W29N08GV
Release Date: August 26th 2016
8 – Revision A
3. MEMORY ARRAY ORGANIZATION
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st cycle
A7
A6
A5
A4
A3
A2
A1
A0
2nd cycle
L
L
L
L
A11
A10
A9
A8
3rd cycle
A19
A18
A17
A16
A15
A14
A13
A12
4th cycle
A27
A26
A25
A24
A23
A22
A21
A20
5th cycle
L
L
L
L
L
A304
A29
A28
Table 1 Addressing
Notes:
1. “L” indicates a low condition, which must be held during the address cycle to insure correct processing.
2. A0 to A11 during the 1st and 2nd cycles are column addresses. A12 to A30 during the 3rd, 4th and 5th
cycles are row addresses, A18 is plane address,A19 to the last address are block addresses.
3. The device ignores any additional address inputs that exceed the device’s requirement.
4. The last address of W29N08GVxIAA (8Gb-1CE type) is A30.
W29N08GV
Release Date: August 26th 2016
9 – Revision A
4. DEVICE ID
Parts #
# of
CE
1st
Byte/Cycle
2nd
Byte/Cycle
3rd
Byte/Cycle
4th
Byte/Cycle
5th
Byte/Cycle
W29N08GVxIAA
1
EFh
D3h
91h
95h
58h
W29N08GVxIAD
2
EFh
DCh
90h
95h
54h
Description
MFR ID
Device ID
Cache
Programming
Supported
Page Size:2KB
Spare Area
Size:64b
BLK Size w/o
Spare:128KB
Organized:x8 or
x16
Serial Access:25ns
“x” means package code. S :TSOP48, B : BGA63
Table 2 Device ID and configuration codes for Address 00h
W29N08GV
Release Date: August 26th 2016
10 – Revision A
5. DC ELECTRICAL CHARACTERISTICS
5.1 DC Electrical Characteristics
PARAMETER
SYMBOL
CONDITIONS
SPEC
UNIT
MIN
TYP
MAX
Sequential Read current
Icc1
tRC= tRC MIN
#CE=VIL
IOUT=0mA
-
25
35
mA
Program current
Icc2
-
-
25
35
mA
Erase current
Icc3
-
-
25
35
mA
Standby current (TTL)
ISB1
#CE=VIH
#WP=0V/Vcc
-
-
1
mA
Standby current (CMOS)
ISB2
#CE=Vcc – 0.2V
#WP=0V/Vcc
-
20
100
µA
Input leakage current
ILI
VIN= 0 V to Vcc
-
-
±10
µA
Output leakage current
ILO
VOUT=0V to Vcc
-
-
±10
µA
Input high voltage
VIH
I/O15~0, #CE,#WE,#RE,
#WP,CLE,ALE,RY/#BY,
0.8 x Vcc
-
Vcc + 0.3
V
Input low voltage
VIL
-
-0.3
-
0.2 x Vcc
V
Output high voltage(1)
VOH
IOH=-400µA
2.4
-
-
V
Output low voltage(1)
VOL
IOL=2.1mA
-
-
0.4
V
Output low current
IOL(RY/#BY)
VOL=0.4V
8
10
mA
Table 3 DC Electrical Characteristics
Note:
1. VOH and VOL may need to be relaxed if I/O drive strength is not set to full.
2. IOL (RY/#BY) may need to be relaxed if RY/#BY pull-down strength is not set to full
W29N08GV
Release Date: August 26th 2016
11 – Revision A
6. INVALID BLOCKS
The W29N08GV may have initial invalid blocks when it ships from factory. Also, additional invalid
blocks may develop during the use of the device. Nvb represents the minimum number of valid
blocks in the total number of available blocks (See Table 5). An invalid block is defined as blocks
that contain one or more bad bits. Block 0, block address 00h is guaranteed to be a valid block at
the time of shipment.
Parameter
Symbol
Min
Max
Unit
Valid block number
Nvb
8032
8192
blocks
Table 4 Valid Block Number
W29N08GV
Release Date: August 26th 2016
12 – Revision A
7. PACKAGE DIMENSIONS
7.1 TSOP 48-pin 12x20
Figure 5 TSOP 48-PIN 12X20mm
e
1
48
b
E
D
Y
A1
A
A2
L1
L
c
H
D
0.020
0.004
0.007
0.037
0.002
MIN.
0.60
Y
L
L1
c
0.50
0.10
0.70
0.21
MILLIMETER
A
A2
b
A1
0.95
0.17
0.05
Symbol
MIN.
1.20
0.27
1.05
1.00
0.22
MAX.
NOM.
0.028
0.008
0.024
0.011
0.041
0.047
0.009
0.039
NOM.
INCH
MAX.
E
H
D
0
5
0
5
e
D
18.3
18.4
18.5
19.8
20.0
20.2
11.9
12.0
12.1
0.720
0.724
0.728
0.780
0.787
0.795
0.468
0.472
0.476
0.10
0.80
0.031
0.004
0.020
0.50
W29N08GV
Release Date: August 26th 2016
13 – Revision A
7.2 Fine-Pitch Ball Grid Array 63-ball
Figure 6 Fine-Pitch Ball Grid Array 63-Ball
W29N08GV
Release Date: August 26th 2016
14 – Revision A
8. ORDERING INFORMATION
Figure 7 Ordering Part Number Description
Winbond Standard Product
W: Winbond
Product Family
ONFI compatible NAND Flash memory
Density
08: 8 Gbit
Product Version
G
Supply Voltage and Bus Width
V : 2.7~3.6V and X8 device
Packages
S: TSOP-48
B: VFBGA-63
Temparature Ranges
I: -40 to 85'C
Option Information
A: General Product of 3V device
(Contact Winbond for Option information)
Reserved
A: General Product of single CE type
D: General Product of dual CE type
(Contact Winbond for Option information)
W
29N
08
G
V
I
A
A
S
W29N08GV
Release Date: August 26th 2016
15 – Revision A
9. REVISION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A
08/26/16
New Create
Table 5 History Table
Trademarks
Winbond is trademark of Winbond Electronics Corporation.
All other marks are the property of their respective owner.
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in
systems or equipment intended for surgical implantation, atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion
control instruments, or for other applications intended to support or sustain life. Furthermore,
Winbond products are not intended for applications wherein failure of Winbond products could result
or lead to a situation where in personal injury, death or severe property or environmental damage
could occur.
Winbond customers using or selling these products for use in such applications do so at their own
risk and agree to fully indemnify Winbond for any damages resulting from such improper use or
sales.
