S29AS008J 8 Mbit (1M x 8-Bit / 512K x 16-Bit), 1.8 V Boot Sector Flash Distinctive Characteristics Architectural Advantages Single Power Supply Operation - Full voltage range: 1.65 to 1.95 volt read and write operations for battery-powered applications Manufactured on 110 nm Process Technology Secured Silicon Sector region - 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random Electronic Serial Number, accessible through a command sequence - May be programmed and locked at the factory or by the customer Flexible Sector Architecture - Eight 8 Kbyte and fifteen 64 Kbyte sectors (byte mode) - Eight 4 Kword, and fifteen 32 Kword sectors (word mode) Sector Group Protection Features - A hardware method of locking a sector to prevent any program or erase operations within that sector - Sectors can be locked in-system or via programming equipment - Temporary Sector Group Unprotect feature allows code changes in previously locked sectors Unlock Bypass Program Command - Reduces overall programming time when issuing multiple program command sequences Top or Bottom Boot Block Configurations Available Compatibility with JEDEC standards - Pinout and software compatible with single-power supply Flash - Superior inadvertent write protection Performance Characteristics High Performance - Access times as fast as 70 ns - Industrial temperature range (-40C to +85C) - Word programming time as fast as 6 s (typical) Cypress Semiconductor Corporation Document Number: 002-00870 Rev.*K * Ultra Low Power Consumption (typical values at 5 MHz) - 15 A Automatic Sleep mode current - 8 A standby mode current - 8 mA read current - 20 mA program/erase current Cycling Endurance: 1,000,000 cycles per sector typical Data Retention: 20 years typical Package Options 48-ball BGA 48-pin TSOP Software Features CFI (Common Flash Interface) Compliant - Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices Erase Suspend/Erase Resume - Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation Data# Polling and Toggle Bits - Provides a software method of detecting program or erase operation completion Hardware Features Ready/Busy# Pin (RY/BY#) - Provides a hardware method of detecting program or erase cycle completion Hardware Reset Pin (RESET#) - Hardware method to reset the device to reading array data WP# input pin - Write protect (WP#) function allows protection of two outermost boot sectors (boot sector models only), regardless of sector group protect status 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised May 19, 2017 S29AS008J General Description The S29AS008J is a 8 Mbit, 1.8 Volt-only Flash memory organized as 1,048,576 bytes or 524,288 words with a x8/x16 bus and either top or bottom boot sector architecture. The device is offered in 48-pin TSOP and 48-ball FBGA packages. The word-wide data (x16) appears on DQ15-DQ0; the byte-wide (x8) data appears on DQ7-DQ0. This device is designed to be programmed and erased in-system with the standard system 1.8 volt VCC supply. A 12.0 V VPP or 5.0 VCC are not required for program or erase operations. The device can also be programmed in standard EPROM programmers. The device offers access time of 70 ns allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 1.8 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The S29AS008J is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm-- an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm--an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector group protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. Cypress Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. Document Number: 002-00870 Rev.*K Page 2 of 105 S29AS008J Contents 1. Product Selector Guide ............................................... 4 2. Block Diagram.............................................................. 4 3. 3.1 3.2 3.3 Connection Diagrams.................................................. Standard TSOP.............................................................. FBGA Connection Diagram ........................................... Special Handling Instructions......................................... 4. Pin Configuration......................................................... 7 5. Logic Symbol ............................................................... 7 6. 6.1 Ordering Information ................................................... 8 S29AS008J Standard Products ..................................... 8 7. 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 Device Bus Operations................................................ 9 Word/Byte Configuration................................................ 9 Requirements for Reading Array Data........................... 9 Writing Commands/Command Sequences.................. 10 Program and Erase Operation Status.......................... 10 Standby Mode.............................................................. 10 Automatic Sleep Mode................................................. 10 RESET#: Hardware Reset Pin..................................... 11 Output Disable Mode ................................................... 11 Autoselect Mode .......................................................... 11 Sector Address Tables................................................. 13 Sector Group Protection/Unprotection ......................... 15 Temporary Sector Group Unprotect............................. 17 Write Protect (WP#) ..................................................... 17 Hardware Data Protection............................................ 18 8. 8.1 Secured Silicon Sector Flash Memory Region ....... 18 Factory Locked: Secured Silicon Sector Programmed and Protected at the Factory........................................ 19 Customer Lockable: Secured Silicon Sector NOT Programmed or Protected at the Factory .......................................... 19 8.2 5 5 6 6 9. Common Flash Memory Interface (CFI) ................... 21 10. 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 Command Definitions................................................ 25 Reading Array Data ..................................................... 25 Reset Command .......................................................... 25 Autoselect Command Sequence ................................. 25 Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence 26 Word/Byte Program Command Sequence................... 26 Unlock Bypass Command Sequence .......................... 26 Chip Erase Command Sequence ................................ 27 Sector Erase Command Sequence ............................. 28 Erase Suspend/Erase Resume Commands ................ 28 11. Command Definitions................................................ 30 12. 12.1 12.2 12.3 12.4 12.5 Write Operation Status .............................................. DQ7: Data# Polling ...................................................... RY/BY#: Ready/Busy#................................................. DQ6: Toggle Bit I ......................................................... DQ2: Toggle Bit II ........................................................ Reading Toggle Bits DQ6/DQ2.................................... Document Number: 002-00870 Rev.*K 12.6 DQ5: Exceeded Timing Limits ...................................... 38 12.7 DQ3: Sector Erase Timer.............................................. 38 13. Absolute Maximum Ratings....................................... 39 14. Operating Ranges ....................................................... 39 15. DC Characteristics...................................................... 40 15.1 CMOS Compatible ........................................................ 40 16. Test Conditions ........................................................... 41 17. Key to Switching Waveforms..................................... 41 18. 18.1 18.2 18.3 18.4 18.5 18.6 AC Characteristics...................................................... 42 Read Operations........................................................... 42 Hardware Reset (RESET#)........................................... 43 Word/Byte Configuration (BYTE#) ................................ 44 Erase/Program Operations ........................................... 45 Temporary Sector Group Unprotect.............................. 48 Alternate CE# Controlled Erase/Program Operations .. 49 19. Erase and Programming Performance ..................... 51 20. Package Pin Capacitance........................................... 51 21. Physical Dimensions .................................................. 52 21.1 TS 048 - 48-Pin Standard TSOP .................................. 52 21.2 VBK048--48-Ball Fine-Pitch Ball Grid Array (FBGA) 8.15 mm x 6.15 mm ...................................................... 53 22. Revision History.......................................................... 54 34 34 35 36 36 37 Page 3 of 56 S29AS008J 1. Product Selector Guide Family Part Number S29AS008J Voltage Range: VCC = 1.65-1.95 V Speed Option 70 Max access time, ns (tACC) 70 Max CE# access time, ns (tCE) 70 Max OE# access time, ns (tOE) 25 Note See AC Characteristics on page 42 for full specifications. 2. Block Diagram DQ0-DQ15 (A-1) RY/BY# VCC Sector Switches VSS Erase Voltage Generator RESET# BYTE# WP# State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic CE# OE# VCC Detector A0-A18 Document Number: 002-00870 Rev.*K Timer Address Latch WE# Input/Output Buffers Data Latch Y-Decoder Y-Gating X-Decoder Cell Matrix Page 4 of 56 S29AS008J 3. Connection Diagrams 3.1 Standard TSOP A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC WP# RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Document Number: 002-00870 Rev.*K Standard TSOP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 Page 5 of 56 S29AS008J 3.2 FBGA Connection Diagram Fine-pitch Ball Grid Array 3.3 A6 B6 C6 D6 E6 F6 G6 A13 A12 A14 A15 A16 A5 B5 C5 D5 E5 F5 G5 H5 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 A4 B4 C4 D4 E4 F4 G4 H4 WE# RESET# NC NC DQ5 DQ12 VCC DQ4 A3 B3 C3 D3 E3 F3 G3 H3 RY/BY# WP# A18 NC DQ2 DQ10 DQ11 DQ3 A2 B2 C2 D2 E2 F2 G2 H2 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A1 B1 C1 D1 E1 F1 G1 H1 A3 A4 A2 A1 A0 CE# OE# VSS BYTE# DQ15/A-1 H6 VSS Special Handling Instructions Special handling is required for Flash Memory products in BGA packages. Flash memory devices in BGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time. Document Number: 002-00870 Rev.*K Page 6 of 56 S29AS008J 4. Pin Configuration A0-A18 DQ0-DQ14 DQ15/A-1 BYTE# 19 addresses 15 data inputs/outputs DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) Selects 8-bit or 16-bit mode CE# Chip enable OE# Output enable WE# Write enable WP# Write protect: The WP# contains an internal pull-up; when unconnected, WP is at VIH. RESET# RY/BY# Hardware reset pin Ready/Busy output VCC 1.8 volt-only single power supply (see Product Selector Guide on page 4 for speed options and voltage supply tolerances) VSS Device ground NC Pin not connected internally 5. Logic Symbol 19 A0-A18 16 or 8 DQ0-DQ15 (A-1) CE# OE# WE# RESET# BYTE# RY/BY# WP# Document Number: 002-00870 Rev.*K Page 7 of 56 S29AS008J 6. Ordering Information 6.1 S29AS008J Standard Products Cypress standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. S29AS008J 70 T F I 03 0 Packing Type 0 = Tray 2 = 7" Tape and Reel 3 = 13" Tape and Reel Model Number 03 = VCC = 1.65-1.95 V, top boot sector device 04 = VCC = 1.65-1.95 V, bottom boot sector device Temperature Range I = Industrial (-40C to +85C) Package Material Set F = Pb-Free H = Pb-Free, Low-Halogen Package Type T = Thin Small Outline Package (TSOP) Standard Pinout B = Fine-pitch Ball-Grid Array Package Speed Option 70 = 70 ns Access Speed Device Number/Description S29AS008J 8 Megabit Flash Memory manufactured using 110 nm process technology 1.8 Volt-Only Read, Program, and Erase Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. S29AS008J Valid Combinations Device Number Speed Option S29AS008J 70 Package Type, Material, and Temperature Range TFI Model Number Packing Type 03, 04 0, 3 (Note 1) TS048 (Note 2) TSOP 0, 2, 3 VBK048 Fine-Pitch BGA BFI, BHI Package Description Notes 1. Type 0 is standard. Specify other options as required. 2. TSOP package markings omit packing type designator from ordering part number. Document Number: 002-00870 Rev.*K Page 8 of 56 S29AS008J 7. Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. S29AS008J Device Bus Operations DQ8-DQ15 Operation CE# OE# WE# RESET# WP# Addresses (Note 1) DQ0- DQ7 BYTE# = VIH BYTE# = VIL Read L L H H X AIN DOUT DOUT Write (Program/ Erase) L H L H (Note 3 ) AIN DIN DIN DQ8-DQ14 = HighZ, DQ15 = A-1 VCC 0.2 V X X VCC 0.2 V H X High-Z High-Z High-Z Output Disable L H H H X X High-Z High-Z High-Z Reset X X X L X X High-Z High-Z High-Z Sector Group Protect (Note 2) L H L VID X Sector Address, A6 = L, A3 = A2 = L, A1 = H, A0 = L DIN X X Sector Group Unprotect (Note 2) L H L VID H Sector Address, A6 = H, A3 = A2 = L, A1 = H, A0 = L DIN X X Temporary Sector Group Unprotect X X X VID H AIN DIN DIN High-Z Standby Legend L = Logic Low = VIL, H = Logic High = VIH, VID = 9.0-11.0 V, X = Don't Care, AIN = Address In, DIN = Data In, DOUT = Data Out Notes 1. Addresses are A18:A0 in word mode (BYTE# = VIH), A18:A-1 in byte mode (BYTE# = VIL). 2. The sector group protect and sector group unprotect functions may also be implemented via programming equipment. See Sector Group Protection/Unprotection on page 15. 3. If WP# = VIL, the two outermost boot sectors remain protected. If WP# = VIH, the two outermost boot sector group protection depends on whether they were last protected or unprotected. If WP# = VHH, all sectors are unprotected. 7.1 Word/Byte Configuration The BYTE# pin controls whether the device data I/O pins DQ15-DQ0 operate in the byte or word configuration. If the BYTE# pin is set at logic 1, the device is in word configuration, DQ15-DQ0 are active and controlled by CE# and OE#. If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. 7.2 Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The BYTE# pin determines whether the device outputs array data in words or bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. Document Number: 002-00870 Rev.*K Page 9 of 56 S29AS008J See Reading Array Data on page 25 for more information. Refer to the AC Read Operations on page 42 for timing specifications and to Figure 18.1 on page 42 for the timing diagram. ICC1 in DC Characteristics on page 40 represents the active current specification for reading array data. 7.3 Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. See Word/Byte Configuration on page 9 for more information. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. Word/Byte Program Command Sequence on page 26 has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table on page 13 and Table on page 13 indicate the address space that each sector occupies. A "sector address" consists of the address bits required to uniquely select a sector. The Command Definitions on page 25 has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7-DQ0. Standard read cycle timings apply in this mode. Refer to Autoselect Mode on page 11 and Autoselect Command Sequence on page 25 for more information. ICC2 in DC Characteristics on page 40 represents the active current specification for the write mode. AC Characteristics on page 42 contains timing specification tables and timing diagrams for write operations. 7.4 Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7-DQ0. Standard read cycle timings and ICC read specifications apply. Refer to Write Operation Status on page 34 for more information, and to AC Characteristics on page 42 for timing diagrams. 7.5 Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC 0.2 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC 0.2 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 and ICC4 represents the standby current specification shown in the table in DC Characteristics on page 40. 7.6 Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC5 in the DC Characteristics on page 40 represents the automatic sleep mode current specification. Document Number: 002-00870 Rev.*K Page 10 of 56 S29AS008J 7.7 RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the system drives the RESET# pin to VIL for at least a period of tRP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS0.2 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS0.2 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. Note that the CE# pin should only go to VIL after RESET# has gone to VIH. Keeping CE# at VIL from power up through the first read could cause the first read to retrieve erroneous data. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is 1), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the tables in AC Characteristics on page 42 for RESET# parameters and to Figure 18.2 on page 43 for the timing diagram. If VID (9.0 V - 11.0 V) is applied to the RESET# pin, the device will enter the Temporary Sector Group Unprotect mode. See Temporary Sector Group Unprotect on page 17 for more details on this feature. 7.8 Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. 7.9 Autoselect Mode The autoselect mode provides manufacturer and device identification, sector group protection verification, and Secured Silicon Sector status through identifier codes output on DQ7-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID (9.0 V to 11.0 V) on address pin A9. Address pins A6, A3, A2, A1, and A0 must be as shown in Table . In addition, when verifying sector group protection, the sector address must appear on the appropriate highest order address bits (see Table on page 13 and Table on page 13). Table shows the remaining address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table on page 30. This method does not require VID. See Command Definitions on page 25 for details on using the autoselect mode. Document Number: 002-00870 Rev.*K Page 11 of 56 S29AS008J S29AS008J Autoselect Codes (High Voltage Method) Description Manufacturer ID: Cypress Device ID CE# OE# WE# A18 to A12 A11 to A10 A9 A8 to A7 DQ8 to DQ15 A6 A5 to A4 A3 to A2 A1 BYTE BYTE A0 = VIH = VIL DQ7 to DQ0 L L H X X VID X L X L L L 00h X 01h Cycle 1 L L H X X VID X L X L L H 22h X 7Eh Cycle 2 L L H X X VID X L X H H L 22h X 04h Cycle 3 Sector Group Protection Verification L L H X X VID X L X H H H 22h X 04h (Top Boot), 03h (Bottom Boot) L L H SA X VID X L X L H L X X 01h (protected), 00h (unprotected) Secured Silicon Sector Indicator Bit (DQ7), WP# protects highest address sector L L H X X VID X L X L H H X X 89h (factory locked), 09h (not factory locked) Secured Silicon Sector Indicator Bit (DQ7), WP# protects lowest address sector L L H X X VID X L X L H H X X 91h (factory locked), 11h (not factory locked) Legend L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don't care Note The autoselect codes may also be accessed in-system via command sequences. See Table on page 30. Document Number: 002-00870 Rev.*K Page 12 of 56 S29AS008J 7.10 Sector Address Tables Sector Address Tables (Top Boot Device) Address Range (in hexadecimal) Sector A18 A17 A16 A15 A14 A13 A12 Sector Size (Kbytes/ Kwords) SA0 0 0 0 0 X X X 64/32 00000-0FFFF 00000-07FFF SA1 0 0 0 1 X X X 64/32 10000-1FFFF 08000-0FFFF SA2 0 0 1 0 X X X 64/32 20000-2FFFF 10000-17FFF SA3 0 0 1 1 X X X 64/32 30000-3FFFF 18000-1FFFF SA4 0 1 0 0 X X X 64/32 40000-4FFFF 20000-27FFF SA5 0 1 0 1 X X X 64/32 50000-5FFFF 28000-2FFFF SA6 0 1 1 0 X X X 64/32 60000-6FFFF 30000-37FFF SA7 0 1 1 1 X X X 64/32 70000-7FFFF 38000-3FFFF SA8 1 0 0 0 X X X 64/32 80000-8FFFF 40000-47FFF SA9 1 0 0 1 X X X 64/32 90000-9FFFF 48000-4FFFF SA10 1 0 1 0 X X X 64/32 A0000-AFFFF 50000-57FFF SA11 1 0 1 1 X X X 64/32 B0000-BFFFF 58000-5FFFF SA12 1 1 0 0 X X X 64/32 C0000-CFFFF 60000-67FFF SA13 1 1 0 1 X X X 64/32 D0000-DFFFF 68000-6FFFF SA14 1 1 1 0 X X X 64/32 E0000-EFFFF 70000-77FFF SA15 1 1 1 1 0 0 0 8/4 F0000-F1FFF 78000-78FFF SA16 1 1 1 1 0 0 1 8/4 F2000 - F3FFF 79000-79FFF SA17 1 1 1 1 0 1 0 8/4 F4000 - F5FFF 7A000-7AFFF SA18 1 1 1 1 0 1 1 8/4 F6000 - F7FFF 7B000-7BFFF SA19 1 1 1 1 1 0 0 8/4 F8000 - F9FFF 7C000-7CFFF SA20 1 1 1 1 1 0 1 8/4 FA000 - FBFFF 7D000-7DFFF SA21 1 1 1 1 1 1 0 8/4 FC000 - FDFFF 7E000-7EFFF SA22 1 1 1 1 1 1 1 8/4 FE000 - FFFFF 7F000-7FFFF Byte Mode (x8) Word Mode (x16) Note Address range is A18:A-1 in byte mode and A18:A0 in word mode. See Word/Byte Configuration on page 9. Sector Address Tables (Bottom Boot Device) Address Range (in hexadecimal) Sector A18 A17 A16 A15 A14 A13 A12 Sector Size (Kbytes/ Kwords) SA0 0 0 0 0 0 0 0 8/4 00000-01FFF 00000-00FFF SA1 0 0 0 0 0 0 1 8/4 02000-03FFF 01000-01FFF SA2 0 0 0 0 0 1 0 8/4 04000-05FFF 02000-02FFF SA3 0 0 0 0 0 1 1 8/4 06000-07FFF 03000-03FFF SA4 0 0 0 0 1 0 0 8/4 08000-09FFF 04000-04FFF SA5 0 0 0 0 1 0 1 8/4 0A000-0BFFF 05000-05FFF SA6 0 0 0 0 1 1 0 8/4 0C000-0DFFF 06000-06FFF SA7 0 0 0 0 1 1 1 8/4 0E000-0FFFF 07000-07FFF Document Number: 002-00870 Rev.*K Byte Mode (x8) Word Mode (x16) Page 13 of 56 S29AS008J Sector Address Tables (Bottom Boot Device) Sector A18 A17 A16 A15 A14 A13 A12 Sector Size (Kbytes/ Kwords) SA8 0 0 0 1 X X X 64/32 Address Range (in hexadecimal) Byte Mode (x8) Word Mode (x16) 10000-1FFFF 08000-0FFFF SA9 0 0 1 0 X X X 64/32 20000-2FFFF 10000-17FFF SA10 0 0 1 1 X X X 64/32 30000-3FFFF 18000-1FFFF SA11 0 1 0 0 X X X 64/32 40000-4FFFF 20000-27FFF SA12 0 1 0 1 X X X 64/32 50000-5FFFF 28000-2FFFF SA13 0 1 1 0 X X X 64/32 60000-6FFFF 30000-37FFF SA14 0 1 1 1 X X X 64/32 70000-7FFFF 38000-3FFFF SA15 1 0 0 0 X X X 64/32 80000-8FFFF 40000-47FFF SA16 1 0 0 1 X X X 64/32 90000-9FFFF 48000-4FFFF SA17 1 0 1 0 X X X 64/32 A0000-AFFFF 50000-57FFF SA18 1 0 1 1 X X X 64/32 B0000-BFFFF 58000-5FFFF SA19 1 1 0 0 X X X 64/32 C0000-CFFFF 60000-67FFF SA20 1 1 0 1 X X X 64/32 D0000-DFFFF 68000-6FFFF SA21 1 1 1 0 X X X 64/32 E0000-EFFFF 70000-77FFF SA22 1 1 1 1 X X X 64/32 F0000-FFFFF 78000-7FFFF Note Address range is A18:A-1 in byte mode and A18:A0 in word mode. See the Word/Byte Configuration on page 9. Document Number: 002-00870 Rev.*K Page 14 of 56 S29AS008J 7.11 Sector Group Protection/Unprotection The hardware sector group protection feature disables both program and erase operations in any sector group (see Table on page 13 to Table on page 15). The hardware sector group unprotection feature re-enables both program and erase operations in previously protected sector groups. Sector group protection/unprotection can be implemented via two methods. Sector group protection/unprotection requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 7.1 on page 16 shows the algorithms and Figure 18.11 on page 48 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector group unprotect, all unprotected sector groups must first be protected prior to the first sector group unprotect write cycle. The device is shipped with all sector groups unprotected. Cypress offers the option of programming and protecting sector groups at its factory prior to shipping the device through Cypress Programming Service. Contact a Cypress representative for details. It is possible to determine whether a sector group is protected or unprotected. See Autoselect Mode on page 11 for details. AS008J Top Boot Device Sector/Sector Group Protection Sector / Sector Block A18 A17 A16 A15 A14 A13 A12 Sector / Sector Block Size SA0-SA3 0 0 X X X X X 256 (4x64) Kbytes SA4-SA7 0 1 X X X X X 256 (4x64) Kbytes SA8-SA11 1 0 X X X X X 256 (4x64) Kbytes SA12-SA13 1 1 0 X X X X 128 (2x64) Kbytes SA14 1 1 1 0 X X X 64 Kbytes SA15 1 1 1 1 0 0 0 8 Kbytes SA16 1 1 1 1 0 0 1 8 Kbytes SA17 1 1 1 1 0 1 0 8 Kbytes SA18 1 1 1 1 0 1 1 8 Kbytes SA19 1 1 1 1 1 0 0 8 Kbytes SA20 1 1 1 1 1 0 1 8 Kbytes SA21 1 1 1 1 1 1 0 8 Kbytes SA22 1 1 1 1 1 1 1 8 Kbytes AS008J Bottom Boot Device Sector/Sector Group Protection Sector / Sector Block A18 A17 A16 A15 A14 A13 A12 Sector / Sector Block Size SA0 0 0 0 0 0 0 0 8 Kbytes SA1 0 0 0 0 0 0 1 8 Kbytes SA2 0 0 0 0 0 1 0 8 Kbytes SA3 0 0 0 0 0 1 1 8 Kbytes SA4 0 0 0 0 1 0 0 8 Kbytes SA5 0 0 0 0 1 0 1 8 Kbytes SA6 0 0 0 0 1 1 0 8 Kbytes SA7 0 0 0 0 1 1 1 8 Kbytes SA8 0 0 0 1 X X X 64 Kbytes SA9-SA10 0 0 1 X X X X 128 (2x64) Kbytes SA11-SA14 0 1 X X X X X 256 (4x64) Kbytes SA15-SA18 1 0 X X X X X 256 (4x64) Kbytes SA19-SA22 1 1 X X X X X 256 (4x64) Kbytes Document Number: 002-00870 Rev.*K Page 15 of 56 S29AS008J Figure 7.1 In-System Sector Group Protect/Unprotect Algorithms START RESET# = VID Wait 1 s Temporary Sector Group Unprotect Mode No START Protect all sectors: The indicated portion of the sector group protect algorithm must be performed for all unprotected sector group prior to issuing the first sector group unprotect address PLSCNT = 1 First Write Cycle = 60h? PLSCNT = 1 RESET# = VID Wait 1 s No First Write Cycle = 60h? Temporary Sector Group Unprotect Mode Yes Yes Set up sector address No All sectors protected? Sector Group Protect: Write 60h to sector address with A6 = 0, A3 = A2 = 0, A1 = 1, A0 = 0 Yes Set up first sector group address Sector Group Unprotect: Write 60h to sector address with A6 = 1, A1 = 1, A0 = 0 Wait 100 s Increment PLSCNT Verify Sector Group Protect: Write 40h to sector address with A6 = 0, A3 = A2 = 0, A1 = 1, A0 = 0 Reset PLSCNT = 1 Read from sector address with A6 = 0, A3 = A2 = 0, A1 = 1, A0 = 0 Wait 10 ms Verify Sector Group Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0 Increment PLSCNT Read from sector address with A6 = 1, A3 = A2 = 0, A1 = 1, A0 = 0 No No PLSCNT = 25? Data = 01h? No Yes Yes Device failed Set up next sector address Yes PLSCNT = 1000? Protect another sector? No Yes Data = 00h? Yes No Remove VID from RESET# Device failed Last sector group verified? No Yes Sector Group Protect Algorithm Write reset command Sector Group Protect complete Sector Group Unprotect Algorithm Note 1. If WP# = VIL, the top or bottom two address sectors remains protected for boot sector devices Document Number: 002-00870 Rev.*K Remove VID from RESET# Write reset command Sector Group Unprotect complete Page 16 of 56 S29AS008J 7.12 Temporary Sector Group Unprotect This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Group Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 7.2 shows the algorithm, and Figure 18.10 on page 48 shows the timing diagrams, for this feature. If the WP# pin is at VIL, the sectors protected by the WP# input will remain protected during the Temporary Sector Group Unprotect mode. Figure 7.2 Temporary Sector Group Unprotect Operation START RESET# = VID (Note 1) Perform Erase or Program Operations RESET# = VIH Temporary Sector Group Unprotect Completed (Note 2) Notes 1. All protected sector groups unprotected. 2. All previously protected sector groups are protected once again. 7.13 Write Protect (WP#) The Write Protect function provides a hardware method of protecting certain boot sectors without using VID. This function is one of two provided by the WP# pin. If the system asserts VIL on the WP# pin, the device disables program and erase functions in the two outermost 8-Kbyte boot sectors independently of whether those sectors were protected or unprotected using the method described in Section 7.11, Sector Group Protection/Unprotection on page 15. The two outermost 8-Kbyte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-configured device. If the system asserts VIH on the WP# pin, the device reverts to whether the two outermost 8-KByte boot sectors were last set to be protected or unprotected. That is, sector group protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in Section 7.11. The WP# contains an internal pull-up; when unconnected, WP is at VIH. Document Number: 002-00870 Rev.*K Page 17 of 56 S29AS008J 7.14 Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table on page 30 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. 7.14.1 Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. 7.14.2 Write Pulse Glitch Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. 7.14.3 Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero (VIL) while OE# is a logical one (VIH). 7.14.4 Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up. 8. Secured Silicon Sector Flash Memory Region The Secured Silicon Sector feature provides a 256-byte Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The Secured Silicon Sector uses a Secured Silicon Sector Indicator Bit (DQ7) to indicate whether or not the Secured Silicon Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory-locked part. This ensures the security of the ESN once the product is shipped to the field. Cypress offers the device with the Secured Silicon Sector either factory-locked or customer-lockable. The factory-locked version is always protected when shipped from the factory, and has the Secured Silicon Sector Indicator Bit permanently set to a 1. The customer-lockable version is shipped with the Secured Silicon Sector group unprotected, allowing customers to utilize the that sector in any manner they choose. The customer-lockable version has the Secured Silicon Sector Indicator Bit permanently set to a 0. Thus, the Secured Silicon Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. The system accesses the Secured Silicon Sector through a command sequence (see Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence on page 26). After the system writes the Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors. Document Number: 002-00870 Rev.*K Page 18 of 56 S29AS008J 8.1 Factory Locked: Secured Silicon Sector Programmed and Protected at the Factory In a factory locked device, the Secured Silicon Sector is protected when the device is shipped from the factory. The Secured Silicon Sector cannot be modified in any way. The device is available pre-programmed with one of the following: A random, secure ESN only. Customer code through the ExpressFlash service. Both a random, secure ESN and customer code through the ExpressFlash service. In devices that have an ESN, a Bottom Boot device has the 16-byte (8-word) ESN in sector 0 at addresses 00000h-0000Fh in byte mode (or 00000h-00007h in word mode). In the Top Boot device, the ESN is in sector 22 at addresses FFFF0h-FFFFFh in byte mode (or 7FFF8h-7FFFFh in word mode). Customers may opt to have their code programmed by Cypress through the Cypress ExpressFlash service. Cypress programs the customer's code, with or without the random ESN. The devices are then shipped from the Cypress factory with the Secured Silicon Sector permanently locked. Contact a Cypress representative for details on using the Cypress ExpressFlash service. 8.2 Customer Lockable: Secured Silicon Sector NOT Programmed or Protected at the Factory The customer lockable version allows the Secured Silicon Sector to be programmed once, and then permanently locked after it ships from Cypress. Note that unlock bypass functions are not available when programming the Secured Silicon Sector. The Secured Silicon Sector area can be protected using the following procedures: Write the three-cycle Enter Secured Silicon Region command sequence, and then follow the in-system sector group protect algorithm as shown in Figure 7.1 on page 16, substituting the sector group address with the Secured Silicon Sector group address (A0=0, A1=1, A2=0, A3=1, A4=1, A5=0, A6=0, A7=0). This allows in-system protection of the Secured Silicon Sector without raising any device pin to a high voltage. Note that this method is only applicable to the Secured Silicon Sector. To verify the protect/unprotect status of the Secured Silicon Sector, follow the algorithm shown in Figure 8.1 on page 20. Once the Secured Silicon Sector is locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence to return to reading and writing the remainder of the array. The Secured Silicon Sector protection must be used with caution since, once protected, there is no procedure available for unprotecting the Secured Silicon Sector area, and none of the bits in the Secured Silicon Sector memory space can be modified in any way. Document Number: 002-00870 Rev.*K Page 19 of 56 S29AS008J Figure 8.1 Secured Silicon Sector Protect Verify START RESET# = VID Wait 1 ms Write 60h to any address Write 40h to Secured Silicon Sector address with A0=0, A1=1, A2=0, A3=1, A4=1, A5=0, A6=0, A7=0 Read from Secured Silicon Sector address with A0=0, A1=1 A2=0, A3=1, A4=1 A5=0, A6=0, A7=0 Document Number: 002-00870 Rev.*K If data = 00h, Secured Silicon Sector is unprotected. If data = 01h, Secured Silicon Sector is protected. Remove VID from RESET# Write reset command Secured Silicon Sector Protect Verify complete Page 20 of 56 S29AS008J 9. Common Flash Memory Interface (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be deviceindependent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Table to Table on page 23. In word mode, the upper address bits (A7-MSB) must be all zeros. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Table to Table on page 23. The system must write the reset command to return the device to the autoselect mode. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http:// www.amd.com/products/nvd/overview/cfi.html. Alternatively, contact a Cypress representative for copies of these documents. CFI Query Identification String Addresses (Word Mode) Addresses (Byte Mode) Data 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h Query Unique ASCII string "QRY" 13h 14h 26h 28h 0002h 0000h Primary OEM Command Set 15h 16h 2Ah 2Ch 0040h 0000h Address for Primary Extended Table 17h 18h 2Eh 30h 0000h 0000h Alternate OEM Command Set (00h = none exists) 19h 1Ah 32h 34h 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) Document Number: 002-00870 Rev.*K Description Page 21 of 56 S29AS008J System Interface String Addresses (Word Mode) Addresses (Byte Mode) Data Description 1Bh 36h 0017h VCC Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt 1Ch 38h 0019h VCC Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt 1Dh 3Ah 0000h VPP Min. voltage (00h = no VPP pin present) 1Eh 3Ch 0000h VPP Max. voltage (00h = no VPP pin present) 1Fh 3Eh 0003h Typical timeout per single byte/word write 2N s 20h 40h 0000h Typical timeout for Min. size buffer write 2N s (00h = not supported) 21h 42h 0009h Typical timeout per individual block erase 2N ms 22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supported) 23h 46h 0005h Max. timeout for byte/word write 2N times typical 24h 48h 0000h Max. timeout for buffer write 2N times typical 25h 4Ah 0004h Max. timeout per individual block erase 2N times typical 26h 4Ch 0000h Max. timeout for full chip erase 2N times typical (00h = not supported) Device Geometry Definition Addresses (Word Mode) Addresses (Byte Mode) Data Description N 27h 4Eh 0014h Device Size = 2 byte 28h 29h 50h 52h 0002h 0000h Flash Device Interface description (refer to CFI publication 100) 2Ah 2Bh 54h 56h 0000h 0000h Max. number of byte in multi-byte write = 2N (00h = not supported) 2Ch 58h 0002h Number of Erase Block Regions within device 2Dh 2Eh 2Fh 30h 5Ah 5Ch 5Eh 60h 0007h 0000h 0020h 0000h Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) 31h 32h 33h 34h 62h 64h 66h 68h 000Eh 0000h 0000h 0001h Erase Block Region 2 Information 35h 36h 37h 38h 6Ah 6Ch 6Eh 70h 0000h 0000h 0000h 0000h Erase Block Region 3 Information 39h 3Ah 3Bh 3Ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h Erase Block Region 4 Information Document Number: 002-00870 Rev.*K Page 22 of 56 S29AS008J Primary Vendor-Specific Extended Query Addresses (Word Mode) Addresses (Byte Mode) Data 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h Query-unique ASCII string "PRI" 43h 86h 0031h Major version number, ASCII 44h 88h 0033h Minor version number, ASCII 45h 8Ah 000Ch Address Sensitive Unlock 0 = Required 1 = Not Required Description 46h 8Ch 0002h Erase Suspend 0 = Not Supported 1 = To Read Only 2 = To Read & Write 47h 8Eh 0001h Sector Group Protect 0 = Not Supported X = Number of sectors in smallest sector group 48h 90h 0001h Sector Group Temporary Unprotect 00 = Not Supported 01 = Supported 49h 92h 0004h Sector Group Protect/Unprotect scheme 01 = 29F040 mode 02 = 29F016 mode 03 = 29F400 mode 04 = 29LV800A mode 4Ah 94h 0000h Simultaneous Operation 00 = Not Supported 01 = Supported 4Bh 96h 0000h Burst Mode Type 00 = Not Supported 01 = Supported 0000h Page Mode Type 00 = Not Supported 01 = 4 Word Page 02 = 8 Word Page 0000h ACC (Acceleration) Supply Minimum 00 = Not Supported D7-D4: Volt D3-D0: 100 mV 0000h ACC (Acceleration) Supply Maximum 00 = Not Supported D7-D4: Volt D3-D0: 100 mV 4Ch 4Dh 4Eh 98h 9Ah 9Ch Document Number: 002-00870 Rev.*K Page 23 of 56 S29AS008J Primary Vendor-Specific Extended Query (Continued) Addresses (Word Mode) Addresses (Byte Mode) Data Description 4Fh 9Eh 00XXh WP# Protection 02 = Bottom Boot Device with WP Protect 03 = Top Boot Device with WP Protect 50h A0h 0000h Program Suspend 00 = Not Supported 01 = Supported Document Number: 002-00870 Rev.*K Page 24 of 56 S29AS008J 10. Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. Table on page 30 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in AC Characteristics on page 42. 10.1 Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See Erase Suspend/Erase Resume Commands on page 28 for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See Reset Command on page 25. See also Requirements for Reading Array Data on page 9 for more information. The Read Operations on page 42 provides the read parameters, and Figure 18.1 on page 42 shows the timing diagram. 10.2 Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don't care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend). 10.3 Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. Table on page 30 shows the address and data requirements. This method is an alternative to that shown in Table on page 12, which is intended for PROM programmers and requires VID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h in word mode (or 04h in byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Table on page 13 and Table on page 13 for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. Document Number: 002-00870 Rev.*K Page 25 of 56 S29AS008J 10.4 Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence The Secured Silicon Sector region provides a secured data area containing a random, sixteen-byte electronic serial number (ESN). The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence. The Exit Secured Silicon Sector command sequence returns the device to normal operation. Table shows the addresses and data requirements for both command sequences. Note that the unlock bypass mode is not available when the device enters the Secured Silicon Sector. For further information, see Secured Silicon Sector Flash Memory Region on page 18. 10.5 Word/Byte Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically generates the program pulses and verifies the programmed cell margin. Table on page 30 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See Write Operation Status on page 34 for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The Byte Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a 0 back to a 1. Attempting to do so may halt the operation and set DQ5 to 1, or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still 0. Only erase operations can convert a 0 to a 1. 10.6 Unlock Bypass Command Sequence The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table on page 30 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the data F0h. Addresses are don't care for both cycles. The device then returns to reading array data. Figure 10.1 on page 27 illustrates the algorithm for the program operation. See Erase/Program Operations on page 45 for parameters, and to Figure 18.5 on page 46 for timing diagrams. Document Number: 002-00870 Rev.*K Page 26 of 56 S29AS008J Figure 10.1 Program Operation START Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Yes Increment Address No Last Address? Yes Programming Completed Note See Table on page 30 for program command sequence. 10.7 Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table on page 30 shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See Write Operation Status on page 34 for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 10.2 on page 29 illustrates the algorithm for the erase operation. See Erase/Program Operations on page 45 for parameters, and Figure 18.6 on page 46 for timing diagrams. Document Number: 002-00870 Rev.*K Page 27 of 56 S29AS008J 10.8 Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. Table on page 30 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 s begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out. (See DQ3: Sector Erase Timer on page 38.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. Note that a hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. (Refer to Write Operation Status on page 34 for information on these status bits.) Figure 10.2 on page 29 illustrates the algorithm for the erase operation. Refer to Erase/Program Operations on page 45 for parameters, and to Figure 18.6 on page 46 for timing diagrams. 10.9 Erase Suspend/Erase Resume Commands The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are don't-cares when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 35 s to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See Write Operation Status on page 34 for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status on page 34 for more information. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence on page 25 for more information. Document Number: 002-00870 Rev.*K Page 28 of 56 S29AS008J The system must write the Erase Resume command (address bits are don't care) to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing. Figure 10.2 Erase Operation START Write Erase Command Sequence Data Poll from System Embedded Erase algorithm in progress No Data = FFh? Yes Erasure Completed Notes 1. See Table on page 30 for erase command sequence. 2. See DQ3: Sector Erase Timer on page 38 for more information. Document Number: 002-00870 Rev.*K Page 29 of 56 S29AS008J 11. Command Definitions Command Sequence (Note 1) Cycles S29AS008J Command Definitions (Word Mode) Bus Cycles (Notes 2-5) First Second Third Addr Data Addr Data Addr Data Fourth Fifth Addr Data Sixth Addr Data Addr Data 1 RA RD Reset (Note 7) 1 XXX F0 Manufacturer ID 4 555 AA 2AA 55 555 90 X00 01 Device ID, Top Boot Block 6 555 AA 2AA 55 555 90 X01 227E X0E 2204 X0F 2204 Device ID, Bottom Boot Block 6 555 AA 2AA 55 555 90 X01 227E X0E 2204 X0F 2203 Secured Silicon Sector Factory Protect, Top Boot (Note 9) 4 555 AA 2AA 55 555 90 X03 0089/ 0009 Secured Silicon Sector Factory Protect, Bottom Boot (Note 9) 4 555 AA 2AA 55 555 90 X03 0091/ 0011 Sector Group Protect Verify (Note 10) 4 555 AA 2AA 55 555 90 (SA)X02 XX00/ XX01 Enter Secured Silicon Sector 3 555 AA 2AA 55 555 88 Exit Secured Silicon Sector 4 555 AA 2AA 55 555 90 XXX 00 CFI Query (Note 11) 1 55 98 PA PD Autoselect (Note 8) Read (Note 6) Program 4 555 AA 2AA 55 555 A0 Unlock Bypass 3 555 AA 2AA 55 555 20 Unlock Bypass Program (Note 12) 2 XXX A0 PA PD Unlock Bypass Reset (Note 13) 2 XXX 90 XXX F0 Chip Erase 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 2AA 55 555 80 555 AA 2AA 55 SA 30 6 Sector Erase 6 555 AA Erase Suspend (Note 14) 1 XXX B0 Erase Resume (Note 15) 1 XXX 30 Legend X = Don't care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. Document Number: 002-00870 Rev.*K PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A18-A12 uniquely select any sector. Page 30 of 56 S29AS008J Notes 1. See Table on page 9 for description of bus operations. 2. All values are in hexadecimal. 10. The data is 00h for an unprotected sector and 01h for a protected sector. See Autoselect Command Sequence on page 25 for more information. 3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 11. Command is valid when device is ready to read array data or when device is in autoselect mode. 4. Data bits DQ15-DQ8 are don't cares for unlock and command cycles. 12. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 5. Address bits A18-A11 are don't cares for unlock and command cycles, unless SA or PA required. 6. No unlock or command cycles required when reading array data. 7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data). 8. The fourth cycle of the autoselect command sequence is a read cycle. 13. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. F0 is also acceptable. 14. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 15. The Erase Resume command is valid only during the Erase Suspend mode. 9. For top boot, 89h = factory locked, 09h = not factory locked. For bottom boot, 91h = factory locked, 11h = not factory locked. Document Number: 002-00870 Rev.*K Page 31 of 56 S29AS008J S29AS008J Command Definitions (Byte Mode) Command Sequence (Note 1) Cycles Bus Cycles (Notes 2-5) First Addr Dat a Second Third Addr Data Addr Data Fourth Fifth Addr Data Sixth Addr Data Addr Data 1 RA RD 1 XXX F0 Manufacturer ID 4 AAA AA 555 55 AAA 90 X00 01 Device ID, Top Boot Block 6 AAA AA 555 55 AAA 90 X02 7E X1C 04 X1E 04 Device ID, Bottom Boot Block 6 AAA AA 555 55 AAA 90 X02 7E X1C 04 X1E 03 Secured Silicon Sector Factory Protect, Top Boot (Note 9) 4 AAA AA 555 55 AAA 90 X06 89/09 Secured Silicon Sector Factory Protect, Bottom Boot (Note 9) 4 AAA AA 555 55 AAA 90 X06 91/11 Sector Group Protect Verify (Note 10) 4 AAA AA 555 55 AAA 90 (SA)X04 00/01 Enter Secured Silicon Sector 3 AAA AA 555 55 AAA 88 Exit Secured Silicon Sector 4 AAA AA 555 55 AAA 90 XXX 00 CFI Query (Note 11) 1 AA 98 Program 4 AAA AA 555 55 AAA A0 PA PD Unlock Bypass 3 AAA AA 555 55 AAA 20 Unlock Bypass Program (Note 12) 2 XXX A0 PA PD Unlock Bypass Reset (Note 13) 2 XXX 90 XXX F0 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10 555 55 AAA 80 AAA AA 555 55 SA 30 Autoselect (Note 8) Read (Note 6) Reset (Note 7) Chip Erase Sector Erase 6 AAA AA Erase Suspend (Note 14) 1 XXX B0 Erase Resume (Note 15) 1 XXX 30 Legend X = Don't care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. Document Number: 002-00870 Rev.*K PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A18-A12 uniquely select any sector. Page 32 of 56 S29AS008J Notes 1. See Table on page 9 for description of bus operations. 2. All values are in hexadecimal. 10. The data is 00h for an unprotected sector and 01h for a protected sector. See Autoselect Command Sequence on page 25 for more information. 3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 11. Command is valid when device is ready to read array data or when device is in autoselect mode. 4. Data bits DQ15-DQ8 are don't cares for unlock and command cycles. 12. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 5. Address bits A18-A11 are don't cares for unlock and command cycles, unless SA or PA required. 6. No unlock or command cycles required when reading array data. 7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data). 8. The fourth cycle of the autoselect command sequence is a read cycle. 13. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. F0 is also acceptable. 14. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 15. The Erase Resume command is valid only during the Erase Suspend mode. 9. For top boot, 89h = factory locked, 09h = not factory locked. For bottom boot, 91h = factory locked, 11h = not factory locked. Document Number: 002-00870 Rev.*K Page 33 of 56 S29AS008J 12. Write Operation Status The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table on page 38 and the following subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. 12.1 DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 s, then the device returns to reading array data. During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7. This is analogous to the complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to 1; prior to this, the device outputs the complement, or 0. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 s, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. When the system detects DQ7 has changed from the complement to true data, it can read valid data (at DQ7-DQ0 in byte mode or DQ15-DQ0 in word mode) on the following read cycles. This is because DQ7 may change asynchronously with DQ0-DQ6 while Output Enable (OE#) is asserted low. Figure 18.7 on page 47, illustrates this. Table on page 38 shows the outputs for Data# Polling on DQ7. Figure 12.2 on page 37 shows the Data# Polling algorithm. Document Number: 002-00870 Rev.*K Page 34 of 56 S29AS008J Figure 12.1 Data# Polling Algorithm START Read DQ7-DQ0 Addr = VA DQ7 = Data? Yes No No DQ5 = 1? Yes Read DQ7-DQ0 Addr = VA DQ7 = Data? Yes No FAIL PASS Notes 1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5. 12.2 RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table on page 38 shows the outputs for RY/BY#. Figures Figure 18.1 on page 42, Figure 18.2 on page 43, Figure 18.5 on page 46 and Figure 18.6 on page 46 shows RY/BY# for read, reset, program, and erase operations, respectively. Document Number: 002-00870 Rev.*K Page 35 of 56 S29AS008J 12.3 DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erasesuspended. Alternatively, the system can use DQ7 (see DQ7: Data# Polling on page 34). If a program address falls within a protected sector, DQ6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table on page 38 shows the outputs for Toggle Bit I on DQ6. Figure 12.2 on page 37 shows the toggle bit algorithm in flowchart form, and Reading Toggle Bits DQ6/DQ2 on page 37 explains the algorithm. Figure 18.8 on page 47 shows the toggle bit timing diagrams. Figure 18.9 on page 47 shows the differences between DQ2 and DQ6 in graphical form. See also DQ2: Toggle Bit II on page 36. 12.4 DQ2: Toggle Bit II The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erasesuspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table on page 38 to compare outputs for DQ2 and DQ6. Figure 12.2 on page 37 shows the toggle bit algorithm in flowchart form, and the section Reading Toggle Bits DQ6/DQ2 on page 37 explains the algorithm. See also DQ6: Toggle Bit I on page 36. Figure 18.8 on page 47 shows the toggle bit timing diagram. Figure 18.9 on page 47 shows the differences between DQ2 and DQ6 in graphical form. Document Number: 002-00870 Rev.*K Page 36 of 56 S29AS008J 12.5 Reading Toggle Bits DQ6/DQ2 Refer to Figure 12.2 on page 37 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data (at DQ7-DQ0 in byte mode or DQ15-DQ0 in word mode) on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see DQ5: Exceeded Timing Limits on page 38). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 12.2 on page 37). Figure 12.2 Toggle Bit Algorithm START (Note 1) Read DQ7-DQ0 Read DQ7-DQ0 Toggle Bit = Toggle? No Yes No DQ5 = 1? Yes (Notes 1, 2) Read DQ7-DQ0 Twice Toggle Bit = Toggle? No Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete Notes 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to 1. See text. Document Number: 002-00870 Rev.*K Page 37 of 56 S29AS008J 12.6 DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a 1. This is a failure condition that indicates the program or erase cycle was not successfully completed. The DQ5 failure condition may appear if the system tries to program a 1 to a location that is previously programmed to 0. Only an erase operation can change a 0 back to a 1. Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a 1. Under both these conditions, the system must issue the reset command to return the device to reading array data. 12.7 DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from 0 to 1. The system may ignore DQ3 if the system can guarantee that the time between additional sector erase commands will always be less than 50 s. See also Sector Erase Command Sequence on page 28. After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read DQ3. If DQ3 is 1, the internally controlled erase cycle has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 0, the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table shows the outputs for DQ3. Write Operation Status DQ7 (Note 2) DQ6 DQ5 (Note 1) DQ3 DQ2 (Note 2) RY/BY# DQ7# Toggle 0 N/A No toggle 0 Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0 Reading within Erase Suspended Sector 1 No toggle 0 N/A Toggle 1 Reading within Non-Erase Suspended Sector Data Data Data Data Data 1 Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0 Operation Standard Mode Erase Suspend Mode Embedded Program Algorithm Notes 1. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See DQ5: Exceeded Timing Limits on page 38 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. Document Number: 002-00870 Rev.*K Page 38 of 56 S29AS008J 13. Absolute Maximum Ratings Storage Temperature Plastic Packages -65C to +150C Ambient Temperature with Power Applied -65C to +125C Voltage with Respect to Ground VCC (Note 1) -0.5 V to +2.0 V A9, RESET# (Note 2) -0.5 V to +11.0 V All other pins (Note 1) -0.5 V to VCC+0.5 V Output Short Circuit Current (Note 3) 200 mA Notes 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 14.1 on page 39. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 14.2 on page 39. 2. Minimum DC input voltage on pins A9, OE#, and RESET# is -0.5 V. During voltage transitions, A9 and RESET# may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 14.1 on page 39. Maximum DC input voltage on pin A9 is +11.0 V which may overshoot to 12.5 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 4. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 14. Operating Ranges Description Range Ambient Temperature (TA) Industrial (I) Devices -40C to +85C VCC Supply Voltages Standard Voltage Range 1.65 V to 1.95 V Note Operating ranges define those limits between which the functionality of the device is guaranteed. Figure 14.1 Maximum Negative Overshoot Waveform 20 ns 20 ns +0.8 V -0.5 V -2.0 V 20 ns Figure 14.2 Maximum Positive Overshoot Waveform 20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns Document Number: 002-00870 Rev.*K Page 39 of 56 S29AS008J 15. DC Characteristics 15.1 CMOS Compatible Parameter ILI ILI ILO ICC1 Description Test Conditions Min Typ Max Input Load Current VIN = VSS to VCC, VCC = VCC max 1.0 WP# Input Load Current VCC = VCC max; WP# = VSS0.2 V -15 A9, RESET# Input Load Current VCC = VCC max; A9, RESET# = 11.0 V 35 Output Leakage Current VOUT = VSS to VCC, VCC = VCC max VCC Active Read Current (Note 1) CE# = VIL, OE# = VIH, Byte Mode CE# = VIL, OE# = VIH, Word Mode Unit A 1.0 5 MHz 8 12 1 MHz 2 4 5 MHz 8 12 1 MHz 2 4 mA ICC2 VCC Active Write Current (Notes 2, 3) CE# = VIL, OE# = VIH 20 30 mA ICC3 VCC Standby Current CE#, RESET# = VCC0.2 V 8 30 A ICC4 VCC Standby Current During Reset RESET# = VSS 0.2 V 8 30 A ICC5 Automatic Sleep Mode (Note 4) VIH = VCC 0.2 V; VIL = VSS 0.2 V 15 70 A VIL Input Low Voltage -0.5 0.3 x VCC VIH Input High Voltage 0.7 x VCC VCC + 0.3 VID Voltage for Autoselect and Temporary Sector Group Unprotect VCC = 1.65 to 1.95 V 9.0 11.0 VOL Output Low Voltage IOL = 2.0 mA, VCC = VCC min VOH1 VOH2 VLKO Output High Voltage 0.25 IOH = -2.0 mA, VCC = VCC min 0.85 x VCC IOH = -100 A, VCC = VCC min VCC-0.1 Low VCC Lock-Out Voltage (Note 3) 1.2 V 1.4 Notes 1. The ICC current listed is typically less than 1 mA/MHz, with OE# at VIH. 2. ICC active while Embedded Erase or Embedded Program is in progress. 3. Not 100% tested. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 15 A. Document Number: 002-00870 Rev.*K Page 40 of 56 S29AS008J 16. Test Conditions Figure 16.1 Test Setup Device Under Test CL Test Specifications Test Condition Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels 70 Unit 100 pF 3 ns 0.0 - 2.0 Input timing measurement reference levels 1.0 Output timing measurement reference levels 1.0 V 17. Key to Switching Waveforms Waveform Inputs Outputs Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) Figure 17.1 Input Waveforms and Measurement Levels Vcc Input Vcc/2 Measurement Level Vcc/2 Output 0.0 V Document Number: 002-00870 Rev.*K Page 41 of 56 S29AS008J 18. AC Characteristics 18.1 Read Operations Speed Options Parameter JEDEC Std tAVAV tRC Read Cycle Time (Note 1) tAVQV tACC Address to Output Delay tELQV tCE Chip Enable to Output Delay tGLQV tOE tEHQZ tGHQZ tAXQX Description Test Setup 70 Min 70 CE# = VIL OE# = VIL Max 70 OE# = VIL Max 70 Output Enable to Output Delay Max 25 tDF Chip Enable to Output High Z (Note 1) Max 25 tDF Output Enable to Output High Z (Note 1) Max 25 Read Min 0 Toggle and Data# Polling Min 10 Min 0 tOEH Output Enable Hold Time (Note 1) tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1) Unit ns Notes 1. Not 100% tested. 2. See Figure 16.1 on page 41 and Table on page 41 for test specifications. Figure 18.1 Read Operations Timings tRC Addresses Stable Addresses tACC CE# OE# tDF tOE tSR/W tOEH WE# tCE HIGH Z Outputs tOH Output Valid HIGH Z RESET# RY/BY# 0V Document Number: 002-00870 Rev.*K Page 42 of 56 S29AS008J 18.2 Hardware Reset (RESET#) Parameter JEDEC Std Description Test Setup All Speed Options Unit s tREADY RESET# Pin Low (During Embedded Algorithms) to Read or Write (See Note) Max 35 tREADY RESET# Pin Low (NOT During Embedded Algorithms) to Read or Write (See Note) Max 500 tRP RESET# Pulse Width 500 tRH RESET# High Time Before Read (See Note) tRPD RESET# Low to Standby Mode tRB RY/BY# Recovery Time ns 50 Min 20 s 0 ns Note Not 100% tested. Figure 18.2 RESET# Timings RY/BY# CE#, OE# tRH RESET# tRP tReady Reset Timings NOT during Embedded Algorithms (Note 1) Reset Timings during Embedded Algorithms tReady RY/BY# tRB CE#, OE# RESET# tRP Note 1. CE# should only go low after RESET# has gone high. Keeping CE# low from power-up through the first read could cause the first read to retrieve erroneous data. Document Number: 002-00870 Rev.*K Page 43 of 56 S29AS008J 18.3 Word/Byte Configuration (BYTE#) Parameter JEDEC Speed Options Std Description tELFL/tELFH 70 CE# to BYTE# Switching Low or High Max 5 tFLQZ BYTE# Switching Low to Output HIGH Z Max 25 tFHQV BYTE# Switching High to Output Active Min 70 Unit ns Figure 18.3 BYTE# Timings for Read Operations CE# OE# BYTE# BYTE# Switching from word to byte mode tELFL Data Output (DQ0-DQ7) Data Output (DQ0-DQ14) DQ0-DQ14 Address Input DQ15 Output DQ15/A-1 tFLQZ tELFH BYTE# BYTE# Switching from byte to word mode Data Output (DQ0-DQ7) DQ0-DQ14 Address Input DQ15/A-1 Data Output (DQ0-DQ14) DQ15 Output tFHQV Figure 18.4 BYTE# Timings for Write Operations CE# The falling edge of the last WE# signal WE# BYTE# tSET (tAS) tHOLD (tAH) Note Refer to Erase/Program Operations on page 45 for tAS and tAH specifications. Document Number: 002-00870 Rev.*K Page 44 of 56 S29AS008J 18.4 Erase/Program Operations Parameter Speed Options JEDEC Std Description 70 tAVAV tWC Write Cycle Time (Note 1) 70 tAVWL tAS Address Setup Time 0 tWLAX tAH Address Hold Time 45 tDVWH tDS Data Setup Time 35 tWHDX tDH Data Hold Time 0 tOES Output Enable Setup Time Min 0 Read Recovery Time Before Write (OE# High to WE# Low) 0 0 tGHWL tGHWL tELWL tCS CE# Setup Time tWHEH tCH CE# Hold Time 0 tWLWH tWP Write Pulse Width 35 tWHWL tWPH Write Pulse Width High 20 tSR/W Latency Between Read and Write Operations tWHWH1 tWHWH1 Programming Operation (Note 2) tWHWH2 tWHWH2 Sector Erase Operation (Note 2) tVCS VCC Setup Time (Note 1) tRB Recovery Time from RY/BY# tBUSY Program/Erase Valid to RY/BY# Delay Min 20 Typ 6 Byte Word 6 Min Max Unit ns ns s 0.5 sec 50 s 0 90 ns Notes 1. Not 100% tested. 2. See Erase and Programming Performance on page 51 for more information. Document Number: 002-00870 Rev.*K Page 45 of 56 S29AS008J Figure 18.5 Program Operation Timings Read Status Data (last two cycles) Program Command Sequence (last two cycles) tAS tWC Addresses 555h PA PA PA tAH CE# tCH OE# tWHWH1 tWP WE# tWPH tCS tDS tDH PD A0h Data Status DOUT tBUSY tRB RY/BY# tVCS VCC Notes 1. PA = program address, PD = program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode. Figure 18.6 Chip/Sector Erase Operation Timings Erase Command Sequence (last two cycles) tAS tWC 2AAh Addresses Read Status Data VA SA VA 555h for chip erase tAH CE# tCH OE# tWP WE# tWPH tCS tWHWH2 tDS tDH Data 55h In Progress 30h Complete 10 for Chip Erase tBUSY tRB RY/BY# tVCS VCC Notes 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 34). 2. Illustration shows device in word mode. Document Number: 002-00870 Rev.*K Page 46 of 56 S29AS008J Figure 18.7 Data# Polling Timings (During Embedded Algorithms) tRC Addresses VA VA VA tACC tCE CE# tCH tOE OE# tOEH tDF WE# tOH High Z DQ7 Complement Complement Status Data Status Data Valid Data True High Z DQ0-DQ6 Valid Data True tBUSY RY/BY# Note VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Figure 18.8 Toggle Bit Timings (During Embedded Algorithms) tRC Addresses VA VA VA VA tACC tCE CE# tCH tOE OE# tOEH tDF WE# tOH High Z DQ6/DQ2 tBUSY Valid Status Valid Status (first read) (second read) Valid Status Valid Data (stops toggling) RY/BY# Note VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. Figure 18.9 DQ2 vs. DQ6 for Erase and Erase Suspend Operations Enter Embedded Erasing WE# Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Read Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete DQ6 DQ2 Note The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector. Document Number: 002-00870 Rev.*K Page 47 of 56 S29AS008J 18.5 Temporary Sector Group Unprotect Parameter JEDEC Std Description All Speed Options Unit tVIDR VID Rise and Fall Time (See Note) Min 500 ns tRSP RESET# Setup Time for Temporary Sector Group Unprotect Min 4 s Note Not 100% tested. Figure 18.10 Temporary Sector Group Unprotect/Timing Diagram 11 V RESET# 0 or 1.95 V tVIDR tVIDR Program or Erase Command Sequence CE# WE# tRSP RY/BY# Figure 18.11 Sector Group Protect/Unprotect Timing Diagram VID VIH RESET# SA, A6, A1, A0 Valid* Valid* Sector Group Protect/Unprotect Data 60h 1 s Valid* Verify 60h 40h Status Sector Group Protect: 150 s Sector Group Unprotect: 15 ms CE# WE# OE# Note For sector group protect, A6 = 0, A1 = 1, A0 = 0. For sector group unprotect, A6 = 1, A1 = 1, A0 = 0. Document Number: 002-00870 Rev.*K Page 48 of 56 S29AS008J 18.6 Alternate CE# Controlled Erase/Program Operations Parameter Speed Options JEDEC Std Description 70 Unit tAVAV tWC Write Cycle Time (Note 1) Min 70 ns tAVEL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 ns tDVEH tDS Data Setup Time Min 35 ns tEHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 35 ns tEHEL tCPH CE# Pulse Width High Min 20 ns tSR/W Latency Between Read and Write Operations Min 20 ns tWHWH1 tWHWH1 Programming Operation (Note 2) tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Byte Typ 6 Word Typ 6 Typ 0.5 s sec Notes 1. Not 100% tested. 2. See Erase and Programming Performance on page 51 for more information. Document Number: 002-00870 Rev.*K Page 49 of 56 S29AS008J Figure 18.12 Alternate CE# Controlled Write Operation Timings 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase Data# Polling Addresses PA tWC tAS tAH tWH WE# tGHEL OE# tCP CE# tWS tWHWH1 or 2 tCPH tBUSY tDS tDH DQ7# Data tRH A0 for program 55 for erase DOUT PD for program 30 for sector erase 10 for chip erase RESET# RY/BY# Notes 1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the device. 2. Figure indicates the last two bus cycles of the command sequence. 3. Word mode address used as an example. Document Number: 002-00870 Rev.*K Page 50 of 56 S29AS008J 19. Erase and Programming Performance Parameter Typ (Note 1) Max (Note 2) Sector Erase Time 0.5 10 Chip Erase Time 11.5 s Byte Programming Time 6 s Word Programming Time 6 Chip Programming Time (Note 3) Unit s 150 s Byte Mode 20 160 s Word Mode 14 120 s Comments Excludes 00h programming prior to erasure (Note 4) Excludes system level overhead (Note 5) Notes 1. Typical program and erase times assume the following conditions: 25C, VCC = 1.8 V, 100,000 cycles, checkerboard data pattern. 2. Under worst case conditions of 90C, VCC = 1.65 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table on page 30 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 100,000 cycles per sector. 20. Package Pin Capacitance Parameter Symbol Parameter Description Test Setup CIN Input Capacitance VIN = 0 COUT Output Capacitance VOUT = 0 CIN2 Control Pin Capacitance VIN = 0 CIN3 WP# Pin Capacitance VIN = 0 Package Typ Max TSOP 4 6 BGA 4.2 5.0 TSOP 4.5 5.5 BGA 5.4 6.5 TSOP 5 6.5 BGA 3.9 4.7 TSOP 8.5 10.0 BGA 8.5 10.0 Unit pF Notes 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz. Document Number: 002-00870 Rev.*K Page 51 of 56 S29AS008J 21. Physical Dimensions 21.1 TS 048 - 48-Pin Standard TSOP 2X 0.10 STANDARD PIN OUT (TOP VIEW) 2X (N/2 TIPS) 2X 2 0.10 0.10 1 A2 N SEE DETAIL B A REVERSE PIN OUT (TOP VIEW) 3 B 1 N E 5 N +1 2 N 2 D1 2X (N/2 TIPS) 9 A1 4 D 0.25 e 5 B A B N +1 2 N 2 C SEATING PLANE SEE DETAIL A 0.08MM (0.0031") b M C A-B S 6 7 WITH PLATING 7 (c) c1 b1 SECTION B-B BASE METAL R (c) e/2 GAUGE PLANE PARALLEL TO SEATING PLANE 0.25MM (0.0098") BSC X C L DETAIL A X = A OR B DETAIL B NOTES: Jedec MO-142 (D) DD Symbol A A1 A2 b1 b c1 c D D1 E e L 0 R N MAX 1.20 0.15 0.05 1.05 1.00 0.95 0.20 0.23 0.17 0.27 0.22 0.17 0.16 0.10 0.21 0.10 19.80 20.00 20.20 18.30 18.40 18.50 11.90 12.00 12.10 0.50 BASIC 0.70 0.50 0.60 8 0 0.20 0.08 48 MIN NOM 1 CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm). (DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982) 2 PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP). 3 PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK. 4 TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE. 5 DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS 0.15mm (.0059") PER SIDE. 6 DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE 0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028"). 7 THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND 0.25MM (0.0098") FROM THE LEAD TIP. 8 LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE. 9 DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS. 3355 \ 16-038.10c Note For reference only. BSC is an ANSI standard for Basic Space Centering. Document Number: 002-00870 Rev.*K Page 52 of 56 S29AS008J 21.2 VBK048--48-Ball Fine-Pitch Ball Grid Array (FBGA) 8.15 mm x 6.15 mm 0.10 D (4X) D1 A 6 5 7 e 4 E SE E1 3 2 1 H PIN A1 CORNER INDEX MARK 6 B 10 G F b E D C SD B A A1 CORNER 7 0.08 M C TOP VIEW 0.15 M C A B BOTTOM VIEW 0.10 C A2 A SEATING PLANE A1 C 0.08 C SIDE VIEW NOTES: PACKAGE VBK 048 JEDEC 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. N/A 2. ALL DIMENSIONS ARE IN MILLIMETERS. 8.15 mm x 6.15 mm NOM PACKAGE SYMBOL MIN NOM MAX A --- --- 1.00 A1 0.18 --- --- A2 0.62 --- 0.76 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). NOTE OVERALL THICKNESS BALL HEIGHT 8.15 BSC. BODY SIZE E 6.15 BSC. BODY SIZE D1 5.60 BSC. BALL FOOTPRINT E1 4.00 BSC. BALL FOOTPRINT MD 8 ROW MATRIX SIZE D DIRECTION ME 6 ROW MATRIX SIZE E DIRECTION N 48 TOTAL BALL COUNT 0.35 --- 0.43 BALL DIAMETER e 0.80 BSC. BALL PITCH SD / SE 0.40 BSC. SOLDER BALL PLACEMENT --- DEPOPULATED SOLDER BALLS e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. BODY THICKNESS D b 4. N IS THE TOTAL NUMBER OF SOLDER BALLS. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3338 \ 16-038.25b Document Number: 002-00870 Rev.*K Page 53 of 56 S29AS008J 22. Revision History Document Title:S29AS008J 8 Mbit (1M x 8-Bit / 512K x 16-Bit), 1.8 V Boot Sector Flash Document Number: 002-00870 Rev. ECN No. Orig. of Change ** - RYSU *A - RYSU 10/30/2007 02:Ordering Information Deleted all Leaded package offerings Table Primary Vendor-Specific Extended Query Corrected the data of CFI address 44 Hex *B - RYSU 06/06/2008 03:Ordering Information Removed all 50 ns speed option and FBGA package offerings Updated the Valid Combination table CMOS Compatible Updated Note 4 TSOP and BGA Pin Capacitance Changed Title to Package Pin Capacitance Added WLCSP Information Connection Diagram Removed VBK048 Added WLCSP Physical Dimention Removed VBK048 Added WLCSP Common Flash Memory Interface Updated Table Primary Vendor-Specific Extended Query *C - RYSU 08/19/2008 04:Sector Protection/Unprotection Replaced entire section. Global Modified all references to sector protection, sector unprotection, temporary sector unprotect, and temporary sector unprotect to sector group protection, sector groupunprotection, temporary sector group unprotect, and temporary sector group unprotect. In-System Group Protect/Unprotect Algorithms Added Note Read Operations Added note 3 *D - RYSU 10/27/2008 05:Sector Programmed and Protected at the Factory Modified first bullet Updated figure Secured Silicon Sector Protect Verify TSOP and Pin Capacitance Updated Table *E - RYSU 03/06/2009 06:Ordering Information Updated the Valid Communication table Connection Diagrams Added VBK048 Special Handling Instructions Added section Package Pin Capacitance Updated table Physical Dimensions Added VBK048 Table: Erase and Programming Performance Updated table *F - RYSU 04/27/2009 07:Ordering Information Updated the Valid combination *G - RYSU 07/16/2009 08:Global Removed all references to WLCSP from data sheet. Sector Address Tables Corrected notes to Tables 7.3 and 7.4 Read Operations Removed note 3 from section 18.1 *H - RYSU 11/09/2011 *I - RYSU 12/09/2011 10:RESET#: Hardware Reset Pin Added sentence regarding use of CE# with RESET# RESET# Timings Figure Added note Document Number: 002-00870 Rev.*K Submission Date Description of Change 07/27/2007 Spansion Publication Number: S29AS008J_00 01:Initial release 09:Ordering Information Added Low Halogen BGA ordering option Page 54 of 56 S29AS008J Document Title:S29AS008J 8 Mbit (1M x 8-Bit / 512K x 16-Bit), 1.8 V Boot Sector Flash Document Number: 002-00870 ECN No. Orig. of Change *J 5039748 RYSU 12/08/2015 Updated to Cypress Template *K 5741566 NIBK 05/18/2017 Updated Cypress Logo and Copyright. Rev. Document Number: 002-00870 Rev.*K Submission Date Description of Change Page 55 of 56 S29AS008J Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, Document Number: 002-00870 Rev.*K Revised May 19, 2017 Page 56 of 56