W24258 32K x 8 CMOS STATIC RAM GENERAL DESCRIPTION The W24258 is a normal speed, very low power CMOS static RAM organized as 32768 x 8 bits that operates on a wide voltage range from 2.7V to 5.5V power supply. The W24258 family, W2425870LE and W24258-70LI, can meet requirement of various operating temperature. This device is manufactured using Winbond's high performance CMOS technology. FEATURES * * * * * Low power consumption: - Active: 350 mW (max.) - Standby: 6 W (max.)/3V 25 W (max.)/5V Access time: 70 nS (max.)/5V 100 nS (max.)/3V Single 3V/5V power supply Fully static operation * * * * All inputs and outputs directly TTL compatible Three-state outputs Battery back-up operation capability Data retention voltage: 2V (min.) Packaged in 28-pin 600 mil DIP, 330 mil SOP and standard type one TSOP (8 mm x 13.4 mm) BLOCK DIAGRAM PIN CONFIGURATIONS CLK GEN. PRECHARGE CKT. R O W CORE CELL ARRAY A12 A14 A2 A14 1 28 VDD A3 A12 2 27 WE A4 A7 3 26 A13 A5 A6 4 25 A8 A6 A5 5 24 A9 A7 A4 6 23 A11 A13 28-pin DIP A3 7 22 OE I/O1 A2 8 21 A10 I/O8 A1 9 20 CS A0 10 19 I/O8 D E C O D E R DATA CNTRL. 512 ROWS 64 X 8 COLUMNS I/O CKT. COLUMN DECODER CLK GEN. I/O1 11 18 I/O7 I/O2 12 17 I/O6 WE CS I/O3 13 16 I/O5 OE VSS 14 15 I/O4 A11 A10 A1 A0 A8 A9 PIN DESCRIPTION OE A11 A9 A8 A13 WE VDD A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 28-pin TSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 SYMBOL A0-A14 I/O1-I/O8 -1- CS DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Input WE Write Enable Input OE VDD VSS Output Enable Input Power Supply Ground Publication Release Date: November 1998 Revision A8 W24258 TRUTH TABLE CS H OE X WE X L H L L MODE VDD CURRENT I/O1-I/O8 Not Selected High Z ISB, ISB1 H Output Disable High Z IDD L H Read Data Out IDD X L Write Data In IDD DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER RATING UNIT -0.5 to +7.0 V Input/Output to VSS Potential -0.5 to VDD +0.5 V Allowable Power Dissipation 1.0 W -65 to +150 C LE -20 to 85 C LI -40 to 85 C Supply Voltage to VSS Potential Storage Temperature Operating Temperature Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. Operating Characteristics (VDD = 5V 10%; VDD = 3V 10%; VSS = 0V; TA (C) = -20 to 85 for LE; -40 to 85 for LI) PARAMETER SYM. 5V 10% TEST CONDITIONS 3V 10% MIN. MAX. MIN. MAX. UNIT Input Low Voltage VIL - -0.5 +0.8 -0.5 +0.6 V Input High Voltage VIH - +2.2 VDD +0.5 +2.0 VDD +0.5 V Input Leakage Current ILI VIN = VSS to VDD -1 +1 -1 +1 A Output Leakage Current ILO VI/O = VSS to VDD, CS = VIH (min.) or OE = VIH (min.) or WE = VIL (max.) -1 +1 -1 +1 A Output Low Voltage VOL IOL = +2.1 mA - 0.4 - 0.4 V Output High Voltage VOH IOH = -1.0 mA 2.4 - 2.2 - V -2- W24258 Operating Characteristics, continued PARAMETER Operating Power Supply Current Standby Power Supply Current SYM. 5V 10% TEST CONDITIONS MIN. TYP. 3V 10% UNIT MAX. MIN. TYP. MAX. IDD CS = VIL (max.), I/O = 0 mA, Cycle = min., Duty = 100% - - 70 - - 30 mA ISB CS = VIH (min.), Cycle = min., Duty = 100% - - 3 - - 1 mA ISB1 CS VDD -0.2V - 0.7 5 - 0.5 2 A Note: Typical parameter is measured under ambient temperature TA = 25 C and VDD = 5V / 3V. CAPACITANCE (VDD = 5V, TA = 25 C, f = 1 MHz) PARAMETER Input Capacitance Input/Output Capacitance SYM. CONDITIONS MAX. UNIT CIN CI/O VIN = 0V VOUT = 0V 6 8 pF pF Note: These parameters are sampled but not 100% tested. AC CHARACTERISTICS AC Test Conditions PARAMETER CONDITIONS Input Pulse Levels 3V 10%, 0V to 2.4V Input Rise and Fall Times Input and Output Timing Reference Level Output Load 5V 10%, 0V to 3.0V 5 nS 1.5V See the drawing below AC Test Loads and Waveform 1 TTL 1 TTL OUTPUT OUTPUT 100 pF Including Jig and Scope 5 pF Including Jig and Scope (For TCLZ, TOLZ, TCHZ, TOHZ, TWHZ, TOW ) 2.4V/3.0V 90% 10% 0V 5 nS 90% 10% 5 nS -3- Publication Release Date: November 1998 Revision A8 W24258 AC Characteristics, continued (VDD = 5V 10%; VDD = 3V 10%; VSS = 0V; TA (C) = -20 to 85 for LE; -40 to 85 for LI) Read Cycle PARAMETER SYM. 5V 3V UNIT MIN. MAX. MIN. MAX. Read Cycle Time TRC 70 - 100 - nS Address Access Time TAA - 70 - 100 nS Chip Select Access Time TACS - 70 - 100 nS Output Enable to Output Valid TAOE - 35 - 50 nS Chip Selection to Output in Low Z TCLZ* 10 - 15 - nS Output Enable to Output in Low Z TOLZ* 5 - 5 - nS Chip Deselection to Output in High Z TCHZ* - 30 - 35 nS Output Disable to Output in High Z TOHZ* - 30 - 35 nS Output Hold from Address Change TOH 10 - 15 - nS These parameters are sampled but not 100% tested Write Cycle PARAMETER SYM. 5V 3V UNIT MIN. MAX. MIN. MAX. Write Cycle Time TWC 70 - 100 - nS Chip Selection to End of Write TCW 50 - 70 - nS Address Valid to End of Write TAW 50 - 70 - nS Address Setup Time TAS 0 - 0 - nS Write Pulse Width TWP 50 - 70 - nS TWR 0 - 0 - nS Data Valid to End of Write TDW 30 - 50 - nS Data Hold from End of Write TDH 0 - 0 - nS Write to Output in High Z TWHZ* - 25 - 30 nS Output Disable to Output in High Z TOHZ* - 25 - 30 nS Output Active from End of Write TOW 5 - 10 - nS Write Recovery Time CS, WE These parameters are sampled but not 100% tested -4- W24258 TIMING WAVEFORMS Read Cycle 1 (Address Controlled) TRC Address TOH TAA TOH DOUT Read Cycle 2 (Chip Select Controlled) CS TACS TCHZ TCLZ DOUT Read Cycle 3 (Output Enable Controlled) T RC Address T AA OE T OH T AOE T OLZ CS T ACS D OUT T CHZ T OHZ TCLZ -5- Publication Release Date: November 1998 Revision A8 W24258 Timing Waveforms, continued Write Cycle 1 TWC Address T WR OE TCW CS T AW WE T WP TAS TOHZ (1, 4) D OUT T DW TDH D IN Write Cycle 2 (OE = VIL Fixed) T WC Address TWR TCW CS TAW WE T WP TAS TOH TWHZ (1, 4) D OUT TDW (2) (3) TOW TDH DIN Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from DOUT are the same as the data written to DIN during the write cycle. 3. DOUT provides the read data for the next address. 4. Transition is measured 500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested. -6- W24258 DATA RETENTION CHARACTERISTICS (TA (C) =-20 to 85 for LE; -40 to 85 for LI) PARAMETER SYM. TEST CONDITIONS VDD for Data Retention VDR CS VDD -0.2V Data Retention Current IDDDR Chip Deselect to Data Retention Time TCDR Operation Recovery Time TR MIN. TYP. MAX. UNIT 2.0 - - V CS VDD -0.2V, VDD = 3V - - 2 A See data retention waveform 0 - - nS TRC* - - nS * Read Cycle Time DATA RETENTION WAVEFORM VDD 0.9 VDD 0.9 V DD VDR > = 2V TCDR > V DD - 0.2V CS = VIH CS TR VIH ORDERING INFORMATION PART NO. ACCESS TIME (nS) OPERATING VOLTAGE (V) OPERATING TEMPERATURE (C) 100 3V 0 to 70 W24258-70LE 70/100 5V/3V -20 to 85 600 mil DIP W24258S-70LE 70/100 5V/3V -20 to 85 330 mil SOP W24258Q-70LE 70/100 5V/3V -20 to 85 Standard type one TSOP W24258-70LI 70/100 5V/3V -40 to 85 600 mil DIP W24258S-70LI 70/100 5V/3V -40 to 85 330 mil SOP W24258Q-70LI 70/100 5V/3V -40 to 85 Standard type one TSOP W24258H PACKAGE Die form Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. -7- Publication Release Date: November 1998 Revision A8 W24258 BONDING PAD DIAGRAM 6 5 4 A4 A5 A6 3 7 28 28 27 S-2 S-1 2 1 A7 A1 2 A1 4 26 25 VDD VDD WE A13 A8 24 PAD NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14S-1 14S-2 15 16 17 18 19 20 21 22 23 24 25 26 27 28S-1 28S-2 23 A9 A11 22 A 3 OE Y X 21 8 A2 A10 9 A1 10 11 12 13 14 14 S-1 S-2 15 16 17 18 19 20 A0 I/O1 I/O2 I/O3 VSS VSS I/O4 I/O3 I/O6 I/O7 I/O8 CS X -276.73 -421.97 -568.93 -714.17 -861.13 -1006.37 -1190.70 -1190.70 -1023.69 -878.45 -730.05 -584.79 -438.69 -293.69 -152.23 -9.22 437.42 582.68 730.42 875.68 1025.65 1189.20 1188.70 1025.68 878.72 733.48 586.52 441.28 18.40 -131.73 Y 2047.90 2047.90 2047.90 2047.90 2047.90 2047.90 1796.55 -1797.65 -2049.00 -2049.00 -2049.00 -2049.00 -2049.00 -2049.00 -2049.00 -2049.00 -2049.00 -2049.00 -2049.00 -2049.00 -2049.00 -1797.65 1796.55 2047.90 2047.90 2047.90 2047.90 2047.90 2047.90 2047.90 Note: For bare chip form (C.O.B.) applications, the substrate must be connected to VDD or left floating in the PCB layout. -8- W24258 PACKAGE DIMENSIONS 28-pin P-DIP Dimension in Inches Symbol A A1 A2 B B1 c D E E1 e1 L D 28 15 a E1 eA S Notes: 1 14 E S c A A2 Base Plane A1 L Seating Plane B e1 eA a B1 Min. Nom. Max. Dimension in mm Min. Nom. Max. 0.210 0.010 5.33 0.25 0.150 0.155 0.160 3.81 3.94 4.06 0.016 0.018 0.022 0.41 0.46 0.56 0.058 0.060 0.064 1.47 1.52 1.63 0.008 0.010 0.014 0.20 0.25 0.36 1.460 1.470 37.08 37.34 0.590 0.600 0.610 14.99 15.24 15.49 0.540 0.545 0.550 13.72 13.84 13.97 0.090 0.100 0.110 2.29 2.54 2.79 0.120 0.130 0.140 3.05 3.30 3.56 15 0 0.670 16.00 16.51 17.02 0 0.630 0.650 15 0.090 2.29 1. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimensions D & E1 include mold mismatch and are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec. 28-pin SOP Wide Body Dimension in Inches Symbol 28 A A1 A2 b c D E e HE L LE S y 15 e1 E HE L Detail F 14 1 b e1 c A2 A e y Dimension in mm Min. Nom. Max. 2.85 0.112 0.004 0.10 0.093 0.098 0.103 2.36 2.49 0.014 0.016 0.020 0.36 0.41 0.51 0.010 0.014 0.20 0.25 0.36 0.713 0.733 18.11 18.62 0.008 2.62 0.326 0.331 0.336 8.28 8.41 8.53 0.044 0.050 0.056 1.12 1.27 1.42 0.453 0.465 0.477 11.51 11.81 12.12 0.028 0.036 0.044 0.71 0.91 1.12 0.059 0.067 0.075 1.50 1.70 1.91 0.047 1.19 0.10 0.004 0 10 0 10 Notes: D S Min. Nom. Max. 1. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion/intrusion. 3. Dimensions D & E include mold mismatch . and determined at the mold parting line. 4. Controlling dimension: Inches. 5. General appearance spec should be based on final visual inspection spec. LE A1 See Detail F Seating Plane -9- Publication Release Date: November 1998 Revision A8 W24258 Package Dimensions, continued 28-pin Standard Type One TSOP HD Dimension In Inches Dimension In mm Min. Min. Symbol D c A A1 A2 b c D E HD e L L1 Y 1 e E b A2 A A1 L L1 - 10 - Nom. Max. Nom. 0.002 0.006 0.05 0.15 0.035 0.040 0.041 0.95 1.00 0.007 0.008 0.011 0.17 0.20 0.27 0.004 0.006 0.008 0.10 0.15 0.21 11.90 1.05 0.461 0.465 0.469 11.70 11.80 0.311 0.315 0.319 7.90 8.00 8.10 0.520 0.528 0.536 13.20 13.40 13.60 0.020 0.024 0.028 0.50 0.60 0.55 0.022 0.010 0.000 0 3 0.70 0.25 0.004 0.00 5 0 Controlling dimension: Millimeters Y Max. 1.20 0.047 0.10 3 5 W24258 VERSION HISTORY VERSION DATE PAGE A4 Mar. 1997 8 Add bonding PAD diagram A5 Jan. 1998 8 Modify bonding PAD diagram A6 Feb. 1998 1, 2, 4, 7 A7 Apr. 1998 3 A8 Nov. 1998 1, 3, 7, 10 Headquarters DESCRIPTION Delete operating temperature (SL = 0 to 70 C) Add standby power supply current (ISB1) typical parameter when operation temperature TA = 25 C Deduct reverse type one TSOP package Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. - 11 - Publication Release Date: November 1998 Revision A8