74AC573, 74ACT573 Octal Latch with 3-STATE Outputs Features General Description ICC and IOZ reduced by 50% Inputs and outputs on opposite sides of package The 74AC573 and 74ACT573 are high-speed octal latches with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. allowing easy interface with microprocessors Useful as input or output port for microprocessors Functionally identical to 74AC373 and 74ACT373 3-STATE outputs for bus interfacing The 74AC573 and 74ACT573 are functionally identical to the 74AC373 and 74ACT373 but with inputs and outputs on opposite sides. Outputs source/sink 24mA 74ACT573 has TTL-compatible inputs Ordering Information Order Number 74AC573SC 74AC573SJ Package Number Package Description M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT573SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT573SJ 74ACT573MTC 74ACT573PC MTC20 N20A 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. (c)1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.6.0 www.fairchildsemi.com 74AC573, 74ACT573 -- Octal Latch with 3-STATE Outputs January 2008 74AC573, 74ACT573 -- Octal Latch with 3-STATE Outputs Connection Diagram Logic Symbols IEEE/IEC Pin Description Pin Names D0-D7 Description Data Inputs LE Latch Enable Input OE 3-STATE Output Enable Input O0-O7 3-STATE Latch Outputs Functional Description Truth Table The 74AC573 and 74ACT573 contain eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D-type input changes. When LE is LOW the latches store the information that was present on the D-type inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. Inputs Outputs OE LE D On L H H H L H L L L L X O0 H X X Z H = HIGH Voltage L = LOW Voltage Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable (c)1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.6.0 www.fairchildsemi.com 2 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. (c)1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.6.0 www.fairchildsemi.com 3 74AC573, 74ACT573 -- Octal Latch with 3-STATE Outputs Logic Diagram Symbol VCC IIK Parameter Rating Supply Voltage -0.5V to +7.0V DC Input Diode Current VI = -0.5V -20mA VI = VCC + 0.5 +20mA VI DC Input Voltage -0.5V to VCC + 0.5V IOK DC Output Diode Current VO = -0.5V -20mA VO = VCC + 0.5V +20mA VO DC Output Voltage -0.5V to VCC + 0.5V IO DC Output Source or Sink Current 50mA ICC or IGND DC VCC or Ground Current per Output Pin TSTG Storage Temperature TJ 50mA -65C to +150C Junction Temperature 140C Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC Parameter Supply Voltage AC 2.0V to 6.0V ACT 4.5V to 5.5V VI Input Voltage VO Output Voltage TA Operating Temperature V / t Rating 0V to VCC 0V to VCC -40C to +85C Minimum Input Edge Rate, AC Devices: 125mV/ns VIN from 30% to 70% of VCC, VCC @ 3.3V, 4.5V, 5.5V V / t 125mV/ns Minimum Input Edge Rate, ACT Devices: VIN from 0.8V to 2.0V, VCC @ 4.5V, 5.5V (c)1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.6.0 www.fairchildsemi.com 4 74AC573, 74ACT573 -- Octal Latch with 3-STATE Outputs Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA = +25C Symbol Parameter VCC (V) VIH Minimum HIGH Level Input Voltage 3.0 Maximum LOW Level Input Voltage 3.0 Minimum HIGH Level Output Voltage 3.0 Conditions VOUT = 0.1V or VCC - 0.1V Units 2.1 2.1 2.25 3.15 3.15 2.75 3.85 3.85 1.5 0.9 0.9 2.25 1.35 1.35 2.75 1.65 1.65 2.99 2.9 2.9 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 2.56 2.46 3.86 3.76 4.86 4.76 0.002 0.1 0.1 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 0.36 0.44 0.36 0.44 0.36 0.44 0.1 1.0 A 4.5 4.5 VOUT = 0.1V or VCC - 0.1V 5.5 VOH Guaranteed Limits 1.5 5.5 VIL Typ. TA = -40C to +85C 3.0 IOUT = -50A VIN = VIL or VIH, V V V IOH = -12mA 4.5 VIN = VIL or VIH, IOH = -24mA 5.5 VIN = VIL or VIH, IOH = VOL Maximum LOW Level Output Voltage 3.0 3.0 -24mA(1) IOUT = 50A VIN = VIL or VIH, V IOL = 12mA 4.5 VIN = VIL or VIH, IOL = 24mA 5.5 VIN = VIL or VIH, IOL = 24mA(1) IIN(2) Maximum Input Leakage Current 5.5 VI = VCC, GND IOLD Minimum Dynamic Output Current(3) 5.5 VOLD = 1.65V Max. 75 mA 5.5 VOHD = 3.85V Min. -75 mA Maximum Quiescent Supply Current 5.5 VIN = VCC or GND 4.0 40.0 A Maximum 3-STATE Leakage Current 5.5 VI (OE) = VIL, VIH; VI = VCC, GND; VO = VCC, GND 0.25 2.5 A IOHD ICC (2) IOZ Notes: 1. All outputs loaded; thresholds on input associated with output under test. 2. IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. 3. Maximum test duration 2.0ms, one output loaded at a time. (c)1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.6.0 www.fairchildsemi.com 5 74AC573, 74ACT573 -- Octal Latch with 3-STATE Outputs DC Electrical Characteristics for AC TA = +25C Symbol Parameter VCC (V) VIH Minimum HIGH Level Input Voltage 4.5 5.5 Maximum LOW Level Input Voltage VIL VOH Minimum HIGH Level Output Voltage Conditions Typ. TA = -40C to +85C Guaranteed Limits VOUT = 0.1V or VCC - 0.1V 1.5 2.0 2.0 1.5 2.0 2.0 VOUT = 0.1V or VCC - 0.1V 1.5 0.8 0.8 5.5 1.5 0.8 0.8 4.5 IOUT = -50A 4.49 4.4 4.4 4.5 5.5 4.5 5.49 VIN = VIL or VIH, 5.4 5.4 3.86 3.76 4.86 4.76 0.1 0.1 Units V V V IOH = -24mA 5.5 VIN = VIL or VIH, IOH = -24mA(4) VOL Maximum LOW Level Output Voltage 4.5 IOUT = 50A 5.5 4.5 0.001 0.001 VIN = VIL or VIH, 0.1 0.1 0.36 0.44 0.36 0.44 V IOL = 24mA 5.5 VIN = VIL or VIH, IOL = 24mA(4) IIN Maximum Input Leakage Current 5.5 VI = VCC, GND 0.1 1.0 A IOZ Maximum 3-STATE Leakage Current 5.5 VI = VIL, VIH; VO = VCC, GND 0.25 2.5 A ICCT Maximum ICC/Input 5.5 VI = VCC - 2.1V 1.5 mA IOLD Minimum Dynamic Output Current(5) 5.5 VOLD = 1.65V Max. 75 mA 5.5 VOHD = 3.85V Min. -75 mA Maximum Quiescent Supply Current 5.5 VIN = VCC or GND 40.0 A IOHD ICC 0.6 4.0 Notes: 4. All outputs loaded; thresholds on input associated with output under test. 5. Maximum test duration 2.0ms, one output loaded at a time. (c)1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.6.0 www.fairchildsemi.com 6 74AC573, 74ACT573 -- Octal Latch with 3-STATE Outputs DC Electrical Characteristics for ACT TA = +25C, CL = 50pF TA = -40C to +85C, CL = 50pF VCC (V)(6) Min. Typ. Max. Min. Max. Units tPHL, tPLH Propagation Delay, Dn to On 3.3 0.5 8.5 10.5 2.5 11.0 ns 5.0 1.5 5.5 7.0 1.5 7.5 tPLH, tPHL Propagation Delay, LE to On 3.3 2.5 8.5 12.0 2.5 12.5 5.0 2.0 6.0 8.0 2.0 8.5 tPZL, tPZH Output Enable Time 3.3 2.5 8.5 13.0 2.5 13.5 5.0 1.5 6.0 8.5 1.5 9.0 Symbol Parameter tPHZ, tPLZ Output Disable Time 3.3 1.0 9.0 14.5 1.0 15.0 5.0 1.0 6.0 9.5 1.0 10.0 ns ns ns Note: 6. Voltage range 5.0 is 5.0V 0.5V. Voltage range 3.3 is 3.3V 0.3V. AC Operating Requirements for AC TA = +25C, CL = 50pF Symbol tS tH tW TA = -40C to +85C, CL = 50pF VCC (V)(7) Typ. Setup Time, HIGH or LOW, Dn to LE 3.3 0 3.0 3.0 5.0 0 3.0 3.0 Hold Time, HIGH or LOW, Dn to LE 3.3 0 1.5 1.5 5.0 0 1.5 1.5 LE Pulse Width, HIGH 3.3 2.0 4.0 4.0 5.0 2.0 4.0 4.0 Parameter Guaranteed Minimum Units ns ns ns Note: 7. Voltage range 5.0 is 5.0V 0.5V. Voltage range 3.3 is 3.3V 0.3V. (c)1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.6.0 www.fairchildsemi.com 7 74AC573, 74ACT573 -- Octal Latch with 3-STATE Outputs AC Electrical Characteristics for AC TA = +25C, CL = 50pF TA = -40C to +85C, CL = 50pF VCC (V)(8) Min. Typ. Max. Min. Max. Units Propagation Delay, Dn to On 5.0 2.5 6.0 10.5 2.0 12.0 ns tPLH Propagation Delay, LE to On 5.0 3.0 6.0 10.5 2.5 12.0 ns tPHL Propagation Delay, LE to On 5.0 2.5 5.5 9.5 2.0 10.5 ns tPZH Output Enable Time 5.0 2.0 5.5 10.0 1.5 11.0 ns tPZL Output Enable Time 5.0 1.5 5.5 9.5 1.5 10.5 ns tPHZ Output Disable Time 5.0 2.5 6.5 11.0 1.5 12.5 ns tPLZ Output Disable Time 5.0 1.5 5.0 8.5 1.0 9.5 ns Symbol Parameter tPLH, tPHL Note: 8. Voltage range 5.0 is 5.0V 0.5V. AC Operating Requirements for ACT TA = +25C, CL = 50pF Symbol Parameter VCC (V)(9) Typ. TA = -40C to +85C, CL = 50pF Guaranteed Minimum Units tS Setup Time, HIGH or LOW, Dn to LE 5.0 1.5 3.0 3.5 ns tH Hold Time, HIGH or LOW, Dn to LE 5.0 -1.5 0 0 ns tW LE Pulse Width, HIGH 5.0 2.0 3.5 4.0 ns Note: 9. Voltage range 5.0 is 5.0V 0.5V. Capacitance Symbol Parameter Conditions Typ. Units 5.0 pF AC 25.0 pF ACT 42.0 CIN Input Capacitance VCC = OPEN CPD Power Dissipation Capacitance VCC = 5.0V (c)1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.6.0 www.fairchildsemi.com 8 74AC573, 74ACT573 -- Octal Latch with 3-STATE Outputs AC Electrical Characteristics for ACT 13.00 12.60 A 11.43 20 11 B 9.50 10.65 7.60 10.00 7.40 2.25 1 PIN ONE INDICATOR 10 0.51 0.35 0.25 M 0.65 1.27 1.27 C B A LAND PATTERN RECOMMENDATION 2.65 MAX SEE DETAIL A 0.33 0.20 C 0.75 0.25 X 45 SEATING PLANE NOTES: UNLESS OTHERWISE SPECIFIED (R0.10) GAGE PLANE (R0.10) 0.10 C 0.30 0.10 0.25 8 0 A) THIS PACKAGE CONFORMS TO JEDEC MS-013, VARIATION AC, ISSUE E B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) CONFORMS TO ASME Y14.5M-1994 1.27 0.40 SEATING PLANE E) LANDPATTERN STANDARD: SOIC127P1030X265-20L (1.40) DETAIL A F) DRAWING FILENAME: MKT-M20BREV3 SCALE: 2:1 Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ (c)1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.6.0 www.fairchildsemi.com 9 74AC573, 74ACT573 -- Octal Latch with 3-STATE Outputs Physical Dimensions 74AC573, 74ACT573 -- Octal Latch with 3-STATE Outputs Physical Dimensions (Continued) Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ (c)1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.6.0 www.fairchildsemi.com 10 74AC573, 74ACT573 -- Octal Latch with 3-STATE Outputs Physical Dimensions (Continued) Figure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ (c)1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.6.0 www.fairchildsemi.com 11 74AC573, 74ACT573 -- Octal Latch with 3-STATE Outputs Physical Dimensions (Continued) 26.92 24.89 7.11 6.09 PIN #1 (0.97) 1.78 1.14 2.54 0.36 0.56 .001[.025] 3.43 3.17 5.33 MAX 7 TYP 7.87 7 TYP 3.55 3.17 0.38 MIN 7.62 10.92 MAX 0.20 0.35 C NOTES: Figure 4. 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ (c)1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.6.0 www.fairchildsemi.com 12 ACEx(R) Build it NowTM CorePLUSTM CROSSVOLTTM CTLTM Current Transfer LogicTM EcoSPARK(R) EZSWITCHTM * TM PDP-SPMTM SyncFETTM (R) Power220(R) (R) Power247 The Power Franchise(R) POWEREDGE(R) Power-SPMTM PowerTrench(R) TinyBoostTM Programmable Active DroopTM TinyBuckTM (R) QFET TinyLogic(R) QSTM TINYOPTOTM QT OptoelectronicsTM TinyPowerTM (R) Quiet SeriesTM TinyPWMTM RapidConfigureTM TinyWireTM Fairchild(R) SMART STARTTM Fairchild Semiconductor(R) SerDesTM (R) SPM FACT Quiet SeriesTM UHC(R) STEALTHTM FACT(R) Ultra FRFETTM SuperFETTM FAST(R) UniFETTM SuperSOTTM-3 FastvCoreTM VCXTM (R) (R)* SuperSOTTM-6 FlashWriter SuperSOTTM-8 * EZSWITCHTM and FlashWriter(R) are trademarks of System General Corporation, used under license by Fairchild Semiconductor. FPSTM FRFET(R) Global Power ResourceSM Green FPSTM Green FPSTM e-SeriesTM GTOTM i-LoTM IntelliMAXTM ISOPLANARTM MegaBuckTM MICROCOUPLERTM MicroFETTM MicroPakTM MillerDriveTM Motion-SPMTM OPTOLOGIC(R) OPTOPLANAR(R) DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD'S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I32 (c)1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Rev. 1.6.0 www.fairchildsemi.com 13 74AC573, 74ACT573 -- Octal Latch with 3-STATE Outputs TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.