TLE8102SG
Smart Dual Channel Powertrain Switch
coreFLEX
Data Sheet, V1.5, August 2012
Automotive Power
Data Sheet 2 V1.5, 2012-08-17
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Maximum Ratings and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 Electrical and Functional Description of Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2 Parallel Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.3 Power Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.3.1 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.3.2 Inductive Output Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.3.3 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.3.3.1 Over Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.3.3.2 Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3.4 Reverse Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3.5 Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.4 Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.5 Current Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.6 SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.6.1 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.6.2 Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.7 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6 SPI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7 Application Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table of Contents
PG-DSO-12-11
Type Package Marking
TLE8102SG PG-DSO-12-11 TLE8102SG
Data Sheet 3 V1.5, 2012-08-17
Smart Dual Channel Powertrain Switch
coreFLEX
TLE8102SG
1 Overview
Features
• Overload Protection
• DMOS Overtemperature protection
• Open load detection
• Current limitation
• Low quiescent current mode
• 3.3 V μC compatible input
• Electrostatic discharge (ESD) protection
• Green Product (RoHS compliant)
• AEC Qualified
Description
• Proportional load current sense with improved Precision:
+/- 6% at ID=3A and +/-3% Current Sense Temperature Deviation refering to TJ=25°C
• Two Low-Side Channels with RON(max. @ 150°C) = 360mOhm.
• IC Overtemperature warning
• 8-Bit SPI (for diagnosis and control)
• Short to GND detection
• Programmable overload behaviour
Dual Current Sense Low-Side Switch in Smart Power Technology (SPT) with two open drain DMOS output stages.
The TLE8102SG is protected by embedded protection functions and designed for automotive applications. The
output stages can be controlled directly by parallel inputs for PWM applications (e.g. Oxygen Probe Heater) or by
SPI. All output stages can provide a load current proportional sense signal. Diagnosis can be read from an 8-bit
SPI or by the external fault pin.
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Overview
Data Sheet 4 V1.5, 2012-08-17
Parameter Summary
Parameter Symbol Value Unit
Supply voltage VDD 4.5 … 5.5 V
Drain source voltage VDS(CL) 48 … 60 V
On resistance RON(max. @ 150°C) 0.36 Ω
Overview.emf
CS
SI
SCLK
CO2 [SO / ST2]
SPI
control,
diagnostic
and
protective
functions
under current
detection
short circuit
detection
gate control
open load
detection
GND
IN1
VDD
OUT2
OUT1
hardware
configuration
input control
reset
IN2
temperature
sensor
proportional
current sense
CO1 [IS1 / IS2 /
ST1 / FAULT]
sleep mode
current sense /
diagnosis
selectable
current limit
Figure 1 Block Diagram
Data Sheet 5 V1.5, 2012-08-17
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Overview
2Overview
2.1 Terms
Figure 2 shows all terms used in this Target Data Sheet.
V
SCLK
V
SI
V
CS
V
SO / ST2
I
IS1 / IS2 / ST1 / FAULT
CO1 [IS1 / IS2 / ST1 / FAULT]
I
SI
SI
CO2 [SO / ST2]
I
SCLK
SCLK
V
IS1 / IS2 / ST1 / FAULT
GND
I
GND
OUT1
V
DS1
I
D2
OUT2
V
DS2
I
D1
V
bat
V
IN1
V
DD
IN2
IN1
VDD
I
IN2
I
IN1
I
VDD
I
CS
CS
V
IN2
I
SO
I
ST2
Figure 2 Terms
In all tables of electrical characteristics is valid: Channel related symbols without channel number are valid for each
channel separately (e.g. VDS specification is valid for VDS1 and VDS2).
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Pin Configuration
Data Sheet 6 V1.5, 2012-08-17
3 Pin Configuration
3.1 Pin Assignment
1
2
3
4
5
6
12
10
9
8
7
11
P-DSO-12
P-DSO- 12_TLE8102.vsd
IN2
SI
OUT2
CO1
SCLK
GND
GND
CO2
VDD
OUT1
CS
IN1
Figure 3 Pin Configuration (top view)
Both GND pins and the heat sink must be connected to GND externally.
3.2 Pin Definitions and Functions
Pin Symbol Function
1IN2 Input Channel 2
2SI SPI Signal In
3OUT2 Power Output Channel 2
4CO1 Current Sense 1/2/Fault/Status Ch1
5SCLK SPI Clock
6GND Ground
7IN1 Input Channel 1
8CS SPI Chip Select
9OUT1 Power Output Channel 1
10 VDD Supply Voltage
11 CO2 SPI Signal Out/Status Ch2
12 GND Ground
Data Sheet 7 V1.5, 2012-08-17
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Maximum Ratings and Operating Conditions
4 Maximum Ratings and Operating Conditions
4.1 Absolute Maximum Ratings
Tj = -40 ⋅C to +150 ⋅C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Max.
Supply Voltage VDD -0.3 7 V –
Continuous Drain Source Voltage
(OUT1 to OUT2)
VDS -0.3 48 V –
Input Voltage, All Inputs and Data
outputs, Sense Lines
VIN -0.3 7 V –
Output Current per Channel2)
2) Output current rating as long as maximum junction temperature is not exceeded. The maximum output current in the
application has to be calculated using RthJA depending onmounting conditions.
ID-3 ID(lim1,2) min. AOutput ON
Maximum Voltage for short circuit
Protection (single event)3)
3) Device mounted on PCB (50 mm × 50 mm × 1.5 mm epoxy, FR4) with 6 cm2 copper heatsink area (one layer, 70 μm thick);
PCB in test chamber with blown air.
VSC, single –48 VCurrent Limit 2, slew
rate 1 (default setting)
–32 VCurrent Limit 2,
slew rate 2
–18 VCurrent Limit 1,
slew rate 1 or 2
Electrostatic Discharge Voltage
(human body model) according to
EIA/JESD22-A114-E
VESD -4000
-2000
4000
2000
V
V
Output Pins
All other Pins
DIN Humidity Category, DIN 40 040 E –
IEC Climatic Category, DIN IEC 68-1 40/150/ 56 –
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Absolute Maximum Ratings 1)
1) Not subject to production test, specified by design.
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
4.1.8
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Maximum Ratings and Operating Conditions
Data Sheet 8 V1.5, 2012-08-17
4.2 Operating Conditions
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
Output Clamping Energy (single
event), linearly decreasing current1)
1) Pulse shape represents inductive switch off: ID(t) = ID(0) × (1 - t / tpulse); 0 < t < tpulse
EAS – – 75 mJ ID(0) = 2 A,
TJ(0) = 150 °C, max.
100 cycles over
lifetime
Junction to case RthJSP –1.3 2K/W Pv = 2W
Junction to ambient (see Figure 4)RthJA –25 –K/W Pv = 2W
Operating Temperature Range Tj-40 –150 °C –
Storage Temperature Range Tstg -55 –150 °C –
70µm modeled (traces)
35µm, 90% metalization
35
µ
m
,
90
%
metalizatio
n
1
,5
mm
70
µ
m
,
5% metalization
Thermal_Setup.vsd
PCB Dimensions: 76.2 x 114.3 x 1.5 mm³, FR4
Thermal Vias: diameter = 0.3 mm; plating 25 µm; 14 pcs.
Metallisation according JEDEC 2s2p (JESD 51-7) + (JESD 51-5)
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given by the related electrical characteristics table.
Figure 4 Thermal Simulation - PCB set-up
4.2.1
Thermal Resistance
4.2.2
4.2.3
Temperature Range
4.2.4
4.2.5
Data Sheet 9 V1.5, 2012-08-17
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Electrical and Functional Description of Blocks
5 Electrical and Functional Description of Blocks
5.1 Power Supply
The TLE8102SG is supplied by power supply line VDD, used for the digital as well as the analog functions of the
device including the gate control of the power stages. A capacitor between pins VDD to GND is recommended.
The TLE8102SG can be programmed via SPI to enter sleep mode. In sleep mode, all outputs are turned off and
all diagnosis and biasing circuits are disabled. These actions reduce the quiescent current consumption from the
power supply. However, the SPI configuration registers (except for the channel on/off register) are not reset when
the TLE8102SG enters sleep mode. To exit sleep mode, a wake up command must be sent via SPI.
VDD = 4.5 V to 5.5 V, Tj = -40 ⋅C to +150 ⋅C, (unless otherwise specified)
all voltages with respect to ground, positive current flowing into pin
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
Supply Voltage VDD 4.5 –5.5 V –
Supply Current IVDD ––5mA –
Supply Current in Sleep Mode IVDD(sleep) – – 10 μA –
Wake up Time (after sleep mode)1)
1) Not subject to production test, specified by design.
twake – – 100 μs –
5.2 Parallel Inputs
There are two input pins available on the TLE8102SG to control the output stages.
Each input signal controls the output stages of its assigned channel. For example, IN1 controls OUT1 and IN2
controls OUT2. Please refer to Figure 5 for details. The input pins are active high and each have an integrated
pull-down current source. A comparator with hysteresis determines the state of the signal on INn. The zener diode
protects the input circuit against ESD pulses.
The BOL bit can be set via SPI. This bit determines if the output is exclusively controlled by the INn signals,
exclusively controlled by the corresponding data bits CHnIN or by a Boolean OR or AND operation of the two
inputs. The default setting of the BOL bits programs the outputs to be controlled exclusively by the INn signals.
The SLEn bit can be set via SPI. This bit sets the slew rate of its assigned channel by selecting either slew rate 1
or slew rate 2. The slew rate also changes the over load switch off delay time (only for current limit 2).
Figure 5 Input Control and Boolean Operator
Electrical Characteristics: Power Supply
5.1.1
5.1.2
5.1.3
5.1.4
VDD = 4.5 V to 5.5 V, Tj = -40 ⋅C to +150 ⋅C, (unless otherwise specified)
all voltages with respect to ground, positive current flowing into pin
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
Input Low Voltage VINL – – 1.0 V –
Input High Voltage VINH 2.0 – – V –
Input Voltage Hysteresis1)
1) Not subject to production test, specified by design.
VINHys 100 200 400 mV –
Input Pull-down Current
(IN1 to IN2)
IIN(1 … 2) 20 50 100 μA –
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Electrical and Functional Description of Blocks
Data Sheet 10 V1.5, 2012-08-17
5.3 Power Outputs
5.3.1 Timing Diagrams
The power transistors are switched on and off with a dedicated slope either via the parallel inputs or by
the CHnIN bits of the serial peripheral interface SPI. The switching times tON and tOFF are designed equally. The
switching time of each channel can be selected via SPI by programming the SLEn bit of the desired output. See
Figure 6 for details
CS
V
DS
t
t
ON
t
OFF
t
20%
80%
SPI: ON SPI: OFF
Figure 6 Switching a Resistive Load
5.3.2 Inductive Output Clamp
When switching off inductive loads, the potential at pin OUT rises to VDS(CL), as the inductance continues to drive
current. The inductive output clamp is necessary to prevent destruction of the device. See Figure 7 for details.
The maximum allowed load inductance and current, however, are limited.
V
bat
I
D
V
DS(CL)
OUT
V
DS
GND
L,
R
L
Figure 7 Inductive Output Clamp
Electrical Characteristics: Parallel Inputs
5.2.1
5.2.2
5.2.3
5.2.4
Data Sheet 11 V1.5, 2012-08-17
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Electrical and Functional Description of Blocks
Maximum Load Inductance
During demagnetization of inductive loads, energy has to be dissipated in the TLE8102SG. This energy can be
calculated with following equation:
EV
DS(CL)
Vbat V–DS(CL)
RL
-------------------------------------ln⋅1RLID
⋅
Vbat V–DS(CL)
-------------------------------------
–
⎝⎠
⎜⎟
⎛⎞
ID
+L
RL
------
⋅⋅=
The equation simplifies under the assumption of RL = 0:
E1
2
---LID
21Vbat
Vbat V–DS(CL)
-------------------------------------
–
⎝⎠
⎜⎟
⎛⎞
⋅=
The energy, which is converted into heat, is limited by the thermal design of the component.
5.3.3 Protection Functions
The TLE8102SG provides embedded protective functions. Integrated protection functions are designed to prevent
IC destruction under fault conditions described in this data sheet. Fault conditions are considered “outside” the
normal operating range. Protection functions are not designed for continuous repetitive operation.
Over load and over temperature protections are implemented in the TLE8102SG. Figure 8 gives an overview pf
the protective functions.
OUTn
SPI
INn
temperature
monitor
current
limitation /
shutdown
gate control
T
Tn
GND
SCLK
Input Control
SI
SO
FAULT
CLn
ST Status
CS
Figure 8 Protection Functions
5.3.3.1 Over Load Protection
The TLE8102SG is protected in case of over load or short circuit of the load. If the device is programmed for
current limitation (current limit 1), the current is limited to IDS(lim1). After time td(fault), the corresponding over load
flag CLn is set. If using the status outputs for diagnosis, the over load flag is cleared immediately after the over
load condition is no longer present. If using the SPI interface and fault pin for diagnosis, the over load flag of the
affected channel is cleared by the rising edge of the CS signal after a successful SPI transmission.
If the TLE8102SG is programmed for current shutdown (current limit 2), the current threshold is IDS(lim2). However,
unlike in current limit 1, after time td(fault), the affected channel is turned off and the according over load flag CLn is
set. To turn on the channel again, this overload latch has to be reset by turning off the affected channel with either
the parallel input or SPI. In addition, the switch off delay time can be programmed by changing the slew rate
setting. If using the SPI interface and fault pin for diagnosis in case of current limit 2, the over load flag of the
affected channel is cleared by the rising edge of the CS signal after a successful SPI transmission when the IN
pin is low. A valid SPI cycle would not lead to a reset of the OVL flag of the affected channel during the IN-Pin is
high.
In both cases, the channel may shut down due to over temperature.
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Electrical and Functional Description of Blocks
Data Sheet 12 V1.5, 2012-08-17
For timing information, please refer to Figure 9 and Figure 10 for details.
OL_CurrLim1.vsd
IN
I
OUT
I
D(lim1)
ST
FAULT
I
nom
OVL
Condition
HL
(OVL)
HLHL
SO
t<t
d(fault)
CS
Valid SPI cycles
OVL
I
nom
I*R
ON
V
OUT
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
(Normal Function)
HH HH HH HHHH HL
set
reset
reset
V
Bat
ON OFF
NO
OVL
reset
set
reset
set
IN
I
OUT
I
D(lim1)
ST
FAULT
I
nom
OVL
Condition
HL
(OVL)
HLHL
SO
t<t
d(fault)
CS
Valid SPI cycles
OVL
I
nom
I*R
ON
V
OUT
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
(Normal Function)
HH HH HH HHHH HL
set
reset
reset
V
Bat
ON OFF
NO
OVL
reset
set
reset
set
reset reset
Figure 9 Over Load Behavior - Current Limitation (current limit 1)
OL_CurrLim2.vsd
td(off)
Inom
td(off) td(off)
IN ON OFF
OVL
Condition
OVL
I
OUT
ST
CS
V
OUT
FAULT
(OVL)
SO
(Normal Function)
HH
Valid SPI cycles
ID(lim2)
I*RON
HL HLHL HHHHHH
set
shutdown shutdown shutdown
reset
reset
VBat
reset
set
ILIM2 Failure
latched
ILIM2 Failure
latched
ILIM2 Failure
latched
set
td(off)
Inom
td(off) td(off)
IN ON OFF
OVL
Condition
OVL
I
OUT
ST
CS
V
OUT
FAULT
(OVL)
SO
(Normal Function)
HH
Valid SPI cycles
ID(lim2)
I*RON
HL HLHL HHHHHH
set
shutdown shutdown shutdown
reset
reset
VBat
reset
set
ILIM2 Failure
latched
ILIM2 Failure
latched
ILIM2 Failure
latched
set
Data Sheet 13 V1.5, 2012-08-17
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Electrical and Functional Description of Blocks
Figure 10 Over Load Behavior - Latched Shutdown (current limit 2)
5.3.3.2 Over Temperature Protection
A dedicated temperature sensor for each channel detects if the temperature of its channel exceeds the over
temperature shutdown threshold. If the channel temperature exceeds the over temperature shutdown threshold,
the overheated channel is switched off immediately to prevent destruction. At the same time (no delay), the over
temperature flag Tn is set. If the status outputs are used for diagnosis, the over temperature flag is cleared
immediately after the over temperature condition is no longer present. If using the SPI interface and fault pin for
diagnosis, the over temperature flag of the affected channel is cleared by the rising edge of the CS signal after a
successful SPI transmission.
The restart response of the channel can be programmed via SPI. If automatic autorestart is selected, after cooling
down, the channel is switched on again with thermal hysteresis ΔTj. If latching shutdown is selected, the channel
remains switched off even after cooling down. The channel can be restarted only if first turned off with either the
parallel input or SPI. In addition, the channel must first be turned off before the the over temperature flag of the
affected channel can be cleared by the rising edge of the CS signal after a successful SPI transmission.
For timing information, please refer to Figure 11 and Figure 12 for details.
OT_behaviour_Restart.vsd
HLHL (OVL)
Two Bit
Diagnostic:
IN
IOUT
ST
CS
VOUT
FAULT
SO
OT
Valid SPI cycles
H
H (OT)
OT Flag: LL
HH (Normal Function)
HH HH
L (No OT condition)
reset
reset
set (without delay time)
set
ONOFF
Output channel
with OT condition No OT condition
H
rewritten
HL
H
HL
H
Thermal toggling Thermal toggling Thermal toggling
HLHL (OVL)
Two Bit
Diagnostic:
IN
IOUT
ST
CS
VOUT
FAULT
SO
OT
Valid SPI cycles
H
H (OT)
OT Flag: LL
HH (Normal Function)
HH HH
L (No OT condition)
reset
reset
set (without delay time)
set
ONOFF
Output channel
with OT condition No OT condition
H
rewritten
HL
H
HL
H
Thermal toggling Thermal toggling Thermal toggling
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Electrical and Functional Description of Blocks
Data Sheet 14 V1.5, 2012-08-17
Figure 11 Over Temperature Behavior - Automatic Autorestart
OT_behaviour_Latch.vsd
HL
Two Bit
Diagnostic:
IN
I
OUT
ST
CS
V
OUT
FAULT
SO
OT
Valid SPI cycles
H
OT Flag: LL
HH HH HH (Normal Function)
L (No OT condition)
HL (OVL)
H (OT)
reset
reset
set
set
reset
ONOFF
Thermal shutdown
Output channel
with OT condition No OT condition
HL
H
rewritten
OT Failure
latched
HL
Two Bit
Diagnostic:
IN
I
OUT
ST
CS
V
OUT
FAULT
SO
OT
Valid SPI cycles
H
OT Flag: LL
HH HH HH (Normal Function)
L (No OT condition)
HL (OVL)
H (OT)
reset
reset
set
set
reset
ONOFF
Thermal shutdown
Output channel
with OT condition No OT condition
HL
H
rewritten
OT Failure
latched
Data Sheet 15 V1.5, 2012-08-17
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Electrical and Functional Description of Blocks
Figure 12 Over Temperature Behavior - Latched Shutdown
5.3.4 Reverse Current
In the case of reverse polarity when outputs are turned on, the power stages of the TLE8102SG are able to
conduct reverse current Irev, defined as current that flows from ground to the output pin. Please note that neither
the over load, over temperature, nor current sense diagnostics are functional in reverse current operation.
Additionally, it is possible for the supply current IVDD to be greater than 5 mA.
5.3.5 Reverse Polarity Protection
In the case of reverse polarity when outputs are turned off, the intrinsic body diode of the power transistor causes
power dissipation. The reverse current through the intrinsic body diode has to be limited by the connected load.
The VDD supply pin must be protected against reverse polarity externally. Please note that neither the over load,
over temperature, nor current sense diagnostics are functional in reverse current operation.
VDD = 4.5 V to 5.5 V, Tj = -40 ⋅C to +150 ⋅C, (unless otherwise specified)
all voltages with respect to ground, positive current flowing into pin
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
ON Resistance RDS(ON) –0.18 –ΩTJ = 25 °C,1)
VDD = 5 V,
ID = 2 A
–0.27 –ΩTJ = 125 °C,1)
VDD = 5 V,
ID = 2 A
–0.3 0.36 ΩTJ = 150 °C,
VDD = 5 V,
ID = 2 A
Output Clamping Voltage VDS(CL) 48 –60 Voutput OFF
Current Limit 1: Current limitation ID(lim1) 56.5 8 A –
Current Limit 2: Overload switch off ID(lim2) 910.5 12 AVDD ≥ 5 V
9 – 12 AVDD < 5 V,
TJ ≤ 125 °C
8 – 12 AVDD < 5 V,
TJ > 125 °C1)
1) Not subject to production test, specified by design.
Reverse Current per channel1)2)
2) Device functions normally, but supply current IVDD can be greater than 5 mA.
Irev – – 2 A –
Output Leakage Current ID(lkg) ––5μASleep mode active
Turn-On Time 1
Turn-On Time 2
tON –
–
5
20
10
50
μsID = 2 A,
resistive load
Turn-Off Time 1
Turn-Off Time 2
tOFF –
–
5
20
10
50
μsID = 2 A,
resistive load
Turn On slew rate
Slew rate 1
Slew rate 2
sON
1
–
5
1
20
5
V/μsVbat = 14 V, ID = 2 A,
resistive load, UDS
= 80% to 30%
Turn Off slew rate
Slew rate 1
Slew rate 2
sOFF
1
–
5
1
20
5
V/μsVbat = 14 V, ID = 2 A,
resistive load, UDS
= 30% to 80%
IC Overtemperature Warning1)
Hysteresis1)
Tw
T(w) hys
155
–
–
10
185
–
°C
K
–
–
Channel Overtemp. Shutdown1)
Hysteresis1)
Tth(sd)
T(sd)hys
170
–
–
10
200
–
°C
K
–
–
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Electrical and Functional Description of Blocks
Data Sheet 16 V1.5, 2012-08-17
Electrical Characteristics: Power Outputs
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
5.3.10
5.3.11
5.3.12
Data Sheet 17 V1.5, 2012-08-17
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Electrical and Functional Description of Blocks
5.4 Diagnostic Functions
The TLE8102SG provides diagnosis information about the device and about the load. The following diagnosis
functions are implemented:
• The protective functions (flags CLn and Tn) of channel n are registered in the diagnosis flag Pn.
• The open load diagnosis of channel n is registered in the diagnosis flag OLn.
• The under current diagnosis of channel n is registered in the diagnosis flag UCn.
• The short to ground monitor information of channel n is registered in the diagnosis flag SGn
The diagnosis information of the TLE8102SG can either be accessed by status (ST) pins or the SPI interface
and/or fault pin. With the exception of over temperature, a fault is only recognized if it lasts longer than the fault
delay time td(fault). If using the status pins for diagnosis, the status pins change state in normal operation to match
the input signal of the corresponding channel. If a fault condition appears and the fault delay time elapses, the
status pin for the channel shows the inverted input signal. This diagnosis flag is not latched. Therefore, if the fault
condition is removed, the status pins will indicate normal operation.
Unlike the status pins, when using the SPI interface and/or fault pin, diagnosis flags are latched in the diagnosis
register of the SPI interface. In this case, diagnosis flags are cleared by the rising edge of the CS signal after a
successful SPI transmission.
Please see Table 1 and Figure 13 for details.
Table 1 Diagnostic Information
Operating Condition Control
Input
Power
Output
Filter
Time
Status
Output
Fault
Output
Channel
Diagnosis
Bits
MSB, LSB
Channel
Overtemp.
Flag
Sleep Mode xoff –LH– – –
Normal Operation L
H
off
on
– L
H
H
H
H, H
H, H
L
L
Short to ground L
H
off
on
td(fault)
td(fault)
H
L
L
L
L, L
L, H
L
L
Open load,
Under current.1)
1) Short to ground/open load/ under current /overload/short-to-supply - events shorter than min. time td(fault) will not be
latched and not reported at the diagnosis pins.
L
H
off
on
td(fault)
td(fault)
H
L
L
L
L, H
L, H
L
L
Over load (current limit 1,
current limitation)1)
Hon td(fault) LLH, L L
Over load (current limit 2,
latching shutdown)2)
2) Overload/short-to-supply - events shorter than min. time td(off) will not be latched and not reported at the diagnosis pins.
Hoff td(off) LLH, L L
Overtemp. (autorestart) Hoff3)
3) Off as long as overtemperature occurs, restart after cooling down.
–LLH, L H
Overtemp. (latching
shutdown)
Hoff4)
4) Shutdown latch reset by falling input edge.
–LLH, L H
OUTn
IDS(PD)
SGn
VDD VDS(SG)
IDS(SG)
diagnosis.emf
protective functions
CLn
Tn
OR
SPI
MUX
00
01
10
OLn
VDS(OL)
CHn
gate control
Pn
GND
OR
STn /
FAULT
under current
detection
UCn
OR
IIS n
current sense
ISn
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Electrical and Functional Description of Blocks
Data Sheet 18 V1.5, 2012-08-17
Figure 13 Block Diagram of Diagnostic Functions
VDD = 4.5 V to 5.5 V, Tj = -40 ⋅C to +150 ⋅C, (unless otherwise specified)
all voltages with respect to ground, positive current flowing into pin
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
Open Load Detection Voltage
(Channel OFF)
VDS(OL) 0.5 ×
VDD
0.6 ×
VDD
0.7 ×
VDD
V –
Output Pull-down Current
(Channel OFF)
IPD(OL) 25 50 100 μA –
Fault Filtering Time td(fault) 50 100 200 μs –
Overload switch off delay time
(only current limit 2)
Td(off) 10
10
–
–
50
150
μsSlew rate 1
Slew rate 2
Short to Ground Detection Voltage VDS(SHG) 0.3 ×
VDD
0.4 ×
VDD
0.5 ×
VDD
V –
Output Pull-up Current
(Channel OFF)
IPU(SHG) -50 -100 -150 μA –
Under Current Detection Threshold
(Channel ON)
ID(OL) 100 170 300 mA –
Electrical Characteristics: Diagnostic Functions
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
Data Sheet 19 V1.5, 2012-08-17
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Electrical and Functional Description of Blocks
Figure 14 Open load (off) and Short to GND Diagnostics
UC_OL.vsd
I
D(UC)
t<t
d(fault)
LH LH
I
nom
LH LH
IN
I
OUT
ST
CS
V
OUT
FAULT
SO
(OL)
HH
OL(“OFF”)/UC(“ON”) Condition
OL/
UC
NO
OL/UC
ON OFF
V
DS(OL)
I*R
ON
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
reset
reset
LH LH LHHH HH HH HHHH
Valid SPI cycles
set
set
(Normal
Function)
(UC)
reset reset
rewritten
V
Bat
reset
reset
rewritten
I
D(UC)
t<t
d(fault)
LH LH
I
nom
LH LH
IN
I
OUT
ST
CS
V
OUT
FAULT
SO
(OL)
HH
OL(“OFF”)/UC(“ON”) Condition
OL/
UC
NO
OL/UC
ON OFF
V
DS(OL)
I*R
ON
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
reset
reset
LH LH LHHH HH HH HHHH
Valid SPI cycles
set
set
(Normal
Function)
(UC)
reset reset
rewritten
V
Bat
reset
reset
rewritten
Figure 15 Diagnostic at "Open Load/Under Current" Condition
UC_S_GND.vsd
I
D(UC)
t<t
d(fault)
LH LL
I
nom
LL LL
IN
I
OUT
ST
CS
V
OUT
FAULT
SO
(SHG)
HH
SHG(“OFF”) /UC(“ON”)
Condition
SHG/
UC
NO SHG/UC
ON OFF
V
DS(SHG)
I*R
ON
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
reset
reset
LH LH LHHH HH HH HHHH
Valid SPI cycles
set
(Normal
Function)
(UC)
reset reset
V
Bat
rewritten
reset
reset
set
set
rewritten
I
D(UC)
t<t
d(fault)
LH LL
I
nom
LL LL
IN
I
OUT
ST
CS
V
OUT
FAULT
SO
(SHG)
HH
SHG(“OFF”) /UC(“ON”)
Condition
SHG/
UC
NO SHG/UC
ON OFF
V
DS(SHG)
I*R
ON
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
t
d(fault)
reset
reset
LH LH LHHH HH HH HHHH
Valid SPI cycles
set
(Normal
Function)
(UC)
reset reset
V
Bat
rewritten
reset
reset
set
set
rewritten
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Electrical and Functional Description of Blocks
Data Sheet 20 V1.5, 2012-08-17
Figure 16 Diagnostic at "Short to GND/Under Current" Condition
5.5 Current Sense
The TLE8102SG includes an integrated current sense feature. If the device is programmed (via SPI) to use this
feature, the current source IIS of the current sense pin becomes active and generates a pull-down current
proportional to the load current of the selected channel. An external pull-up resistor must be connected to the
current sense pin to generate a voltage signal proportional to the load current of the selected channel. To achieve
the specified accuracy for current sensing, the voltage VIS at the current sense pin must always be greater than or
equal to 2 V. The current source IIS can also be programmed to generate a current proportional to the sum of the
load current of both channels.
VDD = 4.5 V to 5.5 V, Tj = -40 ⋅C to +150 ⋅C, (unless otherwise specified)
all voltages with respect to ground, positive current flowing into pin
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
Current Sense Precision (single
channel)1)
1) If the summed current is sensed the tolerances of the single channels are added.
IFB/IOUT
PIS
0.50
0.80
0.90
0.93
0.94
0.95
1.00
1.50
1.20
1.10
1.07
1.06
1.05
mA/A VDD = 5 V,
UCO1 ≥ 2 V
ID = 100 mA,
ID = 200 mA,
ID = 500 mA,
ID = 1 A,
ID = 3 A,
ID = 5 A,
Current Sense Temperature
Deviation 3) at
1) 2)
2) Not subject to production test, specified by design.
3) Temperature Variation of one single device.
IStemp
- 25
-10
-4
-3
-3
-3
PIS(25°C,
ID)
+25
+10
+4
+3
+3
+3
%VDD = 5 V,
UCO1 ≥ 2 V
ID = 100 mA,
ID = 200 mA,
ID = 500 mA,
ID = 1 A,
ID = 3 A,
ID = 5 A,
Current Sense Settle time2) tIS ––4μsUCO1 ≥ 2 V,
Rsense = 2.5 kΩ
(IDmax = 1 A)
Current Sense Settle time2) tIS ––2μsUCO1 ≥ 2 V,
Rsense = 500 Ω
(IDmax = 5 A)
Output Tri-state Leakage Current ISOlkg -10 010 μACS = H,
0 ≤ VSO ≤ VDD
FAULT Output Low Voltage VFAULTL – – 0.4 VIFAULT = 1.6 mA
Status Output Low Voltage VST – – 0.4 VIST = 1.6 mA
Data Sheet 21 V1.5, 2012-08-17
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Electrical and Functional Description of Blocks
Electrical Characteristics: Current Sense
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
5.5.6
5.5.7
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 I
D
[A]
1
0.90
0.80
0.70
0.60
1.40
1.30
1.20
1.10
I
FB
/I
OUT
[mA/A]
Cur rent_Sense_points.vsd
1.50
0.60
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Electrical and Functional Description of Blocks
Data Sheet 22 V1.5, 2012-08-17
Figure 17 Current Sense Precision
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 I
D
[A]
1
0.90
0.80
0.70
0.60
1.40
1.30
1.20
1.10
I
FB
/I
OUT
[mA/A]
Current_Sense_range.vsd
Expected Distribution of Current Sense Precision. Not testet.
1.50
0.50
Figure 18 Current Sense Precision - range of expected distribution.
Data Sheet 23 V1.5, 2012-08-17
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Electrical and Functional Description of Blocks
5.6 SPI Interface
The diagnosis and control interface is based on a serial peripheral interface (SPI).
The SPI is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CS. Data is
transferred by the lines SI and SO at the data rate given by SCLK. The falling edge of CS indicates the beginning
of a data access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising
edge of SCLK. Each access must be terminated by a rising edge of CS. The interface provides daisy chain
capability.
6 5
6 5MSB
MSB LSB2 1
2 1 LSB
4
4
3
3
SO
SI
CS
SCLK
time
Figure 19 Serial Peripheral Interface
The SPI protocol is described in Section 6. All registers are reset to default values after power-on reset or if the
chip is programmed via SPI to enter sleep mode.
5.6.1 SPI Signal Description
CS - Chip Select: The system micro controller selects the TLE8102SG by means of the CS pin. Whenever the
pin is in low state, data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are
ignored and SO is forced into a high impedance state.
CS High to Low transition:
• The diagnosis information is transferred into the shift register.
CS Low to High transition:
• Command decoding is only done after the falling edge of CS if the command is valid.
• Data from shift register is transferred into the input matrix register.
• The diagnosis flags are cleared.
SCLK - Serial Clock: This input pin clocks the internal shift register. The serial input (SI) transfers data into the
shift register on the falling edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising
edge of the serial clock. It is essential that the SCLK pin is in low state whenever chip select CS makes any
transition.
SI - Serial Input: Serial input data bits are shifted in at this pin, the most significant bit first. SI information is read
on the falling edge of SCLK. The 8 bit input data consist of two parts (control and data). Please refer to Section 6
for further information.
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Electrical and Functional Description of Blocks
Data Sheet 24 V1.5, 2012-08-17
SO - Serial Output: Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance
state until the CS pin goes to low state. New data will appear at the SO pin following the rising edge of SCLK.
Please refer to Section 6 for further information.
5.6.2 Daisy Chain Capability
The SPI of TLE8102SG is daisy chain capable. In this configuration several devices are activated by the same
signal CS. The SI line of one device is connected with the SO line of another device (see Figure 20), which builds
a chain. The ends of the chain are connected with the output and input of the master device, SO and SI
respectively. The master device provides the master clock SCLK, which is connected to the SCLK line of each
device in the chain.
SI
device 1
SPI
SCLK
SO
CS
SI
device 2
SPI
SCLK
SO
CS
SI
device 3
SPI
SCLK
SO
CS
SO
SI
CS
SCLK
Figure 20 Daisy Chain Configuration
In the SPI block of each device, there is one shift register where one bit from SI line is shifted in each SCLK. The
bit shifted out can be seen at SO. After 8 SCLK cycles, the data transfer for one device has been finished. In single
chip configuration, the CS line must go high to make the device accept the transferred data. In daisy chain
configuration the data shifted out at device 1 has been shifted in to device 2. When using three TLE8102SG
devices in daisy chain, three times 8 bits have to be shifted through the devices. After that, the CS line must go
high (see Figure 21).
SI
SO
CS
CLK
SI device 3 SI device 2 SI device 1
SO device 3 SO device 2 SO device 1
time
Figure 21 Data Transfer in Daisy Chain Configuration
Electrical Characteristics: SPI Interface
VDD = 4.5 V to 5.5 V, Tj = -40 ⋅C to +150 ⋅C, (unless otherwise specified)
all voltages with respect to ground, positive current flowing into pin
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
5.6.1 Input Pull-down Current (SI, SCLK) IIN(SI,SCLK) 10 20 50 μA –
5.6.2 Input Pull-up Current (CS)IIN(CS) 10 20 50 μA –
Data Sheet 25 V1.5, 2012-08-17
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Electrical and Functional Description of Blocks
5.6.3 SO High State Output Voltage VSOH VDD -
0.4
––VISOH = 2 mA
5.6.4 SO Low State Output Voltage VSOL – – 0.4 VISOL = 2.5 mA
5.6.5 Serial Clock Frequency
(depending on SO load)
fSCK DC –5MHz –
5.6.6 Serial Clock Period (1/fsclk)tp(SCK) 200 ––ns –
5.6.7 Serial Clock High Time tSCKH 80 ––ns –
5.6.8 Serial Clock Low Time tSCKL 80 ––ns –
5.6.9 Enable Lead Time (falling edge of
CS to rising edge of SCLK)
tlead 200 ––ns –
5.6.10 Enable Lag Time (falling edge of
SCLK to rising edge of CS)
tlag 200 ––ns –
5.6.11 Data Setup Time (required time SI
to falling of SCLK)
tSU 20 ––ns –
5.6.12 Data Hold Time (falling edge of
SCLK to SI)
tH20 ––ns –
5.6.13 Disable Time1) tDIS – – 150 ns –
5.6.14 Transfer Delay Time2) (CS high time
between two accesses)
tdt 300 ––ns –
5.6.15 Data Valid Time tvalid –
–
–
–
120
150
ns CL = 50 pF1)
CL = 100 pF1)
1) Not subject to production test, specified by design.
2) This time is necessary between two write accesses. To get the correct diagnostic information, the transfer delay time has
to be extended to the maximum fault delay time td(fault)max = 200 μs.
Electrical Characteristics: SPI Interface (cont’d)
VDD = 4.5 V to 5.5 V, Tj = -40 ⋅C to +150 ⋅C, (unless otherwise specified)
all voltages with respect to ground, positive current flowing into pin
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Electrical and Functional Description of Blocks
Data Sheet 26 V1.5, 2012-08-17
5.7 Timing Diagrams
CS
SCLK
SI
tCS(lead) tCS(t d)
tCS(lag)
tSCLK(H) tSCLK(L)
tSCLK(P)
tSI(su) tSI(h)
SO
t
SO(v) tSO(dis)
0.7V
dd
0.2V
dd
0.7V
dd
0.2V
dd
0.7V
dd
0.2V
dd
0.7V
dd
0.2V
dd
spi_timing_TLE8102L.vsd
Figure 22 Serial Interface Timing Diagram
Data Sheet 27 V1.5, 2012-08-17
TLE 8102 SG
Smart Dual Channel Powertrain Switch
SPI Control
6SPI Control
The SPI protocol of the TLE8102SG provides two types of registers: control and diagnosis. After power-on reset,
all register bits are set to default values.
Serial Input
Default Value: xxxxH
Field Bits Type Description
CMD 7:5 wCommand
001 Diagnosis only: The requested data is shifted out at SO.
The data bits are ignored.
010 Output Configure: Configures the behavior of the power
outputs.
011 I/O Configure: Configures the behavior of the
I/O ports.
100 Reset Registers: Resets all internal registers to their reset
values. The data bits are ignored.
101 Sleep Mode: Activates the low quiescent mode. In sleep
mode, only the command “wake up” will be accepted.
Other commands will not be accepted. Wake up can be
performed by sending the wake up command or by
performing an undervoltage reset. The data bits are
ignored.
110 Wake up: Deactivates the sleep mode. After time delay
twake, the device becomes fully functional. The data bits
are ignored.
111 Channels ON/OFF: Turns on/off the power outputs (if
configured for serial control)
000 No command: Not accepted as a valid command and the
data bits will be ignored. Additionally, the diagnosis register
will not be reset.
DATA 4:0 wData
Data written to register selected by CMD
76543210
CMD DATA
wwwwwwww
Output Configure
Default Value: 00H
76543210
0 1 0 LIM2 LIM1 RES SLE2 SLE1
wwwwwwww
Field Bits Type Description
LIMnn+2 wOver load current limitation channel n
0 Current limit 2 is active (IDn(lim2))
1 Current limit 1 is active (IDn(lim1))
Data Sheet 28 V1.5, 2012-08-17
TLE 8102 SG
Smart Dual Channel Powertrain Switch
SPI Control
RES 2 w Over temperature behavior of all channels
0 Automatic autorestart of a channel after cooling down
1 Latching shutdown at over temperature
SLEnn-1 wSlew rate of channel n
0 Slew rate 1
1 Slew rate 2
Field Bits Type Description
DIA 4 w Status / SPI of diagnostic information
0 Diagnosis output with one status output per channel (ST1,
ST2)
1 Diagnosis output with SPI interface (SO) and fault pin /
current sense
BOL 3:2 wParallel / Serial control of all channels
00 With parallel input only (IN1, IN2)
01 With logic OR operation of INn and data bits
10 With logic AND operation of INn and data bits
11 With SPI interface only
SENS 1:0 wFunction of fault / current sense output
00 General fault pin
01 Current sense output of channel 1 (IIS1)
10 Current sense output of channel 2 (IIS2)
11 Current sense output of channel 1+2 (IIS1+IIS2)
Field Bits Type Description
CTRLnn+2 wSPI control of channel n (CHnIN)
0 Output off
1 Output on
Field Bits Type Description
I/O Configure
Default Value: 00H
76543210
0 1 1 DIA BOL SENS
wwwwwwww
Channels ON/OFF
Default Value: 00H
76543210
1 1 1 CTRL2 CTRL1 X X X
wwwwwwww
Data Sheet 29 V1.5, 2012-08-17
TLE 8102 SG
Smart Dual Channel Powertrain Switch
SPI Control
E
Field Bits Type Description
CHn 2n+1: 2n rStandard Diagnosis for Channel n
00 Short circuit to ground
01 Open load / Under current
10 Over load / over temperature
11 Normal operation
Channel over
temp.
1 r Channel Over Temperature Flag
0 No channel has an over temperature condition
1 One or both channels has an over temperature condition
IC
Over temp.
0 r Device Over Temperature Flag
0 IC temperature is below IC over temperature warning
threshold Tw
1 IC temperature has exceeded IC over temperature warning
threshold Tw
Serial Output (Standard Diagnosis)
Default Value: FFH
76543210
–– CH2
(CH21 CH20)
CH1
(CH11 CH10)
Channel
Over temp.
IC
Over temp.
rrrrrrrr
Data Sheet 30 V1.5, 2012-08-17
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Application Description
7 Application Description
IN1
IN2
ST2
SCLK
CS
SI
VDD
control, protection and diagnosis
12V
5V
SPI
LDO
PWM
I/O
ST1
µC
I/O
PWM
OUT1
OUT2
10 µF
10
kOhm
AppDiag_Status.vsd
10
kOhm
Figure 23 Application Circuit using Status Outputs only
IN1
IN2
SO
SCLK
CS
SI
VDD
contr ol, protection and diagnosis
12V
5V
SPI
LDO
PWM
I/O
IS1 /
IS2 /
IS1+2
µC
I/O
PWM
OUT1
OUT2
10 µF
500
Ohm
Figure 24 Application Circuit using SPI and Current Sense Output
IN1
IN2
SO
SCLK
CS
SI
VDD
control, protection and diagnosis
12V
5V
SPI
LDO
PWM
I/O
FAULT
µC
I/O
PWM
OUT1
OUT2
10 µF
10kOhm
AppDiag_SPI_Fault.vsd
Data Sheet 31 V1.5, 2012-08-17
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Application Description
Figure 25 Application Circuit using SPI and Fault Flag
AppDiag_noSPI.vsd
IN1
IN2
ST 2
SCLK
CS
SI
VDD
control, protection and diagnosis
ST1
OUT 1
OUT 2
Micro Controller
VBatt
I/O
I/O
I/O
I/O
10k
10µF
10k
Figure 26 Application Circuit using parallel Inputs and Status Outputs, no SPI.
Data Sheet 32 V1.5, 2012-08-17
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Package Outlines
8 Package Outlines
1) Does not include plastic or metal protrusion of
(Heatslug)
STANDOFF
Index Marking
1
12
2.6 MAX.
7.8
(Body)
2.35
±0.1
0+0.1
(4.4 Mold)
6
(Mold)
7
6 1
7 12
0.8
±0.1
(1.55)
0.25
5˚
±3˚
Heatslu
(Metal)
0.1
10.3
±0.3
0.25B
7.5
±0.1
1)
B
+0.075
-0.035
7.6
+0.13
-0.1
0.7
±0.15
B
6.4
±0.1
1)
+0.13
0.4
0.25
M
AC B
12x
15 x=5
(1.8 Mold)
±0.1
1.6
±0.1
(Metal)
4.2
(Metal)
5.1
±0.1
1
Bottom View
Figure 27 PG-DSO-12-11 (Plastic Dual Small Outline Package) - Green Product.
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.Dimensions in mm
Green Product
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Data Sheet 33 V1.5, 2012-08-17
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Revision History
9 Revision History
Version Date Changes
2012-08-17: Version 1.5: Data Sheet:
V1.5 2012-08-17 Figure 26 corrected. No Functional Change
08-05-08: Version 1.4: Data Sheet:
V1.4 08-05-08 Table 1 corrected. Functionality not changed.
V1.4 08-05-08 Figure 14 corrected. No functional change.
08-04-24: Version 1.3: Data Sheet:
V1.3 08-04-24 Data Sheet released
Edition 2012-08-17
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2012.
All Rights Reserved.
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characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values
stated herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
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question please contact your nearest Infineon Technologies Office.
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