PIC24HJ128GP310-I/PT - Microchip Technology, Inc.

PIC24H Family

Data Sheet

High-Performance, 16-bit

Microcontrollers

Information contained in this publication regarding device

applications a nd the like is p ro vid ed only f or yo ur c o n ve nience

and may be supers eded by updates. It is y our res po nsibilit y to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICST ART ,

PRO MAT E, Pow erSmart, rfPIC and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,

SEEV AL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active

Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLI NK, PIC kit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInf o, PowerMate, PowerTool, REAL ICE , rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporat ed in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrit y of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violat ion of the Digital Millennium Copyright Act. If suc h ac t s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

T empe, Arizona, Gresham, Oregon and Mountain View , California. The

Company’s quality system processes and procedures are for its

PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

PIC24H

Operating Range:

• DC – 40 MIPS (40 MIPS @ 3.0-3.6V,

-40°C to +85°C)

• Industri al tem pera ture range (-40°C to +85°C )

High-Performance DSC CPU:

• Modified Harvard architecture

• C co mpiler optimized instruction set

• 16-bit wide data path

• 24-bit wide instructions

• Linear program memor y addressing up to 4M

instruction words

• Linear data memory addressing up to 64 Kbytes

• 71 base inst ructi ons: most ly 1 wo rd/1 cycle

• Sixteen 16-bit General Purpose Registers

• Flexible and powerful Indirect Addressing modes

• Software stack

• 16 x 16 multiply operations

• 32/16 and 16/16 divide operations

• Up to ±16-bit data shifts

Direct Memory Access (DMA):

• 8-chann el hardware DMA

• 2 Kbytes dual ported DMA buffer area

(DMA RAM) to store data transferred via DMA:

- Allows data transfer between RAM and a

peripheral while CPU is executing code

(no cycle stealing)

• Most peripherals support DMA

Interrupt Controller:

• 5-cycle latency

• 118 interrupt vectors

• Up to 61 available interrupt sources

• Up to 5 external interrupts

• 7 programmable priority levels

• 5 processor exceptions

Digital I/O:

• Up to 85 programmable digital I /O pins

• Wake-up/Interrupt-on-Change on up to 24 pins

• Output pins can drive from 3.0V to 3.6V

• All digital input pins are 5V tolerant

• 4 mA sink on all I/O pins

On-Chip Flash and SRAM:

• Flash program memory, up to 256 Kbytes

• Data SRAM, up to 16 Kbytes (includes 2 Kbytes

of DMA RAM)

System Management:

• Flexible clock options:

- External, crystal, resonator, internal RC

- Fully integrated PLL

- Extremely low jitter PLL

• Power-up Timer

• Oscillator Start-up Timer/Stabilizer

• Watchdog Timer with its own RC oscillator

• Fail- Safe C lock Monitor

• Reset by multiple sources

Power Management:

• On-chip 2.5V voltage regulator

• Switch between clock sources in real time

• Idle, Sleep and Doze modes with fast wake-up

Timers/Capture/Compare/PWM:

• Timer/Counters, up to nine 16-bit timers:

- Can pair up to make four 32-bit timers

- 1 timer runs as Re al-T ime Clock with ex ternal

32.768 kHz oscillator

- Programmable prescaler

• Input Capture (up to 8 channels):

- Capture on up, down or both edges

- 16-bit capture input functions

- 4-deep FIFO on each capture

• Output Compare (up to 8 channels):

- Single or Dual 16-Bit Compare mode

- 16-bit Glitchless PWM mode

High-Performance, 16-bit Microcontrollers

PIC24H

Communication Modules:

• 3-wire SPI (up to 2 modules):

- Framing supports I/O interface to simple

codecs

- Supports 8-bit and 16-bit data

- Supports all serial clock formats and

sampling modes

•I

2C™ (up to 2 modules):

- Full Multi-Master Sl ave m ode support

- 7-bit and 10-bit addressing

- Bus collision detection and arbitration

- Integrated signal conditioning

- Slave address masking

• UART (up to 2 modules):

- Interrupt on addr ess bit detect

- Interrupt on UART error

- Wake-up on Start bit from Sleep mode

- 4-character TX and RX FIFO buffers

- LIN bus support

-IrDA

® encoding and decoding in hardware

- High-Speed Baud mode

- Hardware Flow Control with CTS and RTS

• Enhanced CAN (ECAN™ module) 2.0B active

(up to 2 modules):

- Up to 8 transmit and up to 32 receive buffers

- 16 receive filters and 3 masks

- Loopback, Listen Only and Listen All

Messages modes for diagnostics and bus

monitoring

- Wake-up on CAN message

- Automatic processing of Remote

Transmission Requests

- FIFO mode using DMA

- DeviceNet™ addressing support

Analog-to-Di gital Converters:

• Up to two A/D modules in a device

• 10-bit, 1.1 Msps or 12-bit, 500 ksps conversion:

- 2, 4 or 8 simultaneous samples

- Up to 32 input channels with auto-scanning

- Conversion start can be manual or

synchronized with 1 of 4 trigger sources

- Conversion possible in Sleep mode

- ±2 LSb max integral nonlinearity

- ±1 LSb max differential nonlinearity

CMOS Flash Technology:

• Low-power, high-speed Flash technology

• Fully static design

• 3.3V (±10%) operating voltage

• Industrial temperature

• Low-power consumption

Packaging:

• 100-pin TQ FP (1 4x14x1 mm and 12x12x1 mm)

• 64-pin TQFP (10x10x1 mm)

Note: See the device variant tables for exact

peripheral features per device.

PIC24H

PIC24H PRODUCT FAMILIES

The PIC24H General Purpose Family is ideal for a wide

variety of 16-bit MCU embedded applications. The

device names, pin counts, memory sizes and periph-

eral availab ility of each f amily ar e liste d below, fol lowed

by their pinout diagrams.

PIC24H General Purpose Family Variants

Device Pins Program

Flash

Memory (KB)

RAM(1) (KB)

DMA Channels

Timer 16-bit

Input Ca pture

Output Compare

Std. PWM

Codec

Interface

ADC

UART

SPI

I2C™

CAN

I/O Pi ns (M ax)(2)

Packages

PIC24HJ64GP206 64 64 8 8 9 8 8 0 1 ADC,

18 ch 2 2 1 0 53 PT

PIC24HJ64GP210 100 64 8 8 9 8 8 0 1 ADC,

32 ch 2 2 2 0 85 PF, PT

PIC24HJ64GP506 64 64 8 8 9 8 8 0 1 ADC,

18 ch 222 153 PT

PIC24HJ64GP510 100 64 8 8 9 8 8 0 1 ADC,

32 ch 222 185PF, PT

PIC24HJ128GP206 64 128 8 8 9 8 8 0 1 ADC,

18 ch 2 2 2 0 53 PT

PIC24HJ128GP210 100 128 8 8 9 8 8 0 1 ADC,

32 ch 2 2 2 0 85 PF, PT

PIC24HJ128GP506 64 128 8 8 9 8 8 0 1 ADC,

18 ch 222 153 PT

PIC24HJ128GP510 100 128 8 8 9 8 8 0 1 ADC,

32 ch 222 185PF, PT

PIC24HJ128GP306 64 128 16 8 9 8 8 0 1 ADC,

18 ch 2 2 2 0 53 PT

PIC24HJ128GP310 100 128 16 8 9 8 8 0 1 ADC,

32 ch 2 2 2 0 85 PF, PT

PIC24HJ256GP206 64 256 16 8 9 8 8 0 1 ADC,

18 ch 222 053 PT

PIC24HJ256GP210 100 256 16 8 9 8 8 0 1 ADC,

32 ch 222 085PF, PT

PIC24HJ256GP610 100 256 16 8 9 8 8 0 2 ADC,

32 ch 2 2 2 2 85 PF, PT

Note 1: R AM size is inclusive of 2 Kbytes DMA RAM.

2: Maximum I/O pin count includes pins shared by the peripheral functions.

PIC24H

Pin Diagrams

64-Pin TQFP

13 36

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14

PGD2/EMUD2/SOSCI/T4CK/CN1/RC13

OC1/RD0

IC4/INT4/RD11

IC2/U1CTS/INT2/RD9

IC1/INT1/RD8

VSS

OSC2/CLKO/RC15

OSC1/CLKIN/RC12

VDD

SCL1/RG2

U1RTS/SCK1/INT0/RF6

U1RX/SDI1/RF2

U1TX/SDO1/RF3

RG15

AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

VSS

VDD

AN3/CN5/RB3

AN2/SS1/CN4/RB2

PGC3/EMUC3/AN1/VREF-/CN3/RB1

PGD3/EMUD3/AN0/VREF+/CN2/RB0

OC8/CN16/RD7

RG13

RG12

RG14

VDDCORE

RG1

RF1

RG0

OC2/RD1

OC3/RD2

PGC1/EMUC1/AN6/OCFA/RB6

PGD1/EMUD1/AN7/RB7

AVDD

AVSS

U2CTS/AN8/RB8

AN9/RB9

TMS/AN10/RB10

TDO/AN11/RB11

VSS

VDD

TCK/AN12/RB12

TDI/AN13/RB13

U2RTS/AN14/RB14

AN15/OCFB/CN12/RB15

U2TX/CN18/RF5

U2RX/CN17/RF4

SDA1/RG3

SS2/T5CK/CN11/RG9

AN5/IC8/CN7/RB5

AN4/IC7/CN6/RB4

IC3/INT3/RD10

VDD

RF0

OC4/RD3

OC7/CN15/RD6

OC6/IC6/CN14/RD5

OC5/IC5/CN13/RD4

PIC24HJ64GP206

PIC24HJ128GP206

PIC24HJ256GP206

Note: The PIC24HJ64GP206 device does not have the SCL2 and SDA2 pins.

PIC24H

Pin Diagrams (Continued)

64-Pin TQFP

13 36

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14

PGD2/EMUD2/SOSCI/T4CK/CN1/RC13

OC1/RD0

IC4/INT4/RD11

IC2/U1CTS/INT2/RD9

IC1/INT1/RD8

VSS

OSC2/CLKO/RC15

OSC1/CLKIN/RC12

VDD

SCL1/RG2

U1RTS/SCK1/INT0/RF6

U1RX/SDI1/RF2

U1TX/SDO1/RF3

RG15

AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

VSS

VDD

AN3/CN5/RB3

AN2/SS1/CN4/RB2

PGC3/EMUC3/AN1/VREF-/CN3/RB1

PGD3/EMUD3/AN0/VREF+/CN2/RB0

OC8/CN16/RD7

RG13

RG12

RG14

VDDCORE

RG1

RF1

RG0

OC2/RD1

OC3/RD2

PGC1/EMUC1/AN6/OCFA/RB6

PGD1/EMUD1/AN7/RB7

AVDD

AVSS

U2CTS/AN8/RB8

AN9/RB9

TMS/AN10/RB10

TDO/AN11/RB11

VSS

VDD

TCK/AN12/RB12

TDI/AN13/RB13

U2RTS/AN14/RB14

AN15/OCFB/CN12/RB15

U2TX/SCL2/CN18/RF5

U2RX/SDA2/CN17/RF4

SDA1/RG3

SS2/T5CK/CN11/RG9

AN5/IC8/CN7/RB5

AN4/IC7/CN6/RB4

IC3/INT3/RD10

VDD

RF0

OC4/RD3

OC7/CN15/RD6

OC6/IC6/CN14/RD5

OC5/IC5/CN13/RD4

PIC24HJ128GP306

PIC24H

Pin Diagrams (Continued)

64-Pin TQFP

13 36

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14

PGD2/EMUD2/SOSCI/T4CK/CN1/RC13

OC1/RD0

IC4/INT4/RD11

IC2/U1CTS/INT2/RD9

IC1/INT1/RD8

VSS

OSC2/CLKO/RC15

OSC1/CLKIN/RC12

VDD

SCL1/RG2

U1RTS/SCK1/INT0/RF6

U1RX/SDI1/RF2

U1TX/SDO1/RF3

COFS/RG15

AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

VSS

VDD

AN3/CN5/RB3

AN2/SS1/CN4/RB2

PGC3/EMUC3/AN1/VREF-/CN3/RB1

PGD3/EMUD3/AN0/VREF+/CN2/RB0

OC8/CN16/RD7

CSDO/RG13

CSDI/RG12

CSCK/RG14

VDDCORE

RG1

C1TX/RF1

RG0

OC2/RD1

OC3/RD2

PGC1/EMUC1/AN6/OCFA/RB6

PGD1/EMUD1/AN7/RB7

AVDD

AVSS

U2CTS/AN8/RB8

AN9/RB9

TMS/AN10/RB10

TDO/AN11/RB11

VSS

VDD

TCK/AN12/RB12

TDI/AN13/RB13

U2RTS/AN14/RB14

AN15/OCFB/CN12/RB15

U2TX/SCL2/CN18/RF5

U2RX/SDA2/CN17/RF4

SDA1/RG3

SS2/T5CK/CN11/RG9

AN5/IC8/CN7/RB5

AN4/IC7/CN6/RB4

IC3/INT3/RD10

VDD

C1RX/RF0

OC4/RD3

OC7/CN15/RD6

OC6/IC6/CN14/RD5

OC5/IC5/CN13/RD4

PIC24HJ64GP506

PIC24HJ128GP506

PIC24H

Pin Diagrams (Continued)

OC6/CN14/RD5

OC5/CN13/RD4

IC6/CN19/RD13

IC5/RD12

OC4/RD3

OC3/RD2

OC2/RD1

AN23/CN23/RA7

AN22/CN22/RA6

AN26/RE2

RG13

RG12

RG14

AN25/RE1

AN24/RE0

RG0

AN28/RE4

AN27/RE3

RF0

DDCORE

PGD2/EMUD2/SOSCI/CN1/RC13

OC1/RD0

IC3/RD10

IC2/RD9

IC1/RD8

IC4/RD11

SDA2/RA3

SCL2/RA2

OSC2/CLKO/RC15

OSC1/CLKIN/RC12

SCL1/RG2

SCK1/INT0/RF6

SDI1/RF7

SDO1/RF8

SDA1/RG3

U1RX/RF2

U1TX/RF3

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14

REF

+/RA10

REF

-/RA9

AN8/RB8

AN9/RB9

AN10/RB10

AN11/RB11

U2CTS/RF12

U2RTS/RF13

IC7/U1CTS/CN20/RD14

IC8/U1RTS/CN21/RD15

PGC1/EMUC1/AN6/OCFA/RB6

PGD1/EMUD1/AN7/RB7

U2TX/CN18/RF5

U2RX/CN17/RF4

AN29/RE5

AN30/RE6

AN31/RE7

AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2

AN18/T4CK/T9CK/RC3

AN19/T5CK/T8CK/RC4

SCK2/CN8/RG6

TMS/RA0

AN20/INT1/RA12

AN21/INT2/RA13

AN5/CN7/RB5

AN4/CN6/RB4

AN3/CN5/RB3

AN2/SS1/CN4/RB2

SDI2/CN9/RG7

SDO2/CN10/RG8

PGC3/EMUC3/AN1/CN3/RB1

PGD3/EMUD3/AN0/CN2/RB0

RG15

SS2/CN11/RG9

MCLR

AN12/RB12

AN13/RB13

AN14/RB14

AN15/OCFB/CN12/RB15

RG1

RF1

OC8/CN16/RD7

OC7/CN15/RD6

TDO/RA5

INT4/RA15

INT3/RA14

TDI/RA4

TCK/RA1

100-Pin TQFP

PIC24HJ64GP210

PIC24HJ128GP210

100

PIC24HJ128GP310

PIC24HJ256GP210

PIC24H

Pin Diagrams (Continued)

OC6/CN14/RD5

OC5/CN13/RD4

IC6/CN19/RD13

IC5/RD12

OC4/RD3

OC3/RD2

OC2/RD1

AN23/CN23/RA7

AN22/CN22/RA6

AN26/RE2

RG13

RG12

RG14

AN25/RE1

AN24/RE0

RG0

AN28/RE4

AN27/RE3

C1RX/RF0

DDCORE

PGD2/EMUD2/SOSCI/CN1/RC13

OC1/RD0

IC3/RD10

IC2/RD9

IC1/RD8

IC4/RD11

SDA2/RA3

SCL2/RA2

OSC2/CLKO/RC15

OSC1/CLKIN/RC12

SCL1/RG2

SCK1/INT0/RF6

SDI1/RF7

SDO1/RF8

SDA1/RG3

U1RX/RF2

U1TX/RF3

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14

REF

+/RA10

REF

-/RA9

AN8/RB8

AN9/RB9

AN10/RB10

AN11/RB11

U2CTS/RF12

U2RTS/RF13

IC7/U1CTS/CN20/RD14

IC8/U1RTS/CN21/RD15

PGC1/EMUC1/AN6/OCFA/RB6

PGD1/EMUD1/AN7/RB7

U2TX/CN18/RF5

U2RX/CN17/RF4

AN29/RE5

AN30/RE6

AN31/RE7

AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2

AN18/T4CK/T9CK/RC3

AN19/T5CK/T8CK/RC4

SCK2/CN8/RG6

TMS/RA0

AN20/INT1/RA12

AN21/INT2/RA13

AN5/CN7/RB5

AN4/CN6/RB4

AN3/CN5/RB3

AN2/SS1/CN4/RB2

SDI2/CN9/RG7

SDO2/CN10/RG8

PGC3/EMUC3/AN1/CN3/RB1

PGD3/EMUD3/AN0/CN2/RB0

RG15

SS2/CN11/RG9

MCLR

AN12/RB12

AN13/RB13

AN14/RB14

AN15/OCFB/CN12/RB15

RG1

C1TX/RF1

OC8/CN16/RD7

OC7/CN15/RD6

TDO/RA5

INT4/RA15

INT3/RA14

TDI/RA4

TCK/RA1

100-Pin TQFP

PIC24HJ64GP510

100

PIC24HJ128GP510

PIC24H

Pin Diagrams (Continued)

OC6/CN14/RD5

OC5/CN13/RD4

IC6/CN19/RD13

IC5/RD12

OC4/RD3

OC3/RD2

OC2/RD1

AN23/CN23/RA7

AN22/CN22/RA6

AN26/RE2

RG13

RG12

RG14

AN25/RE1

AN24/RE0

C2RX/RG0

AN28/RE4

AN27/RE3

C1RX/RF0

DDCORE

PGD2/EMUD2/SOSCI/CN1/RC13

OC1/RD0

IC3/RD10

IC2/RD9

IC1/RD8

IC4/RD11

SDA2/RA3

SCL2/RA2

OSC2/CLKO/RC15

OSC1/CLKIN/RC12

SCL1/RG2

SCK1/INT0/RF6

SDI1/RF7

SDO1/RF8

SDA1/RG3

U1RX/RF2

U1TX/RF3

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14

REF

+/RA10

REF

-/RA9

AN8/RB8

AN9/RB9

AN10/RB10

AN11/RB11

U2CTS/RF12

U2RTS/RF13

IC7/U1CTS/CN20/RD14

IC8/U1RTS/CN21/RD15

PGC1/EMUC1/AN6/OCFA/RB6

PGD1/EMUD1/AN7/RB7

U2TX/CN18/RF5

U2RX/CN17/RF4

AN29/RE5

AN30/RE6

AN31/RE7

AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2

AN18/T4CK/T9CK/RC3

AN19/T5CK/T8CK/RC4

SCK2/CN8/RG6

TMS/RA0

AN20/INT1/RA12

AN21/INT2/RA13

AN5/CN7/RB5

AN4/CN6/RB4

AN3/CN5/RB3

AN2/SS1/CN4/RB2

SDI2/CN9/RG7

SDO2/CN10/RG8

PGC3/EMUC3/AN1/CN3/RB1

PGD3/EMUD3/AN0/CN2/RB0

RG15

SS2/CN11/RG9

MCLR

AN12/RB12

AN13/RB13

AN14/RB14

AN15/OCFB/CN12/RB15

C2TX/RG1

C1TX/RF1

OC8/CN16/RD7

OC7/CN15/RD6

TDO/RA5

INT4/RA15

INT3/RA14

TDI/RA4

TCK/RA1

100-Pin TQFP

100

PIC24HJ256GP610

PIC24H
DS70175D-page 10 Preliminary © 2006 Microchip Technology Inc.
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 13
2.0 CPU............................................................................................................................................................................................ 17
3.0 Memory O rganization................................................................................................................................................................. 25
4.0 Flash Pro g ram Memory................. ................... ....................... ................... ................................................................................ 55
5.0 Resets ....................................................................................................................................................................................... 61
6.0 Inter rupt Cont r o lle r ............ ................... ............................. ................... ................... ................................................................... 67
7.0 Direct Mem o ry  Access (DM A)..... ............... ................... ................... ................... ................... .................................................. 113
8.0 Oscillator Configuration............................................................................................................................................................ 127
9.0 Power-Savin g Features............. .............................. ............................. ............................. ....................................................... 135
10.0 I/O Ports........................................ ........................ ....................... ....................... ..................................................................... 137
11.0 Timer1...................................................................................................................................................................................... 139
12.0 Tim er2/3, Timer4/5 , Timer6/7 and Timer8/9 ............................................................................................................................ 141
13.0 Input Capture........................... .. .. ....... .... .. .. .... .. ....... .... .. .. .... .. ....... .. .... .. .... .. .. ....... .... .. ............................................................... 147
14.0 Output Compa re................ ................... ................... ............................. ................... ................................................................. 149
15.0 Serial Peripheral Interf ace (SP I)............................................................................................................................................... 153
16.0 Inter-I ntegrated Circuit (I2C)..................................................................................................................................................... 161
17.0 U nivers al Asynchr onous Receiver  Transmi tter (UART)........................................................................................................... 171
18.0 Enhanced CAN Module............... .. ....... .. .. .. .. .. .... ..... .. .. .. .... .. .. .. ..... .. .... .. .. .. .. .. ....... .. .. .. .. .. .... ... .................................................... 179
19.0 10-bit/12-bi t A/D Converter.......... .............................. ....................... ................... ..................................................................... 209
20.0 Special Features ...................................................................................................................................................................... 223
21.0 Instruction Set Summary.......................................................................................................................................................... 231
22.0 Development Support............................................................................................................................................................... 239
23.0 Electrical Characteristics.......................................................................................................................................................... 243
24.0 Packagin g  In fo rmation................... .............................. ................... ................... ....................................................................... 277
Appendix A: Revision History............................................................................................................................................................. 281
Index .................................................................................................................................................................................................  283
The Micro chip Web Site.................. ....................... ....................... ....................... .............................................................................. 287
Customer Change Notification Service .................... ............. ...... ...... ............... ...... ............... .... ......................................................... 287
Customer Support.......... ............. ...... .... ............. ...... ............. ...... .... ............. ...... ............. ................................................................... 287
Reader Response.............................................................................................................................................................................. 288
Product Identification System............................................................................................................................................................. 289
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PIC24H

1.0 DEVICE OVERVIEW

This do cu me n t conta i ns dev ic e spec if i c in f orm at i on fo r

the following devices:

• PIC24HJ64GP206

• PIC24HJ64GP210

• PIC24HJ64GP506

• PIC24HJ64GP510

• PIC24HJ128GP206

• PIC24HJ128GP210

• PIC24HJ128GP506

• PIC24HJ128GP510

• PIC24HJ128GP306

• PIC24HJ128GP310

• PIC24HJ256GP206

• PIC24HJ256GP210

• PIC24HJ256GP610

The PIC24H device family includes devices with differ-

ent pin counts (64 and 100 pins), different program

memory sizes (6 4 Kbytes, 128 Kbytes and 256 Kbyte s)

and different RAM sizes (8 Kbytes and 16 Kbytes).

This m ake s these fam il ies s uitable for a wide v arie t y of

high-performance digital signal control applications.

The devi ces are pin compat ible with the dsPIC33F fam-

ily of devices, and also share a very high degree of

compatibility with the dsPIC30F family devices. This

allows easy migration between device families as may

be nec essitat ed by t he speci fic fu nctio nality, computa -

tional resource and system cost requirements of the

application.

The PIC24H device family employs a powerful 16-bit

architecture, ideal for applications that rely on

high-sp eed, repeti tive compu tations , as well as contro l.

The 17 x 17 multiplier, hardware support for division

oper at i on s, mu l ti - bit da ta shi f ter, a larg e a rr ay of 16- bi t

workin g registers and a wide va riety of dat a addr essing

modes, together provide the PIC24H Central

Processing Unit (CPU) with extensive mathematical

processing capability. Flexible and deterministic

interrupt handling, coupled with a powerful array of

peripherals, renders the PIC24H devices suitable for

control applications. Further, Direct Memory Access

(DMA) e nables ove rhead-f ree tran sfer of d ata betwee n

several peripherals and a dedicated DMA RAM.

Reliable, field programmable Flash program memory

ensures scalability of applications that use PIC24H

devices.

Figure 1-1 shows a general block diagram of the

various core and peripheral modules in the PIC24H

family of devices, while Table 1-1 lists the functions of

the various pins shown in the pinout diagrams.

Note: This data sheet summarizes the features

of this group of PIC24H devices. It is not

intende d to be a comprehe nsive referenc e

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

PIC24H

FIGURE 1-1: PIC24H GENERAL BLOCK DIAGRAM

OSC1/CLKI

OSC2/CLKO

VDD, VSS

Timing

Generation

MCLR

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Precision

Reference

Band Gap

FRC/LPRC

Oscillators

Regulator

Voltage

VDDCORE/VCAP

UART1,2

ECAN1,2

IC1-8 OC/ SPI1,2 I2C1,2

PORTA

Note: Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins

and features present on each device.

PWM1-8 CN1-23

Instruction

Decode &

Control

PCH PCL

Program Counter

16-bit ALU

Instruction Reg

PCU

16 x 16

W Register Array

ROM Latch

EA MUX

Interrupt

Controller

PSV & Table

Data Access

Control Block

Stack

Control

Logic

Loop

Control

Logic

Address Latch

Program Memory

Data Latch

Address Bus

Literal Data

16 16

Data Latch

Address

Latch

X RAM

Data Bus

17 x 17 Mult iplier

Divide Support

DMA

RAM

DMA

Controller

Control Signals

to Various Blocks

ADC1,2

Timers

PORTB

PORTC

PORTD

PORTE

PORTF

PORTG

Address Generator Units

1-9

PIC24H

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name Pin

Type Buffer

Type Description

AN0- A N31 I Anal og Analog in put ch annels.

AVDD P P Positive supply for analog modules.

AVSS P P G r ound refer ence for anal og modules.

CLKI

CLKO I

OST/CMOS

—External cl ock source inpu t. Al w ay s associat ed wi t h O SC 1 pin function.

Oscillator cryst al o ut put. Connects to crysta l or resonat or in Crysta l Os c illa to r mode.

Option al ly fu nctions as CL KO in R C and EC modes. Always associated with OS C 2

pin function.

CN0-CN23 I ST Input change notification inputs.

Can be s of twa re programm ed for internal w eak pull-ups on all in puts .

C1RX

C1TX

C2RX

C2TX

—

ECAN1 bus rece ive pi n.

ECAN1 bus transm i t pin .

ECAN2 bus rece ive pi n.

ECAN2 bus transm i t pin .

PGD1/EMUD1

PGC1/EMUC1

PGD2/EMUD2

PGC2/EMUC2

PGD3/EMUD3

PGC3/EMUC3

I/O

Data I/O pin for programming/debugging communication channel 1.

Clock input pin for pr ogr am ming/d ebugging communication channel 1.

Data I/O pin for programming/debugging communication channel 2.

Clock input pin for pr ogr am ming/d ebugging communication channel 2.

Data I/O pin for programming/debugging communication channel 3.

Clock input pin for pr ogr am ming/d ebugging communication channel 3.

IC1- IC8 I ST Capt ure inputs 1 through 8.

INT0

INT1

INT2

INT3

INT4

Ex tern a l interr u pt 0.

Ex tern a l interr u pt 1.

Ex tern a l interr u pt 2.

Ex tern a l interr u pt 3.

Ex tern a l interr u pt 4.

MCLR I/P ST Master Clear (Reset ) input. This pi n is an active-lo w R ese t to t he device.

OCFA

OCFB

OC1-OC8

—

Comp are Fault A input ( f or Compare Channel s 1, 2, 3 an d 4).

Comp are Fault B input ( f or Compare Channel s 5, 6, 7 an d 8).

Compare outputs 1 throu gh 8.

OSC1

OSC2 I

I/O ST/CMOS

—Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise.

Oscillator cryst al o ut put. Connects to crysta l or resonat or in Crysta l Os c illa to r mode.

Option al ly fu nctions as CLKO i n R C and EC modes.

RA0-RA7

RA9-RA10

RA12-RA15

I/O

PORTA is a bidirec tio nal I/O port.

RB0-R B15 I/O ST PORTB is a bidirectional I/ O port.

RC1-RC4

RC12-RC15 I/O

I/O ST

ST PORTC is a bidirectional I/O port.

RD0-RD15 I/O ST PORTD is a bidirectiona l I/O port.

RE0-R E7 I/O ST PORTE is a bidirectional I/ O port.

RF0-RF8

RF12-RF13 I/O ST P ORT F is a b i d ire c tion al I /O p o rt.

RG0-RG3

RG6-RG9

RG12-RG15

I/O

PORTG is a bidirectional I/O port.

Legend: CMOS = CMOS compatible input or output; Analog = Analog input

ST = Schmitt Trigger input with CMOS levels; O = Output; I = Input; P = Power

PIC24H

SCK1

SDI1

SDO1

SS1

SCK2

SDI2

SDO2

SS2

I/O

—

Synchronous serial clock input/output for SPI1.

SPI1 data in.

SPI1 data out.

SPI1 slave synchronization or frame pulse I/O.

Synchronous serial clock input/output for SPI2.

SPI2 data in.

SPI2 data out.

SPI2 slave synchronization or frame pulse I/O.

SCL1

SDA1

SCL2

SDA2

I/O

Synchronous serial clock input/output for I2C1.

Synchronous serial data input/output for I2C1.

Synchronous serial clock input/output for I2C2.

Synchronous serial data input/output for I2C2.

SOSCI

SOSCO I

OST/CMOS

—32.768 kH z l ow - power osc illat or crystal inpu t; C M O S ot herwise.

32.768 kH z l ow - power osc ill at or cr ystal output.

TMS

TCK

TDI

TDO

—

JTAG Test mode select pin.

JTAG test clock input pin.

JTAG test data input pin.

JTAG te st data ou tp ut pin.

T1CK

T2CK

T3CK

T4CK

T5CK

T6CK

T7CK

T8CK

T9CK

Timer1 external clock input.

Timer2 external clock input.

Timer3 external clock input.

Timer4 external clock input.

Timer5 external clock input.

Timer6 external clock input.

Timer7 external clock input.

Timer8 external clock input.

Timer9 external clock input.

U1CTS

U1RTS

U1RX

U1TX

U2CTS

U2RTS

U2RX

U2TX

—

UART1 clear to sen d .

UART1 ready to send.

UART1 receive.

UART1 tran sm i t .

UART2 clear to sen d .

UART2 ready to send.

UART2 receive.

UART2 tran sm i t .

VDD P — Positive supply for peripheral logic and I/O pins.

VDDCORE P — CPU logic filter capacitor connection.

VSS P — Ground reference for logic and I/O pins.

VREF+ I Analog Analog voltage reference (high) input.

VREF- I Analog Analog voltage reference (low) input.

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin

Type Buffer

Type Description

Legend: CMOS = CMOS compatible input or output; Analog = Analog input

ST = Schmitt Trigger input with CMOS levels; O = Output; I = Input; P = Power

PIC24H

2.0 CPU

The PIC24H CPU module has a 16-bit (data) modified

Harvard architecture with an enhanced instruction set

and ad dressing m odes. The CPU has a 24-bit ins truction

word with a variable length opcode field. The Program

Counter (PC) is 23 bits wide and addresses up to 4M x

24 bits of user program memory space. The actual

amount of program memory implemented varies by

device. A sing le - cycle ins tru ct io n pre fetc h me cha nis m is

used to help maintain throughput and provides

pred ict abl e ex ecut ion. A ll inst ructi ons exec ute i n a s ingl e

cycle, with the exception of instructions that change the

prog ram fl ow, the do uble word move ( MOV.D) i nstruct ion

and the table instructions. Overhead-free, single-cycle

program loop constructs are supported using the

REPEAT instruc tion, w h ic h is i nt erru ptible at any po int.

The PIC24H devices have sixteen, 16-bit working

registers in the programmer’s model. Each of the working

regist e rs can serve as a d ata, ad dres s or ad dr es s offs et

softwa re St ac k Poi nt er (SP) for interrupts a nd c al ls.

The PIC24H instruction set includes many addressing

modes and is designed for optimum C compiler

effi ciency. For most instru ctions, the PI C24H is cap able

of executing a data (or program data) memory read, a

working register (data) read, a data memory write and

a program (instruction) memory read per instruction

cycle. As a result, three parameter instructions can be

supported, allowing A + B = C operations to be

executed in a single cycle.

A block diagram of the CPU is shown in Figure 2-1,

and the programmer’s model for the PIC24H is shown

in Figure 2-2.

2.1 Data Addressing Overview

The data space can be linearly addressed as 32K words

or 64 Kbytes using an Address Generation Unit (AGU).

The upper 32 Kbytes of the data space memory map can

optionally be mapped into program space at any 16K

program word boundary defined by the 8-bit Program

Space Visibility Page (PSVPAG) register. The program

to data space mapping feature lets any instruction

acce ss p rog ram space as i f i t w e re da t a sp a ce .

The data space also includes 2 Kbytes of DMA RAM,

which is primarily used for DMA dat a transfers , but may

be used as general purpose RAM.

2.2 Special MCU Features

The PIC24H features a 17-bit by 17-bit, single-cycle

multiplier. The multiplier can perform signed, unsigned

and mixed-sign multiplication. Using a 17-bit by 17-bit

multiplier for 16-bit by 16-bit multiplication makes

mixed-sign multiplication possible.

The PIC24H supports 16/16 and 32/16 integer divide

operations. All divide instructions are iterative

operations. They must be executed within a REPEAT

loop, resu lting in a tot al exe cution tim e of 19 instructio n

cycl es. The di vide op erati on can be inter rupte d duri ng

any of those 19 cycles without loss of data.

A multi-bit data shifter is used to perform up to a 16-bit,

left or right shift in a single cycle.

Note: This data sheet summarizes the features

of this group of PIC24H devices. It is not

intende d to be a comprehe nsive referenc e

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

PIC24H

FIGURE 2-1: PIC24H CPU CORE BLOCK DIAGRAM

Instruction

Decode &

Control

PCH PCL

Program Counter

16-bit ALU

Instruction Reg

PCU

16 x 16

W Register Array

ROM Latch

EA MUX

Interrupt

Controller

Stack

Control

Logic

Loop

Control

Logic

Control Signals

to V a rious Blocks

Addre ss B us

Literal Data

16 16

To Pe ripheral Modu l es

Data Latch

Address

Latch

X RAM

Address Gen era tor Units

X Data Bus

DMA

Controller

DMA

RAM

17 x 17

Divide Support

PSV & Table

Data Access

Control Block

Program Memory

Data Latch

Address Latch

Multiplier

PIC24H

FIGURE 2-2: PIC24H PROGRAMMER’S MODEL

PC22 PC0

7 0

D0D15

Program Counter

Data Table Page Address

STATUS Register

Working Registers

W10

W11

W12

W13

W14/Frame Pointer

W15/Stack Pointe r

7 0Program Space Visibility Page Address

— — ——

RCOUNT

15 0REPEAT Loop Counter

IPL2 IPL1

SPLIM Stack Pointer Limit Register

SRL

PUSH.S Shadow

DO Shadow

— —

15 0Core Configuration Register

Legend

CORCON

— DC RA N

TBLPAG

PSVPAG

IPL0 OV

W0/WREG

SRH

PIC24H

2.3 CPU Control Registers

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — —DC

bit 15 bit 8

R/W-0(1) R/W-0(2) R/W-0(2) R-0 R/W-0 R/W-0 R/W-0 R/W-0

IPL<2:0>(2) RA N OV Z C

bit 7 bit 0

Legend:

C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’

S = Set only bit W = Writable bit -n = Value at POR

‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-9 Unimplemented: Read as ‘0’

bit 8 DC: MCU ALU Half Carry/Borrow bit

1 = A carry-o ut from the 4th low- order bit (for byte sized da ta) or 8th low-order bit (for w ord sized dat a)

of the result occurred

0 = No carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized

data) of the result occurred

bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2)

111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled

110 = CPU Interrupt Priority Level is 6 (14)

101 = CPU Interrupt Priority Level is 5 (13)

100 = CPU Interrupt Priority Level is 4 (12)

011 = CPU In terrupt Priority Level is 3 (11)

010 = CPU Interrupt Priority Level is 2 (10)

001 = CPU Interrupt Priority Level is 1 (9)

000 = CPU Interrupt Priority Level is 0 (8)

bit 4 RA: REPEAT Loop Active bit

1 = REPEAT loop in progress

0 = REPEAT loop not in progress

bit 3 N: MCU ALU Negative bit

1 = Result was neg ative

0 = Result was non-negative (zero or positive)

bit 2 OV: MCU ALU Overflow bit

This bit is use d for signed arithm etic (2’s com plement). It indic ates an overflow of th e magnit ude which

causes the sign bit to change state.

1 = Overflow occurred for signed arithmetic (i n this ari thmetic operation)

0 = No overflow occurred

bit 1 Z: MCU ALU Zero bit

1 = An operation which affects the Z bit has set it at some time in the past

0 = The most recent operation which affects the Z bit has cleared it (i.e., a non-zero result)

Note 1: The IPL<2: 0> b it s are con ca ten ated with the IPL<3 > bi t (CORCON<3 >) to form the CPU Inte rrup t Prio rity

Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when

IPL<3> = 1.

2: The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>).

PIC24H

bit 0 C: MCU ALU Carry/Borrow bit

1 = A carry-out from the Most Significant bit (MSb) of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note 1: The IPL<2: 0> b it s are con ca ten ated with the IPL<3 > bi t (CORCON<3 >) to form the CPU Inte rrup t Prio rity

Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when

IPL<3> = 1.

2: The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>).

PIC24H

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0

— — — —IPL3

(1) PSV — —

bit 7 bit 0

Legend: C = Clea r only bit

R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set

0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’

bit 15-4 Unimplemented: Read as ‘0’

bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(1)

1 = CPU interrupt priority level is greater than 7

0 = CPU interrupt priority level is 7 or less

bit 2 PSV: Pr ogram Space Visibility in Data Space Enable bit

1 = Pr ogram space v isible in data spac e

0 = Program space not visible in data space

bit 1-0 Unimplemented: Read as ‘0’

Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to fo rm the CPU interrupt priority level.

PIC24H

2.4 Arithmetic Logi c Unit (ALU)

The PIC2 4H ALU is 16 bit s wide and i s capable of addi-

tion, subtracti on, b it s hi ft s and logic ope rati ons . Unl es s

otherwise mentioned, arithmetic operations are 2’s

complement in nature. Depending on th e operation, the

ALU may affect the values of the Carry (C), Zero (Z),

Negative (N), Overflow (OV) and Digit Carry (DC) Sta-

tus bits in the SR register. The C and DC Status bits

operate as Borrow and Digit Borrow bits, respectively,

for subtraction operations.

The ALU can perform 8-bit or 16-bit operations,

depending on the mode of the instruction that is used.

Data for the ALU operation can come from the W reg-

ister array, or data mem ory, dependin g on the addres s-

ing mode of the instruction. Likewise, output data from

the ALU can be writte n to the W re gister array or a data

memory location.

Refer to the “dsPIC30F/33F Programmer ’s Reference

Manual” (DS70157) for information on the SR bits

affected by each instruction.

The PIC24H CPU incorporates hardware support for

both multiplication and division. This includes a dedi-

cated hardware multiplier and support hardware for

16-bit divisor division.

2.4.1 MULTIPLIER

Using the high-speed 17-bit x 17-bit multiplier, the ALU

supports unsigned, signed or mixed-sign operation in

several multiplication modes:

1. 16-bit x 16-bit signed

2. 16-bit x 16-bit unsigned

3. 16-bit signed x 5-bit (literal) unsigned

4. 16-bit unsigned x 16-bit unsigned

5. 16-bit unsigned x 5-bit (literal) unsigned

6. 16-bit unsigned x 16-bit signed

7. 8-bit unsigned x 8-bit unsigned

2.4.2 DIVIDER

The divide block supports 32-bit/16-bit and 16-bit/16-bit

signed and un signed i nteg er d iv ide op erations with the

following data sizes:

1. 32-bit signed/16-bit signed divide

2. 32-bit unsigned/16-bit unsigned divide

3. 16-bit signed/16-bit signed divide

4. 16-bit unsigned/16-bit unsigned divide

The quotient for all divide instructions ends up in W0

and the remainder in W1. Sixteen-bit signed and

unsigned DIV instructions can specify any W register

for both the 16-bit divisor (Wn) and any W register

(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.

The divide algorithm takes one cycle per bit of divisor,

so both 32-bit/16-bit and 16-bit/16-bit instructions take

the same number of cycles to execute.

2.4.3 MULTI-BIT DATA SHIFTER

The multi-bit data shifter is capable of performing up to

16-bit arithmetic or logic right shifts, or up to 16-bit left

shifts in a single cycle. The source can be either a

working register or a memory location.

The sh ifter requi res a s ign ed bi nary v al ue to de term in e

both the m agnitude (number of bits) and direction of the

shift operation. A positive value shifts the o perand right.

A negative value shifts the operand left. A value of ‘0’

does not modify the operand.

PIC24H

NOTES:

PIC24H

3.0 MEMORY ORGANIZATION

The PIC24H architecture features separate program

and data memory spaces and buses. This architecture

also allows the direct access of program memory from

the data space during code execution.

3.1 Program Address Space

The program address memory space of the PIC24H

devices is 4M instructions. The space is addressable by a

24-bit value derived from either the 23-bit Program Counter

(PC) during program execution, or from table operation

or data space remapping as described in Section 3.4

“Interfacing Program and Data Memory Spaces”.

User access to the program memory sp ace is restricted

to the lower half of the address range (0x000000 to

0x7FFFFF ). The exceptio n is the use of TBLRD/TBLWT

operatio ns, w hich u se TBLPAG<7> to perm it acces s to

the Configuration bits and Device ID sections of the

configuration mem ory space.

Memory maps for the PIC24H family of devices are

shown in Figure 3-1.

FIGURE 3-1: PROGRAM MEMORY MAP FOR PIC24H FAMILY DEVICES

Note: This data sheet summarizes the features

of this group of PIC24H devices. It is not

intende d to be a comprehe nsive referenc e

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

Reset Address 0x000000

0x0000FE

0x000002

0x000100

Device Configuration

User Program

Flash Memory

0x00AC00

0x00ABFE

(22K instructions)

0x800000

0xF80000

Registers 0xF80017

0xF80010

DEVID (2) 0xFEFFFE

0xFF0000

0xFFFFFE

0xF7FFFE

Unimplemented

(Read ‘0’s)

GOTO Instructio n

0x000004

Reserved

0x7FFFFE

Reserved

0x000200

0x0001FE

0x000104

Alternate Vect or Table

Reserved

Interrupt Vector Table Reset Address

Device Configuration

Registers

DEVID (2)

Unimplemented

(Read ‘0’s)

GOTO

Instruct ion

Reserved

Alternate Vect or Table

Reserved

Interrupt Vector Table Reset Address

Device Configuration

User Program

Flash Memory

(88K instructions)

Registers

DEVID (2)

GOTO Instr u ctio n

Reserved

Alternate Vec tor Tab le

Reserved

Interrupt Vect or Table

PIC24HJ64XXXXX PIC24HJ128XXXXX PIC24HJ256XXXXX

Configuration Memory Space User Memo ry Space

0x015800

0x0157FE

User Program

(44K instructions)

Flash Memory

(Read ‘0’s)

Unimplemented

0x02AC00

0x02ABFE

PIC24H

3.1.1 PROGRAM MEMORY

ORGANIZATION

The program memory space is organized in word-

addressable blocks. Although it is treated as 24 bits

wide, it is more appropriate to think of each address of

the program memory as a lower and upper word, with

the uppe r byte of the upper word being unimplemented.

The lower word always has an even address, while the

upper word has an odd address (Figure 3-2).

Program memory addresses are always word-aligned

on the lower word, and addresses are incremented or

decremented by two during code execution. This

arrangement also provides compatibility with data

memory space addressing and makes it possible to

access data in the prog ram me mory space.

3.1.2 INTERRUPT AND TRAP VECTORS

All PIC24H devices reserve the addresses between

0x00000 and 0x000200 for hard-coded program exe-

cutio n vec t ors . A ha r dw are Reset ve cto r i s pro vi ded to

redirect code execution from the default value of the

PC on devi ce Reset to the actual st art of code . A GOTO

instruction is programmed by the user at 0x000000,

with the actual address for the start of code at

0x000002.

PIC24H devices also have two interrupt vector tables,

located from 0x000004 to 0x0000FF and 0x000100 to

0x0001F F. The se vec t or t abl es a llow ea ch of the m any

device interrupt sources to be handled by separate

Interrupt Se rvi ce Ro uti nes (ISR s) . A mo re de t ai led dis-

cussion of the interrupt vector tables is provided in

Section 6.1 “Interrupt Vector Table”.

FIGURE 3-2: PROGRAM MEMORY ORGANIZATION

0816

PC Address

0x000000

0x000002

0x000004

0x000006

00000000

Program Memory

‘Phantom’ By te

(read as ‘0’)

least significant word

most significant word

Ins truct ion Width

0x000001

0x000003

0x000005

0x000007

msw

Address (lsw Address)

PIC24H

3.2 Data Address Space

The PIC24H CPU has a separate 16-bit wide data

memory spac e. The dat a sp ace is access ed using sep-

arate Address Generation Units (AGUs) for read and

write operations. Data memory maps of devices with

different RAM sizes are shown in Figure 3-3 and

Figure 3-4.

All Effective Addresses (EAs) in the data memo ry space

are 16 bit s wide and point to bytes within the dat a space.

This arrangement gives a data space address range of

64 Kbytes or 32K words. The lower half of the data

memory space (that is, when EA<15> = 0) is used for

implemented memory addresses, while the upper half

(EA<15> = 1) is reserved for the Program Space

Visibility area (see Section 3.4.3 “Reading Data From

Program Memory Using Program Space Visibility”).

PIC24H devices implement up to 16 Kbytes of data

memory. Should an EA point to a location outside of

this area, an all-zero word or byte will be returned.

3.2.1 DATA SPACE WIDTH

The data memory space is organized in byte address-

able, 16-bit wide blocks. Data is aligned in data

memory and registers as 16-bit words, but all data

space EAs resolve to bytes. The Least Significant

Bytes of each word have even addresses, while the

Most Significant Bytes have odd addresses.

3.2.2 DATA MEM ORY ORGANIZATION

AND ALIGNMENT

To maintain backward compatibility with PICmicro®

MCU devices and improve data space memory usage

efficiency, the PIC24H instruction set supports both

word and byte operations. As a consequence of byte

accessibility, all ef fective addres s calculations are inter-

nally scaled to step through word-aligned memory. For

example, the core recognizes that Post-Modified

a value of Ws + 1 for byte operations and Ws + 2 for

word operations.

Data byte reads will read the complete word that

contains the byte, using the Least Significant bit (LSb)

of any EA to determine which byte to select. The

selected byte is placed onto the Least Significant Byte

(LSB) of the data path. That is, data memory and reg-

isters are organized as two parallel byte-wide entities

with shared (word) address decode but separate write

lines. Data byte writes only write to the corresponding

side of the array or register which matches the byte

address.

All word accesses must be al igned to an even a ddress.

Misaligned word data fetches are not supported, so

care must be taken when mixing byte and word opera-

tions, or translating from 8-bit MCU code. If a mis-

aligned read or write is attempted, an address error

trap is generated. If the error occurred on a read, the

instruction underway is completed; if it occurred on a

write, the instruc tion will be exec uted but the write does

not occ ur . In either case, a trap is then execute d, allow -

ing the system and/or user to examine the machine

state prior to execution of the address Fault.

All byte loads into any W register are loaded into the

Least Significant Byte. The Most Significant Byte

(MSB) is not modified.

A sign-extend instruction (SE) is provided to allow

users to translate 8-bit signed data to 16-bit signed

values. Alternatively, for 16-bit unsigned data, users

can clea r the Most Significa nt Byte of any W register b y

executing a zero-extend (ZE) instruction on the

appropr iate addr ess.

3.2.3 SFR SPAC E

The first 2 Kbytes of the Near Data Sp ace, from 0x0000

to 0x07FF, is primarily occupied by Special Function

Registers (SFRs). The se a re use d by th e PIC24H core

and peripheral modules for controlling the operation of

the device.

SFRs are distributed among the modules that they

control, and are genera lly grouped toge ther by mod ule.

Much of the SFR space contains unused addresses;

these are read as ‘0’. A complete listing of implemented

SFRs, including their addresses, is shown in Table 3-1

through Table 3-31.

3.2.4 N EAR DATA SPACE

The 8-Kbyte area between 0x0000 and 0x1FFF is

referred to as the Near Data Space. Locations in this

space are directly addressable via a 13-bit absolute

address field within all memory direct instructions.

Addition ally , th e whole dat a spa ce is addressa ble using

MOV instructions, which support Memory Direct

Addressing mode with a 16-bit address field, or by

using Indirect Addressing mode using a working

Note: The actual set of peripheral features and

interrupts varies by the device. Please

refer to the corresponding device tables

and pinout diagrams for device-specific

information.

PIC24H

FIGURE 3-3: DATA MEMORY MAP FOR PIC24H DEVICES WITH 8 KBYTES RAM

0x0000

0x07FE

0xFFFE

LSB

Address

16 bits

LSBMSB

MSB

Address

0x0001

0x07FF

0xFFFF

Optionally

Mapped

into Program

Memory

0x27FF 0x27FE

0x0801 0x0800

2-Kbyte

SFR Space

8-Kbyte

SRAM Space

0x8001 0x8000

0x28000x2801

0x1FFE

0x2000

0x1FFF

0x2001

Space

Data

Near

8-Kbyte

SFR Space

X Data

Unimplemented (X)

DMA RAM

X Data RAM (X)

PIC24H

FIGURE 3-4: DATA MEMORY MAP FOR PIC24H DEVICES WITH 16 KBYTES RAM

3.2.5 DMA RAM

Every PIC24H device contains 2 Kbytes of dual ported

DMA RAM located at the end of data space. Memory

locations in the DMA RAM space are accessible

simultaneously by the CPU and the DMA controller

module. DMA RAM is utilized by the DMA controller to

store data to be transferred to various peripherals using

DMA, as well as data transferred from various

peripherals using DMA. The DMA RAM can be

accessed by the DMA controller without having to steal

cycles from the CPU.

When the CPU and the DMA controller attempt to

concurrently write to the same DMA RAM location, the

hardwa re ensu res tha t the CP U is giv en prec edenc e in

acces sing the DMA RAM lo cation . Therefo re, the DM A

RAM provides a reliable means of transferring DMA

data without ever having to stall the CPU.

0x0000

0x07FE

0xFFFE

LSB

Address

16 bits LSBMSB

MSB

Address

0x0001

0x07FF

0xFFFF

Optionally

Mapped

into Program

Memory

0x47FF 0x47FE

0x0801 0x0800 Near

Data

2-Kbyte

SFR Space

16-Kbyte

SRAM Space

8-Kbyte

Space

0x8001 0x8000

0x48000x4801

0x3FFE

0x4000

0x3FFF

0x4001

0x1FFE

0x1FFF

SFR Space

X Data

Unimplemented (X)

DMA RAM

X Data RAM (X)

Note: DMA RAM can be used for general

purpose data storage if the DMA function

is not required in an application.

PIC24H

TABLE 3-1: CPU CORE REGISTERS MAP

SFR Name SFR

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

WREG0 0000 Working Register 0

0000

WREG1 0002 Working Register 1

0000

WREG2 0004 Working Register 2

0000

WREG3 0006 Working Register 3

0000

WREG4 0008 Working Register 4

0000

WREG5 000A Working Register 5

0000

WREG6 000C W orking Register 6

0000

WREG7 000E Working Register 7

0000

WREG8 0010 Working Register 8

0000

WREG9 0012 Working Register 9

0000

WREG10 0014 Wor king Re gist er 10

0000

WREG11 0016 Wor king R egi ster 11

0000

WREG12 0018 Wor king Re gist er 12

0000

WREG13 001A Wor king Re gist er 13

0000

WREG14 001C Wor king Re gist er 14

0000

WREG15 001E Wor king Re gist er 15

0800

SPLIM 0020 S tack Pointer Limit Register

xxxx

PCL 002E Progra m Co un ter Lo w Word Regi ster

0000

PCH 0030 — — — — — — — — Program Counter High Byte Register

0000

TBLPAG 0032 — — — — — — — — Table Page Address Pointer Register

0000

PSVPAG 0034 — — — — — — — — Progr am M em o ry V isi bility P age A ddre s s P oint er R eg ister

0000

RCOUNT 0036 Repe at Lo op Co un ter R eg ister

xxxx

SR 0042 — — — — — — —DC IPL<2:0> RANOVZ C

0000

CORCON 0044 — — — — — — — — — — — — IPL3 PSV — —

0000

DISICNT 0052 —

— Disable Interrupts Counter

xxxx

BSRAM 0750 — — — — — — — — — — — —

IW_BSR

IR_BSR

RL_BSR

0000

SSRAM 0752 — — — — — — — — — — — —

IW_SSR

IR_SSR

RL_SSR

0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 3-2: CHANGE NOTIFICATION REGISTER MAP

SFR

Name SFR

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000

CNEN2 0062

— — — — — — — —

CN23IE CN22IE CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE 0000

CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000

CNPU2 006A

— — — — — — — —

CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24H

TABLE 3-3: INTERRUPT CONTROLLER REGISTER MAP

SFR

Name SFR

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL —0000

INTCON2 0082 ALTIVT DISI — — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000

IFS0 0084 — DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000

IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF IC8IF IC7IF AD2IF INT1IF CNIF — MI2C1IF SI2C1IF 0000

IFS2 0088 T6IF DMA4IF — OC8IF OC7IF OC6IF OC5IF IC6IF IC5IF IC4IF IC3IF DMA3IF C1IF C1RXIF SPI2IF SPI2EIF 0000

IFS3 008A ——DMA5IF — — — — C2IF C2RXIF INT4IF INT3IF T9IF T8IF MI2C2IF SI2C2IF T7IF 0000

IFS4 008C — — — — — — — — C2TXIF C1TXIF DMA7IF DMA6IF —U2EIFU1EIF—0000

IEC0 0094 — DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000

IEC1 0096 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE IC8IE IC7IE AD2IE INT1IE CNIE — MI2C1IE SI2C1IE 0000

IEC2 0098 T6IE DMA4IE — OC8IE OC7IE OC6IE OC5IE IC6IE IC5IE IC4IE IC3IE DMA3IE C1IE C1RXIE SPI2IE SPI2EIE 0000

IEC3 009A ——DMA5IE — — — — C2IE C2RXIE INT4IE INT3IE T9IE T8IE MI2C2IE SI2C2IE T7IE 0000

IEC4 009C — — — — — — — — C2TXIE C1TXIE DMA7IE DMA6IE —U2EIEU1EIE—0000

IPC0 00A4 — T1IP<2:0> —OC1IP<2:0>—IC1IP<2:0>— INT0IP<2:0> 4444

IPC1 00A6 — T2IP<2:0> —OC2IP<2:0>—IC2IP<2:0>— DMA0IP<2:0> 4444

IPC2 00A8 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444

IPC3 00AA — — — — — DMA1IP<2:0> — AD1IP<2:0> — U1TXIP<2:0> 0444

IPC4 00AC — CNIP<2:0> — — — — — MI2C1IP<2:0> — SI2C1IP<2:0> 0044

IPC5 00AE — IC8IP<2:0> —IC7IP<2:0>— AD2IP<2:0> — INT1IP<2:0> 4444

IPC6 00B0 — T4IP<2:0> —OC4IP<2:0>—OC3IP<2:0>— DMA2IP<2:0> 4444

IPC7 00B2 — U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0> 4444

IPC8 00B4 — C1IP<2:0> — C1RXIP<2:0> — SPI2IP<2:0> — SPI2EIP<2:0> 4444

IPC9 00B6 — IC5IP<2:0> —IC4IP<2:0>—IC3IP<2:0>— DMA3IP<2:0> 4444

IPC10 00B8 — OC7IP<2:0> —OC6IP<2:0>—OC5IP<2:0>—IC6IP<2:0>4444

IPC11 00BA — T6IP<2:0> — DMA4IP<2:0> — — — — — OC8IP<2:0> 4404

IPC12 00BC — T8IP<2:0> — MI2C2IP<2:0> — SI2C2IP<2:0> — T7IP<2:0> 4444

IPC13 00BE — C2RXIP<2:0> — INT4IP<2:0> — INT3IP<2:0> — T9IP<2:0> 4444

IPC14 00C0 — — — — — — — — — — — — — C2IP<2:0> 0004

IPC15 00C2 — — — — — — — — — DMA5IP<2:0> — — — — 0040

IPC16 00C4 — — — — — U2EIP<2:0> — U1EIP<2:0> — — — — 4440

IPC17 00C6 — C2TXIP<2:0> — C1TXIP<2:0> — DMA7IP<2:0> — DMA6IP<2:0> 4444

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24H

TA BLE 3-4: TIMER REGISTER MAP

SFR

Name SFR

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

TMR1 0100 T ime r1 Re gist er

xxxx

PR1 0102 Period Register 1

FFFF

T1CON 0104 TON

—

TSIDL

— — — — — —

TGATE TCKPS<1:0>

—

TSYNC TCS

—

0000

TMR2 0106 T ime r2 Re gist er

xxxx

TMR3HLD 0108 T ime r3 H o lding R egi ster (fo r 32- bit tim er oper ation s on ly)

xxxx

TMR3 010A T ime r3 Re gist er

xxxx

PR2 010C Period Register 2

FFFF

PR3 010E Period Register 3

FFFF

T2CON 0110 TON

—

TSIDL

— — — — — —

TGATE TCKPS<1:0> T32

—

TCS

—

0000

T3CON 0112 TON

—

TSIDL

— — — — — —

TGATE TCKPS<1:0>

— —

TCS

—

0000

TMR4 0114 T ime r4 Re gist er

xxxx

TMR 5HL D 01 16 T imer5 Holding R egister (for 32 -bit opera tions only)

xxxx

TMR5 0118 T ime r5 Re gist er

xxxx

PR4 011A Period Register 4

FFFF

PR5 011C Period Register 5

FFFF

T4CON 011E TON

—

TSIDL

— — — — — —

TGATE TCKPS<1:0> T32

—

TCS

—

0000

T5CON 0120 TON

—

TSIDL

— — — — — —

TGATE TCKPS<1:0>

— —

TCS

—

0000

TMR6 0122 T ime r6 Re gist er

xxxx

TMR 7HL D 0124 T imer7 Holding R egister (for 32 -bit opera tions only)

xxxx

TMR7 0126 T ime r7 Re gist er

xxxx

PR6 0128 Period Register 6

FFFF

PR7 012A Period Register 7

FFFF

T6CON 012C TON —TSIDL— — — — — — TGATE TCKPS<1:0> T32 —TCS

—

0000

T7CON 012E TON —TSIDL— — — — — — TGATE TCKPS<1:0> ——TCS

—

0000

TMR8 0130 T ime r8 Re gist er

xxxx

TMR 9HL D 0132 T imer9 Holding R egister (for 32 -bit opera tions only)

xxxx

TMR9 0134 T ime r9 Re gist er

xxxx

PR8 0136 Period Register 8

FFFF

PR9 0138 Period Register 9

FFFF

T8CON 013A TON

—

TSIDL

— — — — — —

TGATE TCKPS<1:0> T32

—

TCS

—

0000

T9CON 013C TON

—

TSIDL

— — — — — —

TGATE TCKPS<1:0>

— —

TCS

—

0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24H

TABLE 3-5: INPUT CAPTURE REGISTER MAP

SFR Name SFR

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

IC1BUF 0140 Input 1 Ca pture R egi ster

xxxx

IC1CON 0142

— —

ICSIDL

— — — — —

ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

0000

IC2BUF 0144 Input 2 Ca pture R egi ster

xxxx

IC2CON 0146

— —

ICSIDL

— — — — —

ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

0000

IC3BUF 0148 Input 3 Ca pture R egi ster

xxxx

IC3CON 014A

— —

ICSIDL

— — — — —

ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

0000

IC4BUF 014C Input 4 Ca pture R egi ster

xxxx

IC4CON 014E

— —

ICSIDL

— — — — —

ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

0000

IC5BUF 0150 Input 5 Ca pture R egi ster

xxxx

IC5CON 0152

— —

ICSIDL

— — — — —

ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

0000

IC6BUF 0154 Input 6 Ca pture R egi ster

xxxx

IC6CON 0156

— —

ICSIDL

— — — — —

ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

0000

IC7BUF 0158 Input 7 Ca pture R egi ster

xxxx

IC7CON 015A

— —

ICSIDL

— — — — —

ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

0000

IC8BUF 015C Input 8 Ca pture R egi ster

xxxx

IC8CON 015E

— —

ICSIDL

— — — — —

ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24H

TABLE 3-6: OUTPUT COMPARE REGISTER MAP

SFR Name SFR

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

OC1RS 0180 Output Compare 1 Secondary Register

xxxx

OC1R 0182 Out pu t Co m par e 1 Re gister

xxxx

OC1CON 0184

— —

OCSIDL

— — — — — — — —

OCFLT OCTSEL OCM<2:0>

0000

OC2RS 0186 Output Compare 2 Secondary Register

xxxx

OC2R 0188 Out pu t Co m par e 2 Re gister

xxxx

OC2CON 018A

— —

OCSIDL

— — — — — — — —

OCFLT OCTSEL OCM<2:0>

0000

OC3R S 018C Outpu t Comp are 3 Sec onda ry Register

xxxx

OC3R 018E Outpu t Co m p are 3 R egi ster

xxxx

OC3CON 0190

— —

OCSIDL

— — — — — — — —

OCFLT OCTSEL OCM<2:0>

0000

OC4RS 0192 Output Compare 4 Secondary Register

xxxx

OC4R 0194 Out pu t Co m par e 4 Re gister

xxxx

OC4CON 0196

— —

OCSIDL

— — — — — — — —

OCFLT OCTSEL OCM<2:0>

0000

OC5RS 0198 Output Compare 5 Secondary Register

xxxx

OC5R 019A Outpu t Co m p are 5 R egi ster

xxxx

OC5CON 019C

— —

OCSIDL

— — — — — — — —

OCFLT OCTSEL OCM<2:0>

0000

OC6RS 019E Output Compare 6 Secondary Register

xxxx

OC6R 01A0 Outpu t Co m p are 6 Re gist er

xxxx

OC6CON 01A2

— —

OCSIDL

— — — — — — — —

OCFLT OCTSEL OCM<2:0>

0000

OC7RS 01A4 Output Compare 7 Secondary Register

xxxx

OC7R 01A6 Outpu t Co m p are 7 Re gist er

xxxx

OC7CON 01A8

— —

OCSIDL

— — — — — — — —

OCFLT OCTSEL OCM<2:0>

0000

OC8RS 01AA Output Compare 8 Secondary Register

xxxx

OC8R 01AC Outpu t Co m p are 8 R egi ster

xxxx

OC8CON 01AE

— —

OCSIDL

— — — — — — — —

OCFLT OCTSEL OCM<2:0>

0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24H

TABLE 3-7: I2C1 REGISTER MAP

SFR Name SFR

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

I2C1RCV 0200 — — — — — — — — Receive Register

0000

I2C1TRN 0202 — — — — — — — — T ransmit Register

00FF

I2C1BRG 0204 — — — — — — — Baud Rate Generator Register

0000

I2C1ON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN

1000

I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF

0000

I2C1ADD 020A — — — — — — Addre ss R e gister

0000

I2C1MSK 020C — — — — — — Add re ss Mask Re gi ste r

0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 3-8: I2C2 REGISTER MAP

SFR Name SFR

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

I2C2RCV 0210 — — — — — — — — Receive Register

0000

I2C2TRN 0212 — — — — — — — — T ran sm it Re gis ter

00FF

I2C2BRG 0214 — — — — — — — Bau d Rate Ge nerator R egiste r

0000

I2C2CON 0216 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN

1000

I2C2STAT 0218 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF

0000

I2C2ADD 021A — — — — — — Add ress Reg ist er

0000

I2C2MSK 021C — — — — — — Address Mask Register

0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 3-9: UART1 REGISTER MAP

SFR Name SFR

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL

0000

U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA

0110

U1TXREG 0224 — — — — — — — UAR T Transmit R egi ster

xxxx

U1RXREG 0226 — — — — — — — UAR T Receiv e Register

0000

U1BRG 0228 Ba ud R a te G en era to r P re sca le r

0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24H

TABLE 3-10: UART2 REGISTER MAP

SFR

Name SFR

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

U2MODE 0230 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL

0000

U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA

0110

U2TXREG 0234 — — — — — — — UAR T Transmit R egi ster

xxxx

U2RXREG 0236 — — — — — — — UART Rec eive Regis ter

0000

U2BRG 0238 Baud Rate G ene rator Pres caler

0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 3-11: SPI1 REGISTER MAP

SFR

Name SFR

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

SPI1STAT 0240 SPIEN — SPISIDL — — — — — — SPIROV — — — — SPITBF SPIRBF

0000

SPI1CON1 0242 ——— DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> PPRE<1:0>

0000

SPI1CON2 0244 FRMEN SPIFSD FRMPOL — — — — — — — — — — —FRMDLY—

0000

SPI1BUF 0248 SPI1 Transmit and Receive Buffer Register

0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 3-12: SPI2 REGISTER MAP

SFR Name SFR

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

SPI2STAT 0260 SPIEN —SPISIDL— — — — — — SPIROV — — — — SPITBF SPIRBF

0000

SPI2CON1 0262 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> PPRE<1:0>

0000

SPI2CON2 0264 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY —

0000

SPI2BUF 0268 SPI2 Transmit and Receive Buffer Register

0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24H

TABLE 3-13: ADC1 REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

ADC1BUF0 0300 ADC Data Buffer 0 xxxx

AD1CON1 0320 ADON — ADSIDL ADDMAB

M— AD12B FORM<1:0> SSRC<2:0> —SIMSA

MASAM SAMP DONE 0000

AD1CON2 0322 VCFG<2:0> —— CSCNA CHPS<1:0> BUFS — SMPI<3:0> BUFM ALTS 0000

AD1CON3 0324 ADRC —— SAMC<4:0> —— ADCS<5:0> 0000

AD1CHS12

30326 — — — — — CH123NB<1:0> CH123S

B— — — — — CH123NA<1:0> CH123S

A0000

AD1CHS0 0328 CH0NB —— CH0SB<4:0> CH0NA —— CH0SA<4:0> 0000

AD1PCFGH 032A PCFG31 PCFG30 PCFG29 PCFG28 PCFG27 PCFG26 PCFG25 PCFG24 PCFG23 PCFG22 PCFG21 PCFG20 PCFG19 PCFG18 PCFG17 PCFG16 0000

AD1PCFGL 032C PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000

AD1CSSH 032E CSS31 CSS30 CSS29 CSS28 CSS27 CSS26 CSS25 CSS24 CSS23 CSS22 CSS21 CSS20 CSS19 CSS18 CSS17 CSS16 0000

AD1CSSL 0330 CSS15 CSS14 CSS13 CSS12 CSS11 CSS10 CSS9 CSS8 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 0000

AD1CON4 0332 — — — — — — — — — — — — — DMABL<2:0> 0000

Reserved 0334-

033E — — — — — — — — — — — — — — — — 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 3-14: ADC2 REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

ADC2BUF0 0340 ADC Dat a Buffer 0 xxxx

AD2CON1 0360 ADON — ADSIDL ADDMAB

M— AD12B FORM<1:0> SSRC<2:0> —SIMSA

MASAM SAMP DONE 0000

AD2CON2 0362 VCFG<2:0> —— CSCNA CHPS<1:0> BUFS — SMPI<3:0> BUFM ALTS 0000

AD2CON3 0364 ADRC —— SAMC<4:0> —— ADCS<5:0> 0000

AD2CHS12

30366 — — — — — CH123NB<1:0> CH123S

B— — — — — CH123NA<1:0> CH123SA 0000

AD2CHS0 0368 CH0NB — — — CH0SB<3:0> CH0NA — — — CH0SA<3:0> 0000

Reserved 036A — — — — — — — — — — — — — — — — 0000

AD2PCFGL 036C PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000

Reserved 036E — — — — — — — — — — — — — — — — 0000

AD2CSSL 0370 CSS15 CSS14 CSS13 CSS12 CSS11 CSS10 CSS9 CSS8 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 0000

AD2CON4 0372 — — — — — — — — — — — — — DMABL<2:0> 0000

Reserved 0374-

037E — — — — — — — — — — — — — — — — 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24H

TABLE 3-15: DMA REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

DMA0CON 0380 CHEN SIZE DIR HALF NULLW — — — — —AMODE<1:0>——MODE<1:0>0000

DMA0REQ 0382 FORCE — — — — — — — — IRQSEL<6:0> 0000

DMA0STA 0384 STA<15:0> 0000

DMA0STB 0386 STB<15:0> 0000

DMA0PAD 0388 PAD<15:0> 0000

DMA0CNT 038A — — — — — — CNT<9:0> 0000

DMA1CON 038C CHEN SIZE DIR HALF NULLW — — — — —AMODE<1:0>——MODE<1:0>0000

DMA1REQ 038E FORCE — — — — — — — — IRQSEL<6:0> 0000

DMA1STA 0390 STA<15:0> 0000

DMA1STB 0392 STB<15:0> 0000

DMA1PAD 0394 PAD<15:0> 0000

DMA1CNT 0396 — — — — — — CNT<9:0> 0000

DMA2CON 0398 CHEN SIZE DIR HALF NULLW — — — — —AMODE<1:0>——MODE<1:0>0000

DMA2REQ 039A FORCE — — — — — — — — IRQSEL<6:0> 0000

DMA2STA 039C STA<15:0> 0000

DMA2STB 039E STB<15:0> 0000

DMA2PAD 03A0 PAD<15:0> 0000

DMA2CNT 03A2 — — — — — — CNT<9:0> 0000

DMA3CON 03A4 CHEN SIZE DIR HALF NULLW — — — — —AMODE<1:0>——MODE<1:0>0000

DMA3REQ 03A6 FORCE — — — — — — — — IRQSEL<6:0> 0000

DMA3STA 03A8 STA<15:0> 0000

DMA3STB 03AA STB<15:0> 0000

DMA3PAD 03AC PAD<15:0> 0000

DMA3CNT 03AE — — — — — — CNT<9:0> 0000

DMA4CON 03B0 CHEN SIZE DIR HALF NULLW — — — — —AMODE<1:0>——MODE<1:0>0000

DMA4REQ 03B2 FORCE — — — — — — — — IRQSEL<6:0> 0000

DMA4STA 03B4 STA<15:0> 0000

DMA4STB 03B6 STB<15:0> 0000

DMA4PAD 03B8 PAD<15:0> 0000

DMA4CNT 03BA — — — — — — CNT<9:0> 0000

DMA5CON 03BC CHEN SIZE DIR HALF NULLW — — — — —AMODE<1:0>——MODE<1:0>0000

DMA5REQ 03BE FORCE — — — — — — — — IRQSEL<6:0> 0000

DMA5STA 03C0 STA<15:0> 0000

DMA5STB 03C2 STB<15:0> 0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24H

DMA5PAD 03C4 PAD<15:0> 0000

DMA5CNT 03C6 — — — — — — CNT<9:0> 0000

DMA6CON 03C8 CHEN SIZE DIR HALF NULLW — — — — —AMODE<1:0>——MODE<1:0>0000

DMA6REQ 03CA FORCE — — — — — — — — IRQSEL<6:0> 0000

DMA6STA 03CC STA<15:0> 0000

DMA6STB 03CE STB<15:0> 0000

DMA6PAD 03D0 PAD<15:0> 0000

DMA6CNT 03D2 — — — — — — CNT<9:0> 0000

DMA7CON 03D4 CHEN SIZE DIR HALF NULLW — — — — —AMODE<1:0>——MODE<1:0>0000

DMA7REQ 03D6 FORCE — — — — — — — — IRQSEL<6:0> 0000

DMA7STA 03D8 STA<15:0> 0000

DMA7STB 03DA STB<15:0> 0000

DMA7PAD 03DC PAD<15:0> 0000

DMA7CNT 03DE — — — — — — CNT<9:0> 0000

DMACS0 03E0 PWCOL7 PWCOL6 PWCOL5 PWCOL4 PWCOL3 PWCOL2 PWCOL1 PWCOL0 XWCOL7 XWCOL6 XWCOL5 XWCOL4 XWCOL3 XWCOL2 XWCOL1 XWCOL0 0000

DMACS1 03E2 — — — — LSTCH<3:0> PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 0000

DSADR 03E4 DSADR<15:0> 0000

TABLE 3-16: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0 OR 1

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

C1CTRL1 0400 —— CSIDL ABAT CANCKS REQOP<2:0> OPMODE<2:0> — CANCAP ——WIN0480

C1CTRL2 0402 — — — — — — — — — — — DNCNT<4:0> 0000

C1VEC 0404 — — —FILHIT<4:0> — ICODE<6:0> 0000

C1FCTRL 0406 DMABS<2:0> — — — — — — — — FSA<4:0> 0000

C1FIFO 0408 —— FBP<5:0> —— FNRB<5:0> 0000

C1INTF 040A —— TXBO TXBP RXBP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBIF 0000

C1INTE 040C — — — — — — — — IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE 0000

C1EC 040E TERRCNT<7:0> RERRCNT<7:0> 0000

C1CFG1 0410 — — — — — — — — SJW<1:0> BRP<5:0> 0000

C1CFG2 0412 — WAKFIL — — — SEG2PH<2:0> SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> 0000

C1FEN1 0414 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8 FLTEN7 FLTEN6 FLTEN5 FLTEN4 FLTEN3 FLTEN2 FLTEN1 FLTEN0 0000

C1FMSKSEL1 0418 F7MSK<1:0> F6MSK<1:0> F5MSK<1:0> F4MSK<1:0> F3MSK<1:0> F2MSK<1:0> F1MSK<1:0> F0MSK<1:0> 0000

C1FMSKSEL2 041A F15MSK<1:0> F14MSK<1:0> F13MSK<1:0> F12MSK<1:0> F11MSK<1:0> F10MSK<1:0> F9MSK<1:0> F8MSK<1:0> 0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TA BLE 3-15: DMA REGISTER MAP (CONTINUED)

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24H

TABLE 3-17: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

0400-

041E See defini tion when WIN = x

C1RXFUL1 0420 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0 0000

C1RXFUL2 0422 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 0000

C1RXOVF1 0428 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 0000

C1RXOVF2 042A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000

C1TR01CON 0430 TXEN1 TX

ABT1 TX

LARB1 TX

ERR1 TX

REQ1 RTREN1 TX1PRI<1:0> TXEN0 TX

ABAT0 TX

LARB0 TX

ERR0 TX

REQ0 RTREN0 TX0PRI<1:0> 0000

C1TR23CON 0432 TXEN3 TX

ABT3 TX

LARB3 TX

ERR3 TX

REQ3 RTREN3 TX3PRI<1:0> TXEN2 TX

ABAT2 TX

LARB2 TX

ERR2 TX

REQ2 RTREN2 TX2PRI<1:0> 0000

C1TR45CON 0434 TXEN5 TX

ABT5 TX

LARB5 TX

ERR5 TX

REQ5 RTREN5 TX5PRI<1:0> TXEN4 TX

ABAT4 TX

LARB4 TX

ERR4 TX

REQ4 RTREN4 TX4PRI<1:0> 0000

C1TR67CON 0436 TXEN7 TX

ABT7 TX

LARB7 TX

ERR7 TX

REQ7 RTREN7 TX7PRI<1:0> TXEN6 TX

ABAT6 TX

LARB6 TX

ERR6 TX

REQ6 RTREN6 TX6PRI<1:0> xxxx

C1RXD 0440 Recieved Data Word xxxx

C1TXD 0442 Transmit Data Word xxxx

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 3-18: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

0400-

041E See definition whe n WIN = x

C1BUFPNT1 0420 F3BP<3:0> F2BP<3:0> F1BP<3:0> F0BP<3:0> 0000

C1BUFPNT2 0422 F7BP<3:0> F6BP<3:0> F5BP<3:0> F4BP<3:0> 0000

C1BUFPNT3 0424 F11BP<3:0> F10BP<3:0> F9BP<3:0> F8BP<3:0> 0000

C1BUFPNT4 0426 F15BP<3:0> F14BP<3:0> F13BP<3:0> F12BP<3:0> 0000

C1RXM0SID 0430 SID<10:3> SID<2:0> —MIDE—EID<17:16>xxxx

C1RXM0EID 0432 EID<15:8> EID<7:0> xxxx

C1RXM1SID 0434 SID<10:3> SID<2:0> —MIDE—EID<17:16>xxxx

C1RXM1EID 0436 EID<15:8> EID<7:0> xxxx

C1RXM2SID 0438 SID<10:3> SID<2:0> —MIDE—EID<17:16>xxxx

C1RXM2EID 043A EID<15:8> EID<7:0> xxxx

C1RXF0SID 0440 SID<10:3> SID<2:0> —EXIDE—EID<17:16>xxxx

C1RXF0EID 0442 EID<15:8> EID<7:0> xxxx

C1RXF1SID 0444 SID<10:3> SID<2:0> —EXIDE—EID<17:16>xxxx

C1RXF1EID 0446 EID<15:8> EID<7:0> xxxx

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24H

C1RXF2SID 0448 SID<10:3> SID<2:0> —EXIDE—EID<17:16>xxxx

C1RXF2EID 044A EID<15:8> EID<7:0> xxxx

C1RXF3SID 044C SID<10:3> SID<2:0> —EXIDE—EID<17:16>xxxx

C1RXF3EID 044E EID<15:8> EID<7:0> xxxx

C1RXF4SID 0450 SID<10:3> SID<2:0> —EXIDE—EID<17:16>xxxx

C1RXF4EID 0452 EID<15:8> EID<7:0> xxxx

C1RXF5SID 0454 SID<10:3> SID<2:0> —EXIDE—EID<17:16>xxxx

C1RXF5EID 0456 EID<15:8> EID<7:0> xxxx

C1RXF6SID 0458 SID<10:3> SID<2:0> —EXIDE—EID<17:16>xxxx

C1RXF6EID 045A EID<15:8> EID<7:0> xxxx

C1RXF7SID 045C SID<10:3> SID<2:0> —EXIDE—EID<17:16>xxxx

C1RXF7EID 045E EID<15:8> EID<7:0> xxxx

C1RXF8SID 0460 SID<10:3> SID<2:0> —EXIDE—EID<17:16>xxxx

C1RXF8EID 0462 EID<15:8> EID<7:0> xxxx

C1RXF9SID 0464 SID<10:3> SID<2:0> —EXIDE—EID<17:16>xxxx

C1RXF9EID 0466 EID<15:8> EID<7:0> xxxx

C1RXF10SID 0468 SID<10:3> SID<2:0> —EXIDE—EID<17:16>xxxx

C1RXF10EID 046A EID<15:8> EID<7:0> xxxx

C1RXF11SID 046C SID<10:3> SID<2:0> —EXIDE—EID<17:16>xxxx

C1RXF11EID 046E EID<15:8> EID<7:0> xxxx

C1RXF12SID 0470 SID<10:3> SID<2:0> —EXIDE—EID<17:16>xxxx

C1RXF12EID 0472 EID<15:8> EID<7:0> xxxx

C1RXF13SID 0474 SID<10:3> SID<2:0> —EXIDE—EID<17:16>xxxx

C1RXF13EID 0476 EID<15:8> EID<7:0> xxxx

C1RXF14SID 0478 SID<10:3> SID<2:0> —EXIDE—EID<17:16>xxxx

C1RXF14EID 047A EID<15:8> EID<7:0> xxxx

C1RXF15SID 047C SID<10:3> SID<2:0> —EXIDE—EID<17:16>xxxx

C1RXF15EID 047E EID<15:8> EID<7:0> xxxx

TABLE 3-18: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 (CONTINUED)

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24H

TABLE 3-19: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 0 OR 1

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

C2CTRL1 0500 —— CSIDL ABAT CANCKS REQOP<2:0> OPMODE<2:0> — CANCAP ——WIN0480

C2CTRL2 0502 — — — — — — — — — — — DNCNT<4:0> 0000

C2VEC 0504 — — —FILHIT<4:0> — ICODE<6:0> 0000

C2FCTRL 0506 DMABS<2:0> — — — — — — — — FSA<4:0> 0000

C2FIFO 0508 —— FBP<5:0> —— FNRB<5:0> 0000

C2INTF 050A —— TXBO TXBP RXBP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBIF 0000

C2INTE 050C — — — — — — — — IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE 0000

C2EC 050E TERRCNT<7:0> RERRCNT<7:0> 0000

C2CFG1 0510 — — — — — — — — SJW<1:0> BRP<5:0> 0000

C2CFG2 0512 — WAKFIL — — — SEG2PH<2:0> SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> 0000

C2FEN1 0514 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8 FLTEN7 FLTEN6 FLTEN5 FLTEN4 FLTEN3 FLTEN2 FLTEN1 FLTEN0 0000

C2FMSKSEL1 0518 F7MSK<1:0> F6MSK<1:0> F5MSK<1:0> F4MSK<1:0> F3MSK<1:0> F2MSK<1:0> F1MSK<1:0> F0MSK<1:0> 0000

C2FMSKSEL2 051A F15MSK<1:0> F14MSK<1:0> F13MSK<1:0> F12MSK<1:0> F11MSK<1:0> F10MSK<1:0> F9MSK<1:0> F8MSK<1:0> 0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 3-20: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 0

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

0500-

051E See definition when WIN = x

C2RXFUL1 0520 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0 0000

C2RXFUL2 0522 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 0000

C2RXOVF1 0528 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF09 RXOVF08 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 0000

C2RXOVF2 052A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000

C2TR01CON 0530 TXEN1 TX

ABAT1 TX

LARB1 TX

ERR1 TX

REQ1 RTREN1 TX1PRI<1:0> TXEN0 TX

ABAT0 TX

LARB0 TX

ERR0 TX

REQ0 RTREN0 TX0PRI<1:0> 0000

C2TR23CON 0532 TXEN3 TX

ABAT3 TX

LARB3 TX

ERR3 TX

REQ3 RTREN3 TX3PRI<1:0> TXEN2 TX

ABAT2 TX

LARB2 TX

ERR2 TX

REQ2 RTREN2 TX2PRI<1:0> 0000

C2TR45CON 0534 TXEN5 TX

ABAT5 TX

LARB5 TX

ERR5 TX

REQ5 RTREN5 TX5PRI<1:0> TXEN4 TX

ABAT4 TX

LARB4 TX

ERR4 TX

REQ4 RTREN4 TX4PRI<1:0> 0000

C2TR67CON 0536 TXEN7 TX

ABAT7 TX

LARB7 TX

ERR7 TX

REQ7 RTREN7 TX7PRI<1:0> TXEN6 TX

ABAT6 TX

LARB6 TX

ERR6 TX

REQ6 RTREN6 TX6PRI<1:0> xxxx

C2RXD 0540 Recieved Data Word xxxx

C2TXD 0542 Transmit Data Word xxxx

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24H

TABLE 3-21: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

0500-

051E See definition when WIN = x

C2BUFPNT1 0520 F3BP<3:0> F2BP<3:0> F1BP<3:0> F0BP<3:0> 0000

C2BUFPNT2 0522 F7BP<3:0> F6BP<3:0> F5BP<3:0> F4BP<3:0> 0000

C2BUFPNT3 0524 F12BP<3:0> F10BP<3:0> F9BP<3:0> F8BP<3:0> 0000

C2BUFPNT4 0526 F15BP<3:0> F14BP<3:0> F13BP<3:0> F12BP<3:0> 0000

C2RXM0SID 0530 SID<10:3> SID<2:0> —MIDE—EID<17:16>xxxx

C2RXM0EID 0532 EID<15:8> EID<7:0> xxxx

C2RXM1SID 0534 SID<10:3> SID<2:0> —MIDE—EID<17:16>xxxx

C2RXM1EID 0536 EID<15:8> EID<7:0> xxxx

C2RXM2SID 0538 SID<10:3> SID<2:0> —MIDE—EID<17:16>xxxx

C2RXM2EID 053A EID<15:8> EID<7:0> xxxx

C2RXF0SID 0540 SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx

C2RXF0EID 0542 EID<15:8> EID<7:0> xxxx

C2RXF1SID 0544 SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx

C2RXF1EID 0546 EID<15:8> EID<7:0> xxxx

C2RXF2SID 0548 SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx

C2RXF2EID 054A EID<15:8> EID<7:0> xxxx

C2RXF3SID 054C SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx

C2RXF3EID 054E EID<15:8> EID<7:0> xxxx

C2RXF4SID 0550 SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx

C2RXF4EID 0552 EID<15:8> EID<7:0> xxxx

C2RXF5SID 0554 SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx

C2RXF5EID 0556 EID<15:8> EID<7:0> xxxx

C2RXF6SID 0558 SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx

C2RXF6EID 055A EID<15:8> EID<7:0> xxxx

C2RXF7SID 055C SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx

C2RXF7EID 055E EID<15:8> EID<7:0> xxxx

C2RXF8SID 0560 SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx

C2RXF8EID 0562 EID<15:8> EID<7:0> xxxx

C2RXF9SID 0564 SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx

C2RXF9EID 0566 EID<15:8> EID<7:0> xxxx

C2RXF10SID 0568 SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx

C2RXF10EID 056A EID<15:8> EID<7:0> xxxx

C2RXF11SID 056C SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24H

C2RXF11EID 056E EID<15:8> EID<7:0> xxxx

C2RXF12SID 0570 SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx

C2RXF12EID 0572 EID<15:8> EID<7:0> xxxx

C2RXF13SID 0574 SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx

C2RXF13EID 0576 EID<15:8> EID<7:0> xxxx

C2RXF14SID 0578 SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx

C2RXF14EID 057A EID<15:8> EID<7:0> xxxx

C2RXF15SID 057C SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx

C2RXF15EID 057E EID<15:8> EID<7:0> xxxx

TABLE 3-21: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1 (CONTINUED)

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24H

TABLE 3-22: PORTA REGISTER MAP(1)

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

TRISA 02C0

TRISA15 TRISA14 TRISA13 TRISA12 — TRISA10 TRISA9 — TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

D6C0

PORTA 02C2

RA15 RA14 RA13 RA12 — RA10 RA9 — RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0

xxxx

LATA 02C4

LATA15 LATA14 LATA13 LATA12 — LATA10 LATA9 — LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0

xxxx

ODCA

(2)

06C0

ODCA15 ODCA14 ODCA13 ODCA12 — — — — — — ODCA5 ODCA4 ODCA3 ODCA2 ODCA1 ODCA0

xxxx

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.

Note 1: The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.

TABLE 3-23: PORTB REGISTER MAP(1)

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 1 1 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

TRISB 02C6 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

FFFF

PORTB 02C8 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0

xxxx

LATB 02CA LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0

xxxx

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.

Note 1: The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.

TABLE 3-24: PORTC REGISTER MAP(1)

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

TRISC 02CC TRISC15 TRISC14 TRISC13 TRISC12 — — — — — — —

TRISC4 TRISC3 TRISC2 TRISC1 —

F01E

PORTC 02CE RC15 RC14 RC13 RC12 — — — — — — —

RC4 RC3 RC2 RC1 —

xxxx

LATC 02D0 LATC15 LATC14 LATC13 LATC12 — — — — — — —

LATC4 LATC3 LATC2 LATC1 —

xxxx

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.

Note 1: The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.

TABLE 3-25: PORTD REGISTER MAP(1)

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

TRISD 02D2

TRISD15 TRISD14 TRISD13 TRISD12

TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0

FFFF

PORTD 02D4

RD15 RD14 RD13 RD12

RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0

xxxx

LATD 02D6

LATD15 LATD14 LATD13 LATD12

LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0

xxxx

ODCD

(2)

06D2

ODCD15 ODCD14 ODCD13 ODCD12 ODCD11 ODCD10 ODCD9 ODCD8 ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0

xxxx

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.

Note 1: The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.

PIC24H

TABLE 3-26: PORTE REGISTER MAP (1)

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

TRISE 02D8 ————————

TRISE7

TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0

03FF

PORTE 02DA ————————

RE7

RE6 RE5 RE4 RE3 RE2 RE1 RE0

xxxx

LATE 02DC ————————

LATE7

LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0

xxxx

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.

Note 1: The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.

TABLE 3-27: PORTF REGISTER MAP(1)

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets

TRISF 02DE — —

TRISF13 TRISF12

— — —

TRISF8 TRISF7

TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0

31FF

PORTF 02E0 — —

RF13 RF12

— — — RF8 RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0

xxxx

LATF 02E2 — —

LATF13 LATF12

— — — LATF8 LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0

xxxx

ODCF

(2)

06DE — —

ODCF13 ODCF12

— — —

ODCF8 ODCF7 ODCF6 ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0

xxxx

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.

Note 1: The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.

TABLE 3-28: PORTG RE GISTER MAP(1)

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

TRISG 02E4

TRISG15 TRISG14 TRISG13 TRISG12 —— TRISG9 TRISG8 TRISG7 TRISG6 —— TRISG3 TRISG2 TRISG1 TRISG0

F3CF

PORTG 02E6

RG15 RG14 RG13 RG12 —— RG9 RG8 RG7 RG6 ——RG3RG2RG1RG0

xxxx

LATG 02E8

LATG15 LATG14 LATG13 LATG12 —— LATG9 LATG8 LATG7 LATG6 —— LATG3 LATG2 LATG1 LATG0

xxxx

ODCG

(2)

06E4

ODCG15 ODCG14 ODCG13 ODCG12

— —

ODCG9 ODCG8 ODCG7 ODCG6 —— ODCG3 ODCG2 ODCG1 ODCG0

xxxx

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.

Note 1: The actual set of I/O port pins varies from one device to another. Please refer to the corresp ond ing pinout diag ram s .

PIC24H

TABLE 3-29: SYSTEM CONTROL REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

RCON 0740 TRAPR IOPUWR — — — — — VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR

xxxx

(1)

OSCCON 0742 —COSC<2:0>— NOSC<2:0> CLKLOCK —LOCK—CF— LPOSCEN OSWEN 0300

(2)

CLKDIV 0744 ROI DOZE<2:0> DOZEN FRCDIV<2:0> PLLPOST<1:0> — PLLPRE<4::0> 0040

PLLFBD 0746 — — — — — — — PLLDIV<8:0> 0030

OSCTUN 0748 — — — — — — — — — — TUN<5:0> 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: RCON register Reset values dependent on type of Reset.

2: OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset.

TABLE 3-30: NVM REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

NVMCON 0760 WR WREN WRERR — — — — — — ERASE ——NVMOP<3:0>

0000

(1)

NVMKEY 0766

— — — — — — — — NVMKEY<7:0>

0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.

TABLE 3-31: PMD REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All

Resets

PMD1 0770 T5MD T4MD T3MD T2MD T1MD

— — —

I2C1MD U2MD U1MD SPI2MD SPI1MD C2MD C1MD AD1MD 0000

PMD2 0772 IC8MD IC7MD IC6MD IC5MD IC4MD IC3MD IC2MD IC1MD OC8MD OC7MD OC6MD OC5MD OC4MD OC3MD OC2MD OC1MD 0000

PMD3 0774 T9MD T8MD T7MD T6MD — — — — — — — — — —I2C2MDAD2MD0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC24H

3.2.6 SOFTWARE STACK

In addition to its use as a working register, the W15

regi ster in t he PIC2 4H devic es is als o used a s a soft -

ware Stack Poi nter. The S tack Pointer always poi nt s to

the first available free word and grows from lower to

higher ad dresses. It pre-dec rements for stack pops and

post-increments for stack pushes, as shown in

Figure 3-5. For a PC push du ring any CALL instruction,

the MSB of the PC is zero-extended before the push,

ensuring that the MSB is always clear.

The Stack Pointer Limit register (SPLIM) associated

with the S t ack Pointe r set s an upp er address bounda ry

for the stack. SPLIM is uninitialized at Reset. As is the

case for the Stack Pointer, SPLIM<0> is forced to ‘0’

because all stack operations must be word-aligned.

Whenever an EA is generated using W15 as a source

or destination pointer, the resulting address is

compared with the value in SPLIM. If the contents of

the Stack Pointer (W15) and the SPLIM register are

equal and a push operation is performed, a stack error

trap will not occur. The stack error trap will occur on a

subsequent push operation. Thus, for example, if it is

desirable to cause a stack error trap when the stack

grows beyond address 0x2000 in RAM, initialize the

SPLIM with the value 0x1FF E.

Similarly, a S t ac k Pointer un derflow (stack error) trap i s

generated when the Stack Pointer address is found to

be less than 0x0800. This prevents the stack from

interfering with the Special Function Register (SFR)

space.

A write to the SPLIM re gister should not be imme diately

followed by an indirect read operation using W15.

FIGURE 3-5: CALL STACK FRAME

3.2.7 DATA RAM PROTECTION FEATURE

The PIC24 H product fam ily support s Data RA M protec-

tion features that enable segments of RAM to be

protected when used in conjunction with Boot and

Secur e Code Se gment S ecurity. BSRAM (Secure RAM

segment for BS) is accessible only from the Boot Seg-

ment Flash code, when enabled. SSRAM (Secure

RAM segment for RAM) is accessible only from the

Secure Segment Flash code, when enabled. See

Table 3-1 for an overview of the BSRAM and SSRAM

SFRs.

3.3 Instruction Addressing Modes

The ad dre ssi ng mod es in Tabl e 3-3 2 for m th e bas is of

the addre ssing mode s optimized to s upport the sp ecific

features of individual instructions. The addressing

modes provided in the MAC class of instructions are

somewhat different from those in the other instruction

types.

3.3.1 FILE REGISTER INSTRUCTIONS

Most fil e re gis ter i ns truc tio ns us e a 1 3-bi t address f iel d

(f) to directly address data present in the first 8192

bytes of data memory (Near Data Space). Most file

whic h is den oted as WREG in these instruc tions. The

destination is typically either the same file register or

WREG (with the exception of the MUL instruction),

which w rites the re sult t o a re gister or regi ster p air. The

MOV instruction allows additional flexibility and can

access the entire data space.

3.3.2 MCU INSTRUCTIONS

The 3-operand MCU instructions are of the form:

Operand 3 = Operand 1 <function> Operand 2

where O pe rand 1 is alw a ys a work in g reg ister (i.e., th e

address ing mo de c an only be R eg is ter Direct) w hic h i s

referred to as Wb. Operand 2 can be a W register,

fetched from data memory, or a 5-bit literal. The result

location can be either a W register or a data memory

location. The following addressing modes are

supported by MCU instructions:

• Register Direct

• Register Indirect

• Register Indirect Post-Modified

• Register Indirect Pre-Modified

• 5-bit or 10-bit Literal

Note: A PC push during exception processing

concat enates the SRL regis ter to the M SB

of the PC prior to the push.

PC<15:0>

000000000

015

W15 (before CALL)

W15 (after CALL)

Stack Grows Toward s

Higher Addres s

0x0000

PC<22:16>

POP : [--W15]

PUSH : [W15++] Note: Not all instructions support all the

addressing modes given above. Individual

instructions may support different subsets

of these addressing modes.

PIC24H

TABLE 3-32: FUNDAMENTAL ADDRESSING MODES SUPPORTED

3.3.3 MOVE INSTRUCTIONS

Move in struction s provide a greater degre e of add ress-

ing flexibility than other instructions. In addition to the

Addressing modes supported by most MCU instruc-

tion s, mov e ins truct ions a lso s upport Regi ster I ndire ct

with Regis ter Of fs et Addr ess in g mod e, als o refer red to

as Register Indexed mode.

In summary, the following Addressing modes are

supported by move instructions:

• Register Di rect

• Register Indi rec t

• Register Indi rec t Post-m od ifi ed

• Regis ter Indi rect Pre-mo dif ied

• Register Indirect with Register Offset (Indexed)

• Register Indirect with Literal Offset

• 8-bit Literal

• 16-bit Literal

3.3.4 OTHER INSTRUCTIONS

Besides the various addressin g modes outlin ed above,

some instructions use literal constants of various sizes.

For example, BRA (branch) instructions use 16-bit

signed literal s to specify th e branch destinat ion direct ly ,

whereas the DISI instruction uses a 14-bit unsigned

literal fiel d. In some instru ctions, the so urce of an oper-

and or result is implied by the opcode itself. Certain

operations, such as NOP, do not have any operands.

3.4 Interfacing Program and Data

Memory Spaces

The PIC24H architecture uses a 24-bit wide program

spac e and a 16-bit w ide data sp ace. The arc hitecture is

also a modified Harvard scheme, meaning that data

can also be present in the program space. To use this

data successfully, it must be accessed in a way that

preserves the alignment of information in both spaces.

Asid e fro m nor mal exec uti on, th e PI C24H ar chi tec tur e

provi de s two m eth od s by w hic h pr ogra m s p ac e c an b e

accessed during operation:

• Using tab le ins tructi ons to acce ss in divid ual by tes

or words anywh ere in the prog ram sp ac e

• Remapping a portion of the program space into

the data space (Program Space Visibility)

Table instructions allow an application to read or write

to small areas of the program memory. This capability

makes the method ideal for accessing data tables that

need to be updated from time to time. It also allows

access to all bytes of the program word. The remap-

ping method allows an application to access a large

block of data on a read-only basis, which is ideal for

look ups from a large table of static data. It can only

access the least significant word of the program word.

3.4.1 ADDRESSING PROGRAM SPACE

Since the address ranges for the data and program

spaces are 16 and 24 bits, respectively, a method is

needed to create a 23-bit or 24-bit program address

from 16-bit da ta regist ers. The soluti on depends on the

interface method to be used.

For table operations, the 8-bit Table Page register

(TBLPAG) is used to define a 32K word region within

the program space. This is concatenated with a 16-bit

EA to arrive at a full 24-bit program space address. In

this format, the Most Significant bit of TBLPAG is used

to determ ine if the ope ration occurs in the user mem ory

(TBLPAG<7> = 0) or the configuration memory

(TBLPAG<7> = 1).

Addressing Mode Description

File Register Direct The address of the file register is specified explicitly.

decremented) by a constant value.

to form the EA.

Note: For the MOV instructions, the Addressing

mode specified in the instruction can differ

for the source and destination EA.

However, the 4-bit Wb (Register Offset)

field is shared between both source and

destination (but typically only used by

one).

Note: Not all instructions support all the

Addressi ng modes given abo ve. Individual

instructions may support different subsets

of these Addressin g modes.

PIC24H

For remapping operations, the 8-bit Program Space

Visibility register (PSVPAG) is used to define a

16K word page in the program space. When the Most

Signific ant bit of the EA is ‘1’, PSVP AG is concatenated

with the lower 15 bits of the EA to form a 23-bit program

space address. Unlike table operations, this limits

remappi ng ope rations stric tly t o the u ser mem ory are a.

Table 3-33 and Figure 3-6 show how the program EA is

created for table operations and remapping accesses

from the data EA. Here, P<23:0> refers to a program

space word, whereas D<15:0> refers to a data space

word.

TABLE 3-33: PROGRAM SPACE ADDRESS CONSTRUCTION

Access Type Access

Space Program Space Address

<23> <22:16> <15> <14:1> <0>

Instruction Access

(Code Execution) User 0PC<22:1> 0

0xx xxxx xxxx xxxx xxxx xxx0

TBLRD/TBLWT

(Byte/Word Read/Write) User TBLPAG<7:0> Data EA<15:0>

0xxx xxxx xxxx xxxx xxxx xxxx

Configuration TBLPAG<7:0> Data EA<15:0>

1xxx xxxx xxxx xxxx xxxx xxxx

Program Space Visibility

(Block Remap/Read) User 0PSVPAG<7:0> Data EA<14:0>(1)

0 xxxx xxxx xxx xxxx xxxx xxxx

Note 1: Data EA<15> is always ‘1’ in this case , but is not used in calc ulati ng the pro gram s pac e addre ss. Bit 15 of

the address is PSVPAG<0>.

PIC24H

FIGURE 3-6: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

0Program Counter

23 bits

PSVPAG

8 bits

15 bit s

Program Counter(1)

Select

TBLPAG

8 bits

16 bits

Byte Select

1/0

User/Configuration

Table Operat ion s(2)

Program Space Visibility(1)

Space Select

24 bi ts

23 bits

(Remapping)

1/0

Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word

alignment of data in the program and data spaces.

2: Table op erations are not req uire d t o be wo rd-al ign ed . Table re ad ope rati on s a re permitt ed

in the configuration mem ory sp ac e.

PIC24H

3.4.2 DATA ACCESS FROM PROGRAM

MEMORY USING TABLE

INSTRUCTIONS

The TBLRDL and TBLWTL instructions offer a direct

method of reading or writing the lower word of any

address within the program space without going

through da ta space. The TBLRDH and TBLWTH instruc-

tions are the only method to read or write the upper

8 bits of a program space word as data.

The PC is incremented by two for each successive

24-bit program word. This allows program memory

addresses to directly map to data space addresses.

Program memory can thus be regarded as two 16-bit,

word wide address s p ac es , res id ing si de by si de, eac h

with the same address range. TBLRDL and TBLWTL

access the space which contains the least significant

data word and TBLRDH and TBLWTH access the space

which contains the upper data byte.

Two table instructions are provided to move byte or

word sized (16-bit) data to and from program space.

Both function as either byte or word operations.

1. TBLRDL (Table Read Low): In Word mode, it

maps the lower word of the program space

location (P<15:0>) to a data address (D<15:0 >).

In Byte mode, either the upper or lower byte of

the lower program word is mapped to the lower

byte of a data address. The upper byte is

selected when Byte Select is ‘1’; the lowe r byt e

is selected when it is ‘0’.

2. TBLRDH (Table Read High): In Word mode, it

maps the entire upper word of a program address

(P<23:16>) to a data address. Note that

D<15:8>, the ‘phantom byte’, will always be ‘0’.

In Byte mo de, it m ap s the up per or lo wer byte of

the program word to D<7:0> of the data

address, as above. Note that the data will

always be ‘0’ when the upper ‘phantom’ byte is

selected (Byte S elect = 1).

In a similar fashion, two table instructions, TBLWTH

and TBLWTL, are used to write individual bytes or

words to a program space address. The details of

their operation are explained in Section 4.0 “Flash

Program Memory”.

For all table operations, the area of program memory

spac e to be ac cess ed is de termin ed by the Table Page

memory space of t he device, in cluding use r and config-

uratio n sp a ce s. W hen TBL PAG<7> = 0, the table page

is located in the user memory space. When

TBLPAG<7> = 1, the page is located in configuration

space.

FIGURE 3-7: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS

081623

00000000

‘Phantom’ Byte

TBLRDH.B (Wn<0> = 0)

TBLRDL.W

TBLRDL.B (Wn<0> = 1)

TBLRDL.B (Wn<0> = 0)

23 15 0

TBLPAG

0x000000

0x800000

0x020000

0x030000

Program Space

The address for the table operation is determi ned by the data EA

within the page defined by the TBLPAG register.

Only read operations are s hown; write operations are also va lid in

the user memory area.

PIC24H

3.4.3 READING DATA FROM PROGRAM

MEMORY USING PROGRAM SPACE

VISIBILITY

The upper 32 Kbytes of data space may optionally be

mapped into any 16K word p age of the progra m sp ace.

This optio n pr ovides transparent acc es s of sto red co n-

stan t data from the dat a space without the need to us e

special instructions (i.e., TBLRDL/H).

Program space access through the data space occurs

if the Mo st Significan t bit of the dat a space EA is ‘ 1’ and

prog ram spac e visib ility is enabl ed by se ttin g the PSV

bit in the Core Control register (CORCON<2>). The

location of the program memory space to be mapped

into the data space is determined by the Program

Space Visibility Page register (PSVPAG). This 8-bit

16K words in program space. In effect, PSVPAG func-

tions as the upper 8 bits of the program memory

address, with the 15 bits of the EA functioning as the

lower bits. Note that by incrementing the PC by 2 for

each program memory word, the lower 15 bits of data

spa ce addresse s directly map to the lowe r 15 bits in the

corresponding program space addresses.

Data reads to this area add an additional cycle to the

instruc tion being ex ecuted, si nce two program memory

fetches are requi red.

Although each data space address, 8000h and higher,

maps directly into a corresponding program memory

address (see Figure 3-8), only the lower 16 bits of the

24-bit program word are used to contain the data. The

upper 8 bits of any program space location used as

data should be programmed with ‘1111 1111’ or

‘0000 0000’ to force a NOP. This prevents possible

issues should the area of code ever be accidentally

executed.

For operations that use PSV and are executed outside

a REPEAT loop, the MOV and MOV.D instructions

require one instructio n cycle in add ition to the sp ecified

execution time. All other instructions require two

instruction cycles in addition to the specified execution

time.

For operations that use PSV, which are executed inside

a REPEAT loop, there will be some instances that

require two instruction cycles in addition to the

specified execution time of the instruction:

• Execution in the fi rst iteration

• Execution in the last iteration

• Execution prior to exiting the loop due to an

interrupt

• Execution upon re-entering the loop after an

interr upt is servi ced

Any other iteration of the REPEAT loop will allow the

instruction accessing data, using PSV, to execute in a

single cycle.

FIGURE 3-8: PROGRAM SPACE VISIBILITY OPERATION

Note: PSV acc ess is tempo raril y disabl ed durin g

table reads/wr ites.

23 15 0

PSVPAG Data Space

Program Space

0x0000

0x8000

0xFFFF

02 0x000000

0x800000

0x010000

0x018000

When CORCON<2> = 1 and EA<15> = 1:

The data in the page

designated by

PSVPAG is mapped

into the upper half of

the data memory

space...

Data EA<14:0>

...while the lower 15 bits

of the EA specify an

exact address within

the PSV area. This

corresponds exactly to

the same lower 15 bits

of the actual program

space address.

PSV Area

PIC24H

NOTES:

PIC24H

4.0 FLASH PR OGRAM MEMORY

The PIC24H devices contain internal Flash program

memory for storing and executing application code.

The memory is readable, writable and erasable during

normal operation over the entire VDD range.

Flash memory can be programmed in two ways:

1. In-Circuit Serial Programming™ (ICSP™)

programming capability

2. Run- Time Self-Programming (RTSP)

ICSP progr amming capabili ty all ows a P IC24H d evice

to be serially programmed while in the end application

circuit. This is simply done with two lines for program-

ming c lock a nd prog ramming dat a (one o f the alterna te

programming pin pairs: PGC1/PGD1, PGC2/PGD2 or

PGC3/PGD3, and three other lines for power (VDD),

ground (VSS) and Master Clear (MCLR). This allows

customers to manufacture boards with unprogrammed

devices and then program the digital signal controller

just before shipping the product. This also allows the

most recent firmware or a custom firmware to be

programmed.

RTSP is accomplished using TBLRD (table read) and

TBLWT (table write) instructions. With RTSP, the user

can write program memory data either in blocks or

‘rows’ of 64 ins truc t io ns (192 byt es ) at a tim e, or si ngl e

instructions and erase program memory in blocks or

‘pages’ of 512 instructions (1536 bytes) at a time.

4.1 Table Instructions and Flash

Programming

Regardless of the method used, all programming of

Flash memory is done with the table read and table

write instructions. These allow direct read and write

access to the program memory space from the data

memory while the device is in normal operating mode.

The 24-bit target address in the program memory is

formed us ing bit s<7:0> of the TBLPAG register and the

Effective Address (EA) from a W register specified in

the table instruction, as shown in Figure 4-1.

The TBLRDL and the TBLWTL instructions are used to

read or write to bits<15:0> of program memory.

TBLRDL and TBLWTL can access program memory in

both Word and Byte modes.

The TBLRDH and TBLWTH instruc tions are us ed to read

or write to bits<23:16> of program memory. TBLRDH

and TBLWTH can also access program memo ry in Word

or Byte mode.

FIGURE 4-1: ADDRESSING FOR TABLE REGISTERS

Note: This data sheet summarizes the features

of this group of PIC24H devices. It is not

intende d to be a comprehe nsive referenc e

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

Program Counter

24 bi ts

Prog ram C ounte r

TBLPAG Reg

8 bits

Worki ng Re g EA

16 bits

Byte

24-bit EA

1/0

Select

Using

Table Instruction

Using

User/Configuration

Sp ace Sel ec t

PIC24H

4.2 RTSP Operation

The PIC24H Flash program memory array is organized

into rows of 64 instructions or 192 bytes. RTSP allows

the user to erase a page of memory, which consists of

eight r ows (5 12 in st ru ct i on s) at a t im e, an d to prog r am

one row or one word at a time. TABLE 23-11: “DC

Characteristics: Program Memory” displays typical

erase an d programm ing times . The 8-row eras e pages

and single row write rows are edge-aligned, from the

beginning of program memory, on boundaries of 1536

bytes and 192 bytes, respectively.

The program memory implements holding buffers that

can contain 64 instructions of programming data. Prior

to the actual programming operation, the write data

must b e loade d into th e buf fers in sequenti al order. Th e

instruction words loaded must always be from a group

of 64 boundary.

The basi c sequence for R TSP programming is to set up

a Table Pointer, then do a series of TBLWT instructions

to lo ad th e buffe rs. P rogram min g is p erfor med by set-

ting the control bits in the NVMCON register. A total of

64 TBLWTL and TBLWTH inst ructio ns a re re quired to

load the instructions.

All of the table write operations are single-word writes

(two instruction cycles) because only the buffers are

written. A programming cycle is required for

programming each row.

4.3 Control Registers

There are two SFRs used to read and write the

program Flash memory: NVMCON and NVMKEY.

The NVMCON register (Register 4-1) controls which

blocks are to be erased, which memory type is to be

programmed and the start of the programming cycle.

NVMKEY is a write-only register that is used for write

protection. To start a programming or erase sequence,

the user must consecutively write 55h and AAh to the

NVMKEY register . Refer to Section 4.4 “Programming

Operations” for further details.

4.4 Programming Operations

A complete programming sequence is necessary for

programming or erasing the internal Flash in RTSP

mode. A programming operation is nominally 4 ms in

duration and the processor stalls (waits) until the oper-

ation is finished. Setting the WR bit (NVMCON<15>)

starts the operation, and the WR bit is automatically

cleared when the operation is finished.

PIC24H

R/SO-0(1) R/W-0(1) R/W-0(1) U-0 U-0 U-0 U-0 U-0

WR WREN WRERR — — — — —

bit 15 bit 8

U-0 R/W-0(1) U-0 U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1)

— ERASE ——NVMOP<3:0>

(2)

bit 7 bit 0

Legend: SO = Sat iab le onl y bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 WR: Write Control bit

1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is

cleared by hardware once operation is complete.

0 = Program or erase operation is complete and inactive

bit 14 WREN: Write Enable bit

1 = Enable Fla sh prog ram /era se operati on s

0 = Inhibit Flash program/erase operations

bit 13 WRERR: Write Sequence Error Flag bit

1 = An improper program or erase sequence attempt or termination has occurred (bit is set

automatically on any set attempt of the WR bit)

0 = The program or erase operation completed normally

bit 12-7 Unimplemented: Read as ‘0’

bit 6 ERASE: Erase/Program Enable bit

1 = Perform the erase operation specified by NVMOP<3:0> on the next WR command

0 = Perform the program operation specified by NVMOP<3:0> on the next WR command

bit 5-4 Unimplemented: Read as ‘0’

bit 3-0 NVMOP<3:0>: NVM Operation Select bits(2)

1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)

1110 = Reserved

1101 = Erase General Segment and FGS Configuration Register

(ERASE = 1) or no operation (ERASE = 0)

1100 = Erase Secure Segment and FSS Configuration Register

(ERASE = 1) or no operation (ERASE = 0)

1011-0100 = Reserved

0011 = Memory word program operation (ERASE = 0) or no operation (ERASE = 1)

0010 = Memory page erase operation (ERASE = 1) or no operation (ERASE = 0)

0001 = Memory row program operation (ERASE = 0) or no operation (ERASE = 1)

0000 = Program or erase a single Configuration register byte

Note 1: These bits can only be reset on POR.

2: All other combinations of NVMOP<3:0> are unimplemented.

PIC24H

4.4.1 PROGRAMMING ALGORITHM FOR

FLASH PROGRAM MEMORY

The user can program one row of program Flash

memory at a time. To do this, it is necessary to erase

the 8-row erase page that contains the desired row.

The general process is:

1. Read eight rows of program memory

(512 instructions) and store in data RAM.

2. Update the program data in RAM with the

desired new data.

3. Erase the page (see Exa m ple 4-1) :

a) Set the NVMOP bits (NVMCON<3:0>) to

‘0010’ to configure for block erase. Set the

ERASE (NVMCON<6>) and WREN

(NVMCON<14>) bits.

b) Wr ite th e s t arti ng add res s o f th e page to be

erased into the TBLPAG and W registers.

c) Perform a dummy table write operation

(TBLWTL) to any address within the page

that needs to be erased.

d) Write 0x 55 to NVMK EY.

e) Write 0xAA to NVMKEY.

f) Set the WR bit (NVMCON<1 5>). The e rase

cycle begins an d the CPU s t al l s f or t he du r a-

tion of the erase cycle. When the erase is

done, the WR bit is cleared aut omatica lly.

4. Write the first 64 instruction s from dat a RAM in to

the prog ram memory buf fers (see Example 4-2).

5. Write the program block to Flash memory:

a) Set the NVMOP bits to ‘0001’ to configure

for row programming. Clear the ERASE bit

and set the WREN bit.

b) Write 0x55 to NVMKEY.

c) Write 0xAA to NVMKEY.

d) Set the WR bit. The programming cycle

begi ns and the CP U stalls for the duration of

the write cycle. When the write to Flash mem-

ory is done, the WR bit is cleared

automatically.

6. Repeat steps 4 and 5, using the next available

64 instructions from the block in data RAM by

incrementing the value in TBLPAG, until all

512 instructions are written back to Flash mem-

ory.

For protection against accidental operations, the write

initiate sequence for NVMKEY must be used to allow

any erase or program operation to proceed. After the

programming command has been executed, the user

must w ait f or t he pro g ram mi ng ti me unt il pro g r am ming

is complete. The two instructions following the start of

the pr og ram mi ng se que nce s hould be NOPs, as shown

in Example 4-3.

EXAMPLE 4-1: ERASING A PROGRAM MEMORY PAGE

; Set up NVMCON for block erase operation

MOV #0x4042, W0 ;

MOV W0, NVMCON ; Initialize NVMCON

; Init pointer to row to be ERASED

MOV #tblpage(PROG_ADDR), W0 ;

MOV W0, TBLPAG ; Initialize PM Page Boundary SFR

MOV #tbloffset(PROG_ADDR), W0 ; Initialize in-page EA<15:0> pointer

TBLWTL W0, [W0] ; Set base address of erase block

DISI #5 ; Block all interrupts with priority <7

; for next 5 instructions

MOV #0x55, W0

MOV W0, NVMKEY ; Write the 55 key

MOV #0xAA, W1 ;

MOV W1, NVMKEY ; Write the AA key

BSET NVMCON, #WR ; Start the erase sequence

NOP ; Insert two NOPs after the erase

NOP ; command is asserted

Note: A program memory page erase operation

is set up by performing a dummy table

write (TBLWTL) operation to any address

within the page. This methodology is dif-

ferent from the page erase operation on

dsPIC30F devices in which the erase

page was selected using a dedicated pair

of registers (NVMADRU and NVMADR).

PIC24H

EXAMPLE 4-2: LOADING THE WRITE BUFFERS

EXAMPLE 4-3: INITIATIN G A PROGRAMMING SEQUENCE

; Set up NVMCON for row programming operations

MOV #0x4001, W0 ;

MOV W0, NVMCON ; Initialize NVMCON

; Set up a pointer to the first program memory location to be written

; program memory selected, and writes enabled

MOV #0x0000, W0 ;

MOV W0, TBLPAG ; Initialize PM Page Boundary SFR

MOV #0x6000, W0 ; An example program memory address

; Perform the TBLWT instructions to write the latches

; 0th_program_word

MOV #LOW_WORD_0, W2 ;

MOV #HIGH_BYTE_0, W3 ;

TBLWTL W2, [W0] ; Write PM low word into program latch

TBLWTH W3, [W0++] ; Write PM high byte into program latch

; 1st_program_word

MOV #LOW_WORD_1, W2 ;

MOV #HIGH_BYTE_1, W3 ;

TBLWTL W2, [W0] ; Write PM low word into program latch

TBLWTH W3, [W0++] ; Write PM high byte into program latch

; 2nd_program_word

MOV #LOW_WORD_2, W2 ;

MOV #HIGH_BYTE_2, W3 ;

TBLWTL W2, [W0] ; Write PM low word into program latch

TBLWTH W3, [W0++] ; Write PM high byte into program latch

•

; 63rd_program_word

MOV #LOW_WORD_31, W2 ;

MOV #HIGH_BYTE_31, W3 ;

TBLWTL W2, [W0] ; Write PM low word into program latch

TBLWTH W3, [W0++] ; Write PM high byte into program latch

DISI #5 ; Block all interrupts with priority <7

; for next 5 instructions

MOV #0x55, W0

MOV W0, NVMKEY ; Write the 55 key

MOV #0xAA, W1 ;

MOV W1, NVMKEY ; Write the AA key

BSET NVMCON, #WR ; Start the erase sequence

NOP ; Insert two NOPs after the

NOP ; erase command is asserted

PIC24H

NOTES:

PIC24H

5.0 RESETS

The Reset module combines all Reset sources and

controls the devi ce Master Reset Signal, SYSRST. The

following is a list of device Reset sources:

• POR: Power-on Reset

• BOR: Brown-out Reset

•MCLR

: Master Clear Pin Reset

•SWR: RESET Instruction

• WDT: Watchdog Ti mer Reset

• TRAPR: Trap Conflict Reset

• IOPUWR: Illegal Opcode and Uninitialized W

A simplified block diagram of the Reset module is

shown in Figure 5-1.

Any active sou rce of Res et will m ake the SYSRST si g-

nal act ive. Many reg isters asso ciated with th e CPU and

peripherals are forced to a known Reset state. Most

registers are unaffected by a Reset; their status is

unknow n on POR and unc hanged by all oth er Resets.

All types of device Reset will set a corresponding st atus

bit in the RCON register to indicate the type of Reset

(see Register 5-1). A POR will clear all bits, except for

the POR bit (RCON <0>), th at are set. The u ser can set

or clear any bit at any time during code execution. The

RCON bit s only ser ve as status bit s. Setting a particular

Reset status bit in software does not cause a device

Reset to occur.

The RCON register also has other bits associated with

the Watchdog Timer and device power-saving states.

The functi on of these bits is discusse d in other section s

of this manual.

FIGURE 5-1: RESET SYSTEM BLOCK DIAGRAM

Note: This data sheet summarizes the features

of this group of PIC24H devices. It is not

intende d to be a comprehe nsive referenc e

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

Note: Refer to the specific peripheral or CPU

section of this manual for register Reset

states.

Note: The status bits in the RCON register

should be cleared after they are read so

that the next RCON register value after a

device Reset will be meaningful.

MCLR

VDD

VDD Rise

Detect POR

Sleep or Idle

RESET Instruction

WDT

Module

Glitch Filter

Trap Conflict

Illegal Opcode

Uninitialized W Register

SYSRST

Internal

Regulator BOR

PIC24H

R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0

TRAPR IOPUWR — — — — —VREGS

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1

EXTR SWR SWDTEN(2) WDTO SLEEP IDLE BOR POR

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 TRAPR: Trap Reset Flag bit

1 = A Trap Conflict Reset has occurred

0 = A Trap Conflict Reset has not occurred

bit 14 IOPUWR: Illega l Opcode or Uninitia lized W Ac cess Reset Flag bit

1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an

Address Pointer caused a Reset

0 = An illegal opcode or uninitialized W Reset has not occurred

bit 13-9 Unimplemented: Read as ‘0’

bit 8 VREGS: Vo ltage Regulator Standby Dur ing Sleep bi t

1 = Voltage regulator goes into Standby mode during Sleep

0 = Voltage regulator is active during Sleep

bit 7 EXTR: External Reset (MCLR) Pin bit

1 = A Master Clear (pin) Reset has occurred

0 = A Master Clear (pin) Reset has not occurred

bit 6 SWR: Soft war e Reset (Instru cti on) Flag bit

1 = A RESET instruction has been executed

0 = A RESET instruction has not been executed

bit 5 SWDTEN: Software Enable/Disable of WDT bit(2)

1 = WDT is enabled

0 = WDT is disabled

bit 4 WDTO: Watchdog Timer Time-out F lag bit

1 = WDT time-out has occurred

0 = WDT time-out has not occurred

bit 3 SLEEP: Wake-up from Sleep Flag bit

1 = Device has been in Sleep mode

0 = Device has not been in Sleep mode

bit 2 IDLE: Wake-up from Idle Flag bit

1 = Device was in Idle mode

0 = Device was not in Idle mode

bit 1 BOR: Brown-out Rese t Flag bit

1 = A Brown-out Reset has occurred

0 = A Brown-out Reset has not occurred

Note 1: All of the Reset st atus bit s may be se t or cleared in so ftware. Setting one of these bit s in software does not

cause a device Reset.

2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the

SWDTEN bit setting.

PIC24H

bit 0 POR: Power-on Reset Flag bit

1 = A Power-on Reset has occurred

0 = A Power-on Reset has not occurred

Note 1: All of the Reset st atus bit s may be se t or cleared in sof tware. Setting one of these bit s in software does not

cause a device Reset.

2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the

SWDTEN bit setting.

PIC24H

TABLE 5-1: RESET FLAG BIT OPERATION

5.1 Clock Source Selection at Reset

If clock switching is enabled, the system clock source at

device Reset is chosen, as shown in Table 5-2. If clock

switching is disab led, the s ystem c lock source is alwa ys

selected according to the oscillator Configuration bits.

Refer to Section 8.0 “Oscillator Configuration” for

further details.

TABLE 5-2: OSCILLATOR SELECTION vs.

TYPE OF RESET (CLOCK

SWITCHING ENABLED)

5.2 Device Reset T imes

The Reset times for various types of device Reset are

summarized in Table 5-3. The system Reset signal is

released after the POR and PWRT delay times expire.

The time at which the devi ce actually be gins to execu te

code also depends on the system oscillator delays,

which include the Oscillator Start-up Timer (OST) and

the PLL lock time. The OST and PLL lock times occur

in parallel with the applicable reset delay times.

The FSCM delay determines the time at which the

FSCM begins to monitor the system clock source after

the reset signal is released.

Flag Bit Setting Event Clearing Event

TRAPR (RCON<15>) Trap conflict event POR

IOPUWR (RCON<14>) Illegal opcode or uninitialized

W register access POR

EXTR (RCON<7>) MCLR Reset POR

SWR (RCON<6>) RESET instruction POR

WDTO (RCON<4>) WDT time-out PWRSAV instruction, POR

SLEEP (RCON<3>) PWRSAV #SLEEP instruction POR

IDLE (RCON<2>) PWRSAV #IDLE instruction POR

BOR (RCON<1>) BOR —

POR (RCON<0>) POR —

Note: All Reset flag bits may be set or cleared by the user software.

Reset Type Clock Source Determinant

POR Oscillator Configuration bits

(FNOSC<2:0>)

BOR

MCLR COSC Control bits

(OSCCON<14:12>)

WDTR

SWR

PIC24H

TABLE 5-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS

5.2.1 POR AND LONG OSCILLATOR

START-UP TIMES

The osci llator st art-up ci rcuitry and it s associa ted delay

timers are not linked to the device Reset delays that

occur at power-up. Some crystal circuits (especially

low-frequency crystals) have a relatively long start-up

time. Th erefore, one or more of the foll owing condit ions

is possible after the Reset signal is released:

• The oscillator circuit has not begun to oscillate.

• The Osc ill ato r Start -up Timer has not expi red (if a

crystal oscillator is used).

• The PLL has not achieved a lock (if PLL is used).

The device will not begin to execute code until a valid

clock source has been released to the system. There-

fore, the oscillator and PLL start-up delays must be

consid ered when th e Reset delay time must b e known.

5.2.2 FAIL-SAFE CLOCK MONITOR

(FSCM) AND DEVICE RESETS

If the FSC M is enable d, it be gins t o monitor t he sys tem

clock source when the Reset signal is released. If a

valid clock source is not available at this time, the

device automati cally switch es to the F RC osc illator and

the user can switch to the desired crystal oscillator in

the Trap Service Ro utine.

5.2.2.1 FSCM Delay for Crystal and PLL

Clock Sources

When the system clock source is provided by a crystal

oscill ator and/or th e PLL, a small delay, TFSCM, is auto-

matically inserted after the POR and PWRT delay

times. Th e FSCM does not begin to monitor the sys tem

clock s ource until th is del ay expi res. The FSCM d elay

time is nominally 100 μs and provides additional time

for the osc illato r and/or PLL to sta biliz e. In mos t cases,

the FSCM delay prevents an oscillator failure trap at a

device Reset when the PWRT is disab led .

5.3 Special Function Register Reset

States

Most of the Special Function Registers (SFRs) associ-

ated with the CPU and peripherals are reset to a

particular value at a device Reset. The SFRs are

grouped by their peripheral or CPU function and their

Reset values are specified in each section of this

manual.

The Reset va lue for ea ch SFR do es not de pend on th e

type of Reset, with the exception of two registers. The

Reset value for the Reset Control register, RCON,

depends on the ty pe of dev ic e R es et. The Reset valu e

for the Oscillator Control register, OSCCON, depends

on the t ype of R eset and th e program med values of the

oscillator Configuration bits in the FOSC Configuration

Reset Type Clock Source SYSRST Delay System Clock

Delay FSCM

Delay Notes

POR EC, FRC, LPRC TPOR + TSTARTUP + T RST ——1, 2, 3

ECPLL, FRCPLL TPOR + TSTARTUP + T RST TLOCK TFSCM 1, 2, 3, 5, 6

XT, HS, SOSC TPOR + TSTARTUP + T RST TOST TFSCM 1, 2, 3, 4, 6

XTPLL, HSPLL TPOR + TSTARTUP + TRST TOST + TLOCK TFSCM 1, 2, 3, 4, 5, 6

MCLR Any Clock TRST ——3

WDT Any Clock TRST ——3

Software Any clock TRST ——3

Illegal Opcode Any Clock TRST ——3

Uninitialized W Any Clock TRST ——3

Trap Conflic t Any Clock T RST ——3

Note 1: TPOR = Power-on Reset delay (10 μs nominal).

2: TSTARTUP = Conditional POR delay of 20 μs nominal (if on-chip regulator is enabled) or 64 ms nominal

Power-up Timer delay (if regulator is disabled). TSTARTUP is also applied to all returns from powered-down

states, including waking from Sleep mode, only if the regulator is enabled.

3: TRST = Internal state Reset time (20 μs nominal).

4: TOST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the

oscillator clock to the system.

5: TLOCK = PLL lock time (20 μs nominal).

6: TFSCM = Fail-Safe Clock Monitor delay (100 μs nomin al).

PIC24H

NOTES:

PIC24H

6.0 INTERRUPT CONTROLLER

The PIC24 H interru pt co ntroller redu ce s the nume rous

periphera l interru pt reques t signa ls to a si ngle in terrupt

request signal to the PIC24H CPU. It has the following

features:

• Up to 8 processor exceptions and software traps

• 7 user-selectable priority levels

• Interrupt Vector Table (IVT) with up to 118 vectors

• A unique vector for each interrupt or exception

source

• Fixed priority within a specified user priority level

• Alternate Interrupt Vector Table (AIVT) for debug

support

• Fixed interrupt entry and return latencies

6.1 Interrupt Vector Table

The Interru pt Vector Table (IVT) is shown in F igure 6-1.

The IVT resides in program memory , starting at location

000004h. The IVT contains 126 vectors consisting of

8 nonmaskable trap vectors plus up to 118 sources of

interrupt. In general, each interrupt source has its own

vector. Each interrupt vector contains a 24-bit wide

address. The value programmed into each interrupt

vector l ocation is th e starti ng address of the assoc iated

Interrupt Service Routine (ISR).

Interrupt vectors are prioritized in terms of their natural

priority; this priority is linked to their position in the

vector table. All other things being equal, lower

addresses have a higher natural priority. For example,

the interrupt associated with vector 0 will take priority

over interrupts at any other vector address.

PIC24H devices implement up to 61 unique interrupts

and 5 nonmaskable traps. These are summarized in

Table 6-1 and Table 6-2.

6.1.1 ALTERNATE VECTOR TABLE

The Alternate Interrupt Vector Table (AIVT) is located

after the IVT, as shown in Figure 6-1. Access to the

AIVT is provided by the ALTIVT control bit

(INTCON2<15>). If the ALTIVT bit is set, all interrupt

and exception processes use the alternate vectors

inst ead of the defa ult vector s. The altern ate vectors a re

organized in the same manner as the default vectors.

The A IVT s up ports debugging b y prov id ing a m ean s to

switch between an application and a support environ-

ment without requiring the interrupt vectors to be

reprogrammed. This feature also enables switching

between applications for evaluation of different soft-

ware algorithms at run time. If the AIVT is not needed,

the AIVT should be programmed with the same

address es used in the IVT.

6.2 Reset Sequence

A device Reset is not a true exception because the

interr upt controller is not involved in the Rese t process.

The PIC2 4H device clears it s re gisters i n respons e to a

Reset which forces the PC to zero. The digital signal

controller then begins program execution at location

0x000000. The user programs a GOTO instruction at the

Reset address which redirects program execution to

the appropriate start-up routine.

Note: This data sheet summarizes the features

of this group of PIC24H devices. It is not

intende d to be a comprehe nsive referenc e

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

Note: Any unimplemented or unused vector

locations in the IVT and AIVT should be

programmed with the address of a default

interrupt handler routine that contains a

RESET instruction.

PIC24H

FIGURE 6-1: PIC24H INTERRUPT VECTOR TABLE

Reset – GOTO Instruction 0x000000

Reset – GOTO Address 0x000002

Reserved 0x000004

Oscillator Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

DMA Error Trap Vector

Reserved

Interrupt Vect or 0 0x 000014

Interrupt Vector 1

Interrupt Vector 52 0x00007C

Interrupt Vector 53 0x00007E

Interrupt Vector 54 0x000080

Interrupt Vector 116 0x0000FC

Interrupt Vector 117 0x0000FE

Reserved 0x000100

Reserved 0x000102

Reserved

Oscillator Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

DMA Error Trap Vector

Reserved

Interrupt Vect or 0 0x 000114

Interrupt Vector 1

Interrupt Vector 52 0x00017C

Interrupt Vector 53 0x00017E

Interrupt Vector 54 0x000180

Interrupt V ector 116

Interrupt Vector 117 0x0001FE

Start of Code 0x000200

Decreasing Natural Order Priority

Interrupt Vector Table (IVT)(1)

Alternate Interrupt Vector Table (AIVT)(1)

Note 1: See Table 6-1 for the list of implemented interrupt vectors.

PIC24H

TABLE 6-1: INTERRUPT VECTORS

Vector

Number

Interrupt

Request (IRQ)

Number IVT Address AIVT Address Interrupt Source

8 0 0x000014 0x000114 INT0 – External Interrupt 0

9 1 0x000016 0x000116 IC1 – Input Compare 1

10 2 0x000018 0x000118 OC1 – Output Compare 1

11 3 0x00001A 0x00011A T1 – Timer1

12 4 0x00001C 0x00011C DMA0 – DMA Channel 0

13 5 0x00001E 0x00011E IC2 – Input Capture 2

14 6 0x000020 0x000120 OC2 – Output Compare 2

15 7 0x000022 0x000122 T2 – Timer2

16 8 0x000024 0x000124 T3 – Timer3

17 9 0x000026 0x000126 SPI1E – SPI1 Error

18 10 0x000028 0x000128 SPI1 – SPI1 Transfer Done

19 11 0x00002A 0x00012A U1RX – UART1 Receiver

20 12 0x00002C 0x00012C U1TX – UART1 Transmitter

21 13 0x00002E 0x00012E ADC1 – A/D Converter 1

22 14 0x000030 0x000130 DMA1 – DMA Channel 1

23 15 0x000032 0x000132 Reserved

24 16 0x00003 4 0x000134 SI2C1 – I2C1 Slave Events

25 17 0x000036 0x000136 MI2C1 – I2C1 Master Events

26 18 0x000038 0x000138 Reserved

27 19 0x00003A 0x00013A CN - Change Notification Interrupt

28 20 0x00003C 0x00013C INT1 – External Interrupt 1

29 21 0x00003E 0x00013E ADC2 – A/D Converter 2

30 22 0x000040 0x000140 IC7 – Input Capture 7

31 23 0x000042 0x000142 IC8 – Input Capture 8

32 24 0x000044 0x000144 DMA2 – DMA Channel 2

33 25 0x000046 0x000146 OC3 – Output Compare 3

34 26 0x000048 0x000148 OC4 – Output Compare 4

35 27 0x00004A 0x00014A T4 – Timer4

36 28 0x00004C 0x00014C T5 – Timer5

37 29 0x00004E 0x00014E INT2 – External Interrupt 2

38 30 0x000050 0x000150 U2RX – UART2 Receiver

39 31 0x000052 0x000152 U2TX – UART2 Transmitter

40 32 0x000054 0x000154 SPI2E – SPI2 Error

41 33 0x000056 0x000156 SPI1 – SPI1 Transfer Done

42 34 0x000058 0x000158 C1RX – ECAN1 Receive Data Ready

43 35 0x00005A 0x00015A C1 – ECAN1 Event

44 36 0x00005C 0x00015C DMA3 – DMA Channel 3

45 37 0x00005E 0x00015E IC3 – Input Capture 3

46 38 0x000060 0x000160 IC4 – Input Capture 4

47 39 0x000062 0x000162 IC5 – Input Capture 5

48 40 0x000064 0x000164 IC6 – Input Capture 6

49 41 0x000066 0x000166 OC5 – Output Compare 5

50 42 0x000068 0x000168 OC6 – Output Compare 6

51 43 0x00006A 0x00016A OC7 – Output Compare 7

52 44 0x00006C 0x00016C OC8 – Output Compare 8

53 45 0x00006E 0x00016E Reserved

PIC24H

TABLE 6-2: TRAP VECTORS

54 46 0x000070 0x000170 DMA4 – DMA Channel 4

55 47 0x000072 0x000172 T6 – Timer6

56 48 0x000074 0x000174 T7 – Timer7

57 49 0x0000 76 0x000176 SI2C2 – I2C2 Slave Events

58 50 0x000078 0x000178 MI2C2 – I2C2 Master Events

59 51 0x00007A 0x00017A T8 – Timer8

60 52 0x00007C 0x00017C T9 – Timer9

61 53 0x00007E 0x00017E INT3 – External Interrupt 3

62 54 0x000080 0x000180 INT4 – External Interrupt 4

63 55 0x000082 0x000182 C2RX – ECAN2 Receive Data Ready

64 56 0x000084 0x000184 C2 – ECAN2 Event

65-68 57-60 0x000086-

0x00008C 0x000186-

0x00018C Reserved

69 61 0x00008E 0x00018E DMA5 – DMA Channel 5

70-72 62-64 0x000090-

0x000094 0x000190-

0x000194 Reserved

73 65 0x000096 0x000196 U1E – UART1 Error

74 66 0x000098 0x000198 U2E – UART2 Error

75 67 0x00009A 0x00019A Reserved

76 68 0x00009C 0x00019C DMA6 – DMA Channel 6

77 69 0x00009E 0x00019E DMA7 – DMA Channel 7

78 70 0x0000A0 0x0001A0 C1TX – ECAN1 Transmit Data Request

79 71 0x0000A2 0x0001A2 C2TX – ECAN2 Transmit Data Request

80-125 72-117 0x0000A4-

0x0000FE 0x0001A4-

0x0001FE Reserved

TABLE 6-1: INTERRUPT VECTORS (CONTINUED)

Vector

Number

Interrupt

Request (IRQ)

Number IVT Address AIVT Address Interrupt Source

Vector Number IVT Address AIVT Address Trap Source

0 0x000004 0x000084 Reserved

1 0x000006 0x000086 Oscillator Failure

2 0x000008 0x00008 8 Address Error

3 0x0 000 0A 0x00008A Stac k Error

4 0x00000C 0x00008C Math Error

5 0x00000E 0x00008E DMA Error Trap

6 0x000010 0x000090 Reserved

7 0x000012 0x000092 Reserved

PIC24H

6.3 Interrupt Control and Status

Registers

PIC24H devices implement a total of 30 registers for

the interrupt controller:

• INTCON1

• INTCON2

• IFS0 through IFS4

• IEC0 through IEC4

• IPC0 through IPC17

•INTTREG

Global interrupt control functions are controlled from

INTCON 1 an d INTC ON2. INT CON1 cont ain s the Inter-

rupt N esting Disa ble (NSTDIS) b it as well as the co ntrol

and status flags for the processor trap sources. The

INTCON2 register controls the external interrupt

request signal behavior and the use of the Alternate

Interrupt Vector Table.

The IFS registers maintain all of the interrupt request

flags. Each source of interrupt has a Status bit, which

is set by the respective peripherals or external signal

and is cleared via software.

The IEC registers maintain all of the interrupt enable

bits. These control bits are used to individually enable

interrupts from the peripherals or external signals.

The IPC registers are used to set the interrupt priority

level for each source of interrupt. Each user interrupt

source can be assigned to one of eight priority levels.

The INTTREG register contains the associated inter-

rupt vector number and the new CPU interrupt priority

level, which are latched into vector number (VEC-

NUM<6:0>) and Interrupt level (ILR<3:0>) bit fields in

the INTTREG register. The new interrupt priority level

is the priority of the pending interrupt.

The interrupt sources are assigned to the IFSx, IECx

and IPCx reg ist ers in th e s ame se quence that they are

listed in Table 6-1. For example, the INT0 (External

Interrupt 0) is shown as having vector number 8 and a

natural order priority of 0. Thus, the INT0IF bit is found

in IFS0<0>, the INT0IE b it i n IEC0< 0>, a nd th e INT0 IP

bits in the first position of IPC0 (IPC0<2:0>).

Although they are not specifically part of the interrupt

control hardware, two of the CPU Control registers con-

tain bits that control interrupt functionality. The CPU

STATUS register, SR, contains the IPL<2:0> bits

(SR<7:5>). These bits indicate the current CPU inter-

rupt priority level. The user can change the current

CPU priority level by writing to the IPL bits.

The CORCON register contains the IPL3 bit which,

together w i th I PL<2:0>, als o ind ic ates th e c urre nt CP U

priori ty level. IPL3 is a read-onl y bit so that tr ap ev ents

cannot be masked by the user softwar e.

All Interrupt registers are described in Register 6-1,

SR: CPU STATUS Register(1) through Register 6-32,

IPC17: Interrupt Priority Control Register 17, in the

following pages.

PIC24H

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — —DC

bit 15 bit 8

R/W-0(3) R/W-0(3) R/W-0(3) R-0 R/W-0 R/W-0 R/W-0 R/W-0

IPL2(2) IPL1(2) IPL0(2) RA N OV Z C

bit 7 bit 0

Legend:

C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’

S = Set only bit W = Writable bit -n = Value at POR

‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2)

111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled

110 = CPU Interrupt Priority Level is 6 (14)

101 = CPU Interrupt Priority Level is 5 (13)

100 = CPU Interrupt Priority Level is 4 (12)

011 = CPU In terrupt Priority Level is 3 (11)

010 = CPU Interrupt Priority Level is 2 (10)

001 = CPU Interrupt Priority Level is 1 (9)

000 = CPU Interrupt Priority Level is 0 (8)

Note 1: For complete register details, see Register 2-1, SR: CPU STATUS Register.

2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority

Lev el. The val ue in paren theses ind icates the IPL if IPL<3> = 1. User interrupt s are dis ab led when

IPL<3> = 1.

3: The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1.

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0

— — — — IPL3(2) PSV — —

bit 7 bit 0

Legend: C = Clea r only bit

R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set

0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’

bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2)

1 = CPU interrupt priority level is greater than 7

0 = CPU interrupt priority level is 7 or less

Note 1: For complete register details, see Register 2-2, CORCON: CORE Control Register.

2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.

PIC24H

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 NSTDIS: Interrupt Nesting Disable bit

1 = Interrupt nesting is disabled

0 = Interrupt nesting is enabled

bit 14 OVAERR: Accumulator A Overflow Trap Flag bit

1 = Trap was caused by overflow of Accumulator A

0 = Trap was not caused by overflow of Accumulator A

bit 13 OVBERR: Accumulator B Overflow Trap Flag bit

1 = Trap was caused by overflow of Accumulator B

0 = Trap was not caused by overflow of Accumulator B

bit 12 COVAERR: Accumulator A Catastrophic Overflow Trap Enable bit

1 = Trap was caused by catastrophic overflow of Accumulator A

0 = Trap was not caused by catastrophic overflow of Accumulator A

bit 11 COVBERR: Accumulator B Catastrophic Overflow Trap Enable bit

1 = Trap was caused by catastrophic overflow of Accumulator B

0 = Trap was not caused by catastrophic overflow of Accumulator B

bit 10 OVATE: Accumulator A Overflow Trap Enable bit

1 = Trap overflow of Accumulator A

0 = Trap disabled

bit 9 OVBTE: Accumulator B Overflow Trap Enable bit

1 = Trap overflow of Accumulator B

0 = Trap disabled

bit 8 COVTE: Catastrophic Overflow Trap Enable bit

1 = Trap on catastrophic overflow of Accumulator A or B enabled

0 = Trap disabled

bit 7 SFTACERR: Shift Accumulator Error Status bit

1 = Math error trap was caused by an invalid accumulator shift

0 = Math error trap was not caused by an invalid accumulator shift

bit 6 DIV0ERR: Arithmetic Error Status bit

1 = Math error trap was caused by a divide by zero

0 = Math error trap was not caused by a divide by zero

bit 5 DMACERR: DMA Controller Error Status bit

1 = DMA controller error trap has occurred

0 = DMA controller error trap has not occurred

bit 4 MATHERR: Arithmetic Error Status bit

1 = Math error trap has occurred

0 = Math error trap has not occurred

PIC24H

bit 3 ADDRERR: Address Error Trap Status bit

1 = Address error trap has occurred

0 = Address error trap has not occurred

bit 2 STKERR: Stack Error Trap Status bit

1 = Stack error trap has occurred

0 = Stack error trap has not occurred

bit 1 OSCFAIL: Oscillator Failure Trap Status bit

1 = Oscillator failure trap has occurred

0 = Oscillator failure trap has not occurred

bit 0 Unimplemented: Read as ‘0’

PIC24H

R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0

ALTIVT DISI — — — — — —

bit 15 bit 8

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — INT4EP INT3EP INT2EP INT1EP INT0EP

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit

1 = Use alternate vector table

0 = Use standard (default) vector table

bit 14 DISI: DISI Instruc tio n Stat us bit

1 = DISI instru cti on is ac tiv e

0 = DISI instru cti on is not ac tiv e

bit 13-5 Unimplemented: Read as ‘0’

bit 4 INT4EP: External Interrupt 4 Edge Detect Polarity Select bit

1 = Interrupt on negative edge

0 = Interrupt on positive edge

bit 3 INT3EP: External Interrupt 3 Edge Detect Polarity Select bit

1 = Interrupt on negative edge

0 = Interrupt on positive edge

bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit

1 = Interrupt on negative edge

0 = Interrupt on positive edge

bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit

1 = Interrupt on negative edge

0 = Interrupt on positive edge

bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit

1 = Interrupt on negative edge

0 = Interrupt on positive edge

PIC24H

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

T2IF OC2IF IC2IF DMA01IF T1IF OC1IF IC1IF INT0IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14 DMA1IF: DMA Channel 1 Data Transfer Complete Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 13 AD1IF: ADC1 Conversion Complete Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 12 U1TXIF: UART1 Transmitter Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 11 U1RXIF: UART1 Receiver Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 10 SPI1IF: SPI1 Event Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 9 SPI1EIF: SPI1 Fault Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 8 T3IF: Timer3 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 7 T2IF: Timer2 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 6 OC2IF: Output Compare Channel 2 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 5 IC2IF: Input Capture Channel 2 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 4 DMA0IF: DMA Channel 0 Data Transfer Complete Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 3 T1IF: Timer1 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

PIC24H

bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 0 INT0IF: External Interrupt 0 Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

PIC24H

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA21IF

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IC8IF IC7IF AD2IF INT1IF CNIF — MI2C1IF SI2C1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 U2TXIF: UART2 Transmitter Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 14 U2RXIF: UART2 Receiver Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 13 INT2IF: External Interrupt 2 Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 12 T5IF: Timer5 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 11 T4IF: Timer4 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 10 OC4IF: Output Compare Channel 4 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 9 OC3IF: Output Compare Channel 3 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 8 DMA2IF: DMA Channel 2 Data Transfer Complete Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 7 IC8IF: Input Capture Channel 8 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 6 IC7IF: Input Capture Channel 7 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 5 AD2IF: ADC2 Conversion Complete Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 4 INT1IF: External Interrupt 1 Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

PIC24H

bit 3 CNIF: Input Change Notification Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 2 Unimplemented: Read as ‘0’

bit 1 MI2C1IF: I2C1 Master Events Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

PIC24H

R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

T6IF DMA4IF — OC8IF OC7IF OC6IF OC5IF IC6IF

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IC5IF IC4IF IC3IF DMA3IF C1IF C1RXIF SPI2IF SPI2EIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 T6IF: Timer6 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 14 DMA4IF: DMA Channel 4 Data Transfer Complete Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 13 Unimplemented: Read as ‘0’

bit 12 OC8IF: Output Compare Channel 8 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 11 OC7IF: Output Compare Channel 7 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 10 OC6IF: Output Compare Channel 6 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 9 OC5IF: Output Compare Channel 5 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 8 IC6IF: Input Capture Channel 6 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 7 IC5IF: Input Capture Channel 5 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 6 IC4IF: Input Capture Channel 4 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 5 IC3IF: Input Capture Channel 3 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 4 DMA3IF: DMA Channel 3 Data Transfer Complete Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 3 C1IF: ECAN1 Event Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

PIC24H

bit 2 C1RXIF: ECAN1 Receive Data Ready Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 1 SPI2IF: SPI2 Event Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 0 SPI2EIF: SPI2 Error Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

PIC24H

U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0

——DMA5IF— — — —C2IF

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

C2RXIF INT4IF INT3IF T9IF T8IF MI2C2IF SI2C2IF T7IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13 DMA5IF: DMA Channel 5 Data Transfer Complete Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 12-9 Unimplemented: Read as ‘0’

bit 8 C2IF: ECAN2 Event Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 7 C2RXIF: ECAN2 Receive Data Ready Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 6 INT4IF: External Interrupt 4 Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 5 INT3IF: External Interrupt 3 Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 4 T9IF: Timer9 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 3 T8IF: Timer8 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 2 MI2C2IF: I2C2 Master Events Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 1 SI2C2IF: I2C2 Slave Events Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 0 T7IF: Timer7 Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

PIC24H

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0

C2TXIF C1TXIF DMA7IF DMA6IF —U2EIFU1EIF—

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 Unimplemented: Read as ‘0’

bit 7 C2TXIF: ECAN2 Transmit Data Request Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 6 C1TXIF: ECAN1 Transmit Data Request Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 5 DMA7IF: DMA Channel 7 Data Transfer Complete Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 4 DMA6IF: DMA Channel 6 Data Transfer Complete Interrupt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 3 Unimplemented: Read as ‘0’

bit 2 U2EIF: UAR T2 Error Interru pt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 1 U1EIF: UAR T1 Error Interru pt Flag Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 0 Unimplemented: Read as ‘0’

PIC24H

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14 DMA1IE: DMA Channel 1 Data Transfer Complete Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 13 AD1IE: ADC1 Conversion Complete Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 12 U1TXIE: UART1 Transmitter In terrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 11 U1RXIE: UART1 Receiver Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 10 SPI1IE: SPI1 Event Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 9 SPI1EIE: SPI1 Error Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 8 T3IE: Timer3 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 7 T2IE: Timer2 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 6 OC2IE: Output Compare Channel 2 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 5 IC2IE: Input Capture Channel 2 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 4 DMA0IE: DMA Channel 0 Data Transfer Complete Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 3 T1IE: Timer1 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

PIC24H

bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 0 INT0IE: External Interrupt 0 Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

PIC24H

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

IC8IE IC7IE AD2IE INT1IE CNIE — MI2C1IE SI2C1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 U2TXIE: UART2 Transmitter Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 14 U2RXIE: UART2 Receiver Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 13 INT2IE: External Interrupt 2 Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 12 T5IE: Timer5 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 11 T4IE: Timer4 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 10 OC4IE: Output Compare Channel 4 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 9 OC3IE: Output Compare Channel 3 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 8 DMA2IE: DMA Channel 2 Data Transfer Complete Interrupt Enable bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 7 IC8IE: Input Capture Channel 8 Interrupt Enable bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 6 IC7IE: Input Capture Channel 7 Interrupt Enable bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 5 AD2IE: ADC2 Conversion Complete Interrupt Enable bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 4 INT1IE: External Interrupt 1 Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

PIC24H

bit 3 CNIE: Input Change Notification Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 2 Unimplemented: Read as ‘0’

bit 1 MI2C1IE: I2C1 Master Events Inte rrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

PIC24H

R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

T6IE DMA4IE — OC8IE OC7IE OC6IE OC5IE IC6IE

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IC5IE IC4IE IC3IE DMA3IE C1IE C1RXIE SPI2IE SPI2EIE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 T6IE: Timer6 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 14 DMA4IE: DMA Channel 4 Data Transfer Complete Interrupt Enable bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 13 Unimplemented: Read as ‘0’

bit 12 OC8IE: Output Compare Channel 8 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 11 OC7IE: Output Compare Channel 7 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 10 OC6IE: Output Compare Channel 6 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 9 OC5IE: Output Compare Channel 5 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 8 IC6IE: Input Capture Channel 6 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 7 IC5IE: Input Capture Channel 5 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 6 IC4IE: Input Capture Channel 4 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 5 IC3IE: Input Capture Channel 3 Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 4 DMA3IE: DMA Channel 3 Data Transfer Complete Interrupt Enable bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 3 C1IE: ECAN1 Event Interrupt Enable bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

PIC24H

bit 2 C1RXIE: ECAN1 Receive Data Ready Interrupt Enable bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 1 SPI2IE: SPI2 Event Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 0 SPI2EIE: SPI2 Error Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

PIC24H

U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0

——DMA5IE— — — —C2IE

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

C2RXIE INT4IE INT3IE T9IE T8IE MI2C2IE SI2C2IE T7IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13 DMA5IE: DMA Channel 5 Data Transfer Complete Interrupt Enable bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 12-9 Unimplemented: Read as ‘0’

bit 8 C2IE: ECAN2 Event Interrupt Enable bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 7 C2RXIE: ECAN2 Receive Data Ready Interrupt Enable bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 6 INT4IE: External Interrupt 4 Enable bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 5 INT3IE: External Interrupt 3 Enable bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 4 T9IE: Timer9 Interrupt Enable bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 3 T8IE: Timer8 Interrupt Enable bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 2 MI2C2IE: I2C2 Master Events Inte rrupt Enable bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 1 SI2C2IE: I2C2 Slave Events Interrupt Enable bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 0 T7IE: Timer7 Interrupt Enable bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

PIC24H

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0

C2TXIE C1TXIE DMA7IE DMA6IE —U2EIEU1EIE—

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 Unimplemented: Read as ‘0’

bit 7 C2TXIE: ECAN2 Transmit Data Request Interrupt Enable bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 6 C1TXIE: ECAN1 Transmit Data Request Interrupt Enable bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 5 DMA7IE: DMA Channel 7 Data Transfer Complete Enable Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 4 DMA6IE: DMA Channel 6 Data Transfer Complete Enable Status bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 3 Unimplemented: Read as ‘0’

bit 2 U2EIE: UART2 Error Interrupt Enable bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 1 U1EIE: UART1 Error Interrupt Enable bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 0 Unimplemented: Read as ‘0’

PIC24H

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— T1IP<2:0> — OC1IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— IC1IP<2:0> — INT0IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 IC1IP<2:0>: Input Captur e Chann e l 1 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 INT0IP<2:0>: External In terrupt 0 Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

PIC24H

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— T2IP<2:0> — OC2IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— IC2IP<2:0> — DMA0IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 IC2IP<2:0>: Input Capture Channel 2 Inte rrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 DMA0IP<2:0>: DMA Channel 0 Data Transfer Complete Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

PIC24H

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— U1RXIP<2:0> — SPI1IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— SPI1EIP<2:0> — T3IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 U1RXIP<2:0>: UAR T1 Rece iv er Interru pt Priori ty bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 SPI1IP<2:0>: SPI1 Event Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 SPI1EIP<2:0>: SPI1 Error Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

PIC24H

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0

— — — — — DMA1IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— AD1IP<2:0> — U1TXIP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-11 Unimplemented: Read as ‘0’

bit 10-8 DMA1IP<2:0>: DMA Channel 1 Data Transfer Complete Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 AD1IP<2:0>: ADC1 Conversion Complete Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

PIC24H

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

—CNIP<2:0>— — — —

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— MI2C1IP<2:0> — SI2C1IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 CNIP<2:0>: Change Notification Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 11-7 Unimplemented: Read as ‘0’

bit 6-4 MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

PIC24H

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— IC8IP<2:0> —IC7IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— AD2IP<2:0> — INT1IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 IC8IP<2:0>: Input Captur e Chann e l 8 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 IC7IP<2:0>: Input C a pture Channel 7 Inte rrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 AD2IP<2:0>: ADC2 Conversion Complete Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

PIC24H

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— T4IP<2:0> — OC4IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

—OC3IP<2:0>— DMA2IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 T4IP<2:0>: Timer4 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 OC4IP<2:0>: Output Compare Channel 4 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 DMA2IP<2:0>: DMA Channel 2 Data Transfer Complete Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

PIC24H

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— U2TXIP<2:0> — U2RXIP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— INT2IP<2:0> — T5IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 U2RXIP<2:0>: UART2 Receiver Interrupt Pr iori ty bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 T5IP<2:0>: Timer5 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

PIC24H

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— C1IP<2:0> — C1RXIP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— SPI2IP<2:0> — SPI2EIP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 C1IP<2:0>: ECAN1 Event Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 C1RXIP<2:0>: ECAN1 Receive Data Ready Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 SPI2IP<2:0>: SPI2 Event Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 SPI2EIP<2:0>: SPI2 Error Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

PIC24H

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— IC5IP<2:0> —IC4IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— IC3IP<2:0> — DMA3IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 IC5IP<2:0>: Input Captur e Chann e l 5 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 IC4IP<2:0>: Input C a pture Channel 4 Inte rrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 IC3IP<2:0>: Input Capture Channel 3 Inte rrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 DMA3IP<2:0>: DMA Channel 3 Data Transfer Complete Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

PIC24H

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

—OC7IP<2:0>— OC6IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

—OC5IP<2:0>— IC6IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 OC7IP<2:0>: Output Compare Channel 7 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 OC6IP<2:0>: Output Compare Channel 6 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 OC5IP<2:0>: Output Compare Channel 5 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 IC6IP<2:0>: Input Captur e Chann e l 6 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

PIC24H

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— T6IP<2:0> — DMA4IP<2:0>

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0

— — — — — OC8IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 T6IP<2:0>: Timer6 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 DMA4IP<2:0>: DMA Channel 4 Data Transfer Complete Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 7-3 Unimplemented: Read as ‘0’

bit 2-0 OC8IP<2:0>: Output Compare Channel 8 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

PIC24H

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— T8IP<2:0> — MI2C2IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— SI2C2IP<2:0> — T7IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 T8IP<2:0>: Timer8 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 MI2C2IP<2:0>: I2C2 Master Events Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 SI2C2IP<2:0>: I2C2 Slave Events Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 T7IP<2:0>: Timer7 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

PIC24H

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— C2RXIP<2:0> — INT4IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— INT3IP<2:0> — T9IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 C2RXIP<2:0>: ECAN2 Receive Data Ready Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 INT4IP<2:0>: External Interrupt 4 Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 INT3IP<2:0>: External Interrupt 3 Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 T9IP<2:0>: Timer9 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

PIC24H

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0

— — — — — C2IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-3 Unimplemented: Read as ‘0’

bit 2-0 C2IP<2:0>: ECAN2 Event Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

PIC24H

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— DMA5IP<2:0> — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-7 Unimplemented: Read as ‘0’

bit 6-4 DMA5IP<2:0>: DMA Channel 5 Data Transfer Complete Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

PIC24H

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0

— — — — — U2EIP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— U1EIP<2:0> — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-11 Unimplemented: Read as ‘0’

bit 10-8 U2EIP<2:0>: UAR T2 Error Interr upt Priority bit s

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 U1EIP<2:0>: UART1 Error Interrupt Prior ity bit s

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

PIC24H

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— C2TXIP<2:0> — C1TXIP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— DMA7IP<2:0> — DMA6IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 C2TXIP<2:0>: ECAN2 Transmit Data Request Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’

bit 10-8 C1TXIP<2:0>: ECAN1 Transmit D a ta Request Inter rupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’

bit 6-4 DMA7IP<2:0>: DMA Channel 7 Data Transfer Complete Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 DMA6IP<2:0>: DMA Channel 6 Data Transfer Complete Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1

000 = Interrupt source is disabled

PIC24H

R-0 R/W-0 U-0 U-0 R-0 R-0 R-0 R-0

— — — —ILR<3:0>

bit 15 bit 8

U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0

— VECNUM<6:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-12 Unimplemented: Read as ‘0’

bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits

1111 = CPU Interrupt Priority Level is 15

•

0001 = CPU Interrupt Priority Level is 1

0000 = CPU Interrupt Priority Level is 0

bit 7 Unimplemented: Read as ‘0’

bit 6-0 VECNUM<6:0>: Vector Number of Pending Interrupt bits

1111111 = Interrupt Ve ctor pending is number 135

•

0000001 = Interrupt Ve ctor pending is number 9

0000000 = Interrupt Ve ctor pending is number 8

PIC24H

6.4 Interrupt Setup Procedures

6.4.1 INITIALIZATION

To configure an interrupt source:

1. Set the NSTDIS bit (INTCON1<15>) if nested

interrupts are not desired.

2. Select the user-assigned priority level for the

interrupt source by writing the control bits in the

appropriate IPCx register. The priority level will

depend on the specific application and type of

inter rupt source . If multipl e priority le vels are n ot

desired, the IPCx register control bits for all

enabled interrupt sources may be programmed

to the same non-zero value.

3. Clear the int errupt flag st atus bi t associa ted with

the peri pheral in the associated IFSx register.

4. Enable the interrupt source by setting the inter-

rupt enable control bit associated with the

source in the app ropriate IECx register.

6.4.2 INTERRUPT SERVICE ROUTINE

The method that is used to declare an ISR and initialize

the IVT with the correct vector address will depend on

the programming language (i.e., C or assembler) and

the language development toolsuite that is used to

develo p the applica tion. In genera l, the user mus t clear

the interru pt flag in the ap propriate IFS x register for the

source of interrupt that the ISR hand les. Otherwise, the

ISR will be re-entered immediately after exiting the

routine. If the ISR is coded in assembly language, it

must be terminated using a RETFIE instruction to

unstack the saved PC value, SRL value and old CPU

priority level.

6.4.3 TRAP SERVICE ROUTINE

A Trap Service Routine (TSR) is coded like an ISR,

except that the appropriate trap status flag in the

INTCON1 register must be cleared to avoid re-entry

into the TSR.

6.4.4 INTERRUPT DISABLE

All user interrupts can be disabled using the following

procedure:

1. Push the current SR value onto the software

stack using the PUSH instructi on.

2. Force the CPU to priority level 7 by inclusive

ORing the value 0x0E with SRL.

To enable user interrupts, the POP instruction may be

used to restore the previous SR value.

Note tha t only user interrupt s with a prio rity leve l of 7 or

less can be disabled. Trap sources (level 8-level 15)

cannot be disabled.

The DISI instruction pro vides a co nvenient way to dis-

able inte rrupts of priority leve ls 1- 6 fo r a fix ed pe riod of

time. Level 7 interrupt sources are not disabled by the

DISI instruction.

Note: At a device Reset, t he IPCx reg ister s are

initialized, such that all user interrupt

sources are assigned to priority level 4.

PIC24H

NOTES:

PIC24H

7.0 DIRECT MEMORY ACCESS

(DMA)

Direct Memory Access (DMA) is a very efficient

mechanism of copying data between peripheral SFRs

(e.g., UART Receive register, Input Capture 1 buffer),

and buffers or variables stored in RAM, with minimal

CPU intervention. The DMA controller can

automatically copy entire blocks of data without

requiring the user software to read or write the

peripheral Special Function Registers (SFRs) every

time a p eriph eral interr upt oc curs. Th e DMA con trol ler

uses a dedicated bus for data transfers and, therefore,

does not steal cycles from the code execution flow of

the CPU. To exploit the DMA capability, the

corresponding user buffers or variables must be

located in DMA RAM.

The PIC2 4H perip herals that ca n ut ilize DMA are li sted

in Table 7-1 along with their associated Interrupt

Request (IRQ) numbers.

TABLE 7-1: PERIPHERALS WITH DMA

SUPPORT

The DMA controller features eight identical data

transfer channels.

Each channel has its own set of control and status

registers. Each DMA channel can be configured to

copy data either from buffers stored in dual port DMA

RAM to peripheral SFRs, or from peripheral SFRs to

buffers in DMA RAM.

The DMA controller supports the following features:

• Word or byte sized data transfers.

• Transfers from peripheral to DMA RAM or DMA

RAM to peripheral.

• Indirect Addressi ng of DMA RAM locations with or

without automatic post-increment.

• Per ipheral Indirect Addressing – In some periph-

erals, the DMA RAM read/write addresses may

be partial ly derived from the peripheral.

• One-Shot Block Transfers – Terminating DMA

transfer after one block transfer.

• Continuous Block Transfers – Reloading DMA

RAM buffer start ad dress after every block

transfer is complete.

• Ping-Pong Mode – Switching between two DMA

RAM start addresses between successive block

transfers, thereby filling two buffers alternately.

• Automatic or manual initiation of block transfers

• Each channel can select from 19 possible

sources of data sources or destinations.

For each DMA channel, a DMA interrupt request is

generated when a block transfer is complete.

Alternatively, an interrupt can be generated wh en half of

the block has been filled.

Note: This data sheet summarizes the features

of this group of PIC24H devices. It is not

intende d to be a comprehe nsive referenc e

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

Peripheral IRQ Number

INT0 0

Input Capture 1 1

Input Capture 2 5

Output Compare 1 2

Output Compare 2 6

Timer2 7

Timer3 8

SPI1 10

SPI2 33

UART1 Reception 11

UART1 Transmission 12

UART2 Reception 30

UART2 Transmission 31

ADC1 13

ADC2 21

ECAN1 Reception 34

ECAN1 Transmission 70

ECAN2 Reception 55

ECAN2 Transmission 71

PIC24H

FIGURE 7-1: TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS

7.1 DMAC Registers

Each DMAC Channel x (x = 0, 1, 2, 3, 4, 5, 6 or 7)

cont ains the followi ng regi ste rs:

• A 16-bit DMA Channel Control register

(DMAxCON)

• A 16-bit DMA Channel IRQ Select register

(DMAxREQ)

• A 16-bit DMA RAM Primary S tart Address register

(DMAxSTA)

• A 16-bit DMA RAM Secondary Start Address

• A 16-bit DMA Peripheral Address register

(DMAxPAD)

• A 10-bit DMA Transfer Count register (DMAx-

CNT)

An additional status register, DMACS, is common to

all DMAC channels. It contains the DMA RAM and

SFR write collision flags, XWCOLx and PWCOLx,

respectively.

The DMAxCON, DMAxREQ, DMAxPAD and

DMAxCNT are all conventional read/write registers.

Reads of DMAxSTA or DMAxSTB will read the con-

tents of the DMA RAM Address register. Writes to

DMAxSTA or DMAxSTB write to the registers. This

allows the user to determine the DMA buffer pointer

value (address) at any time.

The interrupt flags (DMAxIF) are located in an IFSx

interrupt enable control bits (DMAxIE) are located in

an IECx register in the interrupt controller, and the cor-

responding interrupt priority control bits (DMAxIP) are

located in an IPCx register in the interrupt controller.

7.2 DMAC Operating Modes

Each DMA channel has its own status and control reg-

ister (DMAx C ON) that is u se d to con f ig ure t he c ha nne l

to support the following operating modes:

• Word or byte size data transfers

• Peripheral to DMA RAM or DMA RAM to

peripheral transfers

• Post-increment or static DMA RAM address

• One-shot or continuous block transfers

• Auto-switch between two start addresses after

each transfer complete (Ping-Pong mode)

• Force a single DMA transfer (Manual mode)

Each DMA channel can be independently configured

to:

• Select from one of 19 DMA request sources

• Manual ly ena ble or disable the DMA cha nne l

• Interrupt the CPU when th e tra ns fer is hal f o r fully

complete

DMA chann el inte rrupt s are routed to the inte rrupt co n-

troller module and enabled through associated enable

flags.

The channel DMA RAM and peripheral write collision

Faults are combined into a single DMAC error trap

(Level 10) and are not maskable. Each channel has

DMA RAM write collision (XWCOLx) and peripheral

CPU

SRAM DMA RAM

CPU Peripheral DS Bus

Peripheral 3

DMA

Peripheral

Non-DMA

SRAM X-Bus

PORT 2PORT 1

Peripheral 1

DMA

Ready Peripheral 2

DMA

Ready

DMA DS Bus

CPU DMA

CPU DMA CPU DMA

Peripheral Indirect Address

Note: CPU and DMA address buses are not shown for clarity.

DMA

Control

DMA Controller

DMA

Channels

PIC24H

write collision (PWCOLx) status bits in the DMAC Sta-

tus register (DMACS) to allow the DMAC error trap

handler to determ ine the source of th e Fault co ndition.

7.2.1 BY T E OR WORD TRANSFER

Each DMA channel can be configured to transfer

words or bytes. As usual, words can only be moved to

and from aligned (even) addresses. Bytes can be

moved to or from any (legal) address.

If the SIZE bit (DMAxCON<14>) is clear, word sized

data is tra nsferre d. The LSb of the D MA RAM Add res s

Post-Increment Addressing m od e i s e na ble d, t he DMA

RAM Address register is incremented by 2 after every

word transfer.

If the SIZE bit is set, byte sized data is transferred. If

Post-Increment Addressing is enabled, the DMA RAM

Address register is incremented by 1 after every byte

transfer.

7.2.2 ADDRESSING MODES

The DMAC supports Register Indirect and Register

Indirect Post-Increment Addressing modes for DMA

RAM addresses (source or destination). Each channel

can select the DMA RAM Addressing mode indepen-

dently. The Peripheral SFR is always accessed using

Regist er Indi rec t Addressi ng.

If the AMODE<1:0> bits (DMAxCON<5:4>) are set to

‘01’, Register Indirect Addressing without

Post-Increment is used, which implies that the DMA

RAM address remains constant.

If the AMODE<1:0> bits are clear, DMA RAM is

accessed using Register Indirect Addressing with

Post-Increment, which means the DMA RAM address

will be incremented after every access.

Any DMA channel can be configured to operate in

Peripheral Indirect Addressing mode by setting the

AMODE<1:0> bits to ‘10’. In this mode, the DMA RAM

sour ce or desti nation address i s partial ly derive d from

the peripheral as well as the DMA Address registers.

Each perip heral modul e has a pre-a ss ign ed pe rip hera l

indirect address which is logically ORed with the DMA

S t art Addres s registe r to obt ain the ef fecti ve DMA RAM

address. The DMA RAM Start Address register value

must be aligned to a power-of-two boundary.

7.2.3 DMA TRANSFER DIRECTION

Each DMA channel can be configured to transfer data

from a p eriphera l to DMA R AM, or from DMA R AM to a

peripheral.

If the DIR bit (DMAxCON<13>) is clear, the reads

occur from a peripheral SFR (using the DMA Periph-

eral Address register, DMAxPAD) and the writes are

directed to the DMA RAM (using the DMA RAM

Address regi ste r).

If the DIR bit (DMAxCON<13>) is set, the reads occur

from the DMA RAM (using the DMA RAM Address

(using the DMA Peripheral Address register,

DMAxPAD).

7.2.4 NULL DA TA PERIPHERA L WRITE

MODE

If the NULLW bit (DMAxCON<11>) is set, a null data

write to the peripheral SFR is performed in addition to

a data transf er from the pe riphera l SFR t o DMA R AM

(assum ing the DIR bi t is cl ear). Thi s mod e is mos t use-

ful in applicati on s in w hic h s equ ent ial reception of dat a

is required without any data transmission.

Note: DMAxCNT value is independent of data

transfer si ze (byte/word). If an ad dress off-

set is required, a 1-bit left shift of the

counter i s required to g enerate the correc t

offset for (aligned) word transfers.

Note: Only the ECAN and A/D modules can

utilize Peripheral Indirect Addressing.

PIC24H

7.2.5 CONTINUOUS OR ONE-SHOT

OPERATION

Each DMA channel can be configured for One-Shot or

Contin uou s mo de operation.

If MODE<0> (DMAxCON<0>) is clear, the channel

operates in Continuous mode.

When all data has been moved (i.e., buffer end has

been detected), the channel is automatically reconfig-

ured for subsequent use. During the last data transfer,

the next Effective Address generated will be the origi-

nal start address (from the selected DMAxSTA or

DMAxSTB register). If the HALF bit (DMAxCON<12>)

is clear, the transfer complete interrupt flag (DMAxIF)

is set. If the HALF bit is set, DMAxIF will not be set at

this time and the channel will remain enabled.

If MODE<0> is set, the channel operates in One-Shot

mode. When all data has been moved (i.e., buffer end

has been detected), the channel is automatically dis-

abled. During the last data transfer, no new Effective

Address is generated and the DMA RAM Address

accessed. If the HALF bit is clear, the DMAxIF bit is

set. If the HALF bit is set, the DMAxIF will not be set at

this time and the channel is automatically disabled.

7.2.6 PING-PONG MODE

When the MODE<1> bit (DMAxCON<1>) is set by the

use r, Ping-Pong mode is enabled.

In this mode, successive block transfers alternately

select DMAxSTA and DMAxSTB as the DMA RAM

start address. In this way, a single DMA channel can

be used to support two buffers of the same length in

DMA RAM. Using this technique maximizes data

throughput by allowing the CPU time to process one

buffer whi le the other is being loade d .

7.2.7 MANUAL TRANSFER MODE

A manual DMA request can be created by setting the

FORCE bit (DMAxREQ<15>) in software. If already

enabled, the corresponding DMA channel executes a

single data element transfer rather than a block trans-

fer.

The FORCE bit is cleared by hardware when the

forced DMA transfer is complete and cannot be

cleared by the user. Any attempt to set this bit prior to

completion of a DMA request that is underway will

have no effect.

The man ual DMA tr ansfer f unctio n is a o ne-time e vent.

The DMA channel always reverts to normal operation

(i.e., based on hardware DMA requests) after a forced

(manual) transfer.

This mode provides the user a straightforward method

of initiating a block transfer. For example, using

Manual mode to transfer the first data element into a

serial peripheral allows subsequent data within the

buf f er to be m ove d a utomatically by the D MAC usi ng a

‘transmit buffer empty’ DMA request.

7.2.8 DMA REQUEST SOURCE

SELECTION

Each DMA channel can select between one of 128

interrupt sources to be a DMA request for that chan-

nel, based on the contents of the IRQSEL<6:0> bits

(DMAxREQ<6:0>. The available interrupt sources are

device dependent. Please refer to Table 7-1 for IRQ

numbers associated with each of the interrupt sources

that can generate a DMA transfer.

7.3 DMA Interrupts and Traps

Each DMA channel can generate an independent

‘block transfer complete’ (HALF = 0) or ‘half block

transfer complete’ (HALF = 1) interrupt. Every DMA

channel has its own interrupt vector and therefore,

does not use the interrupt vector of the peripheral to

which it is assigned. If a peri phe ral contains mul ti-wo rd

buffers, the buffering function must be disabled in the

peripheral in order to use DMA. DMA interrupt

requests are only generated by data transfers and not

by peripheral error conditions.

The DMA controller can also react to peripheral and

DMA RAM write collision error conditions through a

nonmaskable CPU trap event. A DMA error trap is

generated in either of the following Fault c onditions :

• DMA RAM data write collision between the CPU

and a peripheral

- This condition occurs when t he CPU and a

peripheral attempt to write to the same DMA

RAM address simultaneously

• Perip heral SFR data write collision between the

CPU and the DMA controller

- This condition occurs when the CPU and the

DMA controller attempt to write to the same

peripheral SFR simultaneously

The channel DMA RAM and peripheral write collision

Faults are combined into a single DMAC error trap

(Level 10) and are nonmaskable. Each channel has

DMA RAM Write Collision (XWCOLx) and Peripheral

Write Collision (PWCOLx) status bits in the DMAC

Status register (DMACS) to allow the DMAC error trap

handler to determine the source of the Fault co ndition.

PIC24H

7.4 DMA Initialization Example

The following is a DMA initialization example:

EXAMPLE 7-1: DMA SAMPLE INITIALIZATION METHOD

// Clear all DMA controller status bits to a known state

DMACS0 = 0;

// Set up DMA Channel 0: Word mode, Read from Peripheral & Write to DMA; Interrupt when all the

data has been moved; Indirect with post-increment; Continuous mode with Ping-Pong Disabled

DMA0CON = 0x000D;

//Automatic DMA transfer initiation by DMA request; DMA Peripheral IRQ Number set up for ADC1

DMA0REQ = 0x0000;

// Set up offset into DMA RAM so that the buffer that collects A/D result data starts at the base

of DMA RAM

DMA0STA = 0x0000;

// DMA0PAD should be loaded with the address of the A/D conversion result register

DMA0PAD = (volatile unsigned int) &ADC1BUF0;

// DMA transfer of 256 words of data

DMA0CNT = 0x0100 ;

//Clear the DMA0 Interrupt Flag

IFS0bits.DMA0IF = 0;

//Enable DMA0 Interrupts

IEC0bits.DMA0IE = 1;

//Enable the DMA0 Channel

DMA0CONbits.CHEN = 1;

PIC24H

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0

CHEN SIZE DIR HALF NULLW — — —

bit 15 bit 8

U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0

——AMODE<1:0>——MODE<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 CHEN: Channel Enable bit

1 = Channe l enabled

0 = Channel disabled

bit 14 SIZE: Data Transfer Size bit

1 = Byte

0 = Word

bit 13 DIR: Transfer Direction bit (source/destination bus select)

1 = Read from DMA RAM address, write to peripheral address

0 = Read from peripheral address, write to DMA RAM address

bit 12 HALF: Early Block Transfer Complete Interrupt Select bit

1 = Initiate block transfer complete interrupt when half of the data has been moved

0 = Initiate block transfer complete interrupt when all of the data has been moved

bit 11 NULLW: Null Data Peripheral Write Mode Select bit

1 = Null data write to peripheral in addition to DMA RAM write (DIR bit must also be clear)

0 = Normal operation

bit 10-6 Unimplemented: Read as ‘0’

bit 5-4 AMODE<1:0>: DMA Channel Operating Mode Select bits

11 = Reserved (will act as Peripheral Indirect Addressing mode)

10 = Peripheral Indirect Addressing mode

01 = Register Indirect without Post-Increment mode

00 = Register Indirect with Post-Increment mode

bit 3-2 Unimplemented: Read as ‘0’

bit 1-0 MODE<1:0>: DMA Channel Operating Mode Select bits

11 = One-Shot, Ping-Pong modes enabled (one block transfer from/to each DMA RAM buffer)

10 = Continuous, Ping-Pong modes enabled

01 = One-Shot, Ping-Pong modes disabled

00 = Continuous, Ping-Pong modes disabled

PIC24H

R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

FORCE(1) — — — — — — —

bit 15 bit 8

U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0

— IRQSEL6(2) IRQSEL5(2) IRQSEL4(2) IRQSEL3(2) IRQSEL2(2) IRQSEL1(2) IRQSEL0(2)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 FORCE: Force DMA Transfer bit(1)

1 = Force a single DMA transfer (Manual mode)

0 = Automatic DMA transfer initiation by DMA request

bit 14-7 Unimplemented: Read as ‘0’

bit 6-0 IRQSEL<6:0>: DMA Peripheral IRQ Number Select bits(2)

0000000-1111111 = DMAIRQ0-D MAI RQ1 27 sel ected to be Chann el DMAREQ

Note 1: The FOR CE bit ca nnot be cl eared by th e user. The FORCE bi t is clear ed by har dware when the forc ed

DMA transfer is complete.

2: Please see Table 6-1 for a complete listing of IRQ numbers for all interrupt sources.

PIC24H

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

STA<15:8>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

STA<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 STA<15:0>: Primary DMA RAM Start Address bits (source or destination)

Note 1: A read of this address register will return the current contents of the DMA RAM Address register, not the

contents written to STA<15:0>. If the channel is enabled (i.e., active), writes to this register may result in

unpredictable behavior of the DMA channel and should be avoided.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

STB<15:8>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

STB<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 STB<15:0>: Secondary DMA RAM Start Address bits (source or destination)

Note 1: A read of this address register will return the current contents of the DMA RAM Address register, not the

contents written to STB<15:0>. If the channel is enabled (i.e., active), writes to this register may result in

unpredictable behavior of the DMA channel and should be avoided.

PIC24H

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PAD<15:8>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PAD<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 PAD<15:0>: Peripheral Address Register bits

Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the

DMA channel and should be avoided.

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — — CNT<9:8>(2)

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CNT<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-10 Unimplemented: Read as ‘0’

bit 9-0 CNT<9:0>: DMA Transfer Count Register bits (2)

Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the

DMA channel and should be avoided.

2: Number of DMA transfers = CNT<9:0> + 1.

PIC24H

R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0

PWCOL7 PWCOL6 PWCOL5 PWCOL4 PWCOL3 PWCOL2 PWCOL1 PWCOL0

bit 15 bit 8

R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0

XWCOL7 XWCOL6 XWCOL5 XWCOL4 XWCOL3 XWCOL2 XWCOL1 XWCOL0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 PWCOL7: Channel 7 Peripheral Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

bit 14 PWCOL6: Channel 6 Peripheral Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

bit 13 PWCOL5: Channel 5 Peripheral Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

bit 12 PWCOL4: Channel 4 Peripheral Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

bit 11 PWCOL3: Channel 3 Peripheral Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

bit 10 PWCOL2: Channel 2 Peripheral Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

bit 9 PWCOL1: Channel 1 Peripheral Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

bit 8 PWCOL0: Channel 0 Peripheral Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

bit 7 XWCOL7: Channel 7 DMA RAM Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

bit 6 XWCOL6: Channel 6 DMA RAM Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

bit 5 XWCOL5: Channel 5 DMA RAM Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

bit 4 XWCOL4: Channel 4 DMA RAM Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

PIC24H

bit 3 XWCOL3: Channel 3 DMA RAM Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

bit 2 XWCOL2: Channel 2 DMA RAM Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

bit 1 XWCOL1: Channel 1 DMA RAM Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

bit 0 XWCOL0: Channel 0 DMA RAM Write Collision Flag bit

1 = Write collision detected

0 = No write collision detected

PIC24H

U-0 U-0 U-0 U-0 R-1 R-1 R-1 R-1

— — — — LSTCH<3:0>

bit 15 bit 8

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-12 Unimplemented: Read as ‘0’

bit 11-8 LSTCH<3:0>: Last DMA Channel Active bits

1111 = No DMA transfer has occurred since system Reset

1110-1000 = Reser ved

0111 = Last data transfer was by DMA Channel 7

0110 = Last data transfer was by DMA Channel 6

0101 = Last data transfer was by DMA Channel 5

0100 = Last data transfer was by DMA Channel 4

0011 = Last data transfer was by DMA Channel 3

0010 = Last data transfer was by DMA Channel 2

0001 = Last data transfer was by DMA Channel 1

0000 = Last data transfer was by DMA Channel 0

bit 7 PPST7: Channel 7 Ping-Pong Mode Status Flag bit

1 = DMA7STB register selected

0 = DMA7STA register selected

bit 6 PPST6: Channel 6 Ping-Pong Mode Status Flag bit

1 = DMA6STB register selected

0 = DMA6STA register selected

bit 5 PPST5: Channel 5 Ping-Pong Mode Status Flag bit

1 = DMA5STB register selected

0 = DMA5STA register selected

bit 4 PPST4: Channel 4 Ping-Pong Mode Status Flag bit

1 = DMA4STB register selected

0 = DMA4STA register selected

bit 3 PPST3: Channel 3 Ping-Pong Mode Status Flag bit

1 = DMA3STB register selected

0 = DMA3STA register selected

bit 2 PPST2: Channel 2 Ping-Pong Mode Status Flag bit

1 = DMA2STB register selected

0 = DMA2STA register selected

bit 1 PPST1: Channel 1 Ping-Pong Mode Status Flag bit

1 = DMA1STB register selected

0 = DMA1STA register selected

bit 0 PPST0: Channel 0 Ping-Pong Mode Status Flag bit

1 = DMA0STB register selected

0 = DMA0STA register selected

PIC24H

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

DSADR<15:8>

bit 15 bit 8

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

DSADR<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 DSADR<15:0>: Most Recent DMA RAM Add ress A ccessed by DMA Controll er bits

PIC24H

NOTES:

PIC24H

8.0 OSCILLATOR

CONFIGURATION

The PIC24H oscillator system provides:

• Various external and internal oscillator options as

clock sources

• An on-chip PLL to scale the internal operating

frequency to the required system clock frequency

• The internal FRC oscillator can also be used with

the PLL, thereby allowing full-speed operation

without any external clock generation hardware

• Clock switching between various clock sources

• Programm abl e c loc k pos t s ca ler for syst em po w er

savings

• A Fail-Safe Clock Monitor (FSCM) that detects

clock failure and takes fail-safe meas ures

• A Clock Control register (OSCCON)

• Nonvolatile Configuration bits for main oscillator

selection.

A simplified diagram of the oscillator system is shown

in Figure 8-1.

FIGURE 8-1: PIC24H OSCILLATOR SYSTEM DIAGRAM

Note: This data sheet summarizes the features

of this group of PIC24H devices. It is not

intende d to be a comprehe nsive referenc e

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

PIC24H

PLL

Secondary Osc illa tor

SOSCEN

Enable

Oscillator

SOSCO

SOSCI

Clock Source Option

for other Modules

OSC1

OSC2

Primary Oscillator

XTPLL, HSPLL,

XT, HS, EC

CPU

Peripherals

/FRCDIIV

FRCDIV<2:0>

WDT, PWRT

FRC

Oscillator

LPRC

Oscillator

SOSC

LPRC

/DOZE

Clock Control Logic

Fail-Safe

Clock

Monitor

DOZE<2:0>

ECPLL, FRCPLL

Divide

by 16

, FRCDIVN

, FRCDIV16

PIC24H

8.1 CPU Clocking System

There are seven system clock options provided by the

PIC24H:

• FRC Oscillator

• FRC Oscillator with PLL

• Primary (XT, HS or EC) Oscillator

• Primary Oscillator with PLL

• Secondary (LP) Oscillator

• LPRC Oscillator

• FRC Osci lla tor wi th pos t s ca ler

8.1.1 SYSTEM CLOCK SOURCES

The FR C (Fast RC) i nternal os cillator runs at a n ominal

frequenc y of 7.37 MHz. T he user s oftware c an tune th e

FRC frequency. User software can optionally specify a

factor (ranging from 1:2 to 1:256) by which the FRC

clock frequency is divided. This fac tor is selec ted using

the FRCDIV<2:0> (CLKDIV<10:8>) bits.

The primary oscillator can use one of the following as

its clock source:

1. XT (Crys tal): Cr ystal s and cerami c resonato rs in

the range of 3 MHz to 10 MHz. The crystal is

connected to the OSC1 and OSC2 pins.

2. HS (High-Speed Crystal): Crystals in the range

of 10 MH z to 40 MHz. The crys tal is con nected

to the OSC1 and OSC2 pins.

3. EC (External Clock): External clock signal in the

range of 0.8 MHz to 64 MHz. T he extern al clock

signal is directly applied to the OSC1 pin.

The secondary (LP) oscillator is designed for low power

and uses a 32.768 kHz crystal or ceramic resonator.

The LP oscillator uses the SOSCI and SOSCO pins.

The LPRC (Low-Power RC) internal oscIllator runs at a

nominal frequency of 32.768 kHz. It is also used as a

reference clock by the Watchdog Timer (WDT) and

Fail-Safe Clock Monitor (FSCM).

The clock signals generated by the FRC and primary

oscillators can be optionally applied to an on-chip

Phase Locked Loop (PLL) to provide a wide range of

output frequencies for device operation. PLL

configuration is described in Section 8.1.3 “PLL

Configuration”.

8.1.2 SYSTEM CLOCK SELECTION

The oscillator source that is used at a device Power-on

Reset even t is sel ect ed us ing C onfig ura tion b it se tting s.

The oscillator Configuration bit settings are located in the

Conf iguratio n regis ters in the prog ram memo ry. (R efer to

Section 20.1 “Configuration Bits” for further details.)

The Initial Oscillator Selection Configuration bits,

FNOSC<2:0 > (FOSCSEL<2:0>), and the Primary Oscil-

lator Mode Select Configuration bits, POSCMD<1:0>

(FOSC<1:0>), select the oscillator source that is used at

a Power-on Reset. The FRC primary oscillator is the

default (unprogrammed) selection.

The Configuration bits allow users to choose between

twelve different clock modes, shown in Table 8-1.

The output of the oscillator (or the output of the PLL if

a PLL mod e has bee n select ed) FOSC is d ivided by 2 to

generate the device instruction clock (FCY). FCY

defines the opera ting spee d of the device, and speeds

up to 40 MHz are supported by the PIC24H

architecture.

Instruction execution speed or device operating

frequency, FCY, is given by:

EQUATION 8-1: DEVICE OPERATING

FREQUENCY

8.1.3 PLL CONFIGURATION

The primary oscillator and internal FRC oscillator can

optionally use an on-chip PLL to obta in higher speeds

of operation. The PLL provides a significant amount of

flexibility in selecting the device operating speed. A

block diagram of the PLL is shown in Figure 8-2.

The outp ut of the p rimary os cillator or FRC, den oted as

‘FIN’, is divided down by a prescale factor (N1) of 2, 3,

... or 33 before being provided to the PLL’s Voltage

Controlled Oscillator (VCO). The input to the VCO must

be selected to be in the range of 0.8 MHz to 8 MHz.

Since the minimum presc ale factor is 2, t his implies that

FIN must be chos en to be i n the range of 1.6 MHz to 1 6

MHz. The prescale factor ‘N1’ is selected using the

PLLPRE<4:0> bits (CLKDIV<4:0>).

The PLL Feedba ck Div iso r, select ed usin g the

PLLDI V<8:0> bit s (P LLFBD< 8:0>) , pro vid es a fact or ‘M’ ,

by which the input to the VCO is multiplied. This factor

must be selected such that the resulting VCO output

freq ue nc y is i n t he ra nge of 100 MH z to 2 00 M Hz.

The VCO o utput is furthe r divi ded by a pos ts cale f actor

‘N2’. This factor is selected using the PLLPOST<1:0>

bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4 or 8, and

must be selected such that the PLL output frequency

(FOSC) is in the range of 12.5 MHz to 80 MHz, which

generates device operating speeds of 6.25-40 MIPS.

For a primary oscillator or FRC oscillator, output ‘FIN’,

the PLL output ‘FOSC’ is given by:

EQUATION 8-2: FOSC CALCULATION

FCY = FOSC/2

( )

N1*N2

FOSC = FIN*

PIC24H

For example, suppose a 10 MHz crystal is being used,

with “XT with PLL” being the selected oscillator mode.

If PLLPRE<4:0> = 0, then N1 = 2. This yields a VCO

input of 10/2 = 5 MHz, which is within the acceptable

range of 0.8-8 MHz. If PLLDIV<8:0> = 0x1E, then

M = 32. Thi s yie ld s a VC O ou tput of 5 x 32 = 160 MHz,

which is within the 100-200 MHz ranged needed.

If PLLPOST<1:0> = 0, then N2 = 2. This provides a

Fosc of 160/2 = 80 MHz. The result ant device oper ating

speed is 80/2 = 40 MIPS.

EQUATION 8-3: XT WITH PLL MODE

EXAMPLE

FIGURE 8-2: PIC24H PLL BLOCK DIAGRAM

TABLE 8-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION

FCY = FOSC = 1 (10000000*32) = 40 MIPS

22*2

Oscillato r Mode Oscillator Source POSCMD<1:0> FNOSC<2:0> Note

Fast RC Oscillator with Divide-by-N

(FRCDIVN) Internal 11 111 1, 2

Fast RC Oscillator with Divide-by-1 6

(FRCDIV16) Internal 11 110 1

Low-Power RC Oscillator (LPRC) Internal 11 101 1

Secondary (Timer1) Oscillator (SOSC) Secondary 11 100 1

Primary Oscillator (HS) with PLL

(HSPLL) Primary 10 011

Primary Oscillator (XT) with PLL

(XTPLL) Primary 01 011

Primary Oscillator (EC) with PLL

(ECPLL) Primary 00 011 1

Primary Oscillator (HS) Primary 10 010

Primary Oscillator (XT) Primary 01 010

Primary Oscillator (EC) Primary 00 010 1

Fast RC Oscillator with PLL (FRCPLL) Internal 11 001 1

Fast RC Oscillator (FRC) Internal 11 000 1

Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit.

2: This is the default oscillator mode for an unprogrammed (erased) device.

0.8-8.0 MHz

Here 100-2 00 MHz

Here

Divide by

2, 4, 8

Divide by

2-513

Divi de by

2-33

1.6-16.0 MHz

Source (Crystal, External PLLPRE XVCO

PLLDIV

PLLPOST

Clock or Internal RC)

Here

FOSC

12.5-80 MHz

Here

PIC24H

U-0 R-0 R-0 R-0 U-0 R/W-y R/W-y R/W-y

—COSC<2:0>—NOSC<2:0>

bit 15 bit 8

R/W-0 U-0 R-0 U-0 R/C-0 U-0 R/W-0 R/W-0

CLKLOCK —LOCK—CF — LPOSCEN OSWEN

bit 7 bit 0

Legend: y = Value set from Configuration bits on POR

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 COSC<2:0>: Current Oscillator Selection bits (read-only)

000 = Fast RC oscillator (FRC)

001 = Fast RC oscillator (FRC) with PLL

010 = Primary oscillator (XT, HS, EC)

011 = Primary oscillator (XT, HS, EC) with PLL

100 = Secondary oscillator (SOSC)

101 = Low-Power RC oscillator (LPRC)

110 = Fast RC oscillator (FRC) with Divide-by-16

111 = Fast RC oscillator (FRC) with Divide-by-n

bit 11 Unimplemented: Read as ‘0’

bit 10-8 NOSC<2:0>: New Oscillator Selection bits

000 = Fast RC oscillator (FRC)

001 = Fast RC oscillator (FRC) with PLL

010 = Primary oscillator (XT, HS, EC)

011 = Primary oscillator (XT, HS, EC) with PLL

100 = Secondary oscillator (SOSC)

101 = Low-Power RC oscillator (LPRC)

110 = Fast RC oscillator (FRC) with Divide-by-16

111 = Fast RC oscillator (FRC) with Divide-by-n

bit 7 CLKLOCK: Clock Lock Enab le bit

1 = If (FCKSM1 = 1), then clock and PLL configurations are locked.

If (FCKSM1 = 0), then clock and PLL configurations may be modified.

0 = Clock and PLL selections are not locked, configurations may be modified

bit 6 Unimplemented: Read as ‘0’

bit 5 LOCK: PLL Lock Status bit (read-o nly)

1 = Indicates that PLL is in lock, or PLL start-up timer is satisfied

0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled

bit 4 Unimplemented: Read as ‘0’

bit 3 CF: Clock Fail Detect bit (read/clear by application)

1 = FSCM has detected clock failure

0 = FSCM has not detected clock failure

bit 2 Unimplemented: Read as ‘0’

bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit

1 = Enable secondary oscillator

0 = Disable secondary oscillator

bit 0 OSWEN: Oscillator Switch Enable bit

1 = Request oscillator switch to selection specified by NOSC<2:0> bits

0 = Oscillator switch is complete

PIC24H

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0

ROI DOZE<2:0> DOZEN(1) FRCDIV<2:0>

bit 15 bit 8

R/W-0 R/W-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PLLPOST<1:0> — PLLPRE<4:0>

bit 7 bit 0

Legend: y = Value set from Configuration bits on POR

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ROI: Recover on Interrupt bit

1 = Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1

0 = Interrupts have no effect on the DOZEN bit

bit 14-12 DOZE<2:0>: Processor Clock Reduction Se lect bits

000 = FCY/1 (d efault)

001 = FCY/2

010 = FCY/4

011 = FCY/8

100 = FCY/16

101 = FCY/32

110 = FCY/64

111 = FCY/128

bit 11 DOZEN: DOZE Mode Enab le bit(1)

1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks

0 = Processor clock/peripheral clock ratio forced to 1:1

bit 10-8 FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits

000 = FRC divide by 1

001 = FRC divide by 2

010 = FRC divide by 4

011 = FRC divide by 8 (default)

100 = FRC divide by 16

101 = FRC divide by 32

110 = FRC divide by 64

111 = FRC divide by 256

bit 7-6 PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler)

00 = Output/2

01 = Output/4

10 = Reserved (defaults to output/4)

11 = Output/8

bit 5 Unimplemented: Read as ‘0’

bit 4-0 PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler)

00000 = Input/2

00001 = Input/3

• • •

11111 = Input/33

Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs.

PIC24H

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — —PLLDIV<8>

bit 15 bit 8

R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0

PLLDIV<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-9 Unimplemented: Read as ‘0’

bit 8-0 PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier)

000000000 = 2

000000001 = 3

000000010 = 4

•

111111111 = 513

PIC24H

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— TUN5 TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-6 Unimplemented: Read as ‘0’

bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits

011111 = Center frequency + 11.625% (8.23 MHz)

011110 = Center frequency + 11.25% (8.20 MHz)

•

000001 = Center frequency + 0.375% (7.40 MHz)

000000 = Center frequency (7.37 MHz nominal)

111111 = Center frequency – 0.375% (7.345 MHz)

•

100001 = Center frequency – 11.625% (6.52 MHz)

100000 = Center frequency – 12% (6.49 MHz)

PIC24H

8.2 Clock Switching Opera ti o n

Applications are free to switch between any of the four

clock sources (Primary, LP, FRC and LPRC) under

software control at any time. To limit the possible side

effects that could result from this flexibility, PIC24H

devices have a safeguard lock built into the switch

process.

8.2.1 ENABLING CLOCK SWITCHING

To enable clock switching, the FCKSM1 Configuration

bit in the Configurati on register must be programmed to

‘0’. (Refer to Section 20.1 “Configuration Bits” for

further details.) If the FCKSM1 Configuration bit is

unprogrammed (‘1’), the clock switching function and

Fail-Safe Clock Monitor function are disabled. This is

the default setting.

The NOSC control bits (OSCCON<10:8>) do not

control the clock selection when clock switching is

disabled. However , the COSC bit s (OSCCON<14:12>)

reflect the clock source selected by the FNOSC

Configuration bits.

The OSWEN control bit (OSCCON<0>) has no effect

when clock switching is disabled. It is held at ‘0’ at all

times.

8.2.2 OSCILLATOR SWITCHING

SEQUENCE

At a minimum, performing a clock switch requires this

basi c se que nce:

1. If desired, read the COSC bits

(OSCCON<14:12>) to determine the current

osci llator source.

2. Perform the unlock sequence to allow a write to

the OSCCON register high byte.

3. Write the ap propria te val ue to th e NOSC co ntrol

bits (OSCCON<10:8>) for the new oscillator

source.

4. Perform the unlock sequence to allow a write to

the OSCCON register low byte.

5. Set the OSWEN bit to initiate the oscillator

switch.

Once the basic sequence is completed, the system

clock hardware responds automatically as follows:

1. The clock switching hardware compares the

COSC status bits with the new value of the

NOSC c ontrol bit s. If they ar e the sa me, then th e

clock switch is a redundant operation. In this

case, the OSWEN bit is cleared automatically

and the clock switch is aborted.

2. If a valid clock switch has been initiated, the

LOCK (OSCCON<5>) and the CF

(OSCCON< 3>) st a tus bit s are cl eare d.

3. The new oscillator is turned on by the hardware

if it is not currently running. If a crystal oscillator

must be turned on, the hardware waits until the

Oscillator Start-up Timer (OST) expires. If the

new so urce is using th e PLL, the hardw are waits

until a PLL lock is detected (LOCK = 1).

4. The hardware w aits for 10 clock cycle s fro m the

new clock source and then performs the clock

switch.

5. The ha rdware cle ars the OSWEN bit t o ind ica te a

successful clock transition. In addition, the NOSC

bit valu es are transf erred to the COSC st atus bit s.

6. The old clock source is turned off at this time,

with the exception of LPRC (if WDT or FSCM

are enabled) or LP (if LPOSCEN remains set).

8.3 Fail-Safe Clock Monitor (FSCM)

The Fail-Saf e Cl oc k Mo nito r (FSCM) all ow s the devic e

to conti nue to o pe rate eve n in th e even t of an oscil lator

failure. The FSCM function is enabled by programming.

If the FSCM function is enabled, the LPRC internal

oscillator runs at all times (except during Sleep mode)

and is not subject to control by the Watchdog Timer.

If an oscillator failure occurs, the FSCM generates a

clock failure trap event and switches the system clock

over to the FRC oscillator. Then the application

program can either attempt to restart the oscillator or

execute a controlled shutdown. T he trap can be tre ated

as a warm Reset by simply loading the Reset address

into the oscillator fail trap vector.

If the PLL multiplier is used to scale the system clock,

the internal FRC is also multiplied by the same factor

on clock failure. Essentially, the device switches to

FRC with PLL on a clock failure.

Note: Primary Oscillator mode has three different

submodes (XT, HS and EC) which are

determined by the POSCMD<1:0> Config-

uration bits. While an application can

switch to and from Primary Oscillator

mode in software, it cannot switch

between the different primary submodes

withou t reprog ram ming the dev ic e.

Note 1: The proc esso r con tinues to e xecute c ode

througho ut the cloc k swit ching se quence.

Timing sensitive code should not be

executed during this time.

2: Direct clock switches between any primary

oscillator mode with PLL and FRCPLL

mode are not permitted. This applies to

clock switches in either direction. In these

instances, the application must switch to

FRC mode as a transition clock source

between the two PLL modes.

PIC24H

9.0 POWER-SAVING FEATURES

The PIC24H devices provide the ability to manage

power consumption by selectively managing clocking

to the CPU and the peripherals. In general, a lower

clock frequency and a reduction in the number of cir-

cuit s being c locked constitu tes lower c onsumed power.

PIC24H devices can manage power consumption in

four different ways:

• Clock frequency

• Instructi on-based Sleep and Idle modes

• Software-controlled Doze mode

• Selective peripheral control in software

Combinations of these methods can be used to selec-

tively tailor an application’s power consumption while

still maintaining critical application features, such as

timing-sensitive communications.

9.1 Clock Frequency and Clock

Switching

PIC24H devices allow a wide range of clock frequen-

cies to be selected under application control. If the

system clock configuration is not locked, users can

choose low-power or high-precision oscillators by

simply changing the NOSC bits (OSCCON<10:8>).

The process of changing a system clock during

operation, as well as limitations to the process, are

discussed in more detail in Section 8.0 “Oscillator

Configuration”.

9.2 Instruction-Based Power-Saving

Modes

PIC24H de vices have two specia l power-savin g modes

that are entered through the execution of a special

PWRSAV instruction. Sleep mode stops clock operation

and halts all code execution. Idle mode halts the CPU

and code execution, but allows peripheral modules to

continue operation. The assembly syntax of the

PWRSAV instruction is shown in Example 9-1.

Sleep and Idle modes can be exited as a result of an

enabled interrupt, WDT time-out or a device Reset. When

the device exits these modes, it is said to “wake-up”.

9.2.1 SLEEP MODE

Sleep mode has these features:

• The system clock source is shut d own. If an

on-chip oscillator is used, it is turned off.

• The device current consumption is reduced to a

minimum, provided that no I/O pin is sourcing

current.

• The Fail-Safe Clock Monitor does not operate

during Sleep mode since the system clock source

is disabled.

• The LPRC clo ck continues to run in Sleep mode if

the WDT is enabled.

• The WDT, if enabled, is automatically cleared

prior to entering Sleep mode.

• Some device featu res or p eripherals may continue

to operate in Sleep mode. This includes items such

as the input change notification on the I/O ports, or

peripherals that use an external clock input. Any

peripheral that requires the system clock source for

its operation is dis abled in Slee p mode.

The dev ice will wake-u p from Slee p mode on any o f the

these events:

• Any interrupt source that is individually enabled.

• Any form of device Reset.

• A WDT time-out.

On wake-u p from Sleep, the p rocessor resta rts with th e

same clock source that was active when Sleep mode

was entered.

EXAMP LE 9- 1: PWRSAV INSTRUCTION SYNTAX

Note: This data sheet summarizes the features

of this group of PIC24H devices. It is not

intende d to be a comprehe nsive referenc e

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

Note: SLEEP_MODE and IDLE_MODE are

constants defined in the assembler

include file for the selected device.

PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode

PWRSAV #IDLE_MODE ; Put the device into IDLE mode

PIC24H

9.2.2 IDLE MODE

Idle mode has these feat ure s:

• The CPU stops executing instructions.

• The WDT is automatically cleared.

• The system clock source r emains active. By

default, all peripheral modules continue to operate

normally from the system clock source, but can

also be selectively disabled (see Section 9.4

“Peripheral Mod ule Disable”).

• If the WDT or FSCM is enabled, the LPRC also

remains active.

The device will wake from Idle mode on any of these

events:

• Any interrupt that is individually enabled.

• Any device Reset.

• A WDT time-out.

On wake-up from Idle, the clock is reapplied to the CPU

and instruction execution begins immediately, starting

with the ins truction follo wing the PWRSAV inst ruction , or

the first instruction in the ISR.

9.2.3 INTERRUPTS COINCIDENT WITH

POWER SAVE INSTRUCTIONS

Any interrupt that coincides with the execution of a

PWRSAV instruction is held off until entry into Sleep or

Idle mode has completed. The device then wakes up

from Sleep or Idle mode.

9.3 Doze Mode

Generally , changing clock speed and invoking one of the

power-saving modes are the preferred strategies for

reducing power consumption. There may be cir-

cumstances, however, where this is not practical. For

example, it m ay be necessary for an application to main-

tain uninterrupted synchronous communication, even

while it is doing nothing else. Reducing system clock

speed may in troduce commu nication errors, while using

a power-saving mode may stop communications

completely.

Doze mode is a simple an d effective alternat ive method

to reduce power consumption while the device is still

executing code. In this mode, the system clock contin-

ues to operate from the same source and at the same

speed. Peripheral modules continue to be clocked at

the same speed, while the CPU clock speed is

reduced. Synchronization between the two clock

domains is maintained, allowing the peripherals to

access the SFRs while the CPU executes code at a

slower rate.

Doze mode is enabled by setting the DOZEN bit

(CLKDIV<11>). The ratio between peripheral and core

clock speed is determined by the DOZE<2:0> bits

(CLKDIV<14:12>). There are eight possible

configurations, from 1:1 to 1:128, with 1:1 being the

default set ting.

It is also possible to use Doze mode to selectively

reduce power consumption in event-driven applica-

tions. This allows clock-sensitive functions, such as

synchronous communications, to continue without

interruption while the CPU idles, waiting for something

to invoke an interrupt routine. Enabling the automatic

return to full-speed CPU operation on interrupts is

enabled by setting the ROI bit (CLKDIV<15>). By

default, interrupt events have no effect on Doze mode

operation.

For example, suppose the device is operating at

20 MIPS and the CAN modu le has bee n config ured f or

500 kbps based on this device operating speed. If the

device is now placed in Doze mode with a clock

frequency ratio of 1:4, the CAN module continues to

communicate at the required bit rate of 500 kbps, but

the CPU now starts executing instructions at a

frequency of 5 MIPS.

9.4 Peripheral Module Disable

The Peripheral Module Disable (PMD) registers

provide a method to disable a peripheral module by

stopping all clock sources supplied to that module.

When a pe riphera l is di sable d via t he appro priate P MD

control bit, the peripheral is in a minimum power

consumption state. The control and status registers

associated with the peripheral are also disabled, so

writes to those registers will have no effect and read

values will be invalid.

A peripheral module is only enabled if bot h the associ-

ated bit in the PMD register is cleared and th e peripheral

is supported by the specific dsPIC® DSC variant. If the

peripheral is present in the device, it is enabled in the

PMD r egister by default.

Note: If a PMD bit is set, the corresponding mod-

ule is di sabled after a delay of 1 ins truction

cycle . Simi larly, if a PMD bit i s cl eared, the

corresponding module is enabled after a

delay of 1 instruction cycle (assuming the

module control registers are already

configu r ed to enab le mo dul e opera t io n).

PIC24H

10.0 I/O PORTS

All of the device pins (except VDD, VSS, MCLR and

OSC1/CL KIN) are shared bet ween the pe ripherals an d

the para llel I/O ports. All I/O input port s feat ure Schmitt

Trigger inputs for improved noise immunity.

10.1 Pa ra l le l I/O (PI O ) P o rts

A para llel I/ O port tha t share s a pi n with a periph eral is ,

in general, subservient to the peripheral. The periph-

eral’s output buffer data and control signals are

provided to a pair of multiplexers. The multiplexers

select whether the peripheral or the associated port

has ow nershi p of the outp ut dat a and c ontrol sign als of

the I/O pin. The logic also prevents “loop through”, in

which a port’s digital output can drive the input of a

peripheral that shares the same pin. Figure 10-1 shows

how ports are shared with other peripherals and the

associated I/O pin to which they are connected.

When a peripheral is enabled and actively driving an

assoc iated p in, the use of the pin as a g eneral purpos e

output p in is disa bled. T he I/O pin m ay b e read, but th e

output driver for the parallel port bit will be disabled. If

a peripheral is enabled, but the peripheral is not

actively driving a pin, that pin may be driven by a port.

All port pins have three registers directly associated

with their operation as digital I/O. The data direction

or an output . If the data directi on bit is a ‘1’, then the pin

is an input. All port pins are defined as inputs after a

Reset. Reads from the latch (LATx), read the latch.

Wr ite s to the la tch , writ e th e lat ch . Reads from the po rt

(PORTx), read the port pins, while writes to the port

pins, write the latch.

Any bit and its associated data and control registers

that are not valid for a particular device will be

disabled. That means the corresponding LATx and

TRISx registers and the port pins will read as zeros.

When a pin is shared with another peripheral or func-

tion that is defined as an input only, it is nevertheless

regarded as a dedicated port because there is no

other competing source of outputs. An example is the

INT4 pin.

FIGURE 10-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE

Note: This data sheet summarizes the features

of this group of PIC24H devices. It is not

intende d to be a comprehe nsive referenc e

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

Note: The voltage on a digital input pin can be

between -0.3V to 5.6V.

WR LAT +

TRIS Latch

I/O Pin

WR PORT

Data Bus

Data Latch

Read Port

Read TRIS

WR TRIS

Periphe ral Outp ut Data Output Enable

Periphe ral Inp ut Data

I/O

Peripheral Module

Periphe ral Outp ut Enab le

PIO Module

Output Multiplexers

Output Data

Input Data

Periphe ral Mod ule Enable

Read LA T

PIC24H

10.2 Open-Drain Configuration

In addition to the PORT, LAT and TRIS registers for

data control, each port pin can also be individually

configu red for eithe r digital or open-drai n output . This is

controlled by the Open-Drain Control register, ODCx,

associated with each port. Setting any of the bits con-

figures the corresponding pin to act as an open-drain

output.

The open-drain feature allows the generation of

outputs higher than VDD (e.g., 5V) on any desired digi-

tal only pins by using external pull-up resistors. (The

open-drain I/O feature is not supported on pins that

have analog functionality multiplexed on the pin.) The

maximum open-drain voltage allowed is the same as

the maximum VIH specification. The open-drain output

feature is supported for both port pin and peripheral

configurations.

10.3 Configuring Anal og Port Pins

The use of the ADxPCFGH, ADxPCFGL and TRIS

port pins that are desired as analog inputs must have

their corresponding TRIS bit set (input). If the TRIS bit

is clear ed (output), the digi tal outp ut le ve l (VOH or VOL)

is converted.

Clearing any bit in the ADxPCFGH or ADxPCFGL reg-

ister configures the corresponding bit to be an analog

pin. This is also the Reset state of any I/O pin that has

an analog (ANx) function associated with it.

When read ing the POR T register, all pins confi gured as

analog in put channels will rea d as cleared (a low le vel).

Pins configured as digital inputs will not convert an

analog i nput. Analog leve ls on any pin that is defined as

a digital input (including the ANx pins) can cause the

input buffer to consume current that exceeds the

device specifications.

10.4 I/O Port W rite/Read Timing

One instruction cycle is required between a port

direction change or port write operation and a read

operation of the same port. Typically, this instruction

would be a NOP.

10.5 Input Change Notifi cation

The input change notification function of the I/O ports

allows the PIC24H devices to generate interrupt

requests to the processor in response to a

change-of-state on selected input pins. This feature is

capable of detecting input change-of-states even in

Sleep mode, w hen the cl oc ks are disa ble d. D e pen ding

on the de vice p in count, there are up to 24 exte rnal sig-

nals (CN0 through CN23) that can be selected

(enabled) for generating an interrupt request on a

change-of-state.

There are f our con trol regi ster s assoc iated wi th the C N

module . The C NEN1 and CN EN2 reg is ters co ntain the

CN interr upt ena ble (C NxIE) co ntrol b its for eac h of th e

CN input pins. Setting any of these bits enables a CN

interrupt for the corresponding pins.

Each CN pin also has a weak pull-up connected to it.

The pull-ups act as a current source that is connected

to the pin and eliminate the need for external resistors

when push button or keypad devices are connected.

The pull-ups are enabled separately using the CNPU1

and CNPU2 registers, which contain the weak pull-up

enable (CNxPUE) bits for each of the CN pins. Setting

any of th e control bits e nables th e weak pul l-ups f or the

corresp onding pi ns.

EXAMPLE 10-1: PORT WRITE/READ EXAMPLE

Note: In devices with two A/D modules, if the

corresponding PCFG bit in either

AD1PCFGH(L) and AD2PCFGH(L) is

cleared , the pin is conf igured as an analo g

input.

Note: The v ol t age on an analog input pin can be

between -0.3V to (VDD + 0.3 V).

Note: Pull-ups on change notification pins

should always be disabled whenever the

port pin is configured as a digital output.

MOV 0xFF00, W0 ; Configure PORTB<15:8> as inputs

MOV W0, TRISBB ; and PORTB<7:0> as outputs

NOP ; Delay 1 cycle

btss PORTB, #13 ; Next Instruction

PIC24H

11.0 TIMER1

The Timer1 module is a 16-bit timer, which can serve

as the time counter for the real-time clock, or operate

as a free-running interval timer/counter. Timer1 can

operate in three modes:

• 16-bit Timer

• 16-bit Synchronous Counter

• 16-bit Asynchronous Counter

Timer1 also supports these features:

• Timer gate operation

• Selectable prescaler set tings

• Timer operation during CPU Idle and Sleep

modes

• Interrupt on 16-bit Period register match or falling

edge of external gate signal

Figure 11-1 presents a block diagram of the 16-bit

timer module.

To configure Timer1 for operation:

1. Set the TON bit (= 1) in the T1CON register.

2. Select the timer prescaler ratio using the

TCKPS<1:0> bits in the T1CON register.

3. Set the Clock and Gati ng modes using the TCS

and TGATE bits in the T1CON register.

4. Set or clear the TSYNC bit in T1CON to select

synchronous or asynchronous operation.

5. Load the timer period value into the PR1

6. If interrupts are required, set the interrupt enabl e

bit, T1IE. Use the priority bits, T1IP<2:0>, to set

the interrupt priority.

FIGURE 11-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM

Note: This data sheet summarizes the features

of this group of PIC24H devices. It is not

intende d to be a comprehe nsive referenc e

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

TON

SOSCI

SOSCO/

PR1

Set T1IF

Equal Comparator

TMR1

Reset

SOSCEN

TSYNC

TCKPS<1:0>

Prescaler

1, 8, 64, 256

TGATE

TCY

T1CK

TCS

TGATE

Sync

Gate

Sync

PIC24H

R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

TON —TSIDL— — — — —

bit 15 bit 8

U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0

— TGATE TCKPS<1:0> — TSYNC TCS —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 TON: Timer1 On bit

1 = Starts 16-bit Timer1

0 = Stops 16-bit Timer1

bit 14 Unimplemented: Read as ‘0’

bit 13 TSIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

bit 12-7 Unimplemented: Read as ‘0’

bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit

When T1CS = 1:

This bit is ignored.

When T1CS = 0:

1 = Gated time accumulation enabled

0 = Gated time accumulation disabled

bit 5-4 TCKPS<1:0>: Timer1 Input Clock Prescale Select bits

11 = 1:256

10 = 1:64

01 = 1:8

00 = 1 :1

bit 3 Unimplemented: Read as ‘0’

bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit

When TCS = 1:

1 = Synchronize external clock input

0 = Do not synchronize external clock input

When TCS = 0:

This bit is ignored.

bit 1 TCS: Timer1 Clock Sour ce Se lect bit

1 = External clock from pin T1CK (on the ris ing edge)

0 = Internal clock (FCY)

bit 0 Unimplemented: Read as ‘0’

PIC24H

12.0 T IMER2/ 3, T I MER4/5, TIMER6/7

AND TIMER8/9

The Timer2/3, Timer4/5, Timer6/7 and Timer8/9

modules are 32-bit timers, which can also be config-

ured as four independent 16-bit timers with selectable

operating modes.

As a 32-bit timer, Timer2/3, Timer4/5, Timer6/7 and

Timer8/9 operate in three modes:

• Two Independent 16-bit Timers (e.g., Timer2 and

Timer3) wit h all 16-bit op erat ing modes (except

Asynchronous Counter mode)

• Single 32-bit Timer

• Single 32-bit Synchronous Counter

They also support these features:

• Timer Gate Operation

• Selectable Prescaler Settings

• Timer Operation during Idle and Sleep modes

• Interrupt on a 32-bit Period Register Match

• T ime Ba se for I nput Capture an d Ou tput Comp are

Modules (Timer2 and Timer3 only)

• ADC1 Event Trigger (Timer2/3 only)

• ADC2 Event Trigger (Timer4/5 only)

Individ ually , al l eight of the 16-bit timers can funct ion as

synchronous timers or counters. They also offer the

features listed above, except for the event trigger; this

is implemented only with Timer2/3. The operating

modes and enabled featur es are determin ed by settin g

the appropriate bit(s) in the T2CON, T3CON, T4CON,

T5CON, T6CON, T7CON, T8CON and T9CON regis-

ters. T2CON, T4CON, T6CON and T8CON are shown

in generic form in Register 12-1. T3CON, T5CON,

T7CON and T9CON are shown in Register 12-2.

For 32-bit timer/counter operation, Timer2, Timer4,

Timer6 or Timer8 is the least significant word; Timer3,

Timer5, Timer7 or Timer9 is the most significant word

of the 32-bit timers.

To configure Timer2/3, Timer4/5, Timer6/7 or Timer8/9

for 32-bit operation:

1. Set the corresponding T32 control bit.

2. Select the prescaler ratio for Timer2, Timer4,

Timer6 or Timer8 using the TCKPS<1:0> bits.

3. Set the Clock and Gating modes using the

corresponding TCS and TGATE bits.

4. Load the timer period value. PR3, PR5, PR7 or

PR9 contains the most significant word of the

value, while PR2, PR4, PR6 or PR8 con tains the

least significant word.

5. If interrupts are required, set the interrupt enabl e

bit, T3IE, T5IE, T7IE or T9IE. Use the priority

bits, T3IP<2:0>, T5IP<2:0>, T7IP<2:0> or

T9IP<2:0>, to set the interrupt priority. While

Timer2, Timer4, Timer6 or Timer8 control the

timer, the interrupt ap pears as a T imer3, T imer 5,

Timer 7 or Timer9 interrupt.

6. Set the corresponding TON bit.

The timer value at any point is stored in the register

pair, TMR3:TMR2, TMR5:TMR4, TMR7:TMR6 or

TMR9:TMR8. TMR3, TMR5, TMR7 or TMR9 always

contains the most significant word of the count, while

TMR2, TMR4, TMR6 or TMR8 contains the least

signific ant word.

To configure any of the timers for individual 16-bit

operation:

1. Clear the T32 bit corresponding to that timer.

2. Select the timer prescaler ratio using the

TCKPS<1:0> bits.

3. Set the Clock and Gati ng modes using the TCS

and TGATE bits.

4. Load the timer period value into the PRx

5. If interrupts are required, set the interrupt enabl e

bit, TxIE. Use the priority bits, TxIP<2:0>, to set

the interrupt priority.

6. Set the TON bit.

A block diagram for a 32-bit timer pair (Timer4/5)

example is shown in Figure 12-1 and a timer (Timer4)

operating in 16-bit mode example is shown in

Figure 12-2.

Note: This data sheet summarizes the features

of this group of PIC24H devices. It is not

intende d to be a comprehe nsive referenc e

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

Note: For 32-bit operation, T3CON, T5CON,

T7CON and T9CON control bits are

ignored. Only T2CON, T4CON, T6CON

and T8C ON contro l bits are used for s etup

and control. Timer2, Timer4, Timer6 and

Timer8 clock and gate inputs are utilized

for the 32-bit timer modules, but an inter-

rupt is generated with the Timer3, Timer5,

Ttimer7 and Timer9 interrupt flags.

Note: Only Timer2 and Timer3 can trigger a

DMA data transfer.

PIC24H

FIGURE 12-1: TIMER2/3 (32-BIT) BLOCK DIAGRAM(1)

Set T3IF

Equal Comparator

PR3 PR2

Reset

LSBMSB

Note 1: The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective

to the T2CON register.

2: The ADC event trigger is available only on Timer2/3.

Data Bus<15:0>

TMR3HLD

Read TMR2

Wr i te TMR2 16

TGATE

TON TCKPS<1:0>

TCY

TCS

TGATE

T2CK

ADC Event Trigger(2)

Gate

Sync Prescaler

1, 8, 64, 256

Sync

TMR3 TMR2

PIC24H

FIGURE 12-2: TIMER2 (16-BIT) BLOCK DIAGRAM

TON TCKPS<1:0>

Prescaler

1, 8, 64, 256

TCY TCS

TGATE

T2CK

PR2

Set T2IF

Equal Comparator

TMR2

Reset

TGATE

Gate

Sync

PIC24H

R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

TON —TSIDL— — — — —

bit 15 bit 8

U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0

— TGATE TCKPS<1:0> T32(1) —TCS—

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 TON: Timerx On bit

When T32 = 1:

1 = Starts 32-bit Timerx/y

0 = Stops 32-bit Timerx/y

When T32 = 0:

1 = Starts 16-bit Timerx

0 = Stops 16-bit Timerx

bit 14 Unimplemented: Read as ‘0’

bit 13 TSIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

bit 12-7 Unimplemented: Read as ‘0’

bit 6 TGATE: Timerx Gated Time Accumulation Enable bit

When TCS = 1:

This bit is ignored.

When TCS = 0:

1 = Gated time accumulation enabled

0 = Gated time accumulation disabled

bit 5-4 TCKPS<1:0>: Timerx Input Clock Prescale Select bits

11 = 1:256

10 = 1:64

01 = 1:8

00 = 1:1

bit 3 T32: 32-bit Timer Mode Select bit(1)

1 = Timerx and Timery form a single 32-bit timer

0 = Timerx and Timery act as two 16-bit timers

bit 2 Unimplemented: Read as ‘0’

bit 1 TCS: Timerx Clock Source Se lect bit

1 = External clock from pin TxCK (on the rising edge)

0 = Internal clock (FCY)

bit 0 Unimplemented: Read as ‘0’

Note 1: In 32-bit mode, T3CON control bits do not affect 32-bit timer operation.

PIC24H

R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

TON(1) —TSIDL

(1) — — — — —

bit 15 bit 8

U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0

—TGATE

(1) TCKPS<1:0>(1) ——TCS

(1) —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 TON: Timery On bit(1)

1 = Starts 16-bit Timery

0 = Stops 16-bit Timery

bit 14 Unimplemented: Read as ‘0’

bit 13 TSIDL: Stop in Idle Mode bit(1)

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

bit 12-7 Unimplemented: Read as ‘0’

bit 6 TGATE: Timery Gated Time Accumulation Enable bit(1)

When TCS = 1:

This bit is ignored.

When TCS = 0:

1 = Gated time accumulation enabled

0 = Gated time accumulation disabled

bit 5-4 TCKPS<1:0>: Timer3 Input Clock Prescale Select bits(1)

11 = 1:256

10 = 1:64

01 = 1:8

00 = 1:1

bit 3-2 Unimplemented: Read as ‘0’

bit 1 TCS: Timery Clock Source Se lect bit(1)

1 = External clock from pin TyCK (on the rising edge)

0 = Internal clock (FCY)

bit 0 Unimplemented: Read as ‘0’

Note 1: When 32-b it operatio n is enabl ed (T2CON<3> = 1), these bit s h ave no ef fect on T i mery opera tion; a ll timer

functio ns are set through T2CON.

PIC24H

NOTES:

PIC24H

13.0 INPUT CAPTURE

The input capture module is useful in applications

requiring frequency (period) and pulse measurement.

The PIC24H devices support up to eight input capture

channels.

The input capture module captures the 16-bit value of

the selected Time Base register when an event occurs

at th e ICx pi n. The events th at cause a captu re event

are listed below in three categories:

1. Simple Capture Event modes

-Capture timer value on every falling edge of

input at ICx pin

-Capture timer value on every rising edge of

input at ICx pin

2. Capture timer value on every edge (rising and

falling)

3. Prescale r Captur e Event mo des

-Captur e timer v alue on every 4 th risin g edge

of input at ICx pin

-Capture timer value on every 16th rising

edge of input at ICx pin

Each input capture channel can select between one of

two 16-bit timers (Timer2 or Ti mer3) for the time base.

The selected timer can use either an internal or

external clock.

Other operational features include:

• Device wake-up from capture pin during CPU

Sleep and Idle modes

• Interrupt on input capture event

• 4-word FIFO buffer for capture values

- Interrupt optionally generated after 1, 2, 3 or

4 buf fer locations are fill ed

• Input capture can also be used to provide

additional sources of external interrupts

FIGURE 13-1: INPUT CAPTURE BLOCK DIAGRAM

Note: This data sheet summarizes the features

of this group of PIC24H devices. It is not

intende d to be a comprehe nsive referenc e

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

Note: Only IC1 and IC2 can trigger a DMA data

transfer. If DMA data transfers are

required, the FIFO buffer size must be set

to 1 (ICI<1:0> = 00).

ICxBUF

ICx Pin ICM<2:0> (ICxCON<2:0>)

Mode Select

Set Flag ICxIF

(in IFSn Register)

TMRy TMRz

Edge Detection Logic

16 16

FIFO

R/W

Logic

ICxI<1:0>

ICOV, ICBNE (ICxCON<4: 3>)

ICxCON Interrupt

Logic

System Bus

From 16-bit Timers

ICTMR

(ICxCON<7>)

FIFO

Prescaler

Counter

(1, 4, 16) and

Clock Synchronizer

Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.

PIC24H

13.1 Input Capture Registers

U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

——ICSIDL— — — — —

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R-0, HC R-0, HC R/W-0 R/W-0 R/W-0

ICTMR(1) ICI<1:0> ICOV ICBNE ICM<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13 ICSIDL: Input Capture Module Stop in Idle Control bit

1 = Input capture module will halt in CPU Idle mode

0 = Input capture module will continue to operate in CPU Idle mode

bit 12-8 Unimplemented: Read as ‘0’

bit 7 ICTMR: Input Capture Timer Select bit s(1)

1 = TMR2 contents are captured on capture event

0 = TMR3 contents are captured on capture event

bit 6-5 ICI<1:0>: Select Number of Captures per Interrupt bits

11 = Interrupt on every fourth capture event

10 = Interrupt on ever y third capt ure event

01 = Interrupt on every second capture event

00 = Interrupt on every capture event

bit 4 ICOV: Input Capture Overflow Status Flag bit (read-only)

1 = Input capture overflow occurred

0 = No input capture overflow occurred

bit 3 ICBNE: Input Capture B uffer Empty Status bit (read-only)

1 = Input capture buffer is not empty, at least one more capture value can be read

0 = Input capture buffer is empty

bit 2-0 ICM<2:0>: Input Capture Mode Select bits

111 =Input capture functions as interrupt pin only when device is in Sleep or Idle mode

(Rising edge detect only, all other control bits are not applicable.)

110 =Unused (module disabled)

101 =Capture mode, every 16th rising edge

100 =Capture mode, every 4th rising edge

011 =Capture mode, every rising edge

010 =Capture mode, every falling edge

001 =Capture mode, every edge (rising and falling)

(ICI<1:0> bits do not control interrupt generation for this mode.)

000 =Input capture module turned off

Note 1: Timer selections may vary. Refer to the device data sheet for details.

PIC24H

14.0 OUTPUT COMP ARE

14.1 Setup for Single Output Pulse

Generation

When the O C M co ntro l b it s (O Cx C ON<2 :0> ) are s et to

‘100’, the selected output compare channel initializes

the OCx pin to the low state and generates a single

output pulse.

To generate a single output pulse, the following steps

are required (these steps assume timer source is

initially turned off but this is not a requirement for the

module operation):

1. Determine the instruction clock cycle time. Take

into ac co u nt t h e fr eq ue n cy of t h e ex t ern al c lo ck

to the timer source (i f one is us ed) a nd the timer

prescaler settings.

2. Calculate time to the rising edge of the output

pulse re la ti ve to th e TM Ry start v al ue (0 00 0h ).

3. Calculate the time to the falling edge of the pulse

based on t he des ire d pu ls e w idth an d th e t ime to

the rising ed ge of the pulse.

4. Write the values computed in steps 2 and 3 above

into the Ou tpu t Compare register, OCxR, an d th e

Output Compare Secondary register, OCxRS,

respectively.

5. Set Timer Pe riod reg iste r, PR y, to v alue eq ual to

or greater than value in OCxRS, the Output

Compare Secondary register .

6. Set the OCM bits to ‘100’ and the OCTSEL

(OCxCON<3>) bit to the desired timer source.

The OC x pi n s tate will no w b e driven low.

7. Set the TON (TyCON<15>) bit to ‘1’, which

enabl es th e com p a r e tim e ba s e t o c o unt .

8. Upon the first match between TMRy and OCxR,

the OC x pin will be drive n high .

9. When the incrementing timer, TMRy, matches

the Output Compare Secondary register,

OCxRS, the second and trailing edge (high-to-

low) of t h e p uls e i s dr i ve n ont o t h e OCx pi n. No

additional pulses are driven onto the OCx pin

and it remains at low. As a result of the second

compare match event, the OCxIF interrupt flag

bit is set, which will result in an interrupt if it is

enabled, by setting the OCxIE bit. For further

information on peripheral interrupts, refer to

Section 6.0 “Interrupt Controller”.

10. To initiate another single pulse output, change the

Timer and Compare register settings, if needed,

and then issue a write to set the OCM bits to ‘100’.

Disab li ng an d r e -ena bl in g o f th e t imer, and cle ar -

ing the TMRy register, are not required but may

be advantageous for defining a pulse from a

known ev ent tim e boun dary.

The output compare module does not have to be dis-

abled afte r the falling edge of the ou tput pulse. Another

pulse can be initiated by rewriting the value of the

OCxCON register.

14.2 Setup for Continuous Output

Pulse Generation

When the O C M co ntro l b it s (O Cx CON <2 :0>) are s et to

‘101’, the selected output compare channel initializes

the OCx pin to the low state and generates output

pulses on each and every compare match event.

For the use r to confi gure the modul e for the ge neratio n

of a continuous stream of output pulses, the following

step s are required (these step s ass ume timer sourc e is

initially turned off but this is not a requirement for the

module operation):

1. Determine the ins tru cti on c loc k c yc le ti me. Take

into ac co u nt th e fr e q uen cy of t h e ex ter n al c lo ck

to the timer source (i f one is us ed) and the timer

prescaler settings.

2. Calculate time to the rising edge of the output

pulse re la tiv e to th e TM Ry start value (0 00 0h) .

3. Calcul at e the t ime to the falli ng ed ge of the p ulse ,

based o n t he des ire d pu ls e w idth a nd th e time to

the ris i ng edge o f the pu ls e.

4. Write the values computed in step 2 and 3 above

into the Output Compare register, OCxR, and the

Output Compare Secondary register, OCxRS,

respectively.

5. Set Timer Period register, PRy, to value equal to

or greater than value in OCxRS, the Output

Compare Secondary register .

6. Set the OCM bits to ‘101’ and the OCTSEL bit to

the desired timer source. The OCx pin state will

now be driven low .

7. Enable the compare time base by setting the T ON

(TyCON<15 >) bi t t o ‘1’.

8. Upon the first match between TMRy and OCxR,

the O C x pi n w i ll b e d riven hi gh .

9. When the compare time base, TMRy, matches

the Ou tput Comp are Second ary regis ter , OCxRS,

the second and trailing edge (high-to-low) of the

pulse is driven onto the OCx pin.

10. As a re sult of the secon d compare mat ch event,

the O CxIF interrupt fl ag bi t set.

11. Whe n the co mpare time bas e an d th e va lu e in its

respective T imer Period reg ister match, the TMRy

12. Steps 8 through 11 are repeated and a continu-

ous stream of pulses is generated, indefinitely.

The OCxIF flag is set on each OCxRS-TMRy

compare match event.

Note: This data sheet summarizes the features

of this group of PIC24H devices. It is not

intende d to be a comprehe nsive referenc e

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

PIC24H

14.3 Pulse-Width Modulation Mode

The following steps should be taken when configuring

the output compare module for PWM operation:

1. Set the PWM period by writing to the selected

Timer Period register (PRy).

2. Set the PWM duty cycle by writing to the OCxRS

3. Wri te the OxCR reg ister with the initial duty cycle.

4. Enable interrupts, if required, for the timer and

output compare modules. The output compare

interrupt is required for PWM Fault pin utilization.

5. Configure the outpu t comp are module for one of

two PW M operation modes by writing to the Out-

put Compare Mode bits, OCM<2:0>

(OCxCON<2:0>).

6. Set the TMRy prescale value and enable the

time base by setting TON = 1 (TxCON<15>).

14.3.1 PWM PERIOD

The PWM period is specified by writing to PRy, the

Timer Period register. The PWM period can be

calculated using Equation 14-1:

EQUATION 14-1: CALCULATING THE PWM

PERIOD

14.3.2 PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the OCxRS

but the duty cycle value is not latched into OCxR until a

match between PRy and TMRy occurs (i.e., the period is

complete). This provides a double buffer for the PWM duty

cycle and is essential for glitchless PWM operation. In the

PWM mode, OCxR is a read-only register .

Some important boundary parameters of the PWM duty

cycle include:

• If the Output Compare register, OCxR, is loaded

with 0000h, the OCx pin will remain low (0% duty

cycle).

• If OCxR is greater than PRy (Timer Period register),

the pin will remain high (100% duty cycle).

• If OCxR is equal to PRy, the OCx pin will be low

for one time base count value and high for all

other co unt va lue s.

See Example 14-1 for PWM mode timing details.

Table 14-1 shows example PWM frequencies and

resolutions for a device operating at 10 MIPS.

EQUATION 14-2: CALCULATION FOR MAXIMUM PWM RESOLUTION

EXAMPLE 14-1: PW M PERIOD AND DUTY CYCLE CALCULATIONS

Note: The OCxR register should be initialized

before the output compare module is first

enabled. The OCxR register becomes a

read-only duty cycle register when the

module is operated in the PWM modes.

The value held in OCxR will become the

PWM duty cycle for the first PWM period.

The contents of the Output Compare

Secondary register, OCxRS, will not be

transferred into OCxR until a time base

period match occurs .

Note: A PRy value of N will produce a PWM

period of N + 1 time base count cycles. For

example, a value of 7 written into the PRy

eight time base cycles.

PWM Period = [(PR y) + 1] • TCY • (T imer P rescale Value

)

PWM Frequenc y = 1/[PWM Peri od]

where:

( )

Maximum PWM Resolutio n (bi ts) =

FCY

FPWM

log10

log10(2) bits

1. Find the Timer Period re gister valu e fo r a d esire d PWM fre quency that is 52.08 kHz, wher e FCY = 16 MHz and a Timer 2

prescaler setting of 1:1.

TCY = 62.5 ns

PWM Period = 1/PWM Frequen cy = 1/52.08 kHz = 19.2 μs

PWM Period = (PR2 + 1) • TCY • (Timer2 Prescale Value)

19.2 μs = (PR2 + 1) • 62.5 ns • 1

PR2 = 306

2. Find th e maximum resolution of th e duty cycle that can be u sed with a 52.08 kHz frequency and a 32 MHz device clo ck rate:

PWM Resolution = log10(FCY/FPWM)/log102) bits

=(log

10(16 MHz/52.08 kHz)/log102) bits

= 8.3 bits

PIC24H

TABLE 14-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz)

TABLE 14-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (FCY = 16 MHz)

TABLE 14-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MIPS (FCY = 40 MHz)

FIGURE 14-1: O UTPUT C OMPARE MODULE BLOCK DIAGRAM

PWM Frequency 7.6 Hz 61 Hz 122 Hz 977 Hz 3.9 kHz 31.3 kHz 125 kHz

Timer Prescaler Ratio 8111111

Period Register Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001Fh

Resol uti on (bits) 16 16 15 12 10 7 5

PWM Frequency 30.5 Hz 244 Hz 488 Hz 3.9 kHz 15.6 kHz 125 kHz 500 kHz

Timer Prescaler Ratio 8111111

Period Register Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001Fh

Resol uti on (bits) 16 16 15 12 10 7 5

PWM Frequency 76 Hz 610 Hz 1.22 Hz 9.77 kHz 39 kHz 313 kHz 1.25 MHz

Timer Prescaler Ratio 8111111

Period Register Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001Fh

Resol uti on (bits) 16 16 15 12 10 7 5

Note: Only OC1 and OC2 can trigger a DMA data transfer.

OCxR(1)

Comparator

Output

Logic

OCM2:OCM0

Output Enable

OCx(1)

Set Flag bit

OCxIF(1)

OCxRS(1)

Mode Select

Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels

1 through 8.

2: OCFA pin controls OC1-OC4 channels. OCFB pin controls OC5-OC8 channels.

3: Each output compare channel can use one of two selectable time bases. Refer to the device data sheet for the

time bases associated with the module.

OCTSEL 01

OCFA or OCFB(2)

TMR register inputs

from time bases(3) Period match signals

from time bases(3)

PIC24H

14.4 Output Compare Register

U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

——OCSIDL — — — — —

bit 15 bit 8

U-0 U-0 U-0 R-0 HC R/W-0 R/W-0 R/W-0 R/W-0

— — — OCFLT OCTSEL(1) OCM<2:0>

bit 7 bit 0

Legend: HC = Cleared in Hardware HS = Set in Hardware

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘ 1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13 OCSIDL: Stop Output Compare in Idle Mode Control bit

1 = Output Compare x will halt in CPU Idle mode

0 = Output Compare x will continue to operate in CPU Idle mode

bit 12-5 Unimplemented: Read as ‘0’

bit 4 OCFLT: PWM Fault Condition Status bit

1 = PWM Fault condition has occur red ( c leared in HW only)

0 = No PWM Fault condition has occurred

(This bit is only use d wh en OC M< 2: 0> = 111.)

bit 3 OCTSEL: Output Compare Timer Select bit(1)

1 = Timer3 is the clock source for Compare x

0 = Timer2 is the clock source for Compare x

bit 2-0 OCM<2:0>: Output Compare Mode Select bits

111 = PWM mode on OCx, Fault pin enabled

110 = PWM mode on OCx, Fault pin disabled

101 = Initialize OCx pin low, generate continuous output pulses on OCx pin

100 = Initialize OCx pin low, generate single output pulse on OCx pin

011 = Compare event toggles OCx pin

010 = Initialize OCx pin high, compare event forces OCx pin low

001 = Initialize OCx pin low, compare event forces OCx pin high

000 = Output compare channel is disabled

Note 1: Refer to the device data sheet for specific time bases available to the output compare module.

PIC24H

15.0 SERIAL PERIPHERAL

INTERFACE (SPI)

The Serial Peripheral Interface (SPI) module is a syn-

chronous serial interface useful for communicating with

other peripheral or microcontroller devices. These

peripheral devices may be serial EEPROMs, shift regis-

ters, display drivers, A/D converters, etc. The SPI module

is co m p a tib le wi th SPI and SIOP f rom Mo torola®.

15.1 Operating Function Description

Each SPI module consists of a 16-bit shift register,

SPIxSR (whe re x = 1 or 2), us ed for shifti ng data in and

out, and a buffer register, SPIxBUF. A control register,

SPIxCON, configures the module. Additionally, a sta-

tus register, SPIxSTAT, indicates various status condi-

tions.

The seria l interfac e consis ts of 4 p ins: SDIx (se rial dat a

input), SDOx (serial data output), SCKx (shift clock

input or output), and SSx (active low slave select).

In Mas ter m od e o pera tio n, SCK is a cl ock o utpu t b ut i n

Slave mode, it is a clock input.

A series of eight (8) or sixteen (16) clock pulses shift

out bits from the SPIxSR to SDOx pin and simulta-

neousl y s hi ft in dat a from SDIx pin. An inte rrup t is ge n-

erated when the transfer is complete and the

corresponding interrupt flag bit (SPI1IF or SPI2IF) is

set. This interrupt can be disabled through an interrupt

enable bit (SPI1IE or SPI2IE).

The receive operation is double-buffered. When a com-

plet e by te i s r ecei ved , i t is tra nsf erre d f rom S PIxS R to

SPIxBUF.

If the re ceive buf fer is full when new data is b eing trans-

ferred from SPIxSR to SPIxBUF, the module will set the

SPIROV bit i ndicating an overflow cond ition. The tran s-

fer of the data from SPIxSR to SPIxBUF will not be

completed and the new data will be lost. The module

will no t respond to SCL tran sitions w hile SPIROV is ‘1’,

effectively disabling the module until SPIxBUF is read

by user software.

Transmit writes are also double-buffered. The user

write s to SPIxBU F. Wh en the mast er or slav e transfe r

is completed, the content s of the shift register (SPIxSR)

are moved to the receive buffer. If any transmit data

has been written to the buffer register, the contents of

the tr ansmit b uf fer are mo ved t o SPIxSR. The re ceive d

data is thus placed in SPIxBUF and the trans mit dat a in

SPIxSR is ready for the next transfer.

The modul e supports a basic framed SPI protocol while

operatin g in either Master or Slave mode. A total of four

framed SPI config ura tio ns are sup ported.

The SPI serial interface consists of four pins:

• SDIx: Serial Data Input

• SDOx: Serial Data Output

• SCKx: Shift Clock Input or Output

• SSx: Active-Low Slave Select or Frame

Synchronization I/O Pulse

The SPI module can be configured to operate using 2,

3 or 4 pins. In the 3-pin mode, SSx is not used. In the

2-pin mode, both SDOx and SSx are not used.

A block diagram of an SPI module is shown in

Figure 15-1. All PIC24H devices contain two SPI

modules on a single device.

The SPI module contains an 8-word deep FIFO buffer;

the top of the buffer is denoted as SPIxBUF. If DMA

transfers are enabled, the FIFO buffer must be

disabl ed by cle arin g the ENHB UF bit (SPIxCON2<0 >).

To set up the SPI module for the Master mode of

operation:

1. If using interrupts:

a) Clear the SPIxIF bit in the respective IFSn

b) Set the SPIxIE bit in the respective IECn

c) Write the SPIxIP bits in the respective IPCn

2. Write the desired settings to the SPIxCON

3. Clear the SPIROV bit (SPIxSTAT<6>).

4. Enable SPI operation by setting the SPIEN bit

(SPIxSTAT<15>).

5. Write the data to be transmitted to the SPIxBUF

registe r . T ransmissio n (and receptio n) will start as

soon as d at a i s writte n to the SPIx BUF re gis te r.

Note: This data sheet summarizes the features

of this group of PIC24H devices. It is not

intende d to be a comprehe nsive referenc e

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

Note: In this section, the SPI modules are

referred to together as SPIx, or separately

as SPI1 and SPI2. Special Function Reg-

isters will follow a similar notation. For

example, SPIxCON refers to the control

Note: Both the transmit buffer (SPIxTXB) and

the receive buffer (SPIxRXB) are mapped

to the same register address, SPIxBUF.

Note: Do not perform read-modify-write opera-

tions (such as bit-oriented instructions) on

the SPIxBUF register.

PIC24H

To set up the SPI module for the Slave mode of operation:

1. Clear the SPIxBUF register.

2. If using interrupts:

a) Clear the SPIxIF bit in the respective IFSn

b) Set the SPIxIE bit in the respective IECn

c) Write the SPIxIP bi ts i n the respe ctive IPCn

3. Write the desired se ttin gs to the SPIxCON1 an d

SPIxCON2 registers with MSTEN

(SPIxCON1<5>) = 0.

4. Clear the SMP bit.

5. If the CKE bit is set, then the SSEN bit

(SPIxCON1<7>) must be set to enable the SSx

pin.

6. Clear the SPIROV bit (SPIxSTAT<6>).

7. Enable SPI operation by setting the SPIEN bit

(SPIxSTAT<15>).

The SPI m odule genera tes an interru pt ind icatin g com-

pletion of a by te or word transfe r, as well as a sep arate

interrupt for all SPI error conditions.

FIGURE 15-1: SPI MODULE BLOCK DIAGRAM

Note: Both SPI1 and SPI2 can trigger a DMA

data transfer. If SPI1 or SPI2 is selected

as the DMA IRQ source, a DMA transfer

occurs wh en the SPI1IF or SPI2IF bit get s

set as a result of an SPI1 or SPI2 byte or

word transfer.

Inte rn al Da ta B u s

SDIx

SDOx

SSx

SCKx

SPIxSR

bit 0

Shift Control

Edge

Select

FCY

Primary

1:1/4/16/64

Enable

Prescaler

Sync

SPIxBUF

Control

Transfer

Write SPIxBUF

Read SPIxBUF

SPIxCON1<1:0>

SPIxCON1<4:2>

Master Clock

Clock

Control

Secondary

Prescaler

1:1 to 1:8

SPIxRXB SPIxTXB

PIC24H

FIGURE 15-2: SPI MASTER/SLAVE CONNECTION

FIGURE 15-3: SPI MASTER, FRAME MASTER CONNECTION DIAGRAM

FIGURE 15-4: SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM

Serial Receive Buffer

(SPIxRXB)

LSb

MSb

SDIx

SDOx

PROCESSOR 2 (SPI Slave)

SCKx

SSx(1)

Serial Transmit Buffer

(SPIxTXB)

Serial Receive Buffer

(SPIxRXB)

Shift Regis ter

(SPIxSR)

MSb LSb

SDOx

SDIx

PROCESSOR 1 (SP I Master)

Serial Clock

(SSEN (SPI xCON 1<7> ) = 1 and MSTEN (SPIxCON1<5>) = 0)

Note 1: Using the SSx pin in Slave mode of operation is optional.

2: User must wr ite tra nsmi t data to/r ead rec eive d dat a from SP IxBUF. The SPI xTXB an d SPIx RXB reg ister s are m emory

mapped to SPIxBUF.

SCKx

Serial Transmit Buffer

(SPIxTXB)

(MSTEN (SPIxCON1<5>) = 1)

SPI Buffer

(SPIxBUF)(2)

SPI Buffer

(SPIxBUF)(2)

Shift Regis ter

(SPIxSR)

SDOx

SDIx

PIC24H

Serial Clock

SSx

SCKx

Frame Sync

Pulse

SDIx

SDOx

PROCESSOR 2

SSx

SCKx

(SPI Slave, Frame S lav e)

SDOx

SDIx

PIC24H

Serial Clock

SSx

SCKx

Frame Sync

Pulse

SDIx

SDOx

PROCESSOR 2

SSx

SCKx

(SPI Mas ter, Frame Sl ave)

PIC24H

FIGURE 15-5: SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM

FIGURE 15-6: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM

EQUATION 15-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED

TABLE 15-1: SAMPLE SCKx FREQUENCIES

FCY = 40 MHz Secondary Prescaler Settings

1:1 2:1 4:1 6:1 8:1

Primary Prescaler Settings 1:1 Invalid Invalid 10000 6666.67 5 000

4:1 10000 5000 2500 1666.67 1250

16:1 2500 1250 625 416.67 312.50

64:1 625 312.5 156.25 104.17 78.125

FCY = 5 MHz

Primary Prescaler Settings 1:1 5000 2500 1250 833 625

4:1 1250 625 313 208 156

16:1 313 156 78 52 39

64:17839201310

Note: SCKx frequencies shown in kHz.

SDOx

SDIx

PIC24H

Serial Clock

SSx

SCKx

Frame Sync

Pulse

SDIx

SDOx

PROCESSOR 2

SSx

SCKx

(SPI Slave, Frame Slav e)

SDOx

SDIx

PIC24H

Serial Clock

SSx

SCKx

Frame S ync

Pulse

SDIx

SDOx

PROCESSOR 2

SSx

SCKx

(SPI Master, Frame Slave)

Primary Prescaler * Secondary Prescaler

FCY

FSCK =

PIC24H

R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

SPIEN — SPISIDL — — — — —

bit 15 bit 8

U-0 R/C-0 U-0 U-0 U-0 U-0 R-0 R-0

— SPIROV — — — — SPITBF SPIRBF

bit 7 bit 0

Legend: C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 SPIEN: SPIx Enable bit

1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins

0 = Disables module

bit 14 Unimplemented: Read as ‘0’

bit 13 SPISIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

bit 12-7 Unimplemented: Read as ‘0’

bit 6 SPIROV: Receive Overflow Flag bit

1 = A new byte/word is completely received and discarded. The user software has not read the

previous data in the SPIxBUF register.

0 = No overflow has occurred

bit 5-2 Unimplemented: Read as ‘0’

bit 1 SPITBF: SPIx Transmit Buffer Full Status bit

1 = Transmit not yet started, SPIxTXB is full

0 = Transmit started, SPIxTXB is empty

Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB.

Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR.

bit 0 SPIRBF: SPIx R eceive Bu ffer Full Status bit

1 = Receive complete, SPIxRXB is full

0 = Receive is not complete, SPIxRXB is empty

Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB.

Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB.

PIC24H

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — DISSCK DISSDO MODE16 SMP CKE(1)

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SSEN CKP MSTEN SPRE<2:0> PPRE<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 Unimplemented: Read as ‘0’

bit 12 DISSCK: Disable SCKx pin bit (SPI Master modes only)

1 = Internal SPI clock is disabled, pin functions as I/O

0 = Internal SPI clock is enabled

bit 11 DISSDO: Disable SDOx pin bit

1 = SDOx pin is not used by module; pin functions as I/O

0 = SDOx pin is controlled by the module

bit 10 MODE16: Wo rd/By te Commu nic ati on Sele ct bit

1 = Communication is word-wide (16 bits)

0 = Communication is byte-wide (8 bits)

bit 9 SMP: SPIx Data Input Sample Phase bit

Master mode:

1 = Input data sampled at end of data output time

0 = Input data sampled at middle of data output time

Slave mode:

SMP must be cleared when SPIx is used in Slave mode.

bit 8 CKE: SPIx Clock Edge Selec t bit(1)

1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6)

0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6)

bit 7 SSEN: Slave Select Enable bit (Slave mode)

1 = SSx pin used for Slave mode

0 = SSx pin not used by module. Pin cont rolled by port func tion.

bit 6 CKP: Clock Polarity Select bit

1 = Idle stat e for clock is a high level; active state is a lo w leve l

0 = Idle state for clock is a low level; active state is a high level

bit 5 MSTEN: Master Mode Enable bit

1 = Master mode

0 = Slave mode

bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)

111 = Secondary prescale 1:1

110 = Secondary prescale 2:1

...

000 = Secondary prescale 8:1

bit 1-0 PPRE<1:0>: Primary Prescale bits (M aster mo de)

11 = Primary prescale 1:1

10 = Primary prescale 4:1

01 = Primary prescale 16:1

00 = Primary prescale 64:1

Note 1: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed

SPI modes (FRMEN = 1).

PIC24H

R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0

FRMEN SPIFSD FRMPOL — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0

— — — — — — FRMDLY —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 FRMEN: Framed SPIx Supp ort bit

1 = Framed SPIx support enabled (SSx pin us ed as frame sync pulse input/output)

0 = Framed SPIx support disabled

bit 14 SPIFSD: Frame Sync Pulse Direction Control bit

1 = Frame sync pulse input (slave)

0 = Frame sync pulse output (master)

bit 13 FRMPOL: Frame Sync Pulse Polarity bit

1 = Frame sync pulse is active-high

0 = Frame sync pulse is active-low

bit 12-2 Unimplemented: Read as ‘0’

bit 1 FRMDLY: Frame Sync Pulse Edge Select bit

1 = Frame sync pulse coincides with first bit clock

0 = Frame sync pulse precedes first bit clock

bit 0 Unimplemented: Read as ‘0’

This bit must not be set to ‘1’ by the user application.

PIC24H

NOTES:

PIC24H

16.0 INTER-INTEGRATED CIRCUIT

(I2C)

The Inter-Integrated Circuit (I2C) module provides

complete hardware support for both Slave and Multi-

Master modes of the I2C serial communication

standard, with a 16-bit interface.

The PIC24H devices have up to two I2C interface mo d-

ules, den oted as I2C1 an d I2C 2. Eac h I2C module has

a 2-pin interface: the SCLx pin is clock and the SDAx

pin is data.

Each I2C modul e ‘x’ (x = 1 o r 2) of fers the follo wing ke y

features:

•I

2C interface supporting both master and slave

operation.

•I

2C Slave mode supports 7 and 10-bit address.

•I

2C Master mode supports 7 and 10-bit address.

•I

2C port allows bidirectional transfers between

master and slav es.

• Serial clock synchronization for I2C port can be

used as a ha ndshake mechanis m to suspen d and

resume serial transfer (SCLREL control).

•I

2C supports multi-master operation; detects bus

collision and will arbitrate accordingly.

16.1 Operating Modes

The hardw are fully imple ments al l the master an d slave

functions of the I2C Standard and Fast mode

specifications, as well as 7 and 10-bit addressing.

The I2C module can operate either as a slave or a

master on an I2C bus.

The following types of I2C operation are supported:

•I

2C slave operation with 7-bit address

•I

2C slave operation with 10-bit address

•I

2C master operation with 7 or 10-bit address

For det ails about the comm unicatio n sequence in eac h

of these modes, please refer to the “dsPI C30F F ami ly

Reference Manual” (DS70046).

16.2 I2C Registers

I2CxCON and I2CxSTAT are control and status

registers, respectively. The I2CxCON register is

readable and writable. The lower six bits of I2CxSTAT

are read-only. The remaining bits of the I2CSTAT are

read/write.

I2CxRSR is the shift register used for shifting data,

whereas I2CxRCV is the buffer register to which data

bytes are written, or from which data bytes are read.

I2CxRCV is the rec eive bu ffe r. I2CxTRN is th e trans mit

operation.

The I2CxADD register holds the slave address. A

status bit, ADD10, indicates 10-bit Address mode. The

I2CxBRG acts as the Baud Rate Generator (BRG)

reload value.

In receiv e operations , I2CxRSR and I2Cx RCV together

form a double-buffered receiver. When I2CxRSR

receives a complete byte, it is transferred to I2CxRCV

and an interrupt pulse is generated.

16.3 I2C Interr u p ts

The I2C m odul e gene rates t wo interr upt flags , MI2Cx IF

(I2C Master Events Interrupt Flag) and SI2CxIF (I2C

Slave Events Interrupt Flag). A separate interrupt is

generated for all I2C error conditions.

16.4 Baud Rate Generator

In I2C Master mode, the reload value for the BRG is

located in the I2CxBRG register. When the BRG is

loaded w ith th is v alu e, the BRG c ou nt s d own to ‘0’ and

stop s until anothe r reload has taken pla ce. If clock arbi-

tration i s taking place, for i nstance, the BRG is reloaded

when the SCLx pin is sam pled high.

As per the I2C standard, FSCL may be 100 kHz or

400 kHz. However, the user can specify any baud rate

up to 1 MHz. I2CxBRG values of ‘0’ or ‘1’ are illegal.

EQUATION 16-1: SERIAL CLOCK RATE

Note: This data sheet summarizes the features

of this group of PIC24H devices. It is not

intende d to be a comprehe nsive referenc e

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

I2CxBRG = FCY FCY

FSCL 1,111,111 – 1

–

(

)

PIC24H

FIGURE 16-1: I2C™ BLOCK DIAGRAM (X = 1 OR 2)

Internal

Data Bus

SCLx

SDAx

Shift

Match Detect

I2CxADD

S tart and Stop

Bit Detect

Clock

Address Match

Clock

Stretching

I2CxTRN LSB

Shift Clock

BRG Down Counter

Reload

Control

TCY/2

S tart and Stop

Bit Generation

Acknowledge

Generation

Collision

Detect

I2CxCON

I2CxSTAT

Control Logic

Read

LSB

Write

Read

I2CxBRG

I2CxRSR

Write

Read

Write

Read

Write

Read

Write

Read

Write

Read

I2CxMSK

I2CxRCV

PIC24H

16.5 I2C Module Addresses

The I2CxADD register contains the Slave mode

addresses. The register is a 10-bit register.

If the A10M bit (I2CxCON<10>) is ‘0’, the address is

inter prete d by the mo dul e as a 7 - bit add ress . When an

address is received, it is compared to the 7 Least

Significant bits of the I2CxADD register.

If the A10M bit is ‘1’, the address is assumed to be a

10-bit address. When an address is received, it will be

compared with the binary value, ‘11110 A9 A8’

(where A9 and A8 are two Most Significant bits of

I2CxADD). If that value matches, the next address will

be compared with the Least Significant 8 bits of

I2CxADD, as specified in the 10-bit addressing

protocol.

TABLE 16-1: 7-BIT I2C™ SLAV E

ADDRESSES SUPPORTED BY

PIC24H

16.6 Slave Address Masking

The I2CxMSK register (Register 16-3) designates

address bit positions as “don’t care” for both 7-bit and

10-bit Address modes. Setting a particular bit location

(= 1) in the I2CxMSK reg ister , cause s the slave modul e

to respond, whether the corresponding address bit

value is a ‘0’ or ‘1’. For example , when I2Cx MSK is set

to ‘00100000’, the slave module will detect both

addresses, ‘0000000’ and ‘00100000’.

To enable address masking, the Intelligent Peripheral

Management Interface (IPMI) must be disabled by

clearing the IPMIEN bit (I2CxCON<11>).

16.7 IPMI Support

The con trol bit, IPM IEN, enabl es the modul e to supp ort

the Intelligent Peripheral Ma nagement Interface (IPMI).

When this bit i s s et, t he m od ule ac ce pts an d ac t s upo n

all addres ses .

16.8 General Call Address Support

The general call address can address all devices.

When this address is used, all devices should, in

theory, respond with an Acknowledgement.

The general call address is one of eight addresses

reserved for specific purposes by the I2C protocol. It

consists of all ‘0’s with R_W = 0.

The ge neral call address is recogni zed when the Ge neral

Call Ena bl e (GCEN) bi t is set (I 2Cx CO N<7 > = 1). When

the interrupt is serviced, the source for the interrupt can

be checked by reading the contents of the I2CxRCV to

determine if the address was device -specific or a ge neral

call ad dress.

16.9 Automatic Clock Stretch

In Slave modes, the module can synchronize buffer

reads and writes to the master dev ice by clock

stretching.

16.9.1 TRAN SMIT CLOCK STRE TCHING

Both 10-bi t an d 7-bi t Transmit mode s imp lem ent clock

stretching by asserting the SCLREL bit after the falling

edge of the ninth clock, if the TBF bit is cleared,

indicating the buffer is empty.

In Slave Transmit modes, clock stretching is always

performed, irrespective of the STREN bit. The user’s

ISR must set the SCLREL bit before transmission is

allowed to continue. By holding the SCLx line low, the

user has time to service the ISR and load the contents

of the I2CxTRN before the master device can initiate

another transmit sequence.

16.9.2 RECEIVE CLOCK STRETCHING

The STR EN bit in th e I2CxCON registe r can be used to

enable clock stretching in Slave Receive mode. When

the STREN bit is set, the SCLx pin will be held low at

the end of each data receive sequence.

The user’s ISR must set the SCLR EL bit be fore rece p-

tion is allowed to continue. By holding the SCLx line

low, the user has time to service the ISR and read the

contents of the I2Cx R CV before the master de vic e ca n

initiate another receive sequence. This will prevent

buffer overruns from occurring.

16.10 Software Controlled Clock

Stretching (STREN = 1)

When the STREN bit is ‘1’, the SCLREL bit may be

cleared by software to allow software to control the

clock stretching.

If the STREN bit is ‘0’, a software write to the SCLREL

bit will be disregarded and have no effect on the

SCLREL bit.

0x00 General call address or Start byte

0x01-0x03 Reserved

0x04-0x07 Hs mode Master codes

0x08-0x77 Valid 7-bit addresses

0x78-0x7b Valid 10-bit addresses

(lower 7 bit s)

0x7c-0x7f Reserved

PIC24H

16.11 Slope Control

The I2C standard requires slope control on the SDAx

and SCL x signals for Fast m ode (400 k Hz). The co ntrol

bit, DISSLW , enab les the user to disa ble slew rate co n-

trol if desired. It is necessary to disable the slew rate

control for 1 MHz mode.

16.12 Clock Arbitration

Clock arbitration oc curs when the m aster deasse rts the

SCLx pin (SCLx allowed to float high) during any

receive, transmit or Restart/Stop condition. When the

SCLx pin is allowed to float high, the Baud Rate Gen-

erator (BRG) is suspended from counting until the

SCLx pi n is ac tually sa mp led high. When t he SCL x pi n

is sampled high, the Baud Rate Generator is reloaded

with the contents of I2CxBRG and begins counting.

This ensures that the SCLx high time will always be at

least on e BRG rollov er count in t he event tha t the clock

is held low by an external device.

16.13 Multi-Master Communication, Bus

Collision and Bus Arbitrat ion

Multi-Master mode support is achieved by bus

arbitration. When the master outputs address/data bits

onto the SDAx pin, arbitration takes place when the

master o utputs a ‘1’ on SDAx by letting SDAx fl oat high

while anoth er m ast er as se rt s a ‘ 0’. When the SCLx pin

floats high, data should be stable. If the expected data

on SDAx is a ‘1’ and the data sampled on the

SDAx pin = 0, then a bus col lision has taken place. Th e

master will set the I2C master events interrupt flag and

reset the master portion of the I2C port to its Idle state.

PIC24H

R/W-0 U-0 R/W-0 R/W-1 HC R/W-0 R/W -0 R/W-0 R/W-0

I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 HC R/W-0 HC R/W-0 HC R/W-0 HC R/W-0 HC

GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN

bit 7 bit 0

Legend: U = Unimplemented bit, read as ‘0’

R = Readable bit W = Writable bit HS = Set in hardware HC = Cleared in hardware

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 I2CEN: I2Cx Enable bit

1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins

0 = Disables the I2Cx module. All I2C pins are controlled by port functions.

bit 14 Unimplemented: Read as ‘0’

bit 13 I2CSIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters an Idle mode

0 = Continue module operation in Idle mode

bit 12 SCLREL: SCLx Release Control bit (when operating as I2C slave)

1 = Release SCLx clock

0 = Hold SCLx clock low (clock stretch)

If STREN = 1:

Bit is R/W (i.e., s oftwa re m ay wri te ‘ 0’ to initiate stre tch and write ‘ 1’ to release clock). Hardware clear

at beginning of slave transmission. Hardware clear at end of slave reception.

If STREN = 0:

Bit is R/S (i.e., software may only write ‘1’ to release clock). Hardware clear at beginning of slave

transmission.

bit 11 IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit

1 = IPMI mode is enabled; all addresses Acknowledged

0 = IPMI mode disabled

bit 10 A10M: 10-bit Slave Address bit

1 = I2CxADD is a 10-bit slave address

0 = I2CxADD is a 7-bit slave address

bit 9 DISSLW: Disable Slew Rate Control bit

1 = Slew rate control disabled

0 = Slew rate control enabled

bit 8 SMEN: SMBus Input Levels bit

1 = Enable I/O pin thresholds compliant with SMBus specification

0 = Disable SMBus input thresholds

bit 7 GCEN: General Call Enable bit (when operating as I2C slave)

1 = Enable interrupt when a general call address is received in the I2CxRSR

(module is enabled for reception)

0 = General call address disabled

bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)

Used in conjunction with SCLREL bit.

1 = Enable software or receive clock stretching

0 = Disable software or receive clock stre tching

PIC24H

bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applica ble during master receive)

Value that will be transmitted when the software initiates an Acknowledge sequence.

1 = Send NACK during Acknowled ge

0 = Send ACK during Acknowledge

bit 4 ACKEN: Acknowledge Sequence Enable bit

(when operating as I2C master, applicable during master receive)

1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.

Hardware clear at end of master Acknowledge sequence.

0 = Acknowledge sequence not in progress

bit 3 RCEN: Receive Enable bit (when operating as I2C master)

1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte.

0 = Receive sequence not in progress

bit 2 PEN: Stop Condition Enable bit (when operating as I2C ma st e r )

1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.

0 = Stop condition not in progress

bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I2C master)

1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of

master Repeated Start sequence.

0 = Repeated Start condition not in progress

bit 0 SEN: Start Condition Enable bit (when operating as I2C master)

1 = Initiat e St art c ond itio n on SDAx an d SC Lx pin s. Hard ware c le ar at en d of mas ter Star t sequence .

0 = Start conditi on not in prog res s

PIC24H

R-0 HSC R-0 HSC U-0 U-0 U-0 R/C-0 HS R-0 HSC R-0 HSC

ACKSTAT TRSTAT — — — BCL GCSTAT ADD10

bit 15 bit 8

R/C-0 HS R/C-0 HS R-0 HSC R/C-0 HSC R/C-0 HSC R-0 HSC R-0 HSC R-0 HSC

IWCOL I2COV D_A P S R_W RBF TBF

bit 7 bit 0

Legend: U = Unimplemented bit, read as ‘0’

R = Readable bit W = Writable bit HS = Set in hardware HSC = Hardware set/cleared

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ACKSTAT: Acknowledge Status bit

(when operating as I2C master, applicable to master transmit operation)

1 = NACK received from slave

0 = ACK received from slave

Hardware set or clear at end of slave Acknowledge.

bit 14 TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation)

1 = Master transmit is in progress (8 bits + ACK)

0 = Master transmit is not in progress

Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge.

bit 13-11 Unimplemented: Read as ‘0’

bit 10 BCL: Master Bus Collision Detect bit

1 = A bus collision has been detected during a master operation

0 = No collision

Hardware set at detection of bus collision.

bit 9 GCSTAT: General Call Status bit

1 = General call address was received

0 = General call address was not received

Hardware set when address matches general call address. Hardware clear at Stop detection.

bit 8 ADD10: 10-bit Address Status bit

1 = 10-bit address was matched

0 = 10-bit address was not matched

Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection.

bit 7 IWCOL: Write Collision Detect bit

1 = An attempt to write the I2CxTRN register failed because the I2C module is busy

0 = No collision

Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).

bit 6 I2COV: Receive Overflow Flag bit

1 = A byte was re ceived while the I2CxRCV register is st ill holding the pre v ious byte

0 = No overflow

Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).

bit 5 D_A: Data/Address bit (when operating as I2C slave)

1 = Indicates that the last byte received was data

0 = Indicates that the last byte received was device address

Hardware clear at device address match. Hardware set by reception of slave byte.

bit 4 P: Stop bit

1 = Indicates that a Stop bit has been detected last

0 = Stop bit was not detected last

Hardware set or clear when Start, Repeated Start or Stop detected.

PIC24H

bit 3 S: Start bit

1 = Indicates that a Start (or Repeated Start) bit has been detected last

0 = Start bit was not detected last

Hardware set or clear when Start, Repeated Start or Stop detected.

bit 2 R_W: Read/Write Information bit (when operating as I2C slave)

1 = Read – indicates data transfer is output from slave

0 = Write – indicates data transfer is input to slave

Hardware set or clear after reception of I2C device address byte.

bit 1 RBF: Receive Buffer Full Status bit

1 = Receive complete, I2CxRCV is full

0 = Receive not complete, I2CxRCV is empty

Hardware set when I2CxRCV is written with received byte. Hardware clear when software

reads I2CxRCV.

bit 0 TBF: Transmit Buffer Full Status bit

1 = Transmit in progress, I2CxTRN is full

0 = Transmit complete, I2CxTRN is empty

Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.

PIC24H

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — — AMSK9 AMSK8

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-10 Unimplemented: Read as ‘0’

bit 9-0 AMSKx: Mask for Address bit x Select bit

1 = Enable masking for bit x of incoming message address; bit match not required in this position

0 = Disable masking for bit x; bit match required in this position

PIC24H

NOTES:

PIC24H

17.0 UNIVERSAL ASYNCHRONOUS

RECEIVER TRANSMITTER

(UART)

The Universal Asynchronous Receiver Transmitter

(UART) module is one of the serial I/O modules avail-

able in the PIC24H device family. The UART is a full-

duplex asynchronous system that can communicate

with peripheral devices, such as personal computers,

LIN, RS-232 and RS-485 interfaces. The module also

supports a hardware flow control option with the

UxCTS and UxRTS pins and also includes an IrDA®

encoder and decoder.

The primary features of the UART module are:

• Full-Duplex, 8 or 9-bit Data Transmission through

the UxTX and UxRX pins

• Even, Odd or No Parity Options (for 8-bit data)

• One or Two Stop bits

• Hardware Flow Control Option with UxCTS and

UxRTS pins

• Fully Integrated Baud Rate Generator with 16-bit

Prescaler

• Baud Rates Ranging from 1 Mbps to 15 bps at

16 MIPS

• 4-deep First-In-First-Out (FIFO) Transmit Data

Buffer

• 4-Deep FIFO Receive Data Buffer

• Parity, Framing and Buffer Overrun Error Detection

• Support for 9-bit mode with Address Detect

(9th bit = 1)

• Transmit and Receive Interrupts

• A Separate Interrupt for all UART Error Conditions

• Loopback mode for Diagnostic Support

• Support for Sync and Break Characters

• Supports Automatic Baud Rate Detection

• IrDA Encoder and Decoder Logic

• 16x Baud Clock Output for IrDA Support

A simplified block diagram of the UART is shown in

Figure 17-1. The UART module consists of the key

important hardware elements:

• Baud Rate Generator

• Asynchronous Transmitter

• Asynchronous Receiver

FIGURE 17-1: UART SIMPLIFIED BLOCK DIAGRAM

Note: This data sheet summarizes the features

of this group of PIC24H devices. It is not

intende d to be a comprehe nsive reference

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

Note 1: Both UART1 and UART2 can trigger a DMA data transfer. If U1TX, U1RX, U2TX or U2RX is selected as

a DMA IRQ source, a DMA transfe r occurs when the U1TXIF, U1RXIF, U2TXIF or U2RXIF bit gets set as

a result of a UART1 or UART2 transmission or reception.

2: If DMA transfers are required, the UART TX/RX FIFO buffer must be set to a size of 1 byte/word

(i.e., UTXISEL<1:0> = 00 and URXISEL<1:0> = 00).

UxRX

Hardware Flow Control

UART Receiver

UART Transmitte r UxTX

UxCTS

BCLK

Baud Rate Generator

UxRTS

IrDA®

PIC24H

17.1 UART Baud Rate Generator (BRG)

The UART module includes a dedicated 16-bit Baud

Rate Ge nerato r. The BRGx register c ontrols the perio d

of a f ree-ru nn ing 16-bit timer. Equation 17-1 sho ws th e

formula for computation of the baud rate with

BRGH = 0.

EQUATION 17-1: UART BAUD RATE WITH

BRGH = 0

Example 17-1 shows the calculation of the baud rate

error for the following conditions:

•F

CY = 4 MHz

• Desired Baud R ate = 9600

The maximum baud rate (BRGH = 0) possible is

FCY/16 (for BRGx = 0), and the minimum baud rate

possible is FCY/(16 * 65536).

Equation 17-2 shows the formula for computation of

the baud rate with BRGH = 1.

EQUATION 17-2: UART BAUD RATE WITH

BRGH = 1

The maxim um bau d rate (BRGH = 1) pos si ble is F CY/4

(for BRGx = 0), and the minim um bau d rate possib le i s

FCY/(4 * 65536).

Writing a new value to the BRGx register causes the

BRG timer to be reset (cleared). This ens ures the BRG

does not wai t for a timer overflow be fore generating the

new baud rate.

EXAMPLE 17-1: BAUD RATE ERROR CALCULATION (BRGH = 0)

Note: FCY denotes the instruction cycle clock

frequency (FOSC/2).

Baud Rate = FCY

16 • (BRG x + 1)

FCY

16 • Baud Rate

BRGx = – 1

Note: FCY denotes the instruction cycle clock

frequency (FOSC/2).

Baud Rate = FCY

4 • (BRGx + 1)

FCY

4 • Baud Rate

BRGx = – 1

Desired Baud Ra te = FCY/(16 (BRGx + 1))

Solving for BRGx Value:

BRGx = ((FCY/Desired Baud Rate)/16) – 1

BRGx = ((4000000/9600)/16) – 1

BRGx = 25

Calculated Baud Rate = 4000000/(16 (25 + 1))

= 9615

Error = (Calculated Baud Rate – Desir e d Baud Rate)

Desired Baud Rate

= (9615 – 9 600)/9600

=0.16%

PIC24H

17.2 Transmitting in 8-bit Data Mode

1. Set up the UART:

a) Write appropriate values for data, parity

and Stop bits.

b) Write appropriate baud rate value to the

BRGx regist er.

c) Set up transmit and receive interru pt enable

and priority bits.

2. Enable the UART.

3. Set the UTXEN bit (causes a transmit interrupt).

4. Write data byte to lower byte of U xTXREG word.

The value will be immediately transferred to the

Transmit Shift Register (TSR) and the serial bit

stre am will star t shifti ng out wit h the next rising

edge of the baud cloc k .

5. Alternately, the data byte may be transferred

while UTXEN = 0, and then the user may set

UTXEN. This will cause the serial bit stream to

begin immediately because the baud clock will

start from a cleared state.

6. A transmit interrupt will be generated as per

interrupt control bits, UTXISEL<1:0>.

17.3 Transmitting in 9-bit Data Mode

1. Set up the UART (as described in Section 17.2

“Transmitting in 8-bit Data Mode”).

2. Enable the UART.

3. Set the UTXEN bit (causes a transmit interrupt).

4. Write UxTXR EG as a 16-bit value only.

5. A word write to UxTXREG triggers the transfer

of the 9- bit dat a to th e TSR. Serial bit str eam will

start shifting out with the first rising edge of the

baud clock.

6. A transmit interrupt will be generated as per the

setting of control bits, UTXISEL<1:0>.

17.4 Break and Sync Transmit

Sequence

The following sequence will send a message frame

header made up of a Break, followed by an auto-baud

Sync byte.

1. Configu re the UART for the desire d mode.

2. Set UTXEN and UTXBRK – sets up the Break

character.

3. Load the UxTXREG register with a dummy

character to initiate transmission (value is

ignored).

4. Write 0x55 to UxTXREG – loads Sync character

into the transm it FIFO .

5. After the Break has been sent, the UTXBRK bit

is reset by hardware. The Sync character now

transmits.

17.5 Receiving in 8-bit or 9-bit Data

Mode

1. Set up the UART (as described in Section 17.2

“Transmitting in 8-bit Data Mode”).

2. Enable the UART.

3. A receive interrupt will be generated when one

or mor e da ta c har ac t ers ha ve be e n re ce iv ed as

per interrupt control bits, URXISEL<1:0>.

4. Read the OERR bit to determine if an overrun

error has occ urred. The OERR bit mus t be reset

in software.

5. Read UxRXREG.

The act of reading the UxRXREG character will move

the next character to the top of the receive FIFO,

inc luding a new set of PERR an d FERR values.

17.6 Flow Control Using UxCTS and

UxRTS Pins

UARTx Clear to Send (UxCTS) and Request to Send

(UxRTS) are the two hardware controlled active-low

pins th at are as soc ia ted w ith th e U ART module. Th es e

two pins allow the UART to operate in Simplex and

Flow Control modes. They are implemented to control

the transmission and the reception between the Data

Terminal Equipment (DTE). The UEN<1:0> bits in the

UxMODE register configures these pins.

17.7 Infrared Support

The UART module provides two types of infrared

UART support:

• IrDA clock output to support external IrDA

encoder and decoder device (legacy module

support)

• Full implementation of the IrDA encoder and

decoder.

17.7.1 EXTERNAL IrDA SUPPOR T – IrDA

CLOCK OUTPUT

To support external IrDA encoder and decoder

device s, the BCL K pin (same as the UxR TS pin) ca n be

configured to generate the 16x baud clock. With

UEN<1:0> = 11, the BCLK pi n will outp ut the 16x baud

clock if the UART module is enabled; it can be used to

support the IrD A code c chip.

17.7.2 BUILT-IN IrDA ENCODER AND

DECODER

The UART has full im pl em entation of the IrDA enc od er

and decoder as part of the UART module. The built-in

IrDA encoder and decoder functionality is enabled

using the IREN bit (UxMODE<12>). When enabled

(IREN = 1), the receive pin (UxRX) acts as the input

from the infrared receiver. The t ransmit pin (UxTX) a cts

as the output to the infrared transmitter.

PIC24H

R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0(2) R/W-0(2)

UARTEN — USIDL IREN(1) RTSMD —UEN<1:0>

bit 15 bit 8

R/W-0 HC R/W-0 R/W-0 HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL

bit 7 bit 0

Legend: HC = Hardware cleared

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 UARTEN: UARTx Enable bit

1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>

0 = UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption

minimal

bit 14 Unimplemented: Read as ‘0’

bit 13 USIDL: Stop in Idle Mode bit

1 = Discontinue module operation when d evice ente rs Id le mode.

0 = Continue module operation in Idle mode

bit 12 IREN: IrDA Encoder and Decoder Enable bit(1)

1 = IrDA encoder and decoder enabled

0 = IrDA encoder and decoder disabled

bit 11 RTSMD: Mode Selection for UxRTS Pin bit

1 = UxRTS p in in S implex mod e

0 = UxRTS pin in Flow Control mode

bit 10 Unimplemented: Read as ‘0’

bit 9-8 UEN<1:0>: UARTx Enable bits

11 =UxTX, UxRX and BCLK pins are enabled and used; UxCTS pin controlled by port latches

10 =UxTX, UxRX, UxCTS and UxRTS pins are enabled and used

01 =UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by port latches

00 =UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLK pins controlled by

port latches

bit 7 WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit

1 = UARTx will continue to sample the UxRX pin; interrupt generated on falling edge; bit cleared

in hardware on following rising edge

0 = No wake-up enabled

bit 6 LPBACK: UARTx Loopback Mode Select bit

1 = Enable Loopback mode

0 = Loopback mode is disabled

bit 5 ABAUD: Auto-Baud Enable bit

1 = Enable baud rate measurement on the next character – requires reception of a Sync field (55h);

cleared in hardware upon completion

0 = Baud rate measurement disabled or completed

bit 4 URXINV: Receive Polarity Inversion bit

1 = UxRX Idle state is ‘0’

0 = UxRX Idle state is ‘1’

Note 1: This feature is only available for the 16x BRG mode (BRGH = 0).

2: Bit availability depends on pin availability.

PIC24H

bit 3 BRGH: High Baud Rate Enable bit

1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)

0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode)

bit 2-1 PDSEL<1:0>: Parity and Data Selection bits

11 = 9-bit data, no parity

10 = 8-bit data, odd parity

01 = 8-bit data, even parity

00 = 8-bit data, no parity

bit 0 STSEL: Stop Bit Selection bit

1 = Two Stop bits

0 = One Stop bit

Note 1: This feature is only available for the 16x BRG mode (BRGH = 0).

2: Bit availability depends on pin availability.

PIC24H

R/W-0 R/W-0 R/W-0 U-0 R/W-0 HC R/W-0 R-0 R-1

UTXISEL1 UTXINV(1) UTXISEL0 — UTXBRK UTXEN UTXBF TRMT

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0

URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA

bit 7 bit 0

Legend: HC = Hardware cleared

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15,13 UTXISEL<1:0>: Transmission Interrupt Mode Selection bits

11 =Reserved; do not use

10 =Interrupt when a character is transferred to the Transmit Shift Register, and as a result, the

transmit buffer becomes empty

01 =Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit

operations are completed

00 =Interrupt when a character is transferred to the Transmit Shift Register (this implies there is

at least one character open in the transmit buffer)

bit 14 UTXINV: IrDA Encoder Transmit Polarity Inversion bit(1)

1 = IrDA encoded, UxTX Idle state is ‘1’

0 = IrDA encoded, UxTX Idle state is ‘0’

bit 12 Unimplemented: Read as ‘0’

bit 11 UTXBRK: Transmit Break bit

1 = Send Sync Break on next transm ission – S t art bit, follow ed by twelve ‘ 0’ bits, followed by Stop bit;

cleared by hardware upon completion

0 = Sync Break transmission disabled or completed

bit 10 UTXEN: T r an sm it Enab le bit

1 = Transmit enabled, UxTX pin controlled by UARTx

0 = Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled

by port.

bit 9 UTXBF: Transmit Buffer Full Status bit (read-only)

1 = Transmit buffer is full

0 = Transmit buffer is not full, at least one more character can be written

bit 8 TRMT: Transmit Shift Register Empty bit (read-only)

1 = Transmit Shift Register is emp ty and transmit buffer is empty (the last transmis sion has completed)

0 = Transmit Shift Register is not empty, a transmission is in progress or queued

bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bits

11 =Interrupt is set on UxRSR transfer making the receive buffer full (i.e., has 4 data characters)

10 =Interrupt is set on UxRSR transfer making the receive buffer 3/4 full (i.e., has 3 data characters)

0x =Interrupt is set when any character is received and transferred from the UxRSR to the receive

buffer. Receive buffer has one or more characters.

bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1)

1 = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect.

0 = Address Detect mode disabled

Note 1: Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled

(IREN = 1).

PIC24H

bit 4 RIDLE: Receiver Idle bit (read-only)

1 = Receiver is Idle

0 = Receive r is active

bit 3 PERR: Parity Error Status bit (read-only)

1 = Parity error has been de tected for the cu rrent cha racter (c harac ter at the to p of the rec eive FIFO )

0 = Parity error has not been detected

bit 2 FERR: Framing Error Status bit (read-only)

1 = Framing error has been detected for the current character (character at the top of the receive

FIFO)

0 = Framing error has not been detected

bit 1 OERR: Receive Buffer Overrun Error Status bit (read/clear only)

1 = Receive buffer has ov erflowed

0 = Receive buffer has not overflowed. Clearing a previously set OERR bit (1→0 transition) will reset

the receiver buffer and the UxRSR to the empty state.

bit 0 URXDA: Receive Buffer Data Available bit (read-only)

1 = Receive buffer has data, at least one more character can be read

0 = Receive buffer is em pty

Note 1: Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled

(IREN = 1).

PIC24H

NOTES:

PIC24H

18.0 ENHANCED CAN MODULE

18.1 Overview

The Enhanced Controller Area Network (ECAN) mod-

ule is a serial interface, useful for communicating with

other CAN modules or microcontroller devices. This

interface/protocol was designed to allow communica-

tions within noisy environments. The PIC24H devices

contain up to two ECAN modules.

The CAN module is a communication controller imple-

menting the CAN 2.0 A/B protocol, as defined in the

BOSCH specification. The module will suppo rt CAN 1.2,

CAN 2.0A, CAN 2.0B Passive and CAN 2.0B Active

versions of the protocol. The module implementation is

a full CAN system. The CAN specification is not covered

within this data sheet. The reader may refer to the

BOSCH CAN specification for further det ails .

The module features are as follows:

• Implementation of the CAN protocol, CAN 1.2,

CAN 2.0A and CAN 2 .0B

• Standard and extended data frames

• 0-8 bytes data length

• Programmable bit rate up to 1 Mbit/sec

• Automatic response to remote transmission

requests

• Up to 8 transmit buffers with application specified

priori tization and abort c apabilit y (each buf fer may

contain up to 8 bytes of data)

• Up to 32 rec eiv e b uffers (each buffer may contain

up to 8 bytes of data)

• Up to 16 full (standard/extended identifier)

acceptance filters

• 3 full acceptance filter masks

• DeviceNet™ addressing support

• Programmable wake-up functionality with

integra ted low-pass filter

• Programm abl e Loopba ck m ode su pp orts self-test

operation

• Signaling via interrupt capabilities for all CAN

receiver and transmitter error states

• Programmable clock source

• Programmable link to input capture module (IC2

for both CAN1 and CAN2) for time-stamping and

netw ork synchronizati on

• Low-power Sleep and Idle mode

The CAN bus modu le consist s of a protocol engi ne and

message buffering/control. The CAN protocol engine

handles all functions for receiving and transmitting

messages on the CAN bus. Messages are transmitted

by first loading the appropriate data registers. Status

and errors can be checked by reading the appropriate

registers. Any message detected on the CAN bus is

checked for errors and then matched against filters to

see if it should be received and stored in one of the

receive registers.

18.2 Frame Types

The CAN module transmits various types of frames

which include data messages, remote transmission

requests and as other frames that are automatically

generated for control purposes. The following frame

types are supported:

• Standard Data Frame:

A standard data frame is generated by a node

when the node wishes to transmit data. It includes

an 11-bit standard identifier (SID) but not an 18-bit

extended identifier (EID).

• Extended Data Frame:

An extended data frame is similar to a standard

data frame but includes an extended identifier as

well.

• Remote Frame:

It is possible for a destination node to request the

data from the source. For this purpose, the

destination node sends a remote frame with an

identifier that matches the ident ifier of the required

data frame. Th e appro priate dat a sou rce n ode w ill

then send a data frame as a response to this

remote request.

• Error Frame:

An error frame is generated by any node that

detect s a bus error . An error frame consist s of two

fields: an error flag field and an error delimiter

field.

• Overload Frame:

An overl oad fram e can b e generat ed by a node a s

a result of two conditions. First, the node detects

a domi nant bit durin g interframe space w hich is an

illegal condition. Second, due to internal condi-

tions, the node is not yet able to start reception of

the next message. A node may generate a maxi-

mum of 2 s equ ent ial ove rload frame s to dela y th e

start of the next message.

• Inter frame Space:

Interframe space separates a proceeding frame

(of wha tever type ) from a follo wing da ta or remo te

frame.

Note: This data sheet summarizes the features

of this group of PIC24H devices. It is not

intende d to be a comprehe nsive referenc e

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

PIC24H

FIGURE 18-1: ECAN™ MODULE BLOCK

DIAGRAM

Message Assembly

CAN Protocol

Engine

CiTX(1)

Buffer

CiRX(1)

RXF14 Filter

RXF13 Filter

RXF12 Filter

RXF11 Filter

RXF10 Filter

RXF9 Filter

RXF8 Filter

RXF7 Filter

RXF6 Filter

RXF5 Filter

RXF4 Filter

RXF3 Filter

RXF2 Filter

RXF1 Filter

RXF0 Filter

Transmit Byte

Sequencer

RXM1 Mask

RXM0 Mask

Control

Configuration

Logic

CPU

Bus

Interrupts

TRB0 TX/RX Buffer Control Register

DMA Controller

RXF15 Filter

RXM2 Mask

TRB7 TX/RX Buffer Control Register

TRB6 TX/RX Buffer Control Register

TRB5 TX/RX Buffer Control Register

TRB4 TX/RX Buffer Control Register

TRB3 TX/RX Buffer Control Register

TRB2 TX/RX Buffer Control Register

TRB1 TX/RX Buffer Control Register

Note 1: i = 1 or 2 refers to a particular ECAN modu le (ECAN1 or ECAN 2).

PIC24H

18.3 Modes of Operation

The CAN module can operate in one of several operation

modes selected by the user . These modes include:

• Initialization Mode

• Disable Mode

• Normal Operation Mode

• List en On ly Mode

• List en All Me ss age s Mode

• Loop bac k Mo de

Modes are requested by setting the REQOP<2:0> bits

(CiCTRL1 < 10: 8>). Entry int o a mode is Ackn ow le dge d

by monitoring the OPMODE<2:0> bits

(CiCTRL1<7:5>). T he module will not change th e mode

and the OPMODE bits until a change in mode is

acceptable, generally during bus Idle time, which is

defined as at least 11 consecutive reces siv e bits.

18.3.1 INITIALIZATION MODE

In the Ini tialization mode, the module will not tra nsmit or

receive. The error counters are cleared and the inter-

rupt flags remain unchanged. The programmer will

have access to Configuration registers that are access

restricted in other modes. The module will protect the

user from accidentally violating the CAN protocol

through p rogramming er rors. All registe rs which contro l

the configuration of the module can not be modified

while the module is on-line. The CAN module will not

be allowed to enter the Configuration mode while a

transmission is taking place. The Configuration mode

serves as a lock to protect the following registers.

• All Module Control Registers

• Baud Rate and Interrupt Configuration Registers

• Bus Timing Registers

• Identifier Acceptance Filter Registers

• Identifier Acceptance Mask Registers

18.3.2 DISABLE MODE

In Disable mode, the module will not transmit or

receive . The mo dule has the ability to set the W AKIF b it

due to bus activity, however, any p ending inte rrupts w ill

remain and the error counters will retain their value.

If the REQOP<2:0> bits (CiCTRL1<10:8>) = 001, the

module will enter the Module Disable mode. If the module

is activ e, the m odule wil l wait for 11 reces sive bi ts on the

CAN bus, detect that condition as an Idle bus, then

accept the module disable command. When the

OPMODE<2:0> bits (CiCTRL1<7:5>) = 001, that indi-

cates whether the module successfully went into Module

Disable mode. The I/O pins will revert to normal I/O

function when the mod ule is in the Module Disable mode.

The module can be programmed to apply a low-pass

filter fun ction to the Ci RX inp ut line whil e the m odule or

the CPU is in Sleep mode. The WAKFIL bit

(CiCFG2<14>) enables or disables the filter.

18.3.3 NORMAL OPERATION MODE

Normal Operation mode is selected when

REQOP<2:0> = 000. In this mode, the module is

activated and the I/O pins will assume the CAN bus

functions. The module will transmit and receive CAN

bus messages via the CiTX and CiRX pins.

18.3.4 LISTEN ONLY MODE

If the Li st en O nl y mode is acti va ted , the module on th e

CAN bus is passive. The transmitter buffers revert to

the port I/O function. The receive pins remain inputs.

For the rec eiv er, n o e rror flags or Ac kn ow le dge s ign al s

are sent. The error counters are deactivated in this

state. The Listen Only mode can be used for detecting

the baud rate on the CAN bus. To use this, it is neces-

sary that there are at least two further nodes that

communicate with each other.

18.3.5 LISTEN ALL MESS AGE S MODE

The module can be set to ignore all errors and receive

any message. The Listen All Messages mode is acti-

vated by setting REQOP<2:0> = ‘111’. In this mode,

the data wh ic h i s in th e m es sa ge a ss embly buf f er, until

the time an error occurred, is copied in the receive

buffer and can be read via the CPU interface.

18.3.6 LOOPBACK MODE

If the Loopbac k mode is activ ated, the mo dule will con-

nect the internal transmit signal to the internal receive

signal at the module boundary. The transmit and

receive pins revert to their port I/O function.

18.4 Message Reception

18.4.1 RECEIVE BUFFERS

The CAN bus module has up to 32 receive buffers,

located in DMA RAM. The first 8 buffers need to be

configured as receive buffers by clearing the

corresponding TX/RX buffer selection (TXENn) bit in a

CiTRmnCON register. The overall size of the CAN

buffer are a in DMA RAM is selec tabl e by the us er and

is defined by the DMABS<2:0> bits

(CiFCTRL<15:13>). The first 16 buffers can be

assigned to receive filters, while the rest can be used

only as a FIFO buffer.

Note: Typically, if the CAN module is allowed to

transmit in a particular mode of operation

and a transmission is requested immedi-

ately after the CAN module has been

placed in tha t mode of operati on, the mod-

ule waits for 11 consecutive recessive bits

on the bus before starting transmission. If

the user switches to Disable mode within

this 11 -bi t pe riod , then thi s tr ansm issi on is

aborted and the corresponding TXABT bit

is set and TXREQ bit is cleared.

PIC24H

An additional buffer is always committed to monitoring

the bus for incoming messages. This buffer is called

the Message Assembly Buffer (MAB).

All messages are assembl ed by the MAB and are trans-

ferred to the buf fers only if the acceptance filter criterion

are met. When a message is received, the RBIF flag

(CiINTF<1>) will be set. The user would then need to

inspect the CiVEC and/or CiRXFUL1 register to deter-

mine which filter and buffer caused the interrupt to get

generated. The RBIF bit can only be set by the module

when a message is received. The bit is cleared by the

user when it has completed processing the message in

the buffer. If the RBIE bit is set, an interrupt will be

generated when a messa ge is receiv ed.

18.4.2 FIFO BUFFER MODE

The ECAN modu le p rov ide s FI FO buffer functional ity if

the buf fer pointer for a filter has a value of ‘1111’. In thi s

mode, the results of a hit on that buffer will write to the

next available buffer location within the FIFO.

The CiFCTRL register defines the size of the FIFO. The

FSA<4:0> bits in this register define the start of the

FIFO buffers. The end of the FIFO is defined by the

DMABS<2:0> b its if DM A is enabled . Thus, FIFO sizes

up to 32 buffers are supported.

18.4.3 MESSAGE ACCEPTANC E FILTERS

The me ssage acc eptance filters and masks ar e used to

determine if a message in the message assembly

buffer should be loaded into either of the receive buff-

ers. Once a valid message has been received into the

Message Assembly Buf fer (MAB), the identifier fields of

the message are compared to the filter values. If there

is a match, that message will be loaded into the

appropriate receive buffe r. Each filter is associated with

a buffer pointer (FnBP<3:0>), which is used to link the

filter to one of 16 receive buffers.

The acceptance filter looks at incoming messages for

the IDE bit (CiTRBnSID<0>) to determine how to com-

pare the identifiers. If the IDE bit is clear, the message

is a standard frame and only filters with the EXIDE bit

(CiRXFnSID<3>) clear are compared. If the IDE bit is

set, the m essa ge is an extended fra me, and only fi lter s

with the EXIDE bit set are compared.

18.4.4 MESSAGE ACCEPTANC E FILTER

MASKS

The mask bits e ssential ly determi ne which bit s to appl y

the filter to. If any m as k bit is set to a ze ro, t hen that bit

will automatically be accepted regardless of the filter

bit. There are three programmable acceptance filter

masks associated with the receive buffers. Any of

these thre e masks can be linked to each filte r by select-

ing the desired mask in the FnMSK<1:0> bits in the

appropri ate CiFM SKSELn register.

18.4.5 RECEIVE ERRORS

The CAN module will detect the following receive

errors:

• Cyclic Redundancy Check (CRC) Error

• Bit Stuffing Error

• Invalid Message Rece ive Er ror

These receive errors do not generate an interrupt.

However, the receive error counter is incremented by

one in case one of these errors occur. The RXWAR bit

(CiINTF<9>) indicates that the receive error counter

has reached the CPU warning limit of 96 and an

interrupt is genera ted.

18.4.6 RECEIVE INTERRUPTS

Receive interrupts can be divided into 3 major groups,

each including various conditions that generate

interrupts:

• Receive Interrupt:

A message has been successfully received and

loaded into one of the receive buffers. This inter-

rupt is activated immediately after receiving the

End-of-Frame (EOF) fie ld. Reading the RXnIF flag

will indicate which receive buffer caused the

interrupt.

• Wake-up Interrupt:

The CAN module has woken up from Disable

mode or the device has woken up from Sleep

mode.

• Receive Error Interrupts:

A receive error interrupt will be indicated by the

ERRIF bit. This bit shows that an error condition

occurred. The source of the error can be deter-

mined by checking the bits in the CAN Interrupt

Flag regist er, CiINTF.

- Invalid Message Received:

If any type of error occurred during reception of

the last message, an error will be indicated by

the IVRIF bit.

- Receiver Overrun:

The RBOVIF bit (CiINTF<2>) indicates that an

overrun condition occurred.

- Receiver Warning:

The RXWAR bit indicates that the receive error

counter (RERRCNT<7:0>) has reached the

warning limit of 96.

- Receiver Error Passive:

The RXEP bit indicates that the receive error

counter has exceeded the error passive limit of

127 and the mod ul e h as go ne in to error pa ss iv e

state.

PIC24H

18.5 Message Transmission

18.5.1 TRANSMIT BUFFERS

The CAN module has up to eight transmit buffers,

located in DMA RAM. These 8 buffers need to be con-

figur ed as transmit buf fers by se tting the corres ponding

TX/RX buffer selection (TXENn or TXENm) bit in a

CiTRmnCON register. The overall size of the CAN

buffer are a in DMA RAM is se lec table by th e user and

is defined by the DMABS<2:0> bits

(CiFCTRL<15:13>).

Each tr ansmit buffe r occupies 16 bytes of dat a. Eight of

the bytes are the maximum 8 bytes of the transmitted

message. Five bytes hold the standard and extended

identifiers and other message arbitration information.

The last byte is unused.

18.5.2 TRANS MI T MESSAGE PRIORITY

Transmit priority is a prioritization within each node of

the pending transmittable messages. There are four

levels of transmit priority. If the TXnPRI<1:0> bits (in

CiTRmn CON) for a p articular message bu ffer are s et to

‘11’, that buffer has the highest priority. If the

TXnPRI<1:0> bits for a particular message buffer are

set to ‘10’ or ‘01’ , th at b uffer has an in termedi ate pri or-

ity. If the TXnPRI<1:0> bits for a particular message

buffe r are ‘00’, that buffer has the lowest priority. If two

or more pen ding mes sages hav e th e same priority, the

messa ges are transmi tted in decrea sing order of buff er

index.

18.5.3 TRANSMISSION SEQUENCE

To initiate transmission of the message, the TXREQn

bit (in C iTRmnCON) m ust be set. T he CAN bus mo dule

resolves any t im ing c onf lic ts between th e set ting of th e

TXREQn bit and the Start-of-Frame (SOF), ensuring

that if the priority was changed, it is resolved correctly

before the SOF occurs. When TXREQn is set, the

TXABTn, TXLARBn and TXERRn flag bits are

automatically cleared.

Sett ing t h e TXRE Q n b i t si mp l y f l ags a me ss ag e buffe r

as enqueued for transmission. When the module

detects an available bus, it begins transmitting the

message which has been determined to have the

highest priority.

If the transmission completes successfully on the first

attempt, the TXREQn bit is cleared automatically and

an interrupt is generated if TXnIE was set.

If the mes sa ge transmi ss io n fails, on e of th e error con-

dition flags will be set and the TXREQn bit will remain

set, indicating that the message is still pending for

transmission. If the message encountered an error

condition during the transmission attempt, the TXERRn

bit will be set and the error condition may cause an

interrupt. If the message loses arbitration during the

transmission attempt, the TXLARBn bit is set. No

interrupt is generated to signal the loss of arbitration.

18.5.4 AUTOMATIC PROCESSING OF

REMOTE TRANSMISSION

REQUESTS

If the RTRENn bit (in the CiTRmnCON register) for a

particular transmit buffer is set, the hardware automat-

ically transmits the data in that buffer in response to

remote transmission requests matching the filter that

points to that particular buffer. The user does not need

to manually initiate a transmission in this case.

18.5.5 ABORTING MESSAGE

TRANSMISSION

The system can also abort a message by clearing the

TXREQ bit associated with each message buffer. Set-

ting the ABAT bit (CiCTRL1<12>) will request an abort

of all pending messages. If the message has not yet

started transmission, or if the message started but is

interrupted by loss of arbitration or an error, the abort

will be processed. The abort is indicated when the

module sets the TXABT bit and the TXnIF flag is not

automatically set.

18.5.6 TRANSMISSION ERRORS

The CAN module wil l dete ct the foll owing transm iss io n

errors:

• Acknowledge Error

• Form Error

• Bit Error

These transmission errors will not necessarily generate

an inte rrupt, b ut are indi cated by t he tra nsmis sion error

counter. However, each of these errors will cause the

transmission error counter to be incremented by one.

Once the value of the error counter exceeds the value

of 96, the ERRIF (CiINTF<5>) and the TXWAR bit

(CiINTF<10>) are set. Once the value of the error

counter exceeds the value of 96, an interrupt is

generated and the TXWAR bit in the Interrupt Flag

PIC24H

18.5.7 TRANSMI T INTERRUPTS

T ransmit interrupts can be divided into 2 major groups,

each including various conditions that generate

interrupts:

• Transmit Interrupt:

At least one of the three transmit buffers is empty

(not scheduled) and can be loaded to schedule a

message for transmission. Reading the TXnIF

flags will ind icate which transmit buf fer is available

and caused the interrupt.

• Transmit Error Interrupts:

A transmission error interrupt will be indicated by

the ERRIF flag. T his fl ag show s that an erro r co n-

dition occurred. The source of the error can be

determi ned by check ing the error fl ags in the CAN

Interrupt Flag register, CiINTF. The flags in this

- Transmitter Warning Interrupt:

The TXWAR bit indicates that the transmit error

counter has reached the CPU warning limit

of 96.

- Transmitter Error Passive:

The TXEP bit (CiINTF<12>) indicates that the

transmit error counter has exceeded the error

pas siv e lim it of 127 and the modul e has go ne to

error passive state.

- Bus Off:

The TXBO bit (CiINTF<13>) indicates that the

transmit error counter has exceeded 255 and

the module has gone to the bus off state.

18.6 Baud Rate Setting

All nodes on any particular CAN bus must have the

same nomin al bit rate. In ord er to set the baud rate, the

following parameters have to be initialized:

• Syn chronization Jump Width

• Baud Rate Prescaler

• Phase Segments

• Length Determination of Phase Segment 2

• Sample Point

• Propag ati on Segm en t bit s

18.6.1 BIT TI MING

All controllers on the CAN bus must have the same

baud rate and bit length. However, different controllers

are not required to have the same master oscillator

clock. At different clock frequencies of the individual

controllers, the baud rate has to be adjusted by

adjusti ng the num be r of time quan t a in eac h segm en t.

The nomi nal bit time can be though t of as being div ided

into separate non-overlapping time segments. These

segments are shown in Figure 18-2.

• Synchronization Segment (Sync Seg)

• Propagation Time Segment (Prop Seg)

• Phase Segment 1 (Phase1 Seg)

• Phase Segment 2 (Phase2 Seg)

The time segments and also the nominal bit time are

made up of integer units of time called time quanta or

TQ. By definition, the nominal bit time has a minimum

of 8 TQ and a maximum of 25 TQ. Also, by definition,

the minimum nominal bit time is 1 μsec corresponding

to a maximum bit rate of 1 MHz.

FIGURE 18-2: ECAN™ MODULE BIT TIMING

Note: Both ECAN1 and ECAN2 can trigger a

DMA data transfer. If C1TX, C1RX, C2TX

or C2RX is selected as a DMA IRQ

source, a DMA transfer occurs when the

C1TXIF, C1RXIF, C2TXIF or C2RXIF bit

gets set as a result of an ECAN1 or

ECAN2 transmission or reception.

Input Signal

Sync Prop

Segment Phase

Segment 1 Phase

Segment 2 Sync

Sample Point

PIC24H

18.6.2 PRESCALER SETTING

There is a programmable prescaler with integral values

ranging from 1 to 64, in addition to a fixed divide-by-2

for clock generation. The time quantum (TQ) is a fixed

unit of time derived from the oscillator period and is

given by Equation 18-1.

EQUATION 18-1: TIME QUANTUM FOR

CLOCK GENERATION

18.6.3 PROPAGATION SEGMENT

This p art of t he bit time is u sed to com pensa te phy sica l

delay ti me s withi n the ne twork . These delay times co n-

sist of the signal propagation time on the bus line and

the inte rnal delay time of the no de s. The Prop Seg can

be programmed from 1 TQ to 8 TQ by setting the

PRSEG<2:0> bits (CiCFG2<2: 0>).

18.6.4 PHASE SEGMENTS

The phase segments are used to optimally locate the

sampling of the received bit within the transmitted bit

time. The sampling point is between Phase1 Seg and

Phase2 Seg. These segmen ts are lengthen ed or sho rt-

ened by res ynchronizatio n. The end of the Phase1 Seg

determines the sampling point within a bit period. The

segment is programmable from 1TQ to 8 TQ. Phase2

Seg provides delay to the next transmitted data transi-

tion. Th e segment is programmable from 1 TQ to 8 TQ,

or it may be defined to be equal to the greater of

Phase1 Seg or the in form ati on pro ce ssin g tim e (2 TQ).

The Phase1 Seg is initialized by setting bits

SEG1PH<2:0> (CiCFG2<5:3>) and Phase2 Seg is

initialized by setting SEG2PH<2:0> (CiCFG2<10:8>).

The following requirement must be fulfille d while setting

the lengths of the phase segments :

Prop Seg + Phase1 Seg ≥ Phase2 Seg

18.6.5 SAMPLE POINT

The sample point is the point of time at which the bus

level is read and interpreted as the value of that respec-

tive bi t. The lo ca tion is at the en d of Phas e1 Seg . I f th e

bit timin g is slow and cont ains many TQ, it is pos sible to

specify multiple sampling of the bus line at the sample

point. The level determin ed by the CAN bus the n corre-

sponds to the resu lt from the ma jo rity deci si on of three

values. The majority samples are taken at the sample

point and twice before with a distance of TQ/2. The

CAN module allows the user to choose between sam-

pling three times at the same point or once at the same

point, by settin g or clea ring the SAM bit (CiCFG 2<6>).

Typically, the sampling of the bit should take place at

about 60-70% through the bit time, depending on the

system parameters.

18.6.6 SYNCHRONIZATION

To compensate for phase shifts between the oscillator

frequencies of the different bus stations, each CAN

controller must be able to synchronize to the relevant

signal edge of the incoming signal. When an edge in

the transmitted data is detected, the logic will compare

the loc ation of the edge t o th e expec ted tim e (Syn chro-

nous Segment). The circuit will then adjust the values

of Phase1 Seg and Phase2 Seg. There are two

mechanisms used to synchronize.

18.6.6. 1 Hard Sync hr oni za tio n

Hard synchronization is only done whenever there is a

‘recessive’ to ‘dominant’ edge during bus Idle, indicat-

ing the start of a message. After hard synchronization,

the bit time counters are restarted with the Sync Seg.

Hard synchronization forces the edge which has

caused the hard synchronization to lie within the

synchronization segment of the restarted bit time. If a

hard synchronization is done, there will not be a

resynchronization within that bit time.

18.6.6.2 Resynchronization

As a result of resynchronization, Phase1 Seg may be

lengthened or Phase2 Seg may be shortened. The

amount of lengthening or shortening of the phase

buffer segment has an upper boundary known as the

synchronization jump width, and is specified by the

SJW<1:0> bits (CiCFG1<7:6>). The value of the syn-

chronization jump width will be added to Phase1 Seg or

subtracted from Phase2 Seg. The resynchronization

jump width is programmable between 1TQ and 4 TQ.

The following requirement must be fulfilled while setting

the SJW<1:0> bits:

Phase2 Seg > Synchronization Jump Width

Note: FCAN must not exceed 40 MHz. If

CANCKS = 0, then FCY must not exceed

20 MHz.

TQ = 2 (BRP<5:0> + 1)/FCAN

Note: In the re gister des cripti ons that fo llow , ‘i’ in

the r egister ident ifier de notes th e specif ic

ECAN module (ECAN1 or ECAN2).

‘n’ in the register identifier denotes the

buffer, filter or mask number.

‘m’ in the register identifier denotes the

word number within a particular CAN data

field.

PIC24H

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0

—— CSIDL ABAT CANCKS REQOP<2:0>

bit 15 bit 8

R-1 R-0 R-0 U-0 R/W-0 U-0 U-0 R/W-0

OPMODE<2:0> — CANCAP ——WIN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13 CSIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

bit 12 ABAT: Abort All Pending Transmissions bit

Signal all transmit buffers to abort transmission. Module will clear this bit when all transmissions

are aborted

bit 11 CANCKS: CAN Master Clock Select bit

1 = CAN FCAN clock is FCY

0 = CAN FCAN clock is FOSC

bit 10-8 REQOP<2:0>: Request Operation Mode bits

000 = Set Normal Operation mode

001 = Set Disable mode

010 = Set Loopback mode

011 = Set Listen Only Mode

100 = Set Configuration mode

101 = Reserved – do not us e

110 = Reserved – do not us e

111 = Set Listen All Messages mode

bit 7-5 OPMODE<2:0>: Opera tion Mode bits

000 = Module is in Normal Operation mode

001 = Module is in Disable mode

010 = Module is in Loopback mode

011 = Module is in Listen Only mode

100 = Module is in Configuration mode

101 = Reserved

110 = Reserved

111 = Module is in Listen All Messages mode

bit 4 Unimplemented: Read as ‘0’

bit 3 CANCAP: CAN Message Receive Timer Capture Event Enable bit

1 = Enable input capture based on CAN message receive

0 = Disable CAN capture

bit 2-1 Unimplemented: Read as ‘0’

bit 0 WIN: SFR Map Window Select bit

1 = Use filter window

0 = Use buffer window

PIC24H

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0

— — — DNCNT<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-5 Unimplemented: Read as ‘0’

bit 4-0 DNCNT<4:0>: DeviceNet™ Filter Bit Number bits

10010-11111 = Invalid selection

10001 = Compare up to data byte 3, bit 6 with EID<17>

....

00001 = Compare up to data byte 1, bit 7 with EID<0>

00000 = Do not compare data bytes

PIC24H

U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0

— — —FILHIT<4:0>

bit 15 bit 8

U-0 R-1 R-0 R-0 R-0 R-0 R-0 R-0

— ICODE<6:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 Unimplemented: Read as ‘0’

bit 12-8 FILHIT<4:0>: Filter Hit Number bits

10000-11111 = Reserved

01111 = Filter 15

....

00001 = Filter 1

00000 = Filter 0

bit 7 Unimplemented: Read as ‘0’

bit 6-0 ICODE<6:0>: Interrupt Flag Code bits

1000101-1111111 = Reserved

1000100 = FIFO almost full interrupt

1000011 = Receiver overfl ow interrupt

1000010 = Wake-up interrupt

1000001 = Error interrupt

1000000 = No interrupt

0010000-0111111 = Reserved

0001111 = RB15 buffer Interrupt

....

0001001 = RB9 buffer interrupt

0001000 = RB8 buffer interrupt

0000111 = TRB7 buffer interrupt

0000110 = TRB6 buffer interrupt

0000101 = TRB5 buffer interrupt

0000100 = TRB4 buffer interrupt

0000011 = TRB3 buffer interrupt

0000010 = TRB2 buffer interrupt

0000001 = TRB1 buffer interrupt

0000000 = TRB0 Buffer interrupt

PIC24H

R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0

DMABS<2:0> — — — — —

bit 15 bit 8

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — FSA<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 DMABS<2:0>: DMA Buffer Size bits

111 = Reserved

110 = 32 buffers in DMA RAM

101 = 24 buffers in DMA RAM

100 = 16 buffers in DMA RAM

011 = 12 buffers in DMA RAM

010 = 8 buffers in DMA RAM

001 = 6 buffers in DMA RAM

000 = 4 buffers in DMA RAM

bit 12-5 Unimplemented: Read as ‘0’

bit 4-0 FSA<4:0>: FIFO Area Starts with Buffer bits

11111 = RB31 buffer

11110 = RB30 buffer

....

00001 = TRB1 buffer

00000 = TRB0 buffer

PIC24H

U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0

—— FBP<5:0>

bit 15 bit 8

U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0

—— FNRB<5:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13-8 FBP<5:0>: FIFO Write Buffer Pointer bits

011111 = RB31 buffer

011110 = RB30 buffer

....

000001 = TRB1 buffer

000000 = TRB0 buffer

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 FNRB<5:0>: FIFO Next Read Buffer Pointer bits

011111 = RB31 buffer

011110 = RB30 buffer

....

000001 = TRB1 buffer

000000 = TRB0 buffer

PIC24H

U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0

—— TXBO TXBP RXBP TXWAR RXWAR EWARN

bit 15 bit 8

R/C-0 R/C-0 R/C-0 U-0 R/C-0 R/C-0 R/C-0 R/C-0

IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13 TXBO: Transmitter in Error State Bus Off bit

bit 12 TXBP: Transmitter in Error State Bus Passive bit

bit 11 RXBP: Receiver in Error State Bus Passive bit

bit 10 TXWAR: Transmitter in Error State Warning bit

bit 9 RXWAR: Receiver in Error State Warning bit

bit 8 EWARN: Transmitter or Receiver in Error State Warning bit

bit 7 IVRIF: Invalid Message Received Interrupt Flag bit

bit 6 WAKIF: Bus Wake-up Activity Interrupt Flag bit

bit 5 ERRIF: Error Interrupt Flag bit (multiple sources in CiINTF<13:8> register)

bit 4 Unimplemented: Read as ‘0’

bit 3 FIFOIF: FIFO Almost Full Interrupt Flag bit

bit 2 RBOVIF: RX Buffer Overflow Interrupt Flag bit

bit 1 RBIF: RX Buffer Interrupt Flag bit

bit 0 TBIF: TX Buffer Interrupt Flag bit

PIC24H

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 Unimplemented: Read as ‘0’

bit 7 IVRIE: Invalid Message Received Interrupt Enable bit

bit 6 WAKIE: Bus Wake-up Activity Interrupt Flag bit

bit 5 ERRIE: Error Interrupt Enable bit

bit 4 Unimplemented: Read as ‘0’

bit 3 FIFOIE: FIFO Almost Full Interrupt Enable bit

bit 2 RBOVIE: RX Buffer Overflow Interrupt Enable bit

bit 1 RBIE: RX Buffer Interrupt Enable bit

bit 0 TBIE: TX Buffer Interru pt Enab le bit

PIC24H

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

TERRCNT<7:0>

bit 15 bit 8

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

RERRCNT<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 TERRCNT<7:0>: Transmit Error Count bits

bit 7-0 RERRCNT<7:0>: Receive Error Count bits

PIC24H

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SJW<1:0> BRP<5:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 Unimplemented: Read as ‘0’

bit 7-6 SJW<1:0>: Synchron ization Jump Width bits

11 = Length is 4 x TQ

10 = Length is 3 x TQ

01 = Length is 2 x TQ

00 = Length is 1 x TQ

bit 5-0 BRP<5:0>: Baud Rate Prescaler bits

11 1111 = TQ = 2 x 64 x 1/FCAN

00 0010 = TA = 2 x 3 x 1/FCAN

00 0001 = TA = 2 x 2 x 1/FCAN

00 0000 = TQ = 2 x 1 x 1/FCAN

PIC24H

U-0 R/W-x U-0 U-0 U-0 R/W-x R/W-x R/W-x

— WAKFIL — — — SEG2PH<2:0>

bit 15 bit 8

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14 WAKFIL: Select CAN bus Line Filter for Wake-up bit

1 = Use CAN bus line filter for wake-up

0 = CAN bus line filter is not used for wake-up

bit 13-11 Unimplemented: Read as ‘0’

bit 10-8 SEG2PH<2:0>: Phase Buffer Segment 2 bits

111 = Length is 8 x TQ

000 = Length is 1 x TQ

bit 7 SEG2PHTS: Phase Segment 2 Time Select bit

1 = Freely programmable

0 = Maximum of SEG1PH bits or Information Processing Time (IPT), whichever is greater

bit 6 SAM: Sample of the CAN bus Line bit

1 = Bus line is sampled three times at the sample point

0 = Bus line is sampled once at the sample point

bit 5-3 SEG1PH<2:0>: Phase B uffer S egment 1 bits

111 = Length is 8 x TQ

000 = Length is 1 x TQ

bit 2-0 PRSEG<2:0>: Propagation Time Segment bits

111 = Length is 8 x TQ

000 = Length is 1 x TQ

PIC24H

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8

bit 15 bit 8

R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

FLTEN7 FLTEN6 FLTEN5 FLTEN4 FLTEN3 FLTEN2 FLTEN1 FLTEN0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 FLTENn: Enable Filter n to Accept Messages bits

1 = Enable Filter n

0 = Disable Filter n

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

F3BP<3:0> F2BP<3:0>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

F1BP<3:0> F0BP<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-12 F3BP<3:0>: RX Buffer Written when Filter 3 Hits bits

bit 11-8 F2BP<3:0>: RX Buffer Written when Filter 2 Hits bits

bit 7-4 F1BP<3:0>: RX Buffer Written when Filter 1 Hits bits

bit 3-0 F0BP<3:0>: RX Buffer Written when Filter 0 Hits bits

1111 = Filter hits received in RX FIFO buffer

1110 = Filter hits received in RX Buffer 14

....

0001 = Filter hits received in RX Buffer 1

0000 = Filter hits received in RX Buffer 0

PIC24H

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

F7BP<3:0> F6BP<3:0>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

F5BP<3:0> F4BP<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-12 F7BP<3:0>: RX Buffer Written when Filter 7 Hits bits

bit 11-8 F6BP<3:0>: RX Buffer Written when Filter 6 Hits bits

bit 7-4 F5BP<3:0>: RX Buffer Written when Filter 5 Hits bits

bit 3-0 F4BP<3:0>: RX Buffer Written when Filter 4 Hits bits

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

F11BP<3:0> F10BP<3:0>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

F9BP<3:0> F8BP<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-12 F11BP<3:0>: RX Buffer Written when Filter 11 Hits bits

bit 11-8 F10BP<3:0>: RX Buffer Written when Filter 10 Hits bits

bit 7-4 F9BP<3:0>: RX Buffer Written when Filter 9 Hits bits

bit 3-0 F8BP<3:0>: RX Buffer Written when Filter 8 Hits bits

PIC24H

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

F15BP<3:0> F14BP<3:0>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

F13BP<3:0> F12BP<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-12 F15BP<3:0>: RX Buffer Written when Filter 15 Hits bits

bit 11-8 F14BP<3:0>: RX Buffer Written when Filter 14 Hits bits

bit 7-4 F13BP<3:0>: RX Buffer Written when Filter 13 Hits bits

bit 3-0 F12BP<3:0>: RX Buffer Written when Filter 12 Hits bits

PIC24H

(n = 0, 1, ..., 15)

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3

bit 15 bit 8

R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x

SID2 SID1 SID0 — EXIDE —EID17EID16

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-5 SID<10:0>: Standard Identifier bits

1 = Message address bit SIDx must be ‘1’ to match filter

0 = Message address bit SIDx must be ‘0’ to match filter

bit 4 Unimplemented: Read as ‘0’

bit 3 EXIDE: Extended Identifier Enable bit

If MIDE = 1 the n:

1 = Match only messages with extended identifier addresses

0 = Match only messages with standard identifier addresses

If MIDE = 0 the n:

Ignore EXIDE bit.

bit 2 Unimplemented: Read as ‘0’

bit 1-0 EID<17:16>: Extended Identifier bits

1 = Message address bit EIDx must be ‘1’ to match filter

0 = Message address bit EIDx must be ‘0’ to match filter

(n = 0, 1, ..., 15)

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8

bit 15 bit 8

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 EID<15:0>: Extended Identifier bits

1 = Message address bit EIDx must be ‘1’ to match filter

0 = Message address bit EIDx must be ‘0’ to match filter

PIC24H

ECAN MO DULE

FILTER 7-0 MASK SELECTION REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

F7MSK<1:0> F6MSK<1:0> F5MSK<1:0> F4MSK<1:0>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

F3MSK<1:0> F2MSK<1:0> F1MSK<1:0> F0MSK<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 F7MSK<1:0>: Mask Source for Filter 7 bit

bit 13-12 F6MSK<1:0>: Mask Source for Filter 6 bit

bit 11-10 F5MSK<1:0>: Mask Source for Filter 5 bit

bit 9-8 F4MSK<1:0>: Mask Source for Filter 4 bit

bit 7-6 F3MSK<1:0>: Mask Source for Filter 3 bit

bit 5-4 F2MSK<1:0>: Mask Source for Filter 2 bit

bit 3-2 F1MSK<1:0>: Mask Source for Filter 1 bit

bit 1-0 F0MSK<1:0>: Mask Source for Filter 0 bit

11 = No mask

10 = Acceptance Mask 2 registers contain mask

01 = Acceptance Mask 1 registers contain mask

00 = Acceptance Mask 0 registers contain mask

PIC24H

ECAN MODULE

ACCEPTANCE FILTER MASK n STANDARD

IDENTIFIER

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3

bit 15 bit 8

R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x

SID2 SID1 SID0 —MIDE —EID17EID16

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-5 SID<10:0>: Standard Identifier bits

1 = Include bit SIDx in filter comparison

0 = Bit SIDx is don’t care in filter comparison

bit 4 Unimplemented: Read as ‘0’

bit 3 MIDE: Identifier Receive Mode bit

1 = Match only message types (standard or extended address) that correspond to EXIDE bit in filter

0 = Match either standard or extended address message if filters match

(i.e., if (Filter SID) = (Message SID) or if (Filter SID/EID) = (Message SID/EID))

bit 2 Unimplemented: Read as ‘0’

bit 1-0 EID<17:16>: Extended Identifier bits

1 = Include bit EIDx in filter comparison

0 = Bit EIDx is don’t care in filter comparison

ECAN TECHNOLOGY

ACCEPTANCE FILTER MASK n EXTENDED

IDENTIFIER

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8

bit 15 bit 8

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 EID<15:0>: Extended Identifier bits

1 = Include bit EIDx in filter comparison

0 = Bit EIDx is don’t care in filter comparison

PIC24H

R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0

RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8

bit 15 bit 8

R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0

RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 RXFUL<15:0>: Receive Buffer n Full bits

1 = Buffer is full (set by module)

0 = Buffer is empty (clear by application software)

R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0

RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24

bit 15 bit 8

R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0

RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 RXFUL<31:16>: Receive Buffer n Full bits

1 = Buffer is full (set by module)

0 = Buffer is empty (clear by application software)

PIC24H

R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0

RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8

bit 15 bit 8

R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0

RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 RXOVF<15:0>: Receive Buffer n Overflow bits

1 = Module pointed a write to a full buffer (set by module)

0 = Overflow is clea red (cl ear by app lic at ion software )

R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0

RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24

bit 15 bit 8

R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0

RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 RXOVF<31:16>: Receive Buffer n Overflow bits

1 = Module pointed a write to a full buffer (set by module)

0 = Overflow is clea red (cl ear by app lic at ion software )

PIC24H

REGIST ER 18 -25: CiTRmn CON: ECA N M ODULE

TX/RX BU FFER m CO NTRO L RE GISTER

(m = 0,2,4,6; n = 1,3,5,7)

R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

TXENn TXABTn TXLARBn TXERRn TXREQn RTRENn TXnPRI<1:0>

bit 15 bit 8

R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

TXENm TXABTm(1) TXLARBm(1) TXERRm(1) TXREQm RTRENm TXmPRI<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 See Definition for Bits 7-0, Controls Buffer n

bit 7 TXENm: TX/RX Buffer Selection bit

1 = Buffer TRBn is a transmit buffe r

0 = Buffer TRBn is a receive buffer

bit 6 TXABTm: Message Aborted bit(1)

1 = Message was aborted

0 = Message completed transm ission successfully

bit 5 TXLARBm: Message Lost Arbitration bit(1)

1 = Message lost arbitration while being sent

0 = Message did not lose arbitration while being sent

bit 4 TXERRm: Error Detected During Transmission bit(1)

1 = A bus error occurred while the message was being sent

0 = A bus error did not occur while t he message was being sent

bit 3 TXREQm: Message Send Request bit

Setting this bit to ‘1’ requests sending a message. The bit will automatically clear when the message

is successfully sent. Clearing the bit to ‘0’ while set will request a message abort.

bit 2 RTRENm: Auto-Remote Transmit Enable bit

1 = When a remote transmit is received, TXREQ will be set

0 = When a remote transmit is received, TXREQ will be unaffected

bit 1-0 TXmPRI<1:0>: Message Transmission Priority bits

11 = Highest message priority

10 = High intermediate message priority

01 = Low intermediate message priority

00 = Lowest message priority

Note 1: This bit is cleared when TXREQ is set.

PIC24H

Note: The buffers, SID, EID, DLC, Data Field and Receive Status registers are stored in DMA RAM. These are

not Special Function Registers.

ECAN MODULE

BUFFER n STANDARD IDENTIFIER

(n = 0, 1, ..., 31)

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x

— — — SID10 SID9 SID8 SID7 SID6

bit 15 bit 8

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

SID5 SID4 SID3 SID2 SID1 SID0 SRR IDE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 Unimplemented: Read as ‘0’

bit 12-2 SID<10:0>: Standard Identifier bits

bit 1 SRR: Substitute Remote Request bit

1 = Message will request remote transmission

0 = Normal message

bit 0 IDE: Extended Identifier bit

1 = Message will transm it ext end ed identifie r

0 = Message will transm it st a ndard identif ier

ECAN MODULE

BUFFER n EXTENDED IDENTIFIER

(n = 0, 1, ..., 31)

U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x

— — — — EID17 EID16 EID15 EID14

bit 15 bit 8

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-12 Unimplemented: Read as ‘0’

bit 11-0 EID<17:6>: Extended Identifier bits

PIC24H

(n = 0, 1, ..., 31)

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EID5 EID4 EID3 EID2 EID1 EID0 RTR RB1

bit 15 bit 8

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x

— — — RB0 DLC3 DLC2 DLC1 DLC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-10 EID<5:0>: Extended Identifier bits

bit 9 RTR: Remote Transmission Request bit

1 = Message will request remote transmission

0 = Normal message

bit 8 RB1: Reserved Bit 1

User must set this bit to ‘0’ per CAN protocol.

bit 7-5 Unimplemented: Read as ‘0’

bit 4 RB0: Reserved Bit 0

User must set this bit to ‘0’ per CAN protocol.

bit 3-0 DLC<3:0>: Data Length Code bits

(n = 0, 1, ..., 31 ; m = 0, 1, ..., 7 )

(1)

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

TRBnDm7 TRBnDm6 TRBnDm5 TRBnDm4 TRBnDm3 TRBnDm2 TRBnDm1 TRBnDm0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 TRnDm<7:0>: Data Fiel d Buffe r ‘n’ Byte ‘m’ bits

Note 1: The Most Significant Byte contains byte (m + 1) of the buffer.

PIC24H

(n = 0, 1, ..., 31)

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x

— — — FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 Unimplemented: Read as ‘0’

bit 12-8 FILHIT<4:0>: Filter Hit Code bits (only written by module for receive buffers, unused for transmit buffers)

Encodes number of filter that resulted in writing this buffer.

bit 7-0 Unimplemented: Read as ‘0’

PIC24H

NOTES:

PIC24H

19.0 10-BIT/12-BIT A/D CONVERTER

The PIC24 H devices have up to 32 A/D input ch annels.

These devices also have up to 2 A/D converter mod-

ules (AD Cx, where ‘x’ = 1 or 2), ea ch with it s own set of

Special Function Registers.

The AD12B bit (ADxCON1<10>) allows each of the

A/D modules to be configured by the user as either a

10-bit, 4-sample/hold A/D (default configuration) or a

12-bit, 1-sample/hold A/D.

19.1 Key Features

The 10-bit A/D configuration has the following key

features:

• Successive Approximation (SAR) conversion

• Conversion speeds of up to 1.1 Msps

• Up to 32 analog input pins

• External voltage reference input pins

• Simultaneous sampling of up to four analog input

pins

• Automatic Channel Scan mode

• Selectable conversion trigger source

• Selectable Buffer Fill modes

• Four result alignment options (signed/unsigned,

fractional/integer)

• Operati on duri ng CP U Sleep and Idle mode s

The 12-bit A/D configuration supports all the above

features, except:

• In the 12-bit configuration, conversion speeds of

up to 500 ksps are supported

• There i s only 1 sample/hold amplifier in the 12-bit

configuration, so simultaneous sampling of

multiple channels is not supported.

Depending on the pa rticular device p inout, the A/D con-

verter can have up to 32 analog input pins, designated

AN0 through AN31. In addition, there are two analog

input pins for external voltage reference connections.

These voltage reference inputs may be shared with

other analog input pins. The actual number of analog

input pins and external voltage reference input config-

uration will depend on the specific device. Refer to the

device data sheet for further details.

A block diagram of the A/D converter is shown in

Figure 19-1.

19.2 A/D Initialization

The foll owing c onfigurati on step s shoul d be perfo rmed.

1. Configure the A/D module:

a) Select port pins as analog inputs

(ADxPCFGH <15:0> or ADxP CFG L<15:0>)

b) Select voltage reference source to match

expected range on analog inputs

(ADxCON2<15:13>)

c) Select the analog conversion clock to

match desired data rate with processor

clock (ADxCON3 <5:0>)

d) Determine how many S/H channels will

be used (ADxCON2<9:8> and

ADxPCFGH<15:0> or ADxPCFGL<15:0>)

e) Select the appropriate sample/conversion

sequence (ADxCON1<7:5> and

ADxCON3<12:8>)

f) Select how conversion results are

presented in the buffer (ADxCON1<9:8>)

g) Turn on A/D module (ADxCON1<15>)

2. Configure A/D interrupt (if required):

a) Clear the ADxIF bit

b) Select A/D interrupt priority

19.3 ADC and DMA

If more than one conversion result needs to be buf fered

before triggering an interrupt, DMA data transfers can

be used . Both ADC1 and ADC2 can trigger a DM A data

transfer. If ADC1 or ADC2 is selected as the DMA IRQ

source, a DMA transfer occurs when the AD1IF or

AD2IF bit gets set as a result of an ADC1 or ADC2

sample conversion sequence.

The SMPI<3:0> bits (ADxCON2<5:2>) are used to

select how often the DMA RAM buffer pointer is

incremented.

The ADDMABM bit (ADxCON1<12>) determines how

the conversion results are filled in the DMA RAM buffer

area being used for ADC. If this bit is set, DMA buffers

are written in the order of conversion. The module will

provide an address to the DMA channel that is the

same as the address used for the non-DMA

stand-alone buffer. If the ADDMABM bit is cleared,

then DMA buffers are written in Scatter/Gather mode.

The modu le will provide a sc atter/gathe r addres s to the

DMA c hannel , based o n the in dex of t he anal og input

and the size of the DMA buffer.

Note: This data sheet summarizes the features

of this group of PIC24H devices. It is not

intende d to be a comprehe nsive referenc e

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

Note: The A/D module needs to be disabled

before modifying the AD12B bit.

PIC24H

FIGURE 19-1: ADC1 MODULE BLOCK DIAGRAM

S/H

Conversion Conversion Logic

VREF+(1)

AVSS

AVDD

ADC1

Data Format

16-bit

ADC Output

Bus Interface

00000

00101

00111

01001

11110

11111

00001

00010

00011

00100

00110

01000

01010

01011

AN30

AN31

AN8

AN9

AN10

AN11

AN2

AN4

AN7

AN0

AN3

AN1

AN5

CH1(2)

CH2(2)

CH3(2)

CH0

AN5

AN2

AN11

AN8

VREF-

AN4

AN1

AN10

AN7

VREF-

AN3

AN0

AN9

AN6

VREF-

AN1

VREF-

VREF-(1)

Sample/Sequence

Control

Sample

CH1,CH2,

CH3,CH0

Input MUX

Control

Input

Switches

S/H

AN6

Buffer

Result

Note 1: VREF+, VREF- inputs may be multiplexed with other analog inputs. See device data sheet for details.

2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.

PIC24H

FIGURE 19-2: ADC2 MODULE BLOCK DIAGRAM(1)

S/H

Conversion Conversion Logic

VREF+(2)

AVSS

AVDD

ADC2

Data Format

16-bit

ADC Output

Bus Interface

00000

00101

00111

01001

11110

11111

00001

00010

00011

00100

00110

01000

01010

01011

AN14

AN15

AN8

AN9

AN10

AN11

AN2

AN4

AN7

AN0

AN3

AN1

AN5

CH1(3)

CH2(3)

CH3(3)

CH0

AN5

AN2

AN11

AN8

VREF-

AN4

AN1

AN10

AN7

VREF-

AN3

AN0

AN9

AN6

VREF-

AN1

VREF-

VREF-(2)

Sample/Sequence

Control

Sample

CH1,CH2,

CH3,CH0

Input MUX

Control

Input

Switches

S/H

AN6

Buffer

Result

Note 1: On devices with two ADC modules, AN0-AN15 can be read by either ADC1, ADC2 or both ADCs.

2: VREF+, VREF- inputs may be multiplexed with other analog inputs. See device data sheet for details.

3: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.

PIC24H

EQUATION 19-1: A/D CONVERSION CLOCK PERIOD

FIGURE 19-3: A/D TRANSFER FUNCTION (10-BIT EXAMPLE)

FIGURE 19-4: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM

TAD = TCY(ADCS + 1)

ADCS = TAD

TCY – 1

10 0000 0010 (= 514)

10 0000 0011 (= 515)

01 1111 1101 (= 509)

01 1111 1110 (= 510)

01 1111 1111 (= 511)

11 1111 1110 (= 1022)

11 1111 1111 (= 1023)

00 0000 0000 (= 0)

00 0000 0001 (= 1)

Output Code

10 0000 0000 (= 512)

(VINH – VINL)

VREFL VREFH – VREFL

1024

VREFH

VREFL +

10 0000 0001 (= 513)

512 * (VREFH – VREFL)

1024

VREFL + 1023 * (VREFH – VREFL)

1024

VREFL +

ADC Internal

RC Clock

TOSC(1) X2

ADC Conversion

Clock Multiplier

1, 2, 3, 4, 5,..., 64

ADxCON3<15>

TCY

TAD

ADxCON3<5:0>

1. Refer to Figure 8-2 for the derivation of FOSC when the PLL is enabled. If the PLL is not used, FOSC is equal to the clock

source frequency. Tosc = 1/Fosc.

PIC24H

R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0

ADON — ADSIDL ADDMABM —AD12B FORM<1:0>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0

HC,HS R/C-0

HC, HS

SSRC<2:0> — SIMSAM ASAM SAMP DONE

bit 7 bit 0

Legend: HC = Cleared by hardware HS = Set by hardware

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ADON: A/D Operating Mode bit

1 = A/D converter module is operating

0 = A/D converter is off

bit 14 Unimplemented: Read as ‘0’

bit 13 ADSIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

bit 12 ADDMABM: DMA Buffer Build Mode bit

1 = DMA buffers are written in the order of conversion. The module will provide an address to the

DMA channel that is the same as the address used for the non-DMA stand-alone buffer.

0 = DMA buffers are written in Scatter/Gather mode. The mo dule will provide a scatter/ga ther address

to the DMA channel, based on the index of the analog input and the size of the DMA buffer.

bit 11 Unimplemented: Read as ‘0’

bit 10 AD12B: 10-bit or 12-bit Operation Mode bit

1 = 12-bit, 1-channel A/D operation

0 = 10-bit, 4-channel A/D operation

bit 9-8 FORM<1:0>: Data Output Format bits

For 10-bit operation:

11 = Signed fractional (DOUT = sddd dddd dd00 0000, where s = .NOT.d<9>)

10 = Fractional (DOUT = dddd dddd dd00 0000)

01 = Signed integer (DOUT = ssss sssd dddd dddd, where s = .NOT.d<9>)

00 = Integer (DOUT = 0000 00dd dddd dddd)

For 12-bit operation:

11 = Signed fractional (DOUT = sddd dddd dddd 0000, where s = .NOT.d<11>)

10 = Fractional (DOUT = dddd dddd dddd 0000)

01 = Signed Integer (DOUT = ssss sddd dddd dddd, where s = .NOT.d<11>)

00 = Integer (DOUT = 0000 dddd dddd dddd)

bit 7-5 SSRC<2:0>: Sample Clock Source Select bits

111 = Internal counter ends sampling and starts conversion (auto-convert)

110 = Reserved

101 = Reserved

100 = Reserved

011 = Reserved

010 = GP timer (Timer3 for ADC1, Timer5 for ADC2) compare ends sampling and starts conversion

001 = Active transition on INTx pin ends sampling and starts conversion

000 = Clearing sample bit ends sampling and starts conversion

bit 4 Unimplemented: Read as ‘0’

PIC24H

bit 3 SIMSAM: Simultaneous Sample Select bit (only applicable when CHPS<1:0> = 01 or 1x)

When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’

1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or

Samples CH0 and CH1 simultaneously (when CHPS<1:0> = 01)

0 = Samples multiple channels individually in sequence

bit 2 ASAM: A/D Sample Auto-Start bit

1 = Sampling begins immediately after last conversion. SAMP bit is auto-set.

0 = Sampling begins when SAMP bit is set

bit 1 SAMP: A/D Sample Enable bit

1 = A/D sample/hold amplifiers are sampling

0 = A/D sample/hold amplifiers are holding

If ASAM = 0, software may write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1.

If SSRC = 000, software may write ‘0’ to end sampling and start conversion. If SSRC ≠ 000,

automatically cleared by hardware to end sampling and start conversion.

bit 0 DONE: A/D Conversion Status bit

1 = A/D conversion cycle is completed.

0 = A/D conversion not started or in progress

Automatically set by hardware when A/D conversion is complete. Software may write ‘0’ to clear

DONE status (software not allowed to write ‘1’). Clearing this bit will NOT affect any operation in

progress. Automatically cleared by hardware at start of a new conversion.

PIC24H

R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0

VCFG<2:0> —— CSCNA CHPS<1:0>

bit 15 bit 8

R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BUFS — SMPI<3:0> BUFM ALTS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 VCFG<2:0>: Converter Voltage Reference Configuration bits

bit 12-11 Unimplemented: Read as ‘0’

bit 10 CSCNA: Scan Input Selections for CH0+ during Sample A bit

1 = Scan inputs

0 = Do not scan inputs

bit 9-8 CHPS<1:0>: Selects Channels Utilized bits

When AD12B = 1, CHPS<1:0> is: U-0, Unimplemented, Read as ‘0’

1x =Converts CH0, CH1, CH2 and CH3

01 =Converts CH0 and CH1

00 =Converts CH0

bit 7 BUFS: Buffer Fill Status bit (only valid when BUFM = 1)

1 = A/D is currently filling buffer 0x8-0xF, user should access data in 0x0-0x7

0 = A/D is currently filling buffer 0x0-0x7, user should access data in 0x8-0xF

bit 6 Unimplemented: Read as ‘0’

bit 5-2 SMPI<3:0>: Selects Increment Rate for DMA Addresses bits or number of sample/conversion

operations per interrupt

1111 = Increments the DMA address or generates interrupt after completion of every 16th

sample/conversion operation

1110 = Increments the DMA address or generates interrupt after completion of every 15th

sample/conversion operation

• • •

0001 = Increments the DMA address or generates interrupt after completion of every 2nd

sample/conversion operation

0000 = Increments the DMA address or generates interrupt after completion of every

sample/conversion operation

bit 1 BUFM: Buffer Fill Mode Select bit

1 = Starts buffer filling at address 0x0 on first interrupt and 0x8 on next interrupt

0 = Always starts filling buffer at address 0x0

bit 0 ALTS: Alternate Input Sample Mode Select bit

1 = Uses channel input selects for Sample A on first sample and Sample B on next sample

0 = Always uses channel input selects for Sample A

ADREF+ ADREF-

000 AVDD AVSS

001 External V REF+AVSS

010 AVDD External VREF-

011 External V REF+ External VREF-

1xx AVDD AVSS

PIC24H

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADRC —— SAMC<4:0>

bit 15 bit 8

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

——ADCS<5:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ADRC: A/D Conversion Clock Source bit

1 = A/D internal RC clock

0 = Clock derived from sy stem cl ock

bit 14-13 Unimplemented: Read as ‘0’

bit 12-8 SAMC<4:0>: Auto Sam ple Time bits

11111 = 31 TAD

• • •

00001 = 1 TAD

00000 = 0 TAD

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 ADCS<5:0>: A/D Conversi on Cloc k Sele ct bits

111111 = TCY · (ADCS<7:0> + 1) = 64 · TCY = TAD

• • •

000010 = TCY · (ADCS<7:0> + 1) = 3 · TCY = TAD

000001 = TCY · (ADCS<7:0> + 1) = 2 · TCY = TAD

000000 = TCY · (ADCS<7:0> + 1) = 1 · TCY = TAD

PIC24H

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — DMABL<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-3 Unimplemented: Read as ‘0’

bit 2-0 DMABL<2:0>: Selects Number of DM A Buffer Locations per Analog Input bits

111 =Allocates 128 words of buffer to each analog input

110 =Allocates 64 words of buffer to each analog input

101 =Allocates 32 words of buffer to each analog input

100 =Allocates 16 words of buffer to each analog input

011 =Allocates 8 words of buffer to each analog input

010 =Allocates 4 words of buffer to each analog input

001 =Allocates 2 words of buffer to each analog input

000 =Allocates 1 word of buffer to each analog input

PIC24H

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — CH123NB<1:0> CH123SB

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — CH123NA<1:0> CH123SA

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-11 Unimplemented: Read as ‘0’

bit 10-9 CH123NB<1:0>: Channel 1, 2, 3 Negative Input Select for Sample B bits

When AD12B = 1, CHxNB is: U-0, Unimplemented, Read as ‘0’

11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11

10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8

0x = CH1, CH2, CH3 negative input is VREF-

bit 8 CH123SB: Channel 1, 2, 3 Positive Input Select for Sample B bit

When AD12B = 1, CHxSA is: U-0, Unimplemented, Read as ‘0’

1 = CH1 positive input is AN3, CH2 positi ve input is AN4, CH3 positive input is AN5

0 = CH1 positive input is AN0, CH2 positi ve input is AN1, CH3 positive input is AN2

bit 7-3 Unimplemented: Read as ‘0’

bit 2-1 CH123NA<1:0>: Channel 1, 2, 3 Negative Input Select for Sample A bits

When AD12B = 1, CHxNA is: U-0, Unimplemented, Read as ‘0’

11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11

10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8

0x = CH1, CH2, CH3 negative input is VREF-

bit 0 CH123SA: Channel 1, 2, 3 Positive Input Select for Sample A bit

When AD12B = 1, CHxSA is: U-0, Unimplemented, Read as ‘0’

1 = CH1 positive input is AN3, CH2 positi ve input is AN4, CH3 positive input is AN5

0 = CH1 positive input is AN0, CH2 positi ve input is AN1, CH3 positive input is AN2

PIC24H

R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CH0NB —— CH0SB<4:0>

bit 15 bit 8

R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CH0NA —— CH0SA<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 CH0NB: Channel 0 Negative Input Select for Sample B bit

Same definiti on as bit 7.

bit 14-13 Unimplemented: Read as ‘0’

bit 12-8 CH0SB<4:0>: Channel 0 Positive Input Select for Sample B bits

Same definiti on as bit <4:0 >.

bit 7 CH0NA: Channel 0 Negative Input Select for Sample A bit

1 = Channel 0 negative input is AN1

0 = Channel 0 negative input is VREF-

bit 6-5 Unimplemented: Read as ‘0’

bit 4-0 CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits

11111 = Channel 0 positive input is AN31

11110 = Channel 0 positive input is AN30

• • •

00010 = Channel 0 positive input is AN2

00001 = Channel 0 positive input is AN1

00000 = Channel 0 positive input is AN0

PIC24H

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CSS31 CSS30 CSS29 CSS28 CSS27 CSS26 CSS25 CSS24

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CSS23 CSS22 CSS21 CSS20 CSS19 CSS18 CSS17 CSS16

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 CSS<31:16>: A/D Input Scan Selection bits

1 = Select ANx for input scan

0 = Skip ANx for input scan

Note 1: On devices without 32 analog inputs, all ADxCSSL bits may be selected by user. However, inputs

selected for scan without a corresponding input on device will convert ADREF-.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CSS15 CSS14 CSS13 CSS12 CSS11 CSS10 CSS9 CSS8

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 CSS<15:0>: A/D Input Scan Selection bits

1 = Select ANx for input scan

0 = Skip ANx for input scan

Note 1: On devices without 16 analog inputs, all ADxCSSL bits may be selected by user. However, inputs

selected for scan without a corresponding input on device will convert ADREF-.

PIC24H

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PCFG31 PCFG30 PCFG29 PCFG28 PCFG27 PCFG26 PCFG25 PCFG24

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PCFG23 PCFG22 PCFG21 PCFG20 PCFG19 PCFG18 PCFG17 PCFG16

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 PCFG<31:16>: A/D Port Configuration Control bits

1 = Port pin in Digital mode, port read input enabled, A/D input multiplexor connected to AVSS

0 = Port pin in Analog mode, port read input disabled, A/D samples pin voltage

Note 1: On devices without 32 analog inputs, all PCFG bits are R/W by user. However, PCFG bits are ignored on

ports without a corresponding input on device.

2: ADC2 only supports analog inputs AN0-AN15; therefore, no ADC2 high port Configuration r egister exis ts.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 PCFG<15:0>: A/D Port Configuration Control bits

1 = Port pin in Digital mode, port read input enabled, A/D input multiplexor connected to AVSS

0 = Port pin in Analog mode, port read input disabled, A/D samples pin voltage

Note 1: On devices without 16 analog inputs, all PCFG bits are R/W by user. However, PCFG bits are ignored on

ports without a corresponding input on device.

2: On dev ices with 2 analo g-to-digit al mod ules, bot h AD1PC FGL and A D2PCFGL w ill af fect th e config uration

of port pins multiplexed with AN0-AN15.

PIC24H

NOTES:

PIC24H

20.0 SPECIAL FEATURES

PIC24H devices include several features intended to

maximize application flexibility and reliability, and mini-

mize cost through elimination of external components.

These are:

• Flexible Configuration

• Watchdog Timer (WDT)

• Code Protection and CodeGuard™ Security

• JTAG Boundary Scan Interface

• In-Circuit Serial Programming™ (ICSP™)

programming capability

• In-Circuit Emulatio n

20.1 Configurati on Bits

The Configuration bits can be programmed (read as

‘0’), or left unprogrammed (read as ‘1’), to select vari-

ous device configurations. These bits are mapped

starting at program memory location 0xF80000.

The device Configuration register map is shown in

Table 20-1.

The individual Configuration bit descriptions for the

FBS, FS S, FGS, FOSCS EL, FOSC, FW DT and FPOR

Configuration registe rs are shown in Table 20-1.

Note that address 0xF80000 is beyond the user program

memory space. In fact, it belongs to the configuration

memory space (0x800000-0xFFFFFF), which can only

be accessed using table reads and table writes.

The upper byte of all device Configuration registers

should always be ‘1111 1111’. This makes them

appear to be NOP instructions in the remote event that

their locations are ever executed by accident. Since

Configuration bits are not implemented in the

corresponding locations, writing ‘1’s to these locations

has no effect on device operation.

To prevent inadvertent configuration changes during

code execution, all programmable Configuration bits

are writ e-once. After a b it is initial ly programmed d uring

a power cycle, it cannot be written to again. Changing

a device configurati on requires that power to th e device

be cycled.

TABLE 20-1: DEVICE CONFIGURATION REGISTER MAP

Note: This data sheet summarizes the features

of this group of PIC24H devices. It is not

intende d to be a comprehe nsive referenc e

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0xF80000 FBS RBS<1:0> —— BSS<2:0> BWRP

0xF80002 FSS RSS<1:0> —— SSS<2:0> SWRP

0xF80004 FGS — — — — — GSS<1:0> GWRP

0xF80006 FOSCSEL IESO —TEMP ——FNOSC<2:0>

0xF80008 FOSC FCKSM<1:0> — — — OSCIOFNC POSCMD<1:0>

0xF8000A FWDT FWDTEN WINDIS — WDTPRE WDTPOST<3:0>

0xF8000C FPOR Reserved(2) ——FPWRT<2:0>

0xF8000E RESERVED3 Reserved

0xF80010 FUID0 User Unit ID Byte 0

0xF80012 FUID1 User Unit ID Byte 1

0xF80014 FUID2 User Unit ID Byte 2

0xF80016 FUID3 User Unit ID Byte 3

Note 1: This reserved bit is a read-onl y copy of the GC P bit.

2: Reserved bi ts are r ead as ‘1’ and must be pro grammed as ‘1’.

PIC24H

TABLE 20-2: PIC24H CONFIGURATION BITS DESCRIPTION

Bit Field Register Description

BWRP FBS Boot Segment Program Flash Write Protection

1 = Boot segment may be written

0 = Boot segment is write-protected

BSS<2:0> FBS Boot Segment Program Flash Code Protection Size

X11 = No Boot program Flash segment

Boot space is 1K IW less VS

110 = Standard security; boot program Flash segment starts at End of

VS, ends at 0x0007FE

010 = High security; boot pr ogram Flash segment starts at End of VS,

ends at 0x0007FE

Boot space is 4K IW less VS

101 = Standard security; boot program Flash segment starts at End of

VS, ends at 0x001FFE

001 = High security; boot pr ogram Flash segment starts at End of VS,

ends at 0x001FFE

Boot space is 8K IW less VS

100 = Standard security; boot program Flash segment starts at End of

VS, ends at 0x003FFE

000 = High security; boot pr ogram Flash segment starts at End of VS,

ends at 0x003FFE

RBS<1:0> FBS Boot Segment RAM Code Protection

10 = No Boot RAM defined

10 = Boot RAM is 128 Bytes

01 = Boot RAM is 256 Bytes

00 = Boot RAM is 1024 Bytes

SWRP FSS Secur e Segment Progra m Flas h W ri te Protec tio n

1 = Secure segment may be written

0 = Secure segment is write-protected.

PIC24H

SSS<2:0> FSS Secure Segment Program Flash Code Protection Size

(FOR 128K and 256K DE VICES)

X11 = No Secure program Flash segment

Secure space is 8K IW less BS

110 = Standard security; secure program Flash segment starts at End

of BS, ends at 0x003FFE

010 = High security; secure program Flash segment starts at End of

BS, ends at 0x003FFE

Secure space is 16K IW less BS

101 = Standard security; secure program Flash segment starts at End

of BS, ends at 0x007FFE

001 = High security; secure program Flash segment starts at End of

BS, ends at 0x007FFE

Secure space is 32K IW less BS

100 = Standard security; secure program Flash segment starts at End

of BS, ends at 0x00FFFE

000 = High security; secure program Flash segment starts at End of

BS, ends at 0x00FFFE

(FOR 64K DEVICES)

X11 = No Secure program Flash segment

Secure space is 4K IW less BS

110 = Standard security; secure program Flash segment starts at End

of BS, ends at 0x001FFE

010 = High security; secure program Flash segment starts at End of

BS, ends at 0x001FFE

Secure space is 8K IW less BS

101 = Standard security; secure program Flash segment starts at End

of BS, ends at 0x003FFE

001 = High security; secure program Flash segment starts at End of

BS, ends at 0x003FFE

Secure space is 16K IW less BS

100 = Standard security; secure program Flash segment starts at End

of BS, ends at 0x007FFE

000 = High security; secure program Flash segment starts at End of

BS, ends at 0x007FFE

RSS<1:0> FSS Secure Segment RAM Code Protection

10 = No Secure RAM defined

10 = Secu re RAM is 256 By tes less BS RAM

01 = Secure RAM is 2048 Bytes less BS RAM

00 = Secure RAM is 4096 Bytes less BS RAM

GSS<1:0> FGS General Segment Code-Protect bit

11 = User program memory is not code-protected

10 = Standard Security; general program Flash segment starts at End

of SS, ends at EOM

0x = High Security; general program Flash segment starts at End of

ESS, ends at EOM

TABLE 20-2: PIC24H CONFIGURATION BITS DESCRIPTION (CONTINUED)

Bit Field Register Description

PIC24H

GWRP FGS General Segment Write-Protect bit

1 = User program memory is not write-protected

0 = User program memory is write-protected

IESO FOSCSEL Internal External Start-up Option bit

1 = Start-up device with FRC, then automatically switch to the

user-sel ect ed osc il lat or sou rce w hen ready

0 = Start-up device with user-selected oscillator source

TEMP FOSCSEL Temperature Protection Enable bit

1 = Temperature protection disabled

0 = Temperature protection enabled

FNOSC<2:0 > FOSCSEL Initial Oscilla tor Sourc e Sele cti on bits

111 = Internal Fast RC (FRC) oscillator with postscaler

110 = Reserved

101 = LPRC oscillator

100 = Secondary (LP) oscillator

011 = Primary (XT, HS, EC) oscillator with PLL

010 = Primary (XT, HS, EC) oscillator

001 = Internal Fast RC (FRC) oscillator with PLL

000 = FRC oscillator

FCKSM<1:0> FOSC Clock Switching Mode bits

1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled

01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled

00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled

OSCIOFNC FOSC OSC2 Pin Function bit (except in XT and HS modes)

1 = OSC2 is clock output

0 = OSC2 is general purpose digital I/O pin

POSCMD<1:0> FOSC Primary Oscillator Mode Select bits

11 = Primary oscillator disabled

10 = HS Crystal Oscillator mode

01 = XT Crystal Oscillator mode

00 = EC (External Clock) mode

FWDTEN FWDT W a tch dog Timer Enable bit

1 = W atch dog T im er alway s enabl ed (LPR C oscil lator ca nnot be disa bled.

Cleari ng th e S WDTEN bit in the RCO N reg is te r wi ll h ave no effect.)

0 = Watchdog Timer enabled/disabled by user software (LPRC can be

disabled by clearing the SWDTEN bit in the RCON register)

WINDIS FWDT Watchdog Timer Window Enable bit

1 = Watchdog Timer in Non-Window mode

0 = Watchdog Timer in Window mode

WDTPRE FWDT Watchdog Timer Prescaler bit

1 = 1:128

0 = 1:32

WDTPOST FWDT Watchdog Ti mer Postscaler bits

1111 = 1:32,768

1110 = 1:16,384

0001 = 1:2

0000 = 1:1

TABLE 20-2: PIC24H CONFIGURATION BITS DESCRIPTION (CONTINUED)

Bit Field Register Description

PIC24H

20.2 On-Chip Voltage Regulator

All of the PIC24H devices power their core digital logic

at a no minal 2.5V. This m ay create an is sue for design s

that are required to operate at a higher typical voltage,

such as 3.3V. To simplify system design, all devices in

the PIC24H family incorporate an on-chip regulator that

allows the device to run its core logic from VDD.

The regul ator provides power to the core f rom the other

VDD pins. When the regulator is enabled, a low-ESR

(less than 5 ohms) capacitor (such as tantalum or

ceramic) must be connected to the VDDCORE/VCAP pin

(Figure 20-1). This helps to maintain the stability of the

regulator. The recommended value for the filter capac-

itor is provided in TABLE 23-12: “Internal Voltage

Regulator Specifications” located in Section 23.1

“DC Characteristics”.

On a POR, i t take s approxim ately 20 μs for the on- chip

voltage regulator to generate an output voltage. During

this time, designated as TSTARTUP, code execution is

disabled. TSTARTUP is applied every time the device

resumes operation after any power-down.

FIGURE 20-1: CONNECTIONS FOR THE

ON-CHIP VOLTAGE

REGULATOR(1)

FPWRT<2:0> FPOR Power-on Reset Timer Va lue Select bits

111 = PWRT = 128 ms

110 = PWRT = 64 ms

101 = PWRT = 32 ms

100 = PWRT = 16 ms

011 = PWRT = 8 ms

010 = PWRT = 4 ms

001 = PWRT = 2 ms

000 = PWRT = Disabled

Reserved FPOR,

RESERVED3 Reserved (read as ‘1’ and m ust be program med as ‘1’)

— FGS, FOSCSEL,

FOSC, FWDT,

FPOR

Unimplemented (read as ‘0’, write as ‘0’)

TABLE 20-2: PIC24H CONFIGURATION BITS DESCRIPTION (CONTINUED)

Bit Field Register Description

Note 1: These are typical operating voltages. Refer

to TABLE 23-12: “Internal Voltage Regu-

lator Specifications” located in

Section 23.1 “DC Characteristics” for the

full operating ranges of VDD and VDDCORE.

VDD

VDDCORE/VCAP

VSS

PIC24H

3.3V

10 μF

PIC24H

20.3 Watchdog Timer (WDT)

For PIC24H devices, the WDT is driven by the LPRC

oscillator. When the WDT is enabled, the clock source

is al so enable d.

The nominal WDT clock source from LPRC is 32 kHz.

This fee ds a presca ler than can b e configured for either

5-bit (divide-by-32) or 7-bit (divide-by-128) operation.

The presc aler is set by the WDTPRE Con figurati on bit.

With a 32 kHz input, the prescaler yields a nominal

WDT time-out period (TWDT) of 1 ms in 5- bit mode , or

4 ms in 7-bit mode.

A variable postscaler divides down the WDT prescaler

output and allows for a wide range of time-out periods.

The postscaler is controlled by the WDTPOST<3:0>

Config uration bit s (FWDT <3:0>) whic h allo w the se lec-

tion of a tot al of 16 set tings, from 1:1 to 1:32, 768. Using

the prescaler and postscaler, time-out periods ranging

from 1 ms to 131 seconds can be achieved.

The WDT, prescaler and postscaler are reset:

• On any device Reset

• On the completion of a clock switch, whether

invoked by software (i.e., setting the OSWEN bit

after changing the NOSC bits) or by hardw are

(i.e., Fail-Safe Clock Monitor)

• When a PWRSAV instruction is executed

(i.e., Sleep or Idle mode is entered)

• When the device exits Sleep or Idle mode to

resume normal operation

•By a CLRWDT instruction during normal execution

If the WDT is enabled, it will continue to run during Sleep

or Idle modes. When the WDT time-out occurs, the

device will wake the device and code executio n will con-

tinue f rom whe re the PWRSAV instruct ion was e xecuted.

The corresponding SLEEP or IDLE bits (RCON<3,2>)

will need to be cleared in software after the device wakes

up.

The WDT flag bit, WDTO (RCON<4>), is not automatically

cleared following a WDT time-out. To detect subsequent

WDT event s, the flag m ust be c leared in softw are.

The WDT is enabled or disabled by the FWDTEN

Configuration bit in the FWDT Configuration register.

When the FWDTEN Configura tion bit is set, the WDT is

always en abled.

The WDT can be optio nally contro lled in softwa re when

the FWDTEN Configuration bit has been programmed

to ‘0’. The WDT is enabled in software by setting the

SWDTEN control bit (RCON<5>). The SWDTEN con-

trol bit is cleared on any device Reset. The software

WDT opti on allows the user to enable the WDT for crit-

ical code segments and disable the WDT during

non- critical segme nts for maximu m power savings.

FIGURE 20-2: WDT BLOCK DIAGRAM

Note: The CLRWDT and PWRSAV instructions

clear the prescaler and postscaler counts

when executed.

Note: If the WINDIS bit (FWD T<6>) is cleared, the

CLRWDT instru ction shou ld be execu ted by

the applic at ion so ftw a re only d uring the las t

1/4 of the WDT period. This CLRWDT win-

dow ca n be de termi ned b y usin g a ti mer. If

a CLRWDT instruction is executed before

this wi nd ow, a WDT Rese t o c cu rs .

LPRC Input WDT Overflow

Wake from Sleep

32.768 kHz

Prescaler Postscaler

WDTPRE

SWDTEN

FWDTEN

Reset

All Device Resets

Sleep or Idle Mode

LPRC Cont rol

CLRWDT Instr.

PWRSAV Instr.

WDTPOST<3:0>

1 ms/4 ms

Exit Sleep or

Idle Mode

WDT

Counter

Transition to

New Clock Source

PIC24H

20.4 JTAG Interface

PIC24H devices implement a JTAG interface, which

supports boundary scan device testing, as well as

in-circuit programming. Detailed information on the

interface will be provided in future revisions of the

document.

20.5 Code Protection and

CodeGuard™ Security

The PIC24H product families offer advanced imple-

mentation of CodeGuard™ Security. CodeGuard

Security enables multiple parties to securely share

resources (memory, interrupts and peripherals) on a

single chip. This feature helps protect individual

Intellectual Property in collaborative system designs.

When coupled with software encryption libraries,

CodeGuard Security can be used to securely update

Flash even when multiple IP are resident on the single

chip. The co de prote ction f eatures vary de pending on

the actual PIC24H implemented. The following

sections provide an overview these features.

The code protection features are controlled by the

Configuration registers: FBS, FSS and FGS.

20.6 In-Circuit Serial Programming

Programming Capability

PIC24H family digital signal controllers can be serially

progra mmed w hile in t he en d app licati on c ircuit. This i s

simply done with tw o lines for cl ock and data and thre e

other lines for power, ground and the programming

sequence. This allows customers to manufacture

boards with unprogrammed devices and then program

the digital signal controller just before shipping the

product. This also allows the most recent firmware or a

custom firmware, to be programmed. Please refer to

the “dsPIC33F Flash Programming Specification”

(DS70152) document for details about ICSP

programming capability.

Any 1 out of 3 pairs of programming clock/data pins

may be used:

• PGC1/EMUC1 and PGD1/EMUD1

• PGC2/EMUC2 and PGD2/EMUD2

• PGC3/EMUC3 and PGD3/EMUD3

20.7 In-Circuit Debugger

When MPLAB® ICD 2 is selected as a debugger, the

in-circuit debugging functionality is enabled. This func-

tion all ows simp le de buggin g func tions whe n used w ith

MPLAB IDE. Debugging functionality is controlled

through the EMUCx (Emulation/Debug Clock) and

EMUDx (Emulation/Debug Data) pin functions.

Any 1 out of 3 pairs of debugging clock/data pins may

be used:

• PGC1/EMUC1 and PGD1/EMUD1

• PGC2/EMUC2 and PGD2/EMUD2

• PGC3/EMUC3 and PGD3/EMUD3

To use the in-circuit debugger function of the device,

the design must implement ICSP programming capa-

bility connections to MCLR, VDD, VSS, PGC, PGD and

the EMUDx /EMU Cx pi n p a ir. In addition, wh en t he fe a-

ture is enabled, some of the reso urces are not available

for general use. These resources include the first 80

bytes of data RAM and two I/O pins.

Note: Refer to CodeGuard Security Reference

Manual (DS70180) for further information

on usage, configuration and operation of

Code Guard Security.

PIC24H

NOTES:

PIC24H

21.0 INSTRUCTION SET SUMMARY

The PIC24H instruction set is identical to that of the

PIC24F, and is a subset of the dsPIC30F/33F

instruction set.

Most instructions are a single program memory word

(24 bits). Only three instructions require two program

memory locations.

Each single-word instruction is a 24-bit word, divided

into an 8-bit opcode, which specifies the instruction

type and one or more operands, which further specify

the operation of the instruction.

The instruction set is highly orthog onal and is grouped

into five bas ic ca tego ries:

• Word or byte-oriented operations

• Bit-oriented operations

• Literal operations

• DSP operations

• Control operations

Table 21-1 shows the general symbols used in

des c ribing t he instructions.

The P IC24H ins truction set sum mary in Table 21-2 li sts

all the instructions, along with the status flags affected

by each instructio n.

Most word or byte-oriented W register instructions

(including barrel shift instructions) have three

operands:

• The first source operand which is typically a

• The seco nd source operand which is typically a

• The destination of the result which is typically a

However, word or byte-oriented file register instruc-

tions have two operands:

• The file register specified by the value ‘f’

• The destination, which could either be the file

‘WREG’

Most bit-oriented instructions (including simple

rotate/shift instructions) have two operands:

• The W register (with or without an address

modifier) or file register (specified by the value of

‘Ws’ or ‘f’)

• The bit in the W register or file register

(specified by a literal value or indirectly by the

contents of register ‘Wb’)

The litera l instruct ions that invo lve data m ovement ma y

use some of the following operands:

• A lite ral value to be lo ad ed into a W regi ster or file

• The W register or file register where the literal

value is to be loaded (specified by ‘Wb’ or ‘f’)

However, literal instructions that involve arithmetic or

logical operations use some of the following operands:

• The first source operand which is a register ‘Wb’

without any addre s s modifier

• The second source operand which is a literal

value

• The dest ination of the result (only if not the same

as the first source operand) which is typically a

The control instructions may use some of the following

operands:

• A program memory address

• The mode of the table read and table write

instructions

Note: This data sheet summarizes the features

of this group of PIC24H devices. It is not

intende d to be a comprehe nsive referenc e

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

PIC24H

All instructions are a single word, except for certain

double word instructions, which were made double

word instructions so that all the required information is

available in these 48 bits. In the second word, the

8MSbs are ‘0’s. I f t hi s s e co nd w o rd i s e x ec ut e d a s an

instruction (by itself), it will execute as a NOP.

Most single-word instructions are executed in a single

instruction cycle, unless a conditional test is true, or the

program counter is changed as a result of the instruc-

tion. In these cases, the execution takes two instruction

cycles with the additional instruction cycle(s) executed

as a NOP. Notable exceptions are the BRA (uncondi-

tional/computed branch), indirect CALL/GOTO, all table

reads and writes and RETURN/RETFIE instructions,

which are single-word instructions but take two or three

cycles. Cert ain instructions that involve skipping over the

subsequent instruction require eithe r two or three cycles

if the skip is performed, depending on whether the

instruction being skipped is a single-word or double word

instruction. Moreover, double word moves require two

cycles. The double word instructions execute in two

instruction cy cles.

Note: For more details on the instruction set,

refer to the “dsPIC30F/33F Programmer’s

Reference Manual” (DS70157).

TABLE 21-1: SYMBOLS USED IN OPCODE DESCRIPTIONS

Field Description

#text Means literal defined by “text”

(text) Means “content of text”

[text] Means “the location addressed by text”

{ } Optional field or operation

<n:m> Register bit field

.b Byte mode selection

.d Double Word mode selection

.S Shadow register select

.w Word mode selection (default)

bit4 4-bit bit selection field (used in word addressed instructions) ∈ {0...15}

C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero

Expr Absolute address, label or expression (resolved by the linker)

f File register address ∈ {0x0000...0x1FFF}

lit1 1-bit unsigned literal ∈ {0,1}

lit4 4-bit unsigned literal ∈ {0...15}

lit5 5-bit unsigned literal ∈ {0...31}

lit8 8-bit unsigned literal ∈ {0...255}

lit10 10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode

lit14 14-bit unsigned literal ∈ {0...16384}

lit16 16-bit unsigned literal ∈ {0...65535}

lit23 23-bit unsigned literal ∈ {0...8388608}; LSB must be ‘0’

None Field does not require an entry, may be blank

PC Program Counter

Slit10 10-bit signed literal ∈ {-512...511}

Slit16 16-bit signed literal ∈ {-32768...32767}

Slit6 6-bit signed literal ∈ {-16...16}

Wb Base W register ∈ {W0..W15}

Wd Destination W register ∈ { Wd, [Wd ], [Wd++], [Wd - -], [++Wd], [--Wd] }

Wdo Destination W register ∈

{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }

Wm,Wn Dividend, Divisor working register pair (direct addressing)

Wm*Wm Multiplicand and Multiplier working register pair for Square instructions ∈

{W4 * W4,W5 * W5,W6 * W6,W7 * W7}

Wm*Wn Multiplicand and Multiplier working register pair for DSP instructions ∈

{W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7}

Wn O ne of 16 working registers ∈ {W0..W15}

PIC24H

Wnd One of 16 destination working registers ∈ {W0..W15}

Wns One of 16 source working registers ∈ {W0..W15}

WREG W0 (working register used in file register instructions)

Ws Source W register ∈ { Ws, [Ws], [Ws++ ], [Ws--] , [++W s], [-- Ws] }

Wso Source W register ∈

{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }

TABLE 21-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)

Field Description

PIC24H

TABLE 21-2: INSTRUCTION SET OVERVIEW

Base

Instr

Assembly

Mnemonic Assemb ly S yntax Description # of

Words # of

Cycles Status Flags

Affected

1ADD ADD f f = f + WREG 1 1 C,DC,N,OV,Z

ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z

ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z

ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z

ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z

2 ADDC ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z

ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z

ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z

ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z

ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z

3 AND AND f f = f .AND. WREG 1 1 N,Z

AND f,WREG WREG = f .AND. WREG 1 1 N,Z

AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z

AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z

AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z

4 ASR ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z

ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z

ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C, N,OV,Z

ASR Wb,Wn s,Wnd Wnd = Arithmetic Right Sh ift Wb by Wns 1 1 N,Z

ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z

5 BCLR BCLR f ,#bit4 Bit Clear f 1 1 None

BCLR Ws,#bit4 Bit Clear Ws 1 1 None

6 BRA BRA C,Expr Branch if Carry 1 1 (2) None

BRA GE,Expr Branch if greater than or equal 1 1 (2) None

BRA GEU,Expr Branc h if unsigned greater than or equ al 1 1 (2) None

BRA GT,Expr Branch if greater than 1 1 (2) None

BRA GTU,Expr Branch if unsigned greater than 1 1 (2) None

BRA LE,Expr Branch if less than or equal 1 1 (2) None

BRA LEU, Ex pr Branc h if unsigned less than or equal 1 1 (2) None

BRA LT,Ex pr Branch if less than 1 1 (2) N o ne

BRA LTU,Expr Branch if unsigned less than 1 1 (2) None

BRA N,Expr Branch if Negative 1 1 (2) None

BRA NC,Expr Branch if Not Carry 1 1 (2) No ne

BRA NN,Expr Branch if Not Negative 1 1 (2) None

BRA NZ,Expr Branch if Not Zero 1 1 (2) None

BRA Expr Branch Unconditionally 1 2 No ne

BRA Z,E xpr Bran ch if Zero 1 1 (2) N o ne

BRA Wn Computed Branch 1 2 None

7 BSET BSET f,#bit4 Bit Set f 1 1 None

BSET Ws,#bit4 Bit Set Ws 1 1 None

8 BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None

BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None

9 BTG BTG f,#bit4 Bit Toggle f 1 1 None

BTG Ws,#bit4 Bit Toggle Ws 1 1 None

10 BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1

(2 or 3) None

BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1

(2 or 3) None

11 BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1

(2 or 3) None

BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1

(2 or 3) None

PIC24H

12 BTST BTST f,#bit4 Bit Test f 1 1 Z

BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C

BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z

BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C

BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z

13 BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z

BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C

BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z

14 CALL CALL lit23 Call subroutine 2 2 None

CALL Wn Call indirect subroutine 1 2 None

15 CLR CLR f f = 0x0000 1 1 None

CLR WREG WREG = 0x0000 1 1 None

CLR Ws Ws = 0x0000 1 1 None

16 CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO,Sleep

17 COM COM f f = f 11 N,Z

COM f,WREG WREG = f 11 N,Z

COM Ws,Wd Wd = Ws 11 N,Z

18 CP CP f Compare f with WREG 1 1 C,DC,N,OV,Z

CP Wb,#lit5 Compare Wb with lit5 1 1 C,DC,N,OV,Z

CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C,DC,N,OV,Z

19 CP0 CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z

CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z

20 CPB CPB f Compare f with WREG, with Borrow 1 1 C,DC,N,OV,Z

CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C,DC,N,OV,Z

CPB Wb,Ws Compare Wb with Ws, with Borrow

(Wb – Ws – C)1 1 C,DC,N,OV,Z

21 CPSEQ CPSEQ Wb, Wn Compare Wb wit h Wn, skip if = 1 1

(2 or 3) None

22 CPSGT CPSGT Wb, Wn Compare Wb with Wn, skip if > 1 1

(2 or 3) None

23 CPSLT CPSLT Wb, Wn Compare Wb with Wn, skip if < 1 1

(2 or 3) None

24 CPSNE CPSNE Wb, Wn Compare Wb with Wn, skip if ≠11

(2 or 3) None

25 DAW DA W Wn Wn = decimal adjust Wn 1 1 C

26 DEC DEC f f = f – 1 1 1 C,DC,N,OV,Z

DEC f,WREG WREG = f – 1 1 1 C,DC,N,OV,Z

DEC Ws,Wd Wd = Ws – 1 1 1 C,DC,N,OV,Z

27 DEC2 DEC2 f f = f – 2 1 1 C,DC,N,OV,Z

DEC2 f,WREG WREG = f – 2 1 1 C,DC,N,OV,Z

DEC2 Ws,Wd Wd = Ws – 2 1 1 C,DC,N,OV,Z

28 DISI DISI #lit14 Disable Interrupts for k instruction cycles 1 1 None

29 DIV DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C,OV

DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV

DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV

DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N,Z,C,OV

30 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None

31 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C

32 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C

33 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C

34 GOTO GOTO Expr Go to address 2 2 None

GOTO Wn Go to indirect 1 2 None

TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

Assembly

Mnemonic Assemb ly S yntax Desc r ipt ion # of

Words # of

Cycles Status Flags

Affected

PIC24H

35 INC INC f f = f + 1 1 1 C,DC,N,OV,Z

INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z

INC Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z

36 INC2 INC2 f f = f + 2 1 1 C,DC,N,OV,Z

INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z

INC2 Ws,Wd Wd = Ws + 2 1 1 C,DC,N,OV,Z

37 IOR IOR f f = f .IOR. WREG 1 1 N,Z

IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z

IOR # lit 10, Wn Wd = lit10 .IOR. Wd 1 1 N,Z

IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z

IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z

38 LNK LNK #lit14 Link Frame Pointer 1 1 None

39 LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z

LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z

LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z

LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z

LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z

40 MOV MOV f,Wn Move f to Wn 1 1 None

MOV f Move f to f 1 1 N,Z

MOV f,WREG Move f t o WREG 1 1 N,Z

MOV #lit16,Wn Move 16-bit literal to Wn 1 1 None

MOV.b #lit8,Wn Move 8-bit literal to Wn 1 1 None

MOV Wn,f Move Wn to f 1 1 None

MOV Wso,Wdo Move Ws to Wd 1 1 None

MOV WREG,f Move WREG to f 1 1 N,Z

MOV.D Wns,Wd Move Double from W(ns):W(ns + 1) to Wd 1 2 None

MOV.D Ws,Wnd Move Double from Ws to W(nd + 1):W(nd) 1 2 None

41 MUL MUL.SS Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) 1 1 None

MUL.SU Wb,Ws,Wnd {Wnd + 1, W nd} = sign ed (W b ) * un s ign ed (Ws ) 1 1 None

MUL.US Wb,Ws,Wnd {Wnd + 1, W nd } = uns ign ed (W b ) * s ign ed (W s) 1 1 None

MUL.UU Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) *

unsigned(Ws) 11 None

MUL.SU Wb,#lit5,Wnd {Wnd + 1, Wnd} = si gn ed (Wb ) * unsi g ne d( li t5 ) 1 1 None

MUL.UU Wb,#lit5,Wnd {Wnd + 1, Wnd} = unsigned(Wb) *

unsigned(lit5) 11 None

MUL f W3:W2 = f * WREG 1 1 None

42 NEG NEG f f = f + 1 1 1 C,DC,N,OV,Z

NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z

NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z

43 NOP NOP No Operation 1 1 None

NOPR No Oper ation 1 1 None

44 POP POP f Pop f from Top-of-Stack (TOS) 1 1 None

POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None

POP.D Wnd Pop from Top-of-Stack (TOS) to

W(nd):W(nd + 1) 12 None

POP.S Pop Sh ad ow Re giste rs 1 1 All

45 PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None

PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None

PUSH.D Wns Push W(ns) :W(ns + 1) to Top-of-Stack

(TOS) 12 None

PUSH.S Push Shadow Registers 1 1 None

46 PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO,Sleep

TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

Assembly

Mnemonic Assemb ly S yntax Desc r ipt ion # of

Words # of

Cycles Status Flags

Affected

PIC24H

47 RCALL RCALL Expr Relative Call 1 2 None

RCALL Wn Computed Call 1 2 None

48 REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None

REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None

49 RESET RESET Software device Reset 1 1 None

50 RETFIE RETFIE Return from interrupt 1 3 (2) None

51 RETLW RETLW #lit10,Wn Return with literal in Wn 1 3 (2) None

52 RETURN RETURN Return from Subroutine 1 3 (2) None

53 RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z

RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z

RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z

54 RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N,Z

RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z

RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z

55 RRC RRC f f = Rotate Right through Carry f 1 1 C,N,Z

RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z

RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z

56 RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N,Z

RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z

RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z

57 SE SE Ws,Wnd Wnd = sign-extended Ws 1 1 C,N,Z

58 SETM SETM f f = 0xFFFF 1 1 None

SETM WREG WREG = 0xFFFF 1 1 None

SETM Ws Ws = 0xFFFF 1 1 None

59 SL SL f f = Left Shift f 1 1 C,N,OV,Z

SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z

SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z

SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z

SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z

60 SUB SUB f f = f – WREG 1 1 C,DC,N,OV,Z

SUB f,WREG WREG = f – WREG 1 1 C,DC,N,OV,Z

SUB #lit10,Wn Wn = Wn – lit10 1 1 C,DC,N,OV,Z

SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C,DC,N,OV,Z

SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C,DC,N,OV,Z

61 SUBB SUBB f f = f – WREG – (C) 1 1 C,DC,N,OV,Z

SUBB f,WREG WREG = f – WREG – (C) 1 1 C,DC,N,OV,Z

SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C,DC,N,OV,Z

SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C,DC,N,OV,Z

SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C,DC,N,OV,Z

62 SUBR SUBR f f = WREG – f 1 1 C,DC,N,OV,Z

SUBR f,WREG WREG = WREG – f 1 1 C,DC,N,OV,Z

SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C,DC,N,OV,Z

SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C,DC,N,OV,Z

63 SUBBR SUBBR f f = WREG – f – (C) 1 1 C,DC,N,OV,Z

SUBBR f,WREG WREG = WREG – f – (C) 1 1 C,DC,N,OV,Z

SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C,DC,N,OV,Z

SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C,DC,N,OV,Z

64 SWAP SWAP.b Wn Wn = nibble swap Wn 1 1 None

SWAP Wn Wn = byte swap Wn 1 1 None

65 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None

TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

Assembly

Mnemonic Assemb ly S yntax Desc r ipt ion # of

Words # of

Cycles Status Flags

Affected

PIC24H

66 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None

67 TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None

68 TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None

69 ULNK ULNK Unlink Frame Pointer 1 1 None

70 XOR XOR f f = f .XOR. WREG 1 1 N,Z

XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z

XOR #lit10,W n Wd = lit10 .XOR. Wd 1 1 N,Z

XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z

XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z

71 ZE ZE Ws,Wnd Wnd = Zero-extend Ws 1 1 C,Z,N

TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

Assembly

Mnemonic Assemb ly S yntax Desc r ipt ion # of

Words # of

Cycles Status Flags

Affected

PIC24H

22.0 DEVELOPMENT SUPPORT

The PICmicro® microcontrollers are supported with a

full ran ge of hardware a nd softwa re develo pment to ols:

• Integrated Development Environment

- MPLAB® IDE Software

• Assemblers/Compilers/Linkers

- MPASMTM Assembler

- MPLAB C18 and MPLAB C30 C Compilers

-MPLINK

TM Object Linker/

MPLIBTM Object Librarian

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

- MPLAB SIM Software Simulator

•Emulators

- MPLAB ICE 2000 In-Circuit Emulator

- MPLAB ICE 4000 In-Circuit Emulator

• In-Circuit Debugger

- MPLAB ICD 2

• Device Progra mmers

- PICSTART® Plus Development Programmer

- MPLAB PM3 Device Programmer

- PICkit™ 2 Development Programmer

• Low-Cost Demonstration and Development

Boards and Evaluation Kits

22.1 MPLAB Integrated Development

Environment Software

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit micro-

controller market. The MPLAB IDE is a Windows®

operating system-based application that contains:

• A single graphical interface to all debugging tools

- Simulator

- Programmer (sold separately)

- Emulator (sold separatel y)

- In-C ircuit D ebugger (so ld separately)

• A full-featured editor with color-coded context

• A multiple project manager

• Customizable data windows with direct edit of

contents

• High-level source code debugging

• Visual device initializer for easy register

initialization

• Mouse over variable inspection

• Drag and drop variables from source to watch

windows

• Exten si ve on-l in e help

• Integration of select third party tools, such as

HI-TECH Software C Compilers and IAR

C Compilers

The MPLAB IDE allows you to:

• Edit your source files (eithe r assembly or C)

• One touch assemble (or compile) and download

to PICmicro MCU emulator and simulator tools

(automatically updates all project information)

• Debug us ing :

- Source files (assemb ly or C)

- Mixed assembly and C

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

PIC24H

22.2 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assembler for all PICmicro MCUs.

The MPASM Assembler generates relocatable object

files fo r the MPLINK Ob ject Linker , Int el® standa rd HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• User-defined macros to streamline

assembly code

• Conditional assembly for multi-purpose

sour ce fil es

• Directives that allow complete control over the

assembly process

22.3 MPLAB C18 and MPLAB C30

C Compilers

The MPLAB C18 and MPLAB C30 Code Development

Systems are complete ANSI C compilers for

Microchip’s PIC18 family of microcontrollers and the

dsPIC30, dsPIC33 and PIC24 family of digital signal

controllers. These compilers provide powerful integra-

tion capabilities, superior code optimization and ease

of use not found with other compilers.

For easy source level debugging, the compilers provide

symbol info rmation tha t is optimized to the MPLAB IDE

debugger.

22.4 MPLINK Object Linker/

MPLIB Object Librari an

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB O bject Li brarian manag es the cre ation an d

modification of library files of precompiled code. When

a routine from a library is called from a source file , only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, de letion and extraction

22.5 MPLAB ASM30 Assembler, Linker

and Librarian

MPLAB ASM30 Assembler produces relocatable

machine code from symbolic assembly language for

dsPIC30F devices. MPLAB C30 C Compiler uses the

assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or lin ked with other relocatable ob ject files and

arch ives to c rea te an e xecu tabl e fil e. N otabl e fe atu res

of the assembler include:

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Rich dire cti ve set

• Flexible macro language

• MPLAB IDE compatibility

22.6 MPLAB SIM Software Simulator

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PICmicro MCUs and dsPIC® DSCs on an

instruction level. On any given instruction, the data

areas can be examined or modified and stimuli can be

applied from a comprehensive stimulus controller.

Registers can be logged to files for further run-time

analysis. The trace buffer and logic analyzer display

extend the power of the simulator to record and track

program execution, actions on I/O, most peripherals

and internal registers.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C18 and

MPLAB C30 C Compilers, and the MPASM and

MPLAB ASM30 Assemblers. The software simulator

offers the flexibility to develop and debug code outside

of the hardware laboratory environment, making it an

excellent, economical software development tool.

PIC24H

22.7 MPLAB ICE 2000

High-Performance

In-Circui t Emu lator

The MPLAB ICE 2000 In-Circuit Emulator is intended

to provide the product development engineer with a

complete microcontroller design tool set for PICmicro

microcontrollers. Software control of the MPLAB ICE

2000 In-Circuit Emulator is advanced by the MPLAB

Integrated Development Environment, which allows

editing, building, downloading and source debugging

from a single environment.

The MPLAB ICE 2000 is a full-featured emulator

system with enhanced trace, trigger and data monitor-

ing feat ures. Interc hangeabl e proces sor modul es allow

the system to be easily reconfigured for emulation of

different processors. The architecture of the MPLAB

ICE 2000 In-Circuit Emulator allows expansion to

support new PICmicro microcontrollers.

The MPLAB ICE 2000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft® Windows® 32-bit operating system were

chosen to best make these features available in a

simple, unified application.

22.8 MPLAB ICE 4000

High-Performance

In-Circui t Emu lator

The MPLAB ICE 4000 In-Circuit Emu lator is intende d to

provide the product development engineer with a

complete microcontroller design tool set for high-end

PICmicro MCUs and dsPIC DSCs. Software control of

the MPLAB ICE 4000 In-Circuit Emulator is provided by

the MPLAB Integrated Development Environment,

which allows editing, building, downloading and source

debugging from a single environm ent.

The MPLAB ICE 4000 is a premium emulator system,

providing the features of MPLAB ICE 2000, but with

increased emulation memory and high-speed perfor-

mance for dsPIC30F and PIC18XXXX devices. Its

advanc ed emulator fe atures inc lude complex t riggering

and timing, and up to 2 Mb of emulation memory.

The MPLAB ICE 4000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft Windows 32-bit operating system were

chosen to best make these features available in a

simple, unified application.

22.9 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low-cost, run-time development tool,

connecting to the host PC via an RS-232 or high-speed

USB interface. This tool is based on the Flash PICmicro

MCUs and can be used to develop for these and other

PICmicro MCUs and dsPIC DSCs. The MPLAB ICD 2

utilizes the in-circuit debugging capability built into

the Flash devices. This feature, along with Microchip’s

In-Circuit Serial ProgrammingTM (ICSPTM) protocol,

offers cost-effective, in-circuit Flash debugging from the

graphical user interface of the MPLAB Integrated

Development Environment. This enables a designer to

develop and debug source code by setting breakpoints,

single stepping and watching variables, and CPU

status and peripheral registers. Running at full speed

enables testing hardware and applications in real

time. MPLAB ICD 2 also serves as a development

programmer for selected PICmicro MCU devices.

22.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64 ) for men us an d error m essages and a m odu-

lar, detachable socket assembly to support various

package types. The ICSP™ programming capability

cable assembly is included as a standard item. In

Stand-Alone mode, the MPLAB PM3 Device Program-

mer can read, verify and program PICmicro MCU

devices without a PC connection. It can also set code

protection in this mode. The MPLAB PM3 connects to

the host PC via an RS-232 or USB cable. The MPLAB

PM3 has high-speed communications and optimized

algorithms for quick programming of large memory

device s and inc orporates a n SD/MMC card for file st or-

age and secure data applications.

PIC24H

22.11 PICSTART Plus Development

Programmer

The PICSTART Plus Development Programmer is an

easy-to-use, low-cost, prototype programmer. It

connects to the PC via a COM (RS-232) port. MPLAB

Inte grated Dev elopmen t En vironme nt so ftware makes

using the programmer simple and efficient. The

PICSTART Plus Development Programmer supports

most PICmicro MCU devices in DIP packages up to 40

pins. Larger pin count devices, such as the PIC16C92X

and PIC17C76X, may be supported with an adapter

socket. T he PICSTART Pl us Development

Programmer is CE compli ant.

22.12 PICkit 2 Development Programmer

The PICkit™ 2 Development Programmer is a low-cost

programmer with an easy-to-use interface for pro-

gramming many of Microchip’s baseline, mid-range

and PIC1 8F families of Fl ash memory mic rocontrollers.

The PICkit 2 S tar ter Kit includes a pr ototypin g develop-

ment board, twelve sequential lessons, software and

HI-TECH’s PICC™ Lite C compiler, and is designed to

help get up to speed quickly using PIC® micro-

controllers. The kit provides everything needed to

program, evaluate and develop applications using

Microchip’s powerful, mid-range Flash memory family

of microcontroll ers.

22.13 Demonstration, Development and

Evaluation Boards

A wide variety of demonstration, development and

evaluation boards for various PICmicro MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards incl ude prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The board s suppo rt a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory .

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

for analog filter design, KEELOQ® security ICs, CAN,

IrDA®, PowerSmart® battery management, SEEVAL®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

Check the Microchip web page (www.microchip.com)

and the latest “Product Selector Guide” (DS00148) for

the complete list of demonstration, development and

evaluation kits.

PIC24H

23.0 ELECTRICAL CHARACTERISTICS

This section provides an overview of PIC24H electrical characteristics. Additional information will be provided in future

revisions of this document as it becomes available.

Absolute maximum ratings for the PIC24H family are listed below. Exposure to these maximum rating conditions for

extende d peri ods may aff ec t devi ce re liabil ity. Functio nal o peratio n of t he devi ce at these or a ny other condi tions abov e

the parameters indicated in the operation listings of this specification is not implied.

Absolute Maximum Ratings(Not e 1)

Ambient temperature under bias...............................................................................................................-40°C to +85°C

Storage temperature.............................................................................................................................. -65°C to +150°C

Volta ge on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V

Voltage on any combined analog and digital pin and MCLR, with respect to VSS .........................-0.3V to (VDD + 0.3V)

Voltage on any digital-only pin with respect to VSS .................................................................................. -0.3V to +5.6V

Volta ge on VDDCORE with respect to VSS ................................................................................................ 2.25V to 2.75V

Maximum curr ent o ut of VSS pin ...........................................................................................................................300 mA

Maximum curr ent i nto VDD pin (Note 2)................................................................................................................250 mA

Maximum output current sunk by any I/O pin (Note 3).............................................................................................4 mA

Maximum output current sourced by any I/O pin (N ote 3)........................................................................................4 mA

Maximum current sunk by all ports.......................................................................................................................200 mA

Maximum current sourced by all ports (Note 2)....................................................................................................200 mA

Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions

above those indicated in the operation listings of this specification is not implied. Exposure to maximum

rating conditions for extended periods may affect device reliability.

2: Maximum allowable current is a function of device maximum power dissipation (see Table 23-2).

3: Exceptions are CLKOUT, which is able to sink/source 25 mA, and the VREF+, VREF-, SCLx, SDAx, PGCx

and PGDx pins, which are able to sink/source 12 mA.

PIC24H

23.1 DC Characteristi cs

TABLE 23-1: OPERATING MIPS VS. VOLTAGE

Characteristic VDD Range

(in Volts) Temp Range

(in °C)

Max MIPS

PIC24H

DC5 3.0 -3.6 V -40°C to +85°C 40

TABLE 23-2: THERMAL OPERATING CONDITIONS

Rating Symbol Min Typ Max Unit

PIC24HOperating Junction Temperature Range TJ-40 — +125 °C

Operating Ambient Temperature Range TA-40 — +85 °C

Power Dissipation:

Internal ch ip pow er dis sip ation:

PINT = VDD x (IDD – Σ IOH) PDPINT + PI/OW

I/O Pin Power Dissipation:

I/O = Σ ({VDD – VOH} x IOH) + Σ (VOL x IOL)

Maximum Allowed Power Dissipation PDMAX (TJ – TA)/θJA W

TABLE 23-3: THERMAL PACKAGING CHARACTERISTICS

Characteristic Symbol Typ Max Unit Notes

Package Thermal Resistance, 100-pin TQFP (14x14x1 mm) θJA 48.4 — °C/W 1

Package Thermal Resistance, 100-pin TQFP (12x12x1 mm) θJA 52.3 — °C/W 1

Package T hermal Resistan ce, 80-pin TQFP (12x12x1 mm) θJA 38.7 — °C/W 1

Package T hermal Resistan ce, 64-pin TQFP (10x10x1 mm) θJA 38.3 — °C/W 1

Legend: TBD = To Be Determined

Note 1: Junction to ambient thermal resistance, Theta-JA (θJA) numbers are achieved by package simulations.

TABLE 23-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

Param

No. Symbol Characteristic Min Typ(1) Max Units Conditions

Operating Voltage

DC10 Supply Voltage

VDD 3.0 — 3.6 V

DC12 VDR RAM Data Retention Voltage(2) —2.8—V

DC16 VPOR VDD Start Voltage

to ensure internal

Power-on Reset signal

—V

SS —V

DC17 SVDD VDD Rise Rate

to ensure internal

Power-on Reset signal

0.05 — — V/ms 0-3.3V in 0.1s

0-2.5V in 60 ms

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: This is the limit to which VDD can be lowered without losing RAM data.

PIC24H

TABLE 23-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)

DC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

Parameter

No. Typical(1) Max Units Conditions

Operating Current (IDD)(2)

DC20 27 — mA +25°C 3.3V 10 MIPS

DC20a 26 — mA +85°C

DC21 33 — mA +25°C 3.3V 16 MIPS

DC21a 32 — mA +85°C

DC22 44 — mA +25°C 3.3V 20 MIPS

DC22a 43 — mA +85°C

DC23 60 — mA +25°C 3.3V 30 MIPS

DC23a 58 — mA +85°C

DC24 74 — mA +25°C 3.3V 40 MIPS

DC24a 72 — mA +85°C

Legend: TBD = To Be Determined

Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O

pin load in g an d s w itc hi ng ra te, os cil la tor ty pe , in ternal cod e e xe cut ion p attern and temperat ure, also h av e

an imp act on the current c onsumpti on. The tes t condi tions fo r all IDD measureme nt s are as foll ows : OSC1

driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VSS.

MCLR = VDD, WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are

operational. No peripheral modules are operating; however, every peripheral is being clocked (PMD bits

are all zeroed.

PIC24H

TABLE 23-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)

DC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temp erature -40°C ≤ TA ≤ +85°C for Industrial

Parameter

No. Typical(1) Max Units Conditions

Idle Current (IIDLE): Core OFF Clock ON Base Current(2)

DC40 TBD — mA +25°C 3.3V 10 MIPS

DC40a TBD — mA +85°C

DC41 TBD — mA +25°C 3 .3V 16 MIPS

DC41a TBD — mA +85°C

DC42 TBD — mA +25°C 3 .3V 20 MIPS

DC42a TBD — mA +85°C

DC43 TBD — mA +25°C 3 .3V 30 MIPS

DC43a TBD — mA +85°C

DC44 16.5 — mA +25°C 3 .3V 40 MIPS

DC44a 16 — mA +85°C

Legend: TBD = To Be Determined

Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

2: Base IIDLE current is measured with core off, clock on and all modules turned off. Peripheral Module

Disable SFR registers are zeroed. All I/O pins are configured as inputs and pulled to VSS.

TABLE 23-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)

DC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise st ated)

Operati ng tem pera ture -40°C ≤ TA ≤ +85°C for Industrial

Parameter

No. Typical(1) Max Units Conditions

Power-Down Current (IPD)(2)

DC60 200 — μA+25°C

3.0V Base Power-Down Current(3,4)

DC60a TBD — μA+85°C

DC61 TBD — μA+25°C

3.0V Watchdog Ti mer Current: ΔIWDT(3)

DC61a TBD — μA+85°C

Legend: TBD = To Be Determined

Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

2: Base IPD is measured with all peripherals and clocks shut down. All I/O pins are configured as inputs and

pulled to VSS. WDT, etc., are all switched off.

3: The Δ current is the additional current consumed when the module is enabled. This current should be

added to the base IPD current.

4: These currents are measured on the device containing the most memory in this family.

PIC24H

TABLE 23-8: DC CHARACTERISTICS:DOZE CURRENT (IDOZE)

DC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

Parameter No. Typical(1) Max Doze

Ratio Units Conditions

DC70a 42 — 1:2 mA

25°C 3.3V

40 MIPS

DC70f 26 — 1:64

DC70g 25 — 1:128

DC71a 41 — 1:2 mA

85°C

DC71f 25 — 1:64

DC71g 24 — 1:128

Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

PIC24H

TABLE 23-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

Param

No. Symbol Characteristic Min Typ(1) Max Units Conditions

VIL Input Low Voltage

DI10 I/O pins VSS —0.2VDD V

DI15 MCLR VSS —0.2VDD V

DI16 OSC1 (XT mode) VSS —0.2VDD V

DI17 OSC1 (HS mode) VSS —0.2VDD V

DI18 SDAx, SCLx VSS —0.3VDD V SMBus dis ab led

DI19 SDAx, SCLx VSS —0.2VDD V SMBus ena ble d

VIH Input High Voltage

DI20 I/O pins :

with analog functions

digital-only 0.8 VDD

0.8 VDD —

—VDD

5.5 V

DI25 MCLR 0.8 VDD —VDD V

DI26 OSC1 (XT mode) 0.7 VDD —VDD V

DI27 OSC1 (HS mode) 0.7 VDD —VDD V

DI28 SDAx, SCLx 0.7 VDD —VDD V SMB us dis ab led

DI29 SDAx, SCLx 0.8 VDD —VDD V SMB us ena ble d

ICNPU CNx Pull-up Current

DI30 50 250 400 μAV

DD = 3.3V, VPIN = VSS

IIL Input Leakage Current(2)(3)

DI50 I/O ports — TBD TBD μAVSS ≤ VPIN ≤ VDD,

Pin at high-impedance

DI51 Analog Input Pins — TBD TBD μAV

SS ≤ VPIN ≤ VDD,

Pin at high-impedance

DI55 MCLR —TBDTBDμAVSS ≤ VPIN ≤ VDD

DI56 OSC1 — TBD TBD μAVSS ≤ VPIN ≤ VDD,

XT and HS modes

Legend: TBD = To Be Determined

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

PIC24H

TABLE 23-12: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS

TABLE 23-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industri al

Param

No. Symbol Characteristic Min Typ(1) Max Units Conditions

VOL Output Low Voltage

DO10 I/O ports — — 0.4 V IOL = TBD mA, VDD = 3.3V

DO16 OSC2/CLKO — — 0.4 V IOL = TBD mA, VDD = 3.3V

VOH Output High Voltage

DO20 I/O ports 2 .4 — — V IOH = -3.0 mA, VDD = 3.3V

DO26 OSC2/CLKO 2.4 — — V IOH = -1.3 mA, VDD = 3.3V

Legend: TBD = To Be Determined

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

TABLE 23-11: DC CHARACTERISTICS: PROGRAM MEMORY

DC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industri al

Param

No. Symbol Characteristic Min Typ(1) Max Units Conditions

Program Flash Memory

D130 EPCell Endu rance 100 1000 — E/W -40°C to +85°C

D131 VPR VDD for Read VMIN —3.6VVMIN = Minimum operating

voltage

D132B VPEW VDD for Self-Timed Write VMIN —3.6VVMIN = Minimum operating

voltage

D133A TIW Self-Timed Write Cycle Time — 1.5 — ms

D134 TRETD Characteristic Retention 20 — — Year Provided no other specifications

are violated

D135 IDDP Supply Current during

Programming —10—mA

D136 TRW Self-Timed Row Write Cycle

Time —1.6—ms

D137 TPE Self-Timed Page Erase

Cycl e Time —20.5— ms

D138 TWW Word Write Cycle Time 20 — 40 μs

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

Operating Conditions: -40°C < TA < +85°C (unless otherwise stated)

Param

No. Symbol Characteristics Min Typ Max Units Comments

CEFC External Filter Cap ac itor

Value 110—μF Capac itor must be l ow series

resistance (< 5 ohms)

PIC24H

23.2 AC Characteristi cs and Timing

Parameters

The information contained in this section defines

PIC24H AC characteristics and timing parameters.

TABLE 23-13: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

FIGURE 23-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

TABLE 23-14: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise st ated)

Operati ng tem pera ture -40°C ≤ TA ≤ +85°C for Industrial

Operati ng voltage VDD range as described in Section 23.0 “Electrical

Characteristics”.

Param

No. Symbol Characteristic Min Typ(1) Max Units Conditions

DO50 COSC2 OSC2/SOSC2 pin — — 15 pF In XT and HS modes when

external clock is used to drive

OSC1

DO56 CIO All I/O pins and OSC2 — — 50 pF EC mode

DO58 CBSCLx, SDAx — — 400 pF In I2C™ mode

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

VDD/2

VSS

RL= 464Ω

CL= 50 pF for all pins except OSC2

15 pF for OSC2 output

Load Cond itio n 1 – for all pins except OSC2 Load Condition 2 – for OSC2

PIC24H

FIGURE 23-2: EXTERNAL CLOCK TIMING

Q1 Q2 Q3 Q4

OSC1

CLKO

Q1 Q2 Q3 Q4

OS20

OS25

OS30 OS30

OS40

OS41

OS31 OS31

TABLE 23-15: EXTERNAL CLOCK TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 3.6V

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

Param

No. Symb Characteristic Min Typ(1) Max Units Conditions

OS10 FIN External CLKI Frequency

(External clocks allowed only

in EC and ECPLL modes)

0.8

4—

—64

8MHz

MHz EC

ECPLL

Oscilla tor C rys tal Frequency 3

—

MHz

kHz

XTPLL

HSPLL

SOSC

OS20 TOSC TOSC = 1/ FOSC 12.5 — DC ns

OS25 TCY Instr uction Cycle Time(2) 25 — DC ns

OS30 TosL,

TosH External Clock in (OSC1)

High or Low Ti me 0.625 x TOSC ——nsEC

OS31 TosR,

TosF External Clock in (OSC1)

Rise or Fall Time ——TBDnsEC

OS40 TckR CLKO Rise Time(3) —6TBDns

OS41 TckF CLKO Fall Time(3) —6TBDns

Legend: TBD = To Be Determined

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values

are based on characterization data for that particular oscillator type under standard operating conditions

with the device executing code. Exceeding these specified limits may result in an unstable oscillator

operation and/or higher than expected current consumption. All devices are tested to operate at “min.”

values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the

“max.” cycle time limit is “DC” (no clock) for all devices.

3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.

PIC24H

TABLE 23-16: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V)

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise sta ted)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

OS50 FPLLI PLL Voltage Controlled

Oscillator (VCO) Input

Frequency Range

0.8 — 8 MHz ECPLL, HSPLL, XTPLL

modes

OS51 FSYS On-Chip VCO System

Frequency 100 — 200 MHz

OS52 TLOC PLL Start-up Time (Lock Time) TBD 100 TBD μs

OS53 DCLK CLKO Stability (Jitter) TBD 1 TBD % Measured over 100 ms

period

Legend: TBD = To Be Determined

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

TABLE 23-17: AC CHARACTERISTICS: INTERNAL RC ACCURACY

AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

Param

No. Characteristic Min Typ Max Units Conditions

Internal FRC Accuracy @ 7.3728 MHz(1)

F20 FRC TBD — TBD % +25°C VDD = 3.0-3.6V

TBD — TBD % -40°C ≤ TA ≤ +85°C VDD = 3.0-3.6V

Legend: TBD = To Be Determined

Note 1: Frequency calibrated at 25°C and 3.3V. TUN bits can be used to compensate for temperature drift.

TABLE 23-18: INTERNAL RC ACCURACY

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industri al

Param

No. Characteristic Min Typ Max Units Conditions

LPRC @ 32.768 kHz(1)

F21 TBD — TBD % +25°C VDD = 3.0-3.6V

TBD — TBD % -40°C ≤ TA ≤ +85°C VDD = 3.0-3.6 V

Legend: TBD = To Be Determined

Note 1: Change of LPRC frequency as VDD changes .

PIC24H

FIGURE 23-3: CLKO AND I/O TIMING CHARACTERISTICS

Note: Refer to Figure 23-1 for load conditions.

I/O Pin

(Input)

I/O Pin

(Output)

DI35

Old Value New Value

DI40

DO31

DO32

TABLE 23-19: CLKO AND I/O TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise st ated)

Operati ng tem pera ture -40°C ≤ TA ≤ +85°C for Industrial

Param

No. Symbol Characteristic Min Typ(1) Max Units Conditions

DO31 TIOR Port Output Rise Time — 10 25 ns —

DO32 TIOF Port Output Fall Time — 10 25 ns —

DI35 TINP INTx Pin High or Low Time (output) 20 — — ns —

DI40 TRBP CNx High or Low Time (input) 2 — — TCY —

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

PIC24H

FIGURE 23-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING CHARACTERISTICS

VDD

MCLR

Internal

POR

PWRT

Time-out

OSC

Time-out

Internal

Reset

Watchdog

Timer

Reset

SY11

SY10

SY20

SY13

I/O Pins

SY13

Note: Refer to Figure 23-1 for load conditions.

FSCM

Delay

SY35

SY30

SY12

PIC24H

TABLE 23-20: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SY10 TMCLMCLR Pulse Width (low) 2 — — μs -40°C to +85°C

SY11 TPWRT Power-up Timer Period 0.75

1.5

128

1.25

2.5

160

ms -40°C to +85°C

User programmable

SY12 TPOR Power-on Reset Delay 3 10 30 μs -40°C to +85°C

SY13 TIOZ I/O High-Impedance from MCLR

Low or Watchdog Timer Reset —0.81.0μs

SY20 TWDT1 Watchdog Timer Time-out Period

(No Prescaler) 1.8 2.0 2.2 ms VDD = 5V, -40°C to +85°C

TWDT2 1.9 2.1 2.3 ms VDD = 3V, -40°C to +85°C

SY30 TOST Oscillator Start-up Timer Period — 1024 TOSC ——TOSC = OSC1 period

SY35 TFSCM Fail-Safe Clock Monitor Delay — 500 900 μs -40°C to +85°C

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated.

3: Characterized by design but not tested.

PIC24H

FIGURE 23-5: TIMER1, 2, 3, 4, 5, 6, 7, 8 AND 9 EXTERNAL CLOCK TIMING CHARACTERISTICS

TABLE 23-21: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)

Note: Refer to Figure 23-1 for load conditions.

Tx11

Tx15

Tx10

Tx20

TMRx OS60

TxCK

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operati ng tem pe rature -40°C ≤ TA ≤ +85°C

Param

No. Symbol Characteristic Min Typ Max Units Conditions

TA10 TTXH TxCK High Time Synchronous,

no prescaler 0.5 TCY + 20 — — ns Must also meet

parameter TA15

Synchronous,

with presca ler 10 — — ns

Asynchronous 10 — — ns

TA11 TTXL TxCK Low Time Synchronous,

no prescaler 0.5 TCY + 20 — — ns Must also meet

parameter TA15

Synchronous,

with presca ler 10 — — ns

Asynchronous 10 — — ns

TA15 TTXP TxCK Input Period Synchronous,

no prescaler TCY + 10 — — ns

Synchronous,

with presca ler Greater of:

20 ns or

(TCY + 40)/N

— — — N = prescale

value

(1, 8, 64, 256)

Asynchronous 20 — — ns

OS60 Ft1 SOSC1/T 1CK Oscillator Input

frequency Ran ge (osci llator enable d

by setting bit TCS (T1CON<1>))

DC — 50 kHz

TA20 TCKEXTMRL Delay from External TxCK Clock

Edge to Timer Increment 0.5 TCY 1.5 TCY —

Note 1: Timer1 is a Type A.

PIC24H

TABLE 23-22: TIMER2, TIMER4, TIMER6 AND TIMER8 EXTERNAL CLOCK TIMING

REQUIREMENTS

TABLE 23-23: TIMER3, TIMER5, TIMER7 AND TIMER9 EXTERNAL CLOCK TIMING

REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operati ng tem pe rature -40°C ≤ TA ≤ +85°C

Param

No. Symbol Characteristic Min Typ Max Units Conditions

TB10 TtxH TxCK High Time Synchronous,

no prescaler 0.5 TCY + 20 — — ns Must also meet

parameter TB15

Synchronous,

with prescale r 10 — — ns

TB11 TtxL TxCK Low Time Synchronous,

no prescaler 0.5 TCY + 20 — — ns Must also meet

parameter TB15

Synchronous,

with prescale r 10 — — ns

TB15 TtxP TxCK Input Period Synchronous,

no prescaler TCY + 10 — — ns N = prescale

value

(1, 8, 64, 256)

Synchronous,

with prescale r Greater of:

20 ns or

(TCY + 40)/N

TB20 TCKEXTMRL Delay from External TxCK Clock

Edge to Timer Increment 0.5 TCY — 1 .5 TCY —

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise st ated)

Operati ng tem pera ture -40°C ≤ TA ≤ +85°C

Param

No. Symbol Characteristic Min Typ Max Units Conditions

TC10 TtxH TxCK High Time Synchronous 0.5 TCY + 20 — — ns Must also meet

parameter TC15

TC11 TtxL TxCK Low Time Synchronous 0.5 TCY + 20 — — ns Must also meet

parameter TC15

TC15 TtxP TxCK Inpu t Period Synchronou s,

no prescaler TCY + 10 — — ns N = prescale

value

(1, 8, 64, 256)

Synchronous,

with prescaler Greater of:

20 ns or

(TCY + 40)/N

TC20 TCKEXTMRL Delay from External TxCK Clock

Edge to Timer Increment 0.5 TCY —1.5 TCY —

PIC24H

FIGURE 23-6: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS

TABLE 23-24: INPUT CAPTURE TIMING REQUIREMENTS

FIGURE 23-7: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS

TABLE 23-25: OUTPUT COMPARE MODULE TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C

Param

No. Symbol Characteristic(1) Min Max Units Conditions

IC10 TccL ICx Input Low Time No Prescaler 0.5 TCY + 20 — ns

With Prescaler 10 — ns

IC11 TccH ICx Input High Time No Prescaler 0.5 TCY + 20 — ns

With Prescaler 10 — ns

IC15 TccP ICx Input Period (2 TCY + 40)/N — ns N = prescale

va lue (1, 4, 16)

Note 1: These parameters are characterized but not tested in manufacturing.

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Ope rati ng temperature -40°C ≤ TA ≤ +85°C

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

OC10 TccF OCx Output Fall Time — — — ns See parameter D032

OC11 TccR OCx Output Rise Time — — — ns See parameter D031

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” colum n is at 5V, 25°C unless otherwi se st ated. Parameters are for des ign guid anc e on ly and

are not tested.

ICx

IC10 IC11

IC15

Note: Refer to Figure 23-1 for load conditio ns .

OCx

OC11 OC10

(Output Compare

Note: Refer to Figure 23-1 for load conditions.

or PWM Mode)

PIC24H

FIGURE 23-8: OC/PWM MODULE TIMING CHARACTERISTICS

TABLE 23-26: SIMPLE OC/PWM MODE TIMING REQUIREMENTS

FIGURE 23-9: SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS

OCFA/OCFB

OCx

OC20

OC15

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

OC15 TFD Fault Input to PWM I/O

Change — — 50 ns —

OC20 TFLT Fault Input Pulse Width 50 — — ns —

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data i n “Typ” column is at 5V, 25°C unless o therwise s t ated. Paramete rs are for design guida nc e on ly and

are not tested.

SCKx

(CKP = 0)

SCKx

(CKP = 1)

SDOx

SDIx

SP11 SP10

SP40 SP41

SP21

SP20

SP35

SP20

SP21

MSb LSb

Bit 14 - - - - - -1

MSb In LSb In

Bit 14 - - - -1

SP30

SP31

Note: Refer to Figure 23-1 for load conditions.

PIC24H

TABLE 23-27: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS

FIGURE 23-10: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operati ng tem per ature -40°C ≤ TA ≤ +85°C

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SP10 TscL SCKx Output Low Time(3) TCY/2 — — ns —

SP11 TscH SCKx Outp ut High Time(3) TCY/2 — — ns —

SP20 TscF SCKx Output Fall Time(4) — — — ns See parameter D032

SP21 TscR SCKx Out put Rise Time(4) — — — ns See parameter D031

SP30 Td oF SDOx Data Output Fall Time(4) — — — ns See parameter D032

SP31 T doR SDOx Data Output Rise Time(4) — — — ns See parameter D031

SP35 TscH2doV,

TscL2doV SDOx Data Output Valid after

SCKx Edge — — 30 ns —

SP40 TdiV2scH,

TdiV2scL Setup Time of SDIx Data Input

to SCKx Edge 20 — — ns —

SP41 TscH2diL,

TscL2diL Hold Time of SDIx Data Input

to SCKx Edge 20 — — ns —

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data i n “Typ” column is at 5V, 25°C unless o the rw is e stated. Parameters ar e for design guidanc e on ly and

are not tested.

3: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not

violate this specificat ion.

4: Assumes 50 pF load on all SPIx pins.

SCKX

(CKP = 0)

SCKX

(CKP = 1)

SDOX

SDIX

SP36

SP30,SP31

SP35

MSb

MSb In

Bit 14 - - - - - -1

LSb In

Bit 14 - - - -1

LSb

Note: Refer to Figure 23-1 for load conditions.

SP11 SP10 SP20

SP21

SP20

SP40

SP41

PIC24H

TABLE 23-28: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENT S

FIGURE 23-11: SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SP10 TscL SCKx Output Low Time(3) TCY/2 — — ns —

SP11 TscH SCKx Output High Time(3) TCY/2 — — ns —

SP20 TscF S CKx Outpu t Fall Time(4) — — — ns See parameter D032

SP21 TscR SCKx Ou tput Ris e Time(4) — — — ns See parameter D031

SP30 TdoF SDOx Data Output Fall

Time(4) — — — ns See parameter D032

SP31 TdoR SDOx Data Output Rise

Time(4) — — — ns See parameter D031

SP35 TscH2doV,

TscL2doV SDOx Data Output Valid after

SCKx Edge ———ns —

SP36 TdoV2sc,

TdoV2scL SDOx Data Output Setup to

First SCKx Edge 30 — — ns —

SP40 TdiV2scH,

TdiV2scL Setup Time of SDIx Data

Input to SCKx Edge 20 — — ns —

SP41 TscH2diL,

TscL2diL Hold Time of SDIx Data Input

to SCKx Edge 20 — — ns —

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data i n “Typ” column is at 5V, 25°C unless o therwise s t ated. Paramete rs are for design guida nc e on ly and

are not tested.

3: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not

violate this specificat ion.

4: Assumes 50 pF load on all SPIx pins.

SSX

SCKX

(CKP =

)

SCKX

(CKP =

)

SDOX

SP50

SP40 SP41

SP30,SP31 SP51

SP35

MSb LSb

Bit 14 - - - - - -1

MSb In Bit 14 - - - -1 LSb In

SP52

SP73

SP72

SP73

SP71 SP70

Note: Refer to Figure 23-1 for load conditions.

SDIX

PIC24H

TABLE 23-29: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SP70 TscL SCKx Input Low Time 30 — — ns —

SP71 TscH SCKx Input High Time 30 — — ns —

SP72 TscF SCKx Input Fall Time(3) — 1025ns —

SP73 TscR SCKx Input Rise Time(3) — 1025ns —

SP30 TdoF SDOx Data Output Fall Time(3) — — — ns See parameter D032

SP31 TdoR SDOx Data Output Rise Time(3) — — — ns See parameter D031

SP35 TscH2doV,

TscL2doV SDOx Data Output Valid after

SCKx Edge — — 30 ns —

SP40 TdiV2scH,

TdiV2scL Setup Time of SDIx Data Input

to SCKx Edge 20 — — ns —

SP41 TscH2diL,

TscL2diL Hold Time of SDIx Data Input

to SCKx Edge 20 — — ns —

SP50 TssL2scH,

TssL2scL SSx ↓ to SCKx ↑ or SCKx Input 120 — — ns —

SP51 TssH2doZ SSx ↑ to SD Ox O u tput

High-Impedance(3) 10 — 50 ns —

SP52 TscH2ssH

TscL2ssH SSx after SCKx Edge 1.5 TCY +40 — — ns —

Note 1: These parameters are characterized but not tested in manufacturing.

2: Dat a in “Typ” colu mn is at 5V, 25°C unless oth erwise s tate d. Parame ters are for de sign gu idanc e only an d

are not t ested.

3: Assumes 50 pF load on all SPIx pins.

PIC24H

FIGURE 23-12: SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS

SSx

SCKx

(CKP = 0)

SCKx

(CKP = 1)

SDOx

SDI

SP50

SP60

SDIx

SP30,SP31

MSb Bit 14 - - - - - -1 LSb

SP51

MSb In Bit 14 - - - -1 LSb In

SP35

SP52

SP73

SP72

SP73

SP71 SP70

SP40 SP41

Note: Refer to Figure 23-1 for load conditions.

PIC24H

TABLE 23-30: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operati ng tem per ature -40°C ≤ TA ≤ +85°C

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

SP70 TscL SCKx Input Low Time 30 — — ns —

SP71 TscH SCKx Input High Time 30 — — ns —

SP72 TscF SCKx Inp ut Fall Time(3) —1025ns —

SP73 TscR SCKx Input Rise Time(3) —1025ns —

SP30 TdoF SDOx Data Output Fall Time(3) — — — ns See parameter D032

SP31 TdoR SDOx Data Output Rise Time(3) — — — ns See para meter D031

SP35 TscH2doV,

TscL2doV SDOx Data Output Valid after

SCKx Edge — — 30 ns —

SP40 TdiV2scH,

TdiV2scL Setup Time of SDIx Data Input

to SCKx Edge 20 — — ns —

SP41 TscH2diL,

TscL2diL Hold Time of SDIx Data Input

to SCKx Edge 20 — — ns —

SP50 TssL2scH,

TssL2scL SSx ↓ to SCKx ↓ or SCKx ↑

Input 120 — — ns —

SP51 TssH2doZ SSx ↑ to SDOX Output

High-Impedance(4) 10 — 50 ns —

SP52 TscH2ssH

TscL2ssH SSx ↑ after SCKx Edge 1.5 TCY + 40 — — ns —

SP60 TssL2doV SDOx Data Output Va lid after

SSx Edge — — 50 ns —

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data i n “Typ” column is at 5V, 25°C unless o the rw is e stated. Parameters ar e for design guidanc e on ly and

are not tested.

3: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not

violate this specificat ion.

4: Assumes 50 pF load on all SPIx pins.

PIC24H

FIGURE 23-13: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)

FIGURE 23-14: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)

IM31 IM34

SCLx

SDAx

Start

Condition Stop

Condition

IM30 IM33

Note: Refer to Figure 23-1 for load conditions.

IM11 IM10 IM33

IM11 IM10

IM20

IM26 IM25

IM40 IM40 IM45

IM21

SCLx

SDAx

Out

Note: Refer to Figure 23-1 for load conditions.

PIC24H

TABLE 23-31: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C

Param

No. Symbol Characteristic Min(1) Max Units Conditions

IM10 TLO:SCL Clo ck Lo w Time 100 kHz mode TCY/2 (BRG + 1) — μs—

400 kHz mode TCY/2 (BRG + 1) — μs—

1 MHz mode(2) TCY/2 (BRG + 1) — μs—

IM11 THI:SCL Clock High Time 100 kH z mode TCY/2 (BRG + 1) — μs—

400 kHz mode TCY/2 (BRG + 1) — μs—

1 MHz mode(2) TCY/2 (BRG + 1) — μs—

IM20 TF:SCL SDAx and SCLx

Fall Time 1 00 kHz mode — 300 ns CB is specif ied to be

from 10 to 400 pF

400 kHz mode 20 + 0.1 CB300 ns

1 MHz mode(2) — 100 ns

IM21 TR:SCL SDAx and SCLx

Rise Time 100 kHz mo de — 1000 ns CB is s pecified to be

from 10 to 400 pF

400 kHz mode 20 + 0.1 CB300 ns

1 MHz mode(2) — 300 ns

IM25 TSU:DAT Data Input

Setup Time 100 kHz mode 250 — ns —

400 kHz mode 100 — ns

1 MHz mode(2) TBD — ns

IM26 THD:DAT Data Input

Hold Time 100 kHz mode 0 — ns —

400 kHz mode 0 0.9 μs

1 MHz mode(2) TBD — ns

IM30 TSU:STA Start Cond itio n

Setup Time 100 kHz mode TCY/2 (BRG + 1) — μs Onl y r ele va nt for

Repeated Start

condition

400 kHz mode TCY/2 (BRG + 1) — μs

1 MHz mode(2) TCY/2 (BRG + 1) — μs

IM31 THD:STA Start Co nd itio n

Hold Time 100 kHz mode TCY/2 (BRG + 1) — μs After this period the

first clock pulse i s

generated

400 kHz mode TCY/2 (BRG + 1) — μs

1 MHz mode(2) TCY/2 (BRG + 1) — μs

IM33 TSU:STO Stop Condition

Setup Time 100 kHz mode TCY/2 (BRG + 1) — μs—

400 kHz mode TCY/2 (BRG + 1) — μs

1 MHz mode(2) TCY/2 (BRG + 1) — μs

IM34 THD:STO Stop Conditi on 100 kHz mode TCY/2 (BRG + 1) — ns —

Hold Time 400 kHz mode TCY/2 (BRG + 1) — ns

1 MHz mode(2) TCY/2 (BRG + 1) — ns

IM40 TAA:SCL Output Valid

From Clock 100 kHz mode — 3500 ns —

400 kHz mode — 1000 ns —

1 MHz mode(2) ——ns —

IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be

free before a new

transmission can start

400 kHz mode 1.3 — μs

1 MHz mode(2) TBD — μs

IM50 CBBus Capacitive Loading — 400 pF

Legend: TBD = To Be Determined

Note 1: BRG is the value o f th e I 2C Bau d Rate Generato r. Refer to Section 21 . “Int er-Inte grate d Circ uit (I2C™)”

in the “dsPIC30F Family Reference Manual” (DS70046).

2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).

PIC24H

FIGURE 23-15: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)

FIGURE 23-16: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)

IS31 IS34

SCLx

SDAx

Start

Condition Stop

Condition

IS30 IS33

IS30 IS31 IS33

IS11

IS10

IS20

IS26 IS25

IS40 IS40 IS45

IS21

SCLx

SDAx

Out

PIC24H

TABLE 23-32: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)

AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operati ng tem pera ture -40°C ≤ TA ≤ +85°C

Param

No. Symbol Characteristic Min Max Units Conditions

IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — μs Device must operate at a

minimum of 1.5 MHz

400 kHz mode 1.3 — μs Device must operate at a

minimum of 10 MHz

1 MHz mode(1) 0.5 — μs—

IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — μs Device must operate at a

minimum of 1.5 MHz

400 kHz mode 0.6 — μs Device must operate at a

minimum of 10 MHz

1 MHz mode(1) 0.5 — μs—

IS20 TF:SCL SDAx and SCLx

Fall Time 100 kHz mode — 300 ns CB is specified to be from

10 to 400 pF

400 kHz mode 20 + 0.1 CB300 ns

1 MHz mode(1) — 100 ns

IS21 TR:SCL SDAx and SCLx

Rise Time 100 kHz mode — 1000 ns CB is specified to be from

10 to 400 pF

400 kHz mode 20 + 0.1 CB300 ns

1 MHz mode(1) — 300 ns

IS25 TSU:DAT Data Input

Setup Time 100 kHz mode 250 — ns —

400 kHz mode 100 — ns

1 MHz mode(1) 100 — ns

IS26 THD:DAT Data Input

Hold Time 100 kHz mode 0 — ns —

400 kHz mode 0 0.9 μs

1 MHz mode(1) 00.3μs

IS30 TSU:STA Start Conditi on

Setup Time 100 kHz mode 4.7 — μs Only relevant for Repeated

Start condition

400 kHz mode 0.6 — μs

1 MHz mode(1) 0.25 — μs

IS31 THD:STA Start Condition

Hold Time 100 kHz mode 4.0 — μs After this period, the first

clock pulse is generated

400 kHz mode 0.6 — μs

1 MHz mode(1) 0.25 — μs

IS33 TSU:STO Stop Condition

Setup Time 100 kHz mode 4.7 — μs—

400 kHz mode 0.6 — μs

1 MHz mode(1) 0.6 — μs

IS34 THD:STO Stop Condition

Hold Time 100 kHz mode 4000 — ns —

400 kHz mode 600 — ns

1 MHz mode(1) 250 ns

IS40 TAA:SCL Output V alid From

Clock 100 kHz mode 0 3500 ns —

400 kHz mode 0 1000 ns

1 MHz mode(1) 0 350 ns

IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be free

before a new transmission

can start

400 kHz mode 1.3 — μs

1 MHz mode(1) 0.5 — μs

IS50 CBBus Capacitive Loading — 400 pF —

Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).

PIC24H

FIGURE 23-17: ECAN™ MODULE I/O TIMING CHARACTERISTICS

TABLE 23-33: ECAN™ MODULE I/O TIMING REQUIREMENTS

CiTx Pin

(output)

CA10 CA11

Old Value New Value

CA20

CiRx Pin

(input)

AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V

(unless oth erwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C

Param

No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions

CA10 TioF Port Output Fall Time — — — ns See parameter D032

CA11 TioR Port Output Rise Time — — — ns See parameter D031

CA20 Tcwf Pulse Width to Trigger

CAN Wake-up Filter 500 ns —

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data i n “Typ” column is at 5V, 25°C unless o therwise s t ated. Paramete rs are for design guida nc e on ly and

are not tested.

PIC24H

TABLE 23-34: A/D MODULE SPECIFICATIONS

AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C

Param

No. Symbol Characteristic Min. Typ Max. Units Conditions

Device Supply

AD01 AVDD Module VDD Supply Greate r of

VDD - 0.3

or 3.0

— Lesser of

VDD + 0.3

or 3.6

V—

AD02 AVSS Module VSS Supply VSS - 0.3 — VSS + 0.3 V —

Reference Inputs

AD05 VREFH Reference Voltage High AVSS + 1.7 — AVDD V—

AD06 VREFL Reference Voltage Low AVSS —AVDD - 1.7 V —

AD07 VREF Absolute Reference

Voltage AVSS – 0.3 — AVDD + 0.3 V —

AD08 IREF Current Drain — 200

.001 300

3μA

μAA/D operati ng

A/D off

Analog Input

AD10 VINH-VINL Full-Scale Input Span VREFL VREFH VSee Note

AD11 VIN Absolute Input Voltage AVSS – 0.3 AVDD + 0.3 V —

AD12 — Leakage Current — ±0.001 ±0.610 μAVINL = AVSS = VREFL =

0V, AVDD = VREFH = 5V

Source Impedance =

2.5 KΩ

AD13 — Leakage Current — ±0.001 ±0.610 μAVINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

Source Impedance =

2.5 KΩ

AD17 RIN Recomm ended Impedance

of Analog Voltage Source ——1K

2.5K Ω

Ω10-bit

12-bit

ADC Accuracy (12-bit Mode)

AD20a Nr Resolution 12 data bits bits

AD21a INL Integral Nonlinearity(2) ——<±2LSbVINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

AD22a DNL Differential Nonlinearity(2) ——<±1LSbVINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

AD23a GERR Gain Error(2) TBD TBD ±3 LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

AD24a EOFF Offset Error(2) TBD TBD ±2 LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

AD25a — Monotonicity(1) — — — — Guaranteed

Dynamic Performance (12-bit Mode)

AD30a THD Total Harmoni c Di sto rtio n — TBD — dB —

AD31a SINAD Signal to Noise and

Distortion —TBD— dB —

Legend: TBD = To Be Determined

Note 1: The A/D conv ers io n resul t neve r decre as es w ith an incr ea se in the inp ut vol t ag e, and has no miss in g

codes.

2: Measurements taken with external VREF+ and VREF- used as the ADC voltage reference.

PIC24H

AD32a SFDR Spurious Free Dynamic

Range —TBD— dB —

AD33a FNYQ Input Signal Bandwidth — — 250 kHz —

AD34a ENOB Effective Number of Bits — TBD TBD bits —

ADC Accuracy (10-bit Mode)

AD20b Nr Resolution 10 data bits bits

AD21b INL Integral Nonlinearity — TBD <±2 LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

AD22b DNL Differential Nonlinearity — TBD <±1 LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

AD23b GERR Gain Error — TBD <±3 LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

AD24b EOFF Offset Error — TBD <±2 LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

AD25b — Monotonicity(1) — — — — Guaranteed

Dynamic Performance (10-bit Mode)

AD30b THD Total Harm oni c Disto r tio n — — — dB —

AD31b SINAD Signal to Noise and

Distortion —TBD— dB —

AD32b SFDR Spurious Free Dynamic

Range —TBD— dB —

AD33b FNYQ Input Signal Bandwidth — — 550 kHz —

AD34b ENOB Effective Number of Bits — TBD TBD bits —

TABLE 23-34: A/D MODULE SPECIFICATIONS (CONTINUED)

AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C

Param

No. Symbol Characteristic Min. Typ Max. Units Conditions

Legend: TBD = To Be Determined

Note 1: The A/D conv ers io n resul t neve r decre as es w ith an incr ea se in the inp ut vol t ag e, and has no miss in g

codes.

2: Measurements taken with external VREF+ and VREF- used as the ADC voltage reference.

PIC24H

FIGURE 23-18: A/D CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS

(CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)

AD55

TSAMP

Clear SAMPSet SAMP

AD61

ADCLK

Instruction

SAMP

ch0_dischrg

ch1_samp

AD60

CONV

ADxIF

Buffer(0)

Buffer(1)

1 2 3 4 5 6 8 5 6 7

1– Software sets ADxCON. SAMP to start sampling.

2– Sampling starts after discharge period. TSAMP is described in Section 17 in the “d sPIC 30F Fam ily Reference Manu al”

3– Software clears ADxCON. SAMP to start conversion.

4– Sampling ends, conversion sequence starts.

5– Convert bit 9.

8– One TAD for end of conversion.

AD50

ch0_samp

ch1_dischrg

eoc

AD55

6– Convert bit 8.

7– Convert bit 0.

Execution

(DS70046).

PIC24H

FIGURE 23-19: A/D CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01,

SIMSAM = 0, AS AM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)

AD55

TSAMP

Set ADON

ADCLK

Instruction

SAMP

ch0_dischrg

ch1_samp

CONV

ADxIF

Buffer(0)

Buffer(1)

1 2 3 4 5 6 4 5 6 8

1– Software sets ADxCON. ADON to start AD operation.

2– Sampling starts after discharge period.

3– Convert bit 9.

4– Convert bit 8.

5– Convert bit 0.

AD50

ch0_samp

ch1_dischrg

eoc

7 3

AD55

6– One TAD for end of conversion.

7– Begin conversion of next channel.

8– Sample for time specified by SAMC<4:0>.

TSAMP TCONV

3 4

Execution

TSAMP is described in the “dsPIC30F

Family Reference Manual” (DS70046), Section 17.

PIC24H

TABLE 23-35: A/D CONVERSION (10-BIT MODE) TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C

Param

No. Symbol Characteristic Min. Typ(1) Max. Units Conditions

Clock Parameters

AD50 TAD A/D Clock Period(2) 70 — — ns TCY = 70 ms, ADxCON3

in default state

AD51 tRC A/D Internal RC Oscillator Period — 250 — ns —

Conversion Rate

AD55 tCONV Conversion Time — 12 TAD —— —

AD56 FCNV Throughput Rate — — 1.1 Msps —

AD57 TSAMP Sample Time — 1 TAD —— —

Timing Parameters

AD60 tPCS Conversion Start from Sample

Trigger(3) —1.0 TAD — — Auto-Convert Trigger

(SSRC<2:0> = 111) not

selected

AD61 tPSS Sample Start from Setting

Sample (SAMP) bit 0.5 TAD — 1.5 TAD ——

AD62 tCSS Conversion Completion to

Sample Start (ASAM = 1)(3) —0.5 TAD —— —

AD63 tDPU Time to Stabilize Analog Stage

from A/D Off to A/D On(3) —20—μs—

Note 1: These parameters are characterized but not tested in manufacturing.

2: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity

performance, especially at elevated temperatures.

3: Characterized by design but not tested.

PIC24H

FIGURE 23-20: A/D CONVERSION (12-BIT MODE) TIMING CHARACTERISTICS

(ASAM = 0, SSRC<2:0> = 000)

AD55

TSAMP

Clear SAMPSet SAMP

AD61

ADCLK

Instruction

SAMP

ch0_dischrg

ch0_samp

AD60

CONV

ADxIF

Buffer(0)

1 2 3 4 5 6 87

1– Software sets ADxCON. SAMP to start sampling.

2– Sampling starts after discharge period.

3– Software clears ADxCON. SAM P to start conversion.

4– Sampling ends, conversion sequence starts.

5– Convert bit 11.

9– One TAD for end of conversion.

AD50

eoc

6– Convert bit 10.

7– Convert bit 1.

8– Convert bit 0.

Execution

TSAMP is described in the “dsPIC30F Family Reference Manual” (DS70046), Section 17.

PIC24H

TABLE 23-36: A/D CONVERSION (12-BIT MODE) TIMING REQUIREMENTS)

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise st ated)

Operating temperature -40°C ≤ TA ≤ +85°C

Param

No. Symbol Characteristic Min. Typ Max. Units Conditions

Clock Parameters

AD50 TAD A/D Clock Period(1) 133 — — ns Tcy = 133 ns, ADxCON3

in default state

AD51 tRC A/D Internal RC Oscillator

Period —250— ns —

Conversion Rate

AD55 tCONV Conversion Time — 14 TAD ns —

AD56 FCNV Throughput Rate — — 500 ksps —

AD57 TSAMP Sample Time — 1 TAD —ns —

Timing Parameters

AD60 tPCS Conversion Start from Sample

Trigger — 1.0 TAD —ns —

AD61 tPSS Sample Start from Setting

Sample (SAMP) bit 0.5 TAD —1.5 TAD ns —

AD62 tCSS Conversion Completion to

Sample Start (ASAM = 1)———ns —

AD63 tDPU Time to Stabilize Analog Stage

from A/D Off to A/D On —20—μs—

Legend: TBD = To Be Determined

Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity

performance, especially at elevated temperatures.

PIC24H

24.0 PACKAGING INFORMATION

24.1 Package Marking Information

64-Lead TQFP (10x10x 1 mm)

XXXXXXXXXX

YYWWNNN

Example

PIC24HJ

256GP706

0510017

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the ful l Micro chip p art num ber can not be ma rked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

100-Lead TQFP (12x 12 x1 mm)

XXXXXXXXXXXX

YYWWNNN

Example

PIC24HJ256

GP710-I/PT

0510017

100-Lead TQFP (14x14x1mm)

XXXXXXXXXXXX

YYWWNNN

100-Lead TQFP (14x14x1mm)

PIC24HJ256

GP710-I/PF

0510017

-I/PT

PIC24H

24.2 Package Details

The following sections give the technical details of the

packages.

64-Lead Plastic Thin-Quad Flatp ack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)

1510515105

Mold Draft An g le Bo tto m 1510515105

Mold Draft Angle Top

0.270.220.17.011.009.007BLead Width 0.230.180.13.009.007.005

Lead Thickness

1616n1Pins per Side

10.1010.009.90.398.394.390D1Molded Package Length 10.1010.009.90.398.394.390E1Molded Package Width 12.2512.0011.75.482.472.463DOverall Length 12.2512.0011.75.482.472.463EOverall Width 73.5073.50

Foot Angle

0.750.600.45.030.024.018LFoot Length 0.250.150.05.010.006.002A1Standoff 1.051.000.95.041.039.037A2Molded Package Thickness 1.201.101.00.047.043.039AOverall Height

0.50.020

Pitch 6464

Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERS

INCHESUnits

Footprint F .039 REF. 1.00 REF.

Pin 1 Corner Chamfer CH .025 .035 .045 0.64 0.89 1.14

REF: Reference Dimension, usually without tolerance, for information purposes only.

Revised 07-22-05

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.

See ASME Y14.5M

Controlling Parameter

JEDEC Equivalent: MS-026

Notes:

DD1

#leads=n1

CH x 45°

Drawing No. C04-085

PIC24H

100-Lead Plastic Thin-Quad Flatpack (PT) 12x12x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)

#leads=n1

D1 D

A1 A2

CH x 45°

1.101.00.043

.039

1.00 REF..039 REF.F

Footprint (Reference)

Units INCHES MILLIMETERS

Dimension Limits MIN NOM MAX MIN NOM MAX

Number of Pins n100 100

Pitch p.016 BSC 0.40 BSC

Overall Height A .047 1.20

Molded Package Thickness A2 .037 .039 .041 0.95 1.00 1.05

Standoff A1 .002 .004 .006 0.05 0.10 0.15

Foot Length L .018 .024 .030 0.45 0.60 0.75

Foot Angle

0° 3.5° 7° 0° 3.5° 7°

Overall Width E .551 BSC 14.00 BSC

Overall Length D .551 BSC 14.00 BSC

Molded Package Width E1 .472 BSC 12.00 BSC

Molded Package Length D1 .472 BSC 12.00 BSC

Pins per Side n1 25 25

Lead Thickness c.004 .006 .008 0.09 0.15 0.20

Lead Width B .005 .007 . 009 0.13 0.18 0.23

Mold Draft Angle Top

5° 10° 15° 5° 10° 15°

Mold Draft Angle Bottom

5° 10° 15° 5° 10° 15°

Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.

Notes:

JEDEC Equivalent: MS-026

Controllin g Parameter

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

See ASME Y14.5M

See ASME Y14.5M Revised 07-22-05

Drawing No. C04-100

PIC24H

100-Lead Plastic Thin-Quad Flatpack (PF) 14x14x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)

#leads=n1

Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.

.630 BSC

NOM

INCHES

.630 BSC

.551 BSC

Overall Width

Overall Length

Foot Angle

Foot Length

Pins per Side

Overall Height

Number of Pins

Lead Width

Revised 07-21-05

Lead Thickness

Molded Package Thickness

Controlling Paramete r

JEDEC Equivalent: MS-026

Mold Draft Angle Bottom

Mold Draft Angle Top

Molded Package Width

Molded Package Length

Footprint

Notes:

Pitch

Standoff

11°

Dimension Limits

11°

.007

.004

.018

0°

MIN

Units

.037

.002

12°11°12° 13°

12°

.009

3.5°

.039 REF

.024

.011

.008

13°

.030

7°

.020 BSC

.039

100

.041

.006

.047

MAX

16.00 BSC

14.00 BSC

0.17

0.09

11°

0.45

0°

0.22

12°

1.00 REF

0.60

3.5°

MILLIMETERS

0.95

0.05

MIN

0.50 BSC

1.00

NOM

100

13°

0.27

0.20

13°

0.75

7°

1.05

0.15

1.20

MAX

REF: Reference Dimension, usually without tolerance, for information purposes only.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

See ASME Y14.5M

Drawing No. C04-110

© 2006 Microchip Technology Inc. Preliminary DS70175D-page 281
PIC24H
APPENDIX A: REVISION HISTORY
Revision A (February 2006)
• Initial release of this document
Revision B (March 2006)
• Updated the Configuration Bits Description table 
(Table 20.1)
• Updated registers and register maps
• Updated Section 15.0 “Serial Peripheral Inter-
face (SPI)”
• Updated Section 23.0 “Elect rical Characteris-
tics”
• Updated pinout diagrams
• Additional minor corrections throughout document 
text
Revision C (May 2006)
• Updated Section 23.0 “Elect rical Characteris-
tics”
• Updated the Configuration Bits Description table 
(Table 20.1)
• Additional minor corrections throughout document 
text
Revision D (July 2006)
• Added FBS and FSS Device Configuration regis-
ters (see Table 20-1) and corresponding bit field 
descriptions (see Table 20-2). These added regis-
ters replaced the former RESERVED1 and 
RESERVED2 registers.
• Added INTTREG Interrupt Control and Status 
register. (See Section 6.3 “Interrupt Control 
and Status Registers”. See also Register 6-33.)
• Added Core Registers BSRAM and SSRAM (see 
Section 3.2.7 “Data Ram Protection Feature”)
• Clarified Fail-Safe Clock Monitor operation (see 
Section 8.3 “Fail-Safe Clock Monitor (FSCM)”) 
• Updated COSC<2:0> and NOSC<2:0> bit config-
urations in OSCCON register (see Register 8-1)
• Updated CLKDIV register bit configurations (see 
Register 8-2)
• Added Word Write Cycle Time parameter (TWW) 
to Program Flash Memory (see Table 23-11)
• Noted exceptions to Absolute Maximum Ratings 
on I/O pin output current (see Section 23.0 
“Electri cal Characteristics”)
• Added ADC2 Event Trigger for Timer4/5 
(Section 12.0 “Timer2/3, Timer4/5, Timer6/7 
and Timer8/9”)
• Corrected mislabeled I2COV bit in I2CxSTAT 
register (see Register 16-2)
• Removed  AD26a, AD27a, AD2 8a, AD26b, AD27 b 
and AD28b from Table 23-34 (A/D Module)
• Revised Table 23-36 (AD63)

PIC24H

NOTES:

© 2006 Microchip Technology Inc. Preliminary DS70175D-page 283
PIC24H
INDEX
A
A/D Converte r.... ............... .............. ................... ...............209
DMA..........................................................................209
Initialization...............................................................209
Key Feat u res........... ................... ............................. ..209
AC Characteristics............................................................250
Internal RC Accuracy................................................252
Load Conditions...................... ..... .... .. .. .. .. .. .. ....... .. .. ..250
ADC Module
ADC1 Register Map....................................................37
ADC2 Register Map....................................................37
Altern a te Vecto r Tab l e  ( AIVT)........................ ................... ..67
Arithm e tic  Logic Unit (ALU).................. .............. ............... ..23
Assembler
MPASM Assembler...................................................240
Automatic Clock Stretc h....................................................163
Receive Mode...........................................................163
Transmit Mode........ ................... ....................... ........16 3
B
Block Diagrams
16-bit Timer1 Module................................................139
A/D Module...................................... .. .... .. .... .....210, 211
Connections for On-Chip Voltage Regulator. ............227
ECAN Module ........... .. .. .... .. .... ....... .. .. .... .. .... ....... .. .. ..180
Input Capture................................. .. .. .... .. .... ....... .. .. ..147
Output Co mpa re ............... ................... ................... ..151
PIC24H .......................................................................14
PIC24H CPU Core......................................................18
PIC24H Oscillator System Diagram..........................127
PIC24H PLL..............................................................129
Reset System..... .............................. ................... ........61
Shared Po rt Structure.................... ...........................13 7
SPI............................................................................154
Timer2 (16-bit) ..........................................................143
Timer2 /3  (32-bi t) ........... ....................... ................... ..142
UART........................................................................171
Watchdog Timer (WDT)............................................228
C
C Compilers
MPLAB C18.................... ....................... ...................240
MPLAB C30.................... ....................... ...................240
Clock Switching.................................................................134
Enabling....................................................................134
Sequence..................................................................134
Code Examples
DMA Sample Initialization Method............................117
Erasing a Program Memory Page...............................58
Initiating a Programming Sequence............................59
Loading Write Buffers .......................... .. .... .. ..... .. .... .. ..59
Port Write/Read ........................................................138
PWRSAV Instruction Synta x........................ .............13 5
Code Protection ........................................................223, 229
Configuration Bits..............................................................223
Description (Table)....................................................224
Configuration Register Map..............................................223
Configuring Analog Port Pins............................................138
CPUControl Register........ ......................... ............... ..........20
CPU Clocking System.......................................................128
PLL Configuration.....................................................128
Selection...................................................................128
Sources.....................................................................128
Customer Change Notification Service.............................287
Customer Support............................................ ........... .... ..287
D
Data Addre ss Space............. .............................. ................ 27
Alignment.................................................................... 27
Memory Map for PIC24H Devices with 16 KBs RAM. 29
Memory Map for PIC24H Devices with 8 KBs RAM... 28
Near Data Space........................................................ 27
Softwar e  Stack .................... ........................... ............ 48
Width .......................................................................... 27
DC Characteristics............................................................ 244
I/O Pin Input Specifications .......................... .. .... .. .... 248
I/O Pin Outpu t Specification s......... ........... ................ 249
Idle Current (IDOZE) .................................................. 247
Idle Current (IIDLE).................................................... 246
Operating Current (IDD) ............................................ 245
Power-Down Current (IPD)........................................ 246
Program Memory...................................................... 249
Temperature and Voltage Specifications .................. 244
Development Support....................................................... 239
DMAInterrupts and Traps ................................................. 116
Request Source Selection........................................ 116
DMA Module
DMA Register Map.............. ............................. .......... 38
DMAC Operating Modes................................................... 114
Addressing................................................................ 115
Byte or Word Transfe r.... ........................ .................. 115
Contin u ous  o r One -Shot............ ................... ............ 116
Manual Transfer ....................................................... 116
Null Data Peripheral Write.......................... .. .... .. .. .. .. 115
Ping-Pong................................................................. 116
Transfe r Direction..... ............... ................... .............. 115
DMAC Registers............................................................... 114
DMAxCNT ................................................................ 114
DMAxCON................................................................ 114
DMAxPAD ................................................................ 114
DMAxREQ................................................................ 114
DMAxSTA................................................................. 114
DMAxSTB................................................................. 114
E
ECAN Module
Baud Rate Setting .................................................... 184
ECAN1 Register Map (C1CTRL1.WIN = 0 or 1)......... 39
ECAN1 Register Map (C1CTRL1.WIN = 0)................ 40
ECAN1 Register Map (C1CTRL1.WIN = 1)................ 40
ECAN2 Register Map (C2CTRL1.WIN = 0 or 1)......... 42
ECAN2 Register Map (C2CTRL1.WIN = 0)................ 42
ECAN2 Register Map (C2CTRL1.WIN = 1)................ 43
Frame Types ............................................................ 179
Message Reception.................................................. 181
Message Transmission............................................. 183
Modes of Ope ration.... ................... ............... ............ 181
Overview................................................................... 179
Electrical Characteristics.................................................. 243
AC............................................................................. 250
Enhanced CAN Module................. .. .... .. .. .... ....... .. .. .... .. .... 179
Equations
A/D Conver sion Clock Perio d........ ............... ............ 212
Calculating the PWM Period...... ................... ............ 150
Calculation for Maximu m PWM Resolu tion.. ...... ...... 150
Device Operating Frequency.................................... 128
FOSC Calcul a tion... ............................. ................... .. 128
Relationship Between Device and 
SPI Clock Speed.............................................. 156
Serial Clock Rate...................................................... 161

PIC24H
DS70175D-page 284 Preliminary © 2006 Microchip Technology Inc.
Time Quantum for Clock Generation . .... .... .. .... .... .....185
UART Baud Rate with BRGH = 0 .............................172
UART Baud Rate with BRGH = 1 .............................172
XT with PLL Mode Example......................................129
Errata ..................................................................................11
F
Flash Pr o g ram Memory..................... ..................................55
Control Reg i sters................ ............... .........................56
Operations ..................................................................56
Programming Al g o rithm................ ....................... .......58
RTSP Operation..........................................................56
Table Instructions........................................................55
Flexible Configuration .......................................................223
FSCM
Delay for Crystal and PLL Clock Sources. ..................65
Device Resets.............................................................65
I
I/O Ports............. ....................... ....................... .................137
Paral l e l  I/O (PIO)................. ............................. .........137
Write/Read Timing....................................................138
I2CAddresses.................................................................163
Baud Rate Generator................................................161
General Call Address Support ..................................163
Interrupts...................................................................161
IPMI Support.............................................. ...... .........163
Master Mode Operation
Clock Arbitration................................................164
Multi-Master Communication, Bus  
Collision and Bus Arbitration.....................164
Operating Modes ......................................................161
Registers...................................................................161
Slave Address Masking ............................................163
Slope Control ............................................................164
Software Controlled Clock Stretching (STREN = 1). .163
I2C Module
I2C1 Regis te r Map..... ................... ................... ...........35
I2C2 Regis te r Map..... ................... ................... ...........35
In-Circuit Debugger...........................................................229
In-Circuit Emulation...........................................................223
In-Circuit Serial Programming (ICSP) .......................223, 229
Infrared Support
Built-in IrDA Encoder and Decoder...........................173
External IrDA, IrDA Clock Output ..............................173
Input Capture
Registers...................................................................148
Input Change Notification Module..... .... .. ....... .. .. .... .. .. .......138
Instruction Addressing Modes.............................................48
File Register Instructions ............................................48
Fundamental Modes Supported..................................49
MCU Inst ruction s .............. ............................. .............48
Move and Accumulator Instructions.. ..........................49
Other Instructions........................................................49
Instruction Set
Overview...................................................................234
Summary...................................................................231
Instruction-Based Power-Saving Modes...........................135
Idle............................................................................136
Sleep.........................................................................135
Internal RC Oscillator
Use with WDT...........................................................228
Inter n e t Ad d ress........... .................................. ...................287
Interrupt Control and Status Registers..................... .... .......71
IECx............................................................................71
IFSx ............................................................................ 71
INTCON1.................................................................... 71
INTCON2.................................................................... 71
INTTREG.................................................................... 71
IPCx............................................................................ 71
Interrupt Setup Procedures............................................... 111
Initialization............................................................... 111
Interrupt Disable.......................................................111
Interrupt Service Routine.......................................... 111
Trap Ser vice Routine.......... ............... ............... ........ 111
Interrupt Vector Table (IVT)................................................ 67
Interrupts Coincident with Power Save Instructions ......... 136
J
JTAG Boundary Scan Interf ace........................................ 223
M
Memory Organization ......................................................... 25
Microc h i p  In te rnet Web Site......................... ................... ..287
Modes of Operation
Disable...................................................................... 181
Initialization............................................................... 181
Listen All Messages........................... .... .. .... ....... .... .. 181
Listen On ly............ .............. ......................... ............. 1 8 1
Loopback.................................................................. 181
Normal Operation....... .......... ................... ............... .. 1 8 1
MPLAB ASM30 Assembler, Linker, Librarian................... 240
MPLAB ICD 2 In-Circuit Debugger................................... 241
MPLAB ICE 2000 High-Perf orm ance Univers a l 
In-Circuit Emulator.................................................... 241
MPLAB ICE 4000 High-Perf orm ance Univers a l 
In-Circuit Emulator.................................................... 241
MPLAB Integrated Development Environment Software.. 239
MPLAB PM3 Device Programmer....................................241
MPLINK Object Linker/MPLIB Object Librarian................ 240
Multi-Bit Data Shifter........................................................... 23
N
NVM Module
Register Map .............. ................... ................... .......... 47
O
Open-Drain Configuration................................................. 138
Output Com p a re................... ................... ......................... 14 9
Registers .................................................................. 152
P
Packaging......................................................................... 277
Details....................................................................... 278
Marking..................................................................... 277
Peripheral Module Disable (PMD) ............. .... .. .... ....... .... ..136
PICSTART Plus Deve lopment Program mer..................... 242
Pinout I/O Descriptions (table)............................................ 15
PMD Module
Register Map .............. ................... ................... .......... 47
POR and Long Oscillator Start-up Times ................... .... .. .. 65
PORTA
Register Map .............. ................... ................... .......... 45
PORTB
Register Map .............. ................... ................... .......... 45
PORTC
Register Map .............. ................... ................... .......... 45
PORTD
Register Map .............. ................... ................... .......... 45
PORTE
Register Map .............. ................... ................... .......... 46

© 2006 Microchip Technology Inc. Preliminary DS70175D-page 285
PIC24H
PORTF
Register Map............... ............................. ...................46
PORTG
Register Map............... ............................. ...................46
Power-Saving Features ....................................................135
Clock Frequency and Switching ................................135
Program Address Space.....................................................25
Construction................................................................50
Data Access from Program Memory 
Using Program Space Visibility...........................53
Data Access from Program Memory Using 
Table Instructions ...............................................52
Data Acces s fr o m, Address Gen era tion.......... .......... ..51
Memory Map...............................................................25
Table Read Instructions
TBLRDH .............................................................52
TBLRDL..............................................................52
Visibility Operation......................................................53
Program Mem ory
Inter rupt Vec to r....... ....................................................26
Organization................................................................26
Reset Vec to r................. ....................... ................... ....26
Pulse-Width Modulation Mode............................. ....... .. .. ..150
PWMDut y Cycl e.. ........... .............. ......................... .............150
Period........................................................................150
R
Reader Response.............................................................288
Registers
ADxCHS0 (ADCx Input Channel 0 Select.................219
ADxCHS123 (ADCx Input Channel 1, 2, 3 Select) ...218
ADxCON1 (ADCx Contro l 1 )............ ............... ..........213
ADxCON2 (ADCx Contro l 2 )............ ............... ..........215
ADxCON3 (ADCx Contro l 3 )............ ............... ..........216
ADxCON4 (ADCx Contro l 4 )............ ............... ..........217
ADxCSSH (ADCx Input Scan Select High)...............220
ADxCSSL (ADCx Input Scan Select Low)................220
ADxPCFGH (ADCx Port Configuration High) ....... .. ..221
ADxPCFGL (ADCx Port Configuration Low).............221
CiBU F PNT1 (E CAN Fi l te r 0-3 Buf fer Po i n te r).......... .1 9 6
CiBU F PNT2 (E CAN Fi l te r 4-7 Buf fer Po i n te r).......... .1 9 7
CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer).........197
CiBUFPNT4 (ECAN Filter 12-15 Buffer Pointer).......198
CiCFG1 (ECAN Baud Rate Configuration 1)............194
CiCFG2 (ECAN Baud Rate Configuration 2)............195
CiCTRL1 (ECAN Control 1) ....... ...... ..................... ....186
CiCTRL2 (ECAN Control 2) ....... ...... ..................... ....187
CiEC (ECAN Transmit/Receive Error Count )............193
CiFCTRL  (ECAN  FIFO Cont r o l ).............. ...... ..... .......189
CiFEN1 (ECAN Acceptance Filter Enable)...............196
CiFIFO (ECAN FIFO Status).....................................190
CiFMSKSEL1 (ECAN Filter 7-0 Mask Selection)......200
CiINTE (ECAN Interrupt Enable) ..............................192
CiINTF (ECAN Int e rrupt Fla g)................ ............... ....19 1
CiRXFnEID (ECAN Acceptance Filter n 
Extended Identifier)...........................................199
CiRXFnSID (ECAN Acceptance Filter n 
Standard Identifier) ...........................................199
CiRXFUL1 (ECAN Receive Buffer Full 1).................202
CiRXFUL2 (ECAN Receive Buffer Full 2).................202
CiRXMnEID (ECAN Acceptance Filter Mask n 
Extended Identifier)...........................................201
CiRXMnSID (ECAN Acceptance Filter Mask n 
Standard Identifier) ...........................................201
CiRXOVF1 (ECAN Receive Buffer Overflow 1)........203
CiRXOVF2 (ECAN Receive Buffer Overflow 2)........ 203
CiTRBnDLC (ECAN Buffer n Data Length Control) . . 206
CiTRBnEID (ECAN Buffer n Extended Identifier)..... 205
CiTRBnSID (ECAN Buffer n Standard Identifier). ..... 205
CiTRBnSTAT (ECAN Receive Buffe r n Status)........ 207
CiTRmnCON (ECAN TX/RX Buffer m Control)........ 204
CiVEC (ECAN Interrupt Code) ............................. .... 188
CLKDIV (Clock Divisor)....... .............. ............... ........ 131
CORCON (Core Control)...................................... 22, 72
DMACS0 (DMA Contro ller Status 0) ........................ 122
DMACS1 (DMA Contro ller Status 1) ........................ 124
DMAxCNT (DMA Channel x Transfer Count)........... 121
DMAxCON (DMA Channel x Control)....................... 118
DMAxPAD (DMA Channel x Peripheral Address).... 121
DMAxREQ (DMA Channel x IRQ Select)............... .. 119
DMAxSTA (DMA Channel x RAM Start Address A). 120
DMAxSTB (DMA Channel x RAM Start Address B). 120
DSA D R  (M o st Rece n t DMA R AM Add r e ss) ............ . 1 2 5
I2CxCON (I2C x Con tr o l)................ ........... ................ 165
I2CxMSK (I2 Cx Slave Mode Addr ess Mask)............ 169
I2CxSTAT (I2Cx Status)........................................... 167
ICxCON (Input Capture x Control)............................ 148
IEC0 (Interrupt Enable Control 0)..................... .. .... .... 84
IEC1 (Interrupt Enable Control 1)..................... .. .... .... 86
IEC2 (Interrupt Enable Control 2)..................... .. .... .... 88
IEC3 (Interrupt Enable Control 3)..................... .. .... .... 90
IEC4 (Interrupt Enable Control 4)..................... .. .... .... 91
IFS0 (I n terrup t Flag Sta tu s 0).......... ..................... ...... 76
IFS1 (I n terrup t Flag Sta tu s 1).......... ..................... ...... 78
IFS2 (I n terrup t Flag Sta tu s 2).......... ..................... ...... 80
IFS3 (I n terrup t Flag Sta tu s 3).......... ..................... ...... 82
IFS4 (I n terrup t Flag Sta tu s 4).......... ..................... ...... 83
INTCON1 (Interrupt Control 1) ................................... 73
INTCON2 (Interrupt Control 2) ................................... 75
IPC0 (Inte r rupt Priority Control 0)........... .............. ...... 92
IPC1 (Inte r rupt Priority Control 1)........... .............. ...... 93
IPC10 (In terrupt Pr io rity Control 10)................. ........ 102
IPC11 (In terrupt Pr io rity Control 11)................. ........ 103
IPC12 (In terrupt Pr io rity Control 12)................. ........ 104
IPC13 (In terrupt Pr io rity Control 13)................. ........ 105
IPC14 (In terrupt Pr io rity Control 14)................. ........ 106
IPC15 (In terrupt Pr io rity Control 15)................. ........ 107
IPC16 (Interrupt Priority Control 16)................. 108, 110
IPC17 (In terrupt Pr io rity Control 17)................. ........ 109
IPC2 (Inte r rupt Priority Control 2)........... .............. ...... 94
IPC3 (Inte r rupt Priority Control 3)........... .............. ...... 95
IPC4 (Inte r rupt Priority Control 4)........... .............. ...... 96
IPC5 (Inte r rupt Priority Control 5)........... .............. ...... 97
IPC6 (Inte r rupt Priority Control 6)........... .............. ...... 98
IPC7 (Inte r rupt Priority Control 7)........... .............. ...... 99
IPC8 (Interrupt Pr io rity Contr o l 8)............. .............. .. 100
IPC9 (Interrupt Pr io rity Contr o l 9)............. .............. .. 101
NVMCON (Flash Memor y Con tr o l)............. .......... ...... 57
OCxCON (Output Compare x Control)..................... 152
OSCCON (Oscillator Control)................................... 130
OSCTUN (FRC Oscillator Tuning)............................ 133
PLLFBD (PLL Feedback Divisor) ............................. 132
RCON (Reset Control) ................................................ 62
SPIxCON1 (SPIx Control 1) ..................................... 158
SPIxCON2 (SPIx Control 2) ..................................... 159
SPIxSTAT (SPIx Status and Control)....................... 157
SR (CPU Status) .................................................. 20, 72
T1CON (Timer1 Con tr o l)..... .............. ............... ........ 140
TxCON (T2CON, T4CON, T6CON or 
T8CON Control).... ........... ..................... ............ 144

PIC24H
DS70175D-page 286 Preliminary © 2006 Microchip Technology Inc.
TyCON (T3CON, T5CON, T7CON or 
T9CON Control)............ ............... .....................145
UxMODE (UARTx  Mode)..........................................174
UxSTA (UARTx Status and Control).............. .. .... .....176
Reset
Clock Source Selection...............................................64
Special Function Register Reset States .....................65
Times ..........................................................................64
Reset Sequence.............................. .. .... ....... .... .... .. .... .........67
Resets.................................................................................61
S
Serial Peripheral Interface (SPI) .......................................153
Setup for Continuous Output Pulse Generation................149
Setup for Single Output Pulse Generation........................149
Softwa re Simulato r (MP L AB SIM)....... ................... ...........240
Software Stack Pointer, Frame Pointer
CALL Stack Frame......................................................48
Special Features...............................................................223
SPI Master, Frame Master Connection ...........................155
Master/Slave Connection....................... .. .... .. .. .... .....155
Slave, Frame Master Connection .............................156
Slave, Frame Slave Connection ........................ .. .....156
SPI Module
Operating Function Description ................................153
SPI1 Register Map......................................................36
SPI2 Register Map......................................................36
Symbols Used in Opcode Descriptions.............................232
System Control
Register Map....................... ................... ................... ..47
T
Temperature and Voltage Specifications
AC.............................................................................250
Timer1...............................................................................139
Timer2/3, Timer4/5, Timer6/7 and Timer8/9 .....................141
Timing Characteristics
CLKO and I/O ...........................................................253
Timing Diagrams
10-bit A/D Conversion (CHPS = 01, SIMSAM = 0, 
ASAM = 0, SSRC = 000) ..................................272
10-bit A/D Conversion (CHPS = 01, SIMSAM =
0, ASAM = 1, SSRC = 111, SAMC  =
00001)...........................................................273
12-bit A/D Conversion (ASAM = 0, SSRC = 000).....275
CAN I/O.....................................................................269
ECAN Bit....................... ............................. ...............184
External Clock...........................................................251
I2Cx Bus Data (Master Mode) ..................................265
I2Cx Bus Data (Slave Mode) . ...................................267
I2Cx Bus Start/Stop Bits (Master Mode)...................265
I2Cx Bus Start/Stop Bits (Slave Mode).....................267
Input Capture (CAPx)............................... .. .... .. .... .....258
OC/PWM...................................................................259
Output Co mpa r e  (OCx )..... ..................... ...................258
Reset, Watchdog Timer, Oscillator Start-up 
Timer and Power-up Timer...............................254
SPIx Master Mode (CKE = 0)....................................259
SPIx Master Mode (CKE = 1)....................................260
SPIx Slave Mode (CKE = 0)......................................261
SPIx Slave Mode (CKE = 1)......................................263
Timer1 , 2 , 3 , 4 , 5 , 6,  7,  8,  9 Exte r n a l  Clo ck...... .........256
Timing Requirements
CLKO and I/O ...........................................................253
External Clock...........................................................251
Input Capture............................................................ 258
Timing Specifications
10-bit A/D Conversion Requirements....................... 274
12-bit A/D Conversion Requirements....................... 276
CAN I/O Requirements........................ .... .... ......... .... 269
I2Cx Bus Data Requirements (Master Mode)........... 266
I2Cx Bus Data Requirements (Slave Mode)............. 268
Output Compare Requirements............. .... .. ....... .... .. 258
PLL Clock ................................................................. 252
Reset, Watchdog Timer, Oscillator Start-up 
Timer, Power-up Timer and Brown-out 
Reset Requirements.............. .. .... .. .... .. ....... .... .. 255
Simple OC/PWM Mode Requirements..................... 259
SPIx Master Mode (CKE = 0) Requirements............ 260
SPIx Master Mode (CKE = 1) Requirements............ 261
SPIx Slave Mode (CKE = 0) Requirements.............. 262
SPIx Slave Mode (CKE = 1) Requirements.............. 264
Timer1 External Clock Requirements....................... 256
Timer2, Timer4, Timer6 and Timer8 External 
Clock Requirements......................................... 257
Timer3, Timer5, Timer7 and Timer9 External 
Clock Requirements......................................... 257
U
UART
Baud Rate
Generator (BRG) ...... .. .... ....... .... .. .... .. ......... .. .... 172
Break and Sync Transmit Sequence........................ 173
Flow Control Using UxCTS and UxRTS Pins........... 173
Receiving  in 8-bit or 9-bit Data  Mode................. ...... 173
Transmitting in 8-bit Data Mode................................ 173
Transmitting in 9-bit Data Mode................................ 173
UART Module
UART1 Register Map.................................................. 35
UART2 Register Map.................................................. 36
V
Voltage Regulator (On-Chip)............................................ 227
W
Watchdog Timer (WDT)................................... .. ....... 223, 228
Program ming  Co n side r a tions...................... ............. 228
WWW Addres s ............... ....................... ....................... .... 287
WWW, On-Line Support..................................................... 11

PIC24H

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PIC24H

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DS70175DPIC24H

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PIC24H

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Architecture: 24 = 16-bit Microcontroller

Flash Memory Family: HJ = Flash program memory, 3.3V, High-speed

Product Group: GP2 = General purpose family

GP3 = Genera l pur po se family

GP5 = Genera l pur po se family

GP6 = Genera l pur po se family

Pin Count: 06 = 64-pin

10 = 100-pin

Temperatu re R ang e: I = -40°C to +85°C (Industrial)

Packa ge: PT = 10x 10 or 12x 12 mmTQF P (Thin Qu ad Flat pack)

PF = 14x14 mmTQFP (Thin Quad Flatpack)

Pattern: Three-digit QTP, SQTP, Code or Special Requirements

(blank otherwise)

ES = Engineer ing Sample

Examples:

a) PIC24HJ256GP210I/PT:

General-purpose PIC24H, 256 KB program

memory, 100-pin, Industrial temp.,

TQFP package.

b) PIC24HJ64GP506I/PT-ES:

General-purpose PIC24H, 64 KB program

memory, 64-pin, Industrial temp.,

TQFP package, Engineering Sample.

Microchip Trademark

Architecture

Flash Memory Family

Program Memory Size (KB)

Produc t Group

Pin Count

Temperature Range

Package

Pattern

PIC 24 HJ 256 GP6 10 T I / PT - XXX

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www.microchip.com

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Habour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

Atlanta

Alpharetta, GA

Tel: 770-640-0034

Fax: 770-640-0307

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Chicago

Itasc a , IL

Tel: 630-285-0071

Fax: 630-285-0075

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

Los A n ge les

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

San Jose

Mountain View, CA

Tel: 650-215-1444

Fax: 650-961-0286

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

ASIA/PACIFIC

Australia - Sydney

Tel: 61-2-9868-67 33

Fax: 61-2-9868-6755

China - Beijing

Tel: 86-10-8528-2 100

Fax: 86-10-8528-2104

China - Chengdu

Tel: 86-28-8676-6 200

Fax: 86-28-8676-6599

China - Fuzhou

Tel: 86-591-8750-3506

Fax: 86-591-8750-3521

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

China - Shanghai

Tel: 86-21-5407-5 533

Fax: 86-21-5407-5066

China - Shenyang

Tel: 86-24-2334-2 829

Fax: 86-24-2334-2393

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

China - Shunde

Tel: 86-757-2839-5507

Fax: 86-757-2839-5571

China - Wuhan

Tel: 86-27-5980-5 300

Fax: 86-27-5980-5118

China - Xian

Tel: 86-29-8833-7 250

Fax: 86-29-8833-7256

ASIA/PACIFIC

India - Bangalore

Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

India - New Delhi

Tel: 91-11-5160-8631

Fax: 91-11-5160-8632

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

Korea - Gumi

Tel: 82-54-473-4301

Fax: 82-54-473-4302

Korea - Seoul

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Malaysia - Penang

Tel: 60-4-646-8870

Fax: 60-4-646-5086

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

Taiwan - Kaohsi ung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Thail a nd - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

EUROPE

Austria - Wels

Tel: 43-7242-2244-3910

Fax: 43-7242-2244-393

Denmark - Copenhage n

Tel: 45-4450-2828

Fax: 45-4485-2829

France - Paris

Tel: 33-1-69-53 -63-20

Fax: 33-1-69-30-90-79

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-14 4-44

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Sp ain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08 -91

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

WORLDWIDE SALES AND SERVICE

06/08/06