© 2006 Microchip Technology Inc. Preliminary DS70175D-page 285
PIC24H
PORTF
Register Map............... ............................. ...................46
PORTG
Register Map............... ............................. ...................46
Power-Saving Features ....................................................135
Clock Frequency and Switching ................................135
Program Address Space.....................................................25
Construction................................................................50
Data Access from Program Memory
Using Program Space Visibility...........................53
Data Access from Program Memory Using
Table Instructions ...............................................52
Data Acces s fr o m, Address Gen era tion.......... .......... ..51
Memory Map...............................................................25
Table Read Instructions
TBLRDH .............................................................52
TBLRDL..............................................................52
Visibility Operation......................................................53
Program Mem ory
Inter rupt Vec to r....... ....................................................26
Organization................................................................26
Reset Vec to r................. ....................... ................... ....26
Pulse-Width Modulation Mode............................. ....... .. .. ..150
PWMDut y Cycl e.. ........... .............. ......................... .............150
Period........................................................................150
R
Reader Response.............................................................288
Registers
ADxCHS0 (ADCx Input Channel 0 Select.................219
ADxCHS123 (ADCx Input Channel 1, 2, 3 Select) ...218
ADxCON1 (ADCx Contro l 1 )............ ............... ..........213
ADxCON2 (ADCx Contro l 2 )............ ............... ..........215
ADxCON3 (ADCx Contro l 3 )............ ............... ..........216
ADxCON4 (ADCx Contro l 4 )............ ............... ..........217
ADxCSSH (ADCx Input Scan Select High)...............220
ADxCSSL (ADCx Input Scan Select Low)................220
ADxPCFGH (ADCx Port Configuration High) ....... .. ..221
ADxPCFGL (ADCx Port Configuration Low).............221
CiBU F PNT1 (E CAN Fi l te r 0-3 Buf fer Po i n te r).......... .1 9 6
CiBU F PNT2 (E CAN Fi l te r 4-7 Buf fer Po i n te r).......... .1 9 7
CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer).........197
CiBUFPNT4 (ECAN Filter 12-15 Buffer Pointer).......198
CiCFG1 (ECAN Baud Rate Configuration 1)............194
CiCFG2 (ECAN Baud Rate Configuration 2)............195
CiCTRL1 (ECAN Control 1) ....... ...... ..................... ....186
CiCTRL2 (ECAN Control 2) ....... ...... ..................... ....187
CiEC (ECAN Transmit/Receive Error Count )............193
CiFCTRL (ECAN FIFO Cont r o l ).............. ...... ..... .......189
CiFEN1 (ECAN Acceptance Filter Enable)...............196
CiFIFO (ECAN FIFO Status).....................................190
CiFMSKSEL1 (ECAN Filter 7-0 Mask Selection)......200
CiINTE (ECAN Interrupt Enable) ..............................192
CiINTF (ECAN Int e rrupt Fla g)................ ............... ....19 1
CiRXFnEID (ECAN Acceptance Filter n
Extended Identifier)...........................................199
CiRXFnSID (ECAN Acceptance Filter n
Standard Identifier) ...........................................199
CiRXFUL1 (ECAN Receive Buffer Full 1).................202
CiRXFUL2 (ECAN Receive Buffer Full 2).................202
CiRXMnEID (ECAN Acceptance Filter Mask n
Extended Identifier)...........................................201
CiRXMnSID (ECAN Acceptance Filter Mask n
Standard Identifier) ...........................................201
CiRXOVF1 (ECAN Receive Buffer Overflow 1)........203
CiRXOVF2 (ECAN Receive Buffer Overflow 2)........ 203
CiTRBnDLC (ECAN Buffer n Data Length Control) . . 206
CiTRBnEID (ECAN Buffer n Extended Identifier)..... 205
CiTRBnSID (ECAN Buffer n Standard Identifier). ..... 205
CiTRBnSTAT (ECAN Receive Buffe r n Status)........ 207
CiTRmnCON (ECAN TX/RX Buffer m Control)........ 204
CiVEC (ECAN Interrupt Code) ............................. .... 188
CLKDIV (Clock Divisor)....... .............. ............... ........ 131
CORCON (Core Control)...................................... 22, 72
DMACS0 (DMA Contro ller Status 0) ........................ 122
DMACS1 (DMA Contro ller Status 1) ........................ 124
DMAxCNT (DMA Channel x Transfer Count)........... 121
DMAxCON (DMA Channel x Control)....................... 118
DMAxPAD (DMA Channel x Peripheral Address).... 121
DMAxREQ (DMA Channel x IRQ Select)............... .. 119
DMAxSTA (DMA Channel x RAM Start Address A). 120
DMAxSTB (DMA Channel x RAM Start Address B). 120
DSA D R (M o st Rece n t DMA R AM Add r e ss) ............ . 1 2 5
I2CxCON (I2C x Con tr o l)................ ........... ................ 165
I2CxMSK (I2 Cx Slave Mode Addr ess Mask)............ 169
I2CxSTAT (I2Cx Status)........................................... 167
ICxCON (Input Capture x Control)............................ 148
IEC0 (Interrupt Enable Control 0)..................... .. .... .... 84
IEC1 (Interrupt Enable Control 1)..................... .. .... .... 86
IEC2 (Interrupt Enable Control 2)..................... .. .... .... 88
IEC3 (Interrupt Enable Control 3)..................... .. .... .... 90
IEC4 (Interrupt Enable Control 4)..................... .. .... .... 91
IFS0 (I n terrup t Flag Sta tu s 0).......... ..................... ...... 76
IFS1 (I n terrup t Flag Sta tu s 1).......... ..................... ...... 78
IFS2 (I n terrup t Flag Sta tu s 2).......... ..................... ...... 80
IFS3 (I n terrup t Flag Sta tu s 3).......... ..................... ...... 82
IFS4 (I n terrup t Flag Sta tu s 4).......... ..................... ...... 83
INTCON1 (Interrupt Control 1) ................................... 73
INTCON2 (Interrupt Control 2) ................................... 75
IPC0 (Inte r rupt Priority Control 0)........... .............. ...... 92
IPC1 (Inte r rupt Priority Control 1)........... .............. ...... 93
IPC10 (In terrupt Pr io rity Control 10)................. ........ 102
IPC11 (In terrupt Pr io rity Control 11)................. ........ 103
IPC12 (In terrupt Pr io rity Control 12)................. ........ 104
IPC13 (In terrupt Pr io rity Control 13)................. ........ 105
IPC14 (In terrupt Pr io rity Control 14)................. ........ 106
IPC15 (In terrupt Pr io rity Control 15)................. ........ 107
IPC16 (Interrupt Priority Control 16)................. 108, 110
IPC17 (In terrupt Pr io rity Control 17)................. ........ 109
IPC2 (Inte r rupt Priority Control 2)........... .............. ...... 94
IPC3 (Inte r rupt Priority Control 3)........... .............. ...... 95
IPC4 (Inte r rupt Priority Control 4)........... .............. ...... 96
IPC5 (Inte r rupt Priority Control 5)........... .............. ...... 97
IPC6 (Inte r rupt Priority Control 6)........... .............. ...... 98
IPC7 (Inte r rupt Priority Control 7)........... .............. ...... 99
IPC8 (Interrupt Pr io rity Contr o l 8)............. .............. .. 100
IPC9 (Interrupt Pr io rity Contr o l 9)............. .............. .. 101
NVMCON (Flash Memor y Con tr o l)............. .......... ...... 57
OCxCON (Output Compare x Control)..................... 152
OSCCON (Oscillator Control)................................... 130
OSCTUN (FRC Oscillator Tuning)............................ 133
PLLFBD (PLL Feedback Divisor) ............................. 132
RCON (Reset Control) ................................................ 62
SPIxCON1 (SPIx Control 1) ..................................... 158
SPIxCON2 (SPIx Control 2) ..................................... 159
SPIxSTAT (SPIx Status and Control)....................... 157
SR (CPU Status) .................................................. 20, 72
T1CON (Timer1 Con tr o l)..... .............. ............... ........ 140
TxCON (T2CON, T4CON, T6CON or
T8CON Control).... ........... ..................... ............ 144