32-Macro ce ll MAX® EPLD
fax id: 6101
CY7C344
CY7C344B
Cypress Semiconductor Corporation • 3901 North First Street • San Jo se • CA 95134 • 408-943-2600
January 1990 – Revised October 1995
1CY7C344B
Features
• High-performance, high-density replacement for TTL,
74HC, and custom logic
• 32 macrocells, 64 expander product terms in one LAB
• 8 dedicated inputs, 16 I/O pins
• 0.8-micron double- metal CMOS EPROM tec hnology
(CY7C344)
• Advanced 0.65-micron CMOS EPROM technology to
increase perform ance (CY7C344B)
• 28-pin 300-mil DIP, cerDIP or 28-pin HLCC, PLCC
package
Functional Description
Available in a 28-pin 300-mil DIP or windowed J-leaded ce-
ramic chip carrier (HLCC), the CY7C344/CY7C344B repre-
sents the densest EPLD of this size. Eight dedicated inputs
and 16 bidire ctional I/O pin s communicate to one logic ar ray
block. In the CY7C344 LAB there are 32 macrocells and 64
expander product terms. When an I/O macroce ll is us ed as an
input, two expanders are used to create an input path. Even if
all of the I/O pins are dr iv en by macrocell registers, ther e are
still 16 “buried” registers available. All inputs, macro cells, and
I/O pin s are interconnected within the LAB.
The speed and density of the CY 7C344/CY7C344B makes it
a na tural for all types o f applications. With ju st th is one device ,
the designer can implement complex state machines, regis-
tered logic, and combinator ial “glue” l o gic, without using mul-
tiple chips. This architectural flexibility allows the
CY7C344/CY7C344B to replace multichip TTL solutions,
whether th ey are synchronous, as ynchronous, combinator ial,
or all three.
Selectio n G uide
7C344B–10 7C344B–12 7C344–15
7C344B–15 7C344–20
7C344B–20 7C344–25
7C344B–25
Maximum Access Time (ns) 10 12 15 20 25
Maximum
Operating
Cur rent (mA)
Commercial 200 200 200 200 200
Military 220 220 220
Industrial 220 220 220 220
Maximum Standby
Cur rent (mA) Commercial 150 150 150 150 150
Military 170 170 170
Industrial 170 170 170 170
Shaded area contains preliminary information.
Note:
1. Numbers in () refer to J-leaded packages.
C344–1
Logic Block Diagram
MACROCELL 2
MACROCELL 4
MACROCELL 6
MACROCELL 8
MACROCELL 10
MACROCELL 12
MACROCELL 14
MACROCELL 16
MACROCELL 18
MACROCELL 20
MACROCELL 22
MACROCELL 24
MACROCELL 26
MACROCELL 28
MACROCELL 30
MACROCELL 32
MACROCELL 1
MACROCELL 3
MACROCELL 5
MACROCELL 7
MACROCELL 9
MACROCELL 11
MACROCELL 13
MACROCELL 15
MACROCELL 17
MACROCELL 19
MACROCELL 21
MACROCELL 23
MACROCELL 25
MACROCELL 27
MACROCELL 29
MACROCELL 31
G
L
O
B
A
L
B
U
S
I
O
C
O
N
T
R
O
L
INPUT
INPUT
INPUT
INPUT
15(22)
15(23)
27(6)
28(7)
INPUT 1(8)
INPUT/CLK 2(9)
INPUT 13(20)
INPUT 14(21)
I/O 3(10)
I/O 4(11)
I/O 5(12)
I/O 6(13)
I/O 9(16)
I/O 10(17)
I/O 11(18)
I/O 12(19)
I/O 17(24)
I/O 18(25)
I/O 19(26)
I/O 20(27)
I/O 23(2)
I/O 24(3)
I/O 25(4)
I/O 26(5)
64 EXPANDER PRODUCT TERM ARRAY 32
Pin Configurations
T op Vie w
HLCC
25
24
23
22
21
20
19
5
6
7
8
9
10
11 12 13 141516 1718
432 28 2726
I/O
I/O
INPUT
INPUT
INPUT
I/O
I/O
INPUT
INPUT
INPUT/CLK
I/O
I/O
1
INPUT
C344–2
INPUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
INPUT
INPUT T op Vie w
CerDIP
INPUT/CLK
I/O
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
INPUT
INPUT
INPUT
I/O
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
INPUT
INPUT C344–3
[1]
CY7C344
CY7C344B
2
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied ................ ................. ..................0°C to +70°C
Maximum Junction Temperat ure (U n der Bias) . ............150°C
Supply Volta ge to Gro und Pote ntial.......... ..... –2.0V to +7.0V
Maximum Power Dissipation...................................1500 mW
DC VCC or GND Current....... ............ .......... ............ ...500 mA
Static Discharg e Volt a ge
(per MIL-S TD-883, Meth od 3015)... ...........................>2001V
DC Output Current, per Pin................. .....–25 mA to +25 mA
DC Input Voltage[2] ......... ..................... ... ........–3. 0V to +7.0V
DC Program Volta ge .................. ................................+13.0V
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C 5V ±5%
Industrial –40°C to +85°C5V ±10%
Military –55°C to +125°C (Case) 5V ±10%
Electrical Characteristics Over the Operating Range[3]
Parameter Description Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 8 mA 0.45 V
VIH Input HIGH Level 2.2 VCC+0.3 V
VIL Input LOW Level –0.3 0.8 V
IIX Input Current GND ≤ VIN ≤ VCC –10 +10 µA
IOZ Output Leakage Current VO = VCC or G ND –40 +40 µA
IOS Output Short Circuit Current VCC = Max., VOUT = 0.5V[4, 5] –30 –90 mA
ICC1 Power Supply
Current (Standby) VI = VCC or GND ( N o Load) Commercial 150 mA
Military/Industrial 170 mA
ICC2 Power Supply Current VI = VCC or GND ( N o Load)
f = 1.0 MHz[4,6] Commercial 200 mA
Military/Industrial 220 mA
tRRecom mended Input Rise T ime 100 ns
tFRecommended Input Fall Time 100 ns
Capacitance
Parameter Description Test Conditions Max. Unit
CIN Input Capaci tance VIN = 2V, f = 1.0 M H z 10 pF
COUT Output Capacitance VOUT = 2.0V, f = 1.0 MHz 10 pF
AC Test Loads and Waveforms[7]
Notes:
2. Minimum DC input is –0.3V. During transitions, the inputs may undershoot to –2.0V for periods less than 20 ns.
3. Typical values are for TA = 25°C and VCC = 5V.
4. Guaranteed by design but not 100% tested.
5. Not more than one output should be tested at a time. Dur ation of the short c ircuit should not be more than one second. VOUT = 0.5V has been chos en to av oid
tes t probl ems caus ed by te ster ground degr adat ion.
6. Measured with device programmed as a 16-bit counter.
7. Part (a) in AC Test Load and W aveforms is us ed for all parameters except tER and tXZ, which is used for part (b) in AC Test Load and W avefor ms. All external timing
parame ters are meas ured re ferenc ed to ext ernal pins of t he devi ce.
3.0V
5V
OUTPUT
R1 464Ω
R2
250Ω
50 pF
INCLUDING
JIGAND
SCOPE
GND
90%
10%
90%
10%
≤ 6ns ≤ 6ns
5V
OUTPUT
R1 464Ω
R2
250Ω
(a) (b)
OUTPUT 1.75V
Equ ivalent to: THÉVENIN EQUIVA LENT (com merci al/ mi litary)
C344–4 C344–5
ALL INPUT PULSES
tf
5pF
C344–6
tRtF
163Ω
CY7C344
CY7C344B
3
Timing Delays
Timing delays within the CY7C344/CY7C344B may be easily
determined using
Warp2
®,
Warp2
Sim™
,
or
Warp3
® software
or by the model shown in
Figu re 1
. The CY7C344/CY7C344B
has fixed internal delays, allowing the user to determine the
worst case timing delays for any design. For complete timi ng
information, the
Warp3
software provides a timing simulator.
Design Recommendations
Operation of the devices described herein with conditions
above those listed under “Absolute Maximum Ratings” may
c aus e pe rmanen t damage to th e dev ice. This is a st ress rating
only and functional operation of the device at thes e or any other
condi t ions above thos e indica ted in the operat iona l section s of
this datasheet is not implied. Exposure to a bsolute maxi mum
ratings c onditions for e xtended p eriods of time may affect de-
vice reliability. The CY7C344/CY7C344B contains circuitr y t o
protect device pins from high-static voltages or electric fields ;
however, normal precautions should be taken to avoid applying
any voltage higher than maximum rated voltages.
For proper operation, input and output pins must be con-
strained to the range GND ≤ (VIN or VOUT) ≤ VCC. Unused in-
puts must always be tied to an appropriate l ogi c level (either VCC or
GND). Each set of VCC and GND pins must be connected together
directly at the device. Power supply decoupling capacitors of at l east
0.2 µF must be conne cted between VCC and G ND. For th e mos t
effective decoupling, each VCC pin shoul d be separately decoupled.
Timing Considerations
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum ex-
pander delay tEXP to the overall delay.
When calculating synchronous frequencies, use tS1 if all inputs
are on the input pins. tS2 shou ld be used if data is ap plied at an I/O
pin. If t S2 is greater than tCO1, 1/tS2 becomes the limiting frequency
in the data-path mode unless 1/(tWH + tWL) is less than 1/tS2.
When expander logic is used in t he data path, add the appro-
priate maximum expander delay, tEXP to tS1. Determin e which of
1/(tWH + tWL), 1/tCO1, or 1/ (tEXP + tS1) is the lowest f requency. The
lowest of these frequenci es is the maximum data-pat h frequency for
the synchronous configuration.
When calculating external asynchronous frequencies, use
tAS1 if all inputs are on dedicated input pins. If any data is appli ed to
an I/O pin , tAS2 must be used as the required set -up time. If (tAS2 +
tAH) is greater tha n tACO1, 1/(tAS2 + tAH) becomes the limiting fre-
quency i n the dat a-path mode unl ess 1/(tAWH + tAWL) is less th an
1/(tAS2 + tAH).
When expander logic is used in t he data path, add the appro-
priate m axi mum expander delay, t EXP to tAS1. Determine which
of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the lowest frequency .
The lowest of these frequencies is the maximum data-path frequency
for the asynchronous configuration.
The parameter tOH indi cates the system compatibi lity of this device
when driving other synchronous logic with positive input hold times,
which is controlled by the same synchronous cl ock. If tOH is greater
than the m inim um required input hold time o f the subsequent syn-
chronous logic, then the devices are guaranteed to function properly
with a common synchronous clock under worst-case envi ronmental
and supply voltage conditions.
The parameter tAOH indicates the system com patibility of this de-
vice when driving subsequent registered logic with a positive hold
time and using the same clock as the CY7C344/CY7C344B.In gen-
eral , if tAOH is greater than the mi nimum required input hold time of
the subsequent logic (synchronous or asynchronous), then the devic-
es are guaranteed to function properly under worst-case environ-
mental and supply voltage conditions, provided the clock signal
source is the same. This also applies if expander logic is used in the
clock signal p ath of the driving device, but not for the driven device.
This i s due to the expander logic in the second device’ s clock signal
path addi ng an additional delay (tEXP), causing t he output data from
the preceding device to change prior to the arr ival of the clock signal
at the following device’ s register.
Figure 1. CY7C344/CY7C344B Tim ing Model
LOGIC ARRAY
CONTROLDELAY
tLAC
EXPANDER
DELAY
tEXP
CLOCK
DELAY
tIC
tRD
tCOMB
tLATCH
INPUT
DELAY
tIN
REGISTER
OUTPUT
DELAY
tOD
tXZ
tZX
LOGIC ARRAY
DELAY
tLAD
FEEDBACK
DELAY
tFD
OUTPUT
INPUT
C344–7
SYSTEM CLOCK DELAY tICS
tRH
tRSU
tPRE
tCLR
I/O
I/O DELAY
tIO
I/O
CY7C344
CY7C344B
4
External Synchronous Switching Cha racteristics[7] Over Operati ng Range
7C344B–10 7C344B–12 7C344–15
7C344B–15
Parameter Description Min. Max. Min. Max. Min. Max. Unit
tPD1 Dedica ted Input to Combinatorial Output Delay[8] Com’l /Ind 10 12 15 ns
Mil 12 15
tPD2 I/O Input to Combin atorial Output Delay[9] Com’l/Ind 10 12 15 ns
Mil 12 15
tPD3 Dedicat e d Input to Combinatorial Output Delay
with Expander Delay[10] Com’l /Ind 16 18 30 ns
Mil 18 30
tPD4 I/O Input to Combin atorial Output Delay with
Expander Dela y[4, 1 1 ] Com’l/Ind 16 18 30 ns
Mil 18 30
tEA Input to Output Enabl e Delay[4] Com’l/Ind 10 12 20 ns
Mil 12 20
tER Input to Output Disable Delay[4] Com’l /Ind 10 12 20 ns
Mil 12 20
tCO1 Sy nchronous Clock Input to Out put Delay Com’l /Ind 5 610ns
Mil 610
t
CO2 Synchronous Clock to Local Feedback to Com-
binatorial Output[4, 12] Com’l /Ind 10 12 20 ns
Mil 12 20
tSDedicat e d Input or Feedback Set-Up Time to
Synchronous Clock Input Com’l/Ind 6 8 10 ns
Mil 810
tHInput Hold T ime f rom Sy nchronou s Clock Input [7] Com’l /Ind 0 0 0ns
Mil 0 0
tWH Synchronous Clock Input HIGH Time[4] Com’l/Ind 4 4.5 6ns
Mil 4.5 6
tWL Synchronous Clock Input LOW Time[4] Com’l /Ind 4 4.5 6ns
Mil 4.5 6
tRW Asynchronous Clear Width[4] Com’l /Ind 10 12 20 ns
Mil 12 20
tRR Asynchronous Clear Recovery Time[4] Com’l /Ind 10 12 20 ns
Mil 12 20
tRO Asynchronous Clear to Registered Output De-
lay[4] Com’l /Ind 10 12 15 ns
Mil 12 15
tPW Asynchronous Preset Wi dth[4] Com’l /Ind 10 12 20 ns
Mil 12 20
tPR Asynchronous Preset Recovery Time[4] Com’l /Ind 10 12 20 ns
Mil 12 20
tPO Asynchronous Preset to Registered Output
Delay[4] Com’l /Ind 10 12 15 ns
Mil 12 15
tCF Synchronous Clock t o Local Fe edbac k Input[4, 13] Com’l /Ind 3 34ns
Mil 34
t
PExternal Synchronous Clock Period (1/fMAX3)[4] Com’l/Ind 8 9 13 ns
Mil 913
fMAX1 External M aximum Frequency(1/(tCO1 + tS))[4, 14] Com’l/Ind 90.9 71.4 50.0 MHz
Mil 71.4 50.0
Shaded area contains preliminary information.
CY7C344
CY7C344B
5
External Sync hronous Switching Characteristics[7 ] Over Operating Range (continued)
7C344B–10 7C344B–12 7C344–15
7C344B–15
Parameter Description Min. Max. Min. Max. Min. Max. Unit
fMAX2 Maximum Frequency with Internal Only Feed-
back (1/(tCF + tS))[ 4, 15] Com’l/Ind 111.1 90.9 71.4 MHz
Mil 90.9 71.4
fMAX3 Data Pa th Maximum Fre quenc y, least of 1/(tWL
+ tWH), 1/(tS + tH), or (1/t CO1)[4, 1 6] Com’l/Ind 125.0 111.1 83.3 MHz
Mil 111.1 83.3
fMAX4 Maximum Register Toggle Frequency 1/(tWL +
tWH)[4 , 17] Com’l/Ind 125.0 111.1 83.3 MHz
Mil 111.1 83.3
tOH O utput Data Stable Time from S ynchronous
Clock Input[4, 18] Co m’l/ Ind 3 3 3 ns
Mil 3 3
Shaded area contains preliminary information.
Notes:
8. This parameter is the delay from an input signal applied to a dedicated i nput pin to a combinatorial output on any output pin. This delay ass umes no expander
terms are used to form the logic function.
9. This parameter is the delay associated with an input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are us ed to
form the logic function.
10. This parameter is the delay associated with an input signal applied to a dedicated input pin to combinatorial output on any output pin. This delay assumes
expander terms are used to form the logic function and includes the worst- case ex pander logic delay for one pass through the expander logic. This parameter
is tested periodically by sampling production material.
11. This parameter is the delay associated with an input signal applied to an I/O macrocell pin to any output pin. This delay assumes expander terms are used
to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by
sampling production material.
12. This specification is a measure of the delay from synchronous register clock input to internal feedback of the register output signal to a combinatorial output
for which the registered output signal is used as an input. This parameter assumes no expanders are used in the logic of the combinatorial output and the
regi ster i s synchron ously cl ocked. Th is paramete r is tested periodical ly by sam pling production material .
13. This specification is a measure of the delay associated with the internal register feedback path. This delay plus the r egister set-up time, tS, is the minimum
internal period fo r an inter nal state machi ne configur ation. This pa ramet er is t ested per iodical ly by samplin g producti on mat erial.
14. This specification indicates the guaranteed maximum frequency at whic h a state machine configuration with external only feedback can operate.
15. This specification indicates the guaranteed maximum frequency at whic h a state mac hine with internal-only feedback can operate. If register output states
must also control external points, this frequency can still be observed as long as it is less than 1/tCO1. This specif ication assumes no expand er log ic is used. This
parameter is tes ted per iodically by sampl ing pr oduction mater ial.
16. This frequency indicates the max imum frequency at which the device may operate in data-path mode (dedicated input pin to output pin). This assumes that
no expander logic is used.
17. This specification indicates the guaranteed maximum frequency in synchronous mode, at whic h an individual output or buried register can be cycled by a
clock signal applied to either a dedicated input pin or an I/O pin.
18. This parameter indicates the mi nimum time after a synchronous register clock input that the previous register output data is maintained on the output pin.
CY7C344
CY7C344B
6
External Sync hronous Switching Characteristics[7 ] Over Operating Range (continued)
7C344–20
7C344B–20 7C344–25
7C344B–25
Parameter Description Min. Max. Min. Max. Unit
tPD1 Dedicated Inp ut to Combinatorial Output Delay[8] Com’l /Ind 20 25 ns
Mil 20 25
tPD2 I/O Input t o Combinatorial Output Delay[9] Com’l/Ind 20 25 ns
Mil 20 25
tPD3 Dedicated Input to Combinatorial Output Delay with Ex-
pander Delay[10] Com’l /Ind 30 40 ns
Mil 30 40
tPD4 I/O Input to Combinatorial Output Delay with Exp ander
Delay[4, 11] Com’l/Ind 30 40 ns
Mil 30 40
tEA In put to Output Enable Delay[4] Com’l/Ind 20 25 ns
Mil 20 25
tER Input to Output Disabl e Delay[4] Com’l /Ind 20 25 ns
Mil 20 25
tCO1 Synchronous Clock Input to Output Dela y Com’l /Ind 12 15 ns
Mil 12 15
tCO2 Synchronous Clo ck to Local Feedback to Combinato-
rial Output[4, 12] Com’l /Ind 22 29 ns
Mil 22 29
tSDedicated Input or Feedback Set-Up Time to Synchro-
nous Clock Input Com’l/Ind 12 15 ns
Mil 12 15
tHInput Hold Time from Synchronous Clock Input[7] Com’l /Ind 0 0 ns
Mil 0 0
tWH Synchronous Clock In put HIGH Time[4] Com’l/Ind 7 8 ns
Mil 7 8
tWL Synchronous Clock In put LOW Time[4] Com’l /Ind 7 8 ns
Mil 7 8
tRW Asynchronous Clear Width[4] Com’l /Ind 20 25 ns
Mil 20 25
tRR Asynchronous Clear Recovery Time[4] Com’l /Ind 20 25 ns
Mil 20 25
tRO Asynchronous Clear to Registered Output Delay[4] Com’l /Ind 20 25 ns
Mil 20 25
tPW Asynchr onous Preset Width[4] Com’l /Ind 20 25 ns
Mil 20 25
tPR Asynchr onous Preset Recovery Time[4] Com’l /Ind 20 25 ns
Mil 20 25
tPO Asynchr onous Preset to Registered Output Delay[4] Com’l /Ind 20 25 ns
Mil 20 25
tCF Synchr o n ous Clock t o Local Feedback Input[4, 13] Com’l /Ind 4 7 ns
Mil 4 7
tPExternal Synchronous Clock Period (1/fMAX3)[4] Com’l/Ind 14 16 ns
Mil 14 16
CY7C344
CY7C344B
7
External Sync hronous Switching Characteristics[7 ] Over Operating Range (continued)
7C344–20
7C344B–20 7C344–25
7C344B–25
Parameter Description Min. Max. Min. Max. Unit
fMAX1 External Maximum Fre quency(1/(tCO1 + tS))[4 , 14 ] Com’l/Ind 41.6 33.3 MHz
Mil 41.6 33.3
fMAX2 Maximum Fre quency wit h Internal Only Feedback
(1/(tCF + tS))[4, 15] Com’l/Ind 62.5 45.4 MHz
Mil 62.5 45.4
fMAX3 Data Path M aximum Fr equency, le ast of 1/(tWL + tWH),
1/(tS + tH), or (1/tCO1)[4, 16] Com’l/Ind 71.4 62.5 MHz
Mil 71.4 62.5
fMAX4 Maximum Register Toggle Frequenc y 1/(tWL + tWH)[4, 17] Com’l/Ind 71.4 62.5 MHz
Mil 71.4 62.5
tOH Output Data Stable Tim e from
Synchronous Clock Input[4, 18] Com’l/ Ind 3 3 ns
Mil 3 3
External Asynchronous Switching Characteristics Over Operating Range[7]
7C344B–10 7C344B–12 7C344–15
7C344B–15
Parameter Description Min. Max. Min. Max. Min. Max. Unit
tACO1 Asynchronous Clock Input to Output Delay Com’l/ Ind 10 12 15 ns
Mil 12 15
tACO2 Asynchronous Clock Input to Local Feedback to
Combinatorial Output[19] Com’l/Ind 15 18 30 ns
Mil 18 30
tAS Dedicated Input or Feedback Set-Up Tim e to
Asynchronous Clock Input Com’l/Ind 4 4 7 ns
Mil 4 7
tAH Input Hold Time from Asynchronous Clock Input Com’l/Ind 3 4 7 ns
Mil 4 7
tAWH Asynchronous Clock Input HIGH Time[4, 20] Com’l/Ind 4 5 6 ns
Mil 5 6
tAWL Asynchronous Clock Input LOW Time[4] Com’l/Ind 5 6 7 ns
Mil 6 7
tACF Asynchronous Clock to Local Feedback Input[4,
21] Com’l /Ind 7 9 18 ns
Mil 9 18
tAP External Asynchronous Clock Period (1/fMAX4)[4] Com’l/Ind 12 12.5 13 ns
Mil 12.5 13
fMAXA1 External Maximum Frequency in Asynchronous
Mode 1/(tACO1 + tAS)[4, 22] Com’l/Ind 71.4 62.5 45.4 MHz
Mil 62.5 45.4
fMAXA2 Maximum Internal Asynchronous Frequency
1/(tACF + tAS) or 1/( t AWH + tAWL)[4, 23] Com’l/Ind 90.9 76.9 40 MHz
Mil 76.9 40
fMAXA3 Data Path Maximum Frequency in Asynchronous
Mode[4, 24] Com’l/Ind 100.0 83.3 66.6 MHz
Mil 83.3 66.6
fMAXA4 Maximum Asynchronous Register Toggle Fre-
quency 1/(tAWH + tAWL)[4, 25] Com’l /Ind 111.1 90.9 76.9 MHz
Mil 90.9 76.9
tAOH Output Data Stable Time from As ynchronous
Clock Input[4, 26] Com’l/Ind 12 12 15 ns
Mil 15
Shaded area contains preliminary information.
CY7C344
CY7C344B
8
External Asynchronous Switching Characteristics Over Operating Range[7] (continued)
7C344–20
7C344B–20 7C344–25
7C344B–25
Parameter Description Min. Max. Min. Max. Unit
tACO1 As ynchronous Clock Input to Output Delay Com’l/ In d 20 25 ns
Mil 20 25
tACO2 Asy nchronous Clock Input to Local Feedba ck to Com-
binatorial Output[19] Com’l/Ind 30 37 ns
Mil 30 37
tAS Dedicated Input or Feedback Set-Up Time to Asyn-
chronous Clock Inp ut Com’l/Ind 9 12 ns
Mil 9 12
tAH Input Hold Time from Asynchronous Clock Input Com’l/Ind 9 12 ns
Mil 9 12
tAWH Asynchronous Clock Input HI GH Time[ 4 , 20 ] Com’l/Ind 7 9 ns
Mil 7 9
tAWL Asynchronous Clock Input LOW Time[4] Com’l/Ind 9 11 ns
Mil 9 11
tACF Asynchronous Clock to Local Feedback I nput[4, 21] Com’l /Ind 18 21 ns
Mil 18 21
tAP External Asynchronous Clock Period (1/fMAX4)[4] Com’l/Ind 16 20 ns
Mil 16 20
fMAXA1 External Ma ximum Frequency in A sync hron ous Mode
1/(tACO1 + tAS)[4, 22] Com’l/Ind 34.4 27 MHz
Mil 34.4 27
fMAXA2 Maximum In ternal Asynchronous Freq uency 1/ (tACF +
tAS) or 1/(tAWH + t AWL)[4, 23] Com’l/Ind 37 30.3 MHz
Mil 37 30.3
fMAXA3 Data Pat h Maximum Frequency in Asynchronous
Mode[4, 2 3] Com’l/Ind 50 40 MHz
Mil 50 40
fMAXA4 Maximum Asynchronous Register Toggle Frequency
1/(tAWH + t AWL)[4, 25 ] Com’l /Ind 62.5 50 MHz
Mil 62.5 50
tAOH Output Data St able Time fr om Asynchronous Clock
Input[4, 26] Com’l/Ind 15 15 ns
Mil 15 15
Notes:
19. This specification is a measure of the delay fr om an asynchronous register clock input to internal feedback of the registered output signal to a combinatorial
output for which the registered output signal is used as an input. Assumes n o expanders are used in logic of combinatorial output or the asynchronous clock
input. Th is parameter i s tested peri odical ly by sampli ng production material .
20. This parameter is measured with a positive-edge-triggered clock at the register. For negative edge triggering, the tAWH and tAWL parameters must be s wapped.
If a gi ven input is u sed to c lock multiple r egis ters with bot h pos itiv e and negati ve po larity, tAWH should b e used fo r b oth tAWH and tAWL.
21. This specification is a measure of the delay associated with the internal register feedback path for an asynchronously clocked reg ister. This delay plus the
asynchronous register set-up time, tAS, is the mi nimum in ternal period fo r an asy nchronously cloc ked stat e machine configura tion. Th is delay assumes no expa nder logic
in the asynchr onous cl ock path. This pa rameter is tes ted peri odical ly by sampling produc tion mat erial.
22. This parameter indicates the guaranteed maximum frequency at which an asynchronously clocked state machine configuration with external feedback can
operate. It is assumed that no expander logic is employ ed in the clock signal path or data path.
23. This specification indicates the guaranteed maximum frequency at which an asynchronous ly clocked state machine with internal-only feedback can operate.
If register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/tACO1. Thi s spec ificat ion
assumes no expand er log ic is ut ilized. Thi s par ameter is teste d per iodically by sampli ng productio n materi al.
24. This specification indicates the guaranteed maximum frequency at whic h an indiv idual output or buried r egister can be cycled in asynchronously clocked
mode. This frequency is least of 1/(tAWH + tAWL), 1 /(t AS + tAH), or 1/tACO1. It al so in dicates the maximum fr equency at whi ch the device may oper ate in the asyn chronous ly
clocked d ata-path m ode. As sumes no expa nder l ogic is u sed.
25. This specification indicates the guaranteed maximum frequency at whic h an indiv idual output or buried r egister can be cycled in asynchronously clocked
mode by a clock signal applied to an external dedicated input or an I/O pin.
26. This parameter indicates the minimum time that the previous register output data is maintained on the output pin after an asynchronous register clock input
to an external dedicated input or I/O pi n.
CY7C344
CY7C344B
9
Typi cal Internal Switching Ch aracteristic s Over Operating Range[7]
7C344B–10 7C344B–12 7C344–15
7C344B–15
Parameter Description Min. Max. Min. Max. Min. Max. Unit
tIN Dedicated Input P ad and Buffer Delay Com’ l/In d 2 2. 5 4 ns
Mil 2.5 4
tIO I/O Input Pad and Buffer Delay Com’l/In d 2 2.5 4 ns
Mil 2.5 4
tEXP Expander Arr ay Del a y Com’l/Ind 6 68ns
Mil 68
t
LAD L ogic Arr a y Data Delay Com’ l/Ind 5 67ns
Mil 67
t
LAC L o gic Arr ay Control Delay Com’l/Ind 5 55ns
Mil 55
t
OD Output Buffer and Pad Delay Com’l/In d 3 34ns
Mil 34
t
ZX Output Buffer Enable Delay[27] Com’l /Ind 5 57ns
Mil 57
t
XZ Output Buff er Disable Delay Com’l/In d 5 57ns
Mil 57
t
RSU Register Set-Up Time Relative to Clock Signal
at Regist er Com’l/Ind 2 2 5ns
Mil 2 5
tRH Register Hold Ti me Relative to Clock Signal at
Register Com’l/Ind 4 5 7ns
Mil 5 7
tLATCH Flow-Through Latch Delay Com’l/Ind 0.5 0.5 1 ns
Mil 0.5 1
tRD Register Delay Com’l/Ind 0.5 0.5 1 ns
Mil 0.5 1
tCOMB Tr ansparent Mode Delay[28] Com’l/Ind 0.5 0.5 1 ns
Mil 0.5 1
tCH Clock HIGH Time Com’l/Ind 3 4 6ns
Mil 4 6
tCL Clock LOW Time Com’l/In d 3 4 6ns
Mil 4 6
tIC Asynchronous Clock L ogic Del a y Com’l/Ind 5 67ns
Mil 67
t
ICS Synchr onous Clock Delay Com’l/Ind 0.5 0.5 1 ns
Mil 0.5 1
tFD Feedback Delay Com’l/Ind 1 11ns
Mil 11
t
PRE Asynchronous Register Preset Time Com’l/Ind 2 35ns
Mil 35
t
CLR A s ynchronous Register Clear Time Com’ l/Ind 2 35ns
Mil 35
t
PCW Asynchronous Preset and Clear Pulse Width Com’l/Ind 2 3 5ns
Mil 3 5
tPCR Asy nchronous Preset and Clear Recovery T ime Com’l/ Ind 2 3 5ns
Mil 3 5
Shaded area contains preliminary information.
Notes:
27. Sample tested only for an output change of 500 mV.
28. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combi-
natorial operation.
CY7C344
CY7C344B
10
Typical Internal Switching Characteristics Over Oper ating Range[7] ( continued)
7C344–20
7C344B–20 7C344–25
7C344B–25
Parameter Description Min. Max. Min. Max. Unit
tIN Dedicated Input Pad and Buffer Delay Com’l/Ind 5 7 ns
Mil 5 7
tIO I/O Input Pad and Buffer Delay Com’l/Ind 5 7 ns
Mil 5 7
tEXP Expander Arr ay Delay Com’l/Ind 10 15 ns
Mil 10 15
tLAD Logic Array Data Delay Com’l/Ind 9 10 ns
Mil 9 10
tLAC Logic Array Control Delay Com’l/Ind 7 7 ns
Mil 7 7
tOD Output Buffer and Pad Delay Com’l/Ind 5 5 ns
Mil 5 5
tZX Output Buffer Enable Del ay[27] Com’l /Ind 8 11 ns
Mil 8 11
tXZ Output Buffer Disable Delay Com’l/Ind 8 11 ns
Mil 8 11
tRSU Register Set-Up Time Relative to Clock Signal at Reg-
ister Com’l/Ind 5 8 ns
Mil 5 8
tRH Register Hold Time Relative to Clock Signal at Register Com’l/Ind 9 12 ns
Mil 9 12
tLATCH Flow- Through Latch Delay Com’l/Ind 1 3 ns
Mil 1 3
tRD Register Delay Com’l/In d 1 1 ns
Mil 1 1
tCOMB Transparent Mode Delay[28] Com’l/Ind 1 3 ns
Mil 1 3
tCH Clock HIGH Time Com’l/Ind 7 8 ns
Mil 7 8
tCL Clock LOW Time Com’l/Ind 7 8 ns
Mil 7 8
tIC Asynchronous Clock Logic Delay Com’l/Ind 8 10 ns
Mil 8 10
tICS Synchronous Clock Delay Com’l/Ind 2 3 ns
Mil 2 3
tFD Feedback Delay Com’l/Ind 1 1 ns
Mil 1 1
tPRE Asynchronous Regi ster Preset Time Com’l/Ind 6 9 ns
Mil 6 9
tCLR Asynchronous Register Clear Time Com’l/Ind 6 9 ns
Mil 6 9
tPCW Asynchronous Preset and Clear Pulse Width Com’l/Ind 5 7 ns
Mil 5 7
tPCR Asynchronous Preset and Clear Recovery Time Com’l/Ind 5 7 ns
Mil 5 7
CY7C344
CY7C344B
11
Switching Waveforms
tACO1
External Combinatorial
External Synchronous
External Asynchronous
tPD1/tPD2
tER
tEA VALID OUTPUT
DEDICATED INPUT/
I/O INPUT
COMBINATORIAL
OUTPUT
COMBINATORIAL O R
REGISTERED OUTP UT
C344–8
HIGH-IMPEDANCE
THREE-STATE
HIGH-IMPEDANCE
THREE-STATE
tH
tStWH tWL
tRR/tPR
tRW/tPW
tOH
tCO1
tRO/tPO
tCO2
C344–9
DEDICATED INPUTS OR
REGISTERED FEEDB ACK
SYNCHRONOUS
CLOCK
ASYNCHRONOUS
CLEAR/PRESET
REGISTERED
OUTPUTS
COMBINATORIAL OUTPUT FROM
REGISTERED FEEDB ACK
tAH
tAS tAWH tAWL
tRR/tPR
tRW/tPW
tAOH
tRO/tPO
tACO2
ASYNCHRONOUS
CLOCK INPUT
ASYNCHRONOUS REGISTERED
OUTPUTS
DEDICATED INPUTS OR
REGISTERED FEEDB ACK
ASYNCHRONOUS
CLEAR/PRESET
COMBINATORIAL OUTPUT FROM
ASYNCH. REGISTERED
FEEDBACK C344–10
[12]
[19]
CY7C344
CY7C344B
12
Switching Waveforms (Continued)
Internal Combinatorial
Internal Asynchronous
Internal Synchronous (Input Path)
tIN
tIO tPIA
tEXP
tLAC,tLAD
C344–11
INPUT PIN
EXPANDER
I/O PIN
LOGIC ARRAY
tIO tAWH tAWL tF
tIN
tIC
tRSU tRH
tRD,tLATCH tFD tCLR,tPRE tFD
ARRA Y DELAY
OUTPUT
LOGIC ARRAY
INPUT
CLOCK PIN
LOGIC ARRAY
LOGIC ARRAY
CLOCK FROM
DATA FROM
CLOCK INTO
LOGIC ARRAY
REGISTER OUTPUT
TO ANOTHER LAB
tPIA
TO LOCAL LAB
REGISTER OUTPUT
LOGIC ARRAY
C344–12
tR
tCH tCL
tIN tICS
tRSU tRH
C344–13
SYSTEM CLOCK PIN
SYSTE M CLO CK
AT REGISTER
DATA FROM
LOGIC ARRAY
CY7C344
CY7C344B
13
Switching Waveforms (Continued)
Internal S ynchronous ( Output Path)
C344–14
tXZ tZX
tOD
HIGH Z
CLOCK FROM
LOGIC ARRAY
LOGIC ARRAY
DATA FROM
OUTPUT PIN
tRD
Orde rin g Inf orm a tio n
Speed
(ns) O rderi n g Code Package
Name Package Type Operating
Range
10 CY7C344B–10HC H64 28-Lead Windowed Leaded Chip Carrier Commercial
CY7C344B–10JC J64 28-Lead Pla stic Leaded Chip Carrier
CY7C344B–10PC P21 28- Lead (300-Mil) Molded DIP
CY7C344B–10WC W22 28- Lead Windowed CerDI P
12 CY7C344B–12HC/HI H64 28-Lead Windowed Leaded Chip Carrier Commercial/Industrial
CY7C344B–12JC/JI J64 28- L ead Plastic Leaded Chip Carr ier
CY7C344B–12PC/PI P21 28-Lead (300-Mil) Molded DIP
CY7C344B–12WC/WI W22 28-Lead Windowed CerDIP
CY7C344B–12HMB H64 28-Lead Windowed Leaded Chip Carrier Military
CY7C344B–12WMB W22 28-Lead Windowed CerDIP
15 CY7C344–15HC/HI H64 28-Lead Windowed Leaded Chip Carrier Commercial/Industrial
CY7C344–15JC/JI J64 28- Lead Pl a stic Leaded C hip Carr ier
CY7C344–15PC/PI P21 2 8-Lead (300-Mil) Molded DIP
CY7C344–15WC/WI W22 28-Lead Windowed CerDIP
CY7C344B–15HC/HI H64 28-Lead Windowed Leaded Chip Carrier
CY7C344B–15JC/JI J64 28- L ead Plastic Leaded Chip Carr ier
CY7C344B–15PC/PI P21 28-Lead (300-Mil) Molded DIP
CY7C344B–15WC/WI W22 28-Lead Windowed CerDIP
CY7C344B–15HMB H64 28-Lead Windowed Leaded Chip Carrier Military
CY7C344B–15WMB W22 28-Lead Windowed CerDIP
20 CY7C344–20HC/HI H64 28-Lead Windowed Leaded Chip Carrier Commercial/Industrial
CY7C344–20JC/JI J64 28- Lead Pl a stic Leaded C hip Carr ier
CY7C344–20PC/PI P21 2 8-Lead (300-Mil) Molded DIP
CY7C344–20WC/WI W22 28-Lead Windowed CerDIP
CY7C344B–20HC/HI H64 28-Lead Windowed Leaded Chip Carrier
CY7C344B–20JC/JI J64 28- L ead Plastic Leaded Chip Carr ier
CY7C344B–20PC/PI P21 28-Lead (300-Mil) Molded DIP
CY7C344B–20WC/WI W22 28-Lead Windowed CerDIP
CY7C344–20HMB H64 28-Lead Windowed Leaded Chip Carrier Military
CY7C344–20WMB W22 2 8-Lead Windowed CerDI P
CY7C344B–20HMB H64 28-Lead Windowed Leaded Chip Carrier
CY7C344B–20WMB W22 28-Lead Windowed CerDIP
Shaded area contains preliminary information.
CY7C344
CY7C344B
14
MIL ITARY SPECIF ICAT IONS
Group A Subgroup Testing
Document #: 38–00127–G
MAX is a registered trademark of Altera Corporati o n.
Warp2
and
Warp3
are register ed trademarks of Cypress Semiconductor Corporation.
Warp2
Sim is a trademark of Cypress Semiconduct or Corporation.
Orde rin g Inf orm a tio n (continued)
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
25 CY7C344–25HC/HI H64 28-Lead Windowed Leaded Chip Carrier Commercial/Industrial
CY7C344–25JC/JI J64 28- Lead Pl a stic Leaded C hip Carr ier
CY7C344–25PC/PI P21 2 8-Lead (300-Mil) Molded DIP
CY7C344–25WC/WI W22 28-Lead Windowed CerDIP
CY7C344B–25HC/HI H64 28-Lead Windowed Leaded Chip Carrier
CY7C344B–25JC/JI J64 28- L ead Plastic Leaded Chip Carr ier
CY7C344B–25PC/PI P21 28-Lead (300-Mil) Molded DIP
CY7C344B–25WC/WI W22 28-Lead Windowed CerDIP
CY7C344–25HMB H64 28-Lead Windowed Leaded Chip Carrier Military
CY7C344–25WMB W22 2 8-Lead Windowed CerDI P
CY7C344B–25HMB H64 28-Lead Windowed Leaded Chip Carrier
CY7C344B–25WMB W22 28-Lead Windowed CerDIP
Shaded area contains preliminary information.
DC Characteristics
Parameter Subgroups
VOH 1, 2, 3
VOL 1, 2, 3
VIH 1, 2, 3
VIL 1, 2, 3
IIX 1, 2, 3
IOZ 1, 2, 3
ICC1 1, 2, 3
Switching Characteristics
Parameter Subgroups
tPD1 7, 8, 9, 10, 11
tPD2 7, 8, 9, 10, 11
tPD3 7, 8, 9, 10, 11
tCO1 7, 8, 9, 10, 11
tS7, 8, 9, 10, 11
tH7, 8, 9, 10, 11
tACO1 7, 8, 9, 10, 11
tACO1 7, 8, 9, 10, 11
tAS 7, 8, 9, 10, 11
tAH 7, 8, 9, 10, 11
CY7C344
CY7C344B
15
Package Diagrams
28-Pin Windowed Leaded Chip Carrier H64
CY7C344
CY7C344B
16
Package Diagrams (Continued)
28-Lead Plastic Leaded Chip Carrier J64
28-Lead (300-Mil) Mold ed DIP P21
CY7C344
CY7C344B
© Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semico nductor Corporation a ssumes no responsibility for the use
of any circuitry othe r than circui try embodi ed in a Cypress Semi conductor prod uct. Nor do es it convey or im ply an y li cens e under p atent or other rights . Cy press Semi conductor does not authori ze
its products for use as critical components in life- support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems appl ication impl ies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypr ess Semiconductor against all charges.
Package Diagrams (Continued)
28-Lead (300-Mil) Windowed CerDIP W22
MIL–STD–1835 D– 15Config.A
