EN5322QI-E - ALTERA - Datasheet.Live

03454 September 12, 2012 Rev: E

Created on 6/26/2012 11:19:00 AM

EN5322QI

2 A Voltage Mode Synchronous Buck PWM

DC-DC Converter with Integrated Inductor

RoHS Compliant

Halogen Free

General Description

The EN5322 is a high efficiency synchronous

buck converter with integrated inductor, PWM

controller, MOSFETS, and compensation

providing the smallest possible solution size.

The 4 MHz operation allows for the use of tiny

MLCC capacitors. It also enables a very wide

control loop bandwidth providing excellent

transient performance and reduced output

impedance. The internal compensation is

designed for unconditional stability across all

operating conditions.

Three VID output voltage select pins provide

seven pre-programmed output voltages along

with an option for external resistor divider.

Output voltage can be programmed on-the-fly to

provide fast, dynamic voltage scaling with

smooth transitions between VID programmed

output voltages.

Applications

• Point of Load Regulation for Low Power

Processors, Network Processors, DSPs’

FPGAs and ASICs

• Replacement of LDOs

• Noise Sensitive Applications such as A/V and

RF

• Computing, Computer Peripherals, Storage,

Networking, and Instrumentation

• DSL, STB, DVR, DTV, and iPC

Ordering Information

Part Numbe

r

Temp Rating (°C) Package

EN5322QI -40 to +85 24-pin QFN T&R

EN5322QI-E QFN Evaluation Board

Features

• Revolutionary Integrated Inductor

• Total Solution Footprint as Small as 50 mm2

• 4 mm x 6 mm x 1.1 mm QFN Package

• 4 MHz Fixed Switching Frequency

• High Efficiency, up to 95 %

• Low Ripple Voltage; 8 mVP-P Typical

• 2% Initial VOUT Accuracy with VID Codes

• 2% Initial 0.6 V Feedback Voltage Accuracy

• 2.4 V to 5.5 V Input Voltage Range

• 2 A Continuous Output Current Capability

• Fast Transient Response

• Low Dropout Operation: 100 % Duty Cycle

• Power OK Signal with 5 mA Sink Capability

• Dynamic Voltage Scaling with VID Codes

• 17 μA Typical Shutdown Current

• Under Voltage Lockout, Over Current, Short

Circuit, and Thermal Protection

• RoHS Compliant; MSL 3 260 °C Reflow

Application Circuit

EN5322

10 uF 47 uF

VOUTPVIN

AGND

VIN VSENSE

POK

VS0

VS1

VS2

ENABLE

AVIN

PGND

CIN COUT

1 uF

VOUT

PGND

Figure 1. Typical Application Circuit

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EN5322QI

Absolute Maximum Rati ngs

CAUTION: Absolute maximum ratings are stress ratings only. Functional operation beyond recommended operating

conditions is not implied. Stress beyond absolute max imum ratings may cause permanent damage to the device.

Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

Absolute Maximum Electrical Ratings MIN MAX

Voltages on: PVIN, AVIN, VOUT -0.3 V 6.5 V

Voltages on: VSENSE, VS0, VS1, VS2, ENABLE, POK -0.3 V VIN

Voltage on: VFB -0.3 V 2.7 V

ESD Rating (Human Body Model) 2 kV

ESD Rating (Charge Device Model) 500 V

Absolute Maximum Thermal Ratings

Ambient Operating Range -40 °C +85 °C

Storage Temperature Range -65 °C +150 °C

Reflow Peak Body Temperature MSL3 (10 s) +260 °C

Thermal Characteristics

PARAMETER SYMBOL MIN TYP MAX UNITS

Thermal Shutdown TSD 155 °C

Thermal Shutdown Hysteresis TSDH 15 °C

Thermal Resistan ce: Junction to Case (0 LFM)

θ

JC 6 °C/W

Thermal Resistan ce: Junction to Ambient (0 LFM)*

θ

JA 36 °C/W

* Based on a 2 oz. copper board and proper thermal design in line with JEDEC EIJ-JESD51 standards

Recommended Operating Conditions

PARAMETER SYMBOL MIN MAX UNITS

Input Voltage Range VIN 2.4 5.5 V

Output Voltage Range VOUT 0.6 VIN - VDROPOUT V

Output Current ILOAD 0 2 A

Operating Junction Temperature TJ -45 +125 °C

Note: VDROPOUT is defined as (ILOAD x Dropout Resistance) includin g temperature effect.

Electrical Characteristics

VIN = 5 V and TA = 25 °C, unless otherwise noted.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Operating Input Voltage VIN 2.4 5.5 V

Under Voltage Lockout VUVLO V

IN going low to high 2.2 V

UVLO Hysteresis 0.15 V

Output Voltage with VID

Codes (Note 1)

VOUT

TA = 25 °C; VIN = 5V

ILOAD = 100 mA

VS2 VS1 VS0 VOUT (V)

0 0 0 3.3

0 0 1 2.5

0 1 0 1.8

0 1 1 1.5

1 0 0 1.25

1 0 1 1.2

1 1 0 0.8

-2.0

+2.0

%

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EN5322QI

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

VFB Voltage VFB TA = 25 °C; VIN = 5V

ILOAD = 100 mA, VS0 = VS1 = VS2 = 1 0.588 0.600 0.612 V

Output Voltage with VID

Codes (Note 1)

VOUT

2.4 V ≤ VIN ≤ 5.5 V, ILOAD = 0 ~ 2 A,

-40°C ≤ TA ≤ +85°C

VS2 VS1 VS0 VOUT (V)

0 0 0 3.3

0 0 1 2.5

0 1 0 1.8

0 1 1 1.5

1 0 0 1.25

1 0 1 1.2

1 1 0 0.8

-3.0

-3.5

+3.0

%

VFB Voltage VFB 2.4 V

≤

VIN

≤

5.5 V, ILOAD = 0 ~ 2 A,

VS0 = VS1 = VS2 = 1,

-40°C ≤ TA ≤ +85°C 0.582 0.600 0.618 V

Dynamic Voltage Slew Rate Switching between VID settings 0.975 1.5 2.025 V/ms

Soft Start Slew Rate VID Mode VOUT Programming 0.975 1.5 2.025 V/ms

Soft Start Time VFB Mode VOUT Programming 0.78 1.2 1.62 ms

VFB, ENABLE, VS0-VS2

Pin Input Current (Note 2) -40°C ≤ TA ≤ +85°C +/-40 nA

ENABLE, VS0-VS2 Voltage

Threshold Logic Low

Logic High 0.0

1.4 0.4

VIN V

POK Upper Threshol d VOUT Rising 111 %

POK Upper Threshol d VOUT Falling 102 %

POK Lower Threshold VOUT Rising 92 %

POK Lower Threshold VOUT Falling 90 %

POK Low Voltage ISINK = 5 mA, -40°C

≤

TA

≤

+85°C 0.15 0.4 V

POK Pin VOH Leakage

Current POK High, -40°C ≤ TA ≤ +85°C 500 nA

Shutdown Current ENABLE Low 17

μ

A

Quiescent Current No Switching 800

μ

A

Quiescent Current Switching, VOUT = 1.2 V 15 mA

Current Limit Threshold 2.4 V

≤

VIN

≤

5.5 V,

-40°C ≤ TA ≤ +85°C 2.1 3.0 A

PFET On Resistance 160 m

Ω

NFET On Resistance 60 m

Ω

Dropout Resistance 200 300 m

Ω

Operating Frequency FOSC 4 MHz

Output Ripple Voltage VRIPPLE

COUT = 1 x 47

μ

F 1206 X5R MLCC,

VOUT = 1.2 V, ILOAD = 2 A 14 mVP-P

COUT = 2 x 22

μ

F 0805 X5R MLCC,

VOUT = 1.2 V, ILOAD = 2 A 8 mVP-P

Note 1: The tolerances hold true only if VIN is greater than (VOUT + VDROPOUT).

Note 2: VFB, ENABLE, VS0-VS2 pin input current specification is guaranteed by design.

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EN5322QI

Pin Configuration

Figure 2. Pin Diagram, Top View.

Pin Description

PIN NAME FUNCTION

1, 21-24 NC(SW)

No Connect. These pins are internally connected to the common drain output of the internal

MOSFETs. NC(SW) pins are not to be electri cally connected to any external signal, ground, or

voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result

in part malfunction or damage.

2-3, 8-9 PGND Input/Output Power Ground. Connect these pins to the ground electrode of the input and

output filter capacitors. Refer to Layout Considerations sectio n for details.

4-7 VOUT Voltage and Power Output. Conne ct these pins to output capacitor(s).

10-12 VS2-0

Output Voltage Select. These pins set one of seven preset output voltages and the external

divider option (refer to Electrical Characteristics table for more details), and can be directly

pulled up to VIN or pulled down to GND; these pins must not be left floating.

13 VSENSE

Sense Pin for Internally Programmed Output Voltages with VID Codes. For either VID cod e or

external resistor divider applications, connect this pin to the last local output filter capacitor for

internal compensation.

14 VFB

Feedback Pin for External Voltage Divider Netwo rk. Connect a resistor divider to this pin to set

the output voltage. Use 340 kΩ, 1% or better for the upper resistor.

15 AGND Analog Ground for the Controller Circuits

16 AVIN

Analog Voltage Input for the Controller Circuits. Con nect this pin to the input power supply.

Use a 1 μF bypass capacitor on this pi n.

17 POK Power OK with an Open Drain Output. Refer to Power OK section.

18 ENABLE

Input Enable. A logic high signal on this pin enables the output and initiates a soft start. A

logic low signal disa bles the output and discharges the output to GND. This pin must not be

left floating.

19-20 PVIN Input Power Supply. Connect to input supply. Decouple with input capacito r(s) to PGND.

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EN5322QI

Functional Block Diagram

Voltage

Select

DAC

Switch

VREF

(+)

(-)

Error

Amp

VSENSE

VFB

VOUT

VS0 VS1 VS2

Package Boun dar y

P-Drive

N-Drive

UVLO

Therm al Lim it

Current Limi t

Soft Start

Sawtooth

Generator

(+)

(-)PWM

Comp

PVIN

ENABLE

PGND

Logic

Compensation

Network

NC (S W)

POK

AVIN AGND

BIAS

Figure 3. Functional Block Diagram.

03454 September 12, 2012 Rev: E

EN5322QI

EN5322

10 uF 47 uF

VOUTPVIN

AGND

VIN VSENSE

POK

VS0

VS1

VS2

ENABLE

AVIN

PGND

CIN COUT

1 uF

VOUT

PGND

RPOK 100k

* Leave open if the POK function is not used.

*

RPOK

POK

Figure 4. Typical Application Circuit with VID Codes.

(NOTE: Enable can be separated from PVIN if the application requires it)

Typical Performance Characteristics

Circuit of Figure 4, VIN = 5 V, VOUT = 1.2 V and TA = 25°C, unless otherwise noted.

Efficiency vs. Load Current (Vin = 5.0V)

50

55

60

65

70

75

80

85

90

95

0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00

Load Current (A)

Efficiency (%)

Top to Bottom: VOUT = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V,

0.8 V

Efficiency vs. Load Current (Vin = 3.3V)

50

55

60

65

70

75

80

85

90

95

0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00

Load Current (A)

Efficiency (%)

Top to Bottom: VOUT = 2.5 V, 1.8 V, 1.5 V, 1.2 V, 0.8 V

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EN5322QI

Quiescent Current (No Switching) vs.

Input Voltage

740

760

780

800

820

840

23456

Input Voltage (V)

Quiescent Current (uA)

Quiescent Current (Switching) vs.

Input Voltage

8

10

12

14

16

18

23456

Input Voltage (V)

Quiescent Current (mA)

Load Regulation (Vin = 5 V)

1.184

1.188

1.192

1.196

1.200

1.204

1.208

0 0.4 0.8 1.2 1.6 2

Load Current (A)

Output Voltage (V)

Load Regulation (Vin = 5 V)

3.284

3.288

3.292

3.296

3.300

3.304

0 0.4 0.8 1.2 1.6 2

Load Current (A)

Output Voltage (V)

Output Ripple at 2 A Load (CH2: VOUT)

VIN = 3.3 V, VOUT = 1.2 V, COUT = 1 x 47 μF

Output Ripple at 2 A Load (CH2: VOUT)

VIN = 3.3 V, VOUT = 1.2 V, COUT = 2 x 22 μF

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EN5322QI

Transient Response at VIN = 5 V

VOUT = 1.2V, COUT = 1 x 47 μF

(0-2 A Load Step, slew rate ≥ 10A/uS)

CH1: VOUT, CH4: ILOAD

Transient Response at VIN = 5 V

VOUT = 3.3V, COUT = 1 x 47 μF

(0-2 A Load Step, slew rate ≥ 10A/uS)

CH1: VOUT, CH4: ILOAD

VOUT Scaling with VID Codes at VIN = 5 V

(VOUT = 1.2 V – 2.5 V, IOUT = 0 – 2 A)

CH1: VS2, CH2: VOUT, CH3: POK

VOUT Scaling with VID Codes at VIN = 3.3 V

(VOUT = 1.2 V – 2.5 V, IOUT = 0 – 2 A)

CH1: VS2, CH2: VOUT, CH3: POK

Power Up/Down at No Load (VIN = 5 V, VOUT = 1.2 V)

CH1: ENABLE, CH2: VOUT, CH3: POK, CH4: IINDUCTOR

Power Up/Down at 0.6 Ω Load (VIN = 5 V, VOUT = 1.2 V)

CH1: ENABLE, CH2: VOUT, CH3: POK, CH4: IINDUCTOR

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EN5322QI

Output Over Load at No Load (VIN = 5 V, VOUT = 1.2 V)

CH2: VOUT, CH3: POK, CH4: IINDUCTOR

Output Over Load at 2 A Load (VIN = 5 V, VOUT = 1.2 V)

CH2: VOUT, CH3: POK, CH4: IINDUCTOR

Output Over Load at No Load (VIN = 5 V, VOUT = 1.2 V)

CH2: VOUT, CH3: POK, CH4: IINDUCTOR

Output Over Load at 2 A Load (VIN = 5 V, VOUT = 1.2 V)

CH2: VOUT, CH3: POK, CH4: IINDUCTOR

Functional Description

The EN5322 leverages advanced CMOS

technology to provide high switching

frequency, while also maintaining high

efficiency.

Packaged in a 4 mm x 6 mm x 1.1 mm QFN,

the EN5322 provides a high degree of flexibility

in circuit design while maintaining a very small

footprint. High switching frequency allows for

the use of very small MLCC input and output

filter capacitors.

The converter uses voltage mode control to

provide high noise immunity, low output

impedance and excellent load transient

response. No external compensation

components are needed for most applications.

Output voltage is chosen from one of seven

preset values via a three-pin VID voltage select

scheme. An external divider option enables the

selection of any output voltage ≥ 0.6 V. The

VID pins can be toggled dynamically to

implement glitch-free dynamic voltage scaling

between any two VID preset values.

POK monitors the output voltage and signals if

it is within ±10% of nominal. Protection

03454 September 12, 2012 Rev: E

EN5322QI

features include under voltage lockout (UVLO),

over current protection, short circuit protection,

and thermal overload protection.

Stability over Wide Range of Operating

Conditions

The EN5322 utilizes an internal compensation

network and is designed to provide stable

operation over a wide range of operating

conditions. To improve transient performance

or reduce output voltage ripple with dynamic

loads you have the option to add

supplementary capacitance to the output.

When programming VOUT using the VID pins,

the EN5322 is stable with up to 60 μF of output

capacitance without compensation adjustment.

Additional output capacitance above 60 μF can

be accommodated with compensation

adjustment depending on the application.

When programming VOUT with the resistor

divider option, the maximum output

capacitance may be limited. Please refer to

the section on soft start for more details. The

high switching frequency allows for a wide

control loop bandwidth.

Soft Start

The EN5322QI has an internal soft-start circuit

that controls the ramp of the output voltage.

The control circuitry limits the VOUT ramp rate to

levels that are safe for the Power MOSFETS

and the integrated inductor.

The EN5322QI has two soft start operating

modes. When VOUT is programmed using a

preset voltage in VID mode, the device has a

constant slew rate. When the EN5322QI is

configured in external resistor divider mode,

the device has a constant VOUT ramp time.

Output voltage slew rate and ramp time is

given in the Electrical Characteristics Table.

Excess bulk capacitance on the output of the

device can cause an over-current condition at

startup.

When operating in VID mode, the maximum

total capacitance on the output, including the

output filter capacitor and bulk and decoupling

capacitance, at the load, is given as:

COUT_TOTAL_MAX = COUT_Filter + COUT_BULK =

1000uF

When the EN5322QI output voltage is

programmed using and external resistor divider

the maximum total capacitance on the output is

given as:

COUT_TOTAL_MAX = 1.867x10-3/VOUT Farads

The above number and formula assume a no

load condition at startup.

Over Current/Short Circuit Protection

When an over current condition occurs, VOUT is

pulled low. This condition is maintained for a

period of 1.2 ms and then a normal soft start

cycle is initiated. If the over current condition

still persists, this cycle will repeat.

Under Voltage Lockout

An under voltage lockout circuit will hold off

switching during initial power up until the input

voltage reaches sufficient level to ensure

proper operation. If the voltage drops below the

UVLO threshold the lockout circuitry will again

disable switching. Hysteresis is included to

prevent chattering between UVLO high and low

states.

Enable

The ENABLE pin provides means to shut down

the converter or initiate normal operation. A

logic high will enable the converter to go

through the soft start cycle and regulate the

output voltage to the desired value. A logic low

will allow the device to discharge the output

and go into shutdown mode for minimal power

consumption. When the output is discharged,

an auxiliary NFET turns on and limits the

discharge current to 300 mA or below. In

shutdown mode, the device typically drains

17μA. The ENABLE pin must not be left

floating.

03454 September 12, 2012 Rev: E

EN5322QI

Thermal Shutdown

When excessive power is dissipated in the

device, its junction temperature rises. Once the

junction temperature exceeds the thermal

shutdown temperature 155 °C, the thermal

shutdown circuit turns off the converter,

allowing the device to cool. When the junction

temperature drops 15 °C, the device will be re-

enabled and go through a normal startup

process.

Power OK

The EN5322 provides an open drain output to

indicate if the output voltage stays within 92%

to 111% of the set value. Within this range, the

POK output is allowed to be pulled high.

Outside this range, POK remains low.

However, during transitions such as power up,

power down, and dynamic voltage scaling, the

POK output will not change state until the

transition is complete for enhanced noise

immunity.

The POK has 5 mA sink capability for events

where it needs to feed a digital controller with

standard CMOS inputs. When POK is pulled

high, the pin leakage current is as low as 500

nA maximum over temperature. This allows a

large pull up resistor such as 100 kΩ to be

used for minimal current consumption in

shutdown mode.

The POK output can also be conveniently used

as an ENABLE input of the next stage for

power sequencing of multiple converters.

Figure 5. Typical Application Circuit with External Resistor Divider.

(NOTE: Enable can be separated from PVIN if the application requires it)

Application Information

Setting the Output Voltage

To provide the highest degree of flexibility in

choosing output voltage, the EN5322QI uses a

3 pin VID (Voltage ID) output voltage select

arrangement. This allows the designer to

choose one of seven preset voltages, or to use

an external voltage divider. Figure 4 shows a

typical application circuit with VID codes.

Internally, the output of the VID multiplexer

sets the value for the voltage reference DAC,

which in turn is connected to the non-inverting

input of the error amplifier. This allows the use

of a single feedback divider with constant loop

gain and optimum compensation, independent

of the output voltage selected.

03454 September 12, 2012 Rev: E

EN5322QI

Table 1 shows the various VS0-VS2 pin logic

states and the associated output voltage

levels. A logic “1” indicates a connection to VIN

or to a “high” logic voltage level. A logic “0”

indicates a connection to ground or to a “low”

logic voltage level. These pins can be either

hardwired to VIN or GND or alternatively can be

driven by standard logic levels. Logic low is

defined as VLOW ≤ 0.4V. Logic high is defined

as VHIGH ≥ 1.4V. Any level between these two

values is indeterminate. These pins must not

be left floating.

Table 1. VID voltage select settings.

VS2 VS1 VS0 VOUT

0 0 0 3.3V

0 0 1 2.5V

0 1 0 1.8V

0 1 1 1.5V

1 0 0 1.25V

1 0 1 1.2V

1 1 0 0.8V

1 1 1 User

Selectable

External Voltage Divider

As described above, the external voltage

divider option is chosen by connecting the

VS0, VS1, and VS2 pins to VIN or logic “high”.

The EN5322QI uses a separate feedback pin,

VFB, when using the external divider. VSENSE

must be connected to VOUT as indicated in

Figure 5.

If the external voltage divider option is chosen,

use 340 kΩ, 1% or better for the upper resistor

Ra. Then the value of the bottom resistor Rb in

kΩ is given as:

Ω

−

=k

V

Rb

OUT 6.0

204

Where VOUT is the output voltage. Rb should

also be a 1% or better resistor.

Power-Up/Down Sequencing

During power-up, ENABLE should not be

asserted before PVIN, and PVIN should not be

asserted before AVIN. The PVIN should never

be powered when AVIN is off. During power

down, the AVIN should not be powered down

before the PVIN. Tying PVIN and AVIN or all

three pins (AVIN, PVIN, ENABLE) together

during power up or power down meets these

requirements.

Pre-Bias Start-up

The EN5322QI does not support startup into a

pre-biased condition. Be sure the output

capacitors are not charged or the output of the

EN5322QI is not pre-biased when the

EN5322QI is first enabled.

Input and Output Capacitor Selection

Low ESR MLC capacitors with X5R or X7R or

equivalent dielectric should be used for input

and output capacitors. Y5V or equivalent

dielectrics lose too much capacitance with

frequency, DC bias, and temperature.

Therefore, they are not suitable for switch-

mode DC-DC converter filtering, and must be

avoided.

A 10 μF, 10 V, 0805 MLC capacitor is needed

on PVIN for all applications. A 1 μF, 10 V, 0402

MLC capacitor on AVIN is needed for high

frequency bypass to ensure clean chip supply

for optimal performance.

A 47 μF, 6.3 V, 1206 MLC capacitor is

recommended on the output for most

applications. The output ripple can be reduced

by approximately 50% by using 2 x 22 μF,

6.3V, 0805 MLC capacitors rather than 1 x 47

μF.

As described in the Soft Start section, there is

a limitation on the maximum bulk capacitance

that can be placed on the output of this device.

Please refer to that section for more details.

03454 September 12, 2012 Rev: E

EN5322QI

Table 2. Recommended input and output capacitors

CIN

Description Mfg. P/N

10μF, 10V,

X5R, 10%,

0805

Taiyo Yuden LMK212BJ106KG

Murata GRM21BR71A106KE51L

Panasonic ECJ-2FB1A106K

COUT 47μF, 6.3V,

X5R, 20%,

1206

Taiyo Yuden JMK316BJ476ML

Murata GRM31CR60J476ME19L

Kemet C1206C476M9PACTU

POK Pull Up Resistor Selection

POK can be pulled up through a resistor to any

voltage source as high as VIN. The simplest

way is to connect POK to the power input of

the converter through a resistor. A 100 kΩ pull

up resistor is typically recommended for most

applications for minimal current drain from the

voltage source and good noise immunity. POK

can sink up to 5mA.

Layout Considerations

Proper layout and placement of external

components is critical to optimal functioning of

the converter and for minimizing radiated and

conducted noise.

Follow these layout guidelines as

demonstrated on the EN5322 customer eval

boards:

1. Input and output capacitors should be

placed on the same side of the PCB as

the EN5322 and immediately adjacent to

their respective pins on the package. To

minimize parasitic inductances, the traces

for making these connections should be

as short and wide as possible.

2. A row of vias connecting these capacitors’

ground pads to the PCB GND plane

should be placed along the edge of the

capacitor ground copper closest to the

positive capacitor pads. These vias

should start as close to the device as

possible and continue underneath the

capacitors.

3. Avoid adding a test pin or test pad for

NC(SW) pins on the PCB. Doing so can

compromise the GND plane and result in

degradation of the performance.

4. There should be as many vias as possible

connecting the thermal pad under the

device to the PCB GND plane for best

thermal performance. Ideally, the vias

should have a drill diameter of 0.33 mm

(10 mils) with at least 1 oz copper plating

in the barrel.

5. Keep the input and output current loops

separate from each other as much as

possible. Keep sensitive signals on the

PCB away from the power supply circuit.

6. Connect the VSENSE trace to the last

local output capacitor. Make sure the

trace inductance between the output

capacitors and the sensing point is

minimized. The VSENSE trace should

also be kept away from noisy signals that

can contaminate it.

7. When using multiple converters on the

same PCB, try to minimize any crosstalk

between them:

- Keep the input circuit of any converter

away from the output circuit of any

other converter.

- Isolate the input circuits from each

other by connecting all the inputs to a

common point using a star

connection. Add a 2.2 μF bypass

capacitor to the GND plane at the star

connection. Some applications may

benefit from an SMT ferrite bead

between the input capacitor of each

converter and the star connection

point.

03454 September 12, 2012 Rev: E

EN5322QI

Design Considerations for Lead-Frame Based Modules

Exposed Metal Pads on Package Bottom

QFN lead-frame based package technology utilizes exposed metal pads on the bottom of the

package that provide improved thermal dissipation and low package thermal resistance,

smaller package footprint and thickness, large lead size and pitch, and excellent lead co-

planarity. As the EN5322 package is a fully integrated module consisting of multiple internal

devices, the lead-frame provides circuit interconnection and mechanical support of these

devices resulting in multiple exposed metal pads on the package bottom.

Only the two large thermal pads and the perimeter leads are to be mechanically/electrically

connected to the PCB through a SMT soldering process. All other exposed metal is to remain

free of any interconnection to the PCB. Figure 6 shows the recommended PCB metal layout

for the EN5322 package. A GND pad with a solder mask "bridge" to separate into two pads

and 24 signal pads are to be used to match the metal on the package. The PCB should be

clear of any other metal, including traces, vias, etc., under the package to avoid electrical

shorting.

Figure 6. Recommended Footprint for PCB.

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EN5322QI

Package and Mechanical

Figure 7. EN5322QI Package Dimensions

03454 September 12, 2012 Rev: E

EN5322QI

Contact Information

Enpirion, Inc.

Perryville III

53 Frontage Road Suite 210

Hampton, NJ 08827

Phone: +1 908-894-6000

Fax: +1 908-894-6090

Enpirion reserves the right to make changes in circuit design and/or specifications at any time without notice. Information furnished by

Enpirion is believed to be accurate and reliable. Enpirion assumes no respo nsibility for its use or for infringement of patents or other third

party rights, which may result from its use. Enpirion products are not authorized for use in nuclear control systems, as critical components in

life support systems or equipment used in hazardous environment without the express written authority fro m Enpirion..