MCS9990 PCIe to 4-Port USB 2.0 Host Controller MCS9990 PCIe to 4-Port USB 2.0 Host Controller Datasheet Revision 3.00 Mar. 10th, 2015 1 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller IMPORTANT NOTICE Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. DISCLAIMER No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of ASIX. ASIX may make changes to the product specifications and descriptions in this document at any time, without notice. ASIX provides this document "as is" without warranty of any kind, either expressed or implied, including without limitation warranties of merchantability, fitness for a particular purpose, and non-infringement. Designers must not rely on the absence or characteristics of any features or registers marked "reserved", "undefined" or "NC". ASIX reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Always contact ASIX to get the latest document before starting a design of ASIX products. TRADEMARKS ASIX, the ASIX logo are registered trademarks of ASIX Electronics Corporation. All other trademarks are the property of their respective owners. 2 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Notation The following conventions are used in this document A word is 16 bits wide A double word or Dword is 32 bits wide [x] Denotes the bit position in the register. [0] bit is the least significant position Base 16 numbers are denoted with a lowercase `h' following a number or with a `0x' preceding a number Base 10 numbers are denoted with the absence of the above notation PU is pull-up on I/O pad PD is pull-down on I/O pad DS is Drive Strength in milli Amperes (mA) N/A is Not Applicable PROG is Programmable I is Input O is Output P is Passive "_N" means the Signal is active low signal RSVD - Reserved The registers follow the following notation for the read and write access Name Description RO Read Only RW Read Write RWC Read/Write 1 to clear RW1 Read or Write 1 to set WO Write Only RC Read on clear 3 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Table of Contents 1. INTRODUCTION ....................................................................................................................... 6 1.1 1.2 1.3 1.4 1.5 1.6 1.7 2. 3. ARCHITECTURAL OVERVIEW ................................................................................................. 12 PIN DESCRIPTION .................................................................................................................. 15 3.1 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4. 5. 6. GENERAL DESCRIPTION ............................................................................................................... 6 FEATURES .................................................................................................................................... 6 APPLICATIONS ............................................................................................................................. 7 BLOCK DIAGRAM ......................................................................................................................... 8 PIN CONFIGURATION................................................................................................................... 9 SUPPORT .................................................................................................................................... 11 ORDERING INFORMATION......................................................................................................... 11 PCI EXPRESS INTERFACE SIGNALS.............................................................................................. 15 USB INTERFACE SIGNALS ........................................................................................................... 16 Port 0 ...................................................................................................................................................16 Port 1 ...................................................................................................................................................16 Port 2 ...................................................................................................................................................17 Port 3 ...................................................................................................................................................17 ISA/GPIO INTERFACE SIGNALS DESCRIPTION ............................................................................ 18 I2C INTERFACE SIGNALS ............................................................................................................ 19 MISC SIGNALS ............................................................................................................................ 20 JTAG SIGNALS ............................................................................................................................ 20 INTERNAL REGULATOR SIGNALS ............................................................................................... 21 POWER SIGNALS ........................................................................................................................ 21 GROUND SIGNALS ..................................................................................................................... 22 MODE SELECTION AND FUNCTION MAPPING ...................................................................... 24 BOOTSTRAP OPTIONS ........................................................................................................... 25 REGISTER INFORMATION ...................................................................................................... 26 6.1 6.1.1 6.1.2 6.1.3 6.2 6.2.1 6.3 6.3.1 6.4 6.4.1 6.5 6.5.1 6.6 6.7 6.7.1 6.8 6.8.1 6.9 PCIE CONFIGURATION SPACE .................................................................................................... 26 PCIe Configuration Space for OHCI Controller 1 - (Function 0) ...........................................................26 PCIe Configuration Space for OHCI Controller 2, 3, and 4 - (Function 2, 4 and 6) ...............................27 PCI Configuration Space for EHCI Controller 1, 2, 3 and 4 - (Function 1, 3, 5 and 7) ...........................28 CONFIGURATION REGISTER SET ................................................................................................ 29 Description of Configuration Registers ................................................................................................31 OHCI REGISTER SET.................................................................................................................... 56 Description of OHCI Operational Registers ..........................................................................................57 EHCI REGISTER SET .................................................................................................................... 80 Description of EHCI Capability and Operational Registers ...................................................................81 OTG REGISTER SET ..................................................................................................................... 97 Description of OTG Device Registers ...................................................................................................98 GPIO REGISTER SET .................................................................................................................. 114 ISA REGISTER SET ..................................................................................................................... 117 Description of ISA Bridge Registers ....................................................................................................117 EEPROM ACCESS REGISTER SET ............................................................................................... 118 Description of I2C Registers ...............................................................................................................118 MISCELLANEOUS REGISTER SET .............................................................................................. 119 4 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 6.9.1 Description of Misc Registers ............................................................................................................120 7. CLOCKS AND RESETS ........................................................................................................... 129 8. EEPROM CONTENT LAYOUT................................................................................................ 130 9. POWER MANAGEMENT ...................................................................................................... 131 10. ELECTRICAL SPECIFICATIONS .......................................................................................... 132 10.1 10.2 10.3 10.4 ABSOLUTE MAXIMUM RATINGS.............................................................................................. 132 RECOMMENDED OPERATING CONDITIONS ............................................................................ 133 POWER CONSUMPTION .......................................................................................................... 134 PCI EXPRESS PHY ELECTRICAL SPECIFICATIONS ....................................................................... 135 10.4.1 10.4.2 10.4.3 10.4.4 10.5 Electrical Characteristics ...............................................................................................................135 Static Characteristics: Digital Pins .................................................................................................135 Static Characteristics: Analog I/O Pins ..........................................................................................136 Auxiliary Signal Timing (power up & reset) ...................................................................................138 USB PHY ELECTRICAL SPECIFICATIONS .................................................................................... 139 10.5.1 10.5.2 10.5.3 10.5.4 Electrical Characteristics ...............................................................................................................139 Static Characteristics: Digital Pins .................................................................................................140 Static Characteristics: Analog I/O Pins (DP/DM) ...........................................................................140 Dynamic Characteristics: Analog I/O Pins (DP/DM) ......................................................................142 11. MECHANICAL DIMENSIONS ............................................................................................ 145 12. ERRATA ............................................................................................................................ 146 REVISION HISTORY ...................................................................................................................... 147 5 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 1. Introduction 1.1 General description MCS9990 is a single lane multi function PCI Express to 4 dedicated USB2.0 host controllers, dedicated bandwidth per port, allowing 4 dedicated USB2.0 host controllers share 2.5Gbps wide PCI Express bus bandwidth. It supports two modes of operation - USB Host mode and OTG mode, selectable through device mode select pins. The USB Host mode supports four USB2.0 Host ports with four dedicated USB host controllers. The OTG mode supports two USB2.0 Host ports, one USB OTG port and provision to select GPIO or ISA interface. The four USB2.0 host ports are integrated with on-chip transceivers and support four dedicated Enhanced Host Controller Interface (EHCI) and four dedicated Open Host Controller Interface (OHCI). The USB OTG port is integrated with OTG PHY and supports host and device operations. The provisional ISA interface supports up to four serial ports and/or up to two parallel ports. The provisional 24 GPIO pins are programmable as an input or output. 1.2 Features PCI Express Single-lane (x1) PCI Express endpoint controller with integrated PHY Compliant with PCI Express base specification revision 1.1 Compliant with PCI Express Card specifications Supports multiple DMA transactions Supports eight PCI Express functions Supports Message TLP (error) generation Supports both legacy and MSI Interrupt mechanism 6 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller USB Four USB 2.0 Host Ports with on-chip transceivers, can handle High-speed (480Mbps), Full-speed (12Mbps) and low-speed (1.5Mbps) transactions One of the USB 2.0 Host Port can support OTG Feature Four dedicated Enhanced Host Controller Interface (EHCI) controllers Four dedicated Companion Open Host Controller Interface (OHCI) controllers Compatible with Bulk, Interrupt and Isochronous type USB devices Simultaneous operation of multiple high-performance USB devices Supports USB Power Management As a peripheral, OTG supports High Speed (HS)/ Full Speed (FS) Operation As a peripheral, OTG supports the following endpoints o One control endpoint o One interrupt IN endpoint o Two Bulk IN endpoints o Two Bulk OUT endpoints General Device Features Device parameters configurable through EEPROM 24 GPIO lines Optionally GPIO lines are configurable to support ISA Interface JTAG Port for board level diagnostics Power Supply requirement : 1.2V for Core & 3.3V for IO's On-chip Voltage regulator for 3.3V to 1.2V 1.3 Applications Extend the USB host/OTG ports on a PC or embedded systems Embedded applications for providing multiple USB ports Add-on I/O cards for serial port and parallel port through ISA interface PC/Server motherboard applications Digital Audio/Video applications NAS, Printer servers Video security monitoring applications 7 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 1.4 Block Diagram 8 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 1.5 Pin Configuration 128-Pin LQFP (14x14) GND26 +3.3VIO USB3_PWR_EN_N USB3_OVCI_N USB2_OTG_ID USB2_PWR_EN_N USB2_OVCI_N +1.2V GND25 +3.3VA GND24 USB2_OTG_VBUS USB2_IBERF GND23 GND22 USB2_DP USB2_DM +3.3VA +3.3VA +1.2V GND21 GND20 +3.3VIO LN_STAT1 LN_STAT0 USB1_PWR_EN_N USB1_OVCI_N LN_STAT2 USB0_PWR_EN_N USB0_OVCI_N +1.2V GND19 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 Top View GND1 1 96 USB1_IBREF +3.3VIN_REG 2 95 GND18 +1.2VOUT_REG 3 94 GND17 PCIE_REFCLKn 4 93 USB1_DP PCIE_REFCLKp 5 92 USB1_DM +1.2VA_AUX 6 91 +3.3VA REXT 7 90 +3.3VA GND2 8 89 USB0_IBREF PCIE_RXDn 9 88 GND16 PCIE_RXDp 10 87 GND15 GND3 11 86 USB0_DP +1.2VA 12 85 USB0_DM PCIE_TXDp 13 84 +3.3VA PCIE_TXDn 14 83 +3.3VA +1.2VA 15 82 USB0_XSCO +3.3VA_PLL 16 81 USB0_XSCI GND4 17 80 +1.2V GND5 18 79 GND14 +3.3VA_AUX 19 78 GPIO22/IOCHRDY1 +1.2V 20 77 GPIO21/A2 GND6 21 76 GPIO20/A1 PCIE_CLKREQ_N 22 75 GPIO19/A0 PCIE_WAKE_N 23 74 GPIO23/IOCHRDY2 MODE_SEL0 24 73 GPIO18/IOR_N +3.3VIO 25 72 GPIO17/IOW_N GND7 26 71 GPIO16/RESET OTG_EN_N 27 70 +3.3VIO PCIE_PERST_N 28 69 GND13 EE_SCL 29 68 GPIO15/CSD_N EE_SDA 30 67 GPIO14/CSC_N SCAN_EN 31 66 GPIO13/CSB_N TEST_EN 32 65 GPIO12/CSA_N MCS9990 56 57 58 59 60 61 62 63 64 USB3_IBREF +1.2V GND12 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N 48 +3.3VIO GND11 47 MODE_SEL1 55 46 GPIO11/INTD GND10 45 GPIO10/INTC 54 44 GPIO9/INTB USB3_DP 43 GPIO8/INTA 53 42 GPIO7/D7 USB3_DM 41 GPIO6/D6 52 40 GPIO5/D5 +3.3VA 39 GPIO4/D4 51 38 GPIO3/D3 +3.3VA 37 GPIO2/D2 50 36 GPIO1/D1 GND9 35 GPIO0/D0 49 34 MODE_SEL2 33 +1.2V GND8 XXXXXXXX YY MM 9 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Pin# Pin Name Pin# Pin Name Pin# Pin Name Pin# Pin Name 1 GND1 33 +1.2V 65 GPIO12/CSA_N 97 GND19 2 +3.3VIN_REG 34 GND8 66 GPIO13/CSB_N 98 +1.2V 3 +1.2VOUT_REG 35 GPIO0/D0 67 GPIO14/CSC_N 99 USB0_OVCI_N 4 PCIE_REFCLKn 36 GPIO1/D1 68 GPIO15/CSD_N 100 USB0_PWR_EN_N 5 PCIE_REFCLKp 37 GPIO2/D2 69 GND13 101 LN_STAT2 6 +1.2VA_AUX 38 GPIO3/D3 70 +3.3VIO 102 USB1_OVCI_N 7 REXT 39 GPIO4/D4 71 GPIO16/RESET 103 USB1_PWR_EN_N 8 GND2 40 GPIO5/D5 72 GPIO17/IOW_N 104 LN_STAT0 9 PCIE_RXDn 41 GPIO6/D6 73 GPIO18/IOR_N 105 LN_STAT1 10 PCIE_RXDp 42 GPIO7/D7 74 GPIO23/IOCHRDY2 106 +3.3VIO 11 GND3 43 GPIO8/INTA 75 GPIO19/A0 107 GND20 12 +1.2VA 44 GPIO9/INTB 76 GPIO20/A1 108 GND21 13 PCIE_TXDp 45 GPIO10/INTC 77 GPIO21/A2 109 +1.2V 14 PCIE_TXDn 46 GPIO11/INTD 78 GPIO22/IOCHRDY1 110 +3.3VA 15 +1.2VA 47 MODE_SEL1 79 GND14 111 +3.3VA 16 +3.3VA_PLL 48 +3.3VIO 80 +1.2V 112 USB2_DM 17 GND4 49 MODE_SEL2 81 USB0_XSCI 113 USB2_DP 18 GND5 50 GND9 82 USB0_XSCO 114 GND22 19 +3.3VA_AUX 51 +3.3VA 83 +3.3VA 115 GND23 20 +1.2V 52 +3.3VA 84 +3.3VA 116 USB2_IBERF 21 GND6 53 USB3_DM 85 USB0_DM 117 USB2_OTG_VBUS 22 PCIE_CLKREQ_N 54 USB3_DP 86 USB0_DP 118 GND24 23 PCIE_WAKE_N 55 GND10 87 GND15 119 +3.3VA 24 MODE_SEL0 56 GND11 88 GND16 120 GND25 25 +3.3VIO 57 USB3_IBREF 89 USB0_IBREF 121 +1.2V 26 GND7 58 +1.2V 90 +3.3VA 122 USB2_OVCI_N 27 OTG_EN_N 59 GND12 91 +3.3VA 123 USB2_PWR_EN_N 28 PCIE_PERST_N 60 JTAG_TCK 92 USB1_DM 124 USB2_OTG_ID 29 EE_SCL 61 JTAG_TDI 93 USB1_DP 125 USB3_OVCI_N 30 EE_SDA 62 JTAG_TDO 94 GND17 126 USB3_PWR_EN_N 31 SCAN_EN 63 JTAG_TMS 95 GND18 127 +3.3VIO 32 TEST_EN 64 JTAG_TRST_N 96 USB1_IBREF 128 GND26 10 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 1.6 Support Reference Schematics Evaluation Board Software Support System Design Data and Other Technical Collateral Certification : Available*** : Available*** : Available*** : Available*** : Already certified for PCIe Compliance through FPGA System *** Please contact ASIX Support Team for above items, write to support@asix.com.tw 1.7 Ordering Information Part Number Operating Temperature Package : MCS9990CV-AA : 0 to 70C : 128 LQFP, RoHS Part Number Operating Temperature Package : MCS9990IV-AA : -40 to 85C : 128 LQFP, RoHS 11 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 2. Architectural Overview MCS9990 is integrated host controller with USB 2.0 transceivers and PCIe interface in to a single chip. It consists of 4 OHCI, 4 EHCI, OTG, ISA, GPIO and I2C cores. MCS9990 compiles with USB specification revision 2.0 and OHCI Interface specification 1.0a for full-/low-speed signaling and Intel's EHCI specification 1.0 for high-speed signaling. MCS9990 contains PCIe PHY compliant with 1.1 PCIe end point controller, 4-port USB and OTG controller and a bridge that controls the transfers between the USB controller and the PCIe interface. In addition, MCS9990 supports an optional ISA interface, I2C, JTAG interface for board testability. PCIe PHY This block is a Single-lane transceivers complaint with the PCIe base specification 1.1 and contains the high speed 2.5Gbps differential transmit and receive lines. This block performs the 8b/10b encoding and decoding, etc. PCIe Endpoint Controller A PCIe endpoint controller is a device, which is similar to PCI/PCI-X based Host Bus Adapters. A root port needs to establish the linkup, initiate credits and then enumerate the endpoint before the endpoint starts any memory write/read cycles. This PCIe endpoint is fully compliant with PCIe base specification 1.1 PCIe architecture is specified in layers. It is classified into three layers namely transaction layer, data link layer, and physical layer. PCIe configuration uses standard mechanisms as defined in the PCI plug-and-play specification. The software layers will generate read and write requests that are transported by the transaction layer to the I/O devices using a packet-based, splittransaction protocol. The link layer adds sequence numbers and CRC to these packets to create a highly reliable data transfer mechanism. The basic physical layer consists of a dual-simplex channel that is implemented as a transmit pair and a receive pair. The link speed of 2.5Gbps/direction provides a 200MBps communication channel that is close to twice the classic PCI data rate. 12 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Bridge Controller The bridge implements application master and application slave functional modules which take care of transmit and receive PCIe TLPs (Transaction Layer Packets). Application master interacts with the transmit channels of the PCIe core and the USB host controller core. The data received on the USB interface are packetized by the application master interface as PCIe TLPs and supplied to the PCIe core for transmitting the data onto PCIe lines. The application slave interacts with receive as well as transmit channels of the PCIe core. It takes care of the TLPs received from the PCIe core and redirecting them to appropriate USB port. Also takes care of the completion packets onto PCIe lines using the transmit channel for the PCIe core. USB 2.0 Host Controllers MCS9990 supports up to 4 USB 2.0 host ports with dedicated EHCI and OHCI host controllers each port. Each USB host port can be operated at full USB 2.0 bandwidth. This feature significantly improves USB 2.0 performance when multiple USB 2.0 devices are used at the same time and allows multiple USB 2.0 devices to be operated at their maximum capabilities without any performance limitations. Under the USB Host mode, all 4 USB host controller ports (Port 0 ~ 3) are available. In the USB OTG mode, 1 USB OTG port (Port 2) and 2 USB host controller ports (Port 0/Port 1) are available. USB OTG Controller The OTG controller is compliant with USB Specification Rev 2.0 and OTG supplement Rev 1.0a. The host controller supports high (480 Mbps), full (12 Mbps) and low (1.5 Mbps) speed modes of operation. The device controller has two BULK IN and two BULK OUT endpoints, one Control and one Interrupt IN endpoint. The OTG controller supports both host negotiation protocol (HNP) and session request protocol (SRP). HNP is used to transfer control of a connection from the default Host (A-device) to the default peripheral (B-device). The OTG supplement defines two methods that are used by the B-device to request that the A-device to begin a session. They are called "Data-Line Pulsing" and "VBUS pulsing". These two methods comprise the Session Request Protocol (SRP). 13 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller ISA Bridge The ISA interface allows expanding the peripheral IOs, such as UARTs, parallel ports through external ISA interface components. ISA interface can be configured to support both 16 (Intel) mode and 68 (Motorola) Mode Data Bus Interface. Configured to support up to 4 UARTs Configured to supports parallel port interface ISA Interface can support following IO Configurations o 1 to 4 UARTs or 1 to 2 UARTs + 1 Parallel Port When ISA Mode is selected, MCS9990 assumes the presence of an external "ISA to 4 Serial" peripheral configuration on the ISA interface, for default mode. GPIO Interface The MCS9990 supports up to 24 General Purpose I/O (GPIO) pins to be used for system control and connection to various devices. Each GPIO pin can be programmed as an input or output and can also be used as interrupt request lines when programmed to input mode. The GPIO's can be configured as open drain signals in O/P mode. Has programmable internal pull-up capability. I2C Interface The MCS9990 supports a 2-wire I2C interface for accessing an external EEPROM that supports both read and write operations. On power-up reset the EEPROM controller checks for the EEPROM presence. If EEPROM is present, controller loads the configuration data from the EEPROM and replaces the corresponding default values. The MCS9990 I2C interface supports two 3.3V I/O signals - Serial Data (SDA) and Serial Clock (SCL) to support 16-bit addressing (as below sample Byte Write instruction figure) 24C32 or higher size I2C EEPROM with frequency rate up to 400 KHz. The I2C EEPROM is required for MCS9990 applications. Note that the I2C EEPROM is ONLY auto-loaded during MCS9990 power-up reset stage. 14 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 3. Pin Description 3.1 PCI Express Interface Signals Pin# Pin Name I/O/P Type DS PU/PD 4 PCIE_REFCLKn I LVDS -- -- 5 PCIE_REFCLKp I LVDS -- -- 7 REXT O Analog -- -- 9 PCIE_RXDn I LVDS -- -- 10 PCIE_RXDp I LVDS -- -- 13 PCIE_TXDp O LVDS -- -- 14 PCIE_TXDn O LVDS -- -- 22 PCIE_CLKREQ_N O LVTTL 4 PU 23 PCIE_WAKE_N O LVTTL 4 PU 28 PCIE_PERST_N I LVTTL -- PU Description PCIe differential clock Negative PCIe differential clock Positive Band gap external resistor, connect resistor to Ground PCIe differential data Receive Negative with integrated 50 termination resistor to ground PCIe differential data Receive Positive with integrated 50- termination resistor to ground PCIe differential data Transmit Positive PCIe differential data Transmit Negative Active low signal to enable/disable the reference clock of PCIe card. When High, Reference clock is disabled. Wakeup, Active low signal to request the host platform to return from a sleep/suspended state to service a PCI express function initiated wake event. Fundamental reset from the PCIe connector. Active Low 15 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 3.2 USB Interface Signals 3.2.1 Port 0 USB Host Mode - Port will be USB 2.0 Host Port OTG Mode - Port will be USB 2.0 Host Port Pin# Pin Name I/O/P Type DS PU/PD Description 81 USB0_XSCI I Analog -- -- Crystal Oscillator Input - 12MHz 82 USB0_XSCO O Analog -- -- Crystal Oscillator Output 85 USB0_DM I/O -- -- 86 USB0_DP I/O -- -- 89 USB0_IBREF I Analog -- -- 99 USB0_OVCI_N I LVTTL -- PU 100 USB0_PWR_EN_N O LVTTL 4 -- Analog Analog USB2.0 differential data negative USB2.0 differential data positive External reference resistor (12.1 K, 1%) connect resistor to Ground USB Over Current Indication USB power enable signal All the four USB Ports will be sharing the USB0_XSCI and USB0_XSCO. 3.2.2 Port 1 USB Host Mode - Port will be USB 2.0 Host Port OTG Mode - Port will be USB 2.0 Host Port Pin# Pin Name I/O/P Type Analog DS PU/PD -- -- -- -- 92 USB1_DM I/O 93 USB1_DP I/O 96 USB1_IBREF I Analog -- -- 102 USB1_OVCI_N I LVTTL -- PU 103 USB1_PWR_EN_N O LVTTL 4 -- Analog Description USB2.0 differential data negative USB2.0 differential data positive External reference resistor (12.1K, 1%) connect resistor to Ground USB Over Current Indication USB power enable signal 16 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 3.2.3 Port 2 USB Host Mode - Port will be USB 2.0 Host Port OTG Mode - Port will be USB OTG Port Pin# Pin Name I/O/P Type Analog DS PU/PD -- -- -- -- 112 USB2_DM I/O 113 USB2_DP I/O 116 USB2_IBREF I Analog -- -- 122 USB2_OVCI_N I LVTTL -- PU 123 USB2_PWR_EN_N O LVTTL 4 -- Analog 124 USB2_OTG_ID I LVTTL -- PROG 117 USB2_OTG_VBUS I LVTTL -- -- DS PU/PD -- -- -- -- Description USB2.0 differential data negative USB2.0 differential data positive External reference resistor (12.1K, 1%) connect resistor to Ground USB Over Current Indication USB power enable signal Identification pin for OTG ports which differentiates A-Device or B-Device Voltage detection circuit input 3.2.4 Port 3 USB Host Mode - Port will be USB 2.0 Host Port OTG Mode - Port will not be available Pin# Pin Name I/O/P Type Analog 53 USB3_DM I/O 54 USB3_DP I/O 57 USB3_IBREF I Analog -- -- 125 USB3_OVCI_N I LVTTL -- PU 126 USB3_PWR_EN_N O LVTTL 4 -- Analog Description USB2.0 differential data negative USB2.0 differential data positive External reference resistor (12.1K, 1%) connect resistor to Ground USB Over Current Indication USB Power Enable Signal 17 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 3.3 ISA/GPIO Interface Signals Description GPIO and ISA pins are multiplexed. These can be used with combination of OTG and 2 USB Host ports. ISA pins are available in 2USB+OTG+ISA Mode and GPIO pins in 2USB+OTG+GPIO Mode. Pin# 35 36 37 38 39 40 41 42 Pin Name D0 D1 D2 D3 D4 D5 D6 D7 I/O/P I/O I/O I/O I/O I/O I/O I/O I/O Type LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL DS 4 4 4 4 4 4 4 4 PU/PD PD PD PD PD PD PD PD PD 43 INTA I LVTTL 4 PU/PD 44 INTB I LVTTL 4 PU/PD 45 INTC I LVTTL 4 PU/PD 46 INTD I LVTTL 4 PU/PD 65 CSA_N O LVTTL 4 -- 66 CSB_N O LVTTL 4 -- 67 CSC_N O LVTTL 4 -- 68 CSD_N O LVTTL 4 -- 71 RESET O LVTTL 4 -- 72 IOW_N O LVTTL 4 -- 73 IOR_N O LVTTL 4 -- 75 76 77 A0 A1 A2 O O O LVTTL LVTTL LVTTL 4 4 4 ---- 78 IOCHRDY1 I LVTTL 4 PU 74 IOCHRDY2 I LVTTL 4 PU Description Data bus signal at ISA interface Data bus signal at ISA interface Data bus signal at ISA interface Data bus signal at ISA interface Data bus signal at ISA interface Data bus signal at ISA interface Data bus signal at ISA interface Data bus signal at ISA interface Interrupt signal coming from Port-A of external peripheral Interrupt signal coming from Port-B of external peripheral Interrupt signal coming from Port-C of external peripheral Interrupt signal coming from Port-D of external peripheral Chip Select line for Port-A of external peripheral Chip Select line for Port-B of external peripheral Chip Select line for Port-C of external peripheral Chip Select line for Port-D of external peripheral Reset signal for external peripheral at ISA interface Write pulse for external peripheral at ISA interface Read pulse for external peripheral at ISA interface External peripheral Address line External peripheral Address line External peripheral Address line IOCHRDY coming from Port-A of external peripheral IOCHRDY coming from Port-C of external peripheral 18 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Note : In Intel mode (default Mode) pads are PD and in Motorola mode pads are PU. GPIO Interface Signals Available in 2USB+OTG+GPIO Mode Only Pin# 35 36 37 38 39 40 41 42 43 44 45 46 65 66 67 68 71 72 73 75 76 77 78 74 Pin Name GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 I/O/P I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Type LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL DS 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 PU/PD PROG PROG PROG PROG PROG PROG PROG PROG PROG PROG PROG PROG PROG PROG PROG PROG PROG PROG PROG PROG PROG PROG PROG PROG Description General Purpose I/O Pins General Purpose I/O Pins General Purpose I/O Pins General Purpose I/O Pins General Purpose I/O Pins General Purpose I/O Pins General Purpose I/O Pins General Purpose I/O Pins General Purpose I/O Pins General Purpose I/O Pins General Purpose I/O Pins General Purpose I/O Pins General Purpose I/O Pins General Purpose I/O Pins General Purpose I/O Pins General Purpose I/O Pins General Purpose I/O Pins General Purpose I/O Pins General Purpose I/O Pins General Purpose I/O Pins General Purpose I/O Pins General Purpose I/O Pins General Purpose I/O Pins General Purpose I/O Pins Note: 1. All the GPIO pins can be either PU or open and the PU's are Programmable. 2. All the GPIO/ISA pins should be made as NC's in the other device modes. 3.4 I2C Interface Signals Pin# Pin Name I/O/P Type DS PU/PD Description 29 EE_SCL I/O LVTTL 4 PU 2-Wire EEPROM Clock 30 EE_SDA I/O LVTTL 4 PU 2-Wire EEPROM Data In/Out 19 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 3.5 Pin# Misc Signals 27 OTG_EN_N I LVTTL -- PU 24 MODE_SEL0 I LVTTL -- PD Description Device Mode Select 1 4 USB Host Controllers mode 0 2 USB Host Controllers, 1 OTG and ISA/GPIO mode Mode select line 47 MODE_SEL1 I LVTTL -- PD Mode select line 49 MODE_SEL2 I LVTTL -- PD Mode select line 31 SCAN_EN I LVTTL -- PD Scan Enable signal 32 TEST_EN I LVTTL -- PD 104 LN_STAT0 I/O LVTTL 4 PD 105 LN_STAT1 I/O LVTTL 4 PD 101 LN_STAT2 I/O LVTTL 4 PD Test Enable signal Active high status signal provides information on link up of PCIe interface. Also a Bootstrap Pin Active high status signal provides information on configuration of PCIe functions on loading the default / EEPROM contents. Also a bootstrap Pin Bootstrap pin. (Please refer to "Bootstrap Options" section) 3.6 Pin Name I/O/P Type DS PU/PD JTAG Signals JTAG interface can be used for board testability Pin# Pin Name I/O/P Type DS PU/PD Description 60 JTAG_TCK I LVTTL -- -- JTAG chain clock 61 JTAG_TDI I LVTTL -- PU JTAG chain input 62 JTAG_TDO O LVTTL 4 -- JTAG chain output 63 JTAG_TMS I LVTTL -- PU JTAG chain Test mode select 64 JTAG_TRST_N I LVTTL -- PU Debug reset signal 20 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 3.7 Pin# Internal Regulator Signals Pin Name I/O/P Type DS PU/PD Description 2 +3.3VIN_REG I Power -- -- Power supply voltage for Voltage Regulator PHY 3 +1.2VOUT_REG O Power -- -- 1.2V output voltage I/O/P Type DS PU/PD 3.8 Pin# Power Signals Pin Name Description 1.2V Analog auxiliary power for PCIe PHY 3.3V Analog auxiliary power for PCIe PHY 3.3V Analog Power Supply for internal PLL used in PCIe PHY 6 +1.2VA_AUX P Power -- -- 19 +3.3VA_AUX P Power -- -- 16 +3.3VA_PLL P Power -- -- 20 +1.2V P Power -- -- 1.2V core power supply 33 +1.2V P Power -- -- 1.2V core power supply 58 +1.2V P Power -- -- 1.2V core power supply 80 +1.2V P Power -- -- 1.2V core power supply 98 +1.2V P Power -- -- 1.2V core power supply 109 +1.2V P Power -- -- 1.2V core power supply 121 +1.2V P Power -- -- 1.2V core power supply 12 +1.2VA P Power -- -- 1.2V Analog/IO power supply 15 +1.2VA P Power -- -- 1.2V Analog/IO power supply 25 +3.3VIO P Power -- -- 3.3V Digital IO Power Supply 48 +3.3VIO P Power -- -- 3.3V Digital IO Power Supply 70 +3.3VIO P Power -- -- 3.3V Digital IO Power Supply 106 +3.3VIO P Power -- -- 3.3V Digital IO Power Supply 21 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Pin# Pin Name I/O/P Type DS PU/PD 127 +3.3VIO P Power -- -- 51 +3.3VA P Power -- -- 52 +3.3VA P Power -- -- 83 +3.3VA P Power -- -- 84 +3.3VA P Power -- -- 90 +3.3VA P Power -- -- 91 +3.3VA P Power -- -- 110 +3.3VA P Power -- -- 111 +3.3VA P Power -- -- 119 +3.3VA P Power -- -- 3.9 Description 3.3V Digital IO Power Supply 3.3V Analog supply for USB3 PHY 3.3V Analog supply for USB3 PHY 3.3V Analog supply for USB0 PHY 3.3V Analog supply for USB0 PHY 3.3V Analog supply for USB1 PHY 3.3V Analog supply for USB1 PHY 3.3V Analog supply for USB2 PHY 3.3V Analog supply for USB2 PHY 3.3V Analog supply for USB OTG PHY Ground Signals Pin# Pin Name I/O/P Type DS PU/PD Description 1 GND1 P Ground -- -- Ground 8 GND2 P Ground -- -- Ground 11 GND3 P Ground -- -- Ground 17 GND4 P Ground -- -- Ground 18 GND5 P Ground -- -- Ground 21 GND6 P Ground -- -- Ground 26 GND7 P Ground -- -- Ground 34 GND8 P Ground -- -- Ground 50 GND9 P Ground -- -- Ground 22 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. voltage voltage voltage voltage voltage voltage voltage voltage voltage MCS9990 PCIe to 4-Port USB 2.0 Host Controller Pin# Pin Name I/O/P Type DS PU/PD Description 55 GND10 P Ground -- -- Ground 56 GND11 P Ground -- -- Ground 59 GND12 P Ground -- -- Ground 69 GND13 P Ground -- -- Ground 79 GND14 P Ground -- -- Ground 87 GND15 P Ground -- -- Ground 88 GND16 P Ground -- -- Ground 94 GND17 P Ground -- -- Ground 95 GND18 P Ground -- -- Ground 97 GND19 P Ground -- -- Ground 107 GND20 P Ground -- -- Ground 108 GND21 P Ground -- -- Ground 114 GND22 P Ground -- -- Ground 115 GND23 P Ground -- -- Ground 118 GND24 P Ground -- -- Ground 120 GND25 P Ground -- -- Ground 128 GND26 P Ground -- -- Ground Note : All ground signal can be shorted at system level, refer to reference schematics for additional details. 23 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 4. Mode Selection and Function Mapping Mode Selection MCS9990 supports following four functional modes, selectable through device mode select pins at board level. The I2C EEPROM is also required to be used in these modes. Mode Selection TEST_EN MODE_SEL2 MODE_SEL1 MODE_SEL0 OTG_EN_N 4 USB Host 0 0 0 0 1 2 USB Host + OTG 0 0 0 1 0 2 USB Host + OTG + ISA 0 0 1 0 0 2 USB Host + OTG + GPIO 0 0 1 1 0 Function Mapping MCS9990 supports four functional modes. All these functional modes have different peripheral mapping with respect to the functions configured by PCIe. In all there are eight functions in all the four modes. Following table shows different function mapping in different functional modes. Function 4 Host USB 2 USB + OTG 2 USB + OTG + ISA 2 USB + OTG + GPIO Function 0 OHCI for CH0 OHCI for CH0 OHCI for CH0 OHCI for CH0 Function 1 EHCI for CH0 EHCI for CH0 EHCI for CH0 EHCI for CH0 Function 2 OHCI for CH1 OHCI for CH1 OHCI for CH1 OHCI for CH1 Function 3 EHCI for CH1 EHCI for CH1 EHCI for CH1 EHCI for CH1 Function 4 OHCI for CH2 OHCI for CH2 OHCI for CH2 OHCI for CH2 Function 5 EHCI for CH2 EHCI for CH2 EHCI for CH2 EHCI for CH2 Function 6 OHCI for CH3 OTG for CH2 OTG for CH2 OTG for CH2 Function 7 EHCI for CH3 NA ISA GPIO 24 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 5. Bootstrap Options In MCS9990, six bootstrap options are present. Pin Name Bootstrap Internal PU/PD Default External PU/PD LN_STAT0 PCIEXP_ERR_MSK PD PU LN_STAT1 MAXRD_128BYTES PD Open LN_STAT2 AUX_POWER PD PU GPIO19 ASPM_CNTRL PU PD GPIO20 ADV_ERROR_REPORT PU Open GPIO21 WAKE_HIB_EN PU Open Description To mask PCIe error bits. By default logic `Low' is present to mask error reporting To set maximum read request size from EP to be 128 bytes by passing high logic on the line. By default logic `Low' is present For auxiliary power detection, connected to `Vaux' detect circuit at board level. By default logic `Low' is present To Provide ASPM support controllability. By default logic `High' is present to enable ASPM To provide Advance Error Report support controllability. By default logic `High' is present to enable the feature. To provide wake from D3 Cold (Hibernate) state through device connected under USB host. By default logic `High' is present to disable this feature. To enable the feature provide weak pull down at board level. 25 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 6. Register Information 6.1 PCIe Configuration Space 6.1.1 PCIe Configuration Space for OHCI Controller 1 - (Function 0) 31 24 23 Device ID Status Register 16 15 8 7 Vendor ID Command Register Class Code Subclass Programming Interface Revision ID BIST Header Type Latency Timer Cache Line Size BAR_OHCI Register Base Address Register 1 Base Address Register 2 Base Address Register 3 Base Address Register 4 Base Address Register 5 Card Bus CIS Subsystem Device ID Subsystem Vendor ID Expansion ROM Reserved Reserved Capabilities Pointer Reserved Max_Lat Min_Gnt Interrupt Pin Interrupt Line 0 Reserved MSI Control Next Item Pointer Message Address Message Upper Address Reserved MSI Capability ID MSI Data MSI Mask Bits (Optional) MSI Pending Bits (Optional) 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 4Ch 50h 54h 58h 5Ch 60h 64h 68h.. Reserved 74h PMC Next Item Pointer PMI Capability ID Data PMCSR_BSE PM Control/Status Register (PMCSR) PCI Express Capabilities Register Next Item Pointer PCIe Capability ID Device Capabilities Device Status Device Control Link Capabilities Link Status Link Control 78h 7Ch 80h 84h 88h 8Ch 90h 94h.. Reserved FCh Next Capability Offset/Version Virtual Channel Capability ID Port VC Capability Register 1 Port VC Capability Register 2 Port VC Status Register Port VC Control Register VC Resource Capability Register VC Resource Control Register VC Resource Status Register RsvdP 100h 104h 108h 10Ch 110h 114h 118h 11Ch.. Reserved 7FCh Next Capability Offset/Version Advanced Error Reporting Capability ID Uncorrectable Error Status Register Uncorrectable Error Mask Register Uncorrectable Error Severity Register Correctable Error Status Register Correctable Error Mask Register Advanced Error Capabilities and Control Register Header Log Register 1 Header Log Register 2 Header Log Register 3 Header Log Register 4 26 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. 800h 804h 808h 80Ch 810h 814h 818h 81Ch 820h 824h 828h MCS9990 PCIe to 4-Port USB 2.0 Host Controller 6.1.2 PCIe Configuration Space for OHCI Controller 2, 3, and 4 - (Function 2, 4 and 6) 31 24 23 16 15 8 7 0 Device ID Vendor ID Status Register Command Register Class Code Subclass Programming Interface Revision ID BIST Header Type Latency Timer Cache Line Size BAR_OHCI Register Base Address Register 1 Base Address Register 2 Base Address Register 3 Base Address Register 4 Base Address Register 5 Card Bus CIS Subsystem Device ID Subsystem Vendor ID Expansion ROM Reserved Reserved Capabilities Pointer Reserved Max_Lat Min_Gnt Interrupt Pin Interrupt Line Reserved MSI Control Reserved Next Item Pointer MSI Capability ID Message Address Message Upper Address MSI Data MSI Mask Bits (Optional) MSI Pending Bits (Optional) Reserved PMC Next Item Pointer PMI Capability ID Data PMCSR_BSE PM Control/Status Register (PMCSR) PCI Express Capabilities Register Next Item Pointer PCIe Capability ID Device Capabilities Device Status Device Control Link Capabilities Link Status Link Control 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 4Ch 50h 54h 58h 5Ch 60h 64h 68h.. 74h 78h 7Ch 80h 84h 88h 8Ch 90h 94h.. Reserved FCh 7FCh Next Capability Offset/Version Advanced Error Reporting Capability ID Uncorrectable Error Status Register Uncorrectable Error Mask Register Uncorrectable Error Severity Register Correctable Error Status Register Correctable Error Mask Register Advanced Error Capabilities and Control Register Header Log Register 1 Header Log Register 2 Header Log Register 3 Header Log Register 4 27 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. 100h 104h 108h 10Ch 110h 114h 118h 11Ch 120h 124h 128h MCS9990 PCIe to 4-Port USB 2.0 Host Controller 6.1.3 PCI Configuration Space for EHCI Controller 1, 2, 3 and 4 - (Function 1, 3, 5 and 7) 31 24 23 Device ID Status Register 16 15 8 7 0 Vendor ID Command Register Class Code Subclass Programming Interface Revision ID BIST Header Type Latency Timer Cache Line Size USBBASE Base Address Register 1 Base Address Register 2 Base Address Register 3 Base Address Register 4 Base Address Register 5 Card Bus CIS Subsystem Device ID Subsystem Vendor ID Expansion ROM Reserved Reserved Capabilities Pointer Reserved Max_Lat Min_Gnt Interrupt Pin Interrupt Line Reserved MSI Control Next Item Pointer Message Address Message Upper Address Reserved PORTWAKECAP MSI Capability ID MSI Data FLADJ SBRN Reserved PMC Next Item Pointer PMI Capability ID Data PMCSR_BSE PM Control/Status Register (PMCSR) PCI Express Capabilities Register Next Item Pointer PCIe Capability ID Device Capabilities Device Status Device Control Link Capabilities Link Status Link Control Reserved Next Capability Offset/Version Advanced Error Reporting Capability ID Uncorrectable Error Status Register Uncorrectable Error Mask Register Uncorrectable Error Severity Register Correctable Error Status Register Correctable Error Mask Register Advanced Error Capabilities and Control Register Header Log Register 1 Header Log Register 2 Header Log Register 3 Header Log Register 4 28 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 4Ch 50h 54h 58h 5Ch 60h 64h.. 74h 78h 7Ch 80h 84h 88h 8Ch 90h 94h.. FCh 100h 104h 108h 10Ch 110h 114h 118h 11Ch 120h 124h 128h MCS9990 PCIe to 4-Port USB 2.0 Host Controller 6.2 Configuration Register Set Following are the configuration register values that are loaded into configuration space to setup the hardware resources, device characteristics, etc. Function Function 0 Function 1 Function 2 Function 3 Function 4 Offset Register Name Access 00h F0_DevIDVenID R 09h F0_Classcode R 10h F0_BAR0 2Ch F0_SubsysDIDVID R 3Dh F0_IntPinMap R 78h F0_DevCapPwrMgtCap R 00h F1_DevIDVenID R 09h F1_Classcode R 10h F1_BAR0 2Ch F1_SubsysDIDVID R 3Dh F1_IntPinMap R 78h F1_DevCapPwrMgtCap R 00h F2_DevIDVenID R 09h F2_Classcode R 10h F2_BAR0 2Ch F2_SubsysDIDVID R 3Dh F2_IntPinMap R 78h F2_DevCapPwrMgtCap R 00h F3_DevIDVenID R 09h F3_Classcode R 10h F3_BAR0 2Ch F3_SubsysDIDVID R 3Dh F3_IntPinMap R 78h F3_DevCapPwrMgtCap R 00h F4_DevIDVenID R RW RW RW RW 29 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Function Function 5 Function 6 Function 7 Offset Register Name Access 09h F4_Classcode R 10h F4_BAR0 2Ch F4_SubsysDIDVID R 3Dh F4_IntPinMap R 78h F4_DevCapPwrMgtCap R 00h F5_DevIDVenID R 09h F5_Classcode R 10h F5_BAR0 2Ch F5_SubsysDIDVID R 3Dh F5_IntPinMap R 78h F5_DevCapPwrMgtCap R 00h F6_DevIDVenID R 09h F6_Classcode R 10h F6_BAR0 2Ch F6_SubsysDIDVID R 3Dh F6_IntPinMap R 78h F6_DevCapPwrMgtCap R 00h F7_DevIDVenID R 09h F7_Classcode R 10h 14h F7_BAR0 F7_BAR1 RW RW 18h F7_BAR2 RW 1Ch F7_BAR3 RW 20h F7_BAR4 RW 2Ch F7_SubsysDIDVID R 3Dh F7_IntPinMap R 78h F7_DevCapPwrMgtCap R RW RW RW 30 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 6.2.1 Description of Configuration Registers F0_DevIDVenID Bit Name Default Description Opmode 31:16 DevID 15:0 VenID Value 4USB 16'h9990 2USB+OTG 16'h9990 2USB+OTG+ISA 16'h9990 2USB+OTG+GPIO 16'h9990 Opmode Value 4USB 16'h9710 2USB+OTG 16'h9710 2USB+OTG+ISA 16'h9710 2USB+OTG+GPIO 16'h9710 Device ID field for Function-0 Vendor ID field for Function-0 F0_Classcode Bit Name Default Opmode 31:24 23:16 15:8 7:0 ClassCode SubClassCode ProgIntfInfo Rsvd Description Value 4USB 8'h0C 2USB+OTG 8'h0C 2USB+OTG+ISA 8'h0C 2USB+OTG+GPIO 8'h0C Opmode Value 4USB 8'h03 2USB+OTG 8'h03 2USB+OTG+ISA 8'h03 2USB+OTG+GPIO 8'h03 Opmode Value 4USB 8'h10 2USB+OTG 8'h10 2USB+OTG+ISA 8'h10 2USB+OTG+GPIO 8'h10 8'h00 Class code field for Function-0 Sub Class Function-0 Code field for Programming Interface Information field for Function-0 Reserved 31 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller F0_BAR0 Bit Name Default Opmode 31:0 BAR0 Description Value 4USB 32'hFFFF_F000 2USB+OTG 32'hFFFF_F000 2USB+OTG+ISA 32'hFFFF_F000 2USB+OTG+GPIO 32'hFFFF_F000 Base Address Register-0 field for Function-0 F0_SubsysDIDVID Bit Name Default Opmode 31:16 15:0 SubsysDID SubsysVID Description Value 4USB 16'h4000 2USB+OTG 16'h4000 2USB+OTG+ISA 16'h4000 2USB+OTG+GPIO 16'h4000 Opmode Value 4USB 16'hA000 2USB+OTG 16'hA000 2USB+OTG+ISA 16'hA000 2USB+OTG+GPIO 16'hA000 Sub System Device ID field for Function-0 Sub System Vendor ID field for Function-0 F0_IntPinMap \ Bit Name Default Description 31:3 Rsvd 29'd0 Reserved 2:0 IntPinMap 3'b001 Interrupt pin [2:0] field for Function-0 32 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller F0_DevCapPwrMgtCap Bit Default Description 31 1'b0 30:28 3'b000 27:25 3'b111 24:22 3'b111 Reserved [14:12] bit field of Device Capability Register for Function-0 Endpoint L1 Acceptable Latency = [11:9] bit field of Device Capability Register for Function-0 Endpoint L0s Acceptable Latency = [8:6] bit field of Device Capability Register for Function-0 Extended Tag field supported = [5] bit field of Device Capability Register for Function-0 DLL Link active reporting Capable = [20] field of Link Capability Register for Function-0 Surprise down error reporting Capable = [19] field of Link Capability Register for Function-0 Max Payload Size Supported = [2:0] bit field of Device Capability Register for Function-0 Reserved D3 cold Support = [31] bit field of Power Management Capability Register for Function-0 D3 hot PME Support = [30] bit field of Power Management Capability Register for Function-0 D2 PME Support = [29] bit field of Power Management Capability Register for Function-0 D1 PME Support = [28] bit field of Power Management Capability Register for Function-0 D0 PME Support = [27] bit field of Power Management Capability Register for Function-0 D2 Support = [26] bit field of Power Management Capability Register for Function-0 D1 Support = [25] bit field of Power Management Capability Register for Function-0 AUX current = [24:22] bit field of Power Management Capability Register for Function-0 No Soft Reset = [3] bit field of Power Management Status/Control Register for Function-0 21 Name DevCap 1'b0 20 1'b0 19 1'b0 18:16 3'b001 15:11 Rsvd 5'd0 10 1'b0 9 1'b0 8 1'b0 7 1'b0 6 PwrMgtCap 1'b0 5 1'b0 4 1'b0 3:1 3'b111 0 1'b1 33 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller F1_DevIDVenID Bit Name Default Description Opmode 31:16 DevID Value 4USB 16'h9990 2USB+OTG 16'h9990 2USB+OTG+ISA 16'h9990 2USB+OTG+GPIO 16'h9990 Opmode 15:0 VenID Device ID field for Function-1 Value 4USB 16'h9710 2USB+OTG 16'h9710 2USB+OTG+ISA 16'h9710 2USB+OTG+GPIO 16'h9710 Vendor ID field for Function-1 F1_Classcode Bit Name Default Opmode 31:24 23:16 15:8 7:0 Classcode SubClassCode ProgIntfInfo Rsvd Description Value 4USB 8'h0C 2USB+OTG 8'h0C 2USB+OTG+ISA 8'h0C 2USB+OTG+GPIO 8'h0C Opmode Value 4USB 8'h03 2USB+OTG 8'h03 2USB+OTG+ISA 8'h03 2USB+OTG+GPIO 8'h03 Opmode Value 4USB 8'h20 2USB+OTG 8'h20 2USB+OTG+ISA 8'h20 2USB+OTG+GPIO 8'h20 8'h00 Class code field for Function-1 Sub Class Code field for Function-1 Programming Interface Information field for Function-1 Reserved 34 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller F1_BAR0 Bit Name Default Description Opmode 31:0 BAR0 Value 4USB 32'hFFFF_FF00 2USB+OTG 32'hFFFF_FF00 2USB+OTG+ISA 32'hFFFF_FF00 2USB+OTG+GPIO 32'hFFFF_FF00 Base Address Register-0 field for Function-1 F1_SubsysDIDVID Bit Name Default Description Opmode 31:16 15:0 SubsysDID SubsysVID Value 4USB 16'h4000 2USB+OTG 16'h4000 2USB+OTG+ISA 16'h4000 2USB+OTG+GPIO 16'h4000 Opmode Value 4USB 16'hA000 2USB+OTG 16'hA000 2USB+OTG+ISA 16'hA000 2USB+OTG+GPIO 16'hA000 Sub System Device ID field for Function-1 Sub System Vendor ID field for Function-1 F1_IntPinMap Bit Name Default Description 31:3 Rsvd 29'd0 Reserved 2:0 IntPinMap 3'b001 Interrupt pin [2:0] field for Function-1 35 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller F1_DevCapPwrMgtCap Bit Default Description 31 1'b0 30:28 3'b000 27:25 3'b111 24:22 3'b111 Reserved [14:12] bit field of Device Capability Register for Function-1 Endpoint L1 Acceptable Latency = [11:9] bit field of Device Capability Register for Function-1 Endpoint L0s Acceptable Latency = [8:6] bit field of Device Capability Register for Function-1 Extended Tag field supported = [5] bit field of Device Capability Register for Function-1 DLL Link active reporting Capable = [20] field of Link Capability Register for Function-1 Surprise down error reporting Capable = [19] field of Link Capability Register for Function-1 Max Payload Size Supported = [2:0] bit field of Device Capability Register for Function-1 Reserved D3 cold Support = [31] bit field of Power Management Capability Register for Function-1 D3 hot PME Support = [30] bit field of Power Management Capability Register for Function-1 D2 PME Support = [29] bit field of Power Management Capability Register for Function-1 D1 PME Support = [28] bit field of Power Management Capability Register for Function-1 D0 PME Support = [27] bit field of Power Management Capability Register for Function-1 D2 Support = [26] bit field of Power Management Capability Register for Function-1 D1 Support = [25] bit field of Power Management Capability Register for Function-1 AUX current = [24:22] bit field of Power Management Capability Register for Function-1 No Soft Reset = [3] bit field of Power Management Status/Control Register for Function-1 21 Name DevCap 1'b0 20 1'b0 19 1'b0 18:16 3'b001 15:11 Rsvd 5'd0 10 1'b0 9 1'b0 8 1'b0 7 1'b0 6 PwrMgtCap 1'b0 5 1'b0 4 1'b0 3:1 3'b111 0 1'b1 36 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller F2_DevIDVenID Bit Name Default Description Opmode 31:16 15:0 DevID VenID Value 4USB 16'h9990 2USB+OTG 16'h9990 2USB+OTG+ISA 16'h9990 2USB+OTG+GPIO 16'h9990 Opmode Value 4USB 16'h9710 2USB+OTG 16'h9710 2USB+OTG+ISA 16'h9710 2USB+OTG+GPIO 16'h9710 Device ID field for Function-2 Vendor ID field for Function-2 F2_Classcode Bit Name Default Opmode 31:24 23:16 15:8 7:0 ClassCode SubClassCode ProgIntfInfo Rsvd Description Value 4USB 8'h0C 2USB+OTG 8'h0C 2USB+OTG+ISA 8'h0C 2USB+OTG+GPIO 8'h0C Opmode Value 4USB 8'h03 2USB+OTG 8'h03 2USB+OTG+ISA 8'h03 2USB+OTG+GPIO 8'h03 Opmode Value 4USB 8'h10 2USB+OTG 8'h10 2USB+OTG+ISA 8'h10 2USB+OTG+GPIO 8'h10 8'h00 Class code field for Function-2 Sub Class Code field for Function-2 Programming Interface Information field for Function-2 Reserved 37 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller F2_BAR0 Bit Name Default Description Opmode 31:0 BAR0 Value 4USB 32'hFFFF_F000 2USB+OTG 32'hFFFF_F000 2USB+OTG+ISA 32'hFFFF_F000 2USB+OTG+GPIO 32'hFFFF_F000 Base Address Register-0 field for Function-2 F2_SubsysDIDVID Bit Name Default Description Opmode 31:16 15:0 SubsysDID SubsysVID Value 4USB 16'h4000 2USB+OTG 16'h4000 2USB+OTG+ISA 16'h4000 2USB+OTG+GPIO 16'h4000 Opmode Value 4USB 16'hA000 2USB+OTG 16'hA000 2USB+OTG+ISA 16'hA000 2USB+OTG+GPIO 16'hA000 Sub System Device ID field for Function-2 Sub System Vendor ID field for Function-2 F2_IntPinMap Bit Name Default Description 31:3 Rsvd 29'd0 Reserved 2:0 IntPinMap 3'b010 Interrupt pin [2:0] field for Function-2 38 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller F2_DevCapPwrMgtCap Bit Default Description 31 1'b0 30:28 3'b000 27:25 3'b111 24:22 3'b111 Reserved [14:12] bit field of Device Capability Register for Function-2 Endpoint L1 Acceptable Latency = [11:9] bit field of Device Capability Register for Function-2 Endpoint L0s Acceptable Latency = [8:6] bit field of Device Capability Register for Function-2 Extended Tag field supported = [5] bit field of Device Capability Register for Function-2 DLL Link active reporting Capable = [20] field of Link Capability Register for Function-2 Surprise down error reporting Capable = [19] field of Link Capability Register for Function-2 Max Payload Size Supported = [2:0] bit field of Device Capability Register for Function-2 Reserved D3 cold Support = [31] bit field of Power Management Capability Register for Function-2 D3 hot PME Support = [30] bit field of Power Management Capability Register for Function-2 D2 PME Support = [29] bit field of Power Management Capability Register for Function-2 D1 PME Support = [28] bit field of Power Management Capability Register for Function-2 D0 PME Support = [27] bit field of Power Management Capability Register for Function-2 D2 Support = [26] bit field of Power Management Capability Register for Function-2 D1 Support = [25] bit field of Power Management Capability Register for Function-2 AUX current = [24:22] bit field of Power Management Capability Register for Function-2 No Soft Reset = [3] bit field of Power Management Status/Control Register for Function-2 21 Name DevCap 1'b0 20 1'b0 19 1'b0 18:16 3'b001 15:11 Rsvd 5'd0 10 1'b0 9 1'b0 8 1'b0 7 1'b0 6 PwrMgtCap 1'b0 5 1'b0 4 1'b0 3:1 3'b111 0 1'b1 39 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller F3_DevIDVenID Bit Name Default Description Opmode 31:16 15:0 DevID VenID Value 4USB 16'h9990 2USB+OTG 16'h9990 2USB+OTG+ISA 16'h9990 2USB+OTG+GPIO 16'h9990 Opmode Value 4USB 16'h9710 2USB+OTG 16'h9710 2USB+OTG+ISA 16'h9710 2USB+OTG+GPIO 16'h9710 Device ID field for Function-3 Vendor ID field for Function-3 F3_Classcode Bit Name Default Opmode 31:24 23:16 15:8 7:0 ClassCode SubClassCode ProgIntfInfo Rsvd Description Value 4USB 8'h0C 2USB+OTG 8'h0C 2USB+OTG+ISA 8'h0C 2USB+OTG+GPIO 8'h0C Opmode Value 4USB 8'h03 2USB+OTG 8'h03 2USB+OTG+ISA 8'h03 2USB+OTG+GPIO 8'h03 Opmode Value 4USB 8'h20 2USB+OTG 8'h20 2USB+OTG+ISA 8'h20 2USB+OTG+GPIO 8'h20 8'h00 Class code field for Function-3 Sub Class Code field for Function-3 Programming Interface Information field for Function-3 Reserved 40 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller F3_BAR0 Bit Name Default Description Opmode 31:0 BAR0 Value 4USB 32'hFFFF_FF00 2USB+OTG 32'hFFFF_FF00 2USB+OTG+ISA 32'hFFFF_FF00 2USB+OTG+GPIO 32'hFFFF_FF00 Base Address Register-0 field for Function-3 F3_SubsysDIDVID Bit Name Default Description Opmode 31:16 15:0 SubsysDID SubsysVID Value 4USB 16'h4000 2USB+OTG 16'h4000 2USB+OTG+ISA 16'h4000 2USB+OTG+GPIO 16'h4000 Opmode Value 4USB 16'hA000 2USB+OTG 16'hA000 2USB+OTG+ISA 16'hA000 2USB+OTG+GPIO 16'hA000 Sub System Device ID field for Function-3 Sub System Vendor ID field for Function-3 F3_IntPinMap Bit Name Default Description 31:3 Rsvd 29'd0 Reserved 2:0 IntPinMap 3'b010 Interrupt pin [2:0] field for Function-3 41 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller F3_DevCapPwrMgtCap Bit Default Description 31 1'b0 30:28 3'b000 27:25 3'b111 24:22 3'b111 Reserved [14:12] bit field of Device Capability Register for Function-3 Endpoint L1 Acceptable Latency = [11:9] bit field of Device Capability Register for Function-3 Endpoint L0s Acceptable Latency = [8:6] bit field of Device Capability Register for Function-3 Extended Tag field supported = [5] bit field of Device Capability Register for Function-3 DLL Link active reporting Capable = [20] field of Link Capability Register for Function-3 Surprise down error reporting Capable = [19] field of Link Capability Register for Function-3 Max Payload Size Supported = [2:0] bit field of Device Capability Register for Function-3 Reserved D3 cold Support = [31] bit field of Power Management Capability Register for Function-3 D3 hot PME Support = [30] bit field of Power Management Capability Register for Function-3 D2 PME Support = [29] bit field of Power Management Capability Register for Function-3 D1 PME Support = [28] bit field of Power Management Capability Register for Function-3 D0 PME Support = [27] bit field of Power Management Capability Register for Function-3 D2 Support = [26] bit field of Power Management Capability Register for Function-3 D1 Support = [25] bit field of Power Management Capability Register for Function-3 AUX current = [24:22] bit field of Power Management Capability Register for Function-3 No Soft Reset = [3] bit field of Power Management Status/Control Register for Function-3 21 Name DevCap 1'b0 20 1'b0 19 1'b0 18:16 3'b001 15:11 Rsvd 5'd0 10 1'b0 9 1'b0 8 1'b0 7 1'b0 6 PwrMgtCap 1'b0 5 1'b0 4 1'b0 3:1 3'b111 0 1'b1 42 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller F4_DevIDVenID Bit Name Default Description Opmode 31:16 15:0 DevID VenID Value 4USB 16'h9990 2USB+OTG 16'h9990 2USB+OTG+ISA 16'h9990 2USB+OTG+GPIO 16'h9990 Opmode Value 4USB 16'h9710 2USB+OTG 16'h9710 2USB+OTG+ISA 16'h9710 2USB+OTG+GPIO 16'h9710 Device ID field for Function-4 Vendor ID field for Function-4 F4_Classcode Bit Name Default Description Opmode 31:24 ClassCode Value 4USB 8'h0C 2USB+OTG 8'h0C 2USB+OTG+ISA 8'h0C 2USB+OTG+GPIO 8'h0C Opmode 23:16 SubClassCode Value 4USB 8'h03 2USB+OTG 8'h03 2USB+OTG+ISA 8'h03 2USB+OTG+GPIO 8'h03 Opmode 15:8 7:0 ProgIntfInfo Rsvd Class code field for Function-4 Sub Class Code field for Function-4 Value 4USB 8'h10 2USB+OTG 8'h10 2USB+OTG+ISA 8'h10 2USB+OTG+GPIO 8'h10 8'h00 Programming Interface Information field for Function-4 Reserved 43 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller F4_BAR0 Bit Name Default Description Opmode 31:0 BAR0 Value 4USB 32'hFFFF_F000 2USB+OTG 32'hFFFF_F000 2USB+OTG+ISA 32'hFFFF_F000 2USB+OTG+GPIO 32'hFFFF_F000 Base Address Register-0 field for Function-4 F4_SubsysDIDVID Bit Name Default Description Opmode 31:16 15:0 SubsysDID SubsysVID Value 4USB 16'h4000 2USB+OTG 16'h4000 2USB+OTG+ISA 16'h4000 2USB+OTG+GPIO 16'h4000 Opmode Value 4USB 16'hA000 2USB+OTG 16'hA000 2USB+OTG+ISA 16'hA000 2USB+OTG+GPIO 16'hA000 Sub System Device ID field for Function-4 Sub System Vendor ID field for Function-4 F4_IntPinMap Bit Name Default Description 31:3 Rsvd 29'd0 Reserved 2:0 IntPinMap 3'b011 Interrupt pin [2:0] field for Function-4 44 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller F4_DevCapPwrMgtCap Bit Default Description 31 1'b0 30:28 3'b000 27:25 3'b111 24:22 3'b111 Reserved [14:12] bit field of Device Capability Register for Function-4 Endpoint L1 Acceptable Latency = [11:9] bit field of Device Capability Register for Function-4 Endpoint L0s Acceptable Latency = [8:6] bit field of Device Capability Register for Function-4 Extended Tag field supported = [5] bit field of Device Capability Register for Function-4 DLL Link active reporting Capable = [20] field of Link Capability Register for Function-4 Surprise down error reporting Capable = [19] field of Link Capability Register for Function-4 Max Payload Size Supported = [2:0] bit field of Device Capability Register for Function-4 Reserved D3 cold Support = [31] bit field of Power Management Capability Register for Function-4 D3 hot PME Support = [30] bit field of Power Management Capability Register for Function-4 D2 PME Support = [29] bit field of Power Management Capability Register for Function-4 D1 PME Support = [28] bit field of Power Management Capability Register for Function-4 D0 PME Support = [27] bit field of Power Management Capability Register for Function-4 D2 Support = [26] bit field of Power Management Capability Register for Function-4 D1 Support = [25] bit field of Power Management Capability Register for Function-4 AUX current = [24:22] bit field of Power Management Capability Register for Function-4 No Soft Reset = [3] bit field of Power Management Status/Control Register for Function-4 21 Name DevCap 1'b0 20 1'b0 19 1'b0 18:16 3'b001 15:11 Rsvd 5'd0 10 1'b0 9 1'b0 8 1'b0 7 1'b0 6 PwrMgtCap 1'b0 5 1'b0 4 1'b0 3:1 3'b111 0 1'b1 45 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller F5_DevIDVenID \ Bit Name Default Description Opmode 31:16 15:0 DevID VenID Value 4USB 16'h9990 2USB+OTG 16'h9990 2USB+OTG+ISA 16'h9990 2USB+OTG+GPIO 16'h9990 Opmode Value 4USB 16'h9710 2USB+OTG 16'h9710 2USB+OTG+ISA 16'h9710 2USB+OTG+GPIO 16'h9710 Device ID field for Function-5 Vendor ID field for Function-5 F5_Classcode Bit Name Default Description Opmode 31:24 ClassCode Value 4USB 8'h0C 2USB+OTG 8'h0C 2USB+OTG+ISA 8'h0C 2USB+OTG+GPIO 8'h0C Opmode 23:16 SubClassCode Value 4USB 8'h03 2USB+OTG 8'h03 2USB+OTG+ISA 8'h03 2USB+OTG+GPIO 8'h03 Opmode 15:8 7:0 ProgIntfInfo Rsvd Class code field for Function-5 Sub Class Code field for Function-5 Value 4USB 8'h20 2USB+OTG 8'h20 2USB+OTG+ISA 8'h20 2USB+OTG+GPIO 8'h20 8'h00 Programming Interface Information field for Function-5 Reserved 46 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller F5_BAR0 Bit Name Default Description Opmode 31:0 BAR0 Value 4USB 32'hFFFF_FF00 2USB+OTG 32'hFFFF_FF00 2USB+OTG+ISA 32'hFFFF_FF00 2USB+OTG+GPIO 32'hFFFF_FF00 Base Address Register-0 field for Function-5 F5_SubsysDIDVID Bit Name Default Description Opmode 31:16 15:0 SubsysDID SubsysVID Value 4USB 16'h4000 2USB+OTG 16'h4000 2USB+OTG+ISA 16'h4000 2USB+OTG+GPIO 16'h4000 Opmode Value 4USB 16'hA000 2USB+OTG 16'hA000 2USB+OTG+ISA 16'hA000 2USB+OTG+GPIO 16'hA000 Sub System Device ID field for Function-5 Sub System Vendor ID field for Function-5 F5_IntPinMap Bit Name Default Description 31:3 Rsvd 29'd0 Reserved 2:0 IntPinMap 3'b011 Interrupt pin [2:0] field for Function-5 47 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller F5_DevCapPwrMgtCap Bit Default Description 31 1'b0 30:28 3'b000 27:25 3'b111 24:22 3'b111 Reserved [14:12] bit field of Device Capability Register for Function-5 Endpoint L1 Acceptable Latency = [11:9] bit field of Device Capability Register for Function-5 Endpoint L0s Acceptable Latency = [8:6] bit field of Device Capability Register for Function-5 Extended Tag field supported = [5] bit field of Device Capability Register for Function-5 DLL Link active reporting Capable = [20] field of Link Capability Register for Function-5 Surprise down error reporting Capable = [19] field of Link Capability Register for Function-5 Max Payload Size Supported = [2:0] bit field of Device Capability Register for Function-5 21 Name DevCap 1'b0 20 1'b0 19 1'b0 18:16 3'b001 15:11 Rsvd 5'd0 10 1'b0 9 1'b0 8 1'b0 7 1'b0 6 PwrMgtCap 1'b0 5 1'b0 4 1'b0 3:1 3'b111 0 1'b1 D3 cold Support = [31] bit field of Power Management Capability Register for Function-5 D3 hot PME Support = [30] bit field of Power Management Capability Register for Function-5 D2 PME Support = [29] bit field of Power Management Capability Register for Function-5 D1 PME Support = [28] bit field of Power Management Capability Register for Function-5 D0 PME Support = [27] bit field of Power Management Capability Register for Function-5 D2 Support = [26] bit field of Power Management Capability Register for Function-5 D1 Support = [25] bit field of Power Management Capability Register for Function-5 AUX current = [24:22] bit field of Power Management Capability Register for Function-5 No Soft Reset = [3] bit field of Power Management Status/Control Register for Function-5 48 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller F6_DevIDVenID Bit Name Default Description Opmode 31:16 15:0 DevID VenID Value 4USB 16'h9990 2USB+OTG 16'h9990 2USB+OTG+ISA 16'h9990 2USB+OTG+GPIO 16'h9990 Opmode Value 4USB 16'h9710 2USB+OTG 16'h9710 2USB+OTG+ISA 16'h9710 2USB+OTG+GPIO 16'h9710 Device ID field for Function-6 Vendor ID field for Function-6 F6_Classcode Bit Name Default Opmode 31:24 ClassCode Value 4USB 8'h0C 2USB+OTG 8'hFF 2USB+OTG+ISA 8'hFF 2USB+OTG+GPIO 8'hFF Opmode 23:16 SubClassCode 7:0 ProgIntfInfo Rsvd Class code field for Function-6 Value 4USB 8'h03 2USB+OTG 8'h00 2USB+OTG+ISA 8'h00 2USB+OTG+GPIO 8'h00 Opmode 15:8 Description Sub Class Code field for Function6 Value 4USB 8'h10 2USB+OTG 8'h00 2USB+OTG+ISA 8'h00 2USB+OTG+GPIO 8'h00 8'h00 Programming Interface Information field for Function-6 Reserved 49 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller F6_BAR0 Bit Name Default Description Opmode 31:0 BAR0 Value 4USB 32'hFFFF_F000 2USB+OTG 32'hFFFF_F000 2USB+OTG+ISA 32'hFFFF_F000 2USB+OTG+GPIO 32'hFFFF_F000 Base Address Register-0 field for Function-6 F6_SubsysDIDVID Bit Name Default Description Opmode 31:16 SubsysDID 15:0 SubsysVID Value 4USB 16'h4000 2USB+OTG 16'h5000 2USB+OTG+ISA 16'h5000 2USB+OTG+GPIO 16'h5000 Opmode Value 4USB 16'hA000 2USB+OTG 16'hA000 2USB+OTG+ISA 16'hA000 2USB+OTG+GPIO 16'hA000 Sub System Device ID field for Function-6 Sub System Vendor ID field for Function-6 F6_IntPinMap Bit Name 31:3 Rsvd Default Reserved Opmode 2:0 IntPinMap Description Value 4USB 3'b100 2USB+OTG 3'b011 2USB+OTG+ISA 3'b011 2USB+OTG+GPIO 3'b011 Interrupt pin [2:0] field for Function6 50 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller F6_DevCapPwrMgtCap Bit Default Description 31 1'b0 30:28 3'b000 27:25 3'b111 24:22 3'b111 Reserved [14:12] bit field of Device Capability Register for Function-6 Endpoint L1 Acceptable Latency = [11:9] bit field of Device Capability Register for Function-6 Endpoint L0s Acceptable Latency = [8:6] bit field of Device Capability Register for Function-6 Extended Tag field supported = [5] bit field of Device Capability Register for Function-6 DLL Link active reporting Capable = [20] field of Link Capability Register for Function-6 Surprise down error reporting Capable = [19] field of Link Capability Register for Function-6 Max Payload Size Supported = [2:0] bit field of Device Capability Register for Function-6 Reserved D3 cold Support = [31] bit field of Power Management Capability Register for Function-6 D3 hot PME Support = [30] bit field of Power Management Capability Register for Function-6 D2 PME Support = [29] bit field of Power Management Capability Register for Function-6 D1 PME Support = [28] bit field of Power Management Capability Register for Function-6 D0 PME Support = [27] bit field of Power Management Capability Register for Function-6 D2 Support = [26] bit field of Power Management Capability Register for Function-6 D1 Support = [25] bit field of Power Management Capability Register for Function-6 AUX current = [24:22] bit field of Power Management Capability Register for Function-6 No Soft Reset = [3] bit field of Power Management Status/Control Register for Function-6 21 Name DevCap 1'b0 20 1'b0 19 1'b0 18:16 3'b001 15:11 Rsvd 5'd0 10 1'b0 9 1'b0 8 1'b0 7 1'b0 6 PwrMgtCap 1'b0 5 1'b0 4 1'b0 3:1 3'b111 0 1'b1 51 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller F7_DevIDVenID Bit Name Default Description Opmode 31:16 15:0 DevID VenID Value 4USB 16'h9990 2USB+OTG 16'h9990 2USB+OTG+ISA 16'h9990 2USB+OTG+GPIO 16'h9990 Opmode Value 4USB 16'h9710 2USB+OTG 16'h9710 2USB+OTG+ISA 16'h9710 2USB+OTG+GPIO 16'h9710 Device ID field for Function-7 Vendor ID field for Function-7 F7_Classcode Bit Name Default Opmode 31:24 ClassCode Value 4USB 8'h0C 2USB+OTG 8'h00 2USB+OTG+ISA 8'h07 2USB+OTG+GPIO 8'hFF Opmode 23:16 SubClassCode 7:0 ProgIntfInfo Rsvd Class code field for Function-7 Value 4USB 8'h03 2USB+OTG 8'h00 2USB+OTG+ISA 8'h80 2USB+OTG+GPIO 8'h00 Opmode 15:8 Description Sub Class Code field for Function7 Value 4USB 8'h20 2USB+OTG 8'h00 2USB+OTG+ISA 8'h00 2USB+OTG+GPIO 8'h01 8'h00 Programming Interface Information field for Function-7 Reserved 52 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller F7_BAR0 Bit Name Default Opmode 31:0 BAR0 Description Value 4USB 32'hFFFF_FF00 2USB+OTG 32'h0000_0000 2USB+OTG+ISA 32'hFFFF_FFF9 2USB+OTG+GPIO 32'hFFFF_FF00 Base Address Register-0 field for Function-7 F7_BAR1 Bit Name Default Opmode 31:0 BAR1 Description Value 4USB 32'h0000_0000 2USB+OTG 32'h0000_0000 2USB+OTG+ISA 32'hFFFF_FFF9 2USB+OTG+GPIO 32'h0000_0000 Base Address Register-1 field for Function-7 F7_BAR2 Bit Name Default Opmode 31:0 BAR2 Description Value 4USB 32'h0000_0000 2USB+OTG 32'h0000_0000 2USB+OTG+ISA 32'hFFFF_FFF9 2USB+OTG+GPIO 32'h0000_0000 Base Address Register-2 field for Function-7 F7_BAR3 Bit Name Default Opmode 31:0 BAR3 Description Value 4USB 32'h0000_0000 2USB+OTG 32'h0000_0000 2USB+OTG+ISA 32'hFFFF_FFF9 2USB+OTG+GPIO 32'h0000_0000 Base Address Register-3 field for Function-7 53 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller F7_BAR4 Bit Name Default Description Opmode 31:0 BAR4 Value 4USB 32'h0000_0000 2USB+OTG 32'h0000_0000 2USB+OTG+ISA 32'hFFFF_F000 2USB+OTG+GPIO 32'h0000_0000 Base Address Register-4 field for Function-7 F7_SubsysDIDVID Bit Name Default Opmode 31:16 15:0 SubsysDID SubsysVID Description Value 4USB 16'h4000 2USB+OTG 16'h0000 2USB+OTG+ISA 16'h3004 2USB+OTG+GPIO 16'h6000 Opmode Value 4USB 16'hA000 2USB+OTG 16'hA000 2USB+OTG+ISA 16'hA000 2USB+OTG+GPIO 16'hA000 Sub System Device ID field for Function-7 Sub System Vendor ID field for Function-7 F7_IntPinMap Bit Name Default Description 31:3 Rsvd 29'd0 Reserved 2:0 IntPinMap 3'b100 Interrupt pin [2:0] field for Function-7 54 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller F7_DevCapPwrMgtCap Bit Default Description 31 1'b0 30:28 3'b000 27:25 3'b111 24:22 3'b111 Reserved [14:12] bit field of Device Capability Register for Function-7 Endpoint L1 Acceptable Latency = [11:9] bit field of Device Capability Register for Function-7 Endpoint L0s Acceptable Latency = [8:6] bit field of Device Capability Register for Function-7 Extended Tag field supported = [5] bit field of Device Capability Register for Function-7 DLL Link active reporting Capable = [20] field of Link Capability Register for Function-7 Surprise down error reporting Capable = [19] field of Link Capability Register for Function-7 Max Payload Size Supported = [2:0] bit field of Device Capability Register for Function-7 Reserved D3 cold Support = [31] bit field of Power Management Capability Register for Function-7 D3 hot PME Support = [30] bit field of Power Management Capability Register for Function-7 D2 PME Support = [29] bit field of Power Management Capability Register for Function-7 D1 PME Support = [28] bit field of Power Management Capability Register for Function-7 D0 PME Support = [27] bit field of Power Management Capability Register for Function-7 D2 Support = [26] bit field of Power Management Capability Register for Function-7 D1 Support = [25] bit field of Power Management Capability Register for Function-7 AUX current = [24:22] bit field of Power Management Capability Register for Function-7 No Soft Reset = [3] bit field of Power Management Status/Control Register for Function-7 21 Name DevCap 1'b0 20 1'b0 19 1'b0 18:16 3'b001 15:11 Rsvd 5'd0 10 1'b0 9 1'b0 8 1'b0 7 1'b0 6 PwrMgtCap 1'b0 5 1'b0 4 1'b0 3:1 3'b111 0 1'b1 55 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 6.3 OHCI Register Set The Host Controller (HC) contains a set of operational registers which are mapped into system memory space. According to the function of these registers, they are divided into four partitions, specifically Control and Status, Memory Pointer, Frame Counter and Root Hub. All of the registers should be read and written as DWORD's (DW). Address to access these registers is calculated by adding BAR0 base address of OHCI function to the offset mentioned below. BAR0 (of OHCI function) + <Offset> Control and Status Register Offset 00-03h 04-07h 08-0Bh 0C-0Fh 10-13h 14-17h Register Name HcRevision HcControl HcCommandStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable Default Value 32'h0000_0010 32'h0000_0000 32'h0000_0000 32'h0000_0000 32'h0000_0000 32'h0000_0000 Access RO RW RW RW RW RW Register Name HcHCCA HcPeriodCurrentED HcControlHeadED HcControlCurrentED HcBulkHeadED HcBulkCurrentED HcDoneHead Default Value 32'h0000_0000 32'h0000_0000 32'h0000_0000 32'h0000_0000 32'h0000_0000 32'h0000_0000 32'h0000_0000 Access RO RW RW RW RW RW RW Register Name HcFmInterval HcFmRemaining HcFmNumber HcPeriodicStart HcLSThreshold Default Value 32'h0000_2EDF 32'h0000_0000 32'h0000_0000 32'h0000_0000 32'h0000_0628 Access RW RW RW RW RW Memory Pointer Register Offset 18-1Bh 1C-1Fh 20-23h 24-27h 28-2Bh 2C-2Fh 30-33h Frame Counter Register Offset 34-37h 38-3Bh 3C-3Fh 40-43h 44-47h 56 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Root Hub Register Offset 48-4Bh 4C-4Fh 50-53h 54-57h Register Name HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus1 Default Value Implementation Specific Implementation Specific 32'h0000_0000 32'h0000_0000 Access RW RW RW RW 6.3.1 Description of OHCI Operational Registers HcRevision Key Bit Reset HCD /HC R/R REV 7:0 Rsvd 31:8 10h Description Revision: This read-only field contains the BCD representation of the version of the HCI specification that is implemented by this OHC. For example, a value of 11h corresponds to version 1.1. Reserved HcControl The HcControl register defines the operating modes for the Host Controller. Most of the fields in this register are modified only by the Host Controller Driver, except Host Controller Functional State and Remote Wakeup Connected. Key Bit Reset HCD/HC CBSR 1:0 00b RW / R PLE 2 0b RW / R Description Control Bulk Service Ratio This specifies the service ratio between Control and Bulk EDs. Before processing any of the non periodic lists, OHC compares the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs .The internal count will be retained when crossing the frame boundary. CBSR | no. of Control EDs Over BulkEDs served 0 1:1 1 2:1 2 3:1 3 4:1 Periodic List Enable This bit is set to enable the processing of the periodic list in the next Frame. OHC must check this bit before it starts processing the list. 57 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Key Bit Reset HCD/HC IE 3 0b RW/R CLE 4 0b RW/R BLE 5 0b RW/R HCFS 7:6 00b RW/RW Description Isochronous Enable This bit is used by HCD to enable/disable processing of isochronous EDs. While processing the periodic list in a Frame, OHC checks the status of this bit when it finds an Isochronous ED (F=1). If set (enabled), OHC continues processing the EDs. If cleared (disabled), OHC halts processing of the periodic list (which now contains only isochronous EDs) and begins processing the Bulk/Control lists. Control List Enable This bit is set to enable the processing g of the Control list in the next Frame. OHC must check this bit whenever it determines to process the list. When disabled, HCD may modify the list. Bulk List Enable This bit is set to enable the processing of the Bulk list in the next Frame. OHC checks this bit whenever it determines to process the list. When disabled, HCD may modify the list. Host Controller Functional State for USB 00b: USBRESET 01b: USBRESUME 10b: USBOPERATIONAL 11b: USBSUSPEND A transition to USBOPERATIONAL from another state causes SOF generation to begin 1ms later. HCD may determine whether OHC has begun sending SOFs by reading the Start of Frame field of HcInterruptStatus. This field may be changed by OHC only when in the USBSUSPEND state. OHC may move from the USBSUSPEND state to the USBRESUME state after detecting the resume signaling from a downstream port. OHC enters USBSUSPEND after software reset, whereas it enters USBRESET after a hardware reset. The latter also resets the Root Hub and asserts subsequent reset signaling to downstream ports. 58 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Key Bit Reset HCD/HC IR 8 0b RW/R RWC 9 0b RW/ RW RWE 10 0b RW/R Rsvd 31:11 Description Interrupt Routing This bit determines the routing of interrupts generated by event registered in HcInterruptStatus. If clear, all interrupts are routed to the normal host bus interrupt mechanism i.e. INT pin. If set, interrupts are routed to the System Management Interrupt. Remote Wakeup Connected This bit indicates whether OHC supports remote wakeup signaling. If remote wakeup is supported and used by the system it is the responsibility of system firmware to set this bit during POST. OHC clears the bit upon a hardware reset but does not alter it upon a software reset. Remote Wakeup Enable This bit is used by HCD to enable or disable the remote wakeup feature upon the detection of upstream resume signaling. When this bit is set and the Resume Detected bit in HcInterruptStatus is set, a remote wakeup is signaled to the host system. Setting this bit has no impact on the generation of hardware interrupt. Reserved HcCommandStatus The HcCommandStatus register is used by the Host Controller to receive commands issued by the Host Controller Driver, as well as reflecting the current status of the Host Controller. The Scheduling Overrun Count field indicates the number of frames with which the Host Controller has detected the scheduling overrun error. This occurs when the Periodic list does not complete before EOF. When a scheduling overrun error is detected, the Host Controller increments the counter and sets the Scheduling Overrun field in the HcInterruptStatus register. Key Bit Reset HCD/HC HCR 0 0b RW/ RW Description HostControllerReset This bit is set by HCD to initiate a software reset of OHC. Regardless of the functional state of OHC, it moves to the USBSUSPEND state in which most of the operational registers are reset except those stated otherwise; 59 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Key Bit Reset HCD/HC CLF 1 0b RW/ RW BLF 2 0b RW/ RW OCR 3 0b RW/ RW Rsvd 15:4 SOC 17:16 00b R/ RW Rsvd 31:18 Description ControlListFilled This bit is used to indicate whether there are any TDs on the Control list. It is set by HCD whenever it adds a TD to an ED in the Control list. When OHC begins to process the head of the Control list, it checks CLF. As long as ControlListFilled is 0, OHC will not start processing the Control list. If CF is 1, OHC will start processing the Control list and will set ControlListFilled to 0. If the HCD does not set ControlListFilled, then ControlListFilled will still be 0 when OHC completes processing the Control list and Control list processing will stop. BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list. It is set by HCD whenever it adds a TD to an ED in the Bulk list. When OHC begins to process the head of the Bulk list, it checks BLF. As long as BulkListFilled is 0, HC will not start processing the Bulk list. If BulkListFilled is 1, HC will start processing the Bulk list and will set BLF to 0. If HCD does not set BulkListFilled, then BulkListFilled will still be 0 when HC completes processing the Bulk list and Bulk list processing will stop. Ownership Change Request This bit is set by an HCD to request a change of control of the OHC. When set OHC will set the Ownership Change field in HcInterruptStatus. After the changeover, this bit is cleared and remains so until the next request from HCD. Reserved Scheduling Overrun Count These bits are incremented on each scheduling overrun error. It is initialized to 00b and wraps around at 11b. This will be incremented when a scheduling overrun is detected even if Scheduling Overrun in HcInterruptStatus has already been set. This is used by HCD to monitor any persistent scheduling problems. Reserved 60 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller HcInterruptstatus This register provides status on various events that cause hardware interrupts. When an event occurs, Host Controller sets the corresponding bit in this register. When a bit becomes set, a hardware interrupt is generated if the interrupt is enabled in the HcInterruptEnable register and the MasterInterruptEnable bit is set. The Host Controller Driver may clear specific bits in this register by writing '1' to bit positions to be cleared. The Host Controller Driver may not set any of these bits. The Host Controller will never clear the bit. Key Bit Reset HCD/HC SO 0 0b RW/ RW WDH 1 0b RW/RW SF 2 0b RW/ RW RD 3 0b RW/ RW UE 4 0b RW/ RW FNO 5 0b RW/ RW Description Scheduling Overrun This bit is set when the USB schedule for the current Frame overruns .A scheduling overrun will also cause the Scheduling Overrun Count of HcCommandStatus to be incremented. WritebackDoneHead This bit is set immediately after OHC has written HcDoneHead to HccaDoneHead. Further updates of the HccaDoneHead will not occur until this bit has been cleared. HCD should only clear this bit after it has saved the content of HccaDoneHead. Start of Frame This bit is set by OHC at each start of a frame and after the update of HccaFrameNumber. OHC also generates a SOF token at the same time. Resume Detected This bit is set when OHC detects that a device on the USB is asserting resume signaling. It is the transition from no resume signaling to resume signaling causing this bit to be set. This bit is not set when HCD sets the USBRESUME state. UnrecoverableError This bit is set when OHC detects a system error not related to USB. OHC should not proceed with any processing or signaling before the system error has been corrected. HCD clears this bit after OHC has been reset. FrameNumberOverflow This bit is set when the MSB of HcFmNumber (bit 15) changes value, from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been updated. 61 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Key Bit Reset HCD/HC RHSC 6 0b RW/ RW OC 30 0b RW/ RW Rsvd 29:7 Description RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any of HcRhPortStatus[NumberofDownstreamPort] has changed. Ownership Change This bit is set by HC when HCD sets the Ownership Change Request field in HcCommandStatus. This event, when unmasked, will always generate a System Management Interrupt (SMI) immediately. This bit is tied to 0b when the SMI pin is not implemented. Reserved HcInterruptEnable Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptEnable register is used to control which events generate a hardware interrupt. When a bit is set in the HcInterruptStatus register AND the corresponding bit in the HcInterruptEnable register is set AND the MasterInterruptEnable bit is set, then a hardware interrupt is requested on the host bus. Key Bit Reset HCD/HC SO 0 0b RW/ R WDH 1 0b RW/R SF 2 0b RW/ R RD 3 0b RW/R UE 4 0b RW/R Description Scheduling Overrun 0 - Ignore 1 - Enable interrupts generation due to Scheduling Overrun. WritebackDoneHead 0 - Ignore 1 - Enable interrupts generation due to HcDoneHead Write back. Start of Frame 0 - Ignore 1 - Enable interrupts generation due to Start of Frame. Resume Detected 0 - Ignore 1 - Enable interrupts generation due to Resume Detect. UnrecoverableError 0 - Ignore 1 - Enable interrupts generation due to Unrecoverable Error. 62 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Key Bit Reset HCD/HC FNO 5 0b RW/R RHSC 6 0b RW/R OC 30 0b RW/R MIE 31 0b RW/R Rsvd 29:7 Description FrameNumberOverflow 0 - Ignore 1 - Enable interrupts generation due to Frame Number Overflow. RootHubStatusChange 0 - Ignore 1 - Enable interrupts generation due to Root Hub Status Change. Ownership Change 0 - Ignore 1 - Enable interrupts generation due to Ownership Change. MasterInterruptEnable A '0' written to this field is ignored by HC. A '1' written to this field enables interrupt generation due to events specified in the other bits of this register. This is used by HCD as a Master Interrupt Enable. Reserved HcInterruptDisable Each disable bit in the HcInterrupJTAG_TDisable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterrupJTAG_TDisable register is coupled with the HcInterruptEnable register. Thus, writing a '1' to a bit in this register clears the corresponding bit in the HcInterruptEnable register, whereas writing a '0' to a bit in this register leaves the corresponding bit in the HcInterruptEnable register unchanged. On read, the current value of the HcInterruptEnable register is returned. Key Bit Reset HCD/HC SO 0 0b RW/ R WDH 1 0b RW/ R SF 2 0b RW/ R Description Scheduling Overrun 0 - Ignore 1 - Disable interrupts generation due to Scheduling Overrun. WritebackDoneHead 0 - Ignore 1 - Disable interrupts generation due to HcDoneHead Write back. Start of Frame 0 - Ignore 1 - Disable interrupts generation due to Start of Frame. 63 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Key Bit Reset HCD/HC RD 3 0b RW/ R UE 4 0b RW/ R FNO 5 0b RW/ R 0b RHSC 6 RW/ R Rsvd 29:7 0 OC 30 0b MIE 31 0b RW/ R RW/ R Description Resume Detected 0 - Ignore 1 - Disable interrupts generation due to Resume Detect. UnrecoverableError 0 - Ignore 1 - Disable interrupts generation due to Unrecoverable Error. FrameNumberOverflow 0 - Ignore 1 - Disable interrupts generation due to Frame Number Overflow. RootHubStatusChange 0 - Ignore 1 - Disable interrupts generation due to Root Hub Status Change. Reserved Ownership Change 0 - Ignore 1 - Disable interrupts generation due to Ownership Change. MasterInterruptEnable A '0' written to this field is ignored by HC. A '1' written to this field enables interrupt generation due to events specified in the other bits of this register. This is used by HCD as a Master Interrupt Enable. HcHCCA The HcHCCA register contains the physical address of the Host Controller Communication Area. This area is used to hold the control structures and the Interrupt table that are accessed by both the Open Host Controller and the Host Controller Driver. Key Bit HCCA 31:8 Rsvd 7:0 Reset 0x400F_D1 (OHCI1) 0x400F_E1 (OHCI2) 0 HCD/HC Description R/R Host Controller Communication Area This is the base address of the Host Controller Communication Area. R/R Reserved 64 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller HcPeriodCurrentED The HcPeriodCurrentED register contains the physical address of the current Isochronous or Interrupt Endpoint Descriptor. Key Bit Reset PCED 31:4 0h Rsvd 3:0 0h HCD/HC R/ RW Description PeriodCurrentED This is used by HC to point to the head of one of the Periodic lists which will be processed in the current Frame. The content of this register is updated by HC after a periodic ED has been processed. HCD may read the content in determining which ED is currently being processed at the time of reading. Reserved HcControlHeadED The HcControlHeadED register contains the physical address of the first Endpoint Descriptor of the Control list. Key Bit Reset CHED 31:4 0h Rsvd 3:0 0h HCD/HC RW/ R Description ControlHeadED OHC traverses the Control list starting with the HcControlHeadED pointer. The content is loaded from HCCA during the initialization of HC. Reserved HcControlCurrentED Key Bit Reset CCED 31:4 0h Rsvd 3:0 0h HCD/HC RW/ RW Description ControlCurrentED This pointer is advanced to the next ED after serving the present one. HC will continue processing the list from where it left off in the last Frame. When it reaches the end of the Control list, HC checks the ControlListFilled of in HcCommandStatus. If set, it copies the content of HcControlHeadED to HcControlCurrentED and clears the bit. If not set, it does nothing. HCD is allowed to modify this register only when the Control List Enable of HcControl is cleared. When set, HCD only reads the instantaneous value of this register. Initially, this is set to zero to indicate the end of the Control list. Reserved 65 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller HcBulkHeadED The HcBulkHeadED register contains the physical address of the first Endpoint Descriptor of the Bulk list. Key Bit Reset HCD/HC BHED 31:4 0h RW/R Rsvd 3:0 0h Description BulkHeadED HC traverses the Bulk list starting with the HcBulkHeadED pointer. Reserved HcBulkCurrentED The HcBulkCurrentED register contains the physical address of the current endpoint of the Bulk list. Key Bit Reset BCED 31:4 0h Rsvd 3:0 0h HCD/HC RW/ RW Description BulkCurrentED This is advanced to the next ED after the HC has served the present one. HC continues processing the list from where it left off in the last Frame. When it reaches the end of the Bulk list, HC checks the ControlListFilled of HcControl. If set, it copies the content of HcBulkHeadED to HcBulkCurrentED and clears the bit. If it is not set, it does nothing. HCD is only allowed to modify this register when the Bulk List Enable of HcControl is cleared. When set, the HCD only reads the instantaneous value of this register. This is initially set to zero to indicate the end of the Bulk list. Reserved HcDoneHead The HcDoneHead register contains the physical address of the last completed Transfer Descriptor that was added to the done queue. In normal operation, the Host Controller Driver should not need to read this register as its content is periodically written to the HCCA. Key Bit Reset DH 31:4 0h Rsvd 3:0 0h HCD/HC R/RW Description DoneHead When a TD is completed, HC writes the content of HcDoneHead to the Next TD field of the TD. HC then overwrites the content of HcDoneHead with the address of this TD. This is set to zero whenever HC writes the content of this register to HCCA. It also sets the write back Done Head of HcInterruptStatus. Reserved 66 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller HcFmInterval The HcFmInterval register contains a 14-bit value which indicates the bit time interval in a Frame, (i.e., between two consecutive SOFs), and a 15-bit value indicating the Full Speed maximum packet size that the Host Controller may transmit or receive without causing scheduling overrun. The Host Controller Driver may carry out minor adjustment on the Frame Interval by writing a new value over the present one at each SOF. This provides the programmability necessary for the Host Controller to synchronize with an external clocking resource. Key Bit Reset HCD/HC FI 13:0 2EDFh RW/ R Rsvd 15:14 0h FSMPS 30:16 - RW/ R FIT 31 0b RW/ R Description Frame Interval This specifies the interval between two consecutive SOFs in bit times. The nominal value is set to be 11,999. HCD should store the current value of this field before resetting HC. By setting the HostControllerReset field of HcCommandStatus as this will cause the HC to reset this field to its nominal value. HCD may choose to restore the stored value upon the completion of the Reset sequence. Reserved FSLargestDataPacket This field specifies a value which is loaded into the Largest Data Packet Counter at the beginning of each frame. The counter value represents the largest amount of data in bits which can be sent or received by the HC in a single transaction at any given time without causing scheduling overrun. The field value is calculated by the HCD. FrameIntervalToggle HCD toggles this bit whenever it loads a new value to Frame Interval. 67 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller HcFmRemaining The HcFmRemaining register is a 14-bit down counter showing the bit time remaining in the current Frame. Key Bit Reset FR 13:0 0h Rsvd 30:14 0h FRT 31 0b HCD /HC R/RW R/RW Description Frame Remaining This counter is decremented at each bit time. When it reaches zero, it is reset by loading the Frame Interval value specified in HcFmInterval at the next bit time boundary. When entering the USBOPERATIONAL state, HC re-loads the content with the Frame Interval of HcFmInterval and uses the updated value from the next SOF. Reserved Frame Remaining Toggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval whenever Frame Remaining reaches 0. This bit is used by HCD for the synchronization between Frame Interval and Frame Remaining. HcFmNumber The HcFmNumber register is a 16-bit counter. It provides a timing reference among events happening in the Host Controller and the Host Controller Driver. Key Bit Reset HCD/HC FN 15:0 0h R/RW Rsvd 31:16 0h Description Frame Number This is incremented when HcFmRemaining is reloaded. It will be rolled over to 0h after ffffh. When entering the USBOPERATIONAL state, this will be incremented. The content will be written to HCCA after HC has incremented the Frame Number at each frame boundary and sent a SOF but before HC reads the first ED in that Frame. After writing to HCCA, HC will set the Start of Frame in HcInterruptStatus. Reserved 68 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller HcPeriodicStart The HcPeriodicStart register has a 14-bit programmable value which determines when is the earliest time HC should start processing the periodic list. Key Bit Reset PS 13:0 0h Rsvd 31:14 0h HCD/HC RW/ R Description PeriodicStart After hardware reset, this field is cleared. This is then set by HCD during the HC initialization. The value is calculated roughly as 10% off from HcFmInterval. When HcFmRemaining reaches the value specified, processing of the periodic lists will have priority over Control/Bulk processing. HC will therefore start processing the Interrupt list after completing the current Control or Bulk transaction that is in progress. Reserved HcLSThreshold The HcLSThreshold register contains an 11-bit value used by the Host Controller to determine whether to commit to the transfer of a maximum of 8-byte LS packet before EOF. Key Bit Reset LST 11:0 0628h Rsvd 31:12 0h HCD/HC RW/ R Description LSThreshold This field contains a value which is compared to the Frame Remaining field prior to initiating a Low Speed transaction. The transaction is started only if Frame Remaining this field. Reserved All registers included in this partition are dedicated to the USB Root Hub which is an integral part of the Host Controller though still a functionally separate entity. The HCD emulates USBD accesses to the Root Hub via a register interface. The HCD maintains many USB-defined hub features which are not required to be supported in hardware. 69 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller HcRhDescriptorA The HcRhDescriptorA register is the first register of two describing the characteristics of the Root Hub. Reset values are implementation-specific. The descriptor length (11), descriptor type (TBD), and hub controller current (0) fields of the hub Class Descriptor are emulated by the HCD. Key Bit Reset HCD/HC NDP 7:0 IS R/ R PSM 8 IS RW/R NPS 9 IS RW/R DT 10 0 R/R Description NumberDownstreamPorts These bits specify the number of downstream ports supported by the Root Hub. It is implementationspecific. The minimum number of ports is 1. The maximum number of ports supported by OpenHCI is 15. PowerSwitchingMode This bit is used to specify how the power switching of the Root Hub ports is controlled. It is implementation-specific. This field is only valid if the NoPowerSwitching field is cleared. 0: All ports are powered at the same time. 1: Each port is powered individually. This mode allows port power to be controlled by either the global switch or per port switching. If the PortPowerControlMask bit is set, the port responds only to port power commands (Set/ClearPortPower). If the port mask is cleared, then the port is controlled only by the global power switch (Set/ClearGlobalPower). NoPowerSwitching These bits are used to specify whether power switching is supported or ports are always powered. It is implementation specific. When this bit is cleared, the PowerSwitchingMode specifies global or per-port switching. 0: Ports are power switched 1: Ports are always powered on when the HC is powered on DeviceType This bit specifies that the Root Hub is not a compound device. The Root Hub is not permitted to be a compound device. This field should always read/write 0. 70 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Key Bit Reset HCD/HC OCPM 11 IS RW/R NOCP 12 IS RW/R Rsvd 23:13 0 POTPGT 31:24 IS RW/R Description OverCurrentProtectionMode This bit describes how the overcurrent statuses for the Root Hub ports are reported. At reset, these fields should reflect the same mode as PowerSwitchingMode. This field is valid only if the NoOverCurrentProtection field is cleared. 0: Over-current status is reported collectively for all downstream ports 1: Over-current status is reported on a per-port basis NoOverCurrentProtection This bit describes how the overcurrent statuses for the Root Hub ports are reported. When this bit is cleared, the OverCurrentProtectionMode field specifies global or per-port reporting. 0: Over-current status is reported collectively for all downstream ports 1: No overcurrent protection supported Reserved PowerOnToPowerGoodTime This byte specifies the duration HCD has to wait before accessing a powered-on port of the Root Hub. It is implementation-specific. The unit of time is 2 ms. The duration is calculated as POTPGT*2 ms. HcRhDescriptorB The HcRhDescriptorB register is the second register of two describing the characteristics of the Root Hub. These fields are written during initialization to correspond with the system implementation. Reset values are implementation-specific. Key DR Bit 15:0 Reset IS HCD/HC Description RW/ R DeviceRemovable Each bit is dedicated to a port of the Root Hub. When cleared, the attached device is removable. When set, the attached device is not removable. bit 0: Reserved bit 1: Device attached to Port #1 bit 2: Device attached to Port #2 ... bit 15: Device attached to Port #15 71 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Key Bit Reset HCD/HC PPCM 31:16 IS RW/ R Description PortPowerControlMask Each bit indicates if a port is affected by a global power control command when PowerSwitchingMode is set. When set, the port's power state is only affected by per-port power control (Set/ClearPortPower). When cleared, the port is controlled by the global power switch (Set/ClearGlobalPower). If the device is configured to global switching mode (PowerSwitchingMode=0), this field is not valid. bit 0: Reserved bit 1: Ganged-power mask on Port #1 bit 2: Ganged-power mask on Port #2 ... bit 15: Ganged-power mask on Port #15 HcRhStatus The HcRhStatus register is divided into two parts. The lower word of a Dword represents the Hub Status field and the upper word represents the Hub Status Change field. Key Bit Reset HCD/HC LPS 0 0 RW/ R OCI 1 0 R/ RW Rsvd 14:2 0 Description (read) LocalPowerStatus The Root Hub does not support the local power status feature; thus, this bit is always read as `0'. (write) ClearGlobalPower In global power mode (PowerSwitchingMode=0), This bit is written to `1' to turn off power to all ports (clear PortPowerStatus). In per-port power mode, it clears PortPowerStatus only on ports whose PortPowerControlMask bit is not set. Writing a `0' has no effect . OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented. When set, an overcurrent condition exists. When cleared, all power operations are normal. If per-port overcurrent protection is implemented this bit is always `0' Reserved 72 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Key Bit Reset HCD/HC DRWE 15 0 RW/R LPSC 16 0 RW/R OCIC 17 0 RW/RW Rsvd 30:18 0 CRWE 31 W/R Description (read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume event, causing a USBSUSPEND to USBRESUME state transition and setting the Resume Detected interrupt. 0 = ConnectStatusChange is not a remote wakeup event. 1 = ConnectStatusChange is a remote wakeup event. (write) SetRemoteWakeupEnable Writing a '1' sets DeviceRemoveWakeupEnable. Writing a '0' has no effect. (read) LocalPowerStatusChange The Root Hub does not support the local power status feature; thus, this bit is always read as `0'. (write) SetGlobalPower. In global power mode (PowerSwitchingMode=0), This bit is written to `1' to turn on power to all ports (clear PortPowerStatus). In per-port power mode, it sets PortPowerStatus only on ports whose PortPowerControlMask bit is not set. Writing a `0' has no effect. OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this register. The HCD clears this bit by writing a `1'. Writing a `0' has no effect. Reserved (write) ClearRemoteWakeupEnable Writing a '1' clears DeviceRemoveWakeupEnable. Writing a '0' has no effect. 73 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller HcRhPortStatus1 The HcRhPortStatus1 register is used to control and report port events on a per-port basis. NumberDownstreamPorts represents the number of HcRhPortStatus registers that are implemented in hardware. The lower word is used to reflect the port status, whereas the upper word reflects the status change bits. Key Bit Reset HCD/HC CCS 0 0 RW/RW PES 1 0 RW/RW Description (read) CurrentConnectStatus This bit reflects the current state of the downstream port. 0 = no device connected 1 = device connected (write) ClearPortEnable The HCD writes a `1' to this bit to clear the PortEnableStatus bit. Writing a `0' has no effect. The CurrentConnectStatus is not affected by any write. Note: This bit is always read `1b' when the attached device is nonremovable (DeviceRemoveable[NDP]). (read) PortEnableStatus This bit indicates whether the port is enabled or disabled. The Root Hub may clear this bit when an overcurrent condition, disconnect event, switchedoff power, or operational bus error such as babble is detected. This change also causes PortEnabledStatusChange to be set. HCD sets this bit by writing SetPortEnable and clears it by writing ClearPortEnable. This bit cannot be set when CurrentConnectStatus is cleared. This bit is also set, if not already, at the completion of a port reset when ResetStatusChange is set or port suspend when SuspendStatusChange is set. 0 = port is disabled 1 = port is enabled (write) SetPortEnable The HCD sets PortEnableStatus by writing a `1'. Writing a `0' has no effect. If CurrentConnectStatus is cleared, this write does not set PortEnableStatus, but instead sets ConnectStatusChange. This informs the driver that it attempted to enable a disconnected port. 74 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Key Bit Reset HCD/HC PSS 2 0 RW/RW POCI 3 0 RW/RW Description (read) PortSuspendStatus This bit indicates the port is suspended or in the resume sequence. It is set by a SetSuspendState write and cleared when PortSuspendStatusChange is set at the end of the resume interval. This bit cannot be set if CurrentConnectStatus is cleared. This bit is also cleared when PortResetStatusChange is set at the end of the port reset or when the HC is placed in the USBRESUME state. If an upstream resume is in progress, it should propagate to the HC. 0 = port is not suspended 1 = port is suspended (write) SetPortSuspend The HCD sets the PortSuspendStatus bit by writing a `1' to this bit. Writing a `0' has no effect. If CurrentConnectStatus is cleared, this write does not set PortSuspendStatus; instead it sets ConnectStatusChange. This informs the driver that it attempted to suspend a disconnected port. (read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in such a way that overcurrent conditions are reported on a per-port basis. If per-port overcurrent reporting is not supported, this bit is set to 0. If cleared, all power operations are normal for this port. If set, an overcurrent condition exists on this port. This bit always reflects the overcurrent input signal 0 = no overcurrent condition. 1 = overcurrent condition detected. (write) ClearSuspendStatus The HCD writes a `1' to initiate a resume. Writing a `0' has no effect. A resume is initiated only if PortSuspendStatus is set. 75 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Key Bit Reset HCD/HC PRS 4 0 RW/RW Rsvd 7:5 0 Description (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted. When reset is completed, this bit is cleared when PortResetStatusChange is set. This bit cannot be set if CurrentConnectStatus is cleared. 0 = port reset signal is not active 1 = port reset signal is active (write) SetPortReset The HCD sets the port reset signaling by writing a `1' to this bit. Writing a `0' has no effect. If CurrentConnectStatus is cleared, this write does not set PortResetStatus, but instead sets ConnectStatusChange. This informs the driver that it attempted to reset a disconnected port. Reserved 76 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Key Bit Reset HCD/HC PPS 8 0 RW/RW LSDA 9 x Rsvd 15:10 0 Description (read) PortPowerStatus This bit reflects the port's power status, regardless of the type of power switching implemented. This bit is cleared if an overcurrent condition is detected. HCD sets this bit by writing SetPortPower or SetGlobalPower. HCD clears this bit by writing ClearPortPower or ClearGlobalPower. Which power control switches are enabled is determined by PowerSwitchingMode and PortPortControlMask[NDP]. In global switching mode (PowerSwitchingMode=0), only Set/ClearGlobalPower controls this bit. In per-port power switching (PowerSwitchingMode=1), if the PortPowerControlMask[NDP] bit for the port is set, only Set/ClearPortPower commands are enabled. If the mask is not set, only Set/ClearGlobalPower commands are enabled. When port power is disabled, CurrentConnectStatus, PortEnableStatus, PortSuspendStatus, and PortResetStatus should be reset. 0 = port power is off 1 = port power is on (write) SetPortPower The HCD writes a `1' to set the PortPowerStatus bit. Writing a `0' has no effect. Note: This bit is always reads `1b' if power switching is not supported. (read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port. When set, a Low Speed device is attached to this port. When clear, a Full Speed device is attached to this port. This field is valid only when the CurrentConnectStatus is set. 0 = full speed device attached 1 = low speed device attached (write) ClearPortPower The HCD clears the PortPowerStatus bit by writing a `1' to this bit. Writing a `0' has no effect. Reserved 77 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Key Bit Reset HCD/HC CSC 16 0 RW/RW PESC 17 0 RW/RW PSSC 18 0 RW/RW OCIC 19 0 RW/RW Description ConnectStatusChange This bit is set whenever a connect or disconnect event occurs. The HCD writes a `1' to clear this bit. Writing a `0' has no effect. If CurrentConnectStatus is cleared when a SetPortReset, SetPortEnable, or SetPortSuspend write occurs, this bit is set to force the driver to re-evaluate the connection status since these writes should not occur if the port is disconnected. 0 = no change in CurrentConnectStatus 1 = change in CurrentConnectStatus Note: If the DeviceRemovable[NDP] bit is set, this bit is set only after a Root Hub reset to inform the system that the device is attached. PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared. Changes from HCD writes do not set this bit. The HCD writes a `1' to clear this bit. Writing a `0' has no effect. 0 = no change in PortEnableStatus 1 = change in PortEnableStatus PortSuspendStatusChange This bit is set when the full resume sequence has been completed. This sequence includes the 20-s resume pulse, LS EOP, and 3-ms resynchronization delay. The HCD writes a `1' to clear this bit. Writing a `0' has no effect. This bit is also cleared when ResetStatusChange is set. 0 = resume is not completed 1 = resume completed PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis. This bit is set when Root Hub changes the PortOverCurrentIndicator bit. The HCD writes a `1' to clear this bit. Writing a `0' has no effect. 0 = no change in PortOverCurrentIndicator 1 = PortOverCurrentIndicator has changed 78 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Key Bit Reset HCD/HC PRSC 20 0 RW/RW Rsvd 31:21 0 Description PortResetStatusChange This bit is set at the end of the 10-ms port reset signal. The HCD writes a `1' to clear this bit. Writing a `0' has no effect. 0 = port reset is not complete 1 = port reset is complete Reserved 79 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 6.4 EHCI Register Set Configuration Registers Offset 09-0Bh 10-13h 60h 61h 62-63h Register Name USBClassCode BAR SerialBusReleaseNumber FrameLengthAdjust PortWakeCapability Default 24'h0C_0320 32'h400F_C000 8'h20 8'h20 16'h0003 Access RO RO RO RW RW Capability Registers The Capability registers address is calculated by adding the BAR0 base address of the enhanced host controller function to the offset mentioned below. BAR0 (of EHCI function) + <Offset> Offset 00h 01h 02h 04-07h 08-0Bh 0C-13h Register Name CAPLENGTH Reserved HCIVERSION *HCSPARAMS *HCCPARAMS *HCSPPORTROUTE Default 8'h20 Access RO 16'h0100 32'h0000_1191 32'h0000_0016 *** RO RO RO RO * Note: 1. Bit 7 in the HC Structural parameters is I2C programmable. 2. Host Controller Port Route is also I2C programmable. *** Depending on the EHCI function, the default value for HCSPPORTROUTE changes as described below Function Function 1 Function 3 Function 5 Function 7 Value 60'h0 60'h1 60'h2 60'h3 80 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Operational Registers The Operational Registers base address is calculated by adding the value in the Capability Registers Length (i.e. 20h) to the BAR0 base address of the enhanced host controller function and to the offset mentioned below. BAR0 (of EHCI function) + <Capability Registers Length = 20h> + <Offset> Offset 00-03h 04-07h 08-0Bh 0C-10h 14-17h 18-1Bh 40-43h 44-47h Register Name Default 32'h0008_0B00 32'h0000_1000 32'h0000_0000 32'h0000_0007 32'h0000_0000 32'h0000_0000 32'h0000_0000 32'h0000_2000 USBCMD USBSTS USBINTR FRINDEX PERIODICLISTBASE ASYNCLISTADDR CONFIGFLAG PORTSC Access RW RO/RW/RWC RW RW RW RW RW RW 6.4.1 Description of EHCI Capability and Operational Registers USBClassCode Bit 23:16 15:8 7:0 Name Base Class Code Sub Class Code Programming Interface Access RO RO RO Default 0Ch 03h 20h Bit 31:8 7:3 2:1 Name Base Address Rsvd Type Access RO Default 400F_C0h 0 Rsvd Description Serial Bus Controller Universal Serial Bus Host Controller USB2.0 Host controller that conforms to this specification. BAR RO 00b Description Corresponds to memory address signals Reserved 00b--May only be mapped into 32-bit addressing space. 01b--May be mapped into 64-bit addressing space. Reserved SerialBusReleaseNumber Bit 7:0 Name Serial Bus Specification Release Number Access RO Default 20h Description Release of the USB Specification with which this USB Host Controller module is compliant. 81 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller FrameLengthAdjust Bit 7:6 5:0 Name Rsvd Frame Length Timing Value Access RW Default 20h Description Reserved Each decimal value change to this register corresponds to 16-high speed bit times. PortWakeCapability Bit 15:0 Name Port Wake up capability mask Access RW Default 16'h0003 Description Bit position zero of this register indicates whether the register is implemented. A one in bit position zero indicates that the register is implemented. Bit positions 1 through 15 correspond to a physical port implemented on this host controller. For example, bit position 1 corresponds to port 1, position 2 to port 2, etc CAPLENGTH Bit Name Access Default Description This register is used as an offset to add to register base to find the beginning of the Operational Register Space. 7:0 CapLen RO 8'h20 Bit Name Access Default 15:0 IntfVerNum RO 16'h0100 HCIVERSION Description This is a two-byte register containing a BCD encoding of the EHCI revision number supported by this host controller. The most significant byte of this register represents a major revision and the least significant byte is the minor revision. 82 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller HCSPARAMS Bit 31:24 Name Rsvd 23:20 DbgPortNum 19:17 Rsvd 16 Access Default RO 0h PortIndi RO 0h 15:12 NumCompCntrl RO 4'h1 9:8 NumPortCompCntrl RO 4'h1 7 PortRoutRules RO 6 :5 Rsvd 1'b1 Description Reserved Optional. This register identifies which of the host controller ports is the debug port. The value is the port number (one-based) of the debug port. A nonzero value in this field indicates the presence of a debug port. The value in this register must not be greater than N_PORTS Reserved This bit indicates whether the ports support port indicator control. When this bit is a one, the port status and control registers include a read/writeable field for controlling the state of the port indicator. This field indicates the number of companion controllers associated with this USB 2.0 host controller. A zero in this field indicates there are no companion host controllers. Portownership hand-off is not supported. Only high-speed devices are supported on the host controller root ports. This field indicates the number of ports supported per companion host controller. It is used to indicate the port routing configuration to system software. This field indicates the method used by this implementation for how all ports are mapped to companion controllers. 0 - The first N_PCC ports are routed to the lowest numbered function companion host controller, the next N_PCC port are routed to the next lowest function companion controller, and so on 1 - The port routing is explicitly enumerated by the first N_PORTS elements of the HCSP-Port Route Array. Reserved 83 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Bit Name Access Default 4 PortPwrCntrl RO 1'b1 3:0 Nports RO 4'h1 Default Description This field indicates whether the host controller implementation includes port power control. A one in this bit indicates the ports have port power switches. A zero in this bit indicates the port do not have port power switches. This field specifies the number of physical down stream ports implemented on this host controller. HCCPARAMS Bit 31:16 Name Rsvd Access 15:8 EHCIExtCapPtr RO 0h 7:4 IsocSchdThr RO 4'h1 3 Rsvd 2 AsynSchdParkCap RO 1h Description Reserved This optional field indicates the existence of a capabilities list. A value of 00h indicates no extended capabilities are implemented. A non-zero value in this register indicates the offset in PCI configuration space of the first EHCI extended capability This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. When bit [7] is zero, the value of the least significant 3 bits indicates the number of micro-frames a host controller can hold a set of isochronous data structures (one or more) before flushing the state. When bit [7] is a one, then host software assumes the host controller may cache an isochronous data structure for an entire frame Reserved If this bit is set to one, the park mode feature is enabled for High speed queue heads of the asynchronous schedule. 84 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Bit Name Access Default 1 PFLF RO 1h 0 64-bit AddrCap RO 0h Description If this bit is set to a zero, then system software must use a frame list length of 1024 elements with this host controller. The USBCMD register Frame List Size field is a read-only register and should be set to zero. If set to a one, then system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K page boundary. This requirement ensures that the frame list is always physically contiguous. This field documents the addressing range capability of this implementation. The value of this field determines whether software should use the data structures defined in Section 3 (32-bit) or those defined in Appendix B (64-bit). Values for this field have the following interpretation: 0b-- data structures using 32-bit address memory pointers 1b-- data structures using 64-bit address memory pointers HCSPPORTROUTE Register bits for updating bits [3:0] of HCSPPORTROUTE register for each port. Bit Name Access Default 59:0 PortRouteDescNum RO 60'hx Description This field is a 15-element nibble array (each 4 bits is one array element). Each array location corresponds one-to-one with a physical port provided by the host controller (e.g. PORTROUTE[0] corresponds to the first PORTSC port, PORTROUTE[1] to the second PORTSC port, etc. 85 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller USBCMD - USB Command register Bit 31:24 Name Rsvd 23:16 IntThrCntrl 15:12 Rsvd 11 AsynSchdParkModeEnable 10 Rsvd 9:8 AsynSchdParkModeCount Access Default RW 08h RW 0b RW 0b Description Reserved This field is used by system software to select the maximum rate at which the host controller will issue interrupts. The only valid values are defined below. Value - Maximum Interrupt Interval 00h - Reserved 01h - 1 micro-frame 02h - 2 micro-frames 04h - 4 micro-frames 08h - 8 micro-frames 10h - 16 micro-frames (Default, 1ms) 20h - 32 micro-frames (2ms) 40h - 64 micro-frames (8 ms) Reserved 1 - Park mode enabled. 0 - Park Mode is disabled. Reserved It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. 86 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Bit Name Access Default 7 LightHostCntrlReset RW 1b 6 IntrptOnAsyncAdvDoorBell RW 0b Description If implemented, it allows the driver to reset the Host controller without affecting the state of the ports or the relationship to the companion host controllers. For example, the PORSTC registers should not be reset to their default values. A host software read of this bit as one indicates the Light Host Controller Reset has completed and it is safe for host software to re-initialize the host controller. A host software read of this bit as a zero indicates the Light Host Controller Reset has not yet completed. This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule state, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Async Advance Enable bit in the USBINTR register is a one then the host controller will assert an interrupt at the next interrupt threshold. The host controller sets this bit to a zero after it has set the Interrupt on Async Advance status bit in the USBSTS register to a one. Software should not write a one to this bit when the asynchronous schedule is disabled. Doing so will yield undefined results. 87 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Bit Name Access Default 5 AsyncSchdEnable RW 0b 4 PeriodicSchdEnable RW 0b 3:2 FrameListSize RW 00b 1 HCRESET RW 1b 0 RunStop RW 0b Description 0 - Do not process the Asynchronous schedule. 1- Use the ASYNCLISTADDR register to access the Asynchronous schedule. 0 - Do not process the Periodic schedule. 1 - Use the PERIODICLISTBASE register to access the Periodic schedule. This field specifies the size of the frame list. The size the frame list controls which bits in the Frame Index Register should be used for the Frame List Current index. Values mean: 00b - 1024 elements (4096 bytes) Default value 01b - 512 elements (2048 bytes) 10b - 256 elements (1024 bytes) # for resource-constrained environments 11b - Reserved This control bit is used by software to reset the host controller. The effects of this are similar to a Chip Hardware Reset. 1 - Run 0 - Stop USBSTS - USB Status Register Bit 31:16 Name Rsvd Access Default Description Reserved 88 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Bit Name Access Default 15 AsyncSchdStatus RO 0b 14 PeriodicSchdStatus RO 0b 13 Reclamation RO 0b 12 HCHalted RO 1b 11:6 Rsvd 5 IntrptOnAsyncAdv RW 0 Description The bit reports the current real status of the Asynchronous schedule. Zero: The status of the Asynchronous schedule is disabled. One: The status of the Asynchronous schedule is Enabled. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous schedule is either enabled (1) or disabled (0). The bit reports the current real status of the periodic schedule. Zero: The status of the periodic schedule is disabled. One: The status of the periodic schedule is Enabled. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic schedule is either enabled (1) or disabled (0). Used to detect an empty asynchronous schedule. This bit is a zero whenever Run/Stop bit is one. The host controller set this bit to one after it has stopped executing as a result of the Run/Stop bit being set to 0.either by software or by the hardware (e.g. Internal error). Reserved System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source. 89 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Bit Name Access Default 4 HostSysError RW 0 3 FrameListRollover RW 0 2 PortChangeDetect RW 0 1 USBERRINT RW 0 0 USBINT RW 0 Description The Host Controller sets this bit to 1 when a serious error occurs during a host system access involving the Host Controller module. When this error occurs, the Host Controller clears the Run/Stop bit in the Command register to prevent further execution of the scheduled Tds. The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, If the size is 512, the Host Controller sets this bit to a one every time FRINDEX [12] toggles. The Host Controller sets this bit to a one when port has a change bit transition from a zero to a one or a Force Port Resume bit transition from a zero to a one as a result of a J-K transition detected on a suspended port. This bit will also be set as a result of the Connect Status Change being set to a one. This bit is loaded with the OR of all of the PORTSC change bits (including: Force port resume, over-current change, enable/disable change and connect status change). The Host Controller sets this bit to 1 when the completion of a USB transaction results in an error condition. (E.g. Error counters underflow). The Host controller sets this bit to 1 on the completion of a USB transaction, which results in the retirement of a Transfer Descriptor that had its IOC bit set. 90 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller USBINTR -USB Interrupt Enable Register This register enables and disables reporting of the corresponding interrupt to the software. When a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. Interrupt sources that are disabled in this register still appear in the USBSTS to allow the software to poll for events. Bit 31:6 Name Rsvd Access Default 5 IntrptOnAsyncAdvEnable RW 1'b0 4 HostSysErrEnable RW 1'b0 3 FrameListRolloverEnable RW 1'b0 2 PortChangeIntrptEnable. RW 1'b0 Description Reserved When this bit is one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the interrupt on Async Advance bit. When this bit is a one, and the Host System Error Status bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Host System Error bit. When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit. When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged edged by software clearing the Port Change Interrupt bit. 91 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Bit Name Access Default 1 USBErrIntrptEnable RW 1'b0 0 USBIntrptEnable RW 1'b0 Description When this bit is one, and the USBERRINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit. When this bit is alone, and the USBINT bit in the UBSSTS register is one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit. FRAME INDEX - Frame Index register This register is used by the host controller to index into the periodic frame list. The register updates every 125 us (Once each micro-frame). Bits [N:3] are used to select a particular entry in the periodic Frame List during scheduled execution. The number of bits used for the index depends on the size of the frame list as set by system software in the Frame List Size field in the USBCMD register. This register cannot be written unless the Host controller is in the Halted state. SOF frame number value for the bus SOF token is derived from this register. The value of FRINDEX must be 125 us ahead of the SOF token value. Bit 31:14 Name Rsvd Access 13:0 FrameIndex RW Default 0b Description 0000_0000h Reserved The value in this register increment at the end of each time frame (e.g. Microframe). Bits [N: 3] are used for the Frame List current index. This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. The following illustrates values on N based on the value of the Frame List Size in the USBCMD register. USBCMD 00b 01b 10b 11b Elements 1024 512 256 Reserved 92 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. N 12 11 10 MCS9990 PCIe to 4-Port USB 2.0 Host Controller PERODICLISTBASE - Periodic Frame List Base Address Register This 32-bit register contains the beginning address of the Periodic frame List in the system memory. System software loads this register prior to starting the schedule execution by the Host controller. The Memory structure referenced by this physical memory pointer is assumed to be 4-K byte aligned. The contents of this register are combined with the Frame Index register (FRINDEX) to enable the Host Controller to step through the Periodic Frame List in sequence. Bit Name Access Default 31:12 BaseAddr RW 20'h0 11:0 Rsvd Description These bits correspond to memory address signals [31:12], respectively. Reserved ASYNCLISTADDR - Current Asynchronous List Address register This 32-bit register contains the address of the next asynchronous queue head to be executed. Bits [4:0] of this register cannot be modified by the system software and will always return a zero when read. The memory structure referenced by this physical memory pointer is assumed to be 32-byte aligned. Bit Name Access Default 31:5 LinkPtr RW 27'h0 4:0 Rsvd Description These bits correspond to memory address signals [31:5] respectively. This field may only reference Queue Head (QH). Reserved CONFIGGLAG - Configuration Flag Register Bit Name Access Default 0 ConfigFlag RW 0b 31:1 Rsvd Description This bit controls the default port-routing control logic. Host software sets this bit as the last action in its process of configuring the host controller Reserved PORTSC - Port Status and Control register A host controller must implement one or more port registers. Software uses this information as an input parameter to determine how many ports need to be serviced. 1.1 Initial Conditions of a port 1.2 No device connected 1.3 Port disabled. 93 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller If the port has port power control, software cannot change the state of the port until after it applies power to the port by setting port power to 1. The host is required to have power stable to the port within 20milliseconds of the zero to one transition. Bit 31:23 Name Rsvd Access Default 22 WKOCE RW 0b 21 WKDSCNNTE RW 0b 20 WKCNNTE RW 0b 19:16 PortTestControl RW 0000b 15:14 PortIndiCntrl 13 PortOwner RW 1b 12 PortPower RW 1'b0 00b Description Reserved Wake on Over-current Enable. Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. Writing this bit to a one enables the port to be sensitive to device disconnects as wakeup events. Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. When this field is zero, the port is NOT operating in test mode. 0000b - Test mode not enabled. 0001b - Test J_STATE 0010b - Test K_STATE 0011b - Test SE0_NAK 0100b - Test Packet 0101b - Test FORCE_ENABLE Writing to these bits has no effect if the P_INDICTAOR bit in the HCPARAMS register is a zero. This bit unconditionally goes to a 0b when the configured bit in the CONFIGFLAG register makes a 0b to 1b transition Host controller has port power control switches. This bit represents the current setting of the switch (0=Off, 1=On). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches etc. 94 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Bit Name 11:10 LineStatus Access Default RO Description These bits reflect the current logical levels of the D+ and D- signal lines. These bits are used for detection of lowspeed USB devices prior to the port reset and enable sequence. This field is valid only when the port enable bit is zero and the current connect status bit is set to a one. The encoding of the Bits[11:10] are Value USB State 9 Rsvd 8 PortReset RW 1'b0 7 Suspend RW 1'b0 6 ForcePortResume RW 1'b0 5 OverCurrentChange RWC 0b 4 OverCurrentActive RO 0b 3 PortEnableDisableChange RWC 0b 00b SE0 01b J_STATE 10b K_STATE 11b Undefined Interpretation Not Low-speed device, perform reset Not Low-speed device, perform reset Not Low-speed device, perform reset Not Low-speed device, perform reset Reserved 1 - Port is in reset 0 - Port is not in reset 1 - Port is in suspend 0 - Pot not in suspend state 1 - Resume detected/driven on port 0 - No resume (K_STATE) detected/driven on port This bit gets set to a one when there is a change to Over-Current Active. Software clears this bit by writing to a one to this bit position 1 = This port currently has an over current condition 0 = This port does not have an over-current condition. 1 = Port enabled/disabled status has changed. 0 = No change. For the root hub, this bit gets set to a one only when a port is disabled due to the appropriate conditions existing at the EOF2 point. 95 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Bit Name Access Default 2 PortEnableDisable RW 1 ConnectStatusChange RWC 0 CurrentConnectStatus RO 0b 0b Description Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. The host controller will only set this bit to a one when the reset sequence determines that the attached device is a high-speed device. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled (0b) downstream propagation of data is blocked on this port, except for reset. This field is zero if Port Power is zero. 1 = Change in current Connect status. 0 = No change. 1 = Device is present on port 0 = No device is present 96 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 6.5 OTG Register Set BAR0 (of OTG function) + <Offset> Offset Register Name Default Category 00-03h OTGDevIntEnable 32'h0000_0000 Device 04-07h OTGDevIntStatus 32'h0000_0000 Device 08-0Bh OTGDevStateAdd 32'h0004_1000 Device 0C-0Fh 10-13h CntrlEPReqBaseAdd CntrlInTDBaseAdd 32'h0000_0000 32'h0000_0000 Device Device 14-17h IntEP1Cntrl 32'h0000_0200 Device 18-1Bh IntEP1TDBaseAdd 32'h0000_0000 Device 1C-1Fh BulkInEP2Cntrl 32'h0000_0200 Device 20-23h BulkInEP2TDBaseAdd 32'h0000_0000 Device 24-27h BulkOutEP3Cntrl 32'h0000_0000 Device 28-2Bh BulkOutEP3BaseAdd 32'h0000_0000 Device 2C-2Fh EPTDCount 32'h0000_0000 Device 30-33h OTGControl 32'h0000_00C0 OTG 34-37h OTGIntEnable 32'h0000_0000 OTG 38-3Bh OTGIntStatus 32'h0000_0000 OTG 3C-3Fh IDSampling 32'h002D_C46A OTGBConnectLongDebo 32'h005B_88D0 unce OTG 44-47h OTGDataLinePulse Time 32'h0004_C471 OTG 48-4Bh OTGChargeVBUS 32'h001B_7740 OTG 4C-4Fh 50-53h 54-57h 58-5Bh BulkInEP4Cntrl BulkInEP4BaseAdd BulkOutEP5Cntrl BulkOutEP5BaseAdd 32'h0000_0000 32'h0000_0000 32'h0000_0000 32'h0000_0000 Device Device Device Device 70-73h BulkInEPMaxPacketSize 32'h0000_0200 Device 40-43h OTG Description Device interrupt enable Register Device interrupt register Device state Address register Control IN Register Control Out Register Endpoint 1 Control Register Endpoint 1 Base Address Endpoint 2 Control Register Endpoint 2 Base Address Endpoint 3 Control Register Endpoint 3 Base Address End point TD count register OTG Controller register OTG interrupt enable register OTG interrupt status register ID Sampling Register OTG B-connect long debounce Register OTG Data line pulse time Register OTG charge VBUS register EP4 Control EP4 Base Address EP5 Control EP5 Base Address Bulk in endpoint max packet size register 97 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Offset Register Name Default Category 74-77h USBDevEPCntrl 32'h0000_0001 Device 78-7Ch 7C-7Fh BulkOutEP3SoftTimer BulkOutEP5SoftTimer 32'h0000_0000 32'h0000_0000 Device Device 84-87h CntrlOutEPTDBaseAdd 32'h0000_0000 Device Description Bulk endpoint control register EP3 soft timer register EP5 soft timer register Control Out EP transfer descriptor base address register 6.5.1 Description of OTG Device Registers OTGDevIntEnable This register will help to enable or disable interrupts on various events. A value of '1' will enable a specific interrupt, while a '0' will disable it. Bit 31:11 Rsvd 10 9 8 7 6 5 4 3 2 1 0 Name Access Default Description RW 0h Reserved Setting this bit to `1' enables the CntrlOUTEPIntrptEn RW 1'b0 Control OUT endpoint (EP) data stage interrupt. Setting this bit to `1' enables the BulkOutEP5IntrptEn RW 1'b0 Bulk OUT (EP5) interrupt Setting this bit to `1' enables the BulkInEP4IntrptEn RW 1'b0 Bulk IN (EP4) interrupt Setting this bit to `1' enables USB HostResetDetect RW 1'b0 protocol reset interrupt. Setting this bit to `1' enables USB HostResumeDetectIntrptEn RW 1'b0 resume interrupt Setting this bit to `1' enables USB SuspendDetectIntrptEn RW 1'b0 suspend interrupt. Setting this bit to `1' enables the BulkOutEP3IntrptEn RW 1'b0 Bulk OUT (EP3) interrupt Setting this bit to `1' enables the BulkInEP2IntrptEn RW 1'b0 Bulk IN (EP2) interrupt Setting this bit to `1' enables the IntrptEP1IntrptEn RW 1'b0 Interrupt IN (EP1) interrupt When set device controller CntrlEPReqPacketIntrptEn RW 1'b0 generates an interrupt, for control endpoint setup stage packet Setting this bit to `1' enables the CntrlInEPIntrptEn RW 1'b0 Control IN endpoint (EP) data stage interrupt. 98 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller OTGDevIntStatus This register will give status of all the interrupts. The events generating the interrupt are same as listed above. Writing a value of '1' to a specific bit will clear the status to '0'. Bit 31:11 Rsvd 10 9 8 7 6 5 4 3 2 Name Access Default Description 0h Reserved Setting this bit to `1' indicates USB Device Control OUT endpoint (EP0) CntrlOutEP0DataIntrpt RWC 1'b0 DMA transfer completion from hardware buffer to system memory Setting this bit to `1' indicates USB Device Bulk OUT endpoint (EP5) BulkOutEP5DataIntrpt RWC 1'b0 DMA transfer completion from hardware buffer to system memory Setting this bit to `1' indicates USB Device Bulk IN endpoint (EP4) DMA BulkInEP4DataIntrpt RWC 1'b0 transfer completion from system memory to hardware buffer Setting this bit to `1' indicates USB USBHostResetDetectIntrpt RWC 1'b0 protocol Reset signaling from peer USB host Setting this bit to `1' indicates USB USBHostResumeDetectIntrpt RWC 1'b0 Resume signal detection during device suspend Setting this bit to `1' indicates USB USBDevSuspendIntrpt RWC 1'b0 device is in suspend state. Setting this bit to `1' indicates USB Device Bulk OUT endpoint (EP3) BulkOUTEP3DataIntrpt RWC 1'b0 DMA transfer completion from hardware buffer to system memory. Setting this bit to `1' indicates USB Device Bulk IN endpoint (EP2) DMA BulkInEP2DataIntrpt RWC 1'b0 transfer completion from system memory to hardware buffer. Setting this bit to `1' indicates USB Device Interrupt IN endpoint (EP1) IntrptInEP1DataIntrpt RWC 1'b0 DMA transfer completion from system memory to hardware buffer. 99 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Bit Name Access Default 1 CntrlInEP0DataIntrpt RWC 1'b0 0 CntrlEP0SetupStageIntrpt RWC 1'b0 Description Setting this bit to `1' indicates USB Device Control IN endpoint (EP0) DMA data transfer completion from system memory to hardware buffer. Setting this bit to `1' indicates USB Device control endpoint (EP0) setup stage packet DMA transfer completion from hardware buffer to system memory. OTGDevStateAdd Bit 31:20 Name Rsvd Access Default 19 SetAddr RW 1'b0 18 DevSpeed RO 1'b1 17 ConfigDone RW 1'b0 16 ClearOutPID RW 1'b0 15:13 Rsvd R0 3'b000 12 DevReset RW 1'b1 11:8 Test RW 1'b0 Description Reserved Used to retain the default address during USB set address command. Software sets this bit to `1' after receiving USB set address command from external host. Hardware clears this bit to `0' after sending the zero length packets for USB set address command in status stage. Note: The access of set address as well as device address is to be done simultaneously. 1 - Indicates that device operates in Full Speed mode. 0 - indicates that device operates in High Speed mode. Configuration done. It is set by the software when it configured the get descriptors. Setting this bit to `1' clears Bulk OUT PID check logic. This bit is self cleared. Reserved Device reset bit. USB Device Soft Reset Control bit. Writing this bit to `0' resets USB device controller. Test signal for USB device controller Test[8] = 1, Test J_STATE Test[9] = 1, Test K_STATE Test[10] = 1, Test SE0_NAK Test[11] = 1, Test Packet 100 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Bit 7 Name Rsvd Access RO Default 1'b0 6:0 DevAddr RW 7'h0 Description Reserved It represents USB Device address. Note: This is to be updated whenever the set address is accessed. CntrlEPReqBaseAdd The Control Endpoint functionality is implemented with the help of 2 registers 'Control Data IN' and 'Control Data OUT'. All the Control Requests will be handled in software. Bit Name Access Default 31:2 AddrPtr RW 30'h0 1:0 Rsvd RW 0h Description System software allocates a chunk of memory large enough to accept an incoming Control request and write the memory base address in this register Reserved CntrlInTDBaseAdd When a Control Request comes, the hardware will generate an ACK in the Setup stage, copies the request in the memory pointed by Control Data IN register and raise an interrupt to indicate this to the software. The software will decode the request and prepare the data to be sent in the response. The software will store this response data in a memory buffer which is DWORD aligned. Then it will write to the Control Data OUT register with ACK and Done bit set. If there was any error while processing the request, it will reset the ACK bit and set the done bit, which will result in STALL being sent out. Bit Name Access Default 31:2 AddrPtr RW 30'h0 1 ACK RW 0b 0 Done RW 0b Description System software writes this register with Control IN TD base pointer. It is DWORD aligned address. This bit gives the response code to be sent in the Data or Status stage. 1 = ACK 0 = STALL This bit is set by the system software when it has completed the control request processing. This bit is self clearing. 101 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller IntEP1Cntrl This register holds some important fields of Endpoint Descriptor as described below: Bit Name Access Default Description Software writes `1' to this bit to enable Interrupt IN endpoint. This endpoint and the 31 Enable RW 0h related 2 registers are valid only if this bit is set. 30:23 Interval RW 0h Interval for polling the endpoint for data transfers. Expressed in frames of microframes depending on the device operating speed. 22:14 Rsvd 0h Reserved When Set to `1' STALL response is sent for 13 EPStall RW 0h Interrupt EP request. Max packet size indicates that this endpoint is capable of sending or receiving those many 3'b011 number of bytes when this configuration is for EP0 selected and EP1 3'b000 - 8bytes 3'b001 - 16bytes 12:10 MaxPacketSize RW 3'b110 3'b010 - 32bytes 3'b011 - 64bytes for EP2,3,4, 3'b100 - 128bytes 3'b101 - 256bytes 5 3'b110 - 512bytes 3'b111 - 1024bytes 9 Direction RO 1b 1 = IN endpoint 8:5 Number RW 0h It represents the endpoint number 4:3 Rsvd RO 0h Reserved 2:0 Type RW 0h Endpoint Descriptor Type The endpoint is valid only when the Enable bit (31) is set. IntEP1TDBaseAdd The Base Address Register, as the name implies, contains the base address or the pointer to the memory in the system area. The software will allocate the memory required for that endpoint operation and initialize this register with the memory address. Bit Name Access Default 31:0 BaseAddr RW 0h Description Software writes the Interrupt IN TD base pointer value in this register 102 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller BulkInEP2Cntrl This register holds some important fields of Endpoint Descriptor as described below: The endpoint is valid only when the Enable bit (31) is set. Bit Name Access Default 31 Enable RW 0h 30:23 Interval RW 0h 22:14 Rsvd 13 EPStall 0h RW 0h 3'b011 for EP0 and EP1 12:10 MaxPacketSize RW 9 8:5 4:3 2:0 Direction Number Rsvd Type RO RW RW 3'b110 for EP2,3,4, 5. 1b 0h 0h 0h Description Software writes `1' to this bit to enable Interrupt IN endpoint. This endpoint and the related 2 registers are valid only if this bit is set. Interval for polling the endpoint for data transfers. Expressed in frames of microframes depending on the device operating speed. Reserved STALL response to be sent for corresponding end point. Max packet size indicates that this endpoint is capable of sending or receiving those many number of bytes when this configuration is selected. 3'b000 - 8bytes 3'b001 - 16bytes 3'b010 - 32bytes 3'b011 - 64bytes 3'b100 - 128bytes 3'b101 - 256bytes 3'b110 - 512bytes 3'b111 - 1024bytes 1 = IN endpoint It represents the endpoint number Reserved Endpoint Descriptor Type BulkInEP2TDBaseAdd The Base Address Register, as the name implies, contains the base address or the pointer to the memory in the system area. The software will allocate the memory required for that endpoint operation and initialize this register with the memory address. Bit Name Access Default 31:2 AddrPtr RW 30'h0 1 Rsvd RW 0h Description It points to the Bulk IN EP transfer descriptor linked list. Reserved 103 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Bit Name Access Default 0 TDValidBit RW 0h Description Software sets this bit after preparing the data structures for associate Endpoint. When this bit is set, hardware loads the software written base address register into local hardware TD base address register, if local hardware TD base address register contains NULL pointer. Hardware clears this bit after loading the base address register value. BulkOutEP3Cntrl This register holds some important fields of Endpoint Descriptor as described below: The endpoint is valid only when the Enable bit (31) is set. Bit Name Access Default 31 Enable RW 0h 30:23 Interval RW 0h 22:14 Rsvd 13 EPStall 0h RW 0h 12:10 MaxPacketsize RW 3'b011 for EP0 and EP1 3'b110 for EP2,3,4, 5. 9 8:5 4:3 2:0 Direction Number Rsvd Type RO RW R RW 0b 0h 0h 0h Description This endpoint and the related 2 registers are valid only if this bit is set. Interval for polling the endpoint for data transfers. Expressed in frames of micro frames depending on the device operating speed. Reserved STALL response is sent for corresponding end point. Max packet size indicates that this endpoint is capable of sending or receiving those many number of bytes when this configuration is selected 3'b000 - 8bytes 3'b001 - 16bytes 3'b010 - 32bytes 3'b011 - 64bytes 3'b100 - 128bytes 3'b101 - 256bytes 3'b110 - 512bytes 3'b111 - 1024bytes 0 = OUT endpoint It represents the endpoint number Reserved Endpoint Descriptor Type 104 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller BulkOutEP3BaseAdd The Base Address Register, as the name implies, contains the base address or the pointer to the memory in the system area. The software will allocate the memory required for that endpoint operation and initialize this register with the memory address. Bit Name Access Default 31:2 AddrPtr RW 30'h0 1 Rsvd RW 0h 0 TDValidBit RW 0h Description It points to the Bulk OUT EP transfer descriptor linked list. Unused Software sets this bit after preparing the data structures for associate Endpoint. When this bit is set, hardware loads the software written base address register into local hardware TD base address register, if local hardware TD base address register contains NULL pointer. Hardware clears this bit after loading the base address register value EPTDCount EP0 TD count is for Control end point, which is incremented by software and it is decremented by hardware. EP1 data available for Interrupt end point, which is updated by software and it is cleared by hardware Bit 31:29 Name Rsvd Access Default 3'b000 8 EP1DataAvailable RW 1'b0 7:5 4:0 Rsvd EP0TDCount RW 3'b000 5'b00000 Description Reserved Interrupt Endpoint EP1 TD data available register Reserved Control Endpoint EP0 TD count register. OTGControl Note: Hardware Read Only. Software Read/Write Bit Name Access Default Device 0 ABusDrop RW 1'b0 A-device Description A-device bus drop. Writing `1' to this bit drops the power to USB bus. This is applicable to OTG Adevice 105 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Bit Name Access Default Device 1 ABusReq RW 1'b0 A-device 2 ASetBHNPEn RW 1'b0 A-device 3 Rsvd RW 1'b0 4 BHNPEn RW 1'b0 B-device 5 BBusReq RW 1'b0 B-device 6 SRPDetEn RW 1'b1 A-device 7 Rsvd 8 DevSuspendDisa ble RW 1'b0 A-device 31:9 Rsvd - 'b0 - Description A-device bus request. Writing `1' to this bit enables the USB bus power. This is applicable to OTG A- device . A-device set BHNPEn. OTG A-device sets this bit at the same time when it sets BHNPEn bit in the B-device. Reserved Setting this feature indicates to the B-device that it has been enabled to perform HNP. An Adevice sets this feature if, and only if, the B-device is connected directly to an A-device port that supports HNP. B-device bus request. B-device application sets this bit when it wants to use the bus. It clears when application running on the B-device does not want to use the bus. Writing `1' to this bit enables the SRP detection at the OTG Adevice. SRP Detection Enable is used by A-Device. This bit will be set and cleared by software. Reserved Software running on A-device clears this bit when it does not want to enable suspend detection logic. Writing `1' to this bit enables suspend detection logic Reserved 106 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller OTGIntEnable Bit 31:18 Name Access Default Rsvd 17 IDPinVldIntrptEn RW 1'b0 16 AConnIntrptEn RW 1'b0 15 BConnIntrptEn RW 1'b0 14 SessionReqDoneIntrptEn RW 1'b0 13 AVbusErrIntrptEn RW 1'b0 12 DevNoResponseIntrptEn RW 1'b0 11 PeripheralOnIntrptEn RW 1'b0 10 HostOnIntrptEn RW 1'b0 9 ASessVldIntrptEn RW 1'b0 8 BSessVldIntrptEn RW 1'b0 7 AVbusVldIntrptEn RW 1'b0 6 IDIntrptEn RW 1'b0 5 ABusResumeIntrptEn RW 1'b0 4 BBusResumeIntrptEn RW 1'b0 3 ABusSuspendIntrptEn RW 1'b0 2 BBusSuspendIntrptEn RW 1'b0 1 BSessEndIntrptEn RW 1'b0 0 ASRPDetIntrptEn RW 1'b0 Description Reserved Setting this bit to `1' enables ID pin valid interrupt. Setting this bit to `1' enables Adevice connect interrupt. Setting this bit to `1' enables Bdevice connect interrupt. Setting this bit to `1' enables Session request done interrupt Setting this bit to `1' enables Adevice Vbus error interrupt Setting this bit to `1' enables Device no response interrupt Setting this bit to `1' enables Peripheral on interrupt Setting this bit to `1' enables Host on interrupt Setting this bit to `1' enables Adevice session valid interrupt. Setting this bit to `1' enables Bdevice session valid interrupt. Setting this bit to `1' enables Adevice VBUS valid interrupt. Setting this bit to `1' enables Identification bit interrupt. Setting this bit to `1' enables Adevice bus resume interrupt. Setting this bit to `1' enables Bdevice bus resume interrupt. Setting this bit to `1' enables Adevice bus suspend interrupt. Setting this bit to `1' enables Bdevice suspend interrupt enable. This bit is asserted when there is a change in B-device session end bit in OTG status register. Setting this bit to `1' enables Bdevice session end interrupt. Setting this bit to `1' enables Adevice SRP detect interrupt. 107 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller OTGIntStatus Bit Name Access Default 31 IDPinVld RO 1'b0 30 IDDig RO 1'b1 29 HostOn RO 1'b0 28 PeripheralOn RO 1'b0 27:18 Rsvd 17 IDPinVldP RWC 1'b0 16 AConnP RWC 1'b0 15 BConnP RWC 1'b0 14 SessionRequestDoneP RWC 1'b0 13 AVbusErrP RWC 1'b0 12 DevNoResponseP RWC 1'b0 11 PeripheralOnPn RWC 1'b0 10 HostOnPn RWC 1'b0 9 ASessVldP RWC 1'b0 8 BSessVldP RWC 1'b0 7 AVbusVldP RWC 1'b0 6 IDDigPn RWC 1'b0 5 ABusResume RWC 1'b0 4 BBusResume RWC 1'b0 Description `1' indicates OTG Identification pin valid signaling This bit reflects the logical level of the ID pin. `1' indicates OTG device is operating in host mode `1' indicates OTG device is operating in peripheral mode. Reserved `1' indicates ID pin has changed from logical state `0' to `1' `1' indicates A-device connect signaling `1' indicates B-device connect signaling `1' indicates B-device SRP session request completion signaling `1' indicates A-device VBUS error signaling `1' indicates device no response signaling `1' indicates peripheral mode change signaling `1' indicates host mode change signaling. `1' indicates A-device session is valid. `1' indicates B-device session is valid. `1' indicates A-device VBUS valid signaling. Hardware asserts this bit to `1' when it detects a change in identification pin logical value '1' indicates A-device has detected USB resume signaling '1' indicates B-device has detected USB resume signaling 108 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Bit Name Access Default 3 ABusSuspend RWC 1'b0 2 BBusSuspend RWC 1'b0 1 BSessEndP RWC 1'b0 0 ASRPDetP RWC 1'b0 Description '1' indicates A-device has detected USB suspend signaling '1' indicates B-device has detected USB suspend signaling. `1' indicates B-device session end signaling on positive edge change. `1' indicates A-device has detected SRP request from the Bdevice on positive edge. BulkInEP4Cntrl This register holds some important fields of Endpoint Descriptor as described below: Bit Name Access Default 31 Enable RW 0h 30:23 Interval RW 0h 22:14 Rsvd 13 12:10 9 8:5 4:3 2:0 0h EPStall RW 0h MaxPacketSize RW 3'b011 for EP0 and EP1 3'b110 for EP2, 3, 4, 5. Direction Number Rsvd Type RO RW R RW 1b 0h 0h 0h Description Software writes `1' to this bit to enable Interrupt IN endpoint. This endpoint and the related 2 registers are valid only if this bit is set. Interval for polling the endpoint for data transfers. Expressed in frames of micro frames depending on the device operating speed. Reserved STALL Request response to be sent for corresponding end point. Max packet size indicates that this endpoint is capable of sending or receiving those many number of bytes when this configuration is selected 3'b000 - 8bytes 3'b001 - 16bytes 3'b010 - 32bytes 3'b011 - 64bytes 3'b100 - 128bytes 3'b101 - 256bytes 3'b110 - 512bytes 3'b111 - 1024bytes 1 = IN endpoint It represents the endpoint number Reserved Endpoint Descriptor Type 109 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller The endpoint is valid only when the Enable bit (31) is set. BulkInEP4BaseAdd The Base Address Register, as the name implies, contains the base address or the pointer to the memory in the system area. The software will allocate the memory required for that endpoint operation and initialize this register with the memory address. Bit Name Access Default 31:2 AddrPtr RW 30'h0 1 Reserved RW 0h 0 TDValidBit RW 0h Description It points to the Bulk IN EP transfer descriptor linked list. Reserved Software sets this bit after preparing the data structures for associate Endpoint. When this bit is set, hardware loads the software written base address register into local hardware TD base address register, if local hardware TD base address register contains NULL pointer. Hardware clears this bit after loading the base address register value. BulkOutEP5Cntrl This register holds some important fields of Endpoint Descriptor as described below: Bit Name Access Default 31 Enable RW 0h 30:23 Interval RW 0h 22:14 Rsvd 13 EPStall 0h RW 0h Description This endpoint and the related 2 registers are valid only if this bit is set. Interval for polling the endpoint for data transfers. Expressed in frames of microframes depending on the device operating speed. Reserved STALL Request response is sent for corresponding end point. 110 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Bit Name Access Default 12:10 MaxPacketSize RW 3'b011 for EP0 and EP1 3'b110 for EP2, 3, 4, 5. 9 8:5 4:3 2:0 Direction Number Rsvd Type RO RW R RW 0b 0h 0h 0h Description Max packet size indicates that this endpoint is capable of sending or receiving those many number of bytes when this configuration is selected 3'b000 -- 8bytes 3'b001 - 16bytes 3'b010 - 32bytes 3'b011 - 64bytes 3'b100 - 128bytes 3'b101 - 256bytes 3'b110 -- 512bytes 3'b111 - 1024bytes 0 = OUT endpoint It represents the endpoint number Reserved Endpoint Descriptor Type The endpoint is valid only when the Enable bit (31) is set. BulkOutEP5BaseAdd The Base Address Register, as the name implies, contains the base address or the pointer to the memory in the system area. The software will allocate the memory required for that endpoint operation and initialize this register with the memory address. Bit Name Access Default 31:2 AddrPtr RW 30'h0 1 Rsvd RW 0h 0 TDValidBit RW 0h Description It points to the Bulk OUT EP transfer descriptor linked list. Reserved Software sets this bit after preparing the data structures for associate Endpoint. When this bit is set, hardware loads the software written base address register into local hardware TD base address register, if local hardware TD base address register contains NULL pointer. Hardware clears this bit after loading the base address register value. 111 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller BulkInEPMaxPacketSize Bit 9:0 31:10 Name BulkInEPMaxPa cketSize Rsvd Access Default RW 200h Description Software writes this register with supported Bulk In max packet size value Reserved USBDevEPCntrl Bit Name Access Default 0 CntrlOutEPEnable RW 1h RW 0h RW 0h 1 2 3 BulkOutEP3TimeOut IntrptEnable BulkOutEP5TimeOut IntrptEnable Rsvd 4 BulkInEP2DataToggleEnab le RW 0h 5 BulkInEP4DataToggleEnab le RW 0h Description Writing `1' to this bit enables Control OUT endpoint logic Writing `1' this bit enable Bulk out endpoint3 time out interrupt logic Writing `1' this bit enable Bulk out endpoint5 time out interrupt logic Reserved Writing `1' to this bit enables the hardware to load the data toggle bit from the Bulk IN EP2 data structure Writing `1' to this bit enables the hardware to load the data toggle bit from the Bulk IN EP4 data structure. BulkOutEP3SoftTimer Bit Name Access Default 31:0 BulkEP3SoftTimer RW 0h Description Software loads this register with a 32-bit value. USB deice waits for the reception of bulk out packet, until this timer expires. It generates a bulk time out interrupt to the system if it does not receive a packet during this time. 112 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller BulkOutEP5SoftTimer Bit Name Access Default 31:0 BulkEP5SoftTimer RW 0h Description Software loads this register with a 32-bit value. USB device waits for the reception of bulk out packet, until this timer expires. It generates a bulk time out interrupt to the system if it does not receive a packet during this time. CntrlOutEPTDBaseAdd Bit Name Access Default 31:2 AddrPtr RW 30'h0 1:0 Rsvd RW 0h Description System software will allocate a chunk of memory large enough to accept an incoming Control Out EP data and write the address in this register. Reserved 113 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 6.6 GPIO Register Set If EEPROM is present and signature ID matches then the DIR register gets updated with the EEPROM contents present in the location from 143-145h, similarly PIN register gets updated with EEPROM contents present in the location from 146-148h. Address for accessing the GPIO registers in 2USB+OTG+GPIO is BAR0 + 16'h0800 + Offset as mentioned. These registers cannot be accessed in any other mode. Offset Name Type Default 140h PIN RW N/A 144h DIR RW 24'hFF_FFFF 148h EventMode RW 24'h00_0000 14Ch OpenDrain RW 24'h00_000 150h PullUp RW 24'h00_0000 154h EventDetect RW 24'h00_0000 Functional Description When DIR bits are ones, gives Pin [7:0] bit values and when DIR bits are zeros, writing this register sets the pin out values. Default all pins are in input mode. 1: To detect '0' to '1' transition on the PINS. 0: To detect '1' to '0' transition on the PINS. (DIR bits should be set to input mode). Controls open drain connectivity of GPIO pads. 1: Enable Open Drain 0: Disable Open Drain Controls pull up connectivity to GPIO pads. 1: Enable Pull Up 0: Disable Pull Up Event detect status on the GPIO lines. Set when there is event on GPIO line of which corresponding EVENT EN bit is set and DIR bits should be set to input mode. 1: Event Occurred 0: No event Once event occurs, write on the same bit to clear the interrupt. 114 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Offset Name Type Default 158h EventEN RW 24'h00_0000 160h PINPS RW N/A 164h DIRPS RW 24'h00_0000 168h EventModePS RW 24'h00_0000 16Ch OpenDrainPS RW 24'h00_000 170h PullUpPS RW 24'h00_0000 Functional Description Enable the event detection on GPIO line. 1: Enable event detection 0: Disable event detection When PIN SELECT bit is high, when DIR bit is one, gives Pin bit value for the selected pin and when DIR bits is zero, writing to the LSB of this register sets the pin out value for the selected pin. When PIN SELECT bit is high, writing at the LSB of register, sets the direction for the selected pin. When PIN SELECT bit is high, 1 : To detect '0' to '1' transition on the PINS. 0 : To detect '1' to '0' transition on the PINS. (DIR bit should be set to input mode). When PIN SELECT bit is high, controls open drain connectivity of selected GPIO pad. 1: Enable Open Drain 0: Disable Open Drain When PIN SELECT bit is high, controls pull up connectivity to selected GPIO pad. 1: Enable Pull Up 0: Disable Pull Up 115 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Offset Name Type Default 174h EventDetectPS RW 24'h00_0000 178h EventENPS RW 24'h00_0000 17Ch PINSelect RW 24'h00_0000 180h EventDetectCntrl RW 24'hFF_FFFF Functional Description When PIN SELECT bit is high, gives event detect status on the selected GPIO line. Set when there is event on GPIO line of which corresponding EVENT EN bit is set and DIR bits should be set to input mode. 1: Event Occurred 0: No event Once event occurs, write on the same bit to clear the interrupt. When PIN SELECT bit is high, enable the event detection on GPIO line. 1: Enable event detection 0: Disable event detection When any bit is set then particular pin is only selected for any operation. To enable the event detection (both positive & negative edge) on the particular GPIO line. 116 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 6.7 ISA Register Set Offset Name Type 104h ISABridgeReg RW Default Description ISACountReg : 8-bit register which stores read-write counter information ISABrdgReg : 8-bit register which stores mode selection information 6.7.1 Description of ISA Bridge Registers ISABridgeReg Bit Name Default 0 ISARstSel = ISABrdgReg[0] 1'b1 1 ISAModeSel = ISABrdgReg[1] 1'b1 2 ISAAddPPSel = ISABrdgReg[2] 1'b0 3 4 5 6 7 11:8 15:12 31:16 ISAUARTSel = ISABrdgReg[3] ISADualUARTSel = ISABrdgReg[4] ISAQuadUARTSel = ISABrdgReg[5] ISAPP1Prsnt = ISABrdgReg[6] ISAPP2Prsnt = ISABrdgReg[7] ISARdCount = ISACountReg[3:0] ISAWrCount = ISACountReg[7:4] Rsvd 1'b0 1'b0 1'b0 Description High in case of Active High Reset for the device to be connected (Default case). Low in case of Active Low reset for the device to be connected. Mode Selection bit. High in case of Intel mode (Default case). Low in case of Motorola mode. Used to generate an extra address line used if parallel port is configured & need extra address line to configure ECP mode. Work in Motorola mode. High in case of single UARTs are connected through ISA interface. Work in Motorola mode. High in case of DUAL UARTs are connected through ISA interface. Work in Motorola mode. High in case of QUAD UARTs are connected through ISA interface. 1'b0 Parallel port is present on Port-A of ISA Interface 1'b0 Parallel port is present on Port-C of ISA Interface 4'd4 4'd4 16'd0 Read counter to made flexibility in changing the width of read signal. Write counter to made flexibility in changing the width of write signal. Reserved 117 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 6.8 EEPROM Access Register Set Address for accessing the register is BAR0 + 16'h0800 + Offset as mentioned below in all the modes, except for 2USB+OTG+ISA opmode where address will be BAR4 + 16'h0800 + Offset. Offset Name Type 100h I2C RW Default Description Contains information read or write access to EEPROM. 6.8.1 Description of I2C Registers I2C Bit Name Default 7:0 I2CData 8'h00 23:8 I2CAdrs 16'h00 24 I2C8-16BitAdrs 1'b1 30:25 I2CDeviceAdrs 6'h28 I2CWRN/ I2CError 1'b0 31 Description During the write operation write data has to be placed and during read operation read data is placed. I2C address needs to be sent on I2C lines to access EEPROM. 8 -16 bit addressing of EEPROM. 1'b1 - 16 bit addressing. 1'b0 - 8 bit addressing. EERPROM device address. I2C read or write operation. 1'b0 - Read Operation 1'b1 - Write Operation. This bit is read as one when there is no EEPROM indicating eeprom error. 118 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 6.9 Miscellaneous Register Set Offset Register Name Type D0h LinkCapRevID D4h ConfigSpaceUpdate R 108h PwrMgtCntrl R 10Ch ConfigSpaceBaseAdrs R 110h TrafficClass R 114h KGbl1 R 118h KGbl2 R 11Ch 120h 124h PCIeTest BridgeCntrl EepromMaxReadreqSZ R R RW 128h PwrMgtAdvErrSupport R NA WakeCount Default RW NA 12Ch KPtr01 R 130h KPtr02 R 134h ReplayAckTimer R 204h 204h 208h 208h INTAMask INTBMask INTCMask INTDMask RW RW RW RW Description Contains information about Link capabilities and the Revision ID. Used to enable programmability of configuration space registers disable_usb_phy: 4-bit register used to disable USB PHYs.. pm_reg : 6-bit register used for PCIe power management control feature. Used to select the base address for accessing the configuration space and peripheral control registers. Used to define traffic class for the functions. Global register used to configure internal device parameters Global register used to configure internal device parameters PCIe test bytes PCIe bridge control signals Setting maximum read request size To provide clock power management & advance error report capability. Count for asserting the WAKE_N signal to wake the system. KPTR0 register used to configure internal device parameters KPTR0 register used to configure internal device parameters To provide programmability for Replay timer & ACK latency timer. Programmability for INTA mask reg Programmability for INTB mask reg Programmability for INTC mask reg Programmability for INTD mask reg 119 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 6.9.1 Description of Misc Registers LinkCapRevID Bit 31:24 23:16 Name Rsvd Rsvd 15:13 Default 8'd0 8'd0 3'b111 12:10 LinkCap 3'b111 9 1'b1 8 1'b1 7:0 RevID 8'd0 Description Reserved Reserved L1 Exit Latency for separated clock = [17:15] bit field of Link Capability Register for every function if common clock is not present. L1 Exit Latency for common clock = [17:15] bit field of Link Capability Register for every function if common clock is present. L1 ASPM support = [11] bit field of Link Capability Register for every function. L0 ASPM support = [10] bit field of Link Capability Register for every function. Revision ID field for every function. ConfigSpaceUpdate Bit 0 31:1 Name Default ConfigSpaceUpdate Rsvd 1'b0 31'h00 Description To enable programmability of PCI express configuration space registers, write 1'b1 over here. Reserved PwrMgtCntrl Bit Name Default 0 EnableWake 1'b1 1 Rsvd 1'b0 2 DisableUSBCH0 1'b0 3 DisableUSBCH1 1'b0 4 DisableUSBCH2 1'b0 5 DisableUSBCH3 1'b0 Rsvd 2'b00 DisableUSBPhyCH0 1'b1 7:6 8 Description 1'b1: Supports remote wake-up through wake-up mechanism. 1'b0 : Does not support 1'b1 : Disable USB CH0 1'b0 : Normal operation. 1'b1 : Disable USB CH1 1'b0 : Normal operation. 1'b1 : Disable USB CH2 1'b0 : Normal operation. 1'b1 : Disable USB CH3 1'b0 : Normal operation. Reserved 1'b0 : Disable USB PHY CH0 1'b1: Normal operation. 120 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Bit Name Default 9 DisableUSBPhyCH1 1'b1 10 DisableUSBPhyCH2 1'b1 11 DisableUSBPhyCH3 1'b1 OTGTxResume Rsvd 1'b0 20'h0 12 31:13 Description 1'b0 : Disable USB PHY CH1 1'b1: Normal operation. 1'b0 : Disable USB PHY CH2 1'b1 : Normal operation. 1'b0 : Disable USB PHY CH3 1'b1 : Normal operation. OTG Transmission resume bit Reserved ConfigSpaceBaseAdrs Bit Name 1:0 ConfigSpaceBaseA drs 2'b10 2 TestBusSel1-3-0-2 1'b0 31:3 Default Rsvd 30'h00 Description To select the base address for accessing the configuration space and peripheral control registers. 2'b00 : Base address is 1K. 2'b01 : Base address is 1K. 2'b10 : Base address is 2K. 2'b11 : Base address is 3K. Testbus set selection line 1'b0 : Testbus set for Port-0 & Port-2 will be selected 1'b1 : Testbus set for Port-1 & Port-3 will be selected Reserved TrafficClass Bit 2:0 5:3 7:6 10:8 13:11 15:14 18:16 21:19 23:22 26:24 29:27 31:30 Name F0TC F1TC Rsvd F2TC F3TC Rsvd F4TC F5TC Rsvd F6TC F7TC Rsvd Default 3'b000 3'b000 2'b00 3'b000 3'b000 2'b00 3'b000 3'b000 2'b00 3'b000 3'b000 2'b00 Description To select Traffic class for Function-0 To select Traffic class for Function-1 Reserved To select Traffic class for Function-2 To select Traffic class for Function-3 Reserved To select Traffic class for Function-4 To select Traffic class for Function-5 Reserved To select Traffic class for Function-6 To select Traffic class for Function-7 Reserved KGbl1 Bit 31:0 Name KGbl1 Default 32'h11FF_0001 Description PCIe global register (KGbl[31:0]) 121 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller KGbl2 Bit 31:0 Name KGbl2 Default 32'h0000_0000 Description PCIe global register (KGbl[63:32]) PCIeTest Bit 31:0 Name PCIeTest Default 32'h0000_0008 Description PCIe test register BridgeCntrl Bit 4:0 7:5 12:8 15:13 31:16 Name BrdgConn Rsvd BrdgT2nT1 Rsvd Rsvd Default 5'h01 3'b000 5'h00 3'b000 16'h00 Description PCIe arbiter connect signal Reserved Selection line to connect either to tier1 or tier2 Reserved Reserved EepromMaxReadreqSZ Bit Name Default 2:0 EepromMaxReadReqSZ 3'b000 31:3 Rsvd 29'd0 Description To select max read request size (in Dword) 3'b000 : 128 DW(i.e. 512 byte data) 3'b001 : 32 DW 3'b010 : 64 DW 3'b011 : 128 DW 3'b100 : 256 DW 3'b101 : 512 DW 3'b110 : 1024 DW Reserved PwrMgtAdvErrSupport Bit Name Default 0 F0AdvErrRep 1'b1 1 F0ClkPwrMgmtSprt 1'b1 2 F1AdvErrRep 1'b1 3 F1ClkPwrMgmtSprt 1'b1 4 F2AdvErrRep 1'b1 Description Advance error report capability feature for Function-0 Clock power management support for Function-0 Advance error report capability feature for Function-1 Clock power management support for Function-1 Advance error report capability feature for Function-2 122 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Bit Name Default 5 F2ClkPwrMgmtSprt 1'b1 6 F3AdvErrRep 1'b1 7 F3ClkPwrMgmtSprt 1'b1 8 F4AdvErrRep 1'b1 9 F4ClkPwrMgmtSprt 1'b1 10 F5AdvErrRep 1'b1 11 F5ClkPwrMgmtSprt 1'b1 12 F6AdvErrRep 1'b1 13 F6ClkPwrMgmtSprt 1'b1 14 F7AdvErrRep 1'b1 15 F7ClkPwrMgmtSprt 1'b1 Rsvd 16'd0 31:16 Description Clock power management support for Function-2 Advance error report capability feature for Function-3 Clock power management support for Function-3 Advance error report capability feature for Function-4 Clock power management support for Function-4 Advance error report capability feature for Function-5 Clock power management support for Function-5 Advance error report capability feature for Function-6 Clock power management support for Function-6 Advance error report capability feature for Function-7 Clock power management support for Function-7 Reserved KPtr01 Bit 31:0 Name KPtr01 Default 32'hFF83_BE00 Description PCIe KPTR0 register (KPTR0[31:0]) Name KPtr02 Rsvd Default 4'hF 28'd0 Description PCIe KPTR0 register (KPTR0[35:32]) Reserved Name AckLatencyTimer Rsvd ReplayTimer Rsvd Default 15'h0000 1'b0 15'h0000 1'b0 KPtr02 Bit 3:0 31:4 ReplayAckTimer Bit 14:0 15 30:16 31 Description Ack latency timer Reserved Replay timer Reserved 123 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller INTAMask Programmable register used to select the interrupts that can be mapped to PCIe INTA pin. Bit Name Default Description Programmable bit for masking the interrupt. 0 CH0USBOHCIIntrpt 1'b1 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking the interrupt. 1 CH0USBEHCIIntrpt 1'b1 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking the interrupt. 2 CH1USBOHCIIntrpt 1'b0 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking the interrupt. 3 CH1USBEHCIIntrpt 1'b0 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking the interrupt. 4 CH2USBOHCIIntrpt 1'b0 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking the interrupt. 5 CH2USBEHCIIntrpt 1'b0 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking the interrupt. 6 CH2HostIntrOTG 1'b0 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking the interrupt. 7 CH3USBOHCIIntrpt 1'b0 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking the interrupt. 8 CH3USBEHCIIntrpt 1'b0 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking the interrupt. 9 ISAIntrpt 1'b0 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking the interrupt. 10 GPIOIntrpt 1'b0 1'b0: Mask interrupt 1'b1: Unmask interrupt 124 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller INTBMask Programmable register used to select the interrupts that can be mapped to PCIe INTB pin. Bit Name Default Description Programmable bit for masking the interrupt. 0 CH0USBOHCIIntrpt 1'b0 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking the interrupt. 1 CH0USBEHCIIntrpt 1'b0 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking the interrupt. 2 CH1USBOHCIIntrpt 1'b1 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking the interrupt. 3 CH1USBEHCIIntrpt 1'b1 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking the interrupt. 4 CH2USBOHCIIntrpt 1'b0 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking the interrupt. 5 CH2USBEHCIIntrpt 1'b0 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking the interrupt. 6 CH2HostIntrOTG 1'b0 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking the interrupt. 7 CH3USBOHCIIntrpt 1'b0 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking the interrupt. 8 CH3USBEHCIIntrpt 1'b0 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking the interrupt. 9 ISAIntrpt 1'b0 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking the interrupt. 10 GPIOIntrpt 1'b0 1'b0: Mask interrupt 1'b1: Unmask interrupt 125 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller INTCMask Programmable register used to select the interrupts that can be mapped to PCIe INTC pin. Bit Name Mode Deafult Description Programmable bit for masking Any functional the interrupt. 0 CH0USBOHCIIntrpt 1'b0 mode 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking Any functional the interrupt. 1 CH0USBEHCIIntrpt 1'b0 mode 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking Any functional the interrupt. 2 CH1USBOHCIIntrpt 1'b0 mode 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking Any functional the interrupt. 3 CH1USBEHCIIntrpt 1'b0 mode 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking Any functional the interrupt. 4 CH2USBOHCIIntrpt 1'b1 mode 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking Any functional the interrupt. 5 CH2USBEHCIIntrpt 1'b1 mode 1'b0: Mask interrupt 1'b1: Unmask interrupt 4USB 1'b0 Programmable bit for masking 2USB+OTG 1'b1 the interrupt. 6 CH2HostIntrOTG 1'b0: Mask interrupt 2USB+OTG+ISA 1'b1 1'b1: Unmask interrupt 2USB+OTG+GPIO 1'b1 Programmable bit for masking Any functional the interrupt. 7 CH3USBOHCIIntrpt 1'b0 mode 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking Any functional the interrupt. 8 CH3USBEHCIIntrpt 1'b0 mode 1'b0: Mask interrupt 1'b1: Unmask interrupt 126 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Bit Name Mode Deafult 9 ISAIntrpt Any functional modes 1'b0 10 GPIOIntrpt Any functional mode 1'b0 Description Programmable bit for masking the interrupt. 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking the interrupt. 1'b0: Mask interrupt 1'b1: Unmask interrupt INTDMask Programmable register used to select the interrupts that can be mapped to PCIe INTD pin. Bit Name Mode Deafult 0 CH0USBOHCIIntrpt Any mode functional 1 CH0USBEHCIIntrpt Any mode functional 2 CH1USBOHCIIntrpt Any mode functional 3 CH1USBEHCIIntrpt Any mode functional 4 CH2USBOHCIIntrpt Any mode functional 5 CH2USBEHCIIntrpt Any mode functional 6 CH2HostIntrOTG Any mode functional 7 4USB 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b1 Description Programmable bit for masking the interrupt. 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking the interrupt. 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking the interrupt. 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking the interrupt. 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking the interrupt. 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking the interrupt. 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking the interrupt. 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking 127 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Bit Name CH3USBOHCIIntrpt 8 CH3USBEHCIIntrpt 9 ISAIntrpt 10 GPIOIntrpt Mode 2USB+OTG 2USB+OTG+ISA 2USB+OTG+GPIO 4USB 2USB+OTG 2USB+OTG+ISA 2USB+OTG+GPIO 4USB 2USB+OTG 2USB+OTG+ISA 2USB+OTG+GPIO 4USB 2USB+OTG 2USB+OTG+ISA 2USB+OTG+GPIO Deafult 1'b0 1'b0 1'b0 1'b1 1'b0 1'b0 1'b0 1'b0 1'b0 1'b1 1'b0 1'b0 1'b0 1'b0 1'b1 Description the interrupt. 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking the interrupt. 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking the interrupt. 1'b0: Mask interrupt 1'b1: Unmask interrupt Programmable bit for masking the interrupt. 1'b0: Mask interrupt 1'b1: Unmask interrupt 128 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 7. Clocks and Resets MCS9990 requires two input clock sources Differential reference clock of 100MHz (PCIE_REFCLKn/PCIE_REFCLKp) from PCIe interface External crystal oscillator of 12MHz MCS9990 device requires one master reset coming from PCIe connector which is also called "Fundamental Reset". The PCIe Fundamental Reset does not reset MCS9990 USB host controllers. Please contact ASIX sales (sales@asix.com.tw) to get MCS9990 Errata document. 129 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 8. EEPROM Content Layout The MCS9990 requires a 3.3V 24C32 or higher size I2C EEPROM (in 16-bit addressing mode, up to 400 KHz) for configuring various configurations and device parameters. Please refer to MCS9990 EEPROM User Guide for detailed EEPROM setting information. MCS9990 supports 4 functional modes through mode select pins (Refer to Section 4 for details) and can be configure at more extended configuration modes via EEPROM. MCS9990 Configuration Modes EEPROM Required? 4 USB Host Yes 3 USB Host Yes 2 USB Host Yes 1 USB Host Yes 2 USB Host + OTG Yes 1 USB Host + OTG Yes 2 USB Host + OTG + GPIO Yes 2 USB Host + GPIO Yes 1 USB Host + OTG + GPIO Yes 1 USB Host + GPIO Yes 2 USB Host + OTG + ISA (4S/3S/2S2P/2S/2P/1S1P/1S/1P) 2 USB Host + ISA (4S/3S/2S2P/2S/2P/1S1P/1S/1P) 1 USB Host + OTG + ISA (4S/3S/2S2P/2S/2P/1S1P/1S/1P) 1 USB Host + ISA (4S/3S/2S2P/2S/2P/1S1P/1S/1P) Yes Yes Yes Yes 130 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 9. Power Management MCS9990 cannot support well the power management feature. Please contact ASIX sales (sales@asix.com.tw) to get MCS9990 Errata document. 131 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 10. Electrical Specifications 10.1 Absolute Maximum Ratings Stresses beyond the indicated values in table below may cause permanent damage to the MCS9990 device, even when there is no immediately apparent sign of failure. Prolonged exposure to conditions at or near the absolute maximum ratings may also result in reduced device life span and reduced reliability. Symbol Parameter Min Max Units +1.2V Core Power Supply -0.5 1.6 V +3.3VIO Power Supply of 3.3V I/O -0.5 4.6 V +3.3VIN_REG Input Voltage of 3.3V I/O -0.5 4.6 V +3.3V 3.3V IO's with 5V tolerance capability -0.5 5.8 V TSTG Storage Temperature -45 150 C TOP Operating Temperature (MCS9990CV-AA) 0 70 C TOP Operating Temperature (MCS9990IV-AA) -40 85 C Tj Junction Operating temperature 0 125 C ESD HBM (MIL-STD 883E Method 3015-7 Class 2) 2000 V ESD MM (JEDEC EIA/JESD22 A115-A) 200 V CDM (JEDEC JESD22 C101-A) 500 V JA Thermal Resistance of Junction to Ambient 44 C/W JC Thermal Resistance of Junction to Case 13 C/W JT Junction to Top of the Package Characterization Parameter 0.54 C/W C/W - o C per Watt , For Still Air Condition 132 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 10.2 Recommended Operating Conditions Symbol Parameter Min Typ Max Units +1.2V 1.2V Core Power Supply 1.08 1.2 1.32 V +1.2VA 1.2V Analog/IO Power supply 1.14 1.2 1.32 V +1.2VA_AUX 1.2V analog aux power for PCIE PHY 1.14 1.2 1.32 V +3.3VIO 3.3V Digital IO Power Supply 2.97 3.3 3.63 V +3.3VA_PLL 3.3V Analog Power Supply for internal PLL used in PCIE PHY 3.15 3.3 3.63 V +3.3VA_AUX 3.3V analog aux power for PCIE PHY 3.15 3.3 3.63 V 3.3V Analog supply voltage for USB PHY 3.0 3.3 3.6 V 3.0 3.3 3.6 V 2.7 3.3 3.6 V 2.7 3.3 3.6 V 1.08 1.2 1.32 V 125 mA +3.3VA +3.3VIN_REG 3.3V Analog supply voltage for internal PLL in the USB PHY 3.3V Analog Power Supply for Voltage Detector used for USB OTG PHY Power supply input for Voltage Regulator +1.2VOUT_REG Regulator output Voltage +1.2VOUT_REG Current rating of Voltage Regulator I1.2V Current in 1.2V Supply 80 90 mA I1.2VA Current in 1.2VA Supply 20 30 mA I3.3V Current of 3.3V Supply 7 10 mA I3.3V A Current in 3.3VA Supply 150 160 mA 133 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 10.3 Power Consumption Symbol Description Min Typ Max Units 4 USB full load at High-Speed I12 Current Consumption of 1.2V - 120 - mA I33 Current Consumption of 3.3V - 155 - mA I12 Current Consumption of 1.2V - 109 - mA I33 Current Consumption of 3.3V - 104 - mA USB no load 134 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 10.4 PCI Express PHY Electrical Specifications 10.4.1 Electrical Characteristics Symbol VCC12A VCC12A_AUX VCC33A_PLL Parameter Condition Analog supply current Analog supply current Analog supply current VCC33A_AUX Analog supply current VCC12K Digital supply current ICC12 1.2 V operating Operating in the P0 mode supply current ICC33 3.3 V operating Operating in the P0 mode supply current ICC(susp) Suspend supply In the P2 mode without current the beacon signal transmitted Min. 1.14 1.14 3.15 Typ. 1.2 1.2 3.3 Max. 1.32 1.32 3.63 Units V V V 3.15 3.3 3.63 V 1.14 1.2 1.32 V - 39 - mA - 51 - mA - 90u - mA 10.4.2 Static Characteristics: Digital Pins Symbol Parameter Input levels VIL Low-level input voltage VIH High-level input voltage Output levels VOL Low-level output voltage VOH High-level output voltage Condition Min. Typ. Max. Unit - 1.0 - 0.4 - V V - VCC-0.1 - 0.1 - V - 135 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 10.4.3 Static Characteristics: Analog I/O Pins Symbol Parameter Input levels (RX) VRX-DIFF-PP Differential RX peakpeak voltage VIDLE Electrical idle detect threshold VRX-CM-AC RX AC common-mode voltage Input levels (REFCLK, 100MHz) Rising Rising Edge Rate Edge Rate (Note 1 & 2) Falling Falling Edge Rate Edge Rate (Note 1 & 2) VIH Differential Input High Voltage (Note 1) VIL Differential Input Low Voltage (Note 1) TPERIOD ABS Absolute Period (including Jitter and Spread Spectrum modulation) (Note 1 & 3) Output levels (TX) VTX-DIFF-PP Differential p-p Tx voltage swing TTX-EYE VTX-IDLE-AC VT-D-R VTX_CM_AC VTX_DEM-ratio FBEACON Transmitter eye including all jitter sources Electrical idle differential peak output voltage The amount of voltage change allowed during receiver detection TX AC common-mode voltage TX de-emphasis level A signal of wake-up mechanism Condition Min. Typ. Max. Unit 2 * |VRX(DIP) - VRX(DIN)|, measured at the connection of receiver's near end. Peak voltage 175 - 1200 mV 65 - 175 mV Peak voltage - - 150 mV - 0.6 - 4.0 V/ns - 0.6 - 4.0 V/ns - +150 - - mV - - - -150 mV - 9.847 10.203 ns 2 * |VTX(DOP) - VTX(DON)|, measured at the connection of transmitter's near end. Does not include SSC or Refclk jitter 800 - 1200 mV 0.75 - - UI - - - 20 mV The total amount of voltage change during TX-Detect-RX - - 600 mV Measured as AC RMS value - - 20 mV Non-transient bits are driven out with degrading amplitude Signal frequency -3 - -4 dB 1 - 15 MHz 136 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Resistance RRX RTX Built-in receiver input impedance Built-in driver output impedance Capacitance CTX AC coupling capacitor - 40 50 60 - 40 50 60 - 75 - 200 nF Notes: 1. Measurement taken from differential waveform. 2. Measured from -150 mV to +150 mV on the differential waveform (derived from PCIE_REFCLKp minus PCIE_REFCLKn). The signal must be monotonic through the measurement region for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing. See below "Differential Measurement Points for Rise and Fall Time" figure for details. 3. Defines as the absolute minimum or maximum instantaneous period. This includes cycle to cycle jitter, relative PPM tolerance, and spread spectrum modulation. See below "Differential Measurement Points for Duty Cycle and Period" figure for details. Differential Measurement Points for Rise and Fall Time: Differential Measurement Points for Duty Cycle and Period: 137 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 10.4.4 Auxiliary Signal Timing (power up & reset) Symbol tPVPERL Parameter Conditions Power stable to PCIE_PERST_N inactive REFCLK stable before PCIE_PERST_N inactive PCIE_PERST_N active time Power level invalid to GND inactive tPERST-CLK tPERST tFAIL Min. 100 Typ. Max. 100 s 100 s 500 3.3Vaux Unit ms ns Wakeup Event tFAIL Power Stable Power Stable 3.3V PCIE_PERST_N # Clock Stable Clock not Stable Clock Stable REFCLK PCIe Link Inactive Active Inactive tPERST_CLK tPERST tPVPERL 138 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. Active MCS9990 PCIe to 4-Port USB 2.0 Host Controller 10.5 USB PHY Electrical Specifications 10.5.1 Electrical Characteristics Symbol VCCA Parameter Analog power supply VCC Vnoise Digital power supply Allowable power noise on analog supply Allowable power noise on digital supply Operating current of VCC33A_HSRT domain in different modes Vnoise IVCC33A_HSRT IVCC33A_PLL IVCC12D_U20 Operating current of VCC33A_PLL domain in different modes Operating current of VCC12D_U20 domain in different modes Conditions VCC33A_HSRT and VCC33A_PLL belong to the VCCA group VCC12D_U20 1 Hz ~ 100 kHz Min. Typ. Max. Unit 3.0 3.3 3.6 V 1.08 - 1.2 - 1.32 300 V mV 1 Hz ~ 100 kHz - - 100 mV - At HS (480 Mbps) - - 35 mA At FS (12 Mbps) - - 20 mA At LS (1.5 Mbps) - - 15 mA In suspend mode (Without pull-up resistor connected on DP) - At HS (480 Mbps) - - 5 A - - 7 mA At FS (12 Mbps) - - 6 mA At LS (1.5 Mbps) - - 6 mA In suspend mode (Without pull-up resistor connected on DP) - At HS (480 Mbps) - - 5 A - - 4 mA At FS (12 Mbps) - - 2 mA At LS (1.5 Mbps) - - 2 mA 139 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Symbol IOZ5.25V Parameter 5-V tolerance current Conditions In suspend mode at 25 C (Without pullup resistor connected on DP) Min. Typ. Max. Unit 200 A In suspend mode at 125 C (Without pullup resistor connected on DP) Measured at DP/DM in suspend mode - 2 mA - 100 uA 10.5.2 Static Characteristics: Digital Pins Symbol Parameter Input levels VIL Low-level input voltage VIH High-level input voltage Output levels VOL Low-level output voltage VOH High-level output voltage Conditions Min. Typ. Max. Unit - 2.0 - 0.8 - V V - VCC - 0.2 - 0.2 - V V 10.5.3 Static Characteristics: Analog I/O Pins (DP/DM) Symbol Parameter USB 2.0 transceiver (HS) Input levels (Differential receiver) VHSDIFF High-speed differential input sensitivity VHSCM High-speed data signaling common mode voltage range VHSSQ High-speed squelch detection threshold VHSDSC High-speed disconnection detection threshold Conditions Min. Typ. Max. Unit |VI(DP) - VI(DM)| Measured at the connection as an application circuit. - 300 - - mV -50 - 500 mV Squelch detected - - 100 mV No squelch detected Disconnection detected Disconnection not detected 200 - - mV 625 - - mV - - 525 mV 140 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Symbol Output levels VHSOI VHSOL VHSOH VCHIRPJ VCHIRPK IDP/DM Resistance RDRV Parameter Conditions Min. Typ. Max. Unit High-speed idle level output voltage (Differential) High-speed low level output voltage (Differential) High-speed high level output voltage (Differential) Chirp-J output voltage (Differential) Chirp-K output voltage (Differential) Allowable output current of DP/DM - -10 - 10 mV - -10 - 10 mV - 360 400 440 mV - 700 - 1100 mV - -900 - -500 mV When the termination is 45 10% 14.55 17.78 21.79 mA Driver output impedance Equivalent resistance used for the internal chip - 40.5 45 49.5 76.5 90 103.5 |VI(DP) - VI(DM)| - 0.2 0.8 - 2.5 V V Equivalent resistance used for the internal chip Equivalent resistance used for the internal chip Equivalent resistance used for the internal chip Equivalent resistance used for the internal chip 40.5 45 49.5 900 - 1575 525 - 1515 14.25 - 24.8 k - 0.8 - 2.0 V - 0 2.8 - 0.3 3.6 V V ZHSTERM Differential impedance USB 1.1 transceiver (FS/LS) Input levels (Differential receiver) VDI Differential input sensitivity VCM Differential common mode voltage ZHSDRV Driver output resistance RPU1 Pull-up resistor during idle RPU2 Driver output resistance RPD Driver output resistance Input levels (Single-ended receiver) VSE Single-ended receiver threshold Output levels VOL Low-level output voltage VOH High-level output voltage 141 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 10.5.4 Dynamic Characteristics: Analog I/O Pins (DP/DM) Symbol Parameter Driver characteristics High-speed mode THSRDRATE High-speed TX data rate THSRDRATE High-speed RX data rate tHSR High-speed differential rise time tHSF High-speed differential fall time Full-speed mode TFSDRATE Full-speed TX data rate TFSRDRATE Full-speed RX data rate tFR Rise time tFF Fall time tFRMA Differential rise/fall time matching (tFR/tFF) VCRS Output signal crossover voltage Low-speed mode TLSDRATE Low-speed TX data rate TLSRDRATE Low-speed RX data rate tLR Rise time tLF Fall time Conditions Min. Typ. Max. Unit - 479.76 - 480.24 Mbps - 479.76 - 480.24 Mbps - 500 - - ps - 500 - - ps - 11.994 - 12.006 Mbps - 11.97 - 12.03 Mbps CL = 50 pF 10% ~ 90% of |VOH - VOL| CL = 50 pF 90% ~ 10% of |VOH - VOL| Excluding the first transition from idle mode 4 - 20 ns 4 - 20 ns 90 - 110 % Excluding the first transition from idle mode 1.3 - 2.0 V - 1.49925 - 1.50075 Mbps - 1.49625 - 1.50375 Mbps CL = 200 pF ~ 600 pF 10% ~ 90% of |VOH - VOL| CL = 200 pF ~ 600 pF 90% ~ 10% of |VOH - VOL| 75 - 300 ns 75 - 300 ns 142 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Symbol tLRMA VCRS Parameter Differential rise/fall time matching (tLR/tLF) Output signal crossover voltage Conditions Excluding the first transition in the idle mode Min. 80 Typ. - Max. 125 Unit % Excluding the first transition in the idle mode 1.3 - 2.0 V - 15 ns - 5 ns - 18.5 9 175 ns ns ns - - ns - 14 ns - 100 ns - 75 45 1.5 ns ns s - - ns - 210 ns Driver timing Full-speed mode VI, FSE0, OE For a detailed description of VI, FSE0, and to DP, DM OE, please refer to USB 1.1 specification. Propagation delay TFDEOP Source jitter for -2 differential transition to SE0 transition TJR1 Receiver jitter To next transition -18.5 TJR2 Receiver jitter For paired transition -9 TFEOPT Source SE0 160 interval of EOP TFEOPR Receiver SE0 82 interval of EOP TFST Width of SE0 interval during differential transition Low-speed mode TLDEOP Source jitter for -40 differential transition to SE0 transition TJR1 Receiver jitter To next transition -75 TJR2 Receiver jitter For paired transition -45 TLEOPT Source SE0 1.25 interval of EOP TLEOPR Receiver SE0 670 interval of EOP TLST Width of SE0 interval during differential transition Not specified: Low-speed delay time is dominated by slow tLR and tLR. Receiver timing Full-speed mode 143 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Symbol tPLH(rcv) tPHL(rcv) tPLH(single) tPHL(single) Parameter Receiver propagation delay (DP; DM to RX_RCV) Receiver propagation delay (DP; DM to RX_DP, RX_DM) Conditions For a detailed description of RCV, please refer to USB 1.1 specification. - Min. - Typ. - Max. 30 Unit ns - - 30 ns 144 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 11. Mechanical Dimensions Note: Symbol 1 TO BE DETERMINED AT SEATING PLANE Dimensions D1 and E1 DO NOT include MOLD PROTRUSION. D1 and E1 are MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 2 DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OF THE FOOT. 3 4 EXAT SHAPE OF EACH CORNER IS OPTIONAL. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10mm AND 0.25mm FROM THE LEAD TIP. 5 A1 IS DEFINED AS THE DISTANCE FROM THE SEATINF PLANE TO THE LOWEST POINT OF THE PACKAGE BODY. 6 7. CONTROLLING DIMENSION: MILLIMETER A A1 A2 b b1 c c1 D D1 E E1 e L L1 R1 R2 S 1 2 3 Dimension in mm Min Nom Max 1.60 0.05 1.35 1.40 1.45 0.13 0.18 0.23 0.13 0.16 0.19 0.09 0.20 0.09 0.16 15.85 16.00 16.15 13.90 14.00 14.10 15.85 16.00 16.15 13.90 14.00 14.10 0.40 BSC 0.45 0.60 0.75 1.00 REF 0.08 0.08 0.20 0.20 0 3.5 7 0 12TYP 12TYP 145 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 12. Errata Please contact ASIX sales (sales@asix.com.tw) to get MCS9990 Errata document. 146 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller Revision History Revision 1.0 1.1 1.2 Date 28/02/2009 30/06/2009 21/08/2009 Comment Initial release to customers Aesthetic / Font changes made in Page#1 & Page#2 Electrical characteristics updated under section 10 Document updated for the addition of Industrial grade part number, under ordering information 1. Changed to ASIX Electronics Corp. logo, strings and contact information. 2. Added ASIX copyright legal header information. 3. Modified the Revision History table format. 4. Updated the block diagram in Section 1.4. 1.3 23/02/2011 2.00 2011/08/05 2.01 2011/09/21 1. Added Section 10.3, 10.4 and 10.5 to indicate the power consumption, USB/PCIe PHY Electrical Characteristics spec. 2.02 2011/10/03 1. Added Section 10.4.4 to indicate the power-up and reset timing. 2.03 2011/11/25 1. Added the PCIe REFCLK signals timing spec. in Section 10.4.3. 2.04 2012/03/20 1. Modified some descriptions in Section 3.1, 4, 8, 10.1. 2.05 2012/03/30 1. Modified some descriptions in Section 1.1, 1.2, 1.3, 2. 2.06 2012/05/10 1. Modified some descriptions in Section 1.7, 10.1. 2.07 2012/10/05 1. Modified some descriptions in Section 8. 2.10 2014/09/12 1. Modified some descriptions in Section 3.5, 5. 2.20 2014/12/10 1. Modified some descriptions in Section 2, 4, 8. 3.00 2015/03/10 1. Added Section 12 "Errata". 2. Modified some descriptions in Section 1, 2, 6-2, 7, 9. 147 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved. MCS9990 PCIe to 4-Port USB 2.0 Host Controller 4F, No. 8, Hsin Ann Rd., HsinChu Science Park, HsinChu, Taiwan, R.O.C. TEL: 886-3-5799500 FAX: 886-3-5799558 Sales Email: sales@asix.com.tw Support Email: support@asix.com.tw Web: http://www.asix.com.tw 148 Copyright (c) 2009-2015 ASIX Electronics Corporation. All rights reserved.