64K (8K x 8) CMOS Prey EEPROM MODULE FEATURES: DESCRIPTION: @ Equivalent to JEDEC standard 8K x 8 monolithic EEPROM e 8,192 x 8 CMOS EEPROM module complete with decoder and decoupling capacitor Fast access times Military: 85ns (max.) Commercial: 70ns (max.) e On-chip timer Automatic byte erase before write Byte write 10ns max. DATA Pollingdetection of write cycle completion Utilizes IDT78C16As high-performance 16K EEPROMs Single 5V (+10%) power supply Data protection circuitry (Vcc lockout for Vec < 3.8V) Provides data integrity on power up/power down Minimum endurance of 10,000 write cycles per byte Endurance failure rate < 0.1% per 1000 cycles Available in 28-pin, 600 mi! DIP compliant to MIL-STD-883, Class B FUNCTIONAL BLOCK DIAGRAM Ag-Aio 1/0 -/Oy WE OE CEMOS is a trademark of Integrated Device Technology, Inc. Military modules available with semiconductor components The IDT78M64 is a 5 volt Programmable Read-Only Mero! co-fired ceramic substrate EEPROMs in leadless chip monolithic 64K EEPROMsg decoder circuit that inte: to select one of the fo __The IDT78M64 o 8K x 8 Electrically Erasable EPROM) constructed on a ig Tour IDT78C16A (2K x 8) rs. Functional equivalence to ieved by utilization of an on-board gher order address A1, and Ay2 G power standby mode. When fomatically go to, andremain in, a @ conditions are held. In standby mode, the m less than 440mW. Substantially DT78M64 is equivalent to monolithic 64K d access time allows zero wait state read lormance microprocessors. ith the latest revision of MIL-STD-883, Class B, m ideally suited to military temperature applications he highest level of performance and reliability. IDT78C16A 2Kx8 CMOS EEPROM cs IDT78C16A 2K x8 CMOS EEPROM cs AyyAte DECODER MILITARY AND COMMERCIAL TEMPERATURE RANGES 1987 integrated Device Technology. Inc. DECEMBER 1987 OSC-8008/-IDT78M64 64K CMOS EEPROM MODULE (8K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS [Vs Nc (]1 281] Voc AyCj2 a7] WE a, C]3 26] NC As C4 25 {1 As AsC]6 2a[ Ag a,Cls 23) Ant As(|7 pes-1 221) OF AoC}s aif Ato Ai C 9 20 [] CE Ao C10 1 1/0, WO C11 18] 1/05 vo, F12 7 Os VO, C13 1e6L] 1/0, end C14 15 (LJ 1/03 DIP TOP VIEW DEVICE OPERATIONAL MODE PIN NAMES PIN Ag -A Addresses MODE CE OE WE Oo - VOz OU 2 Read V, Vv v DATA (Og - 07) CE Chip Enable eat - Byte Writ " ie 7, OAR 7 ) * OE Ouiput Enable le Write - A 5 se 7 No 7 WE Write Enable on ion * Standby Min Care Care | High2 On - VO Data Input {Iq - 17) during write; - - 0 7 Data Output (O, - O7) during read Don't Vv, Dont High Z / / Care IL Care 9 Write Inhibit Dont Dont on on : Care | Care Vin | High 2 NOTE: 4. All control inputs are TTL-compatible. 12-23IDT78M64 64K CMOS EEPROM MODULE (8K x 8-BIT) READ MODE Chip Enable (CE) and Output Enable (OE) must be logically active in order for data to be available at the outputs. After a se- lected byte address is stable, CE is taken to a TTL LOW (enabling chip). The Write Enable (WE) pin should remain deselected (TTL HIGH) during the entire read cycle. Data is gated from the device outputs by selecting the OE pin (TTL LOW). WRITE MODE The IDT78M64 is programmed electrically in-circuit and does not require any external latching, erasing or timing. Writing to the IDT78M64 is as easy as writing to a static RAM. When a write cycle is initiated the device automaticatly latches the address, data and control signals as it begins its write operation. __ __Awrita cycle is initiated when both CE and WE are LOW and OE is HIGH. The 1DT78M64 supports both a CE and WE con- trolled write cycle. All inputs, except for data, are latched on the falling edge of either CE or WE, whichever occurs last. Data is then latched in by the rising edge of either CE or WE, whichever oc- curred first. An automatic byte erase of the existing data at the ad- dressed location is performed before the new data byte is written. Once initiated, a byte write operation will automatically proceed to completion within 10ms. STANDBY MODE The IDT78M64 features a standby mode which reduces the maximum active current from 250mA to 80mA for TTL levels and to 4mA for CMOS levels. With CE = Vin, all outputs are in the high impedance state. DATA PROTECTION Nonvolatile data is protected from inadvertent writes in the fol- lowing manner: Power Up/Down On-chip circuitry provides protection against false write during Vee power up/down. The IDT78M64 features an internal sensing circuit that disables the internal programming circuit if Voc < 3.8V. This prevents input signals at CE, WE and OE from triggering a write cycle during a Vee power up/down event. Noise Protection The IDT78M64 will typically reject write pulses that are less than 15ns. This prevents the initiation of a write cycle by a noise oc- curence. MILITARY AND COMMERCIAL TEMPERATURE RANGES Write Inhibit __ __ Holding either OE LOW, WE HIGH or CE HIGH during a power- on and power-off will inhibit inadvertent writes. DATA POLLING The IDT78M64 has a maximum write cycle time of 10ms; a write will always be completed in less than the maximum cycle time. Write cycle completion is readily determined via a simple software routine (DATA Polling) that performs a read operation while the device is in an automatic write mode. If a read command (ad- dressed to the last byte written) is given while the IDT78M64 is still writing, the inverse of the most significant bit (I/O7 pin) of the last byte written will be present. True data is not released until the write cycle is completed. Thus, a DATA polling monitor of the output (or periodic read of the last written byte) for true data can be used to detect early completion of a write cycle. ENDURANCE IDTs EEPROM technology employs the industry accepted Fowler-Nordheim tunneling across a thin oxide. IDT78M64 EEPROM modules are designed and tested for applications requir- ing extended endurance. The endurance failure mechanism associated with EEPROMs results from the charge trapping in the thin tunneling dielectric. This failure is a function of the number of write cycles that each byte in the part has experienced. Trapped charges accumulate slowly with each write cycle and eventually become large enough to pre- vent reliable writing to the cell. Since some bits may be more sensi- tive than others, an endurance failure is typically a single bit failure (L.e.a failure of a single bit to properly write or retain data). To test for endurance, a sample of devices is written 10,000 times at every byte location and checked for data retention capabil- ity. IDT test screens ensure that shipped devices will write a mini- mum of 10,000 times (at every byte location) with a maximum fail- ure rate of 1%. This means that up to 1% ofa sample of devices will fail to write or retain data after being written to 10,000 times. Those devices that do fail typically have a single bit(s) that fails to retain data after being written. For more detailed information please refer to the /DT Reliability Report on Endurance. 12-241DT78M64 64K CMOS EEPROM MODULE (8K x 8-BIT) ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING MILITARY AND COMMERCIAL TEMPERATURE RANGES SYMBOL RATING COMMERCIAL] MILITARY | UNIT TEMPERATURE AND SUPPLY VOLTAGE Terminal Voltage AMBIENT D Vreaw | With Respect to -0.510 +7.0 }-05to +7.0] Vv GRADE TEMPERATURE GN Vee GND Military -55C to + 125C ov 5.0V + 10% Ta a Oto +70 -55 to +125] C Commercial 0C to + 70C ov 5.0V + 10% Taas | Gee? -55 to +125 |-65to +135] C a RECOMMENDED DC OPERATING CONDITIONS lorage Tste Temperature ~55to +125 |-65to +150) C SYMBOL| PARAMETER min. | Typ. | Max.] UNIT lout DC Cutput Current 50 50 mA Voc Supply Voltage 45 5.0 55 Vv NOTE: Vig {nput High Voltage 22 35 6.0 Vv 1. Stresses greater than those listed under ABSOLUTE MAXIMUM Vie Input Low Voltage -0.3 0.4 0.8 Vv RATINGS may cause permanent damage to the device. This is a stress , ~ rating only and functional operation of the device at these or any other Vwi Write Inhibit 3.8 = - v conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. p " CAPACITANCE (1,= +25C, f = 1.0MHz, Voc = 5.0V) SYMBOL PARAMETER( CONDITIONS TYP. UNIT ENDURANCE Cw Input Capacitance Vin = OV 28 pF PARAMETER VALUE UNIT Cour Output Capacitance Vour = OV 33 pF a NOTE: Minimum Endurance 10,000 Cycles/Byte 1. This parameter is sampled and not 100% tested. DC ELECTRICAL CHARACTERISTICS Following Conditions Apply Unless Otherwise Specified Ta = OC to +70C Voc = 5.0V + 10% (Commercial) Ta = -55C to +125C Veo = 5.0V + 10% (Military) Vic = 0.2V Vue = Veo -0.2V C, = 30pF SYMBOL PARAMETER TEST CONDITIONS MIN. MAX. UNIT Hal Input Leakage Current Vog = Max.,Viy = GND to Voc - 15 HA CE = Vn or OE = Vu. Ihol Output Leakage Current Vio = GND to Voc IW _ 15 WA Operating Power Supply Current CE =V,, _ leer Voc = Max..f = 0 yo = OMA 250 mA | Dynamic Operating Current CE = Vi. _ coe Voo = Max.. t= fuax lwo = OMA 250 mA ; Standby Power Supply Current CE 2M. Voc = Max, lyo = OMA _ 80 mA SB (TTL Level) Vn 2MH OrOSVy SV ! Full Standby Power Supply Current CE > Vac. Vog = Max., lyo = OMA _ 40 mA $81 (CMOS Level) Vin 2 Voc -0.2V or 0 SVy <= 0.2V . VoL Output Low Voltage Voo = Min., Io, = 8mA - 0.4 Vv Vou Output High Voltage Voc = Min., lox = -4mA 2.4 - v AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels GND to 3.0V 5ns 1.5V 1.5V 12-25IDT78M64 64K CMOS EEPROM MODULE (8K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (veo = 5.0V_+10%, C,_ = 30pF) MILITARY ONLY SYMBOL PARAMETER 78M6495/100 |78M6e4120/150 |78m64200 |78Me4250 |7am64300 | 7ame4a50 | UNIT MIN. MAX. MIN. MAX. | MIN. MAX. | MIN. MAX. | MIN. MAX.| MIN. MAX. READ CYCLE tog Chip Enable Access Time - 85/100 - 120/150| - 200 - 250 - 300] - 350 ns tan Address Access Tire - 85/100 120/150} - 200 - 20] 300] - 350 ns toe Output Enable to Output Valid - 60/65 _ 70 - 70 _ 70 _ 70 - 70 ns toiz Chip Enable to Output in Low Z 5 - 5 - 5 - 5 - oy 5 - ns to Output Enable to Output in Low Z 5 - 5 - 5 - 5 - - 5 - ns tonz Chip Disable to Output in High Z 0 30 0 30 0 30 0 30 30 ie} 30 ns tonz Output Disable to Output in High Z 0 30 0 30 0 30 0 30 0 30 ns tou Output Hold from Address Change} 5 ~_ 5 - 5 - 5 - 5 - ns AC ELECTRICAL CHARACTERISTICS (Vcc = 5.0V +10%, C, = 30pF) COMMER oO SYMBOL PARAMETER 78M6470 | 78M6485 | 78M64100 BM 7am6e41s0 | 78mM64200 | UNIT MIN. MAX.| MIN. MAX.| MIN. MAX. . | MIN. MAX. | MIN. MAX. READ CYCLE toe Chip Enable Access Time - 70 _ 85 - 10 120 _ 150 = 200 ns tan Address Access Time - 70 - 8 - 120 - 150 - 200 ns tog Output Enable to Output Valid - 650 - 60 - 70 - 70 - 70 ns toz Chip Enable to Output in Low Z 5 - 5 - 5 5 - 5 - 5 - ns toz Output Enable to Output in Low Z | 5 - 5 - 5 5 - 5 - 5 - ns tcuz _ | Chip Disable to Output in High Z 0. 20 0 20 0 20 0 20 0 20 ns tonz Output Disable to Output in High Z 0 20 0 0 20 0 20 0 20 0 20 ns tou Output Hold from Address Change} 5 - 5 - 5 = 5 - 5 - ns AC ELECTRICAL CHARACTERISTICS (oc + || Temperature Ranges; C, = 30pF) SYMBOL | y | MIN. MAX. UNIT WRITE CYCLE tas Address Set-up Time 5 - ns tan Address Hold Time 50 - ns tos Data Set-up Time 20 - ns ton Data Hold from Write 15 - ns toes Output Enable Set, 5 - ns toe Chip Enable Hold ite Mine 15 - ns toes Chip Enable a - ns toey Chip Enab| Id 0 - ns twe Write Pylse 50 - ns twe Byte Wri cle - 10 ms togy DAT ing to DATA Valid - toe two Write Hold Time 15 - ns top End of Write Pulse to DATA Polling 15 - ns twes Write Enable Set-up Time 0 - ns tweH Write Enable Hold Time 0 = ns tov Data Valid Time - 1 ys NOTES: 1. Data must be valid within 11s maximum and must remain valid if typ is longer than 1ps. 2. This parameter is guaranteed but not tested. 12-26IDT78M64 64K CMOS EEPROM MODULE (8K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF READ CYCLE NO. 1 ADDRESS OE cE touz tonz DATA our DATA VALID NOTE: 1. WE is HIGH for Read Cycle. TIMING WAVEFORM OF READ CYCLE NO. 2 ADDRESS x ja tan t < toy_ OH DATA our } DATA VALID NOTE: _ 1. WE is HIGH; CE = V,; OF = VL TIMING WAVEFORM OF READ CYCLE NO. 3 ce \ * toe tonz + tox 4 DATA out NOTE: 1. WE is HIGH; OE = V,; address valid prior to or coincident with CE transition LOW. 12-27ne IDT78M64 64K CMOS EEPROM MODULE (8K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF WRITE CYCLE NO. 1, WE CONTROLLED tag te__ tan ADDRESS TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE CONTROLLED ADDRESS DATA jw 12-28IDT78M64 64K CMOS EEPROM MODULE (8K x 8-BIT) DATA POLLING top m fet tony MILITARY AND COMMERCIAL TEMPERATURE RANGES -)) POLL DATA DONE AS we a NOTE: 1. Most significant bit of the byte being written is inverted and available at I/O 7 if a Read command is issued. All other outputs are high impedance at this time. True data will not be released until the Write cycle is completed. ORDERING INFORMATION ID XXXKX xX XXX XX xX Device Type Power Speed Package Process/ Temperature Range 78M64 Commercial {(0C to + 70C) Military (-55C to + 125C) Compliant to MIL-STD-883, Class B _ 1 Commercial Only Speed in Nanoseconds Mititary Only Military Only Military Only Standard Power 64K (8K x 8-Bit) EEPROM Module 12-29