W29N02GW/Z
Release Date: August 31th 2018
1 Revision F
W29N02GW/Z
2G-BIT 1.8V
NAND FLASH MEMORY
W29N02GW/Z
Release Date: August 31th 2018
2 Revision F
Table of Contents
1. GENERAL DESCRIPTION ............................................................................................................... 7
2. FEATURES ....................................................................................................................................... 7
3. PACKAGE TYPES AND PIN CONFIGURATIONS .......................................................................... 8
3.1 Pin Assignment 48-pin TSOP ............................................................................................... 8
3.2 Pin Assignment 63 ball VFBGA (x8) .................................................................................... 9
3.3 Pin Assignment 63 ball VFBGA (x16) ................................................................................ 10
3.4 Pin Descriptions .................................................................................................................. 11
4. PIN DESCRITPIONS ...................................................................................................................... 12
4.1 Chip Enable (#CE) .............................................................................................................. 12
4.2 Write Enable (#WE) ............................................................................................................ 12
4.3 Read Enable (#RE) ............................................................................................................ 12
4.4 Address Latch Enable (ALE) .............................................................................................. 12
4.5 Command Latch Enable (CLE) .......................................................................................... 12
4.6 Write Protect (#WP) ............................................................................................................ 12
4.7 Ready/Busy (RY/#BY) ........................................................................................................ 12
4.8 Input and Output (I/Ox) ....................................................................................................... 12
5. BLOCK DIAGRAM .......................................................................................................................... 13
6. MEMORY ARRAY ORGANIZATION .............................................................................................. 14
6.1 Array Organization (x8) ...................................................................................................... 14
6.2 Array Organization (x16) .................................................................................................... 15
7. MODE SELECTION TABLE ........................................................................................................... 16
8. COMMAND TABLE......................................................................................................................... 17
9. DEVICE OPERATIONS .................................................................................................................. 18
9.1 READ Operation ................................................................................................................. 18
9.1.1 PAGE READ (00h-30h)......................................................................................................... 18
9.1.2 TWO PLANE READ (00h-00h-30h) ...................................................................................... 18
9.1.3 RANDOM DATA OUTPUT (05h-E0h) ................................................................................... 20
9.1.4 READ ID (90h) ...................................................................................................................... 21
9.1.5 READ PARAMETER PAGE (ECh) ....................................................................................... 22
9.1.6 READ STATUS (70h)............................................................................................................ 24
9.1.7 READ STATUS ENHANCED (78h) ...................................................................................... 25
9.1.8 READ UNIQUE ID (EDh) ...................................................................................................... 27
9.2 PROGRAM Operation ........................................................................................................ 28
9.2.1 PAGE PROGRAM (80h-10h) ................................................................................................ 28
9.2.2 SERIAL DATA INPUT (80h) .................................................................................................. 28
9.2.3 RANDOM DATA INPUT (85h) .............................................................................................. 29
9.2.4 TWO PLANE PAGE PROGRAM .......................................................................................... 29
9.3 COPY BACK Operation ...................................................................................................... 31
9.3.1 READ for COPY BACK (00h-35h) ........................................................................................ 31
9.3.2 PROGRAM for COPY BACK (85h-10h) ................................................................................ 31
9.3.3 TWO PLANE READ for COPY BACK ................................................................................... 32
9.3.4 TWO PLANE PROGRAM for COPY BACK .......................................................................... 32
9.4 BLOCK ERASE Operation ................................................................................................. 36
W29N02GW/Z
Release Date: August 31th 2018
3 Revision F
9.4.1 BLOCK ERASE (60h-D0h) .................................................................................................... 36
9.4.2 TWO PLANE BLOCK ERASE .................................................................................................. 37
9.5 RESET Operation ............................................................................................................... 38
9.5.1 RESET (FFh) ........................................................................................................................ 38
9.6 FEATURE OPERATION..................................................................................................... 39
9.6.1 GET FEATURES (EEh) ........................................................................................................ 42
9.6.2 SET FEATURES (EFh) ......................................................................................................... 43
9.7 ONE TIME PROGRAMMABLE (OTP) Area ....................................................................... 44
9.8 WRITE PROTECT .............................................................................................................. 45
9.9 BLOCK LOCK ..................................................................................................................... 47
10. ELECTRICAL CHARACTERISTICS............................................................................................... 48
10.1 Absolute Maximum Ratings (1.8V) ..................................................................................... 48
10.2 Operating Ranges (1.8V) ................................................................................................... 48
10.3 Device Power-up Timing .................................................................................................... 49
10.4 DC Electrical Characteristics (1.8V) ................................................................................... 50
10.5 AC Measurement Conditions (1.8V) ................................................................................... 51
10.6 AC Timing Characteristics for Command, Address and Data Input (1.8V) ........................ 52
10.7 AC Timing Characteristics for Operation (1.8V) ................................................................. 53
10.8 Program and Erase Characteristics ................................................................................... 54
11. TIMING DIAGRAMS ....................................................................................................................... 55
12. INVALID BLOCK MANAGEMENT .................................................................................................. 64
12.1 Invalid Blocks ...................................................................................................................... 64
12.2 Initial Invalid Blocks ............................................................................................................ 64
12.3 Error in Operation ............................................................................................................... 65
12.4 Addressing in Program Operation ...................................................................................... 66
13. PACKAGE DIMENSIONS ............................................................................................................... 67
13.1 TSOP 48-pin 12x20 ............................................................................................................ 67
13.2 Fine-Pitch Ball Grid Array 63-ball ....................................................................................... 68
14. ORDERING INFORMATION .......................................................................................................... 69
15. VALID PART NUMBERS ................................................................................................................ 70
16. REVISION HISTORY ...................................................................................................................... 71
W29N02GW/Z
Release Date: August 31th 2018
4 Revision F
List of Tables
Table 3-1 Pin Descriptions .......................................................................................................................... 11
Table 6-1 Addressing (x8) ........................................................................................................................... 14
Table 6-2 Addressing (x16) ......................................................................................................................... 15
Table 7-1 Mode Selection ........................................................................................................................... 16
Table 8-1 Command Table ......................................................................................................................... 17
Table 9-1 Device ID and configuration codes for Address 00h .................................................................. 21
Table 9-2 ONFI Identifying Codes for Address 20h .................................................................................... 21
Table 9-3 Parameter Page Output Value .................................................................................................... 24
Table 9-4 Status Register Bit Definition ...................................................................................................... 25
Table 9-5 Features ...................................................................................................................................... 39
Table 9-6 Feature Address 80h .................................................................................................................. 40
Table 9-7 Feature Address 81h .................................................................................................................. 41
Table 10-1 Absolute Maximum Ratings ...................................................................................................... 48
Table 10-2 Operating Ranges ..................................................................................................................... 48
Table 10-3 DC Electrical Characteristics .................................................................................................... 50
Table 10-4 AC Measurement Conditions .................................................................................................... 51
Table 10-5 AC Timing Characteristics for Command, Address and Data Input ......................................... 52
Table 10-6 AC Timing Characteristics for Operation .................................................................................. 53
Table 10-7 Program and Erase Characteristics .......................................................................................... 54
Table 12-1 Valid Block Number .................................................................................................................. 64
Table 12-2 Block Failure ............................................................................................................................. 65
Table 15-1 Part Numbers for Industrial Grade Temperature ...................................................................... 70
Table 15-2 Part Numbers for Industrial Plus Grade Temperature .............................................................. 70
Table 16-1 History Table ............................................................................................................................. 71
W29N02GW/Z
Release Date: August 31th 2018
5 Revision F
List of Figures
Figure 5-1 NAND Flash Memory Block Diagram ........................................................................................ 13
Figure 6-1 Array Organization (x8) ............................................................................................................. 14
Figure 6-2 Array Organization (x16) ........................................................................................................... 15
Figure 9-1 Page Read Operations .............................................................................................................. 18
Figure 9-2 Two Plane Read Page (00h-00h-30h) Operation ...................................................................... 19
Figure 9-3 Random Data Output ................................................................................................................. 20
Figure 9-4 Two Plane Random Data Read (06h-E0h) Operation ............................................................... 20
Figure 9-5 Read ID ...................................................................................................................................... 21
Figure 9-6 Read Parameter Page ............................................................................................................... 22
Figure 9-7 Read Status Operation .............................................................................................................. 24
Figure 9-8 Read Status Enhanced (78h) Operation ................................................................................... 26
Figure 9-9 Read Unique ID ......................................................................................................................... 27
Figure 9-10 Page Program.......................................................................................................................... 28
Figure 9-11 Random Data Input ................................................................................................................. 29
Figure 9-12 Two Plane Page Program ....................................................................................................... 30
Figure 9-13 Program for Copy Back Operation .......................................................................................... 33
Figure 9-14 Copy Back Operation with Random Data Input ....................................................................... 33
Figure 9-15 Two Plane Copy Back ............................................................................................................. 34
Figure 9-16 Two Plane Copy Back with Random Data Input ..................................................................... 34
Figure 9-17 Two Plane Program for Copy Back ......................................................................................... 35
Figure 9-18 Block Erase Operation ............................................................................................................. 36
Figure 9-19 Two Plane Block Erase Operation........................................................................................... 37
Figure 9-20 Reset Operation....................................................................................................................... 38
Figure 9-21 Get Feature Operation ............................................................................................................. 42
Figure 9-22 Set Feature Operation ............................................................................................................. 43
Figure 9-23 Erase Enable ........................................................................................................................... 45
Figure 9-24 Erase Disable .......................................................................................................................... 45
Figure 9-25 Program Enable ....................................................................................................................... 45
Figure 9-26 Program Disable ...................................................................................................................... 46
Figure 9-27 Program for Copy Back Enable ............................................................................................... 46
Figure 9-28 Program for Copy Back Disable .............................................................................................. 46
Figure 10-1 Power ON/OFF Sequence ....................................................................................................... 49
Figure 11-1 Command Latch Cycle ............................................................................................................ 55
Figure 11-2 Address Latch Cycle ................................................................................................................ 55
Figure 11-3 Data Latch Cycle ..................................................................................................................... 56
Figure 11-4 Serial Access Cycle after Read ............................................................................................... 56
Figure 11-5 Serial Access Cycle after Read (EDO) .................................................................................... 57
Figure 11-6 Read Status Operation ............................................................................................................ 57
Figure 11-7 Page Read Operation .............................................................................................................. 58
Figure 11-8 #CE Don't Care Read Operation ............................................................................................. 58
Figure 11-9 Random Data Output Operation .............................................................................................. 59
Figure 11-10 Read ID .................................................................................................................................. 60
Figure 11-11 Page Program........................................................................................................................ 60
Figure 11-12 #CE Don't Care Page Program Operation ............................................................................ 61
W29N02GW/Z
Release Date: August 31th 2018
6 Revision F
Figure 11-13 Page Program with Random Data Input ................................................................................ 62
Figure 11-14 Copy Back ............................................................................................................................. 62
Figure 11-15 Block Erase ............................................................................................................................ 63
Figure 11-16 Reset ..................................................................................................................................... 63
Figure 12-1 Flow Chart of Create Initial Invalid Block Table ....................................................................... 65
Figure 12-2 Bad Block Replacement .......................................................................................................... 66
Figure 14-1 Ordering Part Number Description .......................................................................................... 69
W29N02GW/Z
Release Date: August 31th 2018
7 Revision F
1. GENERAL DESCRIPTION
The W29N02GW/Z (2G-bit) NAND Flash memory provides a storage solution for embedded systems with
limited space, pins and power. It is ideal for code shadowing to RAM, solid state applications and storing
media data such as, voice, video, text and photos. The device operates on a single 1.7V to 1.95V power
supply with active current consumption as low as 13mA at 1.8V and 10uA for CMOS standby current.
The memory array totals 276,824,064bytes, and organized into 2,048 erasable blocks of 135,168 bytes
(135,168 words). Each block consists of 64 programmable pages of 2,112-bytes (1056 words) each. Each
page consists of 2,048-bytes (1024 words) for the main data storage area and 64-bytes (32words) for the
spare data area (The spare area is typically used for error management functions).
The W29N02GW/Z supports the standard NAND flash memory interface using the multiplexed 8-bit (16-
bit) bus to transfer data, addresses, and command instructions. The five control signals, CLE, ALE, #CE,
#RE and #WE handle the bus interface protocol. Also, the device has two other signal pins, the #WP (Write
Protect) and the RY/#BY (Ready/Busy) for monitoring the device status.
2. FEATURES
Basic Features
– Density : 2Gbit (Single chip solution)
– Vcc : 1.7V to 1.95V
– Bus width : x8 x16
– Operating temperature
Industrial: -40°C to 85°C
Industrial Plus: -40°C to 105°C
Single-Level Cell (SLC) technology.
Organization
– Density: 2G-bit/256M-byte
– Page size
2,112 bytes (2048 + 64 bytes)
1,056 words (1024 + 32 words)
– Block size
64 pages (128K + 4K bytes)
64 pages (64K + 2K words)
Highest Performance
– Read performance (Max.)
Random read: 25us
Sequential read cycle: 25ns
– Write Erase performance
Page program time: 250us(typ.)
Block erase time: 2ms(typ.)
– Endurance 100,000 Erase/Program
Cycles(1)
– 10-years data retention
Command set
– Standard NAND command set
– Additional command support
Copy Back
Two-plane operation
– Contact Winbond for OTP feature
– Contact Winbond for Block Lock feature
Lowest power consumption
– Read: 13mA(typ.)
– Program/Erase: 10mA(typ.)
– CMOS standby: 10uA(typ.)
Space Efficient Packaging
– 48-pin standard TSOP1
– 63-ball VFBGA
– Contact Winbond for stacked
packages/KGD
Note:
1. Endurance specification is based on 1bit/528 byte ECC (Error Correcting Code).
W29N02GW/Z
Release Date: August 31th 2018
8 Revision F
3. PACKAGE TYPES AND PIN CONFIGURATIONS
W29N02GW/Z is offered in a 48-pin TSOP1 package (Code S) and 63-ball VFBGA package (Code
B) as shown in Figure 3-1 to 3-3, respectively. Package diagrams and dimensions are illustrated in
Section: Package Dimensions.
3.1 Pin Assignment 48-pin TSOP
Figure 3-1 Pin Assignment 48-pin TSOP1 (Package code S)
3
4
1
2
Top View
7
8
5
6
11
12
9
10
15
16
13
14
19
20
17
18
23
24
21
22
46
45
48
47
42
41
44
43
38
37
40
39
34
33
36
35
30
29
32
31
26
25
28
27
48-pin TSOP1
Standard package
12mm x 20mm
N.C
N.C
N.C
N.C
IO5
IO4
IO7
IO6
N.C
Vcc
N.C
N.C
N.C
N.C
Vss
N.C
IO1
IO0
IO3
IO2
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
RY/#BY
#RE
N.C
N.C
N.C
Vcc
#CE
N.C
N.C
CLE
Vss
N.C
#WP
DNU
ALE
#WE
N.C
N.C
N.C
N.C
X8X8
N.C
N.C
N.C
N.C
RY/#BY
#RE
N.C
N.C
N.C
Vcc
#CE
N.C
N.C
CLE
Vss
N.C
#WP
DNU
ALE
#WE
N.C
N.C
N.C
N.C
X16
IO14
IO13
N.C
IO15
IO5
IO4
IO7
IO6
N.C
Vcc
IO12
N.C
N.C
IO11
Vss
N.C
IO1
IO0
IO3
IO2
IO8
N.C
IO10
IO9
X16
W29N02GW/Z
Release Date: August 31th 2018
9 Revision F
3.2 Pin Assignment 63 ball VFBGA (x8)
Figure 3-2 Pin Assignment 63-ball VFBGA (Package code B)
3 41 2 7 85 6
A
B
910
E
F
C
D
J
K
G
H
L
M
N.CN.C
N.C
RY/#BY
#RE N.CN.C
#CE
N.CCLE
Vss
N.C
#WP ALE #WE
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.CN.C N.C N.CN.C N.C
N.CN.C N.C N.C N.C
N.CN.C N.C
N.C N.C N.CN.C
N.C N.C IO5
IO4
IO7
IO6
N.C
N.C
IO1
IO0
IO3IO2 Vss
Vcc
Vcc
Vss
DNU DNU
Top View, ball down
W29N02GW/Z
Release Date: August 31th 2018
10 Revision F
3.3 Pin Assignment 63 ball VFBGA (x16)
Figure 3-3 Pin Assignment 63-ball VFBGA (Package code B)
3 41 2 7 85 6
A
B
910
E
F
C
D
J
K
G
H
L
M
N.CN.C
N.C
RY/#BY
#RE N.CN.C
#CE
N.CCLE
Vss
N.C
#WP ALE #WE
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.CN.C N.C N.CN.C N.C
N.CN.C N.C N.C N.C
IO15IO13 N.C
IO8IO10 IO14IO12
IO9IO11 IO5
IO4
IO7
IO6
N.C
N.C
IO1
IO0
IO3IO2 Vss
Vcc
Vcc
Vss
DNU DNU
Top View, ball down
W29N02GW/Z
Release Date: August 31th 2018
11 Revision F
3.4 Pin Descriptions
PIN NAME
I/O
FUNCTION
#WP
I
Write Protect
ALE
I
Address Latch Enable
#CE
I
Chip Enable
#WE
I
Write Enable
RY/#BY
O
Ready/Busy
#RE
I
Read Enable
CLE
I
Command Latch Enable
I/O[0-7]
I/O[0-15]
I/O
Data Input/Output (x8,x16)
Vcc
Supply
Power supply
Vss
Supply
Ground
DNU
-
Do Not Use: DNUs must be left unconnected.
N.C
-
No Connect
Table 3-1 Pin Descriptions
Note:
1. Connect all Vcc and Vss pins to power supply or ground. Do not leave Vcc or Vss disconnected.
W29N02GW/Z
Release Date: August 31th 2018
12 Revision F
4. PIN DESCRITPIONS
4.1 Chip Enable (#CE)
#CE pin enables and disables device operation. When #CE is high the device is disabled and the I/O
pins are set to high impedance and enters into standby mode if not busy. When #CE is set low the
device will be enabled, power consumption will increase to active levels and the device is ready for
Read and Write operations.
4.2 Write Enable (#WE)
#WE pin enables the device to control write operations to input pins of the device. Such as, command
instructions, addresses and data that are latched on the rising edge of #WE.
4.3 Read Enable (#RE)
#RE pin controls serial data output from the pre-loaded Data Register. Valid data is present on the
I/O bus after the tREA period from the falling edge of #RE. Column addresses are incremented for
each #RE pulse.
4.4 Address Latch Enable (ALE)
ALE pin controls address input to the address register of the device. When ALE is active high,
addresses are latched via the I/O pins on the rising edge of #WE.
4.5 Command Latch Enable (CLE)
CLE pin controls command input to the command register of the device. When CLE is active high,
commands are latched into the command register via I/O pins on the rising edge of #WE.
4.6 Write Protect (#WP)
#WP pin can be used to prevent the inadvertent program/erase to the device. When #WP pin is active
low, all program/erase operations are disabled.
4.7 Ready/Busy (RY/#BY)
RY/#BY pin indicates the device status. When RY/#BY output is low, it indicates that the device is
processing either a program, erase or read operations. When it returns to high, those operations have
completed. RY/#BY pin is an open drain.
4.8 Input and Output (I/Ox)
I/Ox bi-directional pins are used for the following; command, address and data operations.
W29N02GW/Z
Release Date: August 31th 2018
13 Revision F
5. BLOCK DIAGRAM
Logic
Control
Status
Register
Command
Register
Address
Register
High Voltage
Generator
NAND Flash
Array
Row Decoder
Column Decoder
Cache Register
Data Register
I/O
Control
#CE
ALE
CLE
#RE
#WE
#WP
I/Ox
RY/#BY
Figure 5-1 NAND Flash Memory Block Diagram
W29N02GW/Z
Release Date: August 31th 2018
14 Revision F
6. MEMORY ARRAY ORGANIZATION
6.1 Array Organization (x8)
Figure 6-1 Array Organization (x8)
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st cycle
A7
A6
A5
A4
A3
A2
A1
A0
2nd cycle
L
L
L
L
A11
A10
A9
A8
3rd cycle
A19
A18
A17
A16
A15
A14
A13
A12
4th cycle
A27
A26
A25
A24
A23
A22
A21
A20
5th cycle
L
L
L
L
L
L
L
A28
Table 6-1 Addressing (x8)
Notes:
1. “L” indicates a low condition, which must be held during the address cycle to insure correct processing.
2. A0 to A11 during the 1st and 2nd cycles are column addresses. A12 to A28 during the 3rd, 4th and 5th cycles
are row addresses.
3. A18 is plane address
4. The device ignores any additional address inputs that exceed the device’s requirement.
Plane of even
-
numbered blocks Plane of odd
-
numbered blocks
1024
blocks
Per plane
2048
blocks
Per device
Data Register
Cache Register 2048
2048
2048
2048
2112 bytes 2112 bytes
64
64
64
64
1 block
1 block
1page = (2k+64bytes)
1block = (2k+64）bytes×64 pages
= (128k+4k)byte
1plane = (128k+4k)byte×1024blocks
= 1056Mb
1device = 1056M ×2planes
= 2112Mb
DQ7
DQ0
W29N02GW/Z
Release Date: August 31th 2018
15 Revision F
6.2 Array Organization (x16)
Figure 6-2 Array Organization (x16)
I/O[15:8]
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st cycle
L
A7
A6
A5
A4
A3
A2
A1
A0
2ndcycle
L
L
L
L
L
L
A10
A9
A8
3rd cycle
L
A18
A17
A16
A15
A14
A13
A12
A11
4th cycle
L
A26
A25
A24
A23
A22
A21
A20
A19
5th cycle
L
L
L
L
L
L
L
L
A27
Table 6-2 Addressing (x16)
Notes:
1. “L” indicates a low condition, which must be held during the address cycle to insure correct processing.
2. A0 to A10 during the 1st and 2nd cycles are column addresses. A11 to A27 during the 3rd, 4th and 5th cycles
are row addresses.
3. A17 is plane address
4. The device ignores any additional address inputs that exceed the device’s requirement.
1block = (1k+32）words×64 pages
= (64k+2k)words
1plane = (64k+2k)words×1024blocks
1device= 1056M ×2planes
= 2112Mb
Plane of even
-
numbered blocks Plane of odd
-
numbered blocks
1024
blocks
Per plane
2048
blocks
Per device
Data Register
Cache Register 1024
1024
1024
1024
1056 words 1056 words
32
32
32
32
1 block
1 block
1page = (1k+32words)
= 1056Mb
DQ15
DQ0
(0,2,4,6...,1020,1022)(1,3,5,7...,1021,1023)
W29N02GW/Z
Release Date: August 31th 2018
16 Revision F
7. MODE SELECTION TABLE
MODE
CLE
ALE
#CE
#WE
#RE
#WP
Read
mode
Command input
H
L
L
H
X
Address input
L
H
L
H
X
Program
Erase
mode
Command input
H
L
L
H
H
Address input
L
H
L
H
H
Data input
L
L
L
H
H
Sequential Read and Data output
L
L
L
H
X
During read (busy)
X
X
X
X
H
X
During program (busy)
X
X
X
X
X
H
During erase (busy)
X
X
X
X
X
H
Write protect
X
X
X
X
X
L
Standby
X
X
H
X
X
0V/Vcc
Table 7-1 Mode Selection
Notes:
1. “H” indicates a HIGH input level, “L” indicates a LOW input level, and “X” indicates a Don’t Care Level.
2. #WP should be biased to CMOS HIGH or LOW for standby.
W29N02GW/Z
Release Date: August 31th 2018
17 Revision F
8. COMMAND TABLE
COMMAND
1ST
CYCLE
2ND
CYCLE
3rd
CYCLE
4th
CYCLE
Acceptable
during
busy
PAGE READ
00h
30h
READ for COPY BACK
00h
35h
READ ID
90h
READ STATUS
70h
Yes
RESET
FFh
Yes
PAGE PROGRAM
80h
10h
PROGRAM for COPY BACK
85h
10h
BLOCK ERASE
60h
D0h
RANDOM DATA INPUT*1
85h
RANDOM DATA OUTPUT*1
05h
E0h
READ PARAMETER PAGE
ECh
READ UNIQUE ID
EDh
GET FEATURES
EEh
SET FEATURES
EFh
READ STATUS ENHANCED
78h
Yes
TWO PLANE READ PAGE
00h
00h
30h
TWO PLANE READ FOR COPY BACK
00h
00h
35h
TWO PLANE RANDOM DATA READ
06h
E0h
TWO PLANE PROGRAM(TRADITIONAL)
80h
11h
81h
10h
TWO PLANE PROGRAM(ONFI)
80h
11h
80h
10h
TWO PLANE PROGRAM FOR COPY
BACK(TRADITIONAL)
85h
11h
81h
10h
TWO PLANE PROGRAM FOR COPY
BACK(ONFI)
85h
11h
85h
10h
TWO PLANE BLOCK ERASE(TRADITIONAL)
60h
60h
D0h
TWO PLANE BLOCK ERASE(ONFI)
60h
D1h
60h
D0h
Table 8-1 Command Table
Notes:
1. RANDOM DATA INPUT and RANDOM DATA OUTPUT command is only to be used within a page.
2. Any commands that are not in the above table are considered as undefined and are prohibited as inputs.
3. Do not cross plane address boundaries when using Copy Back Read and Program for copy back.
W29N02GW/Z
Release Date: August 31th 2018
18 Revision F
9. DEVICE OPERATIONS
9.1 READ Operation
9.1.1 PAGE READ (00h-30h)
When the device powers on, 00h command is latched to command register. Therefore, system only
issues five address cycles and 30h command for initial read from the device. This operation can also
be entered by writing 00h command to the command register, and then write five address cycles,
followed by writing 30h command. After writing 30h command, the data is transferred from NAND
array to Data Register during tR. Data transfer progress can be done by monitoring the status of the
RY/#BY signal output. RY/#BY signal will be LOW during data transfer. Also, there is an alternate
method by using the READ STATUS (70h) command. If the READ STATUS command is issued
during read operation, the Read (00h) command must be re-issued to read out the data from Data
Register. When the data transfer is complete, RY/#BY signal goes HIGH, and the data can be read
from Data Register by toggling #RE. Read is sequential from initial column address to the end of the
page. (See Figure 9-1)
Figure 9-1 Page Read Operations
9.1.2 TWO PLANE READ (00h-00h-30h)
TWO PLANE READ (00h-00h-30h) transfers two pages data from the NAND array to the data
registers. Each page address have to be indicated different plane address.
To set the TWO PLANE READ mode, write the 00h command to the command register, and then
write five address cycles for plane 0. Secondly, write the 00h command to the command register, and
five address cycles for plane 1. Finally, the 30h command is issued. The first-plane and second-plane
addresses must be identical for all of issued address except plane address.
After the 30h command is written, page data is transferred from both planes to their respective data
registers in tR. RY/#BY goes LOW While these are transfered,. When the transfers are complete,
RY/#BY goes HIGH. To read out the data, at first, system writes TWO PLANE RAMDOM DATA READ
(06h-E0h) command to select a plane, next, repeatedly pulse #RE to read out the data from selected
plane. To change the plane address, issues TWO PLANE RANDOM DATA READ (06h-E0h)
Address (5cycles) 30hData Output ( Serial Access )
Don’t care
l/Ox
#RE
RY/#BY
ALE
#WE
#CE
CLE
00h
tR
W29N02GW/Z
Release Date: August 31th 2018
19 Revision F
command to select the another plane address, then repeatedly pulse #RE to read out the data from
the selected plane data register.
Alternatively, data transfers can be monitored by the READ STATUS (70h). When the transfers are
complete, status register bit 6 is set to 1. To read data from the first of the two planes even when
READ STATUS ENHANCED (78h) command is used, the system must issue the TWO PLANE
RANDOM DATA READ (06h-E0h) command at first and pulse #RE repeatedly.
Write a TWO PLANE RANDOM DATA READ (06h-E0h) command to select the other plane ,after the
data cycle is complete. pulse #RE repeatedly to output the data beginning at the specified column
address. During TWO PLANE READ operation,the READ STATUS ENHANCED (78h) command is
prohibited .
Figure 9-2 Two Plane Read Page (00h-00h-30h) Operation
CLE
#WE
ALE
#RE
I/O×
RY/#BY
Col
Add1 Col
Add2 Row
Add1 Row
Add2 Row
Add3 30h
00h
tR
00h
Column address J Plane 1 address
Plane address M
Plane address M
Column address J Plane 0 address
1
CLE
#WE
ALE
#RE
I/O× E0h
06h DOUT0DOUT1DOUTn
Selected Plane data
1
RY/#BY
Plane 0 or Plane 1 address
Address (5cycles)
Col
Add1 Col
Add2 Row
Add1 Row
Add2 Row
Add3
W29N02GW/Z
Release Date: August 31th 2018
20 Revision F
9.1.3 RANDOM DATA OUTPUT (05h-E0h)
The RANDOM DATA OUTPUT allows the selection of random column addresses to read out data
from a single or multiple of addresses. The use of the RANDOM DATA OUTPUT command is
available after the PAGE READ (00h-30h) sequence by writing the 05h command following by the
two cycle column address and then the E0h command. Toggling #RE will output data sequentially.
The RANDOM DATA OUTPUT command can be issued multiple times, but limited to the current
loaded page.
Figure 9-3 Random Data Output
9.1.3.1. TWO PLANE RANDOM DATA OUTPUT (06h-E0h)
TWO PLANE RANDOM DATA READ (06h-E0h) command can indicate to specified plane and
column address on data register . This command is accepted by a device when it is ready.
Issuing 06h to the command register, two column address cycles, three row address cycles, E0h are
followed, this enables data output mode on the address device’s data register at the specified column
address. After the E0h command , the host have to wait at least tWHR before requesting data output.
The selected device is in data output mode until another valid command is issued.
The TWO PLANE RANDOM DATA READ (06h-E0h) command is used to select the data register to
be enabled for data output. When the data output is complete on the selected plane, the command
can be issued again to start data output on another plane.
If there is a need to update the column address without selecting a new data register, the RANDOM
DATA READ (05h-E0h) command can be used instead.
Figure 9-4 Two Plane Random Data Read (06h-E0h) Operation
#RE
RY/#BY
I/Ox 05hE0h
Address(2cycles)
30h
Address(5cycles)
tR
Data out Data out
00h
CLE
ALE
#RE
I/O× E0h
06hData Out
Data Out
#WE
#CE
Address (5cycles)
W29N02GW/Z
Release Date: August 31th 2018
21 Revision F
9.1.4 READ ID (90h)
READ ID command is comprised of two modes determined by the input address, device (00h) or
ONFI (20h) identification information. To enter the READ ID mode, write 90h to the Command
Register followed by a 00h address cycle, then toggle #RE for 5 single byte cycles, W29N02GW/Z.
The pre-programmed code includes the Manufacturer ID, Device ID, and Product-Specific Information
(see Table 9.1). If the READ ID command is followed by 20h address, the output code includes 4
single byte cycles of ONFI identifying information (See Table 9.2). The device remains in the READ
ID Mode until the next valid command is issued.
#WE
CLE
#CE
ALE
#RE
I/Ox 90h00h
(or 20h)
Address 1 Cycle
tAR
tREA
tWHR
Byte0 Byte1 Byte2 Byte3 Byte4
Figure 9-5 Read ID
# of
Byte/Cycles
1st
Byte/Cycle
2nd
Byte/Cycle
3rd
Byte/Cycle
4th
Byte/Cycle
5th
Byte/Cycle
W29N02GZ
EFh
AAh
90h
15h
04h
W29N02GW
EFh
BAh
90h
55h
04h
Description
MFR ID
Device ID
Cache
Programming
not Supported
Page Size:2KB
Spare Area Size:64B
BLK Size w/o Spare:128KB
Organized:x8 or x16
Serial Access:25ns
x16 device : the ID is outputted at word units, and defined lower-byte (IO0-7). ID table shows only lower-byte ID.
Table 9-1 Device ID and configuration codes for Address 00h
# of Byte/Cycles
1st
Byte/Cycle
2nd
Byte/Cycle
3rd
Byte/Cycle
4th
Byte/Cycle
Code
4Fh
4Eh
46h
49h
Table 9-2 ONFI Identifying Codes for Address 20h
W29N02GW/Z
Release Date: August 31th 2018
22 Revision F
9.1.5 READ PARAMETER PAGE (ECh)
READ PARAMETER PAGE can read out the device’s parameter data structure, such as,
manufacturer information, device organization, timing parameters, key features, and other pertinent
device parameters. The data structure is stored with at least three copies in the device’s parameter
page. Figure 9-9 shows the READ PARAMETER PAGE timing. The RANDOM DATA OUTPUT (05h-
E0h) command is supported during data output.
I/Ox
CLE
#WE
ALE
#RE
RY/#BY
ECh P00
00h
tR
・・・
P10P01P11・・・
Figure 9-6 Read Parameter Page
Byte
Description
Value
0-3
Parameter page signature
4Fh, 4Eh, 46h, 49h
4-5
Revision number
02h, 00h
6-7
Features
supported
W29N02GZ
18h,00h
W29N02GW
19h,00h
8-9
Optional commands supported
3Fh,00h
10-31
Reserved
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h
32-43
Device manufacturer
57h, 49h, 4Eh, 42h, 4Fh, 4Eh, 44h, 20h, 20h, 20h, 20h,
20h
44-63
Device model
W29N02GZ
57h,32h,39h,4Eh,30h,32h,47h,5Ah,20h,20h,20h,20h,20
h,20h,20h,20h,20h,20h,20h,20h
W29N02GW
57h,32h,39h,4Eh,30h,32h,47h,57h,20h,20h,20h,20h,20
h,20h,20h,20h,20h,20h,20h,20h
64
Manufacturer ID
EFh
65-66
Date code
00h, 00h
67-79
Reserved
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h
80-83
# of data bytes per page
00h, 08h, 00h, 00h
W29N02GW/Z
Release Date: August 31th 2018
23 Revision F
Byte
Description
Value
84-85
# of spare bytes per page
40h, 00h
86-89
# of data bytes per partial page
00h, 02h, 00h, 00h
90-91
# of spare bytes per partial page
10h, 00h
92-95
# of pages per block
40h, 00h, 00h, 00h
96-99
# of blocks per unit
00h, 08h, 00h, 00h
100
# of logical units
01h
101
# of address cycles
23h
102
# of bits per cell
01h
103-104
Bad blocks maximum per unit
28h, 00h
105-106
Block endurance
01h, 05h
107
Guaranteed valid blocks at beginning of
target
01h
108-109
Block endurance for guaranteed valid
blocks
00h, 00h
110
# of programs per page
04h
111
Partial programming attributes
00h
112
# of ECC bits
01h
113
# of interleaved address bits
01h
114
Interleaved operation attributes
0Ch
115-127
Reserved
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h
128
I/O pin capacitance
0Ah
129-130
Timing mode support
1Fh, 00h
131-132
Program cache timing
1Fh, 00h
133-134
Maximum page program time
BCh, 02h
135-136
Maximum block erase time
10h, 27h
137-138
Maximum random read time
19h, 00h
139-140
tCCS minimum
46h, 00h
141-163
Reserved
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h
164-165
Vendor specific revision #
01h,00h
166-253
Vendor specific
00h
254-255
Integrity CRC
Set at shipment
256-511
Value of bytes 0-255
W29N02GW/Z
Release Date: August 31th 2018
24 Revision F
Byte
Description
Value
512-767
Value of bytes 0-255
>767
Additional redundant parameter pages
x16 device : the ID is outputted at word units, and defined lower-byte (IO0-7). ID table shows only lower-byte ID.
Table 9-3 Parameter Page Output Value
9.1.6 READ STATUS (70h)
The W29N02GW/Z has an 8-bit Status Register which can be read during device operation. Refer to
Table 9.3 for specific Status Register definitions. After writing 70h command to the Command
Register, read cycles will only read from the Status Register. The status can be read from I/O[7:0]
outputs, as long as #CE and #RE are LOW. Note; #RE does not need to be toggled for Status Register
read. The Command Register remains in status read mode until another command is issued. To
change to normal read mode, issue the PAGE READ (00h) command. After the PAGE READ
command is issued, data output starts from the initial column address.
#CE
CLE
#WE
#RE
tCLR
I/Ox 70h Status Output
tREA
Figure 9-7 Read Status Operation
W29N02GW/Z
Release Date: August 31th 2018
25 Revision F
SR bit
Page Read
Page Program
Block Erase
Definition
I/O 0
Not Use
Pass/Fail
Pass/Fail
0=Successful
Program/Erase
1=Error
in Program/Erase
I/O 2
Not Use
Not Use
Not Use
0
I/O 3
Not Use
Not Use
Not Use
0
I/O 4
Not Use
Not Use
Not Use
0
I/O 5
Ready/Busy
Ready/Busy
Ready/Busy
Ready = 1
Busy = 0
I/O 6
Ready/Busy
Ready/Busy
Ready/Busy
Ready = 1
Busy = 0
I/O 7
Write Protect
Write Protect
Write Protect
Unprotected = 1
Protected = 0
Table 9-4 Status Register Bit Definition
9.1.7 READ STATUS ENHANCED (78h)
The READ STATUS ENHANCED (78h) command returns the status of the addressed plane on a
target even when it is busy (SR BIT 6 = 0).
Writing 78h to the command register, followed by three row address cycles containing the page, plane
and block addresses that is same as executed addresses, puts the device into read status mode. The
device stays in this mode until another valid command is issued
The device status is returned when the host requests data output. The SR BIT 6 and SR bit 5 bits of
the status register are shared for all planes on the device. The SR BIT 1 and SR BIT 0 (SR bit0) bits
are specific to the plane specified in the row address.
The READ STATUS ENHANCED (78h) command also enables the device for data output. To begin
data output following a READ operation after the device is ready (SR BIT 6 = 1), issue the READ
MODE (00h) command, then begin data output. If the host needs to change the data register that will
output data, use the TWO PLANE RANDOMDATA READ (06h-E0h) command after the device is
ready.
Use of the READ STATUS ENHANCED (78h) command is prohibited when OTP mode is enabled. It
is also prohibited following some of the other reset, identification.
W29N02GW/Z
Release Date: August 31th 2018
26 Revision F
Figure 9-8 Read Status Enhanced (78h) Operation
CLE
ALE
#RE
I/O× Status Output
78h
#WE
#CE
Address (3cycles)
W29N02GW/Z
Release Date: August 31th 2018
27 Revision F
9.1.8 READ UNIQUE ID (EDh)
The W29N02GW/Z NAND Flash device has a method to uniquely identify each NAND Flash device
by using the READ UNIQUE ID command. The format of the ID is limitless, but the ID for every NAND
Flash device manufactured, will be guaranteed to be unique.
Numerous NAND controllers typically use proprietary error correction code (ECC) schemes. In these
cases Winbond cannot protect unique ID data with factory programmed ECC. However, to ensure
data reliability, Winbond will program the NAND Flash devices with 16 bytes of unique ID code,
starting at byte 0 on the page, immediately followed by 16 bytes of the complement of that unique ID.
The combination of these two actions is then repeated 16 times. This means the final copy of the
unique ID will resides at location byte 511. At this point an XOR or exclusive operation can be
performed on the first copy of the unique ID and its complement. If the unique ID is good, the results
should yield all the bits as 1s. In the event that any of the bits are 0 after the XOR operation, the
procedure can be repeated on a subsequent copy of the unique ID data.
I/Ox
CLE
#WE
ALE
#RE
RY/#BY
EDh
Unique ID data
tR
Byte0 Byte1 Byte14 Byte15
00h
Figure 9-9 Read Unique ID
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Release Date: August 31th 2018
28 Revision F
9.2 PROGRAM Operation
9.2.1 PAGE PROGRAM (80h-10h)
The W29N02GW/Z Page Program command will program pages sequentially within a block, from the
lower order page address to higher order page address. Programming pages out of sequence is
prohibited. The W29N02GW/Z supports partial-page programming operations up to 4 times before
an erase is required if partitioning a page. Note; programming a single bit more than once without
first erasing it is not supported.
9.2.2 SERIAL DATA INPUT (80h)
Page Program operation starts with the execution of the Serial Data Input command (80h) to the
Command Register, following next by inputting five address cycles and then the data is loaded. Serial
data is loaded to Data Register with each #WE cycle. The Program command (10h) is written to the
Command Register after the serial data input is finished. At this time the internal write state controller
automatically executes the algorithms for program and verifies operations. Once the programming
starts, determining the completion of the program process can be done by monitoring the RY/#BY
output or the Status Register Bit 6, which will follow the RY/#BY signal. RY/#BY will stay LOW during
the internal array programming operation during the period of (tPROG). During page program
operation, only two commands are available, READ STATUS (70h) and RESET (FFh). When the
device status goes to the ready state, Status Register Bit 0 (I/O0) indicates whether the program
operation passed (Bit0=0) or failed (Bit0=1), (see Figure 9-13). The Command Register remains in
read status mode until the next command is issued.
Figure 9-10 Page Program
tPROG
Address (5cycles)
RY/#BY
I/Ox Din80h10h70hStatus
I/O0 =0 pass
I/O0 =1 fail
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Release Date: August 31th 2018
29 Revision F
9.2.3 RANDOM DATA INPUT (85h)
After the Page Program (80h) execution of the initial data has been loaded into the Data Register, if
the need for additional writing of data is required, using the RANDOM DATA INPUT (85h) command
can perform this function to a new column address prior to the Program (10h) command. The
RANDOM DATA INPUT command can be issued multiple times in the same page (See Figure 9-14).
Figure 9-11 Random Data Input
9.2.4 TWO PLANE PAGE PROGRAM
TWO PLANE PAGE PROGRAM command make it possible for host to input data to the addressed
plane's data register and queue the data register to be moved to the NAND Flash array.
This command can be issued several times. Each time a new plane address is specified that plane
is also queued for data transfer. To input data for the final plane and to begin the program operation
for all previously queued planes, the PAGE PROGRAM command has to be issued. All of the queued
planes will move the data to the NAND Flash array. When it is ready (SR BIT 6 = 1), this command
is accepted.
At the block and page address is specified, input a page to the data register and queue it to be moved
to the NAND Flash array, the 80h is issued to the command register. Unless this command has been
preceded by a TWO PLANE PAGE PROGRAM command, issuing the 80h to the command register
clears all of the data registers' contents on the selected target. Write five address cycles containing
the column address and row address; data input cycles follow. Serial data is input beginning at the
column address specified. At any time, while the data input cycle, the RANDOM DATA INPUT (85h)
command can be issued. When data input is complete, write 11h to the command register. The device
will go busy (SR BIT 6 = 0, SR BIT 5 = 0) for tDBSY.
To ascertain the progress of tDBSY, the host can monitor the target's RY/#BY signal or, the status
operations (70h, 78h) can be used alternatively. When the device status shows that it is ready (SR
BIT 6 = 1), additional TWO PLANE PAGE PROGRAM commands can be issued to queue additional
planes for data transfer, then, the PAGE PROGRAM commands can be issued.
When the PAGE PROGRAM command is used as the final command of a two plane program
operation, data is transferred from the data registers to the NAND Flash array for all of the addressed
RY/#BY
I/Ox
#WE
ALE
#RE
#CE
Din 70h Status
Address (5cycles)
80h10h
Address
(2cycles)
85hDin
tPROG
Don’t care
CLE
W29N02GW/Z
Release Date: August 31th 2018
30 Revision F
planes during tPROG. When the device is ready (SR BIT 6 = 1, SR BIT 5 = 1), the host should check
the status of the SR BIT 0 for each of the planes to verify that programming completed successfully.
When system issues TWO PLANE PAGE PROGRAM and PAGE PROGRAM commands, READ
STATUS (70h) command can confirm whether the operation(s) passed or failed. If the status after
READ STATUS (70h) command indicates an error (SR BIT 0 = 1 and/or SR BIT 1 = 1), READ
STATUS ENHANCED (78h) command can be determined which plane is failed.
TWO PLANE PROGRAM commands require five-cycle addresses, one address indicates the
operational plane. These addresses are subject to the following requirements:
• The column address bits must be valid address for each plane
• The plane select bit, A18, must be set to “L” for 1st address input, and set to “H” for 2nd address input.
• The page address (A17-A12) and block address (A28-A19) of first input are don’t care. It follows
secondary inputted page address and block address.
Two plane operations must be same type operation across the planes; for example, it is not possible
to perform a PROGRAM operation on one plane with an ERASE operation on another.
Figure 9-12 Two Plane Page Program
RY/#BY
Data
Input
FirstPlane
(1024 block)
Block 0
Block 2
:
Block 2044
Block 2046
Second Plane
(1024 block)
Block 1
Block 3
:
Block 2045
Block 2047
80h
Page program
Setup code
A0-A11=Valid
A12-A17=set to `Low`
A18=set to `Low`
A19-A28=set to `Low`
Confirm
Code Multiplane Page
Program setup
code
A0-A11=Valid
A12-A17=Valid
A18=set to `High`
A19-A28=Valid
Confirm
Code
Read Status
Register
11h81h10h70hSR0
1)The same row address, except for A18, is applied to the two blocks.
2)Any command between 11h and 81h is prohibited except 70h,78h,and FFh
tDBSY tPROG
(Program busy time)
Busy Busy
Address Inputs Data Input Data Input
Address Inputs
l/Ox
80h11h81h10h
※81h:Traditional Protocol 80h:ONFI Protocol
※
W29N02GW/Z
Release Date: August 31th 2018
31 Revision F
9.3 COPY BACK Operation
Copy Back operations require two command sets. Issue a READ for COPY BACK (00h-35h)
command first, then the PROGRAM for COPY BACK (85h-10h) command. Copy back operations are
only supported within a same plane.
9.3.1 READ for COPY BACK (00h-35h)
The READ for COPY BACK command is used together with the PROGRAM for COPY BACK (85h-
10h) command. To start execution, READ for COPY BACK (00h) command is written to the Command
Register, followed by the five cycles of the source page address. To start the transfer of the selected
page data from the memory array to the data register, write the 35h command to the Command
Register.
After execution of the READ for COPY BACK command sequence and RY/#BY returns to HIGH
marking the completion of the operation, the transferred data from the source page into the Data
Register may be read out by toggling #RE. Data is output sequentially from the column address that
was originally specified with the READ for COPY BACK command. RANDOM DATA OUTPUT (05h-
E0h) commands can be issued multiple times without any limitation after READ for COPY BACK
command has been executed (see Figures 9-19 and 9-20).
At this point the device is in ready state to accept the PROGRAM for COPY BACK command.
9.3.2 PROGRAM for COPY BACK (85h-10h)
After the READ for COPY BACK command operation has been completed and RY/#BY goes HIGH,
the PROGRAM for COPY BACK command can be written to the Command Register. The command
results in the transfer of data to the Data Register, then internal operations start programming of the
new destination page. The sequence would be, write 85h to the Command Register, followed by the
five cycle destination page address to the NAND array. Next write the 10h command to the Command
Register; this will signal the internal controller to automatically start to program the data to new
destination page. During this programming time, RY/#BY will LOW. The READ STATUS command
can be used instead of the RY/#BY signal to determine when the program is complete. When Status
Register Bit 6 (I/O6) equals to “1”, Status Register Bit 0 (I/O0) will indicate if the operation was
successful or not.
The RANDOM DATA INPUT (85h) command can be used during the PROGRAM for COPY BACK
command for modifying the original data. Once the data is copied into the Data Register using the
READ for COPY BACK (00h-35h) command, follow by writing the RANDOM DATA INPUT (85h)
command, along with the address of the data to be changed. The data to be changed is placed on
the external data pins. This operation copies the data into the Data Register. Once the 10h command
is written to the Command Register, the original data and the modified data are transferred to the
Data Register, and programming of the new page commences. The RANDOM DATA INPUT
command can be issued numerous times without limitation, as necessary before starting the
programming sequence with 10h command.
Since COPY BACK operations do not use external memory and the data of source page might include
a bit errors, a competent ECC scheme should be developed to check the data before programming
data to a new destination page.
W29N02GW/Z
Release Date: August 31th 2018
32 Revision F
9.3.3 TWO PLANE READ for COPY BACK
To improve read through rate, TWO PLANE READ for COPY BACK operation is copied data
concurrently from one or two plane to the specified data registers.
TWO PLANE PROGRAM for COPY BACK command can move the data in two pages from the data
registers to different pages. This operation improves system performance than PROGRAM for COPY
BACK operation.
9.3.4 TWO PLANE PROGRAM for COPY BACK
Function of TWO PLANE PROGRAM for COPY BACK command is equal to TWO-PLANE PAGE
PROGRAM command, except that when 85h is written to the command register, then data register
contents are not cleared. Refer to TWO-PLANE PAGE PROGRAM for more details features.
W29N02GW/Z
Release Date: August 31th 2018
33 Revision F
Optional No limitation
RY/#BY
I/Ox
tR
CLE
#WE
ALE
#RE
#CE
00h 35h 85h 10h
tPROG
70h
Status
Output
Address(5cycles)
DataOutput
Address
(2cycles)
85h
Don’t care
Address(5Cycles) Data Input Data Input
Figure 9-13 Program for Copy Back Operation
Figure 9-14 Copy Back Operation with Random Data Input
Optional
Data output
No limitation
RY/# BY
I/ Ox
tR tPROG
CLE
#WE
ALE
#RE
#CE
Data Output
00hAddress (5cycles) 35h05hAddress
(2cycles) E0h 85hAddress(5cycles) 10h70hStatus
Output
Don’t care
W29N02GW/Z
Release Date: August 31th 2018
34 Revision F
RY/#BY
I/O× 00h Address(5cycles)
Plane 0 source
00h Address(5cycles)
Plane 1 source
35h
tR
RY/#BY
I/O×
1
85h Address(5cycles)
Plane 0 destination
11h
tDBSY
06h Address(5cycles)
Plane 0 or Plane 1 source address
E0h
#RE
Data Output 06h Address(2cycles)
Data from selected Plane Selected Plane
column address
E0h
#RE
Data Output
Data from selected plane
From new column address
85h Address(5cycles) 10h 70h Status
Plane 1 destination
2
2
RY/#BY
#RE
I/O×
Optional
tPROG
1
Figure 9-15 Two Plane Copy Back
Figure 9-16 Two Plane Copy Back with Random Data Input
00h
I/O× Address(5cycles)
Plane 0 source
00hAddress(5cycles)
Plane 1 source
35h
tR
1
tDBSY
data
Plane 0 destination optional
Unlimited number
of repetitions
85hAddress(5cycles) 10h70hStatus
Plane 1 destination
1
RY/#BY
I/O×
85hData 11h
tPROG
85h
RY/#BY
Address(5cycles) Address(2cycles)
W29N02GW/Z
Release Date: August 31th 2018
35 Revision F
Figure 9-17 Two Plane Program for Copy Back
RY/#BY tR tDBSY
Busy Busy Busy Busy
tPROG
tR
00h 35h 00h 35h 35h Address
(5 cycles) 10h 70h SR0
Col Add.1,2 Row Add.1,2,3
Row Add1,2,3
Col Add1,2
Source address on Plane0 Source address on Plane1
Col Add1,2 Row Add.1,2,3
A0 - A11 = set to `Low’
A12-A17 = Valid
A18 = set to `High’
A19-A28 = Valid
Read
code
Read
code
Copy back
code Copy back
code Read Status Register
85h 11h
Col Add.1,2
Source address on Plane1
Row Add1, 2,3 Destination address on Plane0
l/O Address
(5 cycles)
Address
(5 cycles) Address
(5 cycles) 85h
※
Spare area
SourcePage
TargetPage
Main area
First plane
SourcePage
TargetPage
Main area Spare area
Second plane
(1):Read for copy back on first plane
(2):Read for copy back on second plane
(3):Two-plane copy back program
(1) (3) (2) (3)
※85h:ONFI Protocol
81h:Traditional Protocol
A0 - A11 = don’t care
A12-A17 = don’t care
A18 = set to `Low’
A19- A28 = don’t care
Single plane copy back read can be used to two plane operation.
W29N02GW/Z
Release Date: August 31th 2018
36 Revision F
9.4 BLOCK ERASE Operation
9.4.1 BLOCK ERASE (60h-D0h)
Erase operations happen at the architectural block unit. This W29N02GW/Z has 2048 erase blocks.
Each block is organized into 64 pages (x8:2112 bytes/page, x16:1056 words/page), 132K bytes
(x8:128K + 4K bytes, x16:64 K+ 2Kwords)/block. The BLOCK ERASE command operates on a block
by block basis.
Erase Setup command (60h) is written to the Command Register. Next, the three cycle block address
is written to the device. The page address bits are loaded during address block address cycle, but
are ignored. The Erase Confirm command (D0h) is written to the Command Register at the rising
edge of #WE, RY/#BY goes LOW and the internal controller automatically handles the block erase
sequence of operation. RY/#BY goes LOW during Block Erase internal operations for a period of
tBERS,
The READ STATUS (70h) command can be used for confirm block erase status. When Status
Register Bit6 (I/O6) becomes to “1”, block erase operation is finished. Status Register Bit0 (I/O0) will
indicate a pass/fail condition (see Figure 9-24).
CLE
#WE
ALE
RY/#BY
#CE
#RE
I/Ox
tBERS I / O 0 =0 pass
I/ O 0 =1 fail
Address Input (3cycles)
60hD0h Status Output
70h
Don’t care
Figure 9-18 Block Erase Operation
W29N02GW/Z
Release Date: August 31th 2018
37 Revision F
9.4.2 TWO PLANE BLOCK ERASE
TWO PLANE BLOCK ERASE (60h-D1h) command indicates two blocks in the specified plane that is
to be erased. To start ERASE operation for indicated blocks in the specified plane, write the BLOCK
ERASE (60h-D0h) command.
To indicate a block to be erased, writing 60h to the command register, then, write three address cycles
containing the row address, the page address is ignored. By writing D1h command to command
register, the device will go busy (SR BIT 6 = 0, SR BIT 5 = 0) for tDBSY.
To confirm busy status during tDBSY, the host can monitor RY/#BY signal. Instead, system can use
READ STATUS (70h) or READ STATUS ENHANCED (78h) commands. When the status shows
ready (SR BIT 6 = 1, SR BIT 5 = 1), additional TWO PLANE BLOCK ERASE commands can be
issued for erasing two blocks in a specified plane.
When system issues TWO PLANE BLOCK ERASE (60h-D1h), and BLOCK ERASE (60h-D0h)
commands, READ STATUS (70h) command can confirm whether the operation(s) passed or failed.
If the status after READ STATUS (70h) command indicates an error (SR BIT 0 = 1), READ STATUS
ENHANCED (78h) command can be determined which plane is failed.
TWO PLANE BLOCK ERASE commands require three cycles of row addresses; one address
indicates the operational plane. These addresses are subject to the following requirements:
• The plane select bit, A18, must be set to “L” for 1st address input, and set to “H” for 2nd address input.
• The block address (A29-A19) of first address input is don’t care. It follows secondary inputted block address.
Two plane operations must be same type operation across the planes; for example, it is not possible
to perform a PROGRAM operation on one plane with an ERASE operation on another.
Figure 9-19 Two Plane Block Erase Operation
RY/#BY
CLE
#WE
ALE
#RE
I/Ox
Busy
R1A R2A R3A 60hR1B R2B D0h
D1h R3B
tBERS
Busy
tDBSY
#CE
60h
Don’t care
A17-A12 = don’t care
A18 = set to “Low”
A29-A19 = don’t care
A17-A12 = don’t care
A18 = set to “High”
A29-A19 = Valid
W29N02GW/Z
Release Date: August 31th 2018
38 Revision F
9.5 RESET Operation
9.5.1 RESET (FFh)
READ, PROGRAM, and ERASE commands can be aborted by the RESET (FFh) command during
the time the W29N02GW/Z is in the busy state. The Reset operation puts the device into known status.
The data that is processed in either the programming or erasing operations are no longer valid. This
means the data can be partially programmed or erased and therefore data is invalid. The Command
Register is cleared and is ready to accept next command. The Data Register contents are marked
invalid.
The Status Register indicates a value of E0h when #WP is HIGH; otherwise a value of 60h is written
when #WP is LOW. After RESET command is written to the command register, RY/#BY goes LOW
for a period of tRST (see Figure 9-26).
CLE
#WE
RY/#BY
#CE
I/Ox
RESET
command
tRST
tWB
FFh
Figure 9-20 Reset Operation
W29N02GW/Z
Release Date: August 31th 2018
39 Revision F
9.6 FEATURE OPERATION
The GET FEATURES (EEh) and SET FEATURES (EFh) commands are used to change the NAND
Flash device behavior from the default power on settings. These commands use a one-byte feature
address to determine which feature is to be read or modified. A range of 0 to 255 defines all features;
each is described in the features table (see Table 9.5 thru 9.7). The GET FEATURES (EEh) command
reads 4-Byte parameter in the features table (See GET FEATURES function). The SET FEATURES
(EFh) command places the 4-Byte parameter in the features table (See SET FEATURES function).
When a feature is set, meaning it remains active by default until the device is powered off. The set
feature remains the set even if a RESET (FFh) command is issued.
Feature address
Description
00h
N.A
02h-7Fh
Reserved
80h
Vendor specific parameter : Programmable I/O drive strength
81h
Vendor specific parameter : Programmable RY/#BY pull-down strength
82h-FFh
Reserved
Table 9-5 Features
W29N02GW/Z
Release Date: August 31th 2018
40 Revision F
Feature Address 80h: Programmable I/O Drive Strength
Sub feature
parameter
Options
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
Value
Notes
P1
I/O
drive strength
Full (default)
Reserved (0)
0
0
00h
1
Three-quarters
Reserved (0)
0
1
01h
One-half
Reserved (0)
1
0
02h
One-quarter
Reserved (0)
1
1
03h
P2
Reserved (0)
00h
P3
Reserved (0)
00h
P4
Reserved (0)
00h
Table 9-6 Feature Address 80h
Note:
1. The default drive strength setting is Full strength. The Programmable I/O Drive Strength mode is used to
change from the default I/O drive strength. Drive strength should be selected based on expected loading of
the memory bus. This table shows the four supported output drive-strength settings. The device returns to
the default drive strength mode when a power cycle has occurred. AC timing parameters may need to be
relaxed if I/O drive strength is not set to full.
W29N02GW/Z
Release Date: August 31th 2018
41 Revision F
Feature Address 81h: Programmable RY/#BY Pull-down Strength
Sub feature
parameter
Options
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
Value
Notes
P1
RY/#BY
pull-down
strength
Full (default)
Reserved (0)
0
0
00h
1
Three-quarters
Reserved (0)
0
1
01h
One-half
Reserved (0)
1
0
02h
One-quarter
Reserved (0)
1
1
03h
P2
Reserved (0)
00h
P3
Reserved (0)
00h
P4
Reserved (0)
00h
Table 9-7 Feature Address 81h
Note:
1. The default programmable RY/#BY pull-down strength is set to Full strength. The pull-down strength is used
to change the RY/#BY pull-down strength. RY/#BY pull-down strength should be selected based on expected
loading of RY/#BY. The four supported pull-down strength settings are shown. The device returns to the
default pull-down strength when a power cycle has occurred.
W29N02GW/Z
Release Date: August 31th 2018
42 Revision F
9.6.1 GET FEATURES (EEh)
The GET FEATURES command returns the device feature settings including those previously set by
the SET FEATURES command. To use the Get Feature mode write the command (EEh) to the
Command Register followed by the single cycle byte Feature Address. RY/#BY will goes LOW for the
period of tFEAT. If Read Status (70h) command is issued for monitoring the process completion
status, Read Command (00h) has to be executed to re-establish data output mode. Once, RY/#BY
goes HIGH, the device feature settings can be read by toggling #RE. The device remains in Feature
Mode until another valid command is issued to Command Register. See Figure 9-27.
I/Ox
CLE
#WE
ALE
#RE
RY/#BY
FA
Feature address
1 cycle
#CE
EEh
tFEAT
P1 P2 P4P3
Figure 9-21 Get Feature Operation
W29N02GW/Z
Release Date: August 31th 2018
43 Revision F
9.6.2 SET FEATURES (EFh)
The SET FEATURES command sets the behavior parameters by selecting a specified feature
address. To change device behavioral parameters, execute Set Feature command by writing EFh to
the Command Register, followed by the single cycle feature address. Each feature parameter (P1-
P4) is latched at the rising edge of each #WE. The RY/#BY signal will go LOW during the period of
tFEAT while the four feature parameters are stored. The Read Status (70h) command can be issued
for monitoring the progress status of this operation. The parameters are stored in device until the
device goes through a power on cycle. The device remains in feature mode until another valid
command is issued to Command Register.
I/Ox
CLE
#WE
ALE
#RE
RY/#BY
FA
#CE
EFh
tFEAT
P1 P2 P4P3
tWB
tADL
Figure 9-22 Set Feature Operation
W29N02GW/Z
Release Date: August 31th 2018
44 Revision F
9.7 ONE TIME PROGRAMMABLE (OTP) Area
The device has One-Time Programmable (OTP) memory area comprised of a number of pages (2112
bytes/page) (1056words/page). This entire range of pages is functionally guaranteed. Only the OTP
commands can access the OTP area. When the device ships from Winbond, the OTP area is in an
erase state (all bits equal “1”). The OTP area cannot be erased, therefore protecting the area only
prevent further programming. Contact to Winbond for using this feature.
W29N02GW/Z
Release Date: August 31th 2018
45 Revision F
9.8 WRITE PROTECT
#WP pin can enable or disable program and erase commands preventing or allowing program and
erase operations. Figure 9-29 to 9-34 shows the enabling or disabling timing with #WP setup time
(tWW) that is from rising or falling edge of #WP to latch the first commands. After first command is
latched, #WP pin must not toggle until the command operation is complete and the device is in the
ready state. (Status Register Bit5 (I/O5) equal 1)
I/Ox
#WE
#WP
tWW
RY/#BY
60h D0h
Figure 9-23 Erase Enable
I/Ox
#WE
#WP
tWW
RY/#BY
60hD0h
Figure 9-24 Erase Disable
I/Ox
#WE
#WP
tWW
RY/#BY
10h
( or 15h)
80h
Figure 9-25 Program Enable
W29N02GW/Z
Release Date: August 31th 2018
46 Revision F
I/Ox
#WE
#WP
80 h
tWW
RY/#BY
10h
( or 15h)
Figure 9-26 Program Disable
I/Ox
#WE
#WP
85h
tWW
RY/#BY
10h
Figure 9-27 Program for Copy Back Enable
I/Ox
#WE
#WP
85h
tWW
RY/#BY
10 h
Figure 9-28 Program for Copy Back Disable
W29N02GW/Z
Release Date: August 31th 2018
47 Revision F
9.9 BLOCK LOCK
The device has block lock feature that can protect the entire device or user can indicate a ranges of
blocks from program and erase operations. Using this feature offers increased functionality and
flexibility data protection to prevent unexpected program and erase operations. Contact to Winbond
for using this feature.
W29N02GW/Z
Release Date: August 31th 2018
48 Revision F
10. ELECTRICAL CHARACTERISTICS
10.1 Absolute Maximum Ratings (1.8V)
PARAMETERS
SYMBOL
CONDITIONS
RANGE
UNIT
Supply Voltage
VCC
–0.6 to +2.4
V
Voltage Applied to Any Pin
VIN
Relative to Ground
–0.6 to +2.4
V
Storage Temperature
TSTG
–65 to +150
°C
Short circuit output current, I/Os
5
mA
Table 10-1 Absolute Maximum Ratings
Notes:
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for
periods <30ns.
2. Maximum DC voltage on input/output pins is Vcc+0.3V which, during transitions, may overshoot to Vcc+2.0V
for periods <20ns.
3. This device has been designed and tested for the specified operation ranges. Proper operation outside of
these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability.
Exposure beyond absolute maximum ratings may cause permanent damage.
10.2 Operating Ranges (1.8V)
PARAMETER
SYMBOL
CONDITIONS
SPEC
UNIT
MIN
MAX
Supply Voltage
VCC
1.7
1.95
V
Ambient Temperature,
Operating
TA
Industrial
-40
+85
°C
Industrial Plus
-40
+105
°C
Table 10-2 Operating Ranges
W29N02GW/Z
Release Date: August 31th 2018
49 Revision F
10.3 Device Power-up Timing
The device is designed to avoid unexpected program/erase operations during power transitions.
When the device is powered on, an internal voltage detector disables all functions whenever Vcc is
below about 1.1V at 1.8V device. Write Protect (#WP) pin provides hardware protection and is
recommended to be kept at VIL during power up and power down. A recovery time of minimum 1ms
is required before internal circuit gets ready for any command sequences (See Figure 10-1).
Figure 10-1 Power ON/OFF Sequence
5 ms (Max)
Vcc
RY/#BY
1ms
(Min)
Undefined
#WP
#WE
W29N02GW/Z
Release Date: August 31th 2018
50 Revision F
10.4 DC Electrical Characteristics (1.8V)
PARAMETER
SYMBOL
CONDITIONS
SPEC
UNIT
MIN
TYP
MAX
Sequential Read current
Icc1
tRC= tRC MIN
#CE=VIL
IOUT=0mA
-
13
20
mA
Program current
Icc2
-
-
10
20
mA
Erase current
Icc3
-
-
10
20
mA
Standby current (TTL)
ISB1
#CE=VIH
#WP=0V/Vcc
-
-
1
mA
Standby current (CMOS)
Industrial
ISB2
#CE=Vcc – 0.2V
#WP=0V/Vcc
-
10
50
µA
Standby current (CMOS)
Industrial Plus
-
10
100
µA
Input leakage current
ILI
VIN= 0 V to Vcc
-
-
±10
µA
Output leakage current
ILO
VOUT=0V to Vcc
-
-
±10
µA
Input high voltage
VIH
I/O15~0, #CE,#WE,#RE,
#WP,CLE,ALE
0.8 x Vcc
-
Vcc + 0.3
V
Input low voltage
VIL
-
-0.3
-
0.2 x Vcc
V
Output high voltage(1)
VOH
IOH=-100µA
Vcc -0.1
-
-
V
Output low voltage(1)
VOL
IOL=+100µA
-
-
0.1
V
Output low current
IOL(RY/#BY)
VOL=0.2V
3
4
mA
Table 10-3 DC Electrical Characteristics
Note:
1. VOH and VOL may need to be relaxed if I/O drive strength is not set to full.
W29N02GW/Z
Release Date: August 31th 2018
51 Revision F
10.5 AC Measurement Conditions (1.8V)
PARAMETER
SYMBOL
SPEC
UNIT
MIN
MAX
Input Capacitance(1), (2)
CIN
-
10
pF
Input/Output Capacitance(1), (2)
CIO
-
10
pF
Input Rise and Fall Times
TR/TF
-
2.5
ns
Input Pulse Voltages
-
0 to VCC
V
Input/Output timing Voltage
-
Vcc/2
V
Output load (1)
CL
1TTL GATE and CL=30pF
-
Table 10-4 AC Measurement Conditions
Notes:
1. Verified on device characterization , not 100% tested
2. Test conditions TA=25’C, f=1MHz, VIN=0V
W29N02GW/Z
Release Date: August 31th 2018
52 Revision F
10.6 AC Timing Characteristics for Command, Address and Data Input (1.8V)
PARAMETER
SYMBOL
SPEC
UNIT
MIN
MAX
ALE to Data Loading Time
tADL
70
-
ns
ALE Hold Time
tALH
5
-
ns
ALE setup Time
tALS
10
-
ns
#CE Hold Time
tCH
5
-
ns
CLE Hold Time
tCLH
5
-
ns
CLE setup Time
tCLS
10
-
ns
#CE setup Time
tCS
20
-
ns
Data Hold Time
tDH
5
-
ns
Data setup Time
tDS
10
-
ns
Write Cycle Time
tWC
35
-
ns
#WE High Hold Time
tWH
10
-
ns
#WE Pulse Width
tWP
12
-
ns
#WP setup Time
tWW
100
-
ns
Table 10-5 AC Timing Characteristics for Command, Address and Data Input
Note:
1. tADL is the time from the #WE rising edge of final address cycle to the #WE rising edge of first data cycle.
W29N02GW/Z
Release Date: August 31th 2018
53 Revision F
10.7 AC Timing Characteristics for Operation (1.8V)
PARAMETER
SYMBOL
SPEC
UNIT
MIN
MAX
ALE to #RE Delay
tAR
10
-
ns
#CE Access Time
tCEA
-
30
ns
#CE HIGH to Output High-Z(1)
tCHZ
-
50
ns
CLE to #RE Delay
tCLR
10
-
ns
#CE HIGH to Output Hold
tCOH
15
-
ns
Output High-Z to #RE LOW
tIR
0
-
ns
Data Transfer from Cell to Data Register
tR
-
25
µs
READ Cycle Time
tRC
35
-
ns
#RE Access Time
tREA
-
25
ns
#RE HIGH Hold Time
tREH
10
-
ns
#RE HIGH to Output Hold
tRHOH
15
-
ns
#RE HIGH to #WE LOW
tRHW
100
-
ns
#RE HIGH to Output High-Z(1)
tRHZ
-
100
ns
#RE LOW to output hold
tRLOH
3
-
ns
#RE Pulse Width
tRP
12
-
ns
Ready to #RE LOW
tRR
20
-
ns
Reset Time (READ/PROGRAM/ERASE)(2)
tRST
-
5/10/500
µs
#WE HIGH to Busy(3)
tWB
-
100
ns
#WE HIGH to #RE LOW
tWHR
80
-
ns
Table 10-6 AC Timing Characteristics for Operation
Notes: AC characteristics may need to be relaxed if I/O drive strength is not set to “full.”
1. Transition is measured ±200mV from steady-state voltage with load. This parameter is sampled and not
100 % tested
2. Do not issue new command during tWB, even if RY/#BY is ready.
W29N02GW/Z
Release Date: August 31th 2018
54 Revision F
10.8 Program and Erase Characteristics
PARAMETER
SYMBOL
SPEC
UNIT
TYP
MAX
Number of partial page programs
NoP
-
4
cycles
Page Program time
tPROG
250
700
µs
Busy Time for SET FEATURES /GET FEATURES
tFEAT
-
1
µs
Busy Time for program/erase at locked block
tLBSY
-
3
µs
Busy Time for OTP program when OTP is protected
tOBSY
-
30
µs
Block Erase Time
tBERS
2
10
ms
Last Page Program time (1)
tLPROG
-
-
-
Busy Time for Two Plane page program and Two Plane Block
Erase
tDBSY
0.5
1
µs
Table 10-7 Program and Erase Characteristics
Note:
1. tLPROG = Last Page program time (tPROG) + Last -1 Page program time (tPROG) – Last page Address,
Command and Data load time.
W29N02GW/Z
Release Date: August 31th 2018
55 Revision F
11. TIMING DIAGRAMS
Figure 11-1 Command Latch Cycle
Figure 11-2 Address Latch Cycle
tCS
Command
tWP
tCLHtCLS
tCH
tALS tALH
tDS tDH
Don’t care
CLE
#WE
ALE
I/Ox
#CE
tCS
Address
tWP
tWC
tALS tALH
tDS tDH
tCLS
tWH
Don’t care Undefined
CLE
#CE
I/Ox
#WE
ALE
W29N02GW/Z
Release Date: August 31th 2018
56 Revision F
Figure 11-3 Data Latch Cycle
Note:
1. Din Final = 2,111(x8)
Figure 11-4 Serial Access Cycle after Read
Din 0
tWP
tCLH
tALS
tDS tDH
tWP tWP
Din 1
tDS tDH
tWH
Din Final1
tDS tDH
tCH
tWC
Don’t care
CLE
#CE
I/Ox
#WE
ALE
tCHZ
tCEA
tRP
tRHZ
Dout Dout
tREA
tREH
tREA
Dout
tREA
tRHOH
tCOH
tRHZ
tRR tRC
Don’t care
#CE
I/Ox
#RE
RY/#BY
W29N02GW/Z
Release Date: August 31th 2018
57 Revision F
Figure 11-5 Serial Access Cycle after Read (EDO)
Figure 11-6 Read Status Operation
tCHZ
tCEA
tRP
Dout
tREA
tREH
tREA
tCOH
tRHZ
tRR
tRC
Dout
tRHOH
tRLOH
Don’t care
I/Ox
RY/#BY
#RE
#CE
Dout
#CE
#RE
#WE
tWP tCH
tRHZ
tCHZ
CLE
I/Ox
tCOH
Status
output
tRHOH
tRP
tCEA
tCS
tCLR
tCLS tCLH
70h
tDS tDH tIR tREA
tWHR
Don’t care
W29N02GW/Z
Release Date: August 31th 2018
58 Revision F
Busy
Dout
n+1
Dout
n
Dout
m
00h 30h
tAR
tWB
tCLR
tRC
tRR
tWC
tRP
tRHZ
tR
I/Ox
#WE
ALE
#RE
RY/#BY
CLE
#CE
Don’t care
Address(5Cycles)
Figure 11-7 Page Read Operation
CLE
#WE
ALE
RY/#BY
#CE
#RE
I/Ox
Out
tCEA
tREA
tCOH
tCHZ
#CE
#RE
I/Ox
tR
00hAddress (4 cycles) 30hData output
Don’t care
Figure 11-8 #CE Don't Care Read Operation
W29N02GW/Z
Release Date: August 31th 2018
59 Revision F
tRC
tRR
Column address n
tREA
Column address m
tCLR
tAR
tWB
tWC
tWHR
00h30h05h E0h
Busy
tR
#WE
ALE
#RE
RY/#BY
CLE
#CE
I/Ox
Don’t care
Figure 11-9 Random Data Output Operation
W29N02GW/Z
Release Date: August 31th 2018
60 Revision F
I/Ox
#WE
#RE
CLE
#CE
ALE
tAR
90h
(or 20h)
Address, 1 cycle
00hByte 1Byte 0
tREA
Byte 2 Byte 4
Byte 3
tWHR
Figure 11-10 Read ID
I/Ox
#WE
ALE
#RE
RY/#BY
CLE
#CE
80hCol
add 1 Col
add 2
tWC
Row
add 1 Row
add 2 Status
SERIAL DATA
INPUT command
70h
tPROGtWB
tADL
10h
1 up to m Byte
serial input
PROGRAM
command
READ STATUS
command
x8 device:m = 2112 bytes
tWHR
Don’t care
Figure 11-11 Page Program
W29N02GW/Z
Release Date: August 31th 2018
61 Revision F
I/Ox
CLE
#WE
ALE
#CE
80hAddress(4 cycles) Data input Data input 10h
#WE
#CE
tCS tCH
tWP
Don’t care
Figure 11-12 #CE Don't Care Page Program Operation
W29N02GW/Z
Release Date: August 31th 2018
62 Revision F
I/Ox
CLE
#WE
ALE
#RE
#CE
80hCol
add 2
Col
add 1
ｔWC
Din
ｎ
Din
N+1
Serial Data
Input Command
85hStatus
70h
10h
Din
N+1
Serial INPUT
Command
Program
Command
tADL
tWB
tPROG
Random Data Input
Command
RY/#BY
Column address Serial INPUT
Row
add2
tADL
Col
add1 Col
add2 Din
ｎ
Don’t care
Row
add1
Figure 11-13 Page Program with Random Data Input
Figure 11-14 Copy Back
00h
ｔWC
Serial data INPUT
Command
tADL
Program
Command
tWB
tPROG
I/Ox
CLE
#WE
ALE
#RE
#CE
RY/#BY
tWB
tR
Busy
Col
add 1 Col
add 2 Row
add1 Row
add2 35h85hCol
add 1 Col
add 2 Row
add1 Row
add2 Din
1Din
n10h Status
70h
Don’t care
W29N02GW/Z
Release Date: August 31th 2018
63 Revision F
#RE
RY/#BY
CLE
#CE
#WE
ALE
Busy
60h D0h
tBERS
tWC
Status
70h
BLOCK ERASE SETUP
command
ERASE
command READ STATUS
command
tWB
I/Ox
Don’t care
Address(3cycles)
Figure 11-15 Block Erase
I/Ox
#WE
RY/#BY
CLE
#CE
FFh
tRST
RESET
command
tWB
Figure 11-16 Reset
W29N02GW/Z
Release Date: August 31th 2018
64 Revision F
12. INVALID BLOCK MANAGEMENT
12.1 Invalid Blocks
The W29N02GW/Z may have initial invalid blocks when it ships from factory. Also, additional invalid
blocks may develop during the use of the device. Nvb represents the minimum number of valid blocks
in the total number of available blocks (See Table 12.1). An invalid block is defined as blocks that
contain one or more bad bits. Block 0, block address 00h is guaranteed to be a valid block at the time
of shipment.
Parameter
Symbol
Min
Max
Unit
Valid block number
Nvb
2008
2048
blocks
Table 12-1 Valid Block Number
12.2 Initial Invalid Blocks
Initial invalid blocks are defined as blocks that contain one or more invalid bits when shipped from
factory.
Although the device contains initial invalid blocks, a valid block of the device is of the same quality
and reliability as all valid blocks in the device with reference to AC and DC specifications. The
W29N02GW/Z has internal circuits to isolate each block from other blocks and therefore, the invalid
blocks will not affect the performance of the entire device.
Before the device is shipped from the factory, it will be erased and invalid blocks are marked. All initial
invalid blocks are marked with non-FFh at the first byte of spare area on the 1st or 2nd page. The initial
invalid block information cannot be recovered if inadvertently erased. Therefore, software should be
created to initially check for invalid blocks by reading the marked locations before performing any
program or erase operation, and create a table of initial invalid blocks as following flow chart
W29N02GW/Z
Release Date: August 31th 2018
65 Revision F
Figure 12-1 Flow Chart of Create Initial Invalid Block Table
12.3 Error in Operation
Additional invalid blocks may develop in the device during its life cycle. Following the procedures
herein is required to guarantee reliable data in the device.
After each program and erase operation, check the status read to determine if the operation failed. In
case of failure, a block replacement should be done with a bad-block management algorithm. The
system has to use a minimum 1-bit ECC per 528 bytes of data to ensure data recovery.
Operation
Detection and recommended procedure
Erase
Status read after erase Block Replacement
Program
Status read after program Block Replacement
Read
Verify ECC ECC correction
Table 12-2 Block Failure
W29N02GW/Z
Release Date: August 31th 2018
66 Revision F
Figure 12-2 Bad Block Replacement
Note:
1. An error happens in the nth page of block A during program or erase operation.
2. Copy the data in block A to the same location of block B which is valid block.
3. Copy the nth page data of block A in the buffer memory to the nth page of block B
4. Creating or updating bad block table for preventing further program or erase to block A
.
12.4 Addressing in Program Operation
The pages within the block have to be programmed sequentially from LSB (least significant bit) page
to the MSB (most significant bit) within the block. The LSB is defined as the start page to program,
does not need to be page 0 in the block. Random page programming is prohibited.
W29N02GW/Z
Release Date: August 31th 2018
67 Revision F
13. PACKAGE DIMENSIONS
13.1 TSOP 48-pin 12x20
Figure 13-1 TSOP 48-pin 12x20mm
e
1
48
b
E
D
Y
A1
A
A2
L1
L
c
H
D
0.020
0.004
0.007
0.037
0.002
MIN.
0.60
Y
L
L1
c
0.50
0.10
0.70
0.21
MILLIMETER
A
A2
b
A1
0.95
0.17
0.05
Symbol
MIN.
1.20
0.27
1.05
1.00
0.22
MAX.
NOM.
0.028
0.008
0.024
0.011
0.041
0.047
0.009
0.039
NOM.
INCH
MAX.
E
H
D
0
5
0
5
e
D
18.3
18.4
18.5
19.8
20.0
20.2
11.9
12.0
12.1
0.720
0.724
0.728
0.780
0.787
0.795
0.468
0.472
0.476
0.10
0.80
0.031
0.004
0.020
0.50
W29N02GW/Z
Release Date: August 31th 2018
68 Revision F
13.2 Fine-Pitch Ball Grid Array 63-ball
Figure 13-2 Fine-Pitch Ball Grid Array 63-Ball
W29N02GW/Z
Release Date: August 31th 2018
69 Revision F
14. ORDERING INFORMATION
Figure 14-1 Ordering Part Number Description
Winbond Standard Product
W: Winbond
Product Family
ONFI compatible NAND Flash memory
Density
02: 2 Gbit
Product Version
G
Supply Voltage and Bus Width
W: 1.7~1.95V and X16 device
Z: 1.7~1.95V and X8 device
Packages
B: VFBGA-63
Temperature Ranges
I: -40 to 85'C
Option Information
B: OTP Command Supported
(Contact Winbond for Option Information)
Reserved
A: General Product
W
29N
02
G
W
I
B
A
B
S: TSOP-48
J: -40 to 105'C
W29N02GW/Z
Release Date: August 31th 2018
70 Revision F
15. VALID PART NUMBERS
The following table provides the valid part numbers for the W29N02GW/Z NAND Flash Memory.
Please contact Winbond for specific availability by density and package type. Winbond NAND Flash
memories use a 12-digit Product Number for ordering.
Part Numbers for Industrial Grade Temperature:
PACKAGE
TYPE
DENSITY
VCC
BUS
PRODUCT NUMBER
TOP SIDE MARKING
S
TSOP-48
2G-bit
1.8V
X8
W29N02GZSIBA
W29N02GZSIBA
S
TSOP-48
2G-bit
1.8V
X16
W29N02GWSIBA
W29N02GWSIBA
B
VFBGA-63
2G-bit
1.8V
X8
W29N02GZBIBA
W29N02GZBIBA
B
VFBGA-63
2G-bit
1.8V
X16
W29N02GWBIBA
W29N02GWBIBA
Table 15-1 Part Numbers for Industrial Grade Temperature
Part Numbers for Industrial Plus Grade Temperature:
PACKAGE
TYPE
DENSITY
VCC
BUS
PRODUCT NUMBER
TOP SIDE MARKING
S
TSOP-48
2G-bit
1.8V
X8
W29N02GZSJBA
W29N02GZSJBA
S
TSOP-48
2G-bit
1.8V
X16
W29N02GWSJBA
W29N02GWSJBA
B
VFBGA-63
2G-bit
1.8V
X8
W29N02GZBJBA
W29N02GZBJBA
B
VFBGA-63
2G-bit
1.8V
X16
W29N02GWBJBA
W29N02GWBJBA
Table 15-2 Part Numbers for Industrial Plus Grade Temperature
W29N02GW/Z
Release Date: August 31th 2018
71 Revision F
16. REVISION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
0.1
08/22/14
New Create as preliminary
0.2
10/23/14
77
79
Update POD
Correct Valid Part Numbers
0.3
05/19/15
Remove Cache operation mode
0.4
10/14/15
21
Update Read Parameter Page
A
10/15/15
Remove “Preliminary”
B
02/01/16
21, 22, 47
Update Parameter Page Output Value
Update Notes of Absolute Maximum Ratings
C
03/28/16
8, 67, 69, 70
Add TSOP-48 package
D
05/10/16
52, 53
Update AC timing characteristics
E
12/04/17
11
37
Change description of DNU
Change A18 address input requirement of Two Plane
Block Erase operation
F
08/31/18
48, 50, 69, 70
Add Industrial Plus Grade
Table 16-1 History Table
Trademarks
Winbond is trademark of Winbond Electronics Corporation.
All other marks are the property of their respective owner.
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in
systems or equipment intended for surgical implantation, atomic energy control instruments, airplane
or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, or for other applications intended to support or sustain life. Furthermore, Winbond
products are not intended for applications wherein failure of Winbond products could result or lead to
a situation where in personal injury, death or severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their own
risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
