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FEATURES
10 years minimu m data r et ent io n in the
absence o f exter na l po w er
Dat a is automatically pro tect ed d uring power
loss
Power sup ply monit or r e sets processor when
VCC pow er loss oc cu rs and holds proc essor in
reset during VCC ramp-up
Batt er y monitor checks rema in ing capacity
daily
Read and wr it e access times of 70ns
Unlim ited write cycle endurance
Typ ical st and by curre nt 5 0µA
Upgrade for 512k x 8 SRAM, EEPROM, or
Flash
Lit h iu m bat tery is elect ricall y d isconnect ed to
retain fres hne ss u ntil power is app lied for the
first time
Full ±10% VCC o per ating range (DS1350Y)
or optional ±5% VCC op er ating range
(DS1350AB)
Optional indust rial temperatu r e r ange of
-40°C to +85°C, des ig nat ed I N D
Power Cap Modu le (PCM) packag e
- D ir ect ly sur face-mountable mo dule
- Rep laceab le snap-on Po werCap provides
lit hiu m backup bat ter y
- Standardized pino ut for all non volatile
(NV) SRAM pro ducts
- Det achme nt featur e on PowerCap a llows
easy removal using a regular screwdriver
PIN ASSIGNMENT
PIN DESCRIPTION
A0 – A18 - Address Inputs
DQ0 – DQ7 - Data I n/Dat a Out
CE
- Chip Enable
WE
- Wr ite E nable
OE
- Output Enable
RST
- Res et O utp ut
BW
- B at ter y Warn in g
VCC - Po w er (+5V)
GND - Ground
DESCRIPTION
The DS1350 4096k NV SRAMs are 4,194,304 bit, fully stat ic, NV SRAMs organiz ed as 524,288 wo rds
by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry, which
constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium
energy source is automatically switched on and write protection is unconditionally enabled to prevent
data corruption. Additionally, the DS1350 devices have dedicated circuitry for monitoring the status of
VCC and the status of the internal lit hium battery. DS1350 devices in the Po werCap Module package are
direct ly sur fac e mountable and are nor mally paired with a DS9034PC PowerCap to form a complete NV
SRAM modu le. The devices can be used in p lace o f 512k x 8 SRAM, EEP ROM or Flash components.
DS1350Y/AB
4096k Nonvolatile SRAM
with Battery Mon i to r
19-5585; Rev 10/10
www.maxim-ic.com
1
BW
2
3
A15
A16
RST
VCC
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
4
5
6
7
8
9
10
11
12
13
14
15
16
17
A17
A14
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
34
A18
GND
VBAT
34-P in PowerCa p Module (PCM)
(Uses DS9034PC+ or DS9034PCI+ PowerCap)
DS1350Y/AB
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READ MODE
The DS1350 devices execute a read cycle whenever
WE
(Write Enable) is inact ive (high) and
CE
(Chip
Ena ble ) and
OE
(Output Enable) are active (low). The unique address specified by the 19 address inputs
(A0 -A18) defines which o f t he 524,288 byte s of d ata is t o be accessed. Valid data w ill be a vailable to the
e ig ht dat a out put dr ivers w it hin t ACC (Access T ime) after the last address input sig nal is stable, providing
that
CE
and
OE
(Output Enable) access times are also satisfied. If
OE
and
CE
access times are not
sat isfied, t he n dat a access must be measured fro m t he later -occurring s ig na l (
CE
or
OE
) a nd t he li mitin g
parameter is either tCO for
CE
or tOE for
OE
rather than address access.
WRITE MODE
The DS1350 devices e xecu te a wr ite c ycle wh enever t he
WE
and
CE
signals are in the act ive (low) state
after address inputs are stable. The later-occurring falling edge of
CE
or
WE
will determine the start of
the write c ycle. The wr it e cycle is terminated by the earlier rising edge of
CE
or
WE
. All address inputs
must be k ept va lid t hro ug hout t he wr it e c ycle.
WE
must r et urn t o t he hig h st at e fo r a min i mum reco ve r y
time (tWR) before another cycle can be initiated. The
OE
control signal should be kept inactive (high)
during write cycles to avoid bus contention. However, if the output drivers are enabled (
CE
and
OE
active ) then
WE
will disable the outp uts in tODW from its falling edge.
DATA RETENTION MODE
The DS1350AB pro vides full functional capability for VCC great er than 4.75V and write protects by 4. 5V.
The DS1350Y provides full funct ional capability for VCC greater than 4.5V and write prot ect s by 4.25V.
Data is maintained in the absence of VCC without any additional support circuitry. The NV SRAMs
constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically write protect
themse lves, all input s beco me “don’t care,” and all out put s beco me high-impeda nce. As VCC falls below
approximately 2.7V, the power switching circuit connects the lithium energy source to RAM to retain
data. During po wer-u p, w he n V CC r ise s above ap pr o ximate ly 2.7V , t he power switching circuit con nect s
exte r na l VCC to the RAM a nd d isco nnects t he lit hiu m e nerg y so urce. Nor mal RAM oper at io n ca n resum e
after VCC exceeds 4.75V for the DS1350AB and 4.5V for the DS1350Y.
SYSTEM POWER MONITORING
DS1350 devices have the ability to monitor the external VCC power supply. When an out-of-tolerance
power supply condit io n is detected, the NV SRAMs war n a pro cessor-based system of impending po wer
failure by asserting
RST
. On power-up,
RST
is held active for 200ms nominal to prevent system
oper ation dur ing power-on transients a nd to a llow tREC to elapse.
RST
has an open drain o utput driver .
BATTERY MONITORING
The DS1350 devices automatically perform periodic battery voltage monitoring on a 24-hour time
interval. Such monitoring begins within tREC after VCC rises above VTP and is suspended when power
failure occurs.
After each 24-hour period has elapsed, the battery is connected to an internal 1MΩ test resistor for one
second. During this one second, if battery voltage falls below the battery voltage trip point (2.6V), the
battery warning output
BW
is asserted. Once asserted,
BW
remains act ive unt il the module is replaced.
The bat tery is still ret ested after each VCC power-up , howe ver, even if
BW
is active. If the b attery voltag e
is found to be higher than 2.6V during such testing,
BW
is de-asserted and regular 24-hour testing
resumes.
BW
has an open drain output driver.
DS1350Y/AB
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PACKAGES
The 34-pin PowerCap modu le integrat es SRAM memor y and nonvo lat ile control along with contacts for
connection to the lithium battery in the DS9034PC PowerCap. The PowerCap module package design
allows a DS1350 PCM device to be surface mounted without subjecting its lithium backup battery to
destructive high-temperature reflow soldering. After a DS1350 PCM is reflow soldered, a DS9034PC is
snapped o n top o f the PCM to form a complete No nvo lat ile SRAM modu le. The DS9034PC is keyed to
prevent improper attachment. DS1350 PowerCap modules and DS9034PC PowerCaps are ordered
separately and s hipped in separate cont ainers. See the DS90 34P C dat a sheet for furt her information.
DS1350Y/AB
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ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin Relative to Ground -0.3V to +6. 0V
Operating Te mperat ur e Range
Commercial: 0°C to +70°C
Industrial: -40°C to +85°C
Stor ag e T emperat ur e Range -55° C to +125°C
Lead Temperature ( soldering, 10s) +260°C
Soldering Temper ature (reflow) +260°C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this
specifi c ation is not i m pli ed. Exposure t o absolute max imum rating condi ti ons for extended periods of time m ay affe ct re li ability.
RECOMMENDED DC OPERATING CONDITIONS (TA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
DS1350AB Power S upply Voltage VCC 4.75 5.0 5.25 V
DS1350Y Power Supply Voltage VCC 4.5 5.0 5.5 V
Logic 1 VIH 2.2 VCC V
Logic 0 VIL 0.0 0.8 V
DC ELECTRICAL C HAR AC TE R IS TIC S (VCC = 5V ± 5% for DS1350AB)
(TA: See Note 10) (VCC = 5V ± 10% for D S1350Y)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage Cu r r ent IIL -1.0 +1.0 µA
I/O Leakage Cu r r ent
CE
≥ VIH ≤ VCC IIO -1.0 +1.0 µA
Output Current @ 2.4V IOH -1.0 mA 14
Output Current @ 0.4V IOL 2.0 mA 14
St andby Current
CE
=2.2V ICCS1 200 600 µA
St andby Current
CE
=VCC-0.5V ICCS2 50 150 µA
Operating Current ICCO1 85 mA
Write Protection Voltage ( DS1350AB) VTP 4.50 4.62 4.75 V
Wr it e Protection Volt age (DS1350Y) VTP 4.25 4.37 4.5 V
CAPACITANCE (TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance CIN 5 10 pF
I nput/O utput C a pacit a nce CI/O 5 10 pF
DS1350Y/AB
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AC ELECTRICAL CHARACTERISTICS (VCC = 5V ± 5% for DS1350AB)
(TA: See Note 10) (VCC = 5V ± 10% for D S1350Y)
PARAMETER SYMBOL DS1350AB-70
DS1350Y-70 UNITS NOTES
MIN MAX
Re a d Cycle Time tRC 70 ns
Access Time tACC 70 ns
OE
to O utp ut Valid tOE 35 ns
CE
to O utp ut Valid tCO 70 ns
OE
or
CE
to O utp ut Active tCOE 5 ns 5
Outpu t High Z f rom Desel ec tion tOD 25 ns 5
Output Ho ld from Address
Change tOH 5 ns
Write Cycle Time tWC 70 ns
Writ e P ulse Width tWP 55 ns 3
A ddress Setup Time tAW 0 ns
Writ e Recover y Ti me tWR1
tWR2
5
12 ns 12
13
Outpu t High Z f rom
WE
tODW 25 ns 5
Output Active from
WE
tOEW 5 ns 5
Dat a S et up Time tDS 30 ns 4
Da ta Hold Time tDH1
tDH2
0
7 ns 12
13
READ CYCLE
SEE NOTE 1
DS1350Y/AB
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WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8, and 12
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8, and 13
DS1350Y/AB
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POWER-DOWN/POWER-UP CONDITION
BATTERY WARNING DETECTION
SEE NOTE 14
DS1350Y/AB
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POWER-DOWN/POWER-UP TIMING (TA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
VCC Fail Detect to
CE
and
WE
Inactive tPD 1.5 µs 11
VCC slew from VTP to 0V tF 150 µs
VCC Fail Detect to
RST
Active tRPD 15 µs 14
VCC slew from 0V to VTP tR 150 µs
VCC Valid to
CE
and
WE
Inactive tPU 2 ms
VCC Valid to End of Write Protection tREC 125 ms
VCC Valid to
RST
Inactive tRPU 150 200 350 ms 14
VCC Valid to
BW
Valid tBPU 1 s 14
BATTERY WARNING TIMING (TA: See N ot e 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Batt er y Test Cycle tBTC 24 hr
Batt er y Test P ulse Width tBTPW 1 s
Battery Test to
BW
Active tBW 1 s
(TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Expect ed Data Ret ent io n T ime tDR 10 years 9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mo de.
NOTES:
1.
WE
is high for a Read Cycle.
2.
OE
= VIH o r V IL. If
OE
= VIH d uri ng w rite cycle, the outpu t buffers rema in in a hi gh-impeda nce state.
3. tWP is specified as the logical AND of
CE
and
WE
. tWP is measured from the latter of
CE
or
WE
go ing lo w t o t he ear lier o f
CE
or
WE
go ing h ig h.
4. tDS are measured from the ear lier o f
CE
or
WE
going high.
5. T hese para met er s ar e samp led w ith a 5pF load and are not 100% t ested.
6. I f the
CE
low transitio n occurs simu lta neously wit h o r latter t han the
WE
low t ransit ion, the o utput
buff e rs rema in in a high-impedance stat e during this per iod.
7. If the
CE
high transition occurs prior to or simultaneously with the
WE
high transition, the output
bu ff ers rema in in high-impedance state during this period.
8. If
WE
is low or the
WE
lo w t ra ns ition o cc ur s p r io r t o o r s i mu lta ne o u s ly wit h t h e
CE
lo w t ra ns ition ,
the out put bu f f e rs remain i n a high-impeda nce st at e during this period.
DS1350Y/AB
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9. Each DS1350 has a built -in switc h that d isco nnect s the lit hiu m sou rce unt il t he user fir st app lies VCC.
The expect ed tDR is defined as accu mulat ive time in the absence o f VCC st arting fro m t he time power
is first applied by the user. This parameter is assured by component selection, process control, and
design. It is not measured directly during production testing.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commer c ial pr o d u ct s , t h is range is 0°C t o 70°C. For industria l product s (IND), this range is -40°C t o
+85°C.
11. In a power-dow n c onditio n the voltage on a ny pin may not e xce ed the voltage on VCC.
12. tWR1 and tDH1 are measur ed fro m
WE
go ing h ig h.
13. tWR2 and tDH2 are measur ed from
CE
go ing h ig h.
14.
RST
and
BW
are open drain outputs and cannot source current. External pull-up resistors should be
connected to these pins for proper operation. Both pins will sink 10mA.
15. DS1350 modules are recognized by Underwr iter s Laboratories (UL) under file E99151.
DC TEST CONDITIONS AC TEST CONDITIONS
Output s Open Output Load: 100pF + 1TTL Gate
Cycle = 200ns for operating current Input Pulse Levels: 0 – 3.0V
All voltages are refer enced to grou nd Timing Measur ement Referen ce Le vels
Input: 1.5V
Output : 1.5V
Input pulse Rise and Fall Times: 5ns
ORDERING INFORMATION
PART TEMP RANGE
SUPPLY
TOLERANCE
PIN-PACKAGE
DS1350ABP-70+
0°C to +70°C
5V ± 5%
34 PCAP*
DS1350ABP-70IND+
-40°C to +85°C
5V ± 5%
34 PCAP*
DS1350YP-70+
0°C to +70°C
5V
±
10%
34 PCAP*
DS1350YP-70IND+
-40°C to +85°C
5V ± 10%
34 PCAP*
+Denotes a lead(Pb)-free/RoHS-compli ant package.
* DS9034PC+ or DS9034PCI+ (P owerCap) r equire d. Must be order e d s eparately .
PACKAGE INFORMATION
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a
d ifferent suffix c haracter , but the drawing pertains to the package r egar dless of Ro HS statu s.
PACKAGE TYPE PACK AG E CODE OU TLINE NO .
LAND
PATTERN NO.
34 PCAP PC2+5 21-0246 —
DS1350Y/AB
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REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
10/10
Updated the solde rin g a nd st or ag e informatio n in the Absolute
Maximum Ratings sectio n, r emo ved the u nus e d AC timin g specs in
the AC Electric al Chara cte r is tics table, updated the Ordering
Information tab le, r eplaced the package out line draw ing wit h t he
Package Inf ormation table
1, 4, 5, 9