DEVICE SPECIFICATION AMCG& 20-OUTPUT CLOCK DRIVERS $C3500/06/07/08 FEATURES 20 clock outputs: ~ Grouped into banks of 5 or 10 outputs ~ Output frequency of each bank is user selectable Leading edge skew for all outputs <0.5 ns Proprietary output drivers with: ~ Complementary 24 mA peak outputs, source and sink ~ 50-750 source series termination ~ Dynamic drive adjustment to match load conditions Edge rates less than 1.5 ns * Minimizes the ground-bounce, overshoot, and ringing problems often encountered when using CMOS and Bipolar drivers * 52-pin PQFP package APPLICATIONS Compatible with Intels Pentium processor Compatible with PowerPC processors PCI Bus clock distribution Workstation and server systems with high clock fanout * Datacom and Telecom networks $C3500 Logic Diagram GENERAL DESCRIPTION The SC3500, SC3506, SC3507, and SC3508 are precision clock fan out drivers. They accept a refer- ence dock input from either a single-ended TTL source or a differential PECL frequency source. This reference clock input is distributed through dividers and buffers to the output clock drivers. The 20 outputs are divided into groups of 5 or 10 outputs. The output frequency of each group can be F, F/2, F/4, or F/8, and is user selectable. Each of the clock driver products offers different combina- tions of divide ratios. Applied Micro Circuits Corporation (AMCC) uses proprietary complementary (Source and sink) 24 mA peak output drivers. In addition to their drive capability, these circuits provide source (series) termination at the TTL outputs that minimize over/undershoot without requiring on-board termination networks. They are designed for a maximum output slew rate of =1.5V/ns to minimize simultaneous output switching noise and distortion. +5V __ 20K RESET CLOCK SEL Thy Thy Ff2 Fb SEL Fe SEL BINARY COUNTER F/4 F/R F/2 Fa M/S Fb Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333 Page 3-5MMC. $C3506 Logic Diagram +5V ox & . a Reser aL RS S-R rao4 clock se. [_}_, A> <<) LPM L- uU Fa5-9 R2o%, DELAY $C3507 Logic Diagram +5V = 20K Ri ESE Fa0-4 CLOCK SEL 5 Mh BINARY | F/2 Fas~9 COUNTER MIS mM Fi2 F/4 Fb Fb" SEL Fe Fo SEL $C3508 Logic Diagram Fa Fb Fe Fd Applied Micro Circuits Corporation Page 3-6 6195 Lusk Bivd., San Diego, CA 92121 * (619) 450-933320-OUTPUT CLOCK DRIVERS $C3500/06/07/08 Absolute Maximum Ratings Capacitance (package and die total) Storage Temperature ........... ee -55 to +150C Input PINS 0.0... ee eee ceeeeeneceeseceeeeetetetteenaes 5.0 pF Vcc Potential to Ground -0.5V to +7.0V TTL Output PINS 2.0.0... ccc ceeneteeeesceeeecenes 5.0 pF Input Voltage ....... ee ....0.5V to +Vcc Static Discharge Voltage .......0... ces >1750V Maximum Junction Temperature +140C Latch-up Current ..0.......0.. ee >200 mA Operating Ambient Temperature 0 to +70C Electrical Characteristics Voc = +5.0V + 5%, Tg = 0C to +70C (reference AC Test/Evaluation Circuit) Symbol Parameter Conditions Min Max | Unit VIH input HIGH Voltage (PECL) Differential SourcePECL Vit +0.4 | +Vcc Vv input HIGH Voltage (TTL) All TTL Inputs 2.0 Voc Vv Vit Input LOW Voltage (PECL) Differential Source-PECL Voc -2.0| Vin -0.4] V Input LOW Voltage (TTL) All TTL Inputs -0.5 0.8 Vv hin input HIGH Current (PECL) Vin = Vcc (max) 200 uA CLKSEL Vin = Voc (max) 350 uA Reset Vin = 2.4V -200 uA TTL, CSEL, BSEL Vin = 2.4V 16 uA liv Input LOW Current (PECL) Vin = Vcc -2.0V 15 uA CLKSEL Vin = 0.4V 50 uA Reset Vin = 0.5V -325 uA TTL, CSEL, BSEL Vin = 0.4V 15 uA Von Output HIGH Voltage Fout = 8OMHz max C, = 10pF 2.4 Vv VoL Output LOW Voltage Fout = BOMHz max C, = 10pF 0.6 Vv lors! Output HIGH Short Ckt Current Output High, Vout = OV Typ -55 mA lots? Output LOW Short Ckt Current Output Low, Vout = Vcc Typ 55 mA PWR Static Core Power Dissipation $C3500, 70C, Typ Pwr=370 mW 600 mw $C3506, 70C, Typ Pwr=350 mW 550 mw $C3507, 70C, Typ Pwr=370 mW 600 mw SC3508, 70C, Typ Pwr=340 mw 550 mw 1. Maximum test duration, one second. 2. The $C3500/06/07/08 features source series termination of approximately 40 Ohms to assist in matching 50~-75 Ohm P.C. board environments. PECL Differential Input Voltage Range DC Characteristics The outputs have been designed specifically for clock distribution. In the development of this product, Voc AMCC has made several trade-offs between the Vv Vv historic high drive, totem pole outputs and AMCCs 1H . C IH dynamically adjusting source series terminated outputs. INPUT DIFFERENTIAL Vip 2 400mv As a result of this, the outputs will dynamically Vit Vit source and sink a symmetrical 24 mA of current. Ina Voc -2.0V OC state, it exhibits the following specifications: Conditions Min Max Vou lon = -8MA 2.4V VoL lop = 4mA 0.6V Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333 Page 3-7AMC $C3500/06/07/08 20-OUTPUT CLOCK DRIVERS AC SpecificationsUsing AC Test/Evaluation Circuit Vec = +5.0V + 5%, Ta = 0C to +70C, Ciaap = 10pF Parameter $C3500 $C3506 $C3507 $C3508 Units Maximum Skew Across All Outputs Options: Standard 1.0 10 1.0 1.0 +1 05 05 05 0.5 ns -2 05 0.5 Maximum Skew Chip to Chip Options: Standard _ ~1 _ -2 1.0 1.0 Maximum Skew within an Output Group 0.25 0.25 0.25 0.25 ns Maximum Output Duty Cycle Asymmetry $1.0 +1.0 +1.0 ns Maximum TTL Input Frequency 80 80 80 80 MHz Maximum PECL Differential Input 160 80 160 80 MHz Frequency Maximum Rising/Falling Edge Rate 15 1.5 15 15 ns Notes: 1. Skew is referenced to the rising edges of all outputs. 2. Output Duty Cycle Asymmetry is defined as the Duty Cycle deviation from 50%, measured at 1.5V. Duty Cycle will be effected by voltage, temperature, and toad (including the length of the PC trace). Only applies to divided outputs. 3. Typical skew derating factor for different loads is 50 ps/pF al 1.5V threshold. For example, a SpF load difference equals a 250 ps skew difference. 4. Edge rates are measured from 0.8V to 2.0V. Load consists of a 6" board Irace (70 Ohm) with a 10 pf capacitive !oad. See AC Test/Evaluation Circuit. Synchronous outputs may be paralleled for higher toads. 5. Parameters guaranteed by design and characterization. Threshold Crossing Characteristics 50% + 10% ECL Voh-0.3V Vol+0.3V elo sos} Minimum kk 50% +1 ns = _-_ CLOCK OUTPUT +2.0V +2.0V +1.5V +1.5V +0.8V +0.8V | - T rise 1.5ns 1.5ns T fall NOTE: Trise and Tfall are real load dependent. The values indicated are for 6" of board trace (70 Ohm) with a 10 pF capacitive load. See the Clock Driver Application Note. Applied Micro Circuits Corporation Page 3-8 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333AMCG 20-OUTPUT CLOCK DRIVERS $C3500/06/07/08 DESCRIPTION OF OPERATION (Refer to Logic Diagrams) AMCC has developed a single-chip clock shape and 20-output fan-out device using AMCCs advanced BiCMOS process. This design has been optimized for clock symmetry and absolute minimum skew across all twenty outputs. For highest performance this approach requires a clock source input from a crystal-controlled oscillator (XCO) located adjacent to this clock driver. This oscillator, operating between +5V and ground, can provide either differential ECL inputs (referenced to +5V, PECL) or TTL (CMOS) input levels to AMCCs Clock Driver. The input selection is accomplished via the Clock Sel input where a HIGH" level activates the differential ECL input and a LOW activates the TTL input. This input clock will be fanned out to a divide-down counter and master-slave flip-flops for synchronization (refer to the Logic Diagrams). The RESET input is provided to hold off or clear the outputs as may be required by the users system. This pin may be logically driven from a TTL output. Optionally, if a capacitor (4.7uF = ~100 ms) is con- nected between this pin and ground, the device will respond with a power up reseta delay in the clock outputs becoming active. At the onset of RESET (low) the outputs will go low following five falling edge clock inputs (four clock inputs for the SC3506 and SC3508). At the expiration of RESET (high) out- puts will resume, after five falling edge clock inputs (four clock inputs for the SC3506 and SC3508), from a high (leading edge) count origin (see Figure 5, Reset To Output Timing in the Clock Driver Applica- tion Note). $C3500/06/07/08 Product Selection Guide The output drivers are rise and fall slew rate con- trolled to ~1.5V/ns to minimize noise and distortion resulting from simultaneous switching of the 20 outputs. These outputs also feature series termination (~40 Ohms) to significantly reduce the overshoot and undershoot of non-terminated transmission lines. This will satisfy printed circuit line impedances of 50-75 Ohms terminated into 15 pF (two IC input package receiver pins). When applications require large joad capacitance (>25pF with 50 Ohm P.C. board impedance) and/or large peak voltage amplitudes (>3.5 Volts), two adjacent drivers may be paralleled, thereby halving the series resistance and doubling the peak current. Power and ground are interdigitated with the outputs. Of the 52 package pins, 22 are used for jow impedance on-chip power distribution. Due to the simultaneous switching of outputs, low impedance +V,, and ground planes within the P.C. board are recommended, as well as substantial decoupling capacitance (see the Clock Driver Application Note for recommendations). The IC package and die layouts are tightly coupled to assure precise matching of all of the outputs. Collec- tively, the resistance, inductance, and capacitance of the package and wire bonding is managed to insure that the clock driver will exhibit skews less than the specified maximum. A plastic 52-lead quad flat pack with .039" lead pitch is employed with an outer lead square footprint of approximately 0.7" per side. Output Frequency with Respect to Input Frequency Number of Number of Number of Total Outputs Outputs Outputs PIN Outputs =1 +2 +2or4 Special Features Package $C3500 20 10 5+1or2 5 _ 52 PQFP $C3506 20 10 10 N/A _ 52 PQFP SC3507 20 10 NA 10 52 PQFP SC3508 20 20 NYA N/A 52 PQFP Applied Micro Circuits Corporation 6195 Lusk Blvd, San Diego, CA 92121 (619) 450-9333 Page 3-9AMG $C3500 Output Clock Frequency Selection B SEL C SEL XCO FREQ Fa Fb Fc LO LO F F/2 F/4 F/8 HI LO F F/2 F/2 F/8 LO HI F F/2 F/4 F/4 HI a F F/2 F/2 F/4 Note: XCO is the input frequency for either the PECL Inputs or the TTL Input. Non-crystal oscillator sources may be used ai the user's discretion. See the Clock Driver Application Note. $C3507 Output Clock Frequency Selection B SEL C SEL XCO FREQ Fai, Fa2 Fb Fe LO LO F F/2 F/4 F/4 Hi LO F Fie Ff2 F/4 LO HI F F/2 F/4 F/2 HI HI F F/2 F/2 F/2 Note: XCO is the input frequency for either the PECL inputs or the TTL input. Non-crystal oscillator sources may be used at the user's discretion. See the Clock Driver Application Note $C3506 and SC3508 have no frequency selection capabilities. AC Test/Evaluation Circuit Vee = +5.0V 10 10 10 10 10 10 TW Sload 5 2.0 2.0 20 2.0 2.0 2.0 10 - |}___ ~6 INCHES of 70 OHM P.C.B. > NOTES: All inductance is in nH. Capacitance is in pF. At frequencies above 50 MHz, a single point load destination is recommended. Applied Micro Circuits Corporation Page 3-10 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333AMCG 20-OUTPUT CLOCK DRIVERS Tox TNT Ord (07 -) Power Management The overall goa! of managing the power dissipated by the clock driver is to limit its junction (die) tempera- ture to 140C. A major component of the power dissi- pated internally by the clock driver is determined by the load that each output drives and the frequency that each output is running. The Output Power Dis- sipation table summarizes these dependencies (see the AC Test/Evaluation Circuit, for complete load definition). The output power must be added to the core power (600 mW) of the clock driver to determine the total power being dissipated by the clock driver. This total power is then multiplied by the clock driver's thermal resistance, with the result being added to the ambient temperature to determine the junction temperature of the SC350X. For greatest reliability, this junction temperature should not exceed 140C. The thermal resistance for the clock driver is detailed in the 52- pin PQFP Thermal Dissipation vs. Airflow graph in the Package appendix at the end of this section. Output Power Dissipation For example: An application utilizes an clock driver with 8 Fa outputs driving 10 pF loads at 66 MHz, 3 Fb outputs driving 5 pF loads at 33 MHz and 2 Fc out- puts driving 15 pF loads at 33 MHz. Total chip power is calculated as follows: Core Power (SC3500) = 600 mW 8 Fa, 10 pF, 66 MHz = (8 x 47 mW) = 376 mW 2 Fa, no load, 66 MHz = (2 x 16 mW) = 32 mw 3 Fb, 5 pF, 33 MHz = (3 x 19 mW) = 57 mw 2 Fb, no load, 33 MHz = (2 x 12 mW) = 24 mW 2 Fe, 15 pF, 33 MHz = (2 x 24 mW) = 48 mW 3 Fc, no load, 33 MHz = (3 x 12 mW) = 36 mW Total Power = 1173mW The design specifies a 70C still air ambient. Refer- ring to the 52-pin PQFP Thermal Dissipation vs. Air- flow graph in the Package appendix, the ja for still air is 46.2C/watt. The clock driver's junction temperature would then be: 70C + (1.173 watts x 46.2C/watt) = 124C Note this is below the 140C maximum junction temperature. FREQUENCY | CLoap=5pF | Ctoap=10pF | CLoap=15pF | CLoap=25pF | NO LOAD 80 MHz 42 mW 51 mw 61 mW 88 mW 18 mW 66 MHz 38 mW 47 mW 55 mW 75 mW 16 mW 50 MHz 28 mW 33 mW 39 mW 60 mW 14 mW 40 MHz 25 mW 30 mW 36 mW 52 mW 13 mw 33 MHz 19 mW 22 mW 24 mw 46 mW 12 mW 25 MHz 16 mW 18 mW 20 mW 32 mW 11 mW 20 MHz 14 mW 16 mw 18 mW 24 mW 10 mW Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333 Page 3-11AMCG $C3500/06/07/08 20-OUTPUT CLOCK DRIVERS $C3500 Relative Output Timing VAIN INIASLN FI4 Vo \ Of $C3506 Relative Output Timing INPUT Fol, Fp2 Fal, Fa2 $C3507 Relative Output Timing INPUT n VS VS VSN Fal, Fa2 $C3508 Relative Output Timing INPUT Fa. Fo, Fe, Fd Page 3-12 Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333AMCG $C3500/06/07/08 $C3500 Pinout $C3506 Pinout ry vec CT} GND 42717 Fao 52(T) CLK SEL IJ voc [1] FAS [J GND 44(T7) FAa 46(I-] FA? RESET C11 [IJ GND w 407 TTL Osc 1 PEct oscP [1] PECL OSCN 1 Fc4 maniacs im wliex) C1] GNO 1 Fc2 J vec PTI Fc [1 GND [1] Fco [1 NC mene 52] CLK SEL 46[-.] FA? AESET C1 9 [TT] PECL OScP GnD CY [1] PECL OSCN FB4 1 Fes GND CY] mr vec Fea 1 FBa vec CI 1] GNO FB2 [TJ FB7 cno CJ iT vec Fe: CI ja 1] FB6 vec CI 1 GND Feo O11 1] FBS vec CY PT NC vec C13 sale $C3507 Pinout $C3508 Pinout a oO iB 5 a 3 ES2e 2825 E825E nnAq0q Q 0 NOAA AAA a 8 8 g RESET C41 x GND FB4 CI GND CL FB3 voc Fee CIJ7 GND CI Fei C49 vec Fs0 [70411 yvcc 2 a oS T) PECL OscP CT) PECL OSCN PT Fc4 vcc wale T] GND 1 Fc2 1 vec PFC 1] GND fT Fco PT NC enh [1 PECL OSCP 1 PECL OSCN PT Fc4 vec TFC 1] GNO iT Fc2 Tq vcc [TA Fc1 [1 GND [1 Fco 0 NC male Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333 Page 3-13AMCG $C3500/06/07/08 20-OUTPUT CLOCK DRIVERS Ordering Information AMCC clock driver products are available in several output skew and shipping configurations. The order number is formed by a combination of: SC350X Q * Device Number Package Type * Skew Option (if applicable) * Optional Shipping Configuration Example: SC350XQ-1/D 52-pin PQFP package, 500 ps output-output skew, shipped dry packed in the standard matrix tray. Optional Shipping Configuration Blank = 84-unit matrix tray {D = dry pack {TD = tape, ree! and dry pack Skew Option Blank = 1.0 ns output-output skew 1 = 500 ps output-output skew ~2=1.0ns chip-to-chip skew Package Option Q = 52-pin Plastic Quad Flat Pack (PQFP) Device Number Part Number Standard -1 -2 SC3500 v N/A $C3506 v v SC3507 a N/A SC3508 Y v Page 3-14 Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 * (619) 450-9333