W9425G6DH-75 - Winbond Electronics Corporation America

W9425G6DH

4M × 4 BANKS × 16 BITS DDR SDRAM

Publication Release Date:Feb. 12 , 2008

- 1 - Revision A8

Table of Contents-

1. GENERAL DESCRIPTION............................................................................................................. 4

2. FEATURES .................................................................................................................................... 4

3. KEY PARAMETERS ...................................................................................................................... 5

4. PIN CONFIGURATION.................................................................................................................. 6

5. PIN DESCRIPTION........................................................................................................................ 7

6. BLOCK DIAGRAM ......................................................................................................................... 8

7. FUNCTIONAL DESCRIPTION.......................................................................................................9

7.1 Power Up Sequence............................................................................................................ 9

7.2 Command Function............................................................................................................. 9

7.2.1 Bank Activate Command........................................................................................................9

7.2.2 Bank Precharge Command....................................................................................................9

7.2.3 Precharge All Command ........................................................................................................9

7.2.4 Write Command .....................................................................................................................9

7.2.5 Write with Auto-precharge Command...................................................................................10

7.2.6 Read Command...................................................................................................................10

7.2.7 Read with Auto-precharge Command ..................................................................................10

7.2.8 Mode Register Set Command ..............................................................................................10

7.2.9 Extended Mode Register Set Command..............................................................................10

7.2.10 No-Operation Command ......................................................................................................10

7.2.11 Burst Read Stop Command..................................................................................................11

7.2.12 Device Deselect Command..................................................................................................11

7.2.13 Auto Refresh Command.......................................................................................................11

7.2.14 Self Refresh Entry Command...............................................................................................11

7.2.15 Self Refresh Exit Command.................................................................................................11

7.2.16 Data Write Enable /Disable Command.................................................................................12

7.3 Read Operation................................................................................................................. 12

7.4 Write Operation .................................................................................................................12

7.5 Precharge.......................................................................................................................... 13

7.6 Burst Termination..............................................................................................................13

7.7 Refresh Operation............................................................................................................. 13

7.8 Power Down Mode............................................................................................................13

7.9 Input Clock Frequency Change during Precharge Power Down Mode ............................ 14

7.10 Mode Register Operation ..................................................................................................14

7.10.1 Burst Length field (A2 to A0) ................................................................................................14

W9425G6DH

Publication Release Date:Feb. 12 , 2008

- 2 - Revision A8

7.10.2 Addressing Mode Select (A3)...............................................................................................14

7.10.3 CAS Latency field (A6 to A4)................................................................................................16

7.10.4 DLL Reset bit (A8)................................................................................................................16

7.10.5 Mode Register /Extended Mode register change bits (BS0, BS1)........................................16

7.10.6 Extended Mode Register field ..............................................................................................16

7.10.7 Reserved field ......................................................................................................................16

8. OPERATION MODE .................................................................................................................... 17

8.1 Simplified Truth Table........................................................................................................ 17

8.2 Function Truth Table ......................................................................................................... 18

8.3 Function Truth Table for CKE............................................................................................ 21

8.4 Simplified Stated Diagram................................................................................................. 22

9. ELECTRICAL CHARACTERISTICS............................................................................................ 23

9.1 Absolute Maximum Ratings............................................................................................... 23

9.2 Recommended DC Operating Conditions......................................................................... 23

9.3 Capacitance....................................................................................................................... 24

9.4 Leakage and Output Buffer Characteristics ...................................................................... 24

9.5 DC Characteristics............................................................................................................. 25

9.6 AC Characteristics and Operating Condition..................................................................... 26

9.7 AC Test Conditions............................................................................................................28

10. SYSTEM CHARACTERISTICS FOR DDR SDRAM.................................................................... 30

10.1 Table 1: Input Slew Rate for DQ, DQS, and DM...............................................................30

10.2 Table 2: Input Setup & Hold Time Derating for Slew Rate................................................ 30

10.3 Table 3: Input/Output Setup & Hold Time Derating for Slew Rate.................................... 30

10.4 Table 4: Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate .................... 30

10.5 Table 5: Output Slew Rate Characteristics (X16 Devices only)........................................30

10.6 Table 6: Output Slew Rate Matching Ratio Characteristics.............................................. 31

10.7 Table 7: AC Overshoot/Undershoot Specification for Address and Control Pins ............. 31

10.8 Table 8: Overshoot/Undershoot Specification for Data, Strobe, and Mask Pins .............. 32

10.9 System Notes:...................................................................................................................33

11. TIMING WAVEFORMS................................................................................................................35

11.1 Command Input Timing.....................................................................................................35

11.2 Timing of the CLK Signals................................................................................................. 35

11.3 Read Timing (Burst Length = 4)........................................................................................ 36

11.4 Write Timing (Burst Length = 4) ........................................................................................ 37

11.5 DM, DATA MASK (W9425G6DH)..................................................................................... 38

11.6 Mode Register Set (MRS) Timing .....................................................................................39

11.7 Extend Mode Register Set (EMRS) Timing.......................................................................40

W9425G6DH

Publication Release Date:Feb. 12 , 2008

- 3 - Revision A8

11.8 Auto-precharge Timing (Read Cy cle, CL = 2)...................................................................41

11.9 Auto-precharge Timing (Read cycle, CL = 2), continued.................................................. 42

11.10 Auto-precharge Timing (Write Cycle)................................................................................ 43

11.11 Read Interrupted by Read (CL = 2, BL = 2, 4, 8).............................................................. 44

11.12 Burst Read Stop (BL = 8)..................................................................................................44

11.13 Read Interrupted by Write & BST (BL = 8)........................................................................45

11.14 Read Interrupted by Precharge (BL = 8)...........................................................................45

11.15 Write Interrupted by Write (BL = 2, 4, 8) ........................................................................... 46

11.16 Write Interrupted by Read (CL = 2, BL = 8).......................................................................46

11.17 Write Interrupted by Read (CL = 3, BL = 4).......................................................................47

11.18 Write Interrupted by Precharge (BL = 8) ........................................................................... 47

11.19 2 Bank Interleave Read Operation (CL = 2, BL = 2)......................................................... 48

11.20 2 Bank Interleave Read Operation (CL = 2, BL = 4)......................................................... 48

11.21 4 Bank Interleave Read Operation (CL = 2, BL = 2)......................................................... 49

11.22 4 Bank Interleave Read Operation (CL = 2, BL = 4)......................................................... 49

11.23 Auto Refresh Cycle............................................................................................................50

11.24 Precharge/Activate Power Down Mode Entry and Exit Timing......................................... 50

11.25 Input Clock Frequency Change during Precharge Power Down Mode Timing................. 50

11.26 Self Refresh Entry and Exit Timing ...................................................................................51

12. PACKAGE SPECIFICATION .......................................................................................................52

12.1 TSOP 66 lI – 400 mil .........................................................................................................52

13. REVISION HISTORY................................................................................................................... 53

W9425G6DH

Publication Release Date:Feb. 12 , 2008

- 4 - Revision A8

1. GENERAL DESCRIPTION

W9425G6DH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR

SDRAM), organized as 4,194,304 words × 4 banks × 16 bits. Using pipelined architecture and 0.11 µm

process technology, W9425G6DH delivers a data bandwidth of up to 500M words per second (-4). To

fully comply with the personal computer industrial standard, W9425G6DH is sorted into the following

speed grades: -4/-5/-6/-6F/-6I/-75 and 75I. The -4 is compliant to the DDR500/CL3 specification. The -

5 is compliant to the DDR400/CL3 specification. The -6/-6F is compliant to the DDR333/CL2.5

specification (the -6I grade which is guaranteed to support -40°C ~ 85°C). The -75 is compliant to the

DDR266/CL2 specification (the 75I grade which is guaranteed to support -40°C ~ 85°C).

All Input reference to the positive edge of CLK (except for DQ, DM and CKE). The timing reference

point for the differential clock is when the CLK and CLK signals cross during a transition. Write and

Read data are synschronized with the both edges of DQS (Data Strobe).

By having a programmable Mode Register, the system can change burst length, latency cycle,

interleave or sequential burst to maximize its performance. W9425G6DH is ideal for main memory in

high performance applications.

2. FEATURES

• 2.5V ±0.2V Power Supply for DDR266/DDR333

• 2.6V ±0.1V Power Supply for DDR400/DDR500

• Up to 250 MHz Clock F requency

• Double Data Rate architecture; two data transfers per clock cycle

• Differential clock inputs (CLK and CLK )

• DQS is edge-aligned with data for Read; center-aligned with data for Write

• CAS Latency: 2, 2.5 and 3

• Burst Length: 2, 4 and 8

• Auto Refresh and Self Refresh

• Precharged Power Down and Active Power Down

• Write Data Mask

• Write Latency = 1

• 7.8µS refresh interval (8K / 64 mS refresh)

• Maximum burst refresh cycle: 8

• Interface: SSTL_2

• Packaged in TSOP II 66-pin, 400 mil, 0.65 mm pin pitch, using Pb free with RoHS compliant

W9425G6DH

Publication Release Date:Feb. 12 , 2008

- 5 - Revision A8

3. KEY PARAMETERS

SYMBOL DESCRIPTION MIN./MAX. -4 -5 -6/-6F/-6I -75/75I

Min. - 7.5 nS 7.5 nS 7.5 nS

CL = 2 Max. - 10 nS 12 nS 12 nS

Min. - 6 nS 6 nS 7.5 nS

CL = 2.5 Max. - 10 nS 12 nS 12 nS

Min. 4 nS 5 nS 6 nS 7.5 nS

tCK Clock Cycle Time

CL = 3 Max. 10 nS 10 nS 12 nS 12 nS

tRAS Active to Precharge Command

Period Min. 36 nS 40 nS 42 nS 45 nS

tRC Active to Ref/Active Command

Period Min. 52 nS 55 nS 60 nS 67.5 nS

IDD0 Operating Current:

One Bank Active-Precharge Max. 110 mA 110 mA 110 mA 110 mA

IDD1 Operating Current:

One Bank Active-Read-Precharge Max. 150 mA 150 mA 150 mA 150 mA

IDD4R Burst Operation Read Current Max. 190 mA 180 mA 170 mA 160 mA

IDD4W Burst Operation Write Current Max. 190 mA 180 mA 170 mA 160 mA

IDD5 Auto Refresh Current Max. 190 mA 190 mA 190 mA 190 mA

IDD6 Self Refresh Current Max. 5 mA 3 mA 3 mA 3 mA

W9425G6DH

Publication Release Date:Feb. 12 , 2008

- 6 - Revision A8

4. PIN CONFIGURATION

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

DQ8

UDQS

CLK

CKE

A11

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

BS0

BS1

A10/AP

RAS

CAS

LDM

LDQS

A12

CLK

UDM

REF

W9425G6DH

Publication Release Date:Feb. 12 , 2008

- 7 - Revision A8

5. PIN DESCRIPTION

PIN NUMBER PIN

NAME FUNCTION DESCRIPTION

28 − 32,

35 − 42 A0 − A12 Address

Multiplexed pins for row and column address.

Row address: A0 − A12.

Column address: A0 − A8. (A10 is used for Auto-prec harge)

26, 27 BS0, BS1 Bank Select Select bank to activate during row address latch time, or

bank to read/write during colu mn address latch time.

2, 4, 5, 7, 8, 10,

11, 13, 54, 56, 57,

59, 60, 62, 63, 65 DQ0 −

DQ15 Data Input/ Output The DQ0 – DQ15 input and o utput data are synchronized

with both edges of DQS.

16,51 LDQS,

UDQS Data Strobe DQS is Bi-directional signal. DQS is input signal during write

operation and output signal during read operation. It is Edge-

aligned with read data, Center-alig ned with write data.

24 CS Chip Select Disable or enable the command decoder. When command

decoder is disabled, new command is ignored and previous

operation continues.

23, 22, 21 RAS ,

CAS , WE Command Inputs Comman d in puts (along with CS ) define the command

being entered.

20, 47 LDM, UDM Write Mask When DM is asserted “high” in burst write, the input data is

masked. DM is synchronized with both edg es of DQS.

45, 46 CLK,

CLK Differential Clock

Inputs

All address and control input signals are sampled on the

crossing of the positive edge of CLK and negative edge of

CLK .

44 CKE Clock Enable

CKE controls the clock activation an d deactivation. When

CKE is low, Power Down mode, Suspend mode, or Self

Refresh mode is entered.

49 VREF Reference Voltage VREF is reference voltage for inputs.

1, 18, 33 VDD Power (+2.5V) Power for logic circuit inside DDR SDRAM.

34, 48, 66 VSS Ground Ground for logic circuit inside DDR SDRAM.

3, 9, 15, 55, 61 VDDQ Power (+2.5V) for

I/O Buffer Separated power from VDD, used for output buffer, to

improve noise.

6, 12, 52, 58, 64 VSSQ Ground for I/O

Buffer Separated ground from VSS, used for output buffer, to

improve noise.

14, 17, 19, 25,

43, 50, 53 NC No Connection

No connection (NC pin should be conne cted to GND or

floating)

W9425G6DH

Publication Release Date:Feb. 12 , 2008

- 8 - Revision A8

6. BLOCK DIAGRAM

CKE

A10

DLL

CLOCK

BUFFER

COMMAND

DECODER

ADDRESS

BUFFER

REFRESH

COUNTER

COLUMN

COUNTER

CONTROL

SIGNAL

GENERATOR

MODE

COLUMN DECO D ER

SENSE AMPLIFIER

CELL ARRAY

BANK #2

COLUMN DECO D ER

SENSE AMPLIFIER

CE LL ARR AY

BANK #0

COLUMN DECODER

SENSE AMP L I FIER

CELL ARRAY

BA N K # 3

DATA CONTRO L

CIRCUIT

BUFFER

COLUMN DECODER

SENSE AMP L I FIER

CELL ARRAY

BANK #1

NOTE: The cell array configuration is 8912 * 512 * 16

ROW DECODER ROW DECODER

ROW DECODERROW DECODER

A11

A12

BS1

BS0

RAS

CAS

CLK

DQ0

DQ15

PREFETCH REGISTER

LDM

UDM

UDQS

LDQS

W9425G6DH

Publication Release Date:Feb. 12 , 2008

- 9 - Revision A8

7. FUNCTIONAL DESCRIPTION

7.1 Power Up Sequence

(1) Apply power and attempt to CKE at a low state (

≤

0.2V), all other inputs may be undefined

1) Apply VDD before or at the same time as VDDQ.

2) Apply VDDQ before or at the same time as VTT and VREF.

(2) Start Clock and maintain stable condition for 200 µS (min.).

(3) After stable power and clock, apply NOP and take CKE high.

(4) Issue precharge command for all banks of the device.

(5) Issue EMRS (Extended Mode Regi ster Set) to enable DLL and establish Output Driver Type.

(6) Issue MRS (Mode Regist er Set) to reset DLL and set device to idle with bit A8.

(An additional 200 cycles(min) of clock are required for DLL Lock before any executable

command applied.)

(7) Issue precharge command for all banks of the device.

(8) Issue two or more Auto Refresh commands.

(9) Issue MRS-Initialize device operation with the reset DLL bit deactivated A8 to low.

7.2 Command Function

7.2.1 Bank Activate Command

(RAS = "L", CAS = "H", WE = "H", BS0, BS1 = Bank, A0 to A12 = Row Address)

The Bank Activate command activates the bank designated by the BS (Bank address) signal. Row

addresses are latched on A0 to A12 when this command is issued and the cell data is read out of

the sense amplifiers. The maximum time that each bank can be held in the active state is specified

as tRAS (max). After this command is issued, Read or Write operation can be executed.

7.2.2 Bank Precharge Command

(RAS = "L", CAS = "H", WE = "L", BS0, BS1 = Bank, A10 = "L", A0 to A9, A11, A12 = Don’t

Care)

The Bank Precharge command percharges the bank designated by BS. The precharged bank is

switched from the active state to the idle state.

7.2.3 Precharge All Command

(RAS = "L", CAS = "H", WE = "L", BS0, BS1 = Don’t Care, A10 = "H", A0 to A9, A11, A12 =

Don’t Care)

The Precharge All command precharges all banks simultaneously. Then all banks are switched to

the idle state.

7.2.4 Write Command

(RAS = "H", CAS = "L", WE = "L", BS0, BS1 = Bank, A10 = "L", A0 to A8 = Column Address)

The write command performs a Write operation to the bank designated by BS. The write data are

latched at both edges of DQS. The length of the write data (Burst Length) and column access

sequence (Addressing Mode) must be in the Mode Register at power-up prior to the Write

operation.

W9425G6DH

Publication Release Date:Feb. 12 , 2008

- 10 - Revision A8

7.2.5 Write with Auto-precharge Command

(RAS = "H", CAS = "L", WE = "L", BS0, BS1 = Bank, A10 = "H", A0 to A8 = Column Address)

The Write with Auto-precharge command performs the Precharge operation automatically after the

Write operation. This command must not be interrupted by any other commands.

7.2.6 Read Command

(RAS = "H", CAS = "L", WE = "H", BS0, BS1 = Bank, A10 = "L", A0 to A8 = Column Address)

The Read command performs a Read operation to the bank designated by BS. The read data are

synchronized with both edges of DQS. The length of read data (Burst Length), Addressing Mode

and CAS Latency (access time from CAS command in a clock cycle) must be programmed in the

Mode Register at power-up prior to the Read operation.

7.2.7 Read with Auto-precharge Command

(RAS = "H", CAS= ”L”,WE = ”H”, BS0, BS1 = Bank, A10 = ”H”, A0 to A8 = Column Address)

The Read with Auto-precharge command automatically perform s the Precharge operation after the

Read operation.

1) READA≥tRAS (min) - (BL/2) x tCK

Internal precharge operation begin s after BL/2 cycle from Re ad with Auto-precharge command.

2) tRCD(min) ≤ READA < tRAS(min) - (BL/2) x tCK

Data can be read with shortest latency, but the internal Precharge operation does not begin until

after tRAS (min) has completed.

This command must not be interrupted by any other command.

7.2.8 Mode Register Set Command

(RAS = "L", CAS = "L", WE = "L", BS0 = "L", BS1 = "L", A0 to A12 = Register Data)

The Mode Register Set command programs the values of CAS Latency, Addressing Mode, Burst

Length and DLL reset in the Mode Register. The default values in the Mode Register after power-

up are undefined, therefore this command must be issued during the power-up sequence. Also,

this command can be issued while all banks are in the idle state. Refer to the table for specific

codes.

7.2.9 Extended Mode Register Set Command

(RAS = "L", CAS = "L", WE = "L", BS0 = "H", BS1 = "L", A0 to A12 = Register data)

The Extended Mode Register Set command can be implemented as needed for function

extensions to the standard (SDR-SDRAM). These additional functions include DLL enable/disable,

output drive strength selection. The default value of the extended mode register is not defined;

therefore this command must be issued during the power-up sequence for enabling DLL. Refer to

the table for specific codes.

7.2.10 No-Operation Command

(RAS = "H", CAS = "H", WE = "H")

The No-Operation command simply performs no operation (same command as Device Deselect).

W9425G6DH

Publication Release Date:Feb. 12 , 2008

- 11 - Revision A8

7.2.11 Burst Read Stop Command

(RAS = "H", CAS= "H", WE = "L")

The Burst stop command is used to stop the burst operation. This command is only valid during a

Burst Read operation.

7.2.12 Device Deselect Command

(CS = "H")

The Device Deselect command disables the command decoder so that the RAS , CAS ,

WE and Address inputs are ignored. This command is similar to the No-Operation command.

7.2.13 Auto Refresh Command

(RAS = "L", CAS = "L", WE = "H", CKE = "H", BS0, BS1, A0 to A12 = Don’t Care)

AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous to CAS–

BEFORE–RAS (CBR) refresh in previous DRAM types. This comm and is non persistent, so it

must be issued each time a refre sh i s re quired. The refresh addressing is generated by the

internal refresh controller. This ma kes the address bits ”Don’t Care” during an AUTO REFRES H

command. The DDR SDRAM requires AUTO REFRESH cycles at an average periodic interval of

tREFI (maximum). To allow for improved efficiency in scheduling and switching between tasks,

some flexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH

commands can be posted to any given DDR SDRAM, and the maximum absolute interval

between any AUTO REFRESH command and the next AUTO REFRESH command is 8 * tREFI.

7.2.14 Self Refresh Entry Command

(RAS = "L", CAS = "L", WE = "H", CKE = "L", BS0, BS1, A0 to A12 = Don’t Care)

The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of

the system is powered down. When in the self refresh mode, the DDR SDRAM retains data

without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH

command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF

REFRESH, and is automatically enabled upon exiting SELF REFRESH. Any time the DLL is

enabled a DLL Reset must follow and 200 clock cycles should occur before a READ command

can be issued. Input signals except CKE are “Don’t Care” during SELF REFRESH. Since CKE is

an SSTL_2 input, VREF must be maintained during SELF REF RESH.

7.2.15 Self Refresh Exit Command

(CKE = "H", CS = "H" or CKE = "H", RAS = "H", CAS = "H")

The procedure for exiting self refresh requires a sequence of com mands. First, CLK must be

stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP

commands issue d for tXSNR because time is required for the completion of any internal refresh in

progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for

200 clock cycles before a pplying any other command.

The use of SELF REFREH mode introduces the possibility that an internally timed event can be

missed when CKE is raised for exit from self refresh mode. Upon exit from SELF REFRESH an

extra auto refresh command is recommended.

W9425G6DH

Publication Release Date:Feb. 12 , 2008

- 12 - Revision A8

7.2.16 Data Write Enable /Disable Command

(DM = "L/H" or LDM, UDM = "L/H")

During a Write cycle, the DM or LDM, UDM signal functions as Data Mask and can control every

word of the input data. The LDM signal controls DQ0 to DQ7 and UDM signal controls DQ8 to

DQ15.

7.3 Read Operation

Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read

command is issued after tRCD from the Bank Activate command, the data is read out sequentially,

synchronized with both edges of DQS (Burst Read operation). The initial read data becomes available

after CAS Latency from the issuing of the Read command. The CAS Latency must be set in the Mode

When the Precharge Operation is performed on a bank during a Burst Read and operation, the Burst

operation is terminated.

When the Read with Auto-precharge command is issued, the Precharge operation is performed

automatically after the Read cycle then the bank is switched to the idle state. This command cannot

be interrupted by any other commands. Refer to the diagrams for Read operation.

7.4 Write Operation

Issuing the Write command after tRCD from the bank activate command. The input data is latched

sequentially, synchronizing with both edges(rising & falling) of DQS after the Write command (Burst

write operation). The burst length of the Write data (Burst Length) and Addressing Mode must be set

in the Mode Register at power-up.

When the Precharge operation is performed in a bank during a Burst Write operation, the Burst

operation is terminated.

When the Write with Auto-precharge command is issued, the Precharge operation is performed

automatically after the Write cycle, then the bank is switched to the idle state, The Write with Auto-

precharge command cannot be interrupted by any other command for the entire burst data duration.

Refer to the diagrams for Write operation.

W9425G6DH

Publication Release Date:Feb. 12 , 2008

- 13 - Revision A8

7.5 Precharge

There are two Commands, which perform the precharge operation (Bank Precharge and Precharge

All). When the Bank Precharge command is issued to the active bank, the bank is precharged and

then switched to the idle state. The Bank Precharge command can precharge one bank independently

of the other bank and hold the unprecharged bank in the active state. The maximum time each bank

can be held in the active state is specified as tRAS (max). Therefore, each bank must be precharged

within tRAS(max) from the bank activate command.

The Precharge All command can be used to precharge all banks simultaneously. Even if banks are

not in the active state, the Precharge All command can still be issued. In this case, the Precharge

operation is performed only for the active bank and the precharge bank is then switched to the idle

state.

7.6 Burst Termination

When the Precharge command is used for a bank in a Burst cycle, the Burst operation is terminated.

When Burst Read cycle is interrupted by the Precharge command, read operation is disabled after

clock cycle of (CAS Latency) from the Precharge command. When the Burst Write cycle is interrupted

by the Precharge command, the input circuit is reset at the same clock cycle at which the precharge

command is issued. In this case, the DM signal must be asserted "high" during tWR to prevent writing

the invalided data to the cell array.

When the Burst Read Stop command is issued for the bank in a Burst Read cycle, the Burst Read

operation is terminated. The Burst read Stop command is not supported during a write burst operation.

Refer to the diagrams for Burst termination.

7.7 Refresh Operation

Two types of Refresh operation can be performed on the device: Auto Refresh and Self Refresh. By

repeating the Auto Refresh cycle, each bank in turn refreshed automatically. The Refresh operation

must be performed 8192 times (rows) within 64mS. The period between the Auto Refresh command

and the next command is specified by tRFC.

Self Refresh mode enters issuing the Self Refresh command (CKE asserted "low") while all banks are

in the idle state. The device is in Self Refresh mode for as long as CKE held "low". In the case of

distributed Auto Refresh commands, distributed auto refresh commands must be issued every 7.8 µS

and the last distributed Auto Refresh commands must be performed within 7.8 µS before entering the

self refresh mode. After exiting from the Self Refresh mode, the refresh operation must be performed

within 7.8 µS. In Self Refresh mode, all input/output buffers are disabled, resulting in lower power

dissipation (except CKE buffer). Refer to the diagrams for Refresh operation.

7.8 Power Down Mode

Two types of Power Down Mode can be performed on the device: Active Standby Power Down Mode

and Precharge Standby Power Down Mo de.

When the device enters the Power Down Mode, all input/output buffers and DLL are disabled resulting

in low power dissipation (except CKE buffer).

Power Down Mode enter asserting CKE "low" while the device is not running a burst cycle. Taking

CKE "high" can exit this mode. When CKE goes high, a No operation command must be input at next

CLK rising edge. Refe r to the diagrams for Power Down Mode.

W9425G6DH

Publication Release Date:Feb. 12 , 2008

- 14 - Revision A8

7.9 Input Clock Frequency Change during Precharge Power Down Mode

DDR SDRAM input clock frequency can be changed under followin g condition:

DDR SDRAM must be in precharged powe r down mode with CKE at logic LOW level. After a minimum

of 2 clocks after CKE goes LOW, the clock frequency may chan ge to any frequency between minimum

and maximum operating frequency specified for the particular speed grade. During an input clock

frequency change, CKE must be held LOW. Once the input clock frequency is changed, a stable clock

must be provided to DRAM before precharge power down mode may be exited. The DLL must be

RESET via EMRS after precharge power down exit. An additional MRS command may need to be

issued to appropriately set CL etc. After the DLL relock time, the DRAM is ready to operate with new

clock frequency.

7.10 Mode Register Operation

The mode register is programmed by the Mode Register Set command (MRS/EMRS) when all banks

are in the idle state. The data to be set in the Mode Register is transferred using the A0 to A12 and

BS0, BS1 address inputs.

The Mode Register designates the operation mode for the read or write cycle. The register is divided

into five filed: (1) Burst Length field to set the length of burst data (2) Addressing Mode selected bit to

designate the column access sequence in a Burst cycle (3) CAS Latency field to set the assess time in

clock cycle (4) DLL reset field to reset the DLL (5) Regular/Extended Mode Register filed to select a

type of MRS (Regular/Extended MRS). EMRS cycle can be implemented the extended function (DLL

enable/Disable mode)

The initial value of the Mode Register (including EMRS) after power up is undefined; therefore the

Mode Register Set command must be issued before power operation.

7.10.1 Burst Length field (A2 to A0)

This field specifies the data length for column access using the A2 to A0 pins and sets the Burst

Length to be 2, 4, and 8 words.

A2 A1 A0 BURST LENGTH

0 0 0 Reserved

0 0 1 2 words

0 1 0 4 words

0 1 1 8 words

1 x x Reserved

7.10.2 Addressing Mode Select (A3)

The Addressing Mode can be one of two modes; Interleave mode or Sequential Mode, When the

A3 bit is "0", Sequential mode is selected. When the A3 bit is "1", Interleave mode is selected. Both

addressing M ode support burst length 2, 4, and 8 words.

A3 ADDRESSING MODE

0 Sequential

1 Interleave

W9425G6DH

Publication Release Date:Feb. 12 , 2008

- 15 - Revision A8

7.10.2.1. Addressing Sequence of Sequential Mode

A column access is performed by incrementing the column address input to the device. The

address is varied by the Burst Length as the following.

Addressing Sequence of Sequential Mode

DATA ACCESS ADDRESS BURST LENGTH

Data 0 n 2 words (address bits is A0)

Data 1 n + 1 not carried from A0 to A1

Data 2 n + 2 4 words (address bit A0, A1)

Data 3 n + 3 Not carried from A1 to A2

Data 4 n + 4

Data 5 n + 5 8 words (address bits A2, A1 and A0)

Data 6 n + 6 Not carried from A2 to A3

Data 7 n + 7

7.10.2.2. Addressing Sequence for Interleave Mode

A Column access is started from the inputted column address and is performed by interleaving the

address bits in the sequence shown as the following.

Address Sequence for Interleave Mode

DATA ACCESS ADDRESS BURST LENGTH

Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 2 words

Data 1 A8 A7 A6 A5 A4 A3 A2 A1 A0

Data 2 A8 A7 A6 A5 A4 A3 A2 A1 A0 4 words

Data 3 A8 A7 A6 A5 A4 A3 A2 A1 A0

Data 4 A8 A7 A6 A5 A4 A3 A2 A1 A0 8 words

Data 5 A8 A7 A6 A5 A4 A3 A2 A1 A0

Data 6 A8 A7 A6 A5 A4 A3 A2 A1 A0

Data 7 A8 A7 A6 A5 A4 A3 A2 A1 A0

W9425G6DH

Publication Release Date:Feb. 12 , 2008

- 16 - Revision A8

7.10.3 CAS Latency field (A6 to A4)

This field specifies the number of clock cycles from the assertion of the Read command to the first

data read. The minimum values of CAS Latency depend on the frequency of CLK.

A6 A5 A4 CAS LATENCY

0 0 0 Reserved

0 0 1 Reserved

0 1 0 2

0 1 1 3

1 0 0 Reserved

1 0 1 Reserved

1 1 0 2.5

1 1 1 Reserved

7.10.4 DLL Reset bit (A8)

This bit is used to reset DLL. When the A8 bit is "1", DLL is reset.

7.10.5 Mode Register /Extended Mode register change bits (BS0, BS1)

These bits are used to select MRS/EMRS.

BS1 BS0 A12-A0

0 0 Regular MRS Cycle

0 1 Extended MRS Cycle

1 x Reserved

7.10.6 Extended Mode Register field

1) DLL Switch field (A0)

This bit is used to select DLL enable or disable

A0 DLL

0 Enable

1 Disable

2) Output Driver Size Control field (A1)

This bit is used to select Output Driver Size, both Full strength and Half strength are based on

JEDEC standard.

A1 OUTPUT DRIVER

0 Full Strength

1 Half Strength

7.10.7 Reserved field

• Test mode entry bit (A7)

This bit is used to enter Test mode and must be set to "0" for normal operation.

• Reserved bits (A9, A10, A11, A12)

These bits are reserved for future op erations. They must be set to "0" for normal operation.

W9425G6DH

Publication Release Date:Feb. 12 , 2008

- 17 - Revision A8

8. OPERATION MODE

The following table shows the operation commands.

8.1 Simplified Truth Table

SYM. COMMAND

DEVICE

STATE CKEn-1 CKEn DM(4) BS0,

BS1 A10

A12,

A11,

A9-A0

RAS CAS WE

ACT Bank Active Idle(3) H X X V V V L L H H

PRE Bank Precharge Any(3) H X X V L X L L H L

PREA Precharge All Any H X X X H X L L H L

WRIT Write Active(3) H X X V L V L H L L

WRITA Write with Auto-

precharge Active(3) H X X V H V L H L L

READ Read Active(3) H X X V L V L H L H

READA Read with Auto-

precharge Active(3) H X X V H V L H L H

MRS Mode Register Set Idle H X X L, L C C L L L L

EMRS Extended Mode

NOP No Operation Any H X X X X X L H H H

BST Burst Read Stop Active H X X X X X L H H L

DSL Device Deselect Any H X X X X X H X X X

AREF Auto Refresh Idle H H X X X X L L L H

SELF Self Refresh Entry Idle H L X X X X L L L H

H X X X

SELEX Self Refresh Exit Idle (Self

Refresh) L H X X X X L H H X

H X X X

PD Power Down

Mode Entry Idle/

Active(5) H L X X X X

L H H X

H X X X

PDEX Power Down

Mode Exit Any (Power

Down) L H X X X X L H H X

WDE Data Write Enable Active H X L X X X X X X X

WDD Data Write Disable Active H X H X X X X X X X

Notes:

1. V = Valid X = Don’t Care L = Low level H = High level

2. CKEn signal is input level when commands are issued.

CKEn-1 signal is input level one clock cycle before the commands are issued.

3. These are state designated by the BS0, BS1 signals.

4. LDM, UDM (W9425G6DH).

5. Power Down Mode can not entry in the burst cycle.

W9425G6DH

Publication Release Date:Feb. 12 , 2008

- 18 - Revision A8

8.2 Function Truth Table

(Note 1)

CURRENT

STATE CS RAS CAS WE ADDRESS COMMAND ACTION NOTES

H X X X X DSL NOP

L H H X X NOP/BST NOP

L H L H BS, CA, A10 READ/READA ILLEGAL 3

L H L L BS, CA, A10 WRIT/WRITA ILLEGAL 3

L L H H BS, RA ACT Row activating

L L H L BS, A10 PRE/PREA NOP

L L L H X AREF/SELF Refresh or Self refresh 2

Idle

L L L L Op-Code MRS/EMRS Mode register accessing 2

H X X X X DSL NOP

L H H X X NOP/BST NOP

L H L H BS, CA, A10 READ/READA Begin read: Determine AP 4

L H L L BS, CA, A10 WRIT/WRITA Begin write: Determine AP 4

L L H H BS, RA ACT ILLEGAL 3

L L H L BS, A10 PRE/PREA Precharge 5

L L L H X AREF/SELF ILLEGAL

Row Active

L L L L Op-Code MRS/EMRS ILLEGAL

H X X X X DSL Continue burst to end

L H H H X NOP Continue burst to end

L H H L X BST Burst stop

L H L H BS, CA, A10 READ/READA Term burst, new read: Determine AP 6

L H L L BS, CA, A10 WRIT/WRITA ILLEGAL

L L H H BS, RA ACT ILLEGAL 3

L L H L BS, A10 PRE/PREA Term burst, precharging

L L L H X AREF/SELF ILLEGAL

Read

L L L L Op-Code MRS/EMRS ILLEGAL

H X X X X DSL Continue burst to end

L H H H X NOP Continue burst to end

L H H L X BST ILLEGAL

L H L H BS, CA, A10 READ/READA Term burst, start read: Determine AP 6, 7

L H L L BS, CA, A10 WRIT/WRITA Term burst, start read: Determine AP 6

L L H H BS, RA ACT ILLEGAL 3

L L H L BS, A10 PRE/PREA Term burst, precharging 8

L L L H X AREF/SELF ILLEGAL

Write

L L L L Op-Code MRS/EMRS ILLEGAL

W9425G6DH

Publication Release Date:Feb. 12 , 2008

- 19 - Revision A8

Function Truth Table, continued

CURRENT

STATE CS RAS CAS WE ADDRESS COMMAND ACTION NOTES

H X X X X DSL Continue burst to end

L H H H X NOP Continue burst to end

L H H L X BST ILLEGAL

L H L H BS, CA, A10 READ/READA ILLEGAL

L H L L BS, CA, A10 WRIT/WRITA ILLEGAL 3

L L H H BS, RA ACT ILLEGAL 3

L L H L BS, A10 PRE/PREA ILLEGAL

L L L H X AREF/SELF ILLEGAL

Read with

Auto-

precharge

L L L L Op-Code MRS/EMRS ILLEGAL

H X X X X DSL Continue burst to end

L H H H X NOP Continue burst to end

L H H L X BST ILLEGAL

L H L H BS, CA, A10 READ/READA ILLEGAL

L H L L BS, CA, A10 WRIT/WRITA ILLEGAL

L L H H BS, RA ACT ILLEGAL 3

L L H L BS, A10 PRE/PREA ILLEGAL 3

L L L H X AREF/SELF ILLEGAL

Write with

Auto-

precharge

L L L L Op-Code MRS/EMRS ILLEGAL

H X X X X DSL NOP-> Idle after tRP

L H H H X NOP NOP-> Idle after tRP

L H H L X BST ILLEGAL

L H L H BS, CA, A10 READ/READA ILLEGAL 3

L H L L BS, CA, A10 WRIT/WRITA ILLEGAL 3

L L H H BS, RA ACT ILLEGAL 3

L L H L BS, A10 PRE/PREA Idle after tRP

L L L H X AREF/SELF ILLEGAL

Precharging

L L L L Op-Code MRS/EMRS ILLEGAL

H X X X X DSL NOP-> Row active after tRCD

L H H H X NOP NOP-> Row active after tRCD

L H H L X BST ILLEGAL

L H L H BS, CA, A10 READ/READA ILLEGAL 3

L H L L BS, CA, A10 WRIT/WRITA ILLEGAL 3

L L H H BS, RA ACT ILLEGAL 3

L L H L BS, A10 PRE/PREA ILLEGAL 3

L L L H X AREF/SELF ILLEGAL

Row

Activating

L L L L Op-Code MRS/EMRS ILLEGAL

W9425G6DH

Publication Release Date:Feb. 12 , 2008

- 20 - Revision A8

Function Truth Table, continued

CURRENT

STATE CS RAS CAS WE ADDRESS COMMAND ACTION NOTE

H X X X X DSL NOP->Row active after tWR

L H H H X NOP NOP->Row active after tWR

L H H L X BST ILLEGAL

L H L H BS, CA, A10 READ/READA ILLEGAL 3

L H L L BS, CA, A10 WRIT/WRITA ILLEGAL 3

L L H H BS, RA ACT ILLEGAL 3

L L H L BS, A10 PRE/PREA ILLEGAL 3

L L L H X AREF/SELF ILLEGAL

Write

Recovering

L L L L Op-Code MRS/EMRS ILLEGAL

H X X X X DSL NOP->Enter precharge after tWR

L H H H X NOP NOP->Enter precharge after tWR

L H H L X BST ILLEGAL

L H L H BS, CA, A10 READ/READA ILLEGAL 3

L H L L BS, CA, A10 WRIT/WRITA ILLEGAL 3

L L H H BS, RA ACT ILLEGAL 3

L L H L BS, A10 PRE/PREA ILLEGAL 3

L L L H X AREF/SELF ILLEGAL

Write

Recovering

with Auto-

precharge

L L L L Op-Code MRS/EMRS ILLEGAL

H X X X X DSL NOP->Idle after tRC

L H H H X NOP NOP->Idle after tRC

L H H L X BST ILLEGAL

L H L H X READ/WRIT ILLEGAL

L L H X X ACT/PRE/PREA ILLEGAL

Refreshing

L L L X X AREF/SELF/MRS/EMRS ILLEGAL

H X X X X DSL NOP->Row after tMRD

L H H H X NOP NOP->Row after tMRD

L H H L X BST ILLEGAL

L H L X X READ/WRIT ILLEGAL

Mode

Accessing

L L X X X ACT/PRE/PREA/ARE

F/SELF/MRS/EMRS ILLEGAL

Notes:

1. All entries assume that CKE was active (High level) during the preceding clock cycle and the current clock cycle.

2. Illegal if any bank is not idle.

3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BS), depending on the

state of that bank.

4. Illegal if tRCD is not satisfied.

5. Illegal if tRAS is not satisfied.

6. Must satisfy burst interrupt condition.

7. Must avoid bus contention, bus turn around, and/or satisfy write recovery requirements.

8. Must mask preceding data which don’t satisfy tWR

Remark: H = High level, L = Low level, X = High or Low level (Don’t care), V = Valid data

W9425G6DH

Publication Release Date:Feb. 12 , 2008

- 21 - Revision A8

8.3 Function Truth Table for CKE

CKE

CURRENT

STATE n-1 n

CS RAS CAS WE ADDRESS ACTION NOTES

H X X X X X X INVALID

L H H X X X X Exit Self Refresh->Idle after tXSNR

L H L H H X X Exit Self Refresh->Idle after tXSNR

L H L H L X X ILLEGAL

L H L L X X X ILLEGAL

Self Refresh

L L X X X X X Maintain Self Refresh

H X X X X X X INVALID

L H X X X X X Exit Power down->Idle after tIS

Power Down

L L X X X X X Maintain power down mode

H H X X X X X Refer to Function Truth Table

H L H X X X X Enter Power down 2

H L L H H X X Enter Power down 2

H L L L L H X Self Refresh 1

H L L H L X X ILLEGAL

H L L L X X X ILLEGAL

All banks Idle

L X X X X X X Power down

H H X X X X X Refer to Function Truth Table

H L H X X X X Enter Power down 3

H L L H H X X Enter Power down 3

H L L L L H X ILLEGAL

H L L H L X X ILLEGAL

H L L L X X X ILLEGAL

Row Active

L X X X X X X Power down

Any State

Other Than

Listed Above H H X X X X X Refer to Function Truth Table

Notes:

1. Self refresh can enter only from the all banks idle state.

2. Power Down occurs when all banks are idle; this mode is referred to as precharge power down.

3. Power Down occurs when there is a row active in any bank; this mode is referred to as active power down.

Remark: H = High level, L = Low level, X = High or Low level (Don’t care), V = Valid data

W9425G6DH

Publication Release Date:Feb. 12 , 2008

- 22 - Revision A8

8.4 Simplified Stated Diagram

POWER

APPLIED

Automatic Sequence

Command Sequence

Read A

Write Read

ROW

ACTIVE

POWER

DOWN

IDLE

MODE

SET

AUTO

REFRESH

SELF

REFRESH

Read

Read A

Write

Write A

PRE

CHARGE

POWER

MRS/EMRS AREF

SREF

SREFX

PDEX

ACT

BST

Read

Write

Write A Write A Read A

PRE

ACTIVE

POWERDOWN

PDEX

Read

Read A

W9425G6DH

Publication Release Date:Feb. 12 , 2008

- 23 - Revision A8

9. ELECTRICAL CHARACTERISTICS

9.1 Absolute Maximum Ratings

PARAMETER SYMBOL RATING UNIT

Input/Output Voltage VIN, VOUT -0.3 ~ VDDQ + 0.3 V

Power Supply Voltage VDD, VDDQ -0.3 ~ 3.6 V

Operating Temperature (-4/-5/-6/-6F/-75) TOPR 0 ~ 70 °C

Operating Temperature (-6I/75I) TOPR -40 ~ 85 °C

Storage Temperature TSTG -55 ~ 150 °C

Soldering Temperature (10s) TSOLDER 260 °C

Power Dissipation PD 1 W

Short Circuit Output Current IOUT 50 mA

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

9.2 Recommended DC Operating Conditions

(TA = 0 to 70°C for -4/-5/–6/-6F/-75, TA = -40 to 85°C for -6I/75I)

SYMBOL PARAMETER MIN. TYP. MAX. UNIT NOTES

VDD Power Supply Voltage 2.3 2.5 2.7 V 2

VDDQ Power Supply Voltage (for I/O

Buffer) 2.3 2.5 VDD V 2

VREF Input reference Voltage 0.49 x VDDQ 0.50 x VDDQ 0.51 x VDDQ V 2, 3

VTT Termination Voltage (System) VREF - 0.04 VREF VREF + 0.04 V 2, 8

VIH (DC) Input High Voltage (DC) VREF + 0.15 - VDDQ + 0.3 V 2

VIL (DC) Input Low Voltage (DC) -0.3 - VREF - 0.15 V 2

VICK (DC) Differential Clock DC Input Voltage -0.3 - VDDQ + 0.3 V 15

VID (DC) Input Differential Voltage.

CLK and CLK inputs (DC) 0.36 - VDDQ + 0.6 V 13, 15

VIH (AC) Input High Voltage (AC) VREF + 0.31 - - V 2

VIL (AC) Input Low Voltage (AC) - - VREF - 0.31 V 2

VID (AC) Input Differential Voltage.

CLK and CLK inputs (AC) 0.7 - VDDQ + 0.6 V 13, 15

VX (AC) Differential AC input Cross Po int

Voltage VDDQ/2 - 0.2 - VDDQ/2 + 0.2 V 12, 15

VISO (AC) Differential Clock AC Middle Point VDDQ/2 - 0.2 - VDDQ/2 + 0.2 V 14, 15

Notes: Undershoot Limit: VIL (min) = -1.2V with a pulse width < 3 nS

Overshoot Limit: VIH (max) = VDDQ +1.2V with a pulse width < 3 nS

VIH (DC) and VIL (DC) are levels to maintain the current logic state.

VIH (AC) and VIL (AC) are levels to change to the new logic state.

W9425G6DH

Publication Release Date:Feb. 12 , 2008

- 24 - Revision A8

9.3 Capacitance

(VDD = VDDQ = 2.5V ±0.2V, f = 1 MHz, TA = 25 °C, VOUT (DC) = VDDQ/2, VOUT (Peak to Peak) = 0.2V)

SYMBOL PARAMETER MIN. MAX.

DELTA

(MAX.) UNIT

CIN Input Capacitance (exce pt for CLK pins) 2.0 3.0 0.5 pF

CCLK Input Capacitance (CLK pins) 2.0 3.0 0.25 pF

CI/O DQ, DQS, DM Capacitance 4.0 5.0 0.5 pF

CNC NC Pin Ca pacitance - 1.5 - pF

Notes: These parameters a re periodically sampled and not 100% tested.

9.4 Leakage and Output Buffer Characteristics

SYMBOL PARAMETER MIN. MAX. UNIT NOTES

II (L) Input Leakage Current

(0V < VIN < VDDQ, All other pins not under test = 0V) -2 2 µA

IO (L) Output Leakage Current

(Output disabled, 0V < VOUT < VDDQ) -5 5 µA

VOH Output High Voltage

(under AC test load condition) VTT +0.76 - V

VOL Output Low Voltage

(under AC test load condition) - VTT -0.76 V

IOH (DC) Output Minimum Source DC Current -15.2 - mA 4, 6

IOL (DC) Output Minimum Sink DC Current

Full

Strength

15.2 - mA 4, 6

IOH (DC) Output Minimum Source DC Current -10.4 - mA 5

IOL (DC) Output Minimum Sink DC Current Half

Strength 10.4 - mA 5

W9425G6DH

Publication Release Date:Feb. 12 , 2008

- 25 - Revision A8

9.5 DC Characteristics

MAX.

SYM. PARAMETER

-4 -5 -6/-6F/-6I -75/75I

UNIT NOTES

IDD0

Operating current: One Bank Active-Precharge; tRC = tRC

min; tCK = tCK min; DQ, DM and DQS inputs changing

twice per clock cycle; Address and control inputs

changing once per clock cycle

110 110 110 110 7

IDD1

Operating current: One Bank Active-Read-Precharge;

Burst = 2; tRC = tRC min; CL = 3; tCK = tCK min; IOUT = 0

mA; Address and control inputs changing once per clock

cycle.

150 150 150 150 7, 9

IDD2P Precharge Power Down standby current: All Banks Idle;

Power down mode; CKE < VIL max; tCK = tCK min; Vin =

VREF for DQ, DQS and DM 20 20 20 20

IDD2F

Idle floating standby current: CS > VIH min; All Banks

Idle; CKE > VIH min; Address and other control inputs

changing once per clock cycle; Vin = Vref for DQ, DQS

and DM

45 45 45 40 7

IDD2N

Idle standby current: CS > VIH min; All Banks Idle; CKE

> VIH min; tCK = tCK min; Address and other control inputs

changing once per clock cycle; Vin > VIH min or Vin < VIL

max for DQ, DQS and DM

45 45 45 40 7

IDD2Q Idle quiet standby current: CS > VIH min; All Banks

Idle; CKE > VIH min; tCK = tCK min; Address and other

control inputs stable; Vin > VREF for DQ, DQS and DM 40 40 40 35 mA 7

IDD3P Active Power Down standby current: One Bank Active;

Power down mode; CKE < VIL max; tCK = tCK min 20 20 20 20

IDD3N

Active standby current: CS > VIH min; CKE > VIH min;

One Bank Active-Precharge; tRC = tRAS max; tCK = tCK

min; DQ, DM and DQS inputs changing twice per clock

cycle; Address and other control inputs changing once

per clock cycle

70 70 70 65 7

IDD4R Operating current: Burst = 2; Reads; Continuous burst;

One Bank Active; Address and control inputs changing

once per clock cycle; CL=3; tCK = tCK min; IOUT = 0mA 190 180 170 160 7, 9

IDD4W

Operating current: Burst = 2; Write; Continuous burst;

One Bank Active; Address and control inputs changing

once per clock cycle; CL = 3; tCK = tCK min; DQ, DM and

DQS inputs changing twice per clock cycle

190 180 170 160 7

IDD5 Auto Refresh current: tRC = tRFC min 190 190 190 190 7

IDD6 Self Refresh current: CKE < 0.2V 5 3 3 3

IDD7

Random Read current: 4 Banks Active Read with

activate every 20nS, Auto-precharge Read every 20 nS;

Burst = 4; tRCD = 3; IOUT = 0mA; DQ, DM and DQS inputs

changing twice per clock cycle; Address changing once

per clock cycle

300 300 300 300

W9425G6DH

Publication Release Date:Feb. 12 , 2008

- 26 - Revision A8

9.6 AC Characteristics and Operating Condition

(Notes: 10, 12)

-4 -5

SYM. PARAMETER

MIN. MAX. MIN. MAX.

UNIT NOTES

tRC Active to Ref/Active Command Period 52 55

tRFC Ref to Ref/Active Command Period 60 70

tRAS Active to Precharge Command Period 36 70000 40 70000

tRCD Active to Read/Write Command Delay Time 16 15

tRAP Active to Read with Auto-precharge Enable 16 15

tCCD Read/Write(a) to Read/Write(b) Command Period 1 1 tCK

tRP Precharge to Active Command Period 16 15

tRRD Active(a) to Active(b) Command Period 8 10

tWR Write Recovery Time 15 15 nS

tDAL Auto-precharge Write Recovery + Precharge Time - - tCK 18

2 - - 7.5 10

2.5 - - 6 10

tCK CLK Cycle Time 3 4 10 5 10

tAC Data Access Time from CLK, CLK -0.7 0.7 -0.7 0.7

tDQSCK DQS Output Access Time from CLK, CLK -0.6 0.6 -0.6 0.6 16

tDQSQ Data Strobe Edge to Output Data Edge Skew 0.45 0.4

tCH CLk High Level Width 0.45 0.55 0.45 0.55

tCL CLK Low Level Width 0.45 0.55 0.45 0.55 tCK 11

tHP CLK Half Period (minimum of actual tCH, tCL) Min.

(tCL, tCH) Min.

(tCL, tCH)

tQH DQ Output Data Hold Time from DQS tHP

-0.55 tHP

-0.5 nS

tRPRE DQS Read Preamble Time 0.9 1.1 0.9 1.1

tRPST DQS Read Postamble Time 0.4 0.6 0.4 0.6 tCK 11

tDS DQ and DM Setup Time 0.4 0.4

tDH DQ and DM Hold Time 0.4 0.4

tDIPW DQ and DM Input Pulse Width (for each input) 1.75 1.75 nS

tDQSH DQS Input High Pulse Width 0.35 0.35

tDQSL DQS Input Low Pulse Width 0.35 0.35

tDSS DQS Falling Edge to CLK Setup Time 0.2 0.2

tDSH DQS Falling Edge Hold Time from CLK 0.2 0.2

tCK 11

tWPRES Clock to DQS Write Preamble Set-up Time 0 0 nS

tWPRE DQS Write Preamble Time 0.25 0.25

tWPST DQS Write Postamble Time 0.4 0.6 0.4 0.6

tDQSS Write Command to First DQS Latching Transition 0.85 1.15 0.72 1.25 tCK 11

tIS Input Setup Time 0.6 0.6

tIH Input Hold Time 0.6 0.6

tIPW Control & Address Input Pulse Width (for each input) 2.2 2.2

tHZ Data-out High-impedance Time from CLK, CLK -0.7 0.7 -0.7 0.7

tLZ Data-out Low-impedance Time from CLK, CLK -0.7 0.7 -0.7 0.7

tT(SS) SSTL Input Transition 0.5 1.5 0.5 1.5

tWTR Internal Write to Read Command Delay 2 2 tCK

tXSNR Exit Self Refresh to non-Read Command 72 75 nS

tXSRD Exit Self Refresh to Read Command 200 200 tCK

tREFI Refresh Time (8k/64mS) 7.8 7.8 µS 17

tMRD Mode Register Set Cycle Time 8 10 nS

W9425G6DH

Publication Release Date:Feb. 12 , 2008

- 27 - Revision A8

Continued

-6/-6F/-6I -75/75I

SYM. PARAMETER

MIN. MAX. MIN. MAX.

UNIT NOTES

tRC Active to Ref/Active Command Period 60 67.5

tRFC Ref to Ref/Active Command Period 72 75

tRAS Active to Precharge Command Period 42 100000 45 100000

tRCD Active to Read/Write Command Delay Time 18 20

tRAP Active to Read with Auto-precharge Enable 15 15

tCCD Read/Write(a) to Read/Write(b) Command Period 1 1 tCK

tRP Precharge to Active Command Period 18 20

tRRD Active(a) to Active(b) Command Period 12 15

tWR Write Recovery Time 15 15 nS

tDAL Auto-precharge Write Recovery + Precharge Time - - tCK 18

2 7.5 12 7.5 12

2.5 6 12 7.5 12

tCK CLK Cycle Time 3 6 12 7.5 12

tAC Data Access Time from CLK, CLK -0.7 0.7 -0.75 0.75

tDQSCK DQS Output Access Time from CLK, CLK -0.6 0.6 -0.75 0.75 16

tDQSQ Data Strobe Edge to Output Data Edge Skew 0.45 0.5

tCH CLk High Level Width 0.45 0.55 0.45 0.55

tCL CLK Low Level Width 0.45 0.55 0.45 0.55 tCK 11

tHP CLK Half Period (minimum of actual tCH, tCL) min

(tCL,tCH) Min,

(tCL,tCH)

tQH DQ Output Data Hold Time from DQS tHP

-0.55 tHP

-0.75 nS

tRPRE DQS Read Preamble Time 0.9 1.1 0.9 1.1

tRPST DQS Read Postamble Time 0.4 0.6 0.4 0.6 tCK 11

tDS DQ and DM Setup Time 0.45 0.5

tDH DQ and DM Hold Time 0.45 0.5

tDIPW DQ and DM Input Pulse Width (for each input) 1.75 1.75 nS

tDQSH DQS Input High Pulse Width 0.35 0.35

tDQSL DQS Input Low Pulse Width 0.35 0.35

tDSS DQS Falling Edge to CLK Setup Time 0.2 0.2

tDSH DQS Falling Edge Hold Time from CLK 0.2 0.2

tCK 11

tWPRES Clock to DQS Write Preamble Set-up Time 0 0 nS

tWPRE DQS Write Preamble Time 0.25 0.25

tWPST DQS Write Postamble Time 0.4 0.6 0.4

tDQSS Write Command to First DQS Latching Transition 0.75 1.25 0.75 1.25 tCK 11

tIS Input Setup Time 0.75 0.9

tIH Input Hold Time 0.75 0.9

tIPW Control & Address Input Pulse Width (for each input) 2.2 2.2

tHZ Data-out High-impedance Time from CLK, CLK -0.7 0.7 -0.75 0.75

tLZ Data-out Low-impedance Time from CLK, CLK -0.7 0.7 -0.75 0.75

tT(SS) SSTL Input Transition 0.5 1.5 0.5 1.5

tWTR Internal Write to Read Command Delay 1 1 tCK

tXSNR Exit Self Refresh to non-Read Command 72 75 nS

tXSRD Exit Self Refresh to Read Command 200 200 tCK

tREFI Refresh Time (8k/64mS) 7.8 7.8 µS 17

tMRD Mode Register Set Cycle Time 12 15 nS

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Publication Release Date:Feb. 12 , 2008

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9.7 AC Test Conditions

PARAMETER SYMBOL VALUE UNIT

Input High Voltage (AC) VIH VREF + 0.31 V

Input Low Voltage (AC) VIL VREF - 0.31 V

Input Reference Voltage VREF 0.5 x VDDQ V

Termination Voltage VTT 0.5 x VDDQ V

Differential Clock Input Reference Voltage VR Vx (AC) V

Input Difference Voltage. CLK and CLK Inputs (AC) VID (AC) 1.5 V

Output Timing Measurement Reference Voltage VOTR 0.5 x VDDQ V

SWING (MAX)

min (AC)

REF

max (AC)

SLEW = (V

min (AC) - V

max (AC)) /

Output

50 Ω

VTT

Timing Reference Load

Output

V(out) 30pF

Notes:

(1) Conditions outside the limits listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

(2) All voltages are referenced to VSS, VSSQ.( 2.6V±0.1V for DDR400/DDR500)

(3) Peak to peak AC noise on VREF may not exceed ±2% VREF(DC).

(4) VOH = 1.95V, VOL = 0.35V

(5) VOH = 1.9V, VOL = 0.4V

(6) The values of IOH(DC) is based on VDDQ = 2.3V and VTT = 1.19V.

The values of IOL(DC) is based on VDDQ = 2.3V and VTT = 1.11V.

(7) These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values

of tCK and tRC.

(8) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors is expected to be set

equal to VREF and must track variations in the DC level of VREF.

(9) These parameters depend on the output loading. Specified values are obtained with the output open.

(10) Transition times are measured between VIH min(AC) and VIL max(AC).Transition (rise and fall) of input signals have a fixed

slope.

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(11) IF the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to

the nearest decimal place.

(i.e., TDQSS = 0.75 × tCK, tCK = 7.5 nS, 0.75 × 7.5 nS = 5.625 nS is rounded up to 5.6 nS.)

(12) VX is the differential clock cross point voltage where input timing measurement is referenced.

(13) VID is magnitude of the difference between CLK input level and CLK input level.

(14) VISO means {VICK(CLK)+VICK(CLK )}/2.

(15) Refer to the figure below.

CLK

ICK

ID(AC)

0 V Differential

ISO

ISO(min)

ISO(max)

(16) tAC and tDQSCK depend on the clock jitter. These timing are measured at stable clock.

(17) A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.

(18) tDAL = (tWR/tCK) + (tRP/tCK)

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10. SYSTEM CHARACTERISTICS FOR DDR SDRAM

The following specification parameters are required in systems using DDR400, DDR333 & DDR266

devices to ensure proper system performance. These characteristics are for system simulation

purposes and are guaranteed by design.

10.1 Table 1: Input Slew Rate for DQ, DQS, and DM

AC CHARACTERISTICS DDR400 DDR333 DDR266

PARAMETER SYMBOL MIN. MAX. MIN. MAX. MIN. MAX. UNIT NOTES

DQ/DM/DQS input slew rate

measured between VIH(DC),

VIL(DC) and VIL(DC), VIH(DC) DCSLEW 0.5 4.0 0.5 4.0 0.5 4.0 V/nS a, m

10.2 Table 2: Input Setup & Hold Time Derating for Slew Rate

INPUT SLEW RATE ΔTIS ΔTIH UNIT NOTES

0.5 V/nS 0 0 pS i

0.4 V/nS +50 0 pS i

0.3 V/nS +100 0 pS i

10.3 Table 3: Input/Output Setup & Hold Time Derating for Slew Rate

INPUT SLEW RATE ΔTDS ΔTDH UNIT NOTES

0.5 V/nS 0 0 pS k

0.4 V/nS +75 0 pS k

0.3 V/nS +150 0 pS k

10.4 Table 4: Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate

INPUT SLEW RATE ΔTDS ΔTDH UNIT NOTES

±0.0 nS/V 0 0 pS j

±0.25 nS/V +50 0 pS j

±0.5 nS/V +100 0 pS j

10.5 Table 5: Output Slew Rate Characteristics (X16 Devices only)

SLEW RATE

CHARACTERISTIC

TYPICAL

RANGE (V/NS)

MINIMUM

(V/NS)

MAXIMUM

(V/NS) NOTES

Pullup Slew Rate 1.2 ~ 2.5 0.7 5.0 a, c, d, f, g, h

Pulldown Slew Rate 1.2 ~ 2.5 0.7 5.0 b, c, d, f, g, h

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10.6 Table 6: Output Slew Rate Matching Ratio Characteristics

SLEW RATE CHARACTERISTIC DDR400 DDR333 DDR266

PARAMETER MIN. MAX. MIN. MAX. MIN. MAX. NOTES

Output Slew Rate Matching Ratio

(Pullup to Pulldown) 0.67 1.5 0.67 1.5 0.67 1.5 e, m

10.7 Table 7: AC Overshoot/Undershoot Specification for Address and Control

Pins

SPECIFICATION

PARAMETER DDR400 DDR333 DDR266

Maximum peak amplitude allowed for ov ershoot 1.5 V 1.5 V 1.5 V

Maximum peak amplitude allowed for undershoot 1.5 V 1.5 V 1.5 V

The area between the overshoot signal and VDD

must be less than or equal to Max. area in Figure 3 3.0 V-nS 3.6 V-nS 4.5 V-nS

The area between the undersho ot signal and GND

must be less than or equal to Max. area in Figure 3 3.0 V-nS 3.6 V-nS 4.5 V-nS

0 0.5 0.68751.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.06.3125 6.5 7.0

-5

-4

-3

-2

-1

5Max. amplitude = 1.5V

Overshoot

VDD

Max. area

Max. amplitude = 1.5V GND

Undershoot

Time (nS)

Figure 3: Address and Control AC Overshoot and Undershoot Definition

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10.8 Table 8: Overshoot/Undershoot Specification for Data, Strobe, and Mask Pins

SPECIFICATION

PARAMETER DDR400 DDR333 DDR266

Maximum peak amplitude allowed for ov ershoot 1.2 V 1.2 V 1.2 V

Maximum peak amplitude allowed for undershoot 1.2 V 1.2 V 1.2 V

The area between the overshoot signal and VDD

must be less than or equal to Max. area in Figure 4 1.44 V-nS 2.25 V-nS 2.4 V-nS

The area between the undersho ot signal and GND

must be less than or equal to Max. area in Figure 4 1.44 V-nS 2.25 V-nS 2.4 V-nS

0 0.5 1.0 1.42 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.68 6.0 6.5 7.0

-5

-4

-3

-2

-1

5Max. amplitude = 1.2V

Overshoot

VDD

Max. area

Max. amplitude = 1.2V GND

Undershoot

Time (nS)

Figure 4: DQ/DM/DQS AC Overshoot and Undershoot Definition

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10.9 System Notes:

a. Pullup slew rate is characterized und er the test condition s as shown in Figure 1.

VSSQ

50 Ω

Output Test point

Figure 1: Pullup slew rate test load

b. Pulldown slew rate is measured under the test con ditions shown in Figure 2.

Figure 2: Pulldown slew rate test load

c. Pullup slew rate is measured between (VDDQ/2 - 320 mV ± 250 mV)

Pulldown slew rate is measured between (VDDQ/2 + 320 mV ± 250 mV)

Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs

switching and only one output switching.

Example: For typical slew rate, DQ0 is switching

For minimum slew rate, all DQ bits are switching worst case pattern

For maximum slew rate, on ly one DQ is switching from either high to low, or low to high

The remaining DQ bits remain the same as for previous state

d. Evaluation conditions

Typical: 25

oC (T Ambient), VDDQ = nominal, typical process

Minimum: 70

oC (T Ambient), VDDQ = minimum, slow-slow proce ss

Maximum: 0

oC (T Ambient), VDDQ = maximum, fast-fast process

e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and

voltage, over the entire temperature and voltage range. For a given output, it represents the

maximum difference between pullup and pulldown drivers due to process variation.

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f. Verified under typical conditions for qualification pu rposes.

g. TSOP II package devices only.

h. Only intended for operation up to 266 Mbps per pin .

i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below

0.5 V/nS as shown in Table 2. The Input slew rate is based on the lesser of the slew rates

determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.

j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew

rates differ, as shown in Tables 3 & 4. Input slew rate is based on the larger of AC-AC delta rise,

fall rate and DC-DC delta rise, fall rate. Input slew rate is based on the lesser of the slew rates

determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.

The delta rise/fall rate is calculated as:

{1/(Slew Rate1)}-{1/(sl ew Rate2)}

For example: If Slew Rate 1 is 0.5 V/nS and Slew Rate 2 is 0.4 V/nS, then the delta rise, fall rate is

-0.5 nS/V. Using the table given, this would result in the need for an increase in tDS and tDH of 100

pS.

k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/nS. The

I/O slew rate is based on the lesser of the AC-AC slew rate and the DC-DC slew rate. The input

slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC)

to VIL(DC), and similarly for rising transitions.

m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve

setup and hold times. Signal transition s through the DC region must be monotonic.

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11. TIMING WAVEFORMS

11.1 Command Input Timing

CLK

RAS

CAS

A0~A12

BS0, 1

Refer to the Command Truth Table

11.2 Timing of the CLK Signals

IH(AC)

IL(AC)

CLK

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11.3 Read Timing (Burst Length = 4)

Notes: The correspondence of LD QS, UDQS to DQ. (W9425G6DH)

LDQS DQ0~7

UDQS DQ8~15

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11.4 Write Timing (Burst Length = 4)

tIS tIH tDSH tDSS tDSStDSH

tWPRES

tDHtDHtDH

tDS tDS tDS

tDQSS tDSH tDSHtDSS tDSS

Postamble

tWPRE

Preamble

tDQSH tDQSHtDQSL tWPST

DA0 DA1 DA2 DA3

tWPRES

tDS tDS

tDQSS

tDSH tDSHtDSS tDSS

Postamble

tWPRE

Preamble

tDQSH tDQSHtDQSL tWPST

tWPRES

tDH

tDS tDS

tDQSS

Postamble

tWPRE

Preamble

tDQSH tDQSHtDQSL tWPST

DA0 DA1 DA2 DA3

tDS

tDH tDH

tCH tCL tCK

DQS

Input

(Data)

LDQS

DQ0~7

UDQS

DQ8~15

x4, x8 device

x16 device

ADD

CMD

CLK

WRIT

Col

DA0 DA1 DA2 DA3

tDH

tDS

DA0 DA1 DA2 DA3

tIS tIH

Note: x16 has two DQSs (UDQS for upper byte and LDQS for lower byte). Even if one of the 2 bytes is not used, both UDQS

and LDQS must be toggled.

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11.5 DM, DATA MASK (W9425G6DH)

WRIT

tDIPW

tDHtDHtDStDS

Masked

CLK

CMD

LDQS

LDM

DQ0~DQ7 D3D1D0

tDIPW

tDHtDHtDStDS

Masked

UDQS

UDM

DQ8~DQ15 D3

CLK

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Publication Release Date:Feb. 12 , 2008

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11.6 Mode Register Set (MRS) Timing

MRS

NEXT CMD

tMRD

CLK

CMD

ADD

A2 A1 A0

A6 A5 A4

BS1 BS0

000

001

010

011

100

101

110

111

001

010

011

100

101

110

111

Burst Le ngth

Sequential Interleaved

Reserved Reserved

Reserved

Sequential

Interleaved

Addressing Mode

CAS Latency

DLL Reset

Yes

MRS or EMRS

Regular MRS cycle

Extended MRS cycle

2.5

A10

A11

A12

BS0

BS1 "0"

"0"

DLL Reset

Reserved

Addressing Mode

* "Reserved" should stay "0" during MRS cycle.

Reserved

Mode Regi ster Set

Extended Mode

CAS Latency

Burst Le ngth

Reserved Reserved

W9425G6DH

Publication Release Date:Feb. 12 , 2008

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11.7 Extend Mode Register Set (EMRS) Timing

EMRS

NEXT CMD

tMRD

CLK

CMD

ADD

BS1 BS0

Enable

Disable

DLL Switch

Output Driver Size

Full Strength

Half Strength

MRS or EMRS

Regular MRS cycle

Extended MRS cycle

A10

A11

A12

BS0

BS1 "0"

"0"

* "Reserved" should stay "0" during EMRS cycle.

"0"

Output Driver

DLL Switch

Reserved

Mode Register Set

Extended Mode

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Publication Release Date:Feb. 12 , 2008

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11.8 Auto-precharge Timing (Read Cycle, CL = 2)

1) TRCD (READA) ≥ TRAS (MIN) – (BL/2) × TCK

Q7Q6Q5Q4Q3Q2Q1Q0

ACT

READA

ACT

Q0 Q1 Q2 Q3

ACTREADAACT

Q0 Q1

ACT

READAACT

tRP

RAS

CMD

DQS

CMD

DQS

CMD

DQS

BL=2

BL=4

BL=8

CLK

Notes: CL=2 shown; same command operation t iming with CL = 2,5 and CL=3

In this case, the internal precharge operation begin after BL/2 cycle from READA command.

Represents the start of internal precharging.

The Read with Auto-precharge command cannot be interrupted by any other command.

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11.9 Auto-precharge Timing (Read cycle, CL = 2), continued

2) tRCD/RAP(min) ≤ tRCD (READA) < tRAS (min) – (BL/2) × tCK

Q7Q6Q5Q4Q3Q2Q1Q0

ACT READA ACT

Q0 Q1 Q2 Q3

ACTREADAACT

Q0 Q1

ACT

READAACT

RAS

CMD

DQS

CMD

DQS

CMD

DQS

BL=2

BL=4

BL=8

CLK

RAP

RCD

RAP

RCD

RAP

RCD

Notes: CL2 shown; same command operation timing with CL = 2 .5, CL=3.

In this case, the internal precharge operation does not begin until after tRAS (min) has command.

Represents the start of internal precharging.

The Read with Auto-precharge command cannot be interrupted by any other command.

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11.10 Auto-precharge Timing (Write Cycle)

WRITA ACT

ACTWRITA

CMD

DQS

CMD

DQS

CMD

DQS

BL=2

BL=4

BL=8

CLK

D0 D1

D0 D1 D2 D3

D0 D1 D2 D3 D4 D5 D6 D7

DAL

The Write with Auto-precharge command cannot be interrupted by any other command.

Represents the start of internal precharging .

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11.11 Read Interrupted by Read (CL = 2, BL = 2, 4, 8)

CMD

ADD

DQS

CLK

ACT READ A READ B READ C READ D READ E

Row

Address COl,Add,A Col,Add,B Col,Add,C Col,Add,D Col,Add,E

QC0QA0 QA1 QB0 QB1

CCD

RCD

11.12 Burst Read Stop (BL = 8)

READ

CMD

DQS

CLK

BST

Q0 Q1 Q2 Q3 Q4 Q5

CAS Latency

CAS Latency = 2

DQS

CAS Latency = 3

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11.13 Read Interrupted by Write & BST (BL = 8)

READ

CMD

DQS

CLK

BST

Q0 Q1 Q2 Q3 Q4 Q5

CAS Latency = 2

WRIT

D0 D1 D2 D3 D4 D5 D6 D7

Burst Read cycle must be terminated by BST Command to avoid I/O conflict.

11.14 Read Interrupted by Precharge (BL = 8)

READ

CMD

DQS

CLK

PRE

Q0 Q1 Q2 Q3 Q4 Q5

CAS Latency

CA S La tency = 2

DQS

CA S La tency = 3

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11.15 Write Interrupted by Write (BL = 2, 4, 8)

CMD

ADD

DQS

CLK

ACT WRIT A WRIT B WRIT C WRIT D WRIT E

Row

Address COl. Add. A Col.Add.B Col. Add. C Col. Add. D Col. Add. E

DC0 DC1 DD0 DD1DA0 DA1 DB0 DB1

CCD

RCD

11.16 Write Interrupted by Read (CL = 2, BL = 8)

WRIT

CMD

DQS

CLK

WTR

DQ D4 D5 D6 D7D0 D1 D2 D3

Data must be

masked by DM

READ

Data masked by READ

command, DQS input ignored.

Q4 Q5 Q6 Q7Q0 Q1 Q2 Q3

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11.17 Write Interrupted by Read (CL = 3, BL = 4)

WRIT

CMD

DQS

CLK

READ

tWTR

DQ Q0 Q1 Q2 Q3

D0 D1 D2 D3

Data must be masked by DM

11.18 Write Interrupted by Precharge (BL = 8)

WRIT

CMD

DQS

CLK

ACT

tWR

DQ D4 D5 D6 D7D0 D1 D2 D3

Data must be

masked by DM

PRE

tRP

Data masked by PRE command,

DQS input ignor ed.

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11.19 2 Bank Interleave Read Operation (CL = 2, BL = 2)

∗ tCK = 100 MHz

CMD

DQS

CLK

Q0a Q1a Q0b Q1b

ACTa/b : Bank Act. CMD of bank a/b

READAa/b : Read with Auto Pre.CMD of bank a/b

APa/b : Auto Pre. of bank a/b

ACTa ACTb READAa ACTaREADAb ACTb

APa APb

RCD(a)

RAS(a)

RP(a)

RAS(b)

RCD(b)

RP(b)

CL(a) CL(b)

Preamble Postamble Preamble Postamble

RRD

RC(a)

RC(b)

RRD

11.20 2 Bank Interleave Read Operation (CL = 2, BL = 4)

CMD

DQS

CLK

DQ Q2a Q3a Q2b Q3b

ACTa/b : Bank Act. CMD of bank a/b

READAa/b : Read with Auto Pr e.CM D of bank a/b

APa/b : Auto Pre. of bank a/b

ACTa READAaACTb READAb ACTa ACTb

APa APb

tRCD(a)tRAS(a) tRP(a)

tRAS(b)

tRCD(b) tRP(b)

CL(a) CL(b)

Preamble Postamble

tRRD

tRC(a)

tRC(b)

tRRD

Q0a Q1a Q0b Q1b

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11.21 4 Bank Interleave Read Operation (CL = 2, BL = 2)

CMD

DQS

CLK

DQ Q0a Q1a Q0b Q1b

ACTa/b/c/d : Bank Act. C M D of bank a/b/c/d

R E A D A a /b/c /d : R e a d with Au to P re .C MD o f b an k a /b /c/d

APa/b/c/d : Auto Pre. of bank a/b/c/d

ACTa ACTb READAaACTc READAbACTd READAcACTa

APa APb

tRCD(a)

tRAS(a) tRP

tRAS(b)

tRCD(b)

CL(a) CL(b)

Preamble Postamble Preamble

tRRD

tRC(a)

tRRD

tRAS(c)

tRAS(d)

tRCD(d)

tRCD(c)

tRRD tRRD

11.22 4 Bank Interleave Read Operation (CL = 2, BL = 4)

CMD

DQS

CLK

AC Ta/b/c/d : B ank Act. C M D of bank a/b/c/d

RE AD Aa/b/c/d : R ead with A uto Pre.CM D of bank a/b/c/d

AP a/b/c/d : A uto Pre. of bank a/b/c/d

ACTa READAaACTb READAbACTc READAcACTd READAdACTa

APa APb

tRCD(a) tRAS(a) tRP(a)

tRAS(b)

tRCD(b)

CL(a) CL(b)

tRRD

tRC(a)

tRRD

tRAS(c)

tRAS(d)

tRCD(d)

tRCD(c)

tRRD tRRD

Q2a Q3a Q2b Q3b

Preamble

Q0a Q1a Q0b Q1bQ0a Q1a

CL(c)

APc

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11.23 Auto Refresh Cycle

CMD

CLK

PREA AREF AREF CMDNOP NOP NOP

RFC

Note: CKE has to be kept “High” level for Auto-Refresh cycle.

11.24 Precharge/Activate Power Down Mode Entry and Exit Timing

CMD

CLK

NOP CMDNOP

Exit

Entry

CMD NOP

tIH tIS tCK tIH tIS

CKE

Precharge/Activate

Note 1,2

Note:

1. If power down occurs when all banks are idle, this mode is referred to as precharge power down.

2. If power down occurs when there is a row active in any bank, this mode is referred to as active power down.

11.25 Input Clock Frequency Change during Precharge Power Down Mode Timing

NOP NOP NOP DLL

RESET NOP NOP CMD

200 clocks

tIS

Frequency Change

Occurs here

Minmum 2 clocks

required before

changing frequency

Stable new clock

before power down exit

CLK

CMD

CKE

tRP

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11.26 Self Refresh Entry and Exit Timing

CMD

CLK

tIH tIS tIH tIS

SELF CMDSELEX NOPNOPPREA

Exit

Entry

CKE

tRP

tXSRD

NOPSELF

tXSNR

SELFX NOP ACT READ NOP

Exit

Entry

Note:

If the clock frequency is changed during self refresh mode, a DLL reset is required upon exit.

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- 52 - Revision A8

12. PACKAGE SPECIFICATION

12.1 TSOP 66 lI – 400 mil

EE1

W9425G6DH

Publication Release Date:Feb. 12 , 2008

- 53 - Revision A8

13. REVISION HISTORY

VERSION DATE PAGE DESCRIPTION

P0 May, 2005 All Preliminary data sheet

10 Modify self refresh and auto refresh description

A0 Aug., 2006

25, 26 Modify tDQSCK and tDQSS parameters

A1 Feb., 2007 4 Modify -75 , tRC=67.5nS

A2 Mar. 06, 2007 43, 44 Modify CL 3 drawing

A3 May 22, 2007 29, 30, 31,

32, 33 Add System AC Characteristics with slew rate and

Overshoot/Undershoot Specification detail describes

A4 Jun. 21, 2007 3, 4, 22, 24,

25, 26, 51 Add -6I/75I grade for Ta= -40 to 85°C and update

with package dimensions

A5 Aug. 16, 2007 4, 5, 23, 25,

26, 27, 28 Add -4 grade (DDR500) for TA = 0 to 70°C

A6 Sep. 11, 2007 26 Modify -4 grade, tIS/tIH = 0.6 nS, tWTR = 2 tCK

5, 26, 27,

Add max. values of tCK in key parameters table,

revise tDAL parameter, tDAL = (tWR/tCK) + (tRP/tCK)

and remove tDSSK parameters in AC Characteristics

21, 50 Revise Precharged/Active Power Down Mode

A7 Nov. 20, 2007

14, 50, 51 Add input clock frequency change during precharge

power down mode/self refresh mode

A8 Feb. 12, 2008 4, 5, 23, 25,

27 Add -6F grade

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components

in systems or equipment intended for surgical implantation, atomic energy control

instruments, airplane or spaceship instruments, transportation instruments, traffic signal

instruments, combustion control instruments, or for other applications intended to support or

sustain life. Further more, Winbond products are not intended for applications wherein failure

of Winbond products could result or lead to a situation wherein personal injury, death or

severe property or environmental damage could occur.

Winbond customers using or selling these products for use in such applications do so at their

own risk and agree to fully indemnify Winbond for any damages resulting from such improper

use or sales.