ADVANCE INFORMATION MX29VW160T/B 16M-BIT [2M x 8-BIT/1M x16-BIT] SIMULTANEOUS READ/WRITE SINGLE 3.0V OPERATION FLASH MEMORY FEATURES * Built-in 128 Bytes/64 Words page buffer in each bank - Work as SRAM for temporary data storage - Fast access to temporary data * Low power dissipation (typical values at 8MHz) - 40mA typical for Read While Write - 20mA typical for Read - 1uA typical for standby * Hardware reset pin (RP) - Reset internal state machine and put the device into standby mode * Hardware write protect pin (WP) - Allows protection of the first two 8K Byte blocks, regardless of their orginal protect status. * Group Protection - Hardware method of locking groups to prevent any program or erase operation within that group - Any group can be locked in-system or via programming equipment - Temporary group unprotect feature allows code change in any previously locked group * Two Memory Banks for Simultaneous Read/Write operations - Host system can program or erase in one bank and simultaneously read from the other bank - Zero latency between simultaneous Read/Write operations - Read-While-Erase/Program * Extended Single-supply voltage range from 2.7V to 3.0V for read, erase and write operations * JEDEC-standard EEPROM commands * Minimum 100,000 write/erase cycles * Fast Access time: 90ns * Optimized block architecture: - Bank A - Eight 8K Byte (4K Word) blocks - Three 64K Byte (32K Word) blocks - Bank B - Twenty-eight 64K Byte (32K Word) blocks * Data polling and toggle bit feature for detection of program or erase cycle completion * Ready/Busy output (RY/BY): Hardware method for detection of program or erase cycle completion * Automatic standby mode: When addresses remain stable,automatically switch themselves to low power mode(1uA Typical) * Auto erase operation - Automatically erases any combination of the blocks or the whole chip - Fast erase time: 20ms typical for single block erase and 50ms typical for chip erase and multi-block erase * Auto page program operation - Automatically programs and verifies data at specified addresses - Internal address and data latches for 128 Bytes (64 Word) per page in each bank - Fast program time: 4ms typical for page program P/N:PM0567 * Erase Suspend/Erase Resume - Suspends or resumes erasing blocks to allow reading and programming in other blocks. - It is not necessary to do erase suspend if reading or programming blocks in the other bank * Low Vcc write inhibit is equal to or less than 1.6V * Compatible with JEDEC-standard pinouts - 48-pin TSOP (I) - 48-ball CSP 1 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B GENERAL DESCRIPTION The MX29VW160T/B is a 16Mbit Flash memory organized as either 2M-byte by 8-bit or 1M-word by 16-bit. To provide simultaneous operation which can read a data while program/erase,the 16Mbits of data is divided into two banks of bank A ( 2M bit) and bank B(14M bit). Bank A is organized by eight 8K-byte blocks and three 64k-byte blocks. Bank B is organized by twenty-eight 64K-byte blocks. To allow for simple in-system operation with very low operation voltage, MX29VW160T/B can be operated with a single 2.7V to 3.0V supply voltage.Manufactured with MXIC's advanced nonvolatile memory technology, the device offers access times of 90ns, and a low 1uA typical standby current. The MX29VW160T/B command set is compatible with the JEDEC single-power-supply flash standard. Commands are written to the command register using standard micro-processor write timings. MXIC's flash memory augments EPROM functionality with an internal state machine which controls the erase and program circuitry. The device RY/BY pin provides a convenient way to monitor when a program or erase cycle is complete. A combined feature of Reset Pin (RP), a hardware lockout bit, and software command sequences provide complete data protection. First, software data protection protects the device from inadvertent program or erase. Two "unlock" write cycles must be presented to the device before the program or erase command can be accepted by the device. For hardware data protection, the RP pin provide protection against unwanted command writes due to invalid system bus condition that may occur during system reset and power up/down sequence. Finally, with a hardware lockout bit feature, the device provides complete core security for the kernal code required for system initialization. MXIC's flash technology reliably stores memory contents after 100,000 erase and program cycles. The MXIC's cell is designed to optimize the erase and program mechanism. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produce reliable cycling. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to Vcc+1V. Programming the MX29VW160T/B is performed on a page basis; 128 bytes of data are loaded into the device and then programmed simultaneously. The typical Page Program time is 4ms. The device can also be reprogrammed in standard EPROM programmers. Reading data out of the device is similar to reading from an EPROM or other flash. Erase is accomplished by executing the Erase command sequence. This will invoke the Auto Erase algorithm which is an internal algorithm that automatically times the erase pulse widths and verifies proper cell margin. This device features both chip erase and block erase. Each block can be erased and programmed without affecting other blocks. Using MXIC's advance design technology, no preprogram is required (internally or externally). As a result, the whole chip can be typically erased and verified in as fast as 50ms. P/N:PM0567 2 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B PINOUT PIN DESCRIPTION 48-PIN TSOP(I) 12mm x 20mm A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE RP NC WP RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 MX29VW160T/B A16 BYTE GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 Vcc Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE GND CE A0 SYMBOL A0 ~ A19 Q0 ~ Q14 Q15/A-1 PIN NAME Address Input Data Input/ Output Q15 (word mode)/LSB addr. (byte mode) Chip Enable Input Output Enable Input Write Enable Write Protect Reset/Deep Power-down Ready/Busy Output Word/Byte Selection Input Power Supply Pin (2.25V ~ 3.0V) Ground Pin No Internal Connection Pin CE OE WE WP RP RY/BY BYTE Vcc GND NC 48-Ball CSP 8mm x 13mm x 1.2mm(Ball Pitch = 0.8 mm), Top View, Balls Facing Up A B C D E F G H 1 A3 A4 A2 A1 A0 CE OE GND 2 A7 A17 A6 A5 Q0 Q8 Q9 Q1 3 RY/BY WP A18 NC Q2 Q10 Q11 Q3 4 WE RP NC A19 Q5 Q12 Vcc Q4 5 A9 A8 A10 A11 Q7 Q14 Q13 Q6 6 A13 A12 A14 A15 A16 BYTE Q15/A-1 GND P/N:PM0567 3 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B Table 1 Block Architecture (Word Mode Addr. :A0~A19, BYTE Mode Addr.:A-1~A19) Byte Mode (A-1 TO A19) 1FFFFF~1FE000 1FDFFF~1FC000 1FBFFF~1FA000 1F9FFF~1F8000 1F7FFF~1F6000 1F5FFF~1F4000 1F3FFF~1F2000 1F1FFF~1F0000 1EFFFF~1E0000 1DFFFF~1D0000 1CFFFF~1C0000 1BFFFF~1B0000 1AFFFF~1A0000 19FFFF~190000 18FFFF~180000 17FFFF~170000 16FFFF~160000 15FFFF~150000 14FFFF~140000 13FFFF~130000 12FFFF~120000 11FFFF~110000 10FFFF~100000 0FFFFF~0F0000 0EFFFF~0E0000 0DFFFF~0D0000 0CFFFF~0C0000 0BFFFF~0B0000 0AFFFF~0A0000 09FFFF~090000 08FFFF~080000 07FFFF~070000 06FFFF~060000 05FFFF~050000 04FFFF~040000 03FFFF~030000 02FFFF~020000 01FFFF~010000 00FFFF~000000 Word Mode (A0 TO A19) FFFFF~FF000 FEFFF~FE000 FDFFF~FD000 FCFFF~FC000 FBFFF~FB000 FAFFF~FA000 F9FFF~F9000 F8FFF~F8000 F7FFF~F0000 EFFFF~E8000 E7FFF~E0000 DFFFF~D8000 D7FFF~D0000 CFFFF~C8000 C7FFF~C0000 BFFFF~B8000 B7FFF~B0000 AFFFF~A8000 A7FFF~A0000 9FFFF~98000 97FFF~90000 8FFFF~88000 87FFF~80000 7FFFF~78000 77FFF~70000 6FFFF~68000 67FFF~60000 5FFFF~58000 57FFF~50000 4FFFF~48000 47FFF~40000 3FFFF~38000 37FFF~30000 2FFFF~28000 27FFF~20000 1FFFF~18000 17FFF~10000 0FFFF~08000 07FFF~00000 8K-Byte Block 8K-Byte Block 8K-Byte Block 8K-Byte Block 8K-Byte Block 8K-Byte Block 8K-Byte Block 8K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block SA01 SA02 SA03 SA04 SA05 SA06 SA07 SA08 SA09 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 GA01 GA02 GA03 GA04 GA05 GA06 GA07 GA08 GA09 GA09 GA09 GA10 GA10 GA10 GA10 GA11 GA11 GA11 GA11 GA12 GA12 GA12 GA12 GA13 GA13 GA13 GA13 GA14 GA14 GA14 GA14 GA15 GA15 GA15 GA15 GA16 GA16 GA16 GA17 BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK B BANK B BANK B BANK B BANK B BANK B BANK B BANK B BANK B BANK B BANK B BANK B BANK B BANK B BANK B BANK B BANK B BANK B BANK B BANK B BANK B BANK B BANK B BANK B BANK B BANK B BANK B BANK B MX29VW160T P/N:PM0567 4 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B Byte Mode (A-1 TO A19) 1FFFFF~1F0000 1EFFFF~1E0000 1DFFFF~1D0000 1CFFFF~1C0000 1BFFFF~1B0000 1AFFFF~1A0000 19FFFF~190000 18FFFF~180000 17FFFF~170000 16FFFF~160000 15FFFF~150000 14FFFF~140000 13FFFF~130000 12FFFF~120000 11FFFF~110000 10FFFF~100000 0FFFFF~0F0000 0EFFFF~0E0000 0DFFFF~0D0000 0CFFFF~0C0000 0BFFFF~0B0000 0AFFFF~0A0000 09FFFF~090000 08FFFF~080000 07FFFF~070000 06FFFF~060000 05FFFF~050000 04FFFF~040000 03FFFF~030000 02FFFF~020000 01FFFF~010000 00FFFF~00E000 00DFFF~00C000 00BFFF~00A000 009FFF~008000 007FFF~006000 005FFF~004000 003FFF~002000 001FFF ~000000 Word Mode (A0 TO A19) FFFFF~F8000 F7FFF~F0000 EFFFF~E8000 E7FFF~E0000 DFFFF~D8000 D7FFF~D0000 CFFFF~C8000 C7FFF~C0000 BFFFF~B8000 B7FFF~B0000 AFFFF~A8000 A7FFF~A0000 9FFFF~98000 97FFF~90000 8FFFF~88000 87FFF~80000 7FFFF~78000 77FFF~70000 6FFFF~68000 67FFF~60000 5FFFF~58000 57FFF~50000 4FFFF~48000 47FFF~40000 3FFFF~38000 37FFF~30000 2FFFF~28000 27FFF~20000 1FFFF~18000 17FFF~10000 0FFFF~08000 07FFF~07000 06FFF~06000 05FFF~05000 04FFF~04000 03FFF~03000 02FFF~02000 01FFF~01000 00FFF~00000 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 64K-Byte Block 8K-Byte Block 8K-Byte Block 8K-Byte Block 8K-Byte Block 8K-Byte Block 8K-Byte Block 8K-Byte Block 8K-Byte Block SA01 SA02 SA03 SA04 SA05 SA06 SA07 SA08 SA09 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 GA01 GA02 GA02 GA02 GA03 GA03 GA03 GA03 GA04 GA04 GA04 GA04 GA05 GA05 GA05 GA05 GA06 GA06 GA06 GA06 GA07 GA07 GA07 GA07 GA08 GA08 GA08 GA08 GA09 GA09 GA09 GA10 GA11 GA12 GA13 GA14 GA15 GA16 GA17 BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK A BANK B BANK B BANK B BANK B BANK B BANK B BANK B BANK B BANK B BANK B BANK B MX29VW160B P/N:PM0567 5 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B Block Diagram CE OE WE WP RP Control Input Logic RY/BY Write State Machine (WSM) X-Decoder P/N:PM0567 X-Decoder WSM Y-Decoder MUX Program/ Erase high A-1 Voltage Generator Bank A 4KW/8KB x 8 32KW/64KB x 3 Command Data Latch Page Buffer Y-Pass Gate Sense Amplifier MUX I/O Buffer A0~A19 Address Latch & Buffer Y-Decoder MUX Command Interface Register (CIR) Q0~Q15/A-1 WSM Y-Pass Gate Page Buffer Bank B (32KW/64KB x28) 6 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B BUS OPERATIONS Flash memory reads, erases and writes in-system via the local CPU. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. These bus operations are summarized below. Table 2.1 MX29VW160T/B Bus Operations for Byte-Wide Mode (Byte = VIL) MODE CE OE WE RP WP A0 A1 A6 A9 Q0~Q7 Q8~Q14 Q15/A-1 Notes Read L L H H L/H A0 A1 A6 A9 DOUT HighZ A-1 1,2,7,9 Output Disable L H H H X X X X X HighZ HighZ X 1,6,7 Standby H X X H X X X X X HighZ HighZ X 1,6,7 Hardware Standby X X X L X X X X X HighZ HighZ X 1,3 Manufacturer ID L L H H L/H L L X VID C2H HighZ X 4,8 Device ID L L H H L/H H L X VID 67/68H HighZ X 4,8 L H X VID C2H HighZ X DIN High Z A-1 Block Protect Verify * L L H H H Write L H L H L/H/VID A0 A1 A6 A9 1,5,6,10 Table 2.2 MX29VW160T/B Bus Operations for Word-Wide Mode (Byte = VIH) MODE CE OE WE RP WP A0 A1 A6 A9 Q0~Q7 Q8~Q14 Q15/A-1 Notes Read L L H H L/H A0 A1 A6 A9 DOUT DOUT DOUT 1,2,7 Output Disable L H H H X X X X X HighZ HighZ HighZ 1,6,7 Standby H X X H X X X X X HighZ HighZ HighZ 1,6,7 Hardware Standby X X X L X X X X X HighZ HighZ HighZ 1,3 Manufacturer ID L L H H L/H L L X VID C2H 00H 0B 4,8 Device ID L L H H L/H H L X VID 67/68H 00H 0B 4,8 Block Protect Verify * L L H H H L H X VID C2H 00H 0B Write L H L H L/H/VID A0 DIN DIN DIN A1 A6 A9 1,5,6,10 * : Valid Sector Address must be provided when doing block protect Verify mode. Legend : L = Logic Low = VIL, H = Logic High = VIH ,X = VIL or VIH, VID = 8.5~10.5V ,Refer to DC Characteristics for Voltage loads. Notes: 1. X can be VIH or VIL for address or control pins except for RY/BY which is either VOL or VOH. 2. RY/BY output is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-down mode, RY/BY will be at VOH, if it is tied to Vcc through a 1K ~ 100K resistor. When the RY/BY at VOH is independent of OE while a WSM operation is in progress. 3. RP< GND+0.2V ensures the lowest consumption current. 4. A0 and A1 at VIL provide manufacturer ID code. A0 at VIH and A1 at VIL provide ID code. A0 at VIL, A1 at VIH and with appropriate block address provide Block Protect Code.(Refer to Table 4) 5.Command or different Erase operations, Data program operations or Group protect operation can only be successfully completed through proper command sequence. 6. RY/BY goes to VOH when the WSM is not busy or in erase suspend mode. 7.RY/BY may be at VOL while the WSM is busy performing various operations. 8.VID = 8.5V-10.5V 9. Q15/A-1 = VIL, Q0-Q7 = D0-D7 out. Q15/A-1 = VIH, Q0-Q7 = D8-D15 out. 10. When WP=VIL, the two outer most 8K-Byte blocks be protected. When WP=VIH, all blocks remain orginal protect status. When WP=VID, all blocks be unprotected. P/N:PM0567 7 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B COMMAND DEFINITIONS Table 3 Command Definitions Bus Cycles First Addr Read Reset Manufacturer ID Word Byte Device ID Word Byte Block Protect Word Verify Byte Group Protect Word Byte Chip Unprotect Word Data Addr 1 RA RD 1 XXXH F0H 4 555H AAH AAAH 4 555H AAH AAAH 6 555H AAAH 6 555H 555H AAH 90H Data Fifth Sixth Addr Data Addr Data X00H 00C2H X00H C2H 90H AAAH X01H 0067H/0068H* X02H 67H/68H* 90H AAAH 2AAH 55H 555H Fourth Data Addr AAAH 2AAH 55H 555H 555H AAH Data Addr 2AAH 55H 555H 555H AAH Third 2AAH 55H 555H 555H AAAH 4 555H Second X02H XX01H/XX00H* X04H 01H/00H* 60H AAAH 555H AAH 2AAH 55H GA AAAH 555H 2AAH 55H 555H 60H 555H AAH 2AAH 55H 555H 40H 555H AAAH 555H Byte AAAH Word 555H AAH 2AAH 55H 555H A0H PA Single Block Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA Erase Byte 555H AAAH 555H Multi Block Word 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA Erase Byte 555H AAAH 555H Page Program Chip Erase Word Byte AAAH 6 555H AAH AAAH 6 555H AAH AAAH 1 XXXH B0H Erase Resume 1 XXXH 30H AAAH AAAH AAAH 2AAH 55H 555H 555H Erase Suspend 20H AAAH 80H 555H AAAH AAAH PD AAH 20H 30H 2AAH 55H 555H 10H 555H AAAH Notes: 1. *00H Represents unprotect block & *01H represents protect block in the 4th Bus cycle data of "Block Protect Verify". 2. Address bit A11-A19 = X = "Don't care" for all address commands except for Program Address (PA) and Block Address (SA). 555H and 2AAH address command codes stand for Hex number starting from A0 to A10 in word mode and A-1 to A10 in byte mode. 3.Bus operations are defined in Table 2. 4. RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Address are located on the falling edge of the WE pulse. SA = Address of the block to be erase. The combination of A12-A19 will select any block(Refer to Table 1). GA = Group address to be protect. The combination of A12-A19 will select any group. 5.RD = Data read from location RA during read operation. PD = Data to be Programmed at location PA. Data is latched on the rising edge of WE. 6.Only Q0-Q7 command data is taken, Q8 to Q15 = Don't care. *Refer to Table 4. P/N:PM0567 8 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B FUNCTIONAL DESCRIPTION SIMULTANEOUS OPERATION The MX29VW160T/B provides the simultaneous read/write function. The device is capable of reading data from one bank and simultaneously erasing (so as, programming, erase-suspend reading, and erase suspend programming) data from the other bank. The bank selection can be selected by bank address (A17 to A19) with zero latency. The MX29VW160T/B contains two data banks which are bank A (8K-Byte x 8, 64K-Byte x 3) and Bank B (64K-Byte x 28). Following table describes the detail simultaneous operation. Simultaneous Operation Table Bank-B standby Read Single Multiple block Multiple block Chip Erase Erase Page Group Silicon mode block erase erase erase suspend resume program protect/ ID Bank-A erase (only 1 bank) ( 2 banks) unprotect read Standby O Read mode X O O X O O O X Single block erase O X X Multiple block erase O X (only 1 bank) Multiple block erase X O O O X X ( 2 banks) Chip erase O Erase suspend O O X O Erase resume O O X Page program O X X X X Group protect/ X X X X X X unprotect Silicon ID read O - Legend : "o"=Okay,"X"= Not allow, "-"= Not available. P/N:PM0567 9 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B READ ARRAY MODE READ ID MODE The MX29VW160T/B must satisfy two control functions to obtain data output. CE is the power control and should be used for a device selection. OE is the output control and should be used to gate data to the output pins if a device is selected.(Figure 11) Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer and device codes must be accessible while the device resides in the target system. PROM programmers typically access signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not generally desired system design practice. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from state the falling edge of CE to valid data at the output pins. (Assuming the addresses have been stable for at least tACC - tCE time.) When reading out a data without changing addresses after power-up, it is necessary to input hardware reset or to change CE pin from "H" to "L". READ/RESET COMMAND The Read or Reset operation is initiated by writing the read/reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enable for reads until the command register contents are altered. The MX29VW160T/B contains a Silicon-ID-Read Operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Read Silicon ID command sequence into the command register. Following the command write, a read cycle with A1=VIL, A0=VIL retrieves the manufacturer code of C2H. A read cycle with A1=VIL, A0=VIH returns the device code of 67H for MX29VW160T, 68H for MX29VW160B. The Silicon-ID-Read Operation also covers the block protection verification. A read cycle with A1=VIH, A0= "Don't care" returns data of 00H for"unprotected block" and 01H for "protected block". The device will automatically power-up in the read/reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms (Figure 12) for the specific timing parameters. P/N:PM0567 10 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B Table 4.1 Read ID Mode Table TYPE Manufacturer ID MX29VW160T Device ID MX29VW160B Byte Word Byte Word Block Protection Verify A12 to A19 X X A6 X X A1 L L A0 L H X X L H Block Address X H X A-1 X X X X X X Code (HEX) C2H 67H 0067H 68H 0068H 01H/00H* *01H for "protected block" addresses and 00H for "unprotected block" addresses. Table 4.2 Extended Read ID Mode Table TYPE Code (HEX) Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Manufacturer's ID C2H 0 1 1 0 0 0 0 1 0 A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 1 1 0 0 1 1 1 0 0 0 1 1 0 0 1 1 1 A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 01H/00H** A-1/0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1/0 MX29VW160T Byte 67H Device ID Word 0067H MX29VW160B Byte 68H Word 0068H Block Protection Verify A-1/0 0 0 0 0 0 0 0 0 0 0 0 0 Notes: * Manufacture Code = C2 H, Device Code = 67H/68H when BYTE = VIL Manufacture Code = 00C2H,Device Code =0067H/0068H when BYTE = VIH ** Outputs 01H at protected block address ,00H at unprotected block address. P/N:PM0567 11 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B PROGRAM MODE PAGE PROGRAM The MX29VW160T/B is page programmable with one 128-Byte/ 64-Word page buffer in each bank. To initiate Page program mode, a three-cycle command sequence is required. There are two "unlock" write cycles. These are followed by writing the page program command A0H. Any attempt to write to the device without the three-cycle command sequence will not start the internal Write State Machine (WSM), no data will be written to the device. After three-cycle command sequence is given, a Byte/ Word load is performed by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Maximum of 128-Byte/ 64-Word of data may be loaded into each page. Data loading activity is terminated by issuing same address load twice. The status of program cycle can be determined by checking the Q7 (Data Polling), Q6 (Toggle Bit), or RY/ BY. The automatic programming operation is completed when Q6 stops toggling (See Table 5 of Hardware Sequence Flags.) WRITE OPERATION STATUS BYTE-WIDE LOAD/WORD-WIDE LOAD Byte (Word) loads are used to enter the 128 bytes (64 words) of a page to be programmed or the software codes for data protection. A byte load (word load) is performed by applying a low pulse on the WE or CE input with CE or WE low respectively, and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Either byte-wide load or word-wide load is determined (Byte = VIL or VIH is latched) on the falling edge of the WE (or CE) during the 3rd command write cycle. AUTOMATIC PROGRAM ALGORITHM Any page to be programmed should have the page in the erased state first, i.e. performing block erase is suggested before page programming can be performed. The device is programmed on a page basis. If a byte of data within a page is to be changed, data for the entire page must be loaded into the device. Any byte that is not loaded during the programming of its page will be still in the erased state (i.e. FFH). Once the bytes of the page are loaded into the device, they are simultaneously P/N:PM0567 programmed during the internal programming period. After the first data byte has been loaded into the device, successive bytes are entered in the same manner. A6 to A19 specify the page address, i.e., the device is pagealigned on 128-byte boundary. The page addresses must be valid (Page Address A6-A19 is latched at the 4th bus write-cycle)during each high to low transition of WE or CE. A-1 to A5 specify the byte address during the page. The byte may be loaded in any order; sequential loading is not required. The load period will also end if the same address is consecutively loaded twice. For the last two same address, the first address and data will be treated as normal data to be programmed. The second one must keep the same address and data as the first one. 12 Detailed in Table 5 are all the status flags that can determine the status of the bank for the current mode operation. The read operation from the bank where is not operating Automatic algorithm returns a data of memory cell. These bits offer a method for determining whether a Automatic Algorithm is completed properly. The information on Q2 is address sensitive. This means that if an address from an erasing block is consecutively read, then the Q2 bit will toggle. However, Q2 will not toggle if an address from a non-erasing block is consecutively read. This allows the user to determine which blocks are erasing and which are not. The status flag is not output from bank (non-busy bank) not executing Automatic Algorithm. For example, there is bank (busy bank) which is now executing Automatic Algorithm. When the read sequence is (a)"busy bank" (b)"non-busy bank" and (c )"busy bank" the Q6 is toggling in the case (a) and (c ). In case of (b), the data of memory cell is output. In the erase-suspend read mode with the same read sequence, Q6 will not be toggled in the (a), and (c ). In the erase suspend read mode, Q2 is toggled in the (a) and (c ). In case of (b), the data of memory cell is output. REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B Table 5. Hardware Sequence Flags Table Status Automatic Program Algorithm Automatic Erase Algorithm Erase Erase Suspend Read In Progress Suspend (Erase-Suspend Block) Mode Erase Suspend Read (Non-Erase-Suspend Block) Erase Suspend Program (Non-Erase-Suspend Block) Automatic Program Algorithm Exceeded Automatic Erase Algorithm Time Erase Erase Suspend Program Limits Suspend (Non-Erase-Suspend Block) Mode Q7 Q7 0 1 Q6 Toggle Toggle No Toggle Q5 0 0 0 Q3 N/A 1 N/A Q2 No Toggle Toggle* Toggle RY/BY 0 0 1 Data Data Data Data Data 1 Q7 Toggle 0 N/A N/A 0 Q7 0 Q7 Toggle Toggle Toggle 1 1 1 0 1 0 1 N/A N/A 0 0 0 *. Successive reads from the erasing block will cause Q2 to toggle. Reading from non-erase block address will indicate logic "1" at the Q2 bit. P/N:PM0567 13 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B ERASE MODE ERASE SUSPEND AND RESUME The Erase Suspend command ,B0H allows the user to interrupt a Block Erase operation and then perform data reads from or program to a block not being erased. .This command is applicable ONLY during the Block Erase operation. The Erase Suspend command will be ignored if written during the Chip Erase operation or Auto Program Algorithm. AUTOMATIC CHIP ERASE The MX29VW160T/B does not require pre-program operation prior to erase operation. Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command (80H). Two more "unlock" write cycles are then followed by the Chip Erase command (10H). Writing the Erase Suspend command (B0H) during the multiple block erase operation (before issue same address twice to terminate the block address loading and to start the erase operation) results immediate termination of the address loading and suspension of the erase operation. The system can determine the status of the erase operation by using Q7 (Data Polling), Q6 (Toggle Bit), or RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command sequence and terminates when the data on Q7 is (See Write Operation Status section.) at which time the device returns to read the mode. Writing the Erase Resume command (30H) resumes the erase operation. AUTOMATIC BLOCK ERASE The MX29VW160T/B does not require pre-program operation prior to erase operation. Block erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command (80H). Two more "unlock" write cycles are then followed by the Block Erase command (20H for single-block erase, 30H for multi-block erase). The system is not required to provide any controls or timings during these operations. When erasing a block or blocks the remaining un-selected blocks are not affected. The block address is latched on the falling edge of CE or WE whichever happens later, while the command (data) is latched on the rising edge of CE or WE whichever happens first.After issue same address (A12-A19) twice ,the device will stop block address loading and start erase operation when at multi-block erase mode. Before issued the same address twice to the device, any command other than Erase Suspend (B0H) or multi block Erase (30H) will reset the device to read mode and ignore the previous command string. The system can determine the status of the erase operation by using Q7 (Data Polling), Q6 (Toggle Bit), or RY/BY. P/N:PM0567 14 When the Erase Suspend command is written during the Block Erase operation, the device will take a maximum of 300us to suspend the erase operation. When the devices have entered the erase suspended mode, the RY/BY output pin will be at HighZ . The user must use the Q6 (or RY/BY pin) to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. To resume the operation of Block Erase, the Resume command (30H) should be written . Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing. STANDBY MODE MX29VW160T/B can be set into Standby mode with two different approaches. One is using both CE and RP pins and the other one is using RP pin only. When using both pins of CE and RP, a CMOS Standby mode is achieved with both pins held at Vcc 0.3V. Under this condition, the current consumed is less than 1uA (typ.). During Auto Algorithm operation, Vcc active current (Icc2) is required even CE = "H".The device can be read with standard access time (tCE) from either of these standby modes. REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B When using only RP, a CMOS standby mode is achieved with RP input held at Vss 0.3V Under this condition the current is consumed less than 1uA (typ.). Once the RP pin is taken high,the device is back to active without recovery delay. In the standby mode the outputs are in the high impedance state, independent of the OE input. AUTOMATIC STANDBY MODE MX29VW160T/B is capable to provide the Automatic Standby Mode to restrain power consumption during read-out of data. This mode can be used effectively with an application requested low power consumption such as handy terminals. To active this mode, MX29VW160T/B automatically switch themselves to low power mode when MX29VW160T/B addresses remain stable during access time of 250ns. It is not necessary to control CE, WE, and OE on the mode. Under the mode, the current consumed is typically 1uA (CMOS level). During Simultaneous operation, Vcc active current (Icc2) is required.Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed, the mode is canceled automatically and MX29VW160T/B read-out the data for changed addresses. OUTPUT DISABLE With the OE input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins to be in a high impedance state. DATA PROTECTION The MX29VW160T/B is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the internal state machine in the Read Array mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. TEMPORARY CHIP UNPROTECT This feature allows temoprary unprotection of previously protected group to change data in-system. The Temporary Chip Unprotect mode is activated by setting the RP pin to VID(8.5V-10.5V). During this mode, formerly protected groups can be programmed or erased as un-protected group. Once VID is remove from the RP pin,all the previously protected group are protected again.Figure 1 shows the algorithm, for this feature. GROUP PROTECTION To activate this mode,a six-bus cycle operation is required. there are two "unlock" write cycle. There are followed by writing the setup command.Two more "unlock" write cycles are then followed by the lock group command-20H. Group address(A12~A19) is latched on the falling edge of CE or WE of the sixth cycle of the command sequence. The automatic Lock operation begins on the rising edge of the last WE pulse in the command sequence and terminates when the Q6 stops toggling(or RY/BY =1) at which time the device stays at the read array mode. The devcie remains enabled for read array mode until the CIR contents are altered by a valid command sequence (Refer to the table 3 ). CHIP UNPROTECT It is also possible to unprotect all chip,same as the first five write command cycle in activating chip protection mode followed by the unprotect group command -40H, the automatic unprotect operation begins on the rising edge of the last WE pulse in the command sequence and terminates when the Q6 stops toggling (or RY/BY =1) at with time the device stays at the read array mode.(Refer to table 3 ).Note that all chip are unprotected after chip unprotection completed. The device remains enable for read array mode until the CIR content are altered by a valid command sequence. The device also incorporates several features to prevent inadvertent write cycles resulting from Vcc power-up and power-down transitions or system noise. P/N:PM0567 15 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B RP vs WP Truth Table RP VIL VIH VID WP VIL Hardware Standby The two outer most 8K-Byte be protected, all other blocks remains at original protect The two outer most 8K-Byte blocks be protected, all other blocks be unprotected. status. VIH Hardware Standby All blocks remain at origined protect status. All blocks be unprotected. VID Hardware Standby All blocks be unprotected. All blocks be unprotected. VERIFY BLOCK PROTECT To verify Protect status of the block,operation is initiated by writing Silicon ID read command into the command register. Following the command write ,a read cycle from address XXX2H(A1=VIH) and Group Address (A15~A19) returns data of 00H for " unprotected block". A read cycle from XXX2H(A1=VIH) and group address (A15~A19) returns data of 01H for "protected block". Figure 1 Temporary Chip Unprotect Operation Start RP = VID (Note 1) Perform Erase or Program Operation Operation Completed RP= VIH Temporary Chip Unprotect Completed(Note 2) Note : P/N:PM0567 1. All protected groups are temporary unprotected. VID=8.5V~10.5V 2. All previously protected groups are protected again. 16 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B Figure 2 Group Protection Algorithm (Word Mode) Start PLSCNT = 0 Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 60H Address 555H Write Data AAH Address 555H Increment PLSCNT, To Protect Group Again Write Data 55H Address 2AAH Write Data 20H Group Address Read RY/BY RY/BY = 1? No No Yes Yes PLSCNT =32 ? Group Protect Operation Terminated Device Failed No Write Silicon ID Read Command & Read Data with A1=VIH, A15-A19=Group Address Data = 01H ? Yes * Group Address : A15~A19 Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 60H Address 555H Write Data AAH Address 555H Confirm Group Protection Status Write Data 55H Address 2AAH Write Data 20H Block Address Read RY/BY RY/BY = 1? No Yes Group Protected,Operation Done,Device Stays at Read Array Mode P/N:PM0567 17 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B Figure 3 Chip Unprotection Algorithm (Word Mode) Start PLSCNT = 0 Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 60H Address 555H Write Data AAH Address 555H Increment PLSCNT, To Unprotect Chip Again Write Data 55H Address 2AAH Write Data 40H Address 555H Read RY/BY RY/BY = 1? No No Yes Yes PLSCNT = 32? Unprotect Chip Operation Terminated Device Failed No Write Silicon ID Read Command & Read Data with A1=VIH,A12~A19 = Group Address Read Data for all Chip For all Chip Data = 00H ? Yes Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 60H Address 555H Confirm Chip Unprotection Status Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 40H Address 555H Read RY/BY RY/BY = 1? No Yes Note : *All chip are unprotected after chip unprotection completed. P/N:PM0567 18 Chip Unprotected,Operation Done,Device Stays at Read Array Mode REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B WRITE PULSE "GLITCH" PROTECTION RY/BY: Ready/Busy Noise pulses of less than 5ns (typ.) on CE or WE will not initiate a write cycle. The RY/BY is a dedicated, open-drain output pin that indicates whether an Automatic Erase/Program algorithm is in progress or complete. The RY/BY status is valid after the rising edge of the final WE pulse in the command sequence. Since RY/BY is an open-drain output, several RY/BY pins can be tied together in parallel with a pull-up resistor to Vcc. LOGIC INHIBIT Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE must be a logical "0" while OE is a logical "1". POWER-UP SEQUENCE The MX29VW160T/B powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command sequences. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 5 shows the outputs for RY/BY. POWER SUPPLY DECOUPLING Q6: Toggle Bit I In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected between its Vcc and GND. Toggle Bit I on Q6 indicates whether an Automatic Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE pulse in the command sequence (prior to the program or erase operation), and during the block erase time-out period. Q7: Data Polling The MX29VW160T/B features Data Polling as a method to indicate to the host system that the Automatic Program or Erase algorithms are either in progress or completed. During an Automatic Program or Erase algorithm operation, successive read cycles to any address cause Q6 to toggle. The system may use either OE or CE to control the read cycles. When the operation is complete, Q6 stops toggling. While the Automatic Programming algorithm is in operation, an attempt to read the device will produce the complement data of the data last written to Q7. Upon completion of the Automatic Program algorithm an attempt to read the device will produce the true data last written to Q7. The Data Polling feature is valid after terminating load operation for automatic program. While the Automatic Erase algorithm is in operation, Q7 will read "0" until the erase operation is competed. Upon completion of the erase operation, the data on Q7 will read "1" The Data Polling feature is valid after the rising edge of the sixth WE pulse of six write pulse sequences for automatic chip/block erase. The Data Polling feature is active during Automatic Program/Erase algorithm (see section Q3 Block Erase Status Bit ). P/N:PM0567 19 After an erase command sequence is written, if all blocks selected for erasing are protected, Q6 toggles and returns to reading array data. If not all selected blocks are protected, the Automatic Erase algorithm erases the un-protected blocks, and ignores the selected blocks that are protected. The system can use Q6 and Q2 together to determine whether a block is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling. When the device enters the Erase Suspend mode, Q6 stops toggling. However, the system must also use Q2 to determine which blocks are erasing or erase-suspended. Alternatively, the system can use Q7. REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B Q6 also toggles during the erase-suspend-program mode, and stops toggling once the Automatic Program algorithm is complete. The remaining scenario is that system initially determines that the toggle bit is toggling and Q5 has not gone high. The system may continue to monitor the toggle bit and Q5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. Table 5 shows the outputs for Toggle Bit I on Q6. Q5: Exceeded Timing Limits Q2: Toggle Bit II Q5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions Q5 will produce a "1" This is a time-out condition which indicates that the program or erase cycle was not successfully completed. Data Polling and Toggle Bit are the only operating functions of the device under this condition. If a program address falls within a protected block, Q6 toggles for approximately 1us after the program command sequence is written, then returns to reading array data. The Toggle Bit II on Q2, when used with Q6, indicates whether a particular block is actively erasing (that is the Automatic Erase algorithm is in process), or whether that block is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE pulse in the command sequence. Q2 toggles when the system reads at addresses within those blocks that have been selected for erasure. (The system may use either OE or CE to control the read cycles.) But Q2 cannot distinguish whether the block is actively erasing or is erase-suspended. Q6, by comparison, indicates whether the device is actively erasing or is erase-suspended, but cannot distinguish which blocks are selected for erasure. Thus, both status bits are required for blocks and mode information. Refer to table 5 to compare outputs for Q2 and Q6. If this time-out condition occurs during block erase operation, it is specifiesd that a particular block is bad and it may not be reused. However, other blocks are still functional and may be used for program or erase operation. The device must be reset to use other blocks. Write the Reset command sequence to the device, and then execute program or erase command sequence. This allows the system to continue to use the other active blocks in the device. Reading Toggle Bits Q6/Q2 If this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of blocks are bad. Whenever the system initially begins reading toggle bit status, it must read Q7~Q0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on Q7~Q0 on the following read cycle. The Q5 time-out condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and never completes the Automatic algorithm operation. Hence, the system never reads a valid data on Q7 bit and Q6 never stops toggling. Once the device has exceeded timing limits, the Q5 bit will indicate a logical "1" Please note that this is not a device failure condition since the device was incorrectly used. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of Q5 is high (see the section on Q5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as Q5 went high. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. P/N:PM0567 20 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B Q3: Block Erase Status Bit The MX29VW160T/B provides three difference erase operation :(1) chip erase. (2) single block erase,and (3) mutil-block erase. The device will automatically start erase operation after erase command completed when doing (1) and (2). For the case of (3), toggling the same address (A12 to A19 ) twice is necessary to terminate the block address loading and start the erase operation . No extra time-out is needed to terminate the block address loading or complete the erase operation . During the period of issuing the erase command,Q3 will remain low until the erase operation starts.Data polling and Toggle Bit are valid after the initial block erase command sequence. If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, Q3 may be used to determine if the block address loading window is still open. If Q3 is high (logical "1" the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If Q3 is low (logical "0", the device will be accept additional block erase command. To insure the command has been accepted, the system software should check the status of Q3 prior to and following each subsequent block erase command. If Q3 were high on the second status check, the command may not have been accepted.Note that during the block address loading period,any command other than Multiple Block Erase (30H) or Erase Suspend (B0H) will reset the device to read array mode. WP : Write Protect Pin When system provides VIL to the WP pin, the two outer most 8K-Byte blocks (SA01 and SA02 of MX29VW160T or SA38 and SA39 of MX29VW160B) will be protected from program and erase operations. When WP=VIH, the two outer most 8K-Byte blocks and all other blocks will remain at (or back to) their original protect status. When WP=VID, the whole device will be unprotected. P/N:PM0567 21 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B Figure 4 Data Polling Algorithm Start Read (Q0 to Q7) Yes Q7 = Data ? No No Q5 = 1 ? Yes Read (Q0 to Q7) Yes Q7 = Data ? No exceeded timing limits Pass NOTE : Q7 is rechecked even if Q5 = "1" because Q7 may change simultaneously with Q5. P/N:PM0567 22 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B Figure 5 Toggle Bit Algorithm START Read Q7-Q0 Read Q7-Q0 Q6 Toggle Bit = Toggle ? NO YES NO Q5= 1? YES Read Q7-Q0 Twice NO Toggle bit = Toggle? YES Program/Erase operation Not Complete,Write Reset Command Program/Erase operation Complete Note:The system should recheck the toggle bit even if Q5="1" because the toggle bit may stop toggling as Q5 changes to "1".See the subsections on Q6 and Q2 for more information. P/N:PM0567 23 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B Figure 6 Automatic Erase Alogorithm (Word Mode) Strat Write erase Command Sequence (See below) Data polling/Toggle Bit Successfull Command Erase Completed Chip Erase Command Sequence* (Address/Command): Single-Block Erase Command Sequence (Address/Command): Multi-Block Erase Command Sequence (Address/Command): 555H/AAH 555H/AAH 555H/AAH 2AAH/55H 2AAH/55H 2AAH/55H 555H/80H 555H/80H 555H/80H 555H/AAH 555H/AAH 555H/AAH 2AAH/55H 2AAH/55H 2AAH/55H 555H/10H Block Address/20H Block Address/30H Same Address (A12-A19) Toggling twice ? No Yes P/N:PM0567 24 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B Figure 7 Automatic Page Program Flow Chart (Word Mode) Start Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Loading End? No Yes Reload the last address Check Device Status Q6 = Toggle ? Yes No Q7 = Data ? No Yes Page Program Completed Yes Program Error To Continue Other Operations, Stays at Read Array Mode Program another page ? No Operation Done,Device Stays at Read Array Mode P/N:PM0567 25 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B Table 6 DC CHARACTERISTICS SYMBOL DESCRIPTIONS IIL Input Load Current MIN. TYP. MAX. 1 UNITS uA 10 uA 10 uA 5 mA ILO Output Leakage Current ISB1 Vcc Standby Current (CMOS) ISB2 Vcc Standby Current (TTL) ICC1 Vcc Read Current 20 27 mA ICC2 Vcc Erase/ Suspend Current 20 35 mA ICC3 Vcc Program Current 20 35 mA ICC4 ICC5 ICC6 VIL VIH VOL Vcc Erase Current Vcc Read/Write Current (Note 1) Vcc Read/Erase Current (Note 1) Input Low Voltage Input High Voltage Output Low Voltage 8 25 25 15 45 45 0.8 Vcc+0.3 0.45 mA mA mA V V V VOH Output High Voltage VID Voltage for Read ID Mode 1 -0.5 0.7 x Vcc Vcc-0.4 V 0.85Vcc V 8.5 10 10.5 TEST CONDITIONS Vcc = Vcc Max VIN = Vcc or GND Vcc = Vcc Max VIN = Vcc or GND Vcc = Vcc Max CE = VIH Vcc = Vcc Max CE = VIH Vcc = Vcc Max f = 8MHz, IOUT = 0mA CE = VIH Block Erase Suspend Program in Progress Erase in Progress Read/Write in Progress Read/Erase in Progress IOL = 2.1mA Vcc = Vcc Min IOH = -100uA Vcc = Vcc Min IOH = -2mA Vcc = Vcc Min V Table 7 AC CHARACTERISTICS - READ OPERATIONS SYMBOL tACC tCE tOE tDF tOH DESCRIPTIONS Address to Output Delay CE to Output Delay OE to Output Delay OE High to Output High Z (Note 1) Address to Output Hold MIN. MAX. 90 90 55 40 0 UNIT ns ns ns ns ns CONDITIONS CE=OE=VIL OE=VIL CE=VIL CE=VIL CE=OE=VIL Note 1: Not 100% Tested. P/N:PM0567 26 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B Figure 8 Key to Switching Waveforms WAVEFROM INPUT OUTPUT Must Be Steady Will Be Steady May Be Chang from H to L Will be Changing from H to L May change from L to H Will be Changing from L to H "H" or "L" Any Change Permitted Changing State Unknow Does Not Apply Center Line is HighImpedance "Off" Stste Figure 9 Switching Test Circuits DEVICE UNDER TEST 2.7K ohm +3.3V CL 6.2K ohm DIODES=IN3064 OR EQUIVALENT CL=30pF Including jig capacitance Test Specifications Test Condition Output Load Output Load Capacitance,CL (in cluding jig capacitance) 1TTL 30 pF Input rise & fall time Input pulse Level Input timing measurement reference levels Output timing measurement reference levels 5 0~3.0 1.5 1.5 ns V V V P/N:PM0567 27 Unit REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B Figure 10 Switching Test Waveforms 3.0V 1.5V TEST POINTS 1.5V 0V INPUT OUTPUT Figure 11 AC Waveform for Read Operations tRC Address Address Stable tACC CE tDF tOE OE tOEH tOH WE tCE Output P/N:PM0567 High Z Output Valid 28 High Z REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B Figure 12 AC Waveform for Hardware Reset/Read Operations tRC Address Address Stable tACC CE tRP tRH tCE RP tOH Output High Z Output Valid Table 8 AC CHARACTERISTICS-WRITE/ERASE/PROGRAM OPERATION SYMBOL tWC tAS tAH tDS tDH tOES tCES tGHWL tCS tCH tWP tWPH tVCS tRB tRP tRH tRC tBUSY tREADY P/N:PM0567 DESCRIPTIONS Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time CE Setup Time Read Recover Time Before Write CE Setup Time CE Hold Time Write Pulse Width Write Pulse Width High CE setup Before VCC Ready RY/BY recovery time RP pulse width RP high time before read Read cycle time WE pin High to busy mode Reset pin Low to Read mode MIN. 90 0 65 65 0 0 0 0 0 0 65 35 0 MAX. 0 50 50 90 70 50 29 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us CONDITIONS REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B Figure 13 Automatic Page Program Timing Waveform(Word Mode) Page Program Sequence (Last two cycle) 3rd cycle Address PA (A0~A19) 555H PA (A0~A5) Last PA (A0~A5) Last PA (A0~A5) tWC tAS tAH CE tWP tCS tCH WE tDS Data tWPH tDH A0H PD Last PD PD Last PD Status Status OE Program Operation RY/BY Legend :PA : Program addr. PD : Program data Note : 1.A6~A19 for page addr. 2.It is necessary to write the last PA twice to terminate PD loading operation. Status:Q7: Data Polling,Q6: toggle bit I,Q5:exceeded timing limits,Q3: Block Erase Status bit ,Q2: toggle bit II. P/N:PM0567 30 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B Figure 14 AC Waveform Chip/Block Erase Operations (Word Mode) Address 2AAH 555H tAS tWC 555H 555H 2AAH SA tAH CE tCH tCS OE tGHWL tWP tWPH WE tDS tDH Data AAH 55H 80H AAH 55H 10H/ 30H/20H tVCS Vcc Notes: 1. SA is the sector address for sector Erase Address = 555H(Word),AAAH(Byte) for Chip Erase. = A12~A19 for Block Erase. 2.These Waveform are for the word mode.(The address differ from byte mode.) 3.It is necessary to write the last SA twice to terminate SA loading operation for multi-block erase. P/N:PM0567 31 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B Figure 15 AC Waveforms for Data Polling Automatic Algorithm Operations CE tCH tDF tOE OE tOEH WE tCE Q7 Q7 Q0 to Q6 = Output Flag Q0 to Q6 *Q7 = Valid Data Q0 to Q6 Valid Data tBUSY RY/BY *:Q7 = Valid Data (The device has completed the automatic operation). P/N:PM0567 32 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B Figure 16 AC Waveform for Toggle Bit 1 during Automatic Algorithm Operation Address tAHT tAS tAHTtASO CE tCEPH Toggle Data WE tOEPH tOEH tOEH OE tDH Q6-Q2 tOE Toggle Data DATA tCE Toggle Data * Toggle Data Stop Toggling Output Valid tBUSY RY/BY *: Q6 stops toggling (The Device has completed the Automatic operation). SYMBOL tAHT tASO tCEPH tOEPH tOEH tELFL/ELFH tFHQV tFLQZ P/N:PM0567 DESCRIPTIONS Address hold time from CE or OE high during toggle bit polling Address setup time to OE low during toggle bit polling Chip enable high during toggle bit polling Output enable high during toggle bit polling Output enable hold time CE to BYTE switching low or high BYTE switching high to output active BYTE switching low to output High-Z 33 MIN. 0 15 MAX. 20 10 5 120 30 UNIT ns ns ns ns ns ns ns REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B Figure 17 RY/BY Timing Diagram during Program/Erase Operation CE The rising edge of the last write pulse WE Entire programming or erase operations RY/BY tBUSY Figure 18 RP/RY/BY Timing Diagram WE RP tRP tRB RY/BY tREADY Figure 19 Timing Diagram for Word Mode Configuration CE BYTE Data Output (Q0 to Q7) Q0 to Q14 tELFH Q15/A-1 P/N:PM0567 Data Output (Q0 to Q14) tFHQV A-1 Q15 34 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B Figure 20 Timing Diagram for Byte Mode Configuration CE BYTE tELFL Data Output (Q0 to Q14) Q0 to Q14 Q15/A-1 Data Output (Q0 to Q7) Q15 A-1 tFLQZ Figure 21 AC Waveform for Group Protection (Word Mode) Group Protuct Command Sequence (Last two cycles) 5th cycle Address 6th cycle GA (A12~A19) 2AAH CE WE Data 20H 55H Status OE RY/BY GA : Group Address P/N:PM0567 35 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B Figure 22 AC Waveform For Chip Unprotection (Word Mode) Chip Un-Protuct Command Sequence (Last two cycles) 5th cycle Address 6th cycle 555H 2AAH CE WE Data 40H 55H Status OE RY/BY P/N:PM0567 36 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B Figure 23 ID Code Read Timing Waveform VCC 5V VID VIH VIL A9 VIH A0 VIL tACC tACC VIH A1 VIL A2-A8 A10-A16 CE VIH VIL VIH VIL tCE WE VIH VIL VIH OE tOE tDF VIL tOH tOH DATA Q0-Q15 VIH VIL DATA OUT C2H/00C2H P/N:PM0567 37 DATA OUT 67H/68H(Byte) 0067H/0068H(Word) REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B Figure 24 Back to Back Read/Write Timing Diagram Command Read Command Read Read tRC tWC tRC tWC tRC tRC BA1 BA2 (555H) BA1 BA2 (PA) Read Address BA2 (PA) tACC tAH tAS CE BA1 tAHT tAS tCE tCEPH tOE OE tGHWL tWP tDF tOEH WE tDS Output Valid Output Valid Input tDF tDH Valid Output Valid Input Valid Output Status NOTE : This is example of read for Bank 1 and Embedded Alogorithm (Program) for Bank 2. BA1 :Address of Bank 1. BA2 : Address of Bank 2. P/N:PM0567 38 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B Figure 25 Q2 Vs Q6 Enter Embedded Erasing WE Erase Suspend Erase Enter Suspend Program Erase Resume Erase Suspend Program Erase Suspend Read Erase Suspend Read Erase Erase Complete Q6 Q2 Toggle Q2 and Q6 with OE or CE NOTE : Q2 toggles only when read at an address within an erasing or erase-suspended block. P/N:PM0567 39 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B Table 9 ERASE AND PROGRAMMING PERFORMANCE (1) (2) PARAMETER Single/Block Erase Time Multi Block Erase Time Chip Erase Time Page Programming Time Chip Programming Time Erase/Program Cycles Note: LIMITS TYP.(3) 20 50 50 4 64 MIN. MAX. 160 400 400 120 192 100,000 UNITS ms ms ms ms sec. Cycle 1.Sampled, not 100% tested. 2.Excludes external system level over head 3.Typical values measured at 25C, nominal voltage. Table 10 LATCHUP CHARACTERISTICS MIN. Input Voltage with respect to GND on all pins except I/O pins -1.0 Input Voltage with respect to GND on I/O pins -1.0 Current -100 Includes all pins except Vcc. Test conditions: Vcc = 3.0V, one pin at a time. MAX. 10.5 Vcc+1.0 +100 UNITS V V mA Table 11 ABSOLUTE MAXIMUM RATINGS RATING Ambient Operating Temperature Storage Temperature Applied Input Voltage Applied Output Voltage Vcc to Ground Potential A9,RP,WP VALUE -40C to 85C -65C to 125C -0.5V to Vcc + 4.5 -0.5V to Vcc +0.6 -0.5V to 4.5V -0.5V to 12.5V Table 12 OPERATING RANGES RATING Ambient Temperature Vcc Supply Voltage P/N:PM0567 VALUE 0C to 70C (Comm.) -40C to 85C (Ind.) 2.7V to 3.0V 40 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B Ordering Information Part No. MX29VW160TTC-90 MX29VW160TTI-90 MX29VW160TXBC-90 MX29VW160TXBI-90 Access Time(ns) 90 90 90 90 Temperature Range Comm. Ind. Comm. Ind. Type 48 Pin TSOP 48 Pin TSOP 48 Ball CSP 48 Ball CSP Package Ball Type Ball Pitch BGA BGA 0.80mm 0.80mm Note: 1. Top Boot Block as an sample.For Bottom Boot Block ones,MX29VW160TXXX will be changed to MX29VW160BXXX) P/N:PM0567 41 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B PACKAGE INFORMATION 48-PIN TSOP P/N:PM0567 42 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B 48-Ball CSP P/N:PM0567 43 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B REVISION HISTORY Revision Description Page Date 0.3 CSP package size:7mmx12mm ---> 8mmx13mmx1.2mm Add in ICC6:Vcc Read/Erase Current Remove tBACC & tBHZ Remove LGA Package Change Sector structure of the 2Mb-Bank from 16KBx4+ 8KBx8+32KBx4 to 8KBx8+64KBx1 Add in WP pin Change VIP range from 9.5V~10.5V to 8.5V~10.5V Vcc range change to 2.25V~3.0V Change Group Addr.: A12~A19 Correct ID data Block architecture description correction Modify typing Modify AC Characteristic description Modify Erase/Program Performance Modify Absolute Maximun Rating Remove MX29VW160TXAC-12/TXAI-12 Update the fast access speed from 120ns to 90ns Remove the "byte program" words To added RWW erase/program test Algorithm To added tBUSY/tREADY timing at AC Characteristics Table Content Change Group unprotect--->Chip unprotect Add Package Information Modify 48-Pin CSP Package Information Modify Table 7. AC Characteristics--tACC:120ns-->90ns tCE:120ns-->90ns Modify Table 8. AC Characteristics--tWC:120ns-->90ns tRC:120ns-->90ns 1.Modify Extented Single-supply voltage range from 2.25 to 3.0V --> from 2.7 to 3.0V 2.Modify Test Specifications 3.Modify Figure 10. Switching Test Waveforms 4. Modify Package Information P3 P25 P25 P41 P1, 4, 5, 8 NOV/04/1998 0.4 0.5 0.6 0.7 0.8 0.9 0.9.1 0.9.2 0.9.3 0.9.4 P/N:PM0567 44 P1, 3, 5, 6, 14, 20 P6, 14, 15, 25 P1, 2, 3, 40 P8, 15, 17, 18, 35 P11 P2 P4,5,9,11,13,16 P28,29,32,33,37 P40 P40 P41 P1,2 P8,30,40 P26,27 P29 P15,16,18,36 P42,43 P43 P26 NOV/19/1998 NOV/27/1998 DEC/03/1998 FEB/12/1999 MAY/17/1999 MAR/22/2000 OCT/30/2000 NOV/20/2000 FEB/23/2001 P29 P1,2,40 JUN/06/2001 P27 P28 P42,43 REV. 0.9.4, JUN. 06, 2001 MX29VW160T/B MACRONIX INTERNATIONAL CO., LTD. HEADQUARTERS: TEL:+886-3-578-6688 FAX:+886-3-563-2888 EUROPE OFFICE: TEL:+32-2-456-8020 FAX:+32-2-456-8021 JAPAN OFFICE: TEL:+81-44-246-9100 FAX:+81-44-246-9105 SINGAPORE OFFICE: TEL:+65-348-8385 FAX:+65-348-8096 TAIPEI OFFICE: TEL:+886-2-2509-3300 FAX:+886-2-2509-2200 MACRONIX AMERICA, INC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 45